1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #include <linux/delay.h>
5 
6 #include "igc_hw.h"
7 #include "igc_i225.h"
8 #include "igc_mac.h"
9 #include "igc_base.h"
10 #include "igc.h"
11 
12 /**
13  * igc_set_pcie_completion_timeout - set pci-e completion timeout
14  * @hw: pointer to the HW structure
15  */
16 static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw)
17 {
18 	u32 gcr = rd32(IGC_GCR);
19 	u16 pcie_devctl2;
20 	s32 ret_val = 0;
21 
22 	/* only take action if timeout value is defaulted to 0 */
23 	if (gcr & IGC_GCR_CMPL_TMOUT_MASK)
24 		goto out;
25 
26 	/* if capabilities version is type 1 we can write the
27 	 * timeout of 10ms to 200ms through the GCR register
28 	 */
29 	if (!(gcr & IGC_GCR_CAP_VER2)) {
30 		gcr |= IGC_GCR_CMPL_TMOUT_10ms;
31 		goto out;
32 	}
33 
34 	/* for version 2 capabilities we need to write the config space
35 	 * directly in order to set the completion timeout value for
36 	 * 16ms to 55ms
37 	 */
38 	ret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
39 					&pcie_devctl2);
40 	if (ret_val)
41 		goto out;
42 
43 	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
44 
45 	ret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
46 					 &pcie_devctl2);
47 out:
48 	/* disable completion timeout resend */
49 	gcr &= ~IGC_GCR_CMPL_TMOUT_RESEND;
50 
51 	wr32(IGC_GCR, gcr);
52 
53 	return ret_val;
54 }
55 
56 /**
57  * igc_reset_hw_base - Reset hardware
58  * @hw: pointer to the HW structure
59  *
60  * This resets the hardware into a known state.  This is a
61  * function pointer entry point called by the api module.
62  */
63 static s32 igc_reset_hw_base(struct igc_hw *hw)
64 {
65 	s32 ret_val;
66 	u32 ctrl;
67 
68 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
69 	 * on the last TLP read/write transaction when MAC is reset.
70 	 */
71 	ret_val = igc_disable_pcie_master(hw);
72 	if (ret_val)
73 		hw_dbg("PCI-E Master disable polling has failed.\n");
74 
75 	/* set the completion timeout for interface */
76 	ret_val = igc_set_pcie_completion_timeout(hw);
77 	if (ret_val)
78 		hw_dbg("PCI-E Set completion timeout has failed.\n");
79 
80 	hw_dbg("Masking off all interrupts\n");
81 	wr32(IGC_IMC, 0xffffffff);
82 
83 	wr32(IGC_RCTL, 0);
84 	wr32(IGC_TCTL, IGC_TCTL_PSP);
85 	wrfl();
86 
87 	usleep_range(10000, 20000);
88 
89 	ctrl = rd32(IGC_CTRL);
90 
91 	hw_dbg("Issuing a global reset to MAC\n");
92 	wr32(IGC_CTRL, ctrl | IGC_CTRL_RST);
93 
94 	ret_val = igc_get_auto_rd_done(hw);
95 	if (ret_val) {
96 		/* When auto config read does not complete, do not
97 		 * return with an error. This can happen in situations
98 		 * where there is no eeprom and prevents getting link.
99 		 */
100 		hw_dbg("Auto Read Done did not complete\n");
101 	}
102 
103 	/* Clear any pending interrupt events. */
104 	wr32(IGC_IMC, 0xffffffff);
105 	rd32(IGC_ICR);
106 
107 	return ret_val;
108 }
109 
110 /**
111  * igc_init_nvm_params_base - Init NVM func ptrs.
112  * @hw: pointer to the HW structure
113  */
114 static s32 igc_init_nvm_params_base(struct igc_hw *hw)
115 {
116 	struct igc_nvm_info *nvm = &hw->nvm;
117 	u32 eecd = rd32(IGC_EECD);
118 	u16 size;
119 
120 	size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>
121 		     IGC_EECD_SIZE_EX_SHIFT);
122 
123 	/* Added to a constant, "size" becomes the left-shift value
124 	 * for setting word_size.
125 	 */
126 	size += NVM_WORD_SIZE_BASE_SHIFT;
127 
128 	/* Just in case size is out of range, cap it to the largest
129 	 * EEPROM size supported
130 	 */
131 	if (size > 15)
132 		size = 15;
133 
134 	nvm->type = igc_nvm_eeprom_spi;
135 	nvm->word_size = BIT(size);
136 	nvm->opcode_bits = 8;
137 	nvm->delay_usec = 1;
138 
139 	nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
140 	nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
141 			    16 : 8;
142 
143 	if (nvm->word_size == BIT(15))
144 		nvm->page_size = 128;
145 
146 	return 0;
147 }
148 
149 /**
150  * igc_setup_copper_link_base - Configure copper link settings
151  * @hw: pointer to the HW structure
152  *
153  * Configures the link for auto-neg or forced speed and duplex.  Then we check
154  * for link, once link is established calls to configure collision distance
155  * and flow control are called.
156  */
157 static s32 igc_setup_copper_link_base(struct igc_hw *hw)
158 {
159 	s32  ret_val = 0;
160 	u32 ctrl;
161 
162 	ctrl = rd32(IGC_CTRL);
163 	ctrl |= IGC_CTRL_SLU;
164 	ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
165 	wr32(IGC_CTRL, ctrl);
166 
167 	ret_val = igc_setup_copper_link(hw);
168 
169 	return ret_val;
170 }
171 
172 /**
173  * igc_init_mac_params_base - Init MAC func ptrs.
174  * @hw: pointer to the HW structure
175  */
176 static s32 igc_init_mac_params_base(struct igc_hw *hw)
177 {
178 	struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base;
179 	struct igc_mac_info *mac = &hw->mac;
180 
181 	/* Set mta register count */
182 	mac->mta_reg_count = 128;
183 	mac->rar_entry_count = IGC_RAR_ENTRIES;
184 
185 	/* reset */
186 	mac->ops.reset_hw = igc_reset_hw_base;
187 
188 	mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
189 	mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
190 
191 	/* Allow a single clear of the SW semaphore on I225 */
192 	if (mac->type == igc_i225)
193 		dev_spec->clear_semaphore_once = true;
194 
195 	/* physical interface link setup */
196 	mac->ops.setup_physical_interface = igc_setup_copper_link_base;
197 
198 	return 0;
199 }
200 
201 /**
202  * igc_init_phy_params_base - Init PHY func ptrs.
203  * @hw: pointer to the HW structure
204  */
205 static s32 igc_init_phy_params_base(struct igc_hw *hw)
206 {
207 	struct igc_phy_info *phy = &hw->phy;
208 	s32 ret_val = 0;
209 
210 	if (hw->phy.media_type != igc_media_type_copper) {
211 		phy->type = igc_phy_none;
212 		goto out;
213 	}
214 
215 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;
216 	phy->reset_delay_us	= 100;
217 
218 	/* set lan id */
219 	hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >>
220 			IGC_STATUS_FUNC_SHIFT;
221 
222 	/* Make sure the PHY is in a good state. Several people have reported
223 	 * firmware leaving the PHY's page select register set to something
224 	 * other than the default of zero, which causes the PHY ID read to
225 	 * access something other than the intended register.
226 	 */
227 	ret_val = hw->phy.ops.reset(hw);
228 	if (ret_val) {
229 		hw_dbg("Error resetting the PHY.\n");
230 		goto out;
231 	}
232 
233 	ret_val = igc_get_phy_id(hw);
234 	if (ret_val)
235 		return ret_val;
236 
237 	igc_check_for_copper_link(hw);
238 
239 	/* Verify phy id and set remaining function pointers */
240 	switch (phy->id) {
241 	case I225_I_PHY_ID:
242 		phy->type	= igc_phy_i225;
243 		break;
244 	default:
245 		ret_val = -IGC_ERR_PHY;
246 		goto out;
247 	}
248 
249 out:
250 	return ret_val;
251 }
252 
253 static s32 igc_get_invariants_base(struct igc_hw *hw)
254 {
255 	struct igc_mac_info *mac = &hw->mac;
256 	s32 ret_val = 0;
257 
258 	switch (hw->device_id) {
259 	case IGC_DEV_ID_I225_LM:
260 	case IGC_DEV_ID_I225_V:
261 		mac->type = igc_i225;
262 		break;
263 	default:
264 		return -IGC_ERR_MAC_INIT;
265 	}
266 
267 	hw->phy.media_type = igc_media_type_copper;
268 
269 	/* mac initialization and operations */
270 	ret_val = igc_init_mac_params_base(hw);
271 	if (ret_val)
272 		goto out;
273 
274 	/* NVM initialization */
275 	ret_val = igc_init_nvm_params_base(hw);
276 	switch (hw->mac.type) {
277 	case igc_i225:
278 		ret_val = igc_init_nvm_params_i225(hw);
279 		break;
280 	default:
281 		break;
282 	}
283 
284 	/* setup PHY parameters */
285 	ret_val = igc_init_phy_params_base(hw);
286 	if (ret_val)
287 		goto out;
288 
289 out:
290 	return ret_val;
291 }
292 
293 /**
294  * igc_acquire_phy_base - Acquire rights to access PHY
295  * @hw: pointer to the HW structure
296  *
297  * Acquire access rights to the correct PHY.  This is a
298  * function pointer entry point called by the api module.
299  */
300 static s32 igc_acquire_phy_base(struct igc_hw *hw)
301 {
302 	u16 mask = IGC_SWFW_PHY0_SM;
303 
304 	return hw->mac.ops.acquire_swfw_sync(hw, mask);
305 }
306 
307 /**
308  * igc_release_phy_base - Release rights to access PHY
309  * @hw: pointer to the HW structure
310  *
311  * A wrapper to release access rights to the correct PHY.  This is a
312  * function pointer entry point called by the api module.
313  */
314 static void igc_release_phy_base(struct igc_hw *hw)
315 {
316 	u16 mask = IGC_SWFW_PHY0_SM;
317 
318 	hw->mac.ops.release_swfw_sync(hw, mask);
319 }
320 
321 /**
322  * igc_init_hw_base - Initialize hardware
323  * @hw: pointer to the HW structure
324  *
325  * This inits the hardware readying it for operation.
326  */
327 static s32 igc_init_hw_base(struct igc_hw *hw)
328 {
329 	struct igc_mac_info *mac = &hw->mac;
330 	u16 i, rar_count = mac->rar_entry_count;
331 	s32 ret_val = 0;
332 
333 	/* Setup the receive address */
334 	igc_init_rx_addrs(hw, rar_count);
335 
336 	/* Zero out the Multicast HASH table */
337 	hw_dbg("Zeroing the MTA\n");
338 	for (i = 0; i < mac->mta_reg_count; i++)
339 		array_wr32(IGC_MTA, i, 0);
340 
341 	/* Zero out the Unicast HASH table */
342 	hw_dbg("Zeroing the UTA\n");
343 	for (i = 0; i < mac->uta_reg_count; i++)
344 		array_wr32(IGC_UTA, i, 0);
345 
346 	/* Setup link and flow control */
347 	ret_val = igc_setup_link(hw);
348 
349 	/* Clear all of the statistics registers (clear on read).  It is
350 	 * important that we do this after we have tried to establish link
351 	 * because the symbol error count will increment wildly if there
352 	 * is no link.
353 	 */
354 	igc_clear_hw_cntrs_base(hw);
355 
356 	return ret_val;
357 }
358 
359 /**
360  * igc_power_down_phy_copper_base - Remove link during PHY power down
361  * @hw: pointer to the HW structure
362  *
363  * In the case of a PHY power down to save power, or to turn off link during a
364  * driver unload, or wake on lan is not enabled, remove the link.
365  */
366 void igc_power_down_phy_copper_base(struct igc_hw *hw)
367 {
368 	/* If the management interface is not enabled, then power down */
369 	if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw)))
370 		igc_power_down_phy_copper(hw);
371 }
372 
373 /**
374  * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
375  * @hw: pointer to the HW structure
376  *
377  * After Rx enable, if manageability is enabled then there is likely some
378  * bad data at the start of the fifo and possibly in the DMA fifo.  This
379  * function clears the fifos and flushes any packets that came in as rx was
380  * being enabled.
381  */
382 void igc_rx_fifo_flush_base(struct igc_hw *hw)
383 {
384 	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
385 	int i, ms_wait;
386 
387 	/* disable IPv6 options as per hardware errata */
388 	rfctl = rd32(IGC_RFCTL);
389 	rfctl |= IGC_RFCTL_IPV6_EX_DIS;
390 	wr32(IGC_RFCTL, rfctl);
391 
392 	if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN))
393 		return;
394 
395 	/* Disable all Rx queues */
396 	for (i = 0; i < 4; i++) {
397 		rxdctl[i] = rd32(IGC_RXDCTL(i));
398 		wr32(IGC_RXDCTL(i),
399 		     rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
400 	}
401 	/* Poll all queues to verify they have shut down */
402 	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
403 		usleep_range(1000, 2000);
404 		rx_enabled = 0;
405 		for (i = 0; i < 4; i++)
406 			rx_enabled |= rd32(IGC_RXDCTL(i));
407 		if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
408 			break;
409 	}
410 
411 	if (ms_wait == 10)
412 		pr_debug("Queue disable timed out after 10ms\n");
413 
414 	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
415 	 * incoming packets are rejected.  Set enable and wait 2ms so that
416 	 * any packet that was coming in as RCTL.EN was set is flushed
417 	 */
418 	wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
419 
420 	rlpml = rd32(IGC_RLPML);
421 	wr32(IGC_RLPML, 0);
422 
423 	rctl = rd32(IGC_RCTL);
424 	temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
425 	temp_rctl |= IGC_RCTL_LPE;
426 
427 	wr32(IGC_RCTL, temp_rctl);
428 	wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN);
429 	wrfl();
430 	usleep_range(2000, 3000);
431 
432 	/* Enable Rx queues that were previously enabled and restore our
433 	 * previous state
434 	 */
435 	for (i = 0; i < 4; i++)
436 		wr32(IGC_RXDCTL(i), rxdctl[i]);
437 	wr32(IGC_RCTL, rctl);
438 	wrfl();
439 
440 	wr32(IGC_RLPML, rlpml);
441 	wr32(IGC_RFCTL, rfctl);
442 
443 	/* Flush receive errors generated by workaround */
444 	rd32(IGC_ROC);
445 	rd32(IGC_RNBC);
446 	rd32(IGC_MPC);
447 }
448 
449 static struct igc_mac_operations igc_mac_ops_base = {
450 	.init_hw		= igc_init_hw_base,
451 	.check_for_link		= igc_check_for_copper_link,
452 	.rar_set		= igc_rar_set,
453 	.read_mac_addr		= igc_read_mac_addr,
454 	.get_speed_and_duplex	= igc_get_speed_and_duplex_copper,
455 };
456 
457 static const struct igc_phy_operations igc_phy_ops_base = {
458 	.acquire		= igc_acquire_phy_base,
459 	.release		= igc_release_phy_base,
460 	.reset			= igc_phy_hw_reset,
461 	.read_reg		= igc_read_phy_reg_gpy,
462 	.write_reg		= igc_write_phy_reg_gpy,
463 };
464 
465 const struct igc_info igc_base_info = {
466 	.get_invariants		= igc_get_invariants_base,
467 	.mac_ops		= &igc_mac_ops_base,
468 	.phy_ops		= &igc_phy_ops_base,
469 };
470