1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/delay.h> 5 6 #include "igc_hw.h" 7 #include "igc_i225.h" 8 #include "igc_mac.h" 9 #include "igc_base.h" 10 #include "igc.h" 11 12 /** 13 * igc_reset_hw_base - Reset hardware 14 * @hw: pointer to the HW structure 15 * 16 * This resets the hardware into a known state. This is a 17 * function pointer entry point called by the api module. 18 */ 19 static s32 igc_reset_hw_base(struct igc_hw *hw) 20 { 21 s32 ret_val; 22 u32 ctrl; 23 24 /* Prevent the PCI-E bus from sticking if there is no TLP connection 25 * on the last TLP read/write transaction when MAC is reset. 26 */ 27 ret_val = igc_disable_pcie_master(hw); 28 if (ret_val) 29 hw_dbg("PCI-E Master disable polling has failed.\n"); 30 31 hw_dbg("Masking off all interrupts\n"); 32 wr32(IGC_IMC, 0xffffffff); 33 34 wr32(IGC_RCTL, 0); 35 wr32(IGC_TCTL, IGC_TCTL_PSP); 36 wrfl(); 37 38 usleep_range(10000, 20000); 39 40 ctrl = rd32(IGC_CTRL); 41 42 hw_dbg("Issuing a global reset to MAC\n"); 43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); 44 45 ret_val = igc_get_auto_rd_done(hw); 46 if (ret_val) { 47 /* When auto config read does not complete, do not 48 * return with an error. This can happen in situations 49 * where there is no eeprom and prevents getting link. 50 */ 51 hw_dbg("Auto Read Done did not complete\n"); 52 } 53 54 /* Clear any pending interrupt events. */ 55 wr32(IGC_IMC, 0xffffffff); 56 rd32(IGC_ICR); 57 58 return ret_val; 59 } 60 61 /** 62 * igc_init_nvm_params_base - Init NVM func ptrs. 63 * @hw: pointer to the HW structure 64 */ 65 static s32 igc_init_nvm_params_base(struct igc_hw *hw) 66 { 67 struct igc_nvm_info *nvm = &hw->nvm; 68 u32 eecd = rd32(IGC_EECD); 69 u16 size; 70 71 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >> 72 IGC_EECD_SIZE_EX_SHIFT); 73 74 /* Added to a constant, "size" becomes the left-shift value 75 * for setting word_size. 76 */ 77 size += NVM_WORD_SIZE_BASE_SHIFT; 78 79 /* Just in case size is out of range, cap it to the largest 80 * EEPROM size supported 81 */ 82 if (size > 15) 83 size = 15; 84 85 nvm->type = igc_nvm_eeprom_spi; 86 nvm->word_size = BIT(size); 87 nvm->opcode_bits = 8; 88 nvm->delay_usec = 1; 89 90 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 91 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 92 16 : 8; 93 94 if (nvm->word_size == BIT(15)) 95 nvm->page_size = 128; 96 97 return 0; 98 } 99 100 /** 101 * igc_setup_copper_link_base - Configure copper link settings 102 * @hw: pointer to the HW structure 103 * 104 * Configures the link for auto-neg or forced speed and duplex. Then we check 105 * for link, once link is established calls to configure collision distance 106 * and flow control are called. 107 */ 108 static s32 igc_setup_copper_link_base(struct igc_hw *hw) 109 { 110 s32 ret_val = 0; 111 u32 ctrl; 112 113 ctrl = rd32(IGC_CTRL); 114 ctrl |= IGC_CTRL_SLU; 115 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 116 wr32(IGC_CTRL, ctrl); 117 118 ret_val = igc_setup_copper_link(hw); 119 120 return ret_val; 121 } 122 123 /** 124 * igc_init_mac_params_base - Init MAC func ptrs. 125 * @hw: pointer to the HW structure 126 */ 127 static s32 igc_init_mac_params_base(struct igc_hw *hw) 128 { 129 struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base; 130 struct igc_mac_info *mac = &hw->mac; 131 132 /* Set mta register count */ 133 mac->mta_reg_count = 128; 134 mac->rar_entry_count = IGC_RAR_ENTRIES; 135 136 /* reset */ 137 mac->ops.reset_hw = igc_reset_hw_base; 138 139 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 140 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 141 142 /* Allow a single clear of the SW semaphore on I225 */ 143 if (mac->type == igc_i225) 144 dev_spec->clear_semaphore_once = true; 145 146 /* physical interface link setup */ 147 mac->ops.setup_physical_interface = igc_setup_copper_link_base; 148 149 return 0; 150 } 151 152 /** 153 * igc_init_phy_params_base - Init PHY func ptrs. 154 * @hw: pointer to the HW structure 155 */ 156 static s32 igc_init_phy_params_base(struct igc_hw *hw) 157 { 158 struct igc_phy_info *phy = &hw->phy; 159 s32 ret_val = 0; 160 161 if (hw->phy.media_type != igc_media_type_copper) { 162 phy->type = igc_phy_none; 163 goto out; 164 } 165 166 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 167 phy->reset_delay_us = 100; 168 169 /* set lan id */ 170 hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >> 171 IGC_STATUS_FUNC_SHIFT; 172 173 /* Make sure the PHY is in a good state. Several people have reported 174 * firmware leaving the PHY's page select register set to something 175 * other than the default of zero, which causes the PHY ID read to 176 * access something other than the intended register. 177 */ 178 ret_val = hw->phy.ops.reset(hw); 179 if (ret_val) { 180 hw_dbg("Error resetting the PHY.\n"); 181 goto out; 182 } 183 184 ret_val = igc_get_phy_id(hw); 185 if (ret_val) 186 return ret_val; 187 188 igc_check_for_copper_link(hw); 189 190 /* Verify phy id and set remaining function pointers */ 191 switch (phy->id) { 192 case I225_I_PHY_ID: 193 phy->type = igc_phy_i225; 194 break; 195 default: 196 ret_val = -IGC_ERR_PHY; 197 goto out; 198 } 199 200 out: 201 return ret_val; 202 } 203 204 static s32 igc_get_invariants_base(struct igc_hw *hw) 205 { 206 struct igc_mac_info *mac = &hw->mac; 207 s32 ret_val = 0; 208 209 switch (hw->device_id) { 210 case IGC_DEV_ID_I225_LM: 211 case IGC_DEV_ID_I225_V: 212 mac->type = igc_i225; 213 break; 214 default: 215 return -IGC_ERR_MAC_INIT; 216 } 217 218 hw->phy.media_type = igc_media_type_copper; 219 220 /* mac initialization and operations */ 221 ret_val = igc_init_mac_params_base(hw); 222 if (ret_val) 223 goto out; 224 225 /* NVM initialization */ 226 ret_val = igc_init_nvm_params_base(hw); 227 switch (hw->mac.type) { 228 case igc_i225: 229 ret_val = igc_init_nvm_params_i225(hw); 230 break; 231 default: 232 break; 233 } 234 235 /* setup PHY parameters */ 236 ret_val = igc_init_phy_params_base(hw); 237 if (ret_val) 238 goto out; 239 240 out: 241 return ret_val; 242 } 243 244 /** 245 * igc_acquire_phy_base - Acquire rights to access PHY 246 * @hw: pointer to the HW structure 247 * 248 * Acquire access rights to the correct PHY. This is a 249 * function pointer entry point called by the api module. 250 */ 251 static s32 igc_acquire_phy_base(struct igc_hw *hw) 252 { 253 u16 mask = IGC_SWFW_PHY0_SM; 254 255 return hw->mac.ops.acquire_swfw_sync(hw, mask); 256 } 257 258 /** 259 * igc_release_phy_base - Release rights to access PHY 260 * @hw: pointer to the HW structure 261 * 262 * A wrapper to release access rights to the correct PHY. This is a 263 * function pointer entry point called by the api module. 264 */ 265 static void igc_release_phy_base(struct igc_hw *hw) 266 { 267 u16 mask = IGC_SWFW_PHY0_SM; 268 269 hw->mac.ops.release_swfw_sync(hw, mask); 270 } 271 272 /** 273 * igc_init_hw_base - Initialize hardware 274 * @hw: pointer to the HW structure 275 * 276 * This inits the hardware readying it for operation. 277 */ 278 static s32 igc_init_hw_base(struct igc_hw *hw) 279 { 280 struct igc_mac_info *mac = &hw->mac; 281 u16 i, rar_count = mac->rar_entry_count; 282 s32 ret_val = 0; 283 284 /* Setup the receive address */ 285 igc_init_rx_addrs(hw, rar_count); 286 287 /* Zero out the Multicast HASH table */ 288 hw_dbg("Zeroing the MTA\n"); 289 for (i = 0; i < mac->mta_reg_count; i++) 290 array_wr32(IGC_MTA, i, 0); 291 292 /* Zero out the Unicast HASH table */ 293 hw_dbg("Zeroing the UTA\n"); 294 for (i = 0; i < mac->uta_reg_count; i++) 295 array_wr32(IGC_UTA, i, 0); 296 297 /* Setup link and flow control */ 298 ret_val = igc_setup_link(hw); 299 300 /* Clear all of the statistics registers (clear on read). It is 301 * important that we do this after we have tried to establish link 302 * because the symbol error count will increment wildly if there 303 * is no link. 304 */ 305 igc_clear_hw_cntrs_base(hw); 306 307 return ret_val; 308 } 309 310 /** 311 * igc_power_down_phy_copper_base - Remove link during PHY power down 312 * @hw: pointer to the HW structure 313 * 314 * In the case of a PHY power down to save power, or to turn off link during a 315 * driver unload, or wake on lan is not enabled, remove the link. 316 */ 317 void igc_power_down_phy_copper_base(struct igc_hw *hw) 318 { 319 /* If the management interface is not enabled, then power down */ 320 if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw))) 321 igc_power_down_phy_copper(hw); 322 } 323 324 /** 325 * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable 326 * @hw: pointer to the HW structure 327 * 328 * After Rx enable, if manageability is enabled then there is likely some 329 * bad data at the start of the fifo and possibly in the DMA fifo. This 330 * function clears the fifos and flushes any packets that came in as rx was 331 * being enabled. 332 */ 333 void igc_rx_fifo_flush_base(struct igc_hw *hw) 334 { 335 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 336 int i, ms_wait; 337 338 /* disable IPv6 options as per hardware errata */ 339 rfctl = rd32(IGC_RFCTL); 340 rfctl |= IGC_RFCTL_IPV6_EX_DIS; 341 wr32(IGC_RFCTL, rfctl); 342 343 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) 344 return; 345 346 /* Disable all Rx queues */ 347 for (i = 0; i < 4; i++) { 348 rxdctl[i] = rd32(IGC_RXDCTL(i)); 349 wr32(IGC_RXDCTL(i), 350 rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE); 351 } 352 /* Poll all queues to verify they have shut down */ 353 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 354 usleep_range(1000, 2000); 355 rx_enabled = 0; 356 for (i = 0; i < 4; i++) 357 rx_enabled |= rd32(IGC_RXDCTL(i)); 358 if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE)) 359 break; 360 } 361 362 if (ms_wait == 10) 363 pr_debug("Queue disable timed out after 10ms\n"); 364 365 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 366 * incoming packets are rejected. Set enable and wait 2ms so that 367 * any packet that was coming in as RCTL.EN was set is flushed 368 */ 369 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); 370 371 rlpml = rd32(IGC_RLPML); 372 wr32(IGC_RLPML, 0); 373 374 rctl = rd32(IGC_RCTL); 375 temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP); 376 temp_rctl |= IGC_RCTL_LPE; 377 378 wr32(IGC_RCTL, temp_rctl); 379 wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN); 380 wrfl(); 381 usleep_range(2000, 3000); 382 383 /* Enable Rx queues that were previously enabled and restore our 384 * previous state 385 */ 386 for (i = 0; i < 4; i++) 387 wr32(IGC_RXDCTL(i), rxdctl[i]); 388 wr32(IGC_RCTL, rctl); 389 wrfl(); 390 391 wr32(IGC_RLPML, rlpml); 392 wr32(IGC_RFCTL, rfctl); 393 394 /* Flush receive errors generated by workaround */ 395 rd32(IGC_ROC); 396 rd32(IGC_RNBC); 397 rd32(IGC_MPC); 398 } 399 400 static struct igc_mac_operations igc_mac_ops_base = { 401 .init_hw = igc_init_hw_base, 402 .check_for_link = igc_check_for_copper_link, 403 .rar_set = igc_rar_set, 404 .read_mac_addr = igc_read_mac_addr, 405 .get_speed_and_duplex = igc_get_speed_and_duplex_copper, 406 }; 407 408 static const struct igc_phy_operations igc_phy_ops_base = { 409 .acquire = igc_acquire_phy_base, 410 .release = igc_release_phy_base, 411 .reset = igc_phy_hw_reset, 412 .read_reg = igc_read_phy_reg_gpy, 413 .write_reg = igc_write_phy_reg_gpy, 414 }; 415 416 const struct igc_info igc_base_info = { 417 .get_invariants = igc_get_invariants_base, 418 .mac_ops = &igc_mac_ops_base, 419 .phy_ops = &igc_phy_ops_base, 420 }; 421