1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 14 #include "igc_hw.h" 15 16 /* forward declaration */ 17 void igc_set_ethtool_ops(struct net_device *); 18 19 struct igc_adapter; 20 struct igc_ring; 21 22 void igc_up(struct igc_adapter *adapter); 23 void igc_down(struct igc_adapter *adapter); 24 int igc_setup_tx_resources(struct igc_ring *ring); 25 int igc_setup_rx_resources(struct igc_ring *ring); 26 void igc_free_tx_resources(struct igc_ring *ring); 27 void igc_free_rx_resources(struct igc_ring *ring); 28 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 29 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 30 const u32 max_rss_queues); 31 int igc_reinit_queues(struct igc_adapter *adapter); 32 bool igc_has_link(struct igc_adapter *adapter); 33 void igc_reset(struct igc_adapter *adapter); 34 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 35 36 extern char igc_driver_name[]; 37 extern char igc_driver_version[]; 38 39 #define IGC_REGS_LEN 740 40 #define IGC_RETA_SIZE 128 41 42 /* Interrupt defines */ 43 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 44 #define IGC_FLAG_HAS_MSI BIT(0) 45 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 46 #define IGC_FLAG_DMAC BIT(4) 47 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 48 #define IGC_FLAG_MEDIA_RESET BIT(10) 49 #define IGC_FLAG_MAS_ENABLE BIT(12) 50 #define IGC_FLAG_HAS_MSIX BIT(13) 51 #define IGC_FLAG_VLAN_PROMISC BIT(15) 52 #define IGC_FLAG_RX_LEGACY BIT(16) 53 54 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 55 #define IGC_4K_ITR 980 56 #define IGC_20K_ITR 196 57 #define IGC_70K_ITR 56 58 59 #define IGC_DEFAULT_ITR 3 /* dynamic */ 60 #define IGC_MAX_ITR_USECS 10000 61 #define IGC_MIN_ITR_USECS 10 62 #define NON_Q_VECTORS 1 63 #define MAX_MSIX_ENTRIES 10 64 65 /* TX/RX descriptor defines */ 66 #define IGC_DEFAULT_TXD 256 67 #define IGC_DEFAULT_TX_WORK 128 68 #define IGC_MIN_TXD 80 69 #define IGC_MAX_TXD 4096 70 71 #define IGC_DEFAULT_RXD 256 72 #define IGC_MIN_RXD 80 73 #define IGC_MAX_RXD 4096 74 75 /* Transmit and receive queues */ 76 #define IGC_MAX_RX_QUEUES 4 77 #define IGC_MAX_TX_QUEUES 4 78 79 #define MAX_Q_VECTORS 8 80 #define MAX_STD_JUMBO_FRAME_SIZE 9216 81 82 /* Supported Rx Buffer Sizes */ 83 #define IGC_RXBUFFER_256 256 84 #define IGC_RXBUFFER_2048 2048 85 #define IGC_RXBUFFER_3072 3072 86 87 #define AUTO_ALL_MODES 0 88 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 89 90 /* RX and TX descriptor control thresholds. 91 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 92 * descriptors available in its onboard memory. 93 * Setting this to 0 disables RX descriptor prefetch. 94 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 95 * available in host memory. 96 * If PTHRESH is 0, this should also be 0. 97 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 98 * descriptors until either it has this many to write back, or the 99 * ITR timer expires. 100 */ 101 #define IGC_RX_PTHRESH 8 102 #define IGC_RX_HTHRESH 8 103 #define IGC_TX_PTHRESH 8 104 #define IGC_TX_HTHRESH 1 105 #define IGC_RX_WTHRESH 4 106 #define IGC_TX_WTHRESH 16 107 108 #define IGC_RX_DMA_ATTR \ 109 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 110 111 #define IGC_TS_HDR_LEN 16 112 113 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 114 115 #if (PAGE_SIZE < 8192) 116 #define IGC_MAX_FRAME_BUILD_SKB \ 117 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 118 #else 119 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 120 #endif 121 122 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 123 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 124 125 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 126 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 127 const u32 stat_err_bits) 128 { 129 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 130 } 131 132 enum igc_state_t { 133 __IGC_TESTING, 134 __IGC_RESETTING, 135 __IGC_DOWN, 136 __IGC_PTP_TX_IN_PROGRESS, 137 }; 138 139 enum igc_tx_flags { 140 /* cmd_type flags */ 141 IGC_TX_FLAGS_VLAN = 0x01, 142 IGC_TX_FLAGS_TSO = 0x02, 143 IGC_TX_FLAGS_TSTAMP = 0x04, 144 145 /* olinfo flags */ 146 IGC_TX_FLAGS_IPV4 = 0x10, 147 IGC_TX_FLAGS_CSUM = 0x20, 148 }; 149 150 enum igc_boards { 151 board_base, 152 }; 153 154 /* The largest size we can write to the descriptor is 65535. In order to 155 * maintain a power of two alignment we have to limit ourselves to 32K. 156 */ 157 #define IGC_MAX_TXD_PWR 15 158 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 159 160 /* Tx Descriptors needed, worst case */ 161 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 162 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 163 164 /* wrapper around a pointer to a socket buffer, 165 * so a DMA handle can be stored along with the buffer 166 */ 167 struct igc_tx_buffer { 168 union igc_adv_tx_desc *next_to_watch; 169 unsigned long time_stamp; 170 struct sk_buff *skb; 171 unsigned int bytecount; 172 u16 gso_segs; 173 __be16 protocol; 174 175 DEFINE_DMA_UNMAP_ADDR(dma); 176 DEFINE_DMA_UNMAP_LEN(len); 177 u32 tx_flags; 178 }; 179 180 struct igc_rx_buffer { 181 dma_addr_t dma; 182 struct page *page; 183 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 184 __u32 page_offset; 185 #else 186 __u16 page_offset; 187 #endif 188 __u16 pagecnt_bias; 189 }; 190 191 struct igc_tx_queue_stats { 192 u64 packets; 193 u64 bytes; 194 u64 restart_queue; 195 u64 restart_queue2; 196 }; 197 198 struct igc_rx_queue_stats { 199 u64 packets; 200 u64 bytes; 201 u64 drops; 202 u64 csum_err; 203 u64 alloc_failed; 204 }; 205 206 struct igc_rx_packet_stats { 207 u64 ipv4_packets; /* IPv4 headers processed */ 208 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 209 u64 ipv6_packets; /* IPv6 headers processed */ 210 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 211 u64 tcp_packets; /* TCP headers processed */ 212 u64 udp_packets; /* UDP headers processed */ 213 u64 sctp_packets; /* SCTP headers processed */ 214 u64 nfs_packets; /* NFS headers processe */ 215 u64 other_packets; 216 }; 217 218 struct igc_ring_container { 219 struct igc_ring *ring; /* pointer to linked list of rings */ 220 unsigned int total_bytes; /* total bytes processed this int */ 221 unsigned int total_packets; /* total packets processed this int */ 222 u16 work_limit; /* total work allowed per interrupt */ 223 u8 count; /* total number of rings in vector */ 224 u8 itr; /* current ITR setting for ring */ 225 }; 226 227 struct igc_ring { 228 struct igc_q_vector *q_vector; /* backlink to q_vector */ 229 struct net_device *netdev; /* back pointer to net_device */ 230 struct device *dev; /* device for dma mapping */ 231 union { /* array of buffer info structs */ 232 struct igc_tx_buffer *tx_buffer_info; 233 struct igc_rx_buffer *rx_buffer_info; 234 }; 235 void *desc; /* descriptor ring memory */ 236 unsigned long flags; /* ring specific flags */ 237 void __iomem *tail; /* pointer to ring tail register */ 238 dma_addr_t dma; /* phys address of the ring */ 239 unsigned int size; /* length of desc. ring in bytes */ 240 241 u16 count; /* number of desc. in the ring */ 242 u8 queue_index; /* logical index of the ring*/ 243 u8 reg_idx; /* physical index of the ring */ 244 245 /* everything past this point are written often */ 246 u16 next_to_clean; 247 u16 next_to_use; 248 u16 next_to_alloc; 249 250 union { 251 /* TX */ 252 struct { 253 struct igc_tx_queue_stats tx_stats; 254 struct u64_stats_sync tx_syncp; 255 struct u64_stats_sync tx_syncp2; 256 }; 257 /* RX */ 258 struct { 259 struct igc_rx_queue_stats rx_stats; 260 struct igc_rx_packet_stats pkt_stats; 261 struct u64_stats_sync rx_syncp; 262 struct sk_buff *skb; 263 }; 264 }; 265 } ____cacheline_internodealigned_in_smp; 266 267 struct igc_q_vector { 268 struct igc_adapter *adapter; /* backlink */ 269 void __iomem *itr_register; 270 u32 eims_value; /* EIMS mask value */ 271 272 u16 itr_val; 273 u8 set_itr; 274 275 struct igc_ring_container rx, tx; 276 277 struct napi_struct napi; 278 279 struct rcu_head rcu; /* to avoid race with update stats on free */ 280 char name[IFNAMSIZ + 9]; 281 struct net_device poll_dev; 282 283 /* for dynamic allocation of rings associated with this q_vector */ 284 struct igc_ring ring[0] ____cacheline_internodealigned_in_smp; 285 }; 286 287 struct igc_mac_addr { 288 u8 addr[ETH_ALEN]; 289 u8 queue; 290 u8 state; /* bitmask */ 291 }; 292 293 #define IGC_MAC_STATE_DEFAULT 0x1 294 #define IGC_MAC_STATE_MODIFIED 0x2 295 #define IGC_MAC_STATE_IN_USE 0x4 296 297 /* Board specific private data structure */ 298 struct igc_adapter { 299 struct net_device *netdev; 300 301 unsigned long state; 302 unsigned int flags; 303 unsigned int num_q_vectors; 304 305 struct msix_entry *msix_entries; 306 307 /* TX */ 308 u16 tx_work_limit; 309 u32 tx_timeout_count; 310 int num_tx_queues; 311 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 312 313 /* RX */ 314 int num_rx_queues; 315 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 316 317 struct timer_list watchdog_timer; 318 struct timer_list dma_err_timer; 319 struct timer_list phy_info_timer; 320 321 u16 link_speed; 322 u16 link_duplex; 323 324 u8 port_num; 325 326 u8 __iomem *io_addr; 327 /* Interrupt Throttle Rate */ 328 u32 rx_itr_setting; 329 u32 tx_itr_setting; 330 331 struct work_struct reset_task; 332 struct work_struct watchdog_task; 333 struct work_struct dma_err_task; 334 bool fc_autoneg; 335 336 u8 tx_timeout_factor; 337 338 int msg_enable; 339 u32 max_frame_size; 340 u32 min_frame_size; 341 342 /* OS defined structs */ 343 struct pci_dev *pdev; 344 /* lock for statistics */ 345 spinlock_t stats64_lock; 346 struct rtnl_link_stats64 stats64; 347 348 /* structs defined in igc_hw.h */ 349 struct igc_hw hw; 350 struct igc_hw_stats stats; 351 352 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 353 u32 eims_enable_mask; 354 u32 eims_other; 355 356 u16 tx_ring_count; 357 u16 rx_ring_count; 358 359 u32 *shadow_vfta; 360 361 u32 rss_queues; 362 363 /* lock for RX network flow classification filter */ 364 spinlock_t nfc_lock; 365 366 struct igc_mac_addr *mac_table; 367 368 u8 rss_indir_tbl[IGC_RETA_SIZE]; 369 370 unsigned long link_check_timeout; 371 struct igc_info ei; 372 }; 373 374 /* igc_desc_unused - calculate if we have unused descriptors */ 375 static inline u16 igc_desc_unused(const struct igc_ring *ring) 376 { 377 u16 ntc = ring->next_to_clean; 378 u16 ntu = ring->next_to_use; 379 380 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 381 } 382 383 static inline s32 igc_get_phy_info(struct igc_hw *hw) 384 { 385 if (hw->phy.ops.get_phy_info) 386 return hw->phy.ops.get_phy_info(hw); 387 388 return 0; 389 } 390 391 static inline s32 igc_reset_phy(struct igc_hw *hw) 392 { 393 if (hw->phy.ops.reset) 394 return hw->phy.ops.reset(hw); 395 396 return 0; 397 } 398 399 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 400 { 401 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 402 } 403 404 enum igc_ring_flags_t { 405 IGC_RING_FLAG_RX_3K_BUFFER, 406 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 407 IGC_RING_FLAG_RX_SCTP_CSUM, 408 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 409 IGC_RING_FLAG_TX_CTX_IDX, 410 IGC_RING_FLAG_TX_DETECT_HANG 411 }; 412 413 #define ring_uses_large_buffer(ring) \ 414 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 415 416 #define ring_uses_build_skb(ring) \ 417 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 418 419 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 420 { 421 #if (PAGE_SIZE < 8192) 422 if (ring_uses_large_buffer(ring)) 423 return IGC_RXBUFFER_3072; 424 425 if (ring_uses_build_skb(ring)) 426 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 427 #endif 428 return IGC_RXBUFFER_2048; 429 } 430 431 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 432 { 433 #if (PAGE_SIZE < 8192) 434 if (ring_uses_large_buffer(ring)) 435 return 1; 436 #endif 437 return 0; 438 } 439 440 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 441 { 442 if (hw->phy.ops.read_reg) 443 return hw->phy.ops.read_reg(hw, offset, data); 444 445 return 0; 446 } 447 448 /* forward declaration */ 449 void igc_reinit_locked(struct igc_adapter *); 450 451 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 452 453 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 454 455 #define IGC_RX_DESC(R, i) \ 456 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 457 #define IGC_TX_DESC(R, i) \ 458 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 459 #define IGC_TX_CTXTDESC(R, i) \ 460 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 461 462 #endif /* _IGC_H_ */ 463