1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 void igc_ethtool_set_ops(struct net_device *); 20 21 /* Transmit and receive queues */ 22 #define IGC_MAX_RX_QUEUES 4 23 #define IGC_MAX_TX_QUEUES 4 24 25 #define MAX_Q_VECTORS 8 26 #define MAX_STD_JUMBO_FRAME_SIZE 9216 27 28 #define MAX_ETYPE_FILTER 8 29 #define IGC_RETA_SIZE 128 30 31 /* SDP support */ 32 #define IGC_N_EXTTS 2 33 #define IGC_N_PEROUT 2 34 #define IGC_N_SDP 4 35 36 #define MAX_FLEX_FILTER 32 37 38 enum igc_mac_filter_type { 39 IGC_MAC_FILTER_TYPE_DST = 0, 40 IGC_MAC_FILTER_TYPE_SRC 41 }; 42 43 struct igc_tx_queue_stats { 44 u64 packets; 45 u64 bytes; 46 u64 restart_queue; 47 u64 restart_queue2; 48 }; 49 50 struct igc_rx_queue_stats { 51 u64 packets; 52 u64 bytes; 53 u64 drops; 54 u64 csum_err; 55 u64 alloc_failed; 56 }; 57 58 struct igc_rx_packet_stats { 59 u64 ipv4_packets; /* IPv4 headers processed */ 60 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 61 u64 ipv6_packets; /* IPv6 headers processed */ 62 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 63 u64 tcp_packets; /* TCP headers processed */ 64 u64 udp_packets; /* UDP headers processed */ 65 u64 sctp_packets; /* SCTP headers processed */ 66 u64 nfs_packets; /* NFS headers processe */ 67 u64 other_packets; 68 }; 69 70 struct igc_ring_container { 71 struct igc_ring *ring; /* pointer to linked list of rings */ 72 unsigned int total_bytes; /* total bytes processed this int */ 73 unsigned int total_packets; /* total packets processed this int */ 74 u16 work_limit; /* total work allowed per interrupt */ 75 u8 count; /* total number of rings in vector */ 76 u8 itr; /* current ITR setting for ring */ 77 }; 78 79 struct igc_ring { 80 struct igc_q_vector *q_vector; /* backlink to q_vector */ 81 struct net_device *netdev; /* back pointer to net_device */ 82 struct device *dev; /* device for dma mapping */ 83 union { /* array of buffer info structs */ 84 struct igc_tx_buffer *tx_buffer_info; 85 struct igc_rx_buffer *rx_buffer_info; 86 }; 87 void *desc; /* descriptor ring memory */ 88 unsigned long flags; /* ring specific flags */ 89 void __iomem *tail; /* pointer to ring tail register */ 90 dma_addr_t dma; /* phys address of the ring */ 91 unsigned int size; /* length of desc. ring in bytes */ 92 93 u16 count; /* number of desc. in the ring */ 94 u8 queue_index; /* logical index of the ring*/ 95 u8 reg_idx; /* physical index of the ring */ 96 bool launchtime_enable; /* true if LaunchTime is enabled */ 97 98 u32 start_time; 99 u32 end_time; 100 101 /* everything past this point are written often */ 102 u16 next_to_clean; 103 u16 next_to_use; 104 u16 next_to_alloc; 105 106 union { 107 /* TX */ 108 struct { 109 struct igc_tx_queue_stats tx_stats; 110 struct u64_stats_sync tx_syncp; 111 struct u64_stats_sync tx_syncp2; 112 }; 113 /* RX */ 114 struct { 115 struct igc_rx_queue_stats rx_stats; 116 struct igc_rx_packet_stats pkt_stats; 117 struct u64_stats_sync rx_syncp; 118 struct sk_buff *skb; 119 }; 120 }; 121 122 struct xdp_rxq_info xdp_rxq; 123 struct xsk_buff_pool *xsk_pool; 124 } ____cacheline_internodealigned_in_smp; 125 126 /* Board specific private data structure */ 127 struct igc_adapter { 128 struct net_device *netdev; 129 130 struct ethtool_eee eee; 131 u16 eee_advert; 132 133 unsigned long state; 134 unsigned int flags; 135 unsigned int num_q_vectors; 136 137 struct msix_entry *msix_entries; 138 139 /* TX */ 140 u16 tx_work_limit; 141 u32 tx_timeout_count; 142 int num_tx_queues; 143 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 144 145 /* RX */ 146 int num_rx_queues; 147 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 148 149 struct timer_list watchdog_timer; 150 struct timer_list dma_err_timer; 151 struct timer_list phy_info_timer; 152 153 u32 wol; 154 u32 en_mng_pt; 155 u16 link_speed; 156 u16 link_duplex; 157 158 u8 port_num; 159 160 u8 __iomem *io_addr; 161 /* Interrupt Throttle Rate */ 162 u32 rx_itr_setting; 163 u32 tx_itr_setting; 164 165 struct work_struct reset_task; 166 struct work_struct watchdog_task; 167 struct work_struct dma_err_task; 168 bool fc_autoneg; 169 170 u8 tx_timeout_factor; 171 172 int msg_enable; 173 u32 max_frame_size; 174 u32 min_frame_size; 175 176 ktime_t base_time; 177 ktime_t cycle_time; 178 179 /* OS defined structs */ 180 struct pci_dev *pdev; 181 /* lock for statistics */ 182 spinlock_t stats64_lock; 183 struct rtnl_link_stats64 stats64; 184 185 /* structs defined in igc_hw.h */ 186 struct igc_hw hw; 187 struct igc_hw_stats stats; 188 189 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 190 u32 eims_enable_mask; 191 u32 eims_other; 192 193 u16 tx_ring_count; 194 u16 rx_ring_count; 195 196 u32 tx_hwtstamp_timeouts; 197 u32 tx_hwtstamp_skipped; 198 u32 rx_hwtstamp_cleared; 199 200 u32 rss_queues; 201 u32 rss_indir_tbl_init; 202 203 /* Any access to elements in nfc_rule_list is protected by the 204 * nfc_rule_lock. 205 */ 206 struct mutex nfc_rule_lock; 207 struct list_head nfc_rule_list; 208 unsigned int nfc_rule_count; 209 210 u8 rss_indir_tbl[IGC_RETA_SIZE]; 211 212 unsigned long link_check_timeout; 213 struct igc_info ei; 214 215 u32 test_icr; 216 217 struct ptp_clock *ptp_clock; 218 struct ptp_clock_info ptp_caps; 219 struct work_struct ptp_tx_work; 220 struct sk_buff *ptp_tx_skb; 221 struct hwtstamp_config tstamp_config; 222 unsigned long ptp_tx_start; 223 unsigned int ptp_flags; 224 /* System time value lock */ 225 spinlock_t tmreg_lock; 226 struct cyclecounter cc; 227 struct timecounter tc; 228 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 229 ktime_t ptp_reset_start; /* Reset time in clock mono */ 230 struct system_time_snapshot snapshot; 231 232 char fw_version[32]; 233 234 struct bpf_prog *xdp_prog; 235 236 bool pps_sys_wrap_on; 237 238 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 239 struct { 240 struct timespec64 start; 241 struct timespec64 period; 242 } perout[IGC_N_PEROUT]; 243 }; 244 245 void igc_up(struct igc_adapter *adapter); 246 void igc_down(struct igc_adapter *adapter); 247 int igc_open(struct net_device *netdev); 248 int igc_close(struct net_device *netdev); 249 int igc_setup_tx_resources(struct igc_ring *ring); 250 int igc_setup_rx_resources(struct igc_ring *ring); 251 void igc_free_tx_resources(struct igc_ring *ring); 252 void igc_free_rx_resources(struct igc_ring *ring); 253 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 254 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 255 const u32 max_rss_queues); 256 int igc_reinit_queues(struct igc_adapter *adapter); 257 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 258 bool igc_has_link(struct igc_adapter *adapter); 259 void igc_reset(struct igc_adapter *adapter); 260 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 261 void igc_update_stats(struct igc_adapter *adapter); 262 void igc_disable_rx_ring(struct igc_ring *ring); 263 void igc_enable_rx_ring(struct igc_ring *ring); 264 void igc_disable_tx_ring(struct igc_ring *ring); 265 void igc_enable_tx_ring(struct igc_ring *ring); 266 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 267 268 /* igc_dump declarations */ 269 void igc_rings_dump(struct igc_adapter *adapter); 270 void igc_regs_dump(struct igc_adapter *adapter); 271 272 extern char igc_driver_name[]; 273 274 #define IGC_REGS_LEN 740 275 276 /* flags controlling PTP/1588 function */ 277 #define IGC_PTP_ENABLED BIT(0) 278 279 /* Flags definitions */ 280 #define IGC_FLAG_HAS_MSI BIT(0) 281 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 282 #define IGC_FLAG_DMAC BIT(4) 283 #define IGC_FLAG_PTP BIT(8) 284 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 285 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 286 #define IGC_FLAG_MEDIA_RESET BIT(10) 287 #define IGC_FLAG_MAS_ENABLE BIT(12) 288 #define IGC_FLAG_HAS_MSIX BIT(13) 289 #define IGC_FLAG_EEE BIT(14) 290 #define IGC_FLAG_VLAN_PROMISC BIT(15) 291 #define IGC_FLAG_RX_LEGACY BIT(16) 292 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 293 294 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 295 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 296 297 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 298 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 299 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 300 301 /* Interrupt defines */ 302 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 303 #define IGC_4K_ITR 980 304 #define IGC_20K_ITR 196 305 #define IGC_70K_ITR 56 306 307 #define IGC_DEFAULT_ITR 3 /* dynamic */ 308 #define IGC_MAX_ITR_USECS 10000 309 #define IGC_MIN_ITR_USECS 10 310 #define NON_Q_VECTORS 1 311 #define MAX_MSIX_ENTRIES 10 312 313 /* TX/RX descriptor defines */ 314 #define IGC_DEFAULT_TXD 256 315 #define IGC_DEFAULT_TX_WORK 128 316 #define IGC_MIN_TXD 80 317 #define IGC_MAX_TXD 4096 318 319 #define IGC_DEFAULT_RXD 256 320 #define IGC_MIN_RXD 80 321 #define IGC_MAX_RXD 4096 322 323 /* Supported Rx Buffer Sizes */ 324 #define IGC_RXBUFFER_256 256 325 #define IGC_RXBUFFER_2048 2048 326 #define IGC_RXBUFFER_3072 3072 327 328 #define AUTO_ALL_MODES 0 329 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 330 331 /* Transmit and receive latency (for PTP timestamps) */ 332 #define IGC_I225_TX_LATENCY_10 240 333 #define IGC_I225_TX_LATENCY_100 58 334 #define IGC_I225_TX_LATENCY_1000 80 335 #define IGC_I225_TX_LATENCY_2500 1325 336 #define IGC_I225_RX_LATENCY_10 6450 337 #define IGC_I225_RX_LATENCY_100 185 338 #define IGC_I225_RX_LATENCY_1000 300 339 #define IGC_I225_RX_LATENCY_2500 1485 340 341 /* RX and TX descriptor control thresholds. 342 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 343 * descriptors available in its onboard memory. 344 * Setting this to 0 disables RX descriptor prefetch. 345 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 346 * available in host memory. 347 * If PTHRESH is 0, this should also be 0. 348 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 349 * descriptors until either it has this many to write back, or the 350 * ITR timer expires. 351 */ 352 #define IGC_RX_PTHRESH 8 353 #define IGC_RX_HTHRESH 8 354 #define IGC_TX_PTHRESH 8 355 #define IGC_TX_HTHRESH 1 356 #define IGC_RX_WTHRESH 4 357 #define IGC_TX_WTHRESH 16 358 359 #define IGC_RX_DMA_ATTR \ 360 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 361 362 #define IGC_TS_HDR_LEN 16 363 364 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 365 366 #if (PAGE_SIZE < 8192) 367 #define IGC_MAX_FRAME_BUILD_SKB \ 368 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 369 #else 370 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 371 #endif 372 373 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 374 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 375 376 /* VLAN info */ 377 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 378 #define IGC_TX_FLAGS_VLAN_SHIFT 16 379 380 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 381 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 382 const u32 stat_err_bits) 383 { 384 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 385 } 386 387 enum igc_state_t { 388 __IGC_TESTING, 389 __IGC_RESETTING, 390 __IGC_DOWN, 391 __IGC_PTP_TX_IN_PROGRESS, 392 }; 393 394 enum igc_tx_flags { 395 /* cmd_type flags */ 396 IGC_TX_FLAGS_VLAN = 0x01, 397 IGC_TX_FLAGS_TSO = 0x02, 398 IGC_TX_FLAGS_TSTAMP = 0x04, 399 400 /* olinfo flags */ 401 IGC_TX_FLAGS_IPV4 = 0x10, 402 IGC_TX_FLAGS_CSUM = 0x20, 403 }; 404 405 enum igc_boards { 406 board_base, 407 }; 408 409 /* The largest size we can write to the descriptor is 65535. In order to 410 * maintain a power of two alignment we have to limit ourselves to 32K. 411 */ 412 #define IGC_MAX_TXD_PWR 15 413 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 414 415 /* Tx Descriptors needed, worst case */ 416 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 417 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 418 419 enum igc_tx_buffer_type { 420 IGC_TX_BUFFER_TYPE_SKB, 421 IGC_TX_BUFFER_TYPE_XDP, 422 IGC_TX_BUFFER_TYPE_XSK, 423 }; 424 425 /* wrapper around a pointer to a socket buffer, 426 * so a DMA handle can be stored along with the buffer 427 */ 428 struct igc_tx_buffer { 429 union igc_adv_tx_desc *next_to_watch; 430 unsigned long time_stamp; 431 enum igc_tx_buffer_type type; 432 union { 433 struct sk_buff *skb; 434 struct xdp_frame *xdpf; 435 }; 436 unsigned int bytecount; 437 u16 gso_segs; 438 __be16 protocol; 439 440 DEFINE_DMA_UNMAP_ADDR(dma); 441 DEFINE_DMA_UNMAP_LEN(len); 442 u32 tx_flags; 443 }; 444 445 struct igc_rx_buffer { 446 union { 447 struct { 448 dma_addr_t dma; 449 struct page *page; 450 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 451 __u32 page_offset; 452 #else 453 __u16 page_offset; 454 #endif 455 __u16 pagecnt_bias; 456 }; 457 struct xdp_buff *xdp; 458 }; 459 }; 460 461 struct igc_q_vector { 462 struct igc_adapter *adapter; /* backlink */ 463 void __iomem *itr_register; 464 u32 eims_value; /* EIMS mask value */ 465 466 u16 itr_val; 467 u8 set_itr; 468 469 struct igc_ring_container rx, tx; 470 471 struct napi_struct napi; 472 473 struct rcu_head rcu; /* to avoid race with update stats on free */ 474 char name[IFNAMSIZ + 9]; 475 struct net_device poll_dev; 476 477 /* for dynamic allocation of rings associated with this q_vector */ 478 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 479 }; 480 481 enum igc_filter_match_flags { 482 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 483 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 484 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 485 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 486 IGC_FILTER_FLAG_USER_DATA = BIT(4), 487 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 488 }; 489 490 struct igc_nfc_filter { 491 u8 match_flags; 492 u16 etype; 493 __be16 vlan_etype; 494 u16 vlan_tci; 495 u8 src_addr[ETH_ALEN]; 496 u8 dst_addr[ETH_ALEN]; 497 u8 user_data[8]; 498 u8 user_mask[8]; 499 u8 flex_index; 500 u8 rx_queue; 501 u8 prio; 502 u8 immediate_irq; 503 u8 drop; 504 }; 505 506 struct igc_nfc_rule { 507 struct list_head list; 508 struct igc_nfc_filter filter; 509 u32 location; 510 u16 action; 511 bool flex; 512 }; 513 514 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 515 * based, 8 ethertype based and 32 Flex filter based rules. 516 */ 517 #define IGC_MAX_RXNFC_RULES 64 518 519 struct igc_flex_filter { 520 u8 index; 521 u8 data[128]; 522 u8 mask[16]; 523 u8 length; 524 u8 rx_queue; 525 u8 prio; 526 u8 immediate_irq; 527 u8 drop; 528 }; 529 530 /* igc_desc_unused - calculate if we have unused descriptors */ 531 static inline u16 igc_desc_unused(const struct igc_ring *ring) 532 { 533 u16 ntc = ring->next_to_clean; 534 u16 ntu = ring->next_to_use; 535 536 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 537 } 538 539 static inline s32 igc_get_phy_info(struct igc_hw *hw) 540 { 541 if (hw->phy.ops.get_phy_info) 542 return hw->phy.ops.get_phy_info(hw); 543 544 return 0; 545 } 546 547 static inline s32 igc_reset_phy(struct igc_hw *hw) 548 { 549 if (hw->phy.ops.reset) 550 return hw->phy.ops.reset(hw); 551 552 return 0; 553 } 554 555 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 556 { 557 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 558 } 559 560 enum igc_ring_flags_t { 561 IGC_RING_FLAG_RX_3K_BUFFER, 562 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 563 IGC_RING_FLAG_RX_SCTP_CSUM, 564 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 565 IGC_RING_FLAG_TX_CTX_IDX, 566 IGC_RING_FLAG_TX_DETECT_HANG, 567 IGC_RING_FLAG_AF_XDP_ZC, 568 }; 569 570 #define ring_uses_large_buffer(ring) \ 571 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 572 #define set_ring_uses_large_buffer(ring) \ 573 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 574 #define clear_ring_uses_large_buffer(ring) \ 575 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 576 577 #define ring_uses_build_skb(ring) \ 578 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 579 580 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 581 { 582 #if (PAGE_SIZE < 8192) 583 if (ring_uses_large_buffer(ring)) 584 return IGC_RXBUFFER_3072; 585 586 if (ring_uses_build_skb(ring)) 587 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 588 #endif 589 return IGC_RXBUFFER_2048; 590 } 591 592 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 593 { 594 #if (PAGE_SIZE < 8192) 595 if (ring_uses_large_buffer(ring)) 596 return 1; 597 #endif 598 return 0; 599 } 600 601 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 602 { 603 if (hw->phy.ops.read_reg) 604 return hw->phy.ops.read_reg(hw, offset, data); 605 606 return -EOPNOTSUPP; 607 } 608 609 void igc_reinit_locked(struct igc_adapter *); 610 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 611 u32 location); 612 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 613 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 614 615 void igc_ptp_init(struct igc_adapter *adapter); 616 void igc_ptp_reset(struct igc_adapter *adapter); 617 void igc_ptp_suspend(struct igc_adapter *adapter); 618 void igc_ptp_stop(struct igc_adapter *adapter); 619 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 620 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 621 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 622 void igc_ptp_tx_hang(struct igc_adapter *adapter); 623 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 624 625 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 626 627 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 628 629 #define IGC_RX_DESC(R, i) \ 630 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 631 #define IGC_TX_DESC(R, i) \ 632 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 633 #define IGC_TX_CTXTDESC(R, i) \ 634 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 635 636 #endif /* _IGC_H_ */ 637