1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 /* forward declaration */ 20 void igc_set_ethtool_ops(struct net_device *); 21 22 struct igc_adapter; 23 struct igc_ring; 24 25 void igc_up(struct igc_adapter *adapter); 26 void igc_down(struct igc_adapter *adapter); 27 int igc_setup_tx_resources(struct igc_ring *ring); 28 int igc_setup_rx_resources(struct igc_ring *ring); 29 void igc_free_tx_resources(struct igc_ring *ring); 30 void igc_free_rx_resources(struct igc_ring *ring); 31 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 32 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 33 const u32 max_rss_queues); 34 int igc_reinit_queues(struct igc_adapter *adapter); 35 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 36 bool igc_has_link(struct igc_adapter *adapter); 37 void igc_reset(struct igc_adapter *adapter); 38 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 39 int igc_add_mac_steering_filter(struct igc_adapter *adapter, 40 const u8 *addr, u8 queue, u8 flags); 41 int igc_del_mac_steering_filter(struct igc_adapter *adapter, 42 const u8 *addr, u8 queue, u8 flags); 43 void igc_update_stats(struct igc_adapter *adapter); 44 45 /* igc_dump declarations */ 46 void igc_rings_dump(struct igc_adapter *adapter); 47 void igc_regs_dump(struct igc_adapter *adapter); 48 49 extern char igc_driver_name[]; 50 extern char igc_driver_version[]; 51 52 #define IGC_REGS_LEN 740 53 #define IGC_RETA_SIZE 128 54 55 /* flags controlling PTP/1588 function */ 56 #define IGC_PTP_ENABLED BIT(0) 57 58 /* Interrupt defines */ 59 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 60 61 /* Flags definitions */ 62 #define IGC_FLAG_HAS_MSI BIT(0) 63 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 64 #define IGC_FLAG_DMAC BIT(4) 65 #define IGC_FLAG_PTP BIT(8) 66 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 67 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 68 #define IGC_FLAG_MEDIA_RESET BIT(10) 69 #define IGC_FLAG_MAS_ENABLE BIT(12) 70 #define IGC_FLAG_HAS_MSIX BIT(13) 71 #define IGC_FLAG_VLAN_PROMISC BIT(15) 72 #define IGC_FLAG_RX_LEGACY BIT(16) 73 74 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 75 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 76 77 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 78 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 79 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 80 81 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 82 #define IGC_4K_ITR 980 83 #define IGC_20K_ITR 196 84 #define IGC_70K_ITR 56 85 86 #define IGC_DEFAULT_ITR 3 /* dynamic */ 87 #define IGC_MAX_ITR_USECS 10000 88 #define IGC_MIN_ITR_USECS 10 89 #define NON_Q_VECTORS 1 90 #define MAX_MSIX_ENTRIES 10 91 92 /* TX/RX descriptor defines */ 93 #define IGC_DEFAULT_TXD 256 94 #define IGC_DEFAULT_TX_WORK 128 95 #define IGC_MIN_TXD 80 96 #define IGC_MAX_TXD 4096 97 98 #define IGC_DEFAULT_RXD 256 99 #define IGC_MIN_RXD 80 100 #define IGC_MAX_RXD 4096 101 102 /* Transmit and receive queues */ 103 #define IGC_MAX_RX_QUEUES 4 104 #define IGC_MAX_TX_QUEUES 4 105 106 #define MAX_Q_VECTORS 8 107 #define MAX_STD_JUMBO_FRAME_SIZE 9216 108 109 /* Supported Rx Buffer Sizes */ 110 #define IGC_RXBUFFER_256 256 111 #define IGC_RXBUFFER_2048 2048 112 #define IGC_RXBUFFER_3072 3072 113 114 #define AUTO_ALL_MODES 0 115 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 116 117 /* Transmit and receive latency (for PTP timestamps) */ 118 /* FIXME: These values were estimated using the ones that i225 has as 119 * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 120 * need to confirm them. 121 */ 122 #define IGC_I225_TX_LATENCY_10 9542 123 #define IGC_I225_TX_LATENCY_100 1024 124 #define IGC_I225_TX_LATENCY_1000 178 125 #define IGC_I225_TX_LATENCY_2500 64 126 #define IGC_I225_RX_LATENCY_10 20662 127 #define IGC_I225_RX_LATENCY_100 2213 128 #define IGC_I225_RX_LATENCY_1000 448 129 #define IGC_I225_RX_LATENCY_2500 160 130 131 /* RX and TX descriptor control thresholds. 132 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 133 * descriptors available in its onboard memory. 134 * Setting this to 0 disables RX descriptor prefetch. 135 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 136 * available in host memory. 137 * If PTHRESH is 0, this should also be 0. 138 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 139 * descriptors until either it has this many to write back, or the 140 * ITR timer expires. 141 */ 142 #define IGC_RX_PTHRESH 8 143 #define IGC_RX_HTHRESH 8 144 #define IGC_TX_PTHRESH 8 145 #define IGC_TX_HTHRESH 1 146 #define IGC_RX_WTHRESH 4 147 #define IGC_TX_WTHRESH 16 148 149 #define IGC_RX_DMA_ATTR \ 150 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 151 152 #define IGC_TS_HDR_LEN 16 153 154 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 155 156 #if (PAGE_SIZE < 8192) 157 #define IGC_MAX_FRAME_BUILD_SKB \ 158 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 159 #else 160 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 161 #endif 162 163 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 164 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 165 166 /* VLAN info */ 167 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 168 169 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 170 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 171 const u32 stat_err_bits) 172 { 173 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 174 } 175 176 enum igc_state_t { 177 __IGC_TESTING, 178 __IGC_RESETTING, 179 __IGC_DOWN, 180 __IGC_PTP_TX_IN_PROGRESS, 181 }; 182 183 enum igc_tx_flags { 184 /* cmd_type flags */ 185 IGC_TX_FLAGS_VLAN = 0x01, 186 IGC_TX_FLAGS_TSO = 0x02, 187 IGC_TX_FLAGS_TSTAMP = 0x04, 188 189 /* olinfo flags */ 190 IGC_TX_FLAGS_IPV4 = 0x10, 191 IGC_TX_FLAGS_CSUM = 0x20, 192 }; 193 194 enum igc_boards { 195 board_base, 196 }; 197 198 /* The largest size we can write to the descriptor is 65535. In order to 199 * maintain a power of two alignment we have to limit ourselves to 32K. 200 */ 201 #define IGC_MAX_TXD_PWR 15 202 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 203 204 /* Tx Descriptors needed, worst case */ 205 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 206 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 207 208 /* wrapper around a pointer to a socket buffer, 209 * so a DMA handle can be stored along with the buffer 210 */ 211 struct igc_tx_buffer { 212 union igc_adv_tx_desc *next_to_watch; 213 unsigned long time_stamp; 214 struct sk_buff *skb; 215 unsigned int bytecount; 216 u16 gso_segs; 217 __be16 protocol; 218 219 DEFINE_DMA_UNMAP_ADDR(dma); 220 DEFINE_DMA_UNMAP_LEN(len); 221 u32 tx_flags; 222 }; 223 224 struct igc_rx_buffer { 225 dma_addr_t dma; 226 struct page *page; 227 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 228 __u32 page_offset; 229 #else 230 __u16 page_offset; 231 #endif 232 __u16 pagecnt_bias; 233 }; 234 235 struct igc_tx_queue_stats { 236 u64 packets; 237 u64 bytes; 238 u64 restart_queue; 239 u64 restart_queue2; 240 }; 241 242 struct igc_rx_queue_stats { 243 u64 packets; 244 u64 bytes; 245 u64 drops; 246 u64 csum_err; 247 u64 alloc_failed; 248 }; 249 250 struct igc_rx_packet_stats { 251 u64 ipv4_packets; /* IPv4 headers processed */ 252 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 253 u64 ipv6_packets; /* IPv6 headers processed */ 254 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 255 u64 tcp_packets; /* TCP headers processed */ 256 u64 udp_packets; /* UDP headers processed */ 257 u64 sctp_packets; /* SCTP headers processed */ 258 u64 nfs_packets; /* NFS headers processe */ 259 u64 other_packets; 260 }; 261 262 struct igc_ring_container { 263 struct igc_ring *ring; /* pointer to linked list of rings */ 264 unsigned int total_bytes; /* total bytes processed this int */ 265 unsigned int total_packets; /* total packets processed this int */ 266 u16 work_limit; /* total work allowed per interrupt */ 267 u8 count; /* total number of rings in vector */ 268 u8 itr; /* current ITR setting for ring */ 269 }; 270 271 struct igc_ring { 272 struct igc_q_vector *q_vector; /* backlink to q_vector */ 273 struct net_device *netdev; /* back pointer to net_device */ 274 struct device *dev; /* device for dma mapping */ 275 union { /* array of buffer info structs */ 276 struct igc_tx_buffer *tx_buffer_info; 277 struct igc_rx_buffer *rx_buffer_info; 278 }; 279 void *desc; /* descriptor ring memory */ 280 unsigned long flags; /* ring specific flags */ 281 void __iomem *tail; /* pointer to ring tail register */ 282 dma_addr_t dma; /* phys address of the ring */ 283 unsigned int size; /* length of desc. ring in bytes */ 284 285 u16 count; /* number of desc. in the ring */ 286 u8 queue_index; /* logical index of the ring*/ 287 u8 reg_idx; /* physical index of the ring */ 288 bool launchtime_enable; /* true if LaunchTime is enabled */ 289 290 /* everything past this point are written often */ 291 u16 next_to_clean; 292 u16 next_to_use; 293 u16 next_to_alloc; 294 295 union { 296 /* TX */ 297 struct { 298 struct igc_tx_queue_stats tx_stats; 299 struct u64_stats_sync tx_syncp; 300 struct u64_stats_sync tx_syncp2; 301 }; 302 /* RX */ 303 struct { 304 struct igc_rx_queue_stats rx_stats; 305 struct igc_rx_packet_stats pkt_stats; 306 struct u64_stats_sync rx_syncp; 307 struct sk_buff *skb; 308 }; 309 }; 310 } ____cacheline_internodealigned_in_smp; 311 312 struct igc_q_vector { 313 struct igc_adapter *adapter; /* backlink */ 314 void __iomem *itr_register; 315 u32 eims_value; /* EIMS mask value */ 316 317 u16 itr_val; 318 u8 set_itr; 319 320 struct igc_ring_container rx, tx; 321 322 struct napi_struct napi; 323 324 struct rcu_head rcu; /* to avoid race with update stats on free */ 325 char name[IFNAMSIZ + 9]; 326 struct net_device poll_dev; 327 328 /* for dynamic allocation of rings associated with this q_vector */ 329 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 330 }; 331 332 #define MAX_ETYPE_FILTER (4 - 1) 333 334 enum igc_filter_match_flags { 335 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 336 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 337 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 338 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 339 }; 340 341 /* RX network flow classification data structure */ 342 struct igc_nfc_input { 343 /* Byte layout in order, all values with MSB first: 344 * match_flags - 1 byte 345 * etype - 2 bytes 346 * vlan_tci - 2 bytes 347 */ 348 u8 match_flags; 349 __be16 etype; 350 __be16 vlan_tci; 351 u8 src_addr[ETH_ALEN]; 352 u8 dst_addr[ETH_ALEN]; 353 }; 354 355 struct igc_nfc_filter { 356 struct hlist_node nfc_node; 357 struct igc_nfc_input filter; 358 unsigned long cookie; 359 u16 etype_reg_index; 360 u16 sw_idx; 361 u16 action; 362 }; 363 364 struct igc_mac_addr { 365 u8 addr[ETH_ALEN]; 366 u8 queue; 367 u8 state; /* bitmask */ 368 }; 369 370 #define IGC_MAC_STATE_DEFAULT 0x1 371 #define IGC_MAC_STATE_IN_USE 0x2 372 #define IGC_MAC_STATE_SRC_ADDR 0x4 373 #define IGC_MAC_STATE_QUEUE_STEERING 0x8 374 375 #define IGC_MAX_RXNFC_FILTERS 16 376 377 /* Board specific private data structure */ 378 struct igc_adapter { 379 struct net_device *netdev; 380 381 unsigned long state; 382 unsigned int flags; 383 unsigned int num_q_vectors; 384 385 struct msix_entry *msix_entries; 386 387 /* TX */ 388 u16 tx_work_limit; 389 u32 tx_timeout_count; 390 int num_tx_queues; 391 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 392 393 /* RX */ 394 int num_rx_queues; 395 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 396 397 struct timer_list watchdog_timer; 398 struct timer_list dma_err_timer; 399 struct timer_list phy_info_timer; 400 401 u32 wol; 402 u32 en_mng_pt; 403 u16 link_speed; 404 u16 link_duplex; 405 406 u8 port_num; 407 408 u8 __iomem *io_addr; 409 /* Interrupt Throttle Rate */ 410 u32 rx_itr_setting; 411 u32 tx_itr_setting; 412 413 struct work_struct reset_task; 414 struct work_struct watchdog_task; 415 struct work_struct dma_err_task; 416 bool fc_autoneg; 417 418 u8 tx_timeout_factor; 419 420 int msg_enable; 421 u32 max_frame_size; 422 u32 min_frame_size; 423 424 /* OS defined structs */ 425 struct pci_dev *pdev; 426 /* lock for statistics */ 427 spinlock_t stats64_lock; 428 struct rtnl_link_stats64 stats64; 429 430 /* structs defined in igc_hw.h */ 431 struct igc_hw hw; 432 struct igc_hw_stats stats; 433 434 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 435 u32 eims_enable_mask; 436 u32 eims_other; 437 438 u16 tx_ring_count; 439 u16 rx_ring_count; 440 441 u32 tx_hwtstamp_timeouts; 442 u32 tx_hwtstamp_skipped; 443 u32 rx_hwtstamp_cleared; 444 445 u32 rss_queues; 446 u32 rss_indir_tbl_init; 447 448 /* RX network flow classification support */ 449 struct hlist_head nfc_filter_list; 450 struct hlist_head cls_flower_list; 451 unsigned int nfc_filter_count; 452 453 /* lock for RX network flow classification filter */ 454 spinlock_t nfc_lock; 455 bool etype_bitmap[MAX_ETYPE_FILTER]; 456 457 struct igc_mac_addr *mac_table; 458 459 u8 rss_indir_tbl[IGC_RETA_SIZE]; 460 461 unsigned long link_check_timeout; 462 struct igc_info ei; 463 464 struct ptp_clock *ptp_clock; 465 struct ptp_clock_info ptp_caps; 466 struct work_struct ptp_tx_work; 467 struct sk_buff *ptp_tx_skb; 468 struct hwtstamp_config tstamp_config; 469 unsigned long ptp_tx_start; 470 unsigned long last_rx_ptp_check; 471 unsigned long last_rx_timestamp; 472 unsigned int ptp_flags; 473 /* System time value lock */ 474 spinlock_t tmreg_lock; 475 struct cyclecounter cc; 476 struct timecounter tc; 477 }; 478 479 /* igc_desc_unused - calculate if we have unused descriptors */ 480 static inline u16 igc_desc_unused(const struct igc_ring *ring) 481 { 482 u16 ntc = ring->next_to_clean; 483 u16 ntu = ring->next_to_use; 484 485 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 486 } 487 488 static inline s32 igc_get_phy_info(struct igc_hw *hw) 489 { 490 if (hw->phy.ops.get_phy_info) 491 return hw->phy.ops.get_phy_info(hw); 492 493 return 0; 494 } 495 496 static inline s32 igc_reset_phy(struct igc_hw *hw) 497 { 498 if (hw->phy.ops.reset) 499 return hw->phy.ops.reset(hw); 500 501 return 0; 502 } 503 504 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 505 { 506 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 507 } 508 509 enum igc_ring_flags_t { 510 IGC_RING_FLAG_RX_3K_BUFFER, 511 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 512 IGC_RING_FLAG_RX_SCTP_CSUM, 513 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 514 IGC_RING_FLAG_TX_CTX_IDX, 515 IGC_RING_FLAG_TX_DETECT_HANG 516 }; 517 518 #define ring_uses_large_buffer(ring) \ 519 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 520 521 #define ring_uses_build_skb(ring) \ 522 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 523 524 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 525 { 526 #if (PAGE_SIZE < 8192) 527 if (ring_uses_large_buffer(ring)) 528 return IGC_RXBUFFER_3072; 529 530 if (ring_uses_build_skb(ring)) 531 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 532 #endif 533 return IGC_RXBUFFER_2048; 534 } 535 536 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 537 { 538 #if (PAGE_SIZE < 8192) 539 if (ring_uses_large_buffer(ring)) 540 return 1; 541 #endif 542 return 0; 543 } 544 545 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 546 { 547 if (hw->phy.ops.read_reg) 548 return hw->phy.ops.read_reg(hw, offset, data); 549 550 return 0; 551 } 552 553 /* forward declaration */ 554 void igc_reinit_locked(struct igc_adapter *); 555 int igc_add_filter(struct igc_adapter *adapter, 556 struct igc_nfc_filter *input); 557 int igc_erase_filter(struct igc_adapter *adapter, 558 struct igc_nfc_filter *input); 559 560 void igc_ptp_init(struct igc_adapter *adapter); 561 void igc_ptp_reset(struct igc_adapter *adapter); 562 void igc_ptp_suspend(struct igc_adapter *adapter); 563 void igc_ptp_stop(struct igc_adapter *adapter); 564 void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 565 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 566 struct sk_buff *skb); 567 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 568 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 569 void igc_ptp_tx_hang(struct igc_adapter *adapter); 570 571 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 572 573 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 574 575 #define IGC_RX_DESC(R, i) \ 576 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 577 #define IGC_TX_DESC(R, i) \ 578 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 579 #define IGC_TX_CTXTDESC(R, i) \ 580 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 581 582 #endif /* _IGC_H_ */ 583