1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 void igc_ethtool_set_ops(struct net_device *); 20 21 /* Transmit and receive queues */ 22 #define IGC_MAX_RX_QUEUES 4 23 #define IGC_MAX_TX_QUEUES 4 24 25 #define MAX_Q_VECTORS 8 26 #define MAX_STD_JUMBO_FRAME_SIZE 9216 27 28 #define MAX_ETYPE_FILTER 8 29 #define IGC_RETA_SIZE 128 30 31 enum igc_mac_filter_type { 32 IGC_MAC_FILTER_TYPE_DST = 0, 33 IGC_MAC_FILTER_TYPE_SRC 34 }; 35 36 struct igc_tx_queue_stats { 37 u64 packets; 38 u64 bytes; 39 u64 restart_queue; 40 u64 restart_queue2; 41 }; 42 43 struct igc_rx_queue_stats { 44 u64 packets; 45 u64 bytes; 46 u64 drops; 47 u64 csum_err; 48 u64 alloc_failed; 49 }; 50 51 struct igc_rx_packet_stats { 52 u64 ipv4_packets; /* IPv4 headers processed */ 53 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 54 u64 ipv6_packets; /* IPv6 headers processed */ 55 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 56 u64 tcp_packets; /* TCP headers processed */ 57 u64 udp_packets; /* UDP headers processed */ 58 u64 sctp_packets; /* SCTP headers processed */ 59 u64 nfs_packets; /* NFS headers processe */ 60 u64 other_packets; 61 }; 62 63 struct igc_ring_container { 64 struct igc_ring *ring; /* pointer to linked list of rings */ 65 unsigned int total_bytes; /* total bytes processed this int */ 66 unsigned int total_packets; /* total packets processed this int */ 67 u16 work_limit; /* total work allowed per interrupt */ 68 u8 count; /* total number of rings in vector */ 69 u8 itr; /* current ITR setting for ring */ 70 }; 71 72 struct igc_ring { 73 struct igc_q_vector *q_vector; /* backlink to q_vector */ 74 struct net_device *netdev; /* back pointer to net_device */ 75 struct device *dev; /* device for dma mapping */ 76 union { /* array of buffer info structs */ 77 struct igc_tx_buffer *tx_buffer_info; 78 struct igc_rx_buffer *rx_buffer_info; 79 }; 80 void *desc; /* descriptor ring memory */ 81 unsigned long flags; /* ring specific flags */ 82 void __iomem *tail; /* pointer to ring tail register */ 83 dma_addr_t dma; /* phys address of the ring */ 84 unsigned int size; /* length of desc. ring in bytes */ 85 86 u16 count; /* number of desc. in the ring */ 87 u8 queue_index; /* logical index of the ring*/ 88 u8 reg_idx; /* physical index of the ring */ 89 bool launchtime_enable; /* true if LaunchTime is enabled */ 90 91 u32 start_time; 92 u32 end_time; 93 94 /* everything past this point are written often */ 95 u16 next_to_clean; 96 u16 next_to_use; 97 u16 next_to_alloc; 98 99 union { 100 /* TX */ 101 struct { 102 struct igc_tx_queue_stats tx_stats; 103 struct u64_stats_sync tx_syncp; 104 struct u64_stats_sync tx_syncp2; 105 }; 106 /* RX */ 107 struct { 108 struct igc_rx_queue_stats rx_stats; 109 struct igc_rx_packet_stats pkt_stats; 110 struct u64_stats_sync rx_syncp; 111 struct sk_buff *skb; 112 }; 113 }; 114 115 struct xdp_rxq_info xdp_rxq; 116 } ____cacheline_internodealigned_in_smp; 117 118 /* Board specific private data structure */ 119 struct igc_adapter { 120 struct net_device *netdev; 121 122 struct ethtool_eee eee; 123 u16 eee_advert; 124 125 unsigned long state; 126 unsigned int flags; 127 unsigned int num_q_vectors; 128 129 struct msix_entry *msix_entries; 130 131 /* TX */ 132 u16 tx_work_limit; 133 u32 tx_timeout_count; 134 int num_tx_queues; 135 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 136 137 /* RX */ 138 int num_rx_queues; 139 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 140 141 struct timer_list watchdog_timer; 142 struct timer_list dma_err_timer; 143 struct timer_list phy_info_timer; 144 145 u32 wol; 146 u32 en_mng_pt; 147 u16 link_speed; 148 u16 link_duplex; 149 150 u8 port_num; 151 152 u8 __iomem *io_addr; 153 /* Interrupt Throttle Rate */ 154 u32 rx_itr_setting; 155 u32 tx_itr_setting; 156 157 struct work_struct reset_task; 158 struct work_struct watchdog_task; 159 struct work_struct dma_err_task; 160 bool fc_autoneg; 161 162 u8 tx_timeout_factor; 163 164 int msg_enable; 165 u32 max_frame_size; 166 u32 min_frame_size; 167 168 ktime_t base_time; 169 ktime_t cycle_time; 170 171 /* OS defined structs */ 172 struct pci_dev *pdev; 173 /* lock for statistics */ 174 spinlock_t stats64_lock; 175 struct rtnl_link_stats64 stats64; 176 177 /* structs defined in igc_hw.h */ 178 struct igc_hw hw; 179 struct igc_hw_stats stats; 180 181 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 182 u32 eims_enable_mask; 183 u32 eims_other; 184 185 u16 tx_ring_count; 186 u16 rx_ring_count; 187 188 u32 tx_hwtstamp_timeouts; 189 u32 tx_hwtstamp_skipped; 190 u32 rx_hwtstamp_cleared; 191 192 u32 rss_queues; 193 u32 rss_indir_tbl_init; 194 195 /* Any access to elements in nfc_rule_list is protected by the 196 * nfc_rule_lock. 197 */ 198 struct mutex nfc_rule_lock; 199 struct list_head nfc_rule_list; 200 unsigned int nfc_rule_count; 201 202 u8 rss_indir_tbl[IGC_RETA_SIZE]; 203 204 unsigned long link_check_timeout; 205 struct igc_info ei; 206 207 u32 test_icr; 208 209 struct ptp_clock *ptp_clock; 210 struct ptp_clock_info ptp_caps; 211 struct work_struct ptp_tx_work; 212 struct sk_buff *ptp_tx_skb; 213 struct hwtstamp_config tstamp_config; 214 unsigned long ptp_tx_start; 215 unsigned int ptp_flags; 216 /* System time value lock */ 217 spinlock_t tmreg_lock; 218 struct cyclecounter cc; 219 struct timecounter tc; 220 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 221 ktime_t ptp_reset_start; /* Reset time in clock mono */ 222 223 char fw_version[32]; 224 225 struct bpf_prog *xdp_prog; 226 }; 227 228 void igc_up(struct igc_adapter *adapter); 229 void igc_down(struct igc_adapter *adapter); 230 int igc_open(struct net_device *netdev); 231 int igc_close(struct net_device *netdev); 232 int igc_setup_tx_resources(struct igc_ring *ring); 233 int igc_setup_rx_resources(struct igc_ring *ring); 234 void igc_free_tx_resources(struct igc_ring *ring); 235 void igc_free_rx_resources(struct igc_ring *ring); 236 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 237 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 238 const u32 max_rss_queues); 239 int igc_reinit_queues(struct igc_adapter *adapter); 240 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 241 bool igc_has_link(struct igc_adapter *adapter); 242 void igc_reset(struct igc_adapter *adapter); 243 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 244 void igc_update_stats(struct igc_adapter *adapter); 245 246 /* igc_dump declarations */ 247 void igc_rings_dump(struct igc_adapter *adapter); 248 void igc_regs_dump(struct igc_adapter *adapter); 249 250 extern char igc_driver_name[]; 251 252 #define IGC_REGS_LEN 740 253 254 /* flags controlling PTP/1588 function */ 255 #define IGC_PTP_ENABLED BIT(0) 256 257 /* Flags definitions */ 258 #define IGC_FLAG_HAS_MSI BIT(0) 259 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 260 #define IGC_FLAG_DMAC BIT(4) 261 #define IGC_FLAG_PTP BIT(8) 262 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 263 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 264 #define IGC_FLAG_MEDIA_RESET BIT(10) 265 #define IGC_FLAG_MAS_ENABLE BIT(12) 266 #define IGC_FLAG_HAS_MSIX BIT(13) 267 #define IGC_FLAG_EEE BIT(14) 268 #define IGC_FLAG_VLAN_PROMISC BIT(15) 269 #define IGC_FLAG_RX_LEGACY BIT(16) 270 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 271 272 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 273 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 274 275 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 276 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 277 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 278 279 /* Interrupt defines */ 280 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 281 #define IGC_4K_ITR 980 282 #define IGC_20K_ITR 196 283 #define IGC_70K_ITR 56 284 285 #define IGC_DEFAULT_ITR 3 /* dynamic */ 286 #define IGC_MAX_ITR_USECS 10000 287 #define IGC_MIN_ITR_USECS 10 288 #define NON_Q_VECTORS 1 289 #define MAX_MSIX_ENTRIES 10 290 291 /* TX/RX descriptor defines */ 292 #define IGC_DEFAULT_TXD 256 293 #define IGC_DEFAULT_TX_WORK 128 294 #define IGC_MIN_TXD 80 295 #define IGC_MAX_TXD 4096 296 297 #define IGC_DEFAULT_RXD 256 298 #define IGC_MIN_RXD 80 299 #define IGC_MAX_RXD 4096 300 301 /* Supported Rx Buffer Sizes */ 302 #define IGC_RXBUFFER_256 256 303 #define IGC_RXBUFFER_2048 2048 304 #define IGC_RXBUFFER_3072 3072 305 306 #define AUTO_ALL_MODES 0 307 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 308 309 /* Transmit and receive latency (for PTP timestamps) */ 310 #define IGC_I225_TX_LATENCY_10 240 311 #define IGC_I225_TX_LATENCY_100 58 312 #define IGC_I225_TX_LATENCY_1000 80 313 #define IGC_I225_TX_LATENCY_2500 1325 314 #define IGC_I225_RX_LATENCY_10 6450 315 #define IGC_I225_RX_LATENCY_100 185 316 #define IGC_I225_RX_LATENCY_1000 300 317 #define IGC_I225_RX_LATENCY_2500 1485 318 319 /* RX and TX descriptor control thresholds. 320 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 321 * descriptors available in its onboard memory. 322 * Setting this to 0 disables RX descriptor prefetch. 323 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 324 * available in host memory. 325 * If PTHRESH is 0, this should also be 0. 326 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 327 * descriptors until either it has this many to write back, or the 328 * ITR timer expires. 329 */ 330 #define IGC_RX_PTHRESH 8 331 #define IGC_RX_HTHRESH 8 332 #define IGC_TX_PTHRESH 8 333 #define IGC_TX_HTHRESH 1 334 #define IGC_RX_WTHRESH 4 335 #define IGC_TX_WTHRESH 16 336 337 #define IGC_RX_DMA_ATTR \ 338 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 339 340 #define IGC_TS_HDR_LEN 16 341 342 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 343 344 #if (PAGE_SIZE < 8192) 345 #define IGC_MAX_FRAME_BUILD_SKB \ 346 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 347 #else 348 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 349 #endif 350 351 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 352 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 353 354 /* VLAN info */ 355 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 356 357 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 358 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 359 const u32 stat_err_bits) 360 { 361 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 362 } 363 364 enum igc_state_t { 365 __IGC_TESTING, 366 __IGC_RESETTING, 367 __IGC_DOWN, 368 __IGC_PTP_TX_IN_PROGRESS, 369 }; 370 371 enum igc_tx_flags { 372 /* cmd_type flags */ 373 IGC_TX_FLAGS_VLAN = 0x01, 374 IGC_TX_FLAGS_TSO = 0x02, 375 IGC_TX_FLAGS_TSTAMP = 0x04, 376 377 /* olinfo flags */ 378 IGC_TX_FLAGS_IPV4 = 0x10, 379 IGC_TX_FLAGS_CSUM = 0x20, 380 381 IGC_TX_FLAGS_XDP = 0x100, 382 }; 383 384 enum igc_boards { 385 board_base, 386 }; 387 388 /* The largest size we can write to the descriptor is 65535. In order to 389 * maintain a power of two alignment we have to limit ourselves to 32K. 390 */ 391 #define IGC_MAX_TXD_PWR 15 392 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 393 394 /* Tx Descriptors needed, worst case */ 395 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 396 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 397 398 /* wrapper around a pointer to a socket buffer, 399 * so a DMA handle can be stored along with the buffer 400 */ 401 struct igc_tx_buffer { 402 union igc_adv_tx_desc *next_to_watch; 403 unsigned long time_stamp; 404 union { 405 struct sk_buff *skb; 406 struct xdp_frame *xdpf; 407 }; 408 unsigned int bytecount; 409 u16 gso_segs; 410 __be16 protocol; 411 412 DEFINE_DMA_UNMAP_ADDR(dma); 413 DEFINE_DMA_UNMAP_LEN(len); 414 u32 tx_flags; 415 }; 416 417 struct igc_rx_buffer { 418 dma_addr_t dma; 419 struct page *page; 420 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 421 __u32 page_offset; 422 #else 423 __u16 page_offset; 424 #endif 425 __u16 pagecnt_bias; 426 }; 427 428 struct igc_q_vector { 429 struct igc_adapter *adapter; /* backlink */ 430 void __iomem *itr_register; 431 u32 eims_value; /* EIMS mask value */ 432 433 u16 itr_val; 434 u8 set_itr; 435 436 struct igc_ring_container rx, tx; 437 438 struct napi_struct napi; 439 440 struct rcu_head rcu; /* to avoid race with update stats on free */ 441 char name[IFNAMSIZ + 9]; 442 struct net_device poll_dev; 443 444 /* for dynamic allocation of rings associated with this q_vector */ 445 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 446 }; 447 448 enum igc_filter_match_flags { 449 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 450 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 451 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 452 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 453 }; 454 455 struct igc_nfc_filter { 456 u8 match_flags; 457 u16 etype; 458 u16 vlan_tci; 459 u8 src_addr[ETH_ALEN]; 460 u8 dst_addr[ETH_ALEN]; 461 }; 462 463 struct igc_nfc_rule { 464 struct list_head list; 465 struct igc_nfc_filter filter; 466 u32 location; 467 u16 action; 468 }; 469 470 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority 471 * based, and 8 ethertype based. 472 */ 473 #define IGC_MAX_RXNFC_RULES 32 474 475 /* igc_desc_unused - calculate if we have unused descriptors */ 476 static inline u16 igc_desc_unused(const struct igc_ring *ring) 477 { 478 u16 ntc = ring->next_to_clean; 479 u16 ntu = ring->next_to_use; 480 481 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 482 } 483 484 static inline s32 igc_get_phy_info(struct igc_hw *hw) 485 { 486 if (hw->phy.ops.get_phy_info) 487 return hw->phy.ops.get_phy_info(hw); 488 489 return 0; 490 } 491 492 static inline s32 igc_reset_phy(struct igc_hw *hw) 493 { 494 if (hw->phy.ops.reset) 495 return hw->phy.ops.reset(hw); 496 497 return 0; 498 } 499 500 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 501 { 502 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 503 } 504 505 enum igc_ring_flags_t { 506 IGC_RING_FLAG_RX_3K_BUFFER, 507 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 508 IGC_RING_FLAG_RX_SCTP_CSUM, 509 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 510 IGC_RING_FLAG_TX_CTX_IDX, 511 IGC_RING_FLAG_TX_DETECT_HANG 512 }; 513 514 #define ring_uses_large_buffer(ring) \ 515 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 516 #define set_ring_uses_large_buffer(ring) \ 517 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 518 #define clear_ring_uses_large_buffer(ring) \ 519 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 520 521 #define ring_uses_build_skb(ring) \ 522 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 523 524 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 525 { 526 #if (PAGE_SIZE < 8192) 527 if (ring_uses_large_buffer(ring)) 528 return IGC_RXBUFFER_3072; 529 530 if (ring_uses_build_skb(ring)) 531 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 532 #endif 533 return IGC_RXBUFFER_2048; 534 } 535 536 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 537 { 538 #if (PAGE_SIZE < 8192) 539 if (ring_uses_large_buffer(ring)) 540 return 1; 541 #endif 542 return 0; 543 } 544 545 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 546 { 547 if (hw->phy.ops.read_reg) 548 return hw->phy.ops.read_reg(hw, offset, data); 549 550 return 0; 551 } 552 553 void igc_reinit_locked(struct igc_adapter *); 554 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 555 u32 location); 556 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 557 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 558 559 void igc_ptp_init(struct igc_adapter *adapter); 560 void igc_ptp_reset(struct igc_adapter *adapter); 561 void igc_ptp_suspend(struct igc_adapter *adapter); 562 void igc_ptp_stop(struct igc_adapter *adapter); 563 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 564 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 565 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 566 void igc_ptp_tx_hang(struct igc_adapter *adapter); 567 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 568 569 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 570 571 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 572 573 #define IGC_RX_DESC(R, i) \ 574 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 575 #define IGC_TX_DESC(R, i) \ 576 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 577 #define IGC_TX_CTXTDESC(R, i) \ 578 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 579 580 #endif /* _IGC_H_ */ 581