1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 #include <net/xdp.h> 19 20 #include "igc_hw.h" 21 22 void igc_ethtool_set_ops(struct net_device *); 23 24 /* Transmit and receive queues */ 25 #define IGC_MAX_RX_QUEUES 4 26 #define IGC_MAX_TX_QUEUES 4 27 28 #define MAX_Q_VECTORS 8 29 #define MAX_STD_JUMBO_FRAME_SIZE 9216 30 31 #define MAX_ETYPE_FILTER 8 32 #define IGC_RETA_SIZE 128 33 34 /* SDP support */ 35 #define IGC_N_EXTTS 2 36 #define IGC_N_PEROUT 2 37 #define IGC_N_SDP 4 38 39 #define MAX_FLEX_FILTER 32 40 41 enum igc_mac_filter_type { 42 IGC_MAC_FILTER_TYPE_DST = 0, 43 IGC_MAC_FILTER_TYPE_SRC 44 }; 45 46 struct igc_tx_queue_stats { 47 u64 packets; 48 u64 bytes; 49 u64 restart_queue; 50 u64 restart_queue2; 51 }; 52 53 struct igc_rx_queue_stats { 54 u64 packets; 55 u64 bytes; 56 u64 drops; 57 u64 csum_err; 58 u64 alloc_failed; 59 }; 60 61 struct igc_rx_packet_stats { 62 u64 ipv4_packets; /* IPv4 headers processed */ 63 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 64 u64 ipv6_packets; /* IPv6 headers processed */ 65 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 66 u64 tcp_packets; /* TCP headers processed */ 67 u64 udp_packets; /* UDP headers processed */ 68 u64 sctp_packets; /* SCTP headers processed */ 69 u64 nfs_packets; /* NFS headers processe */ 70 u64 other_packets; 71 }; 72 73 struct igc_ring_container { 74 struct igc_ring *ring; /* pointer to linked list of rings */ 75 unsigned int total_bytes; /* total bytes processed this int */ 76 unsigned int total_packets; /* total packets processed this int */ 77 u16 work_limit; /* total work allowed per interrupt */ 78 u8 count; /* total number of rings in vector */ 79 u8 itr; /* current ITR setting for ring */ 80 }; 81 82 struct igc_ring { 83 struct igc_q_vector *q_vector; /* backlink to q_vector */ 84 struct net_device *netdev; /* back pointer to net_device */ 85 struct device *dev; /* device for dma mapping */ 86 union { /* array of buffer info structs */ 87 struct igc_tx_buffer *tx_buffer_info; 88 struct igc_rx_buffer *rx_buffer_info; 89 }; 90 void *desc; /* descriptor ring memory */ 91 unsigned long flags; /* ring specific flags */ 92 void __iomem *tail; /* pointer to ring tail register */ 93 dma_addr_t dma; /* phys address of the ring */ 94 unsigned int size; /* length of desc. ring in bytes */ 95 96 u16 count; /* number of desc. in the ring */ 97 u8 queue_index; /* logical index of the ring*/ 98 u8 reg_idx; /* physical index of the ring */ 99 bool launchtime_enable; /* true if LaunchTime is enabled */ 100 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 101 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 102 103 u32 start_time; 104 u32 end_time; 105 u32 max_sdu; 106 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 107 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 108 109 /* CBS parameters */ 110 bool cbs_enable; /* indicates if CBS is enabled */ 111 s32 idleslope; /* idleSlope in kbps */ 112 s32 sendslope; /* sendSlope in kbps */ 113 s32 hicredit; /* hiCredit in bytes */ 114 s32 locredit; /* loCredit in bytes */ 115 116 /* everything past this point are written often */ 117 u16 next_to_clean; 118 u16 next_to_use; 119 u16 next_to_alloc; 120 121 union { 122 /* TX */ 123 struct { 124 struct igc_tx_queue_stats tx_stats; 125 struct u64_stats_sync tx_syncp; 126 struct u64_stats_sync tx_syncp2; 127 }; 128 /* RX */ 129 struct { 130 struct igc_rx_queue_stats rx_stats; 131 struct igc_rx_packet_stats pkt_stats; 132 struct u64_stats_sync rx_syncp; 133 struct sk_buff *skb; 134 }; 135 }; 136 137 struct xdp_rxq_info xdp_rxq; 138 struct xsk_buff_pool *xsk_pool; 139 } ____cacheline_internodealigned_in_smp; 140 141 /* Board specific private data structure */ 142 struct igc_adapter { 143 struct net_device *netdev; 144 145 struct ethtool_eee eee; 146 u16 eee_advert; 147 148 unsigned long state; 149 unsigned int flags; 150 unsigned int num_q_vectors; 151 152 struct msix_entry *msix_entries; 153 154 /* TX */ 155 u16 tx_work_limit; 156 u32 tx_timeout_count; 157 int num_tx_queues; 158 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 159 160 /* RX */ 161 int num_rx_queues; 162 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 163 164 struct timer_list watchdog_timer; 165 struct timer_list dma_err_timer; 166 struct timer_list phy_info_timer; 167 struct hrtimer hrtimer; 168 169 u32 wol; 170 u32 en_mng_pt; 171 u16 link_speed; 172 u16 link_duplex; 173 174 u8 port_num; 175 176 u8 __iomem *io_addr; 177 /* Interrupt Throttle Rate */ 178 u32 rx_itr_setting; 179 u32 tx_itr_setting; 180 181 struct work_struct reset_task; 182 struct work_struct watchdog_task; 183 struct work_struct dma_err_task; 184 bool fc_autoneg; 185 186 u8 tx_timeout_factor; 187 188 int msg_enable; 189 u32 max_frame_size; 190 u32 min_frame_size; 191 192 int tc_setup_type; 193 ktime_t base_time; 194 ktime_t cycle_time; 195 bool taprio_offload_enable; 196 u32 qbv_config_change_errors; 197 bool qbv_transition; 198 unsigned int qbv_count; 199 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 200 * are protected by the qbv_tx_lock. 201 */ 202 spinlock_t qbv_tx_lock; 203 204 /* OS defined structs */ 205 struct pci_dev *pdev; 206 /* lock for statistics */ 207 spinlock_t stats64_lock; 208 struct rtnl_link_stats64 stats64; 209 210 /* structs defined in igc_hw.h */ 211 struct igc_hw hw; 212 struct igc_hw_stats stats; 213 214 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 215 u32 eims_enable_mask; 216 u32 eims_other; 217 218 u16 tx_ring_count; 219 u16 rx_ring_count; 220 221 u32 tx_hwtstamp_timeouts; 222 u32 tx_hwtstamp_skipped; 223 u32 rx_hwtstamp_cleared; 224 225 u32 rss_queues; 226 u32 rss_indir_tbl_init; 227 228 /* Any access to elements in nfc_rule_list is protected by the 229 * nfc_rule_lock. 230 */ 231 struct mutex nfc_rule_lock; 232 struct list_head nfc_rule_list; 233 unsigned int nfc_rule_count; 234 235 u8 rss_indir_tbl[IGC_RETA_SIZE]; 236 237 unsigned long link_check_timeout; 238 struct igc_info ei; 239 240 u32 test_icr; 241 242 struct ptp_clock *ptp_clock; 243 struct ptp_clock_info ptp_caps; 244 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 245 * ptp_tx_lock. 246 */ 247 spinlock_t ptp_tx_lock; 248 struct sk_buff *ptp_tx_skb; 249 struct hwtstamp_config tstamp_config; 250 unsigned long ptp_tx_start; 251 unsigned int ptp_flags; 252 /* System time value lock */ 253 spinlock_t tmreg_lock; 254 struct cyclecounter cc; 255 struct timecounter tc; 256 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 257 ktime_t ptp_reset_start; /* Reset time in clock mono */ 258 struct system_time_snapshot snapshot; 259 260 char fw_version[32]; 261 262 struct bpf_prog *xdp_prog; 263 264 bool pps_sys_wrap_on; 265 266 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 267 struct { 268 struct timespec64 start; 269 struct timespec64 period; 270 } perout[IGC_N_PEROUT]; 271 }; 272 273 void igc_up(struct igc_adapter *adapter); 274 void igc_down(struct igc_adapter *adapter); 275 int igc_open(struct net_device *netdev); 276 int igc_close(struct net_device *netdev); 277 int igc_setup_tx_resources(struct igc_ring *ring); 278 int igc_setup_rx_resources(struct igc_ring *ring); 279 void igc_free_tx_resources(struct igc_ring *ring); 280 void igc_free_rx_resources(struct igc_ring *ring); 281 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 282 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 283 const u32 max_rss_queues); 284 int igc_reinit_queues(struct igc_adapter *adapter); 285 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 286 bool igc_has_link(struct igc_adapter *adapter); 287 void igc_reset(struct igc_adapter *adapter); 288 void igc_update_stats(struct igc_adapter *adapter); 289 void igc_disable_rx_ring(struct igc_ring *ring); 290 void igc_enable_rx_ring(struct igc_ring *ring); 291 void igc_disable_tx_ring(struct igc_ring *ring); 292 void igc_enable_tx_ring(struct igc_ring *ring); 293 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 294 295 /* igc_dump declarations */ 296 void igc_rings_dump(struct igc_adapter *adapter); 297 void igc_regs_dump(struct igc_adapter *adapter); 298 299 extern char igc_driver_name[]; 300 301 #define IGC_REGS_LEN 740 302 303 /* flags controlling PTP/1588 function */ 304 #define IGC_PTP_ENABLED BIT(0) 305 306 /* Flags definitions */ 307 #define IGC_FLAG_HAS_MSI BIT(0) 308 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 309 #define IGC_FLAG_DMAC BIT(4) 310 #define IGC_FLAG_PTP BIT(8) 311 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 312 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 313 #define IGC_FLAG_HAS_MSIX BIT(13) 314 #define IGC_FLAG_EEE BIT(14) 315 #define IGC_FLAG_VLAN_PROMISC BIT(15) 316 #define IGC_FLAG_RX_LEGACY BIT(16) 317 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 318 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 319 320 #define IGC_FLAG_TSN_ANY_ENABLED \ 321 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED) 322 323 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 324 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 325 326 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 327 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 328 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 329 330 /* RX-desc Write-Back format RSS Type's */ 331 enum igc_rss_type_num { 332 IGC_RSS_TYPE_NO_HASH = 0, 333 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 334 IGC_RSS_TYPE_HASH_IPV4 = 2, 335 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 336 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 337 IGC_RSS_TYPE_HASH_IPV6 = 5, 338 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 339 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 340 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 341 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 342 IGC_RSS_TYPE_MAX = 10, 343 }; 344 #define IGC_RSS_TYPE_MAX_TABLE 16 345 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 346 347 /* igc_rss_type - Rx descriptor RSS type field */ 348 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 349 { 350 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 351 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 352 * is slightly slower than via u32 (wb.lower.lo_dword.data) 353 */ 354 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 355 } 356 357 /* Interrupt defines */ 358 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 359 #define IGC_4K_ITR 980 360 #define IGC_20K_ITR 196 361 #define IGC_70K_ITR 56 362 363 #define IGC_DEFAULT_ITR 3 /* dynamic */ 364 #define IGC_MAX_ITR_USECS 10000 365 #define IGC_MIN_ITR_USECS 10 366 #define NON_Q_VECTORS 1 367 #define MAX_MSIX_ENTRIES 10 368 369 /* TX/RX descriptor defines */ 370 #define IGC_DEFAULT_TXD 256 371 #define IGC_DEFAULT_TX_WORK 128 372 #define IGC_MIN_TXD 80 373 #define IGC_MAX_TXD 4096 374 375 #define IGC_DEFAULT_RXD 256 376 #define IGC_MIN_RXD 80 377 #define IGC_MAX_RXD 4096 378 379 /* Supported Rx Buffer Sizes */ 380 #define IGC_RXBUFFER_256 256 381 #define IGC_RXBUFFER_2048 2048 382 #define IGC_RXBUFFER_3072 3072 383 384 #define AUTO_ALL_MODES 0 385 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 386 387 /* Transmit and receive latency (for PTP timestamps) */ 388 #define IGC_I225_TX_LATENCY_10 240 389 #define IGC_I225_TX_LATENCY_100 58 390 #define IGC_I225_TX_LATENCY_1000 80 391 #define IGC_I225_TX_LATENCY_2500 1325 392 #define IGC_I225_RX_LATENCY_10 6450 393 #define IGC_I225_RX_LATENCY_100 185 394 #define IGC_I225_RX_LATENCY_1000 300 395 #define IGC_I225_RX_LATENCY_2500 1485 396 397 /* RX and TX descriptor control thresholds. 398 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 399 * descriptors available in its onboard memory. 400 * Setting this to 0 disables RX descriptor prefetch. 401 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 402 * available in host memory. 403 * If PTHRESH is 0, this should also be 0. 404 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 405 * descriptors until either it has this many to write back, or the 406 * ITR timer expires. 407 */ 408 #define IGC_RX_PTHRESH 8 409 #define IGC_RX_HTHRESH 8 410 #define IGC_TX_PTHRESH 8 411 #define IGC_TX_HTHRESH 1 412 #define IGC_RX_WTHRESH 4 413 #define IGC_TX_WTHRESH 16 414 415 #define IGC_RX_DMA_ATTR \ 416 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 417 418 #define IGC_TS_HDR_LEN 16 419 420 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 421 422 #if (PAGE_SIZE < 8192) 423 #define IGC_MAX_FRAME_BUILD_SKB \ 424 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 425 #else 426 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 427 #endif 428 429 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 430 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 431 432 /* VLAN info */ 433 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 434 #define IGC_TX_FLAGS_VLAN_SHIFT 16 435 436 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 437 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 438 const u32 stat_err_bits) 439 { 440 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 441 } 442 443 enum igc_state_t { 444 __IGC_TESTING, 445 __IGC_RESETTING, 446 __IGC_DOWN, 447 }; 448 449 enum igc_tx_flags { 450 /* cmd_type flags */ 451 IGC_TX_FLAGS_VLAN = 0x01, 452 IGC_TX_FLAGS_TSO = 0x02, 453 IGC_TX_FLAGS_TSTAMP = 0x04, 454 455 /* olinfo flags */ 456 IGC_TX_FLAGS_IPV4 = 0x10, 457 IGC_TX_FLAGS_CSUM = 0x20, 458 }; 459 460 enum igc_boards { 461 board_base, 462 }; 463 464 /* The largest size we can write to the descriptor is 65535. In order to 465 * maintain a power of two alignment we have to limit ourselves to 32K. 466 */ 467 #define IGC_MAX_TXD_PWR 15 468 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 469 470 /* Tx Descriptors needed, worst case */ 471 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 472 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 473 474 enum igc_tx_buffer_type { 475 IGC_TX_BUFFER_TYPE_SKB, 476 IGC_TX_BUFFER_TYPE_XDP, 477 IGC_TX_BUFFER_TYPE_XSK, 478 }; 479 480 /* wrapper around a pointer to a socket buffer, 481 * so a DMA handle can be stored along with the buffer 482 */ 483 struct igc_tx_buffer { 484 union igc_adv_tx_desc *next_to_watch; 485 unsigned long time_stamp; 486 enum igc_tx_buffer_type type; 487 union { 488 struct sk_buff *skb; 489 struct xdp_frame *xdpf; 490 }; 491 unsigned int bytecount; 492 u16 gso_segs; 493 __be16 protocol; 494 495 DEFINE_DMA_UNMAP_ADDR(dma); 496 DEFINE_DMA_UNMAP_LEN(len); 497 u32 tx_flags; 498 }; 499 500 struct igc_rx_buffer { 501 union { 502 struct { 503 dma_addr_t dma; 504 struct page *page; 505 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 506 __u32 page_offset; 507 #else 508 __u16 page_offset; 509 #endif 510 __u16 pagecnt_bias; 511 }; 512 struct xdp_buff *xdp; 513 }; 514 }; 515 516 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 517 struct igc_xdp_buff { 518 struct xdp_buff xdp; 519 union igc_adv_rx_desc *rx_desc; 520 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 521 }; 522 523 struct igc_q_vector { 524 struct igc_adapter *adapter; /* backlink */ 525 void __iomem *itr_register; 526 u32 eims_value; /* EIMS mask value */ 527 528 u16 itr_val; 529 u8 set_itr; 530 531 struct igc_ring_container rx, tx; 532 533 struct napi_struct napi; 534 535 struct rcu_head rcu; /* to avoid race with update stats on free */ 536 char name[IFNAMSIZ + 9]; 537 struct net_device poll_dev; 538 539 /* for dynamic allocation of rings associated with this q_vector */ 540 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 541 }; 542 543 enum igc_filter_match_flags { 544 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 545 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 546 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 547 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 548 IGC_FILTER_FLAG_USER_DATA = BIT(4), 549 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 550 }; 551 552 struct igc_nfc_filter { 553 u8 match_flags; 554 u16 etype; 555 __be16 vlan_etype; 556 u16 vlan_tci; 557 u8 src_addr[ETH_ALEN]; 558 u8 dst_addr[ETH_ALEN]; 559 u8 user_data[8]; 560 u8 user_mask[8]; 561 u8 flex_index; 562 u8 rx_queue; 563 u8 prio; 564 u8 immediate_irq; 565 u8 drop; 566 }; 567 568 struct igc_nfc_rule { 569 struct list_head list; 570 struct igc_nfc_filter filter; 571 u32 location; 572 u16 action; 573 bool flex; 574 }; 575 576 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 577 * based, 8 ethertype based and 32 Flex filter based rules. 578 */ 579 #define IGC_MAX_RXNFC_RULES 64 580 581 struct igc_flex_filter { 582 u8 index; 583 u8 data[128]; 584 u8 mask[16]; 585 u8 length; 586 u8 rx_queue; 587 u8 prio; 588 u8 immediate_irq; 589 u8 drop; 590 }; 591 592 /* igc_desc_unused - calculate if we have unused descriptors */ 593 static inline u16 igc_desc_unused(const struct igc_ring *ring) 594 { 595 u16 ntc = ring->next_to_clean; 596 u16 ntu = ring->next_to_use; 597 598 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 599 } 600 601 static inline s32 igc_get_phy_info(struct igc_hw *hw) 602 { 603 if (hw->phy.ops.get_phy_info) 604 return hw->phy.ops.get_phy_info(hw); 605 606 return 0; 607 } 608 609 static inline s32 igc_reset_phy(struct igc_hw *hw) 610 { 611 if (hw->phy.ops.reset) 612 return hw->phy.ops.reset(hw); 613 614 return 0; 615 } 616 617 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 618 { 619 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 620 } 621 622 enum igc_ring_flags_t { 623 IGC_RING_FLAG_RX_3K_BUFFER, 624 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 625 IGC_RING_FLAG_RX_SCTP_CSUM, 626 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 627 IGC_RING_FLAG_TX_CTX_IDX, 628 IGC_RING_FLAG_TX_DETECT_HANG, 629 IGC_RING_FLAG_AF_XDP_ZC, 630 IGC_RING_FLAG_TX_HWTSTAMP, 631 }; 632 633 #define ring_uses_large_buffer(ring) \ 634 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 635 #define set_ring_uses_large_buffer(ring) \ 636 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 637 #define clear_ring_uses_large_buffer(ring) \ 638 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 639 640 #define ring_uses_build_skb(ring) \ 641 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 642 643 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 644 { 645 #if (PAGE_SIZE < 8192) 646 if (ring_uses_large_buffer(ring)) 647 return IGC_RXBUFFER_3072; 648 649 if (ring_uses_build_skb(ring)) 650 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 651 #endif 652 return IGC_RXBUFFER_2048; 653 } 654 655 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 656 { 657 #if (PAGE_SIZE < 8192) 658 if (ring_uses_large_buffer(ring)) 659 return 1; 660 #endif 661 return 0; 662 } 663 664 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 665 { 666 if (hw->phy.ops.read_reg) 667 return hw->phy.ops.read_reg(hw, offset, data); 668 669 return -EOPNOTSUPP; 670 } 671 672 void igc_reinit_locked(struct igc_adapter *); 673 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 674 u32 location); 675 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 676 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 677 678 void igc_ptp_init(struct igc_adapter *adapter); 679 void igc_ptp_reset(struct igc_adapter *adapter); 680 void igc_ptp_suspend(struct igc_adapter *adapter); 681 void igc_ptp_stop(struct igc_adapter *adapter); 682 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 683 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 684 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 685 void igc_ptp_tx_hang(struct igc_adapter *adapter); 686 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 687 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 688 689 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 690 691 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 692 693 #define IGC_RX_DESC(R, i) \ 694 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 695 #define IGC_TX_DESC(R, i) \ 696 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 697 #define IGC_TX_CTXTDESC(R, i) \ 698 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 699 700 #endif /* _IGC_H_ */ 701