1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 void igc_ethtool_set_ops(struct net_device *); 20 21 /* Transmit and receive queues */ 22 #define IGC_MAX_RX_QUEUES 4 23 #define IGC_MAX_TX_QUEUES 4 24 25 #define MAX_Q_VECTORS 8 26 #define MAX_STD_JUMBO_FRAME_SIZE 9216 27 28 #define MAX_ETYPE_FILTER 8 29 #define IGC_RETA_SIZE 128 30 31 enum igc_mac_filter_type { 32 IGC_MAC_FILTER_TYPE_DST = 0, 33 IGC_MAC_FILTER_TYPE_SRC 34 }; 35 36 struct igc_tx_queue_stats { 37 u64 packets; 38 u64 bytes; 39 u64 restart_queue; 40 u64 restart_queue2; 41 }; 42 43 struct igc_rx_queue_stats { 44 u64 packets; 45 u64 bytes; 46 u64 drops; 47 u64 csum_err; 48 u64 alloc_failed; 49 }; 50 51 struct igc_rx_packet_stats { 52 u64 ipv4_packets; /* IPv4 headers processed */ 53 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 54 u64 ipv6_packets; /* IPv6 headers processed */ 55 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 56 u64 tcp_packets; /* TCP headers processed */ 57 u64 udp_packets; /* UDP headers processed */ 58 u64 sctp_packets; /* SCTP headers processed */ 59 u64 nfs_packets; /* NFS headers processe */ 60 u64 other_packets; 61 }; 62 63 struct igc_ring_container { 64 struct igc_ring *ring; /* pointer to linked list of rings */ 65 unsigned int total_bytes; /* total bytes processed this int */ 66 unsigned int total_packets; /* total packets processed this int */ 67 u16 work_limit; /* total work allowed per interrupt */ 68 u8 count; /* total number of rings in vector */ 69 u8 itr; /* current ITR setting for ring */ 70 }; 71 72 struct igc_ring { 73 struct igc_q_vector *q_vector; /* backlink to q_vector */ 74 struct net_device *netdev; /* back pointer to net_device */ 75 struct device *dev; /* device for dma mapping */ 76 union { /* array of buffer info structs */ 77 struct igc_tx_buffer *tx_buffer_info; 78 struct igc_rx_buffer *rx_buffer_info; 79 }; 80 void *desc; /* descriptor ring memory */ 81 unsigned long flags; /* ring specific flags */ 82 void __iomem *tail; /* pointer to ring tail register */ 83 dma_addr_t dma; /* phys address of the ring */ 84 unsigned int size; /* length of desc. ring in bytes */ 85 86 u16 count; /* number of desc. in the ring */ 87 u8 queue_index; /* logical index of the ring*/ 88 u8 reg_idx; /* physical index of the ring */ 89 bool launchtime_enable; /* true if LaunchTime is enabled */ 90 91 u32 start_time; 92 u32 end_time; 93 94 /* everything past this point are written often */ 95 u16 next_to_clean; 96 u16 next_to_use; 97 u16 next_to_alloc; 98 99 union { 100 /* TX */ 101 struct { 102 struct igc_tx_queue_stats tx_stats; 103 struct u64_stats_sync tx_syncp; 104 struct u64_stats_sync tx_syncp2; 105 }; 106 /* RX */ 107 struct { 108 struct igc_rx_queue_stats rx_stats; 109 struct igc_rx_packet_stats pkt_stats; 110 struct u64_stats_sync rx_syncp; 111 struct sk_buff *skb; 112 }; 113 }; 114 } ____cacheline_internodealigned_in_smp; 115 116 /* Board specific private data structure */ 117 struct igc_adapter { 118 struct net_device *netdev; 119 120 unsigned long state; 121 unsigned int flags; 122 unsigned int num_q_vectors; 123 124 struct msix_entry *msix_entries; 125 126 /* TX */ 127 u16 tx_work_limit; 128 u32 tx_timeout_count; 129 int num_tx_queues; 130 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 131 132 /* RX */ 133 int num_rx_queues; 134 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 135 136 struct timer_list watchdog_timer; 137 struct timer_list dma_err_timer; 138 struct timer_list phy_info_timer; 139 140 u32 wol; 141 u32 en_mng_pt; 142 u16 link_speed; 143 u16 link_duplex; 144 145 u8 port_num; 146 147 u8 __iomem *io_addr; 148 /* Interrupt Throttle Rate */ 149 u32 rx_itr_setting; 150 u32 tx_itr_setting; 151 152 struct work_struct reset_task; 153 struct work_struct watchdog_task; 154 struct work_struct dma_err_task; 155 bool fc_autoneg; 156 157 u8 tx_timeout_factor; 158 159 int msg_enable; 160 u32 max_frame_size; 161 u32 min_frame_size; 162 163 ktime_t base_time; 164 ktime_t cycle_time; 165 166 /* OS defined structs */ 167 struct pci_dev *pdev; 168 /* lock for statistics */ 169 spinlock_t stats64_lock; 170 struct rtnl_link_stats64 stats64; 171 172 /* structs defined in igc_hw.h */ 173 struct igc_hw hw; 174 struct igc_hw_stats stats; 175 176 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 177 u32 eims_enable_mask; 178 u32 eims_other; 179 180 u16 tx_ring_count; 181 u16 rx_ring_count; 182 183 u32 tx_hwtstamp_timeouts; 184 u32 tx_hwtstamp_skipped; 185 u32 rx_hwtstamp_cleared; 186 187 u32 rss_queues; 188 u32 rss_indir_tbl_init; 189 190 /* Any access to elements in nfc_rule_list is protected by the 191 * nfc_rule_lock. 192 */ 193 struct mutex nfc_rule_lock; 194 struct list_head nfc_rule_list; 195 unsigned int nfc_rule_count; 196 197 u8 rss_indir_tbl[IGC_RETA_SIZE]; 198 199 unsigned long link_check_timeout; 200 struct igc_info ei; 201 202 u32 test_icr; 203 204 struct ptp_clock *ptp_clock; 205 struct ptp_clock_info ptp_caps; 206 struct work_struct ptp_tx_work; 207 struct sk_buff *ptp_tx_skb; 208 struct hwtstamp_config tstamp_config; 209 unsigned long ptp_tx_start; 210 unsigned long last_rx_ptp_check; 211 unsigned long last_rx_timestamp; 212 unsigned int ptp_flags; 213 /* System time value lock */ 214 spinlock_t tmreg_lock; 215 struct cyclecounter cc; 216 struct timecounter tc; 217 }; 218 219 void igc_up(struct igc_adapter *adapter); 220 void igc_down(struct igc_adapter *adapter); 221 int igc_open(struct net_device *netdev); 222 int igc_close(struct net_device *netdev); 223 int igc_setup_tx_resources(struct igc_ring *ring); 224 int igc_setup_rx_resources(struct igc_ring *ring); 225 void igc_free_tx_resources(struct igc_ring *ring); 226 void igc_free_rx_resources(struct igc_ring *ring); 227 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 228 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 229 const u32 max_rss_queues); 230 int igc_reinit_queues(struct igc_adapter *adapter); 231 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 232 bool igc_has_link(struct igc_adapter *adapter); 233 void igc_reset(struct igc_adapter *adapter); 234 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 235 void igc_update_stats(struct igc_adapter *adapter); 236 237 /* igc_dump declarations */ 238 void igc_rings_dump(struct igc_adapter *adapter); 239 void igc_regs_dump(struct igc_adapter *adapter); 240 241 extern char igc_driver_name[]; 242 extern char igc_driver_version[]; 243 244 #define IGC_REGS_LEN 740 245 246 /* flags controlling PTP/1588 function */ 247 #define IGC_PTP_ENABLED BIT(0) 248 249 /* Flags definitions */ 250 #define IGC_FLAG_HAS_MSI BIT(0) 251 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 252 #define IGC_FLAG_DMAC BIT(4) 253 #define IGC_FLAG_PTP BIT(8) 254 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 255 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 256 #define IGC_FLAG_MEDIA_RESET BIT(10) 257 #define IGC_FLAG_MAS_ENABLE BIT(12) 258 #define IGC_FLAG_HAS_MSIX BIT(13) 259 #define IGC_FLAG_VLAN_PROMISC BIT(15) 260 #define IGC_FLAG_RX_LEGACY BIT(16) 261 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 262 263 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 264 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 265 266 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 267 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 268 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 269 270 /* Interrupt defines */ 271 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 272 #define IGC_4K_ITR 980 273 #define IGC_20K_ITR 196 274 #define IGC_70K_ITR 56 275 276 #define IGC_DEFAULT_ITR 3 /* dynamic */ 277 #define IGC_MAX_ITR_USECS 10000 278 #define IGC_MIN_ITR_USECS 10 279 #define NON_Q_VECTORS 1 280 #define MAX_MSIX_ENTRIES 10 281 282 /* TX/RX descriptor defines */ 283 #define IGC_DEFAULT_TXD 256 284 #define IGC_DEFAULT_TX_WORK 128 285 #define IGC_MIN_TXD 80 286 #define IGC_MAX_TXD 4096 287 288 #define IGC_DEFAULT_RXD 256 289 #define IGC_MIN_RXD 80 290 #define IGC_MAX_RXD 4096 291 292 /* Supported Rx Buffer Sizes */ 293 #define IGC_RXBUFFER_256 256 294 #define IGC_RXBUFFER_2048 2048 295 #define IGC_RXBUFFER_3072 3072 296 297 #define AUTO_ALL_MODES 0 298 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 299 300 /* Transmit and receive latency (for PTP timestamps) */ 301 /* FIXME: These values were estimated using the ones that i225 has as 302 * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 303 * need to confirm them. 304 */ 305 #define IGC_I225_TX_LATENCY_10 9542 306 #define IGC_I225_TX_LATENCY_100 1024 307 #define IGC_I225_TX_LATENCY_1000 178 308 #define IGC_I225_TX_LATENCY_2500 64 309 #define IGC_I225_RX_LATENCY_10 20662 310 #define IGC_I225_RX_LATENCY_100 2213 311 #define IGC_I225_RX_LATENCY_1000 448 312 #define IGC_I225_RX_LATENCY_2500 160 313 314 /* RX and TX descriptor control thresholds. 315 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 316 * descriptors available in its onboard memory. 317 * Setting this to 0 disables RX descriptor prefetch. 318 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 319 * available in host memory. 320 * If PTHRESH is 0, this should also be 0. 321 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 322 * descriptors until either it has this many to write back, or the 323 * ITR timer expires. 324 */ 325 #define IGC_RX_PTHRESH 8 326 #define IGC_RX_HTHRESH 8 327 #define IGC_TX_PTHRESH 8 328 #define IGC_TX_HTHRESH 1 329 #define IGC_RX_WTHRESH 4 330 #define IGC_TX_WTHRESH 16 331 332 #define IGC_RX_DMA_ATTR \ 333 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 334 335 #define IGC_TS_HDR_LEN 16 336 337 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 338 339 #if (PAGE_SIZE < 8192) 340 #define IGC_MAX_FRAME_BUILD_SKB \ 341 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 342 #else 343 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 344 #endif 345 346 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 347 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 348 349 /* VLAN info */ 350 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 351 352 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 353 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 354 const u32 stat_err_bits) 355 { 356 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 357 } 358 359 enum igc_state_t { 360 __IGC_TESTING, 361 __IGC_RESETTING, 362 __IGC_DOWN, 363 __IGC_PTP_TX_IN_PROGRESS, 364 }; 365 366 enum igc_tx_flags { 367 /* cmd_type flags */ 368 IGC_TX_FLAGS_VLAN = 0x01, 369 IGC_TX_FLAGS_TSO = 0x02, 370 IGC_TX_FLAGS_TSTAMP = 0x04, 371 372 /* olinfo flags */ 373 IGC_TX_FLAGS_IPV4 = 0x10, 374 IGC_TX_FLAGS_CSUM = 0x20, 375 }; 376 377 enum igc_boards { 378 board_base, 379 }; 380 381 /* The largest size we can write to the descriptor is 65535. In order to 382 * maintain a power of two alignment we have to limit ourselves to 32K. 383 */ 384 #define IGC_MAX_TXD_PWR 15 385 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 386 387 /* Tx Descriptors needed, worst case */ 388 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 389 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 390 391 /* wrapper around a pointer to a socket buffer, 392 * so a DMA handle can be stored along with the buffer 393 */ 394 struct igc_tx_buffer { 395 union igc_adv_tx_desc *next_to_watch; 396 unsigned long time_stamp; 397 struct sk_buff *skb; 398 unsigned int bytecount; 399 u16 gso_segs; 400 __be16 protocol; 401 402 DEFINE_DMA_UNMAP_ADDR(dma); 403 DEFINE_DMA_UNMAP_LEN(len); 404 u32 tx_flags; 405 }; 406 407 struct igc_rx_buffer { 408 dma_addr_t dma; 409 struct page *page; 410 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 411 __u32 page_offset; 412 #else 413 __u16 page_offset; 414 #endif 415 __u16 pagecnt_bias; 416 }; 417 418 struct igc_q_vector { 419 struct igc_adapter *adapter; /* backlink */ 420 void __iomem *itr_register; 421 u32 eims_value; /* EIMS mask value */ 422 423 u16 itr_val; 424 u8 set_itr; 425 426 struct igc_ring_container rx, tx; 427 428 struct napi_struct napi; 429 430 struct rcu_head rcu; /* to avoid race with update stats on free */ 431 char name[IFNAMSIZ + 9]; 432 struct net_device poll_dev; 433 434 /* for dynamic allocation of rings associated with this q_vector */ 435 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 436 }; 437 438 enum igc_filter_match_flags { 439 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 440 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 441 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 442 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 443 }; 444 445 struct igc_nfc_filter { 446 u8 match_flags; 447 u16 etype; 448 u16 vlan_tci; 449 u8 src_addr[ETH_ALEN]; 450 u8 dst_addr[ETH_ALEN]; 451 }; 452 453 struct igc_nfc_rule { 454 struct list_head list; 455 struct igc_nfc_filter filter; 456 u32 location; 457 u16 action; 458 }; 459 460 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority 461 * based, and 8 ethertype based. 462 */ 463 #define IGC_MAX_RXNFC_RULES 32 464 465 /* igc_desc_unused - calculate if we have unused descriptors */ 466 static inline u16 igc_desc_unused(const struct igc_ring *ring) 467 { 468 u16 ntc = ring->next_to_clean; 469 u16 ntu = ring->next_to_use; 470 471 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 472 } 473 474 static inline s32 igc_get_phy_info(struct igc_hw *hw) 475 { 476 if (hw->phy.ops.get_phy_info) 477 return hw->phy.ops.get_phy_info(hw); 478 479 return 0; 480 } 481 482 static inline s32 igc_reset_phy(struct igc_hw *hw) 483 { 484 if (hw->phy.ops.reset) 485 return hw->phy.ops.reset(hw); 486 487 return 0; 488 } 489 490 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 491 { 492 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 493 } 494 495 enum igc_ring_flags_t { 496 IGC_RING_FLAG_RX_3K_BUFFER, 497 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 498 IGC_RING_FLAG_RX_SCTP_CSUM, 499 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 500 IGC_RING_FLAG_TX_CTX_IDX, 501 IGC_RING_FLAG_TX_DETECT_HANG 502 }; 503 504 #define ring_uses_large_buffer(ring) \ 505 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 506 507 #define ring_uses_build_skb(ring) \ 508 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 509 510 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 511 { 512 #if (PAGE_SIZE < 8192) 513 if (ring_uses_large_buffer(ring)) 514 return IGC_RXBUFFER_3072; 515 516 if (ring_uses_build_skb(ring)) 517 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 518 #endif 519 return IGC_RXBUFFER_2048; 520 } 521 522 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 523 { 524 #if (PAGE_SIZE < 8192) 525 if (ring_uses_large_buffer(ring)) 526 return 1; 527 #endif 528 return 0; 529 } 530 531 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 532 { 533 if (hw->phy.ops.read_reg) 534 return hw->phy.ops.read_reg(hw, offset, data); 535 536 return 0; 537 } 538 539 void igc_reinit_locked(struct igc_adapter *); 540 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 541 u32 location); 542 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 543 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 544 545 void igc_ptp_init(struct igc_adapter *adapter); 546 void igc_ptp_reset(struct igc_adapter *adapter); 547 void igc_ptp_suspend(struct igc_adapter *adapter); 548 void igc_ptp_stop(struct igc_adapter *adapter); 549 void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 550 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 551 struct sk_buff *skb); 552 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 553 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 554 void igc_ptp_tx_hang(struct igc_adapter *adapter); 555 556 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 557 558 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 559 560 #define IGC_RX_DESC(R, i) \ 561 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 562 #define IGC_TX_DESC(R, i) \ 563 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 564 #define IGC_TX_CTXTDESC(R, i) \ 565 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 566 567 #endif /* _IGC_H_ */ 568