1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/bitfield.h> 17 #include <linux/hrtimer.h> 18 19 #include "igc_hw.h" 20 21 void igc_ethtool_set_ops(struct net_device *); 22 23 /* Transmit and receive queues */ 24 #define IGC_MAX_RX_QUEUES 4 25 #define IGC_MAX_TX_QUEUES 4 26 27 #define MAX_Q_VECTORS 8 28 #define MAX_STD_JUMBO_FRAME_SIZE 9216 29 30 #define MAX_ETYPE_FILTER 8 31 #define IGC_RETA_SIZE 128 32 33 /* SDP support */ 34 #define IGC_N_EXTTS 2 35 #define IGC_N_PEROUT 2 36 #define IGC_N_SDP 4 37 38 #define MAX_FLEX_FILTER 32 39 40 enum igc_mac_filter_type { 41 IGC_MAC_FILTER_TYPE_DST = 0, 42 IGC_MAC_FILTER_TYPE_SRC 43 }; 44 45 struct igc_tx_queue_stats { 46 u64 packets; 47 u64 bytes; 48 u64 restart_queue; 49 u64 restart_queue2; 50 }; 51 52 struct igc_rx_queue_stats { 53 u64 packets; 54 u64 bytes; 55 u64 drops; 56 u64 csum_err; 57 u64 alloc_failed; 58 }; 59 60 struct igc_rx_packet_stats { 61 u64 ipv4_packets; /* IPv4 headers processed */ 62 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 63 u64 ipv6_packets; /* IPv6 headers processed */ 64 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 65 u64 tcp_packets; /* TCP headers processed */ 66 u64 udp_packets; /* UDP headers processed */ 67 u64 sctp_packets; /* SCTP headers processed */ 68 u64 nfs_packets; /* NFS headers processe */ 69 u64 other_packets; 70 }; 71 72 struct igc_ring_container { 73 struct igc_ring *ring; /* pointer to linked list of rings */ 74 unsigned int total_bytes; /* total bytes processed this int */ 75 unsigned int total_packets; /* total packets processed this int */ 76 u16 work_limit; /* total work allowed per interrupt */ 77 u8 count; /* total number of rings in vector */ 78 u8 itr; /* current ITR setting for ring */ 79 }; 80 81 struct igc_ring { 82 struct igc_q_vector *q_vector; /* backlink to q_vector */ 83 struct net_device *netdev; /* back pointer to net_device */ 84 struct device *dev; /* device for dma mapping */ 85 union { /* array of buffer info structs */ 86 struct igc_tx_buffer *tx_buffer_info; 87 struct igc_rx_buffer *rx_buffer_info; 88 }; 89 void *desc; /* descriptor ring memory */ 90 unsigned long flags; /* ring specific flags */ 91 void __iomem *tail; /* pointer to ring tail register */ 92 dma_addr_t dma; /* phys address of the ring */ 93 unsigned int size; /* length of desc. ring in bytes */ 94 95 u16 count; /* number of desc. in the ring */ 96 u8 queue_index; /* logical index of the ring*/ 97 u8 reg_idx; /* physical index of the ring */ 98 bool launchtime_enable; /* true if LaunchTime is enabled */ 99 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */ 100 ktime_t last_ff_cycle; /* Last cycle with an active first flag */ 101 102 u32 start_time; 103 u32 end_time; 104 u32 max_sdu; 105 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */ 106 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */ 107 108 /* CBS parameters */ 109 bool cbs_enable; /* indicates if CBS is enabled */ 110 s32 idleslope; /* idleSlope in kbps */ 111 s32 sendslope; /* sendSlope in kbps */ 112 s32 hicredit; /* hiCredit in bytes */ 113 s32 locredit; /* loCredit in bytes */ 114 115 /* everything past this point are written often */ 116 u16 next_to_clean; 117 u16 next_to_use; 118 u16 next_to_alloc; 119 120 union { 121 /* TX */ 122 struct { 123 struct igc_tx_queue_stats tx_stats; 124 struct u64_stats_sync tx_syncp; 125 struct u64_stats_sync tx_syncp2; 126 }; 127 /* RX */ 128 struct { 129 struct igc_rx_queue_stats rx_stats; 130 struct igc_rx_packet_stats pkt_stats; 131 struct u64_stats_sync rx_syncp; 132 struct sk_buff *skb; 133 }; 134 }; 135 136 struct xdp_rxq_info xdp_rxq; 137 struct xsk_buff_pool *xsk_pool; 138 } ____cacheline_internodealigned_in_smp; 139 140 /* Board specific private data structure */ 141 struct igc_adapter { 142 struct net_device *netdev; 143 144 struct ethtool_eee eee; 145 u16 eee_advert; 146 147 unsigned long state; 148 unsigned int flags; 149 unsigned int num_q_vectors; 150 151 struct msix_entry *msix_entries; 152 153 /* TX */ 154 u16 tx_work_limit; 155 u32 tx_timeout_count; 156 int num_tx_queues; 157 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 158 159 /* RX */ 160 int num_rx_queues; 161 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 162 163 struct timer_list watchdog_timer; 164 struct timer_list dma_err_timer; 165 struct timer_list phy_info_timer; 166 struct hrtimer hrtimer; 167 168 u32 wol; 169 u32 en_mng_pt; 170 u16 link_speed; 171 u16 link_duplex; 172 173 u8 port_num; 174 175 u8 __iomem *io_addr; 176 /* Interrupt Throttle Rate */ 177 u32 rx_itr_setting; 178 u32 tx_itr_setting; 179 180 struct work_struct reset_task; 181 struct work_struct watchdog_task; 182 struct work_struct dma_err_task; 183 bool fc_autoneg; 184 185 u8 tx_timeout_factor; 186 187 int msg_enable; 188 u32 max_frame_size; 189 u32 min_frame_size; 190 191 int tc_setup_type; 192 ktime_t base_time; 193 ktime_t cycle_time; 194 bool taprio_offload_enable; 195 u32 qbv_config_change_errors; 196 bool qbv_transition; 197 unsigned int qbv_count; 198 /* Access to oper_gate_closed, admin_gate_closed and qbv_transition 199 * are protected by the qbv_tx_lock. 200 */ 201 spinlock_t qbv_tx_lock; 202 203 /* OS defined structs */ 204 struct pci_dev *pdev; 205 /* lock for statistics */ 206 spinlock_t stats64_lock; 207 struct rtnl_link_stats64 stats64; 208 209 /* structs defined in igc_hw.h */ 210 struct igc_hw hw; 211 struct igc_hw_stats stats; 212 213 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 214 u32 eims_enable_mask; 215 u32 eims_other; 216 217 u16 tx_ring_count; 218 u16 rx_ring_count; 219 220 u32 tx_hwtstamp_timeouts; 221 u32 tx_hwtstamp_skipped; 222 u32 rx_hwtstamp_cleared; 223 224 u32 rss_queues; 225 u32 rss_indir_tbl_init; 226 227 /* Any access to elements in nfc_rule_list is protected by the 228 * nfc_rule_lock. 229 */ 230 struct mutex nfc_rule_lock; 231 struct list_head nfc_rule_list; 232 unsigned int nfc_rule_count; 233 234 u8 rss_indir_tbl[IGC_RETA_SIZE]; 235 236 unsigned long link_check_timeout; 237 struct igc_info ei; 238 239 u32 test_icr; 240 241 struct ptp_clock *ptp_clock; 242 struct ptp_clock_info ptp_caps; 243 /* Access to ptp_tx_skb and ptp_tx_start are protected by the 244 * ptp_tx_lock. 245 */ 246 spinlock_t ptp_tx_lock; 247 struct sk_buff *ptp_tx_skb; 248 struct hwtstamp_config tstamp_config; 249 unsigned long ptp_tx_start; 250 unsigned int ptp_flags; 251 /* System time value lock */ 252 spinlock_t tmreg_lock; 253 struct cyclecounter cc; 254 struct timecounter tc; 255 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 256 ktime_t ptp_reset_start; /* Reset time in clock mono */ 257 struct system_time_snapshot snapshot; 258 259 char fw_version[32]; 260 261 struct bpf_prog *xdp_prog; 262 263 bool pps_sys_wrap_on; 264 265 struct ptp_pin_desc sdp_config[IGC_N_SDP]; 266 struct { 267 struct timespec64 start; 268 struct timespec64 period; 269 } perout[IGC_N_PEROUT]; 270 }; 271 272 void igc_up(struct igc_adapter *adapter); 273 void igc_down(struct igc_adapter *adapter); 274 int igc_open(struct net_device *netdev); 275 int igc_close(struct net_device *netdev); 276 int igc_setup_tx_resources(struct igc_ring *ring); 277 int igc_setup_rx_resources(struct igc_ring *ring); 278 void igc_free_tx_resources(struct igc_ring *ring); 279 void igc_free_rx_resources(struct igc_ring *ring); 280 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 281 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 282 const u32 max_rss_queues); 283 int igc_reinit_queues(struct igc_adapter *adapter); 284 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 285 bool igc_has_link(struct igc_adapter *adapter); 286 void igc_reset(struct igc_adapter *adapter); 287 void igc_update_stats(struct igc_adapter *adapter); 288 void igc_disable_rx_ring(struct igc_ring *ring); 289 void igc_enable_rx_ring(struct igc_ring *ring); 290 void igc_disable_tx_ring(struct igc_ring *ring); 291 void igc_enable_tx_ring(struct igc_ring *ring); 292 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 293 294 /* igc_dump declarations */ 295 void igc_rings_dump(struct igc_adapter *adapter); 296 void igc_regs_dump(struct igc_adapter *adapter); 297 298 extern char igc_driver_name[]; 299 300 #define IGC_REGS_LEN 740 301 302 /* flags controlling PTP/1588 function */ 303 #define IGC_PTP_ENABLED BIT(0) 304 305 /* Flags definitions */ 306 #define IGC_FLAG_HAS_MSI BIT(0) 307 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 308 #define IGC_FLAG_DMAC BIT(4) 309 #define IGC_FLAG_PTP BIT(8) 310 #define IGC_FLAG_WOL_SUPPORTED BIT(8) 311 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 312 #define IGC_FLAG_HAS_MSIX BIT(13) 313 #define IGC_FLAG_EEE BIT(14) 314 #define IGC_FLAG_VLAN_PROMISC BIT(15) 315 #define IGC_FLAG_RX_LEGACY BIT(16) 316 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 317 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) 318 319 #define IGC_FLAG_TSN_ANY_ENABLED \ 320 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED) 321 322 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 323 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 324 325 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 326 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 327 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 328 329 /* RX-desc Write-Back format RSS Type's */ 330 enum igc_rss_type_num { 331 IGC_RSS_TYPE_NO_HASH = 0, 332 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1, 333 IGC_RSS_TYPE_HASH_IPV4 = 2, 334 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3, 335 IGC_RSS_TYPE_HASH_IPV6_EX = 4, 336 IGC_RSS_TYPE_HASH_IPV6 = 5, 337 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6, 338 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7, 339 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8, 340 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9, 341 IGC_RSS_TYPE_MAX = 10, 342 }; 343 #define IGC_RSS_TYPE_MAX_TABLE 16 344 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */ 345 346 /* igc_rss_type - Rx descriptor RSS type field */ 347 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc) 348 { 349 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved) 350 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info) 351 * is slightly slower than via u32 (wb.lower.lo_dword.data) 352 */ 353 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK); 354 } 355 356 /* Interrupt defines */ 357 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 358 #define IGC_4K_ITR 980 359 #define IGC_20K_ITR 196 360 #define IGC_70K_ITR 56 361 362 #define IGC_DEFAULT_ITR 3 /* dynamic */ 363 #define IGC_MAX_ITR_USECS 10000 364 #define IGC_MIN_ITR_USECS 10 365 #define NON_Q_VECTORS 1 366 #define MAX_MSIX_ENTRIES 10 367 368 /* TX/RX descriptor defines */ 369 #define IGC_DEFAULT_TXD 256 370 #define IGC_DEFAULT_TX_WORK 128 371 #define IGC_MIN_TXD 80 372 #define IGC_MAX_TXD 4096 373 374 #define IGC_DEFAULT_RXD 256 375 #define IGC_MIN_RXD 80 376 #define IGC_MAX_RXD 4096 377 378 /* Supported Rx Buffer Sizes */ 379 #define IGC_RXBUFFER_256 256 380 #define IGC_RXBUFFER_2048 2048 381 #define IGC_RXBUFFER_3072 3072 382 383 #define AUTO_ALL_MODES 0 384 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 385 386 /* Transmit and receive latency (for PTP timestamps) */ 387 #define IGC_I225_TX_LATENCY_10 240 388 #define IGC_I225_TX_LATENCY_100 58 389 #define IGC_I225_TX_LATENCY_1000 80 390 #define IGC_I225_TX_LATENCY_2500 1325 391 #define IGC_I225_RX_LATENCY_10 6450 392 #define IGC_I225_RX_LATENCY_100 185 393 #define IGC_I225_RX_LATENCY_1000 300 394 #define IGC_I225_RX_LATENCY_2500 1485 395 396 /* RX and TX descriptor control thresholds. 397 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 398 * descriptors available in its onboard memory. 399 * Setting this to 0 disables RX descriptor prefetch. 400 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 401 * available in host memory. 402 * If PTHRESH is 0, this should also be 0. 403 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 404 * descriptors until either it has this many to write back, or the 405 * ITR timer expires. 406 */ 407 #define IGC_RX_PTHRESH 8 408 #define IGC_RX_HTHRESH 8 409 #define IGC_TX_PTHRESH 8 410 #define IGC_TX_HTHRESH 1 411 #define IGC_RX_WTHRESH 4 412 #define IGC_TX_WTHRESH 16 413 414 #define IGC_RX_DMA_ATTR \ 415 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 416 417 #define IGC_TS_HDR_LEN 16 418 419 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 420 421 #if (PAGE_SIZE < 8192) 422 #define IGC_MAX_FRAME_BUILD_SKB \ 423 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 424 #else 425 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 426 #endif 427 428 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 429 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 430 431 /* VLAN info */ 432 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 433 #define IGC_TX_FLAGS_VLAN_SHIFT 16 434 435 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 436 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 437 const u32 stat_err_bits) 438 { 439 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 440 } 441 442 enum igc_state_t { 443 __IGC_TESTING, 444 __IGC_RESETTING, 445 __IGC_DOWN, 446 }; 447 448 enum igc_tx_flags { 449 /* cmd_type flags */ 450 IGC_TX_FLAGS_VLAN = 0x01, 451 IGC_TX_FLAGS_TSO = 0x02, 452 IGC_TX_FLAGS_TSTAMP = 0x04, 453 454 /* olinfo flags */ 455 IGC_TX_FLAGS_IPV4 = 0x10, 456 IGC_TX_FLAGS_CSUM = 0x20, 457 }; 458 459 enum igc_boards { 460 board_base, 461 }; 462 463 /* The largest size we can write to the descriptor is 65535. In order to 464 * maintain a power of two alignment we have to limit ourselves to 32K. 465 */ 466 #define IGC_MAX_TXD_PWR 15 467 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 468 469 /* Tx Descriptors needed, worst case */ 470 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 471 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 472 473 enum igc_tx_buffer_type { 474 IGC_TX_BUFFER_TYPE_SKB, 475 IGC_TX_BUFFER_TYPE_XDP, 476 IGC_TX_BUFFER_TYPE_XSK, 477 }; 478 479 /* wrapper around a pointer to a socket buffer, 480 * so a DMA handle can be stored along with the buffer 481 */ 482 struct igc_tx_buffer { 483 union igc_adv_tx_desc *next_to_watch; 484 unsigned long time_stamp; 485 enum igc_tx_buffer_type type; 486 union { 487 struct sk_buff *skb; 488 struct xdp_frame *xdpf; 489 }; 490 unsigned int bytecount; 491 u16 gso_segs; 492 __be16 protocol; 493 494 DEFINE_DMA_UNMAP_ADDR(dma); 495 DEFINE_DMA_UNMAP_LEN(len); 496 u32 tx_flags; 497 }; 498 499 struct igc_rx_buffer { 500 union { 501 struct { 502 dma_addr_t dma; 503 struct page *page; 504 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 505 __u32 page_offset; 506 #else 507 __u16 page_offset; 508 #endif 509 __u16 pagecnt_bias; 510 }; 511 struct xdp_buff *xdp; 512 }; 513 }; 514 515 /* context wrapper around xdp_buff to provide access to descriptor metadata */ 516 struct igc_xdp_buff { 517 struct xdp_buff xdp; 518 union igc_adv_rx_desc *rx_desc; 519 ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */ 520 }; 521 522 struct igc_q_vector { 523 struct igc_adapter *adapter; /* backlink */ 524 void __iomem *itr_register; 525 u32 eims_value; /* EIMS mask value */ 526 527 u16 itr_val; 528 u8 set_itr; 529 530 struct igc_ring_container rx, tx; 531 532 struct napi_struct napi; 533 534 struct rcu_head rcu; /* to avoid race with update stats on free */ 535 char name[IFNAMSIZ + 9]; 536 struct net_device poll_dev; 537 538 /* for dynamic allocation of rings associated with this q_vector */ 539 struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 540 }; 541 542 enum igc_filter_match_flags { 543 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 544 IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 545 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 546 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 547 IGC_FILTER_FLAG_USER_DATA = BIT(4), 548 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 549 }; 550 551 struct igc_nfc_filter { 552 u8 match_flags; 553 u16 etype; 554 __be16 vlan_etype; 555 u16 vlan_tci; 556 u8 src_addr[ETH_ALEN]; 557 u8 dst_addr[ETH_ALEN]; 558 u8 user_data[8]; 559 u8 user_mask[8]; 560 u8 flex_index; 561 u8 rx_queue; 562 u8 prio; 563 u8 immediate_irq; 564 u8 drop; 565 }; 566 567 struct igc_nfc_rule { 568 struct list_head list; 569 struct igc_nfc_filter filter; 570 u32 location; 571 u16 action; 572 bool flex; 573 }; 574 575 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 576 * based, 8 ethertype based and 32 Flex filter based rules. 577 */ 578 #define IGC_MAX_RXNFC_RULES 64 579 580 struct igc_flex_filter { 581 u8 index; 582 u8 data[128]; 583 u8 mask[16]; 584 u8 length; 585 u8 rx_queue; 586 u8 prio; 587 u8 immediate_irq; 588 u8 drop; 589 }; 590 591 /* igc_desc_unused - calculate if we have unused descriptors */ 592 static inline u16 igc_desc_unused(const struct igc_ring *ring) 593 { 594 u16 ntc = ring->next_to_clean; 595 u16 ntu = ring->next_to_use; 596 597 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 598 } 599 600 static inline s32 igc_get_phy_info(struct igc_hw *hw) 601 { 602 if (hw->phy.ops.get_phy_info) 603 return hw->phy.ops.get_phy_info(hw); 604 605 return 0; 606 } 607 608 static inline s32 igc_reset_phy(struct igc_hw *hw) 609 { 610 if (hw->phy.ops.reset) 611 return hw->phy.ops.reset(hw); 612 613 return 0; 614 } 615 616 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 617 { 618 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 619 } 620 621 enum igc_ring_flags_t { 622 IGC_RING_FLAG_RX_3K_BUFFER, 623 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 624 IGC_RING_FLAG_RX_SCTP_CSUM, 625 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 626 IGC_RING_FLAG_TX_CTX_IDX, 627 IGC_RING_FLAG_TX_DETECT_HANG, 628 IGC_RING_FLAG_AF_XDP_ZC, 629 IGC_RING_FLAG_TX_HWTSTAMP, 630 }; 631 632 #define ring_uses_large_buffer(ring) \ 633 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 634 #define set_ring_uses_large_buffer(ring) \ 635 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 636 #define clear_ring_uses_large_buffer(ring) \ 637 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 638 639 #define ring_uses_build_skb(ring) \ 640 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 641 642 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 643 { 644 #if (PAGE_SIZE < 8192) 645 if (ring_uses_large_buffer(ring)) 646 return IGC_RXBUFFER_3072; 647 648 if (ring_uses_build_skb(ring)) 649 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 650 #endif 651 return IGC_RXBUFFER_2048; 652 } 653 654 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 655 { 656 #if (PAGE_SIZE < 8192) 657 if (ring_uses_large_buffer(ring)) 658 return 1; 659 #endif 660 return 0; 661 } 662 663 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 664 { 665 if (hw->phy.ops.read_reg) 666 return hw->phy.ops.read_reg(hw, offset, data); 667 668 return -EOPNOTSUPP; 669 } 670 671 void igc_reinit_locked(struct igc_adapter *); 672 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 673 u32 location); 674 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 675 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 676 677 void igc_ptp_init(struct igc_adapter *adapter); 678 void igc_ptp_reset(struct igc_adapter *adapter); 679 void igc_ptp_suspend(struct igc_adapter *adapter); 680 void igc_ptp_stop(struct igc_adapter *adapter); 681 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 682 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 683 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 684 void igc_ptp_tx_hang(struct igc_adapter *adapter); 685 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 686 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter); 687 688 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 689 690 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 691 692 #define IGC_RX_DESC(R, i) \ 693 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 694 #define IGC_TX_DESC(R, i) \ 695 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 696 #define IGC_TX_CTXTDESC(R, i) \ 697 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 698 699 #endif /* _IGC_H_ */ 700