1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/vmalloc.h> 12 13 #include <linux/ethtool.h> 14 15 #include <linux/sctp.h> 16 17 #define IGC_ERR(args...) pr_err("igc: " args) 18 19 #define PFX "igc: " 20 21 #include <linux/timecounter.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/ptp_clock_kernel.h> 24 25 #include "igc_hw.h" 26 27 /* main */ 28 extern char igc_driver_name[]; 29 extern char igc_driver_version[]; 30 31 /* Interrupt defines */ 32 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 33 #define IGC_FLAG_HAS_MSI BIT(0) 34 #define IGC_FLAG_QUEUE_PAIRS BIT(4) 35 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 36 #define IGC_FLAG_MEDIA_RESET BIT(10) 37 #define IGC_FLAG_MAS_ENABLE BIT(12) 38 #define IGC_FLAG_HAS_MSIX BIT(13) 39 #define IGC_FLAG_VLAN_PROMISC BIT(15) 40 41 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 42 #define IGC_4K_ITR 980 43 #define IGC_20K_ITR 196 44 #define IGC_70K_ITR 56 45 46 #define IGC_DEFAULT_ITR 3 /* dynamic */ 47 #define IGC_MAX_ITR_USECS 10000 48 #define IGC_MIN_ITR_USECS 10 49 #define NON_Q_VECTORS 1 50 #define MAX_MSIX_ENTRIES 10 51 52 /* TX/RX descriptor defines */ 53 #define IGC_DEFAULT_TXD 256 54 #define IGC_DEFAULT_TX_WORK 128 55 #define IGC_MIN_TXD 80 56 #define IGC_MAX_TXD 4096 57 58 #define IGC_DEFAULT_RXD 256 59 #define IGC_MIN_RXD 80 60 #define IGC_MAX_RXD 4096 61 62 /* Transmit and receive queues */ 63 #define IGC_MAX_RX_QUEUES 4 64 #define IGC_MAX_TX_QUEUES 4 65 66 #define MAX_Q_VECTORS 8 67 #define MAX_STD_JUMBO_FRAME_SIZE 9216 68 69 /* Supported Rx Buffer Sizes */ 70 #define IGC_RXBUFFER_256 256 71 #define IGC_RXBUFFER_2048 2048 72 #define IGC_RXBUFFER_3072 3072 73 74 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 75 76 /* RX and TX descriptor control thresholds. 77 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 78 * descriptors available in its onboard memory. 79 * Setting this to 0 disables RX descriptor prefetch. 80 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 81 * available in host memory. 82 * If PTHRESH is 0, this should also be 0. 83 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 84 * descriptors until either it has this many to write back, or the 85 * ITR timer expires. 86 */ 87 #define IGC_RX_PTHRESH 8 88 #define IGC_RX_HTHRESH 8 89 #define IGC_TX_PTHRESH 8 90 #define IGC_TX_HTHRESH 1 91 #define IGC_RX_WTHRESH 4 92 #define IGC_TX_WTHRESH 16 93 94 #define IGC_RX_DMA_ATTR \ 95 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 96 97 #define IGC_TS_HDR_LEN 16 98 99 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 100 101 #if (PAGE_SIZE < 8192) 102 #define IGC_MAX_FRAME_BUILD_SKB \ 103 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 104 #else 105 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 106 #endif 107 108 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 109 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 110 111 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 112 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 113 const u32 stat_err_bits) 114 { 115 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 116 } 117 118 enum igc_state_t { 119 __IGC_TESTING, 120 __IGC_RESETTING, 121 __IGC_DOWN, 122 __IGC_PTP_TX_IN_PROGRESS, 123 }; 124 125 enum igc_tx_flags { 126 /* cmd_type flags */ 127 IGC_TX_FLAGS_VLAN = 0x01, 128 IGC_TX_FLAGS_TSO = 0x02, 129 IGC_TX_FLAGS_TSTAMP = 0x04, 130 131 /* olinfo flags */ 132 IGC_TX_FLAGS_IPV4 = 0x10, 133 IGC_TX_FLAGS_CSUM = 0x20, 134 }; 135 136 enum igc_boards { 137 board_base, 138 }; 139 140 /* The largest size we can write to the descriptor is 65535. In order to 141 * maintain a power of two alignment we have to limit ourselves to 32K. 142 */ 143 #define IGC_MAX_TXD_PWR 15 144 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 145 146 /* Tx Descriptors needed, worst case */ 147 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 148 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 149 150 /* wrapper around a pointer to a socket buffer, 151 * so a DMA handle can be stored along with the buffer 152 */ 153 struct igc_tx_buffer { 154 union igc_adv_tx_desc *next_to_watch; 155 unsigned long time_stamp; 156 struct sk_buff *skb; 157 unsigned int bytecount; 158 u16 gso_segs; 159 __be16 protocol; 160 161 DEFINE_DMA_UNMAP_ADDR(dma); 162 DEFINE_DMA_UNMAP_LEN(len); 163 u32 tx_flags; 164 }; 165 166 struct igc_rx_buffer { 167 dma_addr_t dma; 168 struct page *page; 169 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 170 __u32 page_offset; 171 #else 172 __u16 page_offset; 173 #endif 174 __u16 pagecnt_bias; 175 }; 176 177 struct igc_tx_queue_stats { 178 u64 packets; 179 u64 bytes; 180 u64 restart_queue; 181 u64 restart_queue2; 182 }; 183 184 struct igc_rx_queue_stats { 185 u64 packets; 186 u64 bytes; 187 u64 drops; 188 u64 csum_err; 189 u64 alloc_failed; 190 }; 191 192 struct igc_rx_packet_stats { 193 u64 ipv4_packets; /* IPv4 headers processed */ 194 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 195 u64 ipv6_packets; /* IPv6 headers processed */ 196 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 197 u64 tcp_packets; /* TCP headers processed */ 198 u64 udp_packets; /* UDP headers processed */ 199 u64 sctp_packets; /* SCTP headers processed */ 200 u64 nfs_packets; /* NFS headers processe */ 201 u64 other_packets; 202 }; 203 204 struct igc_ring_container { 205 struct igc_ring *ring; /* pointer to linked list of rings */ 206 unsigned int total_bytes; /* total bytes processed this int */ 207 unsigned int total_packets; /* total packets processed this int */ 208 u16 work_limit; /* total work allowed per interrupt */ 209 u8 count; /* total number of rings in vector */ 210 u8 itr; /* current ITR setting for ring */ 211 }; 212 213 struct igc_ring { 214 struct igc_q_vector *q_vector; /* backlink to q_vector */ 215 struct net_device *netdev; /* back pointer to net_device */ 216 struct device *dev; /* device for dma mapping */ 217 union { /* array of buffer info structs */ 218 struct igc_tx_buffer *tx_buffer_info; 219 struct igc_rx_buffer *rx_buffer_info; 220 }; 221 void *desc; /* descriptor ring memory */ 222 unsigned long flags; /* ring specific flags */ 223 void __iomem *tail; /* pointer to ring tail register */ 224 dma_addr_t dma; /* phys address of the ring */ 225 unsigned int size; /* length of desc. ring in bytes */ 226 227 u16 count; /* number of desc. in the ring */ 228 u8 queue_index; /* logical index of the ring*/ 229 u8 reg_idx; /* physical index of the ring */ 230 231 /* everything past this point are written often */ 232 u16 next_to_clean; 233 u16 next_to_use; 234 u16 next_to_alloc; 235 236 union { 237 /* TX */ 238 struct { 239 struct igc_tx_queue_stats tx_stats; 240 struct u64_stats_sync tx_syncp; 241 struct u64_stats_sync tx_syncp2; 242 }; 243 /* RX */ 244 struct { 245 struct igc_rx_queue_stats rx_stats; 246 struct igc_rx_packet_stats pkt_stats; 247 struct u64_stats_sync rx_syncp; 248 struct sk_buff *skb; 249 }; 250 }; 251 } ____cacheline_internodealigned_in_smp; 252 253 struct igc_q_vector { 254 struct igc_adapter *adapter; /* backlink */ 255 void __iomem *itr_register; 256 u32 eims_value; /* EIMS mask value */ 257 258 u16 itr_val; 259 u8 set_itr; 260 261 struct igc_ring_container rx, tx; 262 263 struct napi_struct napi; 264 265 struct rcu_head rcu; /* to avoid race with update stats on free */ 266 char name[IFNAMSIZ + 9]; 267 struct net_device poll_dev; 268 269 /* for dynamic allocation of rings associated with this q_vector */ 270 struct igc_ring ring[0] ____cacheline_internodealigned_in_smp; 271 }; 272 273 struct igc_mac_addr { 274 u8 addr[ETH_ALEN]; 275 u8 queue; 276 u8 state; /* bitmask */ 277 }; 278 279 #define IGC_MAC_STATE_DEFAULT 0x1 280 #define IGC_MAC_STATE_MODIFIED 0x2 281 #define IGC_MAC_STATE_IN_USE 0x4 282 283 /* Board specific private data structure */ 284 struct igc_adapter { 285 struct net_device *netdev; 286 287 unsigned long state; 288 unsigned int flags; 289 unsigned int num_q_vectors; 290 291 struct msix_entry *msix_entries; 292 293 /* TX */ 294 u16 tx_work_limit; 295 u32 tx_timeout_count; 296 int num_tx_queues; 297 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 298 299 /* RX */ 300 int num_rx_queues; 301 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 302 303 struct timer_list watchdog_timer; 304 struct timer_list dma_err_timer; 305 struct timer_list phy_info_timer; 306 307 u16 link_speed; 308 u16 link_duplex; 309 310 u8 port_num; 311 312 u8 __iomem *io_addr; 313 /* Interrupt Throttle Rate */ 314 u32 rx_itr_setting; 315 u32 tx_itr_setting; 316 317 struct work_struct reset_task; 318 struct work_struct watchdog_task; 319 struct work_struct dma_err_task; 320 bool fc_autoneg; 321 322 u8 tx_timeout_factor; 323 324 int msg_enable; 325 u32 max_frame_size; 326 u32 min_frame_size; 327 328 /* OS defined structs */ 329 struct pci_dev *pdev; 330 /* lock for statistics */ 331 spinlock_t stats64_lock; 332 struct rtnl_link_stats64 stats64; 333 334 /* structs defined in igc_hw.h */ 335 struct igc_hw hw; 336 struct igc_hw_stats stats; 337 338 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 339 u32 eims_enable_mask; 340 u32 eims_other; 341 342 u16 tx_ring_count; 343 u16 rx_ring_count; 344 345 u32 *shadow_vfta; 346 347 u32 rss_queues; 348 349 /* lock for RX network flow classification filter */ 350 spinlock_t nfc_lock; 351 352 struct igc_mac_addr *mac_table; 353 354 unsigned long link_check_timeout; 355 struct igc_info ei; 356 }; 357 358 /* igc_desc_unused - calculate if we have unused descriptors */ 359 static inline u16 igc_desc_unused(const struct igc_ring *ring) 360 { 361 u16 ntc = ring->next_to_clean; 362 u16 ntu = ring->next_to_use; 363 364 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 365 } 366 367 static inline s32 igc_get_phy_info(struct igc_hw *hw) 368 { 369 if (hw->phy.ops.get_phy_info) 370 return hw->phy.ops.get_phy_info(hw); 371 372 return 0; 373 } 374 375 static inline s32 igc_reset_phy(struct igc_hw *hw) 376 { 377 if (hw->phy.ops.reset) 378 return hw->phy.ops.reset(hw); 379 380 return 0; 381 } 382 383 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 384 { 385 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 386 } 387 388 enum igc_ring_flags_t { 389 IGC_RING_FLAG_RX_3K_BUFFER, 390 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 391 IGC_RING_FLAG_RX_SCTP_CSUM, 392 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 393 IGC_RING_FLAG_TX_CTX_IDX, 394 IGC_RING_FLAG_TX_DETECT_HANG 395 }; 396 397 #define ring_uses_large_buffer(ring) \ 398 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 399 400 #define ring_uses_build_skb(ring) \ 401 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 402 403 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 404 { 405 #if (PAGE_SIZE < 8192) 406 if (ring_uses_large_buffer(ring)) 407 return IGC_RXBUFFER_3072; 408 409 if (ring_uses_build_skb(ring)) 410 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 411 #endif 412 return IGC_RXBUFFER_2048; 413 } 414 415 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 416 { 417 #if (PAGE_SIZE < 8192) 418 if (ring_uses_large_buffer(ring)) 419 return 1; 420 #endif 421 return 0; 422 } 423 424 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 425 { 426 if (hw->phy.ops.read_reg) 427 return hw->phy.ops.read_reg(hw, offset, data); 428 429 return 0; 430 } 431 432 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 433 434 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 435 436 #define IGC_RX_DESC(R, i) \ 437 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 438 #define IGC_TX_DESC(R, i) \ 439 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 440 #define IGC_TX_CTXTDESC(R, i) \ 441 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 442 443 #endif /* _IGC_H_ */ 444