1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 14 #include "igc_hw.h" 15 16 /* main */ 17 extern char igc_driver_name[]; 18 extern char igc_driver_version[]; 19 20 /* Interrupt defines */ 21 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 22 #define IGC_FLAG_HAS_MSI BIT(0) 23 #define IGC_FLAG_QUEUE_PAIRS BIT(4) 24 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 25 #define IGC_FLAG_MEDIA_RESET BIT(10) 26 #define IGC_FLAG_MAS_ENABLE BIT(12) 27 #define IGC_FLAG_HAS_MSIX BIT(13) 28 #define IGC_FLAG_VLAN_PROMISC BIT(15) 29 30 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 31 #define IGC_4K_ITR 980 32 #define IGC_20K_ITR 196 33 #define IGC_70K_ITR 56 34 35 #define IGC_DEFAULT_ITR 3 /* dynamic */ 36 #define IGC_MAX_ITR_USECS 10000 37 #define IGC_MIN_ITR_USECS 10 38 #define NON_Q_VECTORS 1 39 #define MAX_MSIX_ENTRIES 10 40 41 /* TX/RX descriptor defines */ 42 #define IGC_DEFAULT_TXD 256 43 #define IGC_DEFAULT_TX_WORK 128 44 #define IGC_MIN_TXD 80 45 #define IGC_MAX_TXD 4096 46 47 #define IGC_DEFAULT_RXD 256 48 #define IGC_MIN_RXD 80 49 #define IGC_MAX_RXD 4096 50 51 /* Transmit and receive queues */ 52 #define IGC_MAX_RX_QUEUES 4 53 #define IGC_MAX_TX_QUEUES 4 54 55 #define MAX_Q_VECTORS 8 56 #define MAX_STD_JUMBO_FRAME_SIZE 9216 57 58 /* Supported Rx Buffer Sizes */ 59 #define IGC_RXBUFFER_256 256 60 #define IGC_RXBUFFER_2048 2048 61 #define IGC_RXBUFFER_3072 3072 62 63 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 64 65 /* RX and TX descriptor control thresholds. 66 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 67 * descriptors available in its onboard memory. 68 * Setting this to 0 disables RX descriptor prefetch. 69 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 70 * available in host memory. 71 * If PTHRESH is 0, this should also be 0. 72 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 73 * descriptors until either it has this many to write back, or the 74 * ITR timer expires. 75 */ 76 #define IGC_RX_PTHRESH 8 77 #define IGC_RX_HTHRESH 8 78 #define IGC_TX_PTHRESH 8 79 #define IGC_TX_HTHRESH 1 80 #define IGC_RX_WTHRESH 4 81 #define IGC_TX_WTHRESH 16 82 83 #define IGC_RX_DMA_ATTR \ 84 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 85 86 #define IGC_TS_HDR_LEN 16 87 88 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 89 90 #if (PAGE_SIZE < 8192) 91 #define IGC_MAX_FRAME_BUILD_SKB \ 92 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 93 #else 94 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 95 #endif 96 97 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 98 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 99 100 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 101 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 102 const u32 stat_err_bits) 103 { 104 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 105 } 106 107 enum igc_state_t { 108 __IGC_TESTING, 109 __IGC_RESETTING, 110 __IGC_DOWN, 111 __IGC_PTP_TX_IN_PROGRESS, 112 }; 113 114 enum igc_tx_flags { 115 /* cmd_type flags */ 116 IGC_TX_FLAGS_VLAN = 0x01, 117 IGC_TX_FLAGS_TSO = 0x02, 118 IGC_TX_FLAGS_TSTAMP = 0x04, 119 120 /* olinfo flags */ 121 IGC_TX_FLAGS_IPV4 = 0x10, 122 IGC_TX_FLAGS_CSUM = 0x20, 123 }; 124 125 enum igc_boards { 126 board_base, 127 }; 128 129 /* The largest size we can write to the descriptor is 65535. In order to 130 * maintain a power of two alignment we have to limit ourselves to 32K. 131 */ 132 #define IGC_MAX_TXD_PWR 15 133 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 134 135 /* Tx Descriptors needed, worst case */ 136 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 137 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 138 139 /* wrapper around a pointer to a socket buffer, 140 * so a DMA handle can be stored along with the buffer 141 */ 142 struct igc_tx_buffer { 143 union igc_adv_tx_desc *next_to_watch; 144 unsigned long time_stamp; 145 struct sk_buff *skb; 146 unsigned int bytecount; 147 u16 gso_segs; 148 __be16 protocol; 149 150 DEFINE_DMA_UNMAP_ADDR(dma); 151 DEFINE_DMA_UNMAP_LEN(len); 152 u32 tx_flags; 153 }; 154 155 struct igc_rx_buffer { 156 dma_addr_t dma; 157 struct page *page; 158 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 159 __u32 page_offset; 160 #else 161 __u16 page_offset; 162 #endif 163 __u16 pagecnt_bias; 164 }; 165 166 struct igc_tx_queue_stats { 167 u64 packets; 168 u64 bytes; 169 u64 restart_queue; 170 u64 restart_queue2; 171 }; 172 173 struct igc_rx_queue_stats { 174 u64 packets; 175 u64 bytes; 176 u64 drops; 177 u64 csum_err; 178 u64 alloc_failed; 179 }; 180 181 struct igc_rx_packet_stats { 182 u64 ipv4_packets; /* IPv4 headers processed */ 183 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 184 u64 ipv6_packets; /* IPv6 headers processed */ 185 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 186 u64 tcp_packets; /* TCP headers processed */ 187 u64 udp_packets; /* UDP headers processed */ 188 u64 sctp_packets; /* SCTP headers processed */ 189 u64 nfs_packets; /* NFS headers processe */ 190 u64 other_packets; 191 }; 192 193 struct igc_ring_container { 194 struct igc_ring *ring; /* pointer to linked list of rings */ 195 unsigned int total_bytes; /* total bytes processed this int */ 196 unsigned int total_packets; /* total packets processed this int */ 197 u16 work_limit; /* total work allowed per interrupt */ 198 u8 count; /* total number of rings in vector */ 199 u8 itr; /* current ITR setting for ring */ 200 }; 201 202 struct igc_ring { 203 struct igc_q_vector *q_vector; /* backlink to q_vector */ 204 struct net_device *netdev; /* back pointer to net_device */ 205 struct device *dev; /* device for dma mapping */ 206 union { /* array of buffer info structs */ 207 struct igc_tx_buffer *tx_buffer_info; 208 struct igc_rx_buffer *rx_buffer_info; 209 }; 210 void *desc; /* descriptor ring memory */ 211 unsigned long flags; /* ring specific flags */ 212 void __iomem *tail; /* pointer to ring tail register */ 213 dma_addr_t dma; /* phys address of the ring */ 214 unsigned int size; /* length of desc. ring in bytes */ 215 216 u16 count; /* number of desc. in the ring */ 217 u8 queue_index; /* logical index of the ring*/ 218 u8 reg_idx; /* physical index of the ring */ 219 220 /* everything past this point are written often */ 221 u16 next_to_clean; 222 u16 next_to_use; 223 u16 next_to_alloc; 224 225 union { 226 /* TX */ 227 struct { 228 struct igc_tx_queue_stats tx_stats; 229 struct u64_stats_sync tx_syncp; 230 struct u64_stats_sync tx_syncp2; 231 }; 232 /* RX */ 233 struct { 234 struct igc_rx_queue_stats rx_stats; 235 struct igc_rx_packet_stats pkt_stats; 236 struct u64_stats_sync rx_syncp; 237 struct sk_buff *skb; 238 }; 239 }; 240 } ____cacheline_internodealigned_in_smp; 241 242 struct igc_q_vector { 243 struct igc_adapter *adapter; /* backlink */ 244 void __iomem *itr_register; 245 u32 eims_value; /* EIMS mask value */ 246 247 u16 itr_val; 248 u8 set_itr; 249 250 struct igc_ring_container rx, tx; 251 252 struct napi_struct napi; 253 254 struct rcu_head rcu; /* to avoid race with update stats on free */ 255 char name[IFNAMSIZ + 9]; 256 struct net_device poll_dev; 257 258 /* for dynamic allocation of rings associated with this q_vector */ 259 struct igc_ring ring[0] ____cacheline_internodealigned_in_smp; 260 }; 261 262 struct igc_mac_addr { 263 u8 addr[ETH_ALEN]; 264 u8 queue; 265 u8 state; /* bitmask */ 266 }; 267 268 #define IGC_MAC_STATE_DEFAULT 0x1 269 #define IGC_MAC_STATE_MODIFIED 0x2 270 #define IGC_MAC_STATE_IN_USE 0x4 271 272 /* Board specific private data structure */ 273 struct igc_adapter { 274 struct net_device *netdev; 275 276 unsigned long state; 277 unsigned int flags; 278 unsigned int num_q_vectors; 279 280 struct msix_entry *msix_entries; 281 282 /* TX */ 283 u16 tx_work_limit; 284 u32 tx_timeout_count; 285 int num_tx_queues; 286 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 287 288 /* RX */ 289 int num_rx_queues; 290 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 291 292 struct timer_list watchdog_timer; 293 struct timer_list dma_err_timer; 294 struct timer_list phy_info_timer; 295 296 u16 link_speed; 297 u16 link_duplex; 298 299 u8 port_num; 300 301 u8 __iomem *io_addr; 302 /* Interrupt Throttle Rate */ 303 u32 rx_itr_setting; 304 u32 tx_itr_setting; 305 306 struct work_struct reset_task; 307 struct work_struct watchdog_task; 308 struct work_struct dma_err_task; 309 bool fc_autoneg; 310 311 u8 tx_timeout_factor; 312 313 int msg_enable; 314 u32 max_frame_size; 315 u32 min_frame_size; 316 317 /* OS defined structs */ 318 struct pci_dev *pdev; 319 /* lock for statistics */ 320 spinlock_t stats64_lock; 321 struct rtnl_link_stats64 stats64; 322 323 /* structs defined in igc_hw.h */ 324 struct igc_hw hw; 325 struct igc_hw_stats stats; 326 327 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 328 u32 eims_enable_mask; 329 u32 eims_other; 330 331 u16 tx_ring_count; 332 u16 rx_ring_count; 333 334 u32 *shadow_vfta; 335 336 u32 rss_queues; 337 338 /* lock for RX network flow classification filter */ 339 spinlock_t nfc_lock; 340 341 struct igc_mac_addr *mac_table; 342 343 unsigned long link_check_timeout; 344 struct igc_info ei; 345 }; 346 347 /* igc_desc_unused - calculate if we have unused descriptors */ 348 static inline u16 igc_desc_unused(const struct igc_ring *ring) 349 { 350 u16 ntc = ring->next_to_clean; 351 u16 ntu = ring->next_to_use; 352 353 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 354 } 355 356 static inline s32 igc_get_phy_info(struct igc_hw *hw) 357 { 358 if (hw->phy.ops.get_phy_info) 359 return hw->phy.ops.get_phy_info(hw); 360 361 return 0; 362 } 363 364 static inline s32 igc_reset_phy(struct igc_hw *hw) 365 { 366 if (hw->phy.ops.reset) 367 return hw->phy.ops.reset(hw); 368 369 return 0; 370 } 371 372 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 373 { 374 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 375 } 376 377 enum igc_ring_flags_t { 378 IGC_RING_FLAG_RX_3K_BUFFER, 379 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 380 IGC_RING_FLAG_RX_SCTP_CSUM, 381 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 382 IGC_RING_FLAG_TX_CTX_IDX, 383 IGC_RING_FLAG_TX_DETECT_HANG 384 }; 385 386 #define ring_uses_large_buffer(ring) \ 387 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 388 389 #define ring_uses_build_skb(ring) \ 390 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 391 392 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 393 { 394 #if (PAGE_SIZE < 8192) 395 if (ring_uses_large_buffer(ring)) 396 return IGC_RXBUFFER_3072; 397 398 if (ring_uses_build_skb(ring)) 399 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 400 #endif 401 return IGC_RXBUFFER_2048; 402 } 403 404 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 405 { 406 #if (PAGE_SIZE < 8192) 407 if (ring_uses_large_buffer(ring)) 408 return 1; 409 #endif 410 return 0; 411 } 412 413 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 414 { 415 if (hw->phy.ops.read_reg) 416 return hw->phy.ops.read_reg(hw, offset, data); 417 418 return 0; 419 } 420 421 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 422 423 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 424 425 #define IGC_RX_DESC(R, i) \ 426 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 427 #define IGC_TX_DESC(R, i) \ 428 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 429 #define IGC_TX_CTXTDESC(R, i) \ 430 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 431 432 #endif /* _IGC_H_ */ 433