1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_H_ 5d89f8841SSasha Neftin #define _IGC_H_ 6d89f8841SSasha Neftin 7d89f8841SSasha Neftin #include <linux/kobject.h> 8d89f8841SSasha Neftin #include <linux/pci.h> 9d89f8841SSasha Neftin #include <linux/netdevice.h> 10d89f8841SSasha Neftin #include <linux/vmalloc.h> 11d89f8841SSasha Neftin #include <linux/ethtool.h> 12d89f8841SSasha Neftin #include <linux/sctp.h> 135f295805SVinicius Costa Gomes #include <linux/ptp_clock_kernel.h> 145f295805SVinicius Costa Gomes #include <linux/timecounter.h> 155f295805SVinicius Costa Gomes #include <linux/net_tstamp.h> 16d89f8841SSasha Neftin 17146740f9SSasha Neftin #include "igc_hw.h" 18146740f9SSasha Neftin 198c5ad0daSSasha Neftin /* forward declaration */ 208c5ad0daSSasha Neftin void igc_set_ethtool_ops(struct net_device *); 218c5ad0daSSasha Neftin 228c5ad0daSSasha Neftin struct igc_adapter; 238c5ad0daSSasha Neftin struct igc_ring; 248c5ad0daSSasha Neftin 258c5ad0daSSasha Neftin void igc_up(struct igc_adapter *adapter); 268c5ad0daSSasha Neftin void igc_down(struct igc_adapter *adapter); 278c5ad0daSSasha Neftin int igc_setup_tx_resources(struct igc_ring *ring); 288c5ad0daSSasha Neftin int igc_setup_rx_resources(struct igc_ring *ring); 298c5ad0daSSasha Neftin void igc_free_tx_resources(struct igc_ring *ring); 308c5ad0daSSasha Neftin void igc_free_rx_resources(struct igc_ring *ring); 318c5ad0daSSasha Neftin unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 328c5ad0daSSasha Neftin void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 338c5ad0daSSasha Neftin const u32 max_rss_queues); 348c5ad0daSSasha Neftin int igc_reinit_queues(struct igc_adapter *adapter); 352121c271SSasha Neftin void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 368c5ad0daSSasha Neftin bool igc_has_link(struct igc_adapter *adapter); 378c5ad0daSSasha Neftin void igc_reset(struct igc_adapter *adapter); 388c5ad0daSSasha Neftin int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 396245c848SSasha Neftin int igc_add_mac_steering_filter(struct igc_adapter *adapter, 406245c848SSasha Neftin const u8 *addr, u8 queue, u8 flags); 416245c848SSasha Neftin int igc_del_mac_steering_filter(struct igc_adapter *adapter, 426245c848SSasha Neftin const u8 *addr, u8 queue, u8 flags); 4336b9fea6SSasha Neftin void igc_update_stats(struct igc_adapter *adapter); 448c5ad0daSSasha Neftin 459c384ee3SSasha Neftin /* igc_dump declarations */ 469c384ee3SSasha Neftin void igc_rings_dump(struct igc_adapter *adapter); 479c384ee3SSasha Neftin void igc_regs_dump(struct igc_adapter *adapter); 489c384ee3SSasha Neftin 49d89f8841SSasha Neftin extern char igc_driver_name[]; 50d89f8841SSasha Neftin extern char igc_driver_version[]; 51d89f8841SSasha Neftin 528c5ad0daSSasha Neftin #define IGC_REGS_LEN 740 538c5ad0daSSasha Neftin #define IGC_RETA_SIZE 128 548c5ad0daSSasha Neftin 555f295805SVinicius Costa Gomes /* flags controlling PTP/1588 function */ 565f295805SVinicius Costa Gomes #define IGC_PTP_ENABLED BIT(0) 575f295805SVinicius Costa Gomes 583df25e4cSSasha Neftin /* Interrupt defines */ 593df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */ 603df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSI BIT(0) 618c5ad0daSSasha Neftin #define IGC_FLAG_QUEUE_PAIRS BIT(3) 628c5ad0daSSasha Neftin #define IGC_FLAG_DMAC BIT(4) 635f295805SVinicius Costa Gomes #define IGC_FLAG_PTP BIT(8) 640507ef8aSSasha Neftin #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 65208983f0SSasha Neftin #define IGC_FLAG_MEDIA_RESET BIT(10) 66208983f0SSasha Neftin #define IGC_FLAG_MAS_ENABLE BIT(12) 673df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSIX BIT(13) 680507ef8aSSasha Neftin #define IGC_FLAG_VLAN_PROMISC BIT(15) 698c5ad0daSSasha Neftin #define IGC_FLAG_RX_LEGACY BIT(16) 703df25e4cSSasha Neftin 712121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 722121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 732121c271SSasha Neftin 742121c271SSasha Neftin #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 752121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 762121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 772121c271SSasha Neftin 783df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */ 793df25e4cSSasha Neftin #define IGC_4K_ITR 980 803df25e4cSSasha Neftin #define IGC_20K_ITR 196 813df25e4cSSasha Neftin #define IGC_70K_ITR 56 823df25e4cSSasha Neftin 830507ef8aSSasha Neftin #define IGC_DEFAULT_ITR 3 /* dynamic */ 840507ef8aSSasha Neftin #define IGC_MAX_ITR_USECS 10000 850507ef8aSSasha Neftin #define IGC_MIN_ITR_USECS 10 860507ef8aSSasha Neftin #define NON_Q_VECTORS 1 870507ef8aSSasha Neftin #define MAX_MSIX_ENTRIES 10 880507ef8aSSasha Neftin 890507ef8aSSasha Neftin /* TX/RX descriptor defines */ 900507ef8aSSasha Neftin #define IGC_DEFAULT_TXD 256 910507ef8aSSasha Neftin #define IGC_DEFAULT_TX_WORK 128 920507ef8aSSasha Neftin #define IGC_MIN_TXD 80 930507ef8aSSasha Neftin #define IGC_MAX_TXD 4096 940507ef8aSSasha Neftin 950507ef8aSSasha Neftin #define IGC_DEFAULT_RXD 256 960507ef8aSSasha Neftin #define IGC_MIN_RXD 80 970507ef8aSSasha Neftin #define IGC_MAX_RXD 4096 980507ef8aSSasha Neftin 99c9a11c23SSasha Neftin /* Transmit and receive queues */ 100c9a11c23SSasha Neftin #define IGC_MAX_RX_QUEUES 4 101c9a11c23SSasha Neftin #define IGC_MAX_TX_QUEUES 4 102c9a11c23SSasha Neftin 103c9a11c23SSasha Neftin #define MAX_Q_VECTORS 8 104c9a11c23SSasha Neftin #define MAX_STD_JUMBO_FRAME_SIZE 9216 105c9a11c23SSasha Neftin 10613b5b7fdSSasha Neftin /* Supported Rx Buffer Sizes */ 10713b5b7fdSSasha Neftin #define IGC_RXBUFFER_256 256 10813b5b7fdSSasha Neftin #define IGC_RXBUFFER_2048 2048 10913b5b7fdSSasha Neftin #define IGC_RXBUFFER_3072 3072 11013b5b7fdSSasha Neftin 1118c5ad0daSSasha Neftin #define AUTO_ALL_MODES 0 11213b5b7fdSSasha Neftin #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 11313b5b7fdSSasha Neftin 11481b05520SVinicius Costa Gomes /* Transmit and receive latency (for PTP timestamps) */ 11581b05520SVinicius Costa Gomes /* FIXME: These values were estimated using the ones that i210 has as 11681b05520SVinicius Costa Gomes * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 11781b05520SVinicius Costa Gomes * need to confirm them. 11881b05520SVinicius Costa Gomes */ 11981b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_10 9542 12081b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_100 1024 12181b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_1000 178 12281b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_2500 64 12381b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_10 20662 12481b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_100 2213 12581b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_1000 448 12681b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_2500 160 12781b05520SVinicius Costa Gomes 12813b5b7fdSSasha Neftin /* RX and TX descriptor control thresholds. 12913b5b7fdSSasha Neftin * PTHRESH - MAC will consider prefetch if it has fewer than this number of 13013b5b7fdSSasha Neftin * descriptors available in its onboard memory. 13113b5b7fdSSasha Neftin * Setting this to 0 disables RX descriptor prefetch. 13213b5b7fdSSasha Neftin * HTHRESH - MAC will only prefetch if there are at least this many descriptors 13313b5b7fdSSasha Neftin * available in host memory. 13413b5b7fdSSasha Neftin * If PTHRESH is 0, this should also be 0. 13513b5b7fdSSasha Neftin * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 13613b5b7fdSSasha Neftin * descriptors until either it has this many to write back, or the 13713b5b7fdSSasha Neftin * ITR timer expires. 13813b5b7fdSSasha Neftin */ 13913b5b7fdSSasha Neftin #define IGC_RX_PTHRESH 8 14013b5b7fdSSasha Neftin #define IGC_RX_HTHRESH 8 14113b5b7fdSSasha Neftin #define IGC_TX_PTHRESH 8 14213b5b7fdSSasha Neftin #define IGC_TX_HTHRESH 1 14313b5b7fdSSasha Neftin #define IGC_RX_WTHRESH 4 14413b5b7fdSSasha Neftin #define IGC_TX_WTHRESH 16 14513b5b7fdSSasha Neftin 14613b5b7fdSSasha Neftin #define IGC_RX_DMA_ATTR \ 14713b5b7fdSSasha Neftin (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 14813b5b7fdSSasha Neftin 14913b5b7fdSSasha Neftin #define IGC_TS_HDR_LEN 16 15013b5b7fdSSasha Neftin 15113b5b7fdSSasha Neftin #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 15213b5b7fdSSasha Neftin 15313b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 15413b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB \ 15513b5b7fdSSasha Neftin (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 15613b5b7fdSSasha Neftin #else 15713b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 15813b5b7fdSSasha Neftin #endif 15913b5b7fdSSasha Neftin 1600507ef8aSSasha Neftin /* How many Rx Buffers do we bundle into one write to the hardware ? */ 1610507ef8aSSasha Neftin #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 1620507ef8aSSasha Neftin 163d3ae3cfbSSasha Neftin /* VLAN info */ 164d3ae3cfbSSasha Neftin #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 165d3ae3cfbSSasha Neftin 1660507ef8aSSasha Neftin /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 1670507ef8aSSasha Neftin static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 1680507ef8aSSasha Neftin const u32 stat_err_bits) 1690507ef8aSSasha Neftin { 1700507ef8aSSasha Neftin return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 1710507ef8aSSasha Neftin } 1720507ef8aSSasha Neftin 173c9a11c23SSasha Neftin enum igc_state_t { 174c9a11c23SSasha Neftin __IGC_TESTING, 175c9a11c23SSasha Neftin __IGC_RESETTING, 176c9a11c23SSasha Neftin __IGC_DOWN, 177c9a11c23SSasha Neftin __IGC_PTP_TX_IN_PROGRESS, 178c9a11c23SSasha Neftin }; 179c9a11c23SSasha Neftin 1800507ef8aSSasha Neftin enum igc_tx_flags { 1810507ef8aSSasha Neftin /* cmd_type flags */ 1820507ef8aSSasha Neftin IGC_TX_FLAGS_VLAN = 0x01, 1830507ef8aSSasha Neftin IGC_TX_FLAGS_TSO = 0x02, 1840507ef8aSSasha Neftin IGC_TX_FLAGS_TSTAMP = 0x04, 1850507ef8aSSasha Neftin 1860507ef8aSSasha Neftin /* olinfo flags */ 1870507ef8aSSasha Neftin IGC_TX_FLAGS_IPV4 = 0x10, 1880507ef8aSSasha Neftin IGC_TX_FLAGS_CSUM = 0x20, 1890507ef8aSSasha Neftin }; 1900507ef8aSSasha Neftin 191ab405612SSasha Neftin enum igc_boards { 192ab405612SSasha Neftin board_base, 193ab405612SSasha Neftin }; 194ab405612SSasha Neftin 1950507ef8aSSasha Neftin /* The largest size we can write to the descriptor is 65535. In order to 1960507ef8aSSasha Neftin * maintain a power of two alignment we have to limit ourselves to 32K. 1970507ef8aSSasha Neftin */ 1980507ef8aSSasha Neftin #define IGC_MAX_TXD_PWR 15 1990507ef8aSSasha Neftin #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 2000507ef8aSSasha Neftin 2010507ef8aSSasha Neftin /* Tx Descriptors needed, worst case */ 2020507ef8aSSasha Neftin #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 2030507ef8aSSasha Neftin #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 2040507ef8aSSasha Neftin 20513b5b7fdSSasha Neftin /* wrapper around a pointer to a socket buffer, 20613b5b7fdSSasha Neftin * so a DMA handle can be stored along with the buffer 20713b5b7fdSSasha Neftin */ 20813b5b7fdSSasha Neftin struct igc_tx_buffer { 20913b5b7fdSSasha Neftin union igc_adv_tx_desc *next_to_watch; 21013b5b7fdSSasha Neftin unsigned long time_stamp; 21113b5b7fdSSasha Neftin struct sk_buff *skb; 21213b5b7fdSSasha Neftin unsigned int bytecount; 21313b5b7fdSSasha Neftin u16 gso_segs; 21413b5b7fdSSasha Neftin __be16 protocol; 21513b5b7fdSSasha Neftin 21613b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_ADDR(dma); 21713b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_LEN(len); 21813b5b7fdSSasha Neftin u32 tx_flags; 21913b5b7fdSSasha Neftin }; 22013b5b7fdSSasha Neftin 22113b5b7fdSSasha Neftin struct igc_rx_buffer { 22213b5b7fdSSasha Neftin dma_addr_t dma; 22313b5b7fdSSasha Neftin struct page *page; 22413b5b7fdSSasha Neftin #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 22513b5b7fdSSasha Neftin __u32 page_offset; 22613b5b7fdSSasha Neftin #else 22713b5b7fdSSasha Neftin __u16 page_offset; 22813b5b7fdSSasha Neftin #endif 22913b5b7fdSSasha Neftin __u16 pagecnt_bias; 23013b5b7fdSSasha Neftin }; 23113b5b7fdSSasha Neftin 2323df25e4cSSasha Neftin struct igc_tx_queue_stats { 2333df25e4cSSasha Neftin u64 packets; 2343df25e4cSSasha Neftin u64 bytes; 2353df25e4cSSasha Neftin u64 restart_queue; 2360507ef8aSSasha Neftin u64 restart_queue2; 2373df25e4cSSasha Neftin }; 2383df25e4cSSasha Neftin 2393df25e4cSSasha Neftin struct igc_rx_queue_stats { 2403df25e4cSSasha Neftin u64 packets; 2413df25e4cSSasha Neftin u64 bytes; 2423df25e4cSSasha Neftin u64 drops; 2433df25e4cSSasha Neftin u64 csum_err; 2443df25e4cSSasha Neftin u64 alloc_failed; 2453df25e4cSSasha Neftin }; 2463df25e4cSSasha Neftin 2473df25e4cSSasha Neftin struct igc_rx_packet_stats { 2483df25e4cSSasha Neftin u64 ipv4_packets; /* IPv4 headers processed */ 2493df25e4cSSasha Neftin u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 2503df25e4cSSasha Neftin u64 ipv6_packets; /* IPv6 headers processed */ 2513df25e4cSSasha Neftin u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 2523df25e4cSSasha Neftin u64 tcp_packets; /* TCP headers processed */ 2533df25e4cSSasha Neftin u64 udp_packets; /* UDP headers processed */ 2543df25e4cSSasha Neftin u64 sctp_packets; /* SCTP headers processed */ 2553df25e4cSSasha Neftin u64 nfs_packets; /* NFS headers processe */ 2563df25e4cSSasha Neftin u64 other_packets; 2573df25e4cSSasha Neftin }; 2583df25e4cSSasha Neftin 2593df25e4cSSasha Neftin struct igc_ring_container { 2603df25e4cSSasha Neftin struct igc_ring *ring; /* pointer to linked list of rings */ 2613df25e4cSSasha Neftin unsigned int total_bytes; /* total bytes processed this int */ 2623df25e4cSSasha Neftin unsigned int total_packets; /* total packets processed this int */ 2633df25e4cSSasha Neftin u16 work_limit; /* total work allowed per interrupt */ 2643df25e4cSSasha Neftin u8 count; /* total number of rings in vector */ 2653df25e4cSSasha Neftin u8 itr; /* current ITR setting for ring */ 2663df25e4cSSasha Neftin }; 2673df25e4cSSasha Neftin 2683df25e4cSSasha Neftin struct igc_ring { 2693df25e4cSSasha Neftin struct igc_q_vector *q_vector; /* backlink to q_vector */ 2703df25e4cSSasha Neftin struct net_device *netdev; /* back pointer to net_device */ 2713df25e4cSSasha Neftin struct device *dev; /* device for dma mapping */ 2723df25e4cSSasha Neftin union { /* array of buffer info structs */ 2733df25e4cSSasha Neftin struct igc_tx_buffer *tx_buffer_info; 2743df25e4cSSasha Neftin struct igc_rx_buffer *rx_buffer_info; 2753df25e4cSSasha Neftin }; 2763df25e4cSSasha Neftin void *desc; /* descriptor ring memory */ 2773df25e4cSSasha Neftin unsigned long flags; /* ring specific flags */ 2783df25e4cSSasha Neftin void __iomem *tail; /* pointer to ring tail register */ 2793df25e4cSSasha Neftin dma_addr_t dma; /* phys address of the ring */ 2803df25e4cSSasha Neftin unsigned int size; /* length of desc. ring in bytes */ 2813df25e4cSSasha Neftin 2823df25e4cSSasha Neftin u16 count; /* number of desc. in the ring */ 2833df25e4cSSasha Neftin u8 queue_index; /* logical index of the ring*/ 2843df25e4cSSasha Neftin u8 reg_idx; /* physical index of the ring */ 285d3ae3cfbSSasha Neftin bool launchtime_enable; /* true if LaunchTime is enabled */ 2863df25e4cSSasha Neftin 2873df25e4cSSasha Neftin /* everything past this point are written often */ 2883df25e4cSSasha Neftin u16 next_to_clean; 2893df25e4cSSasha Neftin u16 next_to_use; 2903df25e4cSSasha Neftin u16 next_to_alloc; 2913df25e4cSSasha Neftin 2923df25e4cSSasha Neftin union { 2933df25e4cSSasha Neftin /* TX */ 2943df25e4cSSasha Neftin struct { 2953df25e4cSSasha Neftin struct igc_tx_queue_stats tx_stats; 2960507ef8aSSasha Neftin struct u64_stats_sync tx_syncp; 2970507ef8aSSasha Neftin struct u64_stats_sync tx_syncp2; 2983df25e4cSSasha Neftin }; 2993df25e4cSSasha Neftin /* RX */ 3003df25e4cSSasha Neftin struct { 3013df25e4cSSasha Neftin struct igc_rx_queue_stats rx_stats; 3023df25e4cSSasha Neftin struct igc_rx_packet_stats pkt_stats; 3030507ef8aSSasha Neftin struct u64_stats_sync rx_syncp; 3043df25e4cSSasha Neftin struct sk_buff *skb; 3053df25e4cSSasha Neftin }; 3063df25e4cSSasha Neftin }; 3073df25e4cSSasha Neftin } ____cacheline_internodealigned_in_smp; 3083df25e4cSSasha Neftin 309c9a11c23SSasha Neftin struct igc_q_vector { 310c9a11c23SSasha Neftin struct igc_adapter *adapter; /* backlink */ 3113df25e4cSSasha Neftin void __iomem *itr_register; 3123df25e4cSSasha Neftin u32 eims_value; /* EIMS mask value */ 3133df25e4cSSasha Neftin 3143df25e4cSSasha Neftin u16 itr_val; 3153df25e4cSSasha Neftin u8 set_itr; 3163df25e4cSSasha Neftin 3173df25e4cSSasha Neftin struct igc_ring_container rx, tx; 318c9a11c23SSasha Neftin 319c9a11c23SSasha Neftin struct napi_struct napi; 3203df25e4cSSasha Neftin 3213df25e4cSSasha Neftin struct rcu_head rcu; /* to avoid race with update stats on free */ 3223df25e4cSSasha Neftin char name[IFNAMSIZ + 9]; 3233df25e4cSSasha Neftin struct net_device poll_dev; 3243df25e4cSSasha Neftin 3253df25e4cSSasha Neftin /* for dynamic allocation of rings associated with this q_vector */ 3263df25e4cSSasha Neftin struct igc_ring ring[0] ____cacheline_internodealigned_in_smp; 327c9a11c23SSasha Neftin }; 328c9a11c23SSasha Neftin 3296245c848SSasha Neftin #define MAX_ETYPE_FILTER (4 - 1) 3306245c848SSasha Neftin 3316245c848SSasha Neftin enum igc_filter_match_flags { 3326245c848SSasha Neftin IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 3336245c848SSasha Neftin IGC_FILTER_FLAG_VLAN_TCI = 0x2, 3346245c848SSasha Neftin IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 3356245c848SSasha Neftin IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 3366245c848SSasha Neftin }; 3376245c848SSasha Neftin 3386245c848SSasha Neftin /* RX network flow classification data structure */ 3396245c848SSasha Neftin struct igc_nfc_input { 3406245c848SSasha Neftin /* Byte layout in order, all values with MSB first: 3416245c848SSasha Neftin * match_flags - 1 byte 3426245c848SSasha Neftin * etype - 2 bytes 3436245c848SSasha Neftin * vlan_tci - 2 bytes 3446245c848SSasha Neftin */ 3456245c848SSasha Neftin u8 match_flags; 3466245c848SSasha Neftin __be16 etype; 3476245c848SSasha Neftin __be16 vlan_tci; 3486245c848SSasha Neftin u8 src_addr[ETH_ALEN]; 3496245c848SSasha Neftin u8 dst_addr[ETH_ALEN]; 3506245c848SSasha Neftin }; 3516245c848SSasha Neftin 3526245c848SSasha Neftin struct igc_nfc_filter { 3536245c848SSasha Neftin struct hlist_node nfc_node; 3546245c848SSasha Neftin struct igc_nfc_input filter; 3556245c848SSasha Neftin unsigned long cookie; 3566245c848SSasha Neftin u16 etype_reg_index; 3576245c848SSasha Neftin u16 sw_idx; 3586245c848SSasha Neftin u16 action; 3596245c848SSasha Neftin }; 3606245c848SSasha Neftin 361c9a11c23SSasha Neftin struct igc_mac_addr { 362c9a11c23SSasha Neftin u8 addr[ETH_ALEN]; 363c9a11c23SSasha Neftin u8 queue; 364c9a11c23SSasha Neftin u8 state; /* bitmask */ 365c9a11c23SSasha Neftin }; 366c9a11c23SSasha Neftin 367c9a11c23SSasha Neftin #define IGC_MAC_STATE_DEFAULT 0x1 3686245c848SSasha Neftin #define IGC_MAC_STATE_IN_USE 0x2 3696245c848SSasha Neftin #define IGC_MAC_STATE_SRC_ADDR 0x4 3706245c848SSasha Neftin #define IGC_MAC_STATE_QUEUE_STEERING 0x8 3716245c848SSasha Neftin 3726245c848SSasha Neftin #define IGC_MAX_RXNFC_FILTERS 16 373c9a11c23SSasha Neftin 374146740f9SSasha Neftin /* Board specific private data structure */ 375146740f9SSasha Neftin struct igc_adapter { 376c9a11c23SSasha Neftin struct net_device *netdev; 377c9a11c23SSasha Neftin 378c9a11c23SSasha Neftin unsigned long state; 379c9a11c23SSasha Neftin unsigned int flags; 380c9a11c23SSasha Neftin unsigned int num_q_vectors; 3813df25e4cSSasha Neftin 3823df25e4cSSasha Neftin struct msix_entry *msix_entries; 3833df25e4cSSasha Neftin 3843df25e4cSSasha Neftin /* TX */ 3853df25e4cSSasha Neftin u16 tx_work_limit; 386208983f0SSasha Neftin u32 tx_timeout_count; 3873df25e4cSSasha Neftin int num_tx_queues; 3883df25e4cSSasha Neftin struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 3893df25e4cSSasha Neftin 3903df25e4cSSasha Neftin /* RX */ 3913df25e4cSSasha Neftin int num_rx_queues; 3923df25e4cSSasha Neftin struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 3933df25e4cSSasha Neftin 3943df25e4cSSasha Neftin struct timer_list watchdog_timer; 3953df25e4cSSasha Neftin struct timer_list dma_err_timer; 3963df25e4cSSasha Neftin struct timer_list phy_info_timer; 3973df25e4cSSasha Neftin 3989513d2a5SSasha Neftin u32 wol; 3999513d2a5SSasha Neftin u32 en_mng_pt; 400c9a11c23SSasha Neftin u16 link_speed; 401c9a11c23SSasha Neftin u16 link_duplex; 402c9a11c23SSasha Neftin 403c9a11c23SSasha Neftin u8 port_num; 404c9a11c23SSasha Neftin 405146740f9SSasha Neftin u8 __iomem *io_addr; 4063df25e4cSSasha Neftin /* Interrupt Throttle Rate */ 4073df25e4cSSasha Neftin u32 rx_itr_setting; 4083df25e4cSSasha Neftin u32 tx_itr_setting; 4093df25e4cSSasha Neftin 4103df25e4cSSasha Neftin struct work_struct reset_task; 411c9a11c23SSasha Neftin struct work_struct watchdog_task; 4123df25e4cSSasha Neftin struct work_struct dma_err_task; 4134eb80801SSasha Neftin bool fc_autoneg; 414c9a11c23SSasha Neftin 4150507ef8aSSasha Neftin u8 tx_timeout_factor; 4160507ef8aSSasha Neftin 417c9a11c23SSasha Neftin int msg_enable; 418c9a11c23SSasha Neftin u32 max_frame_size; 4190507ef8aSSasha Neftin u32 min_frame_size; 420146740f9SSasha Neftin 421146740f9SSasha Neftin /* OS defined structs */ 422146740f9SSasha Neftin struct pci_dev *pdev; 4230507ef8aSSasha Neftin /* lock for statistics */ 4240507ef8aSSasha Neftin spinlock_t stats64_lock; 4250507ef8aSSasha Neftin struct rtnl_link_stats64 stats64; 426146740f9SSasha Neftin 427146740f9SSasha Neftin /* structs defined in igc_hw.h */ 428146740f9SSasha Neftin struct igc_hw hw; 4293df25e4cSSasha Neftin struct igc_hw_stats stats; 430c9a11c23SSasha Neftin 431c9a11c23SSasha Neftin struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 4323df25e4cSSasha Neftin u32 eims_enable_mask; 4333df25e4cSSasha Neftin u32 eims_other; 4343df25e4cSSasha Neftin 4353df25e4cSSasha Neftin u16 tx_ring_count; 4363df25e4cSSasha Neftin u16 rx_ring_count; 4373df25e4cSSasha Neftin 43836b9fea6SSasha Neftin u32 tx_hwtstamp_timeouts; 43936b9fea6SSasha Neftin u32 tx_hwtstamp_skipped; 44036b9fea6SSasha Neftin u32 rx_hwtstamp_cleared; 4410507ef8aSSasha Neftin 4423df25e4cSSasha Neftin u32 rss_queues; 4432121c271SSasha Neftin u32 rss_indir_tbl_init; 444c9a11c23SSasha Neftin 4456245c848SSasha Neftin /* RX network flow classification support */ 4466245c848SSasha Neftin struct hlist_head nfc_filter_list; 4476245c848SSasha Neftin struct hlist_head cls_flower_list; 4486245c848SSasha Neftin unsigned int nfc_filter_count; 4496245c848SSasha Neftin 4500507ef8aSSasha Neftin /* lock for RX network flow classification filter */ 4510507ef8aSSasha Neftin spinlock_t nfc_lock; 4526245c848SSasha Neftin bool etype_bitmap[MAX_ETYPE_FILTER]; 4530507ef8aSSasha Neftin 454c9a11c23SSasha Neftin struct igc_mac_addr *mac_table; 455ab405612SSasha Neftin 4568c5ad0daSSasha Neftin u8 rss_indir_tbl[IGC_RETA_SIZE]; 4578c5ad0daSSasha Neftin 458208983f0SSasha Neftin unsigned long link_check_timeout; 459ab405612SSasha Neftin struct igc_info ei; 4605f295805SVinicius Costa Gomes 4615f295805SVinicius Costa Gomes struct ptp_clock *ptp_clock; 4625f295805SVinicius Costa Gomes struct ptp_clock_info ptp_caps; 4635f295805SVinicius Costa Gomes struct work_struct ptp_tx_work; 4645f295805SVinicius Costa Gomes struct sk_buff *ptp_tx_skb; 4655f295805SVinicius Costa Gomes struct hwtstamp_config tstamp_config; 4665f295805SVinicius Costa Gomes unsigned long ptp_tx_start; 4675f295805SVinicius Costa Gomes unsigned long last_rx_ptp_check; 4685f295805SVinicius Costa Gomes unsigned long last_rx_timestamp; 4695f295805SVinicius Costa Gomes unsigned int ptp_flags; 4705f295805SVinicius Costa Gomes /* System time value lock */ 4715f295805SVinicius Costa Gomes spinlock_t tmreg_lock; 4725f295805SVinicius Costa Gomes struct cyclecounter cc; 4735f295805SVinicius Costa Gomes struct timecounter tc; 474146740f9SSasha Neftin }; 475146740f9SSasha Neftin 47613b5b7fdSSasha Neftin /* igc_desc_unused - calculate if we have unused descriptors */ 47713b5b7fdSSasha Neftin static inline u16 igc_desc_unused(const struct igc_ring *ring) 47813b5b7fdSSasha Neftin { 47913b5b7fdSSasha Neftin u16 ntc = ring->next_to_clean; 48013b5b7fdSSasha Neftin u16 ntu = ring->next_to_use; 48113b5b7fdSSasha Neftin 48213b5b7fdSSasha Neftin return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 48313b5b7fdSSasha Neftin } 48413b5b7fdSSasha Neftin 4855586838fSSasha Neftin static inline s32 igc_get_phy_info(struct igc_hw *hw) 4865586838fSSasha Neftin { 4875586838fSSasha Neftin if (hw->phy.ops.get_phy_info) 4885586838fSSasha Neftin return hw->phy.ops.get_phy_info(hw); 4895586838fSSasha Neftin 4905586838fSSasha Neftin return 0; 4915586838fSSasha Neftin } 4925586838fSSasha Neftin 4935586838fSSasha Neftin static inline s32 igc_reset_phy(struct igc_hw *hw) 4945586838fSSasha Neftin { 4955586838fSSasha Neftin if (hw->phy.ops.reset) 4965586838fSSasha Neftin return hw->phy.ops.reset(hw); 4975586838fSSasha Neftin 4985586838fSSasha Neftin return 0; 4995586838fSSasha Neftin } 5005586838fSSasha Neftin 50113b5b7fdSSasha Neftin static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 50213b5b7fdSSasha Neftin { 50313b5b7fdSSasha Neftin return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 50413b5b7fdSSasha Neftin } 50513b5b7fdSSasha Neftin 50613b5b7fdSSasha Neftin enum igc_ring_flags_t { 50713b5b7fdSSasha Neftin IGC_RING_FLAG_RX_3K_BUFFER, 50813b5b7fdSSasha Neftin IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 50913b5b7fdSSasha Neftin IGC_RING_FLAG_RX_SCTP_CSUM, 51013b5b7fdSSasha Neftin IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 51113b5b7fdSSasha Neftin IGC_RING_FLAG_TX_CTX_IDX, 51213b5b7fdSSasha Neftin IGC_RING_FLAG_TX_DETECT_HANG 51313b5b7fdSSasha Neftin }; 51413b5b7fdSSasha Neftin 51513b5b7fdSSasha Neftin #define ring_uses_large_buffer(ring) \ 51613b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 51713b5b7fdSSasha Neftin 51813b5b7fdSSasha Neftin #define ring_uses_build_skb(ring) \ 51913b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 52013b5b7fdSSasha Neftin 52113b5b7fdSSasha Neftin static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 52213b5b7fdSSasha Neftin { 52313b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 52413b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 52513b5b7fdSSasha Neftin return IGC_RXBUFFER_3072; 52613b5b7fdSSasha Neftin 52713b5b7fdSSasha Neftin if (ring_uses_build_skb(ring)) 52813b5b7fdSSasha Neftin return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 52913b5b7fdSSasha Neftin #endif 53013b5b7fdSSasha Neftin return IGC_RXBUFFER_2048; 53113b5b7fdSSasha Neftin } 53213b5b7fdSSasha Neftin 53313b5b7fdSSasha Neftin static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 53413b5b7fdSSasha Neftin { 53513b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 53613b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 53713b5b7fdSSasha Neftin return 1; 53813b5b7fdSSasha Neftin #endif 53913b5b7fdSSasha Neftin return 0; 54013b5b7fdSSasha Neftin } 54113b5b7fdSSasha Neftin 542208983f0SSasha Neftin static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 543208983f0SSasha Neftin { 544208983f0SSasha Neftin if (hw->phy.ops.read_reg) 545208983f0SSasha Neftin return hw->phy.ops.read_reg(hw, offset, data); 546208983f0SSasha Neftin 547208983f0SSasha Neftin return 0; 548208983f0SSasha Neftin } 549208983f0SSasha Neftin 5508c5ad0daSSasha Neftin /* forward declaration */ 5518c5ad0daSSasha Neftin void igc_reinit_locked(struct igc_adapter *); 5526245c848SSasha Neftin int igc_add_filter(struct igc_adapter *adapter, 5536245c848SSasha Neftin struct igc_nfc_filter *input); 5546245c848SSasha Neftin int igc_erase_filter(struct igc_adapter *adapter, 5556245c848SSasha Neftin struct igc_nfc_filter *input); 5568c5ad0daSSasha Neftin 5575f295805SVinicius Costa Gomes void igc_ptp_init(struct igc_adapter *adapter); 5585f295805SVinicius Costa Gomes void igc_ptp_reset(struct igc_adapter *adapter); 5595f295805SVinicius Costa Gomes void igc_ptp_stop(struct igc_adapter *adapter); 56081b05520SVinicius Costa Gomes void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 56181b05520SVinicius Costa Gomes void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 56281b05520SVinicius Costa Gomes struct sk_buff *skb); 5635f295805SVinicius Costa Gomes int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 5645f295805SVinicius Costa Gomes int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 5652c344ae2SVinicius Costa Gomes void igc_ptp_tx_hang(struct igc_adapter *adapter); 5662c344ae2SVinicius Costa Gomes 56713b5b7fdSSasha Neftin #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 56813b5b7fdSSasha Neftin 5690507ef8aSSasha Neftin #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 5700507ef8aSSasha Neftin 57113b5b7fdSSasha Neftin #define IGC_RX_DESC(R, i) \ 57213b5b7fdSSasha Neftin (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 57313b5b7fdSSasha Neftin #define IGC_TX_DESC(R, i) \ 57413b5b7fdSSasha Neftin (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 57513b5b7fdSSasha Neftin #define IGC_TX_CTXTDESC(R, i) \ 57613b5b7fdSSasha Neftin (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 57713b5b7fdSSasha Neftin 578d89f8841SSasha Neftin #endif /* _IGC_H_ */ 579