1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_H_ 5d89f8841SSasha Neftin #define _IGC_H_ 6d89f8841SSasha Neftin 7d89f8841SSasha Neftin #include <linux/kobject.h> 8d89f8841SSasha Neftin #include <linux/pci.h> 9d89f8841SSasha Neftin #include <linux/netdevice.h> 10d89f8841SSasha Neftin #include <linux/vmalloc.h> 11d89f8841SSasha Neftin #include <linux/ethtool.h> 12d89f8841SSasha Neftin #include <linux/sctp.h> 135f295805SVinicius Costa Gomes #include <linux/ptp_clock_kernel.h> 145f295805SVinicius Costa Gomes #include <linux/timecounter.h> 155f295805SVinicius Costa Gomes #include <linux/net_tstamp.h> 16d89f8841SSasha Neftin 17146740f9SSasha Neftin #include "igc_hw.h" 18146740f9SSasha Neftin 197df76bd1SAndre Guedes void igc_ethtool_set_ops(struct net_device *); 208c5ad0daSSasha Neftin 2189d35511SSasha Neftin /* Transmit and receive queues */ 2289d35511SSasha Neftin #define IGC_MAX_RX_QUEUES 4 2389d35511SSasha Neftin #define IGC_MAX_TX_QUEUES 4 2489d35511SSasha Neftin 2589d35511SSasha Neftin #define MAX_Q_VECTORS 8 2689d35511SSasha Neftin #define MAX_STD_JUMBO_FRAME_SIZE 9216 2789d35511SSasha Neftin 28b4d48d96SAndre Guedes #define MAX_ETYPE_FILTER 8 2989d35511SSasha Neftin #define IGC_RETA_SIZE 128 3089d35511SSasha Neftin 3187938851SEderson de Souza /* SDP support */ 3287938851SEderson de Souza #define IGC_N_EXTTS 2 3387938851SEderson de Souza #define IGC_N_PEROUT 2 3487938851SEderson de Souza #define IGC_N_SDP 4 3587938851SEderson de Souza 36750433d0SAndre Guedes enum igc_mac_filter_type { 37750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_DST = 0, 38750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_SRC 39750433d0SAndre Guedes }; 40750433d0SAndre Guedes 4189d35511SSasha Neftin struct igc_tx_queue_stats { 4289d35511SSasha Neftin u64 packets; 4389d35511SSasha Neftin u64 bytes; 4489d35511SSasha Neftin u64 restart_queue; 4589d35511SSasha Neftin u64 restart_queue2; 4689d35511SSasha Neftin }; 4789d35511SSasha Neftin 4889d35511SSasha Neftin struct igc_rx_queue_stats { 4989d35511SSasha Neftin u64 packets; 5089d35511SSasha Neftin u64 bytes; 5189d35511SSasha Neftin u64 drops; 5289d35511SSasha Neftin u64 csum_err; 5389d35511SSasha Neftin u64 alloc_failed; 5489d35511SSasha Neftin }; 5589d35511SSasha Neftin 5689d35511SSasha Neftin struct igc_rx_packet_stats { 5789d35511SSasha Neftin u64 ipv4_packets; /* IPv4 headers processed */ 5889d35511SSasha Neftin u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 5989d35511SSasha Neftin u64 ipv6_packets; /* IPv6 headers processed */ 6089d35511SSasha Neftin u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 6189d35511SSasha Neftin u64 tcp_packets; /* TCP headers processed */ 6289d35511SSasha Neftin u64 udp_packets; /* UDP headers processed */ 6389d35511SSasha Neftin u64 sctp_packets; /* SCTP headers processed */ 6489d35511SSasha Neftin u64 nfs_packets; /* NFS headers processe */ 6589d35511SSasha Neftin u64 other_packets; 6689d35511SSasha Neftin }; 6789d35511SSasha Neftin 6889d35511SSasha Neftin struct igc_ring_container { 6989d35511SSasha Neftin struct igc_ring *ring; /* pointer to linked list of rings */ 7089d35511SSasha Neftin unsigned int total_bytes; /* total bytes processed this int */ 7189d35511SSasha Neftin unsigned int total_packets; /* total packets processed this int */ 7289d35511SSasha Neftin u16 work_limit; /* total work allowed per interrupt */ 7389d35511SSasha Neftin u8 count; /* total number of rings in vector */ 7489d35511SSasha Neftin u8 itr; /* current ITR setting for ring */ 7589d35511SSasha Neftin }; 7689d35511SSasha Neftin 7789d35511SSasha Neftin struct igc_ring { 7889d35511SSasha Neftin struct igc_q_vector *q_vector; /* backlink to q_vector */ 7989d35511SSasha Neftin struct net_device *netdev; /* back pointer to net_device */ 8089d35511SSasha Neftin struct device *dev; /* device for dma mapping */ 8189d35511SSasha Neftin union { /* array of buffer info structs */ 8289d35511SSasha Neftin struct igc_tx_buffer *tx_buffer_info; 8389d35511SSasha Neftin struct igc_rx_buffer *rx_buffer_info; 8489d35511SSasha Neftin }; 8589d35511SSasha Neftin void *desc; /* descriptor ring memory */ 8689d35511SSasha Neftin unsigned long flags; /* ring specific flags */ 8789d35511SSasha Neftin void __iomem *tail; /* pointer to ring tail register */ 8889d35511SSasha Neftin dma_addr_t dma; /* phys address of the ring */ 8989d35511SSasha Neftin unsigned int size; /* length of desc. ring in bytes */ 9089d35511SSasha Neftin 9189d35511SSasha Neftin u16 count; /* number of desc. in the ring */ 9289d35511SSasha Neftin u8 queue_index; /* logical index of the ring*/ 9389d35511SSasha Neftin u8 reg_idx; /* physical index of the ring */ 9489d35511SSasha Neftin bool launchtime_enable; /* true if LaunchTime is enabled */ 9589d35511SSasha Neftin 9689d35511SSasha Neftin u32 start_time; 9789d35511SSasha Neftin u32 end_time; 9889d35511SSasha Neftin 9989d35511SSasha Neftin /* everything past this point are written often */ 10089d35511SSasha Neftin u16 next_to_clean; 10189d35511SSasha Neftin u16 next_to_use; 10289d35511SSasha Neftin u16 next_to_alloc; 10389d35511SSasha Neftin 10489d35511SSasha Neftin union { 10589d35511SSasha Neftin /* TX */ 10689d35511SSasha Neftin struct { 10789d35511SSasha Neftin struct igc_tx_queue_stats tx_stats; 10889d35511SSasha Neftin struct u64_stats_sync tx_syncp; 10989d35511SSasha Neftin struct u64_stats_sync tx_syncp2; 11089d35511SSasha Neftin }; 11189d35511SSasha Neftin /* RX */ 11289d35511SSasha Neftin struct { 11389d35511SSasha Neftin struct igc_rx_queue_stats rx_stats; 11489d35511SSasha Neftin struct igc_rx_packet_stats pkt_stats; 11589d35511SSasha Neftin struct u64_stats_sync rx_syncp; 11689d35511SSasha Neftin struct sk_buff *skb; 11789d35511SSasha Neftin }; 11889d35511SSasha Neftin }; 11973f1071cSAndre Guedes 12073f1071cSAndre Guedes struct xdp_rxq_info xdp_rxq; 121fc9df2a0SAndre Guedes struct xsk_buff_pool *xsk_pool; 12289d35511SSasha Neftin } ____cacheline_internodealigned_in_smp; 12389d35511SSasha Neftin 12489d35511SSasha Neftin /* Board specific private data structure */ 12589d35511SSasha Neftin struct igc_adapter { 12689d35511SSasha Neftin struct net_device *netdev; 12789d35511SSasha Neftin 12893ec439aSSasha Neftin struct ethtool_eee eee; 12993ec439aSSasha Neftin u16 eee_advert; 13093ec439aSSasha Neftin 13189d35511SSasha Neftin unsigned long state; 13289d35511SSasha Neftin unsigned int flags; 13389d35511SSasha Neftin unsigned int num_q_vectors; 13489d35511SSasha Neftin 13589d35511SSasha Neftin struct msix_entry *msix_entries; 13689d35511SSasha Neftin 13789d35511SSasha Neftin /* TX */ 13889d35511SSasha Neftin u16 tx_work_limit; 13989d35511SSasha Neftin u32 tx_timeout_count; 14089d35511SSasha Neftin int num_tx_queues; 14189d35511SSasha Neftin struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 14289d35511SSasha Neftin 14389d35511SSasha Neftin /* RX */ 14489d35511SSasha Neftin int num_rx_queues; 14589d35511SSasha Neftin struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 14689d35511SSasha Neftin 14789d35511SSasha Neftin struct timer_list watchdog_timer; 14889d35511SSasha Neftin struct timer_list dma_err_timer; 14989d35511SSasha Neftin struct timer_list phy_info_timer; 15089d35511SSasha Neftin 15189d35511SSasha Neftin u32 wol; 15289d35511SSasha Neftin u32 en_mng_pt; 15389d35511SSasha Neftin u16 link_speed; 15489d35511SSasha Neftin u16 link_duplex; 15589d35511SSasha Neftin 15689d35511SSasha Neftin u8 port_num; 15789d35511SSasha Neftin 15889d35511SSasha Neftin u8 __iomem *io_addr; 15989d35511SSasha Neftin /* Interrupt Throttle Rate */ 16089d35511SSasha Neftin u32 rx_itr_setting; 16189d35511SSasha Neftin u32 tx_itr_setting; 16289d35511SSasha Neftin 16389d35511SSasha Neftin struct work_struct reset_task; 16489d35511SSasha Neftin struct work_struct watchdog_task; 16589d35511SSasha Neftin struct work_struct dma_err_task; 16689d35511SSasha Neftin bool fc_autoneg; 16789d35511SSasha Neftin 16889d35511SSasha Neftin u8 tx_timeout_factor; 16989d35511SSasha Neftin 17089d35511SSasha Neftin int msg_enable; 17189d35511SSasha Neftin u32 max_frame_size; 17289d35511SSasha Neftin u32 min_frame_size; 17389d35511SSasha Neftin 17489d35511SSasha Neftin ktime_t base_time; 17589d35511SSasha Neftin ktime_t cycle_time; 17689d35511SSasha Neftin 17789d35511SSasha Neftin /* OS defined structs */ 17889d35511SSasha Neftin struct pci_dev *pdev; 17989d35511SSasha Neftin /* lock for statistics */ 18089d35511SSasha Neftin spinlock_t stats64_lock; 18189d35511SSasha Neftin struct rtnl_link_stats64 stats64; 18289d35511SSasha Neftin 18389d35511SSasha Neftin /* structs defined in igc_hw.h */ 18489d35511SSasha Neftin struct igc_hw hw; 18589d35511SSasha Neftin struct igc_hw_stats stats; 18689d35511SSasha Neftin 18789d35511SSasha Neftin struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 18889d35511SSasha Neftin u32 eims_enable_mask; 18989d35511SSasha Neftin u32 eims_other; 19089d35511SSasha Neftin 19189d35511SSasha Neftin u16 tx_ring_count; 19289d35511SSasha Neftin u16 rx_ring_count; 19389d35511SSasha Neftin 19489d35511SSasha Neftin u32 tx_hwtstamp_timeouts; 19589d35511SSasha Neftin u32 tx_hwtstamp_skipped; 19689d35511SSasha Neftin u32 rx_hwtstamp_cleared; 19789d35511SSasha Neftin 19889d35511SSasha Neftin u32 rss_queues; 19989d35511SSasha Neftin u32 rss_indir_tbl_init; 20089d35511SSasha Neftin 20197700bc8SAndre Guedes /* Any access to elements in nfc_rule_list is protected by the 20297700bc8SAndre Guedes * nfc_rule_lock. 20397700bc8SAndre Guedes */ 20442fc5dc0SAndre Guedes struct mutex nfc_rule_lock; 205d957c601SAndre Guedes struct list_head nfc_rule_list; 20697700bc8SAndre Guedes unsigned int nfc_rule_count; 20789d35511SSasha Neftin 20889d35511SSasha Neftin u8 rss_indir_tbl[IGC_RETA_SIZE]; 20989d35511SSasha Neftin 21089d35511SSasha Neftin unsigned long link_check_timeout; 21189d35511SSasha Neftin struct igc_info ei; 21289d35511SSasha Neftin 213f026d8caSVitaly Lifshits u32 test_icr; 214f026d8caSVitaly Lifshits 21589d35511SSasha Neftin struct ptp_clock *ptp_clock; 21689d35511SSasha Neftin struct ptp_clock_info ptp_caps; 21789d35511SSasha Neftin struct work_struct ptp_tx_work; 21889d35511SSasha Neftin struct sk_buff *ptp_tx_skb; 21989d35511SSasha Neftin struct hwtstamp_config tstamp_config; 22089d35511SSasha Neftin unsigned long ptp_tx_start; 22189d35511SSasha Neftin unsigned int ptp_flags; 22289d35511SSasha Neftin /* System time value lock */ 22389d35511SSasha Neftin spinlock_t tmreg_lock; 22489d35511SSasha Neftin struct cyclecounter cc; 22589d35511SSasha Neftin struct timecounter tc; 226b03c49cdSVinicius Costa Gomes struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 227b03c49cdSVinicius Costa Gomes ktime_t ptp_reset_start; /* Reset time in clock mono */ 22801bb6129SSasha Neftin 22994f794d1SSasha Neftin char fw_version[32]; 23026575105SAndre Guedes 23126575105SAndre Guedes struct bpf_prog *xdp_prog; 23264433e5bSEderson de Souza 23364433e5bSEderson de Souza bool pps_sys_wrap_on; 23487938851SEderson de Souza 23587938851SEderson de Souza struct ptp_pin_desc sdp_config[IGC_N_SDP]; 23687938851SEderson de Souza struct { 23787938851SEderson de Souza struct timespec64 start; 23887938851SEderson de Souza struct timespec64 period; 23987938851SEderson de Souza } perout[IGC_N_PEROUT]; 24089d35511SSasha Neftin }; 2418c5ad0daSSasha Neftin 2428c5ad0daSSasha Neftin void igc_up(struct igc_adapter *adapter); 2438c5ad0daSSasha Neftin void igc_down(struct igc_adapter *adapter); 244f026d8caSVitaly Lifshits int igc_open(struct net_device *netdev); 245f026d8caSVitaly Lifshits int igc_close(struct net_device *netdev); 2468c5ad0daSSasha Neftin int igc_setup_tx_resources(struct igc_ring *ring); 2478c5ad0daSSasha Neftin int igc_setup_rx_resources(struct igc_ring *ring); 2488c5ad0daSSasha Neftin void igc_free_tx_resources(struct igc_ring *ring); 2498c5ad0daSSasha Neftin void igc_free_rx_resources(struct igc_ring *ring); 2508c5ad0daSSasha Neftin unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 2518c5ad0daSSasha Neftin void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 2528c5ad0daSSasha Neftin const u32 max_rss_queues); 2538c5ad0daSSasha Neftin int igc_reinit_queues(struct igc_adapter *adapter); 2542121c271SSasha Neftin void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 2558c5ad0daSSasha Neftin bool igc_has_link(struct igc_adapter *adapter); 2568c5ad0daSSasha Neftin void igc_reset(struct igc_adapter *adapter); 2578c5ad0daSSasha Neftin int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 25836b9fea6SSasha Neftin void igc_update_stats(struct igc_adapter *adapter); 259fc9df2a0SAndre Guedes void igc_disable_rx_ring(struct igc_ring *ring); 260fc9df2a0SAndre Guedes void igc_enable_rx_ring(struct igc_ring *ring); 2619acf59a7SAndre Guedes void igc_disable_tx_ring(struct igc_ring *ring); 2629acf59a7SAndre Guedes void igc_enable_tx_ring(struct igc_ring *ring); 263fc9df2a0SAndre Guedes int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 2648c5ad0daSSasha Neftin 2659c384ee3SSasha Neftin /* igc_dump declarations */ 2669c384ee3SSasha Neftin void igc_rings_dump(struct igc_adapter *adapter); 2679c384ee3SSasha Neftin void igc_regs_dump(struct igc_adapter *adapter); 2689c384ee3SSasha Neftin 269d89f8841SSasha Neftin extern char igc_driver_name[]; 270d89f8841SSasha Neftin 2718c5ad0daSSasha Neftin #define IGC_REGS_LEN 740 2728c5ad0daSSasha Neftin 2735f295805SVinicius Costa Gomes /* flags controlling PTP/1588 function */ 2745f295805SVinicius Costa Gomes #define IGC_PTP_ENABLED BIT(0) 2755f295805SVinicius Costa Gomes 27667082b53SSasha Neftin /* Flags definitions */ 2773df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSI BIT(0) 2788c5ad0daSSasha Neftin #define IGC_FLAG_QUEUE_PAIRS BIT(3) 2798c5ad0daSSasha Neftin #define IGC_FLAG_DMAC BIT(4) 2805f295805SVinicius Costa Gomes #define IGC_FLAG_PTP BIT(8) 281e055600dSSasha Neftin #define IGC_FLAG_WOL_SUPPORTED BIT(8) 2820507ef8aSSasha Neftin #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 283208983f0SSasha Neftin #define IGC_FLAG_MEDIA_RESET BIT(10) 284208983f0SSasha Neftin #define IGC_FLAG_MAS_ENABLE BIT(12) 2853df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSIX BIT(13) 28693ec439aSSasha Neftin #define IGC_FLAG_EEE BIT(14) 2870507ef8aSSasha Neftin #define IGC_FLAG_VLAN_PROMISC BIT(15) 2888c5ad0daSSasha Neftin #define IGC_FLAG_RX_LEGACY BIT(16) 289ec50a9d4SVinicius Costa Gomes #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 2903df25e4cSSasha Neftin 2912121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 2922121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 2932121c271SSasha Neftin 2942121c271SSasha Neftin #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 2952121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2962121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2972121c271SSasha Neftin 29864900e8fSSasha Neftin /* Interrupt defines */ 2993df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */ 3003df25e4cSSasha Neftin #define IGC_4K_ITR 980 3013df25e4cSSasha Neftin #define IGC_20K_ITR 196 3023df25e4cSSasha Neftin #define IGC_70K_ITR 56 3033df25e4cSSasha Neftin 3040507ef8aSSasha Neftin #define IGC_DEFAULT_ITR 3 /* dynamic */ 3050507ef8aSSasha Neftin #define IGC_MAX_ITR_USECS 10000 3060507ef8aSSasha Neftin #define IGC_MIN_ITR_USECS 10 3070507ef8aSSasha Neftin #define NON_Q_VECTORS 1 3080507ef8aSSasha Neftin #define MAX_MSIX_ENTRIES 10 3090507ef8aSSasha Neftin 3100507ef8aSSasha Neftin /* TX/RX descriptor defines */ 3110507ef8aSSasha Neftin #define IGC_DEFAULT_TXD 256 3120507ef8aSSasha Neftin #define IGC_DEFAULT_TX_WORK 128 3130507ef8aSSasha Neftin #define IGC_MIN_TXD 80 3140507ef8aSSasha Neftin #define IGC_MAX_TXD 4096 3150507ef8aSSasha Neftin 3160507ef8aSSasha Neftin #define IGC_DEFAULT_RXD 256 3170507ef8aSSasha Neftin #define IGC_MIN_RXD 80 3180507ef8aSSasha Neftin #define IGC_MAX_RXD 4096 3190507ef8aSSasha Neftin 32013b5b7fdSSasha Neftin /* Supported Rx Buffer Sizes */ 32113b5b7fdSSasha Neftin #define IGC_RXBUFFER_256 256 32213b5b7fdSSasha Neftin #define IGC_RXBUFFER_2048 2048 32313b5b7fdSSasha Neftin #define IGC_RXBUFFER_3072 3072 32413b5b7fdSSasha Neftin 3258c5ad0daSSasha Neftin #define AUTO_ALL_MODES 0 32613b5b7fdSSasha Neftin #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 32713b5b7fdSSasha Neftin 32881b05520SVinicius Costa Gomes /* Transmit and receive latency (for PTP timestamps) */ 329f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_10 240 330f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_100 58 331f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_1000 80 332f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_2500 1325 333f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_10 6450 334f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_100 185 335f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_1000 300 336f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_2500 1485 33781b05520SVinicius Costa Gomes 33813b5b7fdSSasha Neftin /* RX and TX descriptor control thresholds. 33913b5b7fdSSasha Neftin * PTHRESH - MAC will consider prefetch if it has fewer than this number of 34013b5b7fdSSasha Neftin * descriptors available in its onboard memory. 34113b5b7fdSSasha Neftin * Setting this to 0 disables RX descriptor prefetch. 34213b5b7fdSSasha Neftin * HTHRESH - MAC will only prefetch if there are at least this many descriptors 34313b5b7fdSSasha Neftin * available in host memory. 34413b5b7fdSSasha Neftin * If PTHRESH is 0, this should also be 0. 34513b5b7fdSSasha Neftin * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 34613b5b7fdSSasha Neftin * descriptors until either it has this many to write back, or the 34713b5b7fdSSasha Neftin * ITR timer expires. 34813b5b7fdSSasha Neftin */ 34913b5b7fdSSasha Neftin #define IGC_RX_PTHRESH 8 35013b5b7fdSSasha Neftin #define IGC_RX_HTHRESH 8 35113b5b7fdSSasha Neftin #define IGC_TX_PTHRESH 8 35213b5b7fdSSasha Neftin #define IGC_TX_HTHRESH 1 35313b5b7fdSSasha Neftin #define IGC_RX_WTHRESH 4 35413b5b7fdSSasha Neftin #define IGC_TX_WTHRESH 16 35513b5b7fdSSasha Neftin 35613b5b7fdSSasha Neftin #define IGC_RX_DMA_ATTR \ 35713b5b7fdSSasha Neftin (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 35813b5b7fdSSasha Neftin 35913b5b7fdSSasha Neftin #define IGC_TS_HDR_LEN 16 36013b5b7fdSSasha Neftin 36113b5b7fdSSasha Neftin #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 36213b5b7fdSSasha Neftin 36313b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 36413b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB \ 36513b5b7fdSSasha Neftin (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 36613b5b7fdSSasha Neftin #else 36713b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 36813b5b7fdSSasha Neftin #endif 36913b5b7fdSSasha Neftin 3700507ef8aSSasha Neftin /* How many Rx Buffers do we bundle into one write to the hardware ? */ 3710507ef8aSSasha Neftin #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 3720507ef8aSSasha Neftin 373d3ae3cfbSSasha Neftin /* VLAN info */ 374d3ae3cfbSSasha Neftin #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 375*8d744963SMuhammad Husaini Zulkifli #define IGC_TX_FLAGS_VLAN_SHIFT 16 376d3ae3cfbSSasha Neftin 3770507ef8aSSasha Neftin /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 3780507ef8aSSasha Neftin static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 3790507ef8aSSasha Neftin const u32 stat_err_bits) 3800507ef8aSSasha Neftin { 3810507ef8aSSasha Neftin return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 3820507ef8aSSasha Neftin } 3830507ef8aSSasha Neftin 384c9a11c23SSasha Neftin enum igc_state_t { 385c9a11c23SSasha Neftin __IGC_TESTING, 386c9a11c23SSasha Neftin __IGC_RESETTING, 387c9a11c23SSasha Neftin __IGC_DOWN, 388c9a11c23SSasha Neftin __IGC_PTP_TX_IN_PROGRESS, 389c9a11c23SSasha Neftin }; 390c9a11c23SSasha Neftin 3910507ef8aSSasha Neftin enum igc_tx_flags { 3920507ef8aSSasha Neftin /* cmd_type flags */ 3930507ef8aSSasha Neftin IGC_TX_FLAGS_VLAN = 0x01, 3940507ef8aSSasha Neftin IGC_TX_FLAGS_TSO = 0x02, 3950507ef8aSSasha Neftin IGC_TX_FLAGS_TSTAMP = 0x04, 3960507ef8aSSasha Neftin 3970507ef8aSSasha Neftin /* olinfo flags */ 3980507ef8aSSasha Neftin IGC_TX_FLAGS_IPV4 = 0x10, 3990507ef8aSSasha Neftin IGC_TX_FLAGS_CSUM = 0x20, 4000507ef8aSSasha Neftin }; 4010507ef8aSSasha Neftin 402ab405612SSasha Neftin enum igc_boards { 403ab405612SSasha Neftin board_base, 404ab405612SSasha Neftin }; 405ab405612SSasha Neftin 4060507ef8aSSasha Neftin /* The largest size we can write to the descriptor is 65535. In order to 4070507ef8aSSasha Neftin * maintain a power of two alignment we have to limit ourselves to 32K. 4080507ef8aSSasha Neftin */ 4090507ef8aSSasha Neftin #define IGC_MAX_TXD_PWR 15 4100507ef8aSSasha Neftin #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 4110507ef8aSSasha Neftin 4120507ef8aSSasha Neftin /* Tx Descriptors needed, worst case */ 4130507ef8aSSasha Neftin #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 4140507ef8aSSasha Neftin #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 4150507ef8aSSasha Neftin 416859b4dfaSAndre Guedes enum igc_tx_buffer_type { 417859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_SKB, 418859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_XDP, 4199acf59a7SAndre Guedes IGC_TX_BUFFER_TYPE_XSK, 420859b4dfaSAndre Guedes }; 421859b4dfaSAndre Guedes 42213b5b7fdSSasha Neftin /* wrapper around a pointer to a socket buffer, 42313b5b7fdSSasha Neftin * so a DMA handle can be stored along with the buffer 42413b5b7fdSSasha Neftin */ 42513b5b7fdSSasha Neftin struct igc_tx_buffer { 42613b5b7fdSSasha Neftin union igc_adv_tx_desc *next_to_watch; 42713b5b7fdSSasha Neftin unsigned long time_stamp; 428859b4dfaSAndre Guedes enum igc_tx_buffer_type type; 42973f1071cSAndre Guedes union { 43013b5b7fdSSasha Neftin struct sk_buff *skb; 43173f1071cSAndre Guedes struct xdp_frame *xdpf; 43273f1071cSAndre Guedes }; 43313b5b7fdSSasha Neftin unsigned int bytecount; 43413b5b7fdSSasha Neftin u16 gso_segs; 43513b5b7fdSSasha Neftin __be16 protocol; 43613b5b7fdSSasha Neftin 43713b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_ADDR(dma); 43813b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_LEN(len); 43913b5b7fdSSasha Neftin u32 tx_flags; 44013b5b7fdSSasha Neftin }; 44113b5b7fdSSasha Neftin 44213b5b7fdSSasha Neftin struct igc_rx_buffer { 443fc9df2a0SAndre Guedes union { 444fc9df2a0SAndre Guedes struct { 44513b5b7fdSSasha Neftin dma_addr_t dma; 44613b5b7fdSSasha Neftin struct page *page; 44713b5b7fdSSasha Neftin #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 44813b5b7fdSSasha Neftin __u32 page_offset; 44913b5b7fdSSasha Neftin #else 45013b5b7fdSSasha Neftin __u16 page_offset; 45113b5b7fdSSasha Neftin #endif 45213b5b7fdSSasha Neftin __u16 pagecnt_bias; 45313b5b7fdSSasha Neftin }; 454fc9df2a0SAndre Guedes struct xdp_buff *xdp; 455fc9df2a0SAndre Guedes }; 456fc9df2a0SAndre Guedes }; 45713b5b7fdSSasha Neftin 458c9a11c23SSasha Neftin struct igc_q_vector { 459c9a11c23SSasha Neftin struct igc_adapter *adapter; /* backlink */ 4603df25e4cSSasha Neftin void __iomem *itr_register; 4613df25e4cSSasha Neftin u32 eims_value; /* EIMS mask value */ 4623df25e4cSSasha Neftin 4633df25e4cSSasha Neftin u16 itr_val; 4643df25e4cSSasha Neftin u8 set_itr; 4653df25e4cSSasha Neftin 4663df25e4cSSasha Neftin struct igc_ring_container rx, tx; 467c9a11c23SSasha Neftin 468c9a11c23SSasha Neftin struct napi_struct napi; 4693df25e4cSSasha Neftin 4703df25e4cSSasha Neftin struct rcu_head rcu; /* to avoid race with update stats on free */ 4713df25e4cSSasha Neftin char name[IFNAMSIZ + 9]; 4723df25e4cSSasha Neftin struct net_device poll_dev; 4733df25e4cSSasha Neftin 4743df25e4cSSasha Neftin /* for dynamic allocation of rings associated with this q_vector */ 475040efdb1SGustavo A. R. Silva struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 476c9a11c23SSasha Neftin }; 477c9a11c23SSasha Neftin 4786245c848SSasha Neftin enum igc_filter_match_flags { 4796245c848SSasha Neftin IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 4806245c848SSasha Neftin IGC_FILTER_FLAG_VLAN_TCI = 0x2, 4816245c848SSasha Neftin IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 4826245c848SSasha Neftin IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 4836245c848SSasha Neftin }; 4846245c848SSasha Neftin 48597700bc8SAndre Guedes struct igc_nfc_filter { 4866245c848SSasha Neftin u8 match_flags; 487c983e327SAndre Guedes u16 etype; 488c983e327SAndre Guedes u16 vlan_tci; 4896245c848SSasha Neftin u8 src_addr[ETH_ALEN]; 4906245c848SSasha Neftin u8 dst_addr[ETH_ALEN]; 4916245c848SSasha Neftin }; 4926245c848SSasha Neftin 49397700bc8SAndre Guedes struct igc_nfc_rule { 494d957c601SAndre Guedes struct list_head list; 49597700bc8SAndre Guedes struct igc_nfc_filter filter; 496d3ba9e6fSAndre Guedes u32 location; 4976245c848SSasha Neftin u16 action; 4986245c848SSasha Neftin }; 4996245c848SSasha Neftin 500e087d3bbSAndre Guedes /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority 501e087d3bbSAndre Guedes * based, and 8 ethertype based. 502e087d3bbSAndre Guedes */ 503e087d3bbSAndre Guedes #define IGC_MAX_RXNFC_RULES 32 504c9a11c23SSasha Neftin 50513b5b7fdSSasha Neftin /* igc_desc_unused - calculate if we have unused descriptors */ 50613b5b7fdSSasha Neftin static inline u16 igc_desc_unused(const struct igc_ring *ring) 50713b5b7fdSSasha Neftin { 50813b5b7fdSSasha Neftin u16 ntc = ring->next_to_clean; 50913b5b7fdSSasha Neftin u16 ntu = ring->next_to_use; 51013b5b7fdSSasha Neftin 51113b5b7fdSSasha Neftin return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 51213b5b7fdSSasha Neftin } 51313b5b7fdSSasha Neftin 5145586838fSSasha Neftin static inline s32 igc_get_phy_info(struct igc_hw *hw) 5155586838fSSasha Neftin { 5165586838fSSasha Neftin if (hw->phy.ops.get_phy_info) 5175586838fSSasha Neftin return hw->phy.ops.get_phy_info(hw); 5185586838fSSasha Neftin 5195586838fSSasha Neftin return 0; 5205586838fSSasha Neftin } 5215586838fSSasha Neftin 5225586838fSSasha Neftin static inline s32 igc_reset_phy(struct igc_hw *hw) 5235586838fSSasha Neftin { 5245586838fSSasha Neftin if (hw->phy.ops.reset) 5255586838fSSasha Neftin return hw->phy.ops.reset(hw); 5265586838fSSasha Neftin 5275586838fSSasha Neftin return 0; 5285586838fSSasha Neftin } 5295586838fSSasha Neftin 53013b5b7fdSSasha Neftin static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 53113b5b7fdSSasha Neftin { 53213b5b7fdSSasha Neftin return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 53313b5b7fdSSasha Neftin } 53413b5b7fdSSasha Neftin 53513b5b7fdSSasha Neftin enum igc_ring_flags_t { 53613b5b7fdSSasha Neftin IGC_RING_FLAG_RX_3K_BUFFER, 53713b5b7fdSSasha Neftin IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 53813b5b7fdSSasha Neftin IGC_RING_FLAG_RX_SCTP_CSUM, 53913b5b7fdSSasha Neftin IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 54013b5b7fdSSasha Neftin IGC_RING_FLAG_TX_CTX_IDX, 541fc9df2a0SAndre Guedes IGC_RING_FLAG_TX_DETECT_HANG, 542fc9df2a0SAndre Guedes IGC_RING_FLAG_AF_XDP_ZC, 54313b5b7fdSSasha Neftin }; 54413b5b7fdSSasha Neftin 54513b5b7fdSSasha Neftin #define ring_uses_large_buffer(ring) \ 54613b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 5471bf33f71SAndre Guedes #define set_ring_uses_large_buffer(ring) \ 5481bf33f71SAndre Guedes set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 5491bf33f71SAndre Guedes #define clear_ring_uses_large_buffer(ring) \ 5501bf33f71SAndre Guedes clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 55113b5b7fdSSasha Neftin 55213b5b7fdSSasha Neftin #define ring_uses_build_skb(ring) \ 55313b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 55413b5b7fdSSasha Neftin 55513b5b7fdSSasha Neftin static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 55613b5b7fdSSasha Neftin { 55713b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 55813b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 55913b5b7fdSSasha Neftin return IGC_RXBUFFER_3072; 56013b5b7fdSSasha Neftin 56113b5b7fdSSasha Neftin if (ring_uses_build_skb(ring)) 56213b5b7fdSSasha Neftin return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 56313b5b7fdSSasha Neftin #endif 56413b5b7fdSSasha Neftin return IGC_RXBUFFER_2048; 56513b5b7fdSSasha Neftin } 56613b5b7fdSSasha Neftin 56713b5b7fdSSasha Neftin static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 56813b5b7fdSSasha Neftin { 56913b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 57013b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 57113b5b7fdSSasha Neftin return 1; 57213b5b7fdSSasha Neftin #endif 57313b5b7fdSSasha Neftin return 0; 57413b5b7fdSSasha Neftin } 57513b5b7fdSSasha Neftin 576208983f0SSasha Neftin static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 577208983f0SSasha Neftin { 578208983f0SSasha Neftin if (hw->phy.ops.read_reg) 579208983f0SSasha Neftin return hw->phy.ops.read_reg(hw, offset, data); 580208983f0SSasha Neftin 581208983f0SSasha Neftin return 0; 582208983f0SSasha Neftin } 583208983f0SSasha Neftin 5848c5ad0daSSasha Neftin void igc_reinit_locked(struct igc_adapter *); 58536fa2152SAndre Guedes struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 58636fa2152SAndre Guedes u32 location); 58736fa2152SAndre Guedes int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 58836fa2152SAndre Guedes void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 5898c5ad0daSSasha Neftin 5905f295805SVinicius Costa Gomes void igc_ptp_init(struct igc_adapter *adapter); 5915f295805SVinicius Costa Gomes void igc_ptp_reset(struct igc_adapter *adapter); 592a5136f76SSasha Neftin void igc_ptp_suspend(struct igc_adapter *adapter); 5935f295805SVinicius Costa Gomes void igc_ptp_stop(struct igc_adapter *adapter); 594e1ed4f92SAndre Guedes ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 5955f295805SVinicius Costa Gomes int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 5965f295805SVinicius Costa Gomes int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 5972c344ae2SVinicius Costa Gomes void igc_ptp_tx_hang(struct igc_adapter *adapter); 598fec49eb4SVinicius Costa Gomes void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 5992c344ae2SVinicius Costa Gomes 60013b5b7fdSSasha Neftin #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 60113b5b7fdSSasha Neftin 6020507ef8aSSasha Neftin #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 6030507ef8aSSasha Neftin 60413b5b7fdSSasha Neftin #define IGC_RX_DESC(R, i) \ 60513b5b7fdSSasha Neftin (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 60613b5b7fdSSasha Neftin #define IGC_TX_DESC(R, i) \ 60713b5b7fdSSasha Neftin (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 60813b5b7fdSSasha Neftin #define IGC_TX_CTXTDESC(R, i) \ 60913b5b7fdSSasha Neftin (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 61013b5b7fdSSasha Neftin 611d89f8841SSasha Neftin #endif /* _IGC_H_ */ 612