1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_H_ 5d89f8841SSasha Neftin #define _IGC_H_ 6d89f8841SSasha Neftin 7d89f8841SSasha Neftin #include <linux/kobject.h> 8d89f8841SSasha Neftin #include <linux/pci.h> 9d89f8841SSasha Neftin #include <linux/netdevice.h> 10d89f8841SSasha Neftin #include <linux/vmalloc.h> 11d89f8841SSasha Neftin #include <linux/ethtool.h> 12d89f8841SSasha Neftin #include <linux/sctp.h> 135f295805SVinicius Costa Gomes #include <linux/ptp_clock_kernel.h> 145f295805SVinicius Costa Gomes #include <linux/timecounter.h> 155f295805SVinicius Costa Gomes #include <linux/net_tstamp.h> 16d89f8841SSasha Neftin 17146740f9SSasha Neftin #include "igc_hw.h" 18146740f9SSasha Neftin 197df76bd1SAndre Guedes void igc_ethtool_set_ops(struct net_device *); 208c5ad0daSSasha Neftin 2189d35511SSasha Neftin /* Transmit and receive queues */ 2289d35511SSasha Neftin #define IGC_MAX_RX_QUEUES 4 2389d35511SSasha Neftin #define IGC_MAX_TX_QUEUES 4 2489d35511SSasha Neftin 2589d35511SSasha Neftin #define MAX_Q_VECTORS 8 2689d35511SSasha Neftin #define MAX_STD_JUMBO_FRAME_SIZE 9216 2789d35511SSasha Neftin 28b4d48d96SAndre Guedes #define MAX_ETYPE_FILTER 8 2989d35511SSasha Neftin #define IGC_RETA_SIZE 128 3089d35511SSasha Neftin 3187938851SEderson de Souza /* SDP support */ 3287938851SEderson de Souza #define IGC_N_EXTTS 2 3387938851SEderson de Souza #define IGC_N_PEROUT 2 3487938851SEderson de Souza #define IGC_N_SDP 4 3587938851SEderson de Souza 366574631bSKurt Kanzenbach #define MAX_FLEX_FILTER 32 376574631bSKurt Kanzenbach 38750433d0SAndre Guedes enum igc_mac_filter_type { 39750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_DST = 0, 40750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_SRC 41750433d0SAndre Guedes }; 42750433d0SAndre Guedes 4389d35511SSasha Neftin struct igc_tx_queue_stats { 4489d35511SSasha Neftin u64 packets; 4589d35511SSasha Neftin u64 bytes; 4689d35511SSasha Neftin u64 restart_queue; 4789d35511SSasha Neftin u64 restart_queue2; 4889d35511SSasha Neftin }; 4989d35511SSasha Neftin 5089d35511SSasha Neftin struct igc_rx_queue_stats { 5189d35511SSasha Neftin u64 packets; 5289d35511SSasha Neftin u64 bytes; 5389d35511SSasha Neftin u64 drops; 5489d35511SSasha Neftin u64 csum_err; 5589d35511SSasha Neftin u64 alloc_failed; 5689d35511SSasha Neftin }; 5789d35511SSasha Neftin 5889d35511SSasha Neftin struct igc_rx_packet_stats { 5989d35511SSasha Neftin u64 ipv4_packets; /* IPv4 headers processed */ 6089d35511SSasha Neftin u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 6189d35511SSasha Neftin u64 ipv6_packets; /* IPv6 headers processed */ 6289d35511SSasha Neftin u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 6389d35511SSasha Neftin u64 tcp_packets; /* TCP headers processed */ 6489d35511SSasha Neftin u64 udp_packets; /* UDP headers processed */ 6589d35511SSasha Neftin u64 sctp_packets; /* SCTP headers processed */ 6689d35511SSasha Neftin u64 nfs_packets; /* NFS headers processe */ 6789d35511SSasha Neftin u64 other_packets; 6889d35511SSasha Neftin }; 6989d35511SSasha Neftin 7089d35511SSasha Neftin struct igc_ring_container { 7189d35511SSasha Neftin struct igc_ring *ring; /* pointer to linked list of rings */ 7289d35511SSasha Neftin unsigned int total_bytes; /* total bytes processed this int */ 7389d35511SSasha Neftin unsigned int total_packets; /* total packets processed this int */ 7489d35511SSasha Neftin u16 work_limit; /* total work allowed per interrupt */ 7589d35511SSasha Neftin u8 count; /* total number of rings in vector */ 7689d35511SSasha Neftin u8 itr; /* current ITR setting for ring */ 7789d35511SSasha Neftin }; 7889d35511SSasha Neftin 7989d35511SSasha Neftin struct igc_ring { 8089d35511SSasha Neftin struct igc_q_vector *q_vector; /* backlink to q_vector */ 8189d35511SSasha Neftin struct net_device *netdev; /* back pointer to net_device */ 8289d35511SSasha Neftin struct device *dev; /* device for dma mapping */ 8389d35511SSasha Neftin union { /* array of buffer info structs */ 8489d35511SSasha Neftin struct igc_tx_buffer *tx_buffer_info; 8589d35511SSasha Neftin struct igc_rx_buffer *rx_buffer_info; 8689d35511SSasha Neftin }; 8789d35511SSasha Neftin void *desc; /* descriptor ring memory */ 8889d35511SSasha Neftin unsigned long flags; /* ring specific flags */ 8989d35511SSasha Neftin void __iomem *tail; /* pointer to ring tail register */ 9089d35511SSasha Neftin dma_addr_t dma; /* phys address of the ring */ 9189d35511SSasha Neftin unsigned int size; /* length of desc. ring in bytes */ 9289d35511SSasha Neftin 9389d35511SSasha Neftin u16 count; /* number of desc. in the ring */ 9489d35511SSasha Neftin u8 queue_index; /* logical index of the ring*/ 9589d35511SSasha Neftin u8 reg_idx; /* physical index of the ring */ 9689d35511SSasha Neftin bool launchtime_enable; /* true if LaunchTime is enabled */ 9789d35511SSasha Neftin 9889d35511SSasha Neftin u32 start_time; 9989d35511SSasha Neftin u32 end_time; 10089d35511SSasha Neftin 10189d35511SSasha Neftin /* everything past this point are written often */ 10289d35511SSasha Neftin u16 next_to_clean; 10389d35511SSasha Neftin u16 next_to_use; 10489d35511SSasha Neftin u16 next_to_alloc; 10589d35511SSasha Neftin 10689d35511SSasha Neftin union { 10789d35511SSasha Neftin /* TX */ 10889d35511SSasha Neftin struct { 10989d35511SSasha Neftin struct igc_tx_queue_stats tx_stats; 11089d35511SSasha Neftin struct u64_stats_sync tx_syncp; 11189d35511SSasha Neftin struct u64_stats_sync tx_syncp2; 11289d35511SSasha Neftin }; 11389d35511SSasha Neftin /* RX */ 11489d35511SSasha Neftin struct { 11589d35511SSasha Neftin struct igc_rx_queue_stats rx_stats; 11689d35511SSasha Neftin struct igc_rx_packet_stats pkt_stats; 11789d35511SSasha Neftin struct u64_stats_sync rx_syncp; 11889d35511SSasha Neftin struct sk_buff *skb; 11989d35511SSasha Neftin }; 12089d35511SSasha Neftin }; 12173f1071cSAndre Guedes 12273f1071cSAndre Guedes struct xdp_rxq_info xdp_rxq; 123fc9df2a0SAndre Guedes struct xsk_buff_pool *xsk_pool; 12489d35511SSasha Neftin } ____cacheline_internodealigned_in_smp; 12589d35511SSasha Neftin 12689d35511SSasha Neftin /* Board specific private data structure */ 12789d35511SSasha Neftin struct igc_adapter { 12889d35511SSasha Neftin struct net_device *netdev; 12989d35511SSasha Neftin 13093ec439aSSasha Neftin struct ethtool_eee eee; 13193ec439aSSasha Neftin u16 eee_advert; 13293ec439aSSasha Neftin 13389d35511SSasha Neftin unsigned long state; 13489d35511SSasha Neftin unsigned int flags; 13589d35511SSasha Neftin unsigned int num_q_vectors; 13689d35511SSasha Neftin 13789d35511SSasha Neftin struct msix_entry *msix_entries; 13889d35511SSasha Neftin 13989d35511SSasha Neftin /* TX */ 14089d35511SSasha Neftin u16 tx_work_limit; 14189d35511SSasha Neftin u32 tx_timeout_count; 14289d35511SSasha Neftin int num_tx_queues; 14389d35511SSasha Neftin struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 14489d35511SSasha Neftin 14589d35511SSasha Neftin /* RX */ 14689d35511SSasha Neftin int num_rx_queues; 14789d35511SSasha Neftin struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 14889d35511SSasha Neftin 14989d35511SSasha Neftin struct timer_list watchdog_timer; 15089d35511SSasha Neftin struct timer_list dma_err_timer; 15189d35511SSasha Neftin struct timer_list phy_info_timer; 15289d35511SSasha Neftin 15389d35511SSasha Neftin u32 wol; 15489d35511SSasha Neftin u32 en_mng_pt; 15589d35511SSasha Neftin u16 link_speed; 15689d35511SSasha Neftin u16 link_duplex; 15789d35511SSasha Neftin 15889d35511SSasha Neftin u8 port_num; 15989d35511SSasha Neftin 16089d35511SSasha Neftin u8 __iomem *io_addr; 16189d35511SSasha Neftin /* Interrupt Throttle Rate */ 16289d35511SSasha Neftin u32 rx_itr_setting; 16389d35511SSasha Neftin u32 tx_itr_setting; 16489d35511SSasha Neftin 16589d35511SSasha Neftin struct work_struct reset_task; 16689d35511SSasha Neftin struct work_struct watchdog_task; 16789d35511SSasha Neftin struct work_struct dma_err_task; 16889d35511SSasha Neftin bool fc_autoneg; 16989d35511SSasha Neftin 17089d35511SSasha Neftin u8 tx_timeout_factor; 17189d35511SSasha Neftin 17289d35511SSasha Neftin int msg_enable; 17389d35511SSasha Neftin u32 max_frame_size; 17489d35511SSasha Neftin u32 min_frame_size; 17589d35511SSasha Neftin 17689d35511SSasha Neftin ktime_t base_time; 17789d35511SSasha Neftin ktime_t cycle_time; 17889d35511SSasha Neftin 17989d35511SSasha Neftin /* OS defined structs */ 18089d35511SSasha Neftin struct pci_dev *pdev; 18189d35511SSasha Neftin /* lock for statistics */ 18289d35511SSasha Neftin spinlock_t stats64_lock; 18389d35511SSasha Neftin struct rtnl_link_stats64 stats64; 18489d35511SSasha Neftin 18589d35511SSasha Neftin /* structs defined in igc_hw.h */ 18689d35511SSasha Neftin struct igc_hw hw; 18789d35511SSasha Neftin struct igc_hw_stats stats; 18889d35511SSasha Neftin 18989d35511SSasha Neftin struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 19089d35511SSasha Neftin u32 eims_enable_mask; 19189d35511SSasha Neftin u32 eims_other; 19289d35511SSasha Neftin 19389d35511SSasha Neftin u16 tx_ring_count; 19489d35511SSasha Neftin u16 rx_ring_count; 19589d35511SSasha Neftin 19689d35511SSasha Neftin u32 tx_hwtstamp_timeouts; 19789d35511SSasha Neftin u32 tx_hwtstamp_skipped; 19889d35511SSasha Neftin u32 rx_hwtstamp_cleared; 19989d35511SSasha Neftin 20089d35511SSasha Neftin u32 rss_queues; 20189d35511SSasha Neftin u32 rss_indir_tbl_init; 20289d35511SSasha Neftin 20397700bc8SAndre Guedes /* Any access to elements in nfc_rule_list is protected by the 20497700bc8SAndre Guedes * nfc_rule_lock. 20597700bc8SAndre Guedes */ 20642fc5dc0SAndre Guedes struct mutex nfc_rule_lock; 207d957c601SAndre Guedes struct list_head nfc_rule_list; 20897700bc8SAndre Guedes unsigned int nfc_rule_count; 20989d35511SSasha Neftin 21089d35511SSasha Neftin u8 rss_indir_tbl[IGC_RETA_SIZE]; 21189d35511SSasha Neftin 21289d35511SSasha Neftin unsigned long link_check_timeout; 21389d35511SSasha Neftin struct igc_info ei; 21489d35511SSasha Neftin 215f026d8caSVitaly Lifshits u32 test_icr; 216f026d8caSVitaly Lifshits 21789d35511SSasha Neftin struct ptp_clock *ptp_clock; 21889d35511SSasha Neftin struct ptp_clock_info ptp_caps; 21989d35511SSasha Neftin struct work_struct ptp_tx_work; 22089d35511SSasha Neftin struct sk_buff *ptp_tx_skb; 22189d35511SSasha Neftin struct hwtstamp_config tstamp_config; 22289d35511SSasha Neftin unsigned long ptp_tx_start; 22389d35511SSasha Neftin unsigned int ptp_flags; 22489d35511SSasha Neftin /* System time value lock */ 22589d35511SSasha Neftin spinlock_t tmreg_lock; 22689d35511SSasha Neftin struct cyclecounter cc; 22789d35511SSasha Neftin struct timecounter tc; 228b03c49cdSVinicius Costa Gomes struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ 229b03c49cdSVinicius Costa Gomes ktime_t ptp_reset_start; /* Reset time in clock mono */ 230a90ec848SVinicius Costa Gomes struct system_time_snapshot snapshot; 23101bb6129SSasha Neftin 23294f794d1SSasha Neftin char fw_version[32]; 23326575105SAndre Guedes 23426575105SAndre Guedes struct bpf_prog *xdp_prog; 23564433e5bSEderson de Souza 23664433e5bSEderson de Souza bool pps_sys_wrap_on; 23787938851SEderson de Souza 23887938851SEderson de Souza struct ptp_pin_desc sdp_config[IGC_N_SDP]; 23987938851SEderson de Souza struct { 24087938851SEderson de Souza struct timespec64 start; 24187938851SEderson de Souza struct timespec64 period; 24287938851SEderson de Souza } perout[IGC_N_PEROUT]; 24389d35511SSasha Neftin }; 2448c5ad0daSSasha Neftin 2458c5ad0daSSasha Neftin void igc_up(struct igc_adapter *adapter); 2468c5ad0daSSasha Neftin void igc_down(struct igc_adapter *adapter); 247f026d8caSVitaly Lifshits int igc_open(struct net_device *netdev); 248f026d8caSVitaly Lifshits int igc_close(struct net_device *netdev); 2498c5ad0daSSasha Neftin int igc_setup_tx_resources(struct igc_ring *ring); 2508c5ad0daSSasha Neftin int igc_setup_rx_resources(struct igc_ring *ring); 2518c5ad0daSSasha Neftin void igc_free_tx_resources(struct igc_ring *ring); 2528c5ad0daSSasha Neftin void igc_free_rx_resources(struct igc_ring *ring); 2538c5ad0daSSasha Neftin unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 2548c5ad0daSSasha Neftin void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 2558c5ad0daSSasha Neftin const u32 max_rss_queues); 2568c5ad0daSSasha Neftin int igc_reinit_queues(struct igc_adapter *adapter); 2572121c271SSasha Neftin void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 2588c5ad0daSSasha Neftin bool igc_has_link(struct igc_adapter *adapter); 2598c5ad0daSSasha Neftin void igc_reset(struct igc_adapter *adapter); 2608c5ad0daSSasha Neftin int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 26136b9fea6SSasha Neftin void igc_update_stats(struct igc_adapter *adapter); 262fc9df2a0SAndre Guedes void igc_disable_rx_ring(struct igc_ring *ring); 263fc9df2a0SAndre Guedes void igc_enable_rx_ring(struct igc_ring *ring); 2649acf59a7SAndre Guedes void igc_disable_tx_ring(struct igc_ring *ring); 2659acf59a7SAndre Guedes void igc_enable_tx_ring(struct igc_ring *ring); 266fc9df2a0SAndre Guedes int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags); 2678c5ad0daSSasha Neftin 2689c384ee3SSasha Neftin /* igc_dump declarations */ 2699c384ee3SSasha Neftin void igc_rings_dump(struct igc_adapter *adapter); 2709c384ee3SSasha Neftin void igc_regs_dump(struct igc_adapter *adapter); 2719c384ee3SSasha Neftin 272d89f8841SSasha Neftin extern char igc_driver_name[]; 273d89f8841SSasha Neftin 2748c5ad0daSSasha Neftin #define IGC_REGS_LEN 740 2758c5ad0daSSasha Neftin 2765f295805SVinicius Costa Gomes /* flags controlling PTP/1588 function */ 2775f295805SVinicius Costa Gomes #define IGC_PTP_ENABLED BIT(0) 2785f295805SVinicius Costa Gomes 27967082b53SSasha Neftin /* Flags definitions */ 2803df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSI BIT(0) 2818c5ad0daSSasha Neftin #define IGC_FLAG_QUEUE_PAIRS BIT(3) 2828c5ad0daSSasha Neftin #define IGC_FLAG_DMAC BIT(4) 2835f295805SVinicius Costa Gomes #define IGC_FLAG_PTP BIT(8) 284e055600dSSasha Neftin #define IGC_FLAG_WOL_SUPPORTED BIT(8) 2850507ef8aSSasha Neftin #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 286208983f0SSasha Neftin #define IGC_FLAG_MEDIA_RESET BIT(10) 287208983f0SSasha Neftin #define IGC_FLAG_MAS_ENABLE BIT(12) 2883df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSIX BIT(13) 28993ec439aSSasha Neftin #define IGC_FLAG_EEE BIT(14) 2900507ef8aSSasha Neftin #define IGC_FLAG_VLAN_PROMISC BIT(15) 2918c5ad0daSSasha Neftin #define IGC_FLAG_RX_LEGACY BIT(16) 292ec50a9d4SVinicius Costa Gomes #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 2933df25e4cSSasha Neftin 294*61572d5fSVinicius Costa Gomes #define IGC_FLAG_TSN_ANY_ENABLED IGC_FLAG_TSN_QBV_ENABLED 295*61572d5fSVinicius Costa Gomes 2962121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 2972121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 2982121c271SSasha Neftin 2992121c271SSasha Neftin #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 3002121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 3012121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 3022121c271SSasha Neftin 30364900e8fSSasha Neftin /* Interrupt defines */ 3043df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */ 3053df25e4cSSasha Neftin #define IGC_4K_ITR 980 3063df25e4cSSasha Neftin #define IGC_20K_ITR 196 3073df25e4cSSasha Neftin #define IGC_70K_ITR 56 3083df25e4cSSasha Neftin 3090507ef8aSSasha Neftin #define IGC_DEFAULT_ITR 3 /* dynamic */ 3100507ef8aSSasha Neftin #define IGC_MAX_ITR_USECS 10000 3110507ef8aSSasha Neftin #define IGC_MIN_ITR_USECS 10 3120507ef8aSSasha Neftin #define NON_Q_VECTORS 1 3130507ef8aSSasha Neftin #define MAX_MSIX_ENTRIES 10 3140507ef8aSSasha Neftin 3150507ef8aSSasha Neftin /* TX/RX descriptor defines */ 3160507ef8aSSasha Neftin #define IGC_DEFAULT_TXD 256 3170507ef8aSSasha Neftin #define IGC_DEFAULT_TX_WORK 128 3180507ef8aSSasha Neftin #define IGC_MIN_TXD 80 3190507ef8aSSasha Neftin #define IGC_MAX_TXD 4096 3200507ef8aSSasha Neftin 3210507ef8aSSasha Neftin #define IGC_DEFAULT_RXD 256 3220507ef8aSSasha Neftin #define IGC_MIN_RXD 80 3230507ef8aSSasha Neftin #define IGC_MAX_RXD 4096 3240507ef8aSSasha Neftin 32513b5b7fdSSasha Neftin /* Supported Rx Buffer Sizes */ 32613b5b7fdSSasha Neftin #define IGC_RXBUFFER_256 256 32713b5b7fdSSasha Neftin #define IGC_RXBUFFER_2048 2048 32813b5b7fdSSasha Neftin #define IGC_RXBUFFER_3072 3072 32913b5b7fdSSasha Neftin 3308c5ad0daSSasha Neftin #define AUTO_ALL_MODES 0 33113b5b7fdSSasha Neftin #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 33213b5b7fdSSasha Neftin 33381b05520SVinicius Costa Gomes /* Transmit and receive latency (for PTP timestamps) */ 334f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_10 240 335f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_100 58 336f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_1000 80 337f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_2500 1325 338f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_10 6450 339f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_100 185 340f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_1000 300 341f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_2500 1485 34281b05520SVinicius Costa Gomes 34313b5b7fdSSasha Neftin /* RX and TX descriptor control thresholds. 34413b5b7fdSSasha Neftin * PTHRESH - MAC will consider prefetch if it has fewer than this number of 34513b5b7fdSSasha Neftin * descriptors available in its onboard memory. 34613b5b7fdSSasha Neftin * Setting this to 0 disables RX descriptor prefetch. 34713b5b7fdSSasha Neftin * HTHRESH - MAC will only prefetch if there are at least this many descriptors 34813b5b7fdSSasha Neftin * available in host memory. 34913b5b7fdSSasha Neftin * If PTHRESH is 0, this should also be 0. 35013b5b7fdSSasha Neftin * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 35113b5b7fdSSasha Neftin * descriptors until either it has this many to write back, or the 35213b5b7fdSSasha Neftin * ITR timer expires. 35313b5b7fdSSasha Neftin */ 35413b5b7fdSSasha Neftin #define IGC_RX_PTHRESH 8 35513b5b7fdSSasha Neftin #define IGC_RX_HTHRESH 8 35613b5b7fdSSasha Neftin #define IGC_TX_PTHRESH 8 35713b5b7fdSSasha Neftin #define IGC_TX_HTHRESH 1 35813b5b7fdSSasha Neftin #define IGC_RX_WTHRESH 4 35913b5b7fdSSasha Neftin #define IGC_TX_WTHRESH 16 36013b5b7fdSSasha Neftin 36113b5b7fdSSasha Neftin #define IGC_RX_DMA_ATTR \ 36213b5b7fdSSasha Neftin (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 36313b5b7fdSSasha Neftin 36413b5b7fdSSasha Neftin #define IGC_TS_HDR_LEN 16 36513b5b7fdSSasha Neftin 36613b5b7fdSSasha Neftin #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 36713b5b7fdSSasha Neftin 36813b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 36913b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB \ 37013b5b7fdSSasha Neftin (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 37113b5b7fdSSasha Neftin #else 37213b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 37313b5b7fdSSasha Neftin #endif 37413b5b7fdSSasha Neftin 3750507ef8aSSasha Neftin /* How many Rx Buffers do we bundle into one write to the hardware ? */ 3760507ef8aSSasha Neftin #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 3770507ef8aSSasha Neftin 378d3ae3cfbSSasha Neftin /* VLAN info */ 379d3ae3cfbSSasha Neftin #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 3808d744963SMuhammad Husaini Zulkifli #define IGC_TX_FLAGS_VLAN_SHIFT 16 381d3ae3cfbSSasha Neftin 3820507ef8aSSasha Neftin /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 3830507ef8aSSasha Neftin static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 3840507ef8aSSasha Neftin const u32 stat_err_bits) 3850507ef8aSSasha Neftin { 3860507ef8aSSasha Neftin return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 3870507ef8aSSasha Neftin } 3880507ef8aSSasha Neftin 389c9a11c23SSasha Neftin enum igc_state_t { 390c9a11c23SSasha Neftin __IGC_TESTING, 391c9a11c23SSasha Neftin __IGC_RESETTING, 392c9a11c23SSasha Neftin __IGC_DOWN, 393c9a11c23SSasha Neftin __IGC_PTP_TX_IN_PROGRESS, 394c9a11c23SSasha Neftin }; 395c9a11c23SSasha Neftin 3960507ef8aSSasha Neftin enum igc_tx_flags { 3970507ef8aSSasha Neftin /* cmd_type flags */ 3980507ef8aSSasha Neftin IGC_TX_FLAGS_VLAN = 0x01, 3990507ef8aSSasha Neftin IGC_TX_FLAGS_TSO = 0x02, 4000507ef8aSSasha Neftin IGC_TX_FLAGS_TSTAMP = 0x04, 4010507ef8aSSasha Neftin 4020507ef8aSSasha Neftin /* olinfo flags */ 4030507ef8aSSasha Neftin IGC_TX_FLAGS_IPV4 = 0x10, 4040507ef8aSSasha Neftin IGC_TX_FLAGS_CSUM = 0x20, 4050507ef8aSSasha Neftin }; 4060507ef8aSSasha Neftin 407ab405612SSasha Neftin enum igc_boards { 408ab405612SSasha Neftin board_base, 409ab405612SSasha Neftin }; 410ab405612SSasha Neftin 4110507ef8aSSasha Neftin /* The largest size we can write to the descriptor is 65535. In order to 4120507ef8aSSasha Neftin * maintain a power of two alignment we have to limit ourselves to 32K. 4130507ef8aSSasha Neftin */ 4140507ef8aSSasha Neftin #define IGC_MAX_TXD_PWR 15 4150507ef8aSSasha Neftin #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 4160507ef8aSSasha Neftin 4170507ef8aSSasha Neftin /* Tx Descriptors needed, worst case */ 4180507ef8aSSasha Neftin #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 4190507ef8aSSasha Neftin #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 4200507ef8aSSasha Neftin 421859b4dfaSAndre Guedes enum igc_tx_buffer_type { 422859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_SKB, 423859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_XDP, 4249acf59a7SAndre Guedes IGC_TX_BUFFER_TYPE_XSK, 425859b4dfaSAndre Guedes }; 426859b4dfaSAndre Guedes 42713b5b7fdSSasha Neftin /* wrapper around a pointer to a socket buffer, 42813b5b7fdSSasha Neftin * so a DMA handle can be stored along with the buffer 42913b5b7fdSSasha Neftin */ 43013b5b7fdSSasha Neftin struct igc_tx_buffer { 43113b5b7fdSSasha Neftin union igc_adv_tx_desc *next_to_watch; 43213b5b7fdSSasha Neftin unsigned long time_stamp; 433859b4dfaSAndre Guedes enum igc_tx_buffer_type type; 43473f1071cSAndre Guedes union { 43513b5b7fdSSasha Neftin struct sk_buff *skb; 43673f1071cSAndre Guedes struct xdp_frame *xdpf; 43773f1071cSAndre Guedes }; 43813b5b7fdSSasha Neftin unsigned int bytecount; 43913b5b7fdSSasha Neftin u16 gso_segs; 44013b5b7fdSSasha Neftin __be16 protocol; 44113b5b7fdSSasha Neftin 44213b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_ADDR(dma); 44313b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_LEN(len); 44413b5b7fdSSasha Neftin u32 tx_flags; 44513b5b7fdSSasha Neftin }; 44613b5b7fdSSasha Neftin 44713b5b7fdSSasha Neftin struct igc_rx_buffer { 448fc9df2a0SAndre Guedes union { 449fc9df2a0SAndre Guedes struct { 45013b5b7fdSSasha Neftin dma_addr_t dma; 45113b5b7fdSSasha Neftin struct page *page; 45213b5b7fdSSasha Neftin #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 45313b5b7fdSSasha Neftin __u32 page_offset; 45413b5b7fdSSasha Neftin #else 45513b5b7fdSSasha Neftin __u16 page_offset; 45613b5b7fdSSasha Neftin #endif 45713b5b7fdSSasha Neftin __u16 pagecnt_bias; 45813b5b7fdSSasha Neftin }; 459fc9df2a0SAndre Guedes struct xdp_buff *xdp; 460fc9df2a0SAndre Guedes }; 461fc9df2a0SAndre Guedes }; 46213b5b7fdSSasha Neftin 463c9a11c23SSasha Neftin struct igc_q_vector { 464c9a11c23SSasha Neftin struct igc_adapter *adapter; /* backlink */ 4653df25e4cSSasha Neftin void __iomem *itr_register; 4663df25e4cSSasha Neftin u32 eims_value; /* EIMS mask value */ 4673df25e4cSSasha Neftin 4683df25e4cSSasha Neftin u16 itr_val; 4693df25e4cSSasha Neftin u8 set_itr; 4703df25e4cSSasha Neftin 4713df25e4cSSasha Neftin struct igc_ring_container rx, tx; 472c9a11c23SSasha Neftin 473c9a11c23SSasha Neftin struct napi_struct napi; 4743df25e4cSSasha Neftin 4753df25e4cSSasha Neftin struct rcu_head rcu; /* to avoid race with update stats on free */ 4763df25e4cSSasha Neftin char name[IFNAMSIZ + 9]; 4773df25e4cSSasha Neftin struct net_device poll_dev; 4783df25e4cSSasha Neftin 4793df25e4cSSasha Neftin /* for dynamic allocation of rings associated with this q_vector */ 480040efdb1SGustavo A. R. Silva struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 481c9a11c23SSasha Neftin }; 482c9a11c23SSasha Neftin 4836245c848SSasha Neftin enum igc_filter_match_flags { 4842b477d05SKurt Kanzenbach IGC_FILTER_FLAG_ETHER_TYPE = BIT(0), 4852b477d05SKurt Kanzenbach IGC_FILTER_FLAG_VLAN_TCI = BIT(1), 4862b477d05SKurt Kanzenbach IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2), 4872b477d05SKurt Kanzenbach IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3), 4882b477d05SKurt Kanzenbach IGC_FILTER_FLAG_USER_DATA = BIT(4), 4892b477d05SKurt Kanzenbach IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5), 4906245c848SSasha Neftin }; 4916245c848SSasha Neftin 49297700bc8SAndre Guedes struct igc_nfc_filter { 4936245c848SSasha Neftin u8 match_flags; 494c983e327SAndre Guedes u16 etype; 4952b477d05SKurt Kanzenbach __be16 vlan_etype; 496c983e327SAndre Guedes u16 vlan_tci; 4976245c848SSasha Neftin u8 src_addr[ETH_ALEN]; 4986245c848SSasha Neftin u8 dst_addr[ETH_ALEN]; 4992b477d05SKurt Kanzenbach u8 user_data[8]; 5002b477d05SKurt Kanzenbach u8 user_mask[8]; 5012b477d05SKurt Kanzenbach u8 flex_index; 5022b477d05SKurt Kanzenbach u8 rx_queue; 5032b477d05SKurt Kanzenbach u8 prio; 5042b477d05SKurt Kanzenbach u8 immediate_irq; 5052b477d05SKurt Kanzenbach u8 drop; 5066245c848SSasha Neftin }; 5076245c848SSasha Neftin 50897700bc8SAndre Guedes struct igc_nfc_rule { 509d957c601SAndre Guedes struct list_head list; 51097700bc8SAndre Guedes struct igc_nfc_filter filter; 511d3ba9e6fSAndre Guedes u32 location; 5126245c848SSasha Neftin u16 action; 51373744262SKurt Kanzenbach bool flex; 5146245c848SSasha Neftin }; 5156245c848SSasha Neftin 5162b477d05SKurt Kanzenbach /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority 5172b477d05SKurt Kanzenbach * based, 8 ethertype based and 32 Flex filter based rules. 518e087d3bbSAndre Guedes */ 5192b477d05SKurt Kanzenbach #define IGC_MAX_RXNFC_RULES 64 520c9a11c23SSasha Neftin 5216574631bSKurt Kanzenbach struct igc_flex_filter { 5226574631bSKurt Kanzenbach u8 index; 5236574631bSKurt Kanzenbach u8 data[128]; 5246574631bSKurt Kanzenbach u8 mask[16]; 5256574631bSKurt Kanzenbach u8 length; 5266574631bSKurt Kanzenbach u8 rx_queue; 5276574631bSKurt Kanzenbach u8 prio; 5286574631bSKurt Kanzenbach u8 immediate_irq; 5296574631bSKurt Kanzenbach u8 drop; 5306574631bSKurt Kanzenbach }; 5316574631bSKurt Kanzenbach 53213b5b7fdSSasha Neftin /* igc_desc_unused - calculate if we have unused descriptors */ 53313b5b7fdSSasha Neftin static inline u16 igc_desc_unused(const struct igc_ring *ring) 53413b5b7fdSSasha Neftin { 53513b5b7fdSSasha Neftin u16 ntc = ring->next_to_clean; 53613b5b7fdSSasha Neftin u16 ntu = ring->next_to_use; 53713b5b7fdSSasha Neftin 53813b5b7fdSSasha Neftin return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 53913b5b7fdSSasha Neftin } 54013b5b7fdSSasha Neftin 5415586838fSSasha Neftin static inline s32 igc_get_phy_info(struct igc_hw *hw) 5425586838fSSasha Neftin { 5435586838fSSasha Neftin if (hw->phy.ops.get_phy_info) 5445586838fSSasha Neftin return hw->phy.ops.get_phy_info(hw); 5455586838fSSasha Neftin 5465586838fSSasha Neftin return 0; 5475586838fSSasha Neftin } 5485586838fSSasha Neftin 5495586838fSSasha Neftin static inline s32 igc_reset_phy(struct igc_hw *hw) 5505586838fSSasha Neftin { 5515586838fSSasha Neftin if (hw->phy.ops.reset) 5525586838fSSasha Neftin return hw->phy.ops.reset(hw); 5535586838fSSasha Neftin 5545586838fSSasha Neftin return 0; 5555586838fSSasha Neftin } 5565586838fSSasha Neftin 55713b5b7fdSSasha Neftin static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 55813b5b7fdSSasha Neftin { 55913b5b7fdSSasha Neftin return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 56013b5b7fdSSasha Neftin } 56113b5b7fdSSasha Neftin 56213b5b7fdSSasha Neftin enum igc_ring_flags_t { 56313b5b7fdSSasha Neftin IGC_RING_FLAG_RX_3K_BUFFER, 56413b5b7fdSSasha Neftin IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 56513b5b7fdSSasha Neftin IGC_RING_FLAG_RX_SCTP_CSUM, 56613b5b7fdSSasha Neftin IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 56713b5b7fdSSasha Neftin IGC_RING_FLAG_TX_CTX_IDX, 568fc9df2a0SAndre Guedes IGC_RING_FLAG_TX_DETECT_HANG, 569fc9df2a0SAndre Guedes IGC_RING_FLAG_AF_XDP_ZC, 57013b5b7fdSSasha Neftin }; 57113b5b7fdSSasha Neftin 57213b5b7fdSSasha Neftin #define ring_uses_large_buffer(ring) \ 57313b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 5741bf33f71SAndre Guedes #define set_ring_uses_large_buffer(ring) \ 5751bf33f71SAndre Guedes set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 5761bf33f71SAndre Guedes #define clear_ring_uses_large_buffer(ring) \ 5771bf33f71SAndre Guedes clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 57813b5b7fdSSasha Neftin 57913b5b7fdSSasha Neftin #define ring_uses_build_skb(ring) \ 58013b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 58113b5b7fdSSasha Neftin 58213b5b7fdSSasha Neftin static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 58313b5b7fdSSasha Neftin { 58413b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 58513b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 58613b5b7fdSSasha Neftin return IGC_RXBUFFER_3072; 58713b5b7fdSSasha Neftin 58813b5b7fdSSasha Neftin if (ring_uses_build_skb(ring)) 58913b5b7fdSSasha Neftin return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 59013b5b7fdSSasha Neftin #endif 59113b5b7fdSSasha Neftin return IGC_RXBUFFER_2048; 59213b5b7fdSSasha Neftin } 59313b5b7fdSSasha Neftin 59413b5b7fdSSasha Neftin static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 59513b5b7fdSSasha Neftin { 59613b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 59713b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 59813b5b7fdSSasha Neftin return 1; 59913b5b7fdSSasha Neftin #endif 60013b5b7fdSSasha Neftin return 0; 60113b5b7fdSSasha Neftin } 60213b5b7fdSSasha Neftin 603208983f0SSasha Neftin static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 604208983f0SSasha Neftin { 605208983f0SSasha Neftin if (hw->phy.ops.read_reg) 606208983f0SSasha Neftin return hw->phy.ops.read_reg(hw, offset, data); 607208983f0SSasha Neftin 60805682a0aSTom Rix return -EOPNOTSUPP; 609208983f0SSasha Neftin } 610208983f0SSasha Neftin 6118c5ad0daSSasha Neftin void igc_reinit_locked(struct igc_adapter *); 61236fa2152SAndre Guedes struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 61336fa2152SAndre Guedes u32 location); 61436fa2152SAndre Guedes int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 61536fa2152SAndre Guedes void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 6168c5ad0daSSasha Neftin 6175f295805SVinicius Costa Gomes void igc_ptp_init(struct igc_adapter *adapter); 6185f295805SVinicius Costa Gomes void igc_ptp_reset(struct igc_adapter *adapter); 619a5136f76SSasha Neftin void igc_ptp_suspend(struct igc_adapter *adapter); 6205f295805SVinicius Costa Gomes void igc_ptp_stop(struct igc_adapter *adapter); 621e1ed4f92SAndre Guedes ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); 6225f295805SVinicius Costa Gomes int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 6235f295805SVinicius Costa Gomes int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 6242c344ae2SVinicius Costa Gomes void igc_ptp_tx_hang(struct igc_adapter *adapter); 625fec49eb4SVinicius Costa Gomes void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); 6262c344ae2SVinicius Costa Gomes 62713b5b7fdSSasha Neftin #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 62813b5b7fdSSasha Neftin 6290507ef8aSSasha Neftin #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 6300507ef8aSSasha Neftin 63113b5b7fdSSasha Neftin #define IGC_RX_DESC(R, i) \ 63213b5b7fdSSasha Neftin (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 63313b5b7fdSSasha Neftin #define IGC_TX_DESC(R, i) \ 63413b5b7fdSSasha Neftin (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 63513b5b7fdSSasha Neftin #define IGC_TX_CTXTDESC(R, i) \ 63613b5b7fdSSasha Neftin (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 63713b5b7fdSSasha Neftin 638d89f8841SSasha Neftin #endif /* _IGC_H_ */ 639