1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_H_ 5d89f8841SSasha Neftin #define _IGC_H_ 6d89f8841SSasha Neftin 7d89f8841SSasha Neftin #include <linux/kobject.h> 8d89f8841SSasha Neftin #include <linux/pci.h> 9d89f8841SSasha Neftin #include <linux/netdevice.h> 10d89f8841SSasha Neftin #include <linux/vmalloc.h> 11d89f8841SSasha Neftin #include <linux/ethtool.h> 12d89f8841SSasha Neftin #include <linux/sctp.h> 135f295805SVinicius Costa Gomes #include <linux/ptp_clock_kernel.h> 145f295805SVinicius Costa Gomes #include <linux/timecounter.h> 155f295805SVinicius Costa Gomes #include <linux/net_tstamp.h> 16d89f8841SSasha Neftin 17146740f9SSasha Neftin #include "igc_hw.h" 18146740f9SSasha Neftin 197df76bd1SAndre Guedes void igc_ethtool_set_ops(struct net_device *); 208c5ad0daSSasha Neftin 2189d35511SSasha Neftin /* Transmit and receive queues */ 2289d35511SSasha Neftin #define IGC_MAX_RX_QUEUES 4 2389d35511SSasha Neftin #define IGC_MAX_TX_QUEUES 4 2489d35511SSasha Neftin 2589d35511SSasha Neftin #define MAX_Q_VECTORS 8 2689d35511SSasha Neftin #define MAX_STD_JUMBO_FRAME_SIZE 9216 2789d35511SSasha Neftin 28b4d48d96SAndre Guedes #define MAX_ETYPE_FILTER 8 2989d35511SSasha Neftin #define IGC_RETA_SIZE 128 3089d35511SSasha Neftin 31750433d0SAndre Guedes enum igc_mac_filter_type { 32750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_DST = 0, 33750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_SRC 34750433d0SAndre Guedes }; 35750433d0SAndre Guedes 3689d35511SSasha Neftin struct igc_tx_queue_stats { 3789d35511SSasha Neftin u64 packets; 3889d35511SSasha Neftin u64 bytes; 3989d35511SSasha Neftin u64 restart_queue; 4089d35511SSasha Neftin u64 restart_queue2; 4189d35511SSasha Neftin }; 4289d35511SSasha Neftin 4389d35511SSasha Neftin struct igc_rx_queue_stats { 4489d35511SSasha Neftin u64 packets; 4589d35511SSasha Neftin u64 bytes; 4689d35511SSasha Neftin u64 drops; 4789d35511SSasha Neftin u64 csum_err; 4889d35511SSasha Neftin u64 alloc_failed; 4989d35511SSasha Neftin }; 5089d35511SSasha Neftin 5189d35511SSasha Neftin struct igc_rx_packet_stats { 5289d35511SSasha Neftin u64 ipv4_packets; /* IPv4 headers processed */ 5389d35511SSasha Neftin u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 5489d35511SSasha Neftin u64 ipv6_packets; /* IPv6 headers processed */ 5589d35511SSasha Neftin u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 5689d35511SSasha Neftin u64 tcp_packets; /* TCP headers processed */ 5789d35511SSasha Neftin u64 udp_packets; /* UDP headers processed */ 5889d35511SSasha Neftin u64 sctp_packets; /* SCTP headers processed */ 5989d35511SSasha Neftin u64 nfs_packets; /* NFS headers processe */ 6089d35511SSasha Neftin u64 other_packets; 6189d35511SSasha Neftin }; 6289d35511SSasha Neftin 6389d35511SSasha Neftin struct igc_ring_container { 6489d35511SSasha Neftin struct igc_ring *ring; /* pointer to linked list of rings */ 6589d35511SSasha Neftin unsigned int total_bytes; /* total bytes processed this int */ 6689d35511SSasha Neftin unsigned int total_packets; /* total packets processed this int */ 6789d35511SSasha Neftin u16 work_limit; /* total work allowed per interrupt */ 6889d35511SSasha Neftin u8 count; /* total number of rings in vector */ 6989d35511SSasha Neftin u8 itr; /* current ITR setting for ring */ 7089d35511SSasha Neftin }; 7189d35511SSasha Neftin 7289d35511SSasha Neftin struct igc_ring { 7389d35511SSasha Neftin struct igc_q_vector *q_vector; /* backlink to q_vector */ 7489d35511SSasha Neftin struct net_device *netdev; /* back pointer to net_device */ 7589d35511SSasha Neftin struct device *dev; /* device for dma mapping */ 7689d35511SSasha Neftin union { /* array of buffer info structs */ 7789d35511SSasha Neftin struct igc_tx_buffer *tx_buffer_info; 7889d35511SSasha Neftin struct igc_rx_buffer *rx_buffer_info; 7989d35511SSasha Neftin }; 8089d35511SSasha Neftin void *desc; /* descriptor ring memory */ 8189d35511SSasha Neftin unsigned long flags; /* ring specific flags */ 8289d35511SSasha Neftin void __iomem *tail; /* pointer to ring tail register */ 8389d35511SSasha Neftin dma_addr_t dma; /* phys address of the ring */ 8489d35511SSasha Neftin unsigned int size; /* length of desc. ring in bytes */ 8589d35511SSasha Neftin 8689d35511SSasha Neftin u16 count; /* number of desc. in the ring */ 8789d35511SSasha Neftin u8 queue_index; /* logical index of the ring*/ 8889d35511SSasha Neftin u8 reg_idx; /* physical index of the ring */ 8989d35511SSasha Neftin bool launchtime_enable; /* true if LaunchTime is enabled */ 9089d35511SSasha Neftin 9189d35511SSasha Neftin u32 start_time; 9289d35511SSasha Neftin u32 end_time; 9389d35511SSasha Neftin 9489d35511SSasha Neftin /* everything past this point are written often */ 9589d35511SSasha Neftin u16 next_to_clean; 9689d35511SSasha Neftin u16 next_to_use; 9789d35511SSasha Neftin u16 next_to_alloc; 9889d35511SSasha Neftin 9989d35511SSasha Neftin union { 10089d35511SSasha Neftin /* TX */ 10189d35511SSasha Neftin struct { 10289d35511SSasha Neftin struct igc_tx_queue_stats tx_stats; 10389d35511SSasha Neftin struct u64_stats_sync tx_syncp; 10489d35511SSasha Neftin struct u64_stats_sync tx_syncp2; 10589d35511SSasha Neftin }; 10689d35511SSasha Neftin /* RX */ 10789d35511SSasha Neftin struct { 10889d35511SSasha Neftin struct igc_rx_queue_stats rx_stats; 10989d35511SSasha Neftin struct igc_rx_packet_stats pkt_stats; 11089d35511SSasha Neftin struct u64_stats_sync rx_syncp; 11189d35511SSasha Neftin struct sk_buff *skb; 11289d35511SSasha Neftin }; 11389d35511SSasha Neftin }; 11489d35511SSasha Neftin } ____cacheline_internodealigned_in_smp; 11589d35511SSasha Neftin 11689d35511SSasha Neftin /* Board specific private data structure */ 11789d35511SSasha Neftin struct igc_adapter { 11889d35511SSasha Neftin struct net_device *netdev; 11989d35511SSasha Neftin 12089d35511SSasha Neftin unsigned long state; 12189d35511SSasha Neftin unsigned int flags; 12289d35511SSasha Neftin unsigned int num_q_vectors; 12389d35511SSasha Neftin 12489d35511SSasha Neftin struct msix_entry *msix_entries; 12589d35511SSasha Neftin 12689d35511SSasha Neftin /* TX */ 12789d35511SSasha Neftin u16 tx_work_limit; 12889d35511SSasha Neftin u32 tx_timeout_count; 12989d35511SSasha Neftin int num_tx_queues; 13089d35511SSasha Neftin struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 13189d35511SSasha Neftin 13289d35511SSasha Neftin /* RX */ 13389d35511SSasha Neftin int num_rx_queues; 13489d35511SSasha Neftin struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 13589d35511SSasha Neftin 13689d35511SSasha Neftin struct timer_list watchdog_timer; 13789d35511SSasha Neftin struct timer_list dma_err_timer; 13889d35511SSasha Neftin struct timer_list phy_info_timer; 13989d35511SSasha Neftin 14089d35511SSasha Neftin u32 wol; 14189d35511SSasha Neftin u32 en_mng_pt; 14289d35511SSasha Neftin u16 link_speed; 14389d35511SSasha Neftin u16 link_duplex; 14489d35511SSasha Neftin 14589d35511SSasha Neftin u8 port_num; 14689d35511SSasha Neftin 14789d35511SSasha Neftin u8 __iomem *io_addr; 14889d35511SSasha Neftin /* Interrupt Throttle Rate */ 14989d35511SSasha Neftin u32 rx_itr_setting; 15089d35511SSasha Neftin u32 tx_itr_setting; 15189d35511SSasha Neftin 15289d35511SSasha Neftin struct work_struct reset_task; 15389d35511SSasha Neftin struct work_struct watchdog_task; 15489d35511SSasha Neftin struct work_struct dma_err_task; 15589d35511SSasha Neftin bool fc_autoneg; 15689d35511SSasha Neftin 15789d35511SSasha Neftin u8 tx_timeout_factor; 15889d35511SSasha Neftin 15989d35511SSasha Neftin int msg_enable; 16089d35511SSasha Neftin u32 max_frame_size; 16189d35511SSasha Neftin u32 min_frame_size; 16289d35511SSasha Neftin 16389d35511SSasha Neftin ktime_t base_time; 16489d35511SSasha Neftin ktime_t cycle_time; 16589d35511SSasha Neftin 16689d35511SSasha Neftin /* OS defined structs */ 16789d35511SSasha Neftin struct pci_dev *pdev; 16889d35511SSasha Neftin /* lock for statistics */ 16989d35511SSasha Neftin spinlock_t stats64_lock; 17089d35511SSasha Neftin struct rtnl_link_stats64 stats64; 17189d35511SSasha Neftin 17289d35511SSasha Neftin /* structs defined in igc_hw.h */ 17389d35511SSasha Neftin struct igc_hw hw; 17489d35511SSasha Neftin struct igc_hw_stats stats; 17589d35511SSasha Neftin 17689d35511SSasha Neftin struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 17789d35511SSasha Neftin u32 eims_enable_mask; 17889d35511SSasha Neftin u32 eims_other; 17989d35511SSasha Neftin 18089d35511SSasha Neftin u16 tx_ring_count; 18189d35511SSasha Neftin u16 rx_ring_count; 18289d35511SSasha Neftin 18389d35511SSasha Neftin u32 tx_hwtstamp_timeouts; 18489d35511SSasha Neftin u32 tx_hwtstamp_skipped; 18589d35511SSasha Neftin u32 rx_hwtstamp_cleared; 18689d35511SSasha Neftin 18789d35511SSasha Neftin u32 rss_queues; 18889d35511SSasha Neftin u32 rss_indir_tbl_init; 18989d35511SSasha Neftin 19097700bc8SAndre Guedes /* Any access to elements in nfc_rule_list is protected by the 19197700bc8SAndre Guedes * nfc_rule_lock. 19297700bc8SAndre Guedes */ 19342fc5dc0SAndre Guedes struct mutex nfc_rule_lock; 194d957c601SAndre Guedes struct list_head nfc_rule_list; 19597700bc8SAndre Guedes unsigned int nfc_rule_count; 19689d35511SSasha Neftin 19789d35511SSasha Neftin u8 rss_indir_tbl[IGC_RETA_SIZE]; 19889d35511SSasha Neftin 19989d35511SSasha Neftin unsigned long link_check_timeout; 20089d35511SSasha Neftin struct igc_info ei; 20189d35511SSasha Neftin 202f026d8caSVitaly Lifshits u32 test_icr; 203f026d8caSVitaly Lifshits 20489d35511SSasha Neftin struct ptp_clock *ptp_clock; 20589d35511SSasha Neftin struct ptp_clock_info ptp_caps; 20689d35511SSasha Neftin struct work_struct ptp_tx_work; 20789d35511SSasha Neftin struct sk_buff *ptp_tx_skb; 20889d35511SSasha Neftin struct hwtstamp_config tstamp_config; 20989d35511SSasha Neftin unsigned long ptp_tx_start; 21089d35511SSasha Neftin unsigned long last_rx_ptp_check; 21189d35511SSasha Neftin unsigned long last_rx_timestamp; 21289d35511SSasha Neftin unsigned int ptp_flags; 21389d35511SSasha Neftin /* System time value lock */ 21489d35511SSasha Neftin spinlock_t tmreg_lock; 21589d35511SSasha Neftin struct cyclecounter cc; 21689d35511SSasha Neftin struct timecounter tc; 21789d35511SSasha Neftin }; 2188c5ad0daSSasha Neftin 2198c5ad0daSSasha Neftin void igc_up(struct igc_adapter *adapter); 2208c5ad0daSSasha Neftin void igc_down(struct igc_adapter *adapter); 221f026d8caSVitaly Lifshits int igc_open(struct net_device *netdev); 222f026d8caSVitaly Lifshits int igc_close(struct net_device *netdev); 2238c5ad0daSSasha Neftin int igc_setup_tx_resources(struct igc_ring *ring); 2248c5ad0daSSasha Neftin int igc_setup_rx_resources(struct igc_ring *ring); 2258c5ad0daSSasha Neftin void igc_free_tx_resources(struct igc_ring *ring); 2268c5ad0daSSasha Neftin void igc_free_rx_resources(struct igc_ring *ring); 2278c5ad0daSSasha Neftin unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 2288c5ad0daSSasha Neftin void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 2298c5ad0daSSasha Neftin const u32 max_rss_queues); 2308c5ad0daSSasha Neftin int igc_reinit_queues(struct igc_adapter *adapter); 2312121c271SSasha Neftin void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 2328c5ad0daSSasha Neftin bool igc_has_link(struct igc_adapter *adapter); 2338c5ad0daSSasha Neftin void igc_reset(struct igc_adapter *adapter); 2348c5ad0daSSasha Neftin int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 23536b9fea6SSasha Neftin void igc_update_stats(struct igc_adapter *adapter); 2368c5ad0daSSasha Neftin 2379c384ee3SSasha Neftin /* igc_dump declarations */ 2389c384ee3SSasha Neftin void igc_rings_dump(struct igc_adapter *adapter); 2399c384ee3SSasha Neftin void igc_regs_dump(struct igc_adapter *adapter); 2409c384ee3SSasha Neftin 241d89f8841SSasha Neftin extern char igc_driver_name[]; 242d89f8841SSasha Neftin extern char igc_driver_version[]; 243d89f8841SSasha Neftin 2448c5ad0daSSasha Neftin #define IGC_REGS_LEN 740 2458c5ad0daSSasha Neftin 2465f295805SVinicius Costa Gomes /* flags controlling PTP/1588 function */ 2475f295805SVinicius Costa Gomes #define IGC_PTP_ENABLED BIT(0) 2485f295805SVinicius Costa Gomes 24967082b53SSasha Neftin /* Flags definitions */ 2503df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSI BIT(0) 2518c5ad0daSSasha Neftin #define IGC_FLAG_QUEUE_PAIRS BIT(3) 2528c5ad0daSSasha Neftin #define IGC_FLAG_DMAC BIT(4) 2535f295805SVinicius Costa Gomes #define IGC_FLAG_PTP BIT(8) 254e055600dSSasha Neftin #define IGC_FLAG_WOL_SUPPORTED BIT(8) 2550507ef8aSSasha Neftin #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 256208983f0SSasha Neftin #define IGC_FLAG_MEDIA_RESET BIT(10) 257208983f0SSasha Neftin #define IGC_FLAG_MAS_ENABLE BIT(12) 2583df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSIX BIT(13) 2590507ef8aSSasha Neftin #define IGC_FLAG_VLAN_PROMISC BIT(15) 2608c5ad0daSSasha Neftin #define IGC_FLAG_RX_LEGACY BIT(16) 261ec50a9d4SVinicius Costa Gomes #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) 2623df25e4cSSasha Neftin 2632121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 2642121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 2652121c271SSasha Neftin 2662121c271SSasha Neftin #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 2672121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2682121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2692121c271SSasha Neftin 27064900e8fSSasha Neftin /* Interrupt defines */ 2713df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */ 2723df25e4cSSasha Neftin #define IGC_4K_ITR 980 2733df25e4cSSasha Neftin #define IGC_20K_ITR 196 2743df25e4cSSasha Neftin #define IGC_70K_ITR 56 2753df25e4cSSasha Neftin 2760507ef8aSSasha Neftin #define IGC_DEFAULT_ITR 3 /* dynamic */ 2770507ef8aSSasha Neftin #define IGC_MAX_ITR_USECS 10000 2780507ef8aSSasha Neftin #define IGC_MIN_ITR_USECS 10 2790507ef8aSSasha Neftin #define NON_Q_VECTORS 1 2800507ef8aSSasha Neftin #define MAX_MSIX_ENTRIES 10 2810507ef8aSSasha Neftin 2820507ef8aSSasha Neftin /* TX/RX descriptor defines */ 2830507ef8aSSasha Neftin #define IGC_DEFAULT_TXD 256 2840507ef8aSSasha Neftin #define IGC_DEFAULT_TX_WORK 128 2850507ef8aSSasha Neftin #define IGC_MIN_TXD 80 2860507ef8aSSasha Neftin #define IGC_MAX_TXD 4096 2870507ef8aSSasha Neftin 2880507ef8aSSasha Neftin #define IGC_DEFAULT_RXD 256 2890507ef8aSSasha Neftin #define IGC_MIN_RXD 80 2900507ef8aSSasha Neftin #define IGC_MAX_RXD 4096 2910507ef8aSSasha Neftin 29213b5b7fdSSasha Neftin /* Supported Rx Buffer Sizes */ 29313b5b7fdSSasha Neftin #define IGC_RXBUFFER_256 256 29413b5b7fdSSasha Neftin #define IGC_RXBUFFER_2048 2048 29513b5b7fdSSasha Neftin #define IGC_RXBUFFER_3072 3072 29613b5b7fdSSasha Neftin 2978c5ad0daSSasha Neftin #define AUTO_ALL_MODES 0 29813b5b7fdSSasha Neftin #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 29913b5b7fdSSasha Neftin 30081b05520SVinicius Costa Gomes /* Transmit and receive latency (for PTP timestamps) */ 301e7d0f4b3SSasha Neftin /* FIXME: These values were estimated using the ones that i225 has as 30281b05520SVinicius Costa Gomes * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 30381b05520SVinicius Costa Gomes * need to confirm them. 30481b05520SVinicius Costa Gomes */ 30581b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_10 9542 30681b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_100 1024 30781b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_1000 178 30881b05520SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_2500 64 30981b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_10 20662 31081b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_100 2213 31181b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_1000 448 31281b05520SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_2500 160 31381b05520SVinicius Costa Gomes 31413b5b7fdSSasha Neftin /* RX and TX descriptor control thresholds. 31513b5b7fdSSasha Neftin * PTHRESH - MAC will consider prefetch if it has fewer than this number of 31613b5b7fdSSasha Neftin * descriptors available in its onboard memory. 31713b5b7fdSSasha Neftin * Setting this to 0 disables RX descriptor prefetch. 31813b5b7fdSSasha Neftin * HTHRESH - MAC will only prefetch if there are at least this many descriptors 31913b5b7fdSSasha Neftin * available in host memory. 32013b5b7fdSSasha Neftin * If PTHRESH is 0, this should also be 0. 32113b5b7fdSSasha Neftin * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 32213b5b7fdSSasha Neftin * descriptors until either it has this many to write back, or the 32313b5b7fdSSasha Neftin * ITR timer expires. 32413b5b7fdSSasha Neftin */ 32513b5b7fdSSasha Neftin #define IGC_RX_PTHRESH 8 32613b5b7fdSSasha Neftin #define IGC_RX_HTHRESH 8 32713b5b7fdSSasha Neftin #define IGC_TX_PTHRESH 8 32813b5b7fdSSasha Neftin #define IGC_TX_HTHRESH 1 32913b5b7fdSSasha Neftin #define IGC_RX_WTHRESH 4 33013b5b7fdSSasha Neftin #define IGC_TX_WTHRESH 16 33113b5b7fdSSasha Neftin 33213b5b7fdSSasha Neftin #define IGC_RX_DMA_ATTR \ 33313b5b7fdSSasha Neftin (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 33413b5b7fdSSasha Neftin 33513b5b7fdSSasha Neftin #define IGC_TS_HDR_LEN 16 33613b5b7fdSSasha Neftin 33713b5b7fdSSasha Neftin #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 33813b5b7fdSSasha Neftin 33913b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 34013b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB \ 34113b5b7fdSSasha Neftin (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 34213b5b7fdSSasha Neftin #else 34313b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 34413b5b7fdSSasha Neftin #endif 34513b5b7fdSSasha Neftin 3460507ef8aSSasha Neftin /* How many Rx Buffers do we bundle into one write to the hardware ? */ 3470507ef8aSSasha Neftin #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 3480507ef8aSSasha Neftin 349d3ae3cfbSSasha Neftin /* VLAN info */ 350d3ae3cfbSSasha Neftin #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 351d3ae3cfbSSasha Neftin 3520507ef8aSSasha Neftin /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 3530507ef8aSSasha Neftin static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 3540507ef8aSSasha Neftin const u32 stat_err_bits) 3550507ef8aSSasha Neftin { 3560507ef8aSSasha Neftin return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 3570507ef8aSSasha Neftin } 3580507ef8aSSasha Neftin 359c9a11c23SSasha Neftin enum igc_state_t { 360c9a11c23SSasha Neftin __IGC_TESTING, 361c9a11c23SSasha Neftin __IGC_RESETTING, 362c9a11c23SSasha Neftin __IGC_DOWN, 363c9a11c23SSasha Neftin __IGC_PTP_TX_IN_PROGRESS, 364c9a11c23SSasha Neftin }; 365c9a11c23SSasha Neftin 3660507ef8aSSasha Neftin enum igc_tx_flags { 3670507ef8aSSasha Neftin /* cmd_type flags */ 3680507ef8aSSasha Neftin IGC_TX_FLAGS_VLAN = 0x01, 3690507ef8aSSasha Neftin IGC_TX_FLAGS_TSO = 0x02, 3700507ef8aSSasha Neftin IGC_TX_FLAGS_TSTAMP = 0x04, 3710507ef8aSSasha Neftin 3720507ef8aSSasha Neftin /* olinfo flags */ 3730507ef8aSSasha Neftin IGC_TX_FLAGS_IPV4 = 0x10, 3740507ef8aSSasha Neftin IGC_TX_FLAGS_CSUM = 0x20, 3750507ef8aSSasha Neftin }; 3760507ef8aSSasha Neftin 377ab405612SSasha Neftin enum igc_boards { 378ab405612SSasha Neftin board_base, 379ab405612SSasha Neftin }; 380ab405612SSasha Neftin 3810507ef8aSSasha Neftin /* The largest size we can write to the descriptor is 65535. In order to 3820507ef8aSSasha Neftin * maintain a power of two alignment we have to limit ourselves to 32K. 3830507ef8aSSasha Neftin */ 3840507ef8aSSasha Neftin #define IGC_MAX_TXD_PWR 15 3850507ef8aSSasha Neftin #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 3860507ef8aSSasha Neftin 3870507ef8aSSasha Neftin /* Tx Descriptors needed, worst case */ 3880507ef8aSSasha Neftin #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 3890507ef8aSSasha Neftin #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 3900507ef8aSSasha Neftin 39113b5b7fdSSasha Neftin /* wrapper around a pointer to a socket buffer, 39213b5b7fdSSasha Neftin * so a DMA handle can be stored along with the buffer 39313b5b7fdSSasha Neftin */ 39413b5b7fdSSasha Neftin struct igc_tx_buffer { 39513b5b7fdSSasha Neftin union igc_adv_tx_desc *next_to_watch; 39613b5b7fdSSasha Neftin unsigned long time_stamp; 39713b5b7fdSSasha Neftin struct sk_buff *skb; 39813b5b7fdSSasha Neftin unsigned int bytecount; 39913b5b7fdSSasha Neftin u16 gso_segs; 40013b5b7fdSSasha Neftin __be16 protocol; 40113b5b7fdSSasha Neftin 40213b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_ADDR(dma); 40313b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_LEN(len); 40413b5b7fdSSasha Neftin u32 tx_flags; 40513b5b7fdSSasha Neftin }; 40613b5b7fdSSasha Neftin 40713b5b7fdSSasha Neftin struct igc_rx_buffer { 40813b5b7fdSSasha Neftin dma_addr_t dma; 40913b5b7fdSSasha Neftin struct page *page; 41013b5b7fdSSasha Neftin #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 41113b5b7fdSSasha Neftin __u32 page_offset; 41213b5b7fdSSasha Neftin #else 41313b5b7fdSSasha Neftin __u16 page_offset; 41413b5b7fdSSasha Neftin #endif 41513b5b7fdSSasha Neftin __u16 pagecnt_bias; 41613b5b7fdSSasha Neftin }; 41713b5b7fdSSasha Neftin 418c9a11c23SSasha Neftin struct igc_q_vector { 419c9a11c23SSasha Neftin struct igc_adapter *adapter; /* backlink */ 4203df25e4cSSasha Neftin void __iomem *itr_register; 4213df25e4cSSasha Neftin u32 eims_value; /* EIMS mask value */ 4223df25e4cSSasha Neftin 4233df25e4cSSasha Neftin u16 itr_val; 4243df25e4cSSasha Neftin u8 set_itr; 4253df25e4cSSasha Neftin 4263df25e4cSSasha Neftin struct igc_ring_container rx, tx; 427c9a11c23SSasha Neftin 428c9a11c23SSasha Neftin struct napi_struct napi; 4293df25e4cSSasha Neftin 4303df25e4cSSasha Neftin struct rcu_head rcu; /* to avoid race with update stats on free */ 4313df25e4cSSasha Neftin char name[IFNAMSIZ + 9]; 4323df25e4cSSasha Neftin struct net_device poll_dev; 4333df25e4cSSasha Neftin 4343df25e4cSSasha Neftin /* for dynamic allocation of rings associated with this q_vector */ 435040efdb1SGustavo A. R. Silva struct igc_ring ring[] ____cacheline_internodealigned_in_smp; 436c9a11c23SSasha Neftin }; 437c9a11c23SSasha Neftin 4386245c848SSasha Neftin enum igc_filter_match_flags { 4396245c848SSasha Neftin IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 4406245c848SSasha Neftin IGC_FILTER_FLAG_VLAN_TCI = 0x2, 4416245c848SSasha Neftin IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 4426245c848SSasha Neftin IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 4436245c848SSasha Neftin }; 4446245c848SSasha Neftin 44597700bc8SAndre Guedes struct igc_nfc_filter { 4466245c848SSasha Neftin u8 match_flags; 447c983e327SAndre Guedes u16 etype; 448c983e327SAndre Guedes u16 vlan_tci; 4496245c848SSasha Neftin u8 src_addr[ETH_ALEN]; 4506245c848SSasha Neftin u8 dst_addr[ETH_ALEN]; 4516245c848SSasha Neftin }; 4526245c848SSasha Neftin 45397700bc8SAndre Guedes struct igc_nfc_rule { 454d957c601SAndre Guedes struct list_head list; 45597700bc8SAndre Guedes struct igc_nfc_filter filter; 456d3ba9e6fSAndre Guedes u32 location; 4576245c848SSasha Neftin u16 action; 4586245c848SSasha Neftin }; 4596245c848SSasha Neftin 46097700bc8SAndre Guedes #define IGC_MAX_RXNFC_RULES 16 461c9a11c23SSasha Neftin 46213b5b7fdSSasha Neftin /* igc_desc_unused - calculate if we have unused descriptors */ 46313b5b7fdSSasha Neftin static inline u16 igc_desc_unused(const struct igc_ring *ring) 46413b5b7fdSSasha Neftin { 46513b5b7fdSSasha Neftin u16 ntc = ring->next_to_clean; 46613b5b7fdSSasha Neftin u16 ntu = ring->next_to_use; 46713b5b7fdSSasha Neftin 46813b5b7fdSSasha Neftin return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 46913b5b7fdSSasha Neftin } 47013b5b7fdSSasha Neftin 4715586838fSSasha Neftin static inline s32 igc_get_phy_info(struct igc_hw *hw) 4725586838fSSasha Neftin { 4735586838fSSasha Neftin if (hw->phy.ops.get_phy_info) 4745586838fSSasha Neftin return hw->phy.ops.get_phy_info(hw); 4755586838fSSasha Neftin 4765586838fSSasha Neftin return 0; 4775586838fSSasha Neftin } 4785586838fSSasha Neftin 4795586838fSSasha Neftin static inline s32 igc_reset_phy(struct igc_hw *hw) 4805586838fSSasha Neftin { 4815586838fSSasha Neftin if (hw->phy.ops.reset) 4825586838fSSasha Neftin return hw->phy.ops.reset(hw); 4835586838fSSasha Neftin 4845586838fSSasha Neftin return 0; 4855586838fSSasha Neftin } 4865586838fSSasha Neftin 48713b5b7fdSSasha Neftin static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 48813b5b7fdSSasha Neftin { 48913b5b7fdSSasha Neftin return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 49013b5b7fdSSasha Neftin } 49113b5b7fdSSasha Neftin 49213b5b7fdSSasha Neftin enum igc_ring_flags_t { 49313b5b7fdSSasha Neftin IGC_RING_FLAG_RX_3K_BUFFER, 49413b5b7fdSSasha Neftin IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 49513b5b7fdSSasha Neftin IGC_RING_FLAG_RX_SCTP_CSUM, 49613b5b7fdSSasha Neftin IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 49713b5b7fdSSasha Neftin IGC_RING_FLAG_TX_CTX_IDX, 49813b5b7fdSSasha Neftin IGC_RING_FLAG_TX_DETECT_HANG 49913b5b7fdSSasha Neftin }; 50013b5b7fdSSasha Neftin 50113b5b7fdSSasha Neftin #define ring_uses_large_buffer(ring) \ 50213b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 50313b5b7fdSSasha Neftin 50413b5b7fdSSasha Neftin #define ring_uses_build_skb(ring) \ 50513b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 50613b5b7fdSSasha Neftin 50713b5b7fdSSasha Neftin static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 50813b5b7fdSSasha Neftin { 50913b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 51013b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 51113b5b7fdSSasha Neftin return IGC_RXBUFFER_3072; 51213b5b7fdSSasha Neftin 51313b5b7fdSSasha Neftin if (ring_uses_build_skb(ring)) 51413b5b7fdSSasha Neftin return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 51513b5b7fdSSasha Neftin #endif 51613b5b7fdSSasha Neftin return IGC_RXBUFFER_2048; 51713b5b7fdSSasha Neftin } 51813b5b7fdSSasha Neftin 51913b5b7fdSSasha Neftin static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 52013b5b7fdSSasha Neftin { 52113b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192) 52213b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring)) 52313b5b7fdSSasha Neftin return 1; 52413b5b7fdSSasha Neftin #endif 52513b5b7fdSSasha Neftin return 0; 52613b5b7fdSSasha Neftin } 52713b5b7fdSSasha Neftin 528208983f0SSasha Neftin static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 529208983f0SSasha Neftin { 530208983f0SSasha Neftin if (hw->phy.ops.read_reg) 531208983f0SSasha Neftin return hw->phy.ops.read_reg(hw, offset, data); 532208983f0SSasha Neftin 533208983f0SSasha Neftin return 0; 534208983f0SSasha Neftin } 535208983f0SSasha Neftin 5368c5ad0daSSasha Neftin void igc_reinit_locked(struct igc_adapter *); 53736fa2152SAndre Guedes struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 53836fa2152SAndre Guedes u32 location); 53936fa2152SAndre Guedes int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 54036fa2152SAndre Guedes void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); 5418c5ad0daSSasha Neftin 5425f295805SVinicius Costa Gomes void igc_ptp_init(struct igc_adapter *adapter); 5435f295805SVinicius Costa Gomes void igc_ptp_reset(struct igc_adapter *adapter); 544a5136f76SSasha Neftin void igc_ptp_suspend(struct igc_adapter *adapter); 5455f295805SVinicius Costa Gomes void igc_ptp_stop(struct igc_adapter *adapter); 54681b05520SVinicius Costa Gomes void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 54781b05520SVinicius Costa Gomes void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 54881b05520SVinicius Costa Gomes struct sk_buff *skb); 5495f295805SVinicius Costa Gomes int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 5505f295805SVinicius Costa Gomes int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 5512c344ae2SVinicius Costa Gomes void igc_ptp_tx_hang(struct igc_adapter *adapter); 5522c344ae2SVinicius Costa Gomes 55313b5b7fdSSasha Neftin #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 55413b5b7fdSSasha Neftin 5550507ef8aSSasha Neftin #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 5560507ef8aSSasha Neftin 55713b5b7fdSSasha Neftin #define IGC_RX_DESC(R, i) \ 55813b5b7fdSSasha Neftin (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 55913b5b7fdSSasha Neftin #define IGC_TX_DESC(R, i) \ 56013b5b7fdSSasha Neftin (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 56113b5b7fdSSasha Neftin #define IGC_TX_CTXTDESC(R, i) \ 56213b5b7fdSSasha Neftin (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 56313b5b7fdSSasha Neftin 564d89f8841SSasha Neftin #endif /* _IGC_H_ */ 565