1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */
2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */
3d89f8841SSasha Neftin
4d89f8841SSasha Neftin #ifndef _IGC_H_
5d89f8841SSasha Neftin #define _IGC_H_
6d89f8841SSasha Neftin
7d89f8841SSasha Neftin #include <linux/kobject.h>
8d89f8841SSasha Neftin #include <linux/pci.h>
9d89f8841SSasha Neftin #include <linux/netdevice.h>
10d89f8841SSasha Neftin #include <linux/vmalloc.h>
11d89f8841SSasha Neftin #include <linux/ethtool.h>
12d89f8841SSasha Neftin #include <linux/sctp.h>
135f295805SVinicius Costa Gomes #include <linux/ptp_clock_kernel.h>
145f295805SVinicius Costa Gomes #include <linux/timecounter.h>
155f295805SVinicius Costa Gomes #include <linux/net_tstamp.h>
1684214ab4SJesper Dangaard Brouer #include <linux/bitfield.h>
17175c2412SMuhammad Husaini Zulkifli #include <linux/hrtimer.h>
1892272ec4SJakub Kicinski #include <net/xdp.h>
19d89f8841SSasha Neftin
20146740f9SSasha Neftin #include "igc_hw.h"
21146740f9SSasha Neftin
227df76bd1SAndre Guedes void igc_ethtool_set_ops(struct net_device *);
238c5ad0daSSasha Neftin
2489d35511SSasha Neftin /* Transmit and receive queues */
2589d35511SSasha Neftin #define IGC_MAX_RX_QUEUES 4
2689d35511SSasha Neftin #define IGC_MAX_TX_QUEUES 4
2789d35511SSasha Neftin
2889d35511SSasha Neftin #define MAX_Q_VECTORS 8
2989d35511SSasha Neftin #define MAX_STD_JUMBO_FRAME_SIZE 9216
3089d35511SSasha Neftin
31b4d48d96SAndre Guedes #define MAX_ETYPE_FILTER 8
3289d35511SSasha Neftin #define IGC_RETA_SIZE 128
3389d35511SSasha Neftin
3487938851SEderson de Souza /* SDP support */
3587938851SEderson de Souza #define IGC_N_EXTTS 2
3687938851SEderson de Souza #define IGC_N_PEROUT 2
3787938851SEderson de Souza #define IGC_N_SDP 4
3887938851SEderson de Souza
396574631bSKurt Kanzenbach #define MAX_FLEX_FILTER 32
406574631bSKurt Kanzenbach
413ed247e7SVinicius Costa Gomes #define IGC_MAX_TX_TSTAMP_REGS 4
423ed247e7SVinicius Costa Gomes
43750433d0SAndre Guedes enum igc_mac_filter_type {
44750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_DST = 0,
45750433d0SAndre Guedes IGC_MAC_FILTER_TYPE_SRC
46750433d0SAndre Guedes };
47750433d0SAndre Guedes
4889d35511SSasha Neftin struct igc_tx_queue_stats {
4989d35511SSasha Neftin u64 packets;
5089d35511SSasha Neftin u64 bytes;
5189d35511SSasha Neftin u64 restart_queue;
5289d35511SSasha Neftin u64 restart_queue2;
5389d35511SSasha Neftin };
5489d35511SSasha Neftin
5589d35511SSasha Neftin struct igc_rx_queue_stats {
5689d35511SSasha Neftin u64 packets;
5789d35511SSasha Neftin u64 bytes;
5889d35511SSasha Neftin u64 drops;
5989d35511SSasha Neftin u64 csum_err;
6089d35511SSasha Neftin u64 alloc_failed;
6189d35511SSasha Neftin };
6289d35511SSasha Neftin
6389d35511SSasha Neftin struct igc_rx_packet_stats {
6489d35511SSasha Neftin u64 ipv4_packets; /* IPv4 headers processed */
6589d35511SSasha Neftin u64 ipv4e_packets; /* IPv4E headers with extensions processed */
6689d35511SSasha Neftin u64 ipv6_packets; /* IPv6 headers processed */
6789d35511SSasha Neftin u64 ipv6e_packets; /* IPv6E headers with extensions processed */
6889d35511SSasha Neftin u64 tcp_packets; /* TCP headers processed */
6989d35511SSasha Neftin u64 udp_packets; /* UDP headers processed */
7089d35511SSasha Neftin u64 sctp_packets; /* SCTP headers processed */
7189d35511SSasha Neftin u64 nfs_packets; /* NFS headers processe */
7289d35511SSasha Neftin u64 other_packets;
7389d35511SSasha Neftin };
7489d35511SSasha Neftin
753ed247e7SVinicius Costa Gomes struct igc_tx_timestamp_request {
763ed247e7SVinicius Costa Gomes struct sk_buff *skb; /* reference to the packet being timestamped */
773ed247e7SVinicius Costa Gomes unsigned long start; /* when the tstamp request started (jiffies) */
783ed247e7SVinicius Costa Gomes u32 mask; /* _TSYNCTXCTL_TXTT_{X} bit for this request */
793ed247e7SVinicius Costa Gomes u32 regl; /* which TXSTMPL_{X} register should be used */
803ed247e7SVinicius Costa Gomes u32 regh; /* which TXSTMPH_{X} register should be used */
813ed247e7SVinicius Costa Gomes u32 flags; /* flags that should be added to the tx_buffer */
823ed247e7SVinicius Costa Gomes };
833ed247e7SVinicius Costa Gomes
8489d35511SSasha Neftin struct igc_ring_container {
8589d35511SSasha Neftin struct igc_ring *ring; /* pointer to linked list of rings */
8689d35511SSasha Neftin unsigned int total_bytes; /* total bytes processed this int */
8789d35511SSasha Neftin unsigned int total_packets; /* total packets processed this int */
8889d35511SSasha Neftin u16 work_limit; /* total work allowed per interrupt */
8989d35511SSasha Neftin u8 count; /* total number of rings in vector */
9089d35511SSasha Neftin u8 itr; /* current ITR setting for ring */
9189d35511SSasha Neftin };
9289d35511SSasha Neftin
9389d35511SSasha Neftin struct igc_ring {
9489d35511SSasha Neftin struct igc_q_vector *q_vector; /* backlink to q_vector */
9589d35511SSasha Neftin struct net_device *netdev; /* back pointer to net_device */
9689d35511SSasha Neftin struct device *dev; /* device for dma mapping */
9789d35511SSasha Neftin union { /* array of buffer info structs */
9889d35511SSasha Neftin struct igc_tx_buffer *tx_buffer_info;
9989d35511SSasha Neftin struct igc_rx_buffer *rx_buffer_info;
10089d35511SSasha Neftin };
10189d35511SSasha Neftin void *desc; /* descriptor ring memory */
10289d35511SSasha Neftin unsigned long flags; /* ring specific flags */
10389d35511SSasha Neftin void __iomem *tail; /* pointer to ring tail register */
10489d35511SSasha Neftin dma_addr_t dma; /* phys address of the ring */
10589d35511SSasha Neftin unsigned int size; /* length of desc. ring in bytes */
10689d35511SSasha Neftin
10789d35511SSasha Neftin u16 count; /* number of desc. in the ring */
10889d35511SSasha Neftin u8 queue_index; /* logical index of the ring*/
10989d35511SSasha Neftin u8 reg_idx; /* physical index of the ring */
11089d35511SSasha Neftin bool launchtime_enable; /* true if LaunchTime is enabled */
111db0b124fSVinicius Costa Gomes ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
112db0b124fSVinicius Costa Gomes ktime_t last_ff_cycle; /* Last cycle with an active first flag */
11389d35511SSasha Neftin
11489d35511SSasha Neftin u32 start_time;
11589d35511SSasha Neftin u32 end_time;
11692a0dcb8STan Tee Min u32 max_sdu;
117175c2412SMuhammad Husaini Zulkifli bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
118175c2412SMuhammad Husaini Zulkifli bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
11989d35511SSasha Neftin
1201ab011b0SAravindhan Gunasekaran /* CBS parameters */
1211ab011b0SAravindhan Gunasekaran bool cbs_enable; /* indicates if CBS is enabled */
1221ab011b0SAravindhan Gunasekaran s32 idleslope; /* idleSlope in kbps */
1231ab011b0SAravindhan Gunasekaran s32 sendslope; /* sendSlope in kbps */
1241ab011b0SAravindhan Gunasekaran s32 hicredit; /* hiCredit in bytes */
1251ab011b0SAravindhan Gunasekaran s32 locredit; /* loCredit in bytes */
1261ab011b0SAravindhan Gunasekaran
12789d35511SSasha Neftin /* everything past this point are written often */
12889d35511SSasha Neftin u16 next_to_clean;
12989d35511SSasha Neftin u16 next_to_use;
13089d35511SSasha Neftin u16 next_to_alloc;
13189d35511SSasha Neftin
13289d35511SSasha Neftin union {
13389d35511SSasha Neftin /* TX */
13489d35511SSasha Neftin struct {
13589d35511SSasha Neftin struct igc_tx_queue_stats tx_stats;
13689d35511SSasha Neftin struct u64_stats_sync tx_syncp;
13789d35511SSasha Neftin struct u64_stats_sync tx_syncp2;
13889d35511SSasha Neftin };
13989d35511SSasha Neftin /* RX */
14089d35511SSasha Neftin struct {
14189d35511SSasha Neftin struct igc_rx_queue_stats rx_stats;
14289d35511SSasha Neftin struct igc_rx_packet_stats pkt_stats;
14389d35511SSasha Neftin struct u64_stats_sync rx_syncp;
14489d35511SSasha Neftin struct sk_buff *skb;
14589d35511SSasha Neftin };
14689d35511SSasha Neftin };
14773f1071cSAndre Guedes
14873f1071cSAndre Guedes struct xdp_rxq_info xdp_rxq;
149fc9df2a0SAndre Guedes struct xsk_buff_pool *xsk_pool;
15089d35511SSasha Neftin } ____cacheline_internodealigned_in_smp;
15189d35511SSasha Neftin
15289d35511SSasha Neftin /* Board specific private data structure */
15389d35511SSasha Neftin struct igc_adapter {
15489d35511SSasha Neftin struct net_device *netdev;
15589d35511SSasha Neftin
15693ec439aSSasha Neftin struct ethtool_eee eee;
15793ec439aSSasha Neftin u16 eee_advert;
15893ec439aSSasha Neftin
15989d35511SSasha Neftin unsigned long state;
16089d35511SSasha Neftin unsigned int flags;
16189d35511SSasha Neftin unsigned int num_q_vectors;
16289d35511SSasha Neftin
16389d35511SSasha Neftin struct msix_entry *msix_entries;
16489d35511SSasha Neftin
16589d35511SSasha Neftin /* TX */
16689d35511SSasha Neftin u16 tx_work_limit;
16789d35511SSasha Neftin u32 tx_timeout_count;
16889d35511SSasha Neftin int num_tx_queues;
16989d35511SSasha Neftin struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
17089d35511SSasha Neftin
17189d35511SSasha Neftin /* RX */
17289d35511SSasha Neftin int num_rx_queues;
17389d35511SSasha Neftin struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
17489d35511SSasha Neftin
17589d35511SSasha Neftin struct timer_list watchdog_timer;
17689d35511SSasha Neftin struct timer_list dma_err_timer;
17789d35511SSasha Neftin struct timer_list phy_info_timer;
178175c2412SMuhammad Husaini Zulkifli struct hrtimer hrtimer;
17989d35511SSasha Neftin
18089d35511SSasha Neftin u32 wol;
18189d35511SSasha Neftin u32 en_mng_pt;
18289d35511SSasha Neftin u16 link_speed;
18389d35511SSasha Neftin u16 link_duplex;
18489d35511SSasha Neftin
18589d35511SSasha Neftin u8 port_num;
18689d35511SSasha Neftin
18789d35511SSasha Neftin u8 __iomem *io_addr;
18889d35511SSasha Neftin /* Interrupt Throttle Rate */
18989d35511SSasha Neftin u32 rx_itr_setting;
19089d35511SSasha Neftin u32 tx_itr_setting;
19189d35511SSasha Neftin
19289d35511SSasha Neftin struct work_struct reset_task;
19389d35511SSasha Neftin struct work_struct watchdog_task;
19489d35511SSasha Neftin struct work_struct dma_err_task;
19589d35511SSasha Neftin bool fc_autoneg;
19689d35511SSasha Neftin
19789d35511SSasha Neftin u8 tx_timeout_factor;
19889d35511SSasha Neftin
19989d35511SSasha Neftin int msg_enable;
20089d35511SSasha Neftin u32 max_frame_size;
20189d35511SSasha Neftin u32 min_frame_size;
20289d35511SSasha Neftin
203ed89b74dSMuhammad Husaini Zulkifli int tc_setup_type;
20489d35511SSasha Neftin ktime_t base_time;
20589d35511SSasha Neftin ktime_t cycle_time;
2068046063dSFlorian Kauer bool taprio_offload_enable;
207ae4fe469SMuhammad Husaini Zulkifli u32 qbv_config_change_errors;
208175c2412SMuhammad Husaini Zulkifli bool qbv_transition;
209175c2412SMuhammad Husaini Zulkifli unsigned int qbv_count;
21006b41258SMuhammad Husaini Zulkifli /* Access to oper_gate_closed, admin_gate_closed and qbv_transition
21106b41258SMuhammad Husaini Zulkifli * are protected by the qbv_tx_lock.
21206b41258SMuhammad Husaini Zulkifli */
21306b41258SMuhammad Husaini Zulkifli spinlock_t qbv_tx_lock;
21489d35511SSasha Neftin
21589d35511SSasha Neftin /* OS defined structs */
21689d35511SSasha Neftin struct pci_dev *pdev;
21789d35511SSasha Neftin /* lock for statistics */
21889d35511SSasha Neftin spinlock_t stats64_lock;
21989d35511SSasha Neftin struct rtnl_link_stats64 stats64;
22089d35511SSasha Neftin
22189d35511SSasha Neftin /* structs defined in igc_hw.h */
22289d35511SSasha Neftin struct igc_hw hw;
22389d35511SSasha Neftin struct igc_hw_stats stats;
22489d35511SSasha Neftin
22589d35511SSasha Neftin struct igc_q_vector *q_vector[MAX_Q_VECTORS];
22689d35511SSasha Neftin u32 eims_enable_mask;
22789d35511SSasha Neftin u32 eims_other;
22889d35511SSasha Neftin
22989d35511SSasha Neftin u16 tx_ring_count;
23089d35511SSasha Neftin u16 rx_ring_count;
23189d35511SSasha Neftin
23289d35511SSasha Neftin u32 tx_hwtstamp_timeouts;
23389d35511SSasha Neftin u32 tx_hwtstamp_skipped;
23489d35511SSasha Neftin u32 rx_hwtstamp_cleared;
23589d35511SSasha Neftin
23689d35511SSasha Neftin u32 rss_queues;
23789d35511SSasha Neftin u32 rss_indir_tbl_init;
23889d35511SSasha Neftin
23997700bc8SAndre Guedes /* Any access to elements in nfc_rule_list is protected by the
24097700bc8SAndre Guedes * nfc_rule_lock.
24197700bc8SAndre Guedes */
24242fc5dc0SAndre Guedes struct mutex nfc_rule_lock;
243d957c601SAndre Guedes struct list_head nfc_rule_list;
24497700bc8SAndre Guedes unsigned int nfc_rule_count;
24589d35511SSasha Neftin
24689d35511SSasha Neftin u8 rss_indir_tbl[IGC_RETA_SIZE];
24789d35511SSasha Neftin
24889d35511SSasha Neftin unsigned long link_check_timeout;
24989d35511SSasha Neftin struct igc_info ei;
25089d35511SSasha Neftin
251f026d8caSVitaly Lifshits u32 test_icr;
252f026d8caSVitaly Lifshits
25389d35511SSasha Neftin struct ptp_clock *ptp_clock;
25489d35511SSasha Neftin struct ptp_clock_info ptp_caps;
2559c50e2b1SVinicius Costa Gomes /* Access to ptp_tx_skb and ptp_tx_start are protected by the
2569c50e2b1SVinicius Costa Gomes * ptp_tx_lock.
2579c50e2b1SVinicius Costa Gomes */
2589c50e2b1SVinicius Costa Gomes spinlock_t ptp_tx_lock;
2593ed247e7SVinicius Costa Gomes struct igc_tx_timestamp_request tx_tstamp[IGC_MAX_TX_TSTAMP_REGS];
26089d35511SSasha Neftin struct hwtstamp_config tstamp_config;
26189d35511SSasha Neftin unsigned int ptp_flags;
26289d35511SSasha Neftin /* System time value lock */
26389d35511SSasha Neftin spinlock_t tmreg_lock;
26489d35511SSasha Neftin struct cyclecounter cc;
26589d35511SSasha Neftin struct timecounter tc;
266b03c49cdSVinicius Costa Gomes struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
267b03c49cdSVinicius Costa Gomes ktime_t ptp_reset_start; /* Reset time in clock mono */
268a90ec848SVinicius Costa Gomes struct system_time_snapshot snapshot;
26901bb6129SSasha Neftin
27094f794d1SSasha Neftin char fw_version[32];
27126575105SAndre Guedes
27226575105SAndre Guedes struct bpf_prog *xdp_prog;
27364433e5bSEderson de Souza
27464433e5bSEderson de Souza bool pps_sys_wrap_on;
27587938851SEderson de Souza
27687938851SEderson de Souza struct ptp_pin_desc sdp_config[IGC_N_SDP];
27787938851SEderson de Souza struct {
27887938851SEderson de Souza struct timespec64 start;
27987938851SEderson de Souza struct timespec64 period;
28087938851SEderson de Souza } perout[IGC_N_PEROUT];
28189d35511SSasha Neftin };
2828c5ad0daSSasha Neftin
2838c5ad0daSSasha Neftin void igc_up(struct igc_adapter *adapter);
2848c5ad0daSSasha Neftin void igc_down(struct igc_adapter *adapter);
285f026d8caSVitaly Lifshits int igc_open(struct net_device *netdev);
286f026d8caSVitaly Lifshits int igc_close(struct net_device *netdev);
2878c5ad0daSSasha Neftin int igc_setup_tx_resources(struct igc_ring *ring);
2888c5ad0daSSasha Neftin int igc_setup_rx_resources(struct igc_ring *ring);
2898c5ad0daSSasha Neftin void igc_free_tx_resources(struct igc_ring *ring);
2908c5ad0daSSasha Neftin void igc_free_rx_resources(struct igc_ring *ring);
2918c5ad0daSSasha Neftin unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
2928c5ad0daSSasha Neftin void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
2938c5ad0daSSasha Neftin const u32 max_rss_queues);
2948c5ad0daSSasha Neftin int igc_reinit_queues(struct igc_adapter *adapter);
2952121c271SSasha Neftin void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
2968c5ad0daSSasha Neftin bool igc_has_link(struct igc_adapter *adapter);
2978c5ad0daSSasha Neftin void igc_reset(struct igc_adapter *adapter);
29836b9fea6SSasha Neftin void igc_update_stats(struct igc_adapter *adapter);
299fc9df2a0SAndre Guedes void igc_disable_rx_ring(struct igc_ring *ring);
300fc9df2a0SAndre Guedes void igc_enable_rx_ring(struct igc_ring *ring);
3019acf59a7SAndre Guedes void igc_disable_tx_ring(struct igc_ring *ring);
3029acf59a7SAndre Guedes void igc_enable_tx_ring(struct igc_ring *ring);
303fc9df2a0SAndre Guedes int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
3048c5ad0daSSasha Neftin
3059c384ee3SSasha Neftin /* igc_dump declarations */
3069c384ee3SSasha Neftin void igc_rings_dump(struct igc_adapter *adapter);
3079c384ee3SSasha Neftin void igc_regs_dump(struct igc_adapter *adapter);
3089c384ee3SSasha Neftin
309d89f8841SSasha Neftin extern char igc_driver_name[];
310d89f8841SSasha Neftin
3118c5ad0daSSasha Neftin #define IGC_REGS_LEN 740
3128c5ad0daSSasha Neftin
3135f295805SVinicius Costa Gomes /* flags controlling PTP/1588 function */
3145f295805SVinicius Costa Gomes #define IGC_PTP_ENABLED BIT(0)
3155f295805SVinicius Costa Gomes
31667082b53SSasha Neftin /* Flags definitions */
3173df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSI BIT(0)
3188c5ad0daSSasha Neftin #define IGC_FLAG_QUEUE_PAIRS BIT(3)
3198c5ad0daSSasha Neftin #define IGC_FLAG_DMAC BIT(4)
3205f295805SVinicius Costa Gomes #define IGC_FLAG_PTP BIT(8)
321e055600dSSasha Neftin #define IGC_FLAG_WOL_SUPPORTED BIT(8)
3220507ef8aSSasha Neftin #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
3233df25e4cSSasha Neftin #define IGC_FLAG_HAS_MSIX BIT(13)
32493ec439aSSasha Neftin #define IGC_FLAG_EEE BIT(14)
3250507ef8aSSasha Neftin #define IGC_FLAG_VLAN_PROMISC BIT(15)
3268c5ad0daSSasha Neftin #define IGC_FLAG_RX_LEGACY BIT(16)
327ec50a9d4SVinicius Costa Gomes #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
3281ab011b0SAravindhan Gunasekaran #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
3293df25e4cSSasha Neftin
3301ab011b0SAravindhan Gunasekaran #define IGC_FLAG_TSN_ANY_ENABLED \
3311ab011b0SAravindhan Gunasekaran (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
33261572d5fSVinicius Costa Gomes
3332121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
3342121c271SSasha Neftin #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
3352121c271SSasha Neftin
3362121c271SSasha Neftin #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
3372121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
3382121c271SSasha Neftin #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
3392121c271SSasha Neftin
34084214ab4SJesper Dangaard Brouer /* RX-desc Write-Back format RSS Type's */
34184214ab4SJesper Dangaard Brouer enum igc_rss_type_num {
34284214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_NO_HASH = 0,
34384214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
34484214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_IPV4 = 2,
34584214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
34684214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_IPV6_EX = 4,
34784214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_IPV6 = 5,
34884214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
34984214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
35084214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
35184214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
35284214ab4SJesper Dangaard Brouer IGC_RSS_TYPE_MAX = 10,
35384214ab4SJesper Dangaard Brouer };
35484214ab4SJesper Dangaard Brouer #define IGC_RSS_TYPE_MAX_TABLE 16
35584214ab4SJesper Dangaard Brouer #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
35684214ab4SJesper Dangaard Brouer
35784214ab4SJesper Dangaard Brouer /* igc_rss_type - Rx descriptor RSS type field */
igc_rss_type(const union igc_adv_rx_desc * rx_desc)35884214ab4SJesper Dangaard Brouer static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
35984214ab4SJesper Dangaard Brouer {
36084214ab4SJesper Dangaard Brouer /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
36184214ab4SJesper Dangaard Brouer * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
36284214ab4SJesper Dangaard Brouer * is slightly slower than via u32 (wb.lower.lo_dword.data)
36384214ab4SJesper Dangaard Brouer */
36484214ab4SJesper Dangaard Brouer return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
36584214ab4SJesper Dangaard Brouer }
36684214ab4SJesper Dangaard Brouer
36764900e8fSSasha Neftin /* Interrupt defines */
3683df25e4cSSasha Neftin #define IGC_START_ITR 648 /* ~6000 ints/sec */
3693df25e4cSSasha Neftin #define IGC_4K_ITR 980
3703df25e4cSSasha Neftin #define IGC_20K_ITR 196
3713df25e4cSSasha Neftin #define IGC_70K_ITR 56
3723df25e4cSSasha Neftin
3730507ef8aSSasha Neftin #define IGC_DEFAULT_ITR 3 /* dynamic */
3740507ef8aSSasha Neftin #define IGC_MAX_ITR_USECS 10000
3750507ef8aSSasha Neftin #define IGC_MIN_ITR_USECS 10
3760507ef8aSSasha Neftin #define NON_Q_VECTORS 1
3770507ef8aSSasha Neftin #define MAX_MSIX_ENTRIES 10
3780507ef8aSSasha Neftin
3790507ef8aSSasha Neftin /* TX/RX descriptor defines */
3800507ef8aSSasha Neftin #define IGC_DEFAULT_TXD 256
3810507ef8aSSasha Neftin #define IGC_DEFAULT_TX_WORK 128
3825aa48279SOlga Zaborska #define IGC_MIN_TXD 64
3830507ef8aSSasha Neftin #define IGC_MAX_TXD 4096
3840507ef8aSSasha Neftin
3850507ef8aSSasha Neftin #define IGC_DEFAULT_RXD 256
3865aa48279SOlga Zaborska #define IGC_MIN_RXD 64
3870507ef8aSSasha Neftin #define IGC_MAX_RXD 4096
3880507ef8aSSasha Neftin
38913b5b7fdSSasha Neftin /* Supported Rx Buffer Sizes */
39013b5b7fdSSasha Neftin #define IGC_RXBUFFER_256 256
39113b5b7fdSSasha Neftin #define IGC_RXBUFFER_2048 2048
39213b5b7fdSSasha Neftin #define IGC_RXBUFFER_3072 3072
39313b5b7fdSSasha Neftin
3948c5ad0daSSasha Neftin #define AUTO_ALL_MODES 0
39513b5b7fdSSasha Neftin #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
39613b5b7fdSSasha Neftin
39781b05520SVinicius Costa Gomes /* Transmit and receive latency (for PTP timestamps) */
398f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_10 240
399f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_100 58
400f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_1000 80
401f03369b9SVinicius Costa Gomes #define IGC_I225_TX_LATENCY_2500 1325
402f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_10 6450
403f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_100 185
404f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_1000 300
405f03369b9SVinicius Costa Gomes #define IGC_I225_RX_LATENCY_2500 1485
40681b05520SVinicius Costa Gomes
40713b5b7fdSSasha Neftin /* RX and TX descriptor control thresholds.
40813b5b7fdSSasha Neftin * PTHRESH - MAC will consider prefetch if it has fewer than this number of
40913b5b7fdSSasha Neftin * descriptors available in its onboard memory.
41013b5b7fdSSasha Neftin * Setting this to 0 disables RX descriptor prefetch.
41113b5b7fdSSasha Neftin * HTHRESH - MAC will only prefetch if there are at least this many descriptors
41213b5b7fdSSasha Neftin * available in host memory.
41313b5b7fdSSasha Neftin * If PTHRESH is 0, this should also be 0.
41413b5b7fdSSasha Neftin * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
41513b5b7fdSSasha Neftin * descriptors until either it has this many to write back, or the
41613b5b7fdSSasha Neftin * ITR timer expires.
41713b5b7fdSSasha Neftin */
41813b5b7fdSSasha Neftin #define IGC_RX_PTHRESH 8
41913b5b7fdSSasha Neftin #define IGC_RX_HTHRESH 8
42013b5b7fdSSasha Neftin #define IGC_TX_PTHRESH 8
42113b5b7fdSSasha Neftin #define IGC_TX_HTHRESH 1
42213b5b7fdSSasha Neftin #define IGC_RX_WTHRESH 4
42313b5b7fdSSasha Neftin #define IGC_TX_WTHRESH 16
42413b5b7fdSSasha Neftin
42513b5b7fdSSasha Neftin #define IGC_RX_DMA_ATTR \
42613b5b7fdSSasha Neftin (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
42713b5b7fdSSasha Neftin
42813b5b7fdSSasha Neftin #define IGC_TS_HDR_LEN 16
42913b5b7fdSSasha Neftin
43013b5b7fdSSasha Neftin #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
43113b5b7fdSSasha Neftin
43213b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192)
43313b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB \
43413b5b7fdSSasha Neftin (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
43513b5b7fdSSasha Neftin #else
43613b5b7fdSSasha Neftin #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
43713b5b7fdSSasha Neftin #endif
43813b5b7fdSSasha Neftin
4390507ef8aSSasha Neftin /* How many Rx Buffers do we bundle into one write to the hardware ? */
4400507ef8aSSasha Neftin #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
4410507ef8aSSasha Neftin
442d3ae3cfbSSasha Neftin /* VLAN info */
443d3ae3cfbSSasha Neftin #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
4448d744963SMuhammad Husaini Zulkifli #define IGC_TX_FLAGS_VLAN_SHIFT 16
445d3ae3cfbSSasha Neftin
4460507ef8aSSasha Neftin /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)4470507ef8aSSasha Neftin static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
4480507ef8aSSasha Neftin const u32 stat_err_bits)
4490507ef8aSSasha Neftin {
4500507ef8aSSasha Neftin return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
4510507ef8aSSasha Neftin }
4520507ef8aSSasha Neftin
453c9a11c23SSasha Neftin enum igc_state_t {
454c9a11c23SSasha Neftin __IGC_TESTING,
455c9a11c23SSasha Neftin __IGC_RESETTING,
456c9a11c23SSasha Neftin __IGC_DOWN,
457c9a11c23SSasha Neftin };
458c9a11c23SSasha Neftin
4590507ef8aSSasha Neftin enum igc_tx_flags {
4600507ef8aSSasha Neftin /* cmd_type flags */
4610507ef8aSSasha Neftin IGC_TX_FLAGS_VLAN = 0x01,
4620507ef8aSSasha Neftin IGC_TX_FLAGS_TSO = 0x02,
4630507ef8aSSasha Neftin IGC_TX_FLAGS_TSTAMP = 0x04,
4640507ef8aSSasha Neftin
4650507ef8aSSasha Neftin /* olinfo flags */
4660507ef8aSSasha Neftin IGC_TX_FLAGS_IPV4 = 0x10,
4670507ef8aSSasha Neftin IGC_TX_FLAGS_CSUM = 0x20,
4683ed247e7SVinicius Costa Gomes
4693ed247e7SVinicius Costa Gomes IGC_TX_FLAGS_TSTAMP_1 = 0x100,
4703ed247e7SVinicius Costa Gomes IGC_TX_FLAGS_TSTAMP_2 = 0x200,
4713ed247e7SVinicius Costa Gomes IGC_TX_FLAGS_TSTAMP_3 = 0x400,
4720507ef8aSSasha Neftin };
4730507ef8aSSasha Neftin
474ab405612SSasha Neftin enum igc_boards {
475ab405612SSasha Neftin board_base,
476ab405612SSasha Neftin };
477ab405612SSasha Neftin
4780507ef8aSSasha Neftin /* The largest size we can write to the descriptor is 65535. In order to
4790507ef8aSSasha Neftin * maintain a power of two alignment we have to limit ourselves to 32K.
4800507ef8aSSasha Neftin */
4810507ef8aSSasha Neftin #define IGC_MAX_TXD_PWR 15
4820507ef8aSSasha Neftin #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
4830507ef8aSSasha Neftin
4840507ef8aSSasha Neftin /* Tx Descriptors needed, worst case */
4850507ef8aSSasha Neftin #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
4860507ef8aSSasha Neftin #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
4870507ef8aSSasha Neftin
488859b4dfaSAndre Guedes enum igc_tx_buffer_type {
489859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_SKB,
490859b4dfaSAndre Guedes IGC_TX_BUFFER_TYPE_XDP,
4919acf59a7SAndre Guedes IGC_TX_BUFFER_TYPE_XSK,
492859b4dfaSAndre Guedes };
493859b4dfaSAndre Guedes
49413b5b7fdSSasha Neftin /* wrapper around a pointer to a socket buffer,
49513b5b7fdSSasha Neftin * so a DMA handle can be stored along with the buffer
49613b5b7fdSSasha Neftin */
49713b5b7fdSSasha Neftin struct igc_tx_buffer {
49813b5b7fdSSasha Neftin union igc_adv_tx_desc *next_to_watch;
49913b5b7fdSSasha Neftin unsigned long time_stamp;
500859b4dfaSAndre Guedes enum igc_tx_buffer_type type;
50173f1071cSAndre Guedes union {
50213b5b7fdSSasha Neftin struct sk_buff *skb;
50373f1071cSAndre Guedes struct xdp_frame *xdpf;
50473f1071cSAndre Guedes };
50513b5b7fdSSasha Neftin unsigned int bytecount;
50613b5b7fdSSasha Neftin u16 gso_segs;
50713b5b7fdSSasha Neftin __be16 protocol;
50813b5b7fdSSasha Neftin
50913b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_ADDR(dma);
51013b5b7fdSSasha Neftin DEFINE_DMA_UNMAP_LEN(len);
51113b5b7fdSSasha Neftin u32 tx_flags;
51213b5b7fdSSasha Neftin };
51313b5b7fdSSasha Neftin
51413b5b7fdSSasha Neftin struct igc_rx_buffer {
515fc9df2a0SAndre Guedes union {
516fc9df2a0SAndre Guedes struct {
51713b5b7fdSSasha Neftin dma_addr_t dma;
51813b5b7fdSSasha Neftin struct page *page;
51913b5b7fdSSasha Neftin #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
52013b5b7fdSSasha Neftin __u32 page_offset;
52113b5b7fdSSasha Neftin #else
52213b5b7fdSSasha Neftin __u16 page_offset;
52313b5b7fdSSasha Neftin #endif
52413b5b7fdSSasha Neftin __u16 pagecnt_bias;
52513b5b7fdSSasha Neftin };
526fc9df2a0SAndre Guedes struct xdp_buff *xdp;
527fc9df2a0SAndre Guedes };
528fc9df2a0SAndre Guedes };
52913b5b7fdSSasha Neftin
53073b7123dSJesper Dangaard Brouer /* context wrapper around xdp_buff to provide access to descriptor metadata */
53173b7123dSJesper Dangaard Brouer struct igc_xdp_buff {
53273b7123dSJesper Dangaard Brouer struct xdp_buff xdp;
5338416814fSJesper Dangaard Brouer union igc_adv_rx_desc *rx_desc;
534d6772667SJesper Dangaard Brouer ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */
53573b7123dSJesper Dangaard Brouer };
53673b7123dSJesper Dangaard Brouer
537c9a11c23SSasha Neftin struct igc_q_vector {
538c9a11c23SSasha Neftin struct igc_adapter *adapter; /* backlink */
5393df25e4cSSasha Neftin void __iomem *itr_register;
5403df25e4cSSasha Neftin u32 eims_value; /* EIMS mask value */
5413df25e4cSSasha Neftin
5423df25e4cSSasha Neftin u16 itr_val;
5433df25e4cSSasha Neftin u8 set_itr;
5443df25e4cSSasha Neftin
5453df25e4cSSasha Neftin struct igc_ring_container rx, tx;
546c9a11c23SSasha Neftin
547c9a11c23SSasha Neftin struct napi_struct napi;
5483df25e4cSSasha Neftin
5493df25e4cSSasha Neftin struct rcu_head rcu; /* to avoid race with update stats on free */
5503df25e4cSSasha Neftin char name[IFNAMSIZ + 9];
5513df25e4cSSasha Neftin struct net_device poll_dev;
5523df25e4cSSasha Neftin
5533df25e4cSSasha Neftin /* for dynamic allocation of rings associated with this q_vector */
554040efdb1SGustavo A. R. Silva struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
555c9a11c23SSasha Neftin };
556c9a11c23SSasha Neftin
5576245c848SSasha Neftin enum igc_filter_match_flags {
5582b477d05SKurt Kanzenbach IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
5592b477d05SKurt Kanzenbach IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
5602b477d05SKurt Kanzenbach IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
5612b477d05SKurt Kanzenbach IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
5622b477d05SKurt Kanzenbach IGC_FILTER_FLAG_USER_DATA = BIT(4),
5632b477d05SKurt Kanzenbach IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
5646245c848SSasha Neftin };
5656245c848SSasha Neftin
56697700bc8SAndre Guedes struct igc_nfc_filter {
5676245c848SSasha Neftin u8 match_flags;
568c983e327SAndre Guedes u16 etype;
5692b477d05SKurt Kanzenbach __be16 vlan_etype;
570c983e327SAndre Guedes u16 vlan_tci;
571*08144bacSKurt Kanzenbach u16 vlan_tci_mask;
5726245c848SSasha Neftin u8 src_addr[ETH_ALEN];
5736245c848SSasha Neftin u8 dst_addr[ETH_ALEN];
5742b477d05SKurt Kanzenbach u8 user_data[8];
5752b477d05SKurt Kanzenbach u8 user_mask[8];
5762b477d05SKurt Kanzenbach u8 flex_index;
5772b477d05SKurt Kanzenbach u8 rx_queue;
5782b477d05SKurt Kanzenbach u8 prio;
5792b477d05SKurt Kanzenbach u8 immediate_irq;
5802b477d05SKurt Kanzenbach u8 drop;
5816245c848SSasha Neftin };
5826245c848SSasha Neftin
58397700bc8SAndre Guedes struct igc_nfc_rule {
584d957c601SAndre Guedes struct list_head list;
58597700bc8SAndre Guedes struct igc_nfc_filter filter;
586d3ba9e6fSAndre Guedes u32 location;
5876245c848SSasha Neftin u16 action;
58873744262SKurt Kanzenbach bool flex;
5896245c848SSasha Neftin };
5906245c848SSasha Neftin
5912b477d05SKurt Kanzenbach /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
5922b477d05SKurt Kanzenbach * based, 8 ethertype based and 32 Flex filter based rules.
593e087d3bbSAndre Guedes */
5942b477d05SKurt Kanzenbach #define IGC_MAX_RXNFC_RULES 64
595c9a11c23SSasha Neftin
5966574631bSKurt Kanzenbach struct igc_flex_filter {
5976574631bSKurt Kanzenbach u8 index;
5986574631bSKurt Kanzenbach u8 data[128];
5996574631bSKurt Kanzenbach u8 mask[16];
6006574631bSKurt Kanzenbach u8 length;
6016574631bSKurt Kanzenbach u8 rx_queue;
6026574631bSKurt Kanzenbach u8 prio;
6036574631bSKurt Kanzenbach u8 immediate_irq;
6046574631bSKurt Kanzenbach u8 drop;
6056574631bSKurt Kanzenbach };
6066574631bSKurt Kanzenbach
60713b5b7fdSSasha Neftin /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)60813b5b7fdSSasha Neftin static inline u16 igc_desc_unused(const struct igc_ring *ring)
60913b5b7fdSSasha Neftin {
61013b5b7fdSSasha Neftin u16 ntc = ring->next_to_clean;
61113b5b7fdSSasha Neftin u16 ntu = ring->next_to_use;
61213b5b7fdSSasha Neftin
61313b5b7fdSSasha Neftin return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
61413b5b7fdSSasha Neftin }
61513b5b7fdSSasha Neftin
igc_get_phy_info(struct igc_hw * hw)6165586838fSSasha Neftin static inline s32 igc_get_phy_info(struct igc_hw *hw)
6175586838fSSasha Neftin {
6185586838fSSasha Neftin if (hw->phy.ops.get_phy_info)
6195586838fSSasha Neftin return hw->phy.ops.get_phy_info(hw);
6205586838fSSasha Neftin
6215586838fSSasha Neftin return 0;
6225586838fSSasha Neftin }
6235586838fSSasha Neftin
igc_reset_phy(struct igc_hw * hw)6245586838fSSasha Neftin static inline s32 igc_reset_phy(struct igc_hw *hw)
6255586838fSSasha Neftin {
6265586838fSSasha Neftin if (hw->phy.ops.reset)
6275586838fSSasha Neftin return hw->phy.ops.reset(hw);
6285586838fSSasha Neftin
6295586838fSSasha Neftin return 0;
6305586838fSSasha Neftin }
6315586838fSSasha Neftin
txring_txq(const struct igc_ring * tx_ring)63213b5b7fdSSasha Neftin static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
63313b5b7fdSSasha Neftin {
63413b5b7fdSSasha Neftin return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
63513b5b7fdSSasha Neftin }
63613b5b7fdSSasha Neftin
63713b5b7fdSSasha Neftin enum igc_ring_flags_t {
63813b5b7fdSSasha Neftin IGC_RING_FLAG_RX_3K_BUFFER,
63913b5b7fdSSasha Neftin IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
64013b5b7fdSSasha Neftin IGC_RING_FLAG_RX_SCTP_CSUM,
64113b5b7fdSSasha Neftin IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
64213b5b7fdSSasha Neftin IGC_RING_FLAG_TX_CTX_IDX,
643fc9df2a0SAndre Guedes IGC_RING_FLAG_TX_DETECT_HANG,
644fc9df2a0SAndre Guedes IGC_RING_FLAG_AF_XDP_ZC,
645ce58c7ccSVinicius Costa Gomes IGC_RING_FLAG_TX_HWTSTAMP,
64613b5b7fdSSasha Neftin };
64713b5b7fdSSasha Neftin
64813b5b7fdSSasha Neftin #define ring_uses_large_buffer(ring) \
64913b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
6501bf33f71SAndre Guedes #define set_ring_uses_large_buffer(ring) \
6511bf33f71SAndre Guedes set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
6521bf33f71SAndre Guedes #define clear_ring_uses_large_buffer(ring) \
6531bf33f71SAndre Guedes clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
65413b5b7fdSSasha Neftin
65513b5b7fdSSasha Neftin #define ring_uses_build_skb(ring) \
65613b5b7fdSSasha Neftin test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
65713b5b7fdSSasha Neftin
igc_rx_bufsz(struct igc_ring * ring)65813b5b7fdSSasha Neftin static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
65913b5b7fdSSasha Neftin {
66013b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192)
66113b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring))
66213b5b7fdSSasha Neftin return IGC_RXBUFFER_3072;
66313b5b7fdSSasha Neftin
66413b5b7fdSSasha Neftin if (ring_uses_build_skb(ring))
66513b5b7fdSSasha Neftin return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
66613b5b7fdSSasha Neftin #endif
66713b5b7fdSSasha Neftin return IGC_RXBUFFER_2048;
66813b5b7fdSSasha Neftin }
66913b5b7fdSSasha Neftin
igc_rx_pg_order(struct igc_ring * ring)67013b5b7fdSSasha Neftin static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
67113b5b7fdSSasha Neftin {
67213b5b7fdSSasha Neftin #if (PAGE_SIZE < 8192)
67313b5b7fdSSasha Neftin if (ring_uses_large_buffer(ring))
67413b5b7fdSSasha Neftin return 1;
67513b5b7fdSSasha Neftin #endif
67613b5b7fdSSasha Neftin return 0;
67713b5b7fdSSasha Neftin }
67813b5b7fdSSasha Neftin
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)679208983f0SSasha Neftin static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
680208983f0SSasha Neftin {
681208983f0SSasha Neftin if (hw->phy.ops.read_reg)
682208983f0SSasha Neftin return hw->phy.ops.read_reg(hw, offset, data);
683208983f0SSasha Neftin
68405682a0aSTom Rix return -EOPNOTSUPP;
685208983f0SSasha Neftin }
686208983f0SSasha Neftin
6878c5ad0daSSasha Neftin void igc_reinit_locked(struct igc_adapter *);
68836fa2152SAndre Guedes struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
68936fa2152SAndre Guedes u32 location);
69036fa2152SAndre Guedes int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
69136fa2152SAndre Guedes void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
6928c5ad0daSSasha Neftin
6935f295805SVinicius Costa Gomes void igc_ptp_init(struct igc_adapter *adapter);
6945f295805SVinicius Costa Gomes void igc_ptp_reset(struct igc_adapter *adapter);
695a5136f76SSasha Neftin void igc_ptp_suspend(struct igc_adapter *adapter);
6965f295805SVinicius Costa Gomes void igc_ptp_stop(struct igc_adapter *adapter);
697e1ed4f92SAndre Guedes ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
6985f295805SVinicius Costa Gomes int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
6995f295805SVinicius Costa Gomes int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
7002c344ae2SVinicius Costa Gomes void igc_ptp_tx_hang(struct igc_adapter *adapter);
701fec49eb4SVinicius Costa Gomes void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
702afa14158SVinicius Costa Gomes void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter);
7032c344ae2SVinicius Costa Gomes
70413b5b7fdSSasha Neftin #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
70513b5b7fdSSasha Neftin
7060507ef8aSSasha Neftin #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
7070507ef8aSSasha Neftin
70813b5b7fdSSasha Neftin #define IGC_RX_DESC(R, i) \
70913b5b7fdSSasha Neftin (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
71013b5b7fdSSasha Neftin #define IGC_TX_DESC(R, i) \
71113b5b7fdSSasha Neftin (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
71213b5b7fdSSasha Neftin #define IGC_TX_CTXTDESC(R, i) \
71313b5b7fdSSasha Neftin (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
71413b5b7fdSSasha Neftin
715d89f8841SSasha Neftin #endif /* _IGC_H_ */
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