1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 2 * 3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/pci.h> 21 #include <linux/ptp_classify.h> 22 23 #include "igb.h" 24 25 #define INCVALUE_MASK 0x7fffffff 26 #define ISGN 0x80000000 27 28 /* The 82580 timesync updates the system timer every 8ns by 8ns, 29 * and this update value cannot be reprogrammed. 30 * 31 * Neither the 82576 nor the 82580 offer registers wide enough to hold 32 * nanoseconds time values for very long. For the 82580, SYSTIM always 33 * counts nanoseconds, but the upper 24 bits are not availible. The 34 * frequency is adjusted by changing the 32 bit fractional nanoseconds 35 * register, TIMINCA. 36 * 37 * For the 82576, the SYSTIM register time unit is affect by the 38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 39 * field are needed to provide the nominal 16 nanosecond period, 40 * leaving 19 bits for fractional nanoseconds. 41 * 42 * We scale the NIC clock cycle by a large factor so that relatively 43 * small clock corrections can be added or subtracted at each clock 44 * tick. The drawbacks of a large factor are a) that the clock 45 * register overflows more quickly (not such a big deal) and b) that 46 * the increment per tick has to fit into 24 bits. As a result we 47 * need to use a shift of 19 so we can fit a value of 16 into the 48 * TIMINCA register. 49 * 50 * 51 * SYSTIMH SYSTIML 52 * +--------------+ +---+---+------+ 53 * 82576 | 32 | | 8 | 5 | 19 | 54 * +--------------+ +---+---+------+ 55 * \________ 45 bits _______/ fract 56 * 57 * +----------+---+ +--------------+ 58 * 82580 | 24 | 8 | | 32 | 59 * +----------+---+ +--------------+ 60 * reserved \______ 40 bits _____/ 61 * 62 * 63 * The 45 bit 82576 SYSTIM overflows every 64 * 2^45 * 10^-9 / 3600 = 9.77 hours. 65 * 66 * The 40 bit 82580 SYSTIM overflows every 67 * 2^40 * 10^-9 / 60 = 18.3 minutes. 68 */ 69 70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 71 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 72 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 73 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) 74 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 75 #define IGB_NBITS_82580 40 76 77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 78 79 /* SYSTIM read access for the 82576 */ 80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) 81 { 82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 83 struct e1000_hw *hw = &igb->hw; 84 u64 val; 85 u32 lo, hi; 86 87 lo = rd32(E1000_SYSTIML); 88 hi = rd32(E1000_SYSTIMH); 89 90 val = ((u64) hi) << 32; 91 val |= lo; 92 93 return val; 94 } 95 96 /* SYSTIM read access for the 82580 */ 97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) 98 { 99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 100 struct e1000_hw *hw = &igb->hw; 101 u32 lo, hi; 102 u64 val; 103 104 /* The timestamp latches on lowest register read. For the 82580 105 * the lowest register is SYSTIMR instead of SYSTIML. However we only 106 * need to provide nanosecond resolution, so we just ignore it. 107 */ 108 rd32(E1000_SYSTIMR); 109 lo = rd32(E1000_SYSTIML); 110 hi = rd32(E1000_SYSTIMH); 111 112 val = ((u64) hi) << 32; 113 val |= lo; 114 115 return val; 116 } 117 118 /* SYSTIM read access for I210/I211 */ 119 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) 120 { 121 struct e1000_hw *hw = &adapter->hw; 122 u32 sec, nsec; 123 124 /* The timestamp latches on lowest register read. For I210/I211, the 125 * lowest register is SYSTIMR. Since we only need to provide nanosecond 126 * resolution, we can ignore it. 127 */ 128 rd32(E1000_SYSTIMR); 129 nsec = rd32(E1000_SYSTIML); 130 sec = rd32(E1000_SYSTIMH); 131 132 ts->tv_sec = sec; 133 ts->tv_nsec = nsec; 134 } 135 136 static void igb_ptp_write_i210(struct igb_adapter *adapter, 137 const struct timespec *ts) 138 { 139 struct e1000_hw *hw = &adapter->hw; 140 141 /* Writing the SYSTIMR register is not necessary as it only provides 142 * sub-nanosecond resolution. 143 */ 144 wr32(E1000_SYSTIML, ts->tv_nsec); 145 wr32(E1000_SYSTIMH, ts->tv_sec); 146 } 147 148 /** 149 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 150 * @adapter: board private structure 151 * @hwtstamps: timestamp structure to update 152 * @systim: unsigned 64bit system time value. 153 * 154 * We need to convert the system time value stored in the RX/TXSTMP registers 155 * into a hwtstamp which can be used by the upper level timestamping functions. 156 * 157 * The 'tmreg_lock' spinlock is used to protect the consistency of the 158 * system time value. This is needed because reading the 64 bit time 159 * value involves reading two (or three) 32 bit registers. The first 160 * read latches the value. Ditto for writing. 161 * 162 * In addition, here have extended the system time with an overflow 163 * counter in software. 164 **/ 165 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 166 struct skb_shared_hwtstamps *hwtstamps, 167 u64 systim) 168 { 169 unsigned long flags; 170 u64 ns; 171 172 switch (adapter->hw.mac.type) { 173 case e1000_82576: 174 case e1000_82580: 175 case e1000_i354: 176 case e1000_i350: 177 spin_lock_irqsave(&adapter->tmreg_lock, flags); 178 179 ns = timecounter_cyc2time(&adapter->tc, systim); 180 181 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 182 183 memset(hwtstamps, 0, sizeof(*hwtstamps)); 184 hwtstamps->hwtstamp = ns_to_ktime(ns); 185 break; 186 case e1000_i210: 187 case e1000_i211: 188 memset(hwtstamps, 0, sizeof(*hwtstamps)); 189 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 190 hwtstamps->hwtstamp = ktime_set(systim >> 32, 191 systim & 0xFFFFFFFF); 192 break; 193 default: 194 break; 195 } 196 } 197 198 /* PTP clock operations */ 199 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 200 { 201 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 202 ptp_caps); 203 struct e1000_hw *hw = &igb->hw; 204 int neg_adj = 0; 205 u64 rate; 206 u32 incvalue; 207 208 if (ppb < 0) { 209 neg_adj = 1; 210 ppb = -ppb; 211 } 212 rate = ppb; 213 rate <<= 14; 214 rate = div_u64(rate, 1953125); 215 216 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 217 218 if (neg_adj) 219 incvalue -= rate; 220 else 221 incvalue += rate; 222 223 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 224 225 return 0; 226 } 227 228 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) 229 { 230 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 231 ptp_caps); 232 struct e1000_hw *hw = &igb->hw; 233 int neg_adj = 0; 234 u64 rate; 235 u32 inca; 236 237 if (ppb < 0) { 238 neg_adj = 1; 239 ppb = -ppb; 240 } 241 rate = ppb; 242 rate <<= 26; 243 rate = div_u64(rate, 1953125); 244 245 inca = rate & INCVALUE_MASK; 246 if (neg_adj) 247 inca |= ISGN; 248 249 wr32(E1000_TIMINCA, inca); 250 251 return 0; 252 } 253 254 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 255 { 256 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 257 ptp_caps); 258 unsigned long flags; 259 s64 now; 260 261 spin_lock_irqsave(&igb->tmreg_lock, flags); 262 263 now = timecounter_read(&igb->tc); 264 now += delta; 265 timecounter_init(&igb->tc, &igb->cc, now); 266 267 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 268 269 return 0; 270 } 271 272 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 273 { 274 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 275 ptp_caps); 276 unsigned long flags; 277 struct timespec now, then = ns_to_timespec(delta); 278 279 spin_lock_irqsave(&igb->tmreg_lock, flags); 280 281 igb_ptp_read_i210(igb, &now); 282 now = timespec_add(now, then); 283 igb_ptp_write_i210(igb, (const struct timespec *)&now); 284 285 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 286 287 return 0; 288 } 289 290 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 291 struct timespec *ts) 292 { 293 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 294 ptp_caps); 295 unsigned long flags; 296 u64 ns; 297 u32 remainder; 298 299 spin_lock_irqsave(&igb->tmreg_lock, flags); 300 301 ns = timecounter_read(&igb->tc); 302 303 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 304 305 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); 306 ts->tv_nsec = remainder; 307 308 return 0; 309 } 310 311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 312 struct timespec *ts) 313 { 314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 315 ptp_caps); 316 unsigned long flags; 317 318 spin_lock_irqsave(&igb->tmreg_lock, flags); 319 320 igb_ptp_read_i210(igb, ts); 321 322 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 323 324 return 0; 325 } 326 327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 328 const struct timespec *ts) 329 { 330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 331 ptp_caps); 332 unsigned long flags; 333 u64 ns; 334 335 ns = ts->tv_sec * 1000000000ULL; 336 ns += ts->tv_nsec; 337 338 spin_lock_irqsave(&igb->tmreg_lock, flags); 339 340 timecounter_init(&igb->tc, &igb->cc, ns); 341 342 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 343 344 return 0; 345 } 346 347 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 348 const struct timespec *ts) 349 { 350 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 351 ptp_caps); 352 unsigned long flags; 353 354 spin_lock_irqsave(&igb->tmreg_lock, flags); 355 356 igb_ptp_write_i210(igb, ts); 357 358 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 359 360 return 0; 361 } 362 363 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 364 struct ptp_clock_request *rq, int on) 365 { 366 return -EOPNOTSUPP; 367 } 368 369 /** 370 * igb_ptp_tx_work 371 * @work: pointer to work struct 372 * 373 * This work function polls the TSYNCTXCTL valid bit to determine when a 374 * timestamp has been taken for the current stored skb. 375 **/ 376 static void igb_ptp_tx_work(struct work_struct *work) 377 { 378 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 379 ptp_tx_work); 380 struct e1000_hw *hw = &adapter->hw; 381 u32 tsynctxctl; 382 383 if (!adapter->ptp_tx_skb) 384 return; 385 386 if (time_is_before_jiffies(adapter->ptp_tx_start + 387 IGB_PTP_TX_TIMEOUT)) { 388 dev_kfree_skb_any(adapter->ptp_tx_skb); 389 adapter->ptp_tx_skb = NULL; 390 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 391 adapter->tx_hwtstamp_timeouts++; 392 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 393 return; 394 } 395 396 tsynctxctl = rd32(E1000_TSYNCTXCTL); 397 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 398 igb_ptp_tx_hwtstamp(adapter); 399 else 400 /* reschedule to check later */ 401 schedule_work(&adapter->ptp_tx_work); 402 } 403 404 static void igb_ptp_overflow_check(struct work_struct *work) 405 { 406 struct igb_adapter *igb = 407 container_of(work, struct igb_adapter, ptp_overflow_work.work); 408 struct timespec ts; 409 410 igb->ptp_caps.gettime(&igb->ptp_caps, &ts); 411 412 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); 413 414 schedule_delayed_work(&igb->ptp_overflow_work, 415 IGB_SYSTIM_OVERFLOW_PERIOD); 416 } 417 418 /** 419 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 420 * @adapter: private network adapter structure 421 * 422 * This watchdog task is scheduled to detect error case where hardware has 423 * dropped an Rx packet that was timestamped when the ring is full. The 424 * particular error is rare but leaves the device in a state unable to timestamp 425 * any future packets. 426 **/ 427 void igb_ptp_rx_hang(struct igb_adapter *adapter) 428 { 429 struct e1000_hw *hw = &adapter->hw; 430 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 431 unsigned long rx_event; 432 433 if (hw->mac.type != e1000_82576) 434 return; 435 436 /* If we don't have a valid timestamp in the registers, just update the 437 * timeout counter and exit 438 */ 439 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 440 adapter->last_rx_ptp_check = jiffies; 441 return; 442 } 443 444 /* Determine the most recent watchdog or rx_timestamp event */ 445 rx_event = adapter->last_rx_ptp_check; 446 if (time_after(adapter->last_rx_timestamp, rx_event)) 447 rx_event = adapter->last_rx_timestamp; 448 449 /* Only need to read the high RXSTMP register to clear the lock */ 450 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 451 rd32(E1000_RXSTMPH); 452 adapter->last_rx_ptp_check = jiffies; 453 adapter->rx_hwtstamp_cleared++; 454 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 455 } 456 } 457 458 /** 459 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 460 * @adapter: Board private structure. 461 * 462 * If we were asked to do hardware stamping and such a time stamp is 463 * available, then it must have been for this skb here because we only 464 * allow only one such packet into the queue. 465 **/ 466 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 467 { 468 struct e1000_hw *hw = &adapter->hw; 469 struct skb_shared_hwtstamps shhwtstamps; 470 u64 regval; 471 472 regval = rd32(E1000_TXSTMPL); 473 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 474 475 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 476 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 477 dev_kfree_skb_any(adapter->ptp_tx_skb); 478 adapter->ptp_tx_skb = NULL; 479 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 480 } 481 482 /** 483 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 484 * @q_vector: Pointer to interrupt specific structure 485 * @va: Pointer to address containing Rx buffer 486 * @skb: Buffer containing timestamp and packet 487 * 488 * This function is meant to retrieve a timestamp from the first buffer of an 489 * incoming frame. The value is stored in little endian format starting on 490 * byte 8. 491 **/ 492 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 493 unsigned char *va, 494 struct sk_buff *skb) 495 { 496 __le64 *regval = (__le64 *)va; 497 498 /* The timestamp is recorded in little endian format. 499 * DWORD: 0 1 2 3 500 * Field: Reserved Reserved SYSTIML SYSTIMH 501 */ 502 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), 503 le64_to_cpu(regval[1])); 504 } 505 506 /** 507 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 508 * @q_vector: Pointer to interrupt specific structure 509 * @skb: Buffer containing timestamp and packet 510 * 511 * This function is meant to retrieve a timestamp from the internal registers 512 * of the adapter and store it in the skb. 513 **/ 514 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 515 struct sk_buff *skb) 516 { 517 struct igb_adapter *adapter = q_vector->adapter; 518 struct e1000_hw *hw = &adapter->hw; 519 u64 regval; 520 521 /* If this bit is set, then the RX registers contain the time stamp. No 522 * other packet will be time stamped until we read these registers, so 523 * read the registers to make them available again. Because only one 524 * packet can be time stamped at a time, we know that the register 525 * values must belong to this one here and therefore we don't need to 526 * compare any of the additional attributes stored for it. 527 * 528 * If nothing went wrong, then it should have a shared tx_flags that we 529 * can turn into a skb_shared_hwtstamps. 530 */ 531 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 532 return; 533 534 regval = rd32(E1000_RXSTMPL); 535 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 536 537 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 538 539 /* Update the last_rx_timestamp timer in order to enable watchdog check 540 * for error case of latched timestamp on a dropped packet. 541 */ 542 adapter->last_rx_timestamp = jiffies; 543 } 544 545 /** 546 * igb_ptp_get_ts_config - get hardware time stamping config 547 * @netdev: 548 * @ifreq: 549 * 550 * Get the hwtstamp_config settings to return to the user. Rather than attempt 551 * to deconstruct the settings from the registers, just return a shadow copy 552 * of the last known settings. 553 **/ 554 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 555 { 556 struct igb_adapter *adapter = netdev_priv(netdev); 557 struct hwtstamp_config *config = &adapter->tstamp_config; 558 559 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 560 -EFAULT : 0; 561 } 562 563 /** 564 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 565 * @adapter: networking device structure 566 * @config: hwtstamp configuration 567 * 568 * Outgoing time stamping can be enabled and disabled. Play nice and 569 * disable it when requested, although it shouldn't case any overhead 570 * when no packet needs it. At most one packet in the queue may be 571 * marked for time stamping, otherwise it would be impossible to tell 572 * for sure to which packet the hardware time stamp belongs. 573 * 574 * Incoming time stamping has to be configured via the hardware 575 * filters. Not all combinations are supported, in particular event 576 * type has to be specified. Matching the kind of event packet is 577 * not supported, with the exception of "all V2 events regardless of 578 * level 2 or 4". 579 */ 580 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 581 struct hwtstamp_config *config) 582 { 583 struct e1000_hw *hw = &adapter->hw; 584 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 585 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 586 u32 tsync_rx_cfg = 0; 587 bool is_l4 = false; 588 bool is_l2 = false; 589 u32 regval; 590 591 /* reserved for future extensions */ 592 if (config->flags) 593 return -EINVAL; 594 595 switch (config->tx_type) { 596 case HWTSTAMP_TX_OFF: 597 tsync_tx_ctl = 0; 598 case HWTSTAMP_TX_ON: 599 break; 600 default: 601 return -ERANGE; 602 } 603 604 switch (config->rx_filter) { 605 case HWTSTAMP_FILTER_NONE: 606 tsync_rx_ctl = 0; 607 break; 608 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 609 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 610 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 611 is_l4 = true; 612 break; 613 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 614 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 615 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 616 is_l4 = true; 617 break; 618 case HWTSTAMP_FILTER_PTP_V2_EVENT: 619 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 620 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 621 case HWTSTAMP_FILTER_PTP_V2_SYNC: 622 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 623 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 624 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 625 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 626 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 627 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 628 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 629 is_l2 = true; 630 is_l4 = true; 631 break; 632 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 633 case HWTSTAMP_FILTER_ALL: 634 /* 82576 cannot timestamp all packets, which it needs to do to 635 * support both V1 Sync and Delay_Req messages 636 */ 637 if (hw->mac.type != e1000_82576) { 638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 639 config->rx_filter = HWTSTAMP_FILTER_ALL; 640 break; 641 } 642 /* fall through */ 643 default: 644 config->rx_filter = HWTSTAMP_FILTER_NONE; 645 return -ERANGE; 646 } 647 648 if (hw->mac.type == e1000_82575) { 649 if (tsync_rx_ctl | tsync_tx_ctl) 650 return -EINVAL; 651 return 0; 652 } 653 654 /* Per-packet timestamping only works if all packets are 655 * timestamped, so enable timestamping in all packets as 656 * long as one Rx filter was configured. 657 */ 658 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 659 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 661 config->rx_filter = HWTSTAMP_FILTER_ALL; 662 is_l2 = true; 663 is_l4 = true; 664 665 if ((hw->mac.type == e1000_i210) || 666 (hw->mac.type == e1000_i211)) { 667 regval = rd32(E1000_RXPBS); 668 regval |= E1000_RXPBS_CFG_TS_EN; 669 wr32(E1000_RXPBS, regval); 670 } 671 } 672 673 /* enable/disable TX */ 674 regval = rd32(E1000_TSYNCTXCTL); 675 regval &= ~E1000_TSYNCTXCTL_ENABLED; 676 regval |= tsync_tx_ctl; 677 wr32(E1000_TSYNCTXCTL, regval); 678 679 /* enable/disable RX */ 680 regval = rd32(E1000_TSYNCRXCTL); 681 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 682 regval |= tsync_rx_ctl; 683 wr32(E1000_TSYNCRXCTL, regval); 684 685 /* define which PTP packets are time stamped */ 686 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 687 688 /* define ethertype filter for timestamped packets */ 689 if (is_l2) 690 wr32(E1000_ETQF(3), 691 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 692 E1000_ETQF_1588 | /* enable timestamping */ 693 ETH_P_1588)); /* 1588 eth protocol type */ 694 else 695 wr32(E1000_ETQF(3), 0); 696 697 /* L4 Queue Filter[3]: filter by destination port and protocol */ 698 if (is_l4) { 699 u32 ftqf = (IPPROTO_UDP /* UDP */ 700 | E1000_FTQF_VF_BP /* VF not compared */ 701 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 702 | E1000_FTQF_MASK); /* mask all inputs */ 703 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 704 705 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 706 wr32(E1000_IMIREXT(3), 707 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 708 if (hw->mac.type == e1000_82576) { 709 /* enable source port check */ 710 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 711 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 712 } 713 wr32(E1000_FTQF(3), ftqf); 714 } else { 715 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 716 } 717 wrfl(); 718 719 /* clear TX/RX time stamp registers, just to be sure */ 720 regval = rd32(E1000_TXSTMPL); 721 regval = rd32(E1000_TXSTMPH); 722 regval = rd32(E1000_RXSTMPL); 723 regval = rd32(E1000_RXSTMPH); 724 725 return 0; 726 } 727 728 /** 729 * igb_ptp_set_ts_config - set hardware time stamping config 730 * @netdev: 731 * @ifreq: 732 * 733 **/ 734 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 735 { 736 struct igb_adapter *adapter = netdev_priv(netdev); 737 struct hwtstamp_config config; 738 int err; 739 740 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 741 return -EFAULT; 742 743 err = igb_ptp_set_timestamp_mode(adapter, &config); 744 if (err) 745 return err; 746 747 /* save these settings for future reference */ 748 memcpy(&adapter->tstamp_config, &config, 749 sizeof(adapter->tstamp_config)); 750 751 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 752 -EFAULT : 0; 753 } 754 755 void igb_ptp_init(struct igb_adapter *adapter) 756 { 757 struct e1000_hw *hw = &adapter->hw; 758 struct net_device *netdev = adapter->netdev; 759 760 switch (hw->mac.type) { 761 case e1000_82576: 762 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 763 adapter->ptp_caps.owner = THIS_MODULE; 764 adapter->ptp_caps.max_adj = 999999881; 765 adapter->ptp_caps.n_ext_ts = 0; 766 adapter->ptp_caps.pps = 0; 767 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 768 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 769 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 770 adapter->ptp_caps.settime = igb_ptp_settime_82576; 771 adapter->ptp_caps.enable = igb_ptp_feature_enable; 772 adapter->cc.read = igb_ptp_read_82576; 773 adapter->cc.mask = CLOCKSOURCE_MASK(64); 774 adapter->cc.mult = 1; 775 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 776 /* Dial the nominal frequency. */ 777 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 778 break; 779 case e1000_82580: 780 case e1000_i354: 781 case e1000_i350: 782 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 783 adapter->ptp_caps.owner = THIS_MODULE; 784 adapter->ptp_caps.max_adj = 62499999; 785 adapter->ptp_caps.n_ext_ts = 0; 786 adapter->ptp_caps.pps = 0; 787 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 788 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 789 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 790 adapter->ptp_caps.settime = igb_ptp_settime_82576; 791 adapter->ptp_caps.enable = igb_ptp_feature_enable; 792 adapter->cc.read = igb_ptp_read_82580; 793 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); 794 adapter->cc.mult = 1; 795 adapter->cc.shift = 0; 796 /* Enable the timer functions by clearing bit 31. */ 797 wr32(E1000_TSAUXC, 0x0); 798 break; 799 case e1000_i210: 800 case e1000_i211: 801 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 802 adapter->ptp_caps.owner = THIS_MODULE; 803 adapter->ptp_caps.max_adj = 62499999; 804 adapter->ptp_caps.n_ext_ts = 0; 805 adapter->ptp_caps.pps = 0; 806 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 807 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 808 adapter->ptp_caps.gettime = igb_ptp_gettime_i210; 809 adapter->ptp_caps.settime = igb_ptp_settime_i210; 810 adapter->ptp_caps.enable = igb_ptp_feature_enable; 811 /* Enable the timer functions by clearing bit 31. */ 812 wr32(E1000_TSAUXC, 0x0); 813 break; 814 default: 815 adapter->ptp_clock = NULL; 816 return; 817 } 818 819 wrfl(); 820 821 spin_lock_init(&adapter->tmreg_lock); 822 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 823 824 /* Initialize the clock and overflow work for devices that need it. */ 825 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 826 struct timespec ts = ktime_to_timespec(ktime_get_real()); 827 828 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 829 } else { 830 timecounter_init(&adapter->tc, &adapter->cc, 831 ktime_to_ns(ktime_get_real())); 832 833 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 834 igb_ptp_overflow_check); 835 836 schedule_delayed_work(&adapter->ptp_overflow_work, 837 IGB_SYSTIM_OVERFLOW_PERIOD); 838 } 839 840 /* Initialize the time sync interrupts for devices that support it. */ 841 if (hw->mac.type >= e1000_82580) { 842 wr32(E1000_TSIM, TSYNC_INTERRUPTS); 843 wr32(E1000_IMS, E1000_IMS_TS); 844 } 845 846 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 847 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 848 849 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 850 &adapter->pdev->dev); 851 if (IS_ERR(adapter->ptp_clock)) { 852 adapter->ptp_clock = NULL; 853 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 854 } else { 855 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 856 adapter->netdev->name); 857 adapter->flags |= IGB_FLAG_PTP; 858 } 859 } 860 861 /** 862 * igb_ptp_stop - Disable PTP device and stop the overflow check. 863 * @adapter: Board private structure. 864 * 865 * This function stops the PTP support and cancels the delayed work. 866 **/ 867 void igb_ptp_stop(struct igb_adapter *adapter) 868 { 869 switch (adapter->hw.mac.type) { 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i354: 873 case e1000_i350: 874 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 875 break; 876 case e1000_i210: 877 case e1000_i211: 878 /* No delayed work to cancel. */ 879 break; 880 default: 881 return; 882 } 883 884 cancel_work_sync(&adapter->ptp_tx_work); 885 if (adapter->ptp_tx_skb) { 886 dev_kfree_skb_any(adapter->ptp_tx_skb); 887 adapter->ptp_tx_skb = NULL; 888 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 889 } 890 891 if (adapter->ptp_clock) { 892 ptp_clock_unregister(adapter->ptp_clock); 893 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 894 adapter->netdev->name); 895 adapter->flags &= ~IGB_FLAG_PTP; 896 } 897 } 898 899 /** 900 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 901 * @adapter: Board private structure. 902 * 903 * This function handles the reset work required to re-enable the PTP device. 904 **/ 905 void igb_ptp_reset(struct igb_adapter *adapter) 906 { 907 struct e1000_hw *hw = &adapter->hw; 908 909 if (!(adapter->flags & IGB_FLAG_PTP)) 910 return; 911 912 /* reset the tstamp_config */ 913 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 914 915 switch (adapter->hw.mac.type) { 916 case e1000_82576: 917 /* Dial the nominal frequency. */ 918 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 919 break; 920 case e1000_82580: 921 case e1000_i354: 922 case e1000_i350: 923 case e1000_i210: 924 case e1000_i211: 925 /* Enable the timer functions and interrupts. */ 926 wr32(E1000_TSAUXC, 0x0); 927 wr32(E1000_TSIM, TSYNC_INTERRUPTS); 928 wr32(E1000_IMS, E1000_IMS_TS); 929 break; 930 default: 931 /* No work to do. */ 932 return; 933 } 934 935 /* Re-initialize the timer. */ 936 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 937 struct timespec ts = ktime_to_timespec(ktime_get_real()); 938 939 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 940 } else { 941 timecounter_init(&adapter->tc, &adapter->cc, 942 ktime_to_ns(ktime_get_real())); 943 } 944 } 945