1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4 #include <linux/module.h> 5 #include <linux/device.h> 6 #include <linux/pci.h> 7 #include <linux/ptp_classify.h> 8 9 #include "igb.h" 10 11 #define INCVALUE_MASK 0x7fffffff 12 #define ISGN 0x80000000 13 14 /* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 * 55 * SYSTIM is converted to real time using a timecounter. As 56 * timecounter_cyc2time() allows old timestamps, the timecounter 57 * needs to be updated at least once per half of the SYSTIM interval. 58 * Scheduling of delayed work is not very accurate, so we aim for 8 59 * minutes to be sure the actual interval is shorter than 9.16 minutes. 60 */ 61 62 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 8) 63 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 64 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 65 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 66 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 67 #define IGB_NBITS_82580 40 68 69 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 70 71 /* SYSTIM read access for the 82576 */ 72 static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 73 { 74 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 75 struct e1000_hw *hw = &igb->hw; 76 u64 val; 77 u32 lo, hi; 78 79 lo = rd32(E1000_SYSTIML); 80 hi = rd32(E1000_SYSTIMH); 81 82 val = ((u64) hi) << 32; 83 val |= lo; 84 85 return val; 86 } 87 88 /* SYSTIM read access for the 82580 */ 89 static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 90 { 91 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 92 struct e1000_hw *hw = &igb->hw; 93 u32 lo, hi; 94 u64 val; 95 96 /* The timestamp latches on lowest register read. For the 82580 97 * the lowest register is SYSTIMR instead of SYSTIML. However we only 98 * need to provide nanosecond resolution, so we just ignore it. 99 */ 100 rd32(E1000_SYSTIMR); 101 lo = rd32(E1000_SYSTIML); 102 hi = rd32(E1000_SYSTIMH); 103 104 val = ((u64) hi) << 32; 105 val |= lo; 106 107 return val; 108 } 109 110 /* SYSTIM read access for I210/I211 */ 111 static void igb_ptp_read_i210(struct igb_adapter *adapter, 112 struct timespec64 *ts) 113 { 114 struct e1000_hw *hw = &adapter->hw; 115 u32 sec, nsec; 116 117 /* The timestamp latches on lowest register read. For I210/I211, the 118 * lowest register is SYSTIMR. Since we only need to provide nanosecond 119 * resolution, we can ignore it. 120 */ 121 rd32(E1000_SYSTIMR); 122 nsec = rd32(E1000_SYSTIML); 123 sec = rd32(E1000_SYSTIMH); 124 125 ts->tv_sec = sec; 126 ts->tv_nsec = nsec; 127 } 128 129 static void igb_ptp_write_i210(struct igb_adapter *adapter, 130 const struct timespec64 *ts) 131 { 132 struct e1000_hw *hw = &adapter->hw; 133 134 /* Writing the SYSTIMR register is not necessary as it only provides 135 * sub-nanosecond resolution. 136 */ 137 wr32(E1000_SYSTIML, ts->tv_nsec); 138 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 139 } 140 141 /** 142 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 143 * @adapter: board private structure 144 * @hwtstamps: timestamp structure to update 145 * @systim: unsigned 64bit system time value. 146 * 147 * We need to convert the system time value stored in the RX/TXSTMP registers 148 * into a hwtstamp which can be used by the upper level timestamping functions. 149 * 150 * The 'tmreg_lock' spinlock is used to protect the consistency of the 151 * system time value. This is needed because reading the 64 bit time 152 * value involves reading two (or three) 32 bit registers. The first 153 * read latches the value. Ditto for writing. 154 * 155 * In addition, here have extended the system time with an overflow 156 * counter in software. 157 **/ 158 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 159 struct skb_shared_hwtstamps *hwtstamps, 160 u64 systim) 161 { 162 unsigned long flags; 163 u64 ns; 164 165 switch (adapter->hw.mac.type) { 166 case e1000_82576: 167 case e1000_82580: 168 case e1000_i354: 169 case e1000_i350: 170 spin_lock_irqsave(&adapter->tmreg_lock, flags); 171 172 ns = timecounter_cyc2time(&adapter->tc, systim); 173 174 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 175 176 memset(hwtstamps, 0, sizeof(*hwtstamps)); 177 hwtstamps->hwtstamp = ns_to_ktime(ns); 178 break; 179 case e1000_i210: 180 case e1000_i211: 181 memset(hwtstamps, 0, sizeof(*hwtstamps)); 182 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 183 hwtstamps->hwtstamp = ktime_set(systim >> 32, 184 systim & 0xFFFFFFFF); 185 break; 186 default: 187 break; 188 } 189 } 190 191 /* PTP clock operations */ 192 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 193 { 194 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 195 ptp_caps); 196 struct e1000_hw *hw = &igb->hw; 197 int neg_adj = 0; 198 u64 rate; 199 u32 incvalue; 200 201 if (ppb < 0) { 202 neg_adj = 1; 203 ppb = -ppb; 204 } 205 rate = ppb; 206 rate <<= 14; 207 rate = div_u64(rate, 1953125); 208 209 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 210 211 if (neg_adj) 212 incvalue -= rate; 213 else 214 incvalue += rate; 215 216 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 217 218 return 0; 219 } 220 221 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 222 { 223 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 224 ptp_caps); 225 struct e1000_hw *hw = &igb->hw; 226 int neg_adj = 0; 227 u64 rate; 228 u32 inca; 229 230 if (scaled_ppm < 0) { 231 neg_adj = 1; 232 scaled_ppm = -scaled_ppm; 233 } 234 rate = scaled_ppm; 235 rate <<= 13; 236 rate = div_u64(rate, 15625); 237 238 inca = rate & INCVALUE_MASK; 239 if (neg_adj) 240 inca |= ISGN; 241 242 wr32(E1000_TIMINCA, inca); 243 244 return 0; 245 } 246 247 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 248 { 249 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 250 ptp_caps); 251 unsigned long flags; 252 253 spin_lock_irqsave(&igb->tmreg_lock, flags); 254 timecounter_adjtime(&igb->tc, delta); 255 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 256 257 return 0; 258 } 259 260 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 261 { 262 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 263 ptp_caps); 264 unsigned long flags; 265 struct timespec64 now, then = ns_to_timespec64(delta); 266 267 spin_lock_irqsave(&igb->tmreg_lock, flags); 268 269 igb_ptp_read_i210(igb, &now); 270 now = timespec64_add(now, then); 271 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 272 273 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 274 275 return 0; 276 } 277 278 static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, 279 struct timespec64 *ts, 280 struct ptp_system_timestamp *sts) 281 { 282 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 283 ptp_caps); 284 struct e1000_hw *hw = &igb->hw; 285 unsigned long flags; 286 u32 lo, hi; 287 u64 ns; 288 289 spin_lock_irqsave(&igb->tmreg_lock, flags); 290 291 ptp_read_system_prets(sts); 292 lo = rd32(E1000_SYSTIML); 293 ptp_read_system_postts(sts); 294 hi = rd32(E1000_SYSTIMH); 295 296 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 297 298 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 299 300 *ts = ns_to_timespec64(ns); 301 302 return 0; 303 } 304 305 static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, 306 struct timespec64 *ts, 307 struct ptp_system_timestamp *sts) 308 { 309 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 310 ptp_caps); 311 struct e1000_hw *hw = &igb->hw; 312 unsigned long flags; 313 u32 lo, hi; 314 u64 ns; 315 316 spin_lock_irqsave(&igb->tmreg_lock, flags); 317 318 ptp_read_system_prets(sts); 319 rd32(E1000_SYSTIMR); 320 ptp_read_system_postts(sts); 321 lo = rd32(E1000_SYSTIML); 322 hi = rd32(E1000_SYSTIMH); 323 324 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 325 326 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 327 328 *ts = ns_to_timespec64(ns); 329 330 return 0; 331 } 332 333 static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, 334 struct timespec64 *ts, 335 struct ptp_system_timestamp *sts) 336 { 337 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 338 ptp_caps); 339 struct e1000_hw *hw = &igb->hw; 340 unsigned long flags; 341 342 spin_lock_irqsave(&igb->tmreg_lock, flags); 343 344 ptp_read_system_prets(sts); 345 rd32(E1000_SYSTIMR); 346 ptp_read_system_postts(sts); 347 ts->tv_nsec = rd32(E1000_SYSTIML); 348 ts->tv_sec = rd32(E1000_SYSTIMH); 349 350 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 351 352 return 0; 353 } 354 355 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 356 const struct timespec64 *ts) 357 { 358 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 359 ptp_caps); 360 unsigned long flags; 361 u64 ns; 362 363 ns = timespec64_to_ns(ts); 364 365 spin_lock_irqsave(&igb->tmreg_lock, flags); 366 367 timecounter_init(&igb->tc, &igb->cc, ns); 368 369 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 370 371 return 0; 372 } 373 374 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 375 const struct timespec64 *ts) 376 { 377 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 378 ptp_caps); 379 unsigned long flags; 380 381 spin_lock_irqsave(&igb->tmreg_lock, flags); 382 383 igb_ptp_write_i210(igb, ts); 384 385 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 386 387 return 0; 388 } 389 390 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 391 { 392 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 393 static const u32 mask[IGB_N_SDP] = { 394 E1000_CTRL_SDP0_DIR, 395 E1000_CTRL_SDP1_DIR, 396 E1000_CTRL_EXT_SDP2_DIR, 397 E1000_CTRL_EXT_SDP3_DIR, 398 }; 399 400 if (input) 401 *ptr &= ~mask[pin]; 402 else 403 *ptr |= mask[pin]; 404 } 405 406 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 407 { 408 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 409 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 410 }; 411 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 412 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 413 }; 414 static const u32 ts_sdp_en[IGB_N_SDP] = { 415 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 416 }; 417 struct e1000_hw *hw = &igb->hw; 418 u32 ctrl, ctrl_ext, tssdp = 0; 419 420 ctrl = rd32(E1000_CTRL); 421 ctrl_ext = rd32(E1000_CTRL_EXT); 422 tssdp = rd32(E1000_TSSDP); 423 424 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 425 426 /* Make sure this pin is not enabled as an output. */ 427 tssdp &= ~ts_sdp_en[pin]; 428 429 if (chan == 1) { 430 tssdp &= ~AUX1_SEL_SDP3; 431 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 432 } else { 433 tssdp &= ~AUX0_SEL_SDP3; 434 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 435 } 436 437 wr32(E1000_TSSDP, tssdp); 438 wr32(E1000_CTRL, ctrl); 439 wr32(E1000_CTRL_EXT, ctrl_ext); 440 } 441 442 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 443 { 444 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 445 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 446 }; 447 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 448 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 449 }; 450 static const u32 ts_sdp_en[IGB_N_SDP] = { 451 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 452 }; 453 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 454 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 455 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 456 }; 457 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 458 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 459 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 460 }; 461 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 462 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 463 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 464 }; 465 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 466 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 467 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 468 }; 469 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 470 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 471 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 472 }; 473 struct e1000_hw *hw = &igb->hw; 474 u32 ctrl, ctrl_ext, tssdp = 0; 475 476 ctrl = rd32(E1000_CTRL); 477 ctrl_ext = rd32(E1000_CTRL_EXT); 478 tssdp = rd32(E1000_TSSDP); 479 480 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 481 482 /* Make sure this pin is not enabled as an input. */ 483 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 484 tssdp &= ~AUX0_TS_SDP_EN; 485 486 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 487 tssdp &= ~AUX1_TS_SDP_EN; 488 489 tssdp &= ~ts_sdp_sel_clr[pin]; 490 if (freq) { 491 if (chan == 1) 492 tssdp |= ts_sdp_sel_fc1[pin]; 493 else 494 tssdp |= ts_sdp_sel_fc0[pin]; 495 } else { 496 if (chan == 1) 497 tssdp |= ts_sdp_sel_tt1[pin]; 498 else 499 tssdp |= ts_sdp_sel_tt0[pin]; 500 } 501 tssdp |= ts_sdp_en[pin]; 502 503 wr32(E1000_TSSDP, tssdp); 504 wr32(E1000_CTRL, ctrl); 505 wr32(E1000_CTRL_EXT, ctrl_ext); 506 } 507 508 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 509 struct ptp_clock_request *rq, int on) 510 { 511 struct igb_adapter *igb = 512 container_of(ptp, struct igb_adapter, ptp_caps); 513 struct e1000_hw *hw = &igb->hw; 514 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 515 unsigned long flags; 516 struct timespec64 ts; 517 int use_freq = 0, pin = -1; 518 s64 ns; 519 520 switch (rq->type) { 521 case PTP_CLK_REQ_EXTTS: 522 if (on) { 523 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 524 rq->extts.index); 525 if (pin < 0) 526 return -EBUSY; 527 } 528 if (rq->extts.index == 1) { 529 tsauxc_mask = TSAUXC_EN_TS1; 530 tsim_mask = TSINTR_AUTT1; 531 } else { 532 tsauxc_mask = TSAUXC_EN_TS0; 533 tsim_mask = TSINTR_AUTT0; 534 } 535 spin_lock_irqsave(&igb->tmreg_lock, flags); 536 tsauxc = rd32(E1000_TSAUXC); 537 tsim = rd32(E1000_TSIM); 538 if (on) { 539 igb_pin_extts(igb, rq->extts.index, pin); 540 tsauxc |= tsauxc_mask; 541 tsim |= tsim_mask; 542 } else { 543 tsauxc &= ~tsauxc_mask; 544 tsim &= ~tsim_mask; 545 } 546 wr32(E1000_TSAUXC, tsauxc); 547 wr32(E1000_TSIM, tsim); 548 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 549 return 0; 550 551 case PTP_CLK_REQ_PEROUT: 552 if (on) { 553 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 554 rq->perout.index); 555 if (pin < 0) 556 return -EBUSY; 557 } 558 ts.tv_sec = rq->perout.period.sec; 559 ts.tv_nsec = rq->perout.period.nsec; 560 ns = timespec64_to_ns(&ts); 561 ns = ns >> 1; 562 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 563 (ns == 250000000LL) || (ns == 500000000LL))) { 564 if (ns < 8LL) 565 return -EINVAL; 566 use_freq = 1; 567 } 568 ts = ns_to_timespec64(ns); 569 if (rq->perout.index == 1) { 570 if (use_freq) { 571 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 572 tsim_mask = 0; 573 } else { 574 tsauxc_mask = TSAUXC_EN_TT1; 575 tsim_mask = TSINTR_TT1; 576 } 577 trgttiml = E1000_TRGTTIML1; 578 trgttimh = E1000_TRGTTIMH1; 579 freqout = E1000_FREQOUT1; 580 } else { 581 if (use_freq) { 582 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 583 tsim_mask = 0; 584 } else { 585 tsauxc_mask = TSAUXC_EN_TT0; 586 tsim_mask = TSINTR_TT0; 587 } 588 trgttiml = E1000_TRGTTIML0; 589 trgttimh = E1000_TRGTTIMH0; 590 freqout = E1000_FREQOUT0; 591 } 592 spin_lock_irqsave(&igb->tmreg_lock, flags); 593 tsauxc = rd32(E1000_TSAUXC); 594 tsim = rd32(E1000_TSIM); 595 if (rq->perout.index == 1) { 596 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 597 tsim &= ~TSINTR_TT1; 598 } else { 599 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 600 tsim &= ~TSINTR_TT0; 601 } 602 if (on) { 603 int i = rq->perout.index; 604 igb_pin_perout(igb, i, pin, use_freq); 605 igb->perout[i].start.tv_sec = rq->perout.start.sec; 606 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 607 igb->perout[i].period.tv_sec = ts.tv_sec; 608 igb->perout[i].period.tv_nsec = ts.tv_nsec; 609 wr32(trgttimh, rq->perout.start.sec); 610 wr32(trgttiml, rq->perout.start.nsec); 611 if (use_freq) 612 wr32(freqout, ns); 613 tsauxc |= tsauxc_mask; 614 tsim |= tsim_mask; 615 } 616 wr32(E1000_TSAUXC, tsauxc); 617 wr32(E1000_TSIM, tsim); 618 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 619 return 0; 620 621 case PTP_CLK_REQ_PPS: 622 spin_lock_irqsave(&igb->tmreg_lock, flags); 623 tsim = rd32(E1000_TSIM); 624 if (on) 625 tsim |= TSINTR_SYS_WRAP; 626 else 627 tsim &= ~TSINTR_SYS_WRAP; 628 igb->pps_sys_wrap_on = !!on; 629 wr32(E1000_TSIM, tsim); 630 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 631 return 0; 632 } 633 634 return -EOPNOTSUPP; 635 } 636 637 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 638 struct ptp_clock_request *rq, int on) 639 { 640 return -EOPNOTSUPP; 641 } 642 643 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 644 enum ptp_pin_function func, unsigned int chan) 645 { 646 switch (func) { 647 case PTP_PF_NONE: 648 case PTP_PF_EXTTS: 649 case PTP_PF_PEROUT: 650 break; 651 case PTP_PF_PHYSYNC: 652 return -1; 653 } 654 return 0; 655 } 656 657 /** 658 * igb_ptp_tx_work 659 * @work: pointer to work struct 660 * 661 * This work function polls the TSYNCTXCTL valid bit to determine when a 662 * timestamp has been taken for the current stored skb. 663 **/ 664 static void igb_ptp_tx_work(struct work_struct *work) 665 { 666 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 667 ptp_tx_work); 668 struct e1000_hw *hw = &adapter->hw; 669 u32 tsynctxctl; 670 671 if (!adapter->ptp_tx_skb) 672 return; 673 674 if (time_is_before_jiffies(adapter->ptp_tx_start + 675 IGB_PTP_TX_TIMEOUT)) { 676 dev_kfree_skb_any(adapter->ptp_tx_skb); 677 adapter->ptp_tx_skb = NULL; 678 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 679 adapter->tx_hwtstamp_timeouts++; 680 /* Clear the tx valid bit in TSYNCTXCTL register to enable 681 * interrupt 682 */ 683 rd32(E1000_TXSTMPH); 684 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 685 return; 686 } 687 688 tsynctxctl = rd32(E1000_TSYNCTXCTL); 689 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 690 igb_ptp_tx_hwtstamp(adapter); 691 else 692 /* reschedule to check later */ 693 schedule_work(&adapter->ptp_tx_work); 694 } 695 696 static void igb_ptp_overflow_check(struct work_struct *work) 697 { 698 struct igb_adapter *igb = 699 container_of(work, struct igb_adapter, ptp_overflow_work.work); 700 struct timespec64 ts; 701 u64 ns; 702 703 /* Update the timecounter */ 704 ns = timecounter_read(&igb->tc); 705 706 ts = ns_to_timespec64(ns); 707 pr_debug("igb overflow check at %lld.%09lu\n", 708 (long long) ts.tv_sec, ts.tv_nsec); 709 710 schedule_delayed_work(&igb->ptp_overflow_work, 711 IGB_SYSTIM_OVERFLOW_PERIOD); 712 } 713 714 /** 715 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 716 * @adapter: private network adapter structure 717 * 718 * This watchdog task is scheduled to detect error case where hardware has 719 * dropped an Rx packet that was timestamped when the ring is full. The 720 * particular error is rare but leaves the device in a state unable to timestamp 721 * any future packets. 722 **/ 723 void igb_ptp_rx_hang(struct igb_adapter *adapter) 724 { 725 struct e1000_hw *hw = &adapter->hw; 726 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 727 unsigned long rx_event; 728 729 /* Other hardware uses per-packet timestamps */ 730 if (hw->mac.type != e1000_82576) 731 return; 732 733 /* If we don't have a valid timestamp in the registers, just update the 734 * timeout counter and exit 735 */ 736 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 737 adapter->last_rx_ptp_check = jiffies; 738 return; 739 } 740 741 /* Determine the most recent watchdog or rx_timestamp event */ 742 rx_event = adapter->last_rx_ptp_check; 743 if (time_after(adapter->last_rx_timestamp, rx_event)) 744 rx_event = adapter->last_rx_timestamp; 745 746 /* Only need to read the high RXSTMP register to clear the lock */ 747 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 748 rd32(E1000_RXSTMPH); 749 adapter->last_rx_ptp_check = jiffies; 750 adapter->rx_hwtstamp_cleared++; 751 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 752 } 753 } 754 755 /** 756 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 757 * @adapter: private network adapter structure 758 */ 759 void igb_ptp_tx_hang(struct igb_adapter *adapter) 760 { 761 struct e1000_hw *hw = &adapter->hw; 762 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 763 IGB_PTP_TX_TIMEOUT); 764 765 if (!adapter->ptp_tx_skb) 766 return; 767 768 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 769 return; 770 771 /* If we haven't received a timestamp within the timeout, it is 772 * reasonable to assume that it will never occur, so we can unlock the 773 * timestamp bit when this occurs. 774 */ 775 if (timeout) { 776 cancel_work_sync(&adapter->ptp_tx_work); 777 dev_kfree_skb_any(adapter->ptp_tx_skb); 778 adapter->ptp_tx_skb = NULL; 779 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 780 adapter->tx_hwtstamp_timeouts++; 781 /* Clear the tx valid bit in TSYNCTXCTL register to enable 782 * interrupt 783 */ 784 rd32(E1000_TXSTMPH); 785 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 786 } 787 } 788 789 /** 790 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 791 * @adapter: Board private structure. 792 * 793 * If we were asked to do hardware stamping and such a time stamp is 794 * available, then it must have been for this skb here because we only 795 * allow only one such packet into the queue. 796 **/ 797 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 798 { 799 struct sk_buff *skb = adapter->ptp_tx_skb; 800 struct e1000_hw *hw = &adapter->hw; 801 struct skb_shared_hwtstamps shhwtstamps; 802 u64 regval; 803 int adjust = 0; 804 805 regval = rd32(E1000_TXSTMPL); 806 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 807 808 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 809 /* adjust timestamp for the TX latency based on link speed */ 810 if (adapter->hw.mac.type == e1000_i210) { 811 switch (adapter->link_speed) { 812 case SPEED_10: 813 adjust = IGB_I210_TX_LATENCY_10; 814 break; 815 case SPEED_100: 816 adjust = IGB_I210_TX_LATENCY_100; 817 break; 818 case SPEED_1000: 819 adjust = IGB_I210_TX_LATENCY_1000; 820 break; 821 } 822 } 823 824 shhwtstamps.hwtstamp = 825 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 826 827 /* Clear the lock early before calling skb_tstamp_tx so that 828 * applications are not woken up before the lock bit is clear. We use 829 * a copy of the skb pointer to ensure other threads can't change it 830 * while we're notifying the stack. 831 */ 832 adapter->ptp_tx_skb = NULL; 833 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 834 835 /* Notify the stack and free the skb after we've unlocked */ 836 skb_tstamp_tx(skb, &shhwtstamps); 837 dev_kfree_skb_any(skb); 838 } 839 840 /** 841 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 842 * @q_vector: Pointer to interrupt specific structure 843 * @va: Pointer to address containing Rx buffer 844 * @skb: Buffer containing timestamp and packet 845 * 846 * This function is meant to retrieve a timestamp from the first buffer of an 847 * incoming frame. The value is stored in little endian format starting on 848 * byte 8. 849 **/ 850 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 851 struct sk_buff *skb) 852 { 853 __le64 *regval = (__le64 *)va; 854 struct igb_adapter *adapter = q_vector->adapter; 855 int adjust = 0; 856 857 /* The timestamp is recorded in little endian format. 858 * DWORD: 0 1 2 3 859 * Field: Reserved Reserved SYSTIML SYSTIMH 860 */ 861 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), 862 le64_to_cpu(regval[1])); 863 864 /* adjust timestamp for the RX latency based on link speed */ 865 if (adapter->hw.mac.type == e1000_i210) { 866 switch (adapter->link_speed) { 867 case SPEED_10: 868 adjust = IGB_I210_RX_LATENCY_10; 869 break; 870 case SPEED_100: 871 adjust = IGB_I210_RX_LATENCY_100; 872 break; 873 case SPEED_1000: 874 adjust = IGB_I210_RX_LATENCY_1000; 875 break; 876 } 877 } 878 skb_hwtstamps(skb)->hwtstamp = 879 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 880 } 881 882 /** 883 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 884 * @q_vector: Pointer to interrupt specific structure 885 * @skb: Buffer containing timestamp and packet 886 * 887 * This function is meant to retrieve a timestamp from the internal registers 888 * of the adapter and store it in the skb. 889 **/ 890 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 891 struct sk_buff *skb) 892 { 893 struct igb_adapter *adapter = q_vector->adapter; 894 struct e1000_hw *hw = &adapter->hw; 895 u64 regval; 896 int adjust = 0; 897 898 /* If this bit is set, then the RX registers contain the time stamp. No 899 * other packet will be time stamped until we read these registers, so 900 * read the registers to make them available again. Because only one 901 * packet can be time stamped at a time, we know that the register 902 * values must belong to this one here and therefore we don't need to 903 * compare any of the additional attributes stored for it. 904 * 905 * If nothing went wrong, then it should have a shared tx_flags that we 906 * can turn into a skb_shared_hwtstamps. 907 */ 908 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 909 return; 910 911 regval = rd32(E1000_RXSTMPL); 912 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 913 914 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 915 916 /* adjust timestamp for the RX latency based on link speed */ 917 if (adapter->hw.mac.type == e1000_i210) { 918 switch (adapter->link_speed) { 919 case SPEED_10: 920 adjust = IGB_I210_RX_LATENCY_10; 921 break; 922 case SPEED_100: 923 adjust = IGB_I210_RX_LATENCY_100; 924 break; 925 case SPEED_1000: 926 adjust = IGB_I210_RX_LATENCY_1000; 927 break; 928 } 929 } 930 skb_hwtstamps(skb)->hwtstamp = 931 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 932 933 /* Update the last_rx_timestamp timer in order to enable watchdog check 934 * for error case of latched timestamp on a dropped packet. 935 */ 936 adapter->last_rx_timestamp = jiffies; 937 } 938 939 /** 940 * igb_ptp_get_ts_config - get hardware time stamping config 941 * @netdev: 942 * @ifreq: 943 * 944 * Get the hwtstamp_config settings to return to the user. Rather than attempt 945 * to deconstruct the settings from the registers, just return a shadow copy 946 * of the last known settings. 947 **/ 948 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 949 { 950 struct igb_adapter *adapter = netdev_priv(netdev); 951 struct hwtstamp_config *config = &adapter->tstamp_config; 952 953 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 954 -EFAULT : 0; 955 } 956 957 /** 958 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 959 * @adapter: networking device structure 960 * @config: hwtstamp configuration 961 * 962 * Outgoing time stamping can be enabled and disabled. Play nice and 963 * disable it when requested, although it shouldn't case any overhead 964 * when no packet needs it. At most one packet in the queue may be 965 * marked for time stamping, otherwise it would be impossible to tell 966 * for sure to which packet the hardware time stamp belongs. 967 * 968 * Incoming time stamping has to be configured via the hardware 969 * filters. Not all combinations are supported, in particular event 970 * type has to be specified. Matching the kind of event packet is 971 * not supported, with the exception of "all V2 events regardless of 972 * level 2 or 4". 973 */ 974 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 975 struct hwtstamp_config *config) 976 { 977 struct e1000_hw *hw = &adapter->hw; 978 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 979 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 980 u32 tsync_rx_cfg = 0; 981 bool is_l4 = false; 982 bool is_l2 = false; 983 u32 regval; 984 985 /* reserved for future extensions */ 986 if (config->flags) 987 return -EINVAL; 988 989 switch (config->tx_type) { 990 case HWTSTAMP_TX_OFF: 991 tsync_tx_ctl = 0; 992 case HWTSTAMP_TX_ON: 993 break; 994 default: 995 return -ERANGE; 996 } 997 998 switch (config->rx_filter) { 999 case HWTSTAMP_FILTER_NONE: 1000 tsync_rx_ctl = 0; 1001 break; 1002 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1003 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1004 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 1005 is_l4 = true; 1006 break; 1007 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1008 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1009 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 1010 is_l4 = true; 1011 break; 1012 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1013 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1014 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1015 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1016 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1017 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1018 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1019 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1020 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1021 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 1022 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1023 is_l2 = true; 1024 is_l4 = true; 1025 break; 1026 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1027 case HWTSTAMP_FILTER_NTP_ALL: 1028 case HWTSTAMP_FILTER_ALL: 1029 /* 82576 cannot timestamp all packets, which it needs to do to 1030 * support both V1 Sync and Delay_Req messages 1031 */ 1032 if (hw->mac.type != e1000_82576) { 1033 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1034 config->rx_filter = HWTSTAMP_FILTER_ALL; 1035 break; 1036 } 1037 /* fall through */ 1038 default: 1039 config->rx_filter = HWTSTAMP_FILTER_NONE; 1040 return -ERANGE; 1041 } 1042 1043 if (hw->mac.type == e1000_82575) { 1044 if (tsync_rx_ctl | tsync_tx_ctl) 1045 return -EINVAL; 1046 return 0; 1047 } 1048 1049 /* Per-packet timestamping only works if all packets are 1050 * timestamped, so enable timestamping in all packets as 1051 * long as one Rx filter was configured. 1052 */ 1053 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1054 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1055 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1056 config->rx_filter = HWTSTAMP_FILTER_ALL; 1057 is_l2 = true; 1058 is_l4 = true; 1059 1060 if ((hw->mac.type == e1000_i210) || 1061 (hw->mac.type == e1000_i211)) { 1062 regval = rd32(E1000_RXPBS); 1063 regval |= E1000_RXPBS_CFG_TS_EN; 1064 wr32(E1000_RXPBS, regval); 1065 } 1066 } 1067 1068 /* enable/disable TX */ 1069 regval = rd32(E1000_TSYNCTXCTL); 1070 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1071 regval |= tsync_tx_ctl; 1072 wr32(E1000_TSYNCTXCTL, regval); 1073 1074 /* enable/disable RX */ 1075 regval = rd32(E1000_TSYNCRXCTL); 1076 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1077 regval |= tsync_rx_ctl; 1078 wr32(E1000_TSYNCRXCTL, regval); 1079 1080 /* define which PTP packets are time stamped */ 1081 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1082 1083 /* define ethertype filter for timestamped packets */ 1084 if (is_l2) 1085 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1086 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1087 E1000_ETQF_1588 | /* enable timestamping */ 1088 ETH_P_1588)); /* 1588 eth protocol type */ 1089 else 1090 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1091 1092 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1093 if (is_l4) { 1094 u32 ftqf = (IPPROTO_UDP /* UDP */ 1095 | E1000_FTQF_VF_BP /* VF not compared */ 1096 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1097 | E1000_FTQF_MASK); /* mask all inputs */ 1098 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1099 1100 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 1101 wr32(E1000_IMIREXT(3), 1102 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1103 if (hw->mac.type == e1000_82576) { 1104 /* enable source port check */ 1105 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 1106 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1107 } 1108 wr32(E1000_FTQF(3), ftqf); 1109 } else { 1110 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1111 } 1112 wrfl(); 1113 1114 /* clear TX/RX time stamp registers, just to be sure */ 1115 regval = rd32(E1000_TXSTMPL); 1116 regval = rd32(E1000_TXSTMPH); 1117 regval = rd32(E1000_RXSTMPL); 1118 regval = rd32(E1000_RXSTMPH); 1119 1120 return 0; 1121 } 1122 1123 /** 1124 * igb_ptp_set_ts_config - set hardware time stamping config 1125 * @netdev: 1126 * @ifreq: 1127 * 1128 **/ 1129 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1130 { 1131 struct igb_adapter *adapter = netdev_priv(netdev); 1132 struct hwtstamp_config config; 1133 int err; 1134 1135 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1136 return -EFAULT; 1137 1138 err = igb_ptp_set_timestamp_mode(adapter, &config); 1139 if (err) 1140 return err; 1141 1142 /* save these settings for future reference */ 1143 memcpy(&adapter->tstamp_config, &config, 1144 sizeof(adapter->tstamp_config)); 1145 1146 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1147 -EFAULT : 0; 1148 } 1149 1150 /** 1151 * igb_ptp_init - Initialize PTP functionality 1152 * @adapter: Board private structure 1153 * 1154 * This function is called at device probe to initialize the PTP 1155 * functionality. 1156 */ 1157 void igb_ptp_init(struct igb_adapter *adapter) 1158 { 1159 struct e1000_hw *hw = &adapter->hw; 1160 struct net_device *netdev = adapter->netdev; 1161 int i; 1162 1163 switch (hw->mac.type) { 1164 case e1000_82576: 1165 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1166 adapter->ptp_caps.owner = THIS_MODULE; 1167 adapter->ptp_caps.max_adj = 999999881; 1168 adapter->ptp_caps.n_ext_ts = 0; 1169 adapter->ptp_caps.pps = 0; 1170 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1171 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1172 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; 1173 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1174 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1175 adapter->cc.read = igb_ptp_read_82576; 1176 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1177 adapter->cc.mult = 1; 1178 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1179 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1180 break; 1181 case e1000_82580: 1182 case e1000_i354: 1183 case e1000_i350: 1184 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1185 adapter->ptp_caps.owner = THIS_MODULE; 1186 adapter->ptp_caps.max_adj = 62499999; 1187 adapter->ptp_caps.n_ext_ts = 0; 1188 adapter->ptp_caps.pps = 0; 1189 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1190 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1191 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; 1192 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1193 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1194 adapter->cc.read = igb_ptp_read_82580; 1195 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1196 adapter->cc.mult = 1; 1197 adapter->cc.shift = 0; 1198 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1199 break; 1200 case e1000_i210: 1201 case e1000_i211: 1202 for (i = 0; i < IGB_N_SDP; i++) { 1203 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1204 1205 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1206 ppd->index = i; 1207 ppd->func = PTP_PF_NONE; 1208 } 1209 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1210 adapter->ptp_caps.owner = THIS_MODULE; 1211 adapter->ptp_caps.max_adj = 62499999; 1212 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1213 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1214 adapter->ptp_caps.n_pins = IGB_N_SDP; 1215 adapter->ptp_caps.pps = 1; 1216 adapter->ptp_caps.pin_config = adapter->sdp_config; 1217 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1218 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1219 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; 1220 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1221 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1222 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1223 break; 1224 default: 1225 adapter->ptp_clock = NULL; 1226 return; 1227 } 1228 1229 spin_lock_init(&adapter->tmreg_lock); 1230 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1231 1232 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1233 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1234 igb_ptp_overflow_check); 1235 1236 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1237 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1238 1239 igb_ptp_reset(adapter); 1240 1241 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1242 &adapter->pdev->dev); 1243 if (IS_ERR(adapter->ptp_clock)) { 1244 adapter->ptp_clock = NULL; 1245 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1246 } else if (adapter->ptp_clock) { 1247 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1248 adapter->netdev->name); 1249 adapter->ptp_flags |= IGB_PTP_ENABLED; 1250 } 1251 } 1252 1253 /** 1254 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1255 * @adapter: Board private structure 1256 * 1257 * This function stops the overflow check work and PTP Tx timestamp work, and 1258 * will prepare the device for OS suspend. 1259 */ 1260 void igb_ptp_suspend(struct igb_adapter *adapter) 1261 { 1262 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1263 return; 1264 1265 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1266 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1267 1268 cancel_work_sync(&adapter->ptp_tx_work); 1269 if (adapter->ptp_tx_skb) { 1270 dev_kfree_skb_any(adapter->ptp_tx_skb); 1271 adapter->ptp_tx_skb = NULL; 1272 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1273 } 1274 } 1275 1276 /** 1277 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1278 * @adapter: Board private structure. 1279 * 1280 * This function stops the PTP support and cancels the delayed work. 1281 **/ 1282 void igb_ptp_stop(struct igb_adapter *adapter) 1283 { 1284 igb_ptp_suspend(adapter); 1285 1286 if (adapter->ptp_clock) { 1287 ptp_clock_unregister(adapter->ptp_clock); 1288 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1289 adapter->netdev->name); 1290 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1291 } 1292 } 1293 1294 /** 1295 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1296 * @adapter: Board private structure. 1297 * 1298 * This function handles the reset work required to re-enable the PTP device. 1299 **/ 1300 void igb_ptp_reset(struct igb_adapter *adapter) 1301 { 1302 struct e1000_hw *hw = &adapter->hw; 1303 unsigned long flags; 1304 1305 /* reset the tstamp_config */ 1306 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1307 1308 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1309 1310 switch (adapter->hw.mac.type) { 1311 case e1000_82576: 1312 /* Dial the nominal frequency. */ 1313 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1314 break; 1315 case e1000_82580: 1316 case e1000_i354: 1317 case e1000_i350: 1318 case e1000_i210: 1319 case e1000_i211: 1320 wr32(E1000_TSAUXC, 0x0); 1321 wr32(E1000_TSSDP, 0x0); 1322 wr32(E1000_TSIM, 1323 TSYNC_INTERRUPTS | 1324 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1325 wr32(E1000_IMS, E1000_IMS_TS); 1326 break; 1327 default: 1328 /* No work to do. */ 1329 goto out; 1330 } 1331 1332 /* Re-initialize the timer. */ 1333 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1334 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1335 1336 igb_ptp_write_i210(adapter, &ts); 1337 } else { 1338 timecounter_init(&adapter->tc, &adapter->cc, 1339 ktime_to_ns(ktime_get_real())); 1340 } 1341 out: 1342 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1343 1344 wrfl(); 1345 1346 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1347 schedule_delayed_work(&adapter->ptp_overflow_work, 1348 IGB_SYSTIM_OVERFLOW_PERIOD); 1349 } 1350