1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
2  *
3  * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
22 
23 #include "igb.h"
24 
25 #define INCVALUE_MASK		0x7fffffff
26 #define ISGN			0x80000000
27 
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29  * and this update value cannot be reprogrammed.
30  *
31  * Neither the 82576 nor the 82580 offer registers wide enough to hold
32  * nanoseconds time values for very long. For the 82580, SYSTIM always
33  * counts nanoseconds, but the upper 24 bits are not available. The
34  * frequency is adjusted by changing the 32 bit fractional nanoseconds
35  * register, TIMINCA.
36  *
37  * For the 82576, the SYSTIM register time unit is affect by the
38  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39  * field are needed to provide the nominal 16 nanosecond period,
40  * leaving 19 bits for fractional nanoseconds.
41  *
42  * We scale the NIC clock cycle by a large factor so that relatively
43  * small clock corrections can be added or subtracted at each clock
44  * tick. The drawbacks of a large factor are a) that the clock
45  * register overflows more quickly (not such a big deal) and b) that
46  * the increment per tick has to fit into 24 bits.  As a result we
47  * need to use a shift of 19 so we can fit a value of 16 into the
48  * TIMINCA register.
49  *
50  *
51  *             SYSTIMH            SYSTIML
52  *        +--------------+   +---+---+------+
53  *  82576 |      32      |   | 8 | 5 |  19  |
54  *        +--------------+   +---+---+------+
55  *         \________ 45 bits _______/  fract
56  *
57  *        +----------+---+   +--------------+
58  *  82580 |    24    | 8 |   |      32      |
59  *        +----------+---+   +--------------+
60  *          reserved  \______ 40 bits _____/
61  *
62  *
63  * The 45 bit 82576 SYSTIM overflows every
64  *   2^45 * 10^-9 / 3600 = 9.77 hours.
65  *
66  * The 40 bit 82580 SYSTIM overflows every
67  *   2^40 * 10^-9 /  60  = 18.3 minutes.
68  */
69 
70 #define IGB_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 9)
71 #define IGB_PTP_TX_TIMEOUT		(HZ * 15)
72 #define INCPERIOD_82576			(1 << E1000_TIMINCA_16NS_SHIFT)
73 #define INCVALUE_82576_MASK		((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74 #define INCVALUE_82576			(16 << IGB_82576_TSYNC_SHIFT)
75 #define IGB_NBITS_82580			40
76 
77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
78 
79 /* SYSTIM read access for the 82576 */
80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
81 {
82 	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 	struct e1000_hw *hw = &igb->hw;
84 	u64 val;
85 	u32 lo, hi;
86 
87 	lo = rd32(E1000_SYSTIML);
88 	hi = rd32(E1000_SYSTIMH);
89 
90 	val = ((u64) hi) << 32;
91 	val |= lo;
92 
93 	return val;
94 }
95 
96 /* SYSTIM read access for the 82580 */
97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
98 {
99 	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 	struct e1000_hw *hw = &igb->hw;
101 	u32 lo, hi;
102 	u64 val;
103 
104 	/* The timestamp latches on lowest register read. For the 82580
105 	 * the lowest register is SYSTIMR instead of SYSTIML.  However we only
106 	 * need to provide nanosecond resolution, so we just ignore it.
107 	 */
108 	rd32(E1000_SYSTIMR);
109 	lo = rd32(E1000_SYSTIML);
110 	hi = rd32(E1000_SYSTIMH);
111 
112 	val = ((u64) hi) << 32;
113 	val |= lo;
114 
115 	return val;
116 }
117 
118 /* SYSTIM read access for I210/I211 */
119 static void igb_ptp_read_i210(struct igb_adapter *adapter,
120 			      struct timespec64 *ts)
121 {
122 	struct e1000_hw *hw = &adapter->hw;
123 	u32 sec, nsec;
124 
125 	/* The timestamp latches on lowest register read. For I210/I211, the
126 	 * lowest register is SYSTIMR. Since we only need to provide nanosecond
127 	 * resolution, we can ignore it.
128 	 */
129 	rd32(E1000_SYSTIMR);
130 	nsec = rd32(E1000_SYSTIML);
131 	sec = rd32(E1000_SYSTIMH);
132 
133 	ts->tv_sec = sec;
134 	ts->tv_nsec = nsec;
135 }
136 
137 static void igb_ptp_write_i210(struct igb_adapter *adapter,
138 			       const struct timespec64 *ts)
139 {
140 	struct e1000_hw *hw = &adapter->hw;
141 
142 	/* Writing the SYSTIMR register is not necessary as it only provides
143 	 * sub-nanosecond resolution.
144 	 */
145 	wr32(E1000_SYSTIML, ts->tv_nsec);
146 	wr32(E1000_SYSTIMH, ts->tv_sec);
147 }
148 
149 /**
150  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
151  * @adapter: board private structure
152  * @hwtstamps: timestamp structure to update
153  * @systim: unsigned 64bit system time value.
154  *
155  * We need to convert the system time value stored in the RX/TXSTMP registers
156  * into a hwtstamp which can be used by the upper level timestamping functions.
157  *
158  * The 'tmreg_lock' spinlock is used to protect the consistency of the
159  * system time value. This is needed because reading the 64 bit time
160  * value involves reading two (or three) 32 bit registers. The first
161  * read latches the value. Ditto for writing.
162  *
163  * In addition, here have extended the system time with an overflow
164  * counter in software.
165  **/
166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
167 				       struct skb_shared_hwtstamps *hwtstamps,
168 				       u64 systim)
169 {
170 	unsigned long flags;
171 	u64 ns;
172 
173 	switch (adapter->hw.mac.type) {
174 	case e1000_82576:
175 	case e1000_82580:
176 	case e1000_i354:
177 	case e1000_i350:
178 		spin_lock_irqsave(&adapter->tmreg_lock, flags);
179 
180 		ns = timecounter_cyc2time(&adapter->tc, systim);
181 
182 		spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
183 
184 		memset(hwtstamps, 0, sizeof(*hwtstamps));
185 		hwtstamps->hwtstamp = ns_to_ktime(ns);
186 		break;
187 	case e1000_i210:
188 	case e1000_i211:
189 		memset(hwtstamps, 0, sizeof(*hwtstamps));
190 		/* Upper 32 bits contain s, lower 32 bits contain ns. */
191 		hwtstamps->hwtstamp = ktime_set(systim >> 32,
192 						systim & 0xFFFFFFFF);
193 		break;
194 	default:
195 		break;
196 	}
197 }
198 
199 /* PTP clock operations */
200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
201 {
202 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
203 					       ptp_caps);
204 	struct e1000_hw *hw = &igb->hw;
205 	int neg_adj = 0;
206 	u64 rate;
207 	u32 incvalue;
208 
209 	if (ppb < 0) {
210 		neg_adj = 1;
211 		ppb = -ppb;
212 	}
213 	rate = ppb;
214 	rate <<= 14;
215 	rate = div_u64(rate, 1953125);
216 
217 	incvalue = 16 << IGB_82576_TSYNC_SHIFT;
218 
219 	if (neg_adj)
220 		incvalue -= rate;
221 	else
222 		incvalue += rate;
223 
224 	wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
225 
226 	return 0;
227 }
228 
229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
230 {
231 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
232 					       ptp_caps);
233 	struct e1000_hw *hw = &igb->hw;
234 	int neg_adj = 0;
235 	u64 rate;
236 	u32 inca;
237 
238 	if (ppb < 0) {
239 		neg_adj = 1;
240 		ppb = -ppb;
241 	}
242 	rate = ppb;
243 	rate <<= 26;
244 	rate = div_u64(rate, 1953125);
245 
246 	inca = rate & INCVALUE_MASK;
247 	if (neg_adj)
248 		inca |= ISGN;
249 
250 	wr32(E1000_TIMINCA, inca);
251 
252 	return 0;
253 }
254 
255 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
256 {
257 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
258 					       ptp_caps);
259 	unsigned long flags;
260 
261 	spin_lock_irqsave(&igb->tmreg_lock, flags);
262 	timecounter_adjtime(&igb->tc, delta);
263 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
264 
265 	return 0;
266 }
267 
268 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
269 {
270 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
271 					       ptp_caps);
272 	unsigned long flags;
273 	struct timespec64 now, then = ns_to_timespec64(delta);
274 
275 	spin_lock_irqsave(&igb->tmreg_lock, flags);
276 
277 	igb_ptp_read_i210(igb, &now);
278 	now = timespec64_add(now, then);
279 	igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
280 
281 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
282 
283 	return 0;
284 }
285 
286 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
287 				 struct timespec64 *ts)
288 {
289 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
290 					       ptp_caps);
291 	unsigned long flags;
292 	u64 ns;
293 
294 	spin_lock_irqsave(&igb->tmreg_lock, flags);
295 
296 	ns = timecounter_read(&igb->tc);
297 
298 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
299 
300 	*ts = ns_to_timespec64(ns);
301 
302 	return 0;
303 }
304 
305 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
306 				struct timespec64 *ts)
307 {
308 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
309 					       ptp_caps);
310 	unsigned long flags;
311 
312 	spin_lock_irqsave(&igb->tmreg_lock, flags);
313 
314 	igb_ptp_read_i210(igb, ts);
315 
316 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
317 
318 	return 0;
319 }
320 
321 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
322 				 const struct timespec64 *ts)
323 {
324 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
325 					       ptp_caps);
326 	unsigned long flags;
327 	u64 ns;
328 
329 	ns = timespec64_to_ns(ts);
330 
331 	spin_lock_irqsave(&igb->tmreg_lock, flags);
332 
333 	timecounter_init(&igb->tc, &igb->cc, ns);
334 
335 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
336 
337 	return 0;
338 }
339 
340 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
341 				const struct timespec64 *ts)
342 {
343 	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
344 					       ptp_caps);
345 	unsigned long flags;
346 
347 	spin_lock_irqsave(&igb->tmreg_lock, flags);
348 
349 	igb_ptp_write_i210(igb, ts);
350 
351 	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
352 
353 	return 0;
354 }
355 
356 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
357 {
358 	u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
359 	static const u32 mask[IGB_N_SDP] = {
360 		E1000_CTRL_SDP0_DIR,
361 		E1000_CTRL_SDP1_DIR,
362 		E1000_CTRL_EXT_SDP2_DIR,
363 		E1000_CTRL_EXT_SDP3_DIR,
364 	};
365 
366 	if (input)
367 		*ptr &= ~mask[pin];
368 	else
369 		*ptr |= mask[pin];
370 }
371 
372 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
373 {
374 	static const u32 aux0_sel_sdp[IGB_N_SDP] = {
375 		AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
376 	};
377 	static const u32 aux1_sel_sdp[IGB_N_SDP] = {
378 		AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
379 	};
380 	static const u32 ts_sdp_en[IGB_N_SDP] = {
381 		TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
382 	};
383 	struct e1000_hw *hw = &igb->hw;
384 	u32 ctrl, ctrl_ext, tssdp = 0;
385 
386 	ctrl = rd32(E1000_CTRL);
387 	ctrl_ext = rd32(E1000_CTRL_EXT);
388 	tssdp = rd32(E1000_TSSDP);
389 
390 	igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
391 
392 	/* Make sure this pin is not enabled as an output. */
393 	tssdp &= ~ts_sdp_en[pin];
394 
395 	if (chan == 1) {
396 		tssdp &= ~AUX1_SEL_SDP3;
397 		tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
398 	} else {
399 		tssdp &= ~AUX0_SEL_SDP3;
400 		tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
401 	}
402 
403 	wr32(E1000_TSSDP, tssdp);
404 	wr32(E1000_CTRL, ctrl);
405 	wr32(E1000_CTRL_EXT, ctrl_ext);
406 }
407 
408 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin)
409 {
410 	static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 		AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
412 	};
413 	static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 		AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
415 	};
416 	static const u32 ts_sdp_en[IGB_N_SDP] = {
417 		TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
418 	};
419 	static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
420 		TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
421 		TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
422 	};
423 	static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
424 		TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
425 		TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
426 	};
427 	static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
428 		TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
429 		TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
430 	};
431 	struct e1000_hw *hw = &igb->hw;
432 	u32 ctrl, ctrl_ext, tssdp = 0;
433 
434 	ctrl = rd32(E1000_CTRL);
435 	ctrl_ext = rd32(E1000_CTRL_EXT);
436 	tssdp = rd32(E1000_TSSDP);
437 
438 	igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
439 
440 	/* Make sure this pin is not enabled as an input. */
441 	if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
442 		tssdp &= ~AUX0_TS_SDP_EN;
443 
444 	if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
445 		tssdp &= ~AUX1_TS_SDP_EN;
446 
447 	tssdp &= ~ts_sdp_sel_clr[pin];
448 	if (chan == 1)
449 		tssdp |= ts_sdp_sel_tt1[pin];
450 	else
451 		tssdp |= ts_sdp_sel_tt0[pin];
452 
453 	tssdp |= ts_sdp_en[pin];
454 
455 	wr32(E1000_TSSDP, tssdp);
456 	wr32(E1000_CTRL, ctrl);
457 	wr32(E1000_CTRL_EXT, ctrl_ext);
458 }
459 
460 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
461 				       struct ptp_clock_request *rq, int on)
462 {
463 	struct igb_adapter *igb =
464 		container_of(ptp, struct igb_adapter, ptp_caps);
465 	struct e1000_hw *hw = &igb->hw;
466 	u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh;
467 	unsigned long flags;
468 	struct timespec ts;
469 	int pin = -1;
470 	s64 ns;
471 
472 	switch (rq->type) {
473 	case PTP_CLK_REQ_EXTTS:
474 		if (on) {
475 			pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
476 					   rq->extts.index);
477 			if (pin < 0)
478 				return -EBUSY;
479 		}
480 		if (rq->extts.index == 1) {
481 			tsauxc_mask = TSAUXC_EN_TS1;
482 			tsim_mask = TSINTR_AUTT1;
483 		} else {
484 			tsauxc_mask = TSAUXC_EN_TS0;
485 			tsim_mask = TSINTR_AUTT0;
486 		}
487 		spin_lock_irqsave(&igb->tmreg_lock, flags);
488 		tsauxc = rd32(E1000_TSAUXC);
489 		tsim = rd32(E1000_TSIM);
490 		if (on) {
491 			igb_pin_extts(igb, rq->extts.index, pin);
492 			tsauxc |= tsauxc_mask;
493 			tsim |= tsim_mask;
494 		} else {
495 			tsauxc &= ~tsauxc_mask;
496 			tsim &= ~tsim_mask;
497 		}
498 		wr32(E1000_TSAUXC, tsauxc);
499 		wr32(E1000_TSIM, tsim);
500 		spin_unlock_irqrestore(&igb->tmreg_lock, flags);
501 		return 0;
502 
503 	case PTP_CLK_REQ_PEROUT:
504 		if (on) {
505 			pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
506 					   rq->perout.index);
507 			if (pin < 0)
508 				return -EBUSY;
509 		}
510 		ts.tv_sec = rq->perout.period.sec;
511 		ts.tv_nsec = rq->perout.period.nsec;
512 		ns = timespec_to_ns(&ts);
513 		ns = ns >> 1;
514 		if (on && ns < 500000LL) {
515 			/* 2k interrupts per second is an awful lot. */
516 			return -EINVAL;
517 		}
518 		ts = ns_to_timespec(ns);
519 		if (rq->perout.index == 1) {
520 			tsauxc_mask = TSAUXC_EN_TT1;
521 			tsim_mask = TSINTR_TT1;
522 			trgttiml = E1000_TRGTTIML1;
523 			trgttimh = E1000_TRGTTIMH1;
524 		} else {
525 			tsauxc_mask = TSAUXC_EN_TT0;
526 			tsim_mask = TSINTR_TT0;
527 			trgttiml = E1000_TRGTTIML0;
528 			trgttimh = E1000_TRGTTIMH0;
529 		}
530 		spin_lock_irqsave(&igb->tmreg_lock, flags);
531 		tsauxc = rd32(E1000_TSAUXC);
532 		tsim = rd32(E1000_TSIM);
533 		if (on) {
534 			int i = rq->perout.index;
535 
536 			igb_pin_perout(igb, i, pin);
537 			igb->perout[i].start.tv_sec = rq->perout.start.sec;
538 			igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
539 			igb->perout[i].period.tv_sec = ts.tv_sec;
540 			igb->perout[i].period.tv_nsec = ts.tv_nsec;
541 			wr32(trgttiml, rq->perout.start.sec);
542 			wr32(trgttimh, rq->perout.start.nsec);
543 			tsauxc |= tsauxc_mask;
544 			tsim |= tsim_mask;
545 		} else {
546 			tsauxc &= ~tsauxc_mask;
547 			tsim &= ~tsim_mask;
548 		}
549 		wr32(E1000_TSAUXC, tsauxc);
550 		wr32(E1000_TSIM, tsim);
551 		spin_unlock_irqrestore(&igb->tmreg_lock, flags);
552 		return 0;
553 
554 	case PTP_CLK_REQ_PPS:
555 		spin_lock_irqsave(&igb->tmreg_lock, flags);
556 		tsim = rd32(E1000_TSIM);
557 		if (on)
558 			tsim |= TSINTR_SYS_WRAP;
559 		else
560 			tsim &= ~TSINTR_SYS_WRAP;
561 		wr32(E1000_TSIM, tsim);
562 		spin_unlock_irqrestore(&igb->tmreg_lock, flags);
563 		return 0;
564 	}
565 
566 	return -EOPNOTSUPP;
567 }
568 
569 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
570 				  struct ptp_clock_request *rq, int on)
571 {
572 	return -EOPNOTSUPP;
573 }
574 
575 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
576 			      enum ptp_pin_function func, unsigned int chan)
577 {
578 	switch (func) {
579 	case PTP_PF_NONE:
580 	case PTP_PF_EXTTS:
581 	case PTP_PF_PEROUT:
582 		break;
583 	case PTP_PF_PHYSYNC:
584 		return -1;
585 	}
586 	return 0;
587 }
588 
589 /**
590  * igb_ptp_tx_work
591  * @work: pointer to work struct
592  *
593  * This work function polls the TSYNCTXCTL valid bit to determine when a
594  * timestamp has been taken for the current stored skb.
595  **/
596 static void igb_ptp_tx_work(struct work_struct *work)
597 {
598 	struct igb_adapter *adapter = container_of(work, struct igb_adapter,
599 						   ptp_tx_work);
600 	struct e1000_hw *hw = &adapter->hw;
601 	u32 tsynctxctl;
602 
603 	if (!adapter->ptp_tx_skb)
604 		return;
605 
606 	if (time_is_before_jiffies(adapter->ptp_tx_start +
607 				   IGB_PTP_TX_TIMEOUT)) {
608 		dev_kfree_skb_any(adapter->ptp_tx_skb);
609 		adapter->ptp_tx_skb = NULL;
610 		clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
611 		adapter->tx_hwtstamp_timeouts++;
612 		dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
613 		return;
614 	}
615 
616 	tsynctxctl = rd32(E1000_TSYNCTXCTL);
617 	if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
618 		igb_ptp_tx_hwtstamp(adapter);
619 	else
620 		/* reschedule to check later */
621 		schedule_work(&adapter->ptp_tx_work);
622 }
623 
624 static void igb_ptp_overflow_check(struct work_struct *work)
625 {
626 	struct igb_adapter *igb =
627 		container_of(work, struct igb_adapter, ptp_overflow_work.work);
628 	struct timespec64 ts;
629 
630 	igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
631 
632 	pr_debug("igb overflow check at %lld.%09lu\n",
633 		 (long long) ts.tv_sec, ts.tv_nsec);
634 
635 	schedule_delayed_work(&igb->ptp_overflow_work,
636 			      IGB_SYSTIM_OVERFLOW_PERIOD);
637 }
638 
639 /**
640  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
641  * @adapter: private network adapter structure
642  *
643  * This watchdog task is scheduled to detect error case where hardware has
644  * dropped an Rx packet that was timestamped when the ring is full. The
645  * particular error is rare but leaves the device in a state unable to timestamp
646  * any future packets.
647  **/
648 void igb_ptp_rx_hang(struct igb_adapter *adapter)
649 {
650 	struct e1000_hw *hw = &adapter->hw;
651 	u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
652 	unsigned long rx_event;
653 
654 	if (hw->mac.type != e1000_82576)
655 		return;
656 
657 	/* If we don't have a valid timestamp in the registers, just update the
658 	 * timeout counter and exit
659 	 */
660 	if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
661 		adapter->last_rx_ptp_check = jiffies;
662 		return;
663 	}
664 
665 	/* Determine the most recent watchdog or rx_timestamp event */
666 	rx_event = adapter->last_rx_ptp_check;
667 	if (time_after(adapter->last_rx_timestamp, rx_event))
668 		rx_event = adapter->last_rx_timestamp;
669 
670 	/* Only need to read the high RXSTMP register to clear the lock */
671 	if (time_is_before_jiffies(rx_event + 5 * HZ)) {
672 		rd32(E1000_RXSTMPH);
673 		adapter->last_rx_ptp_check = jiffies;
674 		adapter->rx_hwtstamp_cleared++;
675 		dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
676 	}
677 }
678 
679 /**
680  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
681  * @adapter: Board private structure.
682  *
683  * If we were asked to do hardware stamping and such a time stamp is
684  * available, then it must have been for this skb here because we only
685  * allow only one such packet into the queue.
686  **/
687 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
688 {
689 	struct e1000_hw *hw = &adapter->hw;
690 	struct skb_shared_hwtstamps shhwtstamps;
691 	u64 regval;
692 
693 	regval = rd32(E1000_TXSTMPL);
694 	regval |= (u64)rd32(E1000_TXSTMPH) << 32;
695 
696 	igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
697 	skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
698 	dev_kfree_skb_any(adapter->ptp_tx_skb);
699 	adapter->ptp_tx_skb = NULL;
700 	clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
701 }
702 
703 /**
704  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
705  * @q_vector: Pointer to interrupt specific structure
706  * @va: Pointer to address containing Rx buffer
707  * @skb: Buffer containing timestamp and packet
708  *
709  * This function is meant to retrieve a timestamp from the first buffer of an
710  * incoming frame.  The value is stored in little endian format starting on
711  * byte 8.
712  **/
713 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
714 			 unsigned char *va,
715 			 struct sk_buff *skb)
716 {
717 	__le64 *regval = (__le64 *)va;
718 
719 	/* The timestamp is recorded in little endian format.
720 	 * DWORD: 0        1        2        3
721 	 * Field: Reserved Reserved SYSTIML  SYSTIMH
722 	 */
723 	igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
724 				   le64_to_cpu(regval[1]));
725 }
726 
727 /**
728  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
729  * @q_vector: Pointer to interrupt specific structure
730  * @skb: Buffer containing timestamp and packet
731  *
732  * This function is meant to retrieve a timestamp from the internal registers
733  * of the adapter and store it in the skb.
734  **/
735 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
736 			 struct sk_buff *skb)
737 {
738 	struct igb_adapter *adapter = q_vector->adapter;
739 	struct e1000_hw *hw = &adapter->hw;
740 	u64 regval;
741 
742 	/* If this bit is set, then the RX registers contain the time stamp. No
743 	 * other packet will be time stamped until we read these registers, so
744 	 * read the registers to make them available again. Because only one
745 	 * packet can be time stamped at a time, we know that the register
746 	 * values must belong to this one here and therefore we don't need to
747 	 * compare any of the additional attributes stored for it.
748 	 *
749 	 * If nothing went wrong, then it should have a shared tx_flags that we
750 	 * can turn into a skb_shared_hwtstamps.
751 	 */
752 	if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
753 		return;
754 
755 	regval = rd32(E1000_RXSTMPL);
756 	regval |= (u64)rd32(E1000_RXSTMPH) << 32;
757 
758 	igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
759 
760 	/* Update the last_rx_timestamp timer in order to enable watchdog check
761 	 * for error case of latched timestamp on a dropped packet.
762 	 */
763 	adapter->last_rx_timestamp = jiffies;
764 }
765 
766 /**
767  * igb_ptp_get_ts_config - get hardware time stamping config
768  * @netdev:
769  * @ifreq:
770  *
771  * Get the hwtstamp_config settings to return to the user. Rather than attempt
772  * to deconstruct the settings from the registers, just return a shadow copy
773  * of the last known settings.
774  **/
775 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
776 {
777 	struct igb_adapter *adapter = netdev_priv(netdev);
778 	struct hwtstamp_config *config = &adapter->tstamp_config;
779 
780 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
781 		-EFAULT : 0;
782 }
783 
784 /**
785  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
786  * @adapter: networking device structure
787  * @config: hwtstamp configuration
788  *
789  * Outgoing time stamping can be enabled and disabled. Play nice and
790  * disable it when requested, although it shouldn't case any overhead
791  * when no packet needs it. At most one packet in the queue may be
792  * marked for time stamping, otherwise it would be impossible to tell
793  * for sure to which packet the hardware time stamp belongs.
794  *
795  * Incoming time stamping has to be configured via the hardware
796  * filters. Not all combinations are supported, in particular event
797  * type has to be specified. Matching the kind of event packet is
798  * not supported, with the exception of "all V2 events regardless of
799  * level 2 or 4".
800  */
801 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
802 				      struct hwtstamp_config *config)
803 {
804 	struct e1000_hw *hw = &adapter->hw;
805 	u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
806 	u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
807 	u32 tsync_rx_cfg = 0;
808 	bool is_l4 = false;
809 	bool is_l2 = false;
810 	u32 regval;
811 
812 	/* reserved for future extensions */
813 	if (config->flags)
814 		return -EINVAL;
815 
816 	switch (config->tx_type) {
817 	case HWTSTAMP_TX_OFF:
818 		tsync_tx_ctl = 0;
819 	case HWTSTAMP_TX_ON:
820 		break;
821 	default:
822 		return -ERANGE;
823 	}
824 
825 	switch (config->rx_filter) {
826 	case HWTSTAMP_FILTER_NONE:
827 		tsync_rx_ctl = 0;
828 		break;
829 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
830 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
831 		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
832 		is_l4 = true;
833 		break;
834 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
835 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
836 		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
837 		is_l4 = true;
838 		break;
839 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
840 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
841 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
842 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
843 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
844 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
845 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
846 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
847 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
848 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
849 		config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
850 		is_l2 = true;
851 		is_l4 = true;
852 		break;
853 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
854 	case HWTSTAMP_FILTER_ALL:
855 		/* 82576 cannot timestamp all packets, which it needs to do to
856 		 * support both V1 Sync and Delay_Req messages
857 		 */
858 		if (hw->mac.type != e1000_82576) {
859 			tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
860 			config->rx_filter = HWTSTAMP_FILTER_ALL;
861 			break;
862 		}
863 		/* fall through */
864 	default:
865 		config->rx_filter = HWTSTAMP_FILTER_NONE;
866 		return -ERANGE;
867 	}
868 
869 	if (hw->mac.type == e1000_82575) {
870 		if (tsync_rx_ctl | tsync_tx_ctl)
871 			return -EINVAL;
872 		return 0;
873 	}
874 
875 	/* Per-packet timestamping only works if all packets are
876 	 * timestamped, so enable timestamping in all packets as
877 	 * long as one Rx filter was configured.
878 	 */
879 	if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
880 		tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
881 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
882 		config->rx_filter = HWTSTAMP_FILTER_ALL;
883 		is_l2 = true;
884 		is_l4 = true;
885 
886 		if ((hw->mac.type == e1000_i210) ||
887 		    (hw->mac.type == e1000_i211)) {
888 			regval = rd32(E1000_RXPBS);
889 			regval |= E1000_RXPBS_CFG_TS_EN;
890 			wr32(E1000_RXPBS, regval);
891 		}
892 	}
893 
894 	/* enable/disable TX */
895 	regval = rd32(E1000_TSYNCTXCTL);
896 	regval &= ~E1000_TSYNCTXCTL_ENABLED;
897 	regval |= tsync_tx_ctl;
898 	wr32(E1000_TSYNCTXCTL, regval);
899 
900 	/* enable/disable RX */
901 	regval = rd32(E1000_TSYNCRXCTL);
902 	regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
903 	regval |= tsync_rx_ctl;
904 	wr32(E1000_TSYNCRXCTL, regval);
905 
906 	/* define which PTP packets are time stamped */
907 	wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
908 
909 	/* define ethertype filter for timestamped packets */
910 	if (is_l2)
911 		wr32(E1000_ETQF(3),
912 		     (E1000_ETQF_FILTER_ENABLE | /* enable filter */
913 		      E1000_ETQF_1588 | /* enable timestamping */
914 		      ETH_P_1588));     /* 1588 eth protocol type */
915 	else
916 		wr32(E1000_ETQF(3), 0);
917 
918 	/* L4 Queue Filter[3]: filter by destination port and protocol */
919 	if (is_l4) {
920 		u32 ftqf = (IPPROTO_UDP /* UDP */
921 			| E1000_FTQF_VF_BP /* VF not compared */
922 			| E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
923 			| E1000_FTQF_MASK); /* mask all inputs */
924 		ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
925 
926 		wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
927 		wr32(E1000_IMIREXT(3),
928 		     (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
929 		if (hw->mac.type == e1000_82576) {
930 			/* enable source port check */
931 			wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
932 			ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
933 		}
934 		wr32(E1000_FTQF(3), ftqf);
935 	} else {
936 		wr32(E1000_FTQF(3), E1000_FTQF_MASK);
937 	}
938 	wrfl();
939 
940 	/* clear TX/RX time stamp registers, just to be sure */
941 	regval = rd32(E1000_TXSTMPL);
942 	regval = rd32(E1000_TXSTMPH);
943 	regval = rd32(E1000_RXSTMPL);
944 	regval = rd32(E1000_RXSTMPH);
945 
946 	return 0;
947 }
948 
949 /**
950  * igb_ptp_set_ts_config - set hardware time stamping config
951  * @netdev:
952  * @ifreq:
953  *
954  **/
955 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
956 {
957 	struct igb_adapter *adapter = netdev_priv(netdev);
958 	struct hwtstamp_config config;
959 	int err;
960 
961 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
962 		return -EFAULT;
963 
964 	err = igb_ptp_set_timestamp_mode(adapter, &config);
965 	if (err)
966 		return err;
967 
968 	/* save these settings for future reference */
969 	memcpy(&adapter->tstamp_config, &config,
970 	       sizeof(adapter->tstamp_config));
971 
972 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
973 		-EFAULT : 0;
974 }
975 
976 void igb_ptp_init(struct igb_adapter *adapter)
977 {
978 	struct e1000_hw *hw = &adapter->hw;
979 	struct net_device *netdev = adapter->netdev;
980 	int i;
981 
982 	switch (hw->mac.type) {
983 	case e1000_82576:
984 		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
985 		adapter->ptp_caps.owner = THIS_MODULE;
986 		adapter->ptp_caps.max_adj = 999999881;
987 		adapter->ptp_caps.n_ext_ts = 0;
988 		adapter->ptp_caps.pps = 0;
989 		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
990 		adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
991 		adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
992 		adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
993 		adapter->ptp_caps.enable = igb_ptp_feature_enable;
994 		adapter->cc.read = igb_ptp_read_82576;
995 		adapter->cc.mask = CYCLECOUNTER_MASK(64);
996 		adapter->cc.mult = 1;
997 		adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
998 		/* Dial the nominal frequency. */
999 		wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1000 		break;
1001 	case e1000_82580:
1002 	case e1000_i354:
1003 	case e1000_i350:
1004 		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1005 		adapter->ptp_caps.owner = THIS_MODULE;
1006 		adapter->ptp_caps.max_adj = 62499999;
1007 		adapter->ptp_caps.n_ext_ts = 0;
1008 		adapter->ptp_caps.pps = 0;
1009 		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1010 		adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1011 		adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1012 		adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1013 		adapter->ptp_caps.enable = igb_ptp_feature_enable;
1014 		adapter->cc.read = igb_ptp_read_82580;
1015 		adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1016 		adapter->cc.mult = 1;
1017 		adapter->cc.shift = 0;
1018 		/* Enable the timer functions by clearing bit 31. */
1019 		wr32(E1000_TSAUXC, 0x0);
1020 		break;
1021 	case e1000_i210:
1022 	case e1000_i211:
1023 		for (i = 0; i < IGB_N_SDP; i++) {
1024 			struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1025 
1026 			snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1027 			ppd->index = i;
1028 			ppd->func = PTP_PF_NONE;
1029 		}
1030 		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1031 		adapter->ptp_caps.owner = THIS_MODULE;
1032 		adapter->ptp_caps.max_adj = 62499999;
1033 		adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1034 		adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1035 		adapter->ptp_caps.n_pins = IGB_N_SDP;
1036 		adapter->ptp_caps.pps = 1;
1037 		adapter->ptp_caps.pin_config = adapter->sdp_config;
1038 		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1039 		adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1040 		adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1041 		adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1042 		adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1043 		adapter->ptp_caps.verify = igb_ptp_verify_pin;
1044 		/* Enable the timer functions by clearing bit 31. */
1045 		wr32(E1000_TSAUXC, 0x0);
1046 		break;
1047 	default:
1048 		adapter->ptp_clock = NULL;
1049 		return;
1050 	}
1051 
1052 	wrfl();
1053 
1054 	spin_lock_init(&adapter->tmreg_lock);
1055 	INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1056 
1057 	/* Initialize the clock and overflow work for devices that need it. */
1058 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1059 		struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1060 
1061 		igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1062 	} else {
1063 		timecounter_init(&adapter->tc, &adapter->cc,
1064 				 ktime_to_ns(ktime_get_real()));
1065 
1066 		INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1067 				  igb_ptp_overflow_check);
1068 
1069 		schedule_delayed_work(&adapter->ptp_overflow_work,
1070 				      IGB_SYSTIM_OVERFLOW_PERIOD);
1071 	}
1072 
1073 	/* Initialize the time sync interrupts for devices that support it. */
1074 	if (hw->mac.type >= e1000_82580) {
1075 		wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1076 		wr32(E1000_IMS, E1000_IMS_TS);
1077 	}
1078 
1079 	adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1080 	adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1081 
1082 	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1083 						&adapter->pdev->dev);
1084 	if (IS_ERR(adapter->ptp_clock)) {
1085 		adapter->ptp_clock = NULL;
1086 		dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1087 	} else {
1088 		dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1089 			 adapter->netdev->name);
1090 		adapter->flags |= IGB_FLAG_PTP;
1091 	}
1092 }
1093 
1094 /**
1095  * igb_ptp_stop - Disable PTP device and stop the overflow check.
1096  * @adapter: Board private structure.
1097  *
1098  * This function stops the PTP support and cancels the delayed work.
1099  **/
1100 void igb_ptp_stop(struct igb_adapter *adapter)
1101 {
1102 	switch (adapter->hw.mac.type) {
1103 	case e1000_82576:
1104 	case e1000_82580:
1105 	case e1000_i354:
1106 	case e1000_i350:
1107 		cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1108 		break;
1109 	case e1000_i210:
1110 	case e1000_i211:
1111 		/* No delayed work to cancel. */
1112 		break;
1113 	default:
1114 		return;
1115 	}
1116 
1117 	cancel_work_sync(&adapter->ptp_tx_work);
1118 	if (adapter->ptp_tx_skb) {
1119 		dev_kfree_skb_any(adapter->ptp_tx_skb);
1120 		adapter->ptp_tx_skb = NULL;
1121 		clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1122 	}
1123 
1124 	if (adapter->ptp_clock) {
1125 		ptp_clock_unregister(adapter->ptp_clock);
1126 		dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1127 			 adapter->netdev->name);
1128 		adapter->flags &= ~IGB_FLAG_PTP;
1129 	}
1130 }
1131 
1132 /**
1133  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1134  * @adapter: Board private structure.
1135  *
1136  * This function handles the reset work required to re-enable the PTP device.
1137  **/
1138 void igb_ptp_reset(struct igb_adapter *adapter)
1139 {
1140 	struct e1000_hw *hw = &adapter->hw;
1141 	unsigned long flags;
1142 
1143 	if (!(adapter->flags & IGB_FLAG_PTP))
1144 		return;
1145 
1146 	/* reset the tstamp_config */
1147 	igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1148 
1149 	spin_lock_irqsave(&adapter->tmreg_lock, flags);
1150 
1151 	switch (adapter->hw.mac.type) {
1152 	case e1000_82576:
1153 		/* Dial the nominal frequency. */
1154 		wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1155 		break;
1156 	case e1000_82580:
1157 	case e1000_i354:
1158 	case e1000_i350:
1159 	case e1000_i210:
1160 	case e1000_i211:
1161 		wr32(E1000_TSAUXC, 0x0);
1162 		wr32(E1000_TSSDP, 0x0);
1163 		wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1164 		wr32(E1000_IMS, E1000_IMS_TS);
1165 		break;
1166 	default:
1167 		/* No work to do. */
1168 		goto out;
1169 	}
1170 
1171 	/* Re-initialize the timer. */
1172 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1173 		struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1174 
1175 		igb_ptp_write_i210(adapter, &ts);
1176 	} else {
1177 		timecounter_init(&adapter->tc, &adapter->cc,
1178 				 ktime_to_ns(ktime_get_real()));
1179 	}
1180 out:
1181 	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1182 }
1183