1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 2 * 3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/pci.h> 21 #include <linux/ptp_classify.h> 22 23 #include "igb.h" 24 25 #define INCVALUE_MASK 0x7fffffff 26 #define ISGN 0x80000000 27 28 /* The 82580 timesync updates the system timer every 8ns by 8ns, 29 * and this update value cannot be reprogrammed. 30 * 31 * Neither the 82576 nor the 82580 offer registers wide enough to hold 32 * nanoseconds time values for very long. For the 82580, SYSTIM always 33 * counts nanoseconds, but the upper 24 bits are not available. The 34 * frequency is adjusted by changing the 32 bit fractional nanoseconds 35 * register, TIMINCA. 36 * 37 * For the 82576, the SYSTIM register time unit is affect by the 38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 39 * field are needed to provide the nominal 16 nanosecond period, 40 * leaving 19 bits for fractional nanoseconds. 41 * 42 * We scale the NIC clock cycle by a large factor so that relatively 43 * small clock corrections can be added or subtracted at each clock 44 * tick. The drawbacks of a large factor are a) that the clock 45 * register overflows more quickly (not such a big deal) and b) that 46 * the increment per tick has to fit into 24 bits. As a result we 47 * need to use a shift of 19 so we can fit a value of 16 into the 48 * TIMINCA register. 49 * 50 * 51 * SYSTIMH SYSTIML 52 * +--------------+ +---+---+------+ 53 * 82576 | 32 | | 8 | 5 | 19 | 54 * +--------------+ +---+---+------+ 55 * \________ 45 bits _______/ fract 56 * 57 * +----------+---+ +--------------+ 58 * 82580 | 24 | 8 | | 32 | 59 * +----------+---+ +--------------+ 60 * reserved \______ 40 bits _____/ 61 * 62 * 63 * The 45 bit 82576 SYSTIM overflows every 64 * 2^45 * 10^-9 / 3600 = 9.77 hours. 65 * 66 * The 40 bit 82580 SYSTIM overflows every 67 * 2^40 * 10^-9 / 60 = 18.3 minutes. 68 */ 69 70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 71 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 72 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 73 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 74 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 75 #define IGB_NBITS_82580 40 76 77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 78 79 /* SYSTIM read access for the 82576 */ 80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) 81 { 82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 83 struct e1000_hw *hw = &igb->hw; 84 u64 val; 85 u32 lo, hi; 86 87 lo = rd32(E1000_SYSTIML); 88 hi = rd32(E1000_SYSTIMH); 89 90 val = ((u64) hi) << 32; 91 val |= lo; 92 93 return val; 94 } 95 96 /* SYSTIM read access for the 82580 */ 97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) 98 { 99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 100 struct e1000_hw *hw = &igb->hw; 101 u32 lo, hi; 102 u64 val; 103 104 /* The timestamp latches on lowest register read. For the 82580 105 * the lowest register is SYSTIMR instead of SYSTIML. However we only 106 * need to provide nanosecond resolution, so we just ignore it. 107 */ 108 rd32(E1000_SYSTIMR); 109 lo = rd32(E1000_SYSTIML); 110 hi = rd32(E1000_SYSTIMH); 111 112 val = ((u64) hi) << 32; 113 val |= lo; 114 115 return val; 116 } 117 118 /* SYSTIM read access for I210/I211 */ 119 static void igb_ptp_read_i210(struct igb_adapter *adapter, 120 struct timespec64 *ts) 121 { 122 struct e1000_hw *hw = &adapter->hw; 123 u32 sec, nsec; 124 125 /* The timestamp latches on lowest register read. For I210/I211, the 126 * lowest register is SYSTIMR. Since we only need to provide nanosecond 127 * resolution, we can ignore it. 128 */ 129 rd32(E1000_SYSTIMR); 130 nsec = rd32(E1000_SYSTIML); 131 sec = rd32(E1000_SYSTIMH); 132 133 ts->tv_sec = sec; 134 ts->tv_nsec = nsec; 135 } 136 137 static void igb_ptp_write_i210(struct igb_adapter *adapter, 138 const struct timespec64 *ts) 139 { 140 struct e1000_hw *hw = &adapter->hw; 141 142 /* Writing the SYSTIMR register is not necessary as it only provides 143 * sub-nanosecond resolution. 144 */ 145 wr32(E1000_SYSTIML, ts->tv_nsec); 146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 147 } 148 149 /** 150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 151 * @adapter: board private structure 152 * @hwtstamps: timestamp structure to update 153 * @systim: unsigned 64bit system time value. 154 * 155 * We need to convert the system time value stored in the RX/TXSTMP registers 156 * into a hwtstamp which can be used by the upper level timestamping functions. 157 * 158 * The 'tmreg_lock' spinlock is used to protect the consistency of the 159 * system time value. This is needed because reading the 64 bit time 160 * value involves reading two (or three) 32 bit registers. The first 161 * read latches the value. Ditto for writing. 162 * 163 * In addition, here have extended the system time with an overflow 164 * counter in software. 165 **/ 166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 167 struct skb_shared_hwtstamps *hwtstamps, 168 u64 systim) 169 { 170 unsigned long flags; 171 u64 ns; 172 173 switch (adapter->hw.mac.type) { 174 case e1000_82576: 175 case e1000_82580: 176 case e1000_i354: 177 case e1000_i350: 178 spin_lock_irqsave(&adapter->tmreg_lock, flags); 179 180 ns = timecounter_cyc2time(&adapter->tc, systim); 181 182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 183 184 memset(hwtstamps, 0, sizeof(*hwtstamps)); 185 hwtstamps->hwtstamp = ns_to_ktime(ns); 186 break; 187 case e1000_i210: 188 case e1000_i211: 189 memset(hwtstamps, 0, sizeof(*hwtstamps)); 190 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 191 hwtstamps->hwtstamp = ktime_set(systim >> 32, 192 systim & 0xFFFFFFFF); 193 break; 194 default: 195 break; 196 } 197 } 198 199 /* PTP clock operations */ 200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 201 { 202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 203 ptp_caps); 204 struct e1000_hw *hw = &igb->hw; 205 int neg_adj = 0; 206 u64 rate; 207 u32 incvalue; 208 209 if (ppb < 0) { 210 neg_adj = 1; 211 ppb = -ppb; 212 } 213 rate = ppb; 214 rate <<= 14; 215 rate = div_u64(rate, 1953125); 216 217 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 218 219 if (neg_adj) 220 incvalue -= rate; 221 else 222 incvalue += rate; 223 224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 225 226 return 0; 227 } 228 229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) 230 { 231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 232 ptp_caps); 233 struct e1000_hw *hw = &igb->hw; 234 int neg_adj = 0; 235 u64 rate; 236 u32 inca; 237 238 if (ppb < 0) { 239 neg_adj = 1; 240 ppb = -ppb; 241 } 242 rate = ppb; 243 rate <<= 26; 244 rate = div_u64(rate, 1953125); 245 246 inca = rate & INCVALUE_MASK; 247 if (neg_adj) 248 inca |= ISGN; 249 250 wr32(E1000_TIMINCA, inca); 251 252 return 0; 253 } 254 255 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 256 { 257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 258 ptp_caps); 259 unsigned long flags; 260 261 spin_lock_irqsave(&igb->tmreg_lock, flags); 262 timecounter_adjtime(&igb->tc, delta); 263 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 264 265 return 0; 266 } 267 268 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 269 { 270 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 271 ptp_caps); 272 unsigned long flags; 273 struct timespec64 now, then = ns_to_timespec64(delta); 274 275 spin_lock_irqsave(&igb->tmreg_lock, flags); 276 277 igb_ptp_read_i210(igb, &now); 278 now = timespec64_add(now, then); 279 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 280 281 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 282 283 return 0; 284 } 285 286 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 287 struct timespec64 *ts) 288 { 289 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 290 ptp_caps); 291 unsigned long flags; 292 u64 ns; 293 294 spin_lock_irqsave(&igb->tmreg_lock, flags); 295 296 ns = timecounter_read(&igb->tc); 297 298 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 299 300 *ts = ns_to_timespec64(ns); 301 302 return 0; 303 } 304 305 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 306 struct timespec64 *ts) 307 { 308 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 309 ptp_caps); 310 unsigned long flags; 311 312 spin_lock_irqsave(&igb->tmreg_lock, flags); 313 314 igb_ptp_read_i210(igb, ts); 315 316 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 317 318 return 0; 319 } 320 321 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 322 const struct timespec64 *ts) 323 { 324 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 325 ptp_caps); 326 unsigned long flags; 327 u64 ns; 328 329 ns = timespec64_to_ns(ts); 330 331 spin_lock_irqsave(&igb->tmreg_lock, flags); 332 333 timecounter_init(&igb->tc, &igb->cc, ns); 334 335 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 336 337 return 0; 338 } 339 340 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 341 const struct timespec64 *ts) 342 { 343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 344 ptp_caps); 345 unsigned long flags; 346 347 spin_lock_irqsave(&igb->tmreg_lock, flags); 348 349 igb_ptp_write_i210(igb, ts); 350 351 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 352 353 return 0; 354 } 355 356 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 357 { 358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 359 static const u32 mask[IGB_N_SDP] = { 360 E1000_CTRL_SDP0_DIR, 361 E1000_CTRL_SDP1_DIR, 362 E1000_CTRL_EXT_SDP2_DIR, 363 E1000_CTRL_EXT_SDP3_DIR, 364 }; 365 366 if (input) 367 *ptr &= ~mask[pin]; 368 else 369 *ptr |= mask[pin]; 370 } 371 372 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 373 { 374 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 375 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 376 }; 377 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 378 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 379 }; 380 static const u32 ts_sdp_en[IGB_N_SDP] = { 381 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 382 }; 383 struct e1000_hw *hw = &igb->hw; 384 u32 ctrl, ctrl_ext, tssdp = 0; 385 386 ctrl = rd32(E1000_CTRL); 387 ctrl_ext = rd32(E1000_CTRL_EXT); 388 tssdp = rd32(E1000_TSSDP); 389 390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 391 392 /* Make sure this pin is not enabled as an output. */ 393 tssdp &= ~ts_sdp_en[pin]; 394 395 if (chan == 1) { 396 tssdp &= ~AUX1_SEL_SDP3; 397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 398 } else { 399 tssdp &= ~AUX0_SEL_SDP3; 400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 401 } 402 403 wr32(E1000_TSSDP, tssdp); 404 wr32(E1000_CTRL, ctrl); 405 wr32(E1000_CTRL_EXT, ctrl_ext); 406 } 407 408 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 409 { 410 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 412 }; 413 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 415 }; 416 static const u32 ts_sdp_en[IGB_N_SDP] = { 417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 418 }; 419 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 420 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 421 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 422 }; 423 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 424 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 425 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 426 }; 427 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 428 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 429 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 430 }; 431 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 432 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 433 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 434 }; 435 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 436 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 437 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 438 }; 439 struct e1000_hw *hw = &igb->hw; 440 u32 ctrl, ctrl_ext, tssdp = 0; 441 442 ctrl = rd32(E1000_CTRL); 443 ctrl_ext = rd32(E1000_CTRL_EXT); 444 tssdp = rd32(E1000_TSSDP); 445 446 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 447 448 /* Make sure this pin is not enabled as an input. */ 449 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 450 tssdp &= ~AUX0_TS_SDP_EN; 451 452 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 453 tssdp &= ~AUX1_TS_SDP_EN; 454 455 tssdp &= ~ts_sdp_sel_clr[pin]; 456 if (freq) { 457 if (chan == 1) 458 tssdp |= ts_sdp_sel_fc1[pin]; 459 else 460 tssdp |= ts_sdp_sel_fc0[pin]; 461 } else { 462 if (chan == 1) 463 tssdp |= ts_sdp_sel_tt1[pin]; 464 else 465 tssdp |= ts_sdp_sel_tt0[pin]; 466 } 467 tssdp |= ts_sdp_en[pin]; 468 469 wr32(E1000_TSSDP, tssdp); 470 wr32(E1000_CTRL, ctrl); 471 wr32(E1000_CTRL_EXT, ctrl_ext); 472 } 473 474 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 475 struct ptp_clock_request *rq, int on) 476 { 477 struct igb_adapter *igb = 478 container_of(ptp, struct igb_adapter, ptp_caps); 479 struct e1000_hw *hw = &igb->hw; 480 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 481 unsigned long flags; 482 struct timespec64 ts; 483 int use_freq = 0, pin = -1; 484 s64 ns; 485 486 switch (rq->type) { 487 case PTP_CLK_REQ_EXTTS: 488 if (on) { 489 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 490 rq->extts.index); 491 if (pin < 0) 492 return -EBUSY; 493 } 494 if (rq->extts.index == 1) { 495 tsauxc_mask = TSAUXC_EN_TS1; 496 tsim_mask = TSINTR_AUTT1; 497 } else { 498 tsauxc_mask = TSAUXC_EN_TS0; 499 tsim_mask = TSINTR_AUTT0; 500 } 501 spin_lock_irqsave(&igb->tmreg_lock, flags); 502 tsauxc = rd32(E1000_TSAUXC); 503 tsim = rd32(E1000_TSIM); 504 if (on) { 505 igb_pin_extts(igb, rq->extts.index, pin); 506 tsauxc |= tsauxc_mask; 507 tsim |= tsim_mask; 508 } else { 509 tsauxc &= ~tsauxc_mask; 510 tsim &= ~tsim_mask; 511 } 512 wr32(E1000_TSAUXC, tsauxc); 513 wr32(E1000_TSIM, tsim); 514 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 515 return 0; 516 517 case PTP_CLK_REQ_PEROUT: 518 if (on) { 519 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 520 rq->perout.index); 521 if (pin < 0) 522 return -EBUSY; 523 } 524 ts.tv_sec = rq->perout.period.sec; 525 ts.tv_nsec = rq->perout.period.nsec; 526 ns = timespec64_to_ns(&ts); 527 ns = ns >> 1; 528 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 529 (ns == 250000000LL) || (ns == 500000000LL))) { 530 if (ns < 8LL) 531 return -EINVAL; 532 use_freq = 1; 533 } 534 ts = ns_to_timespec64(ns); 535 if (rq->perout.index == 1) { 536 if (use_freq) { 537 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 538 tsim_mask = 0; 539 } else { 540 tsauxc_mask = TSAUXC_EN_TT1; 541 tsim_mask = TSINTR_TT1; 542 } 543 trgttiml = E1000_TRGTTIML1; 544 trgttimh = E1000_TRGTTIMH1; 545 freqout = E1000_FREQOUT1; 546 } else { 547 if (use_freq) { 548 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 549 tsim_mask = 0; 550 } else { 551 tsauxc_mask = TSAUXC_EN_TT0; 552 tsim_mask = TSINTR_TT0; 553 } 554 trgttiml = E1000_TRGTTIML0; 555 trgttimh = E1000_TRGTTIMH0; 556 freqout = E1000_FREQOUT0; 557 } 558 spin_lock_irqsave(&igb->tmreg_lock, flags); 559 tsauxc = rd32(E1000_TSAUXC); 560 tsim = rd32(E1000_TSIM); 561 if (rq->perout.index == 1) { 562 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 563 tsim &= ~TSINTR_TT1; 564 } else { 565 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 566 tsim &= ~TSINTR_TT0; 567 } 568 if (on) { 569 int i = rq->perout.index; 570 igb_pin_perout(igb, i, pin, use_freq); 571 igb->perout[i].start.tv_sec = rq->perout.start.sec; 572 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 573 igb->perout[i].period.tv_sec = ts.tv_sec; 574 igb->perout[i].period.tv_nsec = ts.tv_nsec; 575 wr32(trgttimh, rq->perout.start.sec); 576 wr32(trgttiml, rq->perout.start.nsec); 577 if (use_freq) 578 wr32(freqout, ns); 579 tsauxc |= tsauxc_mask; 580 tsim |= tsim_mask; 581 } 582 wr32(E1000_TSAUXC, tsauxc); 583 wr32(E1000_TSIM, tsim); 584 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 585 return 0; 586 587 case PTP_CLK_REQ_PPS: 588 spin_lock_irqsave(&igb->tmreg_lock, flags); 589 tsim = rd32(E1000_TSIM); 590 if (on) 591 tsim |= TSINTR_SYS_WRAP; 592 else 593 tsim &= ~TSINTR_SYS_WRAP; 594 igb->pps_sys_wrap_on = !!on; 595 wr32(E1000_TSIM, tsim); 596 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 597 return 0; 598 } 599 600 return -EOPNOTSUPP; 601 } 602 603 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 604 struct ptp_clock_request *rq, int on) 605 { 606 return -EOPNOTSUPP; 607 } 608 609 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 610 enum ptp_pin_function func, unsigned int chan) 611 { 612 switch (func) { 613 case PTP_PF_NONE: 614 case PTP_PF_EXTTS: 615 case PTP_PF_PEROUT: 616 break; 617 case PTP_PF_PHYSYNC: 618 return -1; 619 } 620 return 0; 621 } 622 623 /** 624 * igb_ptp_tx_work 625 * @work: pointer to work struct 626 * 627 * This work function polls the TSYNCTXCTL valid bit to determine when a 628 * timestamp has been taken for the current stored skb. 629 **/ 630 static void igb_ptp_tx_work(struct work_struct *work) 631 { 632 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 633 ptp_tx_work); 634 struct e1000_hw *hw = &adapter->hw; 635 u32 tsynctxctl; 636 637 if (!adapter->ptp_tx_skb) 638 return; 639 640 if (time_is_before_jiffies(adapter->ptp_tx_start + 641 IGB_PTP_TX_TIMEOUT)) { 642 dev_kfree_skb_any(adapter->ptp_tx_skb); 643 adapter->ptp_tx_skb = NULL; 644 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 645 adapter->tx_hwtstamp_timeouts++; 646 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 647 return; 648 } 649 650 tsynctxctl = rd32(E1000_TSYNCTXCTL); 651 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 652 igb_ptp_tx_hwtstamp(adapter); 653 else 654 /* reschedule to check later */ 655 schedule_work(&adapter->ptp_tx_work); 656 } 657 658 static void igb_ptp_overflow_check(struct work_struct *work) 659 { 660 struct igb_adapter *igb = 661 container_of(work, struct igb_adapter, ptp_overflow_work.work); 662 struct timespec64 ts; 663 664 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts); 665 666 pr_debug("igb overflow check at %lld.%09lu\n", 667 (long long) ts.tv_sec, ts.tv_nsec); 668 669 schedule_delayed_work(&igb->ptp_overflow_work, 670 IGB_SYSTIM_OVERFLOW_PERIOD); 671 } 672 673 /** 674 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 675 * @adapter: private network adapter structure 676 * 677 * This watchdog task is scheduled to detect error case where hardware has 678 * dropped an Rx packet that was timestamped when the ring is full. The 679 * particular error is rare but leaves the device in a state unable to timestamp 680 * any future packets. 681 **/ 682 void igb_ptp_rx_hang(struct igb_adapter *adapter) 683 { 684 struct e1000_hw *hw = &adapter->hw; 685 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 686 unsigned long rx_event; 687 688 /* Other hardware uses per-packet timestamps */ 689 if (hw->mac.type != e1000_82576) 690 return; 691 692 /* If we don't have a valid timestamp in the registers, just update the 693 * timeout counter and exit 694 */ 695 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 696 adapter->last_rx_ptp_check = jiffies; 697 return; 698 } 699 700 /* Determine the most recent watchdog or rx_timestamp event */ 701 rx_event = adapter->last_rx_ptp_check; 702 if (time_after(adapter->last_rx_timestamp, rx_event)) 703 rx_event = adapter->last_rx_timestamp; 704 705 /* Only need to read the high RXSTMP register to clear the lock */ 706 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 707 rd32(E1000_RXSTMPH); 708 adapter->last_rx_ptp_check = jiffies; 709 adapter->rx_hwtstamp_cleared++; 710 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 711 } 712 } 713 714 /** 715 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 716 * @adapter: Board private structure. 717 * 718 * If we were asked to do hardware stamping and such a time stamp is 719 * available, then it must have been for this skb here because we only 720 * allow only one such packet into the queue. 721 **/ 722 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 723 { 724 struct e1000_hw *hw = &adapter->hw; 725 struct skb_shared_hwtstamps shhwtstamps; 726 u64 regval; 727 int adjust = 0; 728 729 regval = rd32(E1000_TXSTMPL); 730 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 731 732 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 733 /* adjust timestamp for the TX latency based on link speed */ 734 if (adapter->hw.mac.type == e1000_i210) { 735 switch (adapter->link_speed) { 736 case SPEED_10: 737 adjust = IGB_I210_TX_LATENCY_10; 738 break; 739 case SPEED_100: 740 adjust = IGB_I210_TX_LATENCY_100; 741 break; 742 case SPEED_1000: 743 adjust = IGB_I210_TX_LATENCY_1000; 744 break; 745 } 746 } 747 748 shhwtstamps.hwtstamp = 749 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 750 751 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 752 dev_kfree_skb_any(adapter->ptp_tx_skb); 753 adapter->ptp_tx_skb = NULL; 754 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 755 } 756 757 /** 758 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 759 * @q_vector: Pointer to interrupt specific structure 760 * @va: Pointer to address containing Rx buffer 761 * @skb: Buffer containing timestamp and packet 762 * 763 * This function is meant to retrieve a timestamp from the first buffer of an 764 * incoming frame. The value is stored in little endian format starting on 765 * byte 8. 766 **/ 767 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 768 unsigned char *va, 769 struct sk_buff *skb) 770 { 771 __le64 *regval = (__le64 *)va; 772 struct igb_adapter *adapter = q_vector->adapter; 773 int adjust = 0; 774 775 /* The timestamp is recorded in little endian format. 776 * DWORD: 0 1 2 3 777 * Field: Reserved Reserved SYSTIML SYSTIMH 778 */ 779 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), 780 le64_to_cpu(regval[1])); 781 782 /* adjust timestamp for the RX latency based on link speed */ 783 if (adapter->hw.mac.type == e1000_i210) { 784 switch (adapter->link_speed) { 785 case SPEED_10: 786 adjust = IGB_I210_RX_LATENCY_10; 787 break; 788 case SPEED_100: 789 adjust = IGB_I210_RX_LATENCY_100; 790 break; 791 case SPEED_1000: 792 adjust = IGB_I210_RX_LATENCY_1000; 793 break; 794 } 795 } 796 skb_hwtstamps(skb)->hwtstamp = 797 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 798 } 799 800 /** 801 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 802 * @q_vector: Pointer to interrupt specific structure 803 * @skb: Buffer containing timestamp and packet 804 * 805 * This function is meant to retrieve a timestamp from the internal registers 806 * of the adapter and store it in the skb. 807 **/ 808 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 809 struct sk_buff *skb) 810 { 811 struct igb_adapter *adapter = q_vector->adapter; 812 struct e1000_hw *hw = &adapter->hw; 813 u64 regval; 814 int adjust = 0; 815 816 /* If this bit is set, then the RX registers contain the time stamp. No 817 * other packet will be time stamped until we read these registers, so 818 * read the registers to make them available again. Because only one 819 * packet can be time stamped at a time, we know that the register 820 * values must belong to this one here and therefore we don't need to 821 * compare any of the additional attributes stored for it. 822 * 823 * If nothing went wrong, then it should have a shared tx_flags that we 824 * can turn into a skb_shared_hwtstamps. 825 */ 826 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 827 return; 828 829 regval = rd32(E1000_RXSTMPL); 830 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 831 832 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 833 834 /* adjust timestamp for the RX latency based on link speed */ 835 if (adapter->hw.mac.type == e1000_i210) { 836 switch (adapter->link_speed) { 837 case SPEED_10: 838 adjust = IGB_I210_RX_LATENCY_10; 839 break; 840 case SPEED_100: 841 adjust = IGB_I210_RX_LATENCY_100; 842 break; 843 case SPEED_1000: 844 adjust = IGB_I210_RX_LATENCY_1000; 845 break; 846 } 847 } 848 skb_hwtstamps(skb)->hwtstamp = 849 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 850 851 /* Update the last_rx_timestamp timer in order to enable watchdog check 852 * for error case of latched timestamp on a dropped packet. 853 */ 854 adapter->last_rx_timestamp = jiffies; 855 } 856 857 /** 858 * igb_ptp_get_ts_config - get hardware time stamping config 859 * @netdev: 860 * @ifreq: 861 * 862 * Get the hwtstamp_config settings to return to the user. Rather than attempt 863 * to deconstruct the settings from the registers, just return a shadow copy 864 * of the last known settings. 865 **/ 866 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 867 { 868 struct igb_adapter *adapter = netdev_priv(netdev); 869 struct hwtstamp_config *config = &adapter->tstamp_config; 870 871 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 872 -EFAULT : 0; 873 } 874 875 /** 876 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 877 * @adapter: networking device structure 878 * @config: hwtstamp configuration 879 * 880 * Outgoing time stamping can be enabled and disabled. Play nice and 881 * disable it when requested, although it shouldn't case any overhead 882 * when no packet needs it. At most one packet in the queue may be 883 * marked for time stamping, otherwise it would be impossible to tell 884 * for sure to which packet the hardware time stamp belongs. 885 * 886 * Incoming time stamping has to be configured via the hardware 887 * filters. Not all combinations are supported, in particular event 888 * type has to be specified. Matching the kind of event packet is 889 * not supported, with the exception of "all V2 events regardless of 890 * level 2 or 4". 891 */ 892 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 893 struct hwtstamp_config *config) 894 { 895 struct e1000_hw *hw = &adapter->hw; 896 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 897 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 898 u32 tsync_rx_cfg = 0; 899 bool is_l4 = false; 900 bool is_l2 = false; 901 u32 regval; 902 903 /* reserved for future extensions */ 904 if (config->flags) 905 return -EINVAL; 906 907 switch (config->tx_type) { 908 case HWTSTAMP_TX_OFF: 909 tsync_tx_ctl = 0; 910 case HWTSTAMP_TX_ON: 911 break; 912 default: 913 return -ERANGE; 914 } 915 916 switch (config->rx_filter) { 917 case HWTSTAMP_FILTER_NONE: 918 tsync_rx_ctl = 0; 919 break; 920 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 921 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 922 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 923 is_l4 = true; 924 break; 925 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 926 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 927 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 928 is_l4 = true; 929 break; 930 case HWTSTAMP_FILTER_PTP_V2_EVENT: 931 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 932 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 933 case HWTSTAMP_FILTER_PTP_V2_SYNC: 934 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 935 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 936 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 937 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 938 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 939 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 940 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 941 is_l2 = true; 942 is_l4 = true; 943 break; 944 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 945 case HWTSTAMP_FILTER_ALL: 946 /* 82576 cannot timestamp all packets, which it needs to do to 947 * support both V1 Sync and Delay_Req messages 948 */ 949 if (hw->mac.type != e1000_82576) { 950 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 951 config->rx_filter = HWTSTAMP_FILTER_ALL; 952 break; 953 } 954 /* fall through */ 955 default: 956 config->rx_filter = HWTSTAMP_FILTER_NONE; 957 return -ERANGE; 958 } 959 960 if (hw->mac.type == e1000_82575) { 961 if (tsync_rx_ctl | tsync_tx_ctl) 962 return -EINVAL; 963 return 0; 964 } 965 966 /* Per-packet timestamping only works if all packets are 967 * timestamped, so enable timestamping in all packets as 968 * long as one Rx filter was configured. 969 */ 970 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 971 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 972 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 973 config->rx_filter = HWTSTAMP_FILTER_ALL; 974 is_l2 = true; 975 is_l4 = true; 976 977 if ((hw->mac.type == e1000_i210) || 978 (hw->mac.type == e1000_i211)) { 979 regval = rd32(E1000_RXPBS); 980 regval |= E1000_RXPBS_CFG_TS_EN; 981 wr32(E1000_RXPBS, regval); 982 } 983 } 984 985 /* enable/disable TX */ 986 regval = rd32(E1000_TSYNCTXCTL); 987 regval &= ~E1000_TSYNCTXCTL_ENABLED; 988 regval |= tsync_tx_ctl; 989 wr32(E1000_TSYNCTXCTL, regval); 990 991 /* enable/disable RX */ 992 regval = rd32(E1000_TSYNCRXCTL); 993 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 994 regval |= tsync_rx_ctl; 995 wr32(E1000_TSYNCRXCTL, regval); 996 997 /* define which PTP packets are time stamped */ 998 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 999 1000 /* define ethertype filter for timestamped packets */ 1001 if (is_l2) 1002 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1003 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1004 E1000_ETQF_1588 | /* enable timestamping */ 1005 ETH_P_1588)); /* 1588 eth protocol type */ 1006 else 1007 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1008 1009 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1010 if (is_l4) { 1011 u32 ftqf = (IPPROTO_UDP /* UDP */ 1012 | E1000_FTQF_VF_BP /* VF not compared */ 1013 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1014 | E1000_FTQF_MASK); /* mask all inputs */ 1015 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1016 1017 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 1018 wr32(E1000_IMIREXT(3), 1019 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1020 if (hw->mac.type == e1000_82576) { 1021 /* enable source port check */ 1022 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 1023 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1024 } 1025 wr32(E1000_FTQF(3), ftqf); 1026 } else { 1027 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1028 } 1029 wrfl(); 1030 1031 /* clear TX/RX time stamp registers, just to be sure */ 1032 regval = rd32(E1000_TXSTMPL); 1033 regval = rd32(E1000_TXSTMPH); 1034 regval = rd32(E1000_RXSTMPL); 1035 regval = rd32(E1000_RXSTMPH); 1036 1037 return 0; 1038 } 1039 1040 /** 1041 * igb_ptp_set_ts_config - set hardware time stamping config 1042 * @netdev: 1043 * @ifreq: 1044 * 1045 **/ 1046 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1047 { 1048 struct igb_adapter *adapter = netdev_priv(netdev); 1049 struct hwtstamp_config config; 1050 int err; 1051 1052 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1053 return -EFAULT; 1054 1055 err = igb_ptp_set_timestamp_mode(adapter, &config); 1056 if (err) 1057 return err; 1058 1059 /* save these settings for future reference */ 1060 memcpy(&adapter->tstamp_config, &config, 1061 sizeof(adapter->tstamp_config)); 1062 1063 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1064 -EFAULT : 0; 1065 } 1066 1067 /** 1068 * igb_ptp_init - Initialize PTP functionality 1069 * @adapter: Board private structure 1070 * 1071 * This function is called at device probe to initialize the PTP 1072 * functionality. 1073 */ 1074 void igb_ptp_init(struct igb_adapter *adapter) 1075 { 1076 struct e1000_hw *hw = &adapter->hw; 1077 struct net_device *netdev = adapter->netdev; 1078 int i; 1079 1080 switch (hw->mac.type) { 1081 case e1000_82576: 1082 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1083 adapter->ptp_caps.owner = THIS_MODULE; 1084 adapter->ptp_caps.max_adj = 999999881; 1085 adapter->ptp_caps.n_ext_ts = 0; 1086 adapter->ptp_caps.pps = 0; 1087 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1088 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1089 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; 1090 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1091 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1092 adapter->cc.read = igb_ptp_read_82576; 1093 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1094 adapter->cc.mult = 1; 1095 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1096 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1097 break; 1098 case e1000_82580: 1099 case e1000_i354: 1100 case e1000_i350: 1101 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1102 adapter->ptp_caps.owner = THIS_MODULE; 1103 adapter->ptp_caps.max_adj = 62499999; 1104 adapter->ptp_caps.n_ext_ts = 0; 1105 adapter->ptp_caps.pps = 0; 1106 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 1107 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1108 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; 1109 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1110 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1111 adapter->cc.read = igb_ptp_read_82580; 1112 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1113 adapter->cc.mult = 1; 1114 adapter->cc.shift = 0; 1115 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1116 break; 1117 case e1000_i210: 1118 case e1000_i211: 1119 for (i = 0; i < IGB_N_SDP; i++) { 1120 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1121 1122 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1123 ppd->index = i; 1124 ppd->func = PTP_PF_NONE; 1125 } 1126 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1127 adapter->ptp_caps.owner = THIS_MODULE; 1128 adapter->ptp_caps.max_adj = 62499999; 1129 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1130 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1131 adapter->ptp_caps.n_pins = IGB_N_SDP; 1132 adapter->ptp_caps.pps = 1; 1133 adapter->ptp_caps.pin_config = adapter->sdp_config; 1134 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 1135 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1136 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210; 1137 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1138 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1139 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1140 break; 1141 default: 1142 adapter->ptp_clock = NULL; 1143 return; 1144 } 1145 1146 spin_lock_init(&adapter->tmreg_lock); 1147 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1148 1149 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1150 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1151 igb_ptp_overflow_check); 1152 1153 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1154 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1155 1156 igb_ptp_reset(adapter); 1157 1158 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1159 &adapter->pdev->dev); 1160 if (IS_ERR(adapter->ptp_clock)) { 1161 adapter->ptp_clock = NULL; 1162 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1163 } else if (adapter->ptp_clock) { 1164 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1165 adapter->netdev->name); 1166 adapter->ptp_flags |= IGB_PTP_ENABLED; 1167 } 1168 } 1169 1170 /** 1171 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1172 * @adapter: Board private structure 1173 * 1174 * This function stops the overflow check work and PTP Tx timestamp work, and 1175 * will prepare the device for OS suspend. 1176 */ 1177 void igb_ptp_suspend(struct igb_adapter *adapter) 1178 { 1179 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1180 return; 1181 1182 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1183 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1184 1185 cancel_work_sync(&adapter->ptp_tx_work); 1186 if (adapter->ptp_tx_skb) { 1187 dev_kfree_skb_any(adapter->ptp_tx_skb); 1188 adapter->ptp_tx_skb = NULL; 1189 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1190 } 1191 } 1192 1193 /** 1194 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1195 * @adapter: Board private structure. 1196 * 1197 * This function stops the PTP support and cancels the delayed work. 1198 **/ 1199 void igb_ptp_stop(struct igb_adapter *adapter) 1200 { 1201 igb_ptp_suspend(adapter); 1202 1203 if (adapter->ptp_clock) { 1204 ptp_clock_unregister(adapter->ptp_clock); 1205 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1206 adapter->netdev->name); 1207 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1208 } 1209 } 1210 1211 /** 1212 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1213 * @adapter: Board private structure. 1214 * 1215 * This function handles the reset work required to re-enable the PTP device. 1216 **/ 1217 void igb_ptp_reset(struct igb_adapter *adapter) 1218 { 1219 struct e1000_hw *hw = &adapter->hw; 1220 unsigned long flags; 1221 1222 /* reset the tstamp_config */ 1223 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1224 1225 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1226 1227 switch (adapter->hw.mac.type) { 1228 case e1000_82576: 1229 /* Dial the nominal frequency. */ 1230 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1231 break; 1232 case e1000_82580: 1233 case e1000_i354: 1234 case e1000_i350: 1235 case e1000_i210: 1236 case e1000_i211: 1237 wr32(E1000_TSAUXC, 0x0); 1238 wr32(E1000_TSSDP, 0x0); 1239 wr32(E1000_TSIM, 1240 TSYNC_INTERRUPTS | 1241 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1242 wr32(E1000_IMS, E1000_IMS_TS); 1243 break; 1244 default: 1245 /* No work to do. */ 1246 goto out; 1247 } 1248 1249 /* Re-initialize the timer. */ 1250 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1251 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1252 1253 igb_ptp_write_i210(adapter, &ts); 1254 } else { 1255 timecounter_init(&adapter->tc, &adapter->cc, 1256 ktime_to_ns(ktime_get_real())); 1257 } 1258 out: 1259 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1260 1261 wrfl(); 1262 1263 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1264 schedule_delayed_work(&adapter->ptp_overflow_work, 1265 IGB_SYSTIM_OVERFLOW_PERIOD); 1266 } 1267