1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4 #include <linux/module.h> 5 #include <linux/device.h> 6 #include <linux/pci.h> 7 #include <linux/ptp_classify.h> 8 9 #include "igb.h" 10 11 #define INCVALUE_MASK 0x7fffffff 12 #define ISGN 0x80000000 13 14 /* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 */ 55 56 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 57 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 58 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 59 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 60 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 61 #define IGB_NBITS_82580 40 62 63 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 64 65 /* SYSTIM read access for the 82576 */ 66 static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 67 { 68 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 69 struct e1000_hw *hw = &igb->hw; 70 u64 val; 71 u32 lo, hi; 72 73 lo = rd32(E1000_SYSTIML); 74 hi = rd32(E1000_SYSTIMH); 75 76 val = ((u64) hi) << 32; 77 val |= lo; 78 79 return val; 80 } 81 82 /* SYSTIM read access for the 82580 */ 83 static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 84 { 85 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 86 struct e1000_hw *hw = &igb->hw; 87 u32 lo, hi; 88 u64 val; 89 90 /* The timestamp latches on lowest register read. For the 82580 91 * the lowest register is SYSTIMR instead of SYSTIML. However we only 92 * need to provide nanosecond resolution, so we just ignore it. 93 */ 94 rd32(E1000_SYSTIMR); 95 lo = rd32(E1000_SYSTIML); 96 hi = rd32(E1000_SYSTIMH); 97 98 val = ((u64) hi) << 32; 99 val |= lo; 100 101 return val; 102 } 103 104 /* SYSTIM read access for I210/I211 */ 105 static void igb_ptp_read_i210(struct igb_adapter *adapter, 106 struct timespec64 *ts) 107 { 108 struct e1000_hw *hw = &adapter->hw; 109 u32 sec, nsec; 110 111 /* The timestamp latches on lowest register read. For I210/I211, the 112 * lowest register is SYSTIMR. Since we only need to provide nanosecond 113 * resolution, we can ignore it. 114 */ 115 rd32(E1000_SYSTIMR); 116 nsec = rd32(E1000_SYSTIML); 117 sec = rd32(E1000_SYSTIMH); 118 119 ts->tv_sec = sec; 120 ts->tv_nsec = nsec; 121 } 122 123 static void igb_ptp_write_i210(struct igb_adapter *adapter, 124 const struct timespec64 *ts) 125 { 126 struct e1000_hw *hw = &adapter->hw; 127 128 /* Writing the SYSTIMR register is not necessary as it only provides 129 * sub-nanosecond resolution. 130 */ 131 wr32(E1000_SYSTIML, ts->tv_nsec); 132 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 133 } 134 135 /** 136 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 137 * @adapter: board private structure 138 * @hwtstamps: timestamp structure to update 139 * @systim: unsigned 64bit system time value. 140 * 141 * We need to convert the system time value stored in the RX/TXSTMP registers 142 * into a hwtstamp which can be used by the upper level timestamping functions. 143 * 144 * The 'tmreg_lock' spinlock is used to protect the consistency of the 145 * system time value. This is needed because reading the 64 bit time 146 * value involves reading two (or three) 32 bit registers. The first 147 * read latches the value. Ditto for writing. 148 * 149 * In addition, here have extended the system time with an overflow 150 * counter in software. 151 **/ 152 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 153 struct skb_shared_hwtstamps *hwtstamps, 154 u64 systim) 155 { 156 unsigned long flags; 157 u64 ns; 158 159 switch (adapter->hw.mac.type) { 160 case e1000_82576: 161 case e1000_82580: 162 case e1000_i354: 163 case e1000_i350: 164 spin_lock_irqsave(&adapter->tmreg_lock, flags); 165 166 ns = timecounter_cyc2time(&adapter->tc, systim); 167 168 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 169 170 memset(hwtstamps, 0, sizeof(*hwtstamps)); 171 hwtstamps->hwtstamp = ns_to_ktime(ns); 172 break; 173 case e1000_i210: 174 case e1000_i211: 175 memset(hwtstamps, 0, sizeof(*hwtstamps)); 176 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 177 hwtstamps->hwtstamp = ktime_set(systim >> 32, 178 systim & 0xFFFFFFFF); 179 break; 180 default: 181 break; 182 } 183 } 184 185 /* PTP clock operations */ 186 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 187 { 188 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 189 ptp_caps); 190 struct e1000_hw *hw = &igb->hw; 191 int neg_adj = 0; 192 u64 rate; 193 u32 incvalue; 194 195 if (ppb < 0) { 196 neg_adj = 1; 197 ppb = -ppb; 198 } 199 rate = ppb; 200 rate <<= 14; 201 rate = div_u64(rate, 1953125); 202 203 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 204 205 if (neg_adj) 206 incvalue -= rate; 207 else 208 incvalue += rate; 209 210 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 211 212 return 0; 213 } 214 215 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 216 { 217 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 218 ptp_caps); 219 struct e1000_hw *hw = &igb->hw; 220 int neg_adj = 0; 221 u64 rate; 222 u32 inca; 223 224 if (scaled_ppm < 0) { 225 neg_adj = 1; 226 scaled_ppm = -scaled_ppm; 227 } 228 rate = scaled_ppm; 229 rate <<= 13; 230 rate = div_u64(rate, 15625); 231 232 inca = rate & INCVALUE_MASK; 233 if (neg_adj) 234 inca |= ISGN; 235 236 wr32(E1000_TIMINCA, inca); 237 238 return 0; 239 } 240 241 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 242 { 243 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 244 ptp_caps); 245 unsigned long flags; 246 247 spin_lock_irqsave(&igb->tmreg_lock, flags); 248 timecounter_adjtime(&igb->tc, delta); 249 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 250 251 return 0; 252 } 253 254 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 255 { 256 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 257 ptp_caps); 258 unsigned long flags; 259 struct timespec64 now, then = ns_to_timespec64(delta); 260 261 spin_lock_irqsave(&igb->tmreg_lock, flags); 262 263 igb_ptp_read_i210(igb, &now); 264 now = timespec64_add(now, then); 265 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 266 267 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 268 269 return 0; 270 } 271 272 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 273 struct timespec64 *ts) 274 { 275 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 276 ptp_caps); 277 unsigned long flags; 278 u64 ns; 279 280 spin_lock_irqsave(&igb->tmreg_lock, flags); 281 282 ns = timecounter_read(&igb->tc); 283 284 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 285 286 *ts = ns_to_timespec64(ns); 287 288 return 0; 289 } 290 291 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 292 struct timespec64 *ts) 293 { 294 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 295 ptp_caps); 296 unsigned long flags; 297 298 spin_lock_irqsave(&igb->tmreg_lock, flags); 299 300 igb_ptp_read_i210(igb, ts); 301 302 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 303 304 return 0; 305 } 306 307 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 308 const struct timespec64 *ts) 309 { 310 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 311 ptp_caps); 312 unsigned long flags; 313 u64 ns; 314 315 ns = timespec64_to_ns(ts); 316 317 spin_lock_irqsave(&igb->tmreg_lock, flags); 318 319 timecounter_init(&igb->tc, &igb->cc, ns); 320 321 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 322 323 return 0; 324 } 325 326 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 327 const struct timespec64 *ts) 328 { 329 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 330 ptp_caps); 331 unsigned long flags; 332 333 spin_lock_irqsave(&igb->tmreg_lock, flags); 334 335 igb_ptp_write_i210(igb, ts); 336 337 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 338 339 return 0; 340 } 341 342 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 343 { 344 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 345 static const u32 mask[IGB_N_SDP] = { 346 E1000_CTRL_SDP0_DIR, 347 E1000_CTRL_SDP1_DIR, 348 E1000_CTRL_EXT_SDP2_DIR, 349 E1000_CTRL_EXT_SDP3_DIR, 350 }; 351 352 if (input) 353 *ptr &= ~mask[pin]; 354 else 355 *ptr |= mask[pin]; 356 } 357 358 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 359 { 360 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 361 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 362 }; 363 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 364 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 365 }; 366 static const u32 ts_sdp_en[IGB_N_SDP] = { 367 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 368 }; 369 struct e1000_hw *hw = &igb->hw; 370 u32 ctrl, ctrl_ext, tssdp = 0; 371 372 ctrl = rd32(E1000_CTRL); 373 ctrl_ext = rd32(E1000_CTRL_EXT); 374 tssdp = rd32(E1000_TSSDP); 375 376 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 377 378 /* Make sure this pin is not enabled as an output. */ 379 tssdp &= ~ts_sdp_en[pin]; 380 381 if (chan == 1) { 382 tssdp &= ~AUX1_SEL_SDP3; 383 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 384 } else { 385 tssdp &= ~AUX0_SEL_SDP3; 386 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 387 } 388 389 wr32(E1000_TSSDP, tssdp); 390 wr32(E1000_CTRL, ctrl); 391 wr32(E1000_CTRL_EXT, ctrl_ext); 392 } 393 394 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 395 { 396 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 397 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 398 }; 399 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 400 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 401 }; 402 static const u32 ts_sdp_en[IGB_N_SDP] = { 403 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 404 }; 405 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 406 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 407 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 408 }; 409 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 410 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 411 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 412 }; 413 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 414 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 415 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 416 }; 417 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 418 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 419 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 420 }; 421 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 422 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 423 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 424 }; 425 struct e1000_hw *hw = &igb->hw; 426 u32 ctrl, ctrl_ext, tssdp = 0; 427 428 ctrl = rd32(E1000_CTRL); 429 ctrl_ext = rd32(E1000_CTRL_EXT); 430 tssdp = rd32(E1000_TSSDP); 431 432 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 433 434 /* Make sure this pin is not enabled as an input. */ 435 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 436 tssdp &= ~AUX0_TS_SDP_EN; 437 438 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 439 tssdp &= ~AUX1_TS_SDP_EN; 440 441 tssdp &= ~ts_sdp_sel_clr[pin]; 442 if (freq) { 443 if (chan == 1) 444 tssdp |= ts_sdp_sel_fc1[pin]; 445 else 446 tssdp |= ts_sdp_sel_fc0[pin]; 447 } else { 448 if (chan == 1) 449 tssdp |= ts_sdp_sel_tt1[pin]; 450 else 451 tssdp |= ts_sdp_sel_tt0[pin]; 452 } 453 tssdp |= ts_sdp_en[pin]; 454 455 wr32(E1000_TSSDP, tssdp); 456 wr32(E1000_CTRL, ctrl); 457 wr32(E1000_CTRL_EXT, ctrl_ext); 458 } 459 460 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 461 struct ptp_clock_request *rq, int on) 462 { 463 struct igb_adapter *igb = 464 container_of(ptp, struct igb_adapter, ptp_caps); 465 struct e1000_hw *hw = &igb->hw; 466 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 467 unsigned long flags; 468 struct timespec64 ts; 469 int use_freq = 0, pin = -1; 470 s64 ns; 471 472 switch (rq->type) { 473 case PTP_CLK_REQ_EXTTS: 474 if (on) { 475 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 476 rq->extts.index); 477 if (pin < 0) 478 return -EBUSY; 479 } 480 if (rq->extts.index == 1) { 481 tsauxc_mask = TSAUXC_EN_TS1; 482 tsim_mask = TSINTR_AUTT1; 483 } else { 484 tsauxc_mask = TSAUXC_EN_TS0; 485 tsim_mask = TSINTR_AUTT0; 486 } 487 spin_lock_irqsave(&igb->tmreg_lock, flags); 488 tsauxc = rd32(E1000_TSAUXC); 489 tsim = rd32(E1000_TSIM); 490 if (on) { 491 igb_pin_extts(igb, rq->extts.index, pin); 492 tsauxc |= tsauxc_mask; 493 tsim |= tsim_mask; 494 } else { 495 tsauxc &= ~tsauxc_mask; 496 tsim &= ~tsim_mask; 497 } 498 wr32(E1000_TSAUXC, tsauxc); 499 wr32(E1000_TSIM, tsim); 500 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 501 return 0; 502 503 case PTP_CLK_REQ_PEROUT: 504 if (on) { 505 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 506 rq->perout.index); 507 if (pin < 0) 508 return -EBUSY; 509 } 510 ts.tv_sec = rq->perout.period.sec; 511 ts.tv_nsec = rq->perout.period.nsec; 512 ns = timespec64_to_ns(&ts); 513 ns = ns >> 1; 514 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 515 (ns == 250000000LL) || (ns == 500000000LL))) { 516 if (ns < 8LL) 517 return -EINVAL; 518 use_freq = 1; 519 } 520 ts = ns_to_timespec64(ns); 521 if (rq->perout.index == 1) { 522 if (use_freq) { 523 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 524 tsim_mask = 0; 525 } else { 526 tsauxc_mask = TSAUXC_EN_TT1; 527 tsim_mask = TSINTR_TT1; 528 } 529 trgttiml = E1000_TRGTTIML1; 530 trgttimh = E1000_TRGTTIMH1; 531 freqout = E1000_FREQOUT1; 532 } else { 533 if (use_freq) { 534 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 535 tsim_mask = 0; 536 } else { 537 tsauxc_mask = TSAUXC_EN_TT0; 538 tsim_mask = TSINTR_TT0; 539 } 540 trgttiml = E1000_TRGTTIML0; 541 trgttimh = E1000_TRGTTIMH0; 542 freqout = E1000_FREQOUT0; 543 } 544 spin_lock_irqsave(&igb->tmreg_lock, flags); 545 tsauxc = rd32(E1000_TSAUXC); 546 tsim = rd32(E1000_TSIM); 547 if (rq->perout.index == 1) { 548 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 549 tsim &= ~TSINTR_TT1; 550 } else { 551 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 552 tsim &= ~TSINTR_TT0; 553 } 554 if (on) { 555 int i = rq->perout.index; 556 igb_pin_perout(igb, i, pin, use_freq); 557 igb->perout[i].start.tv_sec = rq->perout.start.sec; 558 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 559 igb->perout[i].period.tv_sec = ts.tv_sec; 560 igb->perout[i].period.tv_nsec = ts.tv_nsec; 561 wr32(trgttimh, rq->perout.start.sec); 562 wr32(trgttiml, rq->perout.start.nsec); 563 if (use_freq) 564 wr32(freqout, ns); 565 tsauxc |= tsauxc_mask; 566 tsim |= tsim_mask; 567 } 568 wr32(E1000_TSAUXC, tsauxc); 569 wr32(E1000_TSIM, tsim); 570 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 571 return 0; 572 573 case PTP_CLK_REQ_PPS: 574 spin_lock_irqsave(&igb->tmreg_lock, flags); 575 tsim = rd32(E1000_TSIM); 576 if (on) 577 tsim |= TSINTR_SYS_WRAP; 578 else 579 tsim &= ~TSINTR_SYS_WRAP; 580 igb->pps_sys_wrap_on = !!on; 581 wr32(E1000_TSIM, tsim); 582 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 583 return 0; 584 } 585 586 return -EOPNOTSUPP; 587 } 588 589 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 590 struct ptp_clock_request *rq, int on) 591 { 592 return -EOPNOTSUPP; 593 } 594 595 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 596 enum ptp_pin_function func, unsigned int chan) 597 { 598 switch (func) { 599 case PTP_PF_NONE: 600 case PTP_PF_EXTTS: 601 case PTP_PF_PEROUT: 602 break; 603 case PTP_PF_PHYSYNC: 604 return -1; 605 } 606 return 0; 607 } 608 609 /** 610 * igb_ptp_tx_work 611 * @work: pointer to work struct 612 * 613 * This work function polls the TSYNCTXCTL valid bit to determine when a 614 * timestamp has been taken for the current stored skb. 615 **/ 616 static void igb_ptp_tx_work(struct work_struct *work) 617 { 618 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 619 ptp_tx_work); 620 struct e1000_hw *hw = &adapter->hw; 621 u32 tsynctxctl; 622 623 if (!adapter->ptp_tx_skb) 624 return; 625 626 if (time_is_before_jiffies(adapter->ptp_tx_start + 627 IGB_PTP_TX_TIMEOUT)) { 628 dev_kfree_skb_any(adapter->ptp_tx_skb); 629 adapter->ptp_tx_skb = NULL; 630 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 631 adapter->tx_hwtstamp_timeouts++; 632 /* Clear the tx valid bit in TSYNCTXCTL register to enable 633 * interrupt 634 */ 635 rd32(E1000_TXSTMPH); 636 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 637 return; 638 } 639 640 tsynctxctl = rd32(E1000_TSYNCTXCTL); 641 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 642 igb_ptp_tx_hwtstamp(adapter); 643 else 644 /* reschedule to check later */ 645 schedule_work(&adapter->ptp_tx_work); 646 } 647 648 static void igb_ptp_overflow_check(struct work_struct *work) 649 { 650 struct igb_adapter *igb = 651 container_of(work, struct igb_adapter, ptp_overflow_work.work); 652 struct timespec64 ts; 653 654 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts); 655 656 pr_debug("igb overflow check at %lld.%09lu\n", 657 (long long) ts.tv_sec, ts.tv_nsec); 658 659 schedule_delayed_work(&igb->ptp_overflow_work, 660 IGB_SYSTIM_OVERFLOW_PERIOD); 661 } 662 663 /** 664 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 665 * @adapter: private network adapter structure 666 * 667 * This watchdog task is scheduled to detect error case where hardware has 668 * dropped an Rx packet that was timestamped when the ring is full. The 669 * particular error is rare but leaves the device in a state unable to timestamp 670 * any future packets. 671 **/ 672 void igb_ptp_rx_hang(struct igb_adapter *adapter) 673 { 674 struct e1000_hw *hw = &adapter->hw; 675 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 676 unsigned long rx_event; 677 678 /* Other hardware uses per-packet timestamps */ 679 if (hw->mac.type != e1000_82576) 680 return; 681 682 /* If we don't have a valid timestamp in the registers, just update the 683 * timeout counter and exit 684 */ 685 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 686 adapter->last_rx_ptp_check = jiffies; 687 return; 688 } 689 690 /* Determine the most recent watchdog or rx_timestamp event */ 691 rx_event = adapter->last_rx_ptp_check; 692 if (time_after(adapter->last_rx_timestamp, rx_event)) 693 rx_event = adapter->last_rx_timestamp; 694 695 /* Only need to read the high RXSTMP register to clear the lock */ 696 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 697 rd32(E1000_RXSTMPH); 698 adapter->last_rx_ptp_check = jiffies; 699 adapter->rx_hwtstamp_cleared++; 700 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 701 } 702 } 703 704 /** 705 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 706 * @adapter: private network adapter structure 707 */ 708 void igb_ptp_tx_hang(struct igb_adapter *adapter) 709 { 710 struct e1000_hw *hw = &adapter->hw; 711 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 712 IGB_PTP_TX_TIMEOUT); 713 714 if (!adapter->ptp_tx_skb) 715 return; 716 717 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 718 return; 719 720 /* If we haven't received a timestamp within the timeout, it is 721 * reasonable to assume that it will never occur, so we can unlock the 722 * timestamp bit when this occurs. 723 */ 724 if (timeout) { 725 cancel_work_sync(&adapter->ptp_tx_work); 726 dev_kfree_skb_any(adapter->ptp_tx_skb); 727 adapter->ptp_tx_skb = NULL; 728 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 729 adapter->tx_hwtstamp_timeouts++; 730 /* Clear the tx valid bit in TSYNCTXCTL register to enable 731 * interrupt 732 */ 733 rd32(E1000_TXSTMPH); 734 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 735 } 736 } 737 738 /** 739 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 740 * @adapter: Board private structure. 741 * 742 * If we were asked to do hardware stamping and such a time stamp is 743 * available, then it must have been for this skb here because we only 744 * allow only one such packet into the queue. 745 **/ 746 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 747 { 748 struct sk_buff *skb = adapter->ptp_tx_skb; 749 struct e1000_hw *hw = &adapter->hw; 750 struct skb_shared_hwtstamps shhwtstamps; 751 u64 regval; 752 int adjust = 0; 753 754 regval = rd32(E1000_TXSTMPL); 755 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 756 757 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 758 /* adjust timestamp for the TX latency based on link speed */ 759 if (adapter->hw.mac.type == e1000_i210) { 760 switch (adapter->link_speed) { 761 case SPEED_10: 762 adjust = IGB_I210_TX_LATENCY_10; 763 break; 764 case SPEED_100: 765 adjust = IGB_I210_TX_LATENCY_100; 766 break; 767 case SPEED_1000: 768 adjust = IGB_I210_TX_LATENCY_1000; 769 break; 770 } 771 } 772 773 shhwtstamps.hwtstamp = 774 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 775 776 /* Clear the lock early before calling skb_tstamp_tx so that 777 * applications are not woken up before the lock bit is clear. We use 778 * a copy of the skb pointer to ensure other threads can't change it 779 * while we're notifying the stack. 780 */ 781 adapter->ptp_tx_skb = NULL; 782 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 783 784 /* Notify the stack and free the skb after we've unlocked */ 785 skb_tstamp_tx(skb, &shhwtstamps); 786 dev_kfree_skb_any(skb); 787 } 788 789 /** 790 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 791 * @q_vector: Pointer to interrupt specific structure 792 * @va: Pointer to address containing Rx buffer 793 * @skb: Buffer containing timestamp and packet 794 * 795 * This function is meant to retrieve a timestamp from the first buffer of an 796 * incoming frame. The value is stored in little endian format starting on 797 * byte 8. 798 **/ 799 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 800 struct sk_buff *skb) 801 { 802 __le64 *regval = (__le64 *)va; 803 struct igb_adapter *adapter = q_vector->adapter; 804 int adjust = 0; 805 806 /* The timestamp is recorded in little endian format. 807 * DWORD: 0 1 2 3 808 * Field: Reserved Reserved SYSTIML SYSTIMH 809 */ 810 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), 811 le64_to_cpu(regval[1])); 812 813 /* adjust timestamp for the RX latency based on link speed */ 814 if (adapter->hw.mac.type == e1000_i210) { 815 switch (adapter->link_speed) { 816 case SPEED_10: 817 adjust = IGB_I210_RX_LATENCY_10; 818 break; 819 case SPEED_100: 820 adjust = IGB_I210_RX_LATENCY_100; 821 break; 822 case SPEED_1000: 823 adjust = IGB_I210_RX_LATENCY_1000; 824 break; 825 } 826 } 827 skb_hwtstamps(skb)->hwtstamp = 828 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 829 } 830 831 /** 832 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 833 * @q_vector: Pointer to interrupt specific structure 834 * @skb: Buffer containing timestamp and packet 835 * 836 * This function is meant to retrieve a timestamp from the internal registers 837 * of the adapter and store it in the skb. 838 **/ 839 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 840 struct sk_buff *skb) 841 { 842 struct igb_adapter *adapter = q_vector->adapter; 843 struct e1000_hw *hw = &adapter->hw; 844 u64 regval; 845 int adjust = 0; 846 847 /* If this bit is set, then the RX registers contain the time stamp. No 848 * other packet will be time stamped until we read these registers, so 849 * read the registers to make them available again. Because only one 850 * packet can be time stamped at a time, we know that the register 851 * values must belong to this one here and therefore we don't need to 852 * compare any of the additional attributes stored for it. 853 * 854 * If nothing went wrong, then it should have a shared tx_flags that we 855 * can turn into a skb_shared_hwtstamps. 856 */ 857 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 858 return; 859 860 regval = rd32(E1000_RXSTMPL); 861 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 862 863 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 864 865 /* adjust timestamp for the RX latency based on link speed */ 866 if (adapter->hw.mac.type == e1000_i210) { 867 switch (adapter->link_speed) { 868 case SPEED_10: 869 adjust = IGB_I210_RX_LATENCY_10; 870 break; 871 case SPEED_100: 872 adjust = IGB_I210_RX_LATENCY_100; 873 break; 874 case SPEED_1000: 875 adjust = IGB_I210_RX_LATENCY_1000; 876 break; 877 } 878 } 879 skb_hwtstamps(skb)->hwtstamp = 880 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 881 882 /* Update the last_rx_timestamp timer in order to enable watchdog check 883 * for error case of latched timestamp on a dropped packet. 884 */ 885 adapter->last_rx_timestamp = jiffies; 886 } 887 888 /** 889 * igb_ptp_get_ts_config - get hardware time stamping config 890 * @netdev: 891 * @ifreq: 892 * 893 * Get the hwtstamp_config settings to return to the user. Rather than attempt 894 * to deconstruct the settings from the registers, just return a shadow copy 895 * of the last known settings. 896 **/ 897 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 898 { 899 struct igb_adapter *adapter = netdev_priv(netdev); 900 struct hwtstamp_config *config = &adapter->tstamp_config; 901 902 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 903 -EFAULT : 0; 904 } 905 906 /** 907 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 908 * @adapter: networking device structure 909 * @config: hwtstamp configuration 910 * 911 * Outgoing time stamping can be enabled and disabled. Play nice and 912 * disable it when requested, although it shouldn't case any overhead 913 * when no packet needs it. At most one packet in the queue may be 914 * marked for time stamping, otherwise it would be impossible to tell 915 * for sure to which packet the hardware time stamp belongs. 916 * 917 * Incoming time stamping has to be configured via the hardware 918 * filters. Not all combinations are supported, in particular event 919 * type has to be specified. Matching the kind of event packet is 920 * not supported, with the exception of "all V2 events regardless of 921 * level 2 or 4". 922 */ 923 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 924 struct hwtstamp_config *config) 925 { 926 struct e1000_hw *hw = &adapter->hw; 927 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 928 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 929 u32 tsync_rx_cfg = 0; 930 bool is_l4 = false; 931 bool is_l2 = false; 932 u32 regval; 933 934 /* reserved for future extensions */ 935 if (config->flags) 936 return -EINVAL; 937 938 switch (config->tx_type) { 939 case HWTSTAMP_TX_OFF: 940 tsync_tx_ctl = 0; 941 case HWTSTAMP_TX_ON: 942 break; 943 default: 944 return -ERANGE; 945 } 946 947 switch (config->rx_filter) { 948 case HWTSTAMP_FILTER_NONE: 949 tsync_rx_ctl = 0; 950 break; 951 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 952 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 953 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 954 is_l4 = true; 955 break; 956 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 957 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 958 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 959 is_l4 = true; 960 break; 961 case HWTSTAMP_FILTER_PTP_V2_EVENT: 962 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 963 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 964 case HWTSTAMP_FILTER_PTP_V2_SYNC: 965 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 966 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 967 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 968 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 969 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 970 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 971 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 972 is_l2 = true; 973 is_l4 = true; 974 break; 975 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 976 case HWTSTAMP_FILTER_NTP_ALL: 977 case HWTSTAMP_FILTER_ALL: 978 /* 82576 cannot timestamp all packets, which it needs to do to 979 * support both V1 Sync and Delay_Req messages 980 */ 981 if (hw->mac.type != e1000_82576) { 982 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 983 config->rx_filter = HWTSTAMP_FILTER_ALL; 984 break; 985 } 986 /* fall through */ 987 default: 988 config->rx_filter = HWTSTAMP_FILTER_NONE; 989 return -ERANGE; 990 } 991 992 if (hw->mac.type == e1000_82575) { 993 if (tsync_rx_ctl | tsync_tx_ctl) 994 return -EINVAL; 995 return 0; 996 } 997 998 /* Per-packet timestamping only works if all packets are 999 * timestamped, so enable timestamping in all packets as 1000 * long as one Rx filter was configured. 1001 */ 1002 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1003 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1004 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1005 config->rx_filter = HWTSTAMP_FILTER_ALL; 1006 is_l2 = true; 1007 is_l4 = true; 1008 1009 if ((hw->mac.type == e1000_i210) || 1010 (hw->mac.type == e1000_i211)) { 1011 regval = rd32(E1000_RXPBS); 1012 regval |= E1000_RXPBS_CFG_TS_EN; 1013 wr32(E1000_RXPBS, regval); 1014 } 1015 } 1016 1017 /* enable/disable TX */ 1018 regval = rd32(E1000_TSYNCTXCTL); 1019 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1020 regval |= tsync_tx_ctl; 1021 wr32(E1000_TSYNCTXCTL, regval); 1022 1023 /* enable/disable RX */ 1024 regval = rd32(E1000_TSYNCRXCTL); 1025 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1026 regval |= tsync_rx_ctl; 1027 wr32(E1000_TSYNCRXCTL, regval); 1028 1029 /* define which PTP packets are time stamped */ 1030 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1031 1032 /* define ethertype filter for timestamped packets */ 1033 if (is_l2) 1034 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1035 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1036 E1000_ETQF_1588 | /* enable timestamping */ 1037 ETH_P_1588)); /* 1588 eth protocol type */ 1038 else 1039 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1040 1041 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1042 if (is_l4) { 1043 u32 ftqf = (IPPROTO_UDP /* UDP */ 1044 | E1000_FTQF_VF_BP /* VF not compared */ 1045 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1046 | E1000_FTQF_MASK); /* mask all inputs */ 1047 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1048 1049 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 1050 wr32(E1000_IMIREXT(3), 1051 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1052 if (hw->mac.type == e1000_82576) { 1053 /* enable source port check */ 1054 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 1055 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1056 } 1057 wr32(E1000_FTQF(3), ftqf); 1058 } else { 1059 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1060 } 1061 wrfl(); 1062 1063 /* clear TX/RX time stamp registers, just to be sure */ 1064 regval = rd32(E1000_TXSTMPL); 1065 regval = rd32(E1000_TXSTMPH); 1066 regval = rd32(E1000_RXSTMPL); 1067 regval = rd32(E1000_RXSTMPH); 1068 1069 return 0; 1070 } 1071 1072 /** 1073 * igb_ptp_set_ts_config - set hardware time stamping config 1074 * @netdev: 1075 * @ifreq: 1076 * 1077 **/ 1078 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1079 { 1080 struct igb_adapter *adapter = netdev_priv(netdev); 1081 struct hwtstamp_config config; 1082 int err; 1083 1084 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1085 return -EFAULT; 1086 1087 err = igb_ptp_set_timestamp_mode(adapter, &config); 1088 if (err) 1089 return err; 1090 1091 /* save these settings for future reference */ 1092 memcpy(&adapter->tstamp_config, &config, 1093 sizeof(adapter->tstamp_config)); 1094 1095 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1096 -EFAULT : 0; 1097 } 1098 1099 /** 1100 * igb_ptp_init - Initialize PTP functionality 1101 * @adapter: Board private structure 1102 * 1103 * This function is called at device probe to initialize the PTP 1104 * functionality. 1105 */ 1106 void igb_ptp_init(struct igb_adapter *adapter) 1107 { 1108 struct e1000_hw *hw = &adapter->hw; 1109 struct net_device *netdev = adapter->netdev; 1110 int i; 1111 1112 switch (hw->mac.type) { 1113 case e1000_82576: 1114 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1115 adapter->ptp_caps.owner = THIS_MODULE; 1116 adapter->ptp_caps.max_adj = 999999881; 1117 adapter->ptp_caps.n_ext_ts = 0; 1118 adapter->ptp_caps.pps = 0; 1119 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1120 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1121 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; 1122 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1123 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1124 adapter->cc.read = igb_ptp_read_82576; 1125 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1126 adapter->cc.mult = 1; 1127 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1128 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1129 break; 1130 case e1000_82580: 1131 case e1000_i354: 1132 case e1000_i350: 1133 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1134 adapter->ptp_caps.owner = THIS_MODULE; 1135 adapter->ptp_caps.max_adj = 62499999; 1136 adapter->ptp_caps.n_ext_ts = 0; 1137 adapter->ptp_caps.pps = 0; 1138 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1139 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1140 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576; 1141 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1142 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1143 adapter->cc.read = igb_ptp_read_82580; 1144 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1145 adapter->cc.mult = 1; 1146 adapter->cc.shift = 0; 1147 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1148 break; 1149 case e1000_i210: 1150 case e1000_i211: 1151 for (i = 0; i < IGB_N_SDP; i++) { 1152 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1153 1154 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1155 ppd->index = i; 1156 ppd->func = PTP_PF_NONE; 1157 } 1158 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1159 adapter->ptp_caps.owner = THIS_MODULE; 1160 adapter->ptp_caps.max_adj = 62499999; 1161 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1162 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1163 adapter->ptp_caps.n_pins = IGB_N_SDP; 1164 adapter->ptp_caps.pps = 1; 1165 adapter->ptp_caps.pin_config = adapter->sdp_config; 1166 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1167 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1168 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210; 1169 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1170 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1171 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1172 break; 1173 default: 1174 adapter->ptp_clock = NULL; 1175 return; 1176 } 1177 1178 spin_lock_init(&adapter->tmreg_lock); 1179 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1180 1181 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1182 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1183 igb_ptp_overflow_check); 1184 1185 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1186 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1187 1188 igb_ptp_reset(adapter); 1189 1190 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1191 &adapter->pdev->dev); 1192 if (IS_ERR(adapter->ptp_clock)) { 1193 adapter->ptp_clock = NULL; 1194 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1195 } else if (adapter->ptp_clock) { 1196 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1197 adapter->netdev->name); 1198 adapter->ptp_flags |= IGB_PTP_ENABLED; 1199 } 1200 } 1201 1202 /** 1203 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1204 * @adapter: Board private structure 1205 * 1206 * This function stops the overflow check work and PTP Tx timestamp work, and 1207 * will prepare the device for OS suspend. 1208 */ 1209 void igb_ptp_suspend(struct igb_adapter *adapter) 1210 { 1211 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1212 return; 1213 1214 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1215 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1216 1217 cancel_work_sync(&adapter->ptp_tx_work); 1218 if (adapter->ptp_tx_skb) { 1219 dev_kfree_skb_any(adapter->ptp_tx_skb); 1220 adapter->ptp_tx_skb = NULL; 1221 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1222 } 1223 } 1224 1225 /** 1226 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1227 * @adapter: Board private structure. 1228 * 1229 * This function stops the PTP support and cancels the delayed work. 1230 **/ 1231 void igb_ptp_stop(struct igb_adapter *adapter) 1232 { 1233 igb_ptp_suspend(adapter); 1234 1235 if (adapter->ptp_clock) { 1236 ptp_clock_unregister(adapter->ptp_clock); 1237 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1238 adapter->netdev->name); 1239 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1240 } 1241 } 1242 1243 /** 1244 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1245 * @adapter: Board private structure. 1246 * 1247 * This function handles the reset work required to re-enable the PTP device. 1248 **/ 1249 void igb_ptp_reset(struct igb_adapter *adapter) 1250 { 1251 struct e1000_hw *hw = &adapter->hw; 1252 unsigned long flags; 1253 1254 /* reset the tstamp_config */ 1255 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1256 1257 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1258 1259 switch (adapter->hw.mac.type) { 1260 case e1000_82576: 1261 /* Dial the nominal frequency. */ 1262 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1263 break; 1264 case e1000_82580: 1265 case e1000_i354: 1266 case e1000_i350: 1267 case e1000_i210: 1268 case e1000_i211: 1269 wr32(E1000_TSAUXC, 0x0); 1270 wr32(E1000_TSSDP, 0x0); 1271 wr32(E1000_TSIM, 1272 TSYNC_INTERRUPTS | 1273 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1274 wr32(E1000_IMS, E1000_IMS_TS); 1275 break; 1276 default: 1277 /* No work to do. */ 1278 goto out; 1279 } 1280 1281 /* Re-initialize the timer. */ 1282 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1283 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1284 1285 igb_ptp_write_i210(adapter, &ts); 1286 } else { 1287 timecounter_init(&adapter->tc, &adapter->cc, 1288 ktime_to_ns(ktime_get_real())); 1289 } 1290 out: 1291 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1292 1293 wrfl(); 1294 1295 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1296 schedule_delayed_work(&adapter->ptp_overflow_work, 1297 IGB_SYSTIM_OVERFLOW_PERIOD); 1298 } 1299