1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4 #include <linux/module.h> 5 #include <linux/device.h> 6 #include <linux/pci.h> 7 #include <linux/ptp_classify.h> 8 9 #include "igb.h" 10 11 #define INCVALUE_MASK 0x7fffffff 12 #define ISGN 0x80000000 13 14 /* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 * 55 * SYSTIM is converted to real time using a timecounter. As 56 * timecounter_cyc2time() allows old timestamps, the timecounter needs 57 * to be updated at least once per half of the SYSTIM interval. 58 * Scheduling of delayed work is not very accurate, and also the NIC 59 * clock can be adjusted to run up to 6% faster and the system clock 60 * up to 10% slower, so we aim for 6 minutes to be sure the actual 61 * interval in the NIC time is shorter than 9.16 minutes. 62 */ 63 64 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6) 65 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 66 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 68 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 69 #define IGB_NBITS_82580 40 70 71 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 72 static void igb_ptp_sdp_init(struct igb_adapter *adapter); 73 74 /* SYSTIM read access for the 82576 */ 75 static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 76 { 77 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 78 struct e1000_hw *hw = &igb->hw; 79 u64 val; 80 u32 lo, hi; 81 82 lo = rd32(E1000_SYSTIML); 83 hi = rd32(E1000_SYSTIMH); 84 85 val = ((u64) hi) << 32; 86 val |= lo; 87 88 return val; 89 } 90 91 /* SYSTIM read access for the 82580 */ 92 static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 93 { 94 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 95 struct e1000_hw *hw = &igb->hw; 96 u32 lo, hi; 97 u64 val; 98 99 /* The timestamp latches on lowest register read. For the 82580 100 * the lowest register is SYSTIMR instead of SYSTIML. However we only 101 * need to provide nanosecond resolution, so we just ignore it. 102 */ 103 rd32(E1000_SYSTIMR); 104 lo = rd32(E1000_SYSTIML); 105 hi = rd32(E1000_SYSTIMH); 106 107 val = ((u64) hi) << 32; 108 val |= lo; 109 110 return val; 111 } 112 113 /* SYSTIM read access for I210/I211 */ 114 static void igb_ptp_read_i210(struct igb_adapter *adapter, 115 struct timespec64 *ts) 116 { 117 struct e1000_hw *hw = &adapter->hw; 118 u32 sec, nsec; 119 120 /* The timestamp latches on lowest register read. For I210/I211, the 121 * lowest register is SYSTIMR. Since we only need to provide nanosecond 122 * resolution, we can ignore it. 123 */ 124 rd32(E1000_SYSTIMR); 125 nsec = rd32(E1000_SYSTIML); 126 sec = rd32(E1000_SYSTIMH); 127 128 ts->tv_sec = sec; 129 ts->tv_nsec = nsec; 130 } 131 132 static void igb_ptp_write_i210(struct igb_adapter *adapter, 133 const struct timespec64 *ts) 134 { 135 struct e1000_hw *hw = &adapter->hw; 136 137 /* Writing the SYSTIMR register is not necessary as it only provides 138 * sub-nanosecond resolution. 139 */ 140 wr32(E1000_SYSTIML, ts->tv_nsec); 141 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 142 } 143 144 /** 145 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 146 * @adapter: board private structure 147 * @hwtstamps: timestamp structure to update 148 * @systim: unsigned 64bit system time value. 149 * 150 * We need to convert the system time value stored in the RX/TXSTMP registers 151 * into a hwtstamp which can be used by the upper level timestamping functions. 152 * 153 * The 'tmreg_lock' spinlock is used to protect the consistency of the 154 * system time value. This is needed because reading the 64 bit time 155 * value involves reading two (or three) 32 bit registers. The first 156 * read latches the value. Ditto for writing. 157 * 158 * In addition, here have extended the system time with an overflow 159 * counter in software. 160 **/ 161 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 162 struct skb_shared_hwtstamps *hwtstamps, 163 u64 systim) 164 { 165 unsigned long flags; 166 u64 ns; 167 168 memset(hwtstamps, 0, sizeof(*hwtstamps)); 169 170 switch (adapter->hw.mac.type) { 171 case e1000_82576: 172 case e1000_82580: 173 case e1000_i354: 174 case e1000_i350: 175 spin_lock_irqsave(&adapter->tmreg_lock, flags); 176 ns = timecounter_cyc2time(&adapter->tc, systim); 177 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 178 179 hwtstamps->hwtstamp = ns_to_ktime(ns); 180 break; 181 case e1000_i210: 182 case e1000_i211: 183 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 184 hwtstamps->hwtstamp = ktime_set(systim >> 32, 185 systim & 0xFFFFFFFF); 186 break; 187 default: 188 break; 189 } 190 } 191 192 /* PTP clock operations */ 193 static int igb_ptp_adjfine_82576(struct ptp_clock_info *ptp, long scaled_ppm) 194 { 195 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 196 ptp_caps); 197 struct e1000_hw *hw = &igb->hw; 198 int neg_adj = 0; 199 u64 rate; 200 u32 incvalue; 201 202 if (scaled_ppm < 0) { 203 neg_adj = 1; 204 scaled_ppm = -scaled_ppm; 205 } 206 207 incvalue = INCVALUE_82576; 208 rate = mul_u64_u64_div_u64(incvalue, (u64)scaled_ppm, 209 1000000ULL << 16); 210 211 if (neg_adj) 212 incvalue -= rate; 213 else 214 incvalue += rate; 215 216 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 217 218 return 0; 219 } 220 221 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 222 { 223 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 224 ptp_caps); 225 struct e1000_hw *hw = &igb->hw; 226 int neg_adj = 0; 227 u64 rate; 228 u32 inca; 229 230 if (scaled_ppm < 0) { 231 neg_adj = 1; 232 scaled_ppm = -scaled_ppm; 233 } 234 rate = scaled_ppm; 235 rate <<= 13; 236 rate = div_u64(rate, 15625); 237 238 inca = rate & INCVALUE_MASK; 239 if (neg_adj) 240 inca |= ISGN; 241 242 wr32(E1000_TIMINCA, inca); 243 244 return 0; 245 } 246 247 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 248 { 249 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 250 ptp_caps); 251 unsigned long flags; 252 253 spin_lock_irqsave(&igb->tmreg_lock, flags); 254 timecounter_adjtime(&igb->tc, delta); 255 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 256 257 return 0; 258 } 259 260 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 261 { 262 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 263 ptp_caps); 264 unsigned long flags; 265 struct timespec64 now, then = ns_to_timespec64(delta); 266 267 spin_lock_irqsave(&igb->tmreg_lock, flags); 268 269 igb_ptp_read_i210(igb, &now); 270 now = timespec64_add(now, then); 271 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 272 273 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 274 275 return 0; 276 } 277 278 static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, 279 struct timespec64 *ts, 280 struct ptp_system_timestamp *sts) 281 { 282 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 283 ptp_caps); 284 struct e1000_hw *hw = &igb->hw; 285 unsigned long flags; 286 u32 lo, hi; 287 u64 ns; 288 289 spin_lock_irqsave(&igb->tmreg_lock, flags); 290 291 ptp_read_system_prets(sts); 292 lo = rd32(E1000_SYSTIML); 293 ptp_read_system_postts(sts); 294 hi = rd32(E1000_SYSTIMH); 295 296 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 297 298 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 299 300 *ts = ns_to_timespec64(ns); 301 302 return 0; 303 } 304 305 static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, 306 struct timespec64 *ts, 307 struct ptp_system_timestamp *sts) 308 { 309 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 310 ptp_caps); 311 struct e1000_hw *hw = &igb->hw; 312 unsigned long flags; 313 u32 lo, hi; 314 u64 ns; 315 316 spin_lock_irqsave(&igb->tmreg_lock, flags); 317 318 ptp_read_system_prets(sts); 319 rd32(E1000_SYSTIMR); 320 ptp_read_system_postts(sts); 321 lo = rd32(E1000_SYSTIML); 322 hi = rd32(E1000_SYSTIMH); 323 324 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 325 326 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 327 328 *ts = ns_to_timespec64(ns); 329 330 return 0; 331 } 332 333 static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, 334 struct timespec64 *ts, 335 struct ptp_system_timestamp *sts) 336 { 337 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 338 ptp_caps); 339 struct e1000_hw *hw = &igb->hw; 340 unsigned long flags; 341 342 spin_lock_irqsave(&igb->tmreg_lock, flags); 343 344 ptp_read_system_prets(sts); 345 rd32(E1000_SYSTIMR); 346 ptp_read_system_postts(sts); 347 ts->tv_nsec = rd32(E1000_SYSTIML); 348 ts->tv_sec = rd32(E1000_SYSTIMH); 349 350 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 351 352 return 0; 353 } 354 355 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 356 const struct timespec64 *ts) 357 { 358 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 359 ptp_caps); 360 unsigned long flags; 361 u64 ns; 362 363 ns = timespec64_to_ns(ts); 364 365 spin_lock_irqsave(&igb->tmreg_lock, flags); 366 367 timecounter_init(&igb->tc, &igb->cc, ns); 368 369 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 370 371 return 0; 372 } 373 374 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 375 const struct timespec64 *ts) 376 { 377 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 378 ptp_caps); 379 unsigned long flags; 380 381 spin_lock_irqsave(&igb->tmreg_lock, flags); 382 383 igb_ptp_write_i210(igb, ts); 384 385 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 386 387 return 0; 388 } 389 390 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 391 { 392 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 393 static const u32 mask[IGB_N_SDP] = { 394 E1000_CTRL_SDP0_DIR, 395 E1000_CTRL_SDP1_DIR, 396 E1000_CTRL_EXT_SDP2_DIR, 397 E1000_CTRL_EXT_SDP3_DIR, 398 }; 399 400 if (input) 401 *ptr &= ~mask[pin]; 402 else 403 *ptr |= mask[pin]; 404 } 405 406 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 407 { 408 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 409 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 410 }; 411 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 412 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 413 }; 414 static const u32 ts_sdp_en[IGB_N_SDP] = { 415 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 416 }; 417 struct e1000_hw *hw = &igb->hw; 418 u32 ctrl, ctrl_ext, tssdp = 0; 419 420 ctrl = rd32(E1000_CTRL); 421 ctrl_ext = rd32(E1000_CTRL_EXT); 422 tssdp = rd32(E1000_TSSDP); 423 424 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 425 426 /* Make sure this pin is not enabled as an output. */ 427 tssdp &= ~ts_sdp_en[pin]; 428 429 if (chan == 1) { 430 tssdp &= ~AUX1_SEL_SDP3; 431 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 432 } else { 433 tssdp &= ~AUX0_SEL_SDP3; 434 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 435 } 436 437 wr32(E1000_TSSDP, tssdp); 438 wr32(E1000_CTRL, ctrl); 439 wr32(E1000_CTRL_EXT, ctrl_ext); 440 } 441 442 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 443 { 444 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 445 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 446 }; 447 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 448 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 449 }; 450 static const u32 ts_sdp_en[IGB_N_SDP] = { 451 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 452 }; 453 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 454 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 455 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 456 }; 457 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 458 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 459 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 460 }; 461 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 462 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 463 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 464 }; 465 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 466 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 467 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 468 }; 469 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 470 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 471 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 472 }; 473 struct e1000_hw *hw = &igb->hw; 474 u32 ctrl, ctrl_ext, tssdp = 0; 475 476 ctrl = rd32(E1000_CTRL); 477 ctrl_ext = rd32(E1000_CTRL_EXT); 478 tssdp = rd32(E1000_TSSDP); 479 480 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 481 482 /* Make sure this pin is not enabled as an input. */ 483 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 484 tssdp &= ~AUX0_TS_SDP_EN; 485 486 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 487 tssdp &= ~AUX1_TS_SDP_EN; 488 489 tssdp &= ~ts_sdp_sel_clr[pin]; 490 if (freq) { 491 if (chan == 1) 492 tssdp |= ts_sdp_sel_fc1[pin]; 493 else 494 tssdp |= ts_sdp_sel_fc0[pin]; 495 } else { 496 if (chan == 1) 497 tssdp |= ts_sdp_sel_tt1[pin]; 498 else 499 tssdp |= ts_sdp_sel_tt0[pin]; 500 } 501 tssdp |= ts_sdp_en[pin]; 502 503 wr32(E1000_TSSDP, tssdp); 504 wr32(E1000_CTRL, ctrl); 505 wr32(E1000_CTRL_EXT, ctrl_ext); 506 } 507 508 static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp, 509 struct ptp_clock_request *rq, int on) 510 { 511 struct igb_adapter *igb = 512 container_of(ptp, struct igb_adapter, ptp_caps); 513 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml, 514 systimh, level_mask, level, rem; 515 struct e1000_hw *hw = &igb->hw; 516 struct timespec64 ts, start; 517 unsigned long flags; 518 u64 systim, now; 519 int pin = -1; 520 s64 ns; 521 522 switch (rq->type) { 523 case PTP_CLK_REQ_EXTTS: 524 /* Reject requests with unsupported flags */ 525 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 526 PTP_RISING_EDGE | 527 PTP_FALLING_EDGE | 528 PTP_STRICT_FLAGS)) 529 return -EOPNOTSUPP; 530 531 if (on) { 532 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 533 rq->extts.index); 534 if (pin < 0) 535 return -EBUSY; 536 } 537 if (rq->extts.index == 1) { 538 tsauxc_mask = TSAUXC_EN_TS1; 539 tsim_mask = TSINTR_AUTT1; 540 } else { 541 tsauxc_mask = TSAUXC_EN_TS0; 542 tsim_mask = TSINTR_AUTT0; 543 } 544 spin_lock_irqsave(&igb->tmreg_lock, flags); 545 tsauxc = rd32(E1000_TSAUXC); 546 tsim = rd32(E1000_TSIM); 547 if (on) { 548 igb_pin_extts(igb, rq->extts.index, pin); 549 tsauxc |= tsauxc_mask; 550 tsim |= tsim_mask; 551 } else { 552 tsauxc &= ~tsauxc_mask; 553 tsim &= ~tsim_mask; 554 } 555 wr32(E1000_TSAUXC, tsauxc); 556 wr32(E1000_TSIM, tsim); 557 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 558 return 0; 559 560 case PTP_CLK_REQ_PEROUT: 561 /* Reject requests with unsupported flags */ 562 if (rq->perout.flags) 563 return -EOPNOTSUPP; 564 565 if (on) { 566 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 567 rq->perout.index); 568 if (pin < 0) 569 return -EBUSY; 570 } 571 ts.tv_sec = rq->perout.period.sec; 572 ts.tv_nsec = rq->perout.period.nsec; 573 ns = timespec64_to_ns(&ts); 574 ns = ns >> 1; 575 if (on && ns < 8LL) 576 return -EINVAL; 577 ts = ns_to_timespec64(ns); 578 if (rq->perout.index == 1) { 579 tsauxc_mask = TSAUXC_EN_TT1; 580 tsim_mask = TSINTR_TT1; 581 trgttiml = E1000_TRGTTIML1; 582 trgttimh = E1000_TRGTTIMH1; 583 } else { 584 tsauxc_mask = TSAUXC_EN_TT0; 585 tsim_mask = TSINTR_TT0; 586 trgttiml = E1000_TRGTTIML0; 587 trgttimh = E1000_TRGTTIMH0; 588 } 589 spin_lock_irqsave(&igb->tmreg_lock, flags); 590 tsauxc = rd32(E1000_TSAUXC); 591 tsim = rd32(E1000_TSIM); 592 if (rq->perout.index == 1) { 593 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 594 tsim &= ~TSINTR_TT1; 595 } else { 596 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 597 tsim &= ~TSINTR_TT0; 598 } 599 if (on) { 600 int i = rq->perout.index; 601 602 /* read systim registers in sequence */ 603 rd32(E1000_SYSTIMR); 604 systiml = rd32(E1000_SYSTIML); 605 systimh = rd32(E1000_SYSTIMH); 606 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 607 now = timecounter_cyc2time(&igb->tc, systim); 608 609 if (pin < 2) { 610 level_mask = (i == 1) ? 0x80000 : 0x40000; 611 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 612 } else { 613 level_mask = (i == 1) ? 0x80 : 0x40; 614 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 615 } 616 617 div_u64_rem(now, ns, &rem); 618 systim = systim + (ns - rem); 619 620 /* synchronize pin level with rising/falling edges */ 621 div_u64_rem(now, ns << 1, &rem); 622 if (rem < ns) { 623 /* first half of period */ 624 if (level == 0) { 625 /* output is already low, skip this period */ 626 systim += ns; 627 } 628 } else { 629 /* second half of period */ 630 if (level == 1) { 631 /* output is already high, skip this period */ 632 systim += ns; 633 } 634 } 635 636 start = ns_to_timespec64(systim + (ns - rem)); 637 igb_pin_perout(igb, i, pin, 0); 638 igb->perout[i].start.tv_sec = start.tv_sec; 639 igb->perout[i].start.tv_nsec = start.tv_nsec; 640 igb->perout[i].period.tv_sec = ts.tv_sec; 641 igb->perout[i].period.tv_nsec = ts.tv_nsec; 642 643 wr32(trgttiml, (u32)systim); 644 wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF); 645 tsauxc |= tsauxc_mask; 646 tsim |= tsim_mask; 647 } 648 wr32(E1000_TSAUXC, tsauxc); 649 wr32(E1000_TSIM, tsim); 650 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 651 return 0; 652 653 case PTP_CLK_REQ_PPS: 654 return -EOPNOTSUPP; 655 } 656 657 return -EOPNOTSUPP; 658 } 659 660 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 661 struct ptp_clock_request *rq, int on) 662 { 663 struct igb_adapter *igb = 664 container_of(ptp, struct igb_adapter, ptp_caps); 665 struct e1000_hw *hw = &igb->hw; 666 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 667 unsigned long flags; 668 struct timespec64 ts; 669 int use_freq = 0, pin = -1; 670 s64 ns; 671 672 switch (rq->type) { 673 case PTP_CLK_REQ_EXTTS: 674 /* Reject requests with unsupported flags */ 675 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 676 PTP_RISING_EDGE | 677 PTP_FALLING_EDGE | 678 PTP_STRICT_FLAGS)) 679 return -EOPNOTSUPP; 680 681 /* Reject requests failing to enable both edges. */ 682 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 683 (rq->extts.flags & PTP_ENABLE_FEATURE) && 684 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) 685 return -EOPNOTSUPP; 686 687 if (on) { 688 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 689 rq->extts.index); 690 if (pin < 0) 691 return -EBUSY; 692 } 693 if (rq->extts.index == 1) { 694 tsauxc_mask = TSAUXC_EN_TS1; 695 tsim_mask = TSINTR_AUTT1; 696 } else { 697 tsauxc_mask = TSAUXC_EN_TS0; 698 tsim_mask = TSINTR_AUTT0; 699 } 700 spin_lock_irqsave(&igb->tmreg_lock, flags); 701 tsauxc = rd32(E1000_TSAUXC); 702 tsim = rd32(E1000_TSIM); 703 if (on) { 704 igb_pin_extts(igb, rq->extts.index, pin); 705 tsauxc |= tsauxc_mask; 706 tsim |= tsim_mask; 707 } else { 708 tsauxc &= ~tsauxc_mask; 709 tsim &= ~tsim_mask; 710 } 711 wr32(E1000_TSAUXC, tsauxc); 712 wr32(E1000_TSIM, tsim); 713 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 714 return 0; 715 716 case PTP_CLK_REQ_PEROUT: 717 /* Reject requests with unsupported flags */ 718 if (rq->perout.flags) 719 return -EOPNOTSUPP; 720 721 if (on) { 722 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 723 rq->perout.index); 724 if (pin < 0) 725 return -EBUSY; 726 } 727 ts.tv_sec = rq->perout.period.sec; 728 ts.tv_nsec = rq->perout.period.nsec; 729 ns = timespec64_to_ns(&ts); 730 ns = ns >> 1; 731 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 732 (ns == 250000000LL) || (ns == 500000000LL))) { 733 if (ns < 8LL) 734 return -EINVAL; 735 use_freq = 1; 736 } 737 ts = ns_to_timespec64(ns); 738 if (rq->perout.index == 1) { 739 if (use_freq) { 740 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 741 tsim_mask = 0; 742 } else { 743 tsauxc_mask = TSAUXC_EN_TT1; 744 tsim_mask = TSINTR_TT1; 745 } 746 trgttiml = E1000_TRGTTIML1; 747 trgttimh = E1000_TRGTTIMH1; 748 freqout = E1000_FREQOUT1; 749 } else { 750 if (use_freq) { 751 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 752 tsim_mask = 0; 753 } else { 754 tsauxc_mask = TSAUXC_EN_TT0; 755 tsim_mask = TSINTR_TT0; 756 } 757 trgttiml = E1000_TRGTTIML0; 758 trgttimh = E1000_TRGTTIMH0; 759 freqout = E1000_FREQOUT0; 760 } 761 spin_lock_irqsave(&igb->tmreg_lock, flags); 762 tsauxc = rd32(E1000_TSAUXC); 763 tsim = rd32(E1000_TSIM); 764 if (rq->perout.index == 1) { 765 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 766 tsim &= ~TSINTR_TT1; 767 } else { 768 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 769 tsim &= ~TSINTR_TT0; 770 } 771 if (on) { 772 int i = rq->perout.index; 773 igb_pin_perout(igb, i, pin, use_freq); 774 igb->perout[i].start.tv_sec = rq->perout.start.sec; 775 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 776 igb->perout[i].period.tv_sec = ts.tv_sec; 777 igb->perout[i].period.tv_nsec = ts.tv_nsec; 778 wr32(trgttimh, rq->perout.start.sec); 779 wr32(trgttiml, rq->perout.start.nsec); 780 if (use_freq) 781 wr32(freqout, ns); 782 tsauxc |= tsauxc_mask; 783 tsim |= tsim_mask; 784 } 785 wr32(E1000_TSAUXC, tsauxc); 786 wr32(E1000_TSIM, tsim); 787 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 788 return 0; 789 790 case PTP_CLK_REQ_PPS: 791 spin_lock_irqsave(&igb->tmreg_lock, flags); 792 tsim = rd32(E1000_TSIM); 793 if (on) 794 tsim |= TSINTR_SYS_WRAP; 795 else 796 tsim &= ~TSINTR_SYS_WRAP; 797 igb->pps_sys_wrap_on = !!on; 798 wr32(E1000_TSIM, tsim); 799 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 800 return 0; 801 } 802 803 return -EOPNOTSUPP; 804 } 805 806 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 807 struct ptp_clock_request *rq, int on) 808 { 809 return -EOPNOTSUPP; 810 } 811 812 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 813 enum ptp_pin_function func, unsigned int chan) 814 { 815 switch (func) { 816 case PTP_PF_NONE: 817 case PTP_PF_EXTTS: 818 case PTP_PF_PEROUT: 819 break; 820 case PTP_PF_PHYSYNC: 821 return -1; 822 } 823 return 0; 824 } 825 826 /** 827 * igb_ptp_tx_work 828 * @work: pointer to work struct 829 * 830 * This work function polls the TSYNCTXCTL valid bit to determine when a 831 * timestamp has been taken for the current stored skb. 832 **/ 833 static void igb_ptp_tx_work(struct work_struct *work) 834 { 835 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 836 ptp_tx_work); 837 struct e1000_hw *hw = &adapter->hw; 838 u32 tsynctxctl; 839 840 if (!adapter->ptp_tx_skb) 841 return; 842 843 if (time_is_before_jiffies(adapter->ptp_tx_start + 844 IGB_PTP_TX_TIMEOUT)) { 845 dev_kfree_skb_any(adapter->ptp_tx_skb); 846 adapter->ptp_tx_skb = NULL; 847 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 848 adapter->tx_hwtstamp_timeouts++; 849 /* Clear the tx valid bit in TSYNCTXCTL register to enable 850 * interrupt 851 */ 852 rd32(E1000_TXSTMPH); 853 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 854 return; 855 } 856 857 tsynctxctl = rd32(E1000_TSYNCTXCTL); 858 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 859 igb_ptp_tx_hwtstamp(adapter); 860 else 861 /* reschedule to check later */ 862 schedule_work(&adapter->ptp_tx_work); 863 } 864 865 static void igb_ptp_overflow_check(struct work_struct *work) 866 { 867 struct igb_adapter *igb = 868 container_of(work, struct igb_adapter, ptp_overflow_work.work); 869 struct timespec64 ts; 870 u64 ns; 871 872 /* Update the timecounter */ 873 ns = timecounter_read(&igb->tc); 874 875 ts = ns_to_timespec64(ns); 876 pr_debug("igb overflow check at %lld.%09lu\n", 877 (long long) ts.tv_sec, ts.tv_nsec); 878 879 schedule_delayed_work(&igb->ptp_overflow_work, 880 IGB_SYSTIM_OVERFLOW_PERIOD); 881 } 882 883 /** 884 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 885 * @adapter: private network adapter structure 886 * 887 * This watchdog task is scheduled to detect error case where hardware has 888 * dropped an Rx packet that was timestamped when the ring is full. The 889 * particular error is rare but leaves the device in a state unable to timestamp 890 * any future packets. 891 **/ 892 void igb_ptp_rx_hang(struct igb_adapter *adapter) 893 { 894 struct e1000_hw *hw = &adapter->hw; 895 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 896 unsigned long rx_event; 897 898 /* Other hardware uses per-packet timestamps */ 899 if (hw->mac.type != e1000_82576) 900 return; 901 902 /* If we don't have a valid timestamp in the registers, just update the 903 * timeout counter and exit 904 */ 905 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 906 adapter->last_rx_ptp_check = jiffies; 907 return; 908 } 909 910 /* Determine the most recent watchdog or rx_timestamp event */ 911 rx_event = adapter->last_rx_ptp_check; 912 if (time_after(adapter->last_rx_timestamp, rx_event)) 913 rx_event = adapter->last_rx_timestamp; 914 915 /* Only need to read the high RXSTMP register to clear the lock */ 916 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 917 rd32(E1000_RXSTMPH); 918 adapter->last_rx_ptp_check = jiffies; 919 adapter->rx_hwtstamp_cleared++; 920 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 921 } 922 } 923 924 /** 925 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 926 * @adapter: private network adapter structure 927 */ 928 void igb_ptp_tx_hang(struct igb_adapter *adapter) 929 { 930 struct e1000_hw *hw = &adapter->hw; 931 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 932 IGB_PTP_TX_TIMEOUT); 933 934 if (!adapter->ptp_tx_skb) 935 return; 936 937 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 938 return; 939 940 /* If we haven't received a timestamp within the timeout, it is 941 * reasonable to assume that it will never occur, so we can unlock the 942 * timestamp bit when this occurs. 943 */ 944 if (timeout) { 945 cancel_work_sync(&adapter->ptp_tx_work); 946 dev_kfree_skb_any(adapter->ptp_tx_skb); 947 adapter->ptp_tx_skb = NULL; 948 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 949 adapter->tx_hwtstamp_timeouts++; 950 /* Clear the tx valid bit in TSYNCTXCTL register to enable 951 * interrupt 952 */ 953 rd32(E1000_TXSTMPH); 954 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 955 } 956 } 957 958 /** 959 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 960 * @adapter: Board private structure. 961 * 962 * If we were asked to do hardware stamping and such a time stamp is 963 * available, then it must have been for this skb here because we only 964 * allow only one such packet into the queue. 965 **/ 966 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 967 { 968 struct sk_buff *skb = adapter->ptp_tx_skb; 969 struct e1000_hw *hw = &adapter->hw; 970 struct skb_shared_hwtstamps shhwtstamps; 971 u64 regval; 972 int adjust = 0; 973 974 regval = rd32(E1000_TXSTMPL); 975 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 976 977 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 978 /* adjust timestamp for the TX latency based on link speed */ 979 if (adapter->hw.mac.type == e1000_i210) { 980 switch (adapter->link_speed) { 981 case SPEED_10: 982 adjust = IGB_I210_TX_LATENCY_10; 983 break; 984 case SPEED_100: 985 adjust = IGB_I210_TX_LATENCY_100; 986 break; 987 case SPEED_1000: 988 adjust = IGB_I210_TX_LATENCY_1000; 989 break; 990 } 991 } 992 993 shhwtstamps.hwtstamp = 994 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 995 996 /* Clear the lock early before calling skb_tstamp_tx so that 997 * applications are not woken up before the lock bit is clear. We use 998 * a copy of the skb pointer to ensure other threads can't change it 999 * while we're notifying the stack. 1000 */ 1001 adapter->ptp_tx_skb = NULL; 1002 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1003 1004 /* Notify the stack and free the skb after we've unlocked */ 1005 skb_tstamp_tx(skb, &shhwtstamps); 1006 dev_kfree_skb_any(skb); 1007 } 1008 1009 /** 1010 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 1011 * @q_vector: Pointer to interrupt specific structure 1012 * @va: Pointer to address containing Rx buffer 1013 * @timestamp: Pointer where timestamp will be stored 1014 * 1015 * This function is meant to retrieve a timestamp from the first buffer of an 1016 * incoming frame. The value is stored in little endian format starting on 1017 * byte 8 1018 * 1019 * Returns: The timestamp header length or 0 if not available 1020 **/ 1021 int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 1022 ktime_t *timestamp) 1023 { 1024 struct igb_adapter *adapter = q_vector->adapter; 1025 struct skb_shared_hwtstamps ts; 1026 __le64 *regval = (__le64 *)va; 1027 int adjust = 0; 1028 1029 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1030 return 0; 1031 1032 /* The timestamp is recorded in little endian format. 1033 * DWORD: 0 1 2 3 1034 * Field: Reserved Reserved SYSTIML SYSTIMH 1035 */ 1036 1037 /* check reserved dwords are zero, be/le doesn't matter for zero */ 1038 if (regval[0]) 1039 return 0; 1040 1041 igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1])); 1042 1043 /* adjust timestamp for the RX latency based on link speed */ 1044 if (adapter->hw.mac.type == e1000_i210) { 1045 switch (adapter->link_speed) { 1046 case SPEED_10: 1047 adjust = IGB_I210_RX_LATENCY_10; 1048 break; 1049 case SPEED_100: 1050 adjust = IGB_I210_RX_LATENCY_100; 1051 break; 1052 case SPEED_1000: 1053 adjust = IGB_I210_RX_LATENCY_1000; 1054 break; 1055 } 1056 } 1057 1058 *timestamp = ktime_sub_ns(ts.hwtstamp, adjust); 1059 1060 return IGB_TS_HDR_LEN; 1061 } 1062 1063 /** 1064 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 1065 * @q_vector: Pointer to interrupt specific structure 1066 * @skb: Buffer containing timestamp and packet 1067 * 1068 * This function is meant to retrieve a timestamp from the internal registers 1069 * of the adapter and store it in the skb. 1070 **/ 1071 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) 1072 { 1073 struct igb_adapter *adapter = q_vector->adapter; 1074 struct e1000_hw *hw = &adapter->hw; 1075 int adjust = 0; 1076 u64 regval; 1077 1078 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1079 return; 1080 1081 /* If this bit is set, then the RX registers contain the time stamp. No 1082 * other packet will be time stamped until we read these registers, so 1083 * read the registers to make them available again. Because only one 1084 * packet can be time stamped at a time, we know that the register 1085 * values must belong to this one here and therefore we don't need to 1086 * compare any of the additional attributes stored for it. 1087 * 1088 * If nothing went wrong, then it should have a shared tx_flags that we 1089 * can turn into a skb_shared_hwtstamps. 1090 */ 1091 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 1092 return; 1093 1094 regval = rd32(E1000_RXSTMPL); 1095 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 1096 1097 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 1098 1099 /* adjust timestamp for the RX latency based on link speed */ 1100 if (adapter->hw.mac.type == e1000_i210) { 1101 switch (adapter->link_speed) { 1102 case SPEED_10: 1103 adjust = IGB_I210_RX_LATENCY_10; 1104 break; 1105 case SPEED_100: 1106 adjust = IGB_I210_RX_LATENCY_100; 1107 break; 1108 case SPEED_1000: 1109 adjust = IGB_I210_RX_LATENCY_1000; 1110 break; 1111 } 1112 } 1113 skb_hwtstamps(skb)->hwtstamp = 1114 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 1115 1116 /* Update the last_rx_timestamp timer in order to enable watchdog check 1117 * for error case of latched timestamp on a dropped packet. 1118 */ 1119 adapter->last_rx_timestamp = jiffies; 1120 } 1121 1122 /** 1123 * igb_ptp_get_ts_config - get hardware time stamping config 1124 * @netdev: netdev struct 1125 * @ifr: interface struct 1126 * 1127 * Get the hwtstamp_config settings to return to the user. Rather than attempt 1128 * to deconstruct the settings from the registers, just return a shadow copy 1129 * of the last known settings. 1130 **/ 1131 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 1132 { 1133 struct igb_adapter *adapter = netdev_priv(netdev); 1134 struct hwtstamp_config *config = &adapter->tstamp_config; 1135 1136 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 1137 -EFAULT : 0; 1138 } 1139 1140 /** 1141 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 1142 * @adapter: networking device structure 1143 * @config: hwtstamp configuration 1144 * 1145 * Outgoing time stamping can be enabled and disabled. Play nice and 1146 * disable it when requested, although it shouldn't case any overhead 1147 * when no packet needs it. At most one packet in the queue may be 1148 * marked for time stamping, otherwise it would be impossible to tell 1149 * for sure to which packet the hardware time stamp belongs. 1150 * 1151 * Incoming time stamping has to be configured via the hardware 1152 * filters. Not all combinations are supported, in particular event 1153 * type has to be specified. Matching the kind of event packet is 1154 * not supported, with the exception of "all V2 events regardless of 1155 * level 2 or 4". 1156 */ 1157 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 1158 struct hwtstamp_config *config) 1159 { 1160 struct e1000_hw *hw = &adapter->hw; 1161 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 1162 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1163 u32 tsync_rx_cfg = 0; 1164 bool is_l4 = false; 1165 bool is_l2 = false; 1166 u32 regval; 1167 1168 switch (config->tx_type) { 1169 case HWTSTAMP_TX_OFF: 1170 tsync_tx_ctl = 0; 1171 break; 1172 case HWTSTAMP_TX_ON: 1173 break; 1174 default: 1175 return -ERANGE; 1176 } 1177 1178 switch (config->rx_filter) { 1179 case HWTSTAMP_FILTER_NONE: 1180 tsync_rx_ctl = 0; 1181 break; 1182 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1183 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1184 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 1185 is_l4 = true; 1186 break; 1187 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1188 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1189 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 1190 is_l4 = true; 1191 break; 1192 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1193 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1194 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1195 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1196 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1197 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1198 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1199 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1200 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1201 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 1202 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1203 is_l2 = true; 1204 is_l4 = true; 1205 break; 1206 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1207 case HWTSTAMP_FILTER_NTP_ALL: 1208 case HWTSTAMP_FILTER_ALL: 1209 /* 82576 cannot timestamp all packets, which it needs to do to 1210 * support both V1 Sync and Delay_Req messages 1211 */ 1212 if (hw->mac.type != e1000_82576) { 1213 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1214 config->rx_filter = HWTSTAMP_FILTER_ALL; 1215 break; 1216 } 1217 fallthrough; 1218 default: 1219 config->rx_filter = HWTSTAMP_FILTER_NONE; 1220 return -ERANGE; 1221 } 1222 1223 if (hw->mac.type == e1000_82575) { 1224 if (tsync_rx_ctl | tsync_tx_ctl) 1225 return -EINVAL; 1226 return 0; 1227 } 1228 1229 /* Per-packet timestamping only works if all packets are 1230 * timestamped, so enable timestamping in all packets as 1231 * long as one Rx filter was configured. 1232 */ 1233 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1234 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1235 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1236 config->rx_filter = HWTSTAMP_FILTER_ALL; 1237 is_l2 = true; 1238 is_l4 = true; 1239 1240 if ((hw->mac.type == e1000_i210) || 1241 (hw->mac.type == e1000_i211)) { 1242 regval = rd32(E1000_RXPBS); 1243 regval |= E1000_RXPBS_CFG_TS_EN; 1244 wr32(E1000_RXPBS, regval); 1245 } 1246 } 1247 1248 /* enable/disable TX */ 1249 regval = rd32(E1000_TSYNCTXCTL); 1250 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1251 regval |= tsync_tx_ctl; 1252 wr32(E1000_TSYNCTXCTL, regval); 1253 1254 /* enable/disable RX */ 1255 regval = rd32(E1000_TSYNCRXCTL); 1256 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1257 regval |= tsync_rx_ctl; 1258 wr32(E1000_TSYNCRXCTL, regval); 1259 1260 /* define which PTP packets are time stamped */ 1261 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1262 1263 /* define ethertype filter for timestamped packets */ 1264 if (is_l2) 1265 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1266 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1267 E1000_ETQF_1588 | /* enable timestamping */ 1268 ETH_P_1588)); /* 1588 eth protocol type */ 1269 else 1270 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1271 1272 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1273 if (is_l4) { 1274 u32 ftqf = (IPPROTO_UDP /* UDP */ 1275 | E1000_FTQF_VF_BP /* VF not compared */ 1276 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1277 | E1000_FTQF_MASK); /* mask all inputs */ 1278 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1279 1280 wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT)); 1281 wr32(E1000_IMIREXT(3), 1282 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1283 if (hw->mac.type == e1000_82576) { 1284 /* enable source port check */ 1285 wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT)); 1286 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1287 } 1288 wr32(E1000_FTQF(3), ftqf); 1289 } else { 1290 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1291 } 1292 wrfl(); 1293 1294 /* clear TX/RX time stamp registers, just to be sure */ 1295 regval = rd32(E1000_TXSTMPL); 1296 regval = rd32(E1000_TXSTMPH); 1297 regval = rd32(E1000_RXSTMPL); 1298 regval = rd32(E1000_RXSTMPH); 1299 1300 return 0; 1301 } 1302 1303 /** 1304 * igb_ptp_set_ts_config - set hardware time stamping config 1305 * @netdev: netdev struct 1306 * @ifr: interface struct 1307 * 1308 **/ 1309 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1310 { 1311 struct igb_adapter *adapter = netdev_priv(netdev); 1312 struct hwtstamp_config config; 1313 int err; 1314 1315 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1316 return -EFAULT; 1317 1318 err = igb_ptp_set_timestamp_mode(adapter, &config); 1319 if (err) 1320 return err; 1321 1322 /* save these settings for future reference */ 1323 memcpy(&adapter->tstamp_config, &config, 1324 sizeof(adapter->tstamp_config)); 1325 1326 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1327 -EFAULT : 0; 1328 } 1329 1330 /** 1331 * igb_ptp_init - Initialize PTP functionality 1332 * @adapter: Board private structure 1333 * 1334 * This function is called at device probe to initialize the PTP 1335 * functionality. 1336 */ 1337 void igb_ptp_init(struct igb_adapter *adapter) 1338 { 1339 struct e1000_hw *hw = &adapter->hw; 1340 struct net_device *netdev = adapter->netdev; 1341 1342 switch (hw->mac.type) { 1343 case e1000_82576: 1344 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1345 adapter->ptp_caps.owner = THIS_MODULE; 1346 adapter->ptp_caps.max_adj = 999999881; 1347 adapter->ptp_caps.n_ext_ts = 0; 1348 adapter->ptp_caps.pps = 0; 1349 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82576; 1350 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1351 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; 1352 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1353 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1354 adapter->cc.read = igb_ptp_read_82576; 1355 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1356 adapter->cc.mult = 1; 1357 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1358 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1359 break; 1360 case e1000_82580: 1361 case e1000_i354: 1362 case e1000_i350: 1363 igb_ptp_sdp_init(adapter); 1364 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1365 adapter->ptp_caps.owner = THIS_MODULE; 1366 adapter->ptp_caps.max_adj = 62499999; 1367 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1368 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1369 adapter->ptp_caps.n_pins = IGB_N_SDP; 1370 adapter->ptp_caps.pps = 0; 1371 adapter->ptp_caps.pin_config = adapter->sdp_config; 1372 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1373 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1374 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; 1375 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1376 adapter->ptp_caps.enable = igb_ptp_feature_enable_82580; 1377 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1378 adapter->cc.read = igb_ptp_read_82580; 1379 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1380 adapter->cc.mult = 1; 1381 adapter->cc.shift = 0; 1382 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1383 break; 1384 case e1000_i210: 1385 case e1000_i211: 1386 igb_ptp_sdp_init(adapter); 1387 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1388 adapter->ptp_caps.owner = THIS_MODULE; 1389 adapter->ptp_caps.max_adj = 62499999; 1390 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1391 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1392 adapter->ptp_caps.n_pins = IGB_N_SDP; 1393 adapter->ptp_caps.pps = 1; 1394 adapter->ptp_caps.pin_config = adapter->sdp_config; 1395 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1396 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1397 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; 1398 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1399 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1400 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1401 break; 1402 default: 1403 adapter->ptp_clock = NULL; 1404 return; 1405 } 1406 1407 spin_lock_init(&adapter->tmreg_lock); 1408 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1409 1410 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1411 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1412 igb_ptp_overflow_check); 1413 1414 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1415 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1416 1417 igb_ptp_reset(adapter); 1418 1419 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1420 &adapter->pdev->dev); 1421 if (IS_ERR(adapter->ptp_clock)) { 1422 adapter->ptp_clock = NULL; 1423 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1424 } else if (adapter->ptp_clock) { 1425 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1426 adapter->netdev->name); 1427 adapter->ptp_flags |= IGB_PTP_ENABLED; 1428 } 1429 } 1430 1431 /** 1432 * igb_ptp_sdp_init - utility function which inits the SDP config structs 1433 * @adapter: Board private structure. 1434 **/ 1435 void igb_ptp_sdp_init(struct igb_adapter *adapter) 1436 { 1437 int i; 1438 1439 for (i = 0; i < IGB_N_SDP; i++) { 1440 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1441 1442 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1443 ppd->index = i; 1444 ppd->func = PTP_PF_NONE; 1445 } 1446 } 1447 1448 /** 1449 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1450 * @adapter: Board private structure 1451 * 1452 * This function stops the overflow check work and PTP Tx timestamp work, and 1453 * will prepare the device for OS suspend. 1454 */ 1455 void igb_ptp_suspend(struct igb_adapter *adapter) 1456 { 1457 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1458 return; 1459 1460 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1461 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1462 1463 cancel_work_sync(&adapter->ptp_tx_work); 1464 if (adapter->ptp_tx_skb) { 1465 dev_kfree_skb_any(adapter->ptp_tx_skb); 1466 adapter->ptp_tx_skb = NULL; 1467 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1468 } 1469 } 1470 1471 /** 1472 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1473 * @adapter: Board private structure. 1474 * 1475 * This function stops the PTP support and cancels the delayed work. 1476 **/ 1477 void igb_ptp_stop(struct igb_adapter *adapter) 1478 { 1479 igb_ptp_suspend(adapter); 1480 1481 if (adapter->ptp_clock) { 1482 ptp_clock_unregister(adapter->ptp_clock); 1483 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1484 adapter->netdev->name); 1485 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1486 } 1487 } 1488 1489 /** 1490 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1491 * @adapter: Board private structure. 1492 * 1493 * This function handles the reset work required to re-enable the PTP device. 1494 **/ 1495 void igb_ptp_reset(struct igb_adapter *adapter) 1496 { 1497 struct e1000_hw *hw = &adapter->hw; 1498 unsigned long flags; 1499 1500 /* reset the tstamp_config */ 1501 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1502 1503 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1504 1505 switch (adapter->hw.mac.type) { 1506 case e1000_82576: 1507 /* Dial the nominal frequency. */ 1508 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1509 break; 1510 case e1000_82580: 1511 case e1000_i354: 1512 case e1000_i350: 1513 case e1000_i210: 1514 case e1000_i211: 1515 wr32(E1000_TSAUXC, 0x0); 1516 wr32(E1000_TSSDP, 0x0); 1517 wr32(E1000_TSIM, 1518 TSYNC_INTERRUPTS | 1519 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1520 wr32(E1000_IMS, E1000_IMS_TS); 1521 break; 1522 default: 1523 /* No work to do. */ 1524 goto out; 1525 } 1526 1527 /* Re-initialize the timer. */ 1528 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1529 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1530 1531 igb_ptp_write_i210(adapter, &ts); 1532 } else { 1533 timecounter_init(&adapter->tc, &adapter->cc, 1534 ktime_to_ns(ktime_get_real())); 1535 } 1536 out: 1537 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1538 1539 wrfl(); 1540 1541 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1542 schedule_delayed_work(&adapter->ptp_overflow_work, 1543 IGB_SYSTIM_OVERFLOW_PERIOD); 1544 } 1545