1 /* 2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 3 * 4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 #include <linux/module.h> 21 #include <linux/device.h> 22 #include <linux/pci.h> 23 24 #include "igb.h" 25 26 #define INCVALUE_MASK 0x7fffffff 27 #define ISGN 0x80000000 28 29 /* 30 * The 82580 timesync updates the system timer every 8ns by 8ns, 31 * and this update value cannot be reprogrammed. 32 * 33 * Neither the 82576 nor the 82580 offer registers wide enough to hold 34 * nanoseconds time values for very long. For the 82580, SYSTIM always 35 * counts nanoseconds, but the upper 24 bits are not availible. The 36 * frequency is adjusted by changing the 32 bit fractional nanoseconds 37 * register, TIMINCA. 38 * 39 * For the 82576, the SYSTIM register time unit is affect by the 40 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 41 * field are needed to provide the nominal 16 nanosecond period, 42 * leaving 19 bits for fractional nanoseconds. 43 * 44 * We scale the NIC clock cycle by a large factor so that relatively 45 * small clock corrections can be added or subtracted at each clock 46 * tick. The drawbacks of a large factor are a) that the clock 47 * register overflows more quickly (not such a big deal) and b) that 48 * the increment per tick has to fit into 24 bits. As a result we 49 * need to use a shift of 19 so we can fit a value of 16 into the 50 * TIMINCA register. 51 * 52 * 53 * SYSTIMH SYSTIML 54 * +--------------+ +---+---+------+ 55 * 82576 | 32 | | 8 | 5 | 19 | 56 * +--------------+ +---+---+------+ 57 * \________ 45 bits _______/ fract 58 * 59 * +----------+---+ +--------------+ 60 * 82580 | 24 | 8 | | 32 | 61 * +----------+---+ +--------------+ 62 * reserved \______ 40 bits _____/ 63 * 64 * 65 * The 45 bit 82576 SYSTIM overflows every 66 * 2^45 * 10^-9 / 3600 = 9.77 hours. 67 * 68 * The 40 bit 82580 SYSTIM overflows every 69 * 2^40 * 10^-9 / 60 = 18.3 minutes. 70 */ 71 72 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 73 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 74 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) 75 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 76 #define IGB_NBITS_82580 40 77 78 /* 79 * SYSTIM read access for the 82576 80 */ 81 82 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) 83 { 84 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 85 struct e1000_hw *hw = &igb->hw; 86 u64 val; 87 u32 lo, hi; 88 89 lo = rd32(E1000_SYSTIML); 90 hi = rd32(E1000_SYSTIMH); 91 92 val = ((u64) hi) << 32; 93 val |= lo; 94 95 return val; 96 } 97 98 /* 99 * SYSTIM read access for the 82580 100 */ 101 102 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) 103 { 104 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 105 struct e1000_hw *hw = &igb->hw; 106 u64 val; 107 u32 lo, hi, jk; 108 109 /* 110 * The timestamp latches on lowest register read. For the 82580 111 * the lowest register is SYSTIMR instead of SYSTIML. However we only 112 * need to provide nanosecond resolution, so we just ignore it. 113 */ 114 jk = rd32(E1000_SYSTIMR); 115 lo = rd32(E1000_SYSTIML); 116 hi = rd32(E1000_SYSTIMH); 117 118 val = ((u64) hi) << 32; 119 val |= lo; 120 121 return val; 122 } 123 124 /* 125 * SYSTIM read access for I210/I211 126 */ 127 128 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) 129 { 130 struct e1000_hw *hw = &adapter->hw; 131 u32 sec, nsec, jk; 132 133 /* 134 * The timestamp latches on lowest register read. For I210/I211, the 135 * lowest register is SYSTIMR. Since we only need to provide nanosecond 136 * resolution, we can ignore it. 137 */ 138 jk = rd32(E1000_SYSTIMR); 139 nsec = rd32(E1000_SYSTIML); 140 sec = rd32(E1000_SYSTIMH); 141 142 ts->tv_sec = sec; 143 ts->tv_nsec = nsec; 144 } 145 146 static void igb_ptp_write_i210(struct igb_adapter *adapter, 147 const struct timespec *ts) 148 { 149 struct e1000_hw *hw = &adapter->hw; 150 151 /* 152 * Writing the SYSTIMR register is not necessary as it only provides 153 * sub-nanosecond resolution. 154 */ 155 wr32(E1000_SYSTIML, ts->tv_nsec); 156 wr32(E1000_SYSTIMH, ts->tv_sec); 157 } 158 159 /** 160 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 161 * @adapter: board private structure 162 * @hwtstamps: timestamp structure to update 163 * @systim: unsigned 64bit system time value. 164 * 165 * We need to convert the system time value stored in the RX/TXSTMP registers 166 * into a hwtstamp which can be used by the upper level timestamping functions. 167 * 168 * The 'tmreg_lock' spinlock is used to protect the consistency of the 169 * system time value. This is needed because reading the 64 bit time 170 * value involves reading two (or three) 32 bit registers. The first 171 * read latches the value. Ditto for writing. 172 * 173 * In addition, here have extended the system time with an overflow 174 * counter in software. 175 **/ 176 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 177 struct skb_shared_hwtstamps *hwtstamps, 178 u64 systim) 179 { 180 unsigned long flags; 181 u64 ns; 182 183 switch (adapter->hw.mac.type) { 184 case e1000_82576: 185 case e1000_82580: 186 case e1000_i350: 187 spin_lock_irqsave(&adapter->tmreg_lock, flags); 188 189 ns = timecounter_cyc2time(&adapter->tc, systim); 190 191 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 192 193 memset(hwtstamps, 0, sizeof(*hwtstamps)); 194 hwtstamps->hwtstamp = ns_to_ktime(ns); 195 break; 196 case e1000_i210: 197 case e1000_i211: 198 memset(hwtstamps, 0, sizeof(*hwtstamps)); 199 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 200 hwtstamps->hwtstamp = ktime_set(systim >> 32, 201 systim & 0xFFFFFFFF); 202 break; 203 default: 204 break; 205 } 206 } 207 208 /* 209 * PTP clock operations 210 */ 211 212 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 213 { 214 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 215 ptp_caps); 216 struct e1000_hw *hw = &igb->hw; 217 int neg_adj = 0; 218 u64 rate; 219 u32 incvalue; 220 221 if (ppb < 0) { 222 neg_adj = 1; 223 ppb = -ppb; 224 } 225 rate = ppb; 226 rate <<= 14; 227 rate = div_u64(rate, 1953125); 228 229 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 230 231 if (neg_adj) 232 incvalue -= rate; 233 else 234 incvalue += rate; 235 236 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 237 238 return 0; 239 } 240 241 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) 242 { 243 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 244 ptp_caps); 245 struct e1000_hw *hw = &igb->hw; 246 int neg_adj = 0; 247 u64 rate; 248 u32 inca; 249 250 if (ppb < 0) { 251 neg_adj = 1; 252 ppb = -ppb; 253 } 254 rate = ppb; 255 rate <<= 26; 256 rate = div_u64(rate, 1953125); 257 258 inca = rate & INCVALUE_MASK; 259 if (neg_adj) 260 inca |= ISGN; 261 262 wr32(E1000_TIMINCA, inca); 263 264 return 0; 265 } 266 267 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 268 { 269 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 270 ptp_caps); 271 unsigned long flags; 272 s64 now; 273 274 spin_lock_irqsave(&igb->tmreg_lock, flags); 275 276 now = timecounter_read(&igb->tc); 277 now += delta; 278 timecounter_init(&igb->tc, &igb->cc, now); 279 280 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 281 282 return 0; 283 } 284 285 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 286 { 287 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 288 ptp_caps); 289 unsigned long flags; 290 struct timespec now, then = ns_to_timespec(delta); 291 292 spin_lock_irqsave(&igb->tmreg_lock, flags); 293 294 igb_ptp_read_i210(igb, &now); 295 now = timespec_add(now, then); 296 igb_ptp_write_i210(igb, (const struct timespec *)&now); 297 298 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 299 300 return 0; 301 } 302 303 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 304 struct timespec *ts) 305 { 306 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 307 ptp_caps); 308 unsigned long flags; 309 u64 ns; 310 u32 remainder; 311 312 spin_lock_irqsave(&igb->tmreg_lock, flags); 313 314 ns = timecounter_read(&igb->tc); 315 316 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 317 318 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); 319 ts->tv_nsec = remainder; 320 321 return 0; 322 } 323 324 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 325 struct timespec *ts) 326 { 327 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 328 ptp_caps); 329 unsigned long flags; 330 331 spin_lock_irqsave(&igb->tmreg_lock, flags); 332 333 igb_ptp_read_i210(igb, ts); 334 335 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 336 337 return 0; 338 } 339 340 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 341 const struct timespec *ts) 342 { 343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 344 ptp_caps); 345 unsigned long flags; 346 u64 ns; 347 348 ns = ts->tv_sec * 1000000000ULL; 349 ns += ts->tv_nsec; 350 351 spin_lock_irqsave(&igb->tmreg_lock, flags); 352 353 timecounter_init(&igb->tc, &igb->cc, ns); 354 355 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 356 357 return 0; 358 } 359 360 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 361 const struct timespec *ts) 362 { 363 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 364 ptp_caps); 365 unsigned long flags; 366 367 spin_lock_irqsave(&igb->tmreg_lock, flags); 368 369 igb_ptp_write_i210(igb, ts); 370 371 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 372 373 return 0; 374 } 375 376 static int igb_ptp_enable(struct ptp_clock_info *ptp, 377 struct ptp_clock_request *rq, int on) 378 { 379 return -EOPNOTSUPP; 380 } 381 382 /** 383 * igb_ptp_tx_work 384 * @work: pointer to work struct 385 * 386 * This work function polls the TSYNCTXCTL valid bit to determine when a 387 * timestamp has been taken for the current stored skb. 388 */ 389 void igb_ptp_tx_work(struct work_struct *work) 390 { 391 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 392 ptp_tx_work); 393 struct e1000_hw *hw = &adapter->hw; 394 u32 tsynctxctl; 395 396 if (!adapter->ptp_tx_skb) 397 return; 398 399 tsynctxctl = rd32(E1000_TSYNCTXCTL); 400 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 401 igb_ptp_tx_hwtstamp(adapter); 402 else 403 /* reschedule to check later */ 404 schedule_work(&adapter->ptp_tx_work); 405 } 406 407 static void igb_ptp_overflow_check(struct work_struct *work) 408 { 409 struct igb_adapter *igb = 410 container_of(work, struct igb_adapter, ptp_overflow_work.work); 411 struct timespec ts; 412 413 igb->ptp_caps.gettime(&igb->ptp_caps, &ts); 414 415 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); 416 417 schedule_delayed_work(&igb->ptp_overflow_work, 418 IGB_SYSTIM_OVERFLOW_PERIOD); 419 } 420 421 /** 422 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 423 * @adapter: Board private structure. 424 * 425 * If we were asked to do hardware stamping and such a time stamp is 426 * available, then it must have been for this skb here because we only 427 * allow only one such packet into the queue. 428 */ 429 void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 430 { 431 struct e1000_hw *hw = &adapter->hw; 432 struct skb_shared_hwtstamps shhwtstamps; 433 u64 regval; 434 435 regval = rd32(E1000_TXSTMPL); 436 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 437 438 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 439 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 440 dev_kfree_skb_any(adapter->ptp_tx_skb); 441 adapter->ptp_tx_skb = NULL; 442 } 443 444 void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector, 445 union e1000_adv_rx_desc *rx_desc, 446 struct sk_buff *skb) 447 { 448 struct igb_adapter *adapter = q_vector->adapter; 449 struct e1000_hw *hw = &adapter->hw; 450 u64 regval; 451 452 if (!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP | 453 E1000_RXDADV_STAT_TS)) 454 return; 455 456 /* 457 * If this bit is set, then the RX registers contain the time stamp. No 458 * other packet will be time stamped until we read these registers, so 459 * read the registers to make them available again. Because only one 460 * packet can be time stamped at a time, we know that the register 461 * values must belong to this one here and therefore we don't need to 462 * compare any of the additional attributes stored for it. 463 * 464 * If nothing went wrong, then it should have a shared tx_flags that we 465 * can turn into a skb_shared_hwtstamps. 466 */ 467 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 468 u32 *stamp = (u32 *)skb->data; 469 regval = le32_to_cpu(*(stamp + 2)); 470 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32; 471 skb_pull(skb, IGB_TS_HDR_LEN); 472 } else { 473 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 474 return; 475 476 regval = rd32(E1000_RXSTMPL); 477 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 478 } 479 480 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 481 } 482 483 /** 484 * igb_ptp_hwtstamp_ioctl - control hardware time stamping 485 * @netdev: 486 * @ifreq: 487 * @cmd: 488 * 489 * Outgoing time stamping can be enabled and disabled. Play nice and 490 * disable it when requested, although it shouldn't case any overhead 491 * when no packet needs it. At most one packet in the queue may be 492 * marked for time stamping, otherwise it would be impossible to tell 493 * for sure to which packet the hardware time stamp belongs. 494 * 495 * Incoming time stamping has to be configured via the hardware 496 * filters. Not all combinations are supported, in particular event 497 * type has to be specified. Matching the kind of event packet is 498 * not supported, with the exception of "all V2 events regardless of 499 * level 2 or 4". 500 * 501 **/ 502 int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 503 struct ifreq *ifr, int cmd) 504 { 505 struct igb_adapter *adapter = netdev_priv(netdev); 506 struct e1000_hw *hw = &adapter->hw; 507 struct hwtstamp_config config; 508 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 509 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 510 u32 tsync_rx_cfg = 0; 511 bool is_l4 = false; 512 bool is_l2 = false; 513 u32 regval; 514 515 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 516 return -EFAULT; 517 518 /* reserved for future extensions */ 519 if (config.flags) 520 return -EINVAL; 521 522 switch (config.tx_type) { 523 case HWTSTAMP_TX_OFF: 524 tsync_tx_ctl = 0; 525 case HWTSTAMP_TX_ON: 526 break; 527 default: 528 return -ERANGE; 529 } 530 531 switch (config.rx_filter) { 532 case HWTSTAMP_FILTER_NONE: 533 tsync_rx_ctl = 0; 534 break; 535 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 536 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 537 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 538 case HWTSTAMP_FILTER_ALL: 539 /* 540 * register TSYNCRXCFG must be set, therefore it is not 541 * possible to time stamp both Sync and Delay_Req messages 542 * => fall back to time stamping all packets 543 */ 544 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 545 config.rx_filter = HWTSTAMP_FILTER_ALL; 546 break; 547 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 548 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 549 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 550 is_l4 = true; 551 break; 552 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 553 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 554 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 555 is_l4 = true; 556 break; 557 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 558 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 559 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 560 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; 561 is_l2 = true; 562 is_l4 = true; 563 config.rx_filter = HWTSTAMP_FILTER_SOME; 564 break; 565 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 566 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 567 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 568 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; 569 is_l2 = true; 570 is_l4 = true; 571 config.rx_filter = HWTSTAMP_FILTER_SOME; 572 break; 573 case HWTSTAMP_FILTER_PTP_V2_EVENT: 574 case HWTSTAMP_FILTER_PTP_V2_SYNC: 575 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 576 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 577 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 578 is_l2 = true; 579 is_l4 = true; 580 break; 581 default: 582 return -ERANGE; 583 } 584 585 if (hw->mac.type == e1000_82575) { 586 if (tsync_rx_ctl | tsync_tx_ctl) 587 return -EINVAL; 588 return 0; 589 } 590 591 /* 592 * Per-packet timestamping only works if all packets are 593 * timestamped, so enable timestamping in all packets as 594 * long as one rx filter was configured. 595 */ 596 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 597 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 598 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 599 600 if ((hw->mac.type == e1000_i210) || 601 (hw->mac.type == e1000_i211)) { 602 regval = rd32(E1000_RXPBS); 603 regval |= E1000_RXPBS_CFG_TS_EN; 604 wr32(E1000_RXPBS, regval); 605 } 606 } 607 608 /* enable/disable TX */ 609 regval = rd32(E1000_TSYNCTXCTL); 610 regval &= ~E1000_TSYNCTXCTL_ENABLED; 611 regval |= tsync_tx_ctl; 612 wr32(E1000_TSYNCTXCTL, regval); 613 614 /* enable/disable RX */ 615 regval = rd32(E1000_TSYNCRXCTL); 616 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 617 regval |= tsync_rx_ctl; 618 wr32(E1000_TSYNCRXCTL, regval); 619 620 /* define which PTP packets are time stamped */ 621 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 622 623 /* define ethertype filter for timestamped packets */ 624 if (is_l2) 625 wr32(E1000_ETQF(3), 626 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 627 E1000_ETQF_1588 | /* enable timestamping */ 628 ETH_P_1588)); /* 1588 eth protocol type */ 629 else 630 wr32(E1000_ETQF(3), 0); 631 632 #define PTP_PORT 319 633 /* L4 Queue Filter[3]: filter by destination port and protocol */ 634 if (is_l4) { 635 u32 ftqf = (IPPROTO_UDP /* UDP */ 636 | E1000_FTQF_VF_BP /* VF not compared */ 637 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 638 | E1000_FTQF_MASK); /* mask all inputs */ 639 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 640 641 wr32(E1000_IMIR(3), htons(PTP_PORT)); 642 wr32(E1000_IMIREXT(3), 643 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 644 if (hw->mac.type == e1000_82576) { 645 /* enable source port check */ 646 wr32(E1000_SPQF(3), htons(PTP_PORT)); 647 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 648 } 649 wr32(E1000_FTQF(3), ftqf); 650 } else { 651 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 652 } 653 wrfl(); 654 655 /* clear TX/RX time stamp registers, just to be sure */ 656 regval = rd32(E1000_TXSTMPL); 657 regval = rd32(E1000_TXSTMPH); 658 regval = rd32(E1000_RXSTMPL); 659 regval = rd32(E1000_RXSTMPH); 660 661 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 662 -EFAULT : 0; 663 } 664 665 void igb_ptp_init(struct igb_adapter *adapter) 666 { 667 struct e1000_hw *hw = &adapter->hw; 668 struct net_device *netdev = adapter->netdev; 669 670 switch (hw->mac.type) { 671 case e1000_82576: 672 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 673 adapter->ptp_caps.owner = THIS_MODULE; 674 adapter->ptp_caps.max_adj = 1000000000; 675 adapter->ptp_caps.n_ext_ts = 0; 676 adapter->ptp_caps.pps = 0; 677 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 678 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 679 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 680 adapter->ptp_caps.settime = igb_ptp_settime_82576; 681 adapter->ptp_caps.enable = igb_ptp_enable; 682 adapter->cc.read = igb_ptp_read_82576; 683 adapter->cc.mask = CLOCKSOURCE_MASK(64); 684 adapter->cc.mult = 1; 685 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 686 /* Dial the nominal frequency. */ 687 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 688 break; 689 case e1000_82580: 690 case e1000_i350: 691 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 692 adapter->ptp_caps.owner = THIS_MODULE; 693 adapter->ptp_caps.max_adj = 62499999; 694 adapter->ptp_caps.n_ext_ts = 0; 695 adapter->ptp_caps.pps = 0; 696 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 697 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 698 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 699 adapter->ptp_caps.settime = igb_ptp_settime_82576; 700 adapter->ptp_caps.enable = igb_ptp_enable; 701 adapter->cc.read = igb_ptp_read_82580; 702 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); 703 adapter->cc.mult = 1; 704 adapter->cc.shift = 0; 705 /* Enable the timer functions by clearing bit 31. */ 706 wr32(E1000_TSAUXC, 0x0); 707 break; 708 case e1000_i210: 709 case e1000_i211: 710 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 711 adapter->ptp_caps.owner = THIS_MODULE; 712 adapter->ptp_caps.max_adj = 62499999; 713 adapter->ptp_caps.n_ext_ts = 0; 714 adapter->ptp_caps.pps = 0; 715 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 716 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 717 adapter->ptp_caps.gettime = igb_ptp_gettime_i210; 718 adapter->ptp_caps.settime = igb_ptp_settime_i210; 719 adapter->ptp_caps.enable = igb_ptp_enable; 720 /* Enable the timer functions by clearing bit 31. */ 721 wr32(E1000_TSAUXC, 0x0); 722 break; 723 default: 724 adapter->ptp_clock = NULL; 725 return; 726 } 727 728 wrfl(); 729 730 spin_lock_init(&adapter->tmreg_lock); 731 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 732 733 /* Initialize the clock and overflow work for devices that need it. */ 734 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 735 struct timespec ts = ktime_to_timespec(ktime_get_real()); 736 737 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 738 } else { 739 timecounter_init(&adapter->tc, &adapter->cc, 740 ktime_to_ns(ktime_get_real())); 741 742 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 743 igb_ptp_overflow_check); 744 745 schedule_delayed_work(&adapter->ptp_overflow_work, 746 IGB_SYSTIM_OVERFLOW_PERIOD); 747 } 748 749 /* Initialize the time sync interrupts for devices that support it. */ 750 if (hw->mac.type >= e1000_82580) { 751 wr32(E1000_TSIM, E1000_TSIM_TXTS); 752 wr32(E1000_IMS, E1000_IMS_TS); 753 } 754 755 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 756 &adapter->pdev->dev); 757 if (IS_ERR(adapter->ptp_clock)) { 758 adapter->ptp_clock = NULL; 759 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 760 } else { 761 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 762 adapter->netdev->name); 763 adapter->flags |= IGB_FLAG_PTP; 764 } 765 } 766 767 /** 768 * igb_ptp_stop - Disable PTP device and stop the overflow check. 769 * @adapter: Board private structure. 770 * 771 * This function stops the PTP support and cancels the delayed work. 772 **/ 773 void igb_ptp_stop(struct igb_adapter *adapter) 774 { 775 switch (adapter->hw.mac.type) { 776 case e1000_82576: 777 case e1000_82580: 778 case e1000_i350: 779 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 780 break; 781 case e1000_i210: 782 case e1000_i211: 783 /* No delayed work to cancel. */ 784 break; 785 default: 786 return; 787 } 788 789 cancel_work_sync(&adapter->ptp_tx_work); 790 791 if (adapter->ptp_clock) { 792 ptp_clock_unregister(adapter->ptp_clock); 793 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 794 adapter->netdev->name); 795 adapter->flags &= ~IGB_FLAG_PTP; 796 } 797 } 798 799 /** 800 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 801 * @adapter: Board private structure. 802 * 803 * This function handles the reset work required to re-enable the PTP device. 804 **/ 805 void igb_ptp_reset(struct igb_adapter *adapter) 806 { 807 struct e1000_hw *hw = &adapter->hw; 808 809 if (!(adapter->flags & IGB_FLAG_PTP)) 810 return; 811 812 switch (adapter->hw.mac.type) { 813 case e1000_82576: 814 /* Dial the nominal frequency. */ 815 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 816 break; 817 case e1000_82580: 818 case e1000_i350: 819 case e1000_i210: 820 case e1000_i211: 821 /* Enable the timer functions and interrupts. */ 822 wr32(E1000_TSAUXC, 0x0); 823 wr32(E1000_TSIM, E1000_TSIM_TXTS); 824 wr32(E1000_IMS, E1000_IMS_TS); 825 break; 826 default: 827 /* No work to do. */ 828 return; 829 } 830 831 /* Re-initialize the timer. */ 832 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 833 struct timespec ts = ktime_to_timespec(ktime_get_real()); 834 835 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 836 } else { 837 timecounter_init(&adapter->tc, &adapter->cc, 838 ktime_to_ns(ktime_get_real())); 839 } 840 } 841