1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */ 3 4 #include <linux/module.h> 5 #include <linux/device.h> 6 #include <linux/pci.h> 7 #include <linux/ptp_classify.h> 8 9 #include "igb.h" 10 11 #define INCVALUE_MASK 0x7fffffff 12 #define ISGN 0x80000000 13 14 /* The 82580 timesync updates the system timer every 8ns by 8ns, 15 * and this update value cannot be reprogrammed. 16 * 17 * Neither the 82576 nor the 82580 offer registers wide enough to hold 18 * nanoseconds time values for very long. For the 82580, SYSTIM always 19 * counts nanoseconds, but the upper 24 bits are not available. The 20 * frequency is adjusted by changing the 32 bit fractional nanoseconds 21 * register, TIMINCA. 22 * 23 * For the 82576, the SYSTIM register time unit is affect by the 24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 25 * field are needed to provide the nominal 16 nanosecond period, 26 * leaving 19 bits for fractional nanoseconds. 27 * 28 * We scale the NIC clock cycle by a large factor so that relatively 29 * small clock corrections can be added or subtracted at each clock 30 * tick. The drawbacks of a large factor are a) that the clock 31 * register overflows more quickly (not such a big deal) and b) that 32 * the increment per tick has to fit into 24 bits. As a result we 33 * need to use a shift of 19 so we can fit a value of 16 into the 34 * TIMINCA register. 35 * 36 * 37 * SYSTIMH SYSTIML 38 * +--------------+ +---+---+------+ 39 * 82576 | 32 | | 8 | 5 | 19 | 40 * +--------------+ +---+---+------+ 41 * \________ 45 bits _______/ fract 42 * 43 * +----------+---+ +--------------+ 44 * 82580 | 24 | 8 | | 32 | 45 * +----------+---+ +--------------+ 46 * reserved \______ 40 bits _____/ 47 * 48 * 49 * The 45 bit 82576 SYSTIM overflows every 50 * 2^45 * 10^-9 / 3600 = 9.77 hours. 51 * 52 * The 40 bit 82580 SYSTIM overflows every 53 * 2^40 * 10^-9 / 60 = 18.3 minutes. 54 * 55 * SYSTIM is converted to real time using a timecounter. As 56 * timecounter_cyc2time() allows old timestamps, the timecounter needs 57 * to be updated at least once per half of the SYSTIM interval. 58 * Scheduling of delayed work is not very accurate, and also the NIC 59 * clock can be adjusted to run up to 6% faster and the system clock 60 * up to 10% slower, so we aim for 6 minutes to be sure the actual 61 * interval in the NIC time is shorter than 9.16 minutes. 62 */ 63 64 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6) 65 #define IGB_PTP_TX_TIMEOUT (HZ * 15) 66 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT) 67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0) 68 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT) 69 #define IGB_NBITS_82580 40 70 71 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 72 73 /* SYSTIM read access for the 82576 */ 74 static u64 igb_ptp_read_82576(const struct cyclecounter *cc) 75 { 76 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 77 struct e1000_hw *hw = &igb->hw; 78 u64 val; 79 u32 lo, hi; 80 81 lo = rd32(E1000_SYSTIML); 82 hi = rd32(E1000_SYSTIMH); 83 84 val = ((u64) hi) << 32; 85 val |= lo; 86 87 return val; 88 } 89 90 /* SYSTIM read access for the 82580 */ 91 static u64 igb_ptp_read_82580(const struct cyclecounter *cc) 92 { 93 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 94 struct e1000_hw *hw = &igb->hw; 95 u32 lo, hi; 96 u64 val; 97 98 /* The timestamp latches on lowest register read. For the 82580 99 * the lowest register is SYSTIMR instead of SYSTIML. However we only 100 * need to provide nanosecond resolution, so we just ignore it. 101 */ 102 rd32(E1000_SYSTIMR); 103 lo = rd32(E1000_SYSTIML); 104 hi = rd32(E1000_SYSTIMH); 105 106 val = ((u64) hi) << 32; 107 val |= lo; 108 109 return val; 110 } 111 112 /* SYSTIM read access for I210/I211 */ 113 static void igb_ptp_read_i210(struct igb_adapter *adapter, 114 struct timespec64 *ts) 115 { 116 struct e1000_hw *hw = &adapter->hw; 117 u32 sec, nsec; 118 119 /* The timestamp latches on lowest register read. For I210/I211, the 120 * lowest register is SYSTIMR. Since we only need to provide nanosecond 121 * resolution, we can ignore it. 122 */ 123 rd32(E1000_SYSTIMR); 124 nsec = rd32(E1000_SYSTIML); 125 sec = rd32(E1000_SYSTIMH); 126 127 ts->tv_sec = sec; 128 ts->tv_nsec = nsec; 129 } 130 131 static void igb_ptp_write_i210(struct igb_adapter *adapter, 132 const struct timespec64 *ts) 133 { 134 struct e1000_hw *hw = &adapter->hw; 135 136 /* Writing the SYSTIMR register is not necessary as it only provides 137 * sub-nanosecond resolution. 138 */ 139 wr32(E1000_SYSTIML, ts->tv_nsec); 140 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); 141 } 142 143 /** 144 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 145 * @adapter: board private structure 146 * @hwtstamps: timestamp structure to update 147 * @systim: unsigned 64bit system time value. 148 * 149 * We need to convert the system time value stored in the RX/TXSTMP registers 150 * into a hwtstamp which can be used by the upper level timestamping functions. 151 * 152 * The 'tmreg_lock' spinlock is used to protect the consistency of the 153 * system time value. This is needed because reading the 64 bit time 154 * value involves reading two (or three) 32 bit registers. The first 155 * read latches the value. Ditto for writing. 156 * 157 * In addition, here have extended the system time with an overflow 158 * counter in software. 159 **/ 160 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 161 struct skb_shared_hwtstamps *hwtstamps, 162 u64 systim) 163 { 164 unsigned long flags; 165 u64 ns; 166 167 switch (adapter->hw.mac.type) { 168 case e1000_82576: 169 case e1000_82580: 170 case e1000_i354: 171 case e1000_i350: 172 spin_lock_irqsave(&adapter->tmreg_lock, flags); 173 174 ns = timecounter_cyc2time(&adapter->tc, systim); 175 176 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 177 178 memset(hwtstamps, 0, sizeof(*hwtstamps)); 179 hwtstamps->hwtstamp = ns_to_ktime(ns); 180 break; 181 case e1000_i210: 182 case e1000_i211: 183 memset(hwtstamps, 0, sizeof(*hwtstamps)); 184 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 185 hwtstamps->hwtstamp = ktime_set(systim >> 32, 186 systim & 0xFFFFFFFF); 187 break; 188 default: 189 break; 190 } 191 } 192 193 /* PTP clock operations */ 194 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 195 { 196 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 197 ptp_caps); 198 struct e1000_hw *hw = &igb->hw; 199 int neg_adj = 0; 200 u64 rate; 201 u32 incvalue; 202 203 if (ppb < 0) { 204 neg_adj = 1; 205 ppb = -ppb; 206 } 207 rate = ppb; 208 rate <<= 14; 209 rate = div_u64(rate, 1953125); 210 211 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 212 213 if (neg_adj) 214 incvalue -= rate; 215 else 216 incvalue += rate; 217 218 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 219 220 return 0; 221 } 222 223 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm) 224 { 225 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 226 ptp_caps); 227 struct e1000_hw *hw = &igb->hw; 228 int neg_adj = 0; 229 u64 rate; 230 u32 inca; 231 232 if (scaled_ppm < 0) { 233 neg_adj = 1; 234 scaled_ppm = -scaled_ppm; 235 } 236 rate = scaled_ppm; 237 rate <<= 13; 238 rate = div_u64(rate, 15625); 239 240 inca = rate & INCVALUE_MASK; 241 if (neg_adj) 242 inca |= ISGN; 243 244 wr32(E1000_TIMINCA, inca); 245 246 return 0; 247 } 248 249 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 250 { 251 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 252 ptp_caps); 253 unsigned long flags; 254 255 spin_lock_irqsave(&igb->tmreg_lock, flags); 256 timecounter_adjtime(&igb->tc, delta); 257 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 258 259 return 0; 260 } 261 262 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 263 { 264 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 265 ptp_caps); 266 unsigned long flags; 267 struct timespec64 now, then = ns_to_timespec64(delta); 268 269 spin_lock_irqsave(&igb->tmreg_lock, flags); 270 271 igb_ptp_read_i210(igb, &now); 272 now = timespec64_add(now, then); 273 igb_ptp_write_i210(igb, (const struct timespec64 *)&now); 274 275 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 276 277 return 0; 278 } 279 280 static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp, 281 struct timespec64 *ts, 282 struct ptp_system_timestamp *sts) 283 { 284 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 285 ptp_caps); 286 struct e1000_hw *hw = &igb->hw; 287 unsigned long flags; 288 u32 lo, hi; 289 u64 ns; 290 291 spin_lock_irqsave(&igb->tmreg_lock, flags); 292 293 ptp_read_system_prets(sts); 294 lo = rd32(E1000_SYSTIML); 295 ptp_read_system_postts(sts); 296 hi = rd32(E1000_SYSTIMH); 297 298 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 299 300 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 301 302 *ts = ns_to_timespec64(ns); 303 304 return 0; 305 } 306 307 static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp, 308 struct timespec64 *ts, 309 struct ptp_system_timestamp *sts) 310 { 311 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 312 ptp_caps); 313 struct e1000_hw *hw = &igb->hw; 314 unsigned long flags; 315 u32 lo, hi; 316 u64 ns; 317 318 spin_lock_irqsave(&igb->tmreg_lock, flags); 319 320 ptp_read_system_prets(sts); 321 rd32(E1000_SYSTIMR); 322 ptp_read_system_postts(sts); 323 lo = rd32(E1000_SYSTIML); 324 hi = rd32(E1000_SYSTIMH); 325 326 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo); 327 328 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 329 330 *ts = ns_to_timespec64(ns); 331 332 return 0; 333 } 334 335 static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp, 336 struct timespec64 *ts, 337 struct ptp_system_timestamp *sts) 338 { 339 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 340 ptp_caps); 341 struct e1000_hw *hw = &igb->hw; 342 unsigned long flags; 343 344 spin_lock_irqsave(&igb->tmreg_lock, flags); 345 346 ptp_read_system_prets(sts); 347 rd32(E1000_SYSTIMR); 348 ptp_read_system_postts(sts); 349 ts->tv_nsec = rd32(E1000_SYSTIML); 350 ts->tv_sec = rd32(E1000_SYSTIMH); 351 352 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 353 354 return 0; 355 } 356 357 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 358 const struct timespec64 *ts) 359 { 360 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 361 ptp_caps); 362 unsigned long flags; 363 u64 ns; 364 365 ns = timespec64_to_ns(ts); 366 367 spin_lock_irqsave(&igb->tmreg_lock, flags); 368 369 timecounter_init(&igb->tc, &igb->cc, ns); 370 371 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 372 373 return 0; 374 } 375 376 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 377 const struct timespec64 *ts) 378 { 379 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 380 ptp_caps); 381 unsigned long flags; 382 383 spin_lock_irqsave(&igb->tmreg_lock, flags); 384 385 igb_ptp_write_i210(igb, ts); 386 387 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 388 389 return 0; 390 } 391 392 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 393 { 394 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 395 static const u32 mask[IGB_N_SDP] = { 396 E1000_CTRL_SDP0_DIR, 397 E1000_CTRL_SDP1_DIR, 398 E1000_CTRL_EXT_SDP2_DIR, 399 E1000_CTRL_EXT_SDP3_DIR, 400 }; 401 402 if (input) 403 *ptr &= ~mask[pin]; 404 else 405 *ptr |= mask[pin]; 406 } 407 408 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) 409 { 410 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 412 }; 413 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 415 }; 416 static const u32 ts_sdp_en[IGB_N_SDP] = { 417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 418 }; 419 struct e1000_hw *hw = &igb->hw; 420 u32 ctrl, ctrl_ext, tssdp = 0; 421 422 ctrl = rd32(E1000_CTRL); 423 ctrl_ext = rd32(E1000_CTRL_EXT); 424 tssdp = rd32(E1000_TSSDP); 425 426 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); 427 428 /* Make sure this pin is not enabled as an output. */ 429 tssdp &= ~ts_sdp_en[pin]; 430 431 if (chan == 1) { 432 tssdp &= ~AUX1_SEL_SDP3; 433 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; 434 } else { 435 tssdp &= ~AUX0_SEL_SDP3; 436 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; 437 } 438 439 wr32(E1000_TSSDP, tssdp); 440 wr32(E1000_CTRL, ctrl); 441 wr32(E1000_CTRL_EXT, ctrl_ext); 442 } 443 444 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) 445 { 446 static const u32 aux0_sel_sdp[IGB_N_SDP] = { 447 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3, 448 }; 449 static const u32 aux1_sel_sdp[IGB_N_SDP] = { 450 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3, 451 }; 452 static const u32 ts_sdp_en[IGB_N_SDP] = { 453 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN, 454 }; 455 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = { 456 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0, 457 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0, 458 }; 459 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = { 460 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1, 461 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1, 462 }; 463 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = { 464 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0, 465 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0, 466 }; 467 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = { 468 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 469 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 470 }; 471 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = { 472 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1, 473 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1, 474 }; 475 struct e1000_hw *hw = &igb->hw; 476 u32 ctrl, ctrl_ext, tssdp = 0; 477 478 ctrl = rd32(E1000_CTRL); 479 ctrl_ext = rd32(E1000_CTRL_EXT); 480 tssdp = rd32(E1000_TSSDP); 481 482 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext); 483 484 /* Make sure this pin is not enabled as an input. */ 485 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin]) 486 tssdp &= ~AUX0_TS_SDP_EN; 487 488 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin]) 489 tssdp &= ~AUX1_TS_SDP_EN; 490 491 tssdp &= ~ts_sdp_sel_clr[pin]; 492 if (freq) { 493 if (chan == 1) 494 tssdp |= ts_sdp_sel_fc1[pin]; 495 else 496 tssdp |= ts_sdp_sel_fc0[pin]; 497 } else { 498 if (chan == 1) 499 tssdp |= ts_sdp_sel_tt1[pin]; 500 else 501 tssdp |= ts_sdp_sel_tt0[pin]; 502 } 503 tssdp |= ts_sdp_en[pin]; 504 505 wr32(E1000_TSSDP, tssdp); 506 wr32(E1000_CTRL, ctrl); 507 wr32(E1000_CTRL_EXT, ctrl_ext); 508 } 509 510 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp, 511 struct ptp_clock_request *rq, int on) 512 { 513 struct igb_adapter *igb = 514 container_of(ptp, struct igb_adapter, ptp_caps); 515 struct e1000_hw *hw = &igb->hw; 516 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 517 unsigned long flags; 518 struct timespec64 ts; 519 int use_freq = 0, pin = -1; 520 s64 ns; 521 522 switch (rq->type) { 523 case PTP_CLK_REQ_EXTTS: 524 if (on) { 525 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS, 526 rq->extts.index); 527 if (pin < 0) 528 return -EBUSY; 529 } 530 if (rq->extts.index == 1) { 531 tsauxc_mask = TSAUXC_EN_TS1; 532 tsim_mask = TSINTR_AUTT1; 533 } else { 534 tsauxc_mask = TSAUXC_EN_TS0; 535 tsim_mask = TSINTR_AUTT0; 536 } 537 spin_lock_irqsave(&igb->tmreg_lock, flags); 538 tsauxc = rd32(E1000_TSAUXC); 539 tsim = rd32(E1000_TSIM); 540 if (on) { 541 igb_pin_extts(igb, rq->extts.index, pin); 542 tsauxc |= tsauxc_mask; 543 tsim |= tsim_mask; 544 } else { 545 tsauxc &= ~tsauxc_mask; 546 tsim &= ~tsim_mask; 547 } 548 wr32(E1000_TSAUXC, tsauxc); 549 wr32(E1000_TSIM, tsim); 550 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 551 return 0; 552 553 case PTP_CLK_REQ_PEROUT: 554 if (on) { 555 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT, 556 rq->perout.index); 557 if (pin < 0) 558 return -EBUSY; 559 } 560 ts.tv_sec = rq->perout.period.sec; 561 ts.tv_nsec = rq->perout.period.nsec; 562 ns = timespec64_to_ns(&ts); 563 ns = ns >> 1; 564 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) || 565 (ns == 250000000LL) || (ns == 500000000LL))) { 566 if (ns < 8LL) 567 return -EINVAL; 568 use_freq = 1; 569 } 570 ts = ns_to_timespec64(ns); 571 if (rq->perout.index == 1) { 572 if (use_freq) { 573 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1; 574 tsim_mask = 0; 575 } else { 576 tsauxc_mask = TSAUXC_EN_TT1; 577 tsim_mask = TSINTR_TT1; 578 } 579 trgttiml = E1000_TRGTTIML1; 580 trgttimh = E1000_TRGTTIMH1; 581 freqout = E1000_FREQOUT1; 582 } else { 583 if (use_freq) { 584 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0; 585 tsim_mask = 0; 586 } else { 587 tsauxc_mask = TSAUXC_EN_TT0; 588 tsim_mask = TSINTR_TT0; 589 } 590 trgttiml = E1000_TRGTTIML0; 591 trgttimh = E1000_TRGTTIMH0; 592 freqout = E1000_FREQOUT0; 593 } 594 spin_lock_irqsave(&igb->tmreg_lock, flags); 595 tsauxc = rd32(E1000_TSAUXC); 596 tsim = rd32(E1000_TSIM); 597 if (rq->perout.index == 1) { 598 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1); 599 tsim &= ~TSINTR_TT1; 600 } else { 601 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0); 602 tsim &= ~TSINTR_TT0; 603 } 604 if (on) { 605 int i = rq->perout.index; 606 igb_pin_perout(igb, i, pin, use_freq); 607 igb->perout[i].start.tv_sec = rq->perout.start.sec; 608 igb->perout[i].start.tv_nsec = rq->perout.start.nsec; 609 igb->perout[i].period.tv_sec = ts.tv_sec; 610 igb->perout[i].period.tv_nsec = ts.tv_nsec; 611 wr32(trgttimh, rq->perout.start.sec); 612 wr32(trgttiml, rq->perout.start.nsec); 613 if (use_freq) 614 wr32(freqout, ns); 615 tsauxc |= tsauxc_mask; 616 tsim |= tsim_mask; 617 } 618 wr32(E1000_TSAUXC, tsauxc); 619 wr32(E1000_TSIM, tsim); 620 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 621 return 0; 622 623 case PTP_CLK_REQ_PPS: 624 spin_lock_irqsave(&igb->tmreg_lock, flags); 625 tsim = rd32(E1000_TSIM); 626 if (on) 627 tsim |= TSINTR_SYS_WRAP; 628 else 629 tsim &= ~TSINTR_SYS_WRAP; 630 igb->pps_sys_wrap_on = !!on; 631 wr32(E1000_TSIM, tsim); 632 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 633 return 0; 634 } 635 636 return -EOPNOTSUPP; 637 } 638 639 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, 640 struct ptp_clock_request *rq, int on) 641 { 642 return -EOPNOTSUPP; 643 } 644 645 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 646 enum ptp_pin_function func, unsigned int chan) 647 { 648 switch (func) { 649 case PTP_PF_NONE: 650 case PTP_PF_EXTTS: 651 case PTP_PF_PEROUT: 652 break; 653 case PTP_PF_PHYSYNC: 654 return -1; 655 } 656 return 0; 657 } 658 659 /** 660 * igb_ptp_tx_work 661 * @work: pointer to work struct 662 * 663 * This work function polls the TSYNCTXCTL valid bit to determine when a 664 * timestamp has been taken for the current stored skb. 665 **/ 666 static void igb_ptp_tx_work(struct work_struct *work) 667 { 668 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 669 ptp_tx_work); 670 struct e1000_hw *hw = &adapter->hw; 671 u32 tsynctxctl; 672 673 if (!adapter->ptp_tx_skb) 674 return; 675 676 if (time_is_before_jiffies(adapter->ptp_tx_start + 677 IGB_PTP_TX_TIMEOUT)) { 678 dev_kfree_skb_any(adapter->ptp_tx_skb); 679 adapter->ptp_tx_skb = NULL; 680 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 681 adapter->tx_hwtstamp_timeouts++; 682 /* Clear the tx valid bit in TSYNCTXCTL register to enable 683 * interrupt 684 */ 685 rd32(E1000_TXSTMPH); 686 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 687 return; 688 } 689 690 tsynctxctl = rd32(E1000_TSYNCTXCTL); 691 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 692 igb_ptp_tx_hwtstamp(adapter); 693 else 694 /* reschedule to check later */ 695 schedule_work(&adapter->ptp_tx_work); 696 } 697 698 static void igb_ptp_overflow_check(struct work_struct *work) 699 { 700 struct igb_adapter *igb = 701 container_of(work, struct igb_adapter, ptp_overflow_work.work); 702 struct timespec64 ts; 703 u64 ns; 704 705 /* Update the timecounter */ 706 ns = timecounter_read(&igb->tc); 707 708 ts = ns_to_timespec64(ns); 709 pr_debug("igb overflow check at %lld.%09lu\n", 710 (long long) ts.tv_sec, ts.tv_nsec); 711 712 schedule_delayed_work(&igb->ptp_overflow_work, 713 IGB_SYSTIM_OVERFLOW_PERIOD); 714 } 715 716 /** 717 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 718 * @adapter: private network adapter structure 719 * 720 * This watchdog task is scheduled to detect error case where hardware has 721 * dropped an Rx packet that was timestamped when the ring is full. The 722 * particular error is rare but leaves the device in a state unable to timestamp 723 * any future packets. 724 **/ 725 void igb_ptp_rx_hang(struct igb_adapter *adapter) 726 { 727 struct e1000_hw *hw = &adapter->hw; 728 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 729 unsigned long rx_event; 730 731 /* Other hardware uses per-packet timestamps */ 732 if (hw->mac.type != e1000_82576) 733 return; 734 735 /* If we don't have a valid timestamp in the registers, just update the 736 * timeout counter and exit 737 */ 738 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 739 adapter->last_rx_ptp_check = jiffies; 740 return; 741 } 742 743 /* Determine the most recent watchdog or rx_timestamp event */ 744 rx_event = adapter->last_rx_ptp_check; 745 if (time_after(adapter->last_rx_timestamp, rx_event)) 746 rx_event = adapter->last_rx_timestamp; 747 748 /* Only need to read the high RXSTMP register to clear the lock */ 749 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 750 rd32(E1000_RXSTMPH); 751 adapter->last_rx_ptp_check = jiffies; 752 adapter->rx_hwtstamp_cleared++; 753 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); 754 } 755 } 756 757 /** 758 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes 759 * @adapter: private network adapter structure 760 */ 761 void igb_ptp_tx_hang(struct igb_adapter *adapter) 762 { 763 struct e1000_hw *hw = &adapter->hw; 764 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 765 IGB_PTP_TX_TIMEOUT); 766 767 if (!adapter->ptp_tx_skb) 768 return; 769 770 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state)) 771 return; 772 773 /* If we haven't received a timestamp within the timeout, it is 774 * reasonable to assume that it will never occur, so we can unlock the 775 * timestamp bit when this occurs. 776 */ 777 if (timeout) { 778 cancel_work_sync(&adapter->ptp_tx_work); 779 dev_kfree_skb_any(adapter->ptp_tx_skb); 780 adapter->ptp_tx_skb = NULL; 781 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 782 adapter->tx_hwtstamp_timeouts++; 783 /* Clear the tx valid bit in TSYNCTXCTL register to enable 784 * interrupt 785 */ 786 rd32(E1000_TXSTMPH); 787 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); 788 } 789 } 790 791 /** 792 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 793 * @adapter: Board private structure. 794 * 795 * If we were asked to do hardware stamping and such a time stamp is 796 * available, then it must have been for this skb here because we only 797 * allow only one such packet into the queue. 798 **/ 799 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 800 { 801 struct sk_buff *skb = adapter->ptp_tx_skb; 802 struct e1000_hw *hw = &adapter->hw; 803 struct skb_shared_hwtstamps shhwtstamps; 804 u64 regval; 805 int adjust = 0; 806 807 regval = rd32(E1000_TXSTMPL); 808 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 809 810 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 811 /* adjust timestamp for the TX latency based on link speed */ 812 if (adapter->hw.mac.type == e1000_i210) { 813 switch (adapter->link_speed) { 814 case SPEED_10: 815 adjust = IGB_I210_TX_LATENCY_10; 816 break; 817 case SPEED_100: 818 adjust = IGB_I210_TX_LATENCY_100; 819 break; 820 case SPEED_1000: 821 adjust = IGB_I210_TX_LATENCY_1000; 822 break; 823 } 824 } 825 826 shhwtstamps.hwtstamp = 827 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 828 829 /* Clear the lock early before calling skb_tstamp_tx so that 830 * applications are not woken up before the lock bit is clear. We use 831 * a copy of the skb pointer to ensure other threads can't change it 832 * while we're notifying the stack. 833 */ 834 adapter->ptp_tx_skb = NULL; 835 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 836 837 /* Notify the stack and free the skb after we've unlocked */ 838 skb_tstamp_tx(skb, &shhwtstamps); 839 dev_kfree_skb_any(skb); 840 } 841 842 /** 843 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 844 * @q_vector: Pointer to interrupt specific structure 845 * @va: Pointer to address containing Rx buffer 846 * @skb: Buffer containing timestamp and packet 847 * 848 * This function is meant to retrieve a timestamp from the first buffer of an 849 * incoming frame. The value is stored in little endian format starting on 850 * byte 8. 851 **/ 852 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, 853 struct sk_buff *skb) 854 { 855 __le64 *regval = (__le64 *)va; 856 struct igb_adapter *adapter = q_vector->adapter; 857 int adjust = 0; 858 859 /* The timestamp is recorded in little endian format. 860 * DWORD: 0 1 2 3 861 * Field: Reserved Reserved SYSTIML SYSTIMH 862 */ 863 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), 864 le64_to_cpu(regval[1])); 865 866 /* adjust timestamp for the RX latency based on link speed */ 867 if (adapter->hw.mac.type == e1000_i210) { 868 switch (adapter->link_speed) { 869 case SPEED_10: 870 adjust = IGB_I210_RX_LATENCY_10; 871 break; 872 case SPEED_100: 873 adjust = IGB_I210_RX_LATENCY_100; 874 break; 875 case SPEED_1000: 876 adjust = IGB_I210_RX_LATENCY_1000; 877 break; 878 } 879 } 880 skb_hwtstamps(skb)->hwtstamp = 881 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 882 } 883 884 /** 885 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 886 * @q_vector: Pointer to interrupt specific structure 887 * @skb: Buffer containing timestamp and packet 888 * 889 * This function is meant to retrieve a timestamp from the internal registers 890 * of the adapter and store it in the skb. 891 **/ 892 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 893 struct sk_buff *skb) 894 { 895 struct igb_adapter *adapter = q_vector->adapter; 896 struct e1000_hw *hw = &adapter->hw; 897 u64 regval; 898 int adjust = 0; 899 900 /* If this bit is set, then the RX registers contain the time stamp. No 901 * other packet will be time stamped until we read these registers, so 902 * read the registers to make them available again. Because only one 903 * packet can be time stamped at a time, we know that the register 904 * values must belong to this one here and therefore we don't need to 905 * compare any of the additional attributes stored for it. 906 * 907 * If nothing went wrong, then it should have a shared tx_flags that we 908 * can turn into a skb_shared_hwtstamps. 909 */ 910 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 911 return; 912 913 regval = rd32(E1000_RXSTMPL); 914 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 915 916 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 917 918 /* adjust timestamp for the RX latency based on link speed */ 919 if (adapter->hw.mac.type == e1000_i210) { 920 switch (adapter->link_speed) { 921 case SPEED_10: 922 adjust = IGB_I210_RX_LATENCY_10; 923 break; 924 case SPEED_100: 925 adjust = IGB_I210_RX_LATENCY_100; 926 break; 927 case SPEED_1000: 928 adjust = IGB_I210_RX_LATENCY_1000; 929 break; 930 } 931 } 932 skb_hwtstamps(skb)->hwtstamp = 933 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust); 934 935 /* Update the last_rx_timestamp timer in order to enable watchdog check 936 * for error case of latched timestamp on a dropped packet. 937 */ 938 adapter->last_rx_timestamp = jiffies; 939 } 940 941 /** 942 * igb_ptp_get_ts_config - get hardware time stamping config 943 * @netdev: 944 * @ifreq: 945 * 946 * Get the hwtstamp_config settings to return to the user. Rather than attempt 947 * to deconstruct the settings from the registers, just return a shadow copy 948 * of the last known settings. 949 **/ 950 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 951 { 952 struct igb_adapter *adapter = netdev_priv(netdev); 953 struct hwtstamp_config *config = &adapter->tstamp_config; 954 955 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 956 -EFAULT : 0; 957 } 958 959 /** 960 * igb_ptp_set_timestamp_mode - setup hardware for timestamping 961 * @adapter: networking device structure 962 * @config: hwtstamp configuration 963 * 964 * Outgoing time stamping can be enabled and disabled. Play nice and 965 * disable it when requested, although it shouldn't case any overhead 966 * when no packet needs it. At most one packet in the queue may be 967 * marked for time stamping, otherwise it would be impossible to tell 968 * for sure to which packet the hardware time stamp belongs. 969 * 970 * Incoming time stamping has to be configured via the hardware 971 * filters. Not all combinations are supported, in particular event 972 * type has to be specified. Matching the kind of event packet is 973 * not supported, with the exception of "all V2 events regardless of 974 * level 2 or 4". 975 */ 976 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, 977 struct hwtstamp_config *config) 978 { 979 struct e1000_hw *hw = &adapter->hw; 980 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 981 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 982 u32 tsync_rx_cfg = 0; 983 bool is_l4 = false; 984 bool is_l2 = false; 985 u32 regval; 986 987 /* reserved for future extensions */ 988 if (config->flags) 989 return -EINVAL; 990 991 switch (config->tx_type) { 992 case HWTSTAMP_TX_OFF: 993 tsync_tx_ctl = 0; 994 case HWTSTAMP_TX_ON: 995 break; 996 default: 997 return -ERANGE; 998 } 999 1000 switch (config->rx_filter) { 1001 case HWTSTAMP_FILTER_NONE: 1002 tsync_rx_ctl = 0; 1003 break; 1004 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1005 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1006 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 1007 is_l4 = true; 1008 break; 1009 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1010 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 1011 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 1012 is_l4 = true; 1013 break; 1014 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1015 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1016 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1017 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1018 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1019 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1020 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1021 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1022 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1023 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 1024 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1025 is_l2 = true; 1026 is_l4 = true; 1027 break; 1028 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1029 case HWTSTAMP_FILTER_NTP_ALL: 1030 case HWTSTAMP_FILTER_ALL: 1031 /* 82576 cannot timestamp all packets, which it needs to do to 1032 * support both V1 Sync and Delay_Req messages 1033 */ 1034 if (hw->mac.type != e1000_82576) { 1035 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1036 config->rx_filter = HWTSTAMP_FILTER_ALL; 1037 break; 1038 } 1039 /* fall through */ 1040 default: 1041 config->rx_filter = HWTSTAMP_FILTER_NONE; 1042 return -ERANGE; 1043 } 1044 1045 if (hw->mac.type == e1000_82575) { 1046 if (tsync_rx_ctl | tsync_tx_ctl) 1047 return -EINVAL; 1048 return 0; 1049 } 1050 1051 /* Per-packet timestamping only works if all packets are 1052 * timestamped, so enable timestamping in all packets as 1053 * long as one Rx filter was configured. 1054 */ 1055 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 1056 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 1057 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 1058 config->rx_filter = HWTSTAMP_FILTER_ALL; 1059 is_l2 = true; 1060 is_l4 = true; 1061 1062 if ((hw->mac.type == e1000_i210) || 1063 (hw->mac.type == e1000_i211)) { 1064 regval = rd32(E1000_RXPBS); 1065 regval |= E1000_RXPBS_CFG_TS_EN; 1066 wr32(E1000_RXPBS, regval); 1067 } 1068 } 1069 1070 /* enable/disable TX */ 1071 regval = rd32(E1000_TSYNCTXCTL); 1072 regval &= ~E1000_TSYNCTXCTL_ENABLED; 1073 regval |= tsync_tx_ctl; 1074 wr32(E1000_TSYNCTXCTL, regval); 1075 1076 /* enable/disable RX */ 1077 regval = rd32(E1000_TSYNCRXCTL); 1078 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 1079 regval |= tsync_rx_ctl; 1080 wr32(E1000_TSYNCRXCTL, regval); 1081 1082 /* define which PTP packets are time stamped */ 1083 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 1084 1085 /* define ethertype filter for timestamped packets */ 1086 if (is_l2) 1087 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 1088 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 1089 E1000_ETQF_1588 | /* enable timestamping */ 1090 ETH_P_1588)); /* 1588 eth protocol type */ 1091 else 1092 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0); 1093 1094 /* L4 Queue Filter[3]: filter by destination port and protocol */ 1095 if (is_l4) { 1096 u32 ftqf = (IPPROTO_UDP /* UDP */ 1097 | E1000_FTQF_VF_BP /* VF not compared */ 1098 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 1099 | E1000_FTQF_MASK); /* mask all inputs */ 1100 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 1101 1102 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 1103 wr32(E1000_IMIREXT(3), 1104 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 1105 if (hw->mac.type == e1000_82576) { 1106 /* enable source port check */ 1107 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 1108 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 1109 } 1110 wr32(E1000_FTQF(3), ftqf); 1111 } else { 1112 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 1113 } 1114 wrfl(); 1115 1116 /* clear TX/RX time stamp registers, just to be sure */ 1117 regval = rd32(E1000_TXSTMPL); 1118 regval = rd32(E1000_TXSTMPH); 1119 regval = rd32(E1000_RXSTMPL); 1120 regval = rd32(E1000_RXSTMPH); 1121 1122 return 0; 1123 } 1124 1125 /** 1126 * igb_ptp_set_ts_config - set hardware time stamping config 1127 * @netdev: 1128 * @ifreq: 1129 * 1130 **/ 1131 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 1132 { 1133 struct igb_adapter *adapter = netdev_priv(netdev); 1134 struct hwtstamp_config config; 1135 int err; 1136 1137 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1138 return -EFAULT; 1139 1140 err = igb_ptp_set_timestamp_mode(adapter, &config); 1141 if (err) 1142 return err; 1143 1144 /* save these settings for future reference */ 1145 memcpy(&adapter->tstamp_config, &config, 1146 sizeof(adapter->tstamp_config)); 1147 1148 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1149 -EFAULT : 0; 1150 } 1151 1152 /** 1153 * igb_ptp_init - Initialize PTP functionality 1154 * @adapter: Board private structure 1155 * 1156 * This function is called at device probe to initialize the PTP 1157 * functionality. 1158 */ 1159 void igb_ptp_init(struct igb_adapter *adapter) 1160 { 1161 struct e1000_hw *hw = &adapter->hw; 1162 struct net_device *netdev = adapter->netdev; 1163 int i; 1164 1165 switch (hw->mac.type) { 1166 case e1000_82576: 1167 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1168 adapter->ptp_caps.owner = THIS_MODULE; 1169 adapter->ptp_caps.max_adj = 999999881; 1170 adapter->ptp_caps.n_ext_ts = 0; 1171 adapter->ptp_caps.pps = 0; 1172 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 1173 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1174 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576; 1175 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1176 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1177 adapter->cc.read = igb_ptp_read_82576; 1178 adapter->cc.mask = CYCLECOUNTER_MASK(64); 1179 adapter->cc.mult = 1; 1180 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 1181 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1182 break; 1183 case e1000_82580: 1184 case e1000_i354: 1185 case e1000_i350: 1186 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1187 adapter->ptp_caps.owner = THIS_MODULE; 1188 adapter->ptp_caps.max_adj = 62499999; 1189 adapter->ptp_caps.n_ext_ts = 0; 1190 adapter->ptp_caps.pps = 0; 1191 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1192 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 1193 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580; 1194 adapter->ptp_caps.settime64 = igb_ptp_settime_82576; 1195 adapter->ptp_caps.enable = igb_ptp_feature_enable; 1196 adapter->cc.read = igb_ptp_read_82580; 1197 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); 1198 adapter->cc.mult = 1; 1199 adapter->cc.shift = 0; 1200 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK; 1201 break; 1202 case e1000_i210: 1203 case e1000_i211: 1204 for (i = 0; i < IGB_N_SDP; i++) { 1205 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1206 1207 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1208 ppd->index = i; 1209 ppd->func = PTP_PF_NONE; 1210 } 1211 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1212 adapter->ptp_caps.owner = THIS_MODULE; 1213 adapter->ptp_caps.max_adj = 62499999; 1214 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS; 1215 adapter->ptp_caps.n_per_out = IGB_N_PEROUT; 1216 adapter->ptp_caps.n_pins = IGB_N_SDP; 1217 adapter->ptp_caps.pps = 1; 1218 adapter->ptp_caps.pin_config = adapter->sdp_config; 1219 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580; 1220 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 1221 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210; 1222 adapter->ptp_caps.settime64 = igb_ptp_settime_i210; 1223 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210; 1224 adapter->ptp_caps.verify = igb_ptp_verify_pin; 1225 break; 1226 default: 1227 adapter->ptp_clock = NULL; 1228 return; 1229 } 1230 1231 spin_lock_init(&adapter->tmreg_lock); 1232 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 1233 1234 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1235 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 1236 igb_ptp_overflow_check); 1237 1238 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1239 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1240 1241 igb_ptp_reset(adapter); 1242 1243 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1244 &adapter->pdev->dev); 1245 if (IS_ERR(adapter->ptp_clock)) { 1246 adapter->ptp_clock = NULL; 1247 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 1248 } else if (adapter->ptp_clock) { 1249 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 1250 adapter->netdev->name); 1251 adapter->ptp_flags |= IGB_PTP_ENABLED; 1252 } 1253 } 1254 1255 /** 1256 * igb_ptp_suspend - Disable PTP work items and prepare for suspend 1257 * @adapter: Board private structure 1258 * 1259 * This function stops the overflow check work and PTP Tx timestamp work, and 1260 * will prepare the device for OS suspend. 1261 */ 1262 void igb_ptp_suspend(struct igb_adapter *adapter) 1263 { 1264 if (!(adapter->ptp_flags & IGB_PTP_ENABLED)) 1265 return; 1266 1267 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1268 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 1269 1270 cancel_work_sync(&adapter->ptp_tx_work); 1271 if (adapter->ptp_tx_skb) { 1272 dev_kfree_skb_any(adapter->ptp_tx_skb); 1273 adapter->ptp_tx_skb = NULL; 1274 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 1275 } 1276 } 1277 1278 /** 1279 * igb_ptp_stop - Disable PTP device and stop the overflow check. 1280 * @adapter: Board private structure. 1281 * 1282 * This function stops the PTP support and cancels the delayed work. 1283 **/ 1284 void igb_ptp_stop(struct igb_adapter *adapter) 1285 { 1286 igb_ptp_suspend(adapter); 1287 1288 if (adapter->ptp_clock) { 1289 ptp_clock_unregister(adapter->ptp_clock); 1290 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 1291 adapter->netdev->name); 1292 adapter->ptp_flags &= ~IGB_PTP_ENABLED; 1293 } 1294 } 1295 1296 /** 1297 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 1298 * @adapter: Board private structure. 1299 * 1300 * This function handles the reset work required to re-enable the PTP device. 1301 **/ 1302 void igb_ptp_reset(struct igb_adapter *adapter) 1303 { 1304 struct e1000_hw *hw = &adapter->hw; 1305 unsigned long flags; 1306 1307 /* reset the tstamp_config */ 1308 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1309 1310 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1311 1312 switch (adapter->hw.mac.type) { 1313 case e1000_82576: 1314 /* Dial the nominal frequency. */ 1315 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 1316 break; 1317 case e1000_82580: 1318 case e1000_i354: 1319 case e1000_i350: 1320 case e1000_i210: 1321 case e1000_i211: 1322 wr32(E1000_TSAUXC, 0x0); 1323 wr32(E1000_TSSDP, 0x0); 1324 wr32(E1000_TSIM, 1325 TSYNC_INTERRUPTS | 1326 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0)); 1327 wr32(E1000_IMS, E1000_IMS_TS); 1328 break; 1329 default: 1330 /* No work to do. */ 1331 goto out; 1332 } 1333 1334 /* Re-initialize the timer. */ 1335 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 1336 struct timespec64 ts = ktime_to_timespec64(ktime_get_real()); 1337 1338 igb_ptp_write_i210(adapter, &ts); 1339 } else { 1340 timecounter_init(&adapter->tc, &adapter->cc, 1341 ktime_to_ns(ktime_get_real())); 1342 } 1343 out: 1344 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1345 1346 wrfl(); 1347 1348 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) 1349 schedule_delayed_work(&adapter->ptp_overflow_work, 1350 IGB_SYSTIM_OVERFLOW_PERIOD); 1351 } 1352