1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 struct igb_q_vector *new_q_vector; 1206 1207 new_q_vector = kzalloc(size, GFP_KERNEL); 1208 if (new_q_vector) 1209 kfree_rcu(q_vector, rcu); 1210 q_vector = new_q_vector; 1211 } else { 1212 memset(q_vector, 0, size); 1213 } 1214 if (!q_vector) 1215 return -ENOMEM; 1216 1217 /* initialize NAPI */ 1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct net_device *netdev = adapter->netdev; 1690 struct e1000_hw *hw = &adapter->hw; 1691 struct igb_ring *ring; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 ring = adapter->tx_ring[queue]; 1698 1699 /* If any of the Qav features is enabled, configure queues as SR and 1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1701 * as SP. 1702 */ 1703 if (ring->cbs_enable || ring->launchtime_enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 } else { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1709 } 1710 1711 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1712 if (ring->cbs_enable || queue == 0) { 1713 /* i210 does not allow the queue 0 to be in the Strict 1714 * Priority mode while the Qav mode is enabled, so, 1715 * instead of disabling strict priority mode, we give 1716 * queue 0 the maximum of credits possible. 1717 * 1718 * See section 8.12.19 of the i210 datasheet, "Note: 1719 * Queue0 QueueMode must be set to 1b when 1720 * TransmitMode is set to Qav." 1721 */ 1722 if (queue == 0 && !ring->cbs_enable) { 1723 /* max "linkspeed" idleslope in kbps */ 1724 ring->idleslope = 1000000; 1725 ring->hicredit = ETH_FRAME_LEN; 1726 } 1727 1728 /* Always set data transfer arbitration to credit-based 1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1730 * the queues. 1731 */ 1732 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1735 1736 /* According to i210 datasheet section 7.2.7.7, we should set 1737 * the 'idleSlope' field from TQAVCC register following the 1738 * equation: 1739 * 1740 * For 100 Mbps link speed: 1741 * 1742 * value = BW * 0x7735 * 0.2 (E1) 1743 * 1744 * For 1000Mbps link speed: 1745 * 1746 * value = BW * 0x7735 * 2 (E2) 1747 * 1748 * E1 and E2 can be merged into one equation as shown below. 1749 * Note that 'link-speed' is in Mbps. 1750 * 1751 * value = BW * 0x7735 * 2 * link-speed 1752 * -------------- (E3) 1753 * 1000 1754 * 1755 * 'BW' is the percentage bandwidth out of full link speed 1756 * which can be found with the following equation. Note that 1757 * idleSlope here is the parameter from this function which 1758 * is in kbps. 1759 * 1760 * BW = idleSlope 1761 * ----------------- (E4) 1762 * link-speed * 1000 1763 * 1764 * That said, we can come up with a generic equation to 1765 * calculate the value we should set it TQAVCC register by 1766 * replacing 'BW' in E3 by E4. The resulting equation is: 1767 * 1768 * value = idleSlope * 0x7735 * 2 * link-speed 1769 * ----------------- -------------- (E5) 1770 * link-speed * 1000 1000 1771 * 1772 * 'link-speed' is present in both sides of the fraction so 1773 * it is canceled out. The final equation is the following: 1774 * 1775 * value = idleSlope * 61034 1776 * ----------------- (E6) 1777 * 1000000 1778 * 1779 * NOTE: For i210, given the above, we can see that idleslope 1780 * is represented in 16.38431 kbps units by the value at 1781 * the TQAVCC register (1Gbps / 61034), which reduces 1782 * the granularity for idleslope increments. 1783 * For instance, if you want to configure a 2576kbps 1784 * idleslope, the value to be written on the register 1785 * would have to be 157.23. If rounded down, you end 1786 * up with less bandwidth available than originally 1787 * required (~2572 kbps). If rounded up, you end up 1788 * with a higher bandwidth (~2589 kbps). Below the 1789 * approach we take is to always round up the 1790 * calculated value, so the resulting bandwidth might 1791 * be slightly higher for some configurations. 1792 */ 1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1794 1795 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1797 tqavcc |= value; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 wr32(E1000_I210_TQAVHC(queue), 1801 0x80000000 + ring->hicredit * 0x7735); 1802 } else { 1803 1804 /* Set idleSlope to zero. */ 1805 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1808 1809 /* Set hiCredit to zero. */ 1810 wr32(E1000_I210_TQAVHC(queue), 0); 1811 1812 /* If CBS is not enabled for any queues anymore, then return to 1813 * the default state of Data Transmission Arbitration on 1814 * TQAVCTRL. 1815 */ 1816 if (!is_any_cbs_enabled(adapter)) { 1817 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* If LaunchTime is enabled, set DataTranTIM. */ 1824 if (ring->launchtime_enable) { 1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1826 * for any of the SR queues, and configure fetchtime delta. 1827 * XXX NOTE: 1828 * - LaunchTime will be enabled for all SR queues. 1829 * - A fixed offset can be added relative to the launch 1830 * time of all packets if configured at reg LAUNCH_OS0. 1831 * We are keeping it as 0 for now (default value). 1832 */ 1833 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1835 E1000_TQAVCTRL_FETCHTIME_DELTA; 1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1837 } else { 1838 /* If Launchtime is not enabled for any SR queues anymore, 1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1840 * effectively disabling Launchtime. 1841 */ 1842 if (!is_any_txtime_enabled(adapter)) { 1843 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1847 } 1848 } 1849 1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1851 * CBS are not configurable by software so we don't do any 'controller 1852 * configuration' in respect to these parameters. 1853 */ 1854 1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1856 ring->cbs_enable ? "enabled" : "disabled", 1857 ring->launchtime_enable ? "enabled" : "disabled", 1858 queue, 1859 ring->idleslope, ring->sendslope, 1860 ring->hicredit, ring->locredit); 1861 } 1862 1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1864 bool enable) 1865 { 1866 struct igb_ring *ring; 1867 1868 if (queue < 0 || queue > adapter->num_tx_queues) 1869 return -EINVAL; 1870 1871 ring = adapter->tx_ring[queue]; 1872 ring->launchtime_enable = enable; 1873 1874 return 0; 1875 } 1876 1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1878 bool enable, int idleslope, int sendslope, 1879 int hicredit, int locredit) 1880 { 1881 struct igb_ring *ring; 1882 1883 if (queue < 0 || queue > adapter->num_tx_queues) 1884 return -EINVAL; 1885 1886 ring = adapter->tx_ring[queue]; 1887 1888 ring->cbs_enable = enable; 1889 ring->idleslope = idleslope; 1890 ring->sendslope = sendslope; 1891 ring->hicredit = hicredit; 1892 ring->locredit = locredit; 1893 1894 return 0; 1895 } 1896 1897 /** 1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1899 * @adapter: pointer to adapter struct 1900 * 1901 * Configure TQAVCTRL register switching the controller's Tx mode 1902 * if FQTSS mode is enabled or disabled. Additionally, will issue 1903 * a call to igb_config_tx_modes() per queue so any previously saved 1904 * Tx parameters are applied. 1905 **/ 1906 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1907 { 1908 struct net_device *netdev = adapter->netdev; 1909 struct e1000_hw *hw = &adapter->hw; 1910 u32 val; 1911 1912 /* Only i210 controller supports changing the transmission mode. */ 1913 if (hw->mac.type != e1000_i210) 1914 return; 1915 1916 if (is_fqtss_enabled(adapter)) { 1917 int i, max_queue; 1918 1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1921 * so SP queues wait for SR ones. 1922 */ 1923 val = rd32(E1000_I210_TQAVCTRL); 1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1926 wr32(E1000_I210_TQAVCTRL, val); 1927 1928 /* Configure Tx and Rx packet buffers sizes as described in 1929 * i210 datasheet section 7.2.7.7. 1930 */ 1931 val = rd32(E1000_TXPBS); 1932 val &= ~I210_TXPBSIZE_MASK; 1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1935 wr32(E1000_TXPBS, val); 1936 1937 val = rd32(E1000_RXPBS); 1938 val &= ~I210_RXPBSIZE_MASK; 1939 val |= I210_RXPBSIZE_PB_30KB; 1940 wr32(E1000_RXPBS, val); 1941 1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1943 * register should not exceed the buffer size programmed in 1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1945 * so according to the datasheet we should set MAX_TPKT_SIZE to 1946 * 4kB / 64. 1947 * 1948 * However, when we do so, no frame from queue 2 and 3 are 1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1950 * or _equal_ to the buffer size programmed in TXPBS. For this 1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1952 */ 1953 val = (4096 - 1) / 64; 1954 wr32(E1000_I210_DTXMXPKTSZ, val); 1955 1956 /* Since FQTSS mode is enabled, apply any CBS configuration 1957 * previously set. If no previous CBS configuration has been 1958 * done, then the initial configuration is applied, which means 1959 * CBS is disabled. 1960 */ 1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1963 1964 for (i = 0; i < max_queue; i++) { 1965 igb_config_tx_modes(adapter, i); 1966 } 1967 } else { 1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1971 1972 val = rd32(E1000_I210_TQAVCTRL); 1973 /* According to Section 8.12.21, the other flags we've set when 1974 * enabling FQTSS are not relevant when disabling FQTSS so we 1975 * don't set they here. 1976 */ 1977 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1978 wr32(E1000_I210_TQAVCTRL, val); 1979 } 1980 1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1982 "enabled" : "disabled"); 1983 } 1984 1985 /** 1986 * igb_configure - configure the hardware for RX and TX 1987 * @adapter: private board structure 1988 **/ 1989 static void igb_configure(struct igb_adapter *adapter) 1990 { 1991 struct net_device *netdev = adapter->netdev; 1992 int i; 1993 1994 igb_get_hw_control(adapter); 1995 igb_set_rx_mode(netdev); 1996 igb_setup_tx_mode(adapter); 1997 1998 igb_restore_vlan(adapter); 1999 2000 igb_setup_tctl(adapter); 2001 igb_setup_mrqc(adapter); 2002 igb_setup_rctl(adapter); 2003 2004 igb_nfc_filter_restore(adapter); 2005 igb_configure_tx(adapter); 2006 igb_configure_rx(adapter); 2007 2008 igb_rx_fifo_flush_82575(&adapter->hw); 2009 2010 /* call igb_desc_unused which always leaves 2011 * at least 1 descriptor unused to make sure 2012 * next_to_use != next_to_clean 2013 */ 2014 for (i = 0; i < adapter->num_rx_queues; i++) { 2015 struct igb_ring *ring = adapter->rx_ring[i]; 2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2017 } 2018 } 2019 2020 /** 2021 * igb_power_up_link - Power up the phy/serdes link 2022 * @adapter: address of board private structure 2023 **/ 2024 void igb_power_up_link(struct igb_adapter *adapter) 2025 { 2026 igb_reset_phy(&adapter->hw); 2027 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_up_phy_copper(&adapter->hw); 2030 else 2031 igb_power_up_serdes_link_82575(&adapter->hw); 2032 2033 igb_setup_link(&adapter->hw); 2034 } 2035 2036 /** 2037 * igb_power_down_link - Power down the phy/serdes link 2038 * @adapter: address of board private structure 2039 */ 2040 static void igb_power_down_link(struct igb_adapter *adapter) 2041 { 2042 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2043 igb_power_down_phy_copper_82575(&adapter->hw); 2044 else 2045 igb_shutdown_serdes_link_82575(&adapter->hw); 2046 } 2047 2048 /** 2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2050 * @adapter: address of the board private structure 2051 **/ 2052 static void igb_check_swap_media(struct igb_adapter *adapter) 2053 { 2054 struct e1000_hw *hw = &adapter->hw; 2055 u32 ctrl_ext, connsw; 2056 bool swap_now = false; 2057 2058 ctrl_ext = rd32(E1000_CTRL_EXT); 2059 connsw = rd32(E1000_CONNSW); 2060 2061 /* need to live swap if current media is copper and we have fiber/serdes 2062 * to go to. 2063 */ 2064 2065 if ((hw->phy.media_type == e1000_media_type_copper) && 2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2067 swap_now = true; 2068 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2069 !(connsw & E1000_CONNSW_SERDESD)) { 2070 /* copper signal takes time to appear */ 2071 if (adapter->copper_tries < 4) { 2072 adapter->copper_tries++; 2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2074 wr32(E1000_CONNSW, connsw); 2075 return; 2076 } else { 2077 adapter->copper_tries = 0; 2078 if ((connsw & E1000_CONNSW_PHYSD) && 2079 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2080 swap_now = true; 2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2082 wr32(E1000_CONNSW, connsw); 2083 } 2084 } 2085 } 2086 2087 if (!swap_now) 2088 return; 2089 2090 switch (hw->phy.media_type) { 2091 case e1000_media_type_copper: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to fiber/serdes\n"); 2094 ctrl_ext |= 2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 adapter->copper_tries = 0; 2098 break; 2099 case e1000_media_type_internal_serdes: 2100 case e1000_media_type_fiber: 2101 netdev_info(adapter->netdev, 2102 "MAS: changing media to copper\n"); 2103 ctrl_ext &= 2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2105 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2106 break; 2107 default: 2108 /* shouldn't get here during regular operation */ 2109 netdev_err(adapter->netdev, 2110 "AMS: Invalid media type found, returning\n"); 2111 break; 2112 } 2113 wr32(E1000_CTRL_EXT, ctrl_ext); 2114 } 2115 2116 /** 2117 * igb_up - Open the interface and prepare it to handle traffic 2118 * @adapter: board private structure 2119 **/ 2120 int igb_up(struct igb_adapter *adapter) 2121 { 2122 struct e1000_hw *hw = &adapter->hw; 2123 int i; 2124 2125 /* hardware has been reset, we need to reload some things */ 2126 igb_configure(adapter); 2127 2128 clear_bit(__IGB_DOWN, &adapter->state); 2129 2130 for (i = 0; i < adapter->num_q_vectors; i++) 2131 napi_enable(&(adapter->q_vector[i]->napi)); 2132 2133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2134 igb_configure_msix(adapter); 2135 else 2136 igb_assign_vector(adapter->q_vector[0], 0); 2137 2138 /* Clear any pending interrupts. */ 2139 rd32(E1000_TSICR); 2140 rd32(E1000_ICR); 2141 igb_irq_enable(adapter); 2142 2143 /* notify VFs that reset has been completed */ 2144 if (adapter->vfs_allocated_count) { 2145 u32 reg_data = rd32(E1000_CTRL_EXT); 2146 2147 reg_data |= E1000_CTRL_EXT_PFRSTD; 2148 wr32(E1000_CTRL_EXT, reg_data); 2149 } 2150 2151 netif_tx_start_all_queues(adapter->netdev); 2152 2153 /* start the watchdog. */ 2154 hw->mac.get_link_status = 1; 2155 schedule_work(&adapter->watchdog_task); 2156 2157 if ((adapter->flags & IGB_FLAG_EEE) && 2158 (!hw->dev_spec._82575.eee_disable)) 2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2160 2161 return 0; 2162 } 2163 2164 void igb_down(struct igb_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 struct e1000_hw *hw = &adapter->hw; 2168 u32 tctl, rctl; 2169 int i; 2170 2171 /* signal that we're down so the interrupt handler does not 2172 * reschedule our watchdog timer 2173 */ 2174 set_bit(__IGB_DOWN, &adapter->state); 2175 2176 /* disable receives in the hardware */ 2177 rctl = rd32(E1000_RCTL); 2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2179 /* flush and sleep below */ 2180 2181 igb_nfc_filter_exit(adapter); 2182 2183 netif_carrier_off(netdev); 2184 netif_tx_stop_all_queues(netdev); 2185 2186 /* disable transmits in the hardware */ 2187 tctl = rd32(E1000_TCTL); 2188 tctl &= ~E1000_TCTL_EN; 2189 wr32(E1000_TCTL, tctl); 2190 /* flush both disables and wait for them to finish */ 2191 wrfl(); 2192 usleep_range(10000, 11000); 2193 2194 igb_irq_disable(adapter); 2195 2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2197 2198 for (i = 0; i < adapter->num_q_vectors; i++) { 2199 if (adapter->q_vector[i]) { 2200 napi_synchronize(&adapter->q_vector[i]->napi); 2201 napi_disable(&adapter->q_vector[i]->napi); 2202 } 2203 } 2204 2205 del_timer_sync(&adapter->watchdog_timer); 2206 del_timer_sync(&adapter->phy_info_timer); 2207 2208 /* record the stats before reset*/ 2209 spin_lock(&adapter->stats64_lock); 2210 igb_update_stats(adapter); 2211 spin_unlock(&adapter->stats64_lock); 2212 2213 adapter->link_speed = 0; 2214 adapter->link_duplex = 0; 2215 2216 if (!pci_channel_offline(adapter->pdev)) 2217 igb_reset(adapter); 2218 2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2221 2222 igb_clean_all_tx_rings(adapter); 2223 igb_clean_all_rx_rings(adapter); 2224 #ifdef CONFIG_IGB_DCA 2225 2226 /* since we reset the hardware DCA settings were cleared */ 2227 igb_setup_dca(adapter); 2228 #endif 2229 } 2230 2231 void igb_reinit_locked(struct igb_adapter *adapter) 2232 { 2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2234 usleep_range(1000, 2000); 2235 igb_down(adapter); 2236 igb_up(adapter); 2237 clear_bit(__IGB_RESETTING, &adapter->state); 2238 } 2239 2240 /** igb_enable_mas - Media Autosense re-enable after swap 2241 * 2242 * @adapter: adapter struct 2243 **/ 2244 static void igb_enable_mas(struct igb_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 connsw = rd32(E1000_CONNSW); 2248 2249 /* configure for SerDes media detect */ 2250 if ((hw->phy.media_type == e1000_media_type_copper) && 2251 (!(connsw & E1000_CONNSW_SERDESD))) { 2252 connsw |= E1000_CONNSW_ENRGSRC; 2253 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2254 wr32(E1000_CONNSW, connsw); 2255 wrfl(); 2256 } 2257 } 2258 2259 void igb_reset(struct igb_adapter *adapter) 2260 { 2261 struct pci_dev *pdev = adapter->pdev; 2262 struct e1000_hw *hw = &adapter->hw; 2263 struct e1000_mac_info *mac = &hw->mac; 2264 struct e1000_fc_info *fc = &hw->fc; 2265 u32 pba, hwm; 2266 2267 /* Repartition Pba for greater than 9k mtu 2268 * To take effect CTRL.RST is required. 2269 */ 2270 switch (mac->type) { 2271 case e1000_i350: 2272 case e1000_i354: 2273 case e1000_82580: 2274 pba = rd32(E1000_RXPBS); 2275 pba = igb_rxpbs_adjust_82580(pba); 2276 break; 2277 case e1000_82576: 2278 pba = rd32(E1000_RXPBS); 2279 pba &= E1000_RXPBS_SIZE_MASK_82576; 2280 break; 2281 case e1000_82575: 2282 case e1000_i210: 2283 case e1000_i211: 2284 default: 2285 pba = E1000_PBA_34K; 2286 break; 2287 } 2288 2289 if (mac->type == e1000_82575) { 2290 u32 min_rx_space, min_tx_space, needed_tx_space; 2291 2292 /* write Rx PBA so that hardware can report correct Tx PBA */ 2293 wr32(E1000_PBA, pba); 2294 2295 /* To maintain wire speed transmits, the Tx FIFO should be 2296 * large enough to accommodate two full transmit packets, 2297 * rounded up to the next 1KB and expressed in KB. Likewise, 2298 * the Rx FIFO should be large enough to accommodate at least 2299 * one full receive packet and is similarly rounded up and 2300 * expressed in KB. 2301 */ 2302 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2303 2304 /* The Tx FIFO also stores 16 bytes of information about the Tx 2305 * but don't include Ethernet FCS because hardware appends it. 2306 * We only need to round down to the nearest 512 byte block 2307 * count since the value we care about is 2 frames, not 1. 2308 */ 2309 min_tx_space = adapter->max_frame_size; 2310 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2311 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2312 2313 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2314 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2315 2316 /* If current Tx allocation is less than the min Tx FIFO size, 2317 * and the min Tx FIFO size is less than the current Rx FIFO 2318 * allocation, take space away from current Rx allocation. 2319 */ 2320 if (needed_tx_space < pba) { 2321 pba -= needed_tx_space; 2322 2323 /* if short on Rx space, Rx wins and must trump Tx 2324 * adjustment 2325 */ 2326 if (pba < min_rx_space) 2327 pba = min_rx_space; 2328 } 2329 2330 /* adjust PBA for jumbo frames */ 2331 wr32(E1000_PBA, pba); 2332 } 2333 2334 /* flow control settings 2335 * The high water mark must be low enough to fit one full frame 2336 * after transmitting the pause frame. As such we must have enough 2337 * space to allow for us to complete our current transmit and then 2338 * receive the frame that is in progress from the link partner. 2339 * Set it to: 2340 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2341 */ 2342 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2343 2344 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2345 fc->low_water = fc->high_water - 16; 2346 fc->pause_time = 0xFFFF; 2347 fc->send_xon = 1; 2348 fc->current_mode = fc->requested_mode; 2349 2350 /* disable receive for all VFs and wait one second */ 2351 if (adapter->vfs_allocated_count) { 2352 int i; 2353 2354 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2355 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2356 2357 /* ping all the active vfs to let them know we are going down */ 2358 igb_ping_all_vfs(adapter); 2359 2360 /* disable transmits and receives */ 2361 wr32(E1000_VFRE, 0); 2362 wr32(E1000_VFTE, 0); 2363 } 2364 2365 /* Allow time for pending master requests to run */ 2366 hw->mac.ops.reset_hw(hw); 2367 wr32(E1000_WUC, 0); 2368 2369 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2370 /* need to resetup here after media swap */ 2371 adapter->ei.get_invariants(hw); 2372 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2373 } 2374 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2375 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2376 igb_enable_mas(adapter); 2377 } 2378 if (hw->mac.ops.init_hw(hw)) 2379 dev_err(&pdev->dev, "Hardware Error\n"); 2380 2381 /* RAR registers were cleared during init_hw, clear mac table */ 2382 igb_flush_mac_table(adapter); 2383 __dev_uc_unsync(adapter->netdev, NULL); 2384 2385 /* Recover default RAR entry */ 2386 igb_set_default_mac_filter(adapter); 2387 2388 /* Flow control settings reset on hardware reset, so guarantee flow 2389 * control is off when forcing speed. 2390 */ 2391 if (!hw->mac.autoneg) 2392 igb_force_mac_fc(hw); 2393 2394 igb_init_dmac(adapter, pba); 2395 #ifdef CONFIG_IGB_HWMON 2396 /* Re-initialize the thermal sensor on i350 devices. */ 2397 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2398 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2399 /* If present, re-initialize the external thermal sensor 2400 * interface. 2401 */ 2402 if (adapter->ets) 2403 mac->ops.init_thermal_sensor_thresh(hw); 2404 } 2405 } 2406 #endif 2407 /* Re-establish EEE setting */ 2408 if (hw->phy.media_type == e1000_media_type_copper) { 2409 switch (mac->type) { 2410 case e1000_i350: 2411 case e1000_i210: 2412 case e1000_i211: 2413 igb_set_eee_i350(hw, true, true); 2414 break; 2415 case e1000_i354: 2416 igb_set_eee_i354(hw, true, true); 2417 break; 2418 default: 2419 break; 2420 } 2421 } 2422 if (!netif_running(adapter->netdev)) 2423 igb_power_down_link(adapter); 2424 2425 igb_update_mng_vlan(adapter); 2426 2427 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2428 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2429 2430 /* Re-enable PTP, where applicable. */ 2431 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2432 igb_ptp_reset(adapter); 2433 2434 igb_get_phy_info(hw); 2435 } 2436 2437 static netdev_features_t igb_fix_features(struct net_device *netdev, 2438 netdev_features_t features) 2439 { 2440 /* Since there is no support for separate Rx/Tx vlan accel 2441 * enable/disable make sure Tx flag is always in same state as Rx. 2442 */ 2443 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2444 features |= NETIF_F_HW_VLAN_CTAG_TX; 2445 else 2446 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2447 2448 return features; 2449 } 2450 2451 static int igb_set_features(struct net_device *netdev, 2452 netdev_features_t features) 2453 { 2454 netdev_features_t changed = netdev->features ^ features; 2455 struct igb_adapter *adapter = netdev_priv(netdev); 2456 2457 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2458 igb_vlan_mode(netdev, features); 2459 2460 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2461 return 0; 2462 2463 if (!(features & NETIF_F_NTUPLE)) { 2464 struct hlist_node *node2; 2465 struct igb_nfc_filter *rule; 2466 2467 spin_lock(&adapter->nfc_lock); 2468 hlist_for_each_entry_safe(rule, node2, 2469 &adapter->nfc_filter_list, nfc_node) { 2470 igb_erase_filter(adapter, rule); 2471 hlist_del(&rule->nfc_node); 2472 kfree(rule); 2473 } 2474 spin_unlock(&adapter->nfc_lock); 2475 adapter->nfc_filter_count = 0; 2476 } 2477 2478 netdev->features = features; 2479 2480 if (netif_running(netdev)) 2481 igb_reinit_locked(adapter); 2482 else 2483 igb_reset(adapter); 2484 2485 return 1; 2486 } 2487 2488 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2489 struct net_device *dev, 2490 const unsigned char *addr, u16 vid, 2491 u16 flags, 2492 struct netlink_ext_ack *extack) 2493 { 2494 /* guarantee we can provide a unique filter for the unicast address */ 2495 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2496 struct igb_adapter *adapter = netdev_priv(dev); 2497 int vfn = adapter->vfs_allocated_count; 2498 2499 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2500 return -ENOMEM; 2501 } 2502 2503 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2504 } 2505 2506 #define IGB_MAX_MAC_HDR_LEN 127 2507 #define IGB_MAX_NETWORK_HDR_LEN 511 2508 2509 static netdev_features_t 2510 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2511 netdev_features_t features) 2512 { 2513 unsigned int network_hdr_len, mac_hdr_len; 2514 2515 /* Make certain the headers can be described by a context descriptor */ 2516 mac_hdr_len = skb_network_header(skb) - skb->data; 2517 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_HW_VLAN_CTAG_TX | 2522 NETIF_F_TSO | 2523 NETIF_F_TSO6); 2524 2525 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2526 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2527 return features & ~(NETIF_F_HW_CSUM | 2528 NETIF_F_SCTP_CRC | 2529 NETIF_F_GSO_UDP_L4 | 2530 NETIF_F_TSO | 2531 NETIF_F_TSO6); 2532 2533 /* We can only support IPV4 TSO in tunnels if we can mangle the 2534 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2535 */ 2536 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2537 features &= ~NETIF_F_TSO; 2538 2539 return features; 2540 } 2541 2542 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2543 { 2544 if (!is_fqtss_enabled(adapter)) { 2545 enable_fqtss(adapter, true); 2546 return; 2547 } 2548 2549 igb_config_tx_modes(adapter, queue); 2550 2551 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2552 enable_fqtss(adapter, false); 2553 } 2554 2555 static int igb_offload_cbs(struct igb_adapter *adapter, 2556 struct tc_cbs_qopt_offload *qopt) 2557 { 2558 struct e1000_hw *hw = &adapter->hw; 2559 int err; 2560 2561 /* CBS offloading is only supported by i210 controller. */ 2562 if (hw->mac.type != e1000_i210) 2563 return -EOPNOTSUPP; 2564 2565 /* CBS offloading is only supported by queue 0 and queue 1. */ 2566 if (qopt->queue < 0 || qopt->queue > 1) 2567 return -EINVAL; 2568 2569 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2570 qopt->idleslope, qopt->sendslope, 2571 qopt->hicredit, qopt->locredit); 2572 if (err) 2573 return err; 2574 2575 igb_offload_apply(adapter, qopt->queue); 2576 2577 return 0; 2578 } 2579 2580 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2581 #define VLAN_PRIO_FULL_MASK (0x07) 2582 2583 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2584 struct flow_cls_offload *f, 2585 int traffic_class, 2586 struct igb_nfc_filter *input) 2587 { 2588 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2589 struct flow_dissector *dissector = rule->match.dissector; 2590 struct netlink_ext_ack *extack = f->common.extack; 2591 2592 if (dissector->used_keys & 2593 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2594 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2595 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2596 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2597 NL_SET_ERR_MSG_MOD(extack, 2598 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2599 return -EOPNOTSUPP; 2600 } 2601 2602 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2603 struct flow_match_eth_addrs match; 2604 2605 flow_rule_match_eth_addrs(rule, &match); 2606 if (!is_zero_ether_addr(match.mask->dst)) { 2607 if (!is_broadcast_ether_addr(match.mask->dst)) { 2608 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2609 return -EINVAL; 2610 } 2611 2612 input->filter.match_flags |= 2613 IGB_FILTER_FLAG_DST_MAC_ADDR; 2614 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2615 } 2616 2617 if (!is_zero_ether_addr(match.mask->src)) { 2618 if (!is_broadcast_ether_addr(match.mask->src)) { 2619 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2620 return -EINVAL; 2621 } 2622 2623 input->filter.match_flags |= 2624 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2625 ether_addr_copy(input->filter.src_addr, match.key->src); 2626 } 2627 } 2628 2629 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2630 struct flow_match_basic match; 2631 2632 flow_rule_match_basic(rule, &match); 2633 if (match.mask->n_proto) { 2634 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2635 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2636 return -EINVAL; 2637 } 2638 2639 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2640 input->filter.etype = match.key->n_proto; 2641 } 2642 } 2643 2644 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2645 struct flow_match_vlan match; 2646 2647 flow_rule_match_vlan(rule, &match); 2648 if (match.mask->vlan_priority) { 2649 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2650 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2651 return -EINVAL; 2652 } 2653 2654 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2655 input->filter.vlan_tci = 2656 (__force __be16)match.key->vlan_priority; 2657 } 2658 } 2659 2660 input->action = traffic_class; 2661 input->cookie = f->cookie; 2662 2663 return 0; 2664 } 2665 2666 static int igb_configure_clsflower(struct igb_adapter *adapter, 2667 struct flow_cls_offload *cls_flower) 2668 { 2669 struct netlink_ext_ack *extack = cls_flower->common.extack; 2670 struct igb_nfc_filter *filter, *f; 2671 int err, tc; 2672 2673 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2674 if (tc < 0) { 2675 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2676 return -EINVAL; 2677 } 2678 2679 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2680 if (!filter) 2681 return -ENOMEM; 2682 2683 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2684 if (err < 0) 2685 goto err_parse; 2686 2687 spin_lock(&adapter->nfc_lock); 2688 2689 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2690 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2691 err = -EEXIST; 2692 NL_SET_ERR_MSG_MOD(extack, 2693 "This filter is already set in ethtool"); 2694 goto err_locked; 2695 } 2696 } 2697 2698 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2699 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2700 err = -EEXIST; 2701 NL_SET_ERR_MSG_MOD(extack, 2702 "This filter is already set in cls_flower"); 2703 goto err_locked; 2704 } 2705 } 2706 2707 err = igb_add_filter(adapter, filter); 2708 if (err < 0) { 2709 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2710 goto err_locked; 2711 } 2712 2713 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2714 2715 spin_unlock(&adapter->nfc_lock); 2716 2717 return 0; 2718 2719 err_locked: 2720 spin_unlock(&adapter->nfc_lock); 2721 2722 err_parse: 2723 kfree(filter); 2724 2725 return err; 2726 } 2727 2728 static int igb_delete_clsflower(struct igb_adapter *adapter, 2729 struct flow_cls_offload *cls_flower) 2730 { 2731 struct igb_nfc_filter *filter; 2732 int err; 2733 2734 spin_lock(&adapter->nfc_lock); 2735 2736 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2737 if (filter->cookie == cls_flower->cookie) 2738 break; 2739 2740 if (!filter) { 2741 err = -ENOENT; 2742 goto out; 2743 } 2744 2745 err = igb_erase_filter(adapter, filter); 2746 if (err < 0) 2747 goto out; 2748 2749 hlist_del(&filter->nfc_node); 2750 kfree(filter); 2751 2752 out: 2753 spin_unlock(&adapter->nfc_lock); 2754 2755 return err; 2756 } 2757 2758 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2759 struct flow_cls_offload *cls_flower) 2760 { 2761 switch (cls_flower->command) { 2762 case FLOW_CLS_REPLACE: 2763 return igb_configure_clsflower(adapter, cls_flower); 2764 case FLOW_CLS_DESTROY: 2765 return igb_delete_clsflower(adapter, cls_flower); 2766 case FLOW_CLS_STATS: 2767 return -EOPNOTSUPP; 2768 default: 2769 return -EOPNOTSUPP; 2770 } 2771 } 2772 2773 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2774 void *cb_priv) 2775 { 2776 struct igb_adapter *adapter = cb_priv; 2777 2778 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2779 return -EOPNOTSUPP; 2780 2781 switch (type) { 2782 case TC_SETUP_CLSFLOWER: 2783 return igb_setup_tc_cls_flower(adapter, type_data); 2784 2785 default: 2786 return -EOPNOTSUPP; 2787 } 2788 } 2789 2790 static int igb_offload_txtime(struct igb_adapter *adapter, 2791 struct tc_etf_qopt_offload *qopt) 2792 { 2793 struct e1000_hw *hw = &adapter->hw; 2794 int err; 2795 2796 /* Launchtime offloading is only supported by i210 controller. */ 2797 if (hw->mac.type != e1000_i210) 2798 return -EOPNOTSUPP; 2799 2800 /* Launchtime offloading is only supported by queues 0 and 1. */ 2801 if (qopt->queue < 0 || qopt->queue > 1) 2802 return -EINVAL; 2803 2804 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2805 if (err) 2806 return err; 2807 2808 igb_offload_apply(adapter, qopt->queue); 2809 2810 return 0; 2811 } 2812 2813 static LIST_HEAD(igb_block_cb_list); 2814 2815 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2816 void *type_data) 2817 { 2818 struct igb_adapter *adapter = netdev_priv(dev); 2819 2820 switch (type) { 2821 case TC_SETUP_QDISC_CBS: 2822 return igb_offload_cbs(adapter, type_data); 2823 case TC_SETUP_BLOCK: 2824 return flow_block_cb_setup_simple(type_data, 2825 &igb_block_cb_list, 2826 igb_setup_tc_block_cb, 2827 adapter, adapter, true); 2828 2829 case TC_SETUP_QDISC_ETF: 2830 return igb_offload_txtime(adapter, type_data); 2831 2832 default: 2833 return -EOPNOTSUPP; 2834 } 2835 } 2836 2837 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2838 { 2839 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2840 struct igb_adapter *adapter = netdev_priv(dev); 2841 struct bpf_prog *prog = bpf->prog, *old_prog; 2842 bool running = netif_running(dev); 2843 bool need_reset; 2844 2845 /* verify igb ring attributes are sufficient for XDP */ 2846 for (i = 0; i < adapter->num_rx_queues; i++) { 2847 struct igb_ring *ring = adapter->rx_ring[i]; 2848 2849 if (frame_size > igb_rx_bufsz(ring)) { 2850 NL_SET_ERR_MSG_MOD(bpf->extack, 2851 "The RX buffer size is too small for the frame size"); 2852 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2853 igb_rx_bufsz(ring), frame_size); 2854 return -EINVAL; 2855 } 2856 } 2857 2858 old_prog = xchg(&adapter->xdp_prog, prog); 2859 need_reset = (!!prog != !!old_prog); 2860 2861 /* device is up and bpf is added/removed, must setup the RX queues */ 2862 if (need_reset && running) { 2863 igb_close(dev); 2864 } else { 2865 for (i = 0; i < adapter->num_rx_queues; i++) 2866 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2867 adapter->xdp_prog); 2868 } 2869 2870 if (old_prog) 2871 bpf_prog_put(old_prog); 2872 2873 /* bpf is just replaced, RXQ and MTU are already setup */ 2874 if (!need_reset) 2875 return 0; 2876 2877 if (running) 2878 igb_open(dev); 2879 2880 return 0; 2881 } 2882 2883 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2884 { 2885 switch (xdp->command) { 2886 case XDP_SETUP_PROG: 2887 return igb_xdp_setup(dev, xdp); 2888 default: 2889 return -EINVAL; 2890 } 2891 } 2892 2893 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2894 { 2895 /* Force memory writes to complete before letting h/w know there 2896 * are new descriptors to fetch. 2897 */ 2898 wmb(); 2899 writel(ring->next_to_use, ring->tail); 2900 } 2901 2902 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2903 { 2904 unsigned int r_idx = smp_processor_id(); 2905 2906 if (r_idx >= adapter->num_tx_queues) 2907 r_idx = r_idx % adapter->num_tx_queues; 2908 2909 return adapter->tx_ring[r_idx]; 2910 } 2911 2912 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2913 { 2914 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2915 int cpu = smp_processor_id(); 2916 struct igb_ring *tx_ring; 2917 struct netdev_queue *nq; 2918 u32 ret; 2919 2920 if (unlikely(!xdpf)) 2921 return IGB_XDP_CONSUMED; 2922 2923 /* During program transitions its possible adapter->xdp_prog is assigned 2924 * but ring has not been configured yet. In this case simply abort xmit. 2925 */ 2926 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2927 if (unlikely(!tx_ring)) 2928 return IGB_XDP_CONSUMED; 2929 2930 nq = txring_txq(tx_ring); 2931 __netif_tx_lock(nq, cpu); 2932 /* Avoid transmit queue timeout since we share it with the slow path */ 2933 txq_trans_cond_update(nq); 2934 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2935 __netif_tx_unlock(nq); 2936 2937 return ret; 2938 } 2939 2940 static int igb_xdp_xmit(struct net_device *dev, int n, 2941 struct xdp_frame **frames, u32 flags) 2942 { 2943 struct igb_adapter *adapter = netdev_priv(dev); 2944 int cpu = smp_processor_id(); 2945 struct igb_ring *tx_ring; 2946 struct netdev_queue *nq; 2947 int nxmit = 0; 2948 int i; 2949 2950 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2951 return -ENETDOWN; 2952 2953 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2954 return -EINVAL; 2955 2956 /* During program transitions its possible adapter->xdp_prog is assigned 2957 * but ring has not been configured yet. In this case simply abort xmit. 2958 */ 2959 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2960 if (unlikely(!tx_ring)) 2961 return -ENXIO; 2962 2963 nq = txring_txq(tx_ring); 2964 __netif_tx_lock(nq, cpu); 2965 2966 /* Avoid transmit queue timeout since we share it with the slow path */ 2967 txq_trans_cond_update(nq); 2968 2969 for (i = 0; i < n; i++) { 2970 struct xdp_frame *xdpf = frames[i]; 2971 int err; 2972 2973 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2974 if (err != IGB_XDP_TX) 2975 break; 2976 nxmit++; 2977 } 2978 2979 __netif_tx_unlock(nq); 2980 2981 if (unlikely(flags & XDP_XMIT_FLUSH)) 2982 igb_xdp_ring_update_tail(tx_ring); 2983 2984 return nxmit; 2985 } 2986 2987 static const struct net_device_ops igb_netdev_ops = { 2988 .ndo_open = igb_open, 2989 .ndo_stop = igb_close, 2990 .ndo_start_xmit = igb_xmit_frame, 2991 .ndo_get_stats64 = igb_get_stats64, 2992 .ndo_set_rx_mode = igb_set_rx_mode, 2993 .ndo_set_mac_address = igb_set_mac, 2994 .ndo_change_mtu = igb_change_mtu, 2995 .ndo_eth_ioctl = igb_ioctl, 2996 .ndo_tx_timeout = igb_tx_timeout, 2997 .ndo_validate_addr = eth_validate_addr, 2998 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2999 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3000 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3001 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3002 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3003 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3004 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3005 .ndo_get_vf_config = igb_ndo_get_vf_config, 3006 .ndo_fix_features = igb_fix_features, 3007 .ndo_set_features = igb_set_features, 3008 .ndo_fdb_add = igb_ndo_fdb_add, 3009 .ndo_features_check = igb_features_check, 3010 .ndo_setup_tc = igb_setup_tc, 3011 .ndo_bpf = igb_xdp, 3012 .ndo_xdp_xmit = igb_xdp_xmit, 3013 }; 3014 3015 /** 3016 * igb_set_fw_version - Configure version string for ethtool 3017 * @adapter: adapter struct 3018 **/ 3019 void igb_set_fw_version(struct igb_adapter *adapter) 3020 { 3021 struct e1000_hw *hw = &adapter->hw; 3022 struct e1000_fw_version fw; 3023 3024 igb_get_fw_version(hw, &fw); 3025 3026 switch (hw->mac.type) { 3027 case e1000_i210: 3028 case e1000_i211: 3029 if (!(igb_get_flash_presence_i210(hw))) { 3030 snprintf(adapter->fw_version, 3031 sizeof(adapter->fw_version), 3032 "%2d.%2d-%d", 3033 fw.invm_major, fw.invm_minor, 3034 fw.invm_img_type); 3035 break; 3036 } 3037 fallthrough; 3038 default: 3039 /* if option is rom valid, display its version too */ 3040 if (fw.or_valid) { 3041 snprintf(adapter->fw_version, 3042 sizeof(adapter->fw_version), 3043 "%d.%d, 0x%08x, %d.%d.%d", 3044 fw.eep_major, fw.eep_minor, fw.etrack_id, 3045 fw.or_major, fw.or_build, fw.or_patch); 3046 /* no option rom */ 3047 } else if (fw.etrack_id != 0X0000) { 3048 snprintf(adapter->fw_version, 3049 sizeof(adapter->fw_version), 3050 "%d.%d, 0x%08x", 3051 fw.eep_major, fw.eep_minor, fw.etrack_id); 3052 } else { 3053 snprintf(adapter->fw_version, 3054 sizeof(adapter->fw_version), 3055 "%d.%d.%d", 3056 fw.eep_major, fw.eep_minor, fw.eep_build); 3057 } 3058 break; 3059 } 3060 } 3061 3062 /** 3063 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3064 * 3065 * @adapter: adapter struct 3066 **/ 3067 static void igb_init_mas(struct igb_adapter *adapter) 3068 { 3069 struct e1000_hw *hw = &adapter->hw; 3070 u16 eeprom_data; 3071 3072 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3073 switch (hw->bus.func) { 3074 case E1000_FUNC_0: 3075 if (eeprom_data & IGB_MAS_ENABLE_0) { 3076 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3077 netdev_info(adapter->netdev, 3078 "MAS: Enabling Media Autosense for port %d\n", 3079 hw->bus.func); 3080 } 3081 break; 3082 case E1000_FUNC_1: 3083 if (eeprom_data & IGB_MAS_ENABLE_1) { 3084 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3085 netdev_info(adapter->netdev, 3086 "MAS: Enabling Media Autosense for port %d\n", 3087 hw->bus.func); 3088 } 3089 break; 3090 case E1000_FUNC_2: 3091 if (eeprom_data & IGB_MAS_ENABLE_2) { 3092 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3093 netdev_info(adapter->netdev, 3094 "MAS: Enabling Media Autosense for port %d\n", 3095 hw->bus.func); 3096 } 3097 break; 3098 case E1000_FUNC_3: 3099 if (eeprom_data & IGB_MAS_ENABLE_3) { 3100 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3101 netdev_info(adapter->netdev, 3102 "MAS: Enabling Media Autosense for port %d\n", 3103 hw->bus.func); 3104 } 3105 break; 3106 default: 3107 /* Shouldn't get here */ 3108 netdev_err(adapter->netdev, 3109 "MAS: Invalid port configuration, returning\n"); 3110 break; 3111 } 3112 } 3113 3114 /** 3115 * igb_init_i2c - Init I2C interface 3116 * @adapter: pointer to adapter structure 3117 **/ 3118 static s32 igb_init_i2c(struct igb_adapter *adapter) 3119 { 3120 struct e1000_hw *hw = &adapter->hw; 3121 s32 status = 0; 3122 s32 i2cctl; 3123 3124 /* I2C interface supported on i350 devices */ 3125 if (adapter->hw.mac.type != e1000_i350) 3126 return 0; 3127 3128 i2cctl = rd32(E1000_I2CPARAMS); 3129 i2cctl |= E1000_I2CBB_EN 3130 | E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N 3131 | E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 3132 wr32(E1000_I2CPARAMS, i2cctl); 3133 wrfl(); 3134 3135 /* Initialize the i2c bus which is controlled by the registers. 3136 * This bus will use the i2c_algo_bit structure that implements 3137 * the protocol through toggling of the 4 bits in the register. 3138 */ 3139 adapter->i2c_adap.owner = THIS_MODULE; 3140 adapter->i2c_algo = igb_i2c_algo; 3141 adapter->i2c_algo.data = adapter; 3142 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3143 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3144 strscpy(adapter->i2c_adap.name, "igb BB", 3145 sizeof(adapter->i2c_adap.name)); 3146 status = i2c_bit_add_bus(&adapter->i2c_adap); 3147 return status; 3148 } 3149 3150 /** 3151 * igb_probe - Device Initialization Routine 3152 * @pdev: PCI device information struct 3153 * @ent: entry in igb_pci_tbl 3154 * 3155 * Returns 0 on success, negative on failure 3156 * 3157 * igb_probe initializes an adapter identified by a pci_dev structure. 3158 * The OS initialization, configuring of the adapter private structure, 3159 * and a hardware reset occur. 3160 **/ 3161 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3162 { 3163 struct net_device *netdev; 3164 struct igb_adapter *adapter; 3165 struct e1000_hw *hw; 3166 u16 eeprom_data = 0; 3167 s32 ret_val; 3168 static int global_quad_port_a; /* global quad port a indication */ 3169 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3170 u8 part_str[E1000_PBANUM_LENGTH]; 3171 int err; 3172 3173 /* Catch broken hardware that put the wrong VF device ID in 3174 * the PCIe SR-IOV capability. 3175 */ 3176 if (pdev->is_virtfn) { 3177 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3178 pci_name(pdev), pdev->vendor, pdev->device); 3179 return -EINVAL; 3180 } 3181 3182 err = pci_enable_device_mem(pdev); 3183 if (err) 3184 return err; 3185 3186 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3187 if (err) { 3188 dev_err(&pdev->dev, 3189 "No usable DMA configuration, aborting\n"); 3190 goto err_dma; 3191 } 3192 3193 err = pci_request_mem_regions(pdev, igb_driver_name); 3194 if (err) 3195 goto err_pci_reg; 3196 3197 pci_set_master(pdev); 3198 pci_save_state(pdev); 3199 3200 err = -ENOMEM; 3201 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3202 IGB_MAX_TX_QUEUES); 3203 if (!netdev) 3204 goto err_alloc_etherdev; 3205 3206 SET_NETDEV_DEV(netdev, &pdev->dev); 3207 3208 pci_set_drvdata(pdev, netdev); 3209 adapter = netdev_priv(netdev); 3210 adapter->netdev = netdev; 3211 adapter->pdev = pdev; 3212 hw = &adapter->hw; 3213 hw->back = adapter; 3214 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3215 3216 err = -EIO; 3217 adapter->io_addr = pci_iomap(pdev, 0, 0); 3218 if (!adapter->io_addr) 3219 goto err_ioremap; 3220 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3221 hw->hw_addr = adapter->io_addr; 3222 3223 netdev->netdev_ops = &igb_netdev_ops; 3224 igb_set_ethtool_ops(netdev); 3225 netdev->watchdog_timeo = 5 * HZ; 3226 3227 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3228 3229 netdev->mem_start = pci_resource_start(pdev, 0); 3230 netdev->mem_end = pci_resource_end(pdev, 0); 3231 3232 /* PCI config space info */ 3233 hw->vendor_id = pdev->vendor; 3234 hw->device_id = pdev->device; 3235 hw->revision_id = pdev->revision; 3236 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3237 hw->subsystem_device_id = pdev->subsystem_device; 3238 3239 /* Copy the default MAC, PHY and NVM function pointers */ 3240 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3241 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3242 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3243 /* Initialize skew-specific constants */ 3244 err = ei->get_invariants(hw); 3245 if (err) 3246 goto err_sw_init; 3247 3248 /* setup the private structure */ 3249 err = igb_sw_init(adapter); 3250 if (err) 3251 goto err_sw_init; 3252 3253 igb_get_bus_info_pcie(hw); 3254 3255 hw->phy.autoneg_wait_to_complete = false; 3256 3257 /* Copper options */ 3258 if (hw->phy.media_type == e1000_media_type_copper) { 3259 hw->phy.mdix = AUTO_ALL_MODES; 3260 hw->phy.disable_polarity_correction = false; 3261 hw->phy.ms_type = e1000_ms_hw_default; 3262 } 3263 3264 if (igb_check_reset_block(hw)) 3265 dev_info(&pdev->dev, 3266 "PHY reset is blocked due to SOL/IDER session.\n"); 3267 3268 /* features is initialized to 0 in allocation, it might have bits 3269 * set by igb_sw_init so we should use an or instead of an 3270 * assignment. 3271 */ 3272 netdev->features |= NETIF_F_SG | 3273 NETIF_F_TSO | 3274 NETIF_F_TSO6 | 3275 NETIF_F_RXHASH | 3276 NETIF_F_RXCSUM | 3277 NETIF_F_HW_CSUM; 3278 3279 if (hw->mac.type >= e1000_82576) 3280 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3281 3282 if (hw->mac.type >= e1000_i350) 3283 netdev->features |= NETIF_F_HW_TC; 3284 3285 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3286 NETIF_F_GSO_GRE_CSUM | \ 3287 NETIF_F_GSO_IPXIP4 | \ 3288 NETIF_F_GSO_IPXIP6 | \ 3289 NETIF_F_GSO_UDP_TUNNEL | \ 3290 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3291 3292 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3293 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3294 3295 /* copy netdev features into list of user selectable features */ 3296 netdev->hw_features |= netdev->features | 3297 NETIF_F_HW_VLAN_CTAG_RX | 3298 NETIF_F_HW_VLAN_CTAG_TX | 3299 NETIF_F_RXALL; 3300 3301 if (hw->mac.type >= e1000_i350) 3302 netdev->hw_features |= NETIF_F_NTUPLE; 3303 3304 netdev->features |= NETIF_F_HIGHDMA; 3305 3306 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3307 netdev->mpls_features |= NETIF_F_HW_CSUM; 3308 netdev->hw_enc_features |= netdev->vlan_features; 3309 3310 /* set this bit last since it cannot be part of vlan_features */ 3311 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3312 NETIF_F_HW_VLAN_CTAG_RX | 3313 NETIF_F_HW_VLAN_CTAG_TX; 3314 3315 netdev->priv_flags |= IFF_SUPP_NOFCS; 3316 3317 netdev->priv_flags |= IFF_UNICAST_FLT; 3318 3319 /* MTU range: 68 - 9216 */ 3320 netdev->min_mtu = ETH_MIN_MTU; 3321 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3322 3323 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3324 3325 /* before reading the NVM, reset the controller to put the device in a 3326 * known good starting state 3327 */ 3328 hw->mac.ops.reset_hw(hw); 3329 3330 /* make sure the NVM is good , i211/i210 parts can have special NVM 3331 * that doesn't contain a checksum 3332 */ 3333 switch (hw->mac.type) { 3334 case e1000_i210: 3335 case e1000_i211: 3336 if (igb_get_flash_presence_i210(hw)) { 3337 if (hw->nvm.ops.validate(hw) < 0) { 3338 dev_err(&pdev->dev, 3339 "The NVM Checksum Is Not Valid\n"); 3340 err = -EIO; 3341 goto err_eeprom; 3342 } 3343 } 3344 break; 3345 default: 3346 if (hw->nvm.ops.validate(hw) < 0) { 3347 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3348 err = -EIO; 3349 goto err_eeprom; 3350 } 3351 break; 3352 } 3353 3354 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3355 /* copy the MAC address out of the NVM */ 3356 if (hw->mac.ops.read_mac_addr(hw)) 3357 dev_err(&pdev->dev, "NVM Read Error\n"); 3358 } 3359 3360 eth_hw_addr_set(netdev, hw->mac.addr); 3361 3362 if (!is_valid_ether_addr(netdev->dev_addr)) { 3363 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3364 err = -EIO; 3365 goto err_eeprom; 3366 } 3367 3368 igb_set_default_mac_filter(adapter); 3369 3370 /* get firmware version for ethtool -i */ 3371 igb_set_fw_version(adapter); 3372 3373 /* configure RXPBSIZE and TXPBSIZE */ 3374 if (hw->mac.type == e1000_i210) { 3375 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3376 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3377 } 3378 3379 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3380 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3381 3382 INIT_WORK(&adapter->reset_task, igb_reset_task); 3383 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3384 3385 /* Initialize link properties that are user-changeable */ 3386 adapter->fc_autoneg = true; 3387 hw->mac.autoneg = true; 3388 hw->phy.autoneg_advertised = 0x2f; 3389 3390 hw->fc.requested_mode = e1000_fc_default; 3391 hw->fc.current_mode = e1000_fc_default; 3392 3393 igb_validate_mdi_setting(hw); 3394 3395 /* By default, support wake on port A */ 3396 if (hw->bus.func == 0) 3397 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3398 3399 /* Check the NVM for wake support on non-port A ports */ 3400 if (hw->mac.type >= e1000_82580) 3401 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3402 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3403 &eeprom_data); 3404 else if (hw->bus.func == 1) 3405 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3406 3407 if (eeprom_data & IGB_EEPROM_APME) 3408 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3409 3410 /* now that we have the eeprom settings, apply the special cases where 3411 * the eeprom may be wrong or the board simply won't support wake on 3412 * lan on a particular port 3413 */ 3414 switch (pdev->device) { 3415 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3416 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3417 break; 3418 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3419 case E1000_DEV_ID_82576_FIBER: 3420 case E1000_DEV_ID_82576_SERDES: 3421 /* Wake events only supported on port A for dual fiber 3422 * regardless of eeprom setting 3423 */ 3424 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3425 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3426 break; 3427 case E1000_DEV_ID_82576_QUAD_COPPER: 3428 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3429 /* if quad port adapter, disable WoL on all but port A */ 3430 if (global_quad_port_a != 0) 3431 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3432 else 3433 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3434 /* Reset for multiple quad port adapters */ 3435 if (++global_quad_port_a == 4) 3436 global_quad_port_a = 0; 3437 break; 3438 default: 3439 /* If the device can't wake, don't set software support */ 3440 if (!device_can_wakeup(&adapter->pdev->dev)) 3441 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3442 } 3443 3444 /* initialize the wol settings based on the eeprom settings */ 3445 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3446 adapter->wol |= E1000_WUFC_MAG; 3447 3448 /* Some vendors want WoL disabled by default, but still supported */ 3449 if ((hw->mac.type == e1000_i350) && 3450 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3451 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3452 adapter->wol = 0; 3453 } 3454 3455 /* Some vendors want the ability to Use the EEPROM setting as 3456 * enable/disable only, and not for capability 3457 */ 3458 if (((hw->mac.type == e1000_i350) || 3459 (hw->mac.type == e1000_i354)) && 3460 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3461 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3462 adapter->wol = 0; 3463 } 3464 if (hw->mac.type == e1000_i350) { 3465 if (((pdev->subsystem_device == 0x5001) || 3466 (pdev->subsystem_device == 0x5002)) && 3467 (hw->bus.func == 0)) { 3468 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3469 adapter->wol = 0; 3470 } 3471 if (pdev->subsystem_device == 0x1F52) 3472 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3473 } 3474 3475 device_set_wakeup_enable(&adapter->pdev->dev, 3476 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3477 3478 /* reset the hardware with the new settings */ 3479 igb_reset(adapter); 3480 3481 /* Init the I2C interface */ 3482 err = igb_init_i2c(adapter); 3483 if (err) { 3484 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3485 goto err_eeprom; 3486 } 3487 3488 /* let the f/w know that the h/w is now under the control of the 3489 * driver. 3490 */ 3491 igb_get_hw_control(adapter); 3492 3493 strcpy(netdev->name, "eth%d"); 3494 err = register_netdev(netdev); 3495 if (err) 3496 goto err_register; 3497 3498 /* carrier off reporting is important to ethtool even BEFORE open */ 3499 netif_carrier_off(netdev); 3500 3501 #ifdef CONFIG_IGB_DCA 3502 if (dca_add_requester(&pdev->dev) == 0) { 3503 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3504 dev_info(&pdev->dev, "DCA enabled\n"); 3505 igb_setup_dca(adapter); 3506 } 3507 3508 #endif 3509 #ifdef CONFIG_IGB_HWMON 3510 /* Initialize the thermal sensor on i350 devices. */ 3511 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3512 u16 ets_word; 3513 3514 /* Read the NVM to determine if this i350 device supports an 3515 * external thermal sensor. 3516 */ 3517 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3518 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3519 adapter->ets = true; 3520 else 3521 adapter->ets = false; 3522 if (igb_sysfs_init(adapter)) 3523 dev_err(&pdev->dev, 3524 "failed to allocate sysfs resources\n"); 3525 } else { 3526 adapter->ets = false; 3527 } 3528 #endif 3529 /* Check if Media Autosense is enabled */ 3530 adapter->ei = *ei; 3531 if (hw->dev_spec._82575.mas_capable) 3532 igb_init_mas(adapter); 3533 3534 /* do hw tstamp init after resetting */ 3535 igb_ptp_init(adapter); 3536 3537 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3538 /* print bus type/speed/width info, not applicable to i354 */ 3539 if (hw->mac.type != e1000_i354) { 3540 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3541 netdev->name, 3542 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3543 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3544 "unknown"), 3545 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3546 "Width x4" : 3547 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3548 "Width x2" : 3549 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3550 "Width x1" : "unknown"), netdev->dev_addr); 3551 } 3552 3553 if ((hw->mac.type == e1000_82576 && 3554 rd32(E1000_EECD) & E1000_EECD_PRES) || 3555 (hw->mac.type >= e1000_i210 || 3556 igb_get_flash_presence_i210(hw))) { 3557 ret_val = igb_read_part_string(hw, part_str, 3558 E1000_PBANUM_LENGTH); 3559 } else { 3560 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3561 } 3562 3563 if (ret_val) 3564 strcpy(part_str, "Unknown"); 3565 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3566 dev_info(&pdev->dev, 3567 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3568 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3569 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3570 adapter->num_rx_queues, adapter->num_tx_queues); 3571 if (hw->phy.media_type == e1000_media_type_copper) { 3572 switch (hw->mac.type) { 3573 case e1000_i350: 3574 case e1000_i210: 3575 case e1000_i211: 3576 /* Enable EEE for internal copper PHY devices */ 3577 err = igb_set_eee_i350(hw, true, true); 3578 if ((!err) && 3579 (!hw->dev_spec._82575.eee_disable)) { 3580 adapter->eee_advert = 3581 MDIO_EEE_100TX | MDIO_EEE_1000T; 3582 adapter->flags |= IGB_FLAG_EEE; 3583 } 3584 break; 3585 case e1000_i354: 3586 if ((rd32(E1000_CTRL_EXT) & 3587 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3588 err = igb_set_eee_i354(hw, true, true); 3589 if ((!err) && 3590 (!hw->dev_spec._82575.eee_disable)) { 3591 adapter->eee_advert = 3592 MDIO_EEE_100TX | MDIO_EEE_1000T; 3593 adapter->flags |= IGB_FLAG_EEE; 3594 } 3595 } 3596 break; 3597 default: 3598 break; 3599 } 3600 } 3601 3602 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3603 3604 pm_runtime_put_noidle(&pdev->dev); 3605 return 0; 3606 3607 err_register: 3608 igb_release_hw_control(adapter); 3609 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3610 err_eeprom: 3611 if (!igb_check_reset_block(hw)) 3612 igb_reset_phy(hw); 3613 3614 if (hw->flash_address) 3615 iounmap(hw->flash_address); 3616 err_sw_init: 3617 kfree(adapter->mac_table); 3618 kfree(adapter->shadow_vfta); 3619 igb_clear_interrupt_scheme(adapter); 3620 #ifdef CONFIG_PCI_IOV 3621 igb_disable_sriov(pdev); 3622 #endif 3623 pci_iounmap(pdev, adapter->io_addr); 3624 err_ioremap: 3625 free_netdev(netdev); 3626 err_alloc_etherdev: 3627 pci_release_mem_regions(pdev); 3628 err_pci_reg: 3629 err_dma: 3630 pci_disable_device(pdev); 3631 return err; 3632 } 3633 3634 #ifdef CONFIG_PCI_IOV 3635 static int igb_disable_sriov(struct pci_dev *pdev) 3636 { 3637 struct net_device *netdev = pci_get_drvdata(pdev); 3638 struct igb_adapter *adapter = netdev_priv(netdev); 3639 struct e1000_hw *hw = &adapter->hw; 3640 unsigned long flags; 3641 3642 /* reclaim resources allocated to VFs */ 3643 if (adapter->vf_data) { 3644 /* disable iov and allow time for transactions to clear */ 3645 if (pci_vfs_assigned(pdev)) { 3646 dev_warn(&pdev->dev, 3647 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3648 return -EPERM; 3649 } else { 3650 pci_disable_sriov(pdev); 3651 msleep(500); 3652 } 3653 spin_lock_irqsave(&adapter->vfs_lock, flags); 3654 kfree(adapter->vf_mac_list); 3655 adapter->vf_mac_list = NULL; 3656 kfree(adapter->vf_data); 3657 adapter->vf_data = NULL; 3658 adapter->vfs_allocated_count = 0; 3659 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3660 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3661 wrfl(); 3662 msleep(100); 3663 dev_info(&pdev->dev, "IOV Disabled\n"); 3664 3665 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3666 adapter->flags |= IGB_FLAG_DMAC; 3667 } 3668 3669 return 0; 3670 } 3671 3672 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3673 { 3674 struct net_device *netdev = pci_get_drvdata(pdev); 3675 struct igb_adapter *adapter = netdev_priv(netdev); 3676 int old_vfs = pci_num_vf(pdev); 3677 struct vf_mac_filter *mac_list; 3678 int err = 0; 3679 int num_vf_mac_filters, i; 3680 3681 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3682 err = -EPERM; 3683 goto out; 3684 } 3685 if (!num_vfs) 3686 goto out; 3687 3688 if (old_vfs) { 3689 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3690 old_vfs, max_vfs); 3691 adapter->vfs_allocated_count = old_vfs; 3692 } else 3693 adapter->vfs_allocated_count = num_vfs; 3694 3695 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3696 sizeof(struct vf_data_storage), GFP_KERNEL); 3697 3698 /* if allocation failed then we do not support SR-IOV */ 3699 if (!adapter->vf_data) { 3700 adapter->vfs_allocated_count = 0; 3701 err = -ENOMEM; 3702 goto out; 3703 } 3704 3705 /* Due to the limited number of RAR entries calculate potential 3706 * number of MAC filters available for the VFs. Reserve entries 3707 * for PF default MAC, PF MAC filters and at least one RAR entry 3708 * for each VF for VF MAC. 3709 */ 3710 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3711 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3712 adapter->vfs_allocated_count); 3713 3714 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3715 sizeof(struct vf_mac_filter), 3716 GFP_KERNEL); 3717 3718 mac_list = adapter->vf_mac_list; 3719 INIT_LIST_HEAD(&adapter->vf_macs.l); 3720 3721 if (adapter->vf_mac_list) { 3722 /* Initialize list of VF MAC filters */ 3723 for (i = 0; i < num_vf_mac_filters; i++) { 3724 mac_list->vf = -1; 3725 mac_list->free = true; 3726 list_add(&mac_list->l, &adapter->vf_macs.l); 3727 mac_list++; 3728 } 3729 } else { 3730 /* If we could not allocate memory for the VF MAC filters 3731 * we can continue without this feature but warn user. 3732 */ 3733 dev_err(&pdev->dev, 3734 "Unable to allocate memory for VF MAC filter list\n"); 3735 } 3736 3737 /* only call pci_enable_sriov() if no VFs are allocated already */ 3738 if (!old_vfs) { 3739 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3740 if (err) 3741 goto err_out; 3742 } 3743 dev_info(&pdev->dev, "%d VFs allocated\n", 3744 adapter->vfs_allocated_count); 3745 for (i = 0; i < adapter->vfs_allocated_count; i++) 3746 igb_vf_configure(adapter, i); 3747 3748 /* DMA Coalescing is not supported in IOV mode. */ 3749 adapter->flags &= ~IGB_FLAG_DMAC; 3750 goto out; 3751 3752 err_out: 3753 kfree(adapter->vf_mac_list); 3754 adapter->vf_mac_list = NULL; 3755 kfree(adapter->vf_data); 3756 adapter->vf_data = NULL; 3757 adapter->vfs_allocated_count = 0; 3758 out: 3759 return err; 3760 } 3761 3762 #endif 3763 /** 3764 * igb_remove_i2c - Cleanup I2C interface 3765 * @adapter: pointer to adapter structure 3766 **/ 3767 static void igb_remove_i2c(struct igb_adapter *adapter) 3768 { 3769 /* free the adapter bus structure */ 3770 i2c_del_adapter(&adapter->i2c_adap); 3771 } 3772 3773 /** 3774 * igb_remove - Device Removal Routine 3775 * @pdev: PCI device information struct 3776 * 3777 * igb_remove is called by the PCI subsystem to alert the driver 3778 * that it should release a PCI device. The could be caused by a 3779 * Hot-Plug event, or because the driver is going to be removed from 3780 * memory. 3781 **/ 3782 static void igb_remove(struct pci_dev *pdev) 3783 { 3784 struct net_device *netdev = pci_get_drvdata(pdev); 3785 struct igb_adapter *adapter = netdev_priv(netdev); 3786 struct e1000_hw *hw = &adapter->hw; 3787 3788 pm_runtime_get_noresume(&pdev->dev); 3789 #ifdef CONFIG_IGB_HWMON 3790 igb_sysfs_exit(adapter); 3791 #endif 3792 igb_remove_i2c(adapter); 3793 igb_ptp_stop(adapter); 3794 /* The watchdog timer may be rescheduled, so explicitly 3795 * disable watchdog from being rescheduled. 3796 */ 3797 set_bit(__IGB_DOWN, &adapter->state); 3798 del_timer_sync(&adapter->watchdog_timer); 3799 del_timer_sync(&adapter->phy_info_timer); 3800 3801 cancel_work_sync(&adapter->reset_task); 3802 cancel_work_sync(&adapter->watchdog_task); 3803 3804 #ifdef CONFIG_IGB_DCA 3805 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3806 dev_info(&pdev->dev, "DCA disabled\n"); 3807 dca_remove_requester(&pdev->dev); 3808 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3809 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3810 } 3811 #endif 3812 3813 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3814 * would have already happened in close and is redundant. 3815 */ 3816 igb_release_hw_control(adapter); 3817 3818 #ifdef CONFIG_PCI_IOV 3819 rtnl_lock(); 3820 igb_disable_sriov(pdev); 3821 rtnl_unlock(); 3822 #endif 3823 3824 unregister_netdev(netdev); 3825 3826 igb_clear_interrupt_scheme(adapter); 3827 3828 pci_iounmap(pdev, adapter->io_addr); 3829 if (hw->flash_address) 3830 iounmap(hw->flash_address); 3831 pci_release_mem_regions(pdev); 3832 3833 kfree(adapter->mac_table); 3834 kfree(adapter->shadow_vfta); 3835 free_netdev(netdev); 3836 3837 pci_disable_device(pdev); 3838 } 3839 3840 /** 3841 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3842 * @adapter: board private structure to initialize 3843 * 3844 * This function initializes the vf specific data storage and then attempts to 3845 * allocate the VFs. The reason for ordering it this way is because it is much 3846 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3847 * the memory for the VFs. 3848 **/ 3849 static void igb_probe_vfs(struct igb_adapter *adapter) 3850 { 3851 #ifdef CONFIG_PCI_IOV 3852 struct pci_dev *pdev = adapter->pdev; 3853 struct e1000_hw *hw = &adapter->hw; 3854 3855 /* Virtualization features not supported on i210 family. */ 3856 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3857 return; 3858 3859 /* Of the below we really only want the effect of getting 3860 * IGB_FLAG_HAS_MSIX set (if available), without which 3861 * igb_enable_sriov() has no effect. 3862 */ 3863 igb_set_interrupt_capability(adapter, true); 3864 igb_reset_interrupt_capability(adapter); 3865 3866 pci_sriov_set_totalvfs(pdev, 7); 3867 igb_enable_sriov(pdev, max_vfs); 3868 3869 #endif /* CONFIG_PCI_IOV */ 3870 } 3871 3872 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3873 { 3874 struct e1000_hw *hw = &adapter->hw; 3875 unsigned int max_rss_queues; 3876 3877 /* Determine the maximum number of RSS queues supported. */ 3878 switch (hw->mac.type) { 3879 case e1000_i211: 3880 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3881 break; 3882 case e1000_82575: 3883 case e1000_i210: 3884 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3885 break; 3886 case e1000_i350: 3887 /* I350 cannot do RSS and SR-IOV at the same time */ 3888 if (!!adapter->vfs_allocated_count) { 3889 max_rss_queues = 1; 3890 break; 3891 } 3892 fallthrough; 3893 case e1000_82576: 3894 if (!!adapter->vfs_allocated_count) { 3895 max_rss_queues = 2; 3896 break; 3897 } 3898 fallthrough; 3899 case e1000_82580: 3900 case e1000_i354: 3901 default: 3902 max_rss_queues = IGB_MAX_RX_QUEUES; 3903 break; 3904 } 3905 3906 return max_rss_queues; 3907 } 3908 3909 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3910 { 3911 u32 max_rss_queues; 3912 3913 max_rss_queues = igb_get_max_rss_queues(adapter); 3914 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3915 3916 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3917 } 3918 3919 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3920 const u32 max_rss_queues) 3921 { 3922 struct e1000_hw *hw = &adapter->hw; 3923 3924 /* Determine if we need to pair queues. */ 3925 switch (hw->mac.type) { 3926 case e1000_82575: 3927 case e1000_i211: 3928 /* Device supports enough interrupts without queue pairing. */ 3929 break; 3930 case e1000_82576: 3931 case e1000_82580: 3932 case e1000_i350: 3933 case e1000_i354: 3934 case e1000_i210: 3935 default: 3936 /* If rss_queues > half of max_rss_queues, pair the queues in 3937 * order to conserve interrupts due to limited supply. 3938 */ 3939 if (adapter->rss_queues > (max_rss_queues / 2)) 3940 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3941 else 3942 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3943 break; 3944 } 3945 } 3946 3947 /** 3948 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3949 * @adapter: board private structure to initialize 3950 * 3951 * igb_sw_init initializes the Adapter private data structure. 3952 * Fields are initialized based on PCI device information and 3953 * OS network device settings (MTU size). 3954 **/ 3955 static int igb_sw_init(struct igb_adapter *adapter) 3956 { 3957 struct e1000_hw *hw = &adapter->hw; 3958 struct net_device *netdev = adapter->netdev; 3959 struct pci_dev *pdev = adapter->pdev; 3960 3961 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3962 3963 /* set default ring sizes */ 3964 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3965 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3966 3967 /* set default ITR values */ 3968 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3969 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3970 3971 /* set default work limits */ 3972 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3973 3974 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3975 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3976 3977 spin_lock_init(&adapter->nfc_lock); 3978 spin_lock_init(&adapter->stats64_lock); 3979 3980 /* init spinlock to avoid concurrency of VF resources */ 3981 spin_lock_init(&adapter->vfs_lock); 3982 #ifdef CONFIG_PCI_IOV 3983 switch (hw->mac.type) { 3984 case e1000_82576: 3985 case e1000_i350: 3986 if (max_vfs > 7) { 3987 dev_warn(&pdev->dev, 3988 "Maximum of 7 VFs per PF, using max\n"); 3989 max_vfs = adapter->vfs_allocated_count = 7; 3990 } else 3991 adapter->vfs_allocated_count = max_vfs; 3992 if (adapter->vfs_allocated_count) 3993 dev_warn(&pdev->dev, 3994 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3995 break; 3996 default: 3997 break; 3998 } 3999 #endif /* CONFIG_PCI_IOV */ 4000 4001 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4002 adapter->flags |= IGB_FLAG_HAS_MSIX; 4003 4004 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4005 sizeof(struct igb_mac_addr), 4006 GFP_KERNEL); 4007 if (!adapter->mac_table) 4008 return -ENOMEM; 4009 4010 igb_probe_vfs(adapter); 4011 4012 igb_init_queue_configuration(adapter); 4013 4014 /* Setup and initialize a copy of the hw vlan table array */ 4015 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4016 GFP_KERNEL); 4017 if (!adapter->shadow_vfta) 4018 return -ENOMEM; 4019 4020 /* This call may decrease the number of queues */ 4021 if (igb_init_interrupt_scheme(adapter, true)) { 4022 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4023 return -ENOMEM; 4024 } 4025 4026 /* Explicitly disable IRQ since the NIC can be in any state. */ 4027 igb_irq_disable(adapter); 4028 4029 if (hw->mac.type >= e1000_i350) 4030 adapter->flags &= ~IGB_FLAG_DMAC; 4031 4032 set_bit(__IGB_DOWN, &adapter->state); 4033 return 0; 4034 } 4035 4036 /** 4037 * __igb_open - Called when a network interface is made active 4038 * @netdev: network interface device structure 4039 * @resuming: indicates whether we are in a resume call 4040 * 4041 * Returns 0 on success, negative value on failure 4042 * 4043 * The open entry point is called when a network interface is made 4044 * active by the system (IFF_UP). At this point all resources needed 4045 * for transmit and receive operations are allocated, the interrupt 4046 * handler is registered with the OS, the watchdog timer is started, 4047 * and the stack is notified that the interface is ready. 4048 **/ 4049 static int __igb_open(struct net_device *netdev, bool resuming) 4050 { 4051 struct igb_adapter *adapter = netdev_priv(netdev); 4052 struct e1000_hw *hw = &adapter->hw; 4053 struct pci_dev *pdev = adapter->pdev; 4054 int err; 4055 int i; 4056 4057 /* disallow open during test */ 4058 if (test_bit(__IGB_TESTING, &adapter->state)) { 4059 WARN_ON(resuming); 4060 return -EBUSY; 4061 } 4062 4063 if (!resuming) 4064 pm_runtime_get_sync(&pdev->dev); 4065 4066 netif_carrier_off(netdev); 4067 4068 /* allocate transmit descriptors */ 4069 err = igb_setup_all_tx_resources(adapter); 4070 if (err) 4071 goto err_setup_tx; 4072 4073 /* allocate receive descriptors */ 4074 err = igb_setup_all_rx_resources(adapter); 4075 if (err) 4076 goto err_setup_rx; 4077 4078 igb_power_up_link(adapter); 4079 4080 /* before we allocate an interrupt, we must be ready to handle it. 4081 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4082 * as soon as we call pci_request_irq, so we have to setup our 4083 * clean_rx handler before we do so. 4084 */ 4085 igb_configure(adapter); 4086 4087 err = igb_request_irq(adapter); 4088 if (err) 4089 goto err_req_irq; 4090 4091 /* Notify the stack of the actual queue counts. */ 4092 err = netif_set_real_num_tx_queues(adapter->netdev, 4093 adapter->num_tx_queues); 4094 if (err) 4095 goto err_set_queues; 4096 4097 err = netif_set_real_num_rx_queues(adapter->netdev, 4098 adapter->num_rx_queues); 4099 if (err) 4100 goto err_set_queues; 4101 4102 /* From here on the code is the same as igb_up() */ 4103 clear_bit(__IGB_DOWN, &adapter->state); 4104 4105 for (i = 0; i < adapter->num_q_vectors; i++) 4106 napi_enable(&(adapter->q_vector[i]->napi)); 4107 4108 /* Clear any pending interrupts. */ 4109 rd32(E1000_TSICR); 4110 rd32(E1000_ICR); 4111 4112 igb_irq_enable(adapter); 4113 4114 /* notify VFs that reset has been completed */ 4115 if (adapter->vfs_allocated_count) { 4116 u32 reg_data = rd32(E1000_CTRL_EXT); 4117 4118 reg_data |= E1000_CTRL_EXT_PFRSTD; 4119 wr32(E1000_CTRL_EXT, reg_data); 4120 } 4121 4122 netif_tx_start_all_queues(netdev); 4123 4124 if (!resuming) 4125 pm_runtime_put(&pdev->dev); 4126 4127 /* start the watchdog. */ 4128 hw->mac.get_link_status = 1; 4129 schedule_work(&adapter->watchdog_task); 4130 4131 return 0; 4132 4133 err_set_queues: 4134 igb_free_irq(adapter); 4135 err_req_irq: 4136 igb_release_hw_control(adapter); 4137 igb_power_down_link(adapter); 4138 igb_free_all_rx_resources(adapter); 4139 err_setup_rx: 4140 igb_free_all_tx_resources(adapter); 4141 err_setup_tx: 4142 igb_reset(adapter); 4143 if (!resuming) 4144 pm_runtime_put(&pdev->dev); 4145 4146 return err; 4147 } 4148 4149 int igb_open(struct net_device *netdev) 4150 { 4151 return __igb_open(netdev, false); 4152 } 4153 4154 /** 4155 * __igb_close - Disables a network interface 4156 * @netdev: network interface device structure 4157 * @suspending: indicates we are in a suspend call 4158 * 4159 * Returns 0, this is not allowed to fail 4160 * 4161 * The close entry point is called when an interface is de-activated 4162 * by the OS. The hardware is still under the driver's control, but 4163 * needs to be disabled. A global MAC reset is issued to stop the 4164 * hardware, and all transmit and receive resources are freed. 4165 **/ 4166 static int __igb_close(struct net_device *netdev, bool suspending) 4167 { 4168 struct igb_adapter *adapter = netdev_priv(netdev); 4169 struct pci_dev *pdev = adapter->pdev; 4170 4171 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4172 4173 if (!suspending) 4174 pm_runtime_get_sync(&pdev->dev); 4175 4176 igb_down(adapter); 4177 igb_free_irq(adapter); 4178 4179 igb_free_all_tx_resources(adapter); 4180 igb_free_all_rx_resources(adapter); 4181 4182 if (!suspending) 4183 pm_runtime_put_sync(&pdev->dev); 4184 return 0; 4185 } 4186 4187 int igb_close(struct net_device *netdev) 4188 { 4189 if (netif_device_present(netdev) || netdev->dismantle) 4190 return __igb_close(netdev, false); 4191 return 0; 4192 } 4193 4194 /** 4195 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4196 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4197 * 4198 * Return 0 on success, negative on failure 4199 **/ 4200 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4201 { 4202 struct device *dev = tx_ring->dev; 4203 int size; 4204 4205 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4206 4207 tx_ring->tx_buffer_info = vmalloc(size); 4208 if (!tx_ring->tx_buffer_info) 4209 goto err; 4210 4211 /* round up to nearest 4K */ 4212 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4213 tx_ring->size = ALIGN(tx_ring->size, 4096); 4214 4215 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4216 &tx_ring->dma, GFP_KERNEL); 4217 if (!tx_ring->desc) 4218 goto err; 4219 4220 tx_ring->next_to_use = 0; 4221 tx_ring->next_to_clean = 0; 4222 4223 return 0; 4224 4225 err: 4226 vfree(tx_ring->tx_buffer_info); 4227 tx_ring->tx_buffer_info = NULL; 4228 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4229 return -ENOMEM; 4230 } 4231 4232 /** 4233 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4234 * (Descriptors) for all queues 4235 * @adapter: board private structure 4236 * 4237 * Return 0 on success, negative on failure 4238 **/ 4239 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4240 { 4241 struct pci_dev *pdev = adapter->pdev; 4242 int i, err = 0; 4243 4244 for (i = 0; i < adapter->num_tx_queues; i++) { 4245 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4246 if (err) { 4247 dev_err(&pdev->dev, 4248 "Allocation for Tx Queue %u failed\n", i); 4249 for (i--; i >= 0; i--) 4250 igb_free_tx_resources(adapter->tx_ring[i]); 4251 break; 4252 } 4253 } 4254 4255 return err; 4256 } 4257 4258 /** 4259 * igb_setup_tctl - configure the transmit control registers 4260 * @adapter: Board private structure 4261 **/ 4262 void igb_setup_tctl(struct igb_adapter *adapter) 4263 { 4264 struct e1000_hw *hw = &adapter->hw; 4265 u32 tctl; 4266 4267 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4268 wr32(E1000_TXDCTL(0), 0); 4269 4270 /* Program the Transmit Control Register */ 4271 tctl = rd32(E1000_TCTL); 4272 tctl &= ~E1000_TCTL_CT; 4273 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4275 4276 igb_config_collision_dist(hw); 4277 4278 /* Enable transmits */ 4279 tctl |= E1000_TCTL_EN; 4280 4281 wr32(E1000_TCTL, tctl); 4282 } 4283 4284 /** 4285 * igb_configure_tx_ring - Configure transmit ring after Reset 4286 * @adapter: board private structure 4287 * @ring: tx ring to configure 4288 * 4289 * Configure a transmit ring after a reset. 4290 **/ 4291 void igb_configure_tx_ring(struct igb_adapter *adapter, 4292 struct igb_ring *ring) 4293 { 4294 struct e1000_hw *hw = &adapter->hw; 4295 u32 txdctl = 0; 4296 u64 tdba = ring->dma; 4297 int reg_idx = ring->reg_idx; 4298 4299 wr32(E1000_TDLEN(reg_idx), 4300 ring->count * sizeof(union e1000_adv_tx_desc)); 4301 wr32(E1000_TDBAL(reg_idx), 4302 tdba & 0x00000000ffffffffULL); 4303 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4304 4305 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4306 wr32(E1000_TDH(reg_idx), 0); 4307 writel(0, ring->tail); 4308 4309 txdctl |= IGB_TX_PTHRESH; 4310 txdctl |= IGB_TX_HTHRESH << 8; 4311 txdctl |= IGB_TX_WTHRESH << 16; 4312 4313 /* reinitialize tx_buffer_info */ 4314 memset(ring->tx_buffer_info, 0, 4315 sizeof(struct igb_tx_buffer) * ring->count); 4316 4317 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4318 wr32(E1000_TXDCTL(reg_idx), txdctl); 4319 } 4320 4321 /** 4322 * igb_configure_tx - Configure transmit Unit after Reset 4323 * @adapter: board private structure 4324 * 4325 * Configure the Tx unit of the MAC after a reset. 4326 **/ 4327 static void igb_configure_tx(struct igb_adapter *adapter) 4328 { 4329 struct e1000_hw *hw = &adapter->hw; 4330 int i; 4331 4332 /* disable the queues */ 4333 for (i = 0; i < adapter->num_tx_queues; i++) 4334 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4335 4336 wrfl(); 4337 usleep_range(10000, 20000); 4338 4339 for (i = 0; i < adapter->num_tx_queues; i++) 4340 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4341 } 4342 4343 /** 4344 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4345 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4346 * 4347 * Returns 0 on success, negative on failure 4348 **/ 4349 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4350 { 4351 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4352 struct device *dev = rx_ring->dev; 4353 int size, res; 4354 4355 /* XDP RX-queue info */ 4356 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4357 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4358 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4359 rx_ring->queue_index, 0); 4360 if (res < 0) { 4361 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4362 rx_ring->queue_index); 4363 return res; 4364 } 4365 4366 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4367 4368 rx_ring->rx_buffer_info = vmalloc(size); 4369 if (!rx_ring->rx_buffer_info) 4370 goto err; 4371 4372 /* Round up to nearest 4K */ 4373 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4374 rx_ring->size = ALIGN(rx_ring->size, 4096); 4375 4376 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4377 &rx_ring->dma, GFP_KERNEL); 4378 if (!rx_ring->desc) 4379 goto err; 4380 4381 rx_ring->next_to_alloc = 0; 4382 rx_ring->next_to_clean = 0; 4383 rx_ring->next_to_use = 0; 4384 4385 rx_ring->xdp_prog = adapter->xdp_prog; 4386 4387 return 0; 4388 4389 err: 4390 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4391 vfree(rx_ring->rx_buffer_info); 4392 rx_ring->rx_buffer_info = NULL; 4393 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4394 return -ENOMEM; 4395 } 4396 4397 /** 4398 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4399 * (Descriptors) for all queues 4400 * @adapter: board private structure 4401 * 4402 * Return 0 on success, negative on failure 4403 **/ 4404 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4405 { 4406 struct pci_dev *pdev = adapter->pdev; 4407 int i, err = 0; 4408 4409 for (i = 0; i < adapter->num_rx_queues; i++) { 4410 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4411 if (err) { 4412 dev_err(&pdev->dev, 4413 "Allocation for Rx Queue %u failed\n", i); 4414 for (i--; i >= 0; i--) 4415 igb_free_rx_resources(adapter->rx_ring[i]); 4416 break; 4417 } 4418 } 4419 4420 return err; 4421 } 4422 4423 /** 4424 * igb_setup_mrqc - configure the multiple receive queue control registers 4425 * @adapter: Board private structure 4426 **/ 4427 static void igb_setup_mrqc(struct igb_adapter *adapter) 4428 { 4429 struct e1000_hw *hw = &adapter->hw; 4430 u32 mrqc, rxcsum; 4431 u32 j, num_rx_queues; 4432 u32 rss_key[10]; 4433 4434 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4435 for (j = 0; j < 10; j++) 4436 wr32(E1000_RSSRK(j), rss_key[j]); 4437 4438 num_rx_queues = adapter->rss_queues; 4439 4440 switch (hw->mac.type) { 4441 case e1000_82576: 4442 /* 82576 supports 2 RSS queues for SR-IOV */ 4443 if (adapter->vfs_allocated_count) 4444 num_rx_queues = 2; 4445 break; 4446 default: 4447 break; 4448 } 4449 4450 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4451 for (j = 0; j < IGB_RETA_SIZE; j++) 4452 adapter->rss_indir_tbl[j] = 4453 (j * num_rx_queues) / IGB_RETA_SIZE; 4454 adapter->rss_indir_tbl_init = num_rx_queues; 4455 } 4456 igb_write_rss_indir_tbl(adapter); 4457 4458 /* Disable raw packet checksumming so that RSS hash is placed in 4459 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4460 * offloads as they are enabled by default 4461 */ 4462 rxcsum = rd32(E1000_RXCSUM); 4463 rxcsum |= E1000_RXCSUM_PCSD; 4464 4465 if (adapter->hw.mac.type >= e1000_82576) 4466 /* Enable Receive Checksum Offload for SCTP */ 4467 rxcsum |= E1000_RXCSUM_CRCOFL; 4468 4469 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4470 wr32(E1000_RXCSUM, rxcsum); 4471 4472 /* Generate RSS hash based on packet types, TCP/UDP 4473 * port numbers and/or IPv4/v6 src and dst addresses 4474 */ 4475 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4476 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4477 E1000_MRQC_RSS_FIELD_IPV6 | 4478 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4479 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4480 4481 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4482 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4483 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4484 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4485 4486 /* If VMDq is enabled then we set the appropriate mode for that, else 4487 * we default to RSS so that an RSS hash is calculated per packet even 4488 * if we are only using one queue 4489 */ 4490 if (adapter->vfs_allocated_count) { 4491 if (hw->mac.type > e1000_82575) { 4492 /* Set the default pool for the PF's first queue */ 4493 u32 vtctl = rd32(E1000_VT_CTL); 4494 4495 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4496 E1000_VT_CTL_DISABLE_DEF_POOL); 4497 vtctl |= adapter->vfs_allocated_count << 4498 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4499 wr32(E1000_VT_CTL, vtctl); 4500 } 4501 if (adapter->rss_queues > 1) 4502 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4503 else 4504 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4505 } else { 4506 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4507 } 4508 igb_vmm_control(adapter); 4509 4510 wr32(E1000_MRQC, mrqc); 4511 } 4512 4513 /** 4514 * igb_setup_rctl - configure the receive control registers 4515 * @adapter: Board private structure 4516 **/ 4517 void igb_setup_rctl(struct igb_adapter *adapter) 4518 { 4519 struct e1000_hw *hw = &adapter->hw; 4520 u32 rctl; 4521 4522 rctl = rd32(E1000_RCTL); 4523 4524 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4525 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4526 4527 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4528 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4529 4530 /* enable stripping of CRC. It's unlikely this will break BMC 4531 * redirection as it did with e1000. Newer features require 4532 * that the HW strips the CRC. 4533 */ 4534 rctl |= E1000_RCTL_SECRC; 4535 4536 /* disable store bad packets and clear size bits. */ 4537 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4538 4539 /* enable LPE to allow for reception of jumbo frames */ 4540 rctl |= E1000_RCTL_LPE; 4541 4542 /* disable queue 0 to prevent tail write w/o re-config */ 4543 wr32(E1000_RXDCTL(0), 0); 4544 4545 /* Attention!!! For SR-IOV PF driver operations you must enable 4546 * queue drop for all VF and PF queues to prevent head of line blocking 4547 * if an un-trusted VF does not provide descriptors to hardware. 4548 */ 4549 if (adapter->vfs_allocated_count) { 4550 /* set all queue drop enable bits */ 4551 wr32(E1000_QDE, ALL_QUEUES); 4552 } 4553 4554 /* This is useful for sniffing bad packets. */ 4555 if (adapter->netdev->features & NETIF_F_RXALL) { 4556 /* UPE and MPE will be handled by normal PROMISC logic 4557 * in e1000e_set_rx_mode 4558 */ 4559 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4560 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4561 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4562 4563 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4564 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4565 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4566 * and that breaks VLANs. 4567 */ 4568 } 4569 4570 wr32(E1000_RCTL, rctl); 4571 } 4572 4573 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4574 int vfn) 4575 { 4576 struct e1000_hw *hw = &adapter->hw; 4577 u32 vmolr; 4578 4579 if (size > MAX_JUMBO_FRAME_SIZE) 4580 size = MAX_JUMBO_FRAME_SIZE; 4581 4582 vmolr = rd32(E1000_VMOLR(vfn)); 4583 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4584 vmolr |= size | E1000_VMOLR_LPE; 4585 wr32(E1000_VMOLR(vfn), vmolr); 4586 4587 return 0; 4588 } 4589 4590 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4591 int vfn, bool enable) 4592 { 4593 struct e1000_hw *hw = &adapter->hw; 4594 u32 val, reg; 4595 4596 if (hw->mac.type < e1000_82576) 4597 return; 4598 4599 if (hw->mac.type == e1000_i350) 4600 reg = E1000_DVMOLR(vfn); 4601 else 4602 reg = E1000_VMOLR(vfn); 4603 4604 val = rd32(reg); 4605 if (enable) 4606 val |= E1000_VMOLR_STRVLAN; 4607 else 4608 val &= ~(E1000_VMOLR_STRVLAN); 4609 wr32(reg, val); 4610 } 4611 4612 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4613 int vfn, bool aupe) 4614 { 4615 struct e1000_hw *hw = &adapter->hw; 4616 u32 vmolr; 4617 4618 /* This register exists only on 82576 and newer so if we are older then 4619 * we should exit and do nothing 4620 */ 4621 if (hw->mac.type < e1000_82576) 4622 return; 4623 4624 vmolr = rd32(E1000_VMOLR(vfn)); 4625 if (aupe) 4626 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4627 else 4628 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4629 4630 /* clear all bits that might not be set */ 4631 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4632 4633 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4634 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4635 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4636 * multicast packets 4637 */ 4638 if (vfn <= adapter->vfs_allocated_count) 4639 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4640 4641 wr32(E1000_VMOLR(vfn), vmolr); 4642 } 4643 4644 /** 4645 * igb_setup_srrctl - configure the split and replication receive control 4646 * registers 4647 * @adapter: Board private structure 4648 * @ring: receive ring to be configured 4649 **/ 4650 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4651 { 4652 struct e1000_hw *hw = &adapter->hw; 4653 int reg_idx = ring->reg_idx; 4654 u32 srrctl = 0; 4655 4656 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4657 if (ring_uses_large_buffer(ring)) 4658 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4659 else 4660 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4661 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4662 if (hw->mac.type >= e1000_82580) 4663 srrctl |= E1000_SRRCTL_TIMESTAMP; 4664 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4665 * queues and rx flow control is disabled 4666 */ 4667 if (adapter->vfs_allocated_count || 4668 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4669 adapter->num_rx_queues > 1)) 4670 srrctl |= E1000_SRRCTL_DROP_EN; 4671 4672 wr32(E1000_SRRCTL(reg_idx), srrctl); 4673 } 4674 4675 /** 4676 * igb_configure_rx_ring - Configure a receive ring after Reset 4677 * @adapter: board private structure 4678 * @ring: receive ring to be configured 4679 * 4680 * Configure the Rx unit of the MAC after a reset. 4681 **/ 4682 void igb_configure_rx_ring(struct igb_adapter *adapter, 4683 struct igb_ring *ring) 4684 { 4685 struct e1000_hw *hw = &adapter->hw; 4686 union e1000_adv_rx_desc *rx_desc; 4687 u64 rdba = ring->dma; 4688 int reg_idx = ring->reg_idx; 4689 u32 rxdctl = 0; 4690 4691 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4692 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4693 MEM_TYPE_PAGE_SHARED, NULL)); 4694 4695 /* disable the queue */ 4696 wr32(E1000_RXDCTL(reg_idx), 0); 4697 4698 /* Set DMA base address registers */ 4699 wr32(E1000_RDBAL(reg_idx), 4700 rdba & 0x00000000ffffffffULL); 4701 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4702 wr32(E1000_RDLEN(reg_idx), 4703 ring->count * sizeof(union e1000_adv_rx_desc)); 4704 4705 /* initialize head and tail */ 4706 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4707 wr32(E1000_RDH(reg_idx), 0); 4708 writel(0, ring->tail); 4709 4710 /* set descriptor configuration */ 4711 igb_setup_srrctl(adapter, ring); 4712 4713 /* set filtering for VMDQ pools */ 4714 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4715 4716 rxdctl |= IGB_RX_PTHRESH; 4717 rxdctl |= IGB_RX_HTHRESH << 8; 4718 rxdctl |= IGB_RX_WTHRESH << 16; 4719 4720 /* initialize rx_buffer_info */ 4721 memset(ring->rx_buffer_info, 0, 4722 sizeof(struct igb_rx_buffer) * ring->count); 4723 4724 /* initialize Rx descriptor 0 */ 4725 rx_desc = IGB_RX_DESC(ring, 0); 4726 rx_desc->wb.upper.length = 0; 4727 4728 /* enable receive descriptor fetching */ 4729 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4730 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4731 } 4732 4733 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4734 struct igb_ring *rx_ring) 4735 { 4736 /* set build_skb and buffer size flags */ 4737 clear_ring_build_skb_enabled(rx_ring); 4738 clear_ring_uses_large_buffer(rx_ring); 4739 4740 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4741 return; 4742 4743 set_ring_build_skb_enabled(rx_ring); 4744 4745 #if (PAGE_SIZE < 8192) 4746 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4747 return; 4748 4749 set_ring_uses_large_buffer(rx_ring); 4750 #endif 4751 } 4752 4753 /** 4754 * igb_configure_rx - Configure receive Unit after Reset 4755 * @adapter: board private structure 4756 * 4757 * Configure the Rx unit of the MAC after a reset. 4758 **/ 4759 static void igb_configure_rx(struct igb_adapter *adapter) 4760 { 4761 int i; 4762 4763 /* set the correct pool for the PF default MAC address in entry 0 */ 4764 igb_set_default_mac_filter(adapter); 4765 4766 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4767 * the Base and Length of the Rx Descriptor Ring 4768 */ 4769 for (i = 0; i < adapter->num_rx_queues; i++) { 4770 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4771 4772 igb_set_rx_buffer_len(adapter, rx_ring); 4773 igb_configure_rx_ring(adapter, rx_ring); 4774 } 4775 } 4776 4777 /** 4778 * igb_free_tx_resources - Free Tx Resources per Queue 4779 * @tx_ring: Tx descriptor ring for a specific queue 4780 * 4781 * Free all transmit software resources 4782 **/ 4783 void igb_free_tx_resources(struct igb_ring *tx_ring) 4784 { 4785 igb_clean_tx_ring(tx_ring); 4786 4787 vfree(tx_ring->tx_buffer_info); 4788 tx_ring->tx_buffer_info = NULL; 4789 4790 /* if not set, then don't free */ 4791 if (!tx_ring->desc) 4792 return; 4793 4794 dma_free_coherent(tx_ring->dev, tx_ring->size, 4795 tx_ring->desc, tx_ring->dma); 4796 4797 tx_ring->desc = NULL; 4798 } 4799 4800 /** 4801 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4802 * @adapter: board private structure 4803 * 4804 * Free all transmit software resources 4805 **/ 4806 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4807 { 4808 int i; 4809 4810 for (i = 0; i < adapter->num_tx_queues; i++) 4811 if (adapter->tx_ring[i]) 4812 igb_free_tx_resources(adapter->tx_ring[i]); 4813 } 4814 4815 /** 4816 * igb_clean_tx_ring - Free Tx Buffers 4817 * @tx_ring: ring to be cleaned 4818 **/ 4819 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4820 { 4821 u16 i = tx_ring->next_to_clean; 4822 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4823 4824 while (i != tx_ring->next_to_use) { 4825 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4826 4827 /* Free all the Tx ring sk_buffs or xdp frames */ 4828 if (tx_buffer->type == IGB_TYPE_SKB) 4829 dev_kfree_skb_any(tx_buffer->skb); 4830 else 4831 xdp_return_frame(tx_buffer->xdpf); 4832 4833 /* unmap skb header data */ 4834 dma_unmap_single(tx_ring->dev, 4835 dma_unmap_addr(tx_buffer, dma), 4836 dma_unmap_len(tx_buffer, len), 4837 DMA_TO_DEVICE); 4838 4839 /* check for eop_desc to determine the end of the packet */ 4840 eop_desc = tx_buffer->next_to_watch; 4841 tx_desc = IGB_TX_DESC(tx_ring, i); 4842 4843 /* unmap remaining buffers */ 4844 while (tx_desc != eop_desc) { 4845 tx_buffer++; 4846 tx_desc++; 4847 i++; 4848 if (unlikely(i == tx_ring->count)) { 4849 i = 0; 4850 tx_buffer = tx_ring->tx_buffer_info; 4851 tx_desc = IGB_TX_DESC(tx_ring, 0); 4852 } 4853 4854 /* unmap any remaining paged data */ 4855 if (dma_unmap_len(tx_buffer, len)) 4856 dma_unmap_page(tx_ring->dev, 4857 dma_unmap_addr(tx_buffer, dma), 4858 dma_unmap_len(tx_buffer, len), 4859 DMA_TO_DEVICE); 4860 } 4861 4862 tx_buffer->next_to_watch = NULL; 4863 4864 /* move us one more past the eop_desc for start of next pkt */ 4865 tx_buffer++; 4866 i++; 4867 if (unlikely(i == tx_ring->count)) { 4868 i = 0; 4869 tx_buffer = tx_ring->tx_buffer_info; 4870 } 4871 } 4872 4873 /* reset BQL for queue */ 4874 netdev_tx_reset_queue(txring_txq(tx_ring)); 4875 4876 /* reset next_to_use and next_to_clean */ 4877 tx_ring->next_to_use = 0; 4878 tx_ring->next_to_clean = 0; 4879 } 4880 4881 /** 4882 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4883 * @adapter: board private structure 4884 **/ 4885 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4886 { 4887 int i; 4888 4889 for (i = 0; i < adapter->num_tx_queues; i++) 4890 if (adapter->tx_ring[i]) 4891 igb_clean_tx_ring(adapter->tx_ring[i]); 4892 } 4893 4894 /** 4895 * igb_free_rx_resources - Free Rx Resources 4896 * @rx_ring: ring to clean the resources from 4897 * 4898 * Free all receive software resources 4899 **/ 4900 void igb_free_rx_resources(struct igb_ring *rx_ring) 4901 { 4902 igb_clean_rx_ring(rx_ring); 4903 4904 rx_ring->xdp_prog = NULL; 4905 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4906 vfree(rx_ring->rx_buffer_info); 4907 rx_ring->rx_buffer_info = NULL; 4908 4909 /* if not set, then don't free */ 4910 if (!rx_ring->desc) 4911 return; 4912 4913 dma_free_coherent(rx_ring->dev, rx_ring->size, 4914 rx_ring->desc, rx_ring->dma); 4915 4916 rx_ring->desc = NULL; 4917 } 4918 4919 /** 4920 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4921 * @adapter: board private structure 4922 * 4923 * Free all receive software resources 4924 **/ 4925 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4926 { 4927 int i; 4928 4929 for (i = 0; i < adapter->num_rx_queues; i++) 4930 if (adapter->rx_ring[i]) 4931 igb_free_rx_resources(adapter->rx_ring[i]); 4932 } 4933 4934 /** 4935 * igb_clean_rx_ring - Free Rx Buffers per Queue 4936 * @rx_ring: ring to free buffers from 4937 **/ 4938 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4939 { 4940 u16 i = rx_ring->next_to_clean; 4941 4942 dev_kfree_skb(rx_ring->skb); 4943 rx_ring->skb = NULL; 4944 4945 /* Free all the Rx ring sk_buffs */ 4946 while (i != rx_ring->next_to_alloc) { 4947 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4948 4949 /* Invalidate cache lines that may have been written to by 4950 * device so that we avoid corrupting memory. 4951 */ 4952 dma_sync_single_range_for_cpu(rx_ring->dev, 4953 buffer_info->dma, 4954 buffer_info->page_offset, 4955 igb_rx_bufsz(rx_ring), 4956 DMA_FROM_DEVICE); 4957 4958 /* free resources associated with mapping */ 4959 dma_unmap_page_attrs(rx_ring->dev, 4960 buffer_info->dma, 4961 igb_rx_pg_size(rx_ring), 4962 DMA_FROM_DEVICE, 4963 IGB_RX_DMA_ATTR); 4964 __page_frag_cache_drain(buffer_info->page, 4965 buffer_info->pagecnt_bias); 4966 4967 i++; 4968 if (i == rx_ring->count) 4969 i = 0; 4970 } 4971 4972 rx_ring->next_to_alloc = 0; 4973 rx_ring->next_to_clean = 0; 4974 rx_ring->next_to_use = 0; 4975 } 4976 4977 /** 4978 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4979 * @adapter: board private structure 4980 **/ 4981 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4982 { 4983 int i; 4984 4985 for (i = 0; i < adapter->num_rx_queues; i++) 4986 if (adapter->rx_ring[i]) 4987 igb_clean_rx_ring(adapter->rx_ring[i]); 4988 } 4989 4990 /** 4991 * igb_set_mac - Change the Ethernet Address of the NIC 4992 * @netdev: network interface device structure 4993 * @p: pointer to an address structure 4994 * 4995 * Returns 0 on success, negative on failure 4996 **/ 4997 static int igb_set_mac(struct net_device *netdev, void *p) 4998 { 4999 struct igb_adapter *adapter = netdev_priv(netdev); 5000 struct e1000_hw *hw = &adapter->hw; 5001 struct sockaddr *addr = p; 5002 5003 if (!is_valid_ether_addr(addr->sa_data)) 5004 return -EADDRNOTAVAIL; 5005 5006 eth_hw_addr_set(netdev, addr->sa_data); 5007 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5008 5009 /* set the correct pool for the new PF MAC address in entry 0 */ 5010 igb_set_default_mac_filter(adapter); 5011 5012 return 0; 5013 } 5014 5015 /** 5016 * igb_write_mc_addr_list - write multicast addresses to MTA 5017 * @netdev: network interface device structure 5018 * 5019 * Writes multicast address list to the MTA hash table. 5020 * Returns: -ENOMEM on failure 5021 * 0 on no addresses written 5022 * X on writing X addresses to MTA 5023 **/ 5024 static int igb_write_mc_addr_list(struct net_device *netdev) 5025 { 5026 struct igb_adapter *adapter = netdev_priv(netdev); 5027 struct e1000_hw *hw = &adapter->hw; 5028 struct netdev_hw_addr *ha; 5029 u8 *mta_list; 5030 int i; 5031 5032 if (netdev_mc_empty(netdev)) { 5033 /* nothing to program, so clear mc list */ 5034 igb_update_mc_addr_list(hw, NULL, 0); 5035 igb_restore_vf_multicasts(adapter); 5036 return 0; 5037 } 5038 5039 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5040 if (!mta_list) 5041 return -ENOMEM; 5042 5043 /* The shared function expects a packed array of only addresses. */ 5044 i = 0; 5045 netdev_for_each_mc_addr(ha, netdev) 5046 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5047 5048 igb_update_mc_addr_list(hw, mta_list, i); 5049 kfree(mta_list); 5050 5051 return netdev_mc_count(netdev); 5052 } 5053 5054 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5055 { 5056 struct e1000_hw *hw = &adapter->hw; 5057 u32 i, pf_id; 5058 5059 switch (hw->mac.type) { 5060 case e1000_i210: 5061 case e1000_i211: 5062 case e1000_i350: 5063 /* VLAN filtering needed for VLAN prio filter */ 5064 if (adapter->netdev->features & NETIF_F_NTUPLE) 5065 break; 5066 fallthrough; 5067 case e1000_82576: 5068 case e1000_82580: 5069 case e1000_i354: 5070 /* VLAN filtering needed for pool filtering */ 5071 if (adapter->vfs_allocated_count) 5072 break; 5073 fallthrough; 5074 default: 5075 return 1; 5076 } 5077 5078 /* We are already in VLAN promisc, nothing to do */ 5079 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5080 return 0; 5081 5082 if (!adapter->vfs_allocated_count) 5083 goto set_vfta; 5084 5085 /* Add PF to all active pools */ 5086 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5087 5088 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5089 u32 vlvf = rd32(E1000_VLVF(i)); 5090 5091 vlvf |= BIT(pf_id); 5092 wr32(E1000_VLVF(i), vlvf); 5093 } 5094 5095 set_vfta: 5096 /* Set all bits in the VLAN filter table array */ 5097 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5098 hw->mac.ops.write_vfta(hw, i, ~0U); 5099 5100 /* Set flag so we don't redo unnecessary work */ 5101 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5102 5103 return 0; 5104 } 5105 5106 #define VFTA_BLOCK_SIZE 8 5107 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5108 { 5109 struct e1000_hw *hw = &adapter->hw; 5110 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5111 u32 vid_start = vfta_offset * 32; 5112 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5113 u32 i, vid, word, bits, pf_id; 5114 5115 /* guarantee that we don't scrub out management VLAN */ 5116 vid = adapter->mng_vlan_id; 5117 if (vid >= vid_start && vid < vid_end) 5118 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5119 5120 if (!adapter->vfs_allocated_count) 5121 goto set_vfta; 5122 5123 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5124 5125 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5126 u32 vlvf = rd32(E1000_VLVF(i)); 5127 5128 /* pull VLAN ID from VLVF */ 5129 vid = vlvf & VLAN_VID_MASK; 5130 5131 /* only concern ourselves with a certain range */ 5132 if (vid < vid_start || vid >= vid_end) 5133 continue; 5134 5135 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5136 /* record VLAN ID in VFTA */ 5137 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5138 5139 /* if PF is part of this then continue */ 5140 if (test_bit(vid, adapter->active_vlans)) 5141 continue; 5142 } 5143 5144 /* remove PF from the pool */ 5145 bits = ~BIT(pf_id); 5146 bits &= rd32(E1000_VLVF(i)); 5147 wr32(E1000_VLVF(i), bits); 5148 } 5149 5150 set_vfta: 5151 /* extract values from active_vlans and write back to VFTA */ 5152 for (i = VFTA_BLOCK_SIZE; i--;) { 5153 vid = (vfta_offset + i) * 32; 5154 word = vid / BITS_PER_LONG; 5155 bits = vid % BITS_PER_LONG; 5156 5157 vfta[i] |= adapter->active_vlans[word] >> bits; 5158 5159 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5160 } 5161 } 5162 5163 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5164 { 5165 u32 i; 5166 5167 /* We are not in VLAN promisc, nothing to do */ 5168 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5169 return; 5170 5171 /* Set flag so we don't redo unnecessary work */ 5172 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5173 5174 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5175 igb_scrub_vfta(adapter, i); 5176 } 5177 5178 /** 5179 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5180 * @netdev: network interface device structure 5181 * 5182 * The set_rx_mode entry point is called whenever the unicast or multicast 5183 * address lists or the network interface flags are updated. This routine is 5184 * responsible for configuring the hardware for proper unicast, multicast, 5185 * promiscuous mode, and all-multi behavior. 5186 **/ 5187 static void igb_set_rx_mode(struct net_device *netdev) 5188 { 5189 struct igb_adapter *adapter = netdev_priv(netdev); 5190 struct e1000_hw *hw = &adapter->hw; 5191 unsigned int vfn = adapter->vfs_allocated_count; 5192 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5193 int count; 5194 5195 /* Check for Promiscuous and All Multicast modes */ 5196 if (netdev->flags & IFF_PROMISC) { 5197 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5198 vmolr |= E1000_VMOLR_MPME; 5199 5200 /* enable use of UTA filter to force packets to default pool */ 5201 if (hw->mac.type == e1000_82576) 5202 vmolr |= E1000_VMOLR_ROPE; 5203 } else { 5204 if (netdev->flags & IFF_ALLMULTI) { 5205 rctl |= E1000_RCTL_MPE; 5206 vmolr |= E1000_VMOLR_MPME; 5207 } else { 5208 /* Write addresses to the MTA, if the attempt fails 5209 * then we should just turn on promiscuous mode so 5210 * that we can at least receive multicast traffic 5211 */ 5212 count = igb_write_mc_addr_list(netdev); 5213 if (count < 0) { 5214 rctl |= E1000_RCTL_MPE; 5215 vmolr |= E1000_VMOLR_MPME; 5216 } else if (count) { 5217 vmolr |= E1000_VMOLR_ROMPE; 5218 } 5219 } 5220 } 5221 5222 /* Write addresses to available RAR registers, if there is not 5223 * sufficient space to store all the addresses then enable 5224 * unicast promiscuous mode 5225 */ 5226 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5227 rctl |= E1000_RCTL_UPE; 5228 vmolr |= E1000_VMOLR_ROPE; 5229 } 5230 5231 /* enable VLAN filtering by default */ 5232 rctl |= E1000_RCTL_VFE; 5233 5234 /* disable VLAN filtering for modes that require it */ 5235 if ((netdev->flags & IFF_PROMISC) || 5236 (netdev->features & NETIF_F_RXALL)) { 5237 /* if we fail to set all rules then just clear VFE */ 5238 if (igb_vlan_promisc_enable(adapter)) 5239 rctl &= ~E1000_RCTL_VFE; 5240 } else { 5241 igb_vlan_promisc_disable(adapter); 5242 } 5243 5244 /* update state of unicast, multicast, and VLAN filtering modes */ 5245 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5246 E1000_RCTL_VFE); 5247 wr32(E1000_RCTL, rctl); 5248 5249 #if (PAGE_SIZE < 8192) 5250 if (!adapter->vfs_allocated_count) { 5251 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5252 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5253 } 5254 #endif 5255 wr32(E1000_RLPML, rlpml); 5256 5257 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5258 * the VMOLR to enable the appropriate modes. Without this workaround 5259 * we will have issues with VLAN tag stripping not being done for frames 5260 * that are only arriving because we are the default pool 5261 */ 5262 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5263 return; 5264 5265 /* set UTA to appropriate mode */ 5266 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5267 5268 vmolr |= rd32(E1000_VMOLR(vfn)) & 5269 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5270 5271 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5272 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5273 #if (PAGE_SIZE < 8192) 5274 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5275 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5276 else 5277 #endif 5278 vmolr |= MAX_JUMBO_FRAME_SIZE; 5279 vmolr |= E1000_VMOLR_LPE; 5280 5281 wr32(E1000_VMOLR(vfn), vmolr); 5282 5283 igb_restore_vf_multicasts(adapter); 5284 } 5285 5286 static void igb_check_wvbr(struct igb_adapter *adapter) 5287 { 5288 struct e1000_hw *hw = &adapter->hw; 5289 u32 wvbr = 0; 5290 5291 switch (hw->mac.type) { 5292 case e1000_82576: 5293 case e1000_i350: 5294 wvbr = rd32(E1000_WVBR); 5295 if (!wvbr) 5296 return; 5297 break; 5298 default: 5299 break; 5300 } 5301 5302 adapter->wvbr |= wvbr; 5303 } 5304 5305 #define IGB_STAGGERED_QUEUE_OFFSET 8 5306 5307 static void igb_spoof_check(struct igb_adapter *adapter) 5308 { 5309 int j; 5310 5311 if (!adapter->wvbr) 5312 return; 5313 5314 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5315 if (adapter->wvbr & BIT(j) || 5316 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5317 dev_warn(&adapter->pdev->dev, 5318 "Spoof event(s) detected on VF %d\n", j); 5319 adapter->wvbr &= 5320 ~(BIT(j) | 5321 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5322 } 5323 } 5324 } 5325 5326 /* Need to wait a few seconds after link up to get diagnostic information from 5327 * the phy 5328 */ 5329 static void igb_update_phy_info(struct timer_list *t) 5330 { 5331 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5332 igb_get_phy_info(&adapter->hw); 5333 } 5334 5335 /** 5336 * igb_has_link - check shared code for link and determine up/down 5337 * @adapter: pointer to driver private info 5338 **/ 5339 bool igb_has_link(struct igb_adapter *adapter) 5340 { 5341 struct e1000_hw *hw = &adapter->hw; 5342 bool link_active = false; 5343 5344 /* get_link_status is set on LSC (link status) interrupt or 5345 * rx sequence error interrupt. get_link_status will stay 5346 * false until the e1000_check_for_link establishes link 5347 * for copper adapters ONLY 5348 */ 5349 switch (hw->phy.media_type) { 5350 case e1000_media_type_copper: 5351 if (!hw->mac.get_link_status) 5352 return true; 5353 fallthrough; 5354 case e1000_media_type_internal_serdes: 5355 hw->mac.ops.check_for_link(hw); 5356 link_active = !hw->mac.get_link_status; 5357 break; 5358 default: 5359 case e1000_media_type_unknown: 5360 break; 5361 } 5362 5363 if (((hw->mac.type == e1000_i210) || 5364 (hw->mac.type == e1000_i211)) && 5365 (hw->phy.id == I210_I_PHY_ID)) { 5366 if (!netif_carrier_ok(adapter->netdev)) { 5367 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5368 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5369 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5370 adapter->link_check_timeout = jiffies; 5371 } 5372 } 5373 5374 return link_active; 5375 } 5376 5377 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5378 { 5379 bool ret = false; 5380 u32 ctrl_ext, thstat; 5381 5382 /* check for thermal sensor event on i350 copper only */ 5383 if (hw->mac.type == e1000_i350) { 5384 thstat = rd32(E1000_THSTAT); 5385 ctrl_ext = rd32(E1000_CTRL_EXT); 5386 5387 if ((hw->phy.media_type == e1000_media_type_copper) && 5388 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5389 ret = !!(thstat & event); 5390 } 5391 5392 return ret; 5393 } 5394 5395 /** 5396 * igb_check_lvmmc - check for malformed packets received 5397 * and indicated in LVMMC register 5398 * @adapter: pointer to adapter 5399 **/ 5400 static void igb_check_lvmmc(struct igb_adapter *adapter) 5401 { 5402 struct e1000_hw *hw = &adapter->hw; 5403 u32 lvmmc; 5404 5405 lvmmc = rd32(E1000_LVMMC); 5406 if (lvmmc) { 5407 if (unlikely(net_ratelimit())) { 5408 netdev_warn(adapter->netdev, 5409 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5410 lvmmc); 5411 } 5412 } 5413 } 5414 5415 /** 5416 * igb_watchdog - Timer Call-back 5417 * @t: pointer to timer_list containing our private info pointer 5418 **/ 5419 static void igb_watchdog(struct timer_list *t) 5420 { 5421 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5422 /* Do the rest outside of interrupt context */ 5423 schedule_work(&adapter->watchdog_task); 5424 } 5425 5426 static void igb_watchdog_task(struct work_struct *work) 5427 { 5428 struct igb_adapter *adapter = container_of(work, 5429 struct igb_adapter, 5430 watchdog_task); 5431 struct e1000_hw *hw = &adapter->hw; 5432 struct e1000_phy_info *phy = &hw->phy; 5433 struct net_device *netdev = adapter->netdev; 5434 u32 link; 5435 int i; 5436 u32 connsw; 5437 u16 phy_data, retry_count = 20; 5438 5439 link = igb_has_link(adapter); 5440 5441 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5442 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5443 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5444 else 5445 link = false; 5446 } 5447 5448 /* Force link down if we have fiber to swap to */ 5449 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5450 if (hw->phy.media_type == e1000_media_type_copper) { 5451 connsw = rd32(E1000_CONNSW); 5452 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5453 link = 0; 5454 } 5455 } 5456 if (link) { 5457 /* Perform a reset if the media type changed. */ 5458 if (hw->dev_spec._82575.media_changed) { 5459 hw->dev_spec._82575.media_changed = false; 5460 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5461 igb_reset(adapter); 5462 } 5463 /* Cancel scheduled suspend requests. */ 5464 pm_runtime_resume(netdev->dev.parent); 5465 5466 if (!netif_carrier_ok(netdev)) { 5467 u32 ctrl; 5468 5469 hw->mac.ops.get_speed_and_duplex(hw, 5470 &adapter->link_speed, 5471 &adapter->link_duplex); 5472 5473 ctrl = rd32(E1000_CTRL); 5474 /* Links status message must follow this format */ 5475 netdev_info(netdev, 5476 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5477 netdev->name, 5478 adapter->link_speed, 5479 adapter->link_duplex == FULL_DUPLEX ? 5480 "Full" : "Half", 5481 (ctrl & E1000_CTRL_TFCE) && 5482 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5483 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5484 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5485 5486 /* disable EEE if enabled */ 5487 if ((adapter->flags & IGB_FLAG_EEE) && 5488 (adapter->link_duplex == HALF_DUPLEX)) { 5489 dev_info(&adapter->pdev->dev, 5490 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5491 adapter->hw.dev_spec._82575.eee_disable = true; 5492 adapter->flags &= ~IGB_FLAG_EEE; 5493 } 5494 5495 /* check if SmartSpeed worked */ 5496 igb_check_downshift(hw); 5497 if (phy->speed_downgraded) 5498 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5499 5500 /* check for thermal sensor event */ 5501 if (igb_thermal_sensor_event(hw, 5502 E1000_THSTAT_LINK_THROTTLE)) 5503 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5504 5505 /* adjust timeout factor according to speed/duplex */ 5506 adapter->tx_timeout_factor = 1; 5507 switch (adapter->link_speed) { 5508 case SPEED_10: 5509 adapter->tx_timeout_factor = 14; 5510 break; 5511 case SPEED_100: 5512 /* maybe add some timeout factor ? */ 5513 break; 5514 } 5515 5516 if (adapter->link_speed != SPEED_1000 || 5517 !hw->phy.ops.read_reg) 5518 goto no_wait; 5519 5520 /* wait for Remote receiver status OK */ 5521 retry_read_status: 5522 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5523 &phy_data)) { 5524 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5525 retry_count) { 5526 msleep(100); 5527 retry_count--; 5528 goto retry_read_status; 5529 } else if (!retry_count) { 5530 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5531 } 5532 } else { 5533 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5534 } 5535 no_wait: 5536 netif_carrier_on(netdev); 5537 5538 igb_ping_all_vfs(adapter); 5539 igb_check_vf_rate_limit(adapter); 5540 5541 /* link state has changed, schedule phy info update */ 5542 if (!test_bit(__IGB_DOWN, &adapter->state)) 5543 mod_timer(&adapter->phy_info_timer, 5544 round_jiffies(jiffies + 2 * HZ)); 5545 } 5546 } else { 5547 if (netif_carrier_ok(netdev)) { 5548 adapter->link_speed = 0; 5549 adapter->link_duplex = 0; 5550 5551 /* check for thermal sensor event */ 5552 if (igb_thermal_sensor_event(hw, 5553 E1000_THSTAT_PWR_DOWN)) { 5554 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5555 } 5556 5557 /* Links status message must follow this format */ 5558 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5559 netdev->name); 5560 netif_carrier_off(netdev); 5561 5562 igb_ping_all_vfs(adapter); 5563 5564 /* link state has changed, schedule phy info update */ 5565 if (!test_bit(__IGB_DOWN, &adapter->state)) 5566 mod_timer(&adapter->phy_info_timer, 5567 round_jiffies(jiffies + 2 * HZ)); 5568 5569 /* link is down, time to check for alternate media */ 5570 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5571 igb_check_swap_media(adapter); 5572 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5573 schedule_work(&adapter->reset_task); 5574 /* return immediately */ 5575 return; 5576 } 5577 } 5578 pm_schedule_suspend(netdev->dev.parent, 5579 MSEC_PER_SEC * 5); 5580 5581 /* also check for alternate media here */ 5582 } else if (!netif_carrier_ok(netdev) && 5583 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5584 igb_check_swap_media(adapter); 5585 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5586 schedule_work(&adapter->reset_task); 5587 /* return immediately */ 5588 return; 5589 } 5590 } 5591 } 5592 5593 spin_lock(&adapter->stats64_lock); 5594 igb_update_stats(adapter); 5595 spin_unlock(&adapter->stats64_lock); 5596 5597 for (i = 0; i < adapter->num_tx_queues; i++) { 5598 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5599 if (!netif_carrier_ok(netdev)) { 5600 /* We've lost link, so the controller stops DMA, 5601 * but we've got queued Tx work that's never going 5602 * to get done, so reset controller to flush Tx. 5603 * (Do the reset outside of interrupt context). 5604 */ 5605 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5606 adapter->tx_timeout_count++; 5607 schedule_work(&adapter->reset_task); 5608 /* return immediately since reset is imminent */ 5609 return; 5610 } 5611 } 5612 5613 /* Force detection of hung controller every watchdog period */ 5614 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5615 } 5616 5617 /* Cause software interrupt to ensure Rx ring is cleaned */ 5618 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5619 u32 eics = 0; 5620 5621 for (i = 0; i < adapter->num_q_vectors; i++) 5622 eics |= adapter->q_vector[i]->eims_value; 5623 wr32(E1000_EICS, eics); 5624 } else { 5625 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5626 } 5627 5628 igb_spoof_check(adapter); 5629 igb_ptp_rx_hang(adapter); 5630 igb_ptp_tx_hang(adapter); 5631 5632 /* Check LVMMC register on i350/i354 only */ 5633 if ((adapter->hw.mac.type == e1000_i350) || 5634 (adapter->hw.mac.type == e1000_i354)) 5635 igb_check_lvmmc(adapter); 5636 5637 /* Reset the timer */ 5638 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5639 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5640 mod_timer(&adapter->watchdog_timer, 5641 round_jiffies(jiffies + HZ)); 5642 else 5643 mod_timer(&adapter->watchdog_timer, 5644 round_jiffies(jiffies + 2 * HZ)); 5645 } 5646 } 5647 5648 enum latency_range { 5649 lowest_latency = 0, 5650 low_latency = 1, 5651 bulk_latency = 2, 5652 latency_invalid = 255 5653 }; 5654 5655 /** 5656 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5657 * @q_vector: pointer to q_vector 5658 * 5659 * Stores a new ITR value based on strictly on packet size. This 5660 * algorithm is less sophisticated than that used in igb_update_itr, 5661 * due to the difficulty of synchronizing statistics across multiple 5662 * receive rings. The divisors and thresholds used by this function 5663 * were determined based on theoretical maximum wire speed and testing 5664 * data, in order to minimize response time while increasing bulk 5665 * throughput. 5666 * This functionality is controlled by ethtool's coalescing settings. 5667 * NOTE: This function is called only when operating in a multiqueue 5668 * receive environment. 5669 **/ 5670 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5671 { 5672 int new_val = q_vector->itr_val; 5673 int avg_wire_size = 0; 5674 struct igb_adapter *adapter = q_vector->adapter; 5675 unsigned int packets; 5676 5677 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5678 * ints/sec - ITR timer value of 120 ticks. 5679 */ 5680 if (adapter->link_speed != SPEED_1000) { 5681 new_val = IGB_4K_ITR; 5682 goto set_itr_val; 5683 } 5684 5685 packets = q_vector->rx.total_packets; 5686 if (packets) 5687 avg_wire_size = q_vector->rx.total_bytes / packets; 5688 5689 packets = q_vector->tx.total_packets; 5690 if (packets) 5691 avg_wire_size = max_t(u32, avg_wire_size, 5692 q_vector->tx.total_bytes / packets); 5693 5694 /* if avg_wire_size isn't set no work was done */ 5695 if (!avg_wire_size) 5696 goto clear_counts; 5697 5698 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5699 avg_wire_size += 24; 5700 5701 /* Don't starve jumbo frames */ 5702 avg_wire_size = min(avg_wire_size, 3000); 5703 5704 /* Give a little boost to mid-size frames */ 5705 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5706 new_val = avg_wire_size / 3; 5707 else 5708 new_val = avg_wire_size / 2; 5709 5710 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5711 if (new_val < IGB_20K_ITR && 5712 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5713 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5714 new_val = IGB_20K_ITR; 5715 5716 set_itr_val: 5717 if (new_val != q_vector->itr_val) { 5718 q_vector->itr_val = new_val; 5719 q_vector->set_itr = 1; 5720 } 5721 clear_counts: 5722 q_vector->rx.total_bytes = 0; 5723 q_vector->rx.total_packets = 0; 5724 q_vector->tx.total_bytes = 0; 5725 q_vector->tx.total_packets = 0; 5726 } 5727 5728 /** 5729 * igb_update_itr - update the dynamic ITR value based on statistics 5730 * @q_vector: pointer to q_vector 5731 * @ring_container: ring info to update the itr for 5732 * 5733 * Stores a new ITR value based on packets and byte 5734 * counts during the last interrupt. The advantage of per interrupt 5735 * computation is faster updates and more accurate ITR for the current 5736 * traffic pattern. Constants in this function were computed 5737 * based on theoretical maximum wire speed and thresholds were set based 5738 * on testing data as well as attempting to minimize response time 5739 * while increasing bulk throughput. 5740 * This functionality is controlled by ethtool's coalescing settings. 5741 * NOTE: These calculations are only valid when operating in a single- 5742 * queue environment. 5743 **/ 5744 static void igb_update_itr(struct igb_q_vector *q_vector, 5745 struct igb_ring_container *ring_container) 5746 { 5747 unsigned int packets = ring_container->total_packets; 5748 unsigned int bytes = ring_container->total_bytes; 5749 u8 itrval = ring_container->itr; 5750 5751 /* no packets, exit with status unchanged */ 5752 if (packets == 0) 5753 return; 5754 5755 switch (itrval) { 5756 case lowest_latency: 5757 /* handle TSO and jumbo frames */ 5758 if (bytes/packets > 8000) 5759 itrval = bulk_latency; 5760 else if ((packets < 5) && (bytes > 512)) 5761 itrval = low_latency; 5762 break; 5763 case low_latency: /* 50 usec aka 20000 ints/s */ 5764 if (bytes > 10000) { 5765 /* this if handles the TSO accounting */ 5766 if (bytes/packets > 8000) 5767 itrval = bulk_latency; 5768 else if ((packets < 10) || ((bytes/packets) > 1200)) 5769 itrval = bulk_latency; 5770 else if ((packets > 35)) 5771 itrval = lowest_latency; 5772 } else if (bytes/packets > 2000) { 5773 itrval = bulk_latency; 5774 } else if (packets <= 2 && bytes < 512) { 5775 itrval = lowest_latency; 5776 } 5777 break; 5778 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5779 if (bytes > 25000) { 5780 if (packets > 35) 5781 itrval = low_latency; 5782 } else if (bytes < 1500) { 5783 itrval = low_latency; 5784 } 5785 break; 5786 } 5787 5788 /* clear work counters since we have the values we need */ 5789 ring_container->total_bytes = 0; 5790 ring_container->total_packets = 0; 5791 5792 /* write updated itr to ring container */ 5793 ring_container->itr = itrval; 5794 } 5795 5796 static void igb_set_itr(struct igb_q_vector *q_vector) 5797 { 5798 struct igb_adapter *adapter = q_vector->adapter; 5799 u32 new_itr = q_vector->itr_val; 5800 u8 current_itr = 0; 5801 5802 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5803 if (adapter->link_speed != SPEED_1000) { 5804 current_itr = 0; 5805 new_itr = IGB_4K_ITR; 5806 goto set_itr_now; 5807 } 5808 5809 igb_update_itr(q_vector, &q_vector->tx); 5810 igb_update_itr(q_vector, &q_vector->rx); 5811 5812 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5813 5814 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5815 if (current_itr == lowest_latency && 5816 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5817 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5818 current_itr = low_latency; 5819 5820 switch (current_itr) { 5821 /* counts and packets in update_itr are dependent on these numbers */ 5822 case lowest_latency: 5823 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5824 break; 5825 case low_latency: 5826 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5827 break; 5828 case bulk_latency: 5829 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5830 break; 5831 default: 5832 break; 5833 } 5834 5835 set_itr_now: 5836 if (new_itr != q_vector->itr_val) { 5837 /* this attempts to bias the interrupt rate towards Bulk 5838 * by adding intermediate steps when interrupt rate is 5839 * increasing 5840 */ 5841 new_itr = new_itr > q_vector->itr_val ? 5842 max((new_itr * q_vector->itr_val) / 5843 (new_itr + (q_vector->itr_val >> 2)), 5844 new_itr) : new_itr; 5845 /* Don't write the value here; it resets the adapter's 5846 * internal timer, and causes us to delay far longer than 5847 * we should between interrupts. Instead, we write the ITR 5848 * value at the beginning of the next interrupt so the timing 5849 * ends up being correct. 5850 */ 5851 q_vector->itr_val = new_itr; 5852 q_vector->set_itr = 1; 5853 } 5854 } 5855 5856 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5857 struct igb_tx_buffer *first, 5858 u32 vlan_macip_lens, u32 type_tucmd, 5859 u32 mss_l4len_idx) 5860 { 5861 struct e1000_adv_tx_context_desc *context_desc; 5862 u16 i = tx_ring->next_to_use; 5863 struct timespec64 ts; 5864 5865 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5866 5867 i++; 5868 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5869 5870 /* set bits to identify this as an advanced context descriptor */ 5871 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5872 5873 /* For 82575, context index must be unique per ring. */ 5874 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5875 mss_l4len_idx |= tx_ring->reg_idx << 4; 5876 5877 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5878 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5879 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5880 5881 /* We assume there is always a valid tx time available. Invalid times 5882 * should have been handled by the upper layers. 5883 */ 5884 if (tx_ring->launchtime_enable) { 5885 ts = ktime_to_timespec64(first->skb->tstamp); 5886 skb_txtime_consumed(first->skb); 5887 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5888 } else { 5889 context_desc->seqnum_seed = 0; 5890 } 5891 } 5892 5893 static int igb_tso(struct igb_ring *tx_ring, 5894 struct igb_tx_buffer *first, 5895 u8 *hdr_len) 5896 { 5897 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5898 struct sk_buff *skb = first->skb; 5899 union { 5900 struct iphdr *v4; 5901 struct ipv6hdr *v6; 5902 unsigned char *hdr; 5903 } ip; 5904 union { 5905 struct tcphdr *tcp; 5906 struct udphdr *udp; 5907 unsigned char *hdr; 5908 } l4; 5909 u32 paylen, l4_offset; 5910 int err; 5911 5912 if (skb->ip_summed != CHECKSUM_PARTIAL) 5913 return 0; 5914 5915 if (!skb_is_gso(skb)) 5916 return 0; 5917 5918 err = skb_cow_head(skb, 0); 5919 if (err < 0) 5920 return err; 5921 5922 ip.hdr = skb_network_header(skb); 5923 l4.hdr = skb_checksum_start(skb); 5924 5925 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5926 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5927 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5928 5929 /* initialize outer IP header fields */ 5930 if (ip.v4->version == 4) { 5931 unsigned char *csum_start = skb_checksum_start(skb); 5932 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5933 5934 /* IP header will have to cancel out any data that 5935 * is not a part of the outer IP header 5936 */ 5937 ip.v4->check = csum_fold(csum_partial(trans_start, 5938 csum_start - trans_start, 5939 0)); 5940 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5941 5942 ip.v4->tot_len = 0; 5943 first->tx_flags |= IGB_TX_FLAGS_TSO | 5944 IGB_TX_FLAGS_CSUM | 5945 IGB_TX_FLAGS_IPV4; 5946 } else { 5947 ip.v6->payload_len = 0; 5948 first->tx_flags |= IGB_TX_FLAGS_TSO | 5949 IGB_TX_FLAGS_CSUM; 5950 } 5951 5952 /* determine offset of inner transport header */ 5953 l4_offset = l4.hdr - skb->data; 5954 5955 /* remove payload length from inner checksum */ 5956 paylen = skb->len - l4_offset; 5957 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5958 /* compute length of segmentation header */ 5959 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5960 csum_replace_by_diff(&l4.tcp->check, 5961 (__force __wsum)htonl(paylen)); 5962 } else { 5963 /* compute length of segmentation header */ 5964 *hdr_len = sizeof(*l4.udp) + l4_offset; 5965 csum_replace_by_diff(&l4.udp->check, 5966 (__force __wsum)htonl(paylen)); 5967 } 5968 5969 /* update gso size and bytecount with header size */ 5970 first->gso_segs = skb_shinfo(skb)->gso_segs; 5971 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5972 5973 /* MSS L4LEN IDX */ 5974 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5975 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5976 5977 /* VLAN MACLEN IPLEN */ 5978 vlan_macip_lens = l4.hdr - ip.hdr; 5979 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5980 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5981 5982 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5983 type_tucmd, mss_l4len_idx); 5984 5985 return 1; 5986 } 5987 5988 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5989 { 5990 struct sk_buff *skb = first->skb; 5991 u32 vlan_macip_lens = 0; 5992 u32 type_tucmd = 0; 5993 5994 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5995 csum_failed: 5996 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5997 !tx_ring->launchtime_enable) 5998 return; 5999 goto no_csum; 6000 } 6001 6002 switch (skb->csum_offset) { 6003 case offsetof(struct tcphdr, check): 6004 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6005 fallthrough; 6006 case offsetof(struct udphdr, check): 6007 break; 6008 case offsetof(struct sctphdr, checksum): 6009 /* validate that this is actually an SCTP request */ 6010 if (skb_csum_is_sctp(skb)) { 6011 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6012 break; 6013 } 6014 fallthrough; 6015 default: 6016 skb_checksum_help(skb); 6017 goto csum_failed; 6018 } 6019 6020 /* update TX checksum flag */ 6021 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6022 vlan_macip_lens = skb_checksum_start_offset(skb) - 6023 skb_network_offset(skb); 6024 no_csum: 6025 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6026 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6027 6028 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6029 } 6030 6031 #define IGB_SET_FLAG(_input, _flag, _result) \ 6032 ((_flag <= _result) ? \ 6033 ((u32)(_input & _flag) * (_result / _flag)) : \ 6034 ((u32)(_input & _flag) / (_flag / _result))) 6035 6036 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6037 { 6038 /* set type for advanced descriptor with frame checksum insertion */ 6039 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6040 E1000_ADVTXD_DCMD_DEXT | 6041 E1000_ADVTXD_DCMD_IFCS; 6042 6043 /* set HW vlan bit if vlan is present */ 6044 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6045 (E1000_ADVTXD_DCMD_VLE)); 6046 6047 /* set segmentation bits for TSO */ 6048 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6049 (E1000_ADVTXD_DCMD_TSE)); 6050 6051 /* set timestamp bit if present */ 6052 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6053 (E1000_ADVTXD_MAC_TSTAMP)); 6054 6055 /* insert frame checksum */ 6056 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6057 6058 return cmd_type; 6059 } 6060 6061 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6062 union e1000_adv_tx_desc *tx_desc, 6063 u32 tx_flags, unsigned int paylen) 6064 { 6065 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6066 6067 /* 82575 requires a unique index per ring */ 6068 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6069 olinfo_status |= tx_ring->reg_idx << 4; 6070 6071 /* insert L4 checksum */ 6072 olinfo_status |= IGB_SET_FLAG(tx_flags, 6073 IGB_TX_FLAGS_CSUM, 6074 (E1000_TXD_POPTS_TXSM << 8)); 6075 6076 /* insert IPv4 checksum */ 6077 olinfo_status |= IGB_SET_FLAG(tx_flags, 6078 IGB_TX_FLAGS_IPV4, 6079 (E1000_TXD_POPTS_IXSM << 8)); 6080 6081 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6082 } 6083 6084 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6085 { 6086 struct net_device *netdev = tx_ring->netdev; 6087 6088 netif_stop_subqueue(netdev, tx_ring->queue_index); 6089 6090 /* Herbert's original patch had: 6091 * smp_mb__after_netif_stop_queue(); 6092 * but since that doesn't exist yet, just open code it. 6093 */ 6094 smp_mb(); 6095 6096 /* We need to check again in a case another CPU has just 6097 * made room available. 6098 */ 6099 if (igb_desc_unused(tx_ring) < size) 6100 return -EBUSY; 6101 6102 /* A reprieve! */ 6103 netif_wake_subqueue(netdev, tx_ring->queue_index); 6104 6105 u64_stats_update_begin(&tx_ring->tx_syncp2); 6106 tx_ring->tx_stats.restart_queue2++; 6107 u64_stats_update_end(&tx_ring->tx_syncp2); 6108 6109 return 0; 6110 } 6111 6112 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6113 { 6114 if (igb_desc_unused(tx_ring) >= size) 6115 return 0; 6116 return __igb_maybe_stop_tx(tx_ring, size); 6117 } 6118 6119 static int igb_tx_map(struct igb_ring *tx_ring, 6120 struct igb_tx_buffer *first, 6121 const u8 hdr_len) 6122 { 6123 struct sk_buff *skb = first->skb; 6124 struct igb_tx_buffer *tx_buffer; 6125 union e1000_adv_tx_desc *tx_desc; 6126 skb_frag_t *frag; 6127 dma_addr_t dma; 6128 unsigned int data_len, size; 6129 u32 tx_flags = first->tx_flags; 6130 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6131 u16 i = tx_ring->next_to_use; 6132 6133 tx_desc = IGB_TX_DESC(tx_ring, i); 6134 6135 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6136 6137 size = skb_headlen(skb); 6138 data_len = skb->data_len; 6139 6140 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6141 6142 tx_buffer = first; 6143 6144 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6145 if (dma_mapping_error(tx_ring->dev, dma)) 6146 goto dma_error; 6147 6148 /* record length, and DMA address */ 6149 dma_unmap_len_set(tx_buffer, len, size); 6150 dma_unmap_addr_set(tx_buffer, dma, dma); 6151 6152 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6153 6154 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6155 tx_desc->read.cmd_type_len = 6156 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6157 6158 i++; 6159 tx_desc++; 6160 if (i == tx_ring->count) { 6161 tx_desc = IGB_TX_DESC(tx_ring, 0); 6162 i = 0; 6163 } 6164 tx_desc->read.olinfo_status = 0; 6165 6166 dma += IGB_MAX_DATA_PER_TXD; 6167 size -= IGB_MAX_DATA_PER_TXD; 6168 6169 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6170 } 6171 6172 if (likely(!data_len)) 6173 break; 6174 6175 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6176 6177 i++; 6178 tx_desc++; 6179 if (i == tx_ring->count) { 6180 tx_desc = IGB_TX_DESC(tx_ring, 0); 6181 i = 0; 6182 } 6183 tx_desc->read.olinfo_status = 0; 6184 6185 size = skb_frag_size(frag); 6186 data_len -= size; 6187 6188 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6189 size, DMA_TO_DEVICE); 6190 6191 tx_buffer = &tx_ring->tx_buffer_info[i]; 6192 } 6193 6194 /* write last descriptor with RS and EOP bits */ 6195 cmd_type |= size | IGB_TXD_DCMD; 6196 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6197 6198 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6199 6200 /* set the timestamp */ 6201 first->time_stamp = jiffies; 6202 6203 skb_tx_timestamp(skb); 6204 6205 /* Force memory writes to complete before letting h/w know there 6206 * are new descriptors to fetch. (Only applicable for weak-ordered 6207 * memory model archs, such as IA-64). 6208 * 6209 * We also need this memory barrier to make certain all of the 6210 * status bits have been updated before next_to_watch is written. 6211 */ 6212 dma_wmb(); 6213 6214 /* set next_to_watch value indicating a packet is present */ 6215 first->next_to_watch = tx_desc; 6216 6217 i++; 6218 if (i == tx_ring->count) 6219 i = 0; 6220 6221 tx_ring->next_to_use = i; 6222 6223 /* Make sure there is space in the ring for the next send. */ 6224 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6225 6226 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6227 writel(i, tx_ring->tail); 6228 } 6229 return 0; 6230 6231 dma_error: 6232 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6233 tx_buffer = &tx_ring->tx_buffer_info[i]; 6234 6235 /* clear dma mappings for failed tx_buffer_info map */ 6236 while (tx_buffer != first) { 6237 if (dma_unmap_len(tx_buffer, len)) 6238 dma_unmap_page(tx_ring->dev, 6239 dma_unmap_addr(tx_buffer, dma), 6240 dma_unmap_len(tx_buffer, len), 6241 DMA_TO_DEVICE); 6242 dma_unmap_len_set(tx_buffer, len, 0); 6243 6244 if (i-- == 0) 6245 i += tx_ring->count; 6246 tx_buffer = &tx_ring->tx_buffer_info[i]; 6247 } 6248 6249 if (dma_unmap_len(tx_buffer, len)) 6250 dma_unmap_single(tx_ring->dev, 6251 dma_unmap_addr(tx_buffer, dma), 6252 dma_unmap_len(tx_buffer, len), 6253 DMA_TO_DEVICE); 6254 dma_unmap_len_set(tx_buffer, len, 0); 6255 6256 dev_kfree_skb_any(tx_buffer->skb); 6257 tx_buffer->skb = NULL; 6258 6259 tx_ring->next_to_use = i; 6260 6261 return -1; 6262 } 6263 6264 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6265 struct igb_ring *tx_ring, 6266 struct xdp_frame *xdpf) 6267 { 6268 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6269 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6270 u16 count, i, index = tx_ring->next_to_use; 6271 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6272 struct igb_tx_buffer *tx_buffer = tx_head; 6273 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6274 u32 len = xdpf->len, cmd_type, olinfo_status; 6275 void *data = xdpf->data; 6276 6277 count = TXD_USE_COUNT(len); 6278 for (i = 0; i < nr_frags; i++) 6279 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6280 6281 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6282 return IGB_XDP_CONSUMED; 6283 6284 i = 0; 6285 /* record the location of the first descriptor for this packet */ 6286 tx_head->bytecount = xdp_get_frame_len(xdpf); 6287 tx_head->type = IGB_TYPE_XDP; 6288 tx_head->gso_segs = 1; 6289 tx_head->xdpf = xdpf; 6290 6291 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6292 /* 82575 requires a unique index per ring */ 6293 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6294 olinfo_status |= tx_ring->reg_idx << 4; 6295 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6296 6297 for (;;) { 6298 dma_addr_t dma; 6299 6300 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6301 if (dma_mapping_error(tx_ring->dev, dma)) 6302 goto unmap; 6303 6304 /* record length, and DMA address */ 6305 dma_unmap_len_set(tx_buffer, len, len); 6306 dma_unmap_addr_set(tx_buffer, dma, dma); 6307 6308 /* put descriptor type bits */ 6309 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6310 E1000_ADVTXD_DCMD_IFCS | len; 6311 6312 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6313 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6314 6315 tx_buffer->protocol = 0; 6316 6317 if (++index == tx_ring->count) 6318 index = 0; 6319 6320 if (i == nr_frags) 6321 break; 6322 6323 tx_buffer = &tx_ring->tx_buffer_info[index]; 6324 tx_desc = IGB_TX_DESC(tx_ring, index); 6325 tx_desc->read.olinfo_status = 0; 6326 6327 data = skb_frag_address(&sinfo->frags[i]); 6328 len = skb_frag_size(&sinfo->frags[i]); 6329 i++; 6330 } 6331 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6332 6333 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6334 /* set the timestamp */ 6335 tx_head->time_stamp = jiffies; 6336 6337 /* Avoid any potential race with xdp_xmit and cleanup */ 6338 smp_wmb(); 6339 6340 /* set next_to_watch value indicating a packet is present */ 6341 tx_head->next_to_watch = tx_desc; 6342 tx_ring->next_to_use = index; 6343 6344 /* Make sure there is space in the ring for the next send. */ 6345 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6346 6347 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6348 writel(index, tx_ring->tail); 6349 6350 return IGB_XDP_TX; 6351 6352 unmap: 6353 for (;;) { 6354 tx_buffer = &tx_ring->tx_buffer_info[index]; 6355 if (dma_unmap_len(tx_buffer, len)) 6356 dma_unmap_page(tx_ring->dev, 6357 dma_unmap_addr(tx_buffer, dma), 6358 dma_unmap_len(tx_buffer, len), 6359 DMA_TO_DEVICE); 6360 dma_unmap_len_set(tx_buffer, len, 0); 6361 if (tx_buffer == tx_head) 6362 break; 6363 6364 if (!index) 6365 index += tx_ring->count; 6366 index--; 6367 } 6368 6369 return IGB_XDP_CONSUMED; 6370 } 6371 6372 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6373 struct igb_ring *tx_ring) 6374 { 6375 struct igb_tx_buffer *first; 6376 int tso; 6377 u32 tx_flags = 0; 6378 unsigned short f; 6379 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6380 __be16 protocol = vlan_get_protocol(skb); 6381 u8 hdr_len = 0; 6382 6383 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6384 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6385 * + 2 desc gap to keep tail from touching head, 6386 * + 1 desc for context descriptor, 6387 * otherwise try next time 6388 */ 6389 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6390 count += TXD_USE_COUNT(skb_frag_size( 6391 &skb_shinfo(skb)->frags[f])); 6392 6393 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6394 /* this is a hard error */ 6395 return NETDEV_TX_BUSY; 6396 } 6397 6398 /* record the location of the first descriptor for this packet */ 6399 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6400 first->type = IGB_TYPE_SKB; 6401 first->skb = skb; 6402 first->bytecount = skb->len; 6403 first->gso_segs = 1; 6404 6405 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6406 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6407 6408 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6409 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6410 &adapter->state)) { 6411 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6412 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6413 6414 adapter->ptp_tx_skb = skb_get(skb); 6415 adapter->ptp_tx_start = jiffies; 6416 if (adapter->hw.mac.type == e1000_82576) 6417 schedule_work(&adapter->ptp_tx_work); 6418 } else { 6419 adapter->tx_hwtstamp_skipped++; 6420 } 6421 } 6422 6423 if (skb_vlan_tag_present(skb)) { 6424 tx_flags |= IGB_TX_FLAGS_VLAN; 6425 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6426 } 6427 6428 /* record initial flags and protocol */ 6429 first->tx_flags = tx_flags; 6430 first->protocol = protocol; 6431 6432 tso = igb_tso(tx_ring, first, &hdr_len); 6433 if (tso < 0) 6434 goto out_drop; 6435 else if (!tso) 6436 igb_tx_csum(tx_ring, first); 6437 6438 if (igb_tx_map(tx_ring, first, hdr_len)) 6439 goto cleanup_tx_tstamp; 6440 6441 return NETDEV_TX_OK; 6442 6443 out_drop: 6444 dev_kfree_skb_any(first->skb); 6445 first->skb = NULL; 6446 cleanup_tx_tstamp: 6447 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6448 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6449 6450 dev_kfree_skb_any(adapter->ptp_tx_skb); 6451 adapter->ptp_tx_skb = NULL; 6452 if (adapter->hw.mac.type == e1000_82576) 6453 cancel_work_sync(&adapter->ptp_tx_work); 6454 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6455 } 6456 6457 return NETDEV_TX_OK; 6458 } 6459 6460 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6461 struct sk_buff *skb) 6462 { 6463 unsigned int r_idx = skb->queue_mapping; 6464 6465 if (r_idx >= adapter->num_tx_queues) 6466 r_idx = r_idx % adapter->num_tx_queues; 6467 6468 return adapter->tx_ring[r_idx]; 6469 } 6470 6471 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6472 struct net_device *netdev) 6473 { 6474 struct igb_adapter *adapter = netdev_priv(netdev); 6475 6476 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6477 * in order to meet this minimum size requirement. 6478 */ 6479 if (skb_put_padto(skb, 17)) 6480 return NETDEV_TX_OK; 6481 6482 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6483 } 6484 6485 /** 6486 * igb_tx_timeout - Respond to a Tx Hang 6487 * @netdev: network interface device structure 6488 * @txqueue: number of the Tx queue that hung (unused) 6489 **/ 6490 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6491 { 6492 struct igb_adapter *adapter = netdev_priv(netdev); 6493 struct e1000_hw *hw = &adapter->hw; 6494 6495 /* Do the reset outside of interrupt context */ 6496 adapter->tx_timeout_count++; 6497 6498 if (hw->mac.type >= e1000_82580) 6499 hw->dev_spec._82575.global_device_reset = true; 6500 6501 schedule_work(&adapter->reset_task); 6502 wr32(E1000_EICS, 6503 (adapter->eims_enable_mask & ~adapter->eims_other)); 6504 } 6505 6506 static void igb_reset_task(struct work_struct *work) 6507 { 6508 struct igb_adapter *adapter; 6509 adapter = container_of(work, struct igb_adapter, reset_task); 6510 6511 rtnl_lock(); 6512 /* If we're already down or resetting, just bail */ 6513 if (test_bit(__IGB_DOWN, &adapter->state) || 6514 test_bit(__IGB_RESETTING, &adapter->state)) { 6515 rtnl_unlock(); 6516 return; 6517 } 6518 6519 igb_dump(adapter); 6520 netdev_err(adapter->netdev, "Reset adapter\n"); 6521 igb_reinit_locked(adapter); 6522 rtnl_unlock(); 6523 } 6524 6525 /** 6526 * igb_get_stats64 - Get System Network Statistics 6527 * @netdev: network interface device structure 6528 * @stats: rtnl_link_stats64 pointer 6529 **/ 6530 static void igb_get_stats64(struct net_device *netdev, 6531 struct rtnl_link_stats64 *stats) 6532 { 6533 struct igb_adapter *adapter = netdev_priv(netdev); 6534 6535 spin_lock(&adapter->stats64_lock); 6536 igb_update_stats(adapter); 6537 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6538 spin_unlock(&adapter->stats64_lock); 6539 } 6540 6541 /** 6542 * igb_change_mtu - Change the Maximum Transfer Unit 6543 * @netdev: network interface device structure 6544 * @new_mtu: new value for maximum frame size 6545 * 6546 * Returns 0 on success, negative on failure 6547 **/ 6548 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6549 { 6550 struct igb_adapter *adapter = netdev_priv(netdev); 6551 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6552 6553 if (adapter->xdp_prog) { 6554 int i; 6555 6556 for (i = 0; i < adapter->num_rx_queues; i++) { 6557 struct igb_ring *ring = adapter->rx_ring[i]; 6558 6559 if (max_frame > igb_rx_bufsz(ring)) { 6560 netdev_warn(adapter->netdev, 6561 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6562 max_frame); 6563 return -EINVAL; 6564 } 6565 } 6566 } 6567 6568 /* adjust max frame to be at least the size of a standard frame */ 6569 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6570 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6571 6572 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6573 usleep_range(1000, 2000); 6574 6575 /* igb_down has a dependency on max_frame_size */ 6576 adapter->max_frame_size = max_frame; 6577 6578 if (netif_running(netdev)) 6579 igb_down(adapter); 6580 6581 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6582 netdev->mtu, new_mtu); 6583 netdev->mtu = new_mtu; 6584 6585 if (netif_running(netdev)) 6586 igb_up(adapter); 6587 else 6588 igb_reset(adapter); 6589 6590 clear_bit(__IGB_RESETTING, &adapter->state); 6591 6592 return 0; 6593 } 6594 6595 /** 6596 * igb_update_stats - Update the board statistics counters 6597 * @adapter: board private structure 6598 **/ 6599 void igb_update_stats(struct igb_adapter *adapter) 6600 { 6601 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6602 struct e1000_hw *hw = &adapter->hw; 6603 struct pci_dev *pdev = adapter->pdev; 6604 u32 reg, mpc; 6605 int i; 6606 u64 bytes, packets; 6607 unsigned int start; 6608 u64 _bytes, _packets; 6609 6610 /* Prevent stats update while adapter is being reset, or if the pci 6611 * connection is down. 6612 */ 6613 if (adapter->link_speed == 0) 6614 return; 6615 if (pci_channel_offline(pdev)) 6616 return; 6617 6618 bytes = 0; 6619 packets = 0; 6620 6621 rcu_read_lock(); 6622 for (i = 0; i < adapter->num_rx_queues; i++) { 6623 struct igb_ring *ring = adapter->rx_ring[i]; 6624 u32 rqdpc = rd32(E1000_RQDPC(i)); 6625 if (hw->mac.type >= e1000_i210) 6626 wr32(E1000_RQDPC(i), 0); 6627 6628 if (rqdpc) { 6629 ring->rx_stats.drops += rqdpc; 6630 net_stats->rx_fifo_errors += rqdpc; 6631 } 6632 6633 do { 6634 start = u64_stats_fetch_begin(&ring->rx_syncp); 6635 _bytes = ring->rx_stats.bytes; 6636 _packets = ring->rx_stats.packets; 6637 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6638 bytes += _bytes; 6639 packets += _packets; 6640 } 6641 6642 net_stats->rx_bytes = bytes; 6643 net_stats->rx_packets = packets; 6644 6645 bytes = 0; 6646 packets = 0; 6647 for (i = 0; i < adapter->num_tx_queues; i++) { 6648 struct igb_ring *ring = adapter->tx_ring[i]; 6649 do { 6650 start = u64_stats_fetch_begin(&ring->tx_syncp); 6651 _bytes = ring->tx_stats.bytes; 6652 _packets = ring->tx_stats.packets; 6653 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6654 bytes += _bytes; 6655 packets += _packets; 6656 } 6657 net_stats->tx_bytes = bytes; 6658 net_stats->tx_packets = packets; 6659 rcu_read_unlock(); 6660 6661 /* read stats registers */ 6662 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6663 adapter->stats.gprc += rd32(E1000_GPRC); 6664 adapter->stats.gorc += rd32(E1000_GORCL); 6665 rd32(E1000_GORCH); /* clear GORCL */ 6666 adapter->stats.bprc += rd32(E1000_BPRC); 6667 adapter->stats.mprc += rd32(E1000_MPRC); 6668 adapter->stats.roc += rd32(E1000_ROC); 6669 6670 adapter->stats.prc64 += rd32(E1000_PRC64); 6671 adapter->stats.prc127 += rd32(E1000_PRC127); 6672 adapter->stats.prc255 += rd32(E1000_PRC255); 6673 adapter->stats.prc511 += rd32(E1000_PRC511); 6674 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6675 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6676 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6677 adapter->stats.sec += rd32(E1000_SEC); 6678 6679 mpc = rd32(E1000_MPC); 6680 adapter->stats.mpc += mpc; 6681 net_stats->rx_fifo_errors += mpc; 6682 adapter->stats.scc += rd32(E1000_SCC); 6683 adapter->stats.ecol += rd32(E1000_ECOL); 6684 adapter->stats.mcc += rd32(E1000_MCC); 6685 adapter->stats.latecol += rd32(E1000_LATECOL); 6686 adapter->stats.dc += rd32(E1000_DC); 6687 adapter->stats.rlec += rd32(E1000_RLEC); 6688 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6689 adapter->stats.xontxc += rd32(E1000_XONTXC); 6690 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6691 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6692 adapter->stats.fcruc += rd32(E1000_FCRUC); 6693 adapter->stats.gptc += rd32(E1000_GPTC); 6694 adapter->stats.gotc += rd32(E1000_GOTCL); 6695 rd32(E1000_GOTCH); /* clear GOTCL */ 6696 adapter->stats.rnbc += rd32(E1000_RNBC); 6697 adapter->stats.ruc += rd32(E1000_RUC); 6698 adapter->stats.rfc += rd32(E1000_RFC); 6699 adapter->stats.rjc += rd32(E1000_RJC); 6700 adapter->stats.tor += rd32(E1000_TORH); 6701 adapter->stats.tot += rd32(E1000_TOTH); 6702 adapter->stats.tpr += rd32(E1000_TPR); 6703 6704 adapter->stats.ptc64 += rd32(E1000_PTC64); 6705 adapter->stats.ptc127 += rd32(E1000_PTC127); 6706 adapter->stats.ptc255 += rd32(E1000_PTC255); 6707 adapter->stats.ptc511 += rd32(E1000_PTC511); 6708 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6709 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6710 6711 adapter->stats.mptc += rd32(E1000_MPTC); 6712 adapter->stats.bptc += rd32(E1000_BPTC); 6713 6714 adapter->stats.tpt += rd32(E1000_TPT); 6715 adapter->stats.colc += rd32(E1000_COLC); 6716 6717 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6718 /* read internal phy specific stats */ 6719 reg = rd32(E1000_CTRL_EXT); 6720 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6721 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6722 6723 /* this stat has invalid values on i210/i211 */ 6724 if ((hw->mac.type != e1000_i210) && 6725 (hw->mac.type != e1000_i211)) 6726 adapter->stats.tncrs += rd32(E1000_TNCRS); 6727 } 6728 6729 adapter->stats.tsctc += rd32(E1000_TSCTC); 6730 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6731 6732 adapter->stats.iac += rd32(E1000_IAC); 6733 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6734 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6735 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6736 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6737 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6738 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6739 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6740 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6741 6742 /* Fill out the OS statistics structure */ 6743 net_stats->multicast = adapter->stats.mprc; 6744 net_stats->collisions = adapter->stats.colc; 6745 6746 /* Rx Errors */ 6747 6748 /* RLEC on some newer hardware can be incorrect so build 6749 * our own version based on RUC and ROC 6750 */ 6751 net_stats->rx_errors = adapter->stats.rxerrc + 6752 adapter->stats.crcerrs + adapter->stats.algnerrc + 6753 adapter->stats.ruc + adapter->stats.roc + 6754 adapter->stats.cexterr; 6755 net_stats->rx_length_errors = adapter->stats.ruc + 6756 adapter->stats.roc; 6757 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6758 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6759 net_stats->rx_missed_errors = adapter->stats.mpc; 6760 6761 /* Tx Errors */ 6762 net_stats->tx_errors = adapter->stats.ecol + 6763 adapter->stats.latecol; 6764 net_stats->tx_aborted_errors = adapter->stats.ecol; 6765 net_stats->tx_window_errors = adapter->stats.latecol; 6766 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6767 6768 /* Tx Dropped needs to be maintained elsewhere */ 6769 6770 /* Management Stats */ 6771 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6772 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6773 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6774 6775 /* OS2BMC Stats */ 6776 reg = rd32(E1000_MANC); 6777 if (reg & E1000_MANC_EN_BMC2OS) { 6778 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6779 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6780 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6781 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6782 } 6783 } 6784 6785 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6786 { 6787 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6788 struct e1000_hw *hw = &adapter->hw; 6789 struct timespec64 ts; 6790 u32 tsauxc; 6791 6792 if (pin < 0 || pin >= IGB_N_PEROUT) 6793 return; 6794 6795 spin_lock(&adapter->tmreg_lock); 6796 6797 if (hw->mac.type == e1000_82580 || 6798 hw->mac.type == e1000_i354 || 6799 hw->mac.type == e1000_i350) { 6800 s64 ns = timespec64_to_ns(&adapter->perout[pin].period); 6801 u32 systiml, systimh, level_mask, level, rem; 6802 u64 systim, now; 6803 6804 /* read systim registers in sequence */ 6805 rd32(E1000_SYSTIMR); 6806 systiml = rd32(E1000_SYSTIML); 6807 systimh = rd32(E1000_SYSTIMH); 6808 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6809 now = timecounter_cyc2time(&adapter->tc, systim); 6810 6811 if (pin < 2) { 6812 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6813 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6814 } else { 6815 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6816 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6817 } 6818 6819 div_u64_rem(now, ns, &rem); 6820 systim = systim + (ns - rem); 6821 6822 /* synchronize pin level with rising/falling edges */ 6823 div_u64_rem(now, ns << 1, &rem); 6824 if (rem < ns) { 6825 /* first half of period */ 6826 if (level == 0) { 6827 /* output is already low, skip this period */ 6828 systim += ns; 6829 pr_notice("igb: periodic output on %s missed falling edge\n", 6830 adapter->sdp_config[pin].name); 6831 } 6832 } else { 6833 /* second half of period */ 6834 if (level == 1) { 6835 /* output is already high, skip this period */ 6836 systim += ns; 6837 pr_notice("igb: periodic output on %s missed rising edge\n", 6838 adapter->sdp_config[pin].name); 6839 } 6840 } 6841 6842 /* for this chip family tv_sec is the upper part of the binary value, 6843 * so not seconds 6844 */ 6845 ts.tv_nsec = (u32)systim; 6846 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6847 } else { 6848 ts = timespec64_add(adapter->perout[pin].start, 6849 adapter->perout[pin].period); 6850 } 6851 6852 /* u32 conversion of tv_sec is safe until y2106 */ 6853 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6854 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6855 tsauxc = rd32(E1000_TSAUXC); 6856 tsauxc |= TSAUXC_EN_TT0; 6857 wr32(E1000_TSAUXC, tsauxc); 6858 adapter->perout[pin].start = ts; 6859 6860 spin_unlock(&adapter->tmreg_lock); 6861 } 6862 6863 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6864 { 6865 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6866 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6867 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6868 struct e1000_hw *hw = &adapter->hw; 6869 struct ptp_clock_event event; 6870 struct timespec64 ts; 6871 6872 if (pin < 0 || pin >= IGB_N_EXTTS) 6873 return; 6874 6875 if (hw->mac.type == e1000_82580 || 6876 hw->mac.type == e1000_i354 || 6877 hw->mac.type == e1000_i350) { 6878 s64 ns = rd32(auxstmpl); 6879 6880 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6881 ts = ns_to_timespec64(ns); 6882 } else { 6883 ts.tv_nsec = rd32(auxstmpl); 6884 ts.tv_sec = rd32(auxstmph); 6885 } 6886 6887 event.type = PTP_CLOCK_EXTTS; 6888 event.index = tsintr_tt; 6889 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6890 ptp_clock_event(adapter->ptp_clock, &event); 6891 } 6892 6893 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6894 { 6895 struct e1000_hw *hw = &adapter->hw; 6896 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6897 struct ptp_clock_event event; 6898 6899 if (tsicr & TSINTR_SYS_WRAP) { 6900 event.type = PTP_CLOCK_PPS; 6901 if (adapter->ptp_caps.pps) 6902 ptp_clock_event(adapter->ptp_clock, &event); 6903 ack |= TSINTR_SYS_WRAP; 6904 } 6905 6906 if (tsicr & E1000_TSICR_TXTS) { 6907 /* retrieve hardware timestamp */ 6908 schedule_work(&adapter->ptp_tx_work); 6909 ack |= E1000_TSICR_TXTS; 6910 } 6911 6912 if (tsicr & TSINTR_TT0) { 6913 igb_perout(adapter, 0); 6914 ack |= TSINTR_TT0; 6915 } 6916 6917 if (tsicr & TSINTR_TT1) { 6918 igb_perout(adapter, 1); 6919 ack |= TSINTR_TT1; 6920 } 6921 6922 if (tsicr & TSINTR_AUTT0) { 6923 igb_extts(adapter, 0); 6924 ack |= TSINTR_AUTT0; 6925 } 6926 6927 if (tsicr & TSINTR_AUTT1) { 6928 igb_extts(adapter, 1); 6929 ack |= TSINTR_AUTT1; 6930 } 6931 6932 /* acknowledge the interrupts */ 6933 wr32(E1000_TSICR, ack); 6934 } 6935 6936 static irqreturn_t igb_msix_other(int irq, void *data) 6937 { 6938 struct igb_adapter *adapter = data; 6939 struct e1000_hw *hw = &adapter->hw; 6940 u32 icr = rd32(E1000_ICR); 6941 /* reading ICR causes bit 31 of EICR to be cleared */ 6942 6943 if (icr & E1000_ICR_DRSTA) 6944 schedule_work(&adapter->reset_task); 6945 6946 if (icr & E1000_ICR_DOUTSYNC) { 6947 /* HW is reporting DMA is out of sync */ 6948 adapter->stats.doosync++; 6949 /* The DMA Out of Sync is also indication of a spoof event 6950 * in IOV mode. Check the Wrong VM Behavior register to 6951 * see if it is really a spoof event. 6952 */ 6953 igb_check_wvbr(adapter); 6954 } 6955 6956 /* Check for a mailbox event */ 6957 if (icr & E1000_ICR_VMMB) 6958 igb_msg_task(adapter); 6959 6960 if (icr & E1000_ICR_LSC) { 6961 hw->mac.get_link_status = 1; 6962 /* guard against interrupt when we're going down */ 6963 if (!test_bit(__IGB_DOWN, &adapter->state)) 6964 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6965 } 6966 6967 if (icr & E1000_ICR_TS) 6968 igb_tsync_interrupt(adapter); 6969 6970 wr32(E1000_EIMS, adapter->eims_other); 6971 6972 return IRQ_HANDLED; 6973 } 6974 6975 static void igb_write_itr(struct igb_q_vector *q_vector) 6976 { 6977 struct igb_adapter *adapter = q_vector->adapter; 6978 u32 itr_val = q_vector->itr_val & 0x7FFC; 6979 6980 if (!q_vector->set_itr) 6981 return; 6982 6983 if (!itr_val) 6984 itr_val = 0x4; 6985 6986 if (adapter->hw.mac.type == e1000_82575) 6987 itr_val |= itr_val << 16; 6988 else 6989 itr_val |= E1000_EITR_CNT_IGNR; 6990 6991 writel(itr_val, q_vector->itr_register); 6992 q_vector->set_itr = 0; 6993 } 6994 6995 static irqreturn_t igb_msix_ring(int irq, void *data) 6996 { 6997 struct igb_q_vector *q_vector = data; 6998 6999 /* Write the ITR value calculated from the previous interrupt. */ 7000 igb_write_itr(q_vector); 7001 7002 napi_schedule(&q_vector->napi); 7003 7004 return IRQ_HANDLED; 7005 } 7006 7007 #ifdef CONFIG_IGB_DCA 7008 static void igb_update_tx_dca(struct igb_adapter *adapter, 7009 struct igb_ring *tx_ring, 7010 int cpu) 7011 { 7012 struct e1000_hw *hw = &adapter->hw; 7013 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7014 7015 if (hw->mac.type != e1000_82575) 7016 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7017 7018 /* We can enable relaxed ordering for reads, but not writes when 7019 * DCA is enabled. This is due to a known issue in some chipsets 7020 * which will cause the DCA tag to be cleared. 7021 */ 7022 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7023 E1000_DCA_TXCTRL_DATA_RRO_EN | 7024 E1000_DCA_TXCTRL_DESC_DCA_EN; 7025 7026 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7027 } 7028 7029 static void igb_update_rx_dca(struct igb_adapter *adapter, 7030 struct igb_ring *rx_ring, 7031 int cpu) 7032 { 7033 struct e1000_hw *hw = &adapter->hw; 7034 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7035 7036 if (hw->mac.type != e1000_82575) 7037 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7038 7039 /* We can enable relaxed ordering for reads, but not writes when 7040 * DCA is enabled. This is due to a known issue in some chipsets 7041 * which will cause the DCA tag to be cleared. 7042 */ 7043 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7044 E1000_DCA_RXCTRL_DESC_DCA_EN; 7045 7046 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7047 } 7048 7049 static void igb_update_dca(struct igb_q_vector *q_vector) 7050 { 7051 struct igb_adapter *adapter = q_vector->adapter; 7052 int cpu = get_cpu(); 7053 7054 if (q_vector->cpu == cpu) 7055 goto out_no_update; 7056 7057 if (q_vector->tx.ring) 7058 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7059 7060 if (q_vector->rx.ring) 7061 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7062 7063 q_vector->cpu = cpu; 7064 out_no_update: 7065 put_cpu(); 7066 } 7067 7068 static void igb_setup_dca(struct igb_adapter *adapter) 7069 { 7070 struct e1000_hw *hw = &adapter->hw; 7071 int i; 7072 7073 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7074 return; 7075 7076 /* Always use CB2 mode, difference is masked in the CB driver. */ 7077 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7078 7079 for (i = 0; i < adapter->num_q_vectors; i++) { 7080 adapter->q_vector[i]->cpu = -1; 7081 igb_update_dca(adapter->q_vector[i]); 7082 } 7083 } 7084 7085 static int __igb_notify_dca(struct device *dev, void *data) 7086 { 7087 struct net_device *netdev = dev_get_drvdata(dev); 7088 struct igb_adapter *adapter = netdev_priv(netdev); 7089 struct pci_dev *pdev = adapter->pdev; 7090 struct e1000_hw *hw = &adapter->hw; 7091 unsigned long event = *(unsigned long *)data; 7092 7093 switch (event) { 7094 case DCA_PROVIDER_ADD: 7095 /* if already enabled, don't do it again */ 7096 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7097 break; 7098 if (dca_add_requester(dev) == 0) { 7099 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7100 dev_info(&pdev->dev, "DCA enabled\n"); 7101 igb_setup_dca(adapter); 7102 break; 7103 } 7104 fallthrough; /* since DCA is disabled. */ 7105 case DCA_PROVIDER_REMOVE: 7106 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7107 /* without this a class_device is left 7108 * hanging around in the sysfs model 7109 */ 7110 dca_remove_requester(dev); 7111 dev_info(&pdev->dev, "DCA disabled\n"); 7112 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7113 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7114 } 7115 break; 7116 } 7117 7118 return 0; 7119 } 7120 7121 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7122 void *p) 7123 { 7124 int ret_val; 7125 7126 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7127 __igb_notify_dca); 7128 7129 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7130 } 7131 #endif /* CONFIG_IGB_DCA */ 7132 7133 #ifdef CONFIG_PCI_IOV 7134 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7135 { 7136 unsigned char mac_addr[ETH_ALEN]; 7137 7138 eth_zero_addr(mac_addr); 7139 igb_set_vf_mac(adapter, vf, mac_addr); 7140 7141 /* By default spoof check is enabled for all VFs */ 7142 adapter->vf_data[vf].spoofchk_enabled = true; 7143 7144 /* By default VFs are not trusted */ 7145 adapter->vf_data[vf].trusted = false; 7146 7147 return 0; 7148 } 7149 7150 #endif 7151 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7152 { 7153 struct e1000_hw *hw = &adapter->hw; 7154 u32 ping; 7155 int i; 7156 7157 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7158 ping = E1000_PF_CONTROL_MSG; 7159 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7160 ping |= E1000_VT_MSGTYPE_CTS; 7161 igb_write_mbx(hw, &ping, 1, i); 7162 } 7163 } 7164 7165 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7166 { 7167 struct e1000_hw *hw = &adapter->hw; 7168 u32 vmolr = rd32(E1000_VMOLR(vf)); 7169 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7170 7171 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7172 IGB_VF_FLAG_MULTI_PROMISC); 7173 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7174 7175 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7176 vmolr |= E1000_VMOLR_MPME; 7177 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7178 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7179 } else { 7180 /* if we have hashes and we are clearing a multicast promisc 7181 * flag we need to write the hashes to the MTA as this step 7182 * was previously skipped 7183 */ 7184 if (vf_data->num_vf_mc_hashes > 30) { 7185 vmolr |= E1000_VMOLR_MPME; 7186 } else if (vf_data->num_vf_mc_hashes) { 7187 int j; 7188 7189 vmolr |= E1000_VMOLR_ROMPE; 7190 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7191 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7192 } 7193 } 7194 7195 wr32(E1000_VMOLR(vf), vmolr); 7196 7197 /* there are flags left unprocessed, likely not supported */ 7198 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7199 return -EINVAL; 7200 7201 return 0; 7202 } 7203 7204 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7205 u32 *msgbuf, u32 vf) 7206 { 7207 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7208 u16 *hash_list = (u16 *)&msgbuf[1]; 7209 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7210 int i; 7211 7212 /* salt away the number of multicast addresses assigned 7213 * to this VF for later use to restore when the PF multi cast 7214 * list changes 7215 */ 7216 vf_data->num_vf_mc_hashes = n; 7217 7218 /* only up to 30 hash values supported */ 7219 if (n > 30) 7220 n = 30; 7221 7222 /* store the hashes for later use */ 7223 for (i = 0; i < n; i++) 7224 vf_data->vf_mc_hashes[i] = hash_list[i]; 7225 7226 /* Flush and reset the mta with the new values */ 7227 igb_set_rx_mode(adapter->netdev); 7228 7229 return 0; 7230 } 7231 7232 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7233 { 7234 struct e1000_hw *hw = &adapter->hw; 7235 struct vf_data_storage *vf_data; 7236 int i, j; 7237 7238 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7239 u32 vmolr = rd32(E1000_VMOLR(i)); 7240 7241 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7242 7243 vf_data = &adapter->vf_data[i]; 7244 7245 if ((vf_data->num_vf_mc_hashes > 30) || 7246 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7247 vmolr |= E1000_VMOLR_MPME; 7248 } else if (vf_data->num_vf_mc_hashes) { 7249 vmolr |= E1000_VMOLR_ROMPE; 7250 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7251 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7252 } 7253 wr32(E1000_VMOLR(i), vmolr); 7254 } 7255 } 7256 7257 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7258 { 7259 struct e1000_hw *hw = &adapter->hw; 7260 u32 pool_mask, vlvf_mask, i; 7261 7262 /* create mask for VF and other pools */ 7263 pool_mask = E1000_VLVF_POOLSEL_MASK; 7264 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7265 7266 /* drop PF from pool bits */ 7267 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7268 adapter->vfs_allocated_count); 7269 7270 /* Find the vlan filter for this id */ 7271 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7272 u32 vlvf = rd32(E1000_VLVF(i)); 7273 u32 vfta_mask, vid, vfta; 7274 7275 /* remove the vf from the pool */ 7276 if (!(vlvf & vlvf_mask)) 7277 continue; 7278 7279 /* clear out bit from VLVF */ 7280 vlvf ^= vlvf_mask; 7281 7282 /* if other pools are present, just remove ourselves */ 7283 if (vlvf & pool_mask) 7284 goto update_vlvfb; 7285 7286 /* if PF is present, leave VFTA */ 7287 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7288 goto update_vlvf; 7289 7290 vid = vlvf & E1000_VLVF_VLANID_MASK; 7291 vfta_mask = BIT(vid % 32); 7292 7293 /* clear bit from VFTA */ 7294 vfta = adapter->shadow_vfta[vid / 32]; 7295 if (vfta & vfta_mask) 7296 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7297 update_vlvf: 7298 /* clear pool selection enable */ 7299 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7300 vlvf &= E1000_VLVF_POOLSEL_MASK; 7301 else 7302 vlvf = 0; 7303 update_vlvfb: 7304 /* clear pool bits */ 7305 wr32(E1000_VLVF(i), vlvf); 7306 } 7307 } 7308 7309 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7310 { 7311 u32 vlvf; 7312 int idx; 7313 7314 /* short cut the special case */ 7315 if (vlan == 0) 7316 return 0; 7317 7318 /* Search for the VLAN id in the VLVF entries */ 7319 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7320 vlvf = rd32(E1000_VLVF(idx)); 7321 if ((vlvf & VLAN_VID_MASK) == vlan) 7322 break; 7323 } 7324 7325 return idx; 7326 } 7327 7328 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7329 { 7330 struct e1000_hw *hw = &adapter->hw; 7331 u32 bits, pf_id; 7332 int idx; 7333 7334 idx = igb_find_vlvf_entry(hw, vid); 7335 if (!idx) 7336 return; 7337 7338 /* See if any other pools are set for this VLAN filter 7339 * entry other than the PF. 7340 */ 7341 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7342 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7343 bits &= rd32(E1000_VLVF(idx)); 7344 7345 /* Disable the filter so this falls into the default pool. */ 7346 if (!bits) { 7347 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7348 wr32(E1000_VLVF(idx), BIT(pf_id)); 7349 else 7350 wr32(E1000_VLVF(idx), 0); 7351 } 7352 } 7353 7354 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7355 bool add, u32 vf) 7356 { 7357 int pf_id = adapter->vfs_allocated_count; 7358 struct e1000_hw *hw = &adapter->hw; 7359 int err; 7360 7361 /* If VLAN overlaps with one the PF is currently monitoring make 7362 * sure that we are able to allocate a VLVF entry. This may be 7363 * redundant but it guarantees PF will maintain visibility to 7364 * the VLAN. 7365 */ 7366 if (add && test_bit(vid, adapter->active_vlans)) { 7367 err = igb_vfta_set(hw, vid, pf_id, true, false); 7368 if (err) 7369 return err; 7370 } 7371 7372 err = igb_vfta_set(hw, vid, vf, add, false); 7373 7374 if (add && !err) 7375 return err; 7376 7377 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7378 * we may need to drop the PF pool bit in order to allow us to free 7379 * up the VLVF resources. 7380 */ 7381 if (test_bit(vid, adapter->active_vlans) || 7382 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7383 igb_update_pf_vlvf(adapter, vid); 7384 7385 return err; 7386 } 7387 7388 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7389 { 7390 struct e1000_hw *hw = &adapter->hw; 7391 7392 if (vid) 7393 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7394 else 7395 wr32(E1000_VMVIR(vf), 0); 7396 } 7397 7398 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7399 u16 vlan, u8 qos) 7400 { 7401 int err; 7402 7403 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7404 if (err) 7405 return err; 7406 7407 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7408 igb_set_vmolr(adapter, vf, !vlan); 7409 7410 /* revoke access to previous VLAN */ 7411 if (vlan != adapter->vf_data[vf].pf_vlan) 7412 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7413 false, vf); 7414 7415 adapter->vf_data[vf].pf_vlan = vlan; 7416 adapter->vf_data[vf].pf_qos = qos; 7417 igb_set_vf_vlan_strip(adapter, vf, true); 7418 dev_info(&adapter->pdev->dev, 7419 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7420 if (test_bit(__IGB_DOWN, &adapter->state)) { 7421 dev_warn(&adapter->pdev->dev, 7422 "The VF VLAN has been set, but the PF device is not up.\n"); 7423 dev_warn(&adapter->pdev->dev, 7424 "Bring the PF device up before attempting to use the VF device.\n"); 7425 } 7426 7427 return err; 7428 } 7429 7430 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7431 { 7432 /* Restore tagless access via VLAN 0 */ 7433 igb_set_vf_vlan(adapter, 0, true, vf); 7434 7435 igb_set_vmvir(adapter, 0, vf); 7436 igb_set_vmolr(adapter, vf, true); 7437 7438 /* Remove any PF assigned VLAN */ 7439 if (adapter->vf_data[vf].pf_vlan) 7440 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7441 false, vf); 7442 7443 adapter->vf_data[vf].pf_vlan = 0; 7444 adapter->vf_data[vf].pf_qos = 0; 7445 igb_set_vf_vlan_strip(adapter, vf, false); 7446 7447 return 0; 7448 } 7449 7450 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7451 u16 vlan, u8 qos, __be16 vlan_proto) 7452 { 7453 struct igb_adapter *adapter = netdev_priv(netdev); 7454 7455 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7456 return -EINVAL; 7457 7458 if (vlan_proto != htons(ETH_P_8021Q)) 7459 return -EPROTONOSUPPORT; 7460 7461 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7462 igb_disable_port_vlan(adapter, vf); 7463 } 7464 7465 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7466 { 7467 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7468 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7469 int ret; 7470 7471 if (adapter->vf_data[vf].pf_vlan) 7472 return -1; 7473 7474 /* VLAN 0 is a special case, don't allow it to be removed */ 7475 if (!vid && !add) 7476 return 0; 7477 7478 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7479 if (!ret) 7480 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7481 return ret; 7482 } 7483 7484 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7485 { 7486 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7487 7488 /* clear flags - except flag that indicates PF has set the MAC */ 7489 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7490 vf_data->last_nack = jiffies; 7491 7492 /* reset vlans for device */ 7493 igb_clear_vf_vfta(adapter, vf); 7494 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7495 igb_set_vmvir(adapter, vf_data->pf_vlan | 7496 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7497 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7498 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7499 7500 /* reset multicast table array for vf */ 7501 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7502 7503 /* Flush and reset the mta with the new values */ 7504 igb_set_rx_mode(adapter->netdev); 7505 } 7506 7507 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7508 { 7509 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7510 7511 /* clear mac address as we were hotplug removed/added */ 7512 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7513 eth_zero_addr(vf_mac); 7514 7515 /* process remaining reset events */ 7516 igb_vf_reset(adapter, vf); 7517 } 7518 7519 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7520 { 7521 struct e1000_hw *hw = &adapter->hw; 7522 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7523 u32 reg, msgbuf[3] = {}; 7524 u8 *addr = (u8 *)(&msgbuf[1]); 7525 7526 /* process all the same items cleared in a function level reset */ 7527 igb_vf_reset(adapter, vf); 7528 7529 /* set vf mac address */ 7530 igb_set_vf_mac(adapter, vf, vf_mac); 7531 7532 /* enable transmit and receive for vf */ 7533 reg = rd32(E1000_VFTE); 7534 wr32(E1000_VFTE, reg | BIT(vf)); 7535 reg = rd32(E1000_VFRE); 7536 wr32(E1000_VFRE, reg | BIT(vf)); 7537 7538 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7539 7540 /* reply to reset with ack and vf mac address */ 7541 if (!is_zero_ether_addr(vf_mac)) { 7542 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7543 memcpy(addr, vf_mac, ETH_ALEN); 7544 } else { 7545 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7546 } 7547 igb_write_mbx(hw, msgbuf, 3, vf); 7548 } 7549 7550 static void igb_flush_mac_table(struct igb_adapter *adapter) 7551 { 7552 struct e1000_hw *hw = &adapter->hw; 7553 int i; 7554 7555 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7556 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7557 eth_zero_addr(adapter->mac_table[i].addr); 7558 adapter->mac_table[i].queue = 0; 7559 igb_rar_set_index(adapter, i); 7560 } 7561 } 7562 7563 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7564 { 7565 struct e1000_hw *hw = &adapter->hw; 7566 /* do not count rar entries reserved for VFs MAC addresses */ 7567 int rar_entries = hw->mac.rar_entry_count - 7568 adapter->vfs_allocated_count; 7569 int i, count = 0; 7570 7571 for (i = 0; i < rar_entries; i++) { 7572 /* do not count default entries */ 7573 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7574 continue; 7575 7576 /* do not count "in use" entries for different queues */ 7577 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7578 (adapter->mac_table[i].queue != queue)) 7579 continue; 7580 7581 count++; 7582 } 7583 7584 return count; 7585 } 7586 7587 /* Set default MAC address for the PF in the first RAR entry */ 7588 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7589 { 7590 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7591 7592 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7593 mac_table->queue = adapter->vfs_allocated_count; 7594 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7595 7596 igb_rar_set_index(adapter, 0); 7597 } 7598 7599 /* If the filter to be added and an already existing filter express 7600 * the same address and address type, it should be possible to only 7601 * override the other configurations, for example the queue to steer 7602 * traffic. 7603 */ 7604 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7605 const u8 *addr, const u8 flags) 7606 { 7607 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7608 return true; 7609 7610 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7611 (flags & IGB_MAC_STATE_SRC_ADDR)) 7612 return false; 7613 7614 if (!ether_addr_equal(addr, entry->addr)) 7615 return false; 7616 7617 return true; 7618 } 7619 7620 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7621 * 'flags' is used to indicate what kind of match is made, match is by 7622 * default for the destination address, if matching by source address 7623 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7624 */ 7625 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7626 const u8 *addr, const u8 queue, 7627 const u8 flags) 7628 { 7629 struct e1000_hw *hw = &adapter->hw; 7630 int rar_entries = hw->mac.rar_entry_count - 7631 adapter->vfs_allocated_count; 7632 int i; 7633 7634 if (is_zero_ether_addr(addr)) 7635 return -EINVAL; 7636 7637 /* Search for the first empty entry in the MAC table. 7638 * Do not touch entries at the end of the table reserved for the VF MAC 7639 * addresses. 7640 */ 7641 for (i = 0; i < rar_entries; i++) { 7642 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7643 addr, flags)) 7644 continue; 7645 7646 ether_addr_copy(adapter->mac_table[i].addr, addr); 7647 adapter->mac_table[i].queue = queue; 7648 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7649 7650 igb_rar_set_index(adapter, i); 7651 return i; 7652 } 7653 7654 return -ENOSPC; 7655 } 7656 7657 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7658 const u8 queue) 7659 { 7660 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7661 } 7662 7663 /* Remove a MAC filter for 'addr' directing matching traffic to 7664 * 'queue', 'flags' is used to indicate what kind of match need to be 7665 * removed, match is by default for the destination address, if 7666 * matching by source address is to be removed the flag 7667 * IGB_MAC_STATE_SRC_ADDR can be used. 7668 */ 7669 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7670 const u8 *addr, const u8 queue, 7671 const u8 flags) 7672 { 7673 struct e1000_hw *hw = &adapter->hw; 7674 int rar_entries = hw->mac.rar_entry_count - 7675 adapter->vfs_allocated_count; 7676 int i; 7677 7678 if (is_zero_ether_addr(addr)) 7679 return -EINVAL; 7680 7681 /* Search for matching entry in the MAC table based on given address 7682 * and queue. Do not touch entries at the end of the table reserved 7683 * for the VF MAC addresses. 7684 */ 7685 for (i = 0; i < rar_entries; i++) { 7686 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7687 continue; 7688 if ((adapter->mac_table[i].state & flags) != flags) 7689 continue; 7690 if (adapter->mac_table[i].queue != queue) 7691 continue; 7692 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7693 continue; 7694 7695 /* When a filter for the default address is "deleted", 7696 * we return it to its initial configuration 7697 */ 7698 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7699 adapter->mac_table[i].state = 7700 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7701 adapter->mac_table[i].queue = 7702 adapter->vfs_allocated_count; 7703 } else { 7704 adapter->mac_table[i].state = 0; 7705 adapter->mac_table[i].queue = 0; 7706 eth_zero_addr(adapter->mac_table[i].addr); 7707 } 7708 7709 igb_rar_set_index(adapter, i); 7710 return 0; 7711 } 7712 7713 return -ENOENT; 7714 } 7715 7716 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7717 const u8 queue) 7718 { 7719 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7720 } 7721 7722 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7723 const u8 *addr, u8 queue, u8 flags) 7724 { 7725 struct e1000_hw *hw = &adapter->hw; 7726 7727 /* In theory, this should be supported on 82575 as well, but 7728 * that part wasn't easily accessible during development. 7729 */ 7730 if (hw->mac.type != e1000_i210) 7731 return -EOPNOTSUPP; 7732 7733 return igb_add_mac_filter_flags(adapter, addr, queue, 7734 IGB_MAC_STATE_QUEUE_STEERING | flags); 7735 } 7736 7737 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7738 const u8 *addr, u8 queue, u8 flags) 7739 { 7740 return igb_del_mac_filter_flags(adapter, addr, queue, 7741 IGB_MAC_STATE_QUEUE_STEERING | flags); 7742 } 7743 7744 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7745 { 7746 struct igb_adapter *adapter = netdev_priv(netdev); 7747 int ret; 7748 7749 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7750 7751 return min_t(int, ret, 0); 7752 } 7753 7754 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7755 { 7756 struct igb_adapter *adapter = netdev_priv(netdev); 7757 7758 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7759 7760 return 0; 7761 } 7762 7763 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7764 const u32 info, const u8 *addr) 7765 { 7766 struct pci_dev *pdev = adapter->pdev; 7767 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7768 struct list_head *pos; 7769 struct vf_mac_filter *entry = NULL; 7770 int ret = 0; 7771 7772 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7773 !vf_data->trusted) { 7774 dev_warn(&pdev->dev, 7775 "VF %d requested MAC filter but is administratively denied\n", 7776 vf); 7777 return -EINVAL; 7778 } 7779 if (!is_valid_ether_addr(addr)) { 7780 dev_warn(&pdev->dev, 7781 "VF %d attempted to set invalid MAC filter\n", 7782 vf); 7783 return -EINVAL; 7784 } 7785 7786 switch (info) { 7787 case E1000_VF_MAC_FILTER_CLR: 7788 /* remove all unicast MAC filters related to the current VF */ 7789 list_for_each(pos, &adapter->vf_macs.l) { 7790 entry = list_entry(pos, struct vf_mac_filter, l); 7791 if (entry->vf == vf) { 7792 entry->vf = -1; 7793 entry->free = true; 7794 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7795 } 7796 } 7797 break; 7798 case E1000_VF_MAC_FILTER_ADD: 7799 /* try to find empty slot in the list */ 7800 list_for_each(pos, &adapter->vf_macs.l) { 7801 entry = list_entry(pos, struct vf_mac_filter, l); 7802 if (entry->free) 7803 break; 7804 } 7805 7806 if (entry && entry->free) { 7807 entry->free = false; 7808 entry->vf = vf; 7809 ether_addr_copy(entry->vf_mac, addr); 7810 7811 ret = igb_add_mac_filter(adapter, addr, vf); 7812 ret = min_t(int, ret, 0); 7813 } else { 7814 ret = -ENOSPC; 7815 } 7816 7817 if (ret == -ENOSPC) 7818 dev_warn(&pdev->dev, 7819 "VF %d has requested MAC filter but there is no space for it\n", 7820 vf); 7821 break; 7822 default: 7823 ret = -EINVAL; 7824 break; 7825 } 7826 7827 return ret; 7828 } 7829 7830 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7831 { 7832 struct pci_dev *pdev = adapter->pdev; 7833 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7834 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7835 7836 /* The VF MAC Address is stored in a packed array of bytes 7837 * starting at the second 32 bit word of the msg array 7838 */ 7839 unsigned char *addr = (unsigned char *)&msg[1]; 7840 int ret = 0; 7841 7842 if (!info) { 7843 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7844 !vf_data->trusted) { 7845 dev_warn(&pdev->dev, 7846 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7847 vf); 7848 return -EINVAL; 7849 } 7850 7851 if (!is_valid_ether_addr(addr)) { 7852 dev_warn(&pdev->dev, 7853 "VF %d attempted to set invalid MAC\n", 7854 vf); 7855 return -EINVAL; 7856 } 7857 7858 ret = igb_set_vf_mac(adapter, vf, addr); 7859 } else { 7860 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7861 } 7862 7863 return ret; 7864 } 7865 7866 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7867 { 7868 struct e1000_hw *hw = &adapter->hw; 7869 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7870 u32 msg = E1000_VT_MSGTYPE_NACK; 7871 7872 /* if device isn't clear to send it shouldn't be reading either */ 7873 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7874 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7875 igb_write_mbx(hw, &msg, 1, vf); 7876 vf_data->last_nack = jiffies; 7877 } 7878 } 7879 7880 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7881 { 7882 struct pci_dev *pdev = adapter->pdev; 7883 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7884 struct e1000_hw *hw = &adapter->hw; 7885 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7886 s32 retval; 7887 7888 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7889 7890 if (retval) { 7891 /* if receive failed revoke VF CTS stats and restart init */ 7892 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7893 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7894 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7895 goto unlock; 7896 goto out; 7897 } 7898 7899 /* this is a message we already processed, do nothing */ 7900 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7901 goto unlock; 7902 7903 /* until the vf completes a reset it should not be 7904 * allowed to start any configuration. 7905 */ 7906 if (msgbuf[0] == E1000_VF_RESET) { 7907 /* unlocks mailbox */ 7908 igb_vf_reset_msg(adapter, vf); 7909 return; 7910 } 7911 7912 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7913 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7914 goto unlock; 7915 retval = -1; 7916 goto out; 7917 } 7918 7919 switch ((msgbuf[0] & 0xFFFF)) { 7920 case E1000_VF_SET_MAC_ADDR: 7921 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7922 break; 7923 case E1000_VF_SET_PROMISC: 7924 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7925 break; 7926 case E1000_VF_SET_MULTICAST: 7927 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7928 break; 7929 case E1000_VF_SET_LPE: 7930 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7931 break; 7932 case E1000_VF_SET_VLAN: 7933 retval = -1; 7934 if (vf_data->pf_vlan) 7935 dev_warn(&pdev->dev, 7936 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7937 vf); 7938 else 7939 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7940 break; 7941 default: 7942 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7943 retval = -1; 7944 break; 7945 } 7946 7947 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7948 out: 7949 /* notify the VF of the results of what it sent us */ 7950 if (retval) 7951 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7952 else 7953 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7954 7955 /* unlocks mailbox */ 7956 igb_write_mbx(hw, msgbuf, 1, vf); 7957 return; 7958 7959 unlock: 7960 igb_unlock_mbx(hw, vf); 7961 } 7962 7963 static void igb_msg_task(struct igb_adapter *adapter) 7964 { 7965 struct e1000_hw *hw = &adapter->hw; 7966 unsigned long flags; 7967 u32 vf; 7968 7969 spin_lock_irqsave(&adapter->vfs_lock, flags); 7970 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7971 /* process any reset requests */ 7972 if (!igb_check_for_rst(hw, vf)) 7973 igb_vf_reset_event(adapter, vf); 7974 7975 /* process any messages pending */ 7976 if (!igb_check_for_msg(hw, vf)) 7977 igb_rcv_msg_from_vf(adapter, vf); 7978 7979 /* process any acks */ 7980 if (!igb_check_for_ack(hw, vf)) 7981 igb_rcv_ack_from_vf(adapter, vf); 7982 } 7983 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 7984 } 7985 7986 /** 7987 * igb_set_uta - Set unicast filter table address 7988 * @adapter: board private structure 7989 * @set: boolean indicating if we are setting or clearing bits 7990 * 7991 * The unicast table address is a register array of 32-bit registers. 7992 * The table is meant to be used in a way similar to how the MTA is used 7993 * however due to certain limitations in the hardware it is necessary to 7994 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7995 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7996 **/ 7997 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7998 { 7999 struct e1000_hw *hw = &adapter->hw; 8000 u32 uta = set ? ~0 : 0; 8001 int i; 8002 8003 /* we only need to do this if VMDq is enabled */ 8004 if (!adapter->vfs_allocated_count) 8005 return; 8006 8007 for (i = hw->mac.uta_reg_count; i--;) 8008 array_wr32(E1000_UTA, i, uta); 8009 } 8010 8011 /** 8012 * igb_intr_msi - Interrupt Handler 8013 * @irq: interrupt number 8014 * @data: pointer to a network interface device structure 8015 **/ 8016 static irqreturn_t igb_intr_msi(int irq, void *data) 8017 { 8018 struct igb_adapter *adapter = data; 8019 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8020 struct e1000_hw *hw = &adapter->hw; 8021 /* read ICR disables interrupts using IAM */ 8022 u32 icr = rd32(E1000_ICR); 8023 8024 igb_write_itr(q_vector); 8025 8026 if (icr & E1000_ICR_DRSTA) 8027 schedule_work(&adapter->reset_task); 8028 8029 if (icr & E1000_ICR_DOUTSYNC) { 8030 /* HW is reporting DMA is out of sync */ 8031 adapter->stats.doosync++; 8032 } 8033 8034 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8035 hw->mac.get_link_status = 1; 8036 if (!test_bit(__IGB_DOWN, &adapter->state)) 8037 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8038 } 8039 8040 if (icr & E1000_ICR_TS) 8041 igb_tsync_interrupt(adapter); 8042 8043 napi_schedule(&q_vector->napi); 8044 8045 return IRQ_HANDLED; 8046 } 8047 8048 /** 8049 * igb_intr - Legacy Interrupt Handler 8050 * @irq: interrupt number 8051 * @data: pointer to a network interface device structure 8052 **/ 8053 static irqreturn_t igb_intr(int irq, void *data) 8054 { 8055 struct igb_adapter *adapter = data; 8056 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8057 struct e1000_hw *hw = &adapter->hw; 8058 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8059 * need for the IMC write 8060 */ 8061 u32 icr = rd32(E1000_ICR); 8062 8063 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8064 * not set, then the adapter didn't send an interrupt 8065 */ 8066 if (!(icr & E1000_ICR_INT_ASSERTED)) 8067 return IRQ_NONE; 8068 8069 igb_write_itr(q_vector); 8070 8071 if (icr & E1000_ICR_DRSTA) 8072 schedule_work(&adapter->reset_task); 8073 8074 if (icr & E1000_ICR_DOUTSYNC) { 8075 /* HW is reporting DMA is out of sync */ 8076 adapter->stats.doosync++; 8077 } 8078 8079 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8080 hw->mac.get_link_status = 1; 8081 /* guard against interrupt when we're going down */ 8082 if (!test_bit(__IGB_DOWN, &adapter->state)) 8083 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8084 } 8085 8086 if (icr & E1000_ICR_TS) 8087 igb_tsync_interrupt(adapter); 8088 8089 napi_schedule(&q_vector->napi); 8090 8091 return IRQ_HANDLED; 8092 } 8093 8094 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8095 { 8096 struct igb_adapter *adapter = q_vector->adapter; 8097 struct e1000_hw *hw = &adapter->hw; 8098 8099 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8100 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8101 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8102 igb_set_itr(q_vector); 8103 else 8104 igb_update_ring_itr(q_vector); 8105 } 8106 8107 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8108 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8109 wr32(E1000_EIMS, q_vector->eims_value); 8110 else 8111 igb_irq_enable(adapter); 8112 } 8113 } 8114 8115 /** 8116 * igb_poll - NAPI Rx polling callback 8117 * @napi: napi polling structure 8118 * @budget: count of how many packets we should handle 8119 **/ 8120 static int igb_poll(struct napi_struct *napi, int budget) 8121 { 8122 struct igb_q_vector *q_vector = container_of(napi, 8123 struct igb_q_vector, 8124 napi); 8125 bool clean_complete = true; 8126 int work_done = 0; 8127 8128 #ifdef CONFIG_IGB_DCA 8129 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8130 igb_update_dca(q_vector); 8131 #endif 8132 if (q_vector->tx.ring) 8133 clean_complete = igb_clean_tx_irq(q_vector, budget); 8134 8135 if (q_vector->rx.ring) { 8136 int cleaned = igb_clean_rx_irq(q_vector, budget); 8137 8138 work_done += cleaned; 8139 if (cleaned >= budget) 8140 clean_complete = false; 8141 } 8142 8143 /* If all work not completed, return budget and keep polling */ 8144 if (!clean_complete) 8145 return budget; 8146 8147 /* Exit the polling mode, but don't re-enable interrupts if stack might 8148 * poll us due to busy-polling 8149 */ 8150 if (likely(napi_complete_done(napi, work_done))) 8151 igb_ring_irq_enable(q_vector); 8152 8153 return work_done; 8154 } 8155 8156 /** 8157 * igb_clean_tx_irq - Reclaim resources after transmit completes 8158 * @q_vector: pointer to q_vector containing needed info 8159 * @napi_budget: Used to determine if we are in netpoll 8160 * 8161 * returns true if ring is completely cleaned 8162 **/ 8163 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8164 { 8165 struct igb_adapter *adapter = q_vector->adapter; 8166 struct igb_ring *tx_ring = q_vector->tx.ring; 8167 struct igb_tx_buffer *tx_buffer; 8168 union e1000_adv_tx_desc *tx_desc; 8169 unsigned int total_bytes = 0, total_packets = 0; 8170 unsigned int budget = q_vector->tx.work_limit; 8171 unsigned int i = tx_ring->next_to_clean; 8172 8173 if (test_bit(__IGB_DOWN, &adapter->state)) 8174 return true; 8175 8176 tx_buffer = &tx_ring->tx_buffer_info[i]; 8177 tx_desc = IGB_TX_DESC(tx_ring, i); 8178 i -= tx_ring->count; 8179 8180 do { 8181 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8182 8183 /* if next_to_watch is not set then there is no work pending */ 8184 if (!eop_desc) 8185 break; 8186 8187 /* prevent any other reads prior to eop_desc */ 8188 smp_rmb(); 8189 8190 /* if DD is not set pending work has not been completed */ 8191 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8192 break; 8193 8194 /* clear next_to_watch to prevent false hangs */ 8195 tx_buffer->next_to_watch = NULL; 8196 8197 /* update the statistics for this packet */ 8198 total_bytes += tx_buffer->bytecount; 8199 total_packets += tx_buffer->gso_segs; 8200 8201 /* free the skb */ 8202 if (tx_buffer->type == IGB_TYPE_SKB) 8203 napi_consume_skb(tx_buffer->skb, napi_budget); 8204 else 8205 xdp_return_frame(tx_buffer->xdpf); 8206 8207 /* unmap skb header data */ 8208 dma_unmap_single(tx_ring->dev, 8209 dma_unmap_addr(tx_buffer, dma), 8210 dma_unmap_len(tx_buffer, len), 8211 DMA_TO_DEVICE); 8212 8213 /* clear tx_buffer data */ 8214 dma_unmap_len_set(tx_buffer, len, 0); 8215 8216 /* clear last DMA location and unmap remaining buffers */ 8217 while (tx_desc != eop_desc) { 8218 tx_buffer++; 8219 tx_desc++; 8220 i++; 8221 if (unlikely(!i)) { 8222 i -= tx_ring->count; 8223 tx_buffer = tx_ring->tx_buffer_info; 8224 tx_desc = IGB_TX_DESC(tx_ring, 0); 8225 } 8226 8227 /* unmap any remaining paged data */ 8228 if (dma_unmap_len(tx_buffer, len)) { 8229 dma_unmap_page(tx_ring->dev, 8230 dma_unmap_addr(tx_buffer, dma), 8231 dma_unmap_len(tx_buffer, len), 8232 DMA_TO_DEVICE); 8233 dma_unmap_len_set(tx_buffer, len, 0); 8234 } 8235 } 8236 8237 /* move us one more past the eop_desc for start of next pkt */ 8238 tx_buffer++; 8239 tx_desc++; 8240 i++; 8241 if (unlikely(!i)) { 8242 i -= tx_ring->count; 8243 tx_buffer = tx_ring->tx_buffer_info; 8244 tx_desc = IGB_TX_DESC(tx_ring, 0); 8245 } 8246 8247 /* issue prefetch for next Tx descriptor */ 8248 prefetch(tx_desc); 8249 8250 /* update budget accounting */ 8251 budget--; 8252 } while (likely(budget)); 8253 8254 netdev_tx_completed_queue(txring_txq(tx_ring), 8255 total_packets, total_bytes); 8256 i += tx_ring->count; 8257 tx_ring->next_to_clean = i; 8258 u64_stats_update_begin(&tx_ring->tx_syncp); 8259 tx_ring->tx_stats.bytes += total_bytes; 8260 tx_ring->tx_stats.packets += total_packets; 8261 u64_stats_update_end(&tx_ring->tx_syncp); 8262 q_vector->tx.total_bytes += total_bytes; 8263 q_vector->tx.total_packets += total_packets; 8264 8265 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8266 struct e1000_hw *hw = &adapter->hw; 8267 8268 /* Detect a transmit hang in hardware, this serializes the 8269 * check with the clearing of time_stamp and movement of i 8270 */ 8271 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8272 if (tx_buffer->next_to_watch && 8273 time_after(jiffies, tx_buffer->time_stamp + 8274 (adapter->tx_timeout_factor * HZ)) && 8275 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8276 8277 /* detected Tx unit hang */ 8278 dev_err(tx_ring->dev, 8279 "Detected Tx Unit Hang\n" 8280 " Tx Queue <%d>\n" 8281 " TDH <%x>\n" 8282 " TDT <%x>\n" 8283 " next_to_use <%x>\n" 8284 " next_to_clean <%x>\n" 8285 "buffer_info[next_to_clean]\n" 8286 " time_stamp <%lx>\n" 8287 " next_to_watch <%p>\n" 8288 " jiffies <%lx>\n" 8289 " desc.status <%x>\n", 8290 tx_ring->queue_index, 8291 rd32(E1000_TDH(tx_ring->reg_idx)), 8292 readl(tx_ring->tail), 8293 tx_ring->next_to_use, 8294 tx_ring->next_to_clean, 8295 tx_buffer->time_stamp, 8296 tx_buffer->next_to_watch, 8297 jiffies, 8298 tx_buffer->next_to_watch->wb.status); 8299 netif_stop_subqueue(tx_ring->netdev, 8300 tx_ring->queue_index); 8301 8302 /* we are about to reset, no point in enabling stuff */ 8303 return true; 8304 } 8305 } 8306 8307 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8308 if (unlikely(total_packets && 8309 netif_carrier_ok(tx_ring->netdev) && 8310 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8311 /* Make sure that anybody stopping the queue after this 8312 * sees the new next_to_clean. 8313 */ 8314 smp_mb(); 8315 if (__netif_subqueue_stopped(tx_ring->netdev, 8316 tx_ring->queue_index) && 8317 !(test_bit(__IGB_DOWN, &adapter->state))) { 8318 netif_wake_subqueue(tx_ring->netdev, 8319 tx_ring->queue_index); 8320 8321 u64_stats_update_begin(&tx_ring->tx_syncp); 8322 tx_ring->tx_stats.restart_queue++; 8323 u64_stats_update_end(&tx_ring->tx_syncp); 8324 } 8325 } 8326 8327 return !!budget; 8328 } 8329 8330 /** 8331 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8332 * @rx_ring: rx descriptor ring to store buffers on 8333 * @old_buff: donor buffer to have page reused 8334 * 8335 * Synchronizes page for reuse by the adapter 8336 **/ 8337 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8338 struct igb_rx_buffer *old_buff) 8339 { 8340 struct igb_rx_buffer *new_buff; 8341 u16 nta = rx_ring->next_to_alloc; 8342 8343 new_buff = &rx_ring->rx_buffer_info[nta]; 8344 8345 /* update, and store next to alloc */ 8346 nta++; 8347 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8348 8349 /* Transfer page from old buffer to new buffer. 8350 * Move each member individually to avoid possible store 8351 * forwarding stalls. 8352 */ 8353 new_buff->dma = old_buff->dma; 8354 new_buff->page = old_buff->page; 8355 new_buff->page_offset = old_buff->page_offset; 8356 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8357 } 8358 8359 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8360 int rx_buf_pgcnt) 8361 { 8362 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8363 struct page *page = rx_buffer->page; 8364 8365 /* avoid re-using remote and pfmemalloc pages */ 8366 if (!dev_page_is_reusable(page)) 8367 return false; 8368 8369 #if (PAGE_SIZE < 8192) 8370 /* if we are only owner of page we can reuse it */ 8371 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8372 return false; 8373 #else 8374 #define IGB_LAST_OFFSET \ 8375 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8376 8377 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8378 return false; 8379 #endif 8380 8381 /* If we have drained the page fragment pool we need to update 8382 * the pagecnt_bias and page count so that we fully restock the 8383 * number of references the driver holds. 8384 */ 8385 if (unlikely(pagecnt_bias == 1)) { 8386 page_ref_add(page, USHRT_MAX - 1); 8387 rx_buffer->pagecnt_bias = USHRT_MAX; 8388 } 8389 8390 return true; 8391 } 8392 8393 /** 8394 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8395 * @rx_ring: rx descriptor ring to transact packets on 8396 * @rx_buffer: buffer containing page to add 8397 * @skb: sk_buff to place the data into 8398 * @size: size of buffer to be added 8399 * 8400 * This function will add the data contained in rx_buffer->page to the skb. 8401 **/ 8402 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8403 struct igb_rx_buffer *rx_buffer, 8404 struct sk_buff *skb, 8405 unsigned int size) 8406 { 8407 #if (PAGE_SIZE < 8192) 8408 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8409 #else 8410 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8411 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8412 SKB_DATA_ALIGN(size); 8413 #endif 8414 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8415 rx_buffer->page_offset, size, truesize); 8416 #if (PAGE_SIZE < 8192) 8417 rx_buffer->page_offset ^= truesize; 8418 #else 8419 rx_buffer->page_offset += truesize; 8420 #endif 8421 } 8422 8423 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8424 struct igb_rx_buffer *rx_buffer, 8425 struct xdp_buff *xdp, 8426 ktime_t timestamp) 8427 { 8428 #if (PAGE_SIZE < 8192) 8429 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8430 #else 8431 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8432 xdp->data_hard_start); 8433 #endif 8434 unsigned int size = xdp->data_end - xdp->data; 8435 unsigned int headlen; 8436 struct sk_buff *skb; 8437 8438 /* prefetch first cache line of first page */ 8439 net_prefetch(xdp->data); 8440 8441 /* allocate a skb to store the frags */ 8442 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8443 if (unlikely(!skb)) 8444 return NULL; 8445 8446 if (timestamp) 8447 skb_hwtstamps(skb)->hwtstamp = timestamp; 8448 8449 /* Determine available headroom for copy */ 8450 headlen = size; 8451 if (headlen > IGB_RX_HDR_LEN) 8452 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8453 8454 /* align pull length to size of long to optimize memcpy performance */ 8455 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8456 8457 /* update all of the pointers */ 8458 size -= headlen; 8459 if (size) { 8460 skb_add_rx_frag(skb, 0, rx_buffer->page, 8461 (xdp->data + headlen) - page_address(rx_buffer->page), 8462 size, truesize); 8463 #if (PAGE_SIZE < 8192) 8464 rx_buffer->page_offset ^= truesize; 8465 #else 8466 rx_buffer->page_offset += truesize; 8467 #endif 8468 } else { 8469 rx_buffer->pagecnt_bias++; 8470 } 8471 8472 return skb; 8473 } 8474 8475 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8476 struct igb_rx_buffer *rx_buffer, 8477 struct xdp_buff *xdp, 8478 ktime_t timestamp) 8479 { 8480 #if (PAGE_SIZE < 8192) 8481 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8482 #else 8483 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8484 SKB_DATA_ALIGN(xdp->data_end - 8485 xdp->data_hard_start); 8486 #endif 8487 unsigned int metasize = xdp->data - xdp->data_meta; 8488 struct sk_buff *skb; 8489 8490 /* prefetch first cache line of first page */ 8491 net_prefetch(xdp->data_meta); 8492 8493 /* build an skb around the page buffer */ 8494 skb = napi_build_skb(xdp->data_hard_start, truesize); 8495 if (unlikely(!skb)) 8496 return NULL; 8497 8498 /* update pointers within the skb to store the data */ 8499 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8500 __skb_put(skb, xdp->data_end - xdp->data); 8501 8502 if (metasize) 8503 skb_metadata_set(skb, metasize); 8504 8505 if (timestamp) 8506 skb_hwtstamps(skb)->hwtstamp = timestamp; 8507 8508 /* update buffer offset */ 8509 #if (PAGE_SIZE < 8192) 8510 rx_buffer->page_offset ^= truesize; 8511 #else 8512 rx_buffer->page_offset += truesize; 8513 #endif 8514 8515 return skb; 8516 } 8517 8518 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8519 struct igb_ring *rx_ring, 8520 struct xdp_buff *xdp) 8521 { 8522 int err, result = IGB_XDP_PASS; 8523 struct bpf_prog *xdp_prog; 8524 u32 act; 8525 8526 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8527 8528 if (!xdp_prog) 8529 goto xdp_out; 8530 8531 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8532 8533 act = bpf_prog_run_xdp(xdp_prog, xdp); 8534 switch (act) { 8535 case XDP_PASS: 8536 break; 8537 case XDP_TX: 8538 result = igb_xdp_xmit_back(adapter, xdp); 8539 if (result == IGB_XDP_CONSUMED) 8540 goto out_failure; 8541 break; 8542 case XDP_REDIRECT: 8543 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8544 if (err) 8545 goto out_failure; 8546 result = IGB_XDP_REDIR; 8547 break; 8548 default: 8549 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8550 fallthrough; 8551 case XDP_ABORTED: 8552 out_failure: 8553 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8554 fallthrough; 8555 case XDP_DROP: 8556 result = IGB_XDP_CONSUMED; 8557 break; 8558 } 8559 xdp_out: 8560 return ERR_PTR(-result); 8561 } 8562 8563 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8564 unsigned int size) 8565 { 8566 unsigned int truesize; 8567 8568 #if (PAGE_SIZE < 8192) 8569 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8570 #else 8571 truesize = ring_uses_build_skb(rx_ring) ? 8572 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8573 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8574 SKB_DATA_ALIGN(size); 8575 #endif 8576 return truesize; 8577 } 8578 8579 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8580 struct igb_rx_buffer *rx_buffer, 8581 unsigned int size) 8582 { 8583 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8584 #if (PAGE_SIZE < 8192) 8585 rx_buffer->page_offset ^= truesize; 8586 #else 8587 rx_buffer->page_offset += truesize; 8588 #endif 8589 } 8590 8591 static inline void igb_rx_checksum(struct igb_ring *ring, 8592 union e1000_adv_rx_desc *rx_desc, 8593 struct sk_buff *skb) 8594 { 8595 skb_checksum_none_assert(skb); 8596 8597 /* Ignore Checksum bit is set */ 8598 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8599 return; 8600 8601 /* Rx checksum disabled via ethtool */ 8602 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8603 return; 8604 8605 /* TCP/UDP checksum error bit is set */ 8606 if (igb_test_staterr(rx_desc, 8607 E1000_RXDEXT_STATERR_TCPE | 8608 E1000_RXDEXT_STATERR_IPE)) { 8609 /* work around errata with sctp packets where the TCPE aka 8610 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8611 * packets, (aka let the stack check the crc32c) 8612 */ 8613 if (!((skb->len == 60) && 8614 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8615 u64_stats_update_begin(&ring->rx_syncp); 8616 ring->rx_stats.csum_err++; 8617 u64_stats_update_end(&ring->rx_syncp); 8618 } 8619 /* let the stack verify checksum errors */ 8620 return; 8621 } 8622 /* It must be a TCP or UDP packet with a valid checksum */ 8623 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8624 E1000_RXD_STAT_UDPCS)) 8625 skb->ip_summed = CHECKSUM_UNNECESSARY; 8626 8627 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8628 le32_to_cpu(rx_desc->wb.upper.status_error)); 8629 } 8630 8631 static inline void igb_rx_hash(struct igb_ring *ring, 8632 union e1000_adv_rx_desc *rx_desc, 8633 struct sk_buff *skb) 8634 { 8635 if (ring->netdev->features & NETIF_F_RXHASH) 8636 skb_set_hash(skb, 8637 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8638 PKT_HASH_TYPE_L3); 8639 } 8640 8641 /** 8642 * igb_is_non_eop - process handling of non-EOP buffers 8643 * @rx_ring: Rx ring being processed 8644 * @rx_desc: Rx descriptor for current buffer 8645 * 8646 * This function updates next to clean. If the buffer is an EOP buffer 8647 * this function exits returning false, otherwise it will place the 8648 * sk_buff in the next buffer to be chained and return true indicating 8649 * that this is in fact a non-EOP buffer. 8650 **/ 8651 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8652 union e1000_adv_rx_desc *rx_desc) 8653 { 8654 u32 ntc = rx_ring->next_to_clean + 1; 8655 8656 /* fetch, update, and store next to clean */ 8657 ntc = (ntc < rx_ring->count) ? ntc : 0; 8658 rx_ring->next_to_clean = ntc; 8659 8660 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8661 8662 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8663 return false; 8664 8665 return true; 8666 } 8667 8668 /** 8669 * igb_cleanup_headers - Correct corrupted or empty headers 8670 * @rx_ring: rx descriptor ring packet is being transacted on 8671 * @rx_desc: pointer to the EOP Rx descriptor 8672 * @skb: pointer to current skb being fixed 8673 * 8674 * Address the case where we are pulling data in on pages only 8675 * and as such no data is present in the skb header. 8676 * 8677 * In addition if skb is not at least 60 bytes we need to pad it so that 8678 * it is large enough to qualify as a valid Ethernet frame. 8679 * 8680 * Returns true if an error was encountered and skb was freed. 8681 **/ 8682 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8683 union e1000_adv_rx_desc *rx_desc, 8684 struct sk_buff *skb) 8685 { 8686 /* XDP packets use error pointer so abort at this point */ 8687 if (IS_ERR(skb)) 8688 return true; 8689 8690 if (unlikely((igb_test_staterr(rx_desc, 8691 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8692 struct net_device *netdev = rx_ring->netdev; 8693 if (!(netdev->features & NETIF_F_RXALL)) { 8694 dev_kfree_skb_any(skb); 8695 return true; 8696 } 8697 } 8698 8699 /* if eth_skb_pad returns an error the skb was freed */ 8700 if (eth_skb_pad(skb)) 8701 return true; 8702 8703 return false; 8704 } 8705 8706 /** 8707 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8708 * @rx_ring: rx descriptor ring packet is being transacted on 8709 * @rx_desc: pointer to the EOP Rx descriptor 8710 * @skb: pointer to current skb being populated 8711 * 8712 * This function checks the ring, descriptor, and packet information in 8713 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8714 * other fields within the skb. 8715 **/ 8716 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8717 union e1000_adv_rx_desc *rx_desc, 8718 struct sk_buff *skb) 8719 { 8720 struct net_device *dev = rx_ring->netdev; 8721 8722 igb_rx_hash(rx_ring, rx_desc, skb); 8723 8724 igb_rx_checksum(rx_ring, rx_desc, skb); 8725 8726 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8727 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8728 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8729 8730 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8731 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8732 u16 vid; 8733 8734 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8735 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8736 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8737 else 8738 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8739 8740 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8741 } 8742 8743 skb_record_rx_queue(skb, rx_ring->queue_index); 8744 8745 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8746 } 8747 8748 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8749 { 8750 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8751 } 8752 8753 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8754 const unsigned int size, int *rx_buf_pgcnt) 8755 { 8756 struct igb_rx_buffer *rx_buffer; 8757 8758 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8759 *rx_buf_pgcnt = 8760 #if (PAGE_SIZE < 8192) 8761 page_count(rx_buffer->page); 8762 #else 8763 0; 8764 #endif 8765 prefetchw(rx_buffer->page); 8766 8767 /* we are reusing so sync this buffer for CPU use */ 8768 dma_sync_single_range_for_cpu(rx_ring->dev, 8769 rx_buffer->dma, 8770 rx_buffer->page_offset, 8771 size, 8772 DMA_FROM_DEVICE); 8773 8774 rx_buffer->pagecnt_bias--; 8775 8776 return rx_buffer; 8777 } 8778 8779 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8780 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8781 { 8782 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8783 /* hand second half of page back to the ring */ 8784 igb_reuse_rx_page(rx_ring, rx_buffer); 8785 } else { 8786 /* We are not reusing the buffer so unmap it and free 8787 * any references we are holding to it 8788 */ 8789 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8790 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8791 IGB_RX_DMA_ATTR); 8792 __page_frag_cache_drain(rx_buffer->page, 8793 rx_buffer->pagecnt_bias); 8794 } 8795 8796 /* clear contents of rx_buffer */ 8797 rx_buffer->page = NULL; 8798 } 8799 8800 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8801 { 8802 struct igb_adapter *adapter = q_vector->adapter; 8803 struct igb_ring *rx_ring = q_vector->rx.ring; 8804 struct sk_buff *skb = rx_ring->skb; 8805 unsigned int total_bytes = 0, total_packets = 0; 8806 u16 cleaned_count = igb_desc_unused(rx_ring); 8807 unsigned int xdp_xmit = 0; 8808 struct xdp_buff xdp; 8809 u32 frame_sz = 0; 8810 int rx_buf_pgcnt; 8811 8812 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8813 #if (PAGE_SIZE < 8192) 8814 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8815 #endif 8816 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8817 8818 while (likely(total_packets < budget)) { 8819 union e1000_adv_rx_desc *rx_desc; 8820 struct igb_rx_buffer *rx_buffer; 8821 ktime_t timestamp = 0; 8822 int pkt_offset = 0; 8823 unsigned int size; 8824 void *pktbuf; 8825 8826 /* return some buffers to hardware, one at a time is too slow */ 8827 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8828 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8829 cleaned_count = 0; 8830 } 8831 8832 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8833 size = le16_to_cpu(rx_desc->wb.upper.length); 8834 if (!size) 8835 break; 8836 8837 /* This memory barrier is needed to keep us from reading 8838 * any other fields out of the rx_desc until we know the 8839 * descriptor has been written back 8840 */ 8841 dma_rmb(); 8842 8843 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8844 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8845 8846 /* pull rx packet timestamp if available and valid */ 8847 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8848 int ts_hdr_len; 8849 8850 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8851 pktbuf, ×tamp); 8852 8853 pkt_offset += ts_hdr_len; 8854 size -= ts_hdr_len; 8855 } 8856 8857 /* retrieve a buffer from the ring */ 8858 if (!skb) { 8859 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8860 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8861 8862 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8863 xdp_buff_clear_frags_flag(&xdp); 8864 #if (PAGE_SIZE > 4096) 8865 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8866 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8867 #endif 8868 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8869 } 8870 8871 if (IS_ERR(skb)) { 8872 unsigned int xdp_res = -PTR_ERR(skb); 8873 8874 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8875 xdp_xmit |= xdp_res; 8876 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8877 } else { 8878 rx_buffer->pagecnt_bias++; 8879 } 8880 total_packets++; 8881 total_bytes += size; 8882 } else if (skb) 8883 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8884 else if (ring_uses_build_skb(rx_ring)) 8885 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8886 timestamp); 8887 else 8888 skb = igb_construct_skb(rx_ring, rx_buffer, 8889 &xdp, timestamp); 8890 8891 /* exit if we failed to retrieve a buffer */ 8892 if (!skb) { 8893 rx_ring->rx_stats.alloc_failed++; 8894 rx_buffer->pagecnt_bias++; 8895 break; 8896 } 8897 8898 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8899 cleaned_count++; 8900 8901 /* fetch next buffer in frame if non-eop */ 8902 if (igb_is_non_eop(rx_ring, rx_desc)) 8903 continue; 8904 8905 /* verify the packet layout is correct */ 8906 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8907 skb = NULL; 8908 continue; 8909 } 8910 8911 /* probably a little skewed due to removing CRC */ 8912 total_bytes += skb->len; 8913 8914 /* populate checksum, timestamp, VLAN, and protocol */ 8915 igb_process_skb_fields(rx_ring, rx_desc, skb); 8916 8917 napi_gro_receive(&q_vector->napi, skb); 8918 8919 /* reset skb pointer */ 8920 skb = NULL; 8921 8922 /* update budget accounting */ 8923 total_packets++; 8924 } 8925 8926 /* place incomplete frames back on ring for completion */ 8927 rx_ring->skb = skb; 8928 8929 if (xdp_xmit & IGB_XDP_REDIR) 8930 xdp_do_flush(); 8931 8932 if (xdp_xmit & IGB_XDP_TX) { 8933 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8934 8935 igb_xdp_ring_update_tail(tx_ring); 8936 } 8937 8938 u64_stats_update_begin(&rx_ring->rx_syncp); 8939 rx_ring->rx_stats.packets += total_packets; 8940 rx_ring->rx_stats.bytes += total_bytes; 8941 u64_stats_update_end(&rx_ring->rx_syncp); 8942 q_vector->rx.total_packets += total_packets; 8943 q_vector->rx.total_bytes += total_bytes; 8944 8945 if (cleaned_count) 8946 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8947 8948 return total_packets; 8949 } 8950 8951 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8952 struct igb_rx_buffer *bi) 8953 { 8954 struct page *page = bi->page; 8955 dma_addr_t dma; 8956 8957 /* since we are recycling buffers we should seldom need to alloc */ 8958 if (likely(page)) 8959 return true; 8960 8961 /* alloc new page for storage */ 8962 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8963 if (unlikely(!page)) { 8964 rx_ring->rx_stats.alloc_failed++; 8965 return false; 8966 } 8967 8968 /* map page for use */ 8969 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8970 igb_rx_pg_size(rx_ring), 8971 DMA_FROM_DEVICE, 8972 IGB_RX_DMA_ATTR); 8973 8974 /* if mapping failed free memory back to system since 8975 * there isn't much point in holding memory we can't use 8976 */ 8977 if (dma_mapping_error(rx_ring->dev, dma)) { 8978 __free_pages(page, igb_rx_pg_order(rx_ring)); 8979 8980 rx_ring->rx_stats.alloc_failed++; 8981 return false; 8982 } 8983 8984 bi->dma = dma; 8985 bi->page = page; 8986 bi->page_offset = igb_rx_offset(rx_ring); 8987 page_ref_add(page, USHRT_MAX - 1); 8988 bi->pagecnt_bias = USHRT_MAX; 8989 8990 return true; 8991 } 8992 8993 /** 8994 * igb_alloc_rx_buffers - Replace used receive buffers 8995 * @rx_ring: rx descriptor ring to allocate new receive buffers 8996 * @cleaned_count: count of buffers to allocate 8997 **/ 8998 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8999 { 9000 union e1000_adv_rx_desc *rx_desc; 9001 struct igb_rx_buffer *bi; 9002 u16 i = rx_ring->next_to_use; 9003 u16 bufsz; 9004 9005 /* nothing to do */ 9006 if (!cleaned_count) 9007 return; 9008 9009 rx_desc = IGB_RX_DESC(rx_ring, i); 9010 bi = &rx_ring->rx_buffer_info[i]; 9011 i -= rx_ring->count; 9012 9013 bufsz = igb_rx_bufsz(rx_ring); 9014 9015 do { 9016 if (!igb_alloc_mapped_page(rx_ring, bi)) 9017 break; 9018 9019 /* sync the buffer for use by the device */ 9020 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9021 bi->page_offset, bufsz, 9022 DMA_FROM_DEVICE); 9023 9024 /* Refresh the desc even if buffer_addrs didn't change 9025 * because each write-back erases this info. 9026 */ 9027 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9028 9029 rx_desc++; 9030 bi++; 9031 i++; 9032 if (unlikely(!i)) { 9033 rx_desc = IGB_RX_DESC(rx_ring, 0); 9034 bi = rx_ring->rx_buffer_info; 9035 i -= rx_ring->count; 9036 } 9037 9038 /* clear the length for the next_to_use descriptor */ 9039 rx_desc->wb.upper.length = 0; 9040 9041 cleaned_count--; 9042 } while (cleaned_count); 9043 9044 i += rx_ring->count; 9045 9046 if (rx_ring->next_to_use != i) { 9047 /* record the next descriptor to use */ 9048 rx_ring->next_to_use = i; 9049 9050 /* update next to alloc since we have filled the ring */ 9051 rx_ring->next_to_alloc = i; 9052 9053 /* Force memory writes to complete before letting h/w 9054 * know there are new descriptors to fetch. (Only 9055 * applicable for weak-ordered memory model archs, 9056 * such as IA-64). 9057 */ 9058 dma_wmb(); 9059 writel(i, rx_ring->tail); 9060 } 9061 } 9062 9063 /** 9064 * igb_mii_ioctl - 9065 * @netdev: pointer to netdev struct 9066 * @ifr: interface structure 9067 * @cmd: ioctl command to execute 9068 **/ 9069 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9070 { 9071 struct igb_adapter *adapter = netdev_priv(netdev); 9072 struct mii_ioctl_data *data = if_mii(ifr); 9073 9074 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9075 return -EOPNOTSUPP; 9076 9077 switch (cmd) { 9078 case SIOCGMIIPHY: 9079 data->phy_id = adapter->hw.phy.addr; 9080 break; 9081 case SIOCGMIIREG: 9082 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9083 &data->val_out)) 9084 return -EIO; 9085 break; 9086 case SIOCSMIIREG: 9087 default: 9088 return -EOPNOTSUPP; 9089 } 9090 return 0; 9091 } 9092 9093 /** 9094 * igb_ioctl - 9095 * @netdev: pointer to netdev struct 9096 * @ifr: interface structure 9097 * @cmd: ioctl command to execute 9098 **/ 9099 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9100 { 9101 switch (cmd) { 9102 case SIOCGMIIPHY: 9103 case SIOCGMIIREG: 9104 case SIOCSMIIREG: 9105 return igb_mii_ioctl(netdev, ifr, cmd); 9106 case SIOCGHWTSTAMP: 9107 return igb_ptp_get_ts_config(netdev, ifr); 9108 case SIOCSHWTSTAMP: 9109 return igb_ptp_set_ts_config(netdev, ifr); 9110 default: 9111 return -EOPNOTSUPP; 9112 } 9113 } 9114 9115 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9116 { 9117 struct igb_adapter *adapter = hw->back; 9118 9119 pci_read_config_word(adapter->pdev, reg, value); 9120 } 9121 9122 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9123 { 9124 struct igb_adapter *adapter = hw->back; 9125 9126 pci_write_config_word(adapter->pdev, reg, *value); 9127 } 9128 9129 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9130 { 9131 struct igb_adapter *adapter = hw->back; 9132 9133 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9134 return -E1000_ERR_CONFIG; 9135 9136 return 0; 9137 } 9138 9139 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9140 { 9141 struct igb_adapter *adapter = hw->back; 9142 9143 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9144 return -E1000_ERR_CONFIG; 9145 9146 return 0; 9147 } 9148 9149 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9150 { 9151 struct igb_adapter *adapter = netdev_priv(netdev); 9152 struct e1000_hw *hw = &adapter->hw; 9153 u32 ctrl, rctl; 9154 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9155 9156 if (enable) { 9157 /* enable VLAN tag insert/strip */ 9158 ctrl = rd32(E1000_CTRL); 9159 ctrl |= E1000_CTRL_VME; 9160 wr32(E1000_CTRL, ctrl); 9161 9162 /* Disable CFI check */ 9163 rctl = rd32(E1000_RCTL); 9164 rctl &= ~E1000_RCTL_CFIEN; 9165 wr32(E1000_RCTL, rctl); 9166 } else { 9167 /* disable VLAN tag insert/strip */ 9168 ctrl = rd32(E1000_CTRL); 9169 ctrl &= ~E1000_CTRL_VME; 9170 wr32(E1000_CTRL, ctrl); 9171 } 9172 9173 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9174 } 9175 9176 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9177 __be16 proto, u16 vid) 9178 { 9179 struct igb_adapter *adapter = netdev_priv(netdev); 9180 struct e1000_hw *hw = &adapter->hw; 9181 int pf_id = adapter->vfs_allocated_count; 9182 9183 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9184 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9185 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9186 9187 set_bit(vid, adapter->active_vlans); 9188 9189 return 0; 9190 } 9191 9192 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9193 __be16 proto, u16 vid) 9194 { 9195 struct igb_adapter *adapter = netdev_priv(netdev); 9196 int pf_id = adapter->vfs_allocated_count; 9197 struct e1000_hw *hw = &adapter->hw; 9198 9199 /* remove VID from filter table */ 9200 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9201 igb_vfta_set(hw, vid, pf_id, false, true); 9202 9203 clear_bit(vid, adapter->active_vlans); 9204 9205 return 0; 9206 } 9207 9208 static void igb_restore_vlan(struct igb_adapter *adapter) 9209 { 9210 u16 vid = 1; 9211 9212 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9213 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9214 9215 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9216 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9217 } 9218 9219 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9220 { 9221 struct pci_dev *pdev = adapter->pdev; 9222 struct e1000_mac_info *mac = &adapter->hw.mac; 9223 9224 mac->autoneg = 0; 9225 9226 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9227 * for the switch() below to work 9228 */ 9229 if ((spd & 1) || (dplx & ~1)) 9230 goto err_inval; 9231 9232 /* Fiber NIC's only allow 1000 gbps Full duplex 9233 * and 100Mbps Full duplex for 100baseFx sfp 9234 */ 9235 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9236 switch (spd + dplx) { 9237 case SPEED_10 + DUPLEX_HALF: 9238 case SPEED_10 + DUPLEX_FULL: 9239 case SPEED_100 + DUPLEX_HALF: 9240 goto err_inval; 9241 default: 9242 break; 9243 } 9244 } 9245 9246 switch (spd + dplx) { 9247 case SPEED_10 + DUPLEX_HALF: 9248 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9249 break; 9250 case SPEED_10 + DUPLEX_FULL: 9251 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9252 break; 9253 case SPEED_100 + DUPLEX_HALF: 9254 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9255 break; 9256 case SPEED_100 + DUPLEX_FULL: 9257 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9258 break; 9259 case SPEED_1000 + DUPLEX_FULL: 9260 mac->autoneg = 1; 9261 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9262 break; 9263 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9264 default: 9265 goto err_inval; 9266 } 9267 9268 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9269 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9270 9271 return 0; 9272 9273 err_inval: 9274 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9275 return -EINVAL; 9276 } 9277 9278 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9279 bool runtime) 9280 { 9281 struct net_device *netdev = pci_get_drvdata(pdev); 9282 struct igb_adapter *adapter = netdev_priv(netdev); 9283 struct e1000_hw *hw = &adapter->hw; 9284 u32 ctrl, rctl, status; 9285 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9286 bool wake; 9287 9288 rtnl_lock(); 9289 netif_device_detach(netdev); 9290 9291 if (netif_running(netdev)) 9292 __igb_close(netdev, true); 9293 9294 igb_ptp_suspend(adapter); 9295 9296 igb_clear_interrupt_scheme(adapter); 9297 rtnl_unlock(); 9298 9299 status = rd32(E1000_STATUS); 9300 if (status & E1000_STATUS_LU) 9301 wufc &= ~E1000_WUFC_LNKC; 9302 9303 if (wufc) { 9304 igb_setup_rctl(adapter); 9305 igb_set_rx_mode(netdev); 9306 9307 /* turn on all-multi mode if wake on multicast is enabled */ 9308 if (wufc & E1000_WUFC_MC) { 9309 rctl = rd32(E1000_RCTL); 9310 rctl |= E1000_RCTL_MPE; 9311 wr32(E1000_RCTL, rctl); 9312 } 9313 9314 ctrl = rd32(E1000_CTRL); 9315 ctrl |= E1000_CTRL_ADVD3WUC; 9316 wr32(E1000_CTRL, ctrl); 9317 9318 /* Allow time for pending master requests to run */ 9319 igb_disable_pcie_master(hw); 9320 9321 wr32(E1000_WUC, E1000_WUC_PME_EN); 9322 wr32(E1000_WUFC, wufc); 9323 } else { 9324 wr32(E1000_WUC, 0); 9325 wr32(E1000_WUFC, 0); 9326 } 9327 9328 wake = wufc || adapter->en_mng_pt; 9329 if (!wake) 9330 igb_power_down_link(adapter); 9331 else 9332 igb_power_up_link(adapter); 9333 9334 if (enable_wake) 9335 *enable_wake = wake; 9336 9337 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9338 * would have already happened in close and is redundant. 9339 */ 9340 igb_release_hw_control(adapter); 9341 9342 pci_disable_device(pdev); 9343 9344 return 0; 9345 } 9346 9347 static void igb_deliver_wake_packet(struct net_device *netdev) 9348 { 9349 struct igb_adapter *adapter = netdev_priv(netdev); 9350 struct e1000_hw *hw = &adapter->hw; 9351 struct sk_buff *skb; 9352 u32 wupl; 9353 9354 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9355 9356 /* WUPM stores only the first 128 bytes of the wake packet. 9357 * Read the packet only if we have the whole thing. 9358 */ 9359 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9360 return; 9361 9362 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9363 if (!skb) 9364 return; 9365 9366 skb_put(skb, wupl); 9367 9368 /* Ensure reads are 32-bit aligned */ 9369 wupl = roundup(wupl, 4); 9370 9371 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9372 9373 skb->protocol = eth_type_trans(skb, netdev); 9374 netif_rx(skb); 9375 } 9376 9377 static int __maybe_unused igb_suspend(struct device *dev) 9378 { 9379 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9380 } 9381 9382 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9383 { 9384 struct pci_dev *pdev = to_pci_dev(dev); 9385 struct net_device *netdev = pci_get_drvdata(pdev); 9386 struct igb_adapter *adapter = netdev_priv(netdev); 9387 struct e1000_hw *hw = &adapter->hw; 9388 u32 err, val; 9389 9390 pci_set_power_state(pdev, PCI_D0); 9391 pci_restore_state(pdev); 9392 pci_save_state(pdev); 9393 9394 if (!pci_device_is_present(pdev)) 9395 return -ENODEV; 9396 err = pci_enable_device_mem(pdev); 9397 if (err) { 9398 dev_err(&pdev->dev, 9399 "igb: Cannot enable PCI device from suspend\n"); 9400 return err; 9401 } 9402 pci_set_master(pdev); 9403 9404 pci_enable_wake(pdev, PCI_D3hot, 0); 9405 pci_enable_wake(pdev, PCI_D3cold, 0); 9406 9407 if (igb_init_interrupt_scheme(adapter, true)) { 9408 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9409 return -ENOMEM; 9410 } 9411 9412 igb_reset(adapter); 9413 9414 /* let the f/w know that the h/w is now under the control of the 9415 * driver. 9416 */ 9417 igb_get_hw_control(adapter); 9418 9419 val = rd32(E1000_WUS); 9420 if (val & WAKE_PKT_WUS) 9421 igb_deliver_wake_packet(netdev); 9422 9423 wr32(E1000_WUS, ~0); 9424 9425 if (!rpm) 9426 rtnl_lock(); 9427 if (!err && netif_running(netdev)) 9428 err = __igb_open(netdev, true); 9429 9430 if (!err) 9431 netif_device_attach(netdev); 9432 if (!rpm) 9433 rtnl_unlock(); 9434 9435 return err; 9436 } 9437 9438 static int __maybe_unused igb_resume(struct device *dev) 9439 { 9440 return __igb_resume(dev, false); 9441 } 9442 9443 static int __maybe_unused igb_runtime_idle(struct device *dev) 9444 { 9445 struct net_device *netdev = dev_get_drvdata(dev); 9446 struct igb_adapter *adapter = netdev_priv(netdev); 9447 9448 if (!igb_has_link(adapter)) 9449 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9450 9451 return -EBUSY; 9452 } 9453 9454 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9455 { 9456 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9457 } 9458 9459 static int __maybe_unused igb_runtime_resume(struct device *dev) 9460 { 9461 return __igb_resume(dev, true); 9462 } 9463 9464 static void igb_shutdown(struct pci_dev *pdev) 9465 { 9466 bool wake; 9467 9468 __igb_shutdown(pdev, &wake, 0); 9469 9470 if (system_state == SYSTEM_POWER_OFF) { 9471 pci_wake_from_d3(pdev, wake); 9472 pci_set_power_state(pdev, PCI_D3hot); 9473 } 9474 } 9475 9476 #ifdef CONFIG_PCI_IOV 9477 static int igb_sriov_reinit(struct pci_dev *dev) 9478 { 9479 struct net_device *netdev = pci_get_drvdata(dev); 9480 struct igb_adapter *adapter = netdev_priv(netdev); 9481 struct pci_dev *pdev = adapter->pdev; 9482 9483 rtnl_lock(); 9484 9485 if (netif_running(netdev)) 9486 igb_close(netdev); 9487 else 9488 igb_reset(adapter); 9489 9490 igb_clear_interrupt_scheme(adapter); 9491 9492 igb_init_queue_configuration(adapter); 9493 9494 if (igb_init_interrupt_scheme(adapter, true)) { 9495 rtnl_unlock(); 9496 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9497 return -ENOMEM; 9498 } 9499 9500 if (netif_running(netdev)) 9501 igb_open(netdev); 9502 9503 rtnl_unlock(); 9504 9505 return 0; 9506 } 9507 9508 static int igb_pci_disable_sriov(struct pci_dev *dev) 9509 { 9510 int err = igb_disable_sriov(dev); 9511 9512 if (!err) 9513 err = igb_sriov_reinit(dev); 9514 9515 return err; 9516 } 9517 9518 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9519 { 9520 int err = igb_enable_sriov(dev, num_vfs); 9521 9522 if (err) 9523 goto out; 9524 9525 err = igb_sriov_reinit(dev); 9526 if (!err) 9527 return num_vfs; 9528 9529 out: 9530 return err; 9531 } 9532 9533 #endif 9534 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9535 { 9536 #ifdef CONFIG_PCI_IOV 9537 if (num_vfs == 0) 9538 return igb_pci_disable_sriov(dev); 9539 else 9540 return igb_pci_enable_sriov(dev, num_vfs); 9541 #endif 9542 return 0; 9543 } 9544 9545 /** 9546 * igb_io_error_detected - called when PCI error is detected 9547 * @pdev: Pointer to PCI device 9548 * @state: The current pci connection state 9549 * 9550 * This function is called after a PCI bus error affecting 9551 * this device has been detected. 9552 **/ 9553 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9554 pci_channel_state_t state) 9555 { 9556 struct net_device *netdev = pci_get_drvdata(pdev); 9557 struct igb_adapter *adapter = netdev_priv(netdev); 9558 9559 netif_device_detach(netdev); 9560 9561 if (state == pci_channel_io_perm_failure) 9562 return PCI_ERS_RESULT_DISCONNECT; 9563 9564 if (netif_running(netdev)) 9565 igb_down(adapter); 9566 pci_disable_device(pdev); 9567 9568 /* Request a slot reset. */ 9569 return PCI_ERS_RESULT_NEED_RESET; 9570 } 9571 9572 /** 9573 * igb_io_slot_reset - called after the pci bus has been reset. 9574 * @pdev: Pointer to PCI device 9575 * 9576 * Restart the card from scratch, as if from a cold-boot. Implementation 9577 * resembles the first-half of the __igb_resume routine. 9578 **/ 9579 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9580 { 9581 struct net_device *netdev = pci_get_drvdata(pdev); 9582 struct igb_adapter *adapter = netdev_priv(netdev); 9583 struct e1000_hw *hw = &adapter->hw; 9584 pci_ers_result_t result; 9585 9586 if (pci_enable_device_mem(pdev)) { 9587 dev_err(&pdev->dev, 9588 "Cannot re-enable PCI device after reset.\n"); 9589 result = PCI_ERS_RESULT_DISCONNECT; 9590 } else { 9591 pci_set_master(pdev); 9592 pci_restore_state(pdev); 9593 pci_save_state(pdev); 9594 9595 pci_enable_wake(pdev, PCI_D3hot, 0); 9596 pci_enable_wake(pdev, PCI_D3cold, 0); 9597 9598 /* In case of PCI error, adapter lose its HW address 9599 * so we should re-assign it here. 9600 */ 9601 hw->hw_addr = adapter->io_addr; 9602 9603 igb_reset(adapter); 9604 wr32(E1000_WUS, ~0); 9605 result = PCI_ERS_RESULT_RECOVERED; 9606 } 9607 9608 return result; 9609 } 9610 9611 /** 9612 * igb_io_resume - called when traffic can start flowing again. 9613 * @pdev: Pointer to PCI device 9614 * 9615 * This callback is called when the error recovery driver tells us that 9616 * its OK to resume normal operation. Implementation resembles the 9617 * second-half of the __igb_resume routine. 9618 */ 9619 static void igb_io_resume(struct pci_dev *pdev) 9620 { 9621 struct net_device *netdev = pci_get_drvdata(pdev); 9622 struct igb_adapter *adapter = netdev_priv(netdev); 9623 9624 if (netif_running(netdev)) { 9625 if (igb_up(adapter)) { 9626 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9627 return; 9628 } 9629 } 9630 9631 netif_device_attach(netdev); 9632 9633 /* let the f/w know that the h/w is now under the control of the 9634 * driver. 9635 */ 9636 igb_get_hw_control(adapter); 9637 } 9638 9639 /** 9640 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9641 * @adapter: Pointer to adapter structure 9642 * @index: Index of the RAR entry which need to be synced with MAC table 9643 **/ 9644 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9645 { 9646 struct e1000_hw *hw = &adapter->hw; 9647 u32 rar_low, rar_high; 9648 u8 *addr = adapter->mac_table[index].addr; 9649 9650 /* HW expects these to be in network order when they are plugged 9651 * into the registers which are little endian. In order to guarantee 9652 * that ordering we need to do an leXX_to_cpup here in order to be 9653 * ready for the byteswap that occurs with writel 9654 */ 9655 rar_low = le32_to_cpup((__le32 *)(addr)); 9656 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9657 9658 /* Indicate to hardware the Address is Valid. */ 9659 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9660 if (is_valid_ether_addr(addr)) 9661 rar_high |= E1000_RAH_AV; 9662 9663 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9664 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9665 9666 switch (hw->mac.type) { 9667 case e1000_82575: 9668 case e1000_i210: 9669 if (adapter->mac_table[index].state & 9670 IGB_MAC_STATE_QUEUE_STEERING) 9671 rar_high |= E1000_RAH_QSEL_ENABLE; 9672 9673 rar_high |= E1000_RAH_POOL_1 * 9674 adapter->mac_table[index].queue; 9675 break; 9676 default: 9677 rar_high |= E1000_RAH_POOL_1 << 9678 adapter->mac_table[index].queue; 9679 break; 9680 } 9681 } 9682 9683 wr32(E1000_RAL(index), rar_low); 9684 wrfl(); 9685 wr32(E1000_RAH(index), rar_high); 9686 wrfl(); 9687 } 9688 9689 static int igb_set_vf_mac(struct igb_adapter *adapter, 9690 int vf, unsigned char *mac_addr) 9691 { 9692 struct e1000_hw *hw = &adapter->hw; 9693 /* VF MAC addresses start at end of receive addresses and moves 9694 * towards the first, as a result a collision should not be possible 9695 */ 9696 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9697 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9698 9699 ether_addr_copy(vf_mac_addr, mac_addr); 9700 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9701 adapter->mac_table[rar_entry].queue = vf; 9702 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9703 igb_rar_set_index(adapter, rar_entry); 9704 9705 return 0; 9706 } 9707 9708 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9709 { 9710 struct igb_adapter *adapter = netdev_priv(netdev); 9711 9712 if (vf >= adapter->vfs_allocated_count) 9713 return -EINVAL; 9714 9715 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9716 * flag and allows to overwrite the MAC via VF netdev. This 9717 * is necessary to allow libvirt a way to restore the original 9718 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9719 * down a VM. 9720 */ 9721 if (is_zero_ether_addr(mac)) { 9722 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9723 dev_info(&adapter->pdev->dev, 9724 "remove administratively set MAC on VF %d\n", 9725 vf); 9726 } else if (is_valid_ether_addr(mac)) { 9727 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9728 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9729 mac, vf); 9730 dev_info(&adapter->pdev->dev, 9731 "Reload the VF driver to make this change effective."); 9732 /* Generate additional warning if PF is down */ 9733 if (test_bit(__IGB_DOWN, &adapter->state)) { 9734 dev_warn(&adapter->pdev->dev, 9735 "The VF MAC address has been set, but the PF device is not up.\n"); 9736 dev_warn(&adapter->pdev->dev, 9737 "Bring the PF device up before attempting to use the VF device.\n"); 9738 } 9739 } else { 9740 return -EINVAL; 9741 } 9742 return igb_set_vf_mac(adapter, vf, mac); 9743 } 9744 9745 static int igb_link_mbps(int internal_link_speed) 9746 { 9747 switch (internal_link_speed) { 9748 case SPEED_100: 9749 return 100; 9750 case SPEED_1000: 9751 return 1000; 9752 default: 9753 return 0; 9754 } 9755 } 9756 9757 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9758 int link_speed) 9759 { 9760 int rf_dec, rf_int; 9761 u32 bcnrc_val; 9762 9763 if (tx_rate != 0) { 9764 /* Calculate the rate factor values to set */ 9765 rf_int = link_speed / tx_rate; 9766 rf_dec = (link_speed - (rf_int * tx_rate)); 9767 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9768 tx_rate; 9769 9770 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9771 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9772 E1000_RTTBCNRC_RF_INT_MASK); 9773 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9774 } else { 9775 bcnrc_val = 0; 9776 } 9777 9778 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9779 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9780 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9781 */ 9782 wr32(E1000_RTTBCNRM, 0x14); 9783 wr32(E1000_RTTBCNRC, bcnrc_val); 9784 } 9785 9786 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9787 { 9788 int actual_link_speed, i; 9789 bool reset_rate = false; 9790 9791 /* VF TX rate limit was not set or not supported */ 9792 if ((adapter->vf_rate_link_speed == 0) || 9793 (adapter->hw.mac.type != e1000_82576)) 9794 return; 9795 9796 actual_link_speed = igb_link_mbps(adapter->link_speed); 9797 if (actual_link_speed != adapter->vf_rate_link_speed) { 9798 reset_rate = true; 9799 adapter->vf_rate_link_speed = 0; 9800 dev_info(&adapter->pdev->dev, 9801 "Link speed has been changed. VF Transmit rate is disabled\n"); 9802 } 9803 9804 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9805 if (reset_rate) 9806 adapter->vf_data[i].tx_rate = 0; 9807 9808 igb_set_vf_rate_limit(&adapter->hw, i, 9809 adapter->vf_data[i].tx_rate, 9810 actual_link_speed); 9811 } 9812 } 9813 9814 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9815 int min_tx_rate, int max_tx_rate) 9816 { 9817 struct igb_adapter *adapter = netdev_priv(netdev); 9818 struct e1000_hw *hw = &adapter->hw; 9819 int actual_link_speed; 9820 9821 if (hw->mac.type != e1000_82576) 9822 return -EOPNOTSUPP; 9823 9824 if (min_tx_rate) 9825 return -EINVAL; 9826 9827 actual_link_speed = igb_link_mbps(adapter->link_speed); 9828 if ((vf >= adapter->vfs_allocated_count) || 9829 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9830 (max_tx_rate < 0) || 9831 (max_tx_rate > actual_link_speed)) 9832 return -EINVAL; 9833 9834 adapter->vf_rate_link_speed = actual_link_speed; 9835 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9836 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9837 9838 return 0; 9839 } 9840 9841 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9842 bool setting) 9843 { 9844 struct igb_adapter *adapter = netdev_priv(netdev); 9845 struct e1000_hw *hw = &adapter->hw; 9846 u32 reg_val, reg_offset; 9847 9848 if (!adapter->vfs_allocated_count) 9849 return -EOPNOTSUPP; 9850 9851 if (vf >= adapter->vfs_allocated_count) 9852 return -EINVAL; 9853 9854 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9855 reg_val = rd32(reg_offset); 9856 if (setting) 9857 reg_val |= (BIT(vf) | 9858 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9859 else 9860 reg_val &= ~(BIT(vf) | 9861 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9862 wr32(reg_offset, reg_val); 9863 9864 adapter->vf_data[vf].spoofchk_enabled = setting; 9865 return 0; 9866 } 9867 9868 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9869 { 9870 struct igb_adapter *adapter = netdev_priv(netdev); 9871 9872 if (vf >= adapter->vfs_allocated_count) 9873 return -EINVAL; 9874 if (adapter->vf_data[vf].trusted == setting) 9875 return 0; 9876 9877 adapter->vf_data[vf].trusted = setting; 9878 9879 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9880 vf, setting ? "" : "not "); 9881 return 0; 9882 } 9883 9884 static int igb_ndo_get_vf_config(struct net_device *netdev, 9885 int vf, struct ifla_vf_info *ivi) 9886 { 9887 struct igb_adapter *adapter = netdev_priv(netdev); 9888 if (vf >= adapter->vfs_allocated_count) 9889 return -EINVAL; 9890 ivi->vf = vf; 9891 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9892 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9893 ivi->min_tx_rate = 0; 9894 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9895 ivi->qos = adapter->vf_data[vf].pf_qos; 9896 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9897 ivi->trusted = adapter->vf_data[vf].trusted; 9898 return 0; 9899 } 9900 9901 static void igb_vmm_control(struct igb_adapter *adapter) 9902 { 9903 struct e1000_hw *hw = &adapter->hw; 9904 u32 reg; 9905 9906 switch (hw->mac.type) { 9907 case e1000_82575: 9908 case e1000_i210: 9909 case e1000_i211: 9910 case e1000_i354: 9911 default: 9912 /* replication is not supported for 82575 */ 9913 return; 9914 case e1000_82576: 9915 /* notify HW that the MAC is adding vlan tags */ 9916 reg = rd32(E1000_DTXCTL); 9917 reg |= E1000_DTXCTL_VLAN_ADDED; 9918 wr32(E1000_DTXCTL, reg); 9919 fallthrough; 9920 case e1000_82580: 9921 /* enable replication vlan tag stripping */ 9922 reg = rd32(E1000_RPLOLR); 9923 reg |= E1000_RPLOLR_STRVLAN; 9924 wr32(E1000_RPLOLR, reg); 9925 fallthrough; 9926 case e1000_i350: 9927 /* none of the above registers are supported by i350 */ 9928 break; 9929 } 9930 9931 if (adapter->vfs_allocated_count) { 9932 igb_vmdq_set_loopback_pf(hw, true); 9933 igb_vmdq_set_replication_pf(hw, true); 9934 igb_vmdq_set_anti_spoofing_pf(hw, true, 9935 adapter->vfs_allocated_count); 9936 } else { 9937 igb_vmdq_set_loopback_pf(hw, false); 9938 igb_vmdq_set_replication_pf(hw, false); 9939 } 9940 } 9941 9942 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9943 { 9944 struct e1000_hw *hw = &adapter->hw; 9945 u32 dmac_thr; 9946 u16 hwm; 9947 u32 reg; 9948 9949 if (hw->mac.type > e1000_82580) { 9950 if (adapter->flags & IGB_FLAG_DMAC) { 9951 /* force threshold to 0. */ 9952 wr32(E1000_DMCTXTH, 0); 9953 9954 /* DMA Coalescing high water mark needs to be greater 9955 * than the Rx threshold. Set hwm to PBA - max frame 9956 * size in 16B units, capping it at PBA - 6KB. 9957 */ 9958 hwm = 64 * (pba - 6); 9959 reg = rd32(E1000_FCRTC); 9960 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9961 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9962 & E1000_FCRTC_RTH_COAL_MASK); 9963 wr32(E1000_FCRTC, reg); 9964 9965 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9966 * frame size, capping it at PBA - 10KB. 9967 */ 9968 dmac_thr = pba - 10; 9969 reg = rd32(E1000_DMACR); 9970 reg &= ~E1000_DMACR_DMACTHR_MASK; 9971 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9972 & E1000_DMACR_DMACTHR_MASK); 9973 9974 /* transition to L0x or L1 if available..*/ 9975 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9976 9977 /* watchdog timer= +-1000 usec in 32usec intervals */ 9978 reg |= (1000 >> 5); 9979 9980 /* Disable BMC-to-OS Watchdog Enable */ 9981 if (hw->mac.type != e1000_i354) 9982 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9983 wr32(E1000_DMACR, reg); 9984 9985 /* no lower threshold to disable 9986 * coalescing(smart fifb)-UTRESH=0 9987 */ 9988 wr32(E1000_DMCRTRH, 0); 9989 9990 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9991 9992 wr32(E1000_DMCTLX, reg); 9993 9994 /* free space in tx packet buffer to wake from 9995 * DMA coal 9996 */ 9997 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9998 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9999 } 10000 10001 if (hw->mac.type >= e1000_i210 || 10002 (adapter->flags & IGB_FLAG_DMAC)) { 10003 reg = rd32(E1000_PCIEMISC); 10004 reg |= E1000_PCIEMISC_LX_DECISION; 10005 wr32(E1000_PCIEMISC, reg); 10006 } /* endif adapter->dmac is not disabled */ 10007 } else if (hw->mac.type == e1000_82580) { 10008 u32 reg = rd32(E1000_PCIEMISC); 10009 10010 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10011 wr32(E1000_DMACR, 0); 10012 } 10013 } 10014 10015 /** 10016 * igb_read_i2c_byte - Reads 8 bit word over I2C 10017 * @hw: pointer to hardware structure 10018 * @byte_offset: byte offset to read 10019 * @dev_addr: device address 10020 * @data: value read 10021 * 10022 * Performs byte read operation over I2C interface at 10023 * a specified device address. 10024 **/ 10025 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10026 u8 dev_addr, u8 *data) 10027 { 10028 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10029 struct i2c_client *this_client = adapter->i2c_client; 10030 s32 status; 10031 u16 swfw_mask = 0; 10032 10033 if (!this_client) 10034 return E1000_ERR_I2C; 10035 10036 swfw_mask = E1000_SWFW_PHY0_SM; 10037 10038 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10039 return E1000_ERR_SWFW_SYNC; 10040 10041 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10042 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10043 10044 if (status < 0) 10045 return E1000_ERR_I2C; 10046 else { 10047 *data = status; 10048 return 0; 10049 } 10050 } 10051 10052 /** 10053 * igb_write_i2c_byte - Writes 8 bit word over I2C 10054 * @hw: pointer to hardware structure 10055 * @byte_offset: byte offset to write 10056 * @dev_addr: device address 10057 * @data: value to write 10058 * 10059 * Performs byte write operation over I2C interface at 10060 * a specified device address. 10061 **/ 10062 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10063 u8 dev_addr, u8 data) 10064 { 10065 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10066 struct i2c_client *this_client = adapter->i2c_client; 10067 s32 status; 10068 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10069 10070 if (!this_client) 10071 return E1000_ERR_I2C; 10072 10073 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10074 return E1000_ERR_SWFW_SYNC; 10075 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10076 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10077 10078 if (status) 10079 return E1000_ERR_I2C; 10080 else 10081 return 0; 10082 10083 } 10084 10085 int igb_reinit_queues(struct igb_adapter *adapter) 10086 { 10087 struct net_device *netdev = adapter->netdev; 10088 struct pci_dev *pdev = adapter->pdev; 10089 int err = 0; 10090 10091 if (netif_running(netdev)) 10092 igb_close(netdev); 10093 10094 igb_reset_interrupt_capability(adapter); 10095 10096 if (igb_init_interrupt_scheme(adapter, true)) { 10097 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10098 return -ENOMEM; 10099 } 10100 10101 if (netif_running(netdev)) 10102 err = igb_open(netdev); 10103 10104 return err; 10105 } 10106 10107 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10108 { 10109 struct igb_nfc_filter *rule; 10110 10111 spin_lock(&adapter->nfc_lock); 10112 10113 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10114 igb_erase_filter(adapter, rule); 10115 10116 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10117 igb_erase_filter(adapter, rule); 10118 10119 spin_unlock(&adapter->nfc_lock); 10120 } 10121 10122 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10123 { 10124 struct igb_nfc_filter *rule; 10125 10126 spin_lock(&adapter->nfc_lock); 10127 10128 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10129 igb_add_filter(adapter, rule); 10130 10131 spin_unlock(&adapter->nfc_lock); 10132 } 10133 /* igb_main.c */ 10134