1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/pci-aspm.h> 26 #include <linux/delay.h> 27 #include <linux/interrupt.h> 28 #include <linux/ip.h> 29 #include <linux/tcp.h> 30 #include <linux/sctp.h> 31 #include <linux/if_ether.h> 32 #include <linux/aer.h> 33 #include <linux/prefetch.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 #define MAJ 5 43 #define MIN 4 44 #define BUILD 0 45 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 46 __stringify(BUILD) "-k" 47 48 enum queue_mode { 49 QUEUE_MODE_STRICT_PRIORITY, 50 QUEUE_MODE_STREAM_RESERVATION, 51 }; 52 53 enum tx_queue_prio { 54 TX_QUEUE_PRIO_HIGH, 55 TX_QUEUE_PRIO_LOW, 56 }; 57 58 char igb_driver_name[] = "igb"; 59 char igb_driver_version[] = DRV_VERSION; 60 static const char igb_driver_string[] = 61 "Intel(R) Gigabit Ethernet Network Driver"; 62 static const char igb_copyright[] = 63 "Copyright (c) 2007-2014 Intel Corporation."; 64 65 static const struct e1000_info *igb_info_tbl[] = { 66 [board_82575] = &e1000_82575_info, 67 }; 68 69 static const struct pci_device_id igb_pci_tbl[] = { 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 105 /* required last entry */ 106 {0, } 107 }; 108 109 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 110 111 static int igb_setup_all_tx_resources(struct igb_adapter *); 112 static int igb_setup_all_rx_resources(struct igb_adapter *); 113 static void igb_free_all_tx_resources(struct igb_adapter *); 114 static void igb_free_all_rx_resources(struct igb_adapter *); 115 static void igb_setup_mrqc(struct igb_adapter *); 116 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 117 static void igb_remove(struct pci_dev *pdev); 118 static int igb_sw_init(struct igb_adapter *); 119 int igb_open(struct net_device *); 120 int igb_close(struct net_device *); 121 static void igb_configure(struct igb_adapter *); 122 static void igb_configure_tx(struct igb_adapter *); 123 static void igb_configure_rx(struct igb_adapter *); 124 static void igb_clean_all_tx_rings(struct igb_adapter *); 125 static void igb_clean_all_rx_rings(struct igb_adapter *); 126 static void igb_clean_tx_ring(struct igb_ring *); 127 static void igb_clean_rx_ring(struct igb_ring *); 128 static void igb_set_rx_mode(struct net_device *); 129 static void igb_update_phy_info(struct timer_list *); 130 static void igb_watchdog(struct timer_list *); 131 static void igb_watchdog_task(struct work_struct *); 132 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 133 static void igb_get_stats64(struct net_device *dev, 134 struct rtnl_link_stats64 *stats); 135 static int igb_change_mtu(struct net_device *, int); 136 static int igb_set_mac(struct net_device *, void *); 137 static void igb_set_uta(struct igb_adapter *adapter, bool set); 138 static irqreturn_t igb_intr(int irq, void *); 139 static irqreturn_t igb_intr_msi(int irq, void *); 140 static irqreturn_t igb_msix_other(int irq, void *); 141 static irqreturn_t igb_msix_ring(int irq, void *); 142 #ifdef CONFIG_IGB_DCA 143 static void igb_update_dca(struct igb_q_vector *); 144 static void igb_setup_dca(struct igb_adapter *); 145 #endif /* CONFIG_IGB_DCA */ 146 static int igb_poll(struct napi_struct *, int); 147 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 148 static int igb_clean_rx_irq(struct igb_q_vector *, int); 149 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 150 static void igb_tx_timeout(struct net_device *); 151 static void igb_reset_task(struct work_struct *); 152 static void igb_vlan_mode(struct net_device *netdev, 153 netdev_features_t features); 154 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 155 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 156 static void igb_restore_vlan(struct igb_adapter *); 157 static void igb_rar_set_index(struct igb_adapter *, u32); 158 static void igb_ping_all_vfs(struct igb_adapter *); 159 static void igb_msg_task(struct igb_adapter *); 160 static void igb_vmm_control(struct igb_adapter *); 161 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 162 static void igb_flush_mac_table(struct igb_adapter *); 163 static int igb_available_rars(struct igb_adapter *, u8); 164 static void igb_set_default_mac_filter(struct igb_adapter *); 165 static int igb_uc_sync(struct net_device *, const unsigned char *); 166 static int igb_uc_unsync(struct net_device *, const unsigned char *); 167 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 168 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 169 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 170 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 171 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 172 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 173 bool setting); 174 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 180 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 181 182 #ifdef CONFIG_PCI_IOV 183 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185 static int igb_disable_sriov(struct pci_dev *dev); 186 static int igb_pci_disable_sriov(struct pci_dev *dev); 187 #endif 188 189 static int igb_suspend(struct device *); 190 static int igb_resume(struct device *); 191 static int igb_runtime_suspend(struct device *dev); 192 static int igb_runtime_resume(struct device *dev); 193 static int igb_runtime_idle(struct device *dev); 194 static const struct dev_pm_ops igb_pm_ops = { 195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 197 igb_runtime_idle) 198 }; 199 static void igb_shutdown(struct pci_dev *); 200 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 201 #ifdef CONFIG_IGB_DCA 202 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 203 static struct notifier_block dca_notifier = { 204 .notifier_call = igb_notify_dca, 205 .next = NULL, 206 .priority = 0 207 }; 208 #endif 209 #ifdef CONFIG_NET_POLL_CONTROLLER 210 /* for netdump / net console */ 211 static void igb_netpoll(struct net_device *); 212 #endif 213 #ifdef CONFIG_PCI_IOV 214 static unsigned int max_vfs; 215 module_param(max_vfs, uint, 0); 216 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 217 #endif /* CONFIG_PCI_IOV */ 218 219 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 220 pci_channel_state_t); 221 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 222 static void igb_io_resume(struct pci_dev *); 223 224 static const struct pci_error_handlers igb_err_handler = { 225 .error_detected = igb_io_error_detected, 226 .slot_reset = igb_io_slot_reset, 227 .resume = igb_io_resume, 228 }; 229 230 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 231 232 static struct pci_driver igb_driver = { 233 .name = igb_driver_name, 234 .id_table = igb_pci_tbl, 235 .probe = igb_probe, 236 .remove = igb_remove, 237 #ifdef CONFIG_PM 238 .driver.pm = &igb_pm_ops, 239 #endif 240 .shutdown = igb_shutdown, 241 .sriov_configure = igb_pci_sriov_configure, 242 .err_handler = &igb_err_handler 243 }; 244 245 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 246 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 247 MODULE_LICENSE("GPL"); 248 MODULE_VERSION(DRV_VERSION); 249 250 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 251 static int debug = -1; 252 module_param(debug, int, 0); 253 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 254 255 struct igb_reg_info { 256 u32 ofs; 257 char *name; 258 }; 259 260 static const struct igb_reg_info igb_reg_info_tbl[] = { 261 262 /* General Registers */ 263 {E1000_CTRL, "CTRL"}, 264 {E1000_STATUS, "STATUS"}, 265 {E1000_CTRL_EXT, "CTRL_EXT"}, 266 267 /* Interrupt Registers */ 268 {E1000_ICR, "ICR"}, 269 270 /* RX Registers */ 271 {E1000_RCTL, "RCTL"}, 272 {E1000_RDLEN(0), "RDLEN"}, 273 {E1000_RDH(0), "RDH"}, 274 {E1000_RDT(0), "RDT"}, 275 {E1000_RXDCTL(0), "RXDCTL"}, 276 {E1000_RDBAL(0), "RDBAL"}, 277 {E1000_RDBAH(0), "RDBAH"}, 278 279 /* TX Registers */ 280 {E1000_TCTL, "TCTL"}, 281 {E1000_TDBAL(0), "TDBAL"}, 282 {E1000_TDBAH(0), "TDBAH"}, 283 {E1000_TDLEN(0), "TDLEN"}, 284 {E1000_TDH(0), "TDH"}, 285 {E1000_TDT(0), "TDT"}, 286 {E1000_TXDCTL(0), "TXDCTL"}, 287 {E1000_TDFH, "TDFH"}, 288 {E1000_TDFT, "TDFT"}, 289 {E1000_TDFHS, "TDFHS"}, 290 {E1000_TDFPC, "TDFPC"}, 291 292 /* List Terminator */ 293 {} 294 }; 295 296 /* igb_regdump - register printout routine */ 297 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 298 { 299 int n = 0; 300 char rname[16]; 301 u32 regs[8]; 302 303 switch (reginfo->ofs) { 304 case E1000_RDLEN(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDLEN(n)); 307 break; 308 case E1000_RDH(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDH(n)); 311 break; 312 case E1000_RDT(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDT(n)); 315 break; 316 case E1000_RXDCTL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RXDCTL(n)); 319 break; 320 case E1000_RDBAL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAL(n)); 323 break; 324 case E1000_RDBAH(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAH(n)); 327 break; 328 case E1000_TDBAL(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAL(n)); 331 break; 332 case E1000_TDBAH(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDBAH(n)); 335 break; 336 case E1000_TDLEN(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDLEN(n)); 339 break; 340 case E1000_TDH(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDH(n)); 343 break; 344 case E1000_TDT(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDT(n)); 347 break; 348 case E1000_TXDCTL(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TXDCTL(n)); 351 break; 352 default: 353 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 354 return; 355 } 356 357 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 358 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 359 regs[2], regs[3]); 360 } 361 362 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 363 static void igb_dump(struct igb_adapter *adapter) 364 { 365 struct net_device *netdev = adapter->netdev; 366 struct e1000_hw *hw = &adapter->hw; 367 struct igb_reg_info *reginfo; 368 struct igb_ring *tx_ring; 369 union e1000_adv_tx_desc *tx_desc; 370 struct my_u0 { u64 a; u64 b; } *u0; 371 struct igb_ring *rx_ring; 372 union e1000_adv_rx_desc *rx_desc; 373 u32 staterr; 374 u16 i, n; 375 376 if (!netif_msg_hw(adapter)) 377 return; 378 379 /* Print netdevice Info */ 380 if (netdev) { 381 dev_info(&adapter->pdev->dev, "Net device Info\n"); 382 pr_info("Device Name state trans_start\n"); 383 pr_info("%-15s %016lX %016lX\n", netdev->name, 384 netdev->state, dev_trans_start(netdev)); 385 } 386 387 /* Print Registers */ 388 dev_info(&adapter->pdev->dev, "Register Dump\n"); 389 pr_info(" Register Name Value\n"); 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 391 reginfo->name; reginfo++) { 392 igb_regdump(hw, reginfo); 393 } 394 395 /* Print TX Ring Summary */ 396 if (!netdev || !netif_running(netdev)) 397 goto exit; 398 399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 401 for (n = 0; n < adapter->num_tx_queues; n++) { 402 struct igb_tx_buffer *buffer_info; 403 tx_ring = adapter->tx_ring[n]; 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 406 n, tx_ring->next_to_use, tx_ring->next_to_clean, 407 (u64)dma_unmap_addr(buffer_info, dma), 408 dma_unmap_len(buffer_info, len), 409 buffer_info->next_to_watch, 410 (u64)buffer_info->time_stamp); 411 } 412 413 /* Print TX Rings */ 414 if (!netif_msg_tx_done(adapter)) 415 goto rx_ring_summary; 416 417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 418 419 /* Transmit Descriptor Formats 420 * 421 * Advanced Transmit Descriptor 422 * +--------------------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +--------------------------------------------------------------+ 425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 426 * +--------------------------------------------------------------+ 427 * 63 46 45 40 39 38 36 35 32 31 24 15 0 428 */ 429 430 for (n = 0; n < adapter->num_tx_queues; n++) { 431 tx_ring = adapter->tx_ring[n]; 432 pr_info("------------------------------------\n"); 433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 434 pr_info("------------------------------------\n"); 435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 436 437 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 438 const char *next_desc; 439 struct igb_tx_buffer *buffer_info; 440 tx_desc = IGB_TX_DESC(tx_ring, i); 441 buffer_info = &tx_ring->tx_buffer_info[i]; 442 u0 = (struct my_u0 *)tx_desc; 443 if (i == tx_ring->next_to_use && 444 i == tx_ring->next_to_clean) 445 next_desc = " NTC/U"; 446 else if (i == tx_ring->next_to_use) 447 next_desc = " NTU"; 448 else if (i == tx_ring->next_to_clean) 449 next_desc = " NTC"; 450 else 451 next_desc = ""; 452 453 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 454 i, le64_to_cpu(u0->a), 455 le64_to_cpu(u0->b), 456 (u64)dma_unmap_addr(buffer_info, dma), 457 dma_unmap_len(buffer_info, len), 458 buffer_info->next_to_watch, 459 (u64)buffer_info->time_stamp, 460 buffer_info->skb, next_desc); 461 462 if (netif_msg_pktdata(adapter) && buffer_info->skb) 463 print_hex_dump(KERN_INFO, "", 464 DUMP_PREFIX_ADDRESS, 465 16, 1, buffer_info->skb->data, 466 dma_unmap_len(buffer_info, len), 467 true); 468 } 469 } 470 471 /* Print RX Rings Summary */ 472 rx_ring_summary: 473 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 474 pr_info("Queue [NTU] [NTC]\n"); 475 for (n = 0; n < adapter->num_rx_queues; n++) { 476 rx_ring = adapter->rx_ring[n]; 477 pr_info(" %5d %5X %5X\n", 478 n, rx_ring->next_to_use, rx_ring->next_to_clean); 479 } 480 481 /* Print RX Rings */ 482 if (!netif_msg_rx_status(adapter)) 483 goto exit; 484 485 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 486 487 /* Advanced Receive Descriptor (Read) Format 488 * 63 1 0 489 * +-----------------------------------------------------+ 490 * 0 | Packet Buffer Address [63:1] |A0/NSE| 491 * +----------------------------------------------+------+ 492 * 8 | Header Buffer Address [63:1] | DD | 493 * +-----------------------------------------------------+ 494 * 495 * 496 * Advanced Receive Descriptor (Write-Back) Format 497 * 498 * 63 48 47 32 31 30 21 20 17 16 4 3 0 499 * +------------------------------------------------------+ 500 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 501 * | Checksum Ident | | | | Type | Type | 502 * +------------------------------------------------------+ 503 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 504 * +------------------------------------------------------+ 505 * 63 48 47 32 31 20 19 0 506 */ 507 508 for (n = 0; n < adapter->num_rx_queues; n++) { 509 rx_ring = adapter->rx_ring[n]; 510 pr_info("------------------------------------\n"); 511 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 512 pr_info("------------------------------------\n"); 513 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 514 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 515 516 for (i = 0; i < rx_ring->count; i++) { 517 const char *next_desc; 518 struct igb_rx_buffer *buffer_info; 519 buffer_info = &rx_ring->rx_buffer_info[i]; 520 rx_desc = IGB_RX_DESC(rx_ring, i); 521 u0 = (struct my_u0 *)rx_desc; 522 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 523 524 if (i == rx_ring->next_to_use) 525 next_desc = " NTU"; 526 else if (i == rx_ring->next_to_clean) 527 next_desc = " NTC"; 528 else 529 next_desc = ""; 530 531 if (staterr & E1000_RXD_STAT_DD) { 532 /* Descriptor Done */ 533 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 534 "RWB", i, 535 le64_to_cpu(u0->a), 536 le64_to_cpu(u0->b), 537 next_desc); 538 } else { 539 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 540 "R ", i, 541 le64_to_cpu(u0->a), 542 le64_to_cpu(u0->b), 543 (u64)buffer_info->dma, 544 next_desc); 545 546 if (netif_msg_pktdata(adapter) && 547 buffer_info->dma && buffer_info->page) { 548 print_hex_dump(KERN_INFO, "", 549 DUMP_PREFIX_ADDRESS, 550 16, 1, 551 page_address(buffer_info->page) + 552 buffer_info->page_offset, 553 igb_rx_bufsz(rx_ring), true); 554 } 555 } 556 } 557 } 558 559 exit: 560 return; 561 } 562 563 /** 564 * igb_get_i2c_data - Reads the I2C SDA data bit 565 * @hw: pointer to hardware structure 566 * @i2cctl: Current value of I2CCTL register 567 * 568 * Returns the I2C data bit value 569 **/ 570 static int igb_get_i2c_data(void *data) 571 { 572 struct igb_adapter *adapter = (struct igb_adapter *)data; 573 struct e1000_hw *hw = &adapter->hw; 574 s32 i2cctl = rd32(E1000_I2CPARAMS); 575 576 return !!(i2cctl & E1000_I2C_DATA_IN); 577 } 578 579 /** 580 * igb_set_i2c_data - Sets the I2C data bit 581 * @data: pointer to hardware structure 582 * @state: I2C data value (0 or 1) to set 583 * 584 * Sets the I2C data bit 585 **/ 586 static void igb_set_i2c_data(void *data, int state) 587 { 588 struct igb_adapter *adapter = (struct igb_adapter *)data; 589 struct e1000_hw *hw = &adapter->hw; 590 s32 i2cctl = rd32(E1000_I2CPARAMS); 591 592 if (state) 593 i2cctl |= E1000_I2C_DATA_OUT; 594 else 595 i2cctl &= ~E1000_I2C_DATA_OUT; 596 597 i2cctl &= ~E1000_I2C_DATA_OE_N; 598 i2cctl |= E1000_I2C_CLK_OE_N; 599 wr32(E1000_I2CPARAMS, i2cctl); 600 wrfl(); 601 602 } 603 604 /** 605 * igb_set_i2c_clk - Sets the I2C SCL clock 606 * @data: pointer to hardware structure 607 * @state: state to set clock 608 * 609 * Sets the I2C clock line to state 610 **/ 611 static void igb_set_i2c_clk(void *data, int state) 612 { 613 struct igb_adapter *adapter = (struct igb_adapter *)data; 614 struct e1000_hw *hw = &adapter->hw; 615 s32 i2cctl = rd32(E1000_I2CPARAMS); 616 617 if (state) { 618 i2cctl |= E1000_I2C_CLK_OUT; 619 i2cctl &= ~E1000_I2C_CLK_OE_N; 620 } else { 621 i2cctl &= ~E1000_I2C_CLK_OUT; 622 i2cctl &= ~E1000_I2C_CLK_OE_N; 623 } 624 wr32(E1000_I2CPARAMS, i2cctl); 625 wrfl(); 626 } 627 628 /** 629 * igb_get_i2c_clk - Gets the I2C SCL clock state 630 * @data: pointer to hardware structure 631 * 632 * Gets the I2C clock state 633 **/ 634 static int igb_get_i2c_clk(void *data) 635 { 636 struct igb_adapter *adapter = (struct igb_adapter *)data; 637 struct e1000_hw *hw = &adapter->hw; 638 s32 i2cctl = rd32(E1000_I2CPARAMS); 639 640 return !!(i2cctl & E1000_I2C_CLK_IN); 641 } 642 643 static const struct i2c_algo_bit_data igb_i2c_algo = { 644 .setsda = igb_set_i2c_data, 645 .setscl = igb_set_i2c_clk, 646 .getsda = igb_get_i2c_data, 647 .getscl = igb_get_i2c_clk, 648 .udelay = 5, 649 .timeout = 20, 650 }; 651 652 /** 653 * igb_get_hw_dev - return device 654 * @hw: pointer to hardware structure 655 * 656 * used by hardware layer to print debugging information 657 **/ 658 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 659 { 660 struct igb_adapter *adapter = hw->back; 661 return adapter->netdev; 662 } 663 664 /** 665 * igb_init_module - Driver Registration Routine 666 * 667 * igb_init_module is the first routine called when the driver is 668 * loaded. All it does is register with the PCI subsystem. 669 **/ 670 static int __init igb_init_module(void) 671 { 672 int ret; 673 674 pr_info("%s - version %s\n", 675 igb_driver_string, igb_driver_version); 676 pr_info("%s\n", igb_copyright); 677 678 #ifdef CONFIG_IGB_DCA 679 dca_register_notify(&dca_notifier); 680 #endif 681 ret = pci_register_driver(&igb_driver); 682 return ret; 683 } 684 685 module_init(igb_init_module); 686 687 /** 688 * igb_exit_module - Driver Exit Cleanup Routine 689 * 690 * igb_exit_module is called just before the driver is removed 691 * from memory. 692 **/ 693 static void __exit igb_exit_module(void) 694 { 695 #ifdef CONFIG_IGB_DCA 696 dca_unregister_notify(&dca_notifier); 697 #endif 698 pci_unregister_driver(&igb_driver); 699 } 700 701 module_exit(igb_exit_module); 702 703 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 704 /** 705 * igb_cache_ring_register - Descriptor ring to register mapping 706 * @adapter: board private structure to initialize 707 * 708 * Once we know the feature-set enabled for the device, we'll cache 709 * the register offset the descriptor ring is assigned to. 710 **/ 711 static void igb_cache_ring_register(struct igb_adapter *adapter) 712 { 713 int i = 0, j = 0; 714 u32 rbase_offset = adapter->vfs_allocated_count; 715 716 switch (adapter->hw.mac.type) { 717 case e1000_82576: 718 /* The queues are allocated for virtualization such that VF 0 719 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 720 * In order to avoid collision we start at the first free queue 721 * and continue consuming queues in the same sequence 722 */ 723 if (adapter->vfs_allocated_count) { 724 for (; i < adapter->rss_queues; i++) 725 adapter->rx_ring[i]->reg_idx = rbase_offset + 726 Q_IDX_82576(i); 727 } 728 /* Fall through */ 729 case e1000_82575: 730 case e1000_82580: 731 case e1000_i350: 732 case e1000_i354: 733 case e1000_i210: 734 case e1000_i211: 735 /* Fall through */ 736 default: 737 for (; i < adapter->num_rx_queues; i++) 738 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 739 for (; j < adapter->num_tx_queues; j++) 740 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 741 break; 742 } 743 } 744 745 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 746 { 747 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 748 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 749 u32 value = 0; 750 751 if (E1000_REMOVED(hw_addr)) 752 return ~value; 753 754 value = readl(&hw_addr[reg]); 755 756 /* reads should not return all F's */ 757 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 758 struct net_device *netdev = igb->netdev; 759 hw->hw_addr = NULL; 760 netdev_err(netdev, "PCIe link lost\n"); 761 } 762 763 return value; 764 } 765 766 /** 767 * igb_write_ivar - configure ivar for given MSI-X vector 768 * @hw: pointer to the HW structure 769 * @msix_vector: vector number we are allocating to a given ring 770 * @index: row index of IVAR register to write within IVAR table 771 * @offset: column offset of in IVAR, should be multiple of 8 772 * 773 * This function is intended to handle the writing of the IVAR register 774 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 775 * each containing an cause allocation for an Rx and Tx ring, and a 776 * variable number of rows depending on the number of queues supported. 777 **/ 778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 779 int index, int offset) 780 { 781 u32 ivar = array_rd32(E1000_IVAR0, index); 782 783 /* clear any bits that are currently set */ 784 ivar &= ~((u32)0xFF << offset); 785 786 /* write vector and valid bit */ 787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 788 789 array_wr32(E1000_IVAR0, index, ivar); 790 } 791 792 #define IGB_N0_QUEUE -1 793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 794 { 795 struct igb_adapter *adapter = q_vector->adapter; 796 struct e1000_hw *hw = &adapter->hw; 797 int rx_queue = IGB_N0_QUEUE; 798 int tx_queue = IGB_N0_QUEUE; 799 u32 msixbm = 0; 800 801 if (q_vector->rx.ring) 802 rx_queue = q_vector->rx.ring->reg_idx; 803 if (q_vector->tx.ring) 804 tx_queue = q_vector->tx.ring->reg_idx; 805 806 switch (hw->mac.type) { 807 case e1000_82575: 808 /* The 82575 assigns vectors using a bitmask, which matches the 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one 810 * or more queues to a vector, we write the appropriate bits 811 * into the MSIXBM register for that vector. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 815 if (tx_queue > IGB_N0_QUEUE) 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 818 msixbm |= E1000_EIMS_OTHER; 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 820 q_vector->eims_value = msixbm; 821 break; 822 case e1000_82576: 823 /* 82576 uses a table that essentially consists of 2 columns 824 * with 8 rows. The ordering is column-major so we use the 825 * lower 3 bits as the row index, and the 4th bit as the 826 * column offset. 827 */ 828 if (rx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 rx_queue & 0x7, 831 (rx_queue & 0x8) << 1); 832 if (tx_queue > IGB_N0_QUEUE) 833 igb_write_ivar(hw, msix_vector, 834 tx_queue & 0x7, 835 ((tx_queue & 0x8) << 1) + 8); 836 q_vector->eims_value = BIT(msix_vector); 837 break; 838 case e1000_82580: 839 case e1000_i350: 840 case e1000_i354: 841 case e1000_i210: 842 case e1000_i211: 843 /* On 82580 and newer adapters the scheme is similar to 82576 844 * however instead of ordering column-major we have things 845 * ordered row-major. So we traverse the table by using 846 * bit 0 as the column offset, and the remaining bits as the 847 * row index. 848 */ 849 if (rx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 rx_queue >> 1, 852 (rx_queue & 0x1) << 4); 853 if (tx_queue > IGB_N0_QUEUE) 854 igb_write_ivar(hw, msix_vector, 855 tx_queue >> 1, 856 ((tx_queue & 0x1) << 4) + 8); 857 q_vector->eims_value = BIT(msix_vector); 858 break; 859 default: 860 BUG(); 861 break; 862 } 863 864 /* add q_vector eims value to global eims_enable_mask */ 865 adapter->eims_enable_mask |= q_vector->eims_value; 866 867 /* configure q_vector to set itr on first interrupt */ 868 q_vector->set_itr = 1; 869 } 870 871 /** 872 * igb_configure_msix - Configure MSI-X hardware 873 * @adapter: board private structure to initialize 874 * 875 * igb_configure_msix sets up the hardware to properly 876 * generate MSI-X interrupts. 877 **/ 878 static void igb_configure_msix(struct igb_adapter *adapter) 879 { 880 u32 tmp; 881 int i, vector = 0; 882 struct e1000_hw *hw = &adapter->hw; 883 884 adapter->eims_enable_mask = 0; 885 886 /* set vector for other causes, i.e. link changes */ 887 switch (hw->mac.type) { 888 case e1000_82575: 889 tmp = rd32(E1000_CTRL_EXT); 890 /* enable MSI-X PBA support*/ 891 tmp |= E1000_CTRL_EXT_PBA_CLR; 892 893 /* Auto-Mask interrupts upon ICR read. */ 894 tmp |= E1000_CTRL_EXT_EIAME; 895 tmp |= E1000_CTRL_EXT_IRCA; 896 897 wr32(E1000_CTRL_EXT, tmp); 898 899 /* enable msix_other interrupt */ 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 901 adapter->eims_other = E1000_EIMS_OTHER; 902 903 break; 904 905 case e1000_82576: 906 case e1000_82580: 907 case e1000_i350: 908 case e1000_i354: 909 case e1000_i210: 910 case e1000_i211: 911 /* Turn on MSI-X capability first, or our settings 912 * won't stick. And it will take days to debug. 913 */ 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 915 E1000_GPIE_PBA | E1000_GPIE_EIAME | 916 E1000_GPIE_NSICR); 917 918 /* enable msix_other interrupt */ 919 adapter->eims_other = BIT(vector); 920 tmp = (vector++ | E1000_IVAR_VALID) << 8; 921 922 wr32(E1000_IVAR_MISC, tmp); 923 break; 924 default: 925 /* do nothing, since nothing else supports MSI-X */ 926 break; 927 } /* switch (hw->mac.type) */ 928 929 adapter->eims_enable_mask |= adapter->eims_other; 930 931 for (i = 0; i < adapter->num_q_vectors; i++) 932 igb_assign_vector(adapter->q_vector[i], vector++); 933 934 wrfl(); 935 } 936 937 /** 938 * igb_request_msix - Initialize MSI-X interrupts 939 * @adapter: board private structure to initialize 940 * 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 942 * kernel. 943 **/ 944 static int igb_request_msix(struct igb_adapter *adapter) 945 { 946 struct net_device *netdev = adapter->netdev; 947 int i, err = 0, vector = 0, free_vector = 0; 948 949 err = request_irq(adapter->msix_entries[vector].vector, 950 igb_msix_other, 0, netdev->name, adapter); 951 if (err) 952 goto err_out; 953 954 for (i = 0; i < adapter->num_q_vectors; i++) { 955 struct igb_q_vector *q_vector = adapter->q_vector[i]; 956 957 vector++; 958 959 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 960 961 if (q_vector->rx.ring && q_vector->tx.ring) 962 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 963 q_vector->rx.ring->queue_index); 964 else if (q_vector->tx.ring) 965 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 966 q_vector->tx.ring->queue_index); 967 else if (q_vector->rx.ring) 968 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 969 q_vector->rx.ring->queue_index); 970 else 971 sprintf(q_vector->name, "%s-unused", netdev->name); 972 973 err = request_irq(adapter->msix_entries[vector].vector, 974 igb_msix_ring, 0, q_vector->name, 975 q_vector); 976 if (err) 977 goto err_free; 978 } 979 980 igb_configure_msix(adapter); 981 return 0; 982 983 err_free: 984 /* free already assigned IRQs */ 985 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 986 987 vector--; 988 for (i = 0; i < vector; i++) { 989 free_irq(adapter->msix_entries[free_vector++].vector, 990 adapter->q_vector[i]); 991 } 992 err_out: 993 return err; 994 } 995 996 /** 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector 998 * @adapter: board private structure to initialize 999 * @v_idx: Index of vector to be freed 1000 * 1001 * This function frees the memory allocated to the q_vector. 1002 **/ 1003 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1004 { 1005 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1006 1007 adapter->q_vector[v_idx] = NULL; 1008 1009 /* igb_get_stats64() might access the rings on this vector, 1010 * we must wait a grace period before freeing it. 1011 */ 1012 if (q_vector) 1013 kfree_rcu(q_vector, rcu); 1014 } 1015 1016 /** 1017 * igb_reset_q_vector - Reset config for interrupt vector 1018 * @adapter: board private structure to initialize 1019 * @v_idx: Index of vector to be reset 1020 * 1021 * If NAPI is enabled it will delete any references to the 1022 * NAPI struct. This is preparation for igb_free_q_vector. 1023 **/ 1024 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1025 { 1026 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1027 1028 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1029 * allocated. So, q_vector is NULL so we should stop here. 1030 */ 1031 if (!q_vector) 1032 return; 1033 1034 if (q_vector->tx.ring) 1035 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1036 1037 if (q_vector->rx.ring) 1038 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1039 1040 netif_napi_del(&q_vector->napi); 1041 1042 } 1043 1044 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1045 { 1046 int v_idx = adapter->num_q_vectors; 1047 1048 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1049 pci_disable_msix(adapter->pdev); 1050 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1051 pci_disable_msi(adapter->pdev); 1052 1053 while (v_idx--) 1054 igb_reset_q_vector(adapter, v_idx); 1055 } 1056 1057 /** 1058 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1059 * @adapter: board private structure to initialize 1060 * 1061 * This function frees the memory allocated to the q_vectors. In addition if 1062 * NAPI is enabled it will delete any references to the NAPI struct prior 1063 * to freeing the q_vector. 1064 **/ 1065 static void igb_free_q_vectors(struct igb_adapter *adapter) 1066 { 1067 int v_idx = adapter->num_q_vectors; 1068 1069 adapter->num_tx_queues = 0; 1070 adapter->num_rx_queues = 0; 1071 adapter->num_q_vectors = 0; 1072 1073 while (v_idx--) { 1074 igb_reset_q_vector(adapter, v_idx); 1075 igb_free_q_vector(adapter, v_idx); 1076 } 1077 } 1078 1079 /** 1080 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1081 * @adapter: board private structure to initialize 1082 * 1083 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1084 * MSI-X interrupts allocated. 1085 */ 1086 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1087 { 1088 igb_free_q_vectors(adapter); 1089 igb_reset_interrupt_capability(adapter); 1090 } 1091 1092 /** 1093 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1094 * @adapter: board private structure to initialize 1095 * @msix: boolean value of MSIX capability 1096 * 1097 * Attempt to configure interrupts using the best available 1098 * capabilities of the hardware and kernel. 1099 **/ 1100 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1101 { 1102 int err; 1103 int numvecs, i; 1104 1105 if (!msix) 1106 goto msi_only; 1107 adapter->flags |= IGB_FLAG_HAS_MSIX; 1108 1109 /* Number of supported queues. */ 1110 adapter->num_rx_queues = adapter->rss_queues; 1111 if (adapter->vfs_allocated_count) 1112 adapter->num_tx_queues = 1; 1113 else 1114 adapter->num_tx_queues = adapter->rss_queues; 1115 1116 /* start with one vector for every Rx queue */ 1117 numvecs = adapter->num_rx_queues; 1118 1119 /* if Tx handler is separate add 1 for every Tx queue */ 1120 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1121 numvecs += adapter->num_tx_queues; 1122 1123 /* store the number of vectors reserved for queues */ 1124 adapter->num_q_vectors = numvecs; 1125 1126 /* add 1 vector for link status interrupts */ 1127 numvecs++; 1128 for (i = 0; i < numvecs; i++) 1129 adapter->msix_entries[i].entry = i; 1130 1131 err = pci_enable_msix_range(adapter->pdev, 1132 adapter->msix_entries, 1133 numvecs, 1134 numvecs); 1135 if (err > 0) 1136 return; 1137 1138 igb_reset_interrupt_capability(adapter); 1139 1140 /* If we can't do MSI-X, try MSI */ 1141 msi_only: 1142 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1143 #ifdef CONFIG_PCI_IOV 1144 /* disable SR-IOV for non MSI-X configurations */ 1145 if (adapter->vf_data) { 1146 struct e1000_hw *hw = &adapter->hw; 1147 /* disable iov and allow time for transactions to clear */ 1148 pci_disable_sriov(adapter->pdev); 1149 msleep(500); 1150 1151 kfree(adapter->vf_mac_list); 1152 adapter->vf_mac_list = NULL; 1153 kfree(adapter->vf_data); 1154 adapter->vf_data = NULL; 1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1156 wrfl(); 1157 msleep(100); 1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1159 } 1160 #endif 1161 adapter->vfs_allocated_count = 0; 1162 adapter->rss_queues = 1; 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1164 adapter->num_rx_queues = 1; 1165 adapter->num_tx_queues = 1; 1166 adapter->num_q_vectors = 1; 1167 if (!pci_enable_msi(adapter->pdev)) 1168 adapter->flags |= IGB_FLAG_HAS_MSI; 1169 } 1170 1171 static void igb_add_ring(struct igb_ring *ring, 1172 struct igb_ring_container *head) 1173 { 1174 head->ring = ring; 1175 head->count++; 1176 } 1177 1178 /** 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1180 * @adapter: board private structure to initialize 1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1182 * @v_idx: index of vector in adapter struct 1183 * @txr_count: total number of Tx rings to allocate 1184 * @txr_idx: index of first Tx ring to allocate 1185 * @rxr_count: total number of Rx rings to allocate 1186 * @rxr_idx: index of first Rx ring to allocate 1187 * 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1189 **/ 1190 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1191 int v_count, int v_idx, 1192 int txr_count, int txr_idx, 1193 int rxr_count, int rxr_idx) 1194 { 1195 struct igb_q_vector *q_vector; 1196 struct igb_ring *ring; 1197 int ring_count, size; 1198 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1200 if (txr_count > 1 || rxr_count > 1) 1201 return -ENOMEM; 1202 1203 ring_count = txr_count + rxr_count; 1204 size = sizeof(struct igb_q_vector) + 1205 (sizeof(struct igb_ring) * ring_count); 1206 1207 /* allocate q_vector and rings */ 1208 q_vector = adapter->q_vector[v_idx]; 1209 if (!q_vector) { 1210 q_vector = kzalloc(size, GFP_KERNEL); 1211 } else if (size > ksize(q_vector)) { 1212 kfree_rcu(q_vector, rcu); 1213 q_vector = kzalloc(size, GFP_KERNEL); 1214 } else { 1215 memset(q_vector, 0, size); 1216 } 1217 if (!q_vector) 1218 return -ENOMEM; 1219 1220 /* initialize NAPI */ 1221 netif_napi_add(adapter->netdev, &q_vector->napi, 1222 igb_poll, 64); 1223 1224 /* tie q_vector and adapter together */ 1225 adapter->q_vector[v_idx] = q_vector; 1226 q_vector->adapter = adapter; 1227 1228 /* initialize work limits */ 1229 q_vector->tx.work_limit = adapter->tx_work_limit; 1230 1231 /* initialize ITR configuration */ 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1233 q_vector->itr_val = IGB_START_ITR; 1234 1235 /* initialize pointer to rings */ 1236 ring = q_vector->ring; 1237 1238 /* intialize ITR */ 1239 if (rxr_count) { 1240 /* rx or rx/tx vector */ 1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1242 q_vector->itr_val = adapter->rx_itr_setting; 1243 } else { 1244 /* tx only vector */ 1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1246 q_vector->itr_val = adapter->tx_itr_setting; 1247 } 1248 1249 if (txr_count) { 1250 /* assign generic ring traits */ 1251 ring->dev = &adapter->pdev->dev; 1252 ring->netdev = adapter->netdev; 1253 1254 /* configure backlink on ring */ 1255 ring->q_vector = q_vector; 1256 1257 /* update q_vector Tx values */ 1258 igb_add_ring(ring, &q_vector->tx); 1259 1260 /* For 82575, context index must be unique per ring. */ 1261 if (adapter->hw.mac.type == e1000_82575) 1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1263 1264 /* apply Tx specific ring traits */ 1265 ring->count = adapter->tx_ring_count; 1266 ring->queue_index = txr_idx; 1267 1268 ring->cbs_enable = false; 1269 ring->idleslope = 0; 1270 ring->sendslope = 0; 1271 ring->hicredit = 0; 1272 ring->locredit = 0; 1273 1274 u64_stats_init(&ring->tx_syncp); 1275 u64_stats_init(&ring->tx_syncp2); 1276 1277 /* assign ring to adapter */ 1278 adapter->tx_ring[txr_idx] = ring; 1279 1280 /* push pointer to next ring */ 1281 ring++; 1282 } 1283 1284 if (rxr_count) { 1285 /* assign generic ring traits */ 1286 ring->dev = &adapter->pdev->dev; 1287 ring->netdev = adapter->netdev; 1288 1289 /* configure backlink on ring */ 1290 ring->q_vector = q_vector; 1291 1292 /* update q_vector Rx values */ 1293 igb_add_ring(ring, &q_vector->rx); 1294 1295 /* set flag indicating ring supports SCTP checksum offload */ 1296 if (adapter->hw.mac.type >= e1000_82576) 1297 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1298 1299 /* On i350, i354, i210, and i211, loopback VLAN packets 1300 * have the tag byte-swapped. 1301 */ 1302 if (adapter->hw.mac.type >= e1000_i350) 1303 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1304 1305 /* apply Rx specific ring traits */ 1306 ring->count = adapter->rx_ring_count; 1307 ring->queue_index = rxr_idx; 1308 1309 u64_stats_init(&ring->rx_syncp); 1310 1311 /* assign ring to adapter */ 1312 adapter->rx_ring[rxr_idx] = ring; 1313 } 1314 1315 return 0; 1316 } 1317 1318 1319 /** 1320 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1321 * @adapter: board private structure to initialize 1322 * 1323 * We allocate one q_vector per queue interrupt. If allocation fails we 1324 * return -ENOMEM. 1325 **/ 1326 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1327 { 1328 int q_vectors = adapter->num_q_vectors; 1329 int rxr_remaining = adapter->num_rx_queues; 1330 int txr_remaining = adapter->num_tx_queues; 1331 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1332 int err; 1333 1334 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1335 for (; rxr_remaining; v_idx++) { 1336 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1337 0, 0, 1, rxr_idx); 1338 1339 if (err) 1340 goto err_out; 1341 1342 /* update counts and index */ 1343 rxr_remaining--; 1344 rxr_idx++; 1345 } 1346 } 1347 1348 for (; v_idx < q_vectors; v_idx++) { 1349 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1350 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1351 1352 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1353 tqpv, txr_idx, rqpv, rxr_idx); 1354 1355 if (err) 1356 goto err_out; 1357 1358 /* update counts and index */ 1359 rxr_remaining -= rqpv; 1360 txr_remaining -= tqpv; 1361 rxr_idx++; 1362 txr_idx++; 1363 } 1364 1365 return 0; 1366 1367 err_out: 1368 adapter->num_tx_queues = 0; 1369 adapter->num_rx_queues = 0; 1370 adapter->num_q_vectors = 0; 1371 1372 while (v_idx--) 1373 igb_free_q_vector(adapter, v_idx); 1374 1375 return -ENOMEM; 1376 } 1377 1378 /** 1379 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1380 * @adapter: board private structure to initialize 1381 * @msix: boolean value of MSIX capability 1382 * 1383 * This function initializes the interrupts and allocates all of the queues. 1384 **/ 1385 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1386 { 1387 struct pci_dev *pdev = adapter->pdev; 1388 int err; 1389 1390 igb_set_interrupt_capability(adapter, msix); 1391 1392 err = igb_alloc_q_vectors(adapter); 1393 if (err) { 1394 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1395 goto err_alloc_q_vectors; 1396 } 1397 1398 igb_cache_ring_register(adapter); 1399 1400 return 0; 1401 1402 err_alloc_q_vectors: 1403 igb_reset_interrupt_capability(adapter); 1404 return err; 1405 } 1406 1407 /** 1408 * igb_request_irq - initialize interrupts 1409 * @adapter: board private structure to initialize 1410 * 1411 * Attempts to configure interrupts using the best available 1412 * capabilities of the hardware and kernel. 1413 **/ 1414 static int igb_request_irq(struct igb_adapter *adapter) 1415 { 1416 struct net_device *netdev = adapter->netdev; 1417 struct pci_dev *pdev = adapter->pdev; 1418 int err = 0; 1419 1420 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1421 err = igb_request_msix(adapter); 1422 if (!err) 1423 goto request_done; 1424 /* fall back to MSI */ 1425 igb_free_all_tx_resources(adapter); 1426 igb_free_all_rx_resources(adapter); 1427 1428 igb_clear_interrupt_scheme(adapter); 1429 err = igb_init_interrupt_scheme(adapter, false); 1430 if (err) 1431 goto request_done; 1432 1433 igb_setup_all_tx_resources(adapter); 1434 igb_setup_all_rx_resources(adapter); 1435 igb_configure(adapter); 1436 } 1437 1438 igb_assign_vector(adapter->q_vector[0], 0); 1439 1440 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1441 err = request_irq(pdev->irq, igb_intr_msi, 0, 1442 netdev->name, adapter); 1443 if (!err) 1444 goto request_done; 1445 1446 /* fall back to legacy interrupts */ 1447 igb_reset_interrupt_capability(adapter); 1448 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1449 } 1450 1451 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1452 netdev->name, adapter); 1453 1454 if (err) 1455 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1456 err); 1457 1458 request_done: 1459 return err; 1460 } 1461 1462 static void igb_free_irq(struct igb_adapter *adapter) 1463 { 1464 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1465 int vector = 0, i; 1466 1467 free_irq(adapter->msix_entries[vector++].vector, adapter); 1468 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 free_irq(adapter->msix_entries[vector++].vector, 1471 adapter->q_vector[i]); 1472 } else { 1473 free_irq(adapter->pdev->irq, adapter); 1474 } 1475 } 1476 1477 /** 1478 * igb_irq_disable - Mask off interrupt generation on the NIC 1479 * @adapter: board private structure 1480 **/ 1481 static void igb_irq_disable(struct igb_adapter *adapter) 1482 { 1483 struct e1000_hw *hw = &adapter->hw; 1484 1485 /* we need to be careful when disabling interrupts. The VFs are also 1486 * mapped into these registers and so clearing the bits can cause 1487 * issues on the VF drivers so we only need to clear what we set 1488 */ 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 u32 regval = rd32(E1000_EIAM); 1491 1492 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1493 wr32(E1000_EIMC, adapter->eims_enable_mask); 1494 regval = rd32(E1000_EIAC); 1495 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1496 } 1497 1498 wr32(E1000_IAM, 0); 1499 wr32(E1000_IMC, ~0); 1500 wrfl(); 1501 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1502 int i; 1503 1504 for (i = 0; i < adapter->num_q_vectors; i++) 1505 synchronize_irq(adapter->msix_entries[i].vector); 1506 } else { 1507 synchronize_irq(adapter->pdev->irq); 1508 } 1509 } 1510 1511 /** 1512 * igb_irq_enable - Enable default interrupt generation settings 1513 * @adapter: board private structure 1514 **/ 1515 static void igb_irq_enable(struct igb_adapter *adapter) 1516 { 1517 struct e1000_hw *hw = &adapter->hw; 1518 1519 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1520 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1521 u32 regval = rd32(E1000_EIAC); 1522 1523 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1524 regval = rd32(E1000_EIAM); 1525 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1526 wr32(E1000_EIMS, adapter->eims_enable_mask); 1527 if (adapter->vfs_allocated_count) { 1528 wr32(E1000_MBVFIMR, 0xFF); 1529 ims |= E1000_IMS_VMMB; 1530 } 1531 wr32(E1000_IMS, ims); 1532 } else { 1533 wr32(E1000_IMS, IMS_ENABLE_MASK | 1534 E1000_IMS_DRSTA); 1535 wr32(E1000_IAM, IMS_ENABLE_MASK | 1536 E1000_IMS_DRSTA); 1537 } 1538 } 1539 1540 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u16 pf_id = adapter->vfs_allocated_count; 1544 u16 vid = adapter->hw.mng_cookie.vlan_id; 1545 u16 old_vid = adapter->mng_vlan_id; 1546 1547 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1548 /* add VID to filter table */ 1549 igb_vfta_set(hw, vid, pf_id, true, true); 1550 adapter->mng_vlan_id = vid; 1551 } else { 1552 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1553 } 1554 1555 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1556 (vid != old_vid) && 1557 !test_bit(old_vid, adapter->active_vlans)) { 1558 /* remove VID from filter table */ 1559 igb_vfta_set(hw, vid, pf_id, false, true); 1560 } 1561 } 1562 1563 /** 1564 * igb_release_hw_control - release control of the h/w to f/w 1565 * @adapter: address of board private structure 1566 * 1567 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1568 * For ASF and Pass Through versions of f/w this means that the 1569 * driver is no longer loaded. 1570 **/ 1571 static void igb_release_hw_control(struct igb_adapter *adapter) 1572 { 1573 struct e1000_hw *hw = &adapter->hw; 1574 u32 ctrl_ext; 1575 1576 /* Let firmware take over control of h/w */ 1577 ctrl_ext = rd32(E1000_CTRL_EXT); 1578 wr32(E1000_CTRL_EXT, 1579 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1580 } 1581 1582 /** 1583 * igb_get_hw_control - get control of the h/w from f/w 1584 * @adapter: address of board private structure 1585 * 1586 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1587 * For ASF and Pass Through versions of f/w this means that 1588 * the driver is loaded. 1589 **/ 1590 static void igb_get_hw_control(struct igb_adapter *adapter) 1591 { 1592 struct e1000_hw *hw = &adapter->hw; 1593 u32 ctrl_ext; 1594 1595 /* Let firmware know the driver has taken over */ 1596 ctrl_ext = rd32(E1000_CTRL_EXT); 1597 wr32(E1000_CTRL_EXT, 1598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1599 } 1600 1601 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1602 { 1603 struct net_device *netdev = adapter->netdev; 1604 struct e1000_hw *hw = &adapter->hw; 1605 1606 WARN_ON(hw->mac.type != e1000_i210); 1607 1608 if (enable) 1609 adapter->flags |= IGB_FLAG_FQTSS; 1610 else 1611 adapter->flags &= ~IGB_FLAG_FQTSS; 1612 1613 if (netif_running(netdev)) 1614 schedule_work(&adapter->reset_task); 1615 } 1616 1617 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1618 { 1619 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1620 } 1621 1622 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1623 enum tx_queue_prio prio) 1624 { 1625 u32 val; 1626 1627 WARN_ON(hw->mac.type != e1000_i210); 1628 WARN_ON(queue < 0 || queue > 4); 1629 1630 val = rd32(E1000_I210_TXDCTL(queue)); 1631 1632 if (prio == TX_QUEUE_PRIO_HIGH) 1633 val |= E1000_TXDCTL_PRIORITY; 1634 else 1635 val &= ~E1000_TXDCTL_PRIORITY; 1636 1637 wr32(E1000_I210_TXDCTL(queue), val); 1638 } 1639 1640 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1641 { 1642 u32 val; 1643 1644 WARN_ON(hw->mac.type != e1000_i210); 1645 WARN_ON(queue < 0 || queue > 1); 1646 1647 val = rd32(E1000_I210_TQAVCC(queue)); 1648 1649 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1650 val |= E1000_TQAVCC_QUEUEMODE; 1651 else 1652 val &= ~E1000_TQAVCC_QUEUEMODE; 1653 1654 wr32(E1000_I210_TQAVCC(queue), val); 1655 } 1656 1657 /** 1658 * igb_configure_cbs - Configure Credit-Based Shaper (CBS) 1659 * @adapter: pointer to adapter struct 1660 * @queue: queue number 1661 * @enable: true = enable CBS, false = disable CBS 1662 * @idleslope: idleSlope in kbps 1663 * @sendslope: sendSlope in kbps 1664 * @hicredit: hiCredit in bytes 1665 * @locredit: loCredit in bytes 1666 * 1667 * Configure CBS for a given hardware queue. When disabling, idleslope, 1668 * sendslope, hicredit, locredit arguments are ignored. Returns 0 if 1669 * success. Negative otherwise. 1670 **/ 1671 static void igb_configure_cbs(struct igb_adapter *adapter, int queue, 1672 bool enable, int idleslope, int sendslope, 1673 int hicredit, int locredit) 1674 { 1675 struct net_device *netdev = adapter->netdev; 1676 struct e1000_hw *hw = &adapter->hw; 1677 u32 tqavcc; 1678 u16 value; 1679 1680 WARN_ON(hw->mac.type != e1000_i210); 1681 WARN_ON(queue < 0 || queue > 1); 1682 1683 if (enable || queue == 0) { 1684 /* i210 does not allow the queue 0 to be in the Strict 1685 * Priority mode while the Qav mode is enabled, so, 1686 * instead of disabling strict priority mode, we give 1687 * queue 0 the maximum of credits possible. 1688 * 1689 * See section 8.12.19 of the i210 datasheet, "Note: 1690 * Queue0 QueueMode must be set to 1b when 1691 * TransmitMode is set to Qav." 1692 */ 1693 if (queue == 0 && !enable) { 1694 /* max "linkspeed" idleslope in kbps */ 1695 idleslope = 1000000; 1696 hicredit = ETH_FRAME_LEN; 1697 } 1698 1699 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1700 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1701 1702 /* According to i210 datasheet section 7.2.7.7, we should set 1703 * the 'idleSlope' field from TQAVCC register following the 1704 * equation: 1705 * 1706 * For 100 Mbps link speed: 1707 * 1708 * value = BW * 0x7735 * 0.2 (E1) 1709 * 1710 * For 1000Mbps link speed: 1711 * 1712 * value = BW * 0x7735 * 2 (E2) 1713 * 1714 * E1 and E2 can be merged into one equation as shown below. 1715 * Note that 'link-speed' is in Mbps. 1716 * 1717 * value = BW * 0x7735 * 2 * link-speed 1718 * -------------- (E3) 1719 * 1000 1720 * 1721 * 'BW' is the percentage bandwidth out of full link speed 1722 * which can be found with the following equation. Note that 1723 * idleSlope here is the parameter from this function which 1724 * is in kbps. 1725 * 1726 * BW = idleSlope 1727 * ----------------- (E4) 1728 * link-speed * 1000 1729 * 1730 * That said, we can come up with a generic equation to 1731 * calculate the value we should set it TQAVCC register by 1732 * replacing 'BW' in E3 by E4. The resulting equation is: 1733 * 1734 * value = idleSlope * 0x7735 * 2 * link-speed 1735 * ----------------- -------------- (E5) 1736 * link-speed * 1000 1000 1737 * 1738 * 'link-speed' is present in both sides of the fraction so 1739 * it is canceled out. The final equation is the following: 1740 * 1741 * value = idleSlope * 61034 1742 * ----------------- (E6) 1743 * 1000000 1744 * 1745 * NOTE: For i210, given the above, we can see that idleslope 1746 * is represented in 16.38431 kbps units by the value at 1747 * the TQAVCC register (1Gbps / 61034), which reduces 1748 * the granularity for idleslope increments. 1749 * For instance, if you want to configure a 2576kbps 1750 * idleslope, the value to be written on the register 1751 * would have to be 157.23. If rounded down, you end 1752 * up with less bandwidth available than originally 1753 * required (~2572 kbps). If rounded up, you end up 1754 * with a higher bandwidth (~2589 kbps). Below the 1755 * approach we take is to always round up the 1756 * calculated value, so the resulting bandwidth might 1757 * be slightly higher for some configurations. 1758 */ 1759 value = DIV_ROUND_UP_ULL(idleslope * 61034ULL, 1000000); 1760 1761 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1762 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1763 tqavcc |= value; 1764 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1765 1766 wr32(E1000_I210_TQAVHC(queue), 0x80000000 + hicredit * 0x7735); 1767 } else { 1768 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1769 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1770 1771 /* Set idleSlope to zero. */ 1772 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1773 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1774 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1775 1776 /* Set hiCredit to zero. */ 1777 wr32(E1000_I210_TQAVHC(queue), 0); 1778 } 1779 1780 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1781 * CBS are not configurable by software so we don't do any 'controller 1782 * configuration' in respect to these parameters. 1783 */ 1784 1785 netdev_dbg(netdev, "CBS %s: queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1786 (enable) ? "enabled" : "disabled", queue, 1787 idleslope, sendslope, hicredit, locredit); 1788 } 1789 1790 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1791 bool enable, int idleslope, int sendslope, 1792 int hicredit, int locredit) 1793 { 1794 struct igb_ring *ring; 1795 1796 if (queue < 0 || queue > adapter->num_tx_queues) 1797 return -EINVAL; 1798 1799 ring = adapter->tx_ring[queue]; 1800 1801 ring->cbs_enable = enable; 1802 ring->idleslope = idleslope; 1803 ring->sendslope = sendslope; 1804 ring->hicredit = hicredit; 1805 ring->locredit = locredit; 1806 1807 return 0; 1808 } 1809 1810 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1811 { 1812 struct igb_ring *ring; 1813 int i; 1814 1815 for (i = 0; i < adapter->num_tx_queues; i++) { 1816 ring = adapter->tx_ring[i]; 1817 1818 if (ring->cbs_enable) 1819 return true; 1820 } 1821 1822 return false; 1823 } 1824 1825 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1826 { 1827 struct net_device *netdev = adapter->netdev; 1828 struct e1000_hw *hw = &adapter->hw; 1829 u32 val; 1830 1831 /* Only i210 controller supports changing the transmission mode. */ 1832 if (hw->mac.type != e1000_i210) 1833 return; 1834 1835 if (is_fqtss_enabled(adapter)) { 1836 int i, max_queue; 1837 1838 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1839 * set data fetch arbitration to 'round robin' and set data 1840 * transfer arbitration to 'credit shaper algorithm. 1841 */ 1842 val = rd32(E1000_I210_TQAVCTRL); 1843 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_DATATRANARB; 1844 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1845 wr32(E1000_I210_TQAVCTRL, val); 1846 1847 /* Configure Tx and Rx packet buffers sizes as described in 1848 * i210 datasheet section 7.2.7.7. 1849 */ 1850 val = rd32(E1000_TXPBS); 1851 val &= ~I210_TXPBSIZE_MASK; 1852 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1853 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1854 wr32(E1000_TXPBS, val); 1855 1856 val = rd32(E1000_RXPBS); 1857 val &= ~I210_RXPBSIZE_MASK; 1858 val |= I210_RXPBSIZE_PB_32KB; 1859 wr32(E1000_RXPBS, val); 1860 1861 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1862 * register should not exceed the buffer size programmed in 1863 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1864 * so according to the datasheet we should set MAX_TPKT_SIZE to 1865 * 4kB / 64. 1866 * 1867 * However, when we do so, no frame from queue 2 and 3 are 1868 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1869 * or _equal_ to the buffer size programmed in TXPBS. For this 1870 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1871 */ 1872 val = (4096 - 1) / 64; 1873 wr32(E1000_I210_DTXMXPKTSZ, val); 1874 1875 /* Since FQTSS mode is enabled, apply any CBS configuration 1876 * previously set. If no previous CBS configuration has been 1877 * done, then the initial configuration is applied, which means 1878 * CBS is disabled. 1879 */ 1880 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1881 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1882 1883 for (i = 0; i < max_queue; i++) { 1884 struct igb_ring *ring = adapter->tx_ring[i]; 1885 1886 igb_configure_cbs(adapter, i, ring->cbs_enable, 1887 ring->idleslope, ring->sendslope, 1888 ring->hicredit, ring->locredit); 1889 } 1890 } else { 1891 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1892 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1893 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1894 1895 val = rd32(E1000_I210_TQAVCTRL); 1896 /* According to Section 8.12.21, the other flags we've set when 1897 * enabling FQTSS are not relevant when disabling FQTSS so we 1898 * don't set they here. 1899 */ 1900 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1901 wr32(E1000_I210_TQAVCTRL, val); 1902 } 1903 1904 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1905 "enabled" : "disabled"); 1906 } 1907 1908 /** 1909 * igb_configure - configure the hardware for RX and TX 1910 * @adapter: private board structure 1911 **/ 1912 static void igb_configure(struct igb_adapter *adapter) 1913 { 1914 struct net_device *netdev = adapter->netdev; 1915 int i; 1916 1917 igb_get_hw_control(adapter); 1918 igb_set_rx_mode(netdev); 1919 igb_setup_tx_mode(adapter); 1920 1921 igb_restore_vlan(adapter); 1922 1923 igb_setup_tctl(adapter); 1924 igb_setup_mrqc(adapter); 1925 igb_setup_rctl(adapter); 1926 1927 igb_nfc_filter_restore(adapter); 1928 igb_configure_tx(adapter); 1929 igb_configure_rx(adapter); 1930 1931 igb_rx_fifo_flush_82575(&adapter->hw); 1932 1933 /* call igb_desc_unused which always leaves 1934 * at least 1 descriptor unused to make sure 1935 * next_to_use != next_to_clean 1936 */ 1937 for (i = 0; i < adapter->num_rx_queues; i++) { 1938 struct igb_ring *ring = adapter->rx_ring[i]; 1939 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1940 } 1941 } 1942 1943 /** 1944 * igb_power_up_link - Power up the phy/serdes link 1945 * @adapter: address of board private structure 1946 **/ 1947 void igb_power_up_link(struct igb_adapter *adapter) 1948 { 1949 igb_reset_phy(&adapter->hw); 1950 1951 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1952 igb_power_up_phy_copper(&adapter->hw); 1953 else 1954 igb_power_up_serdes_link_82575(&adapter->hw); 1955 1956 igb_setup_link(&adapter->hw); 1957 } 1958 1959 /** 1960 * igb_power_down_link - Power down the phy/serdes link 1961 * @adapter: address of board private structure 1962 */ 1963 static void igb_power_down_link(struct igb_adapter *adapter) 1964 { 1965 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1966 igb_power_down_phy_copper_82575(&adapter->hw); 1967 else 1968 igb_shutdown_serdes_link_82575(&adapter->hw); 1969 } 1970 1971 /** 1972 * Detect and switch function for Media Auto Sense 1973 * @adapter: address of the board private structure 1974 **/ 1975 static void igb_check_swap_media(struct igb_adapter *adapter) 1976 { 1977 struct e1000_hw *hw = &adapter->hw; 1978 u32 ctrl_ext, connsw; 1979 bool swap_now = false; 1980 1981 ctrl_ext = rd32(E1000_CTRL_EXT); 1982 connsw = rd32(E1000_CONNSW); 1983 1984 /* need to live swap if current media is copper and we have fiber/serdes 1985 * to go to. 1986 */ 1987 1988 if ((hw->phy.media_type == e1000_media_type_copper) && 1989 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1990 swap_now = true; 1991 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1992 /* copper signal takes time to appear */ 1993 if (adapter->copper_tries < 4) { 1994 adapter->copper_tries++; 1995 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1996 wr32(E1000_CONNSW, connsw); 1997 return; 1998 } else { 1999 adapter->copper_tries = 0; 2000 if ((connsw & E1000_CONNSW_PHYSD) && 2001 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2002 swap_now = true; 2003 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2004 wr32(E1000_CONNSW, connsw); 2005 } 2006 } 2007 } 2008 2009 if (!swap_now) 2010 return; 2011 2012 switch (hw->phy.media_type) { 2013 case e1000_media_type_copper: 2014 netdev_info(adapter->netdev, 2015 "MAS: changing media to fiber/serdes\n"); 2016 ctrl_ext |= 2017 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2018 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2019 adapter->copper_tries = 0; 2020 break; 2021 case e1000_media_type_internal_serdes: 2022 case e1000_media_type_fiber: 2023 netdev_info(adapter->netdev, 2024 "MAS: changing media to copper\n"); 2025 ctrl_ext &= 2026 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2027 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2028 break; 2029 default: 2030 /* shouldn't get here during regular operation */ 2031 netdev_err(adapter->netdev, 2032 "AMS: Invalid media type found, returning\n"); 2033 break; 2034 } 2035 wr32(E1000_CTRL_EXT, ctrl_ext); 2036 } 2037 2038 /** 2039 * igb_up - Open the interface and prepare it to handle traffic 2040 * @adapter: board private structure 2041 **/ 2042 int igb_up(struct igb_adapter *adapter) 2043 { 2044 struct e1000_hw *hw = &adapter->hw; 2045 int i; 2046 2047 /* hardware has been reset, we need to reload some things */ 2048 igb_configure(adapter); 2049 2050 clear_bit(__IGB_DOWN, &adapter->state); 2051 2052 for (i = 0; i < adapter->num_q_vectors; i++) 2053 napi_enable(&(adapter->q_vector[i]->napi)); 2054 2055 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2056 igb_configure_msix(adapter); 2057 else 2058 igb_assign_vector(adapter->q_vector[0], 0); 2059 2060 /* Clear any pending interrupts. */ 2061 rd32(E1000_ICR); 2062 igb_irq_enable(adapter); 2063 2064 /* notify VFs that reset has been completed */ 2065 if (adapter->vfs_allocated_count) { 2066 u32 reg_data = rd32(E1000_CTRL_EXT); 2067 2068 reg_data |= E1000_CTRL_EXT_PFRSTD; 2069 wr32(E1000_CTRL_EXT, reg_data); 2070 } 2071 2072 netif_tx_start_all_queues(adapter->netdev); 2073 2074 /* start the watchdog. */ 2075 hw->mac.get_link_status = 1; 2076 schedule_work(&adapter->watchdog_task); 2077 2078 if ((adapter->flags & IGB_FLAG_EEE) && 2079 (!hw->dev_spec._82575.eee_disable)) 2080 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2081 2082 return 0; 2083 } 2084 2085 void igb_down(struct igb_adapter *adapter) 2086 { 2087 struct net_device *netdev = adapter->netdev; 2088 struct e1000_hw *hw = &adapter->hw; 2089 u32 tctl, rctl; 2090 int i; 2091 2092 /* signal that we're down so the interrupt handler does not 2093 * reschedule our watchdog timer 2094 */ 2095 set_bit(__IGB_DOWN, &adapter->state); 2096 2097 /* disable receives in the hardware */ 2098 rctl = rd32(E1000_RCTL); 2099 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2100 /* flush and sleep below */ 2101 2102 igb_nfc_filter_exit(adapter); 2103 2104 netif_carrier_off(netdev); 2105 netif_tx_stop_all_queues(netdev); 2106 2107 /* disable transmits in the hardware */ 2108 tctl = rd32(E1000_TCTL); 2109 tctl &= ~E1000_TCTL_EN; 2110 wr32(E1000_TCTL, tctl); 2111 /* flush both disables and wait for them to finish */ 2112 wrfl(); 2113 usleep_range(10000, 11000); 2114 2115 igb_irq_disable(adapter); 2116 2117 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2118 2119 for (i = 0; i < adapter->num_q_vectors; i++) { 2120 if (adapter->q_vector[i]) { 2121 napi_synchronize(&adapter->q_vector[i]->napi); 2122 napi_disable(&adapter->q_vector[i]->napi); 2123 } 2124 } 2125 2126 del_timer_sync(&adapter->watchdog_timer); 2127 del_timer_sync(&adapter->phy_info_timer); 2128 2129 /* record the stats before reset*/ 2130 spin_lock(&adapter->stats64_lock); 2131 igb_update_stats(adapter); 2132 spin_unlock(&adapter->stats64_lock); 2133 2134 adapter->link_speed = 0; 2135 adapter->link_duplex = 0; 2136 2137 if (!pci_channel_offline(adapter->pdev)) 2138 igb_reset(adapter); 2139 2140 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2141 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2142 2143 igb_clean_all_tx_rings(adapter); 2144 igb_clean_all_rx_rings(adapter); 2145 #ifdef CONFIG_IGB_DCA 2146 2147 /* since we reset the hardware DCA settings were cleared */ 2148 igb_setup_dca(adapter); 2149 #endif 2150 } 2151 2152 void igb_reinit_locked(struct igb_adapter *adapter) 2153 { 2154 WARN_ON(in_interrupt()); 2155 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2156 usleep_range(1000, 2000); 2157 igb_down(adapter); 2158 igb_up(adapter); 2159 clear_bit(__IGB_RESETTING, &adapter->state); 2160 } 2161 2162 /** igb_enable_mas - Media Autosense re-enable after swap 2163 * 2164 * @adapter: adapter struct 2165 **/ 2166 static void igb_enable_mas(struct igb_adapter *adapter) 2167 { 2168 struct e1000_hw *hw = &adapter->hw; 2169 u32 connsw = rd32(E1000_CONNSW); 2170 2171 /* configure for SerDes media detect */ 2172 if ((hw->phy.media_type == e1000_media_type_copper) && 2173 (!(connsw & E1000_CONNSW_SERDESD))) { 2174 connsw |= E1000_CONNSW_ENRGSRC; 2175 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2176 wr32(E1000_CONNSW, connsw); 2177 wrfl(); 2178 } 2179 } 2180 2181 void igb_reset(struct igb_adapter *adapter) 2182 { 2183 struct pci_dev *pdev = adapter->pdev; 2184 struct e1000_hw *hw = &adapter->hw; 2185 struct e1000_mac_info *mac = &hw->mac; 2186 struct e1000_fc_info *fc = &hw->fc; 2187 u32 pba, hwm; 2188 2189 /* Repartition Pba for greater than 9k mtu 2190 * To take effect CTRL.RST is required. 2191 */ 2192 switch (mac->type) { 2193 case e1000_i350: 2194 case e1000_i354: 2195 case e1000_82580: 2196 pba = rd32(E1000_RXPBS); 2197 pba = igb_rxpbs_adjust_82580(pba); 2198 break; 2199 case e1000_82576: 2200 pba = rd32(E1000_RXPBS); 2201 pba &= E1000_RXPBS_SIZE_MASK_82576; 2202 break; 2203 case e1000_82575: 2204 case e1000_i210: 2205 case e1000_i211: 2206 default: 2207 pba = E1000_PBA_34K; 2208 break; 2209 } 2210 2211 if (mac->type == e1000_82575) { 2212 u32 min_rx_space, min_tx_space, needed_tx_space; 2213 2214 /* write Rx PBA so that hardware can report correct Tx PBA */ 2215 wr32(E1000_PBA, pba); 2216 2217 /* To maintain wire speed transmits, the Tx FIFO should be 2218 * large enough to accommodate two full transmit packets, 2219 * rounded up to the next 1KB and expressed in KB. Likewise, 2220 * the Rx FIFO should be large enough to accommodate at least 2221 * one full receive packet and is similarly rounded up and 2222 * expressed in KB. 2223 */ 2224 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2225 2226 /* The Tx FIFO also stores 16 bytes of information about the Tx 2227 * but don't include Ethernet FCS because hardware appends it. 2228 * We only need to round down to the nearest 512 byte block 2229 * count since the value we care about is 2 frames, not 1. 2230 */ 2231 min_tx_space = adapter->max_frame_size; 2232 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2233 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2234 2235 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2236 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2237 2238 /* If current Tx allocation is less than the min Tx FIFO size, 2239 * and the min Tx FIFO size is less than the current Rx FIFO 2240 * allocation, take space away from current Rx allocation. 2241 */ 2242 if (needed_tx_space < pba) { 2243 pba -= needed_tx_space; 2244 2245 /* if short on Rx space, Rx wins and must trump Tx 2246 * adjustment 2247 */ 2248 if (pba < min_rx_space) 2249 pba = min_rx_space; 2250 } 2251 2252 /* adjust PBA for jumbo frames */ 2253 wr32(E1000_PBA, pba); 2254 } 2255 2256 /* flow control settings 2257 * The high water mark must be low enough to fit one full frame 2258 * after transmitting the pause frame. As such we must have enough 2259 * space to allow for us to complete our current transmit and then 2260 * receive the frame that is in progress from the link partner. 2261 * Set it to: 2262 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2263 */ 2264 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2265 2266 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2267 fc->low_water = fc->high_water - 16; 2268 fc->pause_time = 0xFFFF; 2269 fc->send_xon = 1; 2270 fc->current_mode = fc->requested_mode; 2271 2272 /* disable receive for all VFs and wait one second */ 2273 if (adapter->vfs_allocated_count) { 2274 int i; 2275 2276 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2277 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2278 2279 /* ping all the active vfs to let them know we are going down */ 2280 igb_ping_all_vfs(adapter); 2281 2282 /* disable transmits and receives */ 2283 wr32(E1000_VFRE, 0); 2284 wr32(E1000_VFTE, 0); 2285 } 2286 2287 /* Allow time for pending master requests to run */ 2288 hw->mac.ops.reset_hw(hw); 2289 wr32(E1000_WUC, 0); 2290 2291 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2292 /* need to resetup here after media swap */ 2293 adapter->ei.get_invariants(hw); 2294 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2295 } 2296 if ((mac->type == e1000_82575) && 2297 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2298 igb_enable_mas(adapter); 2299 } 2300 if (hw->mac.ops.init_hw(hw)) 2301 dev_err(&pdev->dev, "Hardware Error\n"); 2302 2303 /* RAR registers were cleared during init_hw, clear mac table */ 2304 igb_flush_mac_table(adapter); 2305 __dev_uc_unsync(adapter->netdev, NULL); 2306 2307 /* Recover default RAR entry */ 2308 igb_set_default_mac_filter(adapter); 2309 2310 /* Flow control settings reset on hardware reset, so guarantee flow 2311 * control is off when forcing speed. 2312 */ 2313 if (!hw->mac.autoneg) 2314 igb_force_mac_fc(hw); 2315 2316 igb_init_dmac(adapter, pba); 2317 #ifdef CONFIG_IGB_HWMON 2318 /* Re-initialize the thermal sensor on i350 devices. */ 2319 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2320 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2321 /* If present, re-initialize the external thermal sensor 2322 * interface. 2323 */ 2324 if (adapter->ets) 2325 mac->ops.init_thermal_sensor_thresh(hw); 2326 } 2327 } 2328 #endif 2329 /* Re-establish EEE setting */ 2330 if (hw->phy.media_type == e1000_media_type_copper) { 2331 switch (mac->type) { 2332 case e1000_i350: 2333 case e1000_i210: 2334 case e1000_i211: 2335 igb_set_eee_i350(hw, true, true); 2336 break; 2337 case e1000_i354: 2338 igb_set_eee_i354(hw, true, true); 2339 break; 2340 default: 2341 break; 2342 } 2343 } 2344 if (!netif_running(adapter->netdev)) 2345 igb_power_down_link(adapter); 2346 2347 igb_update_mng_vlan(adapter); 2348 2349 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2350 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2351 2352 /* Re-enable PTP, where applicable. */ 2353 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2354 igb_ptp_reset(adapter); 2355 2356 igb_get_phy_info(hw); 2357 } 2358 2359 static netdev_features_t igb_fix_features(struct net_device *netdev, 2360 netdev_features_t features) 2361 { 2362 /* Since there is no support for separate Rx/Tx vlan accel 2363 * enable/disable make sure Tx flag is always in same state as Rx. 2364 */ 2365 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2366 features |= NETIF_F_HW_VLAN_CTAG_TX; 2367 else 2368 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2369 2370 return features; 2371 } 2372 2373 static int igb_set_features(struct net_device *netdev, 2374 netdev_features_t features) 2375 { 2376 netdev_features_t changed = netdev->features ^ features; 2377 struct igb_adapter *adapter = netdev_priv(netdev); 2378 2379 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2380 igb_vlan_mode(netdev, features); 2381 2382 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2383 return 0; 2384 2385 if (!(features & NETIF_F_NTUPLE)) { 2386 struct hlist_node *node2; 2387 struct igb_nfc_filter *rule; 2388 2389 spin_lock(&adapter->nfc_lock); 2390 hlist_for_each_entry_safe(rule, node2, 2391 &adapter->nfc_filter_list, nfc_node) { 2392 igb_erase_filter(adapter, rule); 2393 hlist_del(&rule->nfc_node); 2394 kfree(rule); 2395 } 2396 spin_unlock(&adapter->nfc_lock); 2397 adapter->nfc_filter_count = 0; 2398 } 2399 2400 netdev->features = features; 2401 2402 if (netif_running(netdev)) 2403 igb_reinit_locked(adapter); 2404 else 2405 igb_reset(adapter); 2406 2407 return 0; 2408 } 2409 2410 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2411 struct net_device *dev, 2412 const unsigned char *addr, u16 vid, 2413 u16 flags) 2414 { 2415 /* guarantee we can provide a unique filter for the unicast address */ 2416 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2417 struct igb_adapter *adapter = netdev_priv(dev); 2418 int vfn = adapter->vfs_allocated_count; 2419 2420 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2421 return -ENOMEM; 2422 } 2423 2424 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2425 } 2426 2427 #define IGB_MAX_MAC_HDR_LEN 127 2428 #define IGB_MAX_NETWORK_HDR_LEN 511 2429 2430 static netdev_features_t 2431 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2432 netdev_features_t features) 2433 { 2434 unsigned int network_hdr_len, mac_hdr_len; 2435 2436 /* Make certain the headers can be described by a context descriptor */ 2437 mac_hdr_len = skb_network_header(skb) - skb->data; 2438 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2439 return features & ~(NETIF_F_HW_CSUM | 2440 NETIF_F_SCTP_CRC | 2441 NETIF_F_HW_VLAN_CTAG_TX | 2442 NETIF_F_TSO | 2443 NETIF_F_TSO6); 2444 2445 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2446 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2447 return features & ~(NETIF_F_HW_CSUM | 2448 NETIF_F_SCTP_CRC | 2449 NETIF_F_TSO | 2450 NETIF_F_TSO6); 2451 2452 /* We can only support IPV4 TSO in tunnels if we can mangle the 2453 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2454 */ 2455 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2456 features &= ~NETIF_F_TSO; 2457 2458 return features; 2459 } 2460 2461 static int igb_offload_cbs(struct igb_adapter *adapter, 2462 struct tc_cbs_qopt_offload *qopt) 2463 { 2464 struct e1000_hw *hw = &adapter->hw; 2465 int err; 2466 2467 /* CBS offloading is only supported by i210 controller. */ 2468 if (hw->mac.type != e1000_i210) 2469 return -EOPNOTSUPP; 2470 2471 /* CBS offloading is only supported by queue 0 and queue 1. */ 2472 if (qopt->queue < 0 || qopt->queue > 1) 2473 return -EINVAL; 2474 2475 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2476 qopt->idleslope, qopt->sendslope, 2477 qopt->hicredit, qopt->locredit); 2478 if (err) 2479 return err; 2480 2481 if (is_fqtss_enabled(adapter)) { 2482 igb_configure_cbs(adapter, qopt->queue, qopt->enable, 2483 qopt->idleslope, qopt->sendslope, 2484 qopt->hicredit, qopt->locredit); 2485 2486 if (!is_any_cbs_enabled(adapter)) 2487 enable_fqtss(adapter, false); 2488 2489 } else { 2490 enable_fqtss(adapter, true); 2491 } 2492 2493 return 0; 2494 } 2495 2496 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2497 #define VLAN_PRIO_FULL_MASK (0x07) 2498 2499 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2500 struct tc_cls_flower_offload *f, 2501 int traffic_class, 2502 struct igb_nfc_filter *input) 2503 { 2504 struct netlink_ext_ack *extack = f->common.extack; 2505 2506 if (f->dissector->used_keys & 2507 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2508 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2509 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2510 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2511 NL_SET_ERR_MSG_MOD(extack, 2512 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2513 return -EOPNOTSUPP; 2514 } 2515 2516 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2517 struct flow_dissector_key_eth_addrs *key, *mask; 2518 2519 key = skb_flow_dissector_target(f->dissector, 2520 FLOW_DISSECTOR_KEY_ETH_ADDRS, 2521 f->key); 2522 mask = skb_flow_dissector_target(f->dissector, 2523 FLOW_DISSECTOR_KEY_ETH_ADDRS, 2524 f->mask); 2525 2526 if (!is_zero_ether_addr(mask->dst)) { 2527 if (!is_broadcast_ether_addr(mask->dst)) { 2528 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2529 return -EINVAL; 2530 } 2531 2532 input->filter.match_flags |= 2533 IGB_FILTER_FLAG_DST_MAC_ADDR; 2534 ether_addr_copy(input->filter.dst_addr, key->dst); 2535 } 2536 2537 if (!is_zero_ether_addr(mask->src)) { 2538 if (!is_broadcast_ether_addr(mask->src)) { 2539 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2540 return -EINVAL; 2541 } 2542 2543 input->filter.match_flags |= 2544 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2545 ether_addr_copy(input->filter.src_addr, key->src); 2546 } 2547 } 2548 2549 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) { 2550 struct flow_dissector_key_basic *key, *mask; 2551 2552 key = skb_flow_dissector_target(f->dissector, 2553 FLOW_DISSECTOR_KEY_BASIC, 2554 f->key); 2555 mask = skb_flow_dissector_target(f->dissector, 2556 FLOW_DISSECTOR_KEY_BASIC, 2557 f->mask); 2558 2559 if (mask->n_proto) { 2560 if (mask->n_proto != ETHER_TYPE_FULL_MASK) { 2561 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2562 return -EINVAL; 2563 } 2564 2565 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2566 input->filter.etype = key->n_proto; 2567 } 2568 } 2569 2570 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) { 2571 struct flow_dissector_key_vlan *key, *mask; 2572 2573 key = skb_flow_dissector_target(f->dissector, 2574 FLOW_DISSECTOR_KEY_VLAN, 2575 f->key); 2576 mask = skb_flow_dissector_target(f->dissector, 2577 FLOW_DISSECTOR_KEY_VLAN, 2578 f->mask); 2579 2580 if (mask->vlan_priority) { 2581 if (mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2582 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2583 return -EINVAL; 2584 } 2585 2586 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2587 input->filter.vlan_tci = key->vlan_priority; 2588 } 2589 } 2590 2591 input->action = traffic_class; 2592 input->cookie = f->cookie; 2593 2594 return 0; 2595 } 2596 2597 static int igb_configure_clsflower(struct igb_adapter *adapter, 2598 struct tc_cls_flower_offload *cls_flower) 2599 { 2600 struct netlink_ext_ack *extack = cls_flower->common.extack; 2601 struct igb_nfc_filter *filter, *f; 2602 int err, tc; 2603 2604 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2605 if (tc < 0) { 2606 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2607 return -EINVAL; 2608 } 2609 2610 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2611 if (!filter) 2612 return -ENOMEM; 2613 2614 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2615 if (err < 0) 2616 goto err_parse; 2617 2618 spin_lock(&adapter->nfc_lock); 2619 2620 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2621 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2622 err = -EEXIST; 2623 NL_SET_ERR_MSG_MOD(extack, 2624 "This filter is already set in ethtool"); 2625 goto err_locked; 2626 } 2627 } 2628 2629 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2630 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2631 err = -EEXIST; 2632 NL_SET_ERR_MSG_MOD(extack, 2633 "This filter is already set in cls_flower"); 2634 goto err_locked; 2635 } 2636 } 2637 2638 err = igb_add_filter(adapter, filter); 2639 if (err < 0) { 2640 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2641 goto err_locked; 2642 } 2643 2644 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2645 2646 spin_unlock(&adapter->nfc_lock); 2647 2648 return 0; 2649 2650 err_locked: 2651 spin_unlock(&adapter->nfc_lock); 2652 2653 err_parse: 2654 kfree(filter); 2655 2656 return err; 2657 } 2658 2659 static int igb_delete_clsflower(struct igb_adapter *adapter, 2660 struct tc_cls_flower_offload *cls_flower) 2661 { 2662 struct igb_nfc_filter *filter; 2663 int err; 2664 2665 spin_lock(&adapter->nfc_lock); 2666 2667 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2668 if (filter->cookie == cls_flower->cookie) 2669 break; 2670 2671 if (!filter) { 2672 err = -ENOENT; 2673 goto out; 2674 } 2675 2676 err = igb_erase_filter(adapter, filter); 2677 if (err < 0) 2678 goto out; 2679 2680 hlist_del(&filter->nfc_node); 2681 kfree(filter); 2682 2683 out: 2684 spin_unlock(&adapter->nfc_lock); 2685 2686 return err; 2687 } 2688 2689 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2690 struct tc_cls_flower_offload *cls_flower) 2691 { 2692 switch (cls_flower->command) { 2693 case TC_CLSFLOWER_REPLACE: 2694 return igb_configure_clsflower(adapter, cls_flower); 2695 case TC_CLSFLOWER_DESTROY: 2696 return igb_delete_clsflower(adapter, cls_flower); 2697 case TC_CLSFLOWER_STATS: 2698 return -EOPNOTSUPP; 2699 default: 2700 return -EINVAL; 2701 } 2702 } 2703 2704 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2705 void *cb_priv) 2706 { 2707 struct igb_adapter *adapter = cb_priv; 2708 2709 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2710 return -EOPNOTSUPP; 2711 2712 switch (type) { 2713 case TC_SETUP_CLSFLOWER: 2714 return igb_setup_tc_cls_flower(adapter, type_data); 2715 2716 default: 2717 return -EOPNOTSUPP; 2718 } 2719 } 2720 2721 static int igb_setup_tc_block(struct igb_adapter *adapter, 2722 struct tc_block_offload *f) 2723 { 2724 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2725 return -EOPNOTSUPP; 2726 2727 switch (f->command) { 2728 case TC_BLOCK_BIND: 2729 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb, 2730 adapter, adapter); 2731 case TC_BLOCK_UNBIND: 2732 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb, 2733 adapter); 2734 return 0; 2735 default: 2736 return -EOPNOTSUPP; 2737 } 2738 } 2739 2740 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2741 void *type_data) 2742 { 2743 struct igb_adapter *adapter = netdev_priv(dev); 2744 2745 switch (type) { 2746 case TC_SETUP_QDISC_CBS: 2747 return igb_offload_cbs(adapter, type_data); 2748 case TC_SETUP_BLOCK: 2749 return igb_setup_tc_block(adapter, type_data); 2750 2751 default: 2752 return -EOPNOTSUPP; 2753 } 2754 } 2755 2756 static const struct net_device_ops igb_netdev_ops = { 2757 .ndo_open = igb_open, 2758 .ndo_stop = igb_close, 2759 .ndo_start_xmit = igb_xmit_frame, 2760 .ndo_get_stats64 = igb_get_stats64, 2761 .ndo_set_rx_mode = igb_set_rx_mode, 2762 .ndo_set_mac_address = igb_set_mac, 2763 .ndo_change_mtu = igb_change_mtu, 2764 .ndo_do_ioctl = igb_ioctl, 2765 .ndo_tx_timeout = igb_tx_timeout, 2766 .ndo_validate_addr = eth_validate_addr, 2767 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2768 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2769 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2770 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2771 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2772 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2773 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2774 .ndo_get_vf_config = igb_ndo_get_vf_config, 2775 #ifdef CONFIG_NET_POLL_CONTROLLER 2776 .ndo_poll_controller = igb_netpoll, 2777 #endif 2778 .ndo_fix_features = igb_fix_features, 2779 .ndo_set_features = igb_set_features, 2780 .ndo_fdb_add = igb_ndo_fdb_add, 2781 .ndo_features_check = igb_features_check, 2782 .ndo_setup_tc = igb_setup_tc, 2783 }; 2784 2785 /** 2786 * igb_set_fw_version - Configure version string for ethtool 2787 * @adapter: adapter struct 2788 **/ 2789 void igb_set_fw_version(struct igb_adapter *adapter) 2790 { 2791 struct e1000_hw *hw = &adapter->hw; 2792 struct e1000_fw_version fw; 2793 2794 igb_get_fw_version(hw, &fw); 2795 2796 switch (hw->mac.type) { 2797 case e1000_i210: 2798 case e1000_i211: 2799 if (!(igb_get_flash_presence_i210(hw))) { 2800 snprintf(adapter->fw_version, 2801 sizeof(adapter->fw_version), 2802 "%2d.%2d-%d", 2803 fw.invm_major, fw.invm_minor, 2804 fw.invm_img_type); 2805 break; 2806 } 2807 /* fall through */ 2808 default: 2809 /* if option is rom valid, display its version too */ 2810 if (fw.or_valid) { 2811 snprintf(adapter->fw_version, 2812 sizeof(adapter->fw_version), 2813 "%d.%d, 0x%08x, %d.%d.%d", 2814 fw.eep_major, fw.eep_minor, fw.etrack_id, 2815 fw.or_major, fw.or_build, fw.or_patch); 2816 /* no option rom */ 2817 } else if (fw.etrack_id != 0X0000) { 2818 snprintf(adapter->fw_version, 2819 sizeof(adapter->fw_version), 2820 "%d.%d, 0x%08x", 2821 fw.eep_major, fw.eep_minor, fw.etrack_id); 2822 } else { 2823 snprintf(adapter->fw_version, 2824 sizeof(adapter->fw_version), 2825 "%d.%d.%d", 2826 fw.eep_major, fw.eep_minor, fw.eep_build); 2827 } 2828 break; 2829 } 2830 } 2831 2832 /** 2833 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2834 * 2835 * @adapter: adapter struct 2836 **/ 2837 static void igb_init_mas(struct igb_adapter *adapter) 2838 { 2839 struct e1000_hw *hw = &adapter->hw; 2840 u16 eeprom_data; 2841 2842 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2843 switch (hw->bus.func) { 2844 case E1000_FUNC_0: 2845 if (eeprom_data & IGB_MAS_ENABLE_0) { 2846 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2847 netdev_info(adapter->netdev, 2848 "MAS: Enabling Media Autosense for port %d\n", 2849 hw->bus.func); 2850 } 2851 break; 2852 case E1000_FUNC_1: 2853 if (eeprom_data & IGB_MAS_ENABLE_1) { 2854 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2855 netdev_info(adapter->netdev, 2856 "MAS: Enabling Media Autosense for port %d\n", 2857 hw->bus.func); 2858 } 2859 break; 2860 case E1000_FUNC_2: 2861 if (eeprom_data & IGB_MAS_ENABLE_2) { 2862 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2863 netdev_info(adapter->netdev, 2864 "MAS: Enabling Media Autosense for port %d\n", 2865 hw->bus.func); 2866 } 2867 break; 2868 case E1000_FUNC_3: 2869 if (eeprom_data & IGB_MAS_ENABLE_3) { 2870 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2871 netdev_info(adapter->netdev, 2872 "MAS: Enabling Media Autosense for port %d\n", 2873 hw->bus.func); 2874 } 2875 break; 2876 default: 2877 /* Shouldn't get here */ 2878 netdev_err(adapter->netdev, 2879 "MAS: Invalid port configuration, returning\n"); 2880 break; 2881 } 2882 } 2883 2884 /** 2885 * igb_init_i2c - Init I2C interface 2886 * @adapter: pointer to adapter structure 2887 **/ 2888 static s32 igb_init_i2c(struct igb_adapter *adapter) 2889 { 2890 s32 status = 0; 2891 2892 /* I2C interface supported on i350 devices */ 2893 if (adapter->hw.mac.type != e1000_i350) 2894 return 0; 2895 2896 /* Initialize the i2c bus which is controlled by the registers. 2897 * This bus will use the i2c_algo_bit structue that implements 2898 * the protocol through toggling of the 4 bits in the register. 2899 */ 2900 adapter->i2c_adap.owner = THIS_MODULE; 2901 adapter->i2c_algo = igb_i2c_algo; 2902 adapter->i2c_algo.data = adapter; 2903 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2904 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2905 strlcpy(adapter->i2c_adap.name, "igb BB", 2906 sizeof(adapter->i2c_adap.name)); 2907 status = i2c_bit_add_bus(&adapter->i2c_adap); 2908 return status; 2909 } 2910 2911 /** 2912 * igb_probe - Device Initialization Routine 2913 * @pdev: PCI device information struct 2914 * @ent: entry in igb_pci_tbl 2915 * 2916 * Returns 0 on success, negative on failure 2917 * 2918 * igb_probe initializes an adapter identified by a pci_dev structure. 2919 * The OS initialization, configuring of the adapter private structure, 2920 * and a hardware reset occur. 2921 **/ 2922 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2923 { 2924 struct net_device *netdev; 2925 struct igb_adapter *adapter; 2926 struct e1000_hw *hw; 2927 u16 eeprom_data = 0; 2928 s32 ret_val; 2929 static int global_quad_port_a; /* global quad port a indication */ 2930 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2931 int err, pci_using_dac; 2932 u8 part_str[E1000_PBANUM_LENGTH]; 2933 2934 /* Catch broken hardware that put the wrong VF device ID in 2935 * the PCIe SR-IOV capability. 2936 */ 2937 if (pdev->is_virtfn) { 2938 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2939 pci_name(pdev), pdev->vendor, pdev->device); 2940 return -EINVAL; 2941 } 2942 2943 err = pci_enable_device_mem(pdev); 2944 if (err) 2945 return err; 2946 2947 pci_using_dac = 0; 2948 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2949 if (!err) { 2950 pci_using_dac = 1; 2951 } else { 2952 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2953 if (err) { 2954 dev_err(&pdev->dev, 2955 "No usable DMA configuration, aborting\n"); 2956 goto err_dma; 2957 } 2958 } 2959 2960 err = pci_request_mem_regions(pdev, igb_driver_name); 2961 if (err) 2962 goto err_pci_reg; 2963 2964 pci_enable_pcie_error_reporting(pdev); 2965 2966 pci_set_master(pdev); 2967 pci_save_state(pdev); 2968 2969 err = -ENOMEM; 2970 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2971 IGB_MAX_TX_QUEUES); 2972 if (!netdev) 2973 goto err_alloc_etherdev; 2974 2975 SET_NETDEV_DEV(netdev, &pdev->dev); 2976 2977 pci_set_drvdata(pdev, netdev); 2978 adapter = netdev_priv(netdev); 2979 adapter->netdev = netdev; 2980 adapter->pdev = pdev; 2981 hw = &adapter->hw; 2982 hw->back = adapter; 2983 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2984 2985 err = -EIO; 2986 adapter->io_addr = pci_iomap(pdev, 0, 0); 2987 if (!adapter->io_addr) 2988 goto err_ioremap; 2989 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2990 hw->hw_addr = adapter->io_addr; 2991 2992 netdev->netdev_ops = &igb_netdev_ops; 2993 igb_set_ethtool_ops(netdev); 2994 netdev->watchdog_timeo = 5 * HZ; 2995 2996 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2997 2998 netdev->mem_start = pci_resource_start(pdev, 0); 2999 netdev->mem_end = pci_resource_end(pdev, 0); 3000 3001 /* PCI config space info */ 3002 hw->vendor_id = pdev->vendor; 3003 hw->device_id = pdev->device; 3004 hw->revision_id = pdev->revision; 3005 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3006 hw->subsystem_device_id = pdev->subsystem_device; 3007 3008 /* Copy the default MAC, PHY and NVM function pointers */ 3009 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3010 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3011 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3012 /* Initialize skew-specific constants */ 3013 err = ei->get_invariants(hw); 3014 if (err) 3015 goto err_sw_init; 3016 3017 /* setup the private structure */ 3018 err = igb_sw_init(adapter); 3019 if (err) 3020 goto err_sw_init; 3021 3022 igb_get_bus_info_pcie(hw); 3023 3024 hw->phy.autoneg_wait_to_complete = false; 3025 3026 /* Copper options */ 3027 if (hw->phy.media_type == e1000_media_type_copper) { 3028 hw->phy.mdix = AUTO_ALL_MODES; 3029 hw->phy.disable_polarity_correction = false; 3030 hw->phy.ms_type = e1000_ms_hw_default; 3031 } 3032 3033 if (igb_check_reset_block(hw)) 3034 dev_info(&pdev->dev, 3035 "PHY reset is blocked due to SOL/IDER session.\n"); 3036 3037 /* features is initialized to 0 in allocation, it might have bits 3038 * set by igb_sw_init so we should use an or instead of an 3039 * assignment. 3040 */ 3041 netdev->features |= NETIF_F_SG | 3042 NETIF_F_TSO | 3043 NETIF_F_TSO6 | 3044 NETIF_F_RXHASH | 3045 NETIF_F_RXCSUM | 3046 NETIF_F_HW_CSUM; 3047 3048 if (hw->mac.type >= e1000_82576) 3049 netdev->features |= NETIF_F_SCTP_CRC; 3050 3051 if (hw->mac.type >= e1000_i350) 3052 netdev->features |= NETIF_F_HW_TC; 3053 3054 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3055 NETIF_F_GSO_GRE_CSUM | \ 3056 NETIF_F_GSO_IPXIP4 | \ 3057 NETIF_F_GSO_IPXIP6 | \ 3058 NETIF_F_GSO_UDP_TUNNEL | \ 3059 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3060 3061 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3062 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3063 3064 /* copy netdev features into list of user selectable features */ 3065 netdev->hw_features |= netdev->features | 3066 NETIF_F_HW_VLAN_CTAG_RX | 3067 NETIF_F_HW_VLAN_CTAG_TX | 3068 NETIF_F_RXALL; 3069 3070 if (hw->mac.type >= e1000_i350) 3071 netdev->hw_features |= NETIF_F_NTUPLE; 3072 3073 if (pci_using_dac) 3074 netdev->features |= NETIF_F_HIGHDMA; 3075 3076 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3077 netdev->mpls_features |= NETIF_F_HW_CSUM; 3078 netdev->hw_enc_features |= netdev->vlan_features; 3079 3080 /* set this bit last since it cannot be part of vlan_features */ 3081 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3082 NETIF_F_HW_VLAN_CTAG_RX | 3083 NETIF_F_HW_VLAN_CTAG_TX; 3084 3085 netdev->priv_flags |= IFF_SUPP_NOFCS; 3086 3087 netdev->priv_flags |= IFF_UNICAST_FLT; 3088 3089 /* MTU range: 68 - 9216 */ 3090 netdev->min_mtu = ETH_MIN_MTU; 3091 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3092 3093 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3094 3095 /* before reading the NVM, reset the controller to put the device in a 3096 * known good starting state 3097 */ 3098 hw->mac.ops.reset_hw(hw); 3099 3100 /* make sure the NVM is good , i211/i210 parts can have special NVM 3101 * that doesn't contain a checksum 3102 */ 3103 switch (hw->mac.type) { 3104 case e1000_i210: 3105 case e1000_i211: 3106 if (igb_get_flash_presence_i210(hw)) { 3107 if (hw->nvm.ops.validate(hw) < 0) { 3108 dev_err(&pdev->dev, 3109 "The NVM Checksum Is Not Valid\n"); 3110 err = -EIO; 3111 goto err_eeprom; 3112 } 3113 } 3114 break; 3115 default: 3116 if (hw->nvm.ops.validate(hw) < 0) { 3117 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3118 err = -EIO; 3119 goto err_eeprom; 3120 } 3121 break; 3122 } 3123 3124 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3125 /* copy the MAC address out of the NVM */ 3126 if (hw->mac.ops.read_mac_addr(hw)) 3127 dev_err(&pdev->dev, "NVM Read Error\n"); 3128 } 3129 3130 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3131 3132 if (!is_valid_ether_addr(netdev->dev_addr)) { 3133 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3134 err = -EIO; 3135 goto err_eeprom; 3136 } 3137 3138 igb_set_default_mac_filter(adapter); 3139 3140 /* get firmware version for ethtool -i */ 3141 igb_set_fw_version(adapter); 3142 3143 /* configure RXPBSIZE and TXPBSIZE */ 3144 if (hw->mac.type == e1000_i210) { 3145 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3146 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3147 } 3148 3149 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3150 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3151 3152 INIT_WORK(&adapter->reset_task, igb_reset_task); 3153 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3154 3155 /* Initialize link properties that are user-changeable */ 3156 adapter->fc_autoneg = true; 3157 hw->mac.autoneg = true; 3158 hw->phy.autoneg_advertised = 0x2f; 3159 3160 hw->fc.requested_mode = e1000_fc_default; 3161 hw->fc.current_mode = e1000_fc_default; 3162 3163 igb_validate_mdi_setting(hw); 3164 3165 /* By default, support wake on port A */ 3166 if (hw->bus.func == 0) 3167 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3168 3169 /* Check the NVM for wake support on non-port A ports */ 3170 if (hw->mac.type >= e1000_82580) 3171 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3172 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3173 &eeprom_data); 3174 else if (hw->bus.func == 1) 3175 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3176 3177 if (eeprom_data & IGB_EEPROM_APME) 3178 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3179 3180 /* now that we have the eeprom settings, apply the special cases where 3181 * the eeprom may be wrong or the board simply won't support wake on 3182 * lan on a particular port 3183 */ 3184 switch (pdev->device) { 3185 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3186 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3187 break; 3188 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3189 case E1000_DEV_ID_82576_FIBER: 3190 case E1000_DEV_ID_82576_SERDES: 3191 /* Wake events only supported on port A for dual fiber 3192 * regardless of eeprom setting 3193 */ 3194 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3195 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3196 break; 3197 case E1000_DEV_ID_82576_QUAD_COPPER: 3198 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3199 /* if quad port adapter, disable WoL on all but port A */ 3200 if (global_quad_port_a != 0) 3201 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3202 else 3203 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3204 /* Reset for multiple quad port adapters */ 3205 if (++global_quad_port_a == 4) 3206 global_quad_port_a = 0; 3207 break; 3208 default: 3209 /* If the device can't wake, don't set software support */ 3210 if (!device_can_wakeup(&adapter->pdev->dev)) 3211 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3212 } 3213 3214 /* initialize the wol settings based on the eeprom settings */ 3215 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3216 adapter->wol |= E1000_WUFC_MAG; 3217 3218 /* Some vendors want WoL disabled by default, but still supported */ 3219 if ((hw->mac.type == e1000_i350) && 3220 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3221 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3222 adapter->wol = 0; 3223 } 3224 3225 /* Some vendors want the ability to Use the EEPROM setting as 3226 * enable/disable only, and not for capability 3227 */ 3228 if (((hw->mac.type == e1000_i350) || 3229 (hw->mac.type == e1000_i354)) && 3230 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3231 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3232 adapter->wol = 0; 3233 } 3234 if (hw->mac.type == e1000_i350) { 3235 if (((pdev->subsystem_device == 0x5001) || 3236 (pdev->subsystem_device == 0x5002)) && 3237 (hw->bus.func == 0)) { 3238 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3239 adapter->wol = 0; 3240 } 3241 if (pdev->subsystem_device == 0x1F52) 3242 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3243 } 3244 3245 device_set_wakeup_enable(&adapter->pdev->dev, 3246 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3247 3248 /* reset the hardware with the new settings */ 3249 igb_reset(adapter); 3250 3251 /* Init the I2C interface */ 3252 err = igb_init_i2c(adapter); 3253 if (err) { 3254 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3255 goto err_eeprom; 3256 } 3257 3258 /* let the f/w know that the h/w is now under the control of the 3259 * driver. 3260 */ 3261 igb_get_hw_control(adapter); 3262 3263 strcpy(netdev->name, "eth%d"); 3264 err = register_netdev(netdev); 3265 if (err) 3266 goto err_register; 3267 3268 /* carrier off reporting is important to ethtool even BEFORE open */ 3269 netif_carrier_off(netdev); 3270 3271 #ifdef CONFIG_IGB_DCA 3272 if (dca_add_requester(&pdev->dev) == 0) { 3273 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3274 dev_info(&pdev->dev, "DCA enabled\n"); 3275 igb_setup_dca(adapter); 3276 } 3277 3278 #endif 3279 #ifdef CONFIG_IGB_HWMON 3280 /* Initialize the thermal sensor on i350 devices. */ 3281 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3282 u16 ets_word; 3283 3284 /* Read the NVM to determine if this i350 device supports an 3285 * external thermal sensor. 3286 */ 3287 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3288 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3289 adapter->ets = true; 3290 else 3291 adapter->ets = false; 3292 if (igb_sysfs_init(adapter)) 3293 dev_err(&pdev->dev, 3294 "failed to allocate sysfs resources\n"); 3295 } else { 3296 adapter->ets = false; 3297 } 3298 #endif 3299 /* Check if Media Autosense is enabled */ 3300 adapter->ei = *ei; 3301 if (hw->dev_spec._82575.mas_capable) 3302 igb_init_mas(adapter); 3303 3304 /* do hw tstamp init after resetting */ 3305 igb_ptp_init(adapter); 3306 3307 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3308 /* print bus type/speed/width info, not applicable to i354 */ 3309 if (hw->mac.type != e1000_i354) { 3310 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3311 netdev->name, 3312 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3313 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3314 "unknown"), 3315 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3316 "Width x4" : 3317 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3318 "Width x2" : 3319 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3320 "Width x1" : "unknown"), netdev->dev_addr); 3321 } 3322 3323 if ((hw->mac.type >= e1000_i210 || 3324 igb_get_flash_presence_i210(hw))) { 3325 ret_val = igb_read_part_string(hw, part_str, 3326 E1000_PBANUM_LENGTH); 3327 } else { 3328 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3329 } 3330 3331 if (ret_val) 3332 strcpy(part_str, "Unknown"); 3333 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3334 dev_info(&pdev->dev, 3335 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3336 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3337 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3338 adapter->num_rx_queues, adapter->num_tx_queues); 3339 if (hw->phy.media_type == e1000_media_type_copper) { 3340 switch (hw->mac.type) { 3341 case e1000_i350: 3342 case e1000_i210: 3343 case e1000_i211: 3344 /* Enable EEE for internal copper PHY devices */ 3345 err = igb_set_eee_i350(hw, true, true); 3346 if ((!err) && 3347 (!hw->dev_spec._82575.eee_disable)) { 3348 adapter->eee_advert = 3349 MDIO_EEE_100TX | MDIO_EEE_1000T; 3350 adapter->flags |= IGB_FLAG_EEE; 3351 } 3352 break; 3353 case e1000_i354: 3354 if ((rd32(E1000_CTRL_EXT) & 3355 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3356 err = igb_set_eee_i354(hw, true, true); 3357 if ((!err) && 3358 (!hw->dev_spec._82575.eee_disable)) { 3359 adapter->eee_advert = 3360 MDIO_EEE_100TX | MDIO_EEE_1000T; 3361 adapter->flags |= IGB_FLAG_EEE; 3362 } 3363 } 3364 break; 3365 default: 3366 break; 3367 } 3368 } 3369 pm_runtime_put_noidle(&pdev->dev); 3370 return 0; 3371 3372 err_register: 3373 igb_release_hw_control(adapter); 3374 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3375 err_eeprom: 3376 if (!igb_check_reset_block(hw)) 3377 igb_reset_phy(hw); 3378 3379 if (hw->flash_address) 3380 iounmap(hw->flash_address); 3381 err_sw_init: 3382 kfree(adapter->mac_table); 3383 kfree(adapter->shadow_vfta); 3384 igb_clear_interrupt_scheme(adapter); 3385 #ifdef CONFIG_PCI_IOV 3386 igb_disable_sriov(pdev); 3387 #endif 3388 pci_iounmap(pdev, adapter->io_addr); 3389 err_ioremap: 3390 free_netdev(netdev); 3391 err_alloc_etherdev: 3392 pci_release_mem_regions(pdev); 3393 err_pci_reg: 3394 err_dma: 3395 pci_disable_device(pdev); 3396 return err; 3397 } 3398 3399 #ifdef CONFIG_PCI_IOV 3400 static int igb_disable_sriov(struct pci_dev *pdev) 3401 { 3402 struct net_device *netdev = pci_get_drvdata(pdev); 3403 struct igb_adapter *adapter = netdev_priv(netdev); 3404 struct e1000_hw *hw = &adapter->hw; 3405 3406 /* reclaim resources allocated to VFs */ 3407 if (adapter->vf_data) { 3408 /* disable iov and allow time for transactions to clear */ 3409 if (pci_vfs_assigned(pdev)) { 3410 dev_warn(&pdev->dev, 3411 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3412 return -EPERM; 3413 } else { 3414 pci_disable_sriov(pdev); 3415 msleep(500); 3416 } 3417 3418 kfree(adapter->vf_mac_list); 3419 adapter->vf_mac_list = NULL; 3420 kfree(adapter->vf_data); 3421 adapter->vf_data = NULL; 3422 adapter->vfs_allocated_count = 0; 3423 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3424 wrfl(); 3425 msleep(100); 3426 dev_info(&pdev->dev, "IOV Disabled\n"); 3427 3428 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3429 adapter->flags |= IGB_FLAG_DMAC; 3430 } 3431 3432 return 0; 3433 } 3434 3435 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3436 { 3437 struct net_device *netdev = pci_get_drvdata(pdev); 3438 struct igb_adapter *adapter = netdev_priv(netdev); 3439 int old_vfs = pci_num_vf(pdev); 3440 struct vf_mac_filter *mac_list; 3441 int err = 0; 3442 int num_vf_mac_filters, i; 3443 3444 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3445 err = -EPERM; 3446 goto out; 3447 } 3448 if (!num_vfs) 3449 goto out; 3450 3451 if (old_vfs) { 3452 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3453 old_vfs, max_vfs); 3454 adapter->vfs_allocated_count = old_vfs; 3455 } else 3456 adapter->vfs_allocated_count = num_vfs; 3457 3458 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3459 sizeof(struct vf_data_storage), GFP_KERNEL); 3460 3461 /* if allocation failed then we do not support SR-IOV */ 3462 if (!adapter->vf_data) { 3463 adapter->vfs_allocated_count = 0; 3464 err = -ENOMEM; 3465 goto out; 3466 } 3467 3468 /* Due to the limited number of RAR entries calculate potential 3469 * number of MAC filters available for the VFs. Reserve entries 3470 * for PF default MAC, PF MAC filters and at least one RAR entry 3471 * for each VF for VF MAC. 3472 */ 3473 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3474 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3475 adapter->vfs_allocated_count); 3476 3477 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3478 sizeof(struct vf_mac_filter), 3479 GFP_KERNEL); 3480 3481 mac_list = adapter->vf_mac_list; 3482 INIT_LIST_HEAD(&adapter->vf_macs.l); 3483 3484 if (adapter->vf_mac_list) { 3485 /* Initialize list of VF MAC filters */ 3486 for (i = 0; i < num_vf_mac_filters; i++) { 3487 mac_list->vf = -1; 3488 mac_list->free = true; 3489 list_add(&mac_list->l, &adapter->vf_macs.l); 3490 mac_list++; 3491 } 3492 } else { 3493 /* If we could not allocate memory for the VF MAC filters 3494 * we can continue without this feature but warn user. 3495 */ 3496 dev_err(&pdev->dev, 3497 "Unable to allocate memory for VF MAC filter list\n"); 3498 } 3499 3500 /* only call pci_enable_sriov() if no VFs are allocated already */ 3501 if (!old_vfs) { 3502 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3503 if (err) 3504 goto err_out; 3505 } 3506 dev_info(&pdev->dev, "%d VFs allocated\n", 3507 adapter->vfs_allocated_count); 3508 for (i = 0; i < adapter->vfs_allocated_count; i++) 3509 igb_vf_configure(adapter, i); 3510 3511 /* DMA Coalescing is not supported in IOV mode. */ 3512 adapter->flags &= ~IGB_FLAG_DMAC; 3513 goto out; 3514 3515 err_out: 3516 kfree(adapter->vf_mac_list); 3517 adapter->vf_mac_list = NULL; 3518 kfree(adapter->vf_data); 3519 adapter->vf_data = NULL; 3520 adapter->vfs_allocated_count = 0; 3521 out: 3522 return err; 3523 } 3524 3525 #endif 3526 /** 3527 * igb_remove_i2c - Cleanup I2C interface 3528 * @adapter: pointer to adapter structure 3529 **/ 3530 static void igb_remove_i2c(struct igb_adapter *adapter) 3531 { 3532 /* free the adapter bus structure */ 3533 i2c_del_adapter(&adapter->i2c_adap); 3534 } 3535 3536 /** 3537 * igb_remove - Device Removal Routine 3538 * @pdev: PCI device information struct 3539 * 3540 * igb_remove is called by the PCI subsystem to alert the driver 3541 * that it should release a PCI device. The could be caused by a 3542 * Hot-Plug event, or because the driver is going to be removed from 3543 * memory. 3544 **/ 3545 static void igb_remove(struct pci_dev *pdev) 3546 { 3547 struct net_device *netdev = pci_get_drvdata(pdev); 3548 struct igb_adapter *adapter = netdev_priv(netdev); 3549 struct e1000_hw *hw = &adapter->hw; 3550 3551 pm_runtime_get_noresume(&pdev->dev); 3552 #ifdef CONFIG_IGB_HWMON 3553 igb_sysfs_exit(adapter); 3554 #endif 3555 igb_remove_i2c(adapter); 3556 igb_ptp_stop(adapter); 3557 /* The watchdog timer may be rescheduled, so explicitly 3558 * disable watchdog from being rescheduled. 3559 */ 3560 set_bit(__IGB_DOWN, &adapter->state); 3561 del_timer_sync(&adapter->watchdog_timer); 3562 del_timer_sync(&adapter->phy_info_timer); 3563 3564 cancel_work_sync(&adapter->reset_task); 3565 cancel_work_sync(&adapter->watchdog_task); 3566 3567 #ifdef CONFIG_IGB_DCA 3568 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3569 dev_info(&pdev->dev, "DCA disabled\n"); 3570 dca_remove_requester(&pdev->dev); 3571 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3572 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3573 } 3574 #endif 3575 3576 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3577 * would have already happened in close and is redundant. 3578 */ 3579 igb_release_hw_control(adapter); 3580 3581 #ifdef CONFIG_PCI_IOV 3582 igb_disable_sriov(pdev); 3583 #endif 3584 3585 unregister_netdev(netdev); 3586 3587 igb_clear_interrupt_scheme(adapter); 3588 3589 pci_iounmap(pdev, adapter->io_addr); 3590 if (hw->flash_address) 3591 iounmap(hw->flash_address); 3592 pci_release_mem_regions(pdev); 3593 3594 kfree(adapter->mac_table); 3595 kfree(adapter->shadow_vfta); 3596 free_netdev(netdev); 3597 3598 pci_disable_pcie_error_reporting(pdev); 3599 3600 pci_disable_device(pdev); 3601 } 3602 3603 /** 3604 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3605 * @adapter: board private structure to initialize 3606 * 3607 * This function initializes the vf specific data storage and then attempts to 3608 * allocate the VFs. The reason for ordering it this way is because it is much 3609 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3610 * the memory for the VFs. 3611 **/ 3612 static void igb_probe_vfs(struct igb_adapter *adapter) 3613 { 3614 #ifdef CONFIG_PCI_IOV 3615 struct pci_dev *pdev = adapter->pdev; 3616 struct e1000_hw *hw = &adapter->hw; 3617 3618 /* Virtualization features not supported on i210 family. */ 3619 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3620 return; 3621 3622 /* Of the below we really only want the effect of getting 3623 * IGB_FLAG_HAS_MSIX set (if available), without which 3624 * igb_enable_sriov() has no effect. 3625 */ 3626 igb_set_interrupt_capability(adapter, true); 3627 igb_reset_interrupt_capability(adapter); 3628 3629 pci_sriov_set_totalvfs(pdev, 7); 3630 igb_enable_sriov(pdev, max_vfs); 3631 3632 #endif /* CONFIG_PCI_IOV */ 3633 } 3634 3635 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3636 { 3637 struct e1000_hw *hw = &adapter->hw; 3638 unsigned int max_rss_queues; 3639 3640 /* Determine the maximum number of RSS queues supported. */ 3641 switch (hw->mac.type) { 3642 case e1000_i211: 3643 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3644 break; 3645 case e1000_82575: 3646 case e1000_i210: 3647 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3648 break; 3649 case e1000_i350: 3650 /* I350 cannot do RSS and SR-IOV at the same time */ 3651 if (!!adapter->vfs_allocated_count) { 3652 max_rss_queues = 1; 3653 break; 3654 } 3655 /* fall through */ 3656 case e1000_82576: 3657 if (!!adapter->vfs_allocated_count) { 3658 max_rss_queues = 2; 3659 break; 3660 } 3661 /* fall through */ 3662 case e1000_82580: 3663 case e1000_i354: 3664 default: 3665 max_rss_queues = IGB_MAX_RX_QUEUES; 3666 break; 3667 } 3668 3669 return max_rss_queues; 3670 } 3671 3672 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3673 { 3674 u32 max_rss_queues; 3675 3676 max_rss_queues = igb_get_max_rss_queues(adapter); 3677 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3678 3679 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3680 } 3681 3682 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3683 const u32 max_rss_queues) 3684 { 3685 struct e1000_hw *hw = &adapter->hw; 3686 3687 /* Determine if we need to pair queues. */ 3688 switch (hw->mac.type) { 3689 case e1000_82575: 3690 case e1000_i211: 3691 /* Device supports enough interrupts without queue pairing. */ 3692 break; 3693 case e1000_82576: 3694 case e1000_82580: 3695 case e1000_i350: 3696 case e1000_i354: 3697 case e1000_i210: 3698 default: 3699 /* If rss_queues > half of max_rss_queues, pair the queues in 3700 * order to conserve interrupts due to limited supply. 3701 */ 3702 if (adapter->rss_queues > (max_rss_queues / 2)) 3703 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3704 else 3705 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3706 break; 3707 } 3708 } 3709 3710 /** 3711 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3712 * @adapter: board private structure to initialize 3713 * 3714 * igb_sw_init initializes the Adapter private data structure. 3715 * Fields are initialized based on PCI device information and 3716 * OS network device settings (MTU size). 3717 **/ 3718 static int igb_sw_init(struct igb_adapter *adapter) 3719 { 3720 struct e1000_hw *hw = &adapter->hw; 3721 struct net_device *netdev = adapter->netdev; 3722 struct pci_dev *pdev = adapter->pdev; 3723 3724 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3725 3726 /* set default ring sizes */ 3727 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3728 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3729 3730 /* set default ITR values */ 3731 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3732 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3733 3734 /* set default work limits */ 3735 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3736 3737 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3738 VLAN_HLEN; 3739 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3740 3741 spin_lock_init(&adapter->nfc_lock); 3742 spin_lock_init(&adapter->stats64_lock); 3743 #ifdef CONFIG_PCI_IOV 3744 switch (hw->mac.type) { 3745 case e1000_82576: 3746 case e1000_i350: 3747 if (max_vfs > 7) { 3748 dev_warn(&pdev->dev, 3749 "Maximum of 7 VFs per PF, using max\n"); 3750 max_vfs = adapter->vfs_allocated_count = 7; 3751 } else 3752 adapter->vfs_allocated_count = max_vfs; 3753 if (adapter->vfs_allocated_count) 3754 dev_warn(&pdev->dev, 3755 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3756 break; 3757 default: 3758 break; 3759 } 3760 #endif /* CONFIG_PCI_IOV */ 3761 3762 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3763 adapter->flags |= IGB_FLAG_HAS_MSIX; 3764 3765 adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) * 3766 hw->mac.rar_entry_count, GFP_ATOMIC); 3767 if (!adapter->mac_table) 3768 return -ENOMEM; 3769 3770 igb_probe_vfs(adapter); 3771 3772 igb_init_queue_configuration(adapter); 3773 3774 /* Setup and initialize a copy of the hw vlan table array */ 3775 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3776 GFP_ATOMIC); 3777 if (!adapter->shadow_vfta) 3778 return -ENOMEM; 3779 3780 /* This call may decrease the number of queues */ 3781 if (igb_init_interrupt_scheme(adapter, true)) { 3782 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3783 return -ENOMEM; 3784 } 3785 3786 /* Explicitly disable IRQ since the NIC can be in any state. */ 3787 igb_irq_disable(adapter); 3788 3789 if (hw->mac.type >= e1000_i350) 3790 adapter->flags &= ~IGB_FLAG_DMAC; 3791 3792 set_bit(__IGB_DOWN, &adapter->state); 3793 return 0; 3794 } 3795 3796 /** 3797 * igb_open - Called when a network interface is made active 3798 * @netdev: network interface device structure 3799 * 3800 * Returns 0 on success, negative value on failure 3801 * 3802 * The open entry point is called when a network interface is made 3803 * active by the system (IFF_UP). At this point all resources needed 3804 * for transmit and receive operations are allocated, the interrupt 3805 * handler is registered with the OS, the watchdog timer is started, 3806 * and the stack is notified that the interface is ready. 3807 **/ 3808 static int __igb_open(struct net_device *netdev, bool resuming) 3809 { 3810 struct igb_adapter *adapter = netdev_priv(netdev); 3811 struct e1000_hw *hw = &adapter->hw; 3812 struct pci_dev *pdev = adapter->pdev; 3813 int err; 3814 int i; 3815 3816 /* disallow open during test */ 3817 if (test_bit(__IGB_TESTING, &adapter->state)) { 3818 WARN_ON(resuming); 3819 return -EBUSY; 3820 } 3821 3822 if (!resuming) 3823 pm_runtime_get_sync(&pdev->dev); 3824 3825 netif_carrier_off(netdev); 3826 3827 /* allocate transmit descriptors */ 3828 err = igb_setup_all_tx_resources(adapter); 3829 if (err) 3830 goto err_setup_tx; 3831 3832 /* allocate receive descriptors */ 3833 err = igb_setup_all_rx_resources(adapter); 3834 if (err) 3835 goto err_setup_rx; 3836 3837 igb_power_up_link(adapter); 3838 3839 /* before we allocate an interrupt, we must be ready to handle it. 3840 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3841 * as soon as we call pci_request_irq, so we have to setup our 3842 * clean_rx handler before we do so. 3843 */ 3844 igb_configure(adapter); 3845 3846 err = igb_request_irq(adapter); 3847 if (err) 3848 goto err_req_irq; 3849 3850 /* Notify the stack of the actual queue counts. */ 3851 err = netif_set_real_num_tx_queues(adapter->netdev, 3852 adapter->num_tx_queues); 3853 if (err) 3854 goto err_set_queues; 3855 3856 err = netif_set_real_num_rx_queues(adapter->netdev, 3857 adapter->num_rx_queues); 3858 if (err) 3859 goto err_set_queues; 3860 3861 /* From here on the code is the same as igb_up() */ 3862 clear_bit(__IGB_DOWN, &adapter->state); 3863 3864 for (i = 0; i < adapter->num_q_vectors; i++) 3865 napi_enable(&(adapter->q_vector[i]->napi)); 3866 3867 /* Clear any pending interrupts. */ 3868 rd32(E1000_ICR); 3869 3870 igb_irq_enable(adapter); 3871 3872 /* notify VFs that reset has been completed */ 3873 if (adapter->vfs_allocated_count) { 3874 u32 reg_data = rd32(E1000_CTRL_EXT); 3875 3876 reg_data |= E1000_CTRL_EXT_PFRSTD; 3877 wr32(E1000_CTRL_EXT, reg_data); 3878 } 3879 3880 netif_tx_start_all_queues(netdev); 3881 3882 if (!resuming) 3883 pm_runtime_put(&pdev->dev); 3884 3885 /* start the watchdog. */ 3886 hw->mac.get_link_status = 1; 3887 schedule_work(&adapter->watchdog_task); 3888 3889 return 0; 3890 3891 err_set_queues: 3892 igb_free_irq(adapter); 3893 err_req_irq: 3894 igb_release_hw_control(adapter); 3895 igb_power_down_link(adapter); 3896 igb_free_all_rx_resources(adapter); 3897 err_setup_rx: 3898 igb_free_all_tx_resources(adapter); 3899 err_setup_tx: 3900 igb_reset(adapter); 3901 if (!resuming) 3902 pm_runtime_put(&pdev->dev); 3903 3904 return err; 3905 } 3906 3907 int igb_open(struct net_device *netdev) 3908 { 3909 return __igb_open(netdev, false); 3910 } 3911 3912 /** 3913 * igb_close - Disables a network interface 3914 * @netdev: network interface device structure 3915 * 3916 * Returns 0, this is not allowed to fail 3917 * 3918 * The close entry point is called when an interface is de-activated 3919 * by the OS. The hardware is still under the driver's control, but 3920 * needs to be disabled. A global MAC reset is issued to stop the 3921 * hardware, and all transmit and receive resources are freed. 3922 **/ 3923 static int __igb_close(struct net_device *netdev, bool suspending) 3924 { 3925 struct igb_adapter *adapter = netdev_priv(netdev); 3926 struct pci_dev *pdev = adapter->pdev; 3927 3928 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3929 3930 if (!suspending) 3931 pm_runtime_get_sync(&pdev->dev); 3932 3933 igb_down(adapter); 3934 igb_free_irq(adapter); 3935 3936 igb_free_all_tx_resources(adapter); 3937 igb_free_all_rx_resources(adapter); 3938 3939 if (!suspending) 3940 pm_runtime_put_sync(&pdev->dev); 3941 return 0; 3942 } 3943 3944 int igb_close(struct net_device *netdev) 3945 { 3946 if (netif_device_present(netdev) || netdev->dismantle) 3947 return __igb_close(netdev, false); 3948 return 0; 3949 } 3950 3951 /** 3952 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3953 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3954 * 3955 * Return 0 on success, negative on failure 3956 **/ 3957 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3958 { 3959 struct device *dev = tx_ring->dev; 3960 int size; 3961 3962 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3963 3964 tx_ring->tx_buffer_info = vmalloc(size); 3965 if (!tx_ring->tx_buffer_info) 3966 goto err; 3967 3968 /* round up to nearest 4K */ 3969 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3970 tx_ring->size = ALIGN(tx_ring->size, 4096); 3971 3972 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3973 &tx_ring->dma, GFP_KERNEL); 3974 if (!tx_ring->desc) 3975 goto err; 3976 3977 tx_ring->next_to_use = 0; 3978 tx_ring->next_to_clean = 0; 3979 3980 return 0; 3981 3982 err: 3983 vfree(tx_ring->tx_buffer_info); 3984 tx_ring->tx_buffer_info = NULL; 3985 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3986 return -ENOMEM; 3987 } 3988 3989 /** 3990 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3991 * (Descriptors) for all queues 3992 * @adapter: board private structure 3993 * 3994 * Return 0 on success, negative on failure 3995 **/ 3996 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3997 { 3998 struct pci_dev *pdev = adapter->pdev; 3999 int i, err = 0; 4000 4001 for (i = 0; i < adapter->num_tx_queues; i++) { 4002 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4003 if (err) { 4004 dev_err(&pdev->dev, 4005 "Allocation for Tx Queue %u failed\n", i); 4006 for (i--; i >= 0; i--) 4007 igb_free_tx_resources(adapter->tx_ring[i]); 4008 break; 4009 } 4010 } 4011 4012 return err; 4013 } 4014 4015 /** 4016 * igb_setup_tctl - configure the transmit control registers 4017 * @adapter: Board private structure 4018 **/ 4019 void igb_setup_tctl(struct igb_adapter *adapter) 4020 { 4021 struct e1000_hw *hw = &adapter->hw; 4022 u32 tctl; 4023 4024 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4025 wr32(E1000_TXDCTL(0), 0); 4026 4027 /* Program the Transmit Control Register */ 4028 tctl = rd32(E1000_TCTL); 4029 tctl &= ~E1000_TCTL_CT; 4030 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4031 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4032 4033 igb_config_collision_dist(hw); 4034 4035 /* Enable transmits */ 4036 tctl |= E1000_TCTL_EN; 4037 4038 wr32(E1000_TCTL, tctl); 4039 } 4040 4041 /** 4042 * igb_configure_tx_ring - Configure transmit ring after Reset 4043 * @adapter: board private structure 4044 * @ring: tx ring to configure 4045 * 4046 * Configure a transmit ring after a reset. 4047 **/ 4048 void igb_configure_tx_ring(struct igb_adapter *adapter, 4049 struct igb_ring *ring) 4050 { 4051 struct e1000_hw *hw = &adapter->hw; 4052 u32 txdctl = 0; 4053 u64 tdba = ring->dma; 4054 int reg_idx = ring->reg_idx; 4055 4056 /* disable the queue */ 4057 wr32(E1000_TXDCTL(reg_idx), 0); 4058 wrfl(); 4059 mdelay(10); 4060 4061 wr32(E1000_TDLEN(reg_idx), 4062 ring->count * sizeof(union e1000_adv_tx_desc)); 4063 wr32(E1000_TDBAL(reg_idx), 4064 tdba & 0x00000000ffffffffULL); 4065 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4066 4067 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4068 wr32(E1000_TDH(reg_idx), 0); 4069 writel(0, ring->tail); 4070 4071 txdctl |= IGB_TX_PTHRESH; 4072 txdctl |= IGB_TX_HTHRESH << 8; 4073 txdctl |= IGB_TX_WTHRESH << 16; 4074 4075 /* reinitialize tx_buffer_info */ 4076 memset(ring->tx_buffer_info, 0, 4077 sizeof(struct igb_tx_buffer) * ring->count); 4078 4079 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4080 wr32(E1000_TXDCTL(reg_idx), txdctl); 4081 } 4082 4083 /** 4084 * igb_configure_tx - Configure transmit Unit after Reset 4085 * @adapter: board private structure 4086 * 4087 * Configure the Tx unit of the MAC after a reset. 4088 **/ 4089 static void igb_configure_tx(struct igb_adapter *adapter) 4090 { 4091 int i; 4092 4093 for (i = 0; i < adapter->num_tx_queues; i++) 4094 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4095 } 4096 4097 /** 4098 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4099 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4100 * 4101 * Returns 0 on success, negative on failure 4102 **/ 4103 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4104 { 4105 struct device *dev = rx_ring->dev; 4106 int size; 4107 4108 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4109 4110 rx_ring->rx_buffer_info = vmalloc(size); 4111 if (!rx_ring->rx_buffer_info) 4112 goto err; 4113 4114 /* Round up to nearest 4K */ 4115 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4116 rx_ring->size = ALIGN(rx_ring->size, 4096); 4117 4118 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4119 &rx_ring->dma, GFP_KERNEL); 4120 if (!rx_ring->desc) 4121 goto err; 4122 4123 rx_ring->next_to_alloc = 0; 4124 rx_ring->next_to_clean = 0; 4125 rx_ring->next_to_use = 0; 4126 4127 return 0; 4128 4129 err: 4130 vfree(rx_ring->rx_buffer_info); 4131 rx_ring->rx_buffer_info = NULL; 4132 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4133 return -ENOMEM; 4134 } 4135 4136 /** 4137 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4138 * (Descriptors) for all queues 4139 * @adapter: board private structure 4140 * 4141 * Return 0 on success, negative on failure 4142 **/ 4143 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4144 { 4145 struct pci_dev *pdev = adapter->pdev; 4146 int i, err = 0; 4147 4148 for (i = 0; i < adapter->num_rx_queues; i++) { 4149 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4150 if (err) { 4151 dev_err(&pdev->dev, 4152 "Allocation for Rx Queue %u failed\n", i); 4153 for (i--; i >= 0; i--) 4154 igb_free_rx_resources(adapter->rx_ring[i]); 4155 break; 4156 } 4157 } 4158 4159 return err; 4160 } 4161 4162 /** 4163 * igb_setup_mrqc - configure the multiple receive queue control registers 4164 * @adapter: Board private structure 4165 **/ 4166 static void igb_setup_mrqc(struct igb_adapter *adapter) 4167 { 4168 struct e1000_hw *hw = &adapter->hw; 4169 u32 mrqc, rxcsum; 4170 u32 j, num_rx_queues; 4171 u32 rss_key[10]; 4172 4173 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4174 for (j = 0; j < 10; j++) 4175 wr32(E1000_RSSRK(j), rss_key[j]); 4176 4177 num_rx_queues = adapter->rss_queues; 4178 4179 switch (hw->mac.type) { 4180 case e1000_82576: 4181 /* 82576 supports 2 RSS queues for SR-IOV */ 4182 if (adapter->vfs_allocated_count) 4183 num_rx_queues = 2; 4184 break; 4185 default: 4186 break; 4187 } 4188 4189 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4190 for (j = 0; j < IGB_RETA_SIZE; j++) 4191 adapter->rss_indir_tbl[j] = 4192 (j * num_rx_queues) / IGB_RETA_SIZE; 4193 adapter->rss_indir_tbl_init = num_rx_queues; 4194 } 4195 igb_write_rss_indir_tbl(adapter); 4196 4197 /* Disable raw packet checksumming so that RSS hash is placed in 4198 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4199 * offloads as they are enabled by default 4200 */ 4201 rxcsum = rd32(E1000_RXCSUM); 4202 rxcsum |= E1000_RXCSUM_PCSD; 4203 4204 if (adapter->hw.mac.type >= e1000_82576) 4205 /* Enable Receive Checksum Offload for SCTP */ 4206 rxcsum |= E1000_RXCSUM_CRCOFL; 4207 4208 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4209 wr32(E1000_RXCSUM, rxcsum); 4210 4211 /* Generate RSS hash based on packet types, TCP/UDP 4212 * port numbers and/or IPv4/v6 src and dst addresses 4213 */ 4214 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4215 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4216 E1000_MRQC_RSS_FIELD_IPV6 | 4217 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4218 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4219 4220 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4221 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4222 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4223 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4224 4225 /* If VMDq is enabled then we set the appropriate mode for that, else 4226 * we default to RSS so that an RSS hash is calculated per packet even 4227 * if we are only using one queue 4228 */ 4229 if (adapter->vfs_allocated_count) { 4230 if (hw->mac.type > e1000_82575) { 4231 /* Set the default pool for the PF's first queue */ 4232 u32 vtctl = rd32(E1000_VT_CTL); 4233 4234 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4235 E1000_VT_CTL_DISABLE_DEF_POOL); 4236 vtctl |= adapter->vfs_allocated_count << 4237 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4238 wr32(E1000_VT_CTL, vtctl); 4239 } 4240 if (adapter->rss_queues > 1) 4241 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4242 else 4243 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4244 } else { 4245 if (hw->mac.type != e1000_i211) 4246 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4247 } 4248 igb_vmm_control(adapter); 4249 4250 wr32(E1000_MRQC, mrqc); 4251 } 4252 4253 /** 4254 * igb_setup_rctl - configure the receive control registers 4255 * @adapter: Board private structure 4256 **/ 4257 void igb_setup_rctl(struct igb_adapter *adapter) 4258 { 4259 struct e1000_hw *hw = &adapter->hw; 4260 u32 rctl; 4261 4262 rctl = rd32(E1000_RCTL); 4263 4264 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4265 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4266 4267 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4268 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4269 4270 /* enable stripping of CRC. It's unlikely this will break BMC 4271 * redirection as it did with e1000. Newer features require 4272 * that the HW strips the CRC. 4273 */ 4274 rctl |= E1000_RCTL_SECRC; 4275 4276 /* disable store bad packets and clear size bits. */ 4277 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4278 4279 /* enable LPE to allow for reception of jumbo frames */ 4280 rctl |= E1000_RCTL_LPE; 4281 4282 /* disable queue 0 to prevent tail write w/o re-config */ 4283 wr32(E1000_RXDCTL(0), 0); 4284 4285 /* Attention!!! For SR-IOV PF driver operations you must enable 4286 * queue drop for all VF and PF queues to prevent head of line blocking 4287 * if an un-trusted VF does not provide descriptors to hardware. 4288 */ 4289 if (adapter->vfs_allocated_count) { 4290 /* set all queue drop enable bits */ 4291 wr32(E1000_QDE, ALL_QUEUES); 4292 } 4293 4294 /* This is useful for sniffing bad packets. */ 4295 if (adapter->netdev->features & NETIF_F_RXALL) { 4296 /* UPE and MPE will be handled by normal PROMISC logic 4297 * in e1000e_set_rx_mode 4298 */ 4299 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4300 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4301 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4302 4303 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4304 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4305 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4306 * and that breaks VLANs. 4307 */ 4308 } 4309 4310 wr32(E1000_RCTL, rctl); 4311 } 4312 4313 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4314 int vfn) 4315 { 4316 struct e1000_hw *hw = &adapter->hw; 4317 u32 vmolr; 4318 4319 if (size > MAX_JUMBO_FRAME_SIZE) 4320 size = MAX_JUMBO_FRAME_SIZE; 4321 4322 vmolr = rd32(E1000_VMOLR(vfn)); 4323 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4324 vmolr |= size | E1000_VMOLR_LPE; 4325 wr32(E1000_VMOLR(vfn), vmolr); 4326 4327 return 0; 4328 } 4329 4330 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4331 int vfn, bool enable) 4332 { 4333 struct e1000_hw *hw = &adapter->hw; 4334 u32 val, reg; 4335 4336 if (hw->mac.type < e1000_82576) 4337 return; 4338 4339 if (hw->mac.type == e1000_i350) 4340 reg = E1000_DVMOLR(vfn); 4341 else 4342 reg = E1000_VMOLR(vfn); 4343 4344 val = rd32(reg); 4345 if (enable) 4346 val |= E1000_VMOLR_STRVLAN; 4347 else 4348 val &= ~(E1000_VMOLR_STRVLAN); 4349 wr32(reg, val); 4350 } 4351 4352 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4353 int vfn, bool aupe) 4354 { 4355 struct e1000_hw *hw = &adapter->hw; 4356 u32 vmolr; 4357 4358 /* This register exists only on 82576 and newer so if we are older then 4359 * we should exit and do nothing 4360 */ 4361 if (hw->mac.type < e1000_82576) 4362 return; 4363 4364 vmolr = rd32(E1000_VMOLR(vfn)); 4365 if (aupe) 4366 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4367 else 4368 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4369 4370 /* clear all bits that might not be set */ 4371 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4372 4373 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4374 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4375 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4376 * multicast packets 4377 */ 4378 if (vfn <= adapter->vfs_allocated_count) 4379 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4380 4381 wr32(E1000_VMOLR(vfn), vmolr); 4382 } 4383 4384 /** 4385 * igb_configure_rx_ring - Configure a receive ring after Reset 4386 * @adapter: board private structure 4387 * @ring: receive ring to be configured 4388 * 4389 * Configure the Rx unit of the MAC after a reset. 4390 **/ 4391 void igb_configure_rx_ring(struct igb_adapter *adapter, 4392 struct igb_ring *ring) 4393 { 4394 struct e1000_hw *hw = &adapter->hw; 4395 union e1000_adv_rx_desc *rx_desc; 4396 u64 rdba = ring->dma; 4397 int reg_idx = ring->reg_idx; 4398 u32 srrctl = 0, rxdctl = 0; 4399 4400 /* disable the queue */ 4401 wr32(E1000_RXDCTL(reg_idx), 0); 4402 4403 /* Set DMA base address registers */ 4404 wr32(E1000_RDBAL(reg_idx), 4405 rdba & 0x00000000ffffffffULL); 4406 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4407 wr32(E1000_RDLEN(reg_idx), 4408 ring->count * sizeof(union e1000_adv_rx_desc)); 4409 4410 /* initialize head and tail */ 4411 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4412 wr32(E1000_RDH(reg_idx), 0); 4413 writel(0, ring->tail); 4414 4415 /* set descriptor configuration */ 4416 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4417 if (ring_uses_large_buffer(ring)) 4418 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4419 else 4420 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4421 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4422 if (hw->mac.type >= e1000_82580) 4423 srrctl |= E1000_SRRCTL_TIMESTAMP; 4424 /* Only set Drop Enable if we are supporting multiple queues */ 4425 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 4426 srrctl |= E1000_SRRCTL_DROP_EN; 4427 4428 wr32(E1000_SRRCTL(reg_idx), srrctl); 4429 4430 /* set filtering for VMDQ pools */ 4431 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4432 4433 rxdctl |= IGB_RX_PTHRESH; 4434 rxdctl |= IGB_RX_HTHRESH << 8; 4435 rxdctl |= IGB_RX_WTHRESH << 16; 4436 4437 /* initialize rx_buffer_info */ 4438 memset(ring->rx_buffer_info, 0, 4439 sizeof(struct igb_rx_buffer) * ring->count); 4440 4441 /* initialize Rx descriptor 0 */ 4442 rx_desc = IGB_RX_DESC(ring, 0); 4443 rx_desc->wb.upper.length = 0; 4444 4445 /* enable receive descriptor fetching */ 4446 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4447 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4448 } 4449 4450 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4451 struct igb_ring *rx_ring) 4452 { 4453 /* set build_skb and buffer size flags */ 4454 clear_ring_build_skb_enabled(rx_ring); 4455 clear_ring_uses_large_buffer(rx_ring); 4456 4457 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4458 return; 4459 4460 set_ring_build_skb_enabled(rx_ring); 4461 4462 #if (PAGE_SIZE < 8192) 4463 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4464 return; 4465 4466 set_ring_uses_large_buffer(rx_ring); 4467 #endif 4468 } 4469 4470 /** 4471 * igb_configure_rx - Configure receive Unit after Reset 4472 * @adapter: board private structure 4473 * 4474 * Configure the Rx unit of the MAC after a reset. 4475 **/ 4476 static void igb_configure_rx(struct igb_adapter *adapter) 4477 { 4478 int i; 4479 4480 /* set the correct pool for the PF default MAC address in entry 0 */ 4481 igb_set_default_mac_filter(adapter); 4482 4483 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4484 * the Base and Length of the Rx Descriptor Ring 4485 */ 4486 for (i = 0; i < adapter->num_rx_queues; i++) { 4487 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4488 4489 igb_set_rx_buffer_len(adapter, rx_ring); 4490 igb_configure_rx_ring(adapter, rx_ring); 4491 } 4492 } 4493 4494 /** 4495 * igb_free_tx_resources - Free Tx Resources per Queue 4496 * @tx_ring: Tx descriptor ring for a specific queue 4497 * 4498 * Free all transmit software resources 4499 **/ 4500 void igb_free_tx_resources(struct igb_ring *tx_ring) 4501 { 4502 igb_clean_tx_ring(tx_ring); 4503 4504 vfree(tx_ring->tx_buffer_info); 4505 tx_ring->tx_buffer_info = NULL; 4506 4507 /* if not set, then don't free */ 4508 if (!tx_ring->desc) 4509 return; 4510 4511 dma_free_coherent(tx_ring->dev, tx_ring->size, 4512 tx_ring->desc, tx_ring->dma); 4513 4514 tx_ring->desc = NULL; 4515 } 4516 4517 /** 4518 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4519 * @adapter: board private structure 4520 * 4521 * Free all transmit software resources 4522 **/ 4523 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4524 { 4525 int i; 4526 4527 for (i = 0; i < adapter->num_tx_queues; i++) 4528 if (adapter->tx_ring[i]) 4529 igb_free_tx_resources(adapter->tx_ring[i]); 4530 } 4531 4532 /** 4533 * igb_clean_tx_ring - Free Tx Buffers 4534 * @tx_ring: ring to be cleaned 4535 **/ 4536 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4537 { 4538 u16 i = tx_ring->next_to_clean; 4539 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4540 4541 while (i != tx_ring->next_to_use) { 4542 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4543 4544 /* Free all the Tx ring sk_buffs */ 4545 dev_kfree_skb_any(tx_buffer->skb); 4546 4547 /* unmap skb header data */ 4548 dma_unmap_single(tx_ring->dev, 4549 dma_unmap_addr(tx_buffer, dma), 4550 dma_unmap_len(tx_buffer, len), 4551 DMA_TO_DEVICE); 4552 4553 /* check for eop_desc to determine the end of the packet */ 4554 eop_desc = tx_buffer->next_to_watch; 4555 tx_desc = IGB_TX_DESC(tx_ring, i); 4556 4557 /* unmap remaining buffers */ 4558 while (tx_desc != eop_desc) { 4559 tx_buffer++; 4560 tx_desc++; 4561 i++; 4562 if (unlikely(i == tx_ring->count)) { 4563 i = 0; 4564 tx_buffer = tx_ring->tx_buffer_info; 4565 tx_desc = IGB_TX_DESC(tx_ring, 0); 4566 } 4567 4568 /* unmap any remaining paged data */ 4569 if (dma_unmap_len(tx_buffer, len)) 4570 dma_unmap_page(tx_ring->dev, 4571 dma_unmap_addr(tx_buffer, dma), 4572 dma_unmap_len(tx_buffer, len), 4573 DMA_TO_DEVICE); 4574 } 4575 4576 /* move us one more past the eop_desc for start of next pkt */ 4577 tx_buffer++; 4578 i++; 4579 if (unlikely(i == tx_ring->count)) { 4580 i = 0; 4581 tx_buffer = tx_ring->tx_buffer_info; 4582 } 4583 } 4584 4585 /* reset BQL for queue */ 4586 netdev_tx_reset_queue(txring_txq(tx_ring)); 4587 4588 /* reset next_to_use and next_to_clean */ 4589 tx_ring->next_to_use = 0; 4590 tx_ring->next_to_clean = 0; 4591 } 4592 4593 /** 4594 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4595 * @adapter: board private structure 4596 **/ 4597 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4598 { 4599 int i; 4600 4601 for (i = 0; i < adapter->num_tx_queues; i++) 4602 if (adapter->tx_ring[i]) 4603 igb_clean_tx_ring(adapter->tx_ring[i]); 4604 } 4605 4606 /** 4607 * igb_free_rx_resources - Free Rx Resources 4608 * @rx_ring: ring to clean the resources from 4609 * 4610 * Free all receive software resources 4611 **/ 4612 void igb_free_rx_resources(struct igb_ring *rx_ring) 4613 { 4614 igb_clean_rx_ring(rx_ring); 4615 4616 vfree(rx_ring->rx_buffer_info); 4617 rx_ring->rx_buffer_info = NULL; 4618 4619 /* if not set, then don't free */ 4620 if (!rx_ring->desc) 4621 return; 4622 4623 dma_free_coherent(rx_ring->dev, rx_ring->size, 4624 rx_ring->desc, rx_ring->dma); 4625 4626 rx_ring->desc = NULL; 4627 } 4628 4629 /** 4630 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4631 * @adapter: board private structure 4632 * 4633 * Free all receive software resources 4634 **/ 4635 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4636 { 4637 int i; 4638 4639 for (i = 0; i < adapter->num_rx_queues; i++) 4640 if (adapter->rx_ring[i]) 4641 igb_free_rx_resources(adapter->rx_ring[i]); 4642 } 4643 4644 /** 4645 * igb_clean_rx_ring - Free Rx Buffers per Queue 4646 * @rx_ring: ring to free buffers from 4647 **/ 4648 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4649 { 4650 u16 i = rx_ring->next_to_clean; 4651 4652 if (rx_ring->skb) 4653 dev_kfree_skb(rx_ring->skb); 4654 rx_ring->skb = NULL; 4655 4656 /* Free all the Rx ring sk_buffs */ 4657 while (i != rx_ring->next_to_alloc) { 4658 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4659 4660 /* Invalidate cache lines that may have been written to by 4661 * device so that we avoid corrupting memory. 4662 */ 4663 dma_sync_single_range_for_cpu(rx_ring->dev, 4664 buffer_info->dma, 4665 buffer_info->page_offset, 4666 igb_rx_bufsz(rx_ring), 4667 DMA_FROM_DEVICE); 4668 4669 /* free resources associated with mapping */ 4670 dma_unmap_page_attrs(rx_ring->dev, 4671 buffer_info->dma, 4672 igb_rx_pg_size(rx_ring), 4673 DMA_FROM_DEVICE, 4674 IGB_RX_DMA_ATTR); 4675 __page_frag_cache_drain(buffer_info->page, 4676 buffer_info->pagecnt_bias); 4677 4678 i++; 4679 if (i == rx_ring->count) 4680 i = 0; 4681 } 4682 4683 rx_ring->next_to_alloc = 0; 4684 rx_ring->next_to_clean = 0; 4685 rx_ring->next_to_use = 0; 4686 } 4687 4688 /** 4689 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4690 * @adapter: board private structure 4691 **/ 4692 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4693 { 4694 int i; 4695 4696 for (i = 0; i < adapter->num_rx_queues; i++) 4697 if (adapter->rx_ring[i]) 4698 igb_clean_rx_ring(adapter->rx_ring[i]); 4699 } 4700 4701 /** 4702 * igb_set_mac - Change the Ethernet Address of the NIC 4703 * @netdev: network interface device structure 4704 * @p: pointer to an address structure 4705 * 4706 * Returns 0 on success, negative on failure 4707 **/ 4708 static int igb_set_mac(struct net_device *netdev, void *p) 4709 { 4710 struct igb_adapter *adapter = netdev_priv(netdev); 4711 struct e1000_hw *hw = &adapter->hw; 4712 struct sockaddr *addr = p; 4713 4714 if (!is_valid_ether_addr(addr->sa_data)) 4715 return -EADDRNOTAVAIL; 4716 4717 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4718 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4719 4720 /* set the correct pool for the new PF MAC address in entry 0 */ 4721 igb_set_default_mac_filter(adapter); 4722 4723 return 0; 4724 } 4725 4726 /** 4727 * igb_write_mc_addr_list - write multicast addresses to MTA 4728 * @netdev: network interface device structure 4729 * 4730 * Writes multicast address list to the MTA hash table. 4731 * Returns: -ENOMEM on failure 4732 * 0 on no addresses written 4733 * X on writing X addresses to MTA 4734 **/ 4735 static int igb_write_mc_addr_list(struct net_device *netdev) 4736 { 4737 struct igb_adapter *adapter = netdev_priv(netdev); 4738 struct e1000_hw *hw = &adapter->hw; 4739 struct netdev_hw_addr *ha; 4740 u8 *mta_list; 4741 int i; 4742 4743 if (netdev_mc_empty(netdev)) { 4744 /* nothing to program, so clear mc list */ 4745 igb_update_mc_addr_list(hw, NULL, 0); 4746 igb_restore_vf_multicasts(adapter); 4747 return 0; 4748 } 4749 4750 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4751 if (!mta_list) 4752 return -ENOMEM; 4753 4754 /* The shared function expects a packed array of only addresses. */ 4755 i = 0; 4756 netdev_for_each_mc_addr(ha, netdev) 4757 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4758 4759 igb_update_mc_addr_list(hw, mta_list, i); 4760 kfree(mta_list); 4761 4762 return netdev_mc_count(netdev); 4763 } 4764 4765 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4766 { 4767 struct e1000_hw *hw = &adapter->hw; 4768 u32 i, pf_id; 4769 4770 switch (hw->mac.type) { 4771 case e1000_i210: 4772 case e1000_i211: 4773 case e1000_i350: 4774 /* VLAN filtering needed for VLAN prio filter */ 4775 if (adapter->netdev->features & NETIF_F_NTUPLE) 4776 break; 4777 /* fall through */ 4778 case e1000_82576: 4779 case e1000_82580: 4780 case e1000_i354: 4781 /* VLAN filtering needed for pool filtering */ 4782 if (adapter->vfs_allocated_count) 4783 break; 4784 /* fall through */ 4785 default: 4786 return 1; 4787 } 4788 4789 /* We are already in VLAN promisc, nothing to do */ 4790 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4791 return 0; 4792 4793 if (!adapter->vfs_allocated_count) 4794 goto set_vfta; 4795 4796 /* Add PF to all active pools */ 4797 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4798 4799 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4800 u32 vlvf = rd32(E1000_VLVF(i)); 4801 4802 vlvf |= BIT(pf_id); 4803 wr32(E1000_VLVF(i), vlvf); 4804 } 4805 4806 set_vfta: 4807 /* Set all bits in the VLAN filter table array */ 4808 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4809 hw->mac.ops.write_vfta(hw, i, ~0U); 4810 4811 /* Set flag so we don't redo unnecessary work */ 4812 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4813 4814 return 0; 4815 } 4816 4817 #define VFTA_BLOCK_SIZE 8 4818 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4819 { 4820 struct e1000_hw *hw = &adapter->hw; 4821 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4822 u32 vid_start = vfta_offset * 32; 4823 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4824 u32 i, vid, word, bits, pf_id; 4825 4826 /* guarantee that we don't scrub out management VLAN */ 4827 vid = adapter->mng_vlan_id; 4828 if (vid >= vid_start && vid < vid_end) 4829 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4830 4831 if (!adapter->vfs_allocated_count) 4832 goto set_vfta; 4833 4834 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4835 4836 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4837 u32 vlvf = rd32(E1000_VLVF(i)); 4838 4839 /* pull VLAN ID from VLVF */ 4840 vid = vlvf & VLAN_VID_MASK; 4841 4842 /* only concern ourselves with a certain range */ 4843 if (vid < vid_start || vid >= vid_end) 4844 continue; 4845 4846 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4847 /* record VLAN ID in VFTA */ 4848 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4849 4850 /* if PF is part of this then continue */ 4851 if (test_bit(vid, adapter->active_vlans)) 4852 continue; 4853 } 4854 4855 /* remove PF from the pool */ 4856 bits = ~BIT(pf_id); 4857 bits &= rd32(E1000_VLVF(i)); 4858 wr32(E1000_VLVF(i), bits); 4859 } 4860 4861 set_vfta: 4862 /* extract values from active_vlans and write back to VFTA */ 4863 for (i = VFTA_BLOCK_SIZE; i--;) { 4864 vid = (vfta_offset + i) * 32; 4865 word = vid / BITS_PER_LONG; 4866 bits = vid % BITS_PER_LONG; 4867 4868 vfta[i] |= adapter->active_vlans[word] >> bits; 4869 4870 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4871 } 4872 } 4873 4874 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4875 { 4876 u32 i; 4877 4878 /* We are not in VLAN promisc, nothing to do */ 4879 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4880 return; 4881 4882 /* Set flag so we don't redo unnecessary work */ 4883 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4884 4885 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4886 igb_scrub_vfta(adapter, i); 4887 } 4888 4889 /** 4890 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4891 * @netdev: network interface device structure 4892 * 4893 * The set_rx_mode entry point is called whenever the unicast or multicast 4894 * address lists or the network interface flags are updated. This routine is 4895 * responsible for configuring the hardware for proper unicast, multicast, 4896 * promiscuous mode, and all-multi behavior. 4897 **/ 4898 static void igb_set_rx_mode(struct net_device *netdev) 4899 { 4900 struct igb_adapter *adapter = netdev_priv(netdev); 4901 struct e1000_hw *hw = &adapter->hw; 4902 unsigned int vfn = adapter->vfs_allocated_count; 4903 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4904 int count; 4905 4906 /* Check for Promiscuous and All Multicast modes */ 4907 if (netdev->flags & IFF_PROMISC) { 4908 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4909 vmolr |= E1000_VMOLR_MPME; 4910 4911 /* enable use of UTA filter to force packets to default pool */ 4912 if (hw->mac.type == e1000_82576) 4913 vmolr |= E1000_VMOLR_ROPE; 4914 } else { 4915 if (netdev->flags & IFF_ALLMULTI) { 4916 rctl |= E1000_RCTL_MPE; 4917 vmolr |= E1000_VMOLR_MPME; 4918 } else { 4919 /* Write addresses to the MTA, if the attempt fails 4920 * then we should just turn on promiscuous mode so 4921 * that we can at least receive multicast traffic 4922 */ 4923 count = igb_write_mc_addr_list(netdev); 4924 if (count < 0) { 4925 rctl |= E1000_RCTL_MPE; 4926 vmolr |= E1000_VMOLR_MPME; 4927 } else if (count) { 4928 vmolr |= E1000_VMOLR_ROMPE; 4929 } 4930 } 4931 } 4932 4933 /* Write addresses to available RAR registers, if there is not 4934 * sufficient space to store all the addresses then enable 4935 * unicast promiscuous mode 4936 */ 4937 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 4938 rctl |= E1000_RCTL_UPE; 4939 vmolr |= E1000_VMOLR_ROPE; 4940 } 4941 4942 /* enable VLAN filtering by default */ 4943 rctl |= E1000_RCTL_VFE; 4944 4945 /* disable VLAN filtering for modes that require it */ 4946 if ((netdev->flags & IFF_PROMISC) || 4947 (netdev->features & NETIF_F_RXALL)) { 4948 /* if we fail to set all rules then just clear VFE */ 4949 if (igb_vlan_promisc_enable(adapter)) 4950 rctl &= ~E1000_RCTL_VFE; 4951 } else { 4952 igb_vlan_promisc_disable(adapter); 4953 } 4954 4955 /* update state of unicast, multicast, and VLAN filtering modes */ 4956 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4957 E1000_RCTL_VFE); 4958 wr32(E1000_RCTL, rctl); 4959 4960 #if (PAGE_SIZE < 8192) 4961 if (!adapter->vfs_allocated_count) { 4962 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4963 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4964 } 4965 #endif 4966 wr32(E1000_RLPML, rlpml); 4967 4968 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4969 * the VMOLR to enable the appropriate modes. Without this workaround 4970 * we will have issues with VLAN tag stripping not being done for frames 4971 * that are only arriving because we are the default pool 4972 */ 4973 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4974 return; 4975 4976 /* set UTA to appropriate mode */ 4977 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4978 4979 vmolr |= rd32(E1000_VMOLR(vfn)) & 4980 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4981 4982 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4983 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4984 #if (PAGE_SIZE < 8192) 4985 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4986 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4987 else 4988 #endif 4989 vmolr |= MAX_JUMBO_FRAME_SIZE; 4990 vmolr |= E1000_VMOLR_LPE; 4991 4992 wr32(E1000_VMOLR(vfn), vmolr); 4993 4994 igb_restore_vf_multicasts(adapter); 4995 } 4996 4997 static void igb_check_wvbr(struct igb_adapter *adapter) 4998 { 4999 struct e1000_hw *hw = &adapter->hw; 5000 u32 wvbr = 0; 5001 5002 switch (hw->mac.type) { 5003 case e1000_82576: 5004 case e1000_i350: 5005 wvbr = rd32(E1000_WVBR); 5006 if (!wvbr) 5007 return; 5008 break; 5009 default: 5010 break; 5011 } 5012 5013 adapter->wvbr |= wvbr; 5014 } 5015 5016 #define IGB_STAGGERED_QUEUE_OFFSET 8 5017 5018 static void igb_spoof_check(struct igb_adapter *adapter) 5019 { 5020 int j; 5021 5022 if (!adapter->wvbr) 5023 return; 5024 5025 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5026 if (adapter->wvbr & BIT(j) || 5027 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5028 dev_warn(&adapter->pdev->dev, 5029 "Spoof event(s) detected on VF %d\n", j); 5030 adapter->wvbr &= 5031 ~(BIT(j) | 5032 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5033 } 5034 } 5035 } 5036 5037 /* Need to wait a few seconds after link up to get diagnostic information from 5038 * the phy 5039 */ 5040 static void igb_update_phy_info(struct timer_list *t) 5041 { 5042 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5043 igb_get_phy_info(&adapter->hw); 5044 } 5045 5046 /** 5047 * igb_has_link - check shared code for link and determine up/down 5048 * @adapter: pointer to driver private info 5049 **/ 5050 bool igb_has_link(struct igb_adapter *adapter) 5051 { 5052 struct e1000_hw *hw = &adapter->hw; 5053 bool link_active = false; 5054 5055 /* get_link_status is set on LSC (link status) interrupt or 5056 * rx sequence error interrupt. get_link_status will stay 5057 * false until the e1000_check_for_link establishes link 5058 * for copper adapters ONLY 5059 */ 5060 switch (hw->phy.media_type) { 5061 case e1000_media_type_copper: 5062 if (!hw->mac.get_link_status) 5063 return true; 5064 case e1000_media_type_internal_serdes: 5065 hw->mac.ops.check_for_link(hw); 5066 link_active = !hw->mac.get_link_status; 5067 break; 5068 default: 5069 case e1000_media_type_unknown: 5070 break; 5071 } 5072 5073 if (((hw->mac.type == e1000_i210) || 5074 (hw->mac.type == e1000_i211)) && 5075 (hw->phy.id == I210_I_PHY_ID)) { 5076 if (!netif_carrier_ok(adapter->netdev)) { 5077 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5078 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5079 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5080 adapter->link_check_timeout = jiffies; 5081 } 5082 } 5083 5084 return link_active; 5085 } 5086 5087 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5088 { 5089 bool ret = false; 5090 u32 ctrl_ext, thstat; 5091 5092 /* check for thermal sensor event on i350 copper only */ 5093 if (hw->mac.type == e1000_i350) { 5094 thstat = rd32(E1000_THSTAT); 5095 ctrl_ext = rd32(E1000_CTRL_EXT); 5096 5097 if ((hw->phy.media_type == e1000_media_type_copper) && 5098 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5099 ret = !!(thstat & event); 5100 } 5101 5102 return ret; 5103 } 5104 5105 /** 5106 * igb_check_lvmmc - check for malformed packets received 5107 * and indicated in LVMMC register 5108 * @adapter: pointer to adapter 5109 **/ 5110 static void igb_check_lvmmc(struct igb_adapter *adapter) 5111 { 5112 struct e1000_hw *hw = &adapter->hw; 5113 u32 lvmmc; 5114 5115 lvmmc = rd32(E1000_LVMMC); 5116 if (lvmmc) { 5117 if (unlikely(net_ratelimit())) { 5118 netdev_warn(adapter->netdev, 5119 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5120 lvmmc); 5121 } 5122 } 5123 } 5124 5125 /** 5126 * igb_watchdog - Timer Call-back 5127 * @data: pointer to adapter cast into an unsigned long 5128 **/ 5129 static void igb_watchdog(struct timer_list *t) 5130 { 5131 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5132 /* Do the rest outside of interrupt context */ 5133 schedule_work(&adapter->watchdog_task); 5134 } 5135 5136 static void igb_watchdog_task(struct work_struct *work) 5137 { 5138 struct igb_adapter *adapter = container_of(work, 5139 struct igb_adapter, 5140 watchdog_task); 5141 struct e1000_hw *hw = &adapter->hw; 5142 struct e1000_phy_info *phy = &hw->phy; 5143 struct net_device *netdev = adapter->netdev; 5144 u32 link; 5145 int i; 5146 u32 connsw; 5147 u16 phy_data, retry_count = 20; 5148 5149 link = igb_has_link(adapter); 5150 5151 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5152 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5153 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5154 else 5155 link = false; 5156 } 5157 5158 /* Force link down if we have fiber to swap to */ 5159 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5160 if (hw->phy.media_type == e1000_media_type_copper) { 5161 connsw = rd32(E1000_CONNSW); 5162 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5163 link = 0; 5164 } 5165 } 5166 if (link) { 5167 /* Perform a reset if the media type changed. */ 5168 if (hw->dev_spec._82575.media_changed) { 5169 hw->dev_spec._82575.media_changed = false; 5170 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5171 igb_reset(adapter); 5172 } 5173 /* Cancel scheduled suspend requests. */ 5174 pm_runtime_resume(netdev->dev.parent); 5175 5176 if (!netif_carrier_ok(netdev)) { 5177 u32 ctrl; 5178 5179 hw->mac.ops.get_speed_and_duplex(hw, 5180 &adapter->link_speed, 5181 &adapter->link_duplex); 5182 5183 ctrl = rd32(E1000_CTRL); 5184 /* Links status message must follow this format */ 5185 netdev_info(netdev, 5186 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5187 netdev->name, 5188 adapter->link_speed, 5189 adapter->link_duplex == FULL_DUPLEX ? 5190 "Full" : "Half", 5191 (ctrl & E1000_CTRL_TFCE) && 5192 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5193 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5194 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5195 5196 /* disable EEE if enabled */ 5197 if ((adapter->flags & IGB_FLAG_EEE) && 5198 (adapter->link_duplex == HALF_DUPLEX)) { 5199 dev_info(&adapter->pdev->dev, 5200 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5201 adapter->hw.dev_spec._82575.eee_disable = true; 5202 adapter->flags &= ~IGB_FLAG_EEE; 5203 } 5204 5205 /* check if SmartSpeed worked */ 5206 igb_check_downshift(hw); 5207 if (phy->speed_downgraded) 5208 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5209 5210 /* check for thermal sensor event */ 5211 if (igb_thermal_sensor_event(hw, 5212 E1000_THSTAT_LINK_THROTTLE)) 5213 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5214 5215 /* adjust timeout factor according to speed/duplex */ 5216 adapter->tx_timeout_factor = 1; 5217 switch (adapter->link_speed) { 5218 case SPEED_10: 5219 adapter->tx_timeout_factor = 14; 5220 break; 5221 case SPEED_100: 5222 /* maybe add some timeout factor ? */ 5223 break; 5224 } 5225 5226 if (adapter->link_speed != SPEED_1000) 5227 goto no_wait; 5228 5229 /* wait for Remote receiver status OK */ 5230 retry_read_status: 5231 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5232 &phy_data)) { 5233 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5234 retry_count) { 5235 msleep(100); 5236 retry_count--; 5237 goto retry_read_status; 5238 } else if (!retry_count) { 5239 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5240 } 5241 } else { 5242 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5243 } 5244 no_wait: 5245 netif_carrier_on(netdev); 5246 5247 igb_ping_all_vfs(adapter); 5248 igb_check_vf_rate_limit(adapter); 5249 5250 /* link state has changed, schedule phy info update */ 5251 if (!test_bit(__IGB_DOWN, &adapter->state)) 5252 mod_timer(&adapter->phy_info_timer, 5253 round_jiffies(jiffies + 2 * HZ)); 5254 } 5255 } else { 5256 if (netif_carrier_ok(netdev)) { 5257 adapter->link_speed = 0; 5258 adapter->link_duplex = 0; 5259 5260 /* check for thermal sensor event */ 5261 if (igb_thermal_sensor_event(hw, 5262 E1000_THSTAT_PWR_DOWN)) { 5263 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5264 } 5265 5266 /* Links status message must follow this format */ 5267 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5268 netdev->name); 5269 netif_carrier_off(netdev); 5270 5271 igb_ping_all_vfs(adapter); 5272 5273 /* link state has changed, schedule phy info update */ 5274 if (!test_bit(__IGB_DOWN, &adapter->state)) 5275 mod_timer(&adapter->phy_info_timer, 5276 round_jiffies(jiffies + 2 * HZ)); 5277 5278 /* link is down, time to check for alternate media */ 5279 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5280 igb_check_swap_media(adapter); 5281 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5282 schedule_work(&adapter->reset_task); 5283 /* return immediately */ 5284 return; 5285 } 5286 } 5287 pm_schedule_suspend(netdev->dev.parent, 5288 MSEC_PER_SEC * 5); 5289 5290 /* also check for alternate media here */ 5291 } else if (!netif_carrier_ok(netdev) && 5292 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5293 igb_check_swap_media(adapter); 5294 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5295 schedule_work(&adapter->reset_task); 5296 /* return immediately */ 5297 return; 5298 } 5299 } 5300 } 5301 5302 spin_lock(&adapter->stats64_lock); 5303 igb_update_stats(adapter); 5304 spin_unlock(&adapter->stats64_lock); 5305 5306 for (i = 0; i < adapter->num_tx_queues; i++) { 5307 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5308 if (!netif_carrier_ok(netdev)) { 5309 /* We've lost link, so the controller stops DMA, 5310 * but we've got queued Tx work that's never going 5311 * to get done, so reset controller to flush Tx. 5312 * (Do the reset outside of interrupt context). 5313 */ 5314 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5315 adapter->tx_timeout_count++; 5316 schedule_work(&adapter->reset_task); 5317 /* return immediately since reset is imminent */ 5318 return; 5319 } 5320 } 5321 5322 /* Force detection of hung controller every watchdog period */ 5323 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5324 } 5325 5326 /* Cause software interrupt to ensure Rx ring is cleaned */ 5327 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5328 u32 eics = 0; 5329 5330 for (i = 0; i < adapter->num_q_vectors; i++) 5331 eics |= adapter->q_vector[i]->eims_value; 5332 wr32(E1000_EICS, eics); 5333 } else { 5334 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5335 } 5336 5337 igb_spoof_check(adapter); 5338 igb_ptp_rx_hang(adapter); 5339 igb_ptp_tx_hang(adapter); 5340 5341 /* Check LVMMC register on i350/i354 only */ 5342 if ((adapter->hw.mac.type == e1000_i350) || 5343 (adapter->hw.mac.type == e1000_i354)) 5344 igb_check_lvmmc(adapter); 5345 5346 /* Reset the timer */ 5347 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5348 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5349 mod_timer(&adapter->watchdog_timer, 5350 round_jiffies(jiffies + HZ)); 5351 else 5352 mod_timer(&adapter->watchdog_timer, 5353 round_jiffies(jiffies + 2 * HZ)); 5354 } 5355 } 5356 5357 enum latency_range { 5358 lowest_latency = 0, 5359 low_latency = 1, 5360 bulk_latency = 2, 5361 latency_invalid = 255 5362 }; 5363 5364 /** 5365 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5366 * @q_vector: pointer to q_vector 5367 * 5368 * Stores a new ITR value based on strictly on packet size. This 5369 * algorithm is less sophisticated than that used in igb_update_itr, 5370 * due to the difficulty of synchronizing statistics across multiple 5371 * receive rings. The divisors and thresholds used by this function 5372 * were determined based on theoretical maximum wire speed and testing 5373 * data, in order to minimize response time while increasing bulk 5374 * throughput. 5375 * This functionality is controlled by ethtool's coalescing settings. 5376 * NOTE: This function is called only when operating in a multiqueue 5377 * receive environment. 5378 **/ 5379 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5380 { 5381 int new_val = q_vector->itr_val; 5382 int avg_wire_size = 0; 5383 struct igb_adapter *adapter = q_vector->adapter; 5384 unsigned int packets; 5385 5386 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5387 * ints/sec - ITR timer value of 120 ticks. 5388 */ 5389 if (adapter->link_speed != SPEED_1000) { 5390 new_val = IGB_4K_ITR; 5391 goto set_itr_val; 5392 } 5393 5394 packets = q_vector->rx.total_packets; 5395 if (packets) 5396 avg_wire_size = q_vector->rx.total_bytes / packets; 5397 5398 packets = q_vector->tx.total_packets; 5399 if (packets) 5400 avg_wire_size = max_t(u32, avg_wire_size, 5401 q_vector->tx.total_bytes / packets); 5402 5403 /* if avg_wire_size isn't set no work was done */ 5404 if (!avg_wire_size) 5405 goto clear_counts; 5406 5407 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5408 avg_wire_size += 24; 5409 5410 /* Don't starve jumbo frames */ 5411 avg_wire_size = min(avg_wire_size, 3000); 5412 5413 /* Give a little boost to mid-size frames */ 5414 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5415 new_val = avg_wire_size / 3; 5416 else 5417 new_val = avg_wire_size / 2; 5418 5419 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5420 if (new_val < IGB_20K_ITR && 5421 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5422 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5423 new_val = IGB_20K_ITR; 5424 5425 set_itr_val: 5426 if (new_val != q_vector->itr_val) { 5427 q_vector->itr_val = new_val; 5428 q_vector->set_itr = 1; 5429 } 5430 clear_counts: 5431 q_vector->rx.total_bytes = 0; 5432 q_vector->rx.total_packets = 0; 5433 q_vector->tx.total_bytes = 0; 5434 q_vector->tx.total_packets = 0; 5435 } 5436 5437 /** 5438 * igb_update_itr - update the dynamic ITR value based on statistics 5439 * @q_vector: pointer to q_vector 5440 * @ring_container: ring info to update the itr for 5441 * 5442 * Stores a new ITR value based on packets and byte 5443 * counts during the last interrupt. The advantage of per interrupt 5444 * computation is faster updates and more accurate ITR for the current 5445 * traffic pattern. Constants in this function were computed 5446 * based on theoretical maximum wire speed and thresholds were set based 5447 * on testing data as well as attempting to minimize response time 5448 * while increasing bulk throughput. 5449 * This functionality is controlled by ethtool's coalescing settings. 5450 * NOTE: These calculations are only valid when operating in a single- 5451 * queue environment. 5452 **/ 5453 static void igb_update_itr(struct igb_q_vector *q_vector, 5454 struct igb_ring_container *ring_container) 5455 { 5456 unsigned int packets = ring_container->total_packets; 5457 unsigned int bytes = ring_container->total_bytes; 5458 u8 itrval = ring_container->itr; 5459 5460 /* no packets, exit with status unchanged */ 5461 if (packets == 0) 5462 return; 5463 5464 switch (itrval) { 5465 case lowest_latency: 5466 /* handle TSO and jumbo frames */ 5467 if (bytes/packets > 8000) 5468 itrval = bulk_latency; 5469 else if ((packets < 5) && (bytes > 512)) 5470 itrval = low_latency; 5471 break; 5472 case low_latency: /* 50 usec aka 20000 ints/s */ 5473 if (bytes > 10000) { 5474 /* this if handles the TSO accounting */ 5475 if (bytes/packets > 8000) 5476 itrval = bulk_latency; 5477 else if ((packets < 10) || ((bytes/packets) > 1200)) 5478 itrval = bulk_latency; 5479 else if ((packets > 35)) 5480 itrval = lowest_latency; 5481 } else if (bytes/packets > 2000) { 5482 itrval = bulk_latency; 5483 } else if (packets <= 2 && bytes < 512) { 5484 itrval = lowest_latency; 5485 } 5486 break; 5487 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5488 if (bytes > 25000) { 5489 if (packets > 35) 5490 itrval = low_latency; 5491 } else if (bytes < 1500) { 5492 itrval = low_latency; 5493 } 5494 break; 5495 } 5496 5497 /* clear work counters since we have the values we need */ 5498 ring_container->total_bytes = 0; 5499 ring_container->total_packets = 0; 5500 5501 /* write updated itr to ring container */ 5502 ring_container->itr = itrval; 5503 } 5504 5505 static void igb_set_itr(struct igb_q_vector *q_vector) 5506 { 5507 struct igb_adapter *adapter = q_vector->adapter; 5508 u32 new_itr = q_vector->itr_val; 5509 u8 current_itr = 0; 5510 5511 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5512 if (adapter->link_speed != SPEED_1000) { 5513 current_itr = 0; 5514 new_itr = IGB_4K_ITR; 5515 goto set_itr_now; 5516 } 5517 5518 igb_update_itr(q_vector, &q_vector->tx); 5519 igb_update_itr(q_vector, &q_vector->rx); 5520 5521 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5522 5523 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5524 if (current_itr == lowest_latency && 5525 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5526 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5527 current_itr = low_latency; 5528 5529 switch (current_itr) { 5530 /* counts and packets in update_itr are dependent on these numbers */ 5531 case lowest_latency: 5532 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5533 break; 5534 case low_latency: 5535 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5536 break; 5537 case bulk_latency: 5538 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5539 break; 5540 default: 5541 break; 5542 } 5543 5544 set_itr_now: 5545 if (new_itr != q_vector->itr_val) { 5546 /* this attempts to bias the interrupt rate towards Bulk 5547 * by adding intermediate steps when interrupt rate is 5548 * increasing 5549 */ 5550 new_itr = new_itr > q_vector->itr_val ? 5551 max((new_itr * q_vector->itr_val) / 5552 (new_itr + (q_vector->itr_val >> 2)), 5553 new_itr) : new_itr; 5554 /* Don't write the value here; it resets the adapter's 5555 * internal timer, and causes us to delay far longer than 5556 * we should between interrupts. Instead, we write the ITR 5557 * value at the beginning of the next interrupt so the timing 5558 * ends up being correct. 5559 */ 5560 q_vector->itr_val = new_itr; 5561 q_vector->set_itr = 1; 5562 } 5563 } 5564 5565 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 5566 u32 type_tucmd, u32 mss_l4len_idx) 5567 { 5568 struct e1000_adv_tx_context_desc *context_desc; 5569 u16 i = tx_ring->next_to_use; 5570 5571 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5572 5573 i++; 5574 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5575 5576 /* set bits to identify this as an advanced context descriptor */ 5577 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5578 5579 /* For 82575, context index must be unique per ring. */ 5580 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5581 mss_l4len_idx |= tx_ring->reg_idx << 4; 5582 5583 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5584 context_desc->seqnum_seed = 0; 5585 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5586 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5587 } 5588 5589 static int igb_tso(struct igb_ring *tx_ring, 5590 struct igb_tx_buffer *first, 5591 u8 *hdr_len) 5592 { 5593 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5594 struct sk_buff *skb = first->skb; 5595 union { 5596 struct iphdr *v4; 5597 struct ipv6hdr *v6; 5598 unsigned char *hdr; 5599 } ip; 5600 union { 5601 struct tcphdr *tcp; 5602 unsigned char *hdr; 5603 } l4; 5604 u32 paylen, l4_offset; 5605 int err; 5606 5607 if (skb->ip_summed != CHECKSUM_PARTIAL) 5608 return 0; 5609 5610 if (!skb_is_gso(skb)) 5611 return 0; 5612 5613 err = skb_cow_head(skb, 0); 5614 if (err < 0) 5615 return err; 5616 5617 ip.hdr = skb_network_header(skb); 5618 l4.hdr = skb_checksum_start(skb); 5619 5620 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5621 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5622 5623 /* initialize outer IP header fields */ 5624 if (ip.v4->version == 4) { 5625 unsigned char *csum_start = skb_checksum_start(skb); 5626 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5627 5628 /* IP header will have to cancel out any data that 5629 * is not a part of the outer IP header 5630 */ 5631 ip.v4->check = csum_fold(csum_partial(trans_start, 5632 csum_start - trans_start, 5633 0)); 5634 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5635 5636 ip.v4->tot_len = 0; 5637 first->tx_flags |= IGB_TX_FLAGS_TSO | 5638 IGB_TX_FLAGS_CSUM | 5639 IGB_TX_FLAGS_IPV4; 5640 } else { 5641 ip.v6->payload_len = 0; 5642 first->tx_flags |= IGB_TX_FLAGS_TSO | 5643 IGB_TX_FLAGS_CSUM; 5644 } 5645 5646 /* determine offset of inner transport header */ 5647 l4_offset = l4.hdr - skb->data; 5648 5649 /* compute length of segmentation header */ 5650 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5651 5652 /* remove payload length from inner checksum */ 5653 paylen = skb->len - l4_offset; 5654 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5655 5656 /* update gso size and bytecount with header size */ 5657 first->gso_segs = skb_shinfo(skb)->gso_segs; 5658 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5659 5660 /* MSS L4LEN IDX */ 5661 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5662 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5663 5664 /* VLAN MACLEN IPLEN */ 5665 vlan_macip_lens = l4.hdr - ip.hdr; 5666 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5667 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5668 5669 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5670 5671 return 1; 5672 } 5673 5674 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5675 { 5676 unsigned int offset = 0; 5677 5678 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5679 5680 return offset == skb_checksum_start_offset(skb); 5681 } 5682 5683 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5684 { 5685 struct sk_buff *skb = first->skb; 5686 u32 vlan_macip_lens = 0; 5687 u32 type_tucmd = 0; 5688 5689 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5690 csum_failed: 5691 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5692 return; 5693 goto no_csum; 5694 } 5695 5696 switch (skb->csum_offset) { 5697 case offsetof(struct tcphdr, check): 5698 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5699 /* fall through */ 5700 case offsetof(struct udphdr, check): 5701 break; 5702 case offsetof(struct sctphdr, checksum): 5703 /* validate that this is actually an SCTP request */ 5704 if (((first->protocol == htons(ETH_P_IP)) && 5705 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5706 ((first->protocol == htons(ETH_P_IPV6)) && 5707 igb_ipv6_csum_is_sctp(skb))) { 5708 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5709 break; 5710 } 5711 default: 5712 skb_checksum_help(skb); 5713 goto csum_failed; 5714 } 5715 5716 /* update TX checksum flag */ 5717 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5718 vlan_macip_lens = skb_checksum_start_offset(skb) - 5719 skb_network_offset(skb); 5720 no_csum: 5721 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5722 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5723 5724 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5725 } 5726 5727 #define IGB_SET_FLAG(_input, _flag, _result) \ 5728 ((_flag <= _result) ? \ 5729 ((u32)(_input & _flag) * (_result / _flag)) : \ 5730 ((u32)(_input & _flag) / (_flag / _result))) 5731 5732 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5733 { 5734 /* set type for advanced descriptor with frame checksum insertion */ 5735 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5736 E1000_ADVTXD_DCMD_DEXT | 5737 E1000_ADVTXD_DCMD_IFCS; 5738 5739 /* set HW vlan bit if vlan is present */ 5740 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5741 (E1000_ADVTXD_DCMD_VLE)); 5742 5743 /* set segmentation bits for TSO */ 5744 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5745 (E1000_ADVTXD_DCMD_TSE)); 5746 5747 /* set timestamp bit if present */ 5748 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5749 (E1000_ADVTXD_MAC_TSTAMP)); 5750 5751 /* insert frame checksum */ 5752 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5753 5754 return cmd_type; 5755 } 5756 5757 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5758 union e1000_adv_tx_desc *tx_desc, 5759 u32 tx_flags, unsigned int paylen) 5760 { 5761 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5762 5763 /* 82575 requires a unique index per ring */ 5764 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5765 olinfo_status |= tx_ring->reg_idx << 4; 5766 5767 /* insert L4 checksum */ 5768 olinfo_status |= IGB_SET_FLAG(tx_flags, 5769 IGB_TX_FLAGS_CSUM, 5770 (E1000_TXD_POPTS_TXSM << 8)); 5771 5772 /* insert IPv4 checksum */ 5773 olinfo_status |= IGB_SET_FLAG(tx_flags, 5774 IGB_TX_FLAGS_IPV4, 5775 (E1000_TXD_POPTS_IXSM << 8)); 5776 5777 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5778 } 5779 5780 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5781 { 5782 struct net_device *netdev = tx_ring->netdev; 5783 5784 netif_stop_subqueue(netdev, tx_ring->queue_index); 5785 5786 /* Herbert's original patch had: 5787 * smp_mb__after_netif_stop_queue(); 5788 * but since that doesn't exist yet, just open code it. 5789 */ 5790 smp_mb(); 5791 5792 /* We need to check again in a case another CPU has just 5793 * made room available. 5794 */ 5795 if (igb_desc_unused(tx_ring) < size) 5796 return -EBUSY; 5797 5798 /* A reprieve! */ 5799 netif_wake_subqueue(netdev, tx_ring->queue_index); 5800 5801 u64_stats_update_begin(&tx_ring->tx_syncp2); 5802 tx_ring->tx_stats.restart_queue2++; 5803 u64_stats_update_end(&tx_ring->tx_syncp2); 5804 5805 return 0; 5806 } 5807 5808 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5809 { 5810 if (igb_desc_unused(tx_ring) >= size) 5811 return 0; 5812 return __igb_maybe_stop_tx(tx_ring, size); 5813 } 5814 5815 static int igb_tx_map(struct igb_ring *tx_ring, 5816 struct igb_tx_buffer *first, 5817 const u8 hdr_len) 5818 { 5819 struct sk_buff *skb = first->skb; 5820 struct igb_tx_buffer *tx_buffer; 5821 union e1000_adv_tx_desc *tx_desc; 5822 struct skb_frag_struct *frag; 5823 dma_addr_t dma; 5824 unsigned int data_len, size; 5825 u32 tx_flags = first->tx_flags; 5826 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5827 u16 i = tx_ring->next_to_use; 5828 5829 tx_desc = IGB_TX_DESC(tx_ring, i); 5830 5831 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5832 5833 size = skb_headlen(skb); 5834 data_len = skb->data_len; 5835 5836 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5837 5838 tx_buffer = first; 5839 5840 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5841 if (dma_mapping_error(tx_ring->dev, dma)) 5842 goto dma_error; 5843 5844 /* record length, and DMA address */ 5845 dma_unmap_len_set(tx_buffer, len, size); 5846 dma_unmap_addr_set(tx_buffer, dma, dma); 5847 5848 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5849 5850 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5851 tx_desc->read.cmd_type_len = 5852 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5853 5854 i++; 5855 tx_desc++; 5856 if (i == tx_ring->count) { 5857 tx_desc = IGB_TX_DESC(tx_ring, 0); 5858 i = 0; 5859 } 5860 tx_desc->read.olinfo_status = 0; 5861 5862 dma += IGB_MAX_DATA_PER_TXD; 5863 size -= IGB_MAX_DATA_PER_TXD; 5864 5865 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5866 } 5867 5868 if (likely(!data_len)) 5869 break; 5870 5871 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5872 5873 i++; 5874 tx_desc++; 5875 if (i == tx_ring->count) { 5876 tx_desc = IGB_TX_DESC(tx_ring, 0); 5877 i = 0; 5878 } 5879 tx_desc->read.olinfo_status = 0; 5880 5881 size = skb_frag_size(frag); 5882 data_len -= size; 5883 5884 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5885 size, DMA_TO_DEVICE); 5886 5887 tx_buffer = &tx_ring->tx_buffer_info[i]; 5888 } 5889 5890 /* write last descriptor with RS and EOP bits */ 5891 cmd_type |= size | IGB_TXD_DCMD; 5892 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5893 5894 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5895 5896 /* set the timestamp */ 5897 first->time_stamp = jiffies; 5898 5899 /* Force memory writes to complete before letting h/w know there 5900 * are new descriptors to fetch. (Only applicable for weak-ordered 5901 * memory model archs, such as IA-64). 5902 * 5903 * We also need this memory barrier to make certain all of the 5904 * status bits have been updated before next_to_watch is written. 5905 */ 5906 wmb(); 5907 5908 /* set next_to_watch value indicating a packet is present */ 5909 first->next_to_watch = tx_desc; 5910 5911 i++; 5912 if (i == tx_ring->count) 5913 i = 0; 5914 5915 tx_ring->next_to_use = i; 5916 5917 /* Make sure there is space in the ring for the next send. */ 5918 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5919 5920 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5921 writel(i, tx_ring->tail); 5922 5923 /* we need this if more than one processor can write to our tail 5924 * at a time, it synchronizes IO on IA64/Altix systems 5925 */ 5926 mmiowb(); 5927 } 5928 return 0; 5929 5930 dma_error: 5931 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5932 tx_buffer = &tx_ring->tx_buffer_info[i]; 5933 5934 /* clear dma mappings for failed tx_buffer_info map */ 5935 while (tx_buffer != first) { 5936 if (dma_unmap_len(tx_buffer, len)) 5937 dma_unmap_page(tx_ring->dev, 5938 dma_unmap_addr(tx_buffer, dma), 5939 dma_unmap_len(tx_buffer, len), 5940 DMA_TO_DEVICE); 5941 dma_unmap_len_set(tx_buffer, len, 0); 5942 5943 if (i-- == 0) 5944 i += tx_ring->count; 5945 tx_buffer = &tx_ring->tx_buffer_info[i]; 5946 } 5947 5948 if (dma_unmap_len(tx_buffer, len)) 5949 dma_unmap_single(tx_ring->dev, 5950 dma_unmap_addr(tx_buffer, dma), 5951 dma_unmap_len(tx_buffer, len), 5952 DMA_TO_DEVICE); 5953 dma_unmap_len_set(tx_buffer, len, 0); 5954 5955 dev_kfree_skb_any(tx_buffer->skb); 5956 tx_buffer->skb = NULL; 5957 5958 tx_ring->next_to_use = i; 5959 5960 return -1; 5961 } 5962 5963 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5964 struct igb_ring *tx_ring) 5965 { 5966 struct igb_tx_buffer *first; 5967 int tso; 5968 u32 tx_flags = 0; 5969 unsigned short f; 5970 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5971 __be16 protocol = vlan_get_protocol(skb); 5972 u8 hdr_len = 0; 5973 5974 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5975 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5976 * + 2 desc gap to keep tail from touching head, 5977 * + 1 desc for context descriptor, 5978 * otherwise try next time 5979 */ 5980 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5981 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5982 5983 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5984 /* this is a hard error */ 5985 return NETDEV_TX_BUSY; 5986 } 5987 5988 /* record the location of the first descriptor for this packet */ 5989 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5990 first->skb = skb; 5991 first->bytecount = skb->len; 5992 first->gso_segs = 1; 5993 5994 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5995 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5996 5997 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 5998 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5999 &adapter->state)) { 6000 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6001 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6002 6003 adapter->ptp_tx_skb = skb_get(skb); 6004 adapter->ptp_tx_start = jiffies; 6005 if (adapter->hw.mac.type == e1000_82576) 6006 schedule_work(&adapter->ptp_tx_work); 6007 } else { 6008 adapter->tx_hwtstamp_skipped++; 6009 } 6010 } 6011 6012 skb_tx_timestamp(skb); 6013 6014 if (skb_vlan_tag_present(skb)) { 6015 tx_flags |= IGB_TX_FLAGS_VLAN; 6016 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6017 } 6018 6019 /* record initial flags and protocol */ 6020 first->tx_flags = tx_flags; 6021 first->protocol = protocol; 6022 6023 tso = igb_tso(tx_ring, first, &hdr_len); 6024 if (tso < 0) 6025 goto out_drop; 6026 else if (!tso) 6027 igb_tx_csum(tx_ring, first); 6028 6029 if (igb_tx_map(tx_ring, first, hdr_len)) 6030 goto cleanup_tx_tstamp; 6031 6032 return NETDEV_TX_OK; 6033 6034 out_drop: 6035 dev_kfree_skb_any(first->skb); 6036 first->skb = NULL; 6037 cleanup_tx_tstamp: 6038 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6039 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6040 6041 dev_kfree_skb_any(adapter->ptp_tx_skb); 6042 adapter->ptp_tx_skb = NULL; 6043 if (adapter->hw.mac.type == e1000_82576) 6044 cancel_work_sync(&adapter->ptp_tx_work); 6045 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6046 } 6047 6048 return NETDEV_TX_OK; 6049 } 6050 6051 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6052 struct sk_buff *skb) 6053 { 6054 unsigned int r_idx = skb->queue_mapping; 6055 6056 if (r_idx >= adapter->num_tx_queues) 6057 r_idx = r_idx % adapter->num_tx_queues; 6058 6059 return adapter->tx_ring[r_idx]; 6060 } 6061 6062 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6063 struct net_device *netdev) 6064 { 6065 struct igb_adapter *adapter = netdev_priv(netdev); 6066 6067 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6068 * in order to meet this minimum size requirement. 6069 */ 6070 if (skb_put_padto(skb, 17)) 6071 return NETDEV_TX_OK; 6072 6073 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6074 } 6075 6076 /** 6077 * igb_tx_timeout - Respond to a Tx Hang 6078 * @netdev: network interface device structure 6079 **/ 6080 static void igb_tx_timeout(struct net_device *netdev) 6081 { 6082 struct igb_adapter *adapter = netdev_priv(netdev); 6083 struct e1000_hw *hw = &adapter->hw; 6084 6085 /* Do the reset outside of interrupt context */ 6086 adapter->tx_timeout_count++; 6087 6088 if (hw->mac.type >= e1000_82580) 6089 hw->dev_spec._82575.global_device_reset = true; 6090 6091 schedule_work(&adapter->reset_task); 6092 wr32(E1000_EICS, 6093 (adapter->eims_enable_mask & ~adapter->eims_other)); 6094 } 6095 6096 static void igb_reset_task(struct work_struct *work) 6097 { 6098 struct igb_adapter *adapter; 6099 adapter = container_of(work, struct igb_adapter, reset_task); 6100 6101 igb_dump(adapter); 6102 netdev_err(adapter->netdev, "Reset adapter\n"); 6103 igb_reinit_locked(adapter); 6104 } 6105 6106 /** 6107 * igb_get_stats64 - Get System Network Statistics 6108 * @netdev: network interface device structure 6109 * @stats: rtnl_link_stats64 pointer 6110 **/ 6111 static void igb_get_stats64(struct net_device *netdev, 6112 struct rtnl_link_stats64 *stats) 6113 { 6114 struct igb_adapter *adapter = netdev_priv(netdev); 6115 6116 spin_lock(&adapter->stats64_lock); 6117 igb_update_stats(adapter); 6118 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6119 spin_unlock(&adapter->stats64_lock); 6120 } 6121 6122 /** 6123 * igb_change_mtu - Change the Maximum Transfer Unit 6124 * @netdev: network interface device structure 6125 * @new_mtu: new value for maximum frame size 6126 * 6127 * Returns 0 on success, negative on failure 6128 **/ 6129 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6130 { 6131 struct igb_adapter *adapter = netdev_priv(netdev); 6132 struct pci_dev *pdev = adapter->pdev; 6133 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6134 6135 /* adjust max frame to be at least the size of a standard frame */ 6136 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6137 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6138 6139 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6140 usleep_range(1000, 2000); 6141 6142 /* igb_down has a dependency on max_frame_size */ 6143 adapter->max_frame_size = max_frame; 6144 6145 if (netif_running(netdev)) 6146 igb_down(adapter); 6147 6148 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 6149 netdev->mtu, new_mtu); 6150 netdev->mtu = new_mtu; 6151 6152 if (netif_running(netdev)) 6153 igb_up(adapter); 6154 else 6155 igb_reset(adapter); 6156 6157 clear_bit(__IGB_RESETTING, &adapter->state); 6158 6159 return 0; 6160 } 6161 6162 /** 6163 * igb_update_stats - Update the board statistics counters 6164 * @adapter: board private structure 6165 **/ 6166 void igb_update_stats(struct igb_adapter *adapter) 6167 { 6168 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6169 struct e1000_hw *hw = &adapter->hw; 6170 struct pci_dev *pdev = adapter->pdev; 6171 u32 reg, mpc; 6172 int i; 6173 u64 bytes, packets; 6174 unsigned int start; 6175 u64 _bytes, _packets; 6176 6177 /* Prevent stats update while adapter is being reset, or if the pci 6178 * connection is down. 6179 */ 6180 if (adapter->link_speed == 0) 6181 return; 6182 if (pci_channel_offline(pdev)) 6183 return; 6184 6185 bytes = 0; 6186 packets = 0; 6187 6188 rcu_read_lock(); 6189 for (i = 0; i < adapter->num_rx_queues; i++) { 6190 struct igb_ring *ring = adapter->rx_ring[i]; 6191 u32 rqdpc = rd32(E1000_RQDPC(i)); 6192 if (hw->mac.type >= e1000_i210) 6193 wr32(E1000_RQDPC(i), 0); 6194 6195 if (rqdpc) { 6196 ring->rx_stats.drops += rqdpc; 6197 net_stats->rx_fifo_errors += rqdpc; 6198 } 6199 6200 do { 6201 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6202 _bytes = ring->rx_stats.bytes; 6203 _packets = ring->rx_stats.packets; 6204 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6205 bytes += _bytes; 6206 packets += _packets; 6207 } 6208 6209 net_stats->rx_bytes = bytes; 6210 net_stats->rx_packets = packets; 6211 6212 bytes = 0; 6213 packets = 0; 6214 for (i = 0; i < adapter->num_tx_queues; i++) { 6215 struct igb_ring *ring = adapter->tx_ring[i]; 6216 do { 6217 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6218 _bytes = ring->tx_stats.bytes; 6219 _packets = ring->tx_stats.packets; 6220 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6221 bytes += _bytes; 6222 packets += _packets; 6223 } 6224 net_stats->tx_bytes = bytes; 6225 net_stats->tx_packets = packets; 6226 rcu_read_unlock(); 6227 6228 /* read stats registers */ 6229 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6230 adapter->stats.gprc += rd32(E1000_GPRC); 6231 adapter->stats.gorc += rd32(E1000_GORCL); 6232 rd32(E1000_GORCH); /* clear GORCL */ 6233 adapter->stats.bprc += rd32(E1000_BPRC); 6234 adapter->stats.mprc += rd32(E1000_MPRC); 6235 adapter->stats.roc += rd32(E1000_ROC); 6236 6237 adapter->stats.prc64 += rd32(E1000_PRC64); 6238 adapter->stats.prc127 += rd32(E1000_PRC127); 6239 adapter->stats.prc255 += rd32(E1000_PRC255); 6240 adapter->stats.prc511 += rd32(E1000_PRC511); 6241 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6242 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6243 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6244 adapter->stats.sec += rd32(E1000_SEC); 6245 6246 mpc = rd32(E1000_MPC); 6247 adapter->stats.mpc += mpc; 6248 net_stats->rx_fifo_errors += mpc; 6249 adapter->stats.scc += rd32(E1000_SCC); 6250 adapter->stats.ecol += rd32(E1000_ECOL); 6251 adapter->stats.mcc += rd32(E1000_MCC); 6252 adapter->stats.latecol += rd32(E1000_LATECOL); 6253 adapter->stats.dc += rd32(E1000_DC); 6254 adapter->stats.rlec += rd32(E1000_RLEC); 6255 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6256 adapter->stats.xontxc += rd32(E1000_XONTXC); 6257 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6258 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6259 adapter->stats.fcruc += rd32(E1000_FCRUC); 6260 adapter->stats.gptc += rd32(E1000_GPTC); 6261 adapter->stats.gotc += rd32(E1000_GOTCL); 6262 rd32(E1000_GOTCH); /* clear GOTCL */ 6263 adapter->stats.rnbc += rd32(E1000_RNBC); 6264 adapter->stats.ruc += rd32(E1000_RUC); 6265 adapter->stats.rfc += rd32(E1000_RFC); 6266 adapter->stats.rjc += rd32(E1000_RJC); 6267 adapter->stats.tor += rd32(E1000_TORH); 6268 adapter->stats.tot += rd32(E1000_TOTH); 6269 adapter->stats.tpr += rd32(E1000_TPR); 6270 6271 adapter->stats.ptc64 += rd32(E1000_PTC64); 6272 adapter->stats.ptc127 += rd32(E1000_PTC127); 6273 adapter->stats.ptc255 += rd32(E1000_PTC255); 6274 adapter->stats.ptc511 += rd32(E1000_PTC511); 6275 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6276 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6277 6278 adapter->stats.mptc += rd32(E1000_MPTC); 6279 adapter->stats.bptc += rd32(E1000_BPTC); 6280 6281 adapter->stats.tpt += rd32(E1000_TPT); 6282 adapter->stats.colc += rd32(E1000_COLC); 6283 6284 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6285 /* read internal phy specific stats */ 6286 reg = rd32(E1000_CTRL_EXT); 6287 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6288 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6289 6290 /* this stat has invalid values on i210/i211 */ 6291 if ((hw->mac.type != e1000_i210) && 6292 (hw->mac.type != e1000_i211)) 6293 adapter->stats.tncrs += rd32(E1000_TNCRS); 6294 } 6295 6296 adapter->stats.tsctc += rd32(E1000_TSCTC); 6297 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6298 6299 adapter->stats.iac += rd32(E1000_IAC); 6300 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6301 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6302 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6303 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6304 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6305 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6306 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6307 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6308 6309 /* Fill out the OS statistics structure */ 6310 net_stats->multicast = adapter->stats.mprc; 6311 net_stats->collisions = adapter->stats.colc; 6312 6313 /* Rx Errors */ 6314 6315 /* RLEC on some newer hardware can be incorrect so build 6316 * our own version based on RUC and ROC 6317 */ 6318 net_stats->rx_errors = adapter->stats.rxerrc + 6319 adapter->stats.crcerrs + adapter->stats.algnerrc + 6320 adapter->stats.ruc + adapter->stats.roc + 6321 adapter->stats.cexterr; 6322 net_stats->rx_length_errors = adapter->stats.ruc + 6323 adapter->stats.roc; 6324 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6325 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6326 net_stats->rx_missed_errors = adapter->stats.mpc; 6327 6328 /* Tx Errors */ 6329 net_stats->tx_errors = adapter->stats.ecol + 6330 adapter->stats.latecol; 6331 net_stats->tx_aborted_errors = adapter->stats.ecol; 6332 net_stats->tx_window_errors = adapter->stats.latecol; 6333 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6334 6335 /* Tx Dropped needs to be maintained elsewhere */ 6336 6337 /* Management Stats */ 6338 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6339 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6340 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6341 6342 /* OS2BMC Stats */ 6343 reg = rd32(E1000_MANC); 6344 if (reg & E1000_MANC_EN_BMC2OS) { 6345 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6346 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6347 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6348 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6349 } 6350 } 6351 6352 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6353 { 6354 struct e1000_hw *hw = &adapter->hw; 6355 struct ptp_clock_event event; 6356 struct timespec64 ts; 6357 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6358 6359 if (tsicr & TSINTR_SYS_WRAP) { 6360 event.type = PTP_CLOCK_PPS; 6361 if (adapter->ptp_caps.pps) 6362 ptp_clock_event(adapter->ptp_clock, &event); 6363 ack |= TSINTR_SYS_WRAP; 6364 } 6365 6366 if (tsicr & E1000_TSICR_TXTS) { 6367 /* retrieve hardware timestamp */ 6368 schedule_work(&adapter->ptp_tx_work); 6369 ack |= E1000_TSICR_TXTS; 6370 } 6371 6372 if (tsicr & TSINTR_TT0) { 6373 spin_lock(&adapter->tmreg_lock); 6374 ts = timespec64_add(adapter->perout[0].start, 6375 adapter->perout[0].period); 6376 /* u32 conversion of tv_sec is safe until y2106 */ 6377 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6378 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6379 tsauxc = rd32(E1000_TSAUXC); 6380 tsauxc |= TSAUXC_EN_TT0; 6381 wr32(E1000_TSAUXC, tsauxc); 6382 adapter->perout[0].start = ts; 6383 spin_unlock(&adapter->tmreg_lock); 6384 ack |= TSINTR_TT0; 6385 } 6386 6387 if (tsicr & TSINTR_TT1) { 6388 spin_lock(&adapter->tmreg_lock); 6389 ts = timespec64_add(adapter->perout[1].start, 6390 adapter->perout[1].period); 6391 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6392 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6393 tsauxc = rd32(E1000_TSAUXC); 6394 tsauxc |= TSAUXC_EN_TT1; 6395 wr32(E1000_TSAUXC, tsauxc); 6396 adapter->perout[1].start = ts; 6397 spin_unlock(&adapter->tmreg_lock); 6398 ack |= TSINTR_TT1; 6399 } 6400 6401 if (tsicr & TSINTR_AUTT0) { 6402 nsec = rd32(E1000_AUXSTMPL0); 6403 sec = rd32(E1000_AUXSTMPH0); 6404 event.type = PTP_CLOCK_EXTTS; 6405 event.index = 0; 6406 event.timestamp = sec * 1000000000ULL + nsec; 6407 ptp_clock_event(adapter->ptp_clock, &event); 6408 ack |= TSINTR_AUTT0; 6409 } 6410 6411 if (tsicr & TSINTR_AUTT1) { 6412 nsec = rd32(E1000_AUXSTMPL1); 6413 sec = rd32(E1000_AUXSTMPH1); 6414 event.type = PTP_CLOCK_EXTTS; 6415 event.index = 1; 6416 event.timestamp = sec * 1000000000ULL + nsec; 6417 ptp_clock_event(adapter->ptp_clock, &event); 6418 ack |= TSINTR_AUTT1; 6419 } 6420 6421 /* acknowledge the interrupts */ 6422 wr32(E1000_TSICR, ack); 6423 } 6424 6425 static irqreturn_t igb_msix_other(int irq, void *data) 6426 { 6427 struct igb_adapter *adapter = data; 6428 struct e1000_hw *hw = &adapter->hw; 6429 u32 icr = rd32(E1000_ICR); 6430 /* reading ICR causes bit 31 of EICR to be cleared */ 6431 6432 if (icr & E1000_ICR_DRSTA) 6433 schedule_work(&adapter->reset_task); 6434 6435 if (icr & E1000_ICR_DOUTSYNC) { 6436 /* HW is reporting DMA is out of sync */ 6437 adapter->stats.doosync++; 6438 /* The DMA Out of Sync is also indication of a spoof event 6439 * in IOV mode. Check the Wrong VM Behavior register to 6440 * see if it is really a spoof event. 6441 */ 6442 igb_check_wvbr(adapter); 6443 } 6444 6445 /* Check for a mailbox event */ 6446 if (icr & E1000_ICR_VMMB) 6447 igb_msg_task(adapter); 6448 6449 if (icr & E1000_ICR_LSC) { 6450 hw->mac.get_link_status = 1; 6451 /* guard against interrupt when we're going down */ 6452 if (!test_bit(__IGB_DOWN, &adapter->state)) 6453 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6454 } 6455 6456 if (icr & E1000_ICR_TS) 6457 igb_tsync_interrupt(adapter); 6458 6459 wr32(E1000_EIMS, adapter->eims_other); 6460 6461 return IRQ_HANDLED; 6462 } 6463 6464 static void igb_write_itr(struct igb_q_vector *q_vector) 6465 { 6466 struct igb_adapter *adapter = q_vector->adapter; 6467 u32 itr_val = q_vector->itr_val & 0x7FFC; 6468 6469 if (!q_vector->set_itr) 6470 return; 6471 6472 if (!itr_val) 6473 itr_val = 0x4; 6474 6475 if (adapter->hw.mac.type == e1000_82575) 6476 itr_val |= itr_val << 16; 6477 else 6478 itr_val |= E1000_EITR_CNT_IGNR; 6479 6480 writel(itr_val, q_vector->itr_register); 6481 q_vector->set_itr = 0; 6482 } 6483 6484 static irqreturn_t igb_msix_ring(int irq, void *data) 6485 { 6486 struct igb_q_vector *q_vector = data; 6487 6488 /* Write the ITR value calculated from the previous interrupt. */ 6489 igb_write_itr(q_vector); 6490 6491 napi_schedule(&q_vector->napi); 6492 6493 return IRQ_HANDLED; 6494 } 6495 6496 #ifdef CONFIG_IGB_DCA 6497 static void igb_update_tx_dca(struct igb_adapter *adapter, 6498 struct igb_ring *tx_ring, 6499 int cpu) 6500 { 6501 struct e1000_hw *hw = &adapter->hw; 6502 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6503 6504 if (hw->mac.type != e1000_82575) 6505 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6506 6507 /* We can enable relaxed ordering for reads, but not writes when 6508 * DCA is enabled. This is due to a known issue in some chipsets 6509 * which will cause the DCA tag to be cleared. 6510 */ 6511 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6512 E1000_DCA_TXCTRL_DATA_RRO_EN | 6513 E1000_DCA_TXCTRL_DESC_DCA_EN; 6514 6515 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6516 } 6517 6518 static void igb_update_rx_dca(struct igb_adapter *adapter, 6519 struct igb_ring *rx_ring, 6520 int cpu) 6521 { 6522 struct e1000_hw *hw = &adapter->hw; 6523 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6524 6525 if (hw->mac.type != e1000_82575) 6526 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6527 6528 /* We can enable relaxed ordering for reads, but not writes when 6529 * DCA is enabled. This is due to a known issue in some chipsets 6530 * which will cause the DCA tag to be cleared. 6531 */ 6532 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6533 E1000_DCA_RXCTRL_DESC_DCA_EN; 6534 6535 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6536 } 6537 6538 static void igb_update_dca(struct igb_q_vector *q_vector) 6539 { 6540 struct igb_adapter *adapter = q_vector->adapter; 6541 int cpu = get_cpu(); 6542 6543 if (q_vector->cpu == cpu) 6544 goto out_no_update; 6545 6546 if (q_vector->tx.ring) 6547 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6548 6549 if (q_vector->rx.ring) 6550 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6551 6552 q_vector->cpu = cpu; 6553 out_no_update: 6554 put_cpu(); 6555 } 6556 6557 static void igb_setup_dca(struct igb_adapter *adapter) 6558 { 6559 struct e1000_hw *hw = &adapter->hw; 6560 int i; 6561 6562 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6563 return; 6564 6565 /* Always use CB2 mode, difference is masked in the CB driver. */ 6566 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6567 6568 for (i = 0; i < adapter->num_q_vectors; i++) { 6569 adapter->q_vector[i]->cpu = -1; 6570 igb_update_dca(adapter->q_vector[i]); 6571 } 6572 } 6573 6574 static int __igb_notify_dca(struct device *dev, void *data) 6575 { 6576 struct net_device *netdev = dev_get_drvdata(dev); 6577 struct igb_adapter *adapter = netdev_priv(netdev); 6578 struct pci_dev *pdev = adapter->pdev; 6579 struct e1000_hw *hw = &adapter->hw; 6580 unsigned long event = *(unsigned long *)data; 6581 6582 switch (event) { 6583 case DCA_PROVIDER_ADD: 6584 /* if already enabled, don't do it again */ 6585 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6586 break; 6587 if (dca_add_requester(dev) == 0) { 6588 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6589 dev_info(&pdev->dev, "DCA enabled\n"); 6590 igb_setup_dca(adapter); 6591 break; 6592 } 6593 /* Fall Through since DCA is disabled. */ 6594 case DCA_PROVIDER_REMOVE: 6595 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6596 /* without this a class_device is left 6597 * hanging around in the sysfs model 6598 */ 6599 dca_remove_requester(dev); 6600 dev_info(&pdev->dev, "DCA disabled\n"); 6601 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6602 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6603 } 6604 break; 6605 } 6606 6607 return 0; 6608 } 6609 6610 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6611 void *p) 6612 { 6613 int ret_val; 6614 6615 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6616 __igb_notify_dca); 6617 6618 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6619 } 6620 #endif /* CONFIG_IGB_DCA */ 6621 6622 #ifdef CONFIG_PCI_IOV 6623 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6624 { 6625 unsigned char mac_addr[ETH_ALEN]; 6626 6627 eth_zero_addr(mac_addr); 6628 igb_set_vf_mac(adapter, vf, mac_addr); 6629 6630 /* By default spoof check is enabled for all VFs */ 6631 adapter->vf_data[vf].spoofchk_enabled = true; 6632 6633 /* By default VFs are not trusted */ 6634 adapter->vf_data[vf].trusted = false; 6635 6636 return 0; 6637 } 6638 6639 #endif 6640 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6641 { 6642 struct e1000_hw *hw = &adapter->hw; 6643 u32 ping; 6644 int i; 6645 6646 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6647 ping = E1000_PF_CONTROL_MSG; 6648 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6649 ping |= E1000_VT_MSGTYPE_CTS; 6650 igb_write_mbx(hw, &ping, 1, i); 6651 } 6652 } 6653 6654 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6655 { 6656 struct e1000_hw *hw = &adapter->hw; 6657 u32 vmolr = rd32(E1000_VMOLR(vf)); 6658 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6659 6660 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6661 IGB_VF_FLAG_MULTI_PROMISC); 6662 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6663 6664 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6665 vmolr |= E1000_VMOLR_MPME; 6666 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6667 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6668 } else { 6669 /* if we have hashes and we are clearing a multicast promisc 6670 * flag we need to write the hashes to the MTA as this step 6671 * was previously skipped 6672 */ 6673 if (vf_data->num_vf_mc_hashes > 30) { 6674 vmolr |= E1000_VMOLR_MPME; 6675 } else if (vf_data->num_vf_mc_hashes) { 6676 int j; 6677 6678 vmolr |= E1000_VMOLR_ROMPE; 6679 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6680 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6681 } 6682 } 6683 6684 wr32(E1000_VMOLR(vf), vmolr); 6685 6686 /* there are flags left unprocessed, likely not supported */ 6687 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6688 return -EINVAL; 6689 6690 return 0; 6691 } 6692 6693 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6694 u32 *msgbuf, u32 vf) 6695 { 6696 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6697 u16 *hash_list = (u16 *)&msgbuf[1]; 6698 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6699 int i; 6700 6701 /* salt away the number of multicast addresses assigned 6702 * to this VF for later use to restore when the PF multi cast 6703 * list changes 6704 */ 6705 vf_data->num_vf_mc_hashes = n; 6706 6707 /* only up to 30 hash values supported */ 6708 if (n > 30) 6709 n = 30; 6710 6711 /* store the hashes for later use */ 6712 for (i = 0; i < n; i++) 6713 vf_data->vf_mc_hashes[i] = hash_list[i]; 6714 6715 /* Flush and reset the mta with the new values */ 6716 igb_set_rx_mode(adapter->netdev); 6717 6718 return 0; 6719 } 6720 6721 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6722 { 6723 struct e1000_hw *hw = &adapter->hw; 6724 struct vf_data_storage *vf_data; 6725 int i, j; 6726 6727 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6728 u32 vmolr = rd32(E1000_VMOLR(i)); 6729 6730 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6731 6732 vf_data = &adapter->vf_data[i]; 6733 6734 if ((vf_data->num_vf_mc_hashes > 30) || 6735 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6736 vmolr |= E1000_VMOLR_MPME; 6737 } else if (vf_data->num_vf_mc_hashes) { 6738 vmolr |= E1000_VMOLR_ROMPE; 6739 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6740 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6741 } 6742 wr32(E1000_VMOLR(i), vmolr); 6743 } 6744 } 6745 6746 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6747 { 6748 struct e1000_hw *hw = &adapter->hw; 6749 u32 pool_mask, vlvf_mask, i; 6750 6751 /* create mask for VF and other pools */ 6752 pool_mask = E1000_VLVF_POOLSEL_MASK; 6753 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6754 6755 /* drop PF from pool bits */ 6756 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6757 adapter->vfs_allocated_count); 6758 6759 /* Find the vlan filter for this id */ 6760 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6761 u32 vlvf = rd32(E1000_VLVF(i)); 6762 u32 vfta_mask, vid, vfta; 6763 6764 /* remove the vf from the pool */ 6765 if (!(vlvf & vlvf_mask)) 6766 continue; 6767 6768 /* clear out bit from VLVF */ 6769 vlvf ^= vlvf_mask; 6770 6771 /* if other pools are present, just remove ourselves */ 6772 if (vlvf & pool_mask) 6773 goto update_vlvfb; 6774 6775 /* if PF is present, leave VFTA */ 6776 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6777 goto update_vlvf; 6778 6779 vid = vlvf & E1000_VLVF_VLANID_MASK; 6780 vfta_mask = BIT(vid % 32); 6781 6782 /* clear bit from VFTA */ 6783 vfta = adapter->shadow_vfta[vid / 32]; 6784 if (vfta & vfta_mask) 6785 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6786 update_vlvf: 6787 /* clear pool selection enable */ 6788 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6789 vlvf &= E1000_VLVF_POOLSEL_MASK; 6790 else 6791 vlvf = 0; 6792 update_vlvfb: 6793 /* clear pool bits */ 6794 wr32(E1000_VLVF(i), vlvf); 6795 } 6796 } 6797 6798 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6799 { 6800 u32 vlvf; 6801 int idx; 6802 6803 /* short cut the special case */ 6804 if (vlan == 0) 6805 return 0; 6806 6807 /* Search for the VLAN id in the VLVF entries */ 6808 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6809 vlvf = rd32(E1000_VLVF(idx)); 6810 if ((vlvf & VLAN_VID_MASK) == vlan) 6811 break; 6812 } 6813 6814 return idx; 6815 } 6816 6817 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6818 { 6819 struct e1000_hw *hw = &adapter->hw; 6820 u32 bits, pf_id; 6821 int idx; 6822 6823 idx = igb_find_vlvf_entry(hw, vid); 6824 if (!idx) 6825 return; 6826 6827 /* See if any other pools are set for this VLAN filter 6828 * entry other than the PF. 6829 */ 6830 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6831 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6832 bits &= rd32(E1000_VLVF(idx)); 6833 6834 /* Disable the filter so this falls into the default pool. */ 6835 if (!bits) { 6836 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6837 wr32(E1000_VLVF(idx), BIT(pf_id)); 6838 else 6839 wr32(E1000_VLVF(idx), 0); 6840 } 6841 } 6842 6843 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6844 bool add, u32 vf) 6845 { 6846 int pf_id = adapter->vfs_allocated_count; 6847 struct e1000_hw *hw = &adapter->hw; 6848 int err; 6849 6850 /* If VLAN overlaps with one the PF is currently monitoring make 6851 * sure that we are able to allocate a VLVF entry. This may be 6852 * redundant but it guarantees PF will maintain visibility to 6853 * the VLAN. 6854 */ 6855 if (add && test_bit(vid, adapter->active_vlans)) { 6856 err = igb_vfta_set(hw, vid, pf_id, true, false); 6857 if (err) 6858 return err; 6859 } 6860 6861 err = igb_vfta_set(hw, vid, vf, add, false); 6862 6863 if (add && !err) 6864 return err; 6865 6866 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6867 * we may need to drop the PF pool bit in order to allow us to free 6868 * up the VLVF resources. 6869 */ 6870 if (test_bit(vid, adapter->active_vlans) || 6871 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6872 igb_update_pf_vlvf(adapter, vid); 6873 6874 return err; 6875 } 6876 6877 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6878 { 6879 struct e1000_hw *hw = &adapter->hw; 6880 6881 if (vid) 6882 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6883 else 6884 wr32(E1000_VMVIR(vf), 0); 6885 } 6886 6887 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6888 u16 vlan, u8 qos) 6889 { 6890 int err; 6891 6892 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6893 if (err) 6894 return err; 6895 6896 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6897 igb_set_vmolr(adapter, vf, !vlan); 6898 6899 /* revoke access to previous VLAN */ 6900 if (vlan != adapter->vf_data[vf].pf_vlan) 6901 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6902 false, vf); 6903 6904 adapter->vf_data[vf].pf_vlan = vlan; 6905 adapter->vf_data[vf].pf_qos = qos; 6906 igb_set_vf_vlan_strip(adapter, vf, true); 6907 dev_info(&adapter->pdev->dev, 6908 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6909 if (test_bit(__IGB_DOWN, &adapter->state)) { 6910 dev_warn(&adapter->pdev->dev, 6911 "The VF VLAN has been set, but the PF device is not up.\n"); 6912 dev_warn(&adapter->pdev->dev, 6913 "Bring the PF device up before attempting to use the VF device.\n"); 6914 } 6915 6916 return err; 6917 } 6918 6919 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6920 { 6921 /* Restore tagless access via VLAN 0 */ 6922 igb_set_vf_vlan(adapter, 0, true, vf); 6923 6924 igb_set_vmvir(adapter, 0, vf); 6925 igb_set_vmolr(adapter, vf, true); 6926 6927 /* Remove any PF assigned VLAN */ 6928 if (adapter->vf_data[vf].pf_vlan) 6929 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6930 false, vf); 6931 6932 adapter->vf_data[vf].pf_vlan = 0; 6933 adapter->vf_data[vf].pf_qos = 0; 6934 igb_set_vf_vlan_strip(adapter, vf, false); 6935 6936 return 0; 6937 } 6938 6939 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6940 u16 vlan, u8 qos, __be16 vlan_proto) 6941 { 6942 struct igb_adapter *adapter = netdev_priv(netdev); 6943 6944 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6945 return -EINVAL; 6946 6947 if (vlan_proto != htons(ETH_P_8021Q)) 6948 return -EPROTONOSUPPORT; 6949 6950 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6951 igb_disable_port_vlan(adapter, vf); 6952 } 6953 6954 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6955 { 6956 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6957 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6958 int ret; 6959 6960 if (adapter->vf_data[vf].pf_vlan) 6961 return -1; 6962 6963 /* VLAN 0 is a special case, don't allow it to be removed */ 6964 if (!vid && !add) 6965 return 0; 6966 6967 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6968 if (!ret) 6969 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6970 return ret; 6971 } 6972 6973 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6974 { 6975 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6976 6977 /* clear flags - except flag that indicates PF has set the MAC */ 6978 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6979 vf_data->last_nack = jiffies; 6980 6981 /* reset vlans for device */ 6982 igb_clear_vf_vfta(adapter, vf); 6983 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6984 igb_set_vmvir(adapter, vf_data->pf_vlan | 6985 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6986 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6987 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6988 6989 /* reset multicast table array for vf */ 6990 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6991 6992 /* Flush and reset the mta with the new values */ 6993 igb_set_rx_mode(adapter->netdev); 6994 } 6995 6996 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6997 { 6998 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6999 7000 /* clear mac address as we were hotplug removed/added */ 7001 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7002 eth_zero_addr(vf_mac); 7003 7004 /* process remaining reset events */ 7005 igb_vf_reset(adapter, vf); 7006 } 7007 7008 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7009 { 7010 struct e1000_hw *hw = &adapter->hw; 7011 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7012 u32 reg, msgbuf[3]; 7013 u8 *addr = (u8 *)(&msgbuf[1]); 7014 7015 /* process all the same items cleared in a function level reset */ 7016 igb_vf_reset(adapter, vf); 7017 7018 /* set vf mac address */ 7019 igb_set_vf_mac(adapter, vf, vf_mac); 7020 7021 /* enable transmit and receive for vf */ 7022 reg = rd32(E1000_VFTE); 7023 wr32(E1000_VFTE, reg | BIT(vf)); 7024 reg = rd32(E1000_VFRE); 7025 wr32(E1000_VFRE, reg | BIT(vf)); 7026 7027 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7028 7029 /* reply to reset with ack and vf mac address */ 7030 if (!is_zero_ether_addr(vf_mac)) { 7031 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7032 memcpy(addr, vf_mac, ETH_ALEN); 7033 } else { 7034 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7035 } 7036 igb_write_mbx(hw, msgbuf, 3, vf); 7037 } 7038 7039 static void igb_flush_mac_table(struct igb_adapter *adapter) 7040 { 7041 struct e1000_hw *hw = &adapter->hw; 7042 int i; 7043 7044 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7045 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7046 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7047 adapter->mac_table[i].queue = 0; 7048 igb_rar_set_index(adapter, i); 7049 } 7050 } 7051 7052 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7053 { 7054 struct e1000_hw *hw = &adapter->hw; 7055 /* do not count rar entries reserved for VFs MAC addresses */ 7056 int rar_entries = hw->mac.rar_entry_count - 7057 adapter->vfs_allocated_count; 7058 int i, count = 0; 7059 7060 for (i = 0; i < rar_entries; i++) { 7061 /* do not count default entries */ 7062 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7063 continue; 7064 7065 /* do not count "in use" entries for different queues */ 7066 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7067 (adapter->mac_table[i].queue != queue)) 7068 continue; 7069 7070 count++; 7071 } 7072 7073 return count; 7074 } 7075 7076 /* Set default MAC address for the PF in the first RAR entry */ 7077 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7078 { 7079 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7080 7081 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7082 mac_table->queue = adapter->vfs_allocated_count; 7083 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7084 7085 igb_rar_set_index(adapter, 0); 7086 } 7087 7088 /* If the filter to be added and an already existing filter express 7089 * the same address and address type, it should be possible to only 7090 * override the other configurations, for example the queue to steer 7091 * traffic. 7092 */ 7093 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7094 const u8 *addr, const u8 flags) 7095 { 7096 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7097 return true; 7098 7099 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7100 (flags & IGB_MAC_STATE_SRC_ADDR)) 7101 return false; 7102 7103 if (!ether_addr_equal(addr, entry->addr)) 7104 return false; 7105 7106 return true; 7107 } 7108 7109 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7110 * 'flags' is used to indicate what kind of match is made, match is by 7111 * default for the destination address, if matching by source address 7112 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7113 */ 7114 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7115 const u8 *addr, const u8 queue, 7116 const u8 flags) 7117 { 7118 struct e1000_hw *hw = &adapter->hw; 7119 int rar_entries = hw->mac.rar_entry_count - 7120 adapter->vfs_allocated_count; 7121 int i; 7122 7123 if (is_zero_ether_addr(addr)) 7124 return -EINVAL; 7125 7126 /* Search for the first empty entry in the MAC table. 7127 * Do not touch entries at the end of the table reserved for the VF MAC 7128 * addresses. 7129 */ 7130 for (i = 0; i < rar_entries; i++) { 7131 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7132 addr, flags)) 7133 continue; 7134 7135 ether_addr_copy(adapter->mac_table[i].addr, addr); 7136 adapter->mac_table[i].queue = queue; 7137 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7138 7139 igb_rar_set_index(adapter, i); 7140 return i; 7141 } 7142 7143 return -ENOSPC; 7144 } 7145 7146 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7147 const u8 queue) 7148 { 7149 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7150 } 7151 7152 /* Remove a MAC filter for 'addr' directing matching traffic to 7153 * 'queue', 'flags' is used to indicate what kind of match need to be 7154 * removed, match is by default for the destination address, if 7155 * matching by source address is to be removed the flag 7156 * IGB_MAC_STATE_SRC_ADDR can be used. 7157 */ 7158 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7159 const u8 *addr, const u8 queue, 7160 const u8 flags) 7161 { 7162 struct e1000_hw *hw = &adapter->hw; 7163 int rar_entries = hw->mac.rar_entry_count - 7164 adapter->vfs_allocated_count; 7165 int i; 7166 7167 if (is_zero_ether_addr(addr)) 7168 return -EINVAL; 7169 7170 /* Search for matching entry in the MAC table based on given address 7171 * and queue. Do not touch entries at the end of the table reserved 7172 * for the VF MAC addresses. 7173 */ 7174 for (i = 0; i < rar_entries; i++) { 7175 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7176 continue; 7177 if ((adapter->mac_table[i].state & flags) != flags) 7178 continue; 7179 if (adapter->mac_table[i].queue != queue) 7180 continue; 7181 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7182 continue; 7183 7184 /* When a filter for the default address is "deleted", 7185 * we return it to its initial configuration 7186 */ 7187 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7188 adapter->mac_table[i].state = 7189 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7190 adapter->mac_table[i].queue = 7191 adapter->vfs_allocated_count; 7192 } else { 7193 adapter->mac_table[i].state = 0; 7194 adapter->mac_table[i].queue = 0; 7195 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7196 } 7197 7198 igb_rar_set_index(adapter, i); 7199 return 0; 7200 } 7201 7202 return -ENOENT; 7203 } 7204 7205 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7206 const u8 queue) 7207 { 7208 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7209 } 7210 7211 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7212 const u8 *addr, u8 queue, u8 flags) 7213 { 7214 struct e1000_hw *hw = &adapter->hw; 7215 7216 /* In theory, this should be supported on 82575 as well, but 7217 * that part wasn't easily accessible during development. 7218 */ 7219 if (hw->mac.type != e1000_i210) 7220 return -EOPNOTSUPP; 7221 7222 return igb_add_mac_filter_flags(adapter, addr, queue, 7223 IGB_MAC_STATE_QUEUE_STEERING | flags); 7224 } 7225 7226 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7227 const u8 *addr, u8 queue, u8 flags) 7228 { 7229 return igb_del_mac_filter_flags(adapter, addr, queue, 7230 IGB_MAC_STATE_QUEUE_STEERING | flags); 7231 } 7232 7233 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7234 { 7235 struct igb_adapter *adapter = netdev_priv(netdev); 7236 int ret; 7237 7238 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7239 7240 return min_t(int, ret, 0); 7241 } 7242 7243 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7244 { 7245 struct igb_adapter *adapter = netdev_priv(netdev); 7246 7247 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7248 7249 return 0; 7250 } 7251 7252 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7253 const u32 info, const u8 *addr) 7254 { 7255 struct pci_dev *pdev = adapter->pdev; 7256 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7257 struct list_head *pos; 7258 struct vf_mac_filter *entry = NULL; 7259 int ret = 0; 7260 7261 switch (info) { 7262 case E1000_VF_MAC_FILTER_CLR: 7263 /* remove all unicast MAC filters related to the current VF */ 7264 list_for_each(pos, &adapter->vf_macs.l) { 7265 entry = list_entry(pos, struct vf_mac_filter, l); 7266 if (entry->vf == vf) { 7267 entry->vf = -1; 7268 entry->free = true; 7269 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7270 } 7271 } 7272 break; 7273 case E1000_VF_MAC_FILTER_ADD: 7274 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7275 !vf_data->trusted) { 7276 dev_warn(&pdev->dev, 7277 "VF %d requested MAC filter but is administratively denied\n", 7278 vf); 7279 return -EINVAL; 7280 } 7281 if (!is_valid_ether_addr(addr)) { 7282 dev_warn(&pdev->dev, 7283 "VF %d attempted to set invalid MAC filter\n", 7284 vf); 7285 return -EINVAL; 7286 } 7287 7288 /* try to find empty slot in the list */ 7289 list_for_each(pos, &adapter->vf_macs.l) { 7290 entry = list_entry(pos, struct vf_mac_filter, l); 7291 if (entry->free) 7292 break; 7293 } 7294 7295 if (entry && entry->free) { 7296 entry->free = false; 7297 entry->vf = vf; 7298 ether_addr_copy(entry->vf_mac, addr); 7299 7300 ret = igb_add_mac_filter(adapter, addr, vf); 7301 ret = min_t(int, ret, 0); 7302 } else { 7303 ret = -ENOSPC; 7304 } 7305 7306 if (ret == -ENOSPC) 7307 dev_warn(&pdev->dev, 7308 "VF %d has requested MAC filter but there is no space for it\n", 7309 vf); 7310 break; 7311 default: 7312 ret = -EINVAL; 7313 break; 7314 } 7315 7316 return ret; 7317 } 7318 7319 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7320 { 7321 struct pci_dev *pdev = adapter->pdev; 7322 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7323 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7324 7325 /* The VF MAC Address is stored in a packed array of bytes 7326 * starting at the second 32 bit word of the msg array 7327 */ 7328 unsigned char *addr = (unsigned char *)&msg[1]; 7329 int ret = 0; 7330 7331 if (!info) { 7332 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7333 !vf_data->trusted) { 7334 dev_warn(&pdev->dev, 7335 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7336 vf); 7337 return -EINVAL; 7338 } 7339 7340 if (!is_valid_ether_addr(addr)) { 7341 dev_warn(&pdev->dev, 7342 "VF %d attempted to set invalid MAC\n", 7343 vf); 7344 return -EINVAL; 7345 } 7346 7347 ret = igb_set_vf_mac(adapter, vf, addr); 7348 } else { 7349 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7350 } 7351 7352 return ret; 7353 } 7354 7355 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7356 { 7357 struct e1000_hw *hw = &adapter->hw; 7358 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7359 u32 msg = E1000_VT_MSGTYPE_NACK; 7360 7361 /* if device isn't clear to send it shouldn't be reading either */ 7362 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7363 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7364 igb_write_mbx(hw, &msg, 1, vf); 7365 vf_data->last_nack = jiffies; 7366 } 7367 } 7368 7369 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7370 { 7371 struct pci_dev *pdev = adapter->pdev; 7372 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7373 struct e1000_hw *hw = &adapter->hw; 7374 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7375 s32 retval; 7376 7377 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7378 7379 if (retval) { 7380 /* if receive failed revoke VF CTS stats and restart init */ 7381 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7382 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7383 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7384 goto unlock; 7385 goto out; 7386 } 7387 7388 /* this is a message we already processed, do nothing */ 7389 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7390 goto unlock; 7391 7392 /* until the vf completes a reset it should not be 7393 * allowed to start any configuration. 7394 */ 7395 if (msgbuf[0] == E1000_VF_RESET) { 7396 /* unlocks mailbox */ 7397 igb_vf_reset_msg(adapter, vf); 7398 return; 7399 } 7400 7401 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7402 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7403 goto unlock; 7404 retval = -1; 7405 goto out; 7406 } 7407 7408 switch ((msgbuf[0] & 0xFFFF)) { 7409 case E1000_VF_SET_MAC_ADDR: 7410 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7411 break; 7412 case E1000_VF_SET_PROMISC: 7413 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7414 break; 7415 case E1000_VF_SET_MULTICAST: 7416 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7417 break; 7418 case E1000_VF_SET_LPE: 7419 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7420 break; 7421 case E1000_VF_SET_VLAN: 7422 retval = -1; 7423 if (vf_data->pf_vlan) 7424 dev_warn(&pdev->dev, 7425 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7426 vf); 7427 else 7428 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7429 break; 7430 default: 7431 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7432 retval = -1; 7433 break; 7434 } 7435 7436 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7437 out: 7438 /* notify the VF of the results of what it sent us */ 7439 if (retval) 7440 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7441 else 7442 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7443 7444 /* unlocks mailbox */ 7445 igb_write_mbx(hw, msgbuf, 1, vf); 7446 return; 7447 7448 unlock: 7449 igb_unlock_mbx(hw, vf); 7450 } 7451 7452 static void igb_msg_task(struct igb_adapter *adapter) 7453 { 7454 struct e1000_hw *hw = &adapter->hw; 7455 u32 vf; 7456 7457 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7458 /* process any reset requests */ 7459 if (!igb_check_for_rst(hw, vf)) 7460 igb_vf_reset_event(adapter, vf); 7461 7462 /* process any messages pending */ 7463 if (!igb_check_for_msg(hw, vf)) 7464 igb_rcv_msg_from_vf(adapter, vf); 7465 7466 /* process any acks */ 7467 if (!igb_check_for_ack(hw, vf)) 7468 igb_rcv_ack_from_vf(adapter, vf); 7469 } 7470 } 7471 7472 /** 7473 * igb_set_uta - Set unicast filter table address 7474 * @adapter: board private structure 7475 * @set: boolean indicating if we are setting or clearing bits 7476 * 7477 * The unicast table address is a register array of 32-bit registers. 7478 * The table is meant to be used in a way similar to how the MTA is used 7479 * however due to certain limitations in the hardware it is necessary to 7480 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7481 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7482 **/ 7483 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7484 { 7485 struct e1000_hw *hw = &adapter->hw; 7486 u32 uta = set ? ~0 : 0; 7487 int i; 7488 7489 /* we only need to do this if VMDq is enabled */ 7490 if (!adapter->vfs_allocated_count) 7491 return; 7492 7493 for (i = hw->mac.uta_reg_count; i--;) 7494 array_wr32(E1000_UTA, i, uta); 7495 } 7496 7497 /** 7498 * igb_intr_msi - Interrupt Handler 7499 * @irq: interrupt number 7500 * @data: pointer to a network interface device structure 7501 **/ 7502 static irqreturn_t igb_intr_msi(int irq, void *data) 7503 { 7504 struct igb_adapter *adapter = data; 7505 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7506 struct e1000_hw *hw = &adapter->hw; 7507 /* read ICR disables interrupts using IAM */ 7508 u32 icr = rd32(E1000_ICR); 7509 7510 igb_write_itr(q_vector); 7511 7512 if (icr & E1000_ICR_DRSTA) 7513 schedule_work(&adapter->reset_task); 7514 7515 if (icr & E1000_ICR_DOUTSYNC) { 7516 /* HW is reporting DMA is out of sync */ 7517 adapter->stats.doosync++; 7518 } 7519 7520 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7521 hw->mac.get_link_status = 1; 7522 if (!test_bit(__IGB_DOWN, &adapter->state)) 7523 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7524 } 7525 7526 if (icr & E1000_ICR_TS) 7527 igb_tsync_interrupt(adapter); 7528 7529 napi_schedule(&q_vector->napi); 7530 7531 return IRQ_HANDLED; 7532 } 7533 7534 /** 7535 * igb_intr - Legacy Interrupt Handler 7536 * @irq: interrupt number 7537 * @data: pointer to a network interface device structure 7538 **/ 7539 static irqreturn_t igb_intr(int irq, void *data) 7540 { 7541 struct igb_adapter *adapter = data; 7542 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7543 struct e1000_hw *hw = &adapter->hw; 7544 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7545 * need for the IMC write 7546 */ 7547 u32 icr = rd32(E1000_ICR); 7548 7549 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7550 * not set, then the adapter didn't send an interrupt 7551 */ 7552 if (!(icr & E1000_ICR_INT_ASSERTED)) 7553 return IRQ_NONE; 7554 7555 igb_write_itr(q_vector); 7556 7557 if (icr & E1000_ICR_DRSTA) 7558 schedule_work(&adapter->reset_task); 7559 7560 if (icr & E1000_ICR_DOUTSYNC) { 7561 /* HW is reporting DMA is out of sync */ 7562 adapter->stats.doosync++; 7563 } 7564 7565 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7566 hw->mac.get_link_status = 1; 7567 /* guard against interrupt when we're going down */ 7568 if (!test_bit(__IGB_DOWN, &adapter->state)) 7569 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7570 } 7571 7572 if (icr & E1000_ICR_TS) 7573 igb_tsync_interrupt(adapter); 7574 7575 napi_schedule(&q_vector->napi); 7576 7577 return IRQ_HANDLED; 7578 } 7579 7580 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7581 { 7582 struct igb_adapter *adapter = q_vector->adapter; 7583 struct e1000_hw *hw = &adapter->hw; 7584 7585 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7586 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7587 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7588 igb_set_itr(q_vector); 7589 else 7590 igb_update_ring_itr(q_vector); 7591 } 7592 7593 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7594 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7595 wr32(E1000_EIMS, q_vector->eims_value); 7596 else 7597 igb_irq_enable(adapter); 7598 } 7599 } 7600 7601 /** 7602 * igb_poll - NAPI Rx polling callback 7603 * @napi: napi polling structure 7604 * @budget: count of how many packets we should handle 7605 **/ 7606 static int igb_poll(struct napi_struct *napi, int budget) 7607 { 7608 struct igb_q_vector *q_vector = container_of(napi, 7609 struct igb_q_vector, 7610 napi); 7611 bool clean_complete = true; 7612 int work_done = 0; 7613 7614 #ifdef CONFIG_IGB_DCA 7615 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7616 igb_update_dca(q_vector); 7617 #endif 7618 if (q_vector->tx.ring) 7619 clean_complete = igb_clean_tx_irq(q_vector, budget); 7620 7621 if (q_vector->rx.ring) { 7622 int cleaned = igb_clean_rx_irq(q_vector, budget); 7623 7624 work_done += cleaned; 7625 if (cleaned >= budget) 7626 clean_complete = false; 7627 } 7628 7629 /* If all work not completed, return budget and keep polling */ 7630 if (!clean_complete) 7631 return budget; 7632 7633 /* If not enough Rx work done, exit the polling mode */ 7634 napi_complete_done(napi, work_done); 7635 igb_ring_irq_enable(q_vector); 7636 7637 return 0; 7638 } 7639 7640 /** 7641 * igb_clean_tx_irq - Reclaim resources after transmit completes 7642 * @q_vector: pointer to q_vector containing needed info 7643 * @napi_budget: Used to determine if we are in netpoll 7644 * 7645 * returns true if ring is completely cleaned 7646 **/ 7647 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7648 { 7649 struct igb_adapter *adapter = q_vector->adapter; 7650 struct igb_ring *tx_ring = q_vector->tx.ring; 7651 struct igb_tx_buffer *tx_buffer; 7652 union e1000_adv_tx_desc *tx_desc; 7653 unsigned int total_bytes = 0, total_packets = 0; 7654 unsigned int budget = q_vector->tx.work_limit; 7655 unsigned int i = tx_ring->next_to_clean; 7656 7657 if (test_bit(__IGB_DOWN, &adapter->state)) 7658 return true; 7659 7660 tx_buffer = &tx_ring->tx_buffer_info[i]; 7661 tx_desc = IGB_TX_DESC(tx_ring, i); 7662 i -= tx_ring->count; 7663 7664 do { 7665 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7666 7667 /* if next_to_watch is not set then there is no work pending */ 7668 if (!eop_desc) 7669 break; 7670 7671 /* prevent any other reads prior to eop_desc */ 7672 smp_rmb(); 7673 7674 /* if DD is not set pending work has not been completed */ 7675 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7676 break; 7677 7678 /* clear next_to_watch to prevent false hangs */ 7679 tx_buffer->next_to_watch = NULL; 7680 7681 /* update the statistics for this packet */ 7682 total_bytes += tx_buffer->bytecount; 7683 total_packets += tx_buffer->gso_segs; 7684 7685 /* free the skb */ 7686 napi_consume_skb(tx_buffer->skb, napi_budget); 7687 7688 /* unmap skb header data */ 7689 dma_unmap_single(tx_ring->dev, 7690 dma_unmap_addr(tx_buffer, dma), 7691 dma_unmap_len(tx_buffer, len), 7692 DMA_TO_DEVICE); 7693 7694 /* clear tx_buffer data */ 7695 dma_unmap_len_set(tx_buffer, len, 0); 7696 7697 /* clear last DMA location and unmap remaining buffers */ 7698 while (tx_desc != eop_desc) { 7699 tx_buffer++; 7700 tx_desc++; 7701 i++; 7702 if (unlikely(!i)) { 7703 i -= tx_ring->count; 7704 tx_buffer = tx_ring->tx_buffer_info; 7705 tx_desc = IGB_TX_DESC(tx_ring, 0); 7706 } 7707 7708 /* unmap any remaining paged data */ 7709 if (dma_unmap_len(tx_buffer, len)) { 7710 dma_unmap_page(tx_ring->dev, 7711 dma_unmap_addr(tx_buffer, dma), 7712 dma_unmap_len(tx_buffer, len), 7713 DMA_TO_DEVICE); 7714 dma_unmap_len_set(tx_buffer, len, 0); 7715 } 7716 } 7717 7718 /* move us one more past the eop_desc for start of next pkt */ 7719 tx_buffer++; 7720 tx_desc++; 7721 i++; 7722 if (unlikely(!i)) { 7723 i -= tx_ring->count; 7724 tx_buffer = tx_ring->tx_buffer_info; 7725 tx_desc = IGB_TX_DESC(tx_ring, 0); 7726 } 7727 7728 /* issue prefetch for next Tx descriptor */ 7729 prefetch(tx_desc); 7730 7731 /* update budget accounting */ 7732 budget--; 7733 } while (likely(budget)); 7734 7735 netdev_tx_completed_queue(txring_txq(tx_ring), 7736 total_packets, total_bytes); 7737 i += tx_ring->count; 7738 tx_ring->next_to_clean = i; 7739 u64_stats_update_begin(&tx_ring->tx_syncp); 7740 tx_ring->tx_stats.bytes += total_bytes; 7741 tx_ring->tx_stats.packets += total_packets; 7742 u64_stats_update_end(&tx_ring->tx_syncp); 7743 q_vector->tx.total_bytes += total_bytes; 7744 q_vector->tx.total_packets += total_packets; 7745 7746 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7747 struct e1000_hw *hw = &adapter->hw; 7748 7749 /* Detect a transmit hang in hardware, this serializes the 7750 * check with the clearing of time_stamp and movement of i 7751 */ 7752 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7753 if (tx_buffer->next_to_watch && 7754 time_after(jiffies, tx_buffer->time_stamp + 7755 (adapter->tx_timeout_factor * HZ)) && 7756 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7757 7758 /* detected Tx unit hang */ 7759 dev_err(tx_ring->dev, 7760 "Detected Tx Unit Hang\n" 7761 " Tx Queue <%d>\n" 7762 " TDH <%x>\n" 7763 " TDT <%x>\n" 7764 " next_to_use <%x>\n" 7765 " next_to_clean <%x>\n" 7766 "buffer_info[next_to_clean]\n" 7767 " time_stamp <%lx>\n" 7768 " next_to_watch <%p>\n" 7769 " jiffies <%lx>\n" 7770 " desc.status <%x>\n", 7771 tx_ring->queue_index, 7772 rd32(E1000_TDH(tx_ring->reg_idx)), 7773 readl(tx_ring->tail), 7774 tx_ring->next_to_use, 7775 tx_ring->next_to_clean, 7776 tx_buffer->time_stamp, 7777 tx_buffer->next_to_watch, 7778 jiffies, 7779 tx_buffer->next_to_watch->wb.status); 7780 netif_stop_subqueue(tx_ring->netdev, 7781 tx_ring->queue_index); 7782 7783 /* we are about to reset, no point in enabling stuff */ 7784 return true; 7785 } 7786 } 7787 7788 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7789 if (unlikely(total_packets && 7790 netif_carrier_ok(tx_ring->netdev) && 7791 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7792 /* Make sure that anybody stopping the queue after this 7793 * sees the new next_to_clean. 7794 */ 7795 smp_mb(); 7796 if (__netif_subqueue_stopped(tx_ring->netdev, 7797 tx_ring->queue_index) && 7798 !(test_bit(__IGB_DOWN, &adapter->state))) { 7799 netif_wake_subqueue(tx_ring->netdev, 7800 tx_ring->queue_index); 7801 7802 u64_stats_update_begin(&tx_ring->tx_syncp); 7803 tx_ring->tx_stats.restart_queue++; 7804 u64_stats_update_end(&tx_ring->tx_syncp); 7805 } 7806 } 7807 7808 return !!budget; 7809 } 7810 7811 /** 7812 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7813 * @rx_ring: rx descriptor ring to store buffers on 7814 * @old_buff: donor buffer to have page reused 7815 * 7816 * Synchronizes page for reuse by the adapter 7817 **/ 7818 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7819 struct igb_rx_buffer *old_buff) 7820 { 7821 struct igb_rx_buffer *new_buff; 7822 u16 nta = rx_ring->next_to_alloc; 7823 7824 new_buff = &rx_ring->rx_buffer_info[nta]; 7825 7826 /* update, and store next to alloc */ 7827 nta++; 7828 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7829 7830 /* Transfer page from old buffer to new buffer. 7831 * Move each member individually to avoid possible store 7832 * forwarding stalls. 7833 */ 7834 new_buff->dma = old_buff->dma; 7835 new_buff->page = old_buff->page; 7836 new_buff->page_offset = old_buff->page_offset; 7837 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7838 } 7839 7840 static inline bool igb_page_is_reserved(struct page *page) 7841 { 7842 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7843 } 7844 7845 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7846 { 7847 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7848 struct page *page = rx_buffer->page; 7849 7850 /* avoid re-using remote pages */ 7851 if (unlikely(igb_page_is_reserved(page))) 7852 return false; 7853 7854 #if (PAGE_SIZE < 8192) 7855 /* if we are only owner of page we can reuse it */ 7856 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7857 return false; 7858 #else 7859 #define IGB_LAST_OFFSET \ 7860 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7861 7862 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7863 return false; 7864 #endif 7865 7866 /* If we have drained the page fragment pool we need to update 7867 * the pagecnt_bias and page count so that we fully restock the 7868 * number of references the driver holds. 7869 */ 7870 if (unlikely(!pagecnt_bias)) { 7871 page_ref_add(page, USHRT_MAX); 7872 rx_buffer->pagecnt_bias = USHRT_MAX; 7873 } 7874 7875 return true; 7876 } 7877 7878 /** 7879 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7880 * @rx_ring: rx descriptor ring to transact packets on 7881 * @rx_buffer: buffer containing page to add 7882 * @skb: sk_buff to place the data into 7883 * @size: size of buffer to be added 7884 * 7885 * This function will add the data contained in rx_buffer->page to the skb. 7886 **/ 7887 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7888 struct igb_rx_buffer *rx_buffer, 7889 struct sk_buff *skb, 7890 unsigned int size) 7891 { 7892 #if (PAGE_SIZE < 8192) 7893 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7894 #else 7895 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7896 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7897 SKB_DATA_ALIGN(size); 7898 #endif 7899 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7900 rx_buffer->page_offset, size, truesize); 7901 #if (PAGE_SIZE < 8192) 7902 rx_buffer->page_offset ^= truesize; 7903 #else 7904 rx_buffer->page_offset += truesize; 7905 #endif 7906 } 7907 7908 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 7909 struct igb_rx_buffer *rx_buffer, 7910 union e1000_adv_rx_desc *rx_desc, 7911 unsigned int size) 7912 { 7913 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7914 #if (PAGE_SIZE < 8192) 7915 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7916 #else 7917 unsigned int truesize = SKB_DATA_ALIGN(size); 7918 #endif 7919 unsigned int headlen; 7920 struct sk_buff *skb; 7921 7922 /* prefetch first cache line of first page */ 7923 prefetch(va); 7924 #if L1_CACHE_BYTES < 128 7925 prefetch(va + L1_CACHE_BYTES); 7926 #endif 7927 7928 /* allocate a skb to store the frags */ 7929 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 7930 if (unlikely(!skb)) 7931 return NULL; 7932 7933 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 7934 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 7935 va += IGB_TS_HDR_LEN; 7936 size -= IGB_TS_HDR_LEN; 7937 } 7938 7939 /* Determine available headroom for copy */ 7940 headlen = size; 7941 if (headlen > IGB_RX_HDR_LEN) 7942 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7943 7944 /* align pull length to size of long to optimize memcpy performance */ 7945 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7946 7947 /* update all of the pointers */ 7948 size -= headlen; 7949 if (size) { 7950 skb_add_rx_frag(skb, 0, rx_buffer->page, 7951 (va + headlen) - page_address(rx_buffer->page), 7952 size, truesize); 7953 #if (PAGE_SIZE < 8192) 7954 rx_buffer->page_offset ^= truesize; 7955 #else 7956 rx_buffer->page_offset += truesize; 7957 #endif 7958 } else { 7959 rx_buffer->pagecnt_bias++; 7960 } 7961 7962 return skb; 7963 } 7964 7965 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7966 struct igb_rx_buffer *rx_buffer, 7967 union e1000_adv_rx_desc *rx_desc, 7968 unsigned int size) 7969 { 7970 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7971 #if (PAGE_SIZE < 8192) 7972 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7973 #else 7974 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7975 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7976 #endif 7977 struct sk_buff *skb; 7978 7979 /* prefetch first cache line of first page */ 7980 prefetch(va); 7981 #if L1_CACHE_BYTES < 128 7982 prefetch(va + L1_CACHE_BYTES); 7983 #endif 7984 7985 /* build an skb around the page buffer */ 7986 skb = build_skb(va - IGB_SKB_PAD, truesize); 7987 if (unlikely(!skb)) 7988 return NULL; 7989 7990 /* update pointers within the skb to store the data */ 7991 skb_reserve(skb, IGB_SKB_PAD); 7992 __skb_put(skb, size); 7993 7994 /* pull timestamp out of packet data */ 7995 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7996 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7997 __skb_pull(skb, IGB_TS_HDR_LEN); 7998 } 7999 8000 /* update buffer offset */ 8001 #if (PAGE_SIZE < 8192) 8002 rx_buffer->page_offset ^= truesize; 8003 #else 8004 rx_buffer->page_offset += truesize; 8005 #endif 8006 8007 return skb; 8008 } 8009 8010 static inline void igb_rx_checksum(struct igb_ring *ring, 8011 union e1000_adv_rx_desc *rx_desc, 8012 struct sk_buff *skb) 8013 { 8014 skb_checksum_none_assert(skb); 8015 8016 /* Ignore Checksum bit is set */ 8017 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8018 return; 8019 8020 /* Rx checksum disabled via ethtool */ 8021 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8022 return; 8023 8024 /* TCP/UDP checksum error bit is set */ 8025 if (igb_test_staterr(rx_desc, 8026 E1000_RXDEXT_STATERR_TCPE | 8027 E1000_RXDEXT_STATERR_IPE)) { 8028 /* work around errata with sctp packets where the TCPE aka 8029 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8030 * packets, (aka let the stack check the crc32c) 8031 */ 8032 if (!((skb->len == 60) && 8033 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8034 u64_stats_update_begin(&ring->rx_syncp); 8035 ring->rx_stats.csum_err++; 8036 u64_stats_update_end(&ring->rx_syncp); 8037 } 8038 /* let the stack verify checksum errors */ 8039 return; 8040 } 8041 /* It must be a TCP or UDP packet with a valid checksum */ 8042 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8043 E1000_RXD_STAT_UDPCS)) 8044 skb->ip_summed = CHECKSUM_UNNECESSARY; 8045 8046 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8047 le32_to_cpu(rx_desc->wb.upper.status_error)); 8048 } 8049 8050 static inline void igb_rx_hash(struct igb_ring *ring, 8051 union e1000_adv_rx_desc *rx_desc, 8052 struct sk_buff *skb) 8053 { 8054 if (ring->netdev->features & NETIF_F_RXHASH) 8055 skb_set_hash(skb, 8056 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8057 PKT_HASH_TYPE_L3); 8058 } 8059 8060 /** 8061 * igb_is_non_eop - process handling of non-EOP buffers 8062 * @rx_ring: Rx ring being processed 8063 * @rx_desc: Rx descriptor for current buffer 8064 * @skb: current socket buffer containing buffer in progress 8065 * 8066 * This function updates next to clean. If the buffer is an EOP buffer 8067 * this function exits returning false, otherwise it will place the 8068 * sk_buff in the next buffer to be chained and return true indicating 8069 * that this is in fact a non-EOP buffer. 8070 **/ 8071 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8072 union e1000_adv_rx_desc *rx_desc) 8073 { 8074 u32 ntc = rx_ring->next_to_clean + 1; 8075 8076 /* fetch, update, and store next to clean */ 8077 ntc = (ntc < rx_ring->count) ? ntc : 0; 8078 rx_ring->next_to_clean = ntc; 8079 8080 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8081 8082 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8083 return false; 8084 8085 return true; 8086 } 8087 8088 /** 8089 * igb_cleanup_headers - Correct corrupted or empty headers 8090 * @rx_ring: rx descriptor ring packet is being transacted on 8091 * @rx_desc: pointer to the EOP Rx descriptor 8092 * @skb: pointer to current skb being fixed 8093 * 8094 * Address the case where we are pulling data in on pages only 8095 * and as such no data is present in the skb header. 8096 * 8097 * In addition if skb is not at least 60 bytes we need to pad it so that 8098 * it is large enough to qualify as a valid Ethernet frame. 8099 * 8100 * Returns true if an error was encountered and skb was freed. 8101 **/ 8102 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8103 union e1000_adv_rx_desc *rx_desc, 8104 struct sk_buff *skb) 8105 { 8106 if (unlikely((igb_test_staterr(rx_desc, 8107 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8108 struct net_device *netdev = rx_ring->netdev; 8109 if (!(netdev->features & NETIF_F_RXALL)) { 8110 dev_kfree_skb_any(skb); 8111 return true; 8112 } 8113 } 8114 8115 /* if eth_skb_pad returns an error the skb was freed */ 8116 if (eth_skb_pad(skb)) 8117 return true; 8118 8119 return false; 8120 } 8121 8122 /** 8123 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8124 * @rx_ring: rx descriptor ring packet is being transacted on 8125 * @rx_desc: pointer to the EOP Rx descriptor 8126 * @skb: pointer to current skb being populated 8127 * 8128 * This function checks the ring, descriptor, and packet information in 8129 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8130 * other fields within the skb. 8131 **/ 8132 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8133 union e1000_adv_rx_desc *rx_desc, 8134 struct sk_buff *skb) 8135 { 8136 struct net_device *dev = rx_ring->netdev; 8137 8138 igb_rx_hash(rx_ring, rx_desc, skb); 8139 8140 igb_rx_checksum(rx_ring, rx_desc, skb); 8141 8142 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8143 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8144 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8145 8146 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8147 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8148 u16 vid; 8149 8150 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8151 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8152 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8153 else 8154 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8155 8156 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8157 } 8158 8159 skb_record_rx_queue(skb, rx_ring->queue_index); 8160 8161 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8162 } 8163 8164 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8165 const unsigned int size) 8166 { 8167 struct igb_rx_buffer *rx_buffer; 8168 8169 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8170 prefetchw(rx_buffer->page); 8171 8172 /* we are reusing so sync this buffer for CPU use */ 8173 dma_sync_single_range_for_cpu(rx_ring->dev, 8174 rx_buffer->dma, 8175 rx_buffer->page_offset, 8176 size, 8177 DMA_FROM_DEVICE); 8178 8179 rx_buffer->pagecnt_bias--; 8180 8181 return rx_buffer; 8182 } 8183 8184 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8185 struct igb_rx_buffer *rx_buffer) 8186 { 8187 if (igb_can_reuse_rx_page(rx_buffer)) { 8188 /* hand second half of page back to the ring */ 8189 igb_reuse_rx_page(rx_ring, rx_buffer); 8190 } else { 8191 /* We are not reusing the buffer so unmap it and free 8192 * any references we are holding to it 8193 */ 8194 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8195 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8196 IGB_RX_DMA_ATTR); 8197 __page_frag_cache_drain(rx_buffer->page, 8198 rx_buffer->pagecnt_bias); 8199 } 8200 8201 /* clear contents of rx_buffer */ 8202 rx_buffer->page = NULL; 8203 } 8204 8205 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8206 { 8207 struct igb_ring *rx_ring = q_vector->rx.ring; 8208 struct sk_buff *skb = rx_ring->skb; 8209 unsigned int total_bytes = 0, total_packets = 0; 8210 u16 cleaned_count = igb_desc_unused(rx_ring); 8211 8212 while (likely(total_packets < budget)) { 8213 union e1000_adv_rx_desc *rx_desc; 8214 struct igb_rx_buffer *rx_buffer; 8215 unsigned int size; 8216 8217 /* return some buffers to hardware, one at a time is too slow */ 8218 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8219 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8220 cleaned_count = 0; 8221 } 8222 8223 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8224 size = le16_to_cpu(rx_desc->wb.upper.length); 8225 if (!size) 8226 break; 8227 8228 /* This memory barrier is needed to keep us from reading 8229 * any other fields out of the rx_desc until we know the 8230 * descriptor has been written back 8231 */ 8232 dma_rmb(); 8233 8234 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8235 8236 /* retrieve a buffer from the ring */ 8237 if (skb) 8238 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8239 else if (ring_uses_build_skb(rx_ring)) 8240 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 8241 else 8242 skb = igb_construct_skb(rx_ring, rx_buffer, 8243 rx_desc, size); 8244 8245 /* exit if we failed to retrieve a buffer */ 8246 if (!skb) { 8247 rx_ring->rx_stats.alloc_failed++; 8248 rx_buffer->pagecnt_bias++; 8249 break; 8250 } 8251 8252 igb_put_rx_buffer(rx_ring, rx_buffer); 8253 cleaned_count++; 8254 8255 /* fetch next buffer in frame if non-eop */ 8256 if (igb_is_non_eop(rx_ring, rx_desc)) 8257 continue; 8258 8259 /* verify the packet layout is correct */ 8260 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8261 skb = NULL; 8262 continue; 8263 } 8264 8265 /* probably a little skewed due to removing CRC */ 8266 total_bytes += skb->len; 8267 8268 /* populate checksum, timestamp, VLAN, and protocol */ 8269 igb_process_skb_fields(rx_ring, rx_desc, skb); 8270 8271 napi_gro_receive(&q_vector->napi, skb); 8272 8273 /* reset skb pointer */ 8274 skb = NULL; 8275 8276 /* update budget accounting */ 8277 total_packets++; 8278 } 8279 8280 /* place incomplete frames back on ring for completion */ 8281 rx_ring->skb = skb; 8282 8283 u64_stats_update_begin(&rx_ring->rx_syncp); 8284 rx_ring->rx_stats.packets += total_packets; 8285 rx_ring->rx_stats.bytes += total_bytes; 8286 u64_stats_update_end(&rx_ring->rx_syncp); 8287 q_vector->rx.total_packets += total_packets; 8288 q_vector->rx.total_bytes += total_bytes; 8289 8290 if (cleaned_count) 8291 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8292 8293 return total_packets; 8294 } 8295 8296 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8297 { 8298 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8299 } 8300 8301 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8302 struct igb_rx_buffer *bi) 8303 { 8304 struct page *page = bi->page; 8305 dma_addr_t dma; 8306 8307 /* since we are recycling buffers we should seldom need to alloc */ 8308 if (likely(page)) 8309 return true; 8310 8311 /* alloc new page for storage */ 8312 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8313 if (unlikely(!page)) { 8314 rx_ring->rx_stats.alloc_failed++; 8315 return false; 8316 } 8317 8318 /* map page for use */ 8319 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8320 igb_rx_pg_size(rx_ring), 8321 DMA_FROM_DEVICE, 8322 IGB_RX_DMA_ATTR); 8323 8324 /* if mapping failed free memory back to system since 8325 * there isn't much point in holding memory we can't use 8326 */ 8327 if (dma_mapping_error(rx_ring->dev, dma)) { 8328 __free_pages(page, igb_rx_pg_order(rx_ring)); 8329 8330 rx_ring->rx_stats.alloc_failed++; 8331 return false; 8332 } 8333 8334 bi->dma = dma; 8335 bi->page = page; 8336 bi->page_offset = igb_rx_offset(rx_ring); 8337 bi->pagecnt_bias = 1; 8338 8339 return true; 8340 } 8341 8342 /** 8343 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8344 * @adapter: address of board private structure 8345 **/ 8346 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8347 { 8348 union e1000_adv_rx_desc *rx_desc; 8349 struct igb_rx_buffer *bi; 8350 u16 i = rx_ring->next_to_use; 8351 u16 bufsz; 8352 8353 /* nothing to do */ 8354 if (!cleaned_count) 8355 return; 8356 8357 rx_desc = IGB_RX_DESC(rx_ring, i); 8358 bi = &rx_ring->rx_buffer_info[i]; 8359 i -= rx_ring->count; 8360 8361 bufsz = igb_rx_bufsz(rx_ring); 8362 8363 do { 8364 if (!igb_alloc_mapped_page(rx_ring, bi)) 8365 break; 8366 8367 /* sync the buffer for use by the device */ 8368 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8369 bi->page_offset, bufsz, 8370 DMA_FROM_DEVICE); 8371 8372 /* Refresh the desc even if buffer_addrs didn't change 8373 * because each write-back erases this info. 8374 */ 8375 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8376 8377 rx_desc++; 8378 bi++; 8379 i++; 8380 if (unlikely(!i)) { 8381 rx_desc = IGB_RX_DESC(rx_ring, 0); 8382 bi = rx_ring->rx_buffer_info; 8383 i -= rx_ring->count; 8384 } 8385 8386 /* clear the length for the next_to_use descriptor */ 8387 rx_desc->wb.upper.length = 0; 8388 8389 cleaned_count--; 8390 } while (cleaned_count); 8391 8392 i += rx_ring->count; 8393 8394 if (rx_ring->next_to_use != i) { 8395 /* record the next descriptor to use */ 8396 rx_ring->next_to_use = i; 8397 8398 /* update next to alloc since we have filled the ring */ 8399 rx_ring->next_to_alloc = i; 8400 8401 /* Force memory writes to complete before letting h/w 8402 * know there are new descriptors to fetch. (Only 8403 * applicable for weak-ordered memory model archs, 8404 * such as IA-64). 8405 */ 8406 wmb(); 8407 writel(i, rx_ring->tail); 8408 } 8409 } 8410 8411 /** 8412 * igb_mii_ioctl - 8413 * @netdev: 8414 * @ifreq: 8415 * @cmd: 8416 **/ 8417 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8418 { 8419 struct igb_adapter *adapter = netdev_priv(netdev); 8420 struct mii_ioctl_data *data = if_mii(ifr); 8421 8422 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8423 return -EOPNOTSUPP; 8424 8425 switch (cmd) { 8426 case SIOCGMIIPHY: 8427 data->phy_id = adapter->hw.phy.addr; 8428 break; 8429 case SIOCGMIIREG: 8430 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8431 &data->val_out)) 8432 return -EIO; 8433 break; 8434 case SIOCSMIIREG: 8435 default: 8436 return -EOPNOTSUPP; 8437 } 8438 return 0; 8439 } 8440 8441 /** 8442 * igb_ioctl - 8443 * @netdev: 8444 * @ifreq: 8445 * @cmd: 8446 **/ 8447 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8448 { 8449 switch (cmd) { 8450 case SIOCGMIIPHY: 8451 case SIOCGMIIREG: 8452 case SIOCSMIIREG: 8453 return igb_mii_ioctl(netdev, ifr, cmd); 8454 case SIOCGHWTSTAMP: 8455 return igb_ptp_get_ts_config(netdev, ifr); 8456 case SIOCSHWTSTAMP: 8457 return igb_ptp_set_ts_config(netdev, ifr); 8458 default: 8459 return -EOPNOTSUPP; 8460 } 8461 } 8462 8463 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8464 { 8465 struct igb_adapter *adapter = hw->back; 8466 8467 pci_read_config_word(adapter->pdev, reg, value); 8468 } 8469 8470 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8471 { 8472 struct igb_adapter *adapter = hw->back; 8473 8474 pci_write_config_word(adapter->pdev, reg, *value); 8475 } 8476 8477 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8478 { 8479 struct igb_adapter *adapter = hw->back; 8480 8481 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8482 return -E1000_ERR_CONFIG; 8483 8484 return 0; 8485 } 8486 8487 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8488 { 8489 struct igb_adapter *adapter = hw->back; 8490 8491 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8492 return -E1000_ERR_CONFIG; 8493 8494 return 0; 8495 } 8496 8497 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8498 { 8499 struct igb_adapter *adapter = netdev_priv(netdev); 8500 struct e1000_hw *hw = &adapter->hw; 8501 u32 ctrl, rctl; 8502 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8503 8504 if (enable) { 8505 /* enable VLAN tag insert/strip */ 8506 ctrl = rd32(E1000_CTRL); 8507 ctrl |= E1000_CTRL_VME; 8508 wr32(E1000_CTRL, ctrl); 8509 8510 /* Disable CFI check */ 8511 rctl = rd32(E1000_RCTL); 8512 rctl &= ~E1000_RCTL_CFIEN; 8513 wr32(E1000_RCTL, rctl); 8514 } else { 8515 /* disable VLAN tag insert/strip */ 8516 ctrl = rd32(E1000_CTRL); 8517 ctrl &= ~E1000_CTRL_VME; 8518 wr32(E1000_CTRL, ctrl); 8519 } 8520 8521 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8522 } 8523 8524 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8525 __be16 proto, u16 vid) 8526 { 8527 struct igb_adapter *adapter = netdev_priv(netdev); 8528 struct e1000_hw *hw = &adapter->hw; 8529 int pf_id = adapter->vfs_allocated_count; 8530 8531 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8532 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8533 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8534 8535 set_bit(vid, adapter->active_vlans); 8536 8537 return 0; 8538 } 8539 8540 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8541 __be16 proto, u16 vid) 8542 { 8543 struct igb_adapter *adapter = netdev_priv(netdev); 8544 int pf_id = adapter->vfs_allocated_count; 8545 struct e1000_hw *hw = &adapter->hw; 8546 8547 /* remove VID from filter table */ 8548 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8549 igb_vfta_set(hw, vid, pf_id, false, true); 8550 8551 clear_bit(vid, adapter->active_vlans); 8552 8553 return 0; 8554 } 8555 8556 static void igb_restore_vlan(struct igb_adapter *adapter) 8557 { 8558 u16 vid = 1; 8559 8560 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8561 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8562 8563 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8564 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8565 } 8566 8567 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8568 { 8569 struct pci_dev *pdev = adapter->pdev; 8570 struct e1000_mac_info *mac = &adapter->hw.mac; 8571 8572 mac->autoneg = 0; 8573 8574 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8575 * for the switch() below to work 8576 */ 8577 if ((spd & 1) || (dplx & ~1)) 8578 goto err_inval; 8579 8580 /* Fiber NIC's only allow 1000 gbps Full duplex 8581 * and 100Mbps Full duplex for 100baseFx sfp 8582 */ 8583 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8584 switch (spd + dplx) { 8585 case SPEED_10 + DUPLEX_HALF: 8586 case SPEED_10 + DUPLEX_FULL: 8587 case SPEED_100 + DUPLEX_HALF: 8588 goto err_inval; 8589 default: 8590 break; 8591 } 8592 } 8593 8594 switch (spd + dplx) { 8595 case SPEED_10 + DUPLEX_HALF: 8596 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8597 break; 8598 case SPEED_10 + DUPLEX_FULL: 8599 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8600 break; 8601 case SPEED_100 + DUPLEX_HALF: 8602 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8603 break; 8604 case SPEED_100 + DUPLEX_FULL: 8605 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8606 break; 8607 case SPEED_1000 + DUPLEX_FULL: 8608 mac->autoneg = 1; 8609 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8610 break; 8611 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8612 default: 8613 goto err_inval; 8614 } 8615 8616 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8617 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8618 8619 return 0; 8620 8621 err_inval: 8622 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8623 return -EINVAL; 8624 } 8625 8626 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8627 bool runtime) 8628 { 8629 struct net_device *netdev = pci_get_drvdata(pdev); 8630 struct igb_adapter *adapter = netdev_priv(netdev); 8631 struct e1000_hw *hw = &adapter->hw; 8632 u32 ctrl, rctl, status; 8633 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8634 #ifdef CONFIG_PM 8635 int retval = 0; 8636 #endif 8637 8638 rtnl_lock(); 8639 netif_device_detach(netdev); 8640 8641 if (netif_running(netdev)) 8642 __igb_close(netdev, true); 8643 8644 igb_ptp_suspend(adapter); 8645 8646 igb_clear_interrupt_scheme(adapter); 8647 rtnl_unlock(); 8648 8649 #ifdef CONFIG_PM 8650 retval = pci_save_state(pdev); 8651 if (retval) 8652 return retval; 8653 #endif 8654 8655 status = rd32(E1000_STATUS); 8656 if (status & E1000_STATUS_LU) 8657 wufc &= ~E1000_WUFC_LNKC; 8658 8659 if (wufc) { 8660 igb_setup_rctl(adapter); 8661 igb_set_rx_mode(netdev); 8662 8663 /* turn on all-multi mode if wake on multicast is enabled */ 8664 if (wufc & E1000_WUFC_MC) { 8665 rctl = rd32(E1000_RCTL); 8666 rctl |= E1000_RCTL_MPE; 8667 wr32(E1000_RCTL, rctl); 8668 } 8669 8670 ctrl = rd32(E1000_CTRL); 8671 /* advertise wake from D3Cold */ 8672 #define E1000_CTRL_ADVD3WUC 0x00100000 8673 /* phy power management enable */ 8674 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 8675 ctrl |= E1000_CTRL_ADVD3WUC; 8676 wr32(E1000_CTRL, ctrl); 8677 8678 /* Allow time for pending master requests to run */ 8679 igb_disable_pcie_master(hw); 8680 8681 wr32(E1000_WUC, E1000_WUC_PME_EN); 8682 wr32(E1000_WUFC, wufc); 8683 } else { 8684 wr32(E1000_WUC, 0); 8685 wr32(E1000_WUFC, 0); 8686 } 8687 8688 *enable_wake = wufc || adapter->en_mng_pt; 8689 if (!*enable_wake) 8690 igb_power_down_link(adapter); 8691 else 8692 igb_power_up_link(adapter); 8693 8694 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8695 * would have already happened in close and is redundant. 8696 */ 8697 igb_release_hw_control(adapter); 8698 8699 pci_disable_device(pdev); 8700 8701 return 0; 8702 } 8703 8704 static void igb_deliver_wake_packet(struct net_device *netdev) 8705 { 8706 struct igb_adapter *adapter = netdev_priv(netdev); 8707 struct e1000_hw *hw = &adapter->hw; 8708 struct sk_buff *skb; 8709 u32 wupl; 8710 8711 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8712 8713 /* WUPM stores only the first 128 bytes of the wake packet. 8714 * Read the packet only if we have the whole thing. 8715 */ 8716 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8717 return; 8718 8719 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8720 if (!skb) 8721 return; 8722 8723 skb_put(skb, wupl); 8724 8725 /* Ensure reads are 32-bit aligned */ 8726 wupl = roundup(wupl, 4); 8727 8728 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8729 8730 skb->protocol = eth_type_trans(skb, netdev); 8731 netif_rx(skb); 8732 } 8733 8734 static int __maybe_unused igb_suspend(struct device *dev) 8735 { 8736 int retval; 8737 bool wake; 8738 struct pci_dev *pdev = to_pci_dev(dev); 8739 8740 retval = __igb_shutdown(pdev, &wake, 0); 8741 if (retval) 8742 return retval; 8743 8744 if (wake) { 8745 pci_prepare_to_sleep(pdev); 8746 } else { 8747 pci_wake_from_d3(pdev, false); 8748 pci_set_power_state(pdev, PCI_D3hot); 8749 } 8750 8751 return 0; 8752 } 8753 8754 static int __maybe_unused igb_resume(struct device *dev) 8755 { 8756 struct pci_dev *pdev = to_pci_dev(dev); 8757 struct net_device *netdev = pci_get_drvdata(pdev); 8758 struct igb_adapter *adapter = netdev_priv(netdev); 8759 struct e1000_hw *hw = &adapter->hw; 8760 u32 err, val; 8761 8762 pci_set_power_state(pdev, PCI_D0); 8763 pci_restore_state(pdev); 8764 pci_save_state(pdev); 8765 8766 if (!pci_device_is_present(pdev)) 8767 return -ENODEV; 8768 err = pci_enable_device_mem(pdev); 8769 if (err) { 8770 dev_err(&pdev->dev, 8771 "igb: Cannot enable PCI device from suspend\n"); 8772 return err; 8773 } 8774 pci_set_master(pdev); 8775 8776 pci_enable_wake(pdev, PCI_D3hot, 0); 8777 pci_enable_wake(pdev, PCI_D3cold, 0); 8778 8779 if (igb_init_interrupt_scheme(adapter, true)) { 8780 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8781 return -ENOMEM; 8782 } 8783 8784 igb_reset(adapter); 8785 8786 /* let the f/w know that the h/w is now under the control of the 8787 * driver. 8788 */ 8789 igb_get_hw_control(adapter); 8790 8791 val = rd32(E1000_WUS); 8792 if (val & WAKE_PKT_WUS) 8793 igb_deliver_wake_packet(netdev); 8794 8795 wr32(E1000_WUS, ~0); 8796 8797 rtnl_lock(); 8798 if (!err && netif_running(netdev)) 8799 err = __igb_open(netdev, true); 8800 8801 if (!err) 8802 netif_device_attach(netdev); 8803 rtnl_unlock(); 8804 8805 return err; 8806 } 8807 8808 static int __maybe_unused igb_runtime_idle(struct device *dev) 8809 { 8810 struct pci_dev *pdev = to_pci_dev(dev); 8811 struct net_device *netdev = pci_get_drvdata(pdev); 8812 struct igb_adapter *adapter = netdev_priv(netdev); 8813 8814 if (!igb_has_link(adapter)) 8815 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8816 8817 return -EBUSY; 8818 } 8819 8820 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8821 { 8822 struct pci_dev *pdev = to_pci_dev(dev); 8823 int retval; 8824 bool wake; 8825 8826 retval = __igb_shutdown(pdev, &wake, 1); 8827 if (retval) 8828 return retval; 8829 8830 if (wake) { 8831 pci_prepare_to_sleep(pdev); 8832 } else { 8833 pci_wake_from_d3(pdev, false); 8834 pci_set_power_state(pdev, PCI_D3hot); 8835 } 8836 8837 return 0; 8838 } 8839 8840 static int __maybe_unused igb_runtime_resume(struct device *dev) 8841 { 8842 return igb_resume(dev); 8843 } 8844 8845 static void igb_shutdown(struct pci_dev *pdev) 8846 { 8847 bool wake; 8848 8849 __igb_shutdown(pdev, &wake, 0); 8850 8851 if (system_state == SYSTEM_POWER_OFF) { 8852 pci_wake_from_d3(pdev, wake); 8853 pci_set_power_state(pdev, PCI_D3hot); 8854 } 8855 } 8856 8857 #ifdef CONFIG_PCI_IOV 8858 static int igb_sriov_reinit(struct pci_dev *dev) 8859 { 8860 struct net_device *netdev = pci_get_drvdata(dev); 8861 struct igb_adapter *adapter = netdev_priv(netdev); 8862 struct pci_dev *pdev = adapter->pdev; 8863 8864 rtnl_lock(); 8865 8866 if (netif_running(netdev)) 8867 igb_close(netdev); 8868 else 8869 igb_reset(adapter); 8870 8871 igb_clear_interrupt_scheme(adapter); 8872 8873 igb_init_queue_configuration(adapter); 8874 8875 if (igb_init_interrupt_scheme(adapter, true)) { 8876 rtnl_unlock(); 8877 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8878 return -ENOMEM; 8879 } 8880 8881 if (netif_running(netdev)) 8882 igb_open(netdev); 8883 8884 rtnl_unlock(); 8885 8886 return 0; 8887 } 8888 8889 static int igb_pci_disable_sriov(struct pci_dev *dev) 8890 { 8891 int err = igb_disable_sriov(dev); 8892 8893 if (!err) 8894 err = igb_sriov_reinit(dev); 8895 8896 return err; 8897 } 8898 8899 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8900 { 8901 int err = igb_enable_sriov(dev, num_vfs); 8902 8903 if (err) 8904 goto out; 8905 8906 err = igb_sriov_reinit(dev); 8907 if (!err) 8908 return num_vfs; 8909 8910 out: 8911 return err; 8912 } 8913 8914 #endif 8915 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8916 { 8917 #ifdef CONFIG_PCI_IOV 8918 if (num_vfs == 0) 8919 return igb_pci_disable_sriov(dev); 8920 else 8921 return igb_pci_enable_sriov(dev, num_vfs); 8922 #endif 8923 return 0; 8924 } 8925 8926 #ifdef CONFIG_NET_POLL_CONTROLLER 8927 /* Polling 'interrupt' - used by things like netconsole to send skbs 8928 * without having to re-enable interrupts. It's not called while 8929 * the interrupt routine is executing. 8930 */ 8931 static void igb_netpoll(struct net_device *netdev) 8932 { 8933 struct igb_adapter *adapter = netdev_priv(netdev); 8934 struct e1000_hw *hw = &adapter->hw; 8935 struct igb_q_vector *q_vector; 8936 int i; 8937 8938 for (i = 0; i < adapter->num_q_vectors; i++) { 8939 q_vector = adapter->q_vector[i]; 8940 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8941 wr32(E1000_EIMC, q_vector->eims_value); 8942 else 8943 igb_irq_disable(adapter); 8944 napi_schedule(&q_vector->napi); 8945 } 8946 } 8947 #endif /* CONFIG_NET_POLL_CONTROLLER */ 8948 8949 /** 8950 * igb_io_error_detected - called when PCI error is detected 8951 * @pdev: Pointer to PCI device 8952 * @state: The current pci connection state 8953 * 8954 * This function is called after a PCI bus error affecting 8955 * this device has been detected. 8956 **/ 8957 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8958 pci_channel_state_t state) 8959 { 8960 struct net_device *netdev = pci_get_drvdata(pdev); 8961 struct igb_adapter *adapter = netdev_priv(netdev); 8962 8963 netif_device_detach(netdev); 8964 8965 if (state == pci_channel_io_perm_failure) 8966 return PCI_ERS_RESULT_DISCONNECT; 8967 8968 if (netif_running(netdev)) 8969 igb_down(adapter); 8970 pci_disable_device(pdev); 8971 8972 /* Request a slot slot reset. */ 8973 return PCI_ERS_RESULT_NEED_RESET; 8974 } 8975 8976 /** 8977 * igb_io_slot_reset - called after the pci bus has been reset. 8978 * @pdev: Pointer to PCI device 8979 * 8980 * Restart the card from scratch, as if from a cold-boot. Implementation 8981 * resembles the first-half of the igb_resume routine. 8982 **/ 8983 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8984 { 8985 struct net_device *netdev = pci_get_drvdata(pdev); 8986 struct igb_adapter *adapter = netdev_priv(netdev); 8987 struct e1000_hw *hw = &adapter->hw; 8988 pci_ers_result_t result; 8989 int err; 8990 8991 if (pci_enable_device_mem(pdev)) { 8992 dev_err(&pdev->dev, 8993 "Cannot re-enable PCI device after reset.\n"); 8994 result = PCI_ERS_RESULT_DISCONNECT; 8995 } else { 8996 pci_set_master(pdev); 8997 pci_restore_state(pdev); 8998 pci_save_state(pdev); 8999 9000 pci_enable_wake(pdev, PCI_D3hot, 0); 9001 pci_enable_wake(pdev, PCI_D3cold, 0); 9002 9003 /* In case of PCI error, adapter lose its HW address 9004 * so we should re-assign it here. 9005 */ 9006 hw->hw_addr = adapter->io_addr; 9007 9008 igb_reset(adapter); 9009 wr32(E1000_WUS, ~0); 9010 result = PCI_ERS_RESULT_RECOVERED; 9011 } 9012 9013 err = pci_cleanup_aer_uncorrect_error_status(pdev); 9014 if (err) { 9015 dev_err(&pdev->dev, 9016 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 9017 err); 9018 /* non-fatal, continue */ 9019 } 9020 9021 return result; 9022 } 9023 9024 /** 9025 * igb_io_resume - called when traffic can start flowing again. 9026 * @pdev: Pointer to PCI device 9027 * 9028 * This callback is called when the error recovery driver tells us that 9029 * its OK to resume normal operation. Implementation resembles the 9030 * second-half of the igb_resume routine. 9031 */ 9032 static void igb_io_resume(struct pci_dev *pdev) 9033 { 9034 struct net_device *netdev = pci_get_drvdata(pdev); 9035 struct igb_adapter *adapter = netdev_priv(netdev); 9036 9037 if (netif_running(netdev)) { 9038 if (igb_up(adapter)) { 9039 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9040 return; 9041 } 9042 } 9043 9044 netif_device_attach(netdev); 9045 9046 /* let the f/w know that the h/w is now under the control of the 9047 * driver. 9048 */ 9049 igb_get_hw_control(adapter); 9050 } 9051 9052 /** 9053 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9054 * @adapter: Pointer to adapter structure 9055 * @index: Index of the RAR entry which need to be synced with MAC table 9056 **/ 9057 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9058 { 9059 struct e1000_hw *hw = &adapter->hw; 9060 u32 rar_low, rar_high; 9061 u8 *addr = adapter->mac_table[index].addr; 9062 9063 /* HW expects these to be in network order when they are plugged 9064 * into the registers which are little endian. In order to guarantee 9065 * that ordering we need to do an leXX_to_cpup here in order to be 9066 * ready for the byteswap that occurs with writel 9067 */ 9068 rar_low = le32_to_cpup((__le32 *)(addr)); 9069 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9070 9071 /* Indicate to hardware the Address is Valid. */ 9072 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9073 if (is_valid_ether_addr(addr)) 9074 rar_high |= E1000_RAH_AV; 9075 9076 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9077 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9078 9079 switch (hw->mac.type) { 9080 case e1000_82575: 9081 case e1000_i210: 9082 if (adapter->mac_table[index].state & 9083 IGB_MAC_STATE_QUEUE_STEERING) 9084 rar_high |= E1000_RAH_QSEL_ENABLE; 9085 9086 rar_high |= E1000_RAH_POOL_1 * 9087 adapter->mac_table[index].queue; 9088 break; 9089 default: 9090 rar_high |= E1000_RAH_POOL_1 << 9091 adapter->mac_table[index].queue; 9092 break; 9093 } 9094 } 9095 9096 wr32(E1000_RAL(index), rar_low); 9097 wrfl(); 9098 wr32(E1000_RAH(index), rar_high); 9099 wrfl(); 9100 } 9101 9102 static int igb_set_vf_mac(struct igb_adapter *adapter, 9103 int vf, unsigned char *mac_addr) 9104 { 9105 struct e1000_hw *hw = &adapter->hw; 9106 /* VF MAC addresses start at end of receive addresses and moves 9107 * towards the first, as a result a collision should not be possible 9108 */ 9109 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9110 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9111 9112 ether_addr_copy(vf_mac_addr, mac_addr); 9113 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9114 adapter->mac_table[rar_entry].queue = vf; 9115 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9116 igb_rar_set_index(adapter, rar_entry); 9117 9118 return 0; 9119 } 9120 9121 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9122 { 9123 struct igb_adapter *adapter = netdev_priv(netdev); 9124 9125 if (vf >= adapter->vfs_allocated_count) 9126 return -EINVAL; 9127 9128 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9129 * flag and allows to overwrite the MAC via VF netdev. This 9130 * is necessary to allow libvirt a way to restore the original 9131 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9132 * down a VM. 9133 */ 9134 if (is_zero_ether_addr(mac)) { 9135 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9136 dev_info(&adapter->pdev->dev, 9137 "remove administratively set MAC on VF %d\n", 9138 vf); 9139 } else if (is_valid_ether_addr(mac)) { 9140 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9141 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9142 mac, vf); 9143 dev_info(&adapter->pdev->dev, 9144 "Reload the VF driver to make this change effective."); 9145 /* Generate additional warning if PF is down */ 9146 if (test_bit(__IGB_DOWN, &adapter->state)) { 9147 dev_warn(&adapter->pdev->dev, 9148 "The VF MAC address has been set, but the PF device is not up.\n"); 9149 dev_warn(&adapter->pdev->dev, 9150 "Bring the PF device up before attempting to use the VF device.\n"); 9151 } 9152 } else { 9153 return -EINVAL; 9154 } 9155 return igb_set_vf_mac(adapter, vf, mac); 9156 } 9157 9158 static int igb_link_mbps(int internal_link_speed) 9159 { 9160 switch (internal_link_speed) { 9161 case SPEED_100: 9162 return 100; 9163 case SPEED_1000: 9164 return 1000; 9165 default: 9166 return 0; 9167 } 9168 } 9169 9170 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9171 int link_speed) 9172 { 9173 int rf_dec, rf_int; 9174 u32 bcnrc_val; 9175 9176 if (tx_rate != 0) { 9177 /* Calculate the rate factor values to set */ 9178 rf_int = link_speed / tx_rate; 9179 rf_dec = (link_speed - (rf_int * tx_rate)); 9180 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9181 tx_rate; 9182 9183 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9184 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9185 E1000_RTTBCNRC_RF_INT_MASK); 9186 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9187 } else { 9188 bcnrc_val = 0; 9189 } 9190 9191 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9192 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9193 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9194 */ 9195 wr32(E1000_RTTBCNRM, 0x14); 9196 wr32(E1000_RTTBCNRC, bcnrc_val); 9197 } 9198 9199 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9200 { 9201 int actual_link_speed, i; 9202 bool reset_rate = false; 9203 9204 /* VF TX rate limit was not set or not supported */ 9205 if ((adapter->vf_rate_link_speed == 0) || 9206 (adapter->hw.mac.type != e1000_82576)) 9207 return; 9208 9209 actual_link_speed = igb_link_mbps(adapter->link_speed); 9210 if (actual_link_speed != adapter->vf_rate_link_speed) { 9211 reset_rate = true; 9212 adapter->vf_rate_link_speed = 0; 9213 dev_info(&adapter->pdev->dev, 9214 "Link speed has been changed. VF Transmit rate is disabled\n"); 9215 } 9216 9217 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9218 if (reset_rate) 9219 adapter->vf_data[i].tx_rate = 0; 9220 9221 igb_set_vf_rate_limit(&adapter->hw, i, 9222 adapter->vf_data[i].tx_rate, 9223 actual_link_speed); 9224 } 9225 } 9226 9227 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9228 int min_tx_rate, int max_tx_rate) 9229 { 9230 struct igb_adapter *adapter = netdev_priv(netdev); 9231 struct e1000_hw *hw = &adapter->hw; 9232 int actual_link_speed; 9233 9234 if (hw->mac.type != e1000_82576) 9235 return -EOPNOTSUPP; 9236 9237 if (min_tx_rate) 9238 return -EINVAL; 9239 9240 actual_link_speed = igb_link_mbps(adapter->link_speed); 9241 if ((vf >= adapter->vfs_allocated_count) || 9242 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9243 (max_tx_rate < 0) || 9244 (max_tx_rate > actual_link_speed)) 9245 return -EINVAL; 9246 9247 adapter->vf_rate_link_speed = actual_link_speed; 9248 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9249 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9250 9251 return 0; 9252 } 9253 9254 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9255 bool setting) 9256 { 9257 struct igb_adapter *adapter = netdev_priv(netdev); 9258 struct e1000_hw *hw = &adapter->hw; 9259 u32 reg_val, reg_offset; 9260 9261 if (!adapter->vfs_allocated_count) 9262 return -EOPNOTSUPP; 9263 9264 if (vf >= adapter->vfs_allocated_count) 9265 return -EINVAL; 9266 9267 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9268 reg_val = rd32(reg_offset); 9269 if (setting) 9270 reg_val |= (BIT(vf) | 9271 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9272 else 9273 reg_val &= ~(BIT(vf) | 9274 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9275 wr32(reg_offset, reg_val); 9276 9277 adapter->vf_data[vf].spoofchk_enabled = setting; 9278 return 0; 9279 } 9280 9281 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9282 { 9283 struct igb_adapter *adapter = netdev_priv(netdev); 9284 9285 if (vf >= adapter->vfs_allocated_count) 9286 return -EINVAL; 9287 if (adapter->vf_data[vf].trusted == setting) 9288 return 0; 9289 9290 adapter->vf_data[vf].trusted = setting; 9291 9292 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9293 vf, setting ? "" : "not "); 9294 return 0; 9295 } 9296 9297 static int igb_ndo_get_vf_config(struct net_device *netdev, 9298 int vf, struct ifla_vf_info *ivi) 9299 { 9300 struct igb_adapter *adapter = netdev_priv(netdev); 9301 if (vf >= adapter->vfs_allocated_count) 9302 return -EINVAL; 9303 ivi->vf = vf; 9304 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9305 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9306 ivi->min_tx_rate = 0; 9307 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9308 ivi->qos = adapter->vf_data[vf].pf_qos; 9309 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9310 ivi->trusted = adapter->vf_data[vf].trusted; 9311 return 0; 9312 } 9313 9314 static void igb_vmm_control(struct igb_adapter *adapter) 9315 { 9316 struct e1000_hw *hw = &adapter->hw; 9317 u32 reg; 9318 9319 switch (hw->mac.type) { 9320 case e1000_82575: 9321 case e1000_i210: 9322 case e1000_i211: 9323 case e1000_i354: 9324 default: 9325 /* replication is not supported for 82575 */ 9326 return; 9327 case e1000_82576: 9328 /* notify HW that the MAC is adding vlan tags */ 9329 reg = rd32(E1000_DTXCTL); 9330 reg |= E1000_DTXCTL_VLAN_ADDED; 9331 wr32(E1000_DTXCTL, reg); 9332 /* Fall through */ 9333 case e1000_82580: 9334 /* enable replication vlan tag stripping */ 9335 reg = rd32(E1000_RPLOLR); 9336 reg |= E1000_RPLOLR_STRVLAN; 9337 wr32(E1000_RPLOLR, reg); 9338 /* Fall through */ 9339 case e1000_i350: 9340 /* none of the above registers are supported by i350 */ 9341 break; 9342 } 9343 9344 if (adapter->vfs_allocated_count) { 9345 igb_vmdq_set_loopback_pf(hw, true); 9346 igb_vmdq_set_replication_pf(hw, true); 9347 igb_vmdq_set_anti_spoofing_pf(hw, true, 9348 adapter->vfs_allocated_count); 9349 } else { 9350 igb_vmdq_set_loopback_pf(hw, false); 9351 igb_vmdq_set_replication_pf(hw, false); 9352 } 9353 } 9354 9355 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9356 { 9357 struct e1000_hw *hw = &adapter->hw; 9358 u32 dmac_thr; 9359 u16 hwm; 9360 9361 if (hw->mac.type > e1000_82580) { 9362 if (adapter->flags & IGB_FLAG_DMAC) { 9363 u32 reg; 9364 9365 /* force threshold to 0. */ 9366 wr32(E1000_DMCTXTH, 0); 9367 9368 /* DMA Coalescing high water mark needs to be greater 9369 * than the Rx threshold. Set hwm to PBA - max frame 9370 * size in 16B units, capping it at PBA - 6KB. 9371 */ 9372 hwm = 64 * (pba - 6); 9373 reg = rd32(E1000_FCRTC); 9374 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9375 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9376 & E1000_FCRTC_RTH_COAL_MASK); 9377 wr32(E1000_FCRTC, reg); 9378 9379 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9380 * frame size, capping it at PBA - 10KB. 9381 */ 9382 dmac_thr = pba - 10; 9383 reg = rd32(E1000_DMACR); 9384 reg &= ~E1000_DMACR_DMACTHR_MASK; 9385 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9386 & E1000_DMACR_DMACTHR_MASK); 9387 9388 /* transition to L0x or L1 if available..*/ 9389 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9390 9391 /* watchdog timer= +-1000 usec in 32usec intervals */ 9392 reg |= (1000 >> 5); 9393 9394 /* Disable BMC-to-OS Watchdog Enable */ 9395 if (hw->mac.type != e1000_i354) 9396 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9397 9398 wr32(E1000_DMACR, reg); 9399 9400 /* no lower threshold to disable 9401 * coalescing(smart fifb)-UTRESH=0 9402 */ 9403 wr32(E1000_DMCRTRH, 0); 9404 9405 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9406 9407 wr32(E1000_DMCTLX, reg); 9408 9409 /* free space in tx packet buffer to wake from 9410 * DMA coal 9411 */ 9412 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9413 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9414 9415 /* make low power state decision controlled 9416 * by DMA coal 9417 */ 9418 reg = rd32(E1000_PCIEMISC); 9419 reg &= ~E1000_PCIEMISC_LX_DECISION; 9420 wr32(E1000_PCIEMISC, reg); 9421 } /* endif adapter->dmac is not disabled */ 9422 } else if (hw->mac.type == e1000_82580) { 9423 u32 reg = rd32(E1000_PCIEMISC); 9424 9425 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9426 wr32(E1000_DMACR, 0); 9427 } 9428 } 9429 9430 /** 9431 * igb_read_i2c_byte - Reads 8 bit word over I2C 9432 * @hw: pointer to hardware structure 9433 * @byte_offset: byte offset to read 9434 * @dev_addr: device address 9435 * @data: value read 9436 * 9437 * Performs byte read operation over I2C interface at 9438 * a specified device address. 9439 **/ 9440 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9441 u8 dev_addr, u8 *data) 9442 { 9443 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9444 struct i2c_client *this_client = adapter->i2c_client; 9445 s32 status; 9446 u16 swfw_mask = 0; 9447 9448 if (!this_client) 9449 return E1000_ERR_I2C; 9450 9451 swfw_mask = E1000_SWFW_PHY0_SM; 9452 9453 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9454 return E1000_ERR_SWFW_SYNC; 9455 9456 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9457 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9458 9459 if (status < 0) 9460 return E1000_ERR_I2C; 9461 else { 9462 *data = status; 9463 return 0; 9464 } 9465 } 9466 9467 /** 9468 * igb_write_i2c_byte - Writes 8 bit word over I2C 9469 * @hw: pointer to hardware structure 9470 * @byte_offset: byte offset to write 9471 * @dev_addr: device address 9472 * @data: value to write 9473 * 9474 * Performs byte write operation over I2C interface at 9475 * a specified device address. 9476 **/ 9477 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9478 u8 dev_addr, u8 data) 9479 { 9480 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9481 struct i2c_client *this_client = adapter->i2c_client; 9482 s32 status; 9483 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9484 9485 if (!this_client) 9486 return E1000_ERR_I2C; 9487 9488 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9489 return E1000_ERR_SWFW_SYNC; 9490 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9491 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9492 9493 if (status) 9494 return E1000_ERR_I2C; 9495 else 9496 return 0; 9497 9498 } 9499 9500 int igb_reinit_queues(struct igb_adapter *adapter) 9501 { 9502 struct net_device *netdev = adapter->netdev; 9503 struct pci_dev *pdev = adapter->pdev; 9504 int err = 0; 9505 9506 if (netif_running(netdev)) 9507 igb_close(netdev); 9508 9509 igb_reset_interrupt_capability(adapter); 9510 9511 if (igb_init_interrupt_scheme(adapter, true)) { 9512 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9513 return -ENOMEM; 9514 } 9515 9516 if (netif_running(netdev)) 9517 err = igb_open(netdev); 9518 9519 return err; 9520 } 9521 9522 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9523 { 9524 struct igb_nfc_filter *rule; 9525 9526 spin_lock(&adapter->nfc_lock); 9527 9528 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9529 igb_erase_filter(adapter, rule); 9530 9531 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9532 igb_erase_filter(adapter, rule); 9533 9534 spin_unlock(&adapter->nfc_lock); 9535 } 9536 9537 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9538 { 9539 struct igb_nfc_filter *rule; 9540 9541 spin_lock(&adapter->nfc_lock); 9542 9543 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9544 igb_add_filter(adapter, rule); 9545 9546 spin_unlock(&adapter->nfc_lock); 9547 } 9548 /* igb_main.c */ 9549