1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3 
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5 
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/aer.h>
32 #include <linux/prefetch.h>
33 #include <linux/bpf.h>
34 #include <linux/bpf_trace.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/etherdevice.h>
37 #ifdef CONFIG_IGB_DCA
38 #include <linux/dca.h>
39 #endif
40 #include <linux/i2c.h>
41 #include "igb.h"
42 
43 enum queue_mode {
44 	QUEUE_MODE_STRICT_PRIORITY,
45 	QUEUE_MODE_STREAM_RESERVATION,
46 };
47 
48 enum tx_queue_prio {
49 	TX_QUEUE_PRIO_HIGH,
50 	TX_QUEUE_PRIO_LOW,
51 };
52 
53 char igb_driver_name[] = "igb";
54 static const char igb_driver_string[] =
55 				"Intel(R) Gigabit Ethernet Network Driver";
56 static const char igb_copyright[] =
57 				"Copyright (c) 2007-2014 Intel Corporation.";
58 
59 static const struct e1000_info *igb_info_tbl[] = {
60 	[board_82575] = &e1000_82575_info,
61 };
62 
63 static const struct pci_device_id igb_pci_tbl[] = {
64 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
65 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
66 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
67 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
68 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
69 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
70 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
71 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
72 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
73 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
74 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
75 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
76 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
77 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
78 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
79 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
80 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
81 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
82 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
83 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
84 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
85 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
86 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
87 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
88 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
89 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
90 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
91 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
92 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
93 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
94 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
95 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
96 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
97 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
98 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
99 	/* required last entry */
100 	{0, }
101 };
102 
103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
104 
105 static int igb_setup_all_tx_resources(struct igb_adapter *);
106 static int igb_setup_all_rx_resources(struct igb_adapter *);
107 static void igb_free_all_tx_resources(struct igb_adapter *);
108 static void igb_free_all_rx_resources(struct igb_adapter *);
109 static void igb_setup_mrqc(struct igb_adapter *);
110 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
111 static void igb_remove(struct pci_dev *pdev);
112 static int igb_sw_init(struct igb_adapter *);
113 int igb_open(struct net_device *);
114 int igb_close(struct net_device *);
115 static void igb_configure(struct igb_adapter *);
116 static void igb_configure_tx(struct igb_adapter *);
117 static void igb_configure_rx(struct igb_adapter *);
118 static void igb_clean_all_tx_rings(struct igb_adapter *);
119 static void igb_clean_all_rx_rings(struct igb_adapter *);
120 static void igb_clean_tx_ring(struct igb_ring *);
121 static void igb_clean_rx_ring(struct igb_ring *);
122 static void igb_set_rx_mode(struct net_device *);
123 static void igb_update_phy_info(struct timer_list *);
124 static void igb_watchdog(struct timer_list *);
125 static void igb_watchdog_task(struct work_struct *);
126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127 static void igb_get_stats64(struct net_device *dev,
128 			    struct rtnl_link_stats64 *stats);
129 static int igb_change_mtu(struct net_device *, int);
130 static int igb_set_mac(struct net_device *, void *);
131 static void igb_set_uta(struct igb_adapter *adapter, bool set);
132 static irqreturn_t igb_intr(int irq, void *);
133 static irqreturn_t igb_intr_msi(int irq, void *);
134 static irqreturn_t igb_msix_other(int irq, void *);
135 static irqreturn_t igb_msix_ring(int irq, void *);
136 #ifdef CONFIG_IGB_DCA
137 static void igb_update_dca(struct igb_q_vector *);
138 static void igb_setup_dca(struct igb_adapter *);
139 #endif /* CONFIG_IGB_DCA */
140 static int igb_poll(struct napi_struct *, int);
141 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142 static int igb_clean_rx_irq(struct igb_q_vector *, int);
143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145 static void igb_reset_task(struct work_struct *);
146 static void igb_vlan_mode(struct net_device *netdev,
147 			  netdev_features_t features);
148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150 static void igb_restore_vlan(struct igb_adapter *);
151 static void igb_rar_set_index(struct igb_adapter *, u32);
152 static void igb_ping_all_vfs(struct igb_adapter *);
153 static void igb_msg_task(struct igb_adapter *);
154 static void igb_vmm_control(struct igb_adapter *);
155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156 static void igb_flush_mac_table(struct igb_adapter *);
157 static int igb_available_rars(struct igb_adapter *, u8);
158 static void igb_set_default_mac_filter(struct igb_adapter *);
159 static int igb_uc_sync(struct net_device *, const unsigned char *);
160 static int igb_uc_unsync(struct net_device *, const unsigned char *);
161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 			       int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 				   bool setting);
168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 				bool setting);
170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 				 struct ifla_vf_info *ivi);
172 static void igb_check_vf_rate_limit(struct igb_adapter *);
173 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175 
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
179 static int igb_disable_sriov(struct pci_dev *dev);
180 static int igb_pci_disable_sriov(struct pci_dev *dev);
181 #endif
182 
183 static int igb_suspend(struct device *);
184 static int igb_resume(struct device *);
185 static int igb_runtime_suspend(struct device *dev);
186 static int igb_runtime_resume(struct device *dev);
187 static int igb_runtime_idle(struct device *dev);
188 static const struct dev_pm_ops igb_pm_ops = {
189 	SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 	SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 			igb_runtime_idle)
192 };
193 static void igb_shutdown(struct pci_dev *);
194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 	.notifier_call	= igb_notify_dca,
199 	.next		= NULL,
200 	.priority	= 0
201 };
202 #endif
203 #ifdef CONFIG_PCI_IOV
204 static unsigned int max_vfs;
205 module_param(max_vfs, uint, 0);
206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207 #endif /* CONFIG_PCI_IOV */
208 
209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 		     pci_channel_state_t);
211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212 static void igb_io_resume(struct pci_dev *);
213 
214 static const struct pci_error_handlers igb_err_handler = {
215 	.error_detected = igb_io_error_detected,
216 	.slot_reset = igb_io_slot_reset,
217 	.resume = igb_io_resume,
218 };
219 
220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221 
222 static struct pci_driver igb_driver = {
223 	.name     = igb_driver_name,
224 	.id_table = igb_pci_tbl,
225 	.probe    = igb_probe,
226 	.remove   = igb_remove,
227 #ifdef CONFIG_PM
228 	.driver.pm = &igb_pm_ops,
229 #endif
230 	.shutdown = igb_shutdown,
231 	.sriov_configure = igb_pci_sriov_configure,
232 	.err_handler = &igb_err_handler
233 };
234 
235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237 MODULE_LICENSE("GPL v2");
238 
239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240 static int debug = -1;
241 module_param(debug, int, 0);
242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243 
244 struct igb_reg_info {
245 	u32 ofs;
246 	char *name;
247 };
248 
249 static const struct igb_reg_info igb_reg_info_tbl[] = {
250 
251 	/* General Registers */
252 	{E1000_CTRL, "CTRL"},
253 	{E1000_STATUS, "STATUS"},
254 	{E1000_CTRL_EXT, "CTRL_EXT"},
255 
256 	/* Interrupt Registers */
257 	{E1000_ICR, "ICR"},
258 
259 	/* RX Registers */
260 	{E1000_RCTL, "RCTL"},
261 	{E1000_RDLEN(0), "RDLEN"},
262 	{E1000_RDH(0), "RDH"},
263 	{E1000_RDT(0), "RDT"},
264 	{E1000_RXDCTL(0), "RXDCTL"},
265 	{E1000_RDBAL(0), "RDBAL"},
266 	{E1000_RDBAH(0), "RDBAH"},
267 
268 	/* TX Registers */
269 	{E1000_TCTL, "TCTL"},
270 	{E1000_TDBAL(0), "TDBAL"},
271 	{E1000_TDBAH(0), "TDBAH"},
272 	{E1000_TDLEN(0), "TDLEN"},
273 	{E1000_TDH(0), "TDH"},
274 	{E1000_TDT(0), "TDT"},
275 	{E1000_TXDCTL(0), "TXDCTL"},
276 	{E1000_TDFH, "TDFH"},
277 	{E1000_TDFT, "TDFT"},
278 	{E1000_TDFHS, "TDFHS"},
279 	{E1000_TDFPC, "TDFPC"},
280 
281 	/* List Terminator */
282 	{}
283 };
284 
285 /* igb_regdump - register printout routine */
286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287 {
288 	int n = 0;
289 	char rname[16];
290 	u32 regs[8];
291 
292 	switch (reginfo->ofs) {
293 	case E1000_RDLEN(0):
294 		for (n = 0; n < 4; n++)
295 			regs[n] = rd32(E1000_RDLEN(n));
296 		break;
297 	case E1000_RDH(0):
298 		for (n = 0; n < 4; n++)
299 			regs[n] = rd32(E1000_RDH(n));
300 		break;
301 	case E1000_RDT(0):
302 		for (n = 0; n < 4; n++)
303 			regs[n] = rd32(E1000_RDT(n));
304 		break;
305 	case E1000_RXDCTL(0):
306 		for (n = 0; n < 4; n++)
307 			regs[n] = rd32(E1000_RXDCTL(n));
308 		break;
309 	case E1000_RDBAL(0):
310 		for (n = 0; n < 4; n++)
311 			regs[n] = rd32(E1000_RDBAL(n));
312 		break;
313 	case E1000_RDBAH(0):
314 		for (n = 0; n < 4; n++)
315 			regs[n] = rd32(E1000_RDBAH(n));
316 		break;
317 	case E1000_TDBAL(0):
318 		for (n = 0; n < 4; n++)
319 			regs[n] = rd32(E1000_TDBAL(n));
320 		break;
321 	case E1000_TDBAH(0):
322 		for (n = 0; n < 4; n++)
323 			regs[n] = rd32(E1000_TDBAH(n));
324 		break;
325 	case E1000_TDLEN(0):
326 		for (n = 0; n < 4; n++)
327 			regs[n] = rd32(E1000_TDLEN(n));
328 		break;
329 	case E1000_TDH(0):
330 		for (n = 0; n < 4; n++)
331 			regs[n] = rd32(E1000_TDH(n));
332 		break;
333 	case E1000_TDT(0):
334 		for (n = 0; n < 4; n++)
335 			regs[n] = rd32(E1000_TDT(n));
336 		break;
337 	case E1000_TXDCTL(0):
338 		for (n = 0; n < 4; n++)
339 			regs[n] = rd32(E1000_TXDCTL(n));
340 		break;
341 	default:
342 		pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 		return;
344 	}
345 
346 	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 	pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 		regs[2], regs[3]);
349 }
350 
351 /* igb_dump - Print registers, Tx-rings and Rx-rings */
352 static void igb_dump(struct igb_adapter *adapter)
353 {
354 	struct net_device *netdev = adapter->netdev;
355 	struct e1000_hw *hw = &adapter->hw;
356 	struct igb_reg_info *reginfo;
357 	struct igb_ring *tx_ring;
358 	union e1000_adv_tx_desc *tx_desc;
359 	struct my_u0 { __le64 a; __le64 b; } *u0;
360 	struct igb_ring *rx_ring;
361 	union e1000_adv_rx_desc *rx_desc;
362 	u32 staterr;
363 	u16 i, n;
364 
365 	if (!netif_msg_hw(adapter))
366 		return;
367 
368 	/* Print netdevice Info */
369 	if (netdev) {
370 		dev_info(&adapter->pdev->dev, "Net device Info\n");
371 		pr_info("Device Name     state            trans_start\n");
372 		pr_info("%-15s %016lX %016lX\n", netdev->name,
373 			netdev->state, dev_trans_start(netdev));
374 	}
375 
376 	/* Print Registers */
377 	dev_info(&adapter->pdev->dev, "Register Dump\n");
378 	pr_info(" Register Name   Value\n");
379 	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 	     reginfo->name; reginfo++) {
381 		igb_regdump(hw, reginfo);
382 	}
383 
384 	/* Print TX Ring Summary */
385 	if (!netdev || !netif_running(netdev))
386 		goto exit;
387 
388 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 	pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
390 	for (n = 0; n < adapter->num_tx_queues; n++) {
391 		struct igb_tx_buffer *buffer_info;
392 		tx_ring = adapter->tx_ring[n];
393 		buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 		pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 			n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 			(u64)dma_unmap_addr(buffer_info, dma),
397 			dma_unmap_len(buffer_info, len),
398 			buffer_info->next_to_watch,
399 			(u64)buffer_info->time_stamp);
400 	}
401 
402 	/* Print TX Rings */
403 	if (!netif_msg_tx_done(adapter))
404 		goto rx_ring_summary;
405 
406 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407 
408 	/* Transmit Descriptor Formats
409 	 *
410 	 * Advanced Transmit Descriptor
411 	 *   +--------------------------------------------------------------+
412 	 * 0 |         Buffer Address [63:0]                                |
413 	 *   +--------------------------------------------------------------+
414 	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
415 	 *   +--------------------------------------------------------------+
416 	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
417 	 */
418 
419 	for (n = 0; n < adapter->num_tx_queues; n++) {
420 		tx_ring = adapter->tx_ring[n];
421 		pr_info("------------------------------------\n");
422 		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 		pr_info("------------------------------------\n");
424 		pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
425 
426 		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 			const char *next_desc;
428 			struct igb_tx_buffer *buffer_info;
429 			tx_desc = IGB_TX_DESC(tx_ring, i);
430 			buffer_info = &tx_ring->tx_buffer_info[i];
431 			u0 = (struct my_u0 *)tx_desc;
432 			if (i == tx_ring->next_to_use &&
433 			    i == tx_ring->next_to_clean)
434 				next_desc = " NTC/U";
435 			else if (i == tx_ring->next_to_use)
436 				next_desc = " NTU";
437 			else if (i == tx_ring->next_to_clean)
438 				next_desc = " NTC";
439 			else
440 				next_desc = "";
441 
442 			pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
443 				i, le64_to_cpu(u0->a),
444 				le64_to_cpu(u0->b),
445 				(u64)dma_unmap_addr(buffer_info, dma),
446 				dma_unmap_len(buffer_info, len),
447 				buffer_info->next_to_watch,
448 				(u64)buffer_info->time_stamp,
449 				buffer_info->skb, next_desc);
450 
451 			if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 				print_hex_dump(KERN_INFO, "",
453 					DUMP_PREFIX_ADDRESS,
454 					16, 1, buffer_info->skb->data,
455 					dma_unmap_len(buffer_info, len),
456 					true);
457 		}
458 	}
459 
460 	/* Print RX Rings Summary */
461 rx_ring_summary:
462 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 	pr_info("Queue [NTU] [NTC]\n");
464 	for (n = 0; n < adapter->num_rx_queues; n++) {
465 		rx_ring = adapter->rx_ring[n];
466 		pr_info(" %5d %5X %5X\n",
467 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 	}
469 
470 	/* Print RX Rings */
471 	if (!netif_msg_rx_status(adapter))
472 		goto exit;
473 
474 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475 
476 	/* Advanced Receive Descriptor (Read) Format
477 	 *    63                                           1        0
478 	 *    +-----------------------------------------------------+
479 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
480 	 *    +----------------------------------------------+------+
481 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
482 	 *    +-----------------------------------------------------+
483 	 *
484 	 *
485 	 * Advanced Receive Descriptor (Write-Back) Format
486 	 *
487 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
488 	 *   +------------------------------------------------------+
489 	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
490 	 *   | Checksum   Ident  |   |           |    | Type | Type |
491 	 *   +------------------------------------------------------+
492 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 	 *   +------------------------------------------------------+
494 	 *   63       48 47    32 31            20 19               0
495 	 */
496 
497 	for (n = 0; n < adapter->num_rx_queues; n++) {
498 		rx_ring = adapter->rx_ring[n];
499 		pr_info("------------------------------------\n");
500 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 		pr_info("------------------------------------\n");
502 		pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
503 		pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504 
505 		for (i = 0; i < rx_ring->count; i++) {
506 			const char *next_desc;
507 			struct igb_rx_buffer *buffer_info;
508 			buffer_info = &rx_ring->rx_buffer_info[i];
509 			rx_desc = IGB_RX_DESC(rx_ring, i);
510 			u0 = (struct my_u0 *)rx_desc;
511 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 
513 			if (i == rx_ring->next_to_use)
514 				next_desc = " NTU";
515 			else if (i == rx_ring->next_to_clean)
516 				next_desc = " NTC";
517 			else
518 				next_desc = "";
519 
520 			if (staterr & E1000_RXD_STAT_DD) {
521 				/* Descriptor Done */
522 				pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
523 					"RWB", i,
524 					le64_to_cpu(u0->a),
525 					le64_to_cpu(u0->b),
526 					next_desc);
527 			} else {
528 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
529 					"R  ", i,
530 					le64_to_cpu(u0->a),
531 					le64_to_cpu(u0->b),
532 					(u64)buffer_info->dma,
533 					next_desc);
534 
535 				if (netif_msg_pktdata(adapter) &&
536 				    buffer_info->dma && buffer_info->page) {
537 					print_hex_dump(KERN_INFO, "",
538 					  DUMP_PREFIX_ADDRESS,
539 					  16, 1,
540 					  page_address(buffer_info->page) +
541 						      buffer_info->page_offset,
542 					  igb_rx_bufsz(rx_ring), true);
543 				}
544 			}
545 		}
546 	}
547 
548 exit:
549 	return;
550 }
551 
552 /**
553  *  igb_get_i2c_data - Reads the I2C SDA data bit
554  *  @data: opaque pointer to adapter struct
555  *
556  *  Returns the I2C data bit value
557  **/
558 static int igb_get_i2c_data(void *data)
559 {
560 	struct igb_adapter *adapter = (struct igb_adapter *)data;
561 	struct e1000_hw *hw = &adapter->hw;
562 	s32 i2cctl = rd32(E1000_I2CPARAMS);
563 
564 	return !!(i2cctl & E1000_I2C_DATA_IN);
565 }
566 
567 /**
568  *  igb_set_i2c_data - Sets the I2C data bit
569  *  @data: pointer to hardware structure
570  *  @state: I2C data value (0 or 1) to set
571  *
572  *  Sets the I2C data bit
573  **/
574 static void igb_set_i2c_data(void *data, int state)
575 {
576 	struct igb_adapter *adapter = (struct igb_adapter *)data;
577 	struct e1000_hw *hw = &adapter->hw;
578 	s32 i2cctl = rd32(E1000_I2CPARAMS);
579 
580 	if (state) {
581 		i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
582 	} else {
583 		i2cctl &= ~E1000_I2C_DATA_OE_N;
584 		i2cctl &= ~E1000_I2C_DATA_OUT;
585 	}
586 
587 	wr32(E1000_I2CPARAMS, i2cctl);
588 	wrfl();
589 }
590 
591 /**
592  *  igb_set_i2c_clk - Sets the I2C SCL clock
593  *  @data: pointer to hardware structure
594  *  @state: state to set clock
595  *
596  *  Sets the I2C clock line to state
597  **/
598 static void igb_set_i2c_clk(void *data, int state)
599 {
600 	struct igb_adapter *adapter = (struct igb_adapter *)data;
601 	struct e1000_hw *hw = &adapter->hw;
602 	s32 i2cctl = rd32(E1000_I2CPARAMS);
603 
604 	if (state) {
605 		i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N;
606 	} else {
607 		i2cctl &= ~E1000_I2C_CLK_OUT;
608 		i2cctl &= ~E1000_I2C_CLK_OE_N;
609 	}
610 	wr32(E1000_I2CPARAMS, i2cctl);
611 	wrfl();
612 }
613 
614 /**
615  *  igb_get_i2c_clk - Gets the I2C SCL clock state
616  *  @data: pointer to hardware structure
617  *
618  *  Gets the I2C clock state
619  **/
620 static int igb_get_i2c_clk(void *data)
621 {
622 	struct igb_adapter *adapter = (struct igb_adapter *)data;
623 	struct e1000_hw *hw = &adapter->hw;
624 	s32 i2cctl = rd32(E1000_I2CPARAMS);
625 
626 	return !!(i2cctl & E1000_I2C_CLK_IN);
627 }
628 
629 static const struct i2c_algo_bit_data igb_i2c_algo = {
630 	.setsda		= igb_set_i2c_data,
631 	.setscl		= igb_set_i2c_clk,
632 	.getsda		= igb_get_i2c_data,
633 	.getscl		= igb_get_i2c_clk,
634 	.udelay		= 5,
635 	.timeout	= 20,
636 };
637 
638 /**
639  *  igb_get_hw_dev - return device
640  *  @hw: pointer to hardware structure
641  *
642  *  used by hardware layer to print debugging information
643  **/
644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
645 {
646 	struct igb_adapter *adapter = hw->back;
647 	return adapter->netdev;
648 }
649 
650 /**
651  *  igb_init_module - Driver Registration Routine
652  *
653  *  igb_init_module is the first routine called when the driver is
654  *  loaded. All it does is register with the PCI subsystem.
655  **/
656 static int __init igb_init_module(void)
657 {
658 	int ret;
659 
660 	pr_info("%s\n", igb_driver_string);
661 	pr_info("%s\n", igb_copyright);
662 
663 #ifdef CONFIG_IGB_DCA
664 	dca_register_notify(&dca_notifier);
665 #endif
666 	ret = pci_register_driver(&igb_driver);
667 	return ret;
668 }
669 
670 module_init(igb_init_module);
671 
672 /**
673  *  igb_exit_module - Driver Exit Cleanup Routine
674  *
675  *  igb_exit_module is called just before the driver is removed
676  *  from memory.
677  **/
678 static void __exit igb_exit_module(void)
679 {
680 #ifdef CONFIG_IGB_DCA
681 	dca_unregister_notify(&dca_notifier);
682 #endif
683 	pci_unregister_driver(&igb_driver);
684 }
685 
686 module_exit(igb_exit_module);
687 
688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
689 /**
690  *  igb_cache_ring_register - Descriptor ring to register mapping
691  *  @adapter: board private structure to initialize
692  *
693  *  Once we know the feature-set enabled for the device, we'll cache
694  *  the register offset the descriptor ring is assigned to.
695  **/
696 static void igb_cache_ring_register(struct igb_adapter *adapter)
697 {
698 	int i = 0, j = 0;
699 	u32 rbase_offset = adapter->vfs_allocated_count;
700 
701 	switch (adapter->hw.mac.type) {
702 	case e1000_82576:
703 		/* The queues are allocated for virtualization such that VF 0
704 		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
705 		 * In order to avoid collision we start at the first free queue
706 		 * and continue consuming queues in the same sequence
707 		 */
708 		if (adapter->vfs_allocated_count) {
709 			for (; i < adapter->rss_queues; i++)
710 				adapter->rx_ring[i]->reg_idx = rbase_offset +
711 							       Q_IDX_82576(i);
712 		}
713 		fallthrough;
714 	case e1000_82575:
715 	case e1000_82580:
716 	case e1000_i350:
717 	case e1000_i354:
718 	case e1000_i210:
719 	case e1000_i211:
720 	default:
721 		for (; i < adapter->num_rx_queues; i++)
722 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
723 		for (; j < adapter->num_tx_queues; j++)
724 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
725 		break;
726 	}
727 }
728 
729 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
730 {
731 	struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
732 	u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
733 	u32 value = 0;
734 
735 	if (E1000_REMOVED(hw_addr))
736 		return ~value;
737 
738 	value = readl(&hw_addr[reg]);
739 
740 	/* reads should not return all F's */
741 	if (!(~value) && (!reg || !(~readl(hw_addr)))) {
742 		struct net_device *netdev = igb->netdev;
743 		hw->hw_addr = NULL;
744 		netdev_err(netdev, "PCIe link lost\n");
745 		WARN(pci_device_is_present(igb->pdev),
746 		     "igb: Failed to read reg 0x%x!\n", reg);
747 	}
748 
749 	return value;
750 }
751 
752 /**
753  *  igb_write_ivar - configure ivar for given MSI-X vector
754  *  @hw: pointer to the HW structure
755  *  @msix_vector: vector number we are allocating to a given ring
756  *  @index: row index of IVAR register to write within IVAR table
757  *  @offset: column offset of in IVAR, should be multiple of 8
758  *
759  *  This function is intended to handle the writing of the IVAR register
760  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
761  *  each containing an cause allocation for an Rx and Tx ring, and a
762  *  variable number of rows depending on the number of queues supported.
763  **/
764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 			   int index, int offset)
766 {
767 	u32 ivar = array_rd32(E1000_IVAR0, index);
768 
769 	/* clear any bits that are currently set */
770 	ivar &= ~((u32)0xFF << offset);
771 
772 	/* write vector and valid bit */
773 	ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774 
775 	array_wr32(E1000_IVAR0, index, ivar);
776 }
777 
778 #define IGB_N0_QUEUE -1
779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
780 {
781 	struct igb_adapter *adapter = q_vector->adapter;
782 	struct e1000_hw *hw = &adapter->hw;
783 	int rx_queue = IGB_N0_QUEUE;
784 	int tx_queue = IGB_N0_QUEUE;
785 	u32 msixbm = 0;
786 
787 	if (q_vector->rx.ring)
788 		rx_queue = q_vector->rx.ring->reg_idx;
789 	if (q_vector->tx.ring)
790 		tx_queue = q_vector->tx.ring->reg_idx;
791 
792 	switch (hw->mac.type) {
793 	case e1000_82575:
794 		/* The 82575 assigns vectors using a bitmask, which matches the
795 		 * bitmask for the EICR/EIMS/EIMC registers.  To assign one
796 		 * or more queues to a vector, we write the appropriate bits
797 		 * into the MSIXBM register for that vector.
798 		 */
799 		if (rx_queue > IGB_N0_QUEUE)
800 			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
801 		if (tx_queue > IGB_N0_QUEUE)
802 			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
803 		if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
804 			msixbm |= E1000_EIMS_OTHER;
805 		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
806 		q_vector->eims_value = msixbm;
807 		break;
808 	case e1000_82576:
809 		/* 82576 uses a table that essentially consists of 2 columns
810 		 * with 8 rows.  The ordering is column-major so we use the
811 		 * lower 3 bits as the row index, and the 4th bit as the
812 		 * column offset.
813 		 */
814 		if (rx_queue > IGB_N0_QUEUE)
815 			igb_write_ivar(hw, msix_vector,
816 				       rx_queue & 0x7,
817 				       (rx_queue & 0x8) << 1);
818 		if (tx_queue > IGB_N0_QUEUE)
819 			igb_write_ivar(hw, msix_vector,
820 				       tx_queue & 0x7,
821 				       ((tx_queue & 0x8) << 1) + 8);
822 		q_vector->eims_value = BIT(msix_vector);
823 		break;
824 	case e1000_82580:
825 	case e1000_i350:
826 	case e1000_i354:
827 	case e1000_i210:
828 	case e1000_i211:
829 		/* On 82580 and newer adapters the scheme is similar to 82576
830 		 * however instead of ordering column-major we have things
831 		 * ordered row-major.  So we traverse the table by using
832 		 * bit 0 as the column offset, and the remaining bits as the
833 		 * row index.
834 		 */
835 		if (rx_queue > IGB_N0_QUEUE)
836 			igb_write_ivar(hw, msix_vector,
837 				       rx_queue >> 1,
838 				       (rx_queue & 0x1) << 4);
839 		if (tx_queue > IGB_N0_QUEUE)
840 			igb_write_ivar(hw, msix_vector,
841 				       tx_queue >> 1,
842 				       ((tx_queue & 0x1) << 4) + 8);
843 		q_vector->eims_value = BIT(msix_vector);
844 		break;
845 	default:
846 		BUG();
847 		break;
848 	}
849 
850 	/* add q_vector eims value to global eims_enable_mask */
851 	adapter->eims_enable_mask |= q_vector->eims_value;
852 
853 	/* configure q_vector to set itr on first interrupt */
854 	q_vector->set_itr = 1;
855 }
856 
857 /**
858  *  igb_configure_msix - Configure MSI-X hardware
859  *  @adapter: board private structure to initialize
860  *
861  *  igb_configure_msix sets up the hardware to properly
862  *  generate MSI-X interrupts.
863  **/
864 static void igb_configure_msix(struct igb_adapter *adapter)
865 {
866 	u32 tmp;
867 	int i, vector = 0;
868 	struct e1000_hw *hw = &adapter->hw;
869 
870 	adapter->eims_enable_mask = 0;
871 
872 	/* set vector for other causes, i.e. link changes */
873 	switch (hw->mac.type) {
874 	case e1000_82575:
875 		tmp = rd32(E1000_CTRL_EXT);
876 		/* enable MSI-X PBA support*/
877 		tmp |= E1000_CTRL_EXT_PBA_CLR;
878 
879 		/* Auto-Mask interrupts upon ICR read. */
880 		tmp |= E1000_CTRL_EXT_EIAME;
881 		tmp |= E1000_CTRL_EXT_IRCA;
882 
883 		wr32(E1000_CTRL_EXT, tmp);
884 
885 		/* enable msix_other interrupt */
886 		array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
887 		adapter->eims_other = E1000_EIMS_OTHER;
888 
889 		break;
890 
891 	case e1000_82576:
892 	case e1000_82580:
893 	case e1000_i350:
894 	case e1000_i354:
895 	case e1000_i210:
896 	case e1000_i211:
897 		/* Turn on MSI-X capability first, or our settings
898 		 * won't stick.  And it will take days to debug.
899 		 */
900 		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
901 		     E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 		     E1000_GPIE_NSICR);
903 
904 		/* enable msix_other interrupt */
905 		adapter->eims_other = BIT(vector);
906 		tmp = (vector++ | E1000_IVAR_VALID) << 8;
907 
908 		wr32(E1000_IVAR_MISC, tmp);
909 		break;
910 	default:
911 		/* do nothing, since nothing else supports MSI-X */
912 		break;
913 	} /* switch (hw->mac.type) */
914 
915 	adapter->eims_enable_mask |= adapter->eims_other;
916 
917 	for (i = 0; i < adapter->num_q_vectors; i++)
918 		igb_assign_vector(adapter->q_vector[i], vector++);
919 
920 	wrfl();
921 }
922 
923 /**
924  *  igb_request_msix - Initialize MSI-X interrupts
925  *  @adapter: board private structure to initialize
926  *
927  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
928  *  kernel.
929  **/
930 static int igb_request_msix(struct igb_adapter *adapter)
931 {
932 	unsigned int num_q_vectors = adapter->num_q_vectors;
933 	struct net_device *netdev = adapter->netdev;
934 	int i, err = 0, vector = 0, free_vector = 0;
935 
936 	err = request_irq(adapter->msix_entries[vector].vector,
937 			  igb_msix_other, 0, netdev->name, adapter);
938 	if (err)
939 		goto err_out;
940 
941 	if (num_q_vectors > MAX_Q_VECTORS) {
942 		num_q_vectors = MAX_Q_VECTORS;
943 		dev_warn(&adapter->pdev->dev,
944 			 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
945 			 adapter->num_q_vectors, MAX_Q_VECTORS);
946 	}
947 	for (i = 0; i < num_q_vectors; i++) {
948 		struct igb_q_vector *q_vector = adapter->q_vector[i];
949 
950 		vector++;
951 
952 		q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
953 
954 		if (q_vector->rx.ring && q_vector->tx.ring)
955 			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
956 				q_vector->rx.ring->queue_index);
957 		else if (q_vector->tx.ring)
958 			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
959 				q_vector->tx.ring->queue_index);
960 		else if (q_vector->rx.ring)
961 			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
962 				q_vector->rx.ring->queue_index);
963 		else
964 			sprintf(q_vector->name, "%s-unused", netdev->name);
965 
966 		err = request_irq(adapter->msix_entries[vector].vector,
967 				  igb_msix_ring, 0, q_vector->name,
968 				  q_vector);
969 		if (err)
970 			goto err_free;
971 	}
972 
973 	igb_configure_msix(adapter);
974 	return 0;
975 
976 err_free:
977 	/* free already assigned IRQs */
978 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
979 
980 	vector--;
981 	for (i = 0; i < vector; i++) {
982 		free_irq(adapter->msix_entries[free_vector++].vector,
983 			 adapter->q_vector[i]);
984 	}
985 err_out:
986 	return err;
987 }
988 
989 /**
990  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
991  *  @adapter: board private structure to initialize
992  *  @v_idx: Index of vector to be freed
993  *
994  *  This function frees the memory allocated to the q_vector.
995  **/
996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
997 {
998 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
999 
1000 	adapter->q_vector[v_idx] = NULL;
1001 
1002 	/* igb_get_stats64() might access the rings on this vector,
1003 	 * we must wait a grace period before freeing it.
1004 	 */
1005 	if (q_vector)
1006 		kfree_rcu(q_vector, rcu);
1007 }
1008 
1009 /**
1010  *  igb_reset_q_vector - Reset config for interrupt vector
1011  *  @adapter: board private structure to initialize
1012  *  @v_idx: Index of vector to be reset
1013  *
1014  *  If NAPI is enabled it will delete any references to the
1015  *  NAPI struct. This is preparation for igb_free_q_vector.
1016  **/
1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1018 {
1019 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1020 
1021 	/* Coming from igb_set_interrupt_capability, the vectors are not yet
1022 	 * allocated. So, q_vector is NULL so we should stop here.
1023 	 */
1024 	if (!q_vector)
1025 		return;
1026 
1027 	if (q_vector->tx.ring)
1028 		adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1029 
1030 	if (q_vector->rx.ring)
1031 		adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1032 
1033 	netif_napi_del(&q_vector->napi);
1034 
1035 }
1036 
1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1038 {
1039 	int v_idx = adapter->num_q_vectors;
1040 
1041 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1042 		pci_disable_msix(adapter->pdev);
1043 	else if (adapter->flags & IGB_FLAG_HAS_MSI)
1044 		pci_disable_msi(adapter->pdev);
1045 
1046 	while (v_idx--)
1047 		igb_reset_q_vector(adapter, v_idx);
1048 }
1049 
1050 /**
1051  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1052  *  @adapter: board private structure to initialize
1053  *
1054  *  This function frees the memory allocated to the q_vectors.  In addition if
1055  *  NAPI is enabled it will delete any references to the NAPI struct prior
1056  *  to freeing the q_vector.
1057  **/
1058 static void igb_free_q_vectors(struct igb_adapter *adapter)
1059 {
1060 	int v_idx = adapter->num_q_vectors;
1061 
1062 	adapter->num_tx_queues = 0;
1063 	adapter->num_rx_queues = 0;
1064 	adapter->num_q_vectors = 0;
1065 
1066 	while (v_idx--) {
1067 		igb_reset_q_vector(adapter, v_idx);
1068 		igb_free_q_vector(adapter, v_idx);
1069 	}
1070 }
1071 
1072 /**
1073  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1074  *  @adapter: board private structure to initialize
1075  *
1076  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1077  *  MSI-X interrupts allocated.
1078  */
1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1080 {
1081 	igb_free_q_vectors(adapter);
1082 	igb_reset_interrupt_capability(adapter);
1083 }
1084 
1085 /**
1086  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1087  *  @adapter: board private structure to initialize
1088  *  @msix: boolean value of MSIX capability
1089  *
1090  *  Attempt to configure interrupts using the best available
1091  *  capabilities of the hardware and kernel.
1092  **/
1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1094 {
1095 	int err;
1096 	int numvecs, i;
1097 
1098 	if (!msix)
1099 		goto msi_only;
1100 	adapter->flags |= IGB_FLAG_HAS_MSIX;
1101 
1102 	/* Number of supported queues. */
1103 	adapter->num_rx_queues = adapter->rss_queues;
1104 	if (adapter->vfs_allocated_count)
1105 		adapter->num_tx_queues = 1;
1106 	else
1107 		adapter->num_tx_queues = adapter->rss_queues;
1108 
1109 	/* start with one vector for every Rx queue */
1110 	numvecs = adapter->num_rx_queues;
1111 
1112 	/* if Tx handler is separate add 1 for every Tx queue */
1113 	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1114 		numvecs += adapter->num_tx_queues;
1115 
1116 	/* store the number of vectors reserved for queues */
1117 	adapter->num_q_vectors = numvecs;
1118 
1119 	/* add 1 vector for link status interrupts */
1120 	numvecs++;
1121 	for (i = 0; i < numvecs; i++)
1122 		adapter->msix_entries[i].entry = i;
1123 
1124 	err = pci_enable_msix_range(adapter->pdev,
1125 				    adapter->msix_entries,
1126 				    numvecs,
1127 				    numvecs);
1128 	if (err > 0)
1129 		return;
1130 
1131 	igb_reset_interrupt_capability(adapter);
1132 
1133 	/* If we can't do MSI-X, try MSI */
1134 msi_only:
1135 	adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1136 #ifdef CONFIG_PCI_IOV
1137 	/* disable SR-IOV for non MSI-X configurations */
1138 	if (adapter->vf_data) {
1139 		struct e1000_hw *hw = &adapter->hw;
1140 		/* disable iov and allow time for transactions to clear */
1141 		pci_disable_sriov(adapter->pdev);
1142 		msleep(500);
1143 
1144 		kfree(adapter->vf_mac_list);
1145 		adapter->vf_mac_list = NULL;
1146 		kfree(adapter->vf_data);
1147 		adapter->vf_data = NULL;
1148 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1149 		wrfl();
1150 		msleep(100);
1151 		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1152 	}
1153 #endif
1154 	adapter->vfs_allocated_count = 0;
1155 	adapter->rss_queues = 1;
1156 	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1157 	adapter->num_rx_queues = 1;
1158 	adapter->num_tx_queues = 1;
1159 	adapter->num_q_vectors = 1;
1160 	if (!pci_enable_msi(adapter->pdev))
1161 		adapter->flags |= IGB_FLAG_HAS_MSI;
1162 }
1163 
1164 static void igb_add_ring(struct igb_ring *ring,
1165 			 struct igb_ring_container *head)
1166 {
1167 	head->ring = ring;
1168 	head->count++;
1169 }
1170 
1171 /**
1172  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1173  *  @adapter: board private structure to initialize
1174  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1175  *  @v_idx: index of vector in adapter struct
1176  *  @txr_count: total number of Tx rings to allocate
1177  *  @txr_idx: index of first Tx ring to allocate
1178  *  @rxr_count: total number of Rx rings to allocate
1179  *  @rxr_idx: index of first Rx ring to allocate
1180  *
1181  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1182  **/
1183 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1184 			      int v_count, int v_idx,
1185 			      int txr_count, int txr_idx,
1186 			      int rxr_count, int rxr_idx)
1187 {
1188 	struct igb_q_vector *q_vector;
1189 	struct igb_ring *ring;
1190 	int ring_count;
1191 	size_t size;
1192 
1193 	/* igb only supports 1 Tx and/or 1 Rx queue per vector */
1194 	if (txr_count > 1 || rxr_count > 1)
1195 		return -ENOMEM;
1196 
1197 	ring_count = txr_count + rxr_count;
1198 	size = struct_size(q_vector, ring, ring_count);
1199 
1200 	/* allocate q_vector and rings */
1201 	q_vector = adapter->q_vector[v_idx];
1202 	if (!q_vector) {
1203 		q_vector = kzalloc(size, GFP_KERNEL);
1204 	} else if (size > ksize(q_vector)) {
1205 		kfree_rcu(q_vector, rcu);
1206 		q_vector = kzalloc(size, GFP_KERNEL);
1207 	} else {
1208 		memset(q_vector, 0, size);
1209 	}
1210 	if (!q_vector)
1211 		return -ENOMEM;
1212 
1213 	/* initialize NAPI */
1214 	netif_napi_add(adapter->netdev, &q_vector->napi,
1215 		       igb_poll, 64);
1216 
1217 	/* tie q_vector and adapter together */
1218 	adapter->q_vector[v_idx] = q_vector;
1219 	q_vector->adapter = adapter;
1220 
1221 	/* initialize work limits */
1222 	q_vector->tx.work_limit = adapter->tx_work_limit;
1223 
1224 	/* initialize ITR configuration */
1225 	q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1226 	q_vector->itr_val = IGB_START_ITR;
1227 
1228 	/* initialize pointer to rings */
1229 	ring = q_vector->ring;
1230 
1231 	/* intialize ITR */
1232 	if (rxr_count) {
1233 		/* rx or rx/tx vector */
1234 		if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1235 			q_vector->itr_val = adapter->rx_itr_setting;
1236 	} else {
1237 		/* tx only vector */
1238 		if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1239 			q_vector->itr_val = adapter->tx_itr_setting;
1240 	}
1241 
1242 	if (txr_count) {
1243 		/* assign generic ring traits */
1244 		ring->dev = &adapter->pdev->dev;
1245 		ring->netdev = adapter->netdev;
1246 
1247 		/* configure backlink on ring */
1248 		ring->q_vector = q_vector;
1249 
1250 		/* update q_vector Tx values */
1251 		igb_add_ring(ring, &q_vector->tx);
1252 
1253 		/* For 82575, context index must be unique per ring. */
1254 		if (adapter->hw.mac.type == e1000_82575)
1255 			set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1256 
1257 		/* apply Tx specific ring traits */
1258 		ring->count = adapter->tx_ring_count;
1259 		ring->queue_index = txr_idx;
1260 
1261 		ring->cbs_enable = false;
1262 		ring->idleslope = 0;
1263 		ring->sendslope = 0;
1264 		ring->hicredit = 0;
1265 		ring->locredit = 0;
1266 
1267 		u64_stats_init(&ring->tx_syncp);
1268 		u64_stats_init(&ring->tx_syncp2);
1269 
1270 		/* assign ring to adapter */
1271 		adapter->tx_ring[txr_idx] = ring;
1272 
1273 		/* push pointer to next ring */
1274 		ring++;
1275 	}
1276 
1277 	if (rxr_count) {
1278 		/* assign generic ring traits */
1279 		ring->dev = &adapter->pdev->dev;
1280 		ring->netdev = adapter->netdev;
1281 
1282 		/* configure backlink on ring */
1283 		ring->q_vector = q_vector;
1284 
1285 		/* update q_vector Rx values */
1286 		igb_add_ring(ring, &q_vector->rx);
1287 
1288 		/* set flag indicating ring supports SCTP checksum offload */
1289 		if (adapter->hw.mac.type >= e1000_82576)
1290 			set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1291 
1292 		/* On i350, i354, i210, and i211, loopback VLAN packets
1293 		 * have the tag byte-swapped.
1294 		 */
1295 		if (adapter->hw.mac.type >= e1000_i350)
1296 			set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1297 
1298 		/* apply Rx specific ring traits */
1299 		ring->count = adapter->rx_ring_count;
1300 		ring->queue_index = rxr_idx;
1301 
1302 		u64_stats_init(&ring->rx_syncp);
1303 
1304 		/* assign ring to adapter */
1305 		adapter->rx_ring[rxr_idx] = ring;
1306 	}
1307 
1308 	return 0;
1309 }
1310 
1311 
1312 /**
1313  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1314  *  @adapter: board private structure to initialize
1315  *
1316  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1317  *  return -ENOMEM.
1318  **/
1319 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1320 {
1321 	int q_vectors = adapter->num_q_vectors;
1322 	int rxr_remaining = adapter->num_rx_queues;
1323 	int txr_remaining = adapter->num_tx_queues;
1324 	int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1325 	int err;
1326 
1327 	if (q_vectors >= (rxr_remaining + txr_remaining)) {
1328 		for (; rxr_remaining; v_idx++) {
1329 			err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1330 						 0, 0, 1, rxr_idx);
1331 
1332 			if (err)
1333 				goto err_out;
1334 
1335 			/* update counts and index */
1336 			rxr_remaining--;
1337 			rxr_idx++;
1338 		}
1339 	}
1340 
1341 	for (; v_idx < q_vectors; v_idx++) {
1342 		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1343 		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1344 
1345 		err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1346 					 tqpv, txr_idx, rqpv, rxr_idx);
1347 
1348 		if (err)
1349 			goto err_out;
1350 
1351 		/* update counts and index */
1352 		rxr_remaining -= rqpv;
1353 		txr_remaining -= tqpv;
1354 		rxr_idx++;
1355 		txr_idx++;
1356 	}
1357 
1358 	return 0;
1359 
1360 err_out:
1361 	adapter->num_tx_queues = 0;
1362 	adapter->num_rx_queues = 0;
1363 	adapter->num_q_vectors = 0;
1364 
1365 	while (v_idx--)
1366 		igb_free_q_vector(adapter, v_idx);
1367 
1368 	return -ENOMEM;
1369 }
1370 
1371 /**
1372  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1373  *  @adapter: board private structure to initialize
1374  *  @msix: boolean value of MSIX capability
1375  *
1376  *  This function initializes the interrupts and allocates all of the queues.
1377  **/
1378 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1379 {
1380 	struct pci_dev *pdev = adapter->pdev;
1381 	int err;
1382 
1383 	igb_set_interrupt_capability(adapter, msix);
1384 
1385 	err = igb_alloc_q_vectors(adapter);
1386 	if (err) {
1387 		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1388 		goto err_alloc_q_vectors;
1389 	}
1390 
1391 	igb_cache_ring_register(adapter);
1392 
1393 	return 0;
1394 
1395 err_alloc_q_vectors:
1396 	igb_reset_interrupt_capability(adapter);
1397 	return err;
1398 }
1399 
1400 /**
1401  *  igb_request_irq - initialize interrupts
1402  *  @adapter: board private structure to initialize
1403  *
1404  *  Attempts to configure interrupts using the best available
1405  *  capabilities of the hardware and kernel.
1406  **/
1407 static int igb_request_irq(struct igb_adapter *adapter)
1408 {
1409 	struct net_device *netdev = adapter->netdev;
1410 	struct pci_dev *pdev = adapter->pdev;
1411 	int err = 0;
1412 
1413 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1414 		err = igb_request_msix(adapter);
1415 		if (!err)
1416 			goto request_done;
1417 		/* fall back to MSI */
1418 		igb_free_all_tx_resources(adapter);
1419 		igb_free_all_rx_resources(adapter);
1420 
1421 		igb_clear_interrupt_scheme(adapter);
1422 		err = igb_init_interrupt_scheme(adapter, false);
1423 		if (err)
1424 			goto request_done;
1425 
1426 		igb_setup_all_tx_resources(adapter);
1427 		igb_setup_all_rx_resources(adapter);
1428 		igb_configure(adapter);
1429 	}
1430 
1431 	igb_assign_vector(adapter->q_vector[0], 0);
1432 
1433 	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1434 		err = request_irq(pdev->irq, igb_intr_msi, 0,
1435 				  netdev->name, adapter);
1436 		if (!err)
1437 			goto request_done;
1438 
1439 		/* fall back to legacy interrupts */
1440 		igb_reset_interrupt_capability(adapter);
1441 		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1442 	}
1443 
1444 	err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1445 			  netdev->name, adapter);
1446 
1447 	if (err)
1448 		dev_err(&pdev->dev, "Error %d getting interrupt\n",
1449 			err);
1450 
1451 request_done:
1452 	return err;
1453 }
1454 
1455 static void igb_free_irq(struct igb_adapter *adapter)
1456 {
1457 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1458 		int vector = 0, i;
1459 
1460 		free_irq(adapter->msix_entries[vector++].vector, adapter);
1461 
1462 		for (i = 0; i < adapter->num_q_vectors; i++)
1463 			free_irq(adapter->msix_entries[vector++].vector,
1464 				 adapter->q_vector[i]);
1465 	} else {
1466 		free_irq(adapter->pdev->irq, adapter);
1467 	}
1468 }
1469 
1470 /**
1471  *  igb_irq_disable - Mask off interrupt generation on the NIC
1472  *  @adapter: board private structure
1473  **/
1474 static void igb_irq_disable(struct igb_adapter *adapter)
1475 {
1476 	struct e1000_hw *hw = &adapter->hw;
1477 
1478 	/* we need to be careful when disabling interrupts.  The VFs are also
1479 	 * mapped into these registers and so clearing the bits can cause
1480 	 * issues on the VF drivers so we only need to clear what we set
1481 	 */
1482 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1483 		u32 regval = rd32(E1000_EIAM);
1484 
1485 		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1486 		wr32(E1000_EIMC, adapter->eims_enable_mask);
1487 		regval = rd32(E1000_EIAC);
1488 		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1489 	}
1490 
1491 	wr32(E1000_IAM, 0);
1492 	wr32(E1000_IMC, ~0);
1493 	wrfl();
1494 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1495 		int i;
1496 
1497 		for (i = 0; i < adapter->num_q_vectors; i++)
1498 			synchronize_irq(adapter->msix_entries[i].vector);
1499 	} else {
1500 		synchronize_irq(adapter->pdev->irq);
1501 	}
1502 }
1503 
1504 /**
1505  *  igb_irq_enable - Enable default interrupt generation settings
1506  *  @adapter: board private structure
1507  **/
1508 static void igb_irq_enable(struct igb_adapter *adapter)
1509 {
1510 	struct e1000_hw *hw = &adapter->hw;
1511 
1512 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1513 		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1514 		u32 regval = rd32(E1000_EIAC);
1515 
1516 		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1517 		regval = rd32(E1000_EIAM);
1518 		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1519 		wr32(E1000_EIMS, adapter->eims_enable_mask);
1520 		if (adapter->vfs_allocated_count) {
1521 			wr32(E1000_MBVFIMR, 0xFF);
1522 			ims |= E1000_IMS_VMMB;
1523 		}
1524 		wr32(E1000_IMS, ims);
1525 	} else {
1526 		wr32(E1000_IMS, IMS_ENABLE_MASK |
1527 				E1000_IMS_DRSTA);
1528 		wr32(E1000_IAM, IMS_ENABLE_MASK |
1529 				E1000_IMS_DRSTA);
1530 	}
1531 }
1532 
1533 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1534 {
1535 	struct e1000_hw *hw = &adapter->hw;
1536 	u16 pf_id = adapter->vfs_allocated_count;
1537 	u16 vid = adapter->hw.mng_cookie.vlan_id;
1538 	u16 old_vid = adapter->mng_vlan_id;
1539 
1540 	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1541 		/* add VID to filter table */
1542 		igb_vfta_set(hw, vid, pf_id, true, true);
1543 		adapter->mng_vlan_id = vid;
1544 	} else {
1545 		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1546 	}
1547 
1548 	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1549 	    (vid != old_vid) &&
1550 	    !test_bit(old_vid, adapter->active_vlans)) {
1551 		/* remove VID from filter table */
1552 		igb_vfta_set(hw, vid, pf_id, false, true);
1553 	}
1554 }
1555 
1556 /**
1557  *  igb_release_hw_control - release control of the h/w to f/w
1558  *  @adapter: address of board private structure
1559  *
1560  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1561  *  For ASF and Pass Through versions of f/w this means that the
1562  *  driver is no longer loaded.
1563  **/
1564 static void igb_release_hw_control(struct igb_adapter *adapter)
1565 {
1566 	struct e1000_hw *hw = &adapter->hw;
1567 	u32 ctrl_ext;
1568 
1569 	/* Let firmware take over control of h/w */
1570 	ctrl_ext = rd32(E1000_CTRL_EXT);
1571 	wr32(E1000_CTRL_EXT,
1572 			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1573 }
1574 
1575 /**
1576  *  igb_get_hw_control - get control of the h/w from f/w
1577  *  @adapter: address of board private structure
1578  *
1579  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1580  *  For ASF and Pass Through versions of f/w this means that
1581  *  the driver is loaded.
1582  **/
1583 static void igb_get_hw_control(struct igb_adapter *adapter)
1584 {
1585 	struct e1000_hw *hw = &adapter->hw;
1586 	u32 ctrl_ext;
1587 
1588 	/* Let firmware know the driver has taken over */
1589 	ctrl_ext = rd32(E1000_CTRL_EXT);
1590 	wr32(E1000_CTRL_EXT,
1591 			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1592 }
1593 
1594 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1595 {
1596 	struct net_device *netdev = adapter->netdev;
1597 	struct e1000_hw *hw = &adapter->hw;
1598 
1599 	WARN_ON(hw->mac.type != e1000_i210);
1600 
1601 	if (enable)
1602 		adapter->flags |= IGB_FLAG_FQTSS;
1603 	else
1604 		adapter->flags &= ~IGB_FLAG_FQTSS;
1605 
1606 	if (netif_running(netdev))
1607 		schedule_work(&adapter->reset_task);
1608 }
1609 
1610 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1611 {
1612 	return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1613 }
1614 
1615 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1616 				   enum tx_queue_prio prio)
1617 {
1618 	u32 val;
1619 
1620 	WARN_ON(hw->mac.type != e1000_i210);
1621 	WARN_ON(queue < 0 || queue > 4);
1622 
1623 	val = rd32(E1000_I210_TXDCTL(queue));
1624 
1625 	if (prio == TX_QUEUE_PRIO_HIGH)
1626 		val |= E1000_TXDCTL_PRIORITY;
1627 	else
1628 		val &= ~E1000_TXDCTL_PRIORITY;
1629 
1630 	wr32(E1000_I210_TXDCTL(queue), val);
1631 }
1632 
1633 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1634 {
1635 	u32 val;
1636 
1637 	WARN_ON(hw->mac.type != e1000_i210);
1638 	WARN_ON(queue < 0 || queue > 1);
1639 
1640 	val = rd32(E1000_I210_TQAVCC(queue));
1641 
1642 	if (mode == QUEUE_MODE_STREAM_RESERVATION)
1643 		val |= E1000_TQAVCC_QUEUEMODE;
1644 	else
1645 		val &= ~E1000_TQAVCC_QUEUEMODE;
1646 
1647 	wr32(E1000_I210_TQAVCC(queue), val);
1648 }
1649 
1650 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1651 {
1652 	int i;
1653 
1654 	for (i = 0; i < adapter->num_tx_queues; i++) {
1655 		if (adapter->tx_ring[i]->cbs_enable)
1656 			return true;
1657 	}
1658 
1659 	return false;
1660 }
1661 
1662 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1663 {
1664 	int i;
1665 
1666 	for (i = 0; i < adapter->num_tx_queues; i++) {
1667 		if (adapter->tx_ring[i]->launchtime_enable)
1668 			return true;
1669 	}
1670 
1671 	return false;
1672 }
1673 
1674 /**
1675  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1676  *  @adapter: pointer to adapter struct
1677  *  @queue: queue number
1678  *
1679  *  Configure CBS and Launchtime for a given hardware queue.
1680  *  Parameters are retrieved from the correct Tx ring, so
1681  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1682  *  for setting those correctly prior to this function being called.
1683  **/
1684 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1685 {
1686 	struct net_device *netdev = adapter->netdev;
1687 	struct e1000_hw *hw = &adapter->hw;
1688 	struct igb_ring *ring;
1689 	u32 tqavcc, tqavctrl;
1690 	u16 value;
1691 
1692 	WARN_ON(hw->mac.type != e1000_i210);
1693 	WARN_ON(queue < 0 || queue > 1);
1694 	ring = adapter->tx_ring[queue];
1695 
1696 	/* If any of the Qav features is enabled, configure queues as SR and
1697 	 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1698 	 * as SP.
1699 	 */
1700 	if (ring->cbs_enable || ring->launchtime_enable) {
1701 		set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1702 		set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1703 	} else {
1704 		set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1705 		set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1706 	}
1707 
1708 	/* If CBS is enabled, set DataTranARB and config its parameters. */
1709 	if (ring->cbs_enable || queue == 0) {
1710 		/* i210 does not allow the queue 0 to be in the Strict
1711 		 * Priority mode while the Qav mode is enabled, so,
1712 		 * instead of disabling strict priority mode, we give
1713 		 * queue 0 the maximum of credits possible.
1714 		 *
1715 		 * See section 8.12.19 of the i210 datasheet, "Note:
1716 		 * Queue0 QueueMode must be set to 1b when
1717 		 * TransmitMode is set to Qav."
1718 		 */
1719 		if (queue == 0 && !ring->cbs_enable) {
1720 			/* max "linkspeed" idleslope in kbps */
1721 			ring->idleslope = 1000000;
1722 			ring->hicredit = ETH_FRAME_LEN;
1723 		}
1724 
1725 		/* Always set data transfer arbitration to credit-based
1726 		 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1727 		 * the queues.
1728 		 */
1729 		tqavctrl = rd32(E1000_I210_TQAVCTRL);
1730 		tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1731 		wr32(E1000_I210_TQAVCTRL, tqavctrl);
1732 
1733 		/* According to i210 datasheet section 7.2.7.7, we should set
1734 		 * the 'idleSlope' field from TQAVCC register following the
1735 		 * equation:
1736 		 *
1737 		 * For 100 Mbps link speed:
1738 		 *
1739 		 *     value = BW * 0x7735 * 0.2                          (E1)
1740 		 *
1741 		 * For 1000Mbps link speed:
1742 		 *
1743 		 *     value = BW * 0x7735 * 2                            (E2)
1744 		 *
1745 		 * E1 and E2 can be merged into one equation as shown below.
1746 		 * Note that 'link-speed' is in Mbps.
1747 		 *
1748 		 *     value = BW * 0x7735 * 2 * link-speed
1749 		 *                           --------------               (E3)
1750 		 *                                1000
1751 		 *
1752 		 * 'BW' is the percentage bandwidth out of full link speed
1753 		 * which can be found with the following equation. Note that
1754 		 * idleSlope here is the parameter from this function which
1755 		 * is in kbps.
1756 		 *
1757 		 *     BW =     idleSlope
1758 		 *          -----------------                             (E4)
1759 		 *          link-speed * 1000
1760 		 *
1761 		 * That said, we can come up with a generic equation to
1762 		 * calculate the value we should set it TQAVCC register by
1763 		 * replacing 'BW' in E3 by E4. The resulting equation is:
1764 		 *
1765 		 * value =     idleSlope     * 0x7735 * 2 * link-speed
1766 		 *         -----------------            --------------    (E5)
1767 		 *         link-speed * 1000                 1000
1768 		 *
1769 		 * 'link-speed' is present in both sides of the fraction so
1770 		 * it is canceled out. The final equation is the following:
1771 		 *
1772 		 *     value = idleSlope * 61034
1773 		 *             -----------------                          (E6)
1774 		 *                  1000000
1775 		 *
1776 		 * NOTE: For i210, given the above, we can see that idleslope
1777 		 *       is represented in 16.38431 kbps units by the value at
1778 		 *       the TQAVCC register (1Gbps / 61034), which reduces
1779 		 *       the granularity for idleslope increments.
1780 		 *       For instance, if you want to configure a 2576kbps
1781 		 *       idleslope, the value to be written on the register
1782 		 *       would have to be 157.23. If rounded down, you end
1783 		 *       up with less bandwidth available than originally
1784 		 *       required (~2572 kbps). If rounded up, you end up
1785 		 *       with a higher bandwidth (~2589 kbps). Below the
1786 		 *       approach we take is to always round up the
1787 		 *       calculated value, so the resulting bandwidth might
1788 		 *       be slightly higher for some configurations.
1789 		 */
1790 		value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1791 
1792 		tqavcc = rd32(E1000_I210_TQAVCC(queue));
1793 		tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1794 		tqavcc |= value;
1795 		wr32(E1000_I210_TQAVCC(queue), tqavcc);
1796 
1797 		wr32(E1000_I210_TQAVHC(queue),
1798 		     0x80000000 + ring->hicredit * 0x7735);
1799 	} else {
1800 
1801 		/* Set idleSlope to zero. */
1802 		tqavcc = rd32(E1000_I210_TQAVCC(queue));
1803 		tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1804 		wr32(E1000_I210_TQAVCC(queue), tqavcc);
1805 
1806 		/* Set hiCredit to zero. */
1807 		wr32(E1000_I210_TQAVHC(queue), 0);
1808 
1809 		/* If CBS is not enabled for any queues anymore, then return to
1810 		 * the default state of Data Transmission Arbitration on
1811 		 * TQAVCTRL.
1812 		 */
1813 		if (!is_any_cbs_enabled(adapter)) {
1814 			tqavctrl = rd32(E1000_I210_TQAVCTRL);
1815 			tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1816 			wr32(E1000_I210_TQAVCTRL, tqavctrl);
1817 		}
1818 	}
1819 
1820 	/* If LaunchTime is enabled, set DataTranTIM. */
1821 	if (ring->launchtime_enable) {
1822 		/* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1823 		 * for any of the SR queues, and configure fetchtime delta.
1824 		 * XXX NOTE:
1825 		 *     - LaunchTime will be enabled for all SR queues.
1826 		 *     - A fixed offset can be added relative to the launch
1827 		 *       time of all packets if configured at reg LAUNCH_OS0.
1828 		 *       We are keeping it as 0 for now (default value).
1829 		 */
1830 		tqavctrl = rd32(E1000_I210_TQAVCTRL);
1831 		tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1832 		       E1000_TQAVCTRL_FETCHTIME_DELTA;
1833 		wr32(E1000_I210_TQAVCTRL, tqavctrl);
1834 	} else {
1835 		/* If Launchtime is not enabled for any SR queues anymore,
1836 		 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1837 		 * effectively disabling Launchtime.
1838 		 */
1839 		if (!is_any_txtime_enabled(adapter)) {
1840 			tqavctrl = rd32(E1000_I210_TQAVCTRL);
1841 			tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1842 			tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1843 			wr32(E1000_I210_TQAVCTRL, tqavctrl);
1844 		}
1845 	}
1846 
1847 	/* XXX: In i210 controller the sendSlope and loCredit parameters from
1848 	 * CBS are not configurable by software so we don't do any 'controller
1849 	 * configuration' in respect to these parameters.
1850 	 */
1851 
1852 	netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1853 		   ring->cbs_enable ? "enabled" : "disabled",
1854 		   ring->launchtime_enable ? "enabled" : "disabled",
1855 		   queue,
1856 		   ring->idleslope, ring->sendslope,
1857 		   ring->hicredit, ring->locredit);
1858 }
1859 
1860 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1861 				  bool enable)
1862 {
1863 	struct igb_ring *ring;
1864 
1865 	if (queue < 0 || queue > adapter->num_tx_queues)
1866 		return -EINVAL;
1867 
1868 	ring = adapter->tx_ring[queue];
1869 	ring->launchtime_enable = enable;
1870 
1871 	return 0;
1872 }
1873 
1874 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1875 			       bool enable, int idleslope, int sendslope,
1876 			       int hicredit, int locredit)
1877 {
1878 	struct igb_ring *ring;
1879 
1880 	if (queue < 0 || queue > adapter->num_tx_queues)
1881 		return -EINVAL;
1882 
1883 	ring = adapter->tx_ring[queue];
1884 
1885 	ring->cbs_enable = enable;
1886 	ring->idleslope = idleslope;
1887 	ring->sendslope = sendslope;
1888 	ring->hicredit = hicredit;
1889 	ring->locredit = locredit;
1890 
1891 	return 0;
1892 }
1893 
1894 /**
1895  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1896  *  @adapter: pointer to adapter struct
1897  *
1898  *  Configure TQAVCTRL register switching the controller's Tx mode
1899  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1900  *  a call to igb_config_tx_modes() per queue so any previously saved
1901  *  Tx parameters are applied.
1902  **/
1903 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1904 {
1905 	struct net_device *netdev = adapter->netdev;
1906 	struct e1000_hw *hw = &adapter->hw;
1907 	u32 val;
1908 
1909 	/* Only i210 controller supports changing the transmission mode. */
1910 	if (hw->mac.type != e1000_i210)
1911 		return;
1912 
1913 	if (is_fqtss_enabled(adapter)) {
1914 		int i, max_queue;
1915 
1916 		/* Configure TQAVCTRL register: set transmit mode to 'Qav',
1917 		 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1918 		 * so SP queues wait for SR ones.
1919 		 */
1920 		val = rd32(E1000_I210_TQAVCTRL);
1921 		val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1922 		val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1923 		wr32(E1000_I210_TQAVCTRL, val);
1924 
1925 		/* Configure Tx and Rx packet buffers sizes as described in
1926 		 * i210 datasheet section 7.2.7.7.
1927 		 */
1928 		val = rd32(E1000_TXPBS);
1929 		val &= ~I210_TXPBSIZE_MASK;
1930 		val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1931 			I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1932 		wr32(E1000_TXPBS, val);
1933 
1934 		val = rd32(E1000_RXPBS);
1935 		val &= ~I210_RXPBSIZE_MASK;
1936 		val |= I210_RXPBSIZE_PB_30KB;
1937 		wr32(E1000_RXPBS, val);
1938 
1939 		/* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1940 		 * register should not exceed the buffer size programmed in
1941 		 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1942 		 * so according to the datasheet we should set MAX_TPKT_SIZE to
1943 		 * 4kB / 64.
1944 		 *
1945 		 * However, when we do so, no frame from queue 2 and 3 are
1946 		 * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1947 		 * or _equal_ to the buffer size programmed in TXPBS. For this
1948 		 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1949 		 */
1950 		val = (4096 - 1) / 64;
1951 		wr32(E1000_I210_DTXMXPKTSZ, val);
1952 
1953 		/* Since FQTSS mode is enabled, apply any CBS configuration
1954 		 * previously set. If no previous CBS configuration has been
1955 		 * done, then the initial configuration is applied, which means
1956 		 * CBS is disabled.
1957 		 */
1958 		max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1959 			    adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1960 
1961 		for (i = 0; i < max_queue; i++) {
1962 			igb_config_tx_modes(adapter, i);
1963 		}
1964 	} else {
1965 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1966 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1967 		wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1968 
1969 		val = rd32(E1000_I210_TQAVCTRL);
1970 		/* According to Section 8.12.21, the other flags we've set when
1971 		 * enabling FQTSS are not relevant when disabling FQTSS so we
1972 		 * don't set they here.
1973 		 */
1974 		val &= ~E1000_TQAVCTRL_XMIT_MODE;
1975 		wr32(E1000_I210_TQAVCTRL, val);
1976 	}
1977 
1978 	netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1979 		   "enabled" : "disabled");
1980 }
1981 
1982 /**
1983  *  igb_configure - configure the hardware for RX and TX
1984  *  @adapter: private board structure
1985  **/
1986 static void igb_configure(struct igb_adapter *adapter)
1987 {
1988 	struct net_device *netdev = adapter->netdev;
1989 	int i;
1990 
1991 	igb_get_hw_control(adapter);
1992 	igb_set_rx_mode(netdev);
1993 	igb_setup_tx_mode(adapter);
1994 
1995 	igb_restore_vlan(adapter);
1996 
1997 	igb_setup_tctl(adapter);
1998 	igb_setup_mrqc(adapter);
1999 	igb_setup_rctl(adapter);
2000 
2001 	igb_nfc_filter_restore(adapter);
2002 	igb_configure_tx(adapter);
2003 	igb_configure_rx(adapter);
2004 
2005 	igb_rx_fifo_flush_82575(&adapter->hw);
2006 
2007 	/* call igb_desc_unused which always leaves
2008 	 * at least 1 descriptor unused to make sure
2009 	 * next_to_use != next_to_clean
2010 	 */
2011 	for (i = 0; i < adapter->num_rx_queues; i++) {
2012 		struct igb_ring *ring = adapter->rx_ring[i];
2013 		igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2014 	}
2015 }
2016 
2017 /**
2018  *  igb_power_up_link - Power up the phy/serdes link
2019  *  @adapter: address of board private structure
2020  **/
2021 void igb_power_up_link(struct igb_adapter *adapter)
2022 {
2023 	igb_reset_phy(&adapter->hw);
2024 
2025 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
2026 		igb_power_up_phy_copper(&adapter->hw);
2027 	else
2028 		igb_power_up_serdes_link_82575(&adapter->hw);
2029 
2030 	igb_setup_link(&adapter->hw);
2031 }
2032 
2033 /**
2034  *  igb_power_down_link - Power down the phy/serdes link
2035  *  @adapter: address of board private structure
2036  */
2037 static void igb_power_down_link(struct igb_adapter *adapter)
2038 {
2039 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
2040 		igb_power_down_phy_copper_82575(&adapter->hw);
2041 	else
2042 		igb_shutdown_serdes_link_82575(&adapter->hw);
2043 }
2044 
2045 /**
2046  * igb_check_swap_media -  Detect and switch function for Media Auto Sense
2047  * @adapter: address of the board private structure
2048  **/
2049 static void igb_check_swap_media(struct igb_adapter *adapter)
2050 {
2051 	struct e1000_hw *hw = &adapter->hw;
2052 	u32 ctrl_ext, connsw;
2053 	bool swap_now = false;
2054 
2055 	ctrl_ext = rd32(E1000_CTRL_EXT);
2056 	connsw = rd32(E1000_CONNSW);
2057 
2058 	/* need to live swap if current media is copper and we have fiber/serdes
2059 	 * to go to.
2060 	 */
2061 
2062 	if ((hw->phy.media_type == e1000_media_type_copper) &&
2063 	    (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2064 		swap_now = true;
2065 	} else if ((hw->phy.media_type != e1000_media_type_copper) &&
2066 		   !(connsw & E1000_CONNSW_SERDESD)) {
2067 		/* copper signal takes time to appear */
2068 		if (adapter->copper_tries < 4) {
2069 			adapter->copper_tries++;
2070 			connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2071 			wr32(E1000_CONNSW, connsw);
2072 			return;
2073 		} else {
2074 			adapter->copper_tries = 0;
2075 			if ((connsw & E1000_CONNSW_PHYSD) &&
2076 			    (!(connsw & E1000_CONNSW_PHY_PDN))) {
2077 				swap_now = true;
2078 				connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2079 				wr32(E1000_CONNSW, connsw);
2080 			}
2081 		}
2082 	}
2083 
2084 	if (!swap_now)
2085 		return;
2086 
2087 	switch (hw->phy.media_type) {
2088 	case e1000_media_type_copper:
2089 		netdev_info(adapter->netdev,
2090 			"MAS: changing media to fiber/serdes\n");
2091 		ctrl_ext |=
2092 			E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2093 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
2094 		adapter->copper_tries = 0;
2095 		break;
2096 	case e1000_media_type_internal_serdes:
2097 	case e1000_media_type_fiber:
2098 		netdev_info(adapter->netdev,
2099 			"MAS: changing media to copper\n");
2100 		ctrl_ext &=
2101 			~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2102 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
2103 		break;
2104 	default:
2105 		/* shouldn't get here during regular operation */
2106 		netdev_err(adapter->netdev,
2107 			"AMS: Invalid media type found, returning\n");
2108 		break;
2109 	}
2110 	wr32(E1000_CTRL_EXT, ctrl_ext);
2111 }
2112 
2113 /**
2114  *  igb_up - Open the interface and prepare it to handle traffic
2115  *  @adapter: board private structure
2116  **/
2117 int igb_up(struct igb_adapter *adapter)
2118 {
2119 	struct e1000_hw *hw = &adapter->hw;
2120 	int i;
2121 
2122 	/* hardware has been reset, we need to reload some things */
2123 	igb_configure(adapter);
2124 
2125 	clear_bit(__IGB_DOWN, &adapter->state);
2126 
2127 	for (i = 0; i < adapter->num_q_vectors; i++)
2128 		napi_enable(&(adapter->q_vector[i]->napi));
2129 
2130 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
2131 		igb_configure_msix(adapter);
2132 	else
2133 		igb_assign_vector(adapter->q_vector[0], 0);
2134 
2135 	/* Clear any pending interrupts. */
2136 	rd32(E1000_TSICR);
2137 	rd32(E1000_ICR);
2138 	igb_irq_enable(adapter);
2139 
2140 	/* notify VFs that reset has been completed */
2141 	if (adapter->vfs_allocated_count) {
2142 		u32 reg_data = rd32(E1000_CTRL_EXT);
2143 
2144 		reg_data |= E1000_CTRL_EXT_PFRSTD;
2145 		wr32(E1000_CTRL_EXT, reg_data);
2146 	}
2147 
2148 	netif_tx_start_all_queues(adapter->netdev);
2149 
2150 	/* start the watchdog. */
2151 	hw->mac.get_link_status = 1;
2152 	schedule_work(&adapter->watchdog_task);
2153 
2154 	if ((adapter->flags & IGB_FLAG_EEE) &&
2155 	    (!hw->dev_spec._82575.eee_disable))
2156 		adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2157 
2158 	return 0;
2159 }
2160 
2161 void igb_down(struct igb_adapter *adapter)
2162 {
2163 	struct net_device *netdev = adapter->netdev;
2164 	struct e1000_hw *hw = &adapter->hw;
2165 	u32 tctl, rctl;
2166 	int i;
2167 
2168 	/* signal that we're down so the interrupt handler does not
2169 	 * reschedule our watchdog timer
2170 	 */
2171 	set_bit(__IGB_DOWN, &adapter->state);
2172 
2173 	/* disable receives in the hardware */
2174 	rctl = rd32(E1000_RCTL);
2175 	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2176 	/* flush and sleep below */
2177 
2178 	igb_nfc_filter_exit(adapter);
2179 
2180 	netif_carrier_off(netdev);
2181 	netif_tx_stop_all_queues(netdev);
2182 
2183 	/* disable transmits in the hardware */
2184 	tctl = rd32(E1000_TCTL);
2185 	tctl &= ~E1000_TCTL_EN;
2186 	wr32(E1000_TCTL, tctl);
2187 	/* flush both disables and wait for them to finish */
2188 	wrfl();
2189 	usleep_range(10000, 11000);
2190 
2191 	igb_irq_disable(adapter);
2192 
2193 	adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2194 
2195 	for (i = 0; i < adapter->num_q_vectors; i++) {
2196 		if (adapter->q_vector[i]) {
2197 			napi_synchronize(&adapter->q_vector[i]->napi);
2198 			napi_disable(&adapter->q_vector[i]->napi);
2199 		}
2200 	}
2201 
2202 	del_timer_sync(&adapter->watchdog_timer);
2203 	del_timer_sync(&adapter->phy_info_timer);
2204 
2205 	/* record the stats before reset*/
2206 	spin_lock(&adapter->stats64_lock);
2207 	igb_update_stats(adapter);
2208 	spin_unlock(&adapter->stats64_lock);
2209 
2210 	adapter->link_speed = 0;
2211 	adapter->link_duplex = 0;
2212 
2213 	if (!pci_channel_offline(adapter->pdev))
2214 		igb_reset(adapter);
2215 
2216 	/* clear VLAN promisc flag so VFTA will be updated if necessary */
2217 	adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2218 
2219 	igb_clean_all_tx_rings(adapter);
2220 	igb_clean_all_rx_rings(adapter);
2221 #ifdef CONFIG_IGB_DCA
2222 
2223 	/* since we reset the hardware DCA settings were cleared */
2224 	igb_setup_dca(adapter);
2225 #endif
2226 }
2227 
2228 void igb_reinit_locked(struct igb_adapter *adapter)
2229 {
2230 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2231 		usleep_range(1000, 2000);
2232 	igb_down(adapter);
2233 	igb_up(adapter);
2234 	clear_bit(__IGB_RESETTING, &adapter->state);
2235 }
2236 
2237 /** igb_enable_mas - Media Autosense re-enable after swap
2238  *
2239  * @adapter: adapter struct
2240  **/
2241 static void igb_enable_mas(struct igb_adapter *adapter)
2242 {
2243 	struct e1000_hw *hw = &adapter->hw;
2244 	u32 connsw = rd32(E1000_CONNSW);
2245 
2246 	/* configure for SerDes media detect */
2247 	if ((hw->phy.media_type == e1000_media_type_copper) &&
2248 	    (!(connsw & E1000_CONNSW_SERDESD))) {
2249 		connsw |= E1000_CONNSW_ENRGSRC;
2250 		connsw |= E1000_CONNSW_AUTOSENSE_EN;
2251 		wr32(E1000_CONNSW, connsw);
2252 		wrfl();
2253 	}
2254 }
2255 
2256 void igb_reset(struct igb_adapter *adapter)
2257 {
2258 	struct pci_dev *pdev = adapter->pdev;
2259 	struct e1000_hw *hw = &adapter->hw;
2260 	struct e1000_mac_info *mac = &hw->mac;
2261 	struct e1000_fc_info *fc = &hw->fc;
2262 	u32 pba, hwm;
2263 
2264 	/* Repartition Pba for greater than 9k mtu
2265 	 * To take effect CTRL.RST is required.
2266 	 */
2267 	switch (mac->type) {
2268 	case e1000_i350:
2269 	case e1000_i354:
2270 	case e1000_82580:
2271 		pba = rd32(E1000_RXPBS);
2272 		pba = igb_rxpbs_adjust_82580(pba);
2273 		break;
2274 	case e1000_82576:
2275 		pba = rd32(E1000_RXPBS);
2276 		pba &= E1000_RXPBS_SIZE_MASK_82576;
2277 		break;
2278 	case e1000_82575:
2279 	case e1000_i210:
2280 	case e1000_i211:
2281 	default:
2282 		pba = E1000_PBA_34K;
2283 		break;
2284 	}
2285 
2286 	if (mac->type == e1000_82575) {
2287 		u32 min_rx_space, min_tx_space, needed_tx_space;
2288 
2289 		/* write Rx PBA so that hardware can report correct Tx PBA */
2290 		wr32(E1000_PBA, pba);
2291 
2292 		/* To maintain wire speed transmits, the Tx FIFO should be
2293 		 * large enough to accommodate two full transmit packets,
2294 		 * rounded up to the next 1KB and expressed in KB.  Likewise,
2295 		 * the Rx FIFO should be large enough to accommodate at least
2296 		 * one full receive packet and is similarly rounded up and
2297 		 * expressed in KB.
2298 		 */
2299 		min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2300 
2301 		/* The Tx FIFO also stores 16 bytes of information about the Tx
2302 		 * but don't include Ethernet FCS because hardware appends it.
2303 		 * We only need to round down to the nearest 512 byte block
2304 		 * count since the value we care about is 2 frames, not 1.
2305 		 */
2306 		min_tx_space = adapter->max_frame_size;
2307 		min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2308 		min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2309 
2310 		/* upper 16 bits has Tx packet buffer allocation size in KB */
2311 		needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2312 
2313 		/* If current Tx allocation is less than the min Tx FIFO size,
2314 		 * and the min Tx FIFO size is less than the current Rx FIFO
2315 		 * allocation, take space away from current Rx allocation.
2316 		 */
2317 		if (needed_tx_space < pba) {
2318 			pba -= needed_tx_space;
2319 
2320 			/* if short on Rx space, Rx wins and must trump Tx
2321 			 * adjustment
2322 			 */
2323 			if (pba < min_rx_space)
2324 				pba = min_rx_space;
2325 		}
2326 
2327 		/* adjust PBA for jumbo frames */
2328 		wr32(E1000_PBA, pba);
2329 	}
2330 
2331 	/* flow control settings
2332 	 * The high water mark must be low enough to fit one full frame
2333 	 * after transmitting the pause frame.  As such we must have enough
2334 	 * space to allow for us to complete our current transmit and then
2335 	 * receive the frame that is in progress from the link partner.
2336 	 * Set it to:
2337 	 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2338 	 */
2339 	hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2340 
2341 	fc->high_water = hwm & 0xFFFFFFF0;	/* 16-byte granularity */
2342 	fc->low_water = fc->high_water - 16;
2343 	fc->pause_time = 0xFFFF;
2344 	fc->send_xon = 1;
2345 	fc->current_mode = fc->requested_mode;
2346 
2347 	/* disable receive for all VFs and wait one second */
2348 	if (adapter->vfs_allocated_count) {
2349 		int i;
2350 
2351 		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2352 			adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2353 
2354 		/* ping all the active vfs to let them know we are going down */
2355 		igb_ping_all_vfs(adapter);
2356 
2357 		/* disable transmits and receives */
2358 		wr32(E1000_VFRE, 0);
2359 		wr32(E1000_VFTE, 0);
2360 	}
2361 
2362 	/* Allow time for pending master requests to run */
2363 	hw->mac.ops.reset_hw(hw);
2364 	wr32(E1000_WUC, 0);
2365 
2366 	if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2367 		/* need to resetup here after media swap */
2368 		adapter->ei.get_invariants(hw);
2369 		adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2370 	}
2371 	if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2372 	    (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2373 		igb_enable_mas(adapter);
2374 	}
2375 	if (hw->mac.ops.init_hw(hw))
2376 		dev_err(&pdev->dev, "Hardware Error\n");
2377 
2378 	/* RAR registers were cleared during init_hw, clear mac table */
2379 	igb_flush_mac_table(adapter);
2380 	__dev_uc_unsync(adapter->netdev, NULL);
2381 
2382 	/* Recover default RAR entry */
2383 	igb_set_default_mac_filter(adapter);
2384 
2385 	/* Flow control settings reset on hardware reset, so guarantee flow
2386 	 * control is off when forcing speed.
2387 	 */
2388 	if (!hw->mac.autoneg)
2389 		igb_force_mac_fc(hw);
2390 
2391 	igb_init_dmac(adapter, pba);
2392 #ifdef CONFIG_IGB_HWMON
2393 	/* Re-initialize the thermal sensor on i350 devices. */
2394 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
2395 		if (mac->type == e1000_i350 && hw->bus.func == 0) {
2396 			/* If present, re-initialize the external thermal sensor
2397 			 * interface.
2398 			 */
2399 			if (adapter->ets)
2400 				mac->ops.init_thermal_sensor_thresh(hw);
2401 		}
2402 	}
2403 #endif
2404 	/* Re-establish EEE setting */
2405 	if (hw->phy.media_type == e1000_media_type_copper) {
2406 		switch (mac->type) {
2407 		case e1000_i350:
2408 		case e1000_i210:
2409 		case e1000_i211:
2410 			igb_set_eee_i350(hw, true, true);
2411 			break;
2412 		case e1000_i354:
2413 			igb_set_eee_i354(hw, true, true);
2414 			break;
2415 		default:
2416 			break;
2417 		}
2418 	}
2419 	if (!netif_running(adapter->netdev))
2420 		igb_power_down_link(adapter);
2421 
2422 	igb_update_mng_vlan(adapter);
2423 
2424 	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2425 	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2426 
2427 	/* Re-enable PTP, where applicable. */
2428 	if (adapter->ptp_flags & IGB_PTP_ENABLED)
2429 		igb_ptp_reset(adapter);
2430 
2431 	igb_get_phy_info(hw);
2432 }
2433 
2434 static netdev_features_t igb_fix_features(struct net_device *netdev,
2435 	netdev_features_t features)
2436 {
2437 	/* Since there is no support for separate Rx/Tx vlan accel
2438 	 * enable/disable make sure Tx flag is always in same state as Rx.
2439 	 */
2440 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
2441 		features |= NETIF_F_HW_VLAN_CTAG_TX;
2442 	else
2443 		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2444 
2445 	return features;
2446 }
2447 
2448 static int igb_set_features(struct net_device *netdev,
2449 	netdev_features_t features)
2450 {
2451 	netdev_features_t changed = netdev->features ^ features;
2452 	struct igb_adapter *adapter = netdev_priv(netdev);
2453 
2454 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2455 		igb_vlan_mode(netdev, features);
2456 
2457 	if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2458 		return 0;
2459 
2460 	if (!(features & NETIF_F_NTUPLE)) {
2461 		struct hlist_node *node2;
2462 		struct igb_nfc_filter *rule;
2463 
2464 		spin_lock(&adapter->nfc_lock);
2465 		hlist_for_each_entry_safe(rule, node2,
2466 					  &adapter->nfc_filter_list, nfc_node) {
2467 			igb_erase_filter(adapter, rule);
2468 			hlist_del(&rule->nfc_node);
2469 			kfree(rule);
2470 		}
2471 		spin_unlock(&adapter->nfc_lock);
2472 		adapter->nfc_filter_count = 0;
2473 	}
2474 
2475 	netdev->features = features;
2476 
2477 	if (netif_running(netdev))
2478 		igb_reinit_locked(adapter);
2479 	else
2480 		igb_reset(adapter);
2481 
2482 	return 1;
2483 }
2484 
2485 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2486 			   struct net_device *dev,
2487 			   const unsigned char *addr, u16 vid,
2488 			   u16 flags,
2489 			   struct netlink_ext_ack *extack)
2490 {
2491 	/* guarantee we can provide a unique filter for the unicast address */
2492 	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2493 		struct igb_adapter *adapter = netdev_priv(dev);
2494 		int vfn = adapter->vfs_allocated_count;
2495 
2496 		if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2497 			return -ENOMEM;
2498 	}
2499 
2500 	return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2501 }
2502 
2503 #define IGB_MAX_MAC_HDR_LEN	127
2504 #define IGB_MAX_NETWORK_HDR_LEN	511
2505 
2506 static netdev_features_t
2507 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2508 		   netdev_features_t features)
2509 {
2510 	unsigned int network_hdr_len, mac_hdr_len;
2511 
2512 	/* Make certain the headers can be described by a context descriptor */
2513 	mac_hdr_len = skb_network_header(skb) - skb->data;
2514 	if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2515 		return features & ~(NETIF_F_HW_CSUM |
2516 				    NETIF_F_SCTP_CRC |
2517 				    NETIF_F_GSO_UDP_L4 |
2518 				    NETIF_F_HW_VLAN_CTAG_TX |
2519 				    NETIF_F_TSO |
2520 				    NETIF_F_TSO6);
2521 
2522 	network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2523 	if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2524 		return features & ~(NETIF_F_HW_CSUM |
2525 				    NETIF_F_SCTP_CRC |
2526 				    NETIF_F_GSO_UDP_L4 |
2527 				    NETIF_F_TSO |
2528 				    NETIF_F_TSO6);
2529 
2530 	/* We can only support IPV4 TSO in tunnels if we can mangle the
2531 	 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2532 	 */
2533 	if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2534 		features &= ~NETIF_F_TSO;
2535 
2536 	return features;
2537 }
2538 
2539 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2540 {
2541 	if (!is_fqtss_enabled(adapter)) {
2542 		enable_fqtss(adapter, true);
2543 		return;
2544 	}
2545 
2546 	igb_config_tx_modes(adapter, queue);
2547 
2548 	if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2549 		enable_fqtss(adapter, false);
2550 }
2551 
2552 static int igb_offload_cbs(struct igb_adapter *adapter,
2553 			   struct tc_cbs_qopt_offload *qopt)
2554 {
2555 	struct e1000_hw *hw = &adapter->hw;
2556 	int err;
2557 
2558 	/* CBS offloading is only supported by i210 controller. */
2559 	if (hw->mac.type != e1000_i210)
2560 		return -EOPNOTSUPP;
2561 
2562 	/* CBS offloading is only supported by queue 0 and queue 1. */
2563 	if (qopt->queue < 0 || qopt->queue > 1)
2564 		return -EINVAL;
2565 
2566 	err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2567 				  qopt->idleslope, qopt->sendslope,
2568 				  qopt->hicredit, qopt->locredit);
2569 	if (err)
2570 		return err;
2571 
2572 	igb_offload_apply(adapter, qopt->queue);
2573 
2574 	return 0;
2575 }
2576 
2577 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2578 #define VLAN_PRIO_FULL_MASK (0x07)
2579 
2580 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2581 				struct flow_cls_offload *f,
2582 				int traffic_class,
2583 				struct igb_nfc_filter *input)
2584 {
2585 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2586 	struct flow_dissector *dissector = rule->match.dissector;
2587 	struct netlink_ext_ack *extack = f->common.extack;
2588 
2589 	if (dissector->used_keys &
2590 	    ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2591 	      BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2592 	      BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2593 	      BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2594 		NL_SET_ERR_MSG_MOD(extack,
2595 				   "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2596 		return -EOPNOTSUPP;
2597 	}
2598 
2599 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2600 		struct flow_match_eth_addrs match;
2601 
2602 		flow_rule_match_eth_addrs(rule, &match);
2603 		if (!is_zero_ether_addr(match.mask->dst)) {
2604 			if (!is_broadcast_ether_addr(match.mask->dst)) {
2605 				NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2606 				return -EINVAL;
2607 			}
2608 
2609 			input->filter.match_flags |=
2610 				IGB_FILTER_FLAG_DST_MAC_ADDR;
2611 			ether_addr_copy(input->filter.dst_addr, match.key->dst);
2612 		}
2613 
2614 		if (!is_zero_ether_addr(match.mask->src)) {
2615 			if (!is_broadcast_ether_addr(match.mask->src)) {
2616 				NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2617 				return -EINVAL;
2618 			}
2619 
2620 			input->filter.match_flags |=
2621 				IGB_FILTER_FLAG_SRC_MAC_ADDR;
2622 			ether_addr_copy(input->filter.src_addr, match.key->src);
2623 		}
2624 	}
2625 
2626 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2627 		struct flow_match_basic match;
2628 
2629 		flow_rule_match_basic(rule, &match);
2630 		if (match.mask->n_proto) {
2631 			if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2632 				NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2633 				return -EINVAL;
2634 			}
2635 
2636 			input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2637 			input->filter.etype = match.key->n_proto;
2638 		}
2639 	}
2640 
2641 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2642 		struct flow_match_vlan match;
2643 
2644 		flow_rule_match_vlan(rule, &match);
2645 		if (match.mask->vlan_priority) {
2646 			if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2647 				NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2648 				return -EINVAL;
2649 			}
2650 
2651 			input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2652 			input->filter.vlan_tci =
2653 				(__force __be16)match.key->vlan_priority;
2654 		}
2655 	}
2656 
2657 	input->action = traffic_class;
2658 	input->cookie = f->cookie;
2659 
2660 	return 0;
2661 }
2662 
2663 static int igb_configure_clsflower(struct igb_adapter *adapter,
2664 				   struct flow_cls_offload *cls_flower)
2665 {
2666 	struct netlink_ext_ack *extack = cls_flower->common.extack;
2667 	struct igb_nfc_filter *filter, *f;
2668 	int err, tc;
2669 
2670 	tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2671 	if (tc < 0) {
2672 		NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2673 		return -EINVAL;
2674 	}
2675 
2676 	filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2677 	if (!filter)
2678 		return -ENOMEM;
2679 
2680 	err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2681 	if (err < 0)
2682 		goto err_parse;
2683 
2684 	spin_lock(&adapter->nfc_lock);
2685 
2686 	hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2687 		if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2688 			err = -EEXIST;
2689 			NL_SET_ERR_MSG_MOD(extack,
2690 					   "This filter is already set in ethtool");
2691 			goto err_locked;
2692 		}
2693 	}
2694 
2695 	hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2696 		if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2697 			err = -EEXIST;
2698 			NL_SET_ERR_MSG_MOD(extack,
2699 					   "This filter is already set in cls_flower");
2700 			goto err_locked;
2701 		}
2702 	}
2703 
2704 	err = igb_add_filter(adapter, filter);
2705 	if (err < 0) {
2706 		NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2707 		goto err_locked;
2708 	}
2709 
2710 	hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2711 
2712 	spin_unlock(&adapter->nfc_lock);
2713 
2714 	return 0;
2715 
2716 err_locked:
2717 	spin_unlock(&adapter->nfc_lock);
2718 
2719 err_parse:
2720 	kfree(filter);
2721 
2722 	return err;
2723 }
2724 
2725 static int igb_delete_clsflower(struct igb_adapter *adapter,
2726 				struct flow_cls_offload *cls_flower)
2727 {
2728 	struct igb_nfc_filter *filter;
2729 	int err;
2730 
2731 	spin_lock(&adapter->nfc_lock);
2732 
2733 	hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2734 		if (filter->cookie == cls_flower->cookie)
2735 			break;
2736 
2737 	if (!filter) {
2738 		err = -ENOENT;
2739 		goto out;
2740 	}
2741 
2742 	err = igb_erase_filter(adapter, filter);
2743 	if (err < 0)
2744 		goto out;
2745 
2746 	hlist_del(&filter->nfc_node);
2747 	kfree(filter);
2748 
2749 out:
2750 	spin_unlock(&adapter->nfc_lock);
2751 
2752 	return err;
2753 }
2754 
2755 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2756 				   struct flow_cls_offload *cls_flower)
2757 {
2758 	switch (cls_flower->command) {
2759 	case FLOW_CLS_REPLACE:
2760 		return igb_configure_clsflower(adapter, cls_flower);
2761 	case FLOW_CLS_DESTROY:
2762 		return igb_delete_clsflower(adapter, cls_flower);
2763 	case FLOW_CLS_STATS:
2764 		return -EOPNOTSUPP;
2765 	default:
2766 		return -EOPNOTSUPP;
2767 	}
2768 }
2769 
2770 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2771 				 void *cb_priv)
2772 {
2773 	struct igb_adapter *adapter = cb_priv;
2774 
2775 	if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2776 		return -EOPNOTSUPP;
2777 
2778 	switch (type) {
2779 	case TC_SETUP_CLSFLOWER:
2780 		return igb_setup_tc_cls_flower(adapter, type_data);
2781 
2782 	default:
2783 		return -EOPNOTSUPP;
2784 	}
2785 }
2786 
2787 static int igb_offload_txtime(struct igb_adapter *adapter,
2788 			      struct tc_etf_qopt_offload *qopt)
2789 {
2790 	struct e1000_hw *hw = &adapter->hw;
2791 	int err;
2792 
2793 	/* Launchtime offloading is only supported by i210 controller. */
2794 	if (hw->mac.type != e1000_i210)
2795 		return -EOPNOTSUPP;
2796 
2797 	/* Launchtime offloading is only supported by queues 0 and 1. */
2798 	if (qopt->queue < 0 || qopt->queue > 1)
2799 		return -EINVAL;
2800 
2801 	err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2802 	if (err)
2803 		return err;
2804 
2805 	igb_offload_apply(adapter, qopt->queue);
2806 
2807 	return 0;
2808 }
2809 
2810 static LIST_HEAD(igb_block_cb_list);
2811 
2812 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2813 			void *type_data)
2814 {
2815 	struct igb_adapter *adapter = netdev_priv(dev);
2816 
2817 	switch (type) {
2818 	case TC_SETUP_QDISC_CBS:
2819 		return igb_offload_cbs(adapter, type_data);
2820 	case TC_SETUP_BLOCK:
2821 		return flow_block_cb_setup_simple(type_data,
2822 						  &igb_block_cb_list,
2823 						  igb_setup_tc_block_cb,
2824 						  adapter, adapter, true);
2825 
2826 	case TC_SETUP_QDISC_ETF:
2827 		return igb_offload_txtime(adapter, type_data);
2828 
2829 	default:
2830 		return -EOPNOTSUPP;
2831 	}
2832 }
2833 
2834 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2835 {
2836 	int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2837 	struct igb_adapter *adapter = netdev_priv(dev);
2838 	struct bpf_prog *prog = bpf->prog, *old_prog;
2839 	bool running = netif_running(dev);
2840 	bool need_reset;
2841 
2842 	/* verify igb ring attributes are sufficient for XDP */
2843 	for (i = 0; i < adapter->num_rx_queues; i++) {
2844 		struct igb_ring *ring = adapter->rx_ring[i];
2845 
2846 		if (frame_size > igb_rx_bufsz(ring)) {
2847 			NL_SET_ERR_MSG_MOD(bpf->extack,
2848 					   "The RX buffer size is too small for the frame size");
2849 			netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2850 				    igb_rx_bufsz(ring), frame_size);
2851 			return -EINVAL;
2852 		}
2853 	}
2854 
2855 	old_prog = xchg(&adapter->xdp_prog, prog);
2856 	need_reset = (!!prog != !!old_prog);
2857 
2858 	/* device is up and bpf is added/removed, must setup the RX queues */
2859 	if (need_reset && running) {
2860 		igb_close(dev);
2861 	} else {
2862 		for (i = 0; i < adapter->num_rx_queues; i++)
2863 			(void)xchg(&adapter->rx_ring[i]->xdp_prog,
2864 			    adapter->xdp_prog);
2865 	}
2866 
2867 	if (old_prog)
2868 		bpf_prog_put(old_prog);
2869 
2870 	/* bpf is just replaced, RXQ and MTU are already setup */
2871 	if (!need_reset)
2872 		return 0;
2873 
2874 	if (running)
2875 		igb_open(dev);
2876 
2877 	return 0;
2878 }
2879 
2880 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2881 {
2882 	switch (xdp->command) {
2883 	case XDP_SETUP_PROG:
2884 		return igb_xdp_setup(dev, xdp);
2885 	default:
2886 		return -EINVAL;
2887 	}
2888 }
2889 
2890 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2891 {
2892 	/* Force memory writes to complete before letting h/w know there
2893 	 * are new descriptors to fetch.
2894 	 */
2895 	wmb();
2896 	writel(ring->next_to_use, ring->tail);
2897 }
2898 
2899 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2900 {
2901 	unsigned int r_idx = smp_processor_id();
2902 
2903 	if (r_idx >= adapter->num_tx_queues)
2904 		r_idx = r_idx % adapter->num_tx_queues;
2905 
2906 	return adapter->tx_ring[r_idx];
2907 }
2908 
2909 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2910 {
2911 	struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2912 	int cpu = smp_processor_id();
2913 	struct igb_ring *tx_ring;
2914 	struct netdev_queue *nq;
2915 	u32 ret;
2916 
2917 	if (unlikely(!xdpf))
2918 		return IGB_XDP_CONSUMED;
2919 
2920 	/* During program transitions its possible adapter->xdp_prog is assigned
2921 	 * but ring has not been configured yet. In this case simply abort xmit.
2922 	 */
2923 	tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2924 	if (unlikely(!tx_ring))
2925 		return IGB_XDP_CONSUMED;
2926 
2927 	nq = txring_txq(tx_ring);
2928 	__netif_tx_lock(nq, cpu);
2929 	/* Avoid transmit queue timeout since we share it with the slow path */
2930 	txq_trans_cond_update(nq);
2931 	ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2932 	__netif_tx_unlock(nq);
2933 
2934 	return ret;
2935 }
2936 
2937 static int igb_xdp_xmit(struct net_device *dev, int n,
2938 			struct xdp_frame **frames, u32 flags)
2939 {
2940 	struct igb_adapter *adapter = netdev_priv(dev);
2941 	int cpu = smp_processor_id();
2942 	struct igb_ring *tx_ring;
2943 	struct netdev_queue *nq;
2944 	int nxmit = 0;
2945 	int i;
2946 
2947 	if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2948 		return -ENETDOWN;
2949 
2950 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2951 		return -EINVAL;
2952 
2953 	/* During program transitions its possible adapter->xdp_prog is assigned
2954 	 * but ring has not been configured yet. In this case simply abort xmit.
2955 	 */
2956 	tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2957 	if (unlikely(!tx_ring))
2958 		return -ENXIO;
2959 
2960 	nq = txring_txq(tx_ring);
2961 	__netif_tx_lock(nq, cpu);
2962 
2963 	/* Avoid transmit queue timeout since we share it with the slow path */
2964 	txq_trans_cond_update(nq);
2965 
2966 	for (i = 0; i < n; i++) {
2967 		struct xdp_frame *xdpf = frames[i];
2968 		int err;
2969 
2970 		err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2971 		if (err != IGB_XDP_TX)
2972 			break;
2973 		nxmit++;
2974 	}
2975 
2976 	__netif_tx_unlock(nq);
2977 
2978 	if (unlikely(flags & XDP_XMIT_FLUSH))
2979 		igb_xdp_ring_update_tail(tx_ring);
2980 
2981 	return nxmit;
2982 }
2983 
2984 static const struct net_device_ops igb_netdev_ops = {
2985 	.ndo_open		= igb_open,
2986 	.ndo_stop		= igb_close,
2987 	.ndo_start_xmit		= igb_xmit_frame,
2988 	.ndo_get_stats64	= igb_get_stats64,
2989 	.ndo_set_rx_mode	= igb_set_rx_mode,
2990 	.ndo_set_mac_address	= igb_set_mac,
2991 	.ndo_change_mtu		= igb_change_mtu,
2992 	.ndo_eth_ioctl		= igb_ioctl,
2993 	.ndo_tx_timeout		= igb_tx_timeout,
2994 	.ndo_validate_addr	= eth_validate_addr,
2995 	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
2996 	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
2997 	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
2998 	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
2999 	.ndo_set_vf_rate	= igb_ndo_set_vf_bw,
3000 	.ndo_set_vf_spoofchk	= igb_ndo_set_vf_spoofchk,
3001 	.ndo_set_vf_trust	= igb_ndo_set_vf_trust,
3002 	.ndo_get_vf_config	= igb_ndo_get_vf_config,
3003 	.ndo_fix_features	= igb_fix_features,
3004 	.ndo_set_features	= igb_set_features,
3005 	.ndo_fdb_add		= igb_ndo_fdb_add,
3006 	.ndo_features_check	= igb_features_check,
3007 	.ndo_setup_tc		= igb_setup_tc,
3008 	.ndo_bpf		= igb_xdp,
3009 	.ndo_xdp_xmit		= igb_xdp_xmit,
3010 };
3011 
3012 /**
3013  * igb_set_fw_version - Configure version string for ethtool
3014  * @adapter: adapter struct
3015  **/
3016 void igb_set_fw_version(struct igb_adapter *adapter)
3017 {
3018 	struct e1000_hw *hw = &adapter->hw;
3019 	struct e1000_fw_version fw;
3020 
3021 	igb_get_fw_version(hw, &fw);
3022 
3023 	switch (hw->mac.type) {
3024 	case e1000_i210:
3025 	case e1000_i211:
3026 		if (!(igb_get_flash_presence_i210(hw))) {
3027 			snprintf(adapter->fw_version,
3028 				 sizeof(adapter->fw_version),
3029 				 "%2d.%2d-%d",
3030 				 fw.invm_major, fw.invm_minor,
3031 				 fw.invm_img_type);
3032 			break;
3033 		}
3034 		fallthrough;
3035 	default:
3036 		/* if option is rom valid, display its version too */
3037 		if (fw.or_valid) {
3038 			snprintf(adapter->fw_version,
3039 				 sizeof(adapter->fw_version),
3040 				 "%d.%d, 0x%08x, %d.%d.%d",
3041 				 fw.eep_major, fw.eep_minor, fw.etrack_id,
3042 				 fw.or_major, fw.or_build, fw.or_patch);
3043 		/* no option rom */
3044 		} else if (fw.etrack_id != 0X0000) {
3045 			snprintf(adapter->fw_version,
3046 			    sizeof(adapter->fw_version),
3047 			    "%d.%d, 0x%08x",
3048 			    fw.eep_major, fw.eep_minor, fw.etrack_id);
3049 		} else {
3050 		snprintf(adapter->fw_version,
3051 		    sizeof(adapter->fw_version),
3052 		    "%d.%d.%d",
3053 		    fw.eep_major, fw.eep_minor, fw.eep_build);
3054 		}
3055 		break;
3056 	}
3057 }
3058 
3059 /**
3060  * igb_init_mas - init Media Autosense feature if enabled in the NVM
3061  *
3062  * @adapter: adapter struct
3063  **/
3064 static void igb_init_mas(struct igb_adapter *adapter)
3065 {
3066 	struct e1000_hw *hw = &adapter->hw;
3067 	u16 eeprom_data;
3068 
3069 	hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3070 	switch (hw->bus.func) {
3071 	case E1000_FUNC_0:
3072 		if (eeprom_data & IGB_MAS_ENABLE_0) {
3073 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3074 			netdev_info(adapter->netdev,
3075 				"MAS: Enabling Media Autosense for port %d\n",
3076 				hw->bus.func);
3077 		}
3078 		break;
3079 	case E1000_FUNC_1:
3080 		if (eeprom_data & IGB_MAS_ENABLE_1) {
3081 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3082 			netdev_info(adapter->netdev,
3083 				"MAS: Enabling Media Autosense for port %d\n",
3084 				hw->bus.func);
3085 		}
3086 		break;
3087 	case E1000_FUNC_2:
3088 		if (eeprom_data & IGB_MAS_ENABLE_2) {
3089 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3090 			netdev_info(adapter->netdev,
3091 				"MAS: Enabling Media Autosense for port %d\n",
3092 				hw->bus.func);
3093 		}
3094 		break;
3095 	case E1000_FUNC_3:
3096 		if (eeprom_data & IGB_MAS_ENABLE_3) {
3097 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3098 			netdev_info(adapter->netdev,
3099 				"MAS: Enabling Media Autosense for port %d\n",
3100 				hw->bus.func);
3101 		}
3102 		break;
3103 	default:
3104 		/* Shouldn't get here */
3105 		netdev_err(adapter->netdev,
3106 			"MAS: Invalid port configuration, returning\n");
3107 		break;
3108 	}
3109 }
3110 
3111 /**
3112  *  igb_init_i2c - Init I2C interface
3113  *  @adapter: pointer to adapter structure
3114  **/
3115 static s32 igb_init_i2c(struct igb_adapter *adapter)
3116 {
3117 	struct e1000_hw *hw = &adapter->hw;
3118 	s32 status = 0;
3119 	s32 i2cctl;
3120 
3121 	/* I2C interface supported on i350 devices */
3122 	if (adapter->hw.mac.type != e1000_i350)
3123 		return 0;
3124 
3125 	i2cctl = rd32(E1000_I2CPARAMS);
3126 	i2cctl |= E1000_I2CBB_EN
3127 		| E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N
3128 		| E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
3129 	wr32(E1000_I2CPARAMS, i2cctl);
3130 	wrfl();
3131 
3132 	/* Initialize the i2c bus which is controlled by the registers.
3133 	 * This bus will use the i2c_algo_bit structure that implements
3134 	 * the protocol through toggling of the 4 bits in the register.
3135 	 */
3136 	adapter->i2c_adap.owner = THIS_MODULE;
3137 	adapter->i2c_algo = igb_i2c_algo;
3138 	adapter->i2c_algo.data = adapter;
3139 	adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3140 	adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3141 	strlcpy(adapter->i2c_adap.name, "igb BB",
3142 		sizeof(adapter->i2c_adap.name));
3143 	status = i2c_bit_add_bus(&adapter->i2c_adap);
3144 	return status;
3145 }
3146 
3147 /**
3148  *  igb_probe - Device Initialization Routine
3149  *  @pdev: PCI device information struct
3150  *  @ent: entry in igb_pci_tbl
3151  *
3152  *  Returns 0 on success, negative on failure
3153  *
3154  *  igb_probe initializes an adapter identified by a pci_dev structure.
3155  *  The OS initialization, configuring of the adapter private structure,
3156  *  and a hardware reset occur.
3157  **/
3158 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3159 {
3160 	struct net_device *netdev;
3161 	struct igb_adapter *adapter;
3162 	struct e1000_hw *hw;
3163 	u16 eeprom_data = 0;
3164 	s32 ret_val;
3165 	static int global_quad_port_a; /* global quad port a indication */
3166 	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3167 	int err, pci_using_dac;
3168 	u8 part_str[E1000_PBANUM_LENGTH];
3169 
3170 	/* Catch broken hardware that put the wrong VF device ID in
3171 	 * the PCIe SR-IOV capability.
3172 	 */
3173 	if (pdev->is_virtfn) {
3174 		WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3175 			pci_name(pdev), pdev->vendor, pdev->device);
3176 		return -EINVAL;
3177 	}
3178 
3179 	err = pci_enable_device_mem(pdev);
3180 	if (err)
3181 		return err;
3182 
3183 	pci_using_dac = 0;
3184 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3185 	if (!err) {
3186 		pci_using_dac = 1;
3187 	} else {
3188 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3189 		if (err) {
3190 			dev_err(&pdev->dev,
3191 				"No usable DMA configuration, aborting\n");
3192 			goto err_dma;
3193 		}
3194 	}
3195 
3196 	err = pci_request_mem_regions(pdev, igb_driver_name);
3197 	if (err)
3198 		goto err_pci_reg;
3199 
3200 	pci_enable_pcie_error_reporting(pdev);
3201 
3202 	pci_set_master(pdev);
3203 	pci_save_state(pdev);
3204 
3205 	err = -ENOMEM;
3206 	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3207 				   IGB_MAX_TX_QUEUES);
3208 	if (!netdev)
3209 		goto err_alloc_etherdev;
3210 
3211 	SET_NETDEV_DEV(netdev, &pdev->dev);
3212 
3213 	pci_set_drvdata(pdev, netdev);
3214 	adapter = netdev_priv(netdev);
3215 	adapter->netdev = netdev;
3216 	adapter->pdev = pdev;
3217 	hw = &adapter->hw;
3218 	hw->back = adapter;
3219 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3220 
3221 	err = -EIO;
3222 	adapter->io_addr = pci_iomap(pdev, 0, 0);
3223 	if (!adapter->io_addr)
3224 		goto err_ioremap;
3225 	/* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3226 	hw->hw_addr = adapter->io_addr;
3227 
3228 	netdev->netdev_ops = &igb_netdev_ops;
3229 	igb_set_ethtool_ops(netdev);
3230 	netdev->watchdog_timeo = 5 * HZ;
3231 
3232 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3233 
3234 	netdev->mem_start = pci_resource_start(pdev, 0);
3235 	netdev->mem_end = pci_resource_end(pdev, 0);
3236 
3237 	/* PCI config space info */
3238 	hw->vendor_id = pdev->vendor;
3239 	hw->device_id = pdev->device;
3240 	hw->revision_id = pdev->revision;
3241 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
3242 	hw->subsystem_device_id = pdev->subsystem_device;
3243 
3244 	/* Copy the default MAC, PHY and NVM function pointers */
3245 	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3246 	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3247 	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3248 	/* Initialize skew-specific constants */
3249 	err = ei->get_invariants(hw);
3250 	if (err)
3251 		goto err_sw_init;
3252 
3253 	/* setup the private structure */
3254 	err = igb_sw_init(adapter);
3255 	if (err)
3256 		goto err_sw_init;
3257 
3258 	igb_get_bus_info_pcie(hw);
3259 
3260 	hw->phy.autoneg_wait_to_complete = false;
3261 
3262 	/* Copper options */
3263 	if (hw->phy.media_type == e1000_media_type_copper) {
3264 		hw->phy.mdix = AUTO_ALL_MODES;
3265 		hw->phy.disable_polarity_correction = false;
3266 		hw->phy.ms_type = e1000_ms_hw_default;
3267 	}
3268 
3269 	if (igb_check_reset_block(hw))
3270 		dev_info(&pdev->dev,
3271 			"PHY reset is blocked due to SOL/IDER session.\n");
3272 
3273 	/* features is initialized to 0 in allocation, it might have bits
3274 	 * set by igb_sw_init so we should use an or instead of an
3275 	 * assignment.
3276 	 */
3277 	netdev->features |= NETIF_F_SG |
3278 			    NETIF_F_TSO |
3279 			    NETIF_F_TSO6 |
3280 			    NETIF_F_RXHASH |
3281 			    NETIF_F_RXCSUM |
3282 			    NETIF_F_HW_CSUM;
3283 
3284 	if (hw->mac.type >= e1000_82576)
3285 		netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3286 
3287 	if (hw->mac.type >= e1000_i350)
3288 		netdev->features |= NETIF_F_HW_TC;
3289 
3290 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3291 				  NETIF_F_GSO_GRE_CSUM | \
3292 				  NETIF_F_GSO_IPXIP4 | \
3293 				  NETIF_F_GSO_IPXIP6 | \
3294 				  NETIF_F_GSO_UDP_TUNNEL | \
3295 				  NETIF_F_GSO_UDP_TUNNEL_CSUM)
3296 
3297 	netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3298 	netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3299 
3300 	/* copy netdev features into list of user selectable features */
3301 	netdev->hw_features |= netdev->features |
3302 			       NETIF_F_HW_VLAN_CTAG_RX |
3303 			       NETIF_F_HW_VLAN_CTAG_TX |
3304 			       NETIF_F_RXALL;
3305 
3306 	if (hw->mac.type >= e1000_i350)
3307 		netdev->hw_features |= NETIF_F_NTUPLE;
3308 
3309 	if (pci_using_dac)
3310 		netdev->features |= NETIF_F_HIGHDMA;
3311 
3312 	netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3313 	netdev->mpls_features |= NETIF_F_HW_CSUM;
3314 	netdev->hw_enc_features |= netdev->vlan_features;
3315 
3316 	/* set this bit last since it cannot be part of vlan_features */
3317 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3318 			    NETIF_F_HW_VLAN_CTAG_RX |
3319 			    NETIF_F_HW_VLAN_CTAG_TX;
3320 
3321 	netdev->priv_flags |= IFF_SUPP_NOFCS;
3322 
3323 	netdev->priv_flags |= IFF_UNICAST_FLT;
3324 
3325 	/* MTU range: 68 - 9216 */
3326 	netdev->min_mtu = ETH_MIN_MTU;
3327 	netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3328 
3329 	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3330 
3331 	/* before reading the NVM, reset the controller to put the device in a
3332 	 * known good starting state
3333 	 */
3334 	hw->mac.ops.reset_hw(hw);
3335 
3336 	/* make sure the NVM is good , i211/i210 parts can have special NVM
3337 	 * that doesn't contain a checksum
3338 	 */
3339 	switch (hw->mac.type) {
3340 	case e1000_i210:
3341 	case e1000_i211:
3342 		if (igb_get_flash_presence_i210(hw)) {
3343 			if (hw->nvm.ops.validate(hw) < 0) {
3344 				dev_err(&pdev->dev,
3345 					"The NVM Checksum Is Not Valid\n");
3346 				err = -EIO;
3347 				goto err_eeprom;
3348 			}
3349 		}
3350 		break;
3351 	default:
3352 		if (hw->nvm.ops.validate(hw) < 0) {
3353 			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3354 			err = -EIO;
3355 			goto err_eeprom;
3356 		}
3357 		break;
3358 	}
3359 
3360 	if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3361 		/* copy the MAC address out of the NVM */
3362 		if (hw->mac.ops.read_mac_addr(hw))
3363 			dev_err(&pdev->dev, "NVM Read Error\n");
3364 	}
3365 
3366 	eth_hw_addr_set(netdev, hw->mac.addr);
3367 
3368 	if (!is_valid_ether_addr(netdev->dev_addr)) {
3369 		dev_err(&pdev->dev, "Invalid MAC Address\n");
3370 		err = -EIO;
3371 		goto err_eeprom;
3372 	}
3373 
3374 	igb_set_default_mac_filter(adapter);
3375 
3376 	/* get firmware version for ethtool -i */
3377 	igb_set_fw_version(adapter);
3378 
3379 	/* configure RXPBSIZE and TXPBSIZE */
3380 	if (hw->mac.type == e1000_i210) {
3381 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3382 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3383 	}
3384 
3385 	timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3386 	timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3387 
3388 	INIT_WORK(&adapter->reset_task, igb_reset_task);
3389 	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3390 
3391 	/* Initialize link properties that are user-changeable */
3392 	adapter->fc_autoneg = true;
3393 	hw->mac.autoneg = true;
3394 	hw->phy.autoneg_advertised = 0x2f;
3395 
3396 	hw->fc.requested_mode = e1000_fc_default;
3397 	hw->fc.current_mode = e1000_fc_default;
3398 
3399 	igb_validate_mdi_setting(hw);
3400 
3401 	/* By default, support wake on port A */
3402 	if (hw->bus.func == 0)
3403 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3404 
3405 	/* Check the NVM for wake support on non-port A ports */
3406 	if (hw->mac.type >= e1000_82580)
3407 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3408 				 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3409 				 &eeprom_data);
3410 	else if (hw->bus.func == 1)
3411 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3412 
3413 	if (eeprom_data & IGB_EEPROM_APME)
3414 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3415 
3416 	/* now that we have the eeprom settings, apply the special cases where
3417 	 * the eeprom may be wrong or the board simply won't support wake on
3418 	 * lan on a particular port
3419 	 */
3420 	switch (pdev->device) {
3421 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
3422 		adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3423 		break;
3424 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
3425 	case E1000_DEV_ID_82576_FIBER:
3426 	case E1000_DEV_ID_82576_SERDES:
3427 		/* Wake events only supported on port A for dual fiber
3428 		 * regardless of eeprom setting
3429 		 */
3430 		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3431 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3432 		break;
3433 	case E1000_DEV_ID_82576_QUAD_COPPER:
3434 	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3435 		/* if quad port adapter, disable WoL on all but port A */
3436 		if (global_quad_port_a != 0)
3437 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3438 		else
3439 			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3440 		/* Reset for multiple quad port adapters */
3441 		if (++global_quad_port_a == 4)
3442 			global_quad_port_a = 0;
3443 		break;
3444 	default:
3445 		/* If the device can't wake, don't set software support */
3446 		if (!device_can_wakeup(&adapter->pdev->dev))
3447 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3448 	}
3449 
3450 	/* initialize the wol settings based on the eeprom settings */
3451 	if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3452 		adapter->wol |= E1000_WUFC_MAG;
3453 
3454 	/* Some vendors want WoL disabled by default, but still supported */
3455 	if ((hw->mac.type == e1000_i350) &&
3456 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3457 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3458 		adapter->wol = 0;
3459 	}
3460 
3461 	/* Some vendors want the ability to Use the EEPROM setting as
3462 	 * enable/disable only, and not for capability
3463 	 */
3464 	if (((hw->mac.type == e1000_i350) ||
3465 	     (hw->mac.type == e1000_i354)) &&
3466 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3467 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3468 		adapter->wol = 0;
3469 	}
3470 	if (hw->mac.type == e1000_i350) {
3471 		if (((pdev->subsystem_device == 0x5001) ||
3472 		     (pdev->subsystem_device == 0x5002)) &&
3473 				(hw->bus.func == 0)) {
3474 			adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3475 			adapter->wol = 0;
3476 		}
3477 		if (pdev->subsystem_device == 0x1F52)
3478 			adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3479 	}
3480 
3481 	device_set_wakeup_enable(&adapter->pdev->dev,
3482 				 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3483 
3484 	/* reset the hardware with the new settings */
3485 	igb_reset(adapter);
3486 
3487 	/* Init the I2C interface */
3488 	err = igb_init_i2c(adapter);
3489 	if (err) {
3490 		dev_err(&pdev->dev, "failed to init i2c interface\n");
3491 		goto err_eeprom;
3492 	}
3493 
3494 	/* let the f/w know that the h/w is now under the control of the
3495 	 * driver.
3496 	 */
3497 	igb_get_hw_control(adapter);
3498 
3499 	strcpy(netdev->name, "eth%d");
3500 	err = register_netdev(netdev);
3501 	if (err)
3502 		goto err_register;
3503 
3504 	/* carrier off reporting is important to ethtool even BEFORE open */
3505 	netif_carrier_off(netdev);
3506 
3507 #ifdef CONFIG_IGB_DCA
3508 	if (dca_add_requester(&pdev->dev) == 0) {
3509 		adapter->flags |= IGB_FLAG_DCA_ENABLED;
3510 		dev_info(&pdev->dev, "DCA enabled\n");
3511 		igb_setup_dca(adapter);
3512 	}
3513 
3514 #endif
3515 #ifdef CONFIG_IGB_HWMON
3516 	/* Initialize the thermal sensor on i350 devices. */
3517 	if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3518 		u16 ets_word;
3519 
3520 		/* Read the NVM to determine if this i350 device supports an
3521 		 * external thermal sensor.
3522 		 */
3523 		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3524 		if (ets_word != 0x0000 && ets_word != 0xFFFF)
3525 			adapter->ets = true;
3526 		else
3527 			adapter->ets = false;
3528 		if (igb_sysfs_init(adapter))
3529 			dev_err(&pdev->dev,
3530 				"failed to allocate sysfs resources\n");
3531 	} else {
3532 		adapter->ets = false;
3533 	}
3534 #endif
3535 	/* Check if Media Autosense is enabled */
3536 	adapter->ei = *ei;
3537 	if (hw->dev_spec._82575.mas_capable)
3538 		igb_init_mas(adapter);
3539 
3540 	/* do hw tstamp init after resetting */
3541 	igb_ptp_init(adapter);
3542 
3543 	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3544 	/* print bus type/speed/width info, not applicable to i354 */
3545 	if (hw->mac.type != e1000_i354) {
3546 		dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3547 			 netdev->name,
3548 			 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3549 			  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3550 			   "unknown"),
3551 			 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3552 			  "Width x4" :
3553 			  (hw->bus.width == e1000_bus_width_pcie_x2) ?
3554 			  "Width x2" :
3555 			  (hw->bus.width == e1000_bus_width_pcie_x1) ?
3556 			  "Width x1" : "unknown"), netdev->dev_addr);
3557 	}
3558 
3559 	if ((hw->mac.type == e1000_82576 &&
3560 	     rd32(E1000_EECD) & E1000_EECD_PRES) ||
3561 	    (hw->mac.type >= e1000_i210 ||
3562 	     igb_get_flash_presence_i210(hw))) {
3563 		ret_val = igb_read_part_string(hw, part_str,
3564 					       E1000_PBANUM_LENGTH);
3565 	} else {
3566 		ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3567 	}
3568 
3569 	if (ret_val)
3570 		strcpy(part_str, "Unknown");
3571 	dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3572 	dev_info(&pdev->dev,
3573 		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3574 		(adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3575 		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3576 		adapter->num_rx_queues, adapter->num_tx_queues);
3577 	if (hw->phy.media_type == e1000_media_type_copper) {
3578 		switch (hw->mac.type) {
3579 		case e1000_i350:
3580 		case e1000_i210:
3581 		case e1000_i211:
3582 			/* Enable EEE for internal copper PHY devices */
3583 			err = igb_set_eee_i350(hw, true, true);
3584 			if ((!err) &&
3585 			    (!hw->dev_spec._82575.eee_disable)) {
3586 				adapter->eee_advert =
3587 					MDIO_EEE_100TX | MDIO_EEE_1000T;
3588 				adapter->flags |= IGB_FLAG_EEE;
3589 			}
3590 			break;
3591 		case e1000_i354:
3592 			if ((rd32(E1000_CTRL_EXT) &
3593 			    E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3594 				err = igb_set_eee_i354(hw, true, true);
3595 				if ((!err) &&
3596 					(!hw->dev_spec._82575.eee_disable)) {
3597 					adapter->eee_advert =
3598 					   MDIO_EEE_100TX | MDIO_EEE_1000T;
3599 					adapter->flags |= IGB_FLAG_EEE;
3600 				}
3601 			}
3602 			break;
3603 		default:
3604 			break;
3605 		}
3606 	}
3607 
3608 	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3609 
3610 	pm_runtime_put_noidle(&pdev->dev);
3611 	return 0;
3612 
3613 err_register:
3614 	igb_release_hw_control(adapter);
3615 	memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3616 err_eeprom:
3617 	if (!igb_check_reset_block(hw))
3618 		igb_reset_phy(hw);
3619 
3620 	if (hw->flash_address)
3621 		iounmap(hw->flash_address);
3622 err_sw_init:
3623 	kfree(adapter->mac_table);
3624 	kfree(adapter->shadow_vfta);
3625 	igb_clear_interrupt_scheme(adapter);
3626 #ifdef CONFIG_PCI_IOV
3627 	igb_disable_sriov(pdev);
3628 #endif
3629 	pci_iounmap(pdev, adapter->io_addr);
3630 err_ioremap:
3631 	free_netdev(netdev);
3632 err_alloc_etherdev:
3633 	pci_disable_pcie_error_reporting(pdev);
3634 	pci_release_mem_regions(pdev);
3635 err_pci_reg:
3636 err_dma:
3637 	pci_disable_device(pdev);
3638 	return err;
3639 }
3640 
3641 #ifdef CONFIG_PCI_IOV
3642 static int igb_disable_sriov(struct pci_dev *pdev)
3643 {
3644 	struct net_device *netdev = pci_get_drvdata(pdev);
3645 	struct igb_adapter *adapter = netdev_priv(netdev);
3646 	struct e1000_hw *hw = &adapter->hw;
3647 
3648 	/* reclaim resources allocated to VFs */
3649 	if (adapter->vf_data) {
3650 		/* disable iov and allow time for transactions to clear */
3651 		if (pci_vfs_assigned(pdev)) {
3652 			dev_warn(&pdev->dev,
3653 				 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3654 			return -EPERM;
3655 		} else {
3656 			pci_disable_sriov(pdev);
3657 			msleep(500);
3658 		}
3659 
3660 		kfree(adapter->vf_mac_list);
3661 		adapter->vf_mac_list = NULL;
3662 		kfree(adapter->vf_data);
3663 		adapter->vf_data = NULL;
3664 		adapter->vfs_allocated_count = 0;
3665 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3666 		wrfl();
3667 		msleep(100);
3668 		dev_info(&pdev->dev, "IOV Disabled\n");
3669 
3670 		/* Re-enable DMA Coalescing flag since IOV is turned off */
3671 		adapter->flags |= IGB_FLAG_DMAC;
3672 	}
3673 
3674 	return 0;
3675 }
3676 
3677 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3678 {
3679 	struct net_device *netdev = pci_get_drvdata(pdev);
3680 	struct igb_adapter *adapter = netdev_priv(netdev);
3681 	int old_vfs = pci_num_vf(pdev);
3682 	struct vf_mac_filter *mac_list;
3683 	int err = 0;
3684 	int num_vf_mac_filters, i;
3685 
3686 	if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3687 		err = -EPERM;
3688 		goto out;
3689 	}
3690 	if (!num_vfs)
3691 		goto out;
3692 
3693 	if (old_vfs) {
3694 		dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3695 			 old_vfs, max_vfs);
3696 		adapter->vfs_allocated_count = old_vfs;
3697 	} else
3698 		adapter->vfs_allocated_count = num_vfs;
3699 
3700 	adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3701 				sizeof(struct vf_data_storage), GFP_KERNEL);
3702 
3703 	/* if allocation failed then we do not support SR-IOV */
3704 	if (!adapter->vf_data) {
3705 		adapter->vfs_allocated_count = 0;
3706 		err = -ENOMEM;
3707 		goto out;
3708 	}
3709 
3710 	/* Due to the limited number of RAR entries calculate potential
3711 	 * number of MAC filters available for the VFs. Reserve entries
3712 	 * for PF default MAC, PF MAC filters and at least one RAR entry
3713 	 * for each VF for VF MAC.
3714 	 */
3715 	num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3716 			     (1 + IGB_PF_MAC_FILTERS_RESERVED +
3717 			      adapter->vfs_allocated_count);
3718 
3719 	adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3720 				       sizeof(struct vf_mac_filter),
3721 				       GFP_KERNEL);
3722 
3723 	mac_list = adapter->vf_mac_list;
3724 	INIT_LIST_HEAD(&adapter->vf_macs.l);
3725 
3726 	if (adapter->vf_mac_list) {
3727 		/* Initialize list of VF MAC filters */
3728 		for (i = 0; i < num_vf_mac_filters; i++) {
3729 			mac_list->vf = -1;
3730 			mac_list->free = true;
3731 			list_add(&mac_list->l, &adapter->vf_macs.l);
3732 			mac_list++;
3733 		}
3734 	} else {
3735 		/* If we could not allocate memory for the VF MAC filters
3736 		 * we can continue without this feature but warn user.
3737 		 */
3738 		dev_err(&pdev->dev,
3739 			"Unable to allocate memory for VF MAC filter list\n");
3740 	}
3741 
3742 	/* only call pci_enable_sriov() if no VFs are allocated already */
3743 	if (!old_vfs) {
3744 		err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3745 		if (err)
3746 			goto err_out;
3747 	}
3748 	dev_info(&pdev->dev, "%d VFs allocated\n",
3749 		 adapter->vfs_allocated_count);
3750 	for (i = 0; i < adapter->vfs_allocated_count; i++)
3751 		igb_vf_configure(adapter, i);
3752 
3753 	/* DMA Coalescing is not supported in IOV mode. */
3754 	adapter->flags &= ~IGB_FLAG_DMAC;
3755 	goto out;
3756 
3757 err_out:
3758 	kfree(adapter->vf_mac_list);
3759 	adapter->vf_mac_list = NULL;
3760 	kfree(adapter->vf_data);
3761 	adapter->vf_data = NULL;
3762 	adapter->vfs_allocated_count = 0;
3763 out:
3764 	return err;
3765 }
3766 
3767 #endif
3768 /**
3769  *  igb_remove_i2c - Cleanup  I2C interface
3770  *  @adapter: pointer to adapter structure
3771  **/
3772 static void igb_remove_i2c(struct igb_adapter *adapter)
3773 {
3774 	/* free the adapter bus structure */
3775 	i2c_del_adapter(&adapter->i2c_adap);
3776 }
3777 
3778 /**
3779  *  igb_remove - Device Removal Routine
3780  *  @pdev: PCI device information struct
3781  *
3782  *  igb_remove is called by the PCI subsystem to alert the driver
3783  *  that it should release a PCI device.  The could be caused by a
3784  *  Hot-Plug event, or because the driver is going to be removed from
3785  *  memory.
3786  **/
3787 static void igb_remove(struct pci_dev *pdev)
3788 {
3789 	struct net_device *netdev = pci_get_drvdata(pdev);
3790 	struct igb_adapter *adapter = netdev_priv(netdev);
3791 	struct e1000_hw *hw = &adapter->hw;
3792 
3793 	pm_runtime_get_noresume(&pdev->dev);
3794 #ifdef CONFIG_IGB_HWMON
3795 	igb_sysfs_exit(adapter);
3796 #endif
3797 	igb_remove_i2c(adapter);
3798 	igb_ptp_stop(adapter);
3799 	/* The watchdog timer may be rescheduled, so explicitly
3800 	 * disable watchdog from being rescheduled.
3801 	 */
3802 	set_bit(__IGB_DOWN, &adapter->state);
3803 	del_timer_sync(&adapter->watchdog_timer);
3804 	del_timer_sync(&adapter->phy_info_timer);
3805 
3806 	cancel_work_sync(&adapter->reset_task);
3807 	cancel_work_sync(&adapter->watchdog_task);
3808 
3809 #ifdef CONFIG_IGB_DCA
3810 	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3811 		dev_info(&pdev->dev, "DCA disabled\n");
3812 		dca_remove_requester(&pdev->dev);
3813 		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3814 		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3815 	}
3816 #endif
3817 
3818 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
3819 	 * would have already happened in close and is redundant.
3820 	 */
3821 	igb_release_hw_control(adapter);
3822 
3823 #ifdef CONFIG_PCI_IOV
3824 	igb_disable_sriov(pdev);
3825 #endif
3826 
3827 	unregister_netdev(netdev);
3828 
3829 	igb_clear_interrupt_scheme(adapter);
3830 
3831 	pci_iounmap(pdev, adapter->io_addr);
3832 	if (hw->flash_address)
3833 		iounmap(hw->flash_address);
3834 	pci_release_mem_regions(pdev);
3835 
3836 	kfree(adapter->mac_table);
3837 	kfree(adapter->shadow_vfta);
3838 	free_netdev(netdev);
3839 
3840 	pci_disable_pcie_error_reporting(pdev);
3841 
3842 	pci_disable_device(pdev);
3843 }
3844 
3845 /**
3846  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3847  *  @adapter: board private structure to initialize
3848  *
3849  *  This function initializes the vf specific data storage and then attempts to
3850  *  allocate the VFs.  The reason for ordering it this way is because it is much
3851  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
3852  *  the memory for the VFs.
3853  **/
3854 static void igb_probe_vfs(struct igb_adapter *adapter)
3855 {
3856 #ifdef CONFIG_PCI_IOV
3857 	struct pci_dev *pdev = adapter->pdev;
3858 	struct e1000_hw *hw = &adapter->hw;
3859 
3860 	/* Virtualization features not supported on i210 family. */
3861 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3862 		return;
3863 
3864 	/* Of the below we really only want the effect of getting
3865 	 * IGB_FLAG_HAS_MSIX set (if available), without which
3866 	 * igb_enable_sriov() has no effect.
3867 	 */
3868 	igb_set_interrupt_capability(adapter, true);
3869 	igb_reset_interrupt_capability(adapter);
3870 
3871 	pci_sriov_set_totalvfs(pdev, 7);
3872 	igb_enable_sriov(pdev, max_vfs);
3873 
3874 #endif /* CONFIG_PCI_IOV */
3875 }
3876 
3877 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3878 {
3879 	struct e1000_hw *hw = &adapter->hw;
3880 	unsigned int max_rss_queues;
3881 
3882 	/* Determine the maximum number of RSS queues supported. */
3883 	switch (hw->mac.type) {
3884 	case e1000_i211:
3885 		max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3886 		break;
3887 	case e1000_82575:
3888 	case e1000_i210:
3889 		max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3890 		break;
3891 	case e1000_i350:
3892 		/* I350 cannot do RSS and SR-IOV at the same time */
3893 		if (!!adapter->vfs_allocated_count) {
3894 			max_rss_queues = 1;
3895 			break;
3896 		}
3897 		fallthrough;
3898 	case e1000_82576:
3899 		if (!!adapter->vfs_allocated_count) {
3900 			max_rss_queues = 2;
3901 			break;
3902 		}
3903 		fallthrough;
3904 	case e1000_82580:
3905 	case e1000_i354:
3906 	default:
3907 		max_rss_queues = IGB_MAX_RX_QUEUES;
3908 		break;
3909 	}
3910 
3911 	return max_rss_queues;
3912 }
3913 
3914 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3915 {
3916 	u32 max_rss_queues;
3917 
3918 	max_rss_queues = igb_get_max_rss_queues(adapter);
3919 	adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3920 
3921 	igb_set_flag_queue_pairs(adapter, max_rss_queues);
3922 }
3923 
3924 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3925 			      const u32 max_rss_queues)
3926 {
3927 	struct e1000_hw *hw = &adapter->hw;
3928 
3929 	/* Determine if we need to pair queues. */
3930 	switch (hw->mac.type) {
3931 	case e1000_82575:
3932 	case e1000_i211:
3933 		/* Device supports enough interrupts without queue pairing. */
3934 		break;
3935 	case e1000_82576:
3936 	case e1000_82580:
3937 	case e1000_i350:
3938 	case e1000_i354:
3939 	case e1000_i210:
3940 	default:
3941 		/* If rss_queues > half of max_rss_queues, pair the queues in
3942 		 * order to conserve interrupts due to limited supply.
3943 		 */
3944 		if (adapter->rss_queues > (max_rss_queues / 2))
3945 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3946 		else
3947 			adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3948 		break;
3949 	}
3950 }
3951 
3952 /**
3953  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
3954  *  @adapter: board private structure to initialize
3955  *
3956  *  igb_sw_init initializes the Adapter private data structure.
3957  *  Fields are initialized based on PCI device information and
3958  *  OS network device settings (MTU size).
3959  **/
3960 static int igb_sw_init(struct igb_adapter *adapter)
3961 {
3962 	struct e1000_hw *hw = &adapter->hw;
3963 	struct net_device *netdev = adapter->netdev;
3964 	struct pci_dev *pdev = adapter->pdev;
3965 
3966 	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3967 
3968 	/* set default ring sizes */
3969 	adapter->tx_ring_count = IGB_DEFAULT_TXD;
3970 	adapter->rx_ring_count = IGB_DEFAULT_RXD;
3971 
3972 	/* set default ITR values */
3973 	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3974 	adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3975 
3976 	/* set default work limits */
3977 	adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3978 
3979 	adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
3980 	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3981 
3982 	spin_lock_init(&adapter->nfc_lock);
3983 	spin_lock_init(&adapter->stats64_lock);
3984 #ifdef CONFIG_PCI_IOV
3985 	switch (hw->mac.type) {
3986 	case e1000_82576:
3987 	case e1000_i350:
3988 		if (max_vfs > 7) {
3989 			dev_warn(&pdev->dev,
3990 				 "Maximum of 7 VFs per PF, using max\n");
3991 			max_vfs = adapter->vfs_allocated_count = 7;
3992 		} else
3993 			adapter->vfs_allocated_count = max_vfs;
3994 		if (adapter->vfs_allocated_count)
3995 			dev_warn(&pdev->dev,
3996 				 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3997 		break;
3998 	default:
3999 		break;
4000 	}
4001 #endif /* CONFIG_PCI_IOV */
4002 
4003 	/* Assume MSI-X interrupts, will be checked during IRQ allocation */
4004 	adapter->flags |= IGB_FLAG_HAS_MSIX;
4005 
4006 	adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4007 				     sizeof(struct igb_mac_addr),
4008 				     GFP_KERNEL);
4009 	if (!adapter->mac_table)
4010 		return -ENOMEM;
4011 
4012 	igb_probe_vfs(adapter);
4013 
4014 	igb_init_queue_configuration(adapter);
4015 
4016 	/* Setup and initialize a copy of the hw vlan table array */
4017 	adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4018 				       GFP_KERNEL);
4019 	if (!adapter->shadow_vfta)
4020 		return -ENOMEM;
4021 
4022 	/* This call may decrease the number of queues */
4023 	if (igb_init_interrupt_scheme(adapter, true)) {
4024 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4025 		return -ENOMEM;
4026 	}
4027 
4028 	/* Explicitly disable IRQ since the NIC can be in any state. */
4029 	igb_irq_disable(adapter);
4030 
4031 	if (hw->mac.type >= e1000_i350)
4032 		adapter->flags &= ~IGB_FLAG_DMAC;
4033 
4034 	set_bit(__IGB_DOWN, &adapter->state);
4035 	return 0;
4036 }
4037 
4038 /**
4039  *  __igb_open - Called when a network interface is made active
4040  *  @netdev: network interface device structure
4041  *  @resuming: indicates whether we are in a resume call
4042  *
4043  *  Returns 0 on success, negative value on failure
4044  *
4045  *  The open entry point is called when a network interface is made
4046  *  active by the system (IFF_UP).  At this point all resources needed
4047  *  for transmit and receive operations are allocated, the interrupt
4048  *  handler is registered with the OS, the watchdog timer is started,
4049  *  and the stack is notified that the interface is ready.
4050  **/
4051 static int __igb_open(struct net_device *netdev, bool resuming)
4052 {
4053 	struct igb_adapter *adapter = netdev_priv(netdev);
4054 	struct e1000_hw *hw = &adapter->hw;
4055 	struct pci_dev *pdev = adapter->pdev;
4056 	int err;
4057 	int i;
4058 
4059 	/* disallow open during test */
4060 	if (test_bit(__IGB_TESTING, &adapter->state)) {
4061 		WARN_ON(resuming);
4062 		return -EBUSY;
4063 	}
4064 
4065 	if (!resuming)
4066 		pm_runtime_get_sync(&pdev->dev);
4067 
4068 	netif_carrier_off(netdev);
4069 
4070 	/* allocate transmit descriptors */
4071 	err = igb_setup_all_tx_resources(adapter);
4072 	if (err)
4073 		goto err_setup_tx;
4074 
4075 	/* allocate receive descriptors */
4076 	err = igb_setup_all_rx_resources(adapter);
4077 	if (err)
4078 		goto err_setup_rx;
4079 
4080 	igb_power_up_link(adapter);
4081 
4082 	/* before we allocate an interrupt, we must be ready to handle it.
4083 	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4084 	 * as soon as we call pci_request_irq, so we have to setup our
4085 	 * clean_rx handler before we do so.
4086 	 */
4087 	igb_configure(adapter);
4088 
4089 	err = igb_request_irq(adapter);
4090 	if (err)
4091 		goto err_req_irq;
4092 
4093 	/* Notify the stack of the actual queue counts. */
4094 	err = netif_set_real_num_tx_queues(adapter->netdev,
4095 					   adapter->num_tx_queues);
4096 	if (err)
4097 		goto err_set_queues;
4098 
4099 	err = netif_set_real_num_rx_queues(adapter->netdev,
4100 					   adapter->num_rx_queues);
4101 	if (err)
4102 		goto err_set_queues;
4103 
4104 	/* From here on the code is the same as igb_up() */
4105 	clear_bit(__IGB_DOWN, &adapter->state);
4106 
4107 	for (i = 0; i < adapter->num_q_vectors; i++)
4108 		napi_enable(&(adapter->q_vector[i]->napi));
4109 
4110 	/* Clear any pending interrupts. */
4111 	rd32(E1000_TSICR);
4112 	rd32(E1000_ICR);
4113 
4114 	igb_irq_enable(adapter);
4115 
4116 	/* notify VFs that reset has been completed */
4117 	if (adapter->vfs_allocated_count) {
4118 		u32 reg_data = rd32(E1000_CTRL_EXT);
4119 
4120 		reg_data |= E1000_CTRL_EXT_PFRSTD;
4121 		wr32(E1000_CTRL_EXT, reg_data);
4122 	}
4123 
4124 	netif_tx_start_all_queues(netdev);
4125 
4126 	if (!resuming)
4127 		pm_runtime_put(&pdev->dev);
4128 
4129 	/* start the watchdog. */
4130 	hw->mac.get_link_status = 1;
4131 	schedule_work(&adapter->watchdog_task);
4132 
4133 	return 0;
4134 
4135 err_set_queues:
4136 	igb_free_irq(adapter);
4137 err_req_irq:
4138 	igb_release_hw_control(adapter);
4139 	igb_power_down_link(adapter);
4140 	igb_free_all_rx_resources(adapter);
4141 err_setup_rx:
4142 	igb_free_all_tx_resources(adapter);
4143 err_setup_tx:
4144 	igb_reset(adapter);
4145 	if (!resuming)
4146 		pm_runtime_put(&pdev->dev);
4147 
4148 	return err;
4149 }
4150 
4151 int igb_open(struct net_device *netdev)
4152 {
4153 	return __igb_open(netdev, false);
4154 }
4155 
4156 /**
4157  *  __igb_close - Disables a network interface
4158  *  @netdev: network interface device structure
4159  *  @suspending: indicates we are in a suspend call
4160  *
4161  *  Returns 0, this is not allowed to fail
4162  *
4163  *  The close entry point is called when an interface is de-activated
4164  *  by the OS.  The hardware is still under the driver's control, but
4165  *  needs to be disabled.  A global MAC reset is issued to stop the
4166  *  hardware, and all transmit and receive resources are freed.
4167  **/
4168 static int __igb_close(struct net_device *netdev, bool suspending)
4169 {
4170 	struct igb_adapter *adapter = netdev_priv(netdev);
4171 	struct pci_dev *pdev = adapter->pdev;
4172 
4173 	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4174 
4175 	if (!suspending)
4176 		pm_runtime_get_sync(&pdev->dev);
4177 
4178 	igb_down(adapter);
4179 	igb_free_irq(adapter);
4180 
4181 	igb_free_all_tx_resources(adapter);
4182 	igb_free_all_rx_resources(adapter);
4183 
4184 	if (!suspending)
4185 		pm_runtime_put_sync(&pdev->dev);
4186 	return 0;
4187 }
4188 
4189 int igb_close(struct net_device *netdev)
4190 {
4191 	if (netif_device_present(netdev) || netdev->dismantle)
4192 		return __igb_close(netdev, false);
4193 	return 0;
4194 }
4195 
4196 /**
4197  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
4198  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
4199  *
4200  *  Return 0 on success, negative on failure
4201  **/
4202 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4203 {
4204 	struct device *dev = tx_ring->dev;
4205 	int size;
4206 
4207 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4208 
4209 	tx_ring->tx_buffer_info = vmalloc(size);
4210 	if (!tx_ring->tx_buffer_info)
4211 		goto err;
4212 
4213 	/* round up to nearest 4K */
4214 	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4215 	tx_ring->size = ALIGN(tx_ring->size, 4096);
4216 
4217 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4218 					   &tx_ring->dma, GFP_KERNEL);
4219 	if (!tx_ring->desc)
4220 		goto err;
4221 
4222 	tx_ring->next_to_use = 0;
4223 	tx_ring->next_to_clean = 0;
4224 
4225 	return 0;
4226 
4227 err:
4228 	vfree(tx_ring->tx_buffer_info);
4229 	tx_ring->tx_buffer_info = NULL;
4230 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4231 	return -ENOMEM;
4232 }
4233 
4234 /**
4235  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
4236  *				 (Descriptors) for all queues
4237  *  @adapter: board private structure
4238  *
4239  *  Return 0 on success, negative on failure
4240  **/
4241 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4242 {
4243 	struct pci_dev *pdev = adapter->pdev;
4244 	int i, err = 0;
4245 
4246 	for (i = 0; i < adapter->num_tx_queues; i++) {
4247 		err = igb_setup_tx_resources(adapter->tx_ring[i]);
4248 		if (err) {
4249 			dev_err(&pdev->dev,
4250 				"Allocation for Tx Queue %u failed\n", i);
4251 			for (i--; i >= 0; i--)
4252 				igb_free_tx_resources(adapter->tx_ring[i]);
4253 			break;
4254 		}
4255 	}
4256 
4257 	return err;
4258 }
4259 
4260 /**
4261  *  igb_setup_tctl - configure the transmit control registers
4262  *  @adapter: Board private structure
4263  **/
4264 void igb_setup_tctl(struct igb_adapter *adapter)
4265 {
4266 	struct e1000_hw *hw = &adapter->hw;
4267 	u32 tctl;
4268 
4269 	/* disable queue 0 which is enabled by default on 82575 and 82576 */
4270 	wr32(E1000_TXDCTL(0), 0);
4271 
4272 	/* Program the Transmit Control Register */
4273 	tctl = rd32(E1000_TCTL);
4274 	tctl &= ~E1000_TCTL_CT;
4275 	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4276 		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4277 
4278 	igb_config_collision_dist(hw);
4279 
4280 	/* Enable transmits */
4281 	tctl |= E1000_TCTL_EN;
4282 
4283 	wr32(E1000_TCTL, tctl);
4284 }
4285 
4286 /**
4287  *  igb_configure_tx_ring - Configure transmit ring after Reset
4288  *  @adapter: board private structure
4289  *  @ring: tx ring to configure
4290  *
4291  *  Configure a transmit ring after a reset.
4292  **/
4293 void igb_configure_tx_ring(struct igb_adapter *adapter,
4294 			   struct igb_ring *ring)
4295 {
4296 	struct e1000_hw *hw = &adapter->hw;
4297 	u32 txdctl = 0;
4298 	u64 tdba = ring->dma;
4299 	int reg_idx = ring->reg_idx;
4300 
4301 	wr32(E1000_TDLEN(reg_idx),
4302 	     ring->count * sizeof(union e1000_adv_tx_desc));
4303 	wr32(E1000_TDBAL(reg_idx),
4304 	     tdba & 0x00000000ffffffffULL);
4305 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4306 
4307 	ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4308 	wr32(E1000_TDH(reg_idx), 0);
4309 	writel(0, ring->tail);
4310 
4311 	txdctl |= IGB_TX_PTHRESH;
4312 	txdctl |= IGB_TX_HTHRESH << 8;
4313 	txdctl |= IGB_TX_WTHRESH << 16;
4314 
4315 	/* reinitialize tx_buffer_info */
4316 	memset(ring->tx_buffer_info, 0,
4317 	       sizeof(struct igb_tx_buffer) * ring->count);
4318 
4319 	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4320 	wr32(E1000_TXDCTL(reg_idx), txdctl);
4321 }
4322 
4323 /**
4324  *  igb_configure_tx - Configure transmit Unit after Reset
4325  *  @adapter: board private structure
4326  *
4327  *  Configure the Tx unit of the MAC after a reset.
4328  **/
4329 static void igb_configure_tx(struct igb_adapter *adapter)
4330 {
4331 	struct e1000_hw *hw = &adapter->hw;
4332 	int i;
4333 
4334 	/* disable the queues */
4335 	for (i = 0; i < adapter->num_tx_queues; i++)
4336 		wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4337 
4338 	wrfl();
4339 	usleep_range(10000, 20000);
4340 
4341 	for (i = 0; i < adapter->num_tx_queues; i++)
4342 		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4343 }
4344 
4345 /**
4346  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
4347  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
4348  *
4349  *  Returns 0 on success, negative on failure
4350  **/
4351 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4352 {
4353 	struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4354 	struct device *dev = rx_ring->dev;
4355 	int size;
4356 
4357 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4358 
4359 	rx_ring->rx_buffer_info = vmalloc(size);
4360 	if (!rx_ring->rx_buffer_info)
4361 		goto err;
4362 
4363 	/* Round up to nearest 4K */
4364 	rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4365 	rx_ring->size = ALIGN(rx_ring->size, 4096);
4366 
4367 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4368 					   &rx_ring->dma, GFP_KERNEL);
4369 	if (!rx_ring->desc)
4370 		goto err;
4371 
4372 	rx_ring->next_to_alloc = 0;
4373 	rx_ring->next_to_clean = 0;
4374 	rx_ring->next_to_use = 0;
4375 
4376 	rx_ring->xdp_prog = adapter->xdp_prog;
4377 
4378 	/* XDP RX-queue info */
4379 	if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4380 			     rx_ring->queue_index, 0) < 0)
4381 		goto err;
4382 
4383 	return 0;
4384 
4385 err:
4386 	vfree(rx_ring->rx_buffer_info);
4387 	rx_ring->rx_buffer_info = NULL;
4388 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4389 	return -ENOMEM;
4390 }
4391 
4392 /**
4393  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
4394  *				 (Descriptors) for all queues
4395  *  @adapter: board private structure
4396  *
4397  *  Return 0 on success, negative on failure
4398  **/
4399 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4400 {
4401 	struct pci_dev *pdev = adapter->pdev;
4402 	int i, err = 0;
4403 
4404 	for (i = 0; i < adapter->num_rx_queues; i++) {
4405 		err = igb_setup_rx_resources(adapter->rx_ring[i]);
4406 		if (err) {
4407 			dev_err(&pdev->dev,
4408 				"Allocation for Rx Queue %u failed\n", i);
4409 			for (i--; i >= 0; i--)
4410 				igb_free_rx_resources(adapter->rx_ring[i]);
4411 			break;
4412 		}
4413 	}
4414 
4415 	return err;
4416 }
4417 
4418 /**
4419  *  igb_setup_mrqc - configure the multiple receive queue control registers
4420  *  @adapter: Board private structure
4421  **/
4422 static void igb_setup_mrqc(struct igb_adapter *adapter)
4423 {
4424 	struct e1000_hw *hw = &adapter->hw;
4425 	u32 mrqc, rxcsum;
4426 	u32 j, num_rx_queues;
4427 	u32 rss_key[10];
4428 
4429 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
4430 	for (j = 0; j < 10; j++)
4431 		wr32(E1000_RSSRK(j), rss_key[j]);
4432 
4433 	num_rx_queues = adapter->rss_queues;
4434 
4435 	switch (hw->mac.type) {
4436 	case e1000_82576:
4437 		/* 82576 supports 2 RSS queues for SR-IOV */
4438 		if (adapter->vfs_allocated_count)
4439 			num_rx_queues = 2;
4440 		break;
4441 	default:
4442 		break;
4443 	}
4444 
4445 	if (adapter->rss_indir_tbl_init != num_rx_queues) {
4446 		for (j = 0; j < IGB_RETA_SIZE; j++)
4447 			adapter->rss_indir_tbl[j] =
4448 			(j * num_rx_queues) / IGB_RETA_SIZE;
4449 		adapter->rss_indir_tbl_init = num_rx_queues;
4450 	}
4451 	igb_write_rss_indir_tbl(adapter);
4452 
4453 	/* Disable raw packet checksumming so that RSS hash is placed in
4454 	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
4455 	 * offloads as they are enabled by default
4456 	 */
4457 	rxcsum = rd32(E1000_RXCSUM);
4458 	rxcsum |= E1000_RXCSUM_PCSD;
4459 
4460 	if (adapter->hw.mac.type >= e1000_82576)
4461 		/* Enable Receive Checksum Offload for SCTP */
4462 		rxcsum |= E1000_RXCSUM_CRCOFL;
4463 
4464 	/* Don't need to set TUOFL or IPOFL, they default to 1 */
4465 	wr32(E1000_RXCSUM, rxcsum);
4466 
4467 	/* Generate RSS hash based on packet types, TCP/UDP
4468 	 * port numbers and/or IPv4/v6 src and dst addresses
4469 	 */
4470 	mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4471 	       E1000_MRQC_RSS_FIELD_IPV4_TCP |
4472 	       E1000_MRQC_RSS_FIELD_IPV6 |
4473 	       E1000_MRQC_RSS_FIELD_IPV6_TCP |
4474 	       E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4475 
4476 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4477 		mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4478 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4479 		mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4480 
4481 	/* If VMDq is enabled then we set the appropriate mode for that, else
4482 	 * we default to RSS so that an RSS hash is calculated per packet even
4483 	 * if we are only using one queue
4484 	 */
4485 	if (adapter->vfs_allocated_count) {
4486 		if (hw->mac.type > e1000_82575) {
4487 			/* Set the default pool for the PF's first queue */
4488 			u32 vtctl = rd32(E1000_VT_CTL);
4489 
4490 			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4491 				   E1000_VT_CTL_DISABLE_DEF_POOL);
4492 			vtctl |= adapter->vfs_allocated_count <<
4493 				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4494 			wr32(E1000_VT_CTL, vtctl);
4495 		}
4496 		if (adapter->rss_queues > 1)
4497 			mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4498 		else
4499 			mrqc |= E1000_MRQC_ENABLE_VMDQ;
4500 	} else {
4501 		mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4502 	}
4503 	igb_vmm_control(adapter);
4504 
4505 	wr32(E1000_MRQC, mrqc);
4506 }
4507 
4508 /**
4509  *  igb_setup_rctl - configure the receive control registers
4510  *  @adapter: Board private structure
4511  **/
4512 void igb_setup_rctl(struct igb_adapter *adapter)
4513 {
4514 	struct e1000_hw *hw = &adapter->hw;
4515 	u32 rctl;
4516 
4517 	rctl = rd32(E1000_RCTL);
4518 
4519 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4520 	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4521 
4522 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4523 		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4524 
4525 	/* enable stripping of CRC. It's unlikely this will break BMC
4526 	 * redirection as it did with e1000. Newer features require
4527 	 * that the HW strips the CRC.
4528 	 */
4529 	rctl |= E1000_RCTL_SECRC;
4530 
4531 	/* disable store bad packets and clear size bits. */
4532 	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4533 
4534 	/* enable LPE to allow for reception of jumbo frames */
4535 	rctl |= E1000_RCTL_LPE;
4536 
4537 	/* disable queue 0 to prevent tail write w/o re-config */
4538 	wr32(E1000_RXDCTL(0), 0);
4539 
4540 	/* Attention!!!  For SR-IOV PF driver operations you must enable
4541 	 * queue drop for all VF and PF queues to prevent head of line blocking
4542 	 * if an un-trusted VF does not provide descriptors to hardware.
4543 	 */
4544 	if (adapter->vfs_allocated_count) {
4545 		/* set all queue drop enable bits */
4546 		wr32(E1000_QDE, ALL_QUEUES);
4547 	}
4548 
4549 	/* This is useful for sniffing bad packets. */
4550 	if (adapter->netdev->features & NETIF_F_RXALL) {
4551 		/* UPE and MPE will be handled by normal PROMISC logic
4552 		 * in e1000e_set_rx_mode
4553 		 */
4554 		rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4555 			 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4556 			 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4557 
4558 		rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4559 			  E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4560 		/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4561 		 * and that breaks VLANs.
4562 		 */
4563 	}
4564 
4565 	wr32(E1000_RCTL, rctl);
4566 }
4567 
4568 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4569 				   int vfn)
4570 {
4571 	struct e1000_hw *hw = &adapter->hw;
4572 	u32 vmolr;
4573 
4574 	if (size > MAX_JUMBO_FRAME_SIZE)
4575 		size = MAX_JUMBO_FRAME_SIZE;
4576 
4577 	vmolr = rd32(E1000_VMOLR(vfn));
4578 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
4579 	vmolr |= size | E1000_VMOLR_LPE;
4580 	wr32(E1000_VMOLR(vfn), vmolr);
4581 
4582 	return 0;
4583 }
4584 
4585 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4586 					 int vfn, bool enable)
4587 {
4588 	struct e1000_hw *hw = &adapter->hw;
4589 	u32 val, reg;
4590 
4591 	if (hw->mac.type < e1000_82576)
4592 		return;
4593 
4594 	if (hw->mac.type == e1000_i350)
4595 		reg = E1000_DVMOLR(vfn);
4596 	else
4597 		reg = E1000_VMOLR(vfn);
4598 
4599 	val = rd32(reg);
4600 	if (enable)
4601 		val |= E1000_VMOLR_STRVLAN;
4602 	else
4603 		val &= ~(E1000_VMOLR_STRVLAN);
4604 	wr32(reg, val);
4605 }
4606 
4607 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4608 				 int vfn, bool aupe)
4609 {
4610 	struct e1000_hw *hw = &adapter->hw;
4611 	u32 vmolr;
4612 
4613 	/* This register exists only on 82576 and newer so if we are older then
4614 	 * we should exit and do nothing
4615 	 */
4616 	if (hw->mac.type < e1000_82576)
4617 		return;
4618 
4619 	vmolr = rd32(E1000_VMOLR(vfn));
4620 	if (aupe)
4621 		vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4622 	else
4623 		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4624 
4625 	/* clear all bits that might not be set */
4626 	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4627 
4628 	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4629 		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4630 	/* for VMDq only allow the VFs and pool 0 to accept broadcast and
4631 	 * multicast packets
4632 	 */
4633 	if (vfn <= adapter->vfs_allocated_count)
4634 		vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4635 
4636 	wr32(E1000_VMOLR(vfn), vmolr);
4637 }
4638 
4639 /**
4640  *  igb_setup_srrctl - configure the split and replication receive control
4641  *                     registers
4642  *  @adapter: Board private structure
4643  *  @ring: receive ring to be configured
4644  **/
4645 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4646 {
4647 	struct e1000_hw *hw = &adapter->hw;
4648 	int reg_idx = ring->reg_idx;
4649 	u32 srrctl = 0;
4650 
4651 	srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4652 	if (ring_uses_large_buffer(ring))
4653 		srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4654 	else
4655 		srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4656 	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4657 	if (hw->mac.type >= e1000_82580)
4658 		srrctl |= E1000_SRRCTL_TIMESTAMP;
4659 	/* Only set Drop Enable if VFs allocated, or we are supporting multiple
4660 	 * queues and rx flow control is disabled
4661 	 */
4662 	if (adapter->vfs_allocated_count ||
4663 	    (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4664 	     adapter->num_rx_queues > 1))
4665 		srrctl |= E1000_SRRCTL_DROP_EN;
4666 
4667 	wr32(E1000_SRRCTL(reg_idx), srrctl);
4668 }
4669 
4670 /**
4671  *  igb_configure_rx_ring - Configure a receive ring after Reset
4672  *  @adapter: board private structure
4673  *  @ring: receive ring to be configured
4674  *
4675  *  Configure the Rx unit of the MAC after a reset.
4676  **/
4677 void igb_configure_rx_ring(struct igb_adapter *adapter,
4678 			   struct igb_ring *ring)
4679 {
4680 	struct e1000_hw *hw = &adapter->hw;
4681 	union e1000_adv_rx_desc *rx_desc;
4682 	u64 rdba = ring->dma;
4683 	int reg_idx = ring->reg_idx;
4684 	u32 rxdctl = 0;
4685 
4686 	xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4687 	WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4688 					   MEM_TYPE_PAGE_SHARED, NULL));
4689 
4690 	/* disable the queue */
4691 	wr32(E1000_RXDCTL(reg_idx), 0);
4692 
4693 	/* Set DMA base address registers */
4694 	wr32(E1000_RDBAL(reg_idx),
4695 	     rdba & 0x00000000ffffffffULL);
4696 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4697 	wr32(E1000_RDLEN(reg_idx),
4698 	     ring->count * sizeof(union e1000_adv_rx_desc));
4699 
4700 	/* initialize head and tail */
4701 	ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4702 	wr32(E1000_RDH(reg_idx), 0);
4703 	writel(0, ring->tail);
4704 
4705 	/* set descriptor configuration */
4706 	igb_setup_srrctl(adapter, ring);
4707 
4708 	/* set filtering for VMDQ pools */
4709 	igb_set_vmolr(adapter, reg_idx & 0x7, true);
4710 
4711 	rxdctl |= IGB_RX_PTHRESH;
4712 	rxdctl |= IGB_RX_HTHRESH << 8;
4713 	rxdctl |= IGB_RX_WTHRESH << 16;
4714 
4715 	/* initialize rx_buffer_info */
4716 	memset(ring->rx_buffer_info, 0,
4717 	       sizeof(struct igb_rx_buffer) * ring->count);
4718 
4719 	/* initialize Rx descriptor 0 */
4720 	rx_desc = IGB_RX_DESC(ring, 0);
4721 	rx_desc->wb.upper.length = 0;
4722 
4723 	/* enable receive descriptor fetching */
4724 	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4725 	wr32(E1000_RXDCTL(reg_idx), rxdctl);
4726 }
4727 
4728 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4729 				  struct igb_ring *rx_ring)
4730 {
4731 	/* set build_skb and buffer size flags */
4732 	clear_ring_build_skb_enabled(rx_ring);
4733 	clear_ring_uses_large_buffer(rx_ring);
4734 
4735 	if (adapter->flags & IGB_FLAG_RX_LEGACY)
4736 		return;
4737 
4738 	set_ring_build_skb_enabled(rx_ring);
4739 
4740 #if (PAGE_SIZE < 8192)
4741 	if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4742 		return;
4743 
4744 	set_ring_uses_large_buffer(rx_ring);
4745 #endif
4746 }
4747 
4748 /**
4749  *  igb_configure_rx - Configure receive Unit after Reset
4750  *  @adapter: board private structure
4751  *
4752  *  Configure the Rx unit of the MAC after a reset.
4753  **/
4754 static void igb_configure_rx(struct igb_adapter *adapter)
4755 {
4756 	int i;
4757 
4758 	/* set the correct pool for the PF default MAC address in entry 0 */
4759 	igb_set_default_mac_filter(adapter);
4760 
4761 	/* Setup the HW Rx Head and Tail Descriptor Pointers and
4762 	 * the Base and Length of the Rx Descriptor Ring
4763 	 */
4764 	for (i = 0; i < adapter->num_rx_queues; i++) {
4765 		struct igb_ring *rx_ring = adapter->rx_ring[i];
4766 
4767 		igb_set_rx_buffer_len(adapter, rx_ring);
4768 		igb_configure_rx_ring(adapter, rx_ring);
4769 	}
4770 }
4771 
4772 /**
4773  *  igb_free_tx_resources - Free Tx Resources per Queue
4774  *  @tx_ring: Tx descriptor ring for a specific queue
4775  *
4776  *  Free all transmit software resources
4777  **/
4778 void igb_free_tx_resources(struct igb_ring *tx_ring)
4779 {
4780 	igb_clean_tx_ring(tx_ring);
4781 
4782 	vfree(tx_ring->tx_buffer_info);
4783 	tx_ring->tx_buffer_info = NULL;
4784 
4785 	/* if not set, then don't free */
4786 	if (!tx_ring->desc)
4787 		return;
4788 
4789 	dma_free_coherent(tx_ring->dev, tx_ring->size,
4790 			  tx_ring->desc, tx_ring->dma);
4791 
4792 	tx_ring->desc = NULL;
4793 }
4794 
4795 /**
4796  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4797  *  @adapter: board private structure
4798  *
4799  *  Free all transmit software resources
4800  **/
4801 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4802 {
4803 	int i;
4804 
4805 	for (i = 0; i < adapter->num_tx_queues; i++)
4806 		if (adapter->tx_ring[i])
4807 			igb_free_tx_resources(adapter->tx_ring[i]);
4808 }
4809 
4810 /**
4811  *  igb_clean_tx_ring - Free Tx Buffers
4812  *  @tx_ring: ring to be cleaned
4813  **/
4814 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4815 {
4816 	u16 i = tx_ring->next_to_clean;
4817 	struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4818 
4819 	while (i != tx_ring->next_to_use) {
4820 		union e1000_adv_tx_desc *eop_desc, *tx_desc;
4821 
4822 		/* Free all the Tx ring sk_buffs */
4823 		dev_kfree_skb_any(tx_buffer->skb);
4824 
4825 		/* unmap skb header data */
4826 		dma_unmap_single(tx_ring->dev,
4827 				 dma_unmap_addr(tx_buffer, dma),
4828 				 dma_unmap_len(tx_buffer, len),
4829 				 DMA_TO_DEVICE);
4830 
4831 		/* check for eop_desc to determine the end of the packet */
4832 		eop_desc = tx_buffer->next_to_watch;
4833 		tx_desc = IGB_TX_DESC(tx_ring, i);
4834 
4835 		/* unmap remaining buffers */
4836 		while (tx_desc != eop_desc) {
4837 			tx_buffer++;
4838 			tx_desc++;
4839 			i++;
4840 			if (unlikely(i == tx_ring->count)) {
4841 				i = 0;
4842 				tx_buffer = tx_ring->tx_buffer_info;
4843 				tx_desc = IGB_TX_DESC(tx_ring, 0);
4844 			}
4845 
4846 			/* unmap any remaining paged data */
4847 			if (dma_unmap_len(tx_buffer, len))
4848 				dma_unmap_page(tx_ring->dev,
4849 					       dma_unmap_addr(tx_buffer, dma),
4850 					       dma_unmap_len(tx_buffer, len),
4851 					       DMA_TO_DEVICE);
4852 		}
4853 
4854 		tx_buffer->next_to_watch = NULL;
4855 
4856 		/* move us one more past the eop_desc for start of next pkt */
4857 		tx_buffer++;
4858 		i++;
4859 		if (unlikely(i == tx_ring->count)) {
4860 			i = 0;
4861 			tx_buffer = tx_ring->tx_buffer_info;
4862 		}
4863 	}
4864 
4865 	/* reset BQL for queue */
4866 	netdev_tx_reset_queue(txring_txq(tx_ring));
4867 
4868 	/* reset next_to_use and next_to_clean */
4869 	tx_ring->next_to_use = 0;
4870 	tx_ring->next_to_clean = 0;
4871 }
4872 
4873 /**
4874  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4875  *  @adapter: board private structure
4876  **/
4877 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4878 {
4879 	int i;
4880 
4881 	for (i = 0; i < adapter->num_tx_queues; i++)
4882 		if (adapter->tx_ring[i])
4883 			igb_clean_tx_ring(adapter->tx_ring[i]);
4884 }
4885 
4886 /**
4887  *  igb_free_rx_resources - Free Rx Resources
4888  *  @rx_ring: ring to clean the resources from
4889  *
4890  *  Free all receive software resources
4891  **/
4892 void igb_free_rx_resources(struct igb_ring *rx_ring)
4893 {
4894 	igb_clean_rx_ring(rx_ring);
4895 
4896 	rx_ring->xdp_prog = NULL;
4897 	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4898 	vfree(rx_ring->rx_buffer_info);
4899 	rx_ring->rx_buffer_info = NULL;
4900 
4901 	/* if not set, then don't free */
4902 	if (!rx_ring->desc)
4903 		return;
4904 
4905 	dma_free_coherent(rx_ring->dev, rx_ring->size,
4906 			  rx_ring->desc, rx_ring->dma);
4907 
4908 	rx_ring->desc = NULL;
4909 }
4910 
4911 /**
4912  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
4913  *  @adapter: board private structure
4914  *
4915  *  Free all receive software resources
4916  **/
4917 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4918 {
4919 	int i;
4920 
4921 	for (i = 0; i < adapter->num_rx_queues; i++)
4922 		if (adapter->rx_ring[i])
4923 			igb_free_rx_resources(adapter->rx_ring[i]);
4924 }
4925 
4926 /**
4927  *  igb_clean_rx_ring - Free Rx Buffers per Queue
4928  *  @rx_ring: ring to free buffers from
4929  **/
4930 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4931 {
4932 	u16 i = rx_ring->next_to_clean;
4933 
4934 	dev_kfree_skb(rx_ring->skb);
4935 	rx_ring->skb = NULL;
4936 
4937 	/* Free all the Rx ring sk_buffs */
4938 	while (i != rx_ring->next_to_alloc) {
4939 		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4940 
4941 		/* Invalidate cache lines that may have been written to by
4942 		 * device so that we avoid corrupting memory.
4943 		 */
4944 		dma_sync_single_range_for_cpu(rx_ring->dev,
4945 					      buffer_info->dma,
4946 					      buffer_info->page_offset,
4947 					      igb_rx_bufsz(rx_ring),
4948 					      DMA_FROM_DEVICE);
4949 
4950 		/* free resources associated with mapping */
4951 		dma_unmap_page_attrs(rx_ring->dev,
4952 				     buffer_info->dma,
4953 				     igb_rx_pg_size(rx_ring),
4954 				     DMA_FROM_DEVICE,
4955 				     IGB_RX_DMA_ATTR);
4956 		__page_frag_cache_drain(buffer_info->page,
4957 					buffer_info->pagecnt_bias);
4958 
4959 		i++;
4960 		if (i == rx_ring->count)
4961 			i = 0;
4962 	}
4963 
4964 	rx_ring->next_to_alloc = 0;
4965 	rx_ring->next_to_clean = 0;
4966 	rx_ring->next_to_use = 0;
4967 }
4968 
4969 /**
4970  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
4971  *  @adapter: board private structure
4972  **/
4973 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4974 {
4975 	int i;
4976 
4977 	for (i = 0; i < adapter->num_rx_queues; i++)
4978 		if (adapter->rx_ring[i])
4979 			igb_clean_rx_ring(adapter->rx_ring[i]);
4980 }
4981 
4982 /**
4983  *  igb_set_mac - Change the Ethernet Address of the NIC
4984  *  @netdev: network interface device structure
4985  *  @p: pointer to an address structure
4986  *
4987  *  Returns 0 on success, negative on failure
4988  **/
4989 static int igb_set_mac(struct net_device *netdev, void *p)
4990 {
4991 	struct igb_adapter *adapter = netdev_priv(netdev);
4992 	struct e1000_hw *hw = &adapter->hw;
4993 	struct sockaddr *addr = p;
4994 
4995 	if (!is_valid_ether_addr(addr->sa_data))
4996 		return -EADDRNOTAVAIL;
4997 
4998 	eth_hw_addr_set(netdev, addr->sa_data);
4999 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5000 
5001 	/* set the correct pool for the new PF MAC address in entry 0 */
5002 	igb_set_default_mac_filter(adapter);
5003 
5004 	return 0;
5005 }
5006 
5007 /**
5008  *  igb_write_mc_addr_list - write multicast addresses to MTA
5009  *  @netdev: network interface device structure
5010  *
5011  *  Writes multicast address list to the MTA hash table.
5012  *  Returns: -ENOMEM on failure
5013  *           0 on no addresses written
5014  *           X on writing X addresses to MTA
5015  **/
5016 static int igb_write_mc_addr_list(struct net_device *netdev)
5017 {
5018 	struct igb_adapter *adapter = netdev_priv(netdev);
5019 	struct e1000_hw *hw = &adapter->hw;
5020 	struct netdev_hw_addr *ha;
5021 	u8  *mta_list;
5022 	int i;
5023 
5024 	if (netdev_mc_empty(netdev)) {
5025 		/* nothing to program, so clear mc list */
5026 		igb_update_mc_addr_list(hw, NULL, 0);
5027 		igb_restore_vf_multicasts(adapter);
5028 		return 0;
5029 	}
5030 
5031 	mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5032 	if (!mta_list)
5033 		return -ENOMEM;
5034 
5035 	/* The shared function expects a packed array of only addresses. */
5036 	i = 0;
5037 	netdev_for_each_mc_addr(ha, netdev)
5038 		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5039 
5040 	igb_update_mc_addr_list(hw, mta_list, i);
5041 	kfree(mta_list);
5042 
5043 	return netdev_mc_count(netdev);
5044 }
5045 
5046 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5047 {
5048 	struct e1000_hw *hw = &adapter->hw;
5049 	u32 i, pf_id;
5050 
5051 	switch (hw->mac.type) {
5052 	case e1000_i210:
5053 	case e1000_i211:
5054 	case e1000_i350:
5055 		/* VLAN filtering needed for VLAN prio filter */
5056 		if (adapter->netdev->features & NETIF_F_NTUPLE)
5057 			break;
5058 		fallthrough;
5059 	case e1000_82576:
5060 	case e1000_82580:
5061 	case e1000_i354:
5062 		/* VLAN filtering needed for pool filtering */
5063 		if (adapter->vfs_allocated_count)
5064 			break;
5065 		fallthrough;
5066 	default:
5067 		return 1;
5068 	}
5069 
5070 	/* We are already in VLAN promisc, nothing to do */
5071 	if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5072 		return 0;
5073 
5074 	if (!adapter->vfs_allocated_count)
5075 		goto set_vfta;
5076 
5077 	/* Add PF to all active pools */
5078 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5079 
5080 	for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5081 		u32 vlvf = rd32(E1000_VLVF(i));
5082 
5083 		vlvf |= BIT(pf_id);
5084 		wr32(E1000_VLVF(i), vlvf);
5085 	}
5086 
5087 set_vfta:
5088 	/* Set all bits in the VLAN filter table array */
5089 	for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5090 		hw->mac.ops.write_vfta(hw, i, ~0U);
5091 
5092 	/* Set flag so we don't redo unnecessary work */
5093 	adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5094 
5095 	return 0;
5096 }
5097 
5098 #define VFTA_BLOCK_SIZE 8
5099 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5100 {
5101 	struct e1000_hw *hw = &adapter->hw;
5102 	u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5103 	u32 vid_start = vfta_offset * 32;
5104 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5105 	u32 i, vid, word, bits, pf_id;
5106 
5107 	/* guarantee that we don't scrub out management VLAN */
5108 	vid = adapter->mng_vlan_id;
5109 	if (vid >= vid_start && vid < vid_end)
5110 		vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5111 
5112 	if (!adapter->vfs_allocated_count)
5113 		goto set_vfta;
5114 
5115 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5116 
5117 	for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5118 		u32 vlvf = rd32(E1000_VLVF(i));
5119 
5120 		/* pull VLAN ID from VLVF */
5121 		vid = vlvf & VLAN_VID_MASK;
5122 
5123 		/* only concern ourselves with a certain range */
5124 		if (vid < vid_start || vid >= vid_end)
5125 			continue;
5126 
5127 		if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5128 			/* record VLAN ID in VFTA */
5129 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5130 
5131 			/* if PF is part of this then continue */
5132 			if (test_bit(vid, adapter->active_vlans))
5133 				continue;
5134 		}
5135 
5136 		/* remove PF from the pool */
5137 		bits = ~BIT(pf_id);
5138 		bits &= rd32(E1000_VLVF(i));
5139 		wr32(E1000_VLVF(i), bits);
5140 	}
5141 
5142 set_vfta:
5143 	/* extract values from active_vlans and write back to VFTA */
5144 	for (i = VFTA_BLOCK_SIZE; i--;) {
5145 		vid = (vfta_offset + i) * 32;
5146 		word = vid / BITS_PER_LONG;
5147 		bits = vid % BITS_PER_LONG;
5148 
5149 		vfta[i] |= adapter->active_vlans[word] >> bits;
5150 
5151 		hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5152 	}
5153 }
5154 
5155 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5156 {
5157 	u32 i;
5158 
5159 	/* We are not in VLAN promisc, nothing to do */
5160 	if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5161 		return;
5162 
5163 	/* Set flag so we don't redo unnecessary work */
5164 	adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5165 
5166 	for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5167 		igb_scrub_vfta(adapter, i);
5168 }
5169 
5170 /**
5171  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5172  *  @netdev: network interface device structure
5173  *
5174  *  The set_rx_mode entry point is called whenever the unicast or multicast
5175  *  address lists or the network interface flags are updated.  This routine is
5176  *  responsible for configuring the hardware for proper unicast, multicast,
5177  *  promiscuous mode, and all-multi behavior.
5178  **/
5179 static void igb_set_rx_mode(struct net_device *netdev)
5180 {
5181 	struct igb_adapter *adapter = netdev_priv(netdev);
5182 	struct e1000_hw *hw = &adapter->hw;
5183 	unsigned int vfn = adapter->vfs_allocated_count;
5184 	u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5185 	int count;
5186 
5187 	/* Check for Promiscuous and All Multicast modes */
5188 	if (netdev->flags & IFF_PROMISC) {
5189 		rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5190 		vmolr |= E1000_VMOLR_MPME;
5191 
5192 		/* enable use of UTA filter to force packets to default pool */
5193 		if (hw->mac.type == e1000_82576)
5194 			vmolr |= E1000_VMOLR_ROPE;
5195 	} else {
5196 		if (netdev->flags & IFF_ALLMULTI) {
5197 			rctl |= E1000_RCTL_MPE;
5198 			vmolr |= E1000_VMOLR_MPME;
5199 		} else {
5200 			/* Write addresses to the MTA, if the attempt fails
5201 			 * then we should just turn on promiscuous mode so
5202 			 * that we can at least receive multicast traffic
5203 			 */
5204 			count = igb_write_mc_addr_list(netdev);
5205 			if (count < 0) {
5206 				rctl |= E1000_RCTL_MPE;
5207 				vmolr |= E1000_VMOLR_MPME;
5208 			} else if (count) {
5209 				vmolr |= E1000_VMOLR_ROMPE;
5210 			}
5211 		}
5212 	}
5213 
5214 	/* Write addresses to available RAR registers, if there is not
5215 	 * sufficient space to store all the addresses then enable
5216 	 * unicast promiscuous mode
5217 	 */
5218 	if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5219 		rctl |= E1000_RCTL_UPE;
5220 		vmolr |= E1000_VMOLR_ROPE;
5221 	}
5222 
5223 	/* enable VLAN filtering by default */
5224 	rctl |= E1000_RCTL_VFE;
5225 
5226 	/* disable VLAN filtering for modes that require it */
5227 	if ((netdev->flags & IFF_PROMISC) ||
5228 	    (netdev->features & NETIF_F_RXALL)) {
5229 		/* if we fail to set all rules then just clear VFE */
5230 		if (igb_vlan_promisc_enable(adapter))
5231 			rctl &= ~E1000_RCTL_VFE;
5232 	} else {
5233 		igb_vlan_promisc_disable(adapter);
5234 	}
5235 
5236 	/* update state of unicast, multicast, and VLAN filtering modes */
5237 	rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5238 				     E1000_RCTL_VFE);
5239 	wr32(E1000_RCTL, rctl);
5240 
5241 #if (PAGE_SIZE < 8192)
5242 	if (!adapter->vfs_allocated_count) {
5243 		if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5244 			rlpml = IGB_MAX_FRAME_BUILD_SKB;
5245 	}
5246 #endif
5247 	wr32(E1000_RLPML, rlpml);
5248 
5249 	/* In order to support SR-IOV and eventually VMDq it is necessary to set
5250 	 * the VMOLR to enable the appropriate modes.  Without this workaround
5251 	 * we will have issues with VLAN tag stripping not being done for frames
5252 	 * that are only arriving because we are the default pool
5253 	 */
5254 	if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5255 		return;
5256 
5257 	/* set UTA to appropriate mode */
5258 	igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5259 
5260 	vmolr |= rd32(E1000_VMOLR(vfn)) &
5261 		 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5262 
5263 	/* enable Rx jumbo frames, restrict as needed to support build_skb */
5264 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
5265 #if (PAGE_SIZE < 8192)
5266 	if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5267 		vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5268 	else
5269 #endif
5270 		vmolr |= MAX_JUMBO_FRAME_SIZE;
5271 	vmolr |= E1000_VMOLR_LPE;
5272 
5273 	wr32(E1000_VMOLR(vfn), vmolr);
5274 
5275 	igb_restore_vf_multicasts(adapter);
5276 }
5277 
5278 static void igb_check_wvbr(struct igb_adapter *adapter)
5279 {
5280 	struct e1000_hw *hw = &adapter->hw;
5281 	u32 wvbr = 0;
5282 
5283 	switch (hw->mac.type) {
5284 	case e1000_82576:
5285 	case e1000_i350:
5286 		wvbr = rd32(E1000_WVBR);
5287 		if (!wvbr)
5288 			return;
5289 		break;
5290 	default:
5291 		break;
5292 	}
5293 
5294 	adapter->wvbr |= wvbr;
5295 }
5296 
5297 #define IGB_STAGGERED_QUEUE_OFFSET 8
5298 
5299 static void igb_spoof_check(struct igb_adapter *adapter)
5300 {
5301 	int j;
5302 
5303 	if (!adapter->wvbr)
5304 		return;
5305 
5306 	for (j = 0; j < adapter->vfs_allocated_count; j++) {
5307 		if (adapter->wvbr & BIT(j) ||
5308 		    adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5309 			dev_warn(&adapter->pdev->dev,
5310 				"Spoof event(s) detected on VF %d\n", j);
5311 			adapter->wvbr &=
5312 				~(BIT(j) |
5313 				  BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5314 		}
5315 	}
5316 }
5317 
5318 /* Need to wait a few seconds after link up to get diagnostic information from
5319  * the phy
5320  */
5321 static void igb_update_phy_info(struct timer_list *t)
5322 {
5323 	struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5324 	igb_get_phy_info(&adapter->hw);
5325 }
5326 
5327 /**
5328  *  igb_has_link - check shared code for link and determine up/down
5329  *  @adapter: pointer to driver private info
5330  **/
5331 bool igb_has_link(struct igb_adapter *adapter)
5332 {
5333 	struct e1000_hw *hw = &adapter->hw;
5334 	bool link_active = false;
5335 
5336 	/* get_link_status is set on LSC (link status) interrupt or
5337 	 * rx sequence error interrupt.  get_link_status will stay
5338 	 * false until the e1000_check_for_link establishes link
5339 	 * for copper adapters ONLY
5340 	 */
5341 	switch (hw->phy.media_type) {
5342 	case e1000_media_type_copper:
5343 		if (!hw->mac.get_link_status)
5344 			return true;
5345 		fallthrough;
5346 	case e1000_media_type_internal_serdes:
5347 		hw->mac.ops.check_for_link(hw);
5348 		link_active = !hw->mac.get_link_status;
5349 		break;
5350 	default:
5351 	case e1000_media_type_unknown:
5352 		break;
5353 	}
5354 
5355 	if (((hw->mac.type == e1000_i210) ||
5356 	     (hw->mac.type == e1000_i211)) &&
5357 	     (hw->phy.id == I210_I_PHY_ID)) {
5358 		if (!netif_carrier_ok(adapter->netdev)) {
5359 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5360 		} else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5361 			adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5362 			adapter->link_check_timeout = jiffies;
5363 		}
5364 	}
5365 
5366 	return link_active;
5367 }
5368 
5369 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5370 {
5371 	bool ret = false;
5372 	u32 ctrl_ext, thstat;
5373 
5374 	/* check for thermal sensor event on i350 copper only */
5375 	if (hw->mac.type == e1000_i350) {
5376 		thstat = rd32(E1000_THSTAT);
5377 		ctrl_ext = rd32(E1000_CTRL_EXT);
5378 
5379 		if ((hw->phy.media_type == e1000_media_type_copper) &&
5380 		    !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5381 			ret = !!(thstat & event);
5382 	}
5383 
5384 	return ret;
5385 }
5386 
5387 /**
5388  *  igb_check_lvmmc - check for malformed packets received
5389  *  and indicated in LVMMC register
5390  *  @adapter: pointer to adapter
5391  **/
5392 static void igb_check_lvmmc(struct igb_adapter *adapter)
5393 {
5394 	struct e1000_hw *hw = &adapter->hw;
5395 	u32 lvmmc;
5396 
5397 	lvmmc = rd32(E1000_LVMMC);
5398 	if (lvmmc) {
5399 		if (unlikely(net_ratelimit())) {
5400 			netdev_warn(adapter->netdev,
5401 				    "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5402 				    lvmmc);
5403 		}
5404 	}
5405 }
5406 
5407 /**
5408  *  igb_watchdog - Timer Call-back
5409  *  @t: pointer to timer_list containing our private info pointer
5410  **/
5411 static void igb_watchdog(struct timer_list *t)
5412 {
5413 	struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5414 	/* Do the rest outside of interrupt context */
5415 	schedule_work(&adapter->watchdog_task);
5416 }
5417 
5418 static void igb_watchdog_task(struct work_struct *work)
5419 {
5420 	struct igb_adapter *adapter = container_of(work,
5421 						   struct igb_adapter,
5422 						   watchdog_task);
5423 	struct e1000_hw *hw = &adapter->hw;
5424 	struct e1000_phy_info *phy = &hw->phy;
5425 	struct net_device *netdev = adapter->netdev;
5426 	u32 link;
5427 	int i;
5428 	u32 connsw;
5429 	u16 phy_data, retry_count = 20;
5430 
5431 	link = igb_has_link(adapter);
5432 
5433 	if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5434 		if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5435 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5436 		else
5437 			link = false;
5438 	}
5439 
5440 	/* Force link down if we have fiber to swap to */
5441 	if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5442 		if (hw->phy.media_type == e1000_media_type_copper) {
5443 			connsw = rd32(E1000_CONNSW);
5444 			if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5445 				link = 0;
5446 		}
5447 	}
5448 	if (link) {
5449 		/* Perform a reset if the media type changed. */
5450 		if (hw->dev_spec._82575.media_changed) {
5451 			hw->dev_spec._82575.media_changed = false;
5452 			adapter->flags |= IGB_FLAG_MEDIA_RESET;
5453 			igb_reset(adapter);
5454 		}
5455 		/* Cancel scheduled suspend requests. */
5456 		pm_runtime_resume(netdev->dev.parent);
5457 
5458 		if (!netif_carrier_ok(netdev)) {
5459 			u32 ctrl;
5460 
5461 			hw->mac.ops.get_speed_and_duplex(hw,
5462 							 &adapter->link_speed,
5463 							 &adapter->link_duplex);
5464 
5465 			ctrl = rd32(E1000_CTRL);
5466 			/* Links status message must follow this format */
5467 			netdev_info(netdev,
5468 			       "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5469 			       netdev->name,
5470 			       adapter->link_speed,
5471 			       adapter->link_duplex == FULL_DUPLEX ?
5472 			       "Full" : "Half",
5473 			       (ctrl & E1000_CTRL_TFCE) &&
5474 			       (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5475 			       (ctrl & E1000_CTRL_RFCE) ?  "RX" :
5476 			       (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
5477 
5478 			/* disable EEE if enabled */
5479 			if ((adapter->flags & IGB_FLAG_EEE) &&
5480 				(adapter->link_duplex == HALF_DUPLEX)) {
5481 				dev_info(&adapter->pdev->dev,
5482 				"EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5483 				adapter->hw.dev_spec._82575.eee_disable = true;
5484 				adapter->flags &= ~IGB_FLAG_EEE;
5485 			}
5486 
5487 			/* check if SmartSpeed worked */
5488 			igb_check_downshift(hw);
5489 			if (phy->speed_downgraded)
5490 				netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5491 
5492 			/* check for thermal sensor event */
5493 			if (igb_thermal_sensor_event(hw,
5494 			    E1000_THSTAT_LINK_THROTTLE))
5495 				netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5496 
5497 			/* adjust timeout factor according to speed/duplex */
5498 			adapter->tx_timeout_factor = 1;
5499 			switch (adapter->link_speed) {
5500 			case SPEED_10:
5501 				adapter->tx_timeout_factor = 14;
5502 				break;
5503 			case SPEED_100:
5504 				/* maybe add some timeout factor ? */
5505 				break;
5506 			}
5507 
5508 			if (adapter->link_speed != SPEED_1000)
5509 				goto no_wait;
5510 
5511 			/* wait for Remote receiver status OK */
5512 retry_read_status:
5513 			if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5514 					      &phy_data)) {
5515 				if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5516 				    retry_count) {
5517 					msleep(100);
5518 					retry_count--;
5519 					goto retry_read_status;
5520 				} else if (!retry_count) {
5521 					dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5522 				}
5523 			} else {
5524 				dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5525 			}
5526 no_wait:
5527 			netif_carrier_on(netdev);
5528 
5529 			igb_ping_all_vfs(adapter);
5530 			igb_check_vf_rate_limit(adapter);
5531 
5532 			/* link state has changed, schedule phy info update */
5533 			if (!test_bit(__IGB_DOWN, &adapter->state))
5534 				mod_timer(&adapter->phy_info_timer,
5535 					  round_jiffies(jiffies + 2 * HZ));
5536 		}
5537 	} else {
5538 		if (netif_carrier_ok(netdev)) {
5539 			adapter->link_speed = 0;
5540 			adapter->link_duplex = 0;
5541 
5542 			/* check for thermal sensor event */
5543 			if (igb_thermal_sensor_event(hw,
5544 			    E1000_THSTAT_PWR_DOWN)) {
5545 				netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5546 			}
5547 
5548 			/* Links status message must follow this format */
5549 			netdev_info(netdev, "igb: %s NIC Link is Down\n",
5550 			       netdev->name);
5551 			netif_carrier_off(netdev);
5552 
5553 			igb_ping_all_vfs(adapter);
5554 
5555 			/* link state has changed, schedule phy info update */
5556 			if (!test_bit(__IGB_DOWN, &adapter->state))
5557 				mod_timer(&adapter->phy_info_timer,
5558 					  round_jiffies(jiffies + 2 * HZ));
5559 
5560 			/* link is down, time to check for alternate media */
5561 			if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5562 				igb_check_swap_media(adapter);
5563 				if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5564 					schedule_work(&adapter->reset_task);
5565 					/* return immediately */
5566 					return;
5567 				}
5568 			}
5569 			pm_schedule_suspend(netdev->dev.parent,
5570 					    MSEC_PER_SEC * 5);
5571 
5572 		/* also check for alternate media here */
5573 		} else if (!netif_carrier_ok(netdev) &&
5574 			   (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5575 			igb_check_swap_media(adapter);
5576 			if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5577 				schedule_work(&adapter->reset_task);
5578 				/* return immediately */
5579 				return;
5580 			}
5581 		}
5582 	}
5583 
5584 	spin_lock(&adapter->stats64_lock);
5585 	igb_update_stats(adapter);
5586 	spin_unlock(&adapter->stats64_lock);
5587 
5588 	for (i = 0; i < adapter->num_tx_queues; i++) {
5589 		struct igb_ring *tx_ring = adapter->tx_ring[i];
5590 		if (!netif_carrier_ok(netdev)) {
5591 			/* We've lost link, so the controller stops DMA,
5592 			 * but we've got queued Tx work that's never going
5593 			 * to get done, so reset controller to flush Tx.
5594 			 * (Do the reset outside of interrupt context).
5595 			 */
5596 			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5597 				adapter->tx_timeout_count++;
5598 				schedule_work(&adapter->reset_task);
5599 				/* return immediately since reset is imminent */
5600 				return;
5601 			}
5602 		}
5603 
5604 		/* Force detection of hung controller every watchdog period */
5605 		set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5606 	}
5607 
5608 	/* Cause software interrupt to ensure Rx ring is cleaned */
5609 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5610 		u32 eics = 0;
5611 
5612 		for (i = 0; i < adapter->num_q_vectors; i++)
5613 			eics |= adapter->q_vector[i]->eims_value;
5614 		wr32(E1000_EICS, eics);
5615 	} else {
5616 		wr32(E1000_ICS, E1000_ICS_RXDMT0);
5617 	}
5618 
5619 	igb_spoof_check(adapter);
5620 	igb_ptp_rx_hang(adapter);
5621 	igb_ptp_tx_hang(adapter);
5622 
5623 	/* Check LVMMC register on i350/i354 only */
5624 	if ((adapter->hw.mac.type == e1000_i350) ||
5625 	    (adapter->hw.mac.type == e1000_i354))
5626 		igb_check_lvmmc(adapter);
5627 
5628 	/* Reset the timer */
5629 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
5630 		if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5631 			mod_timer(&adapter->watchdog_timer,
5632 				  round_jiffies(jiffies +  HZ));
5633 		else
5634 			mod_timer(&adapter->watchdog_timer,
5635 				  round_jiffies(jiffies + 2 * HZ));
5636 	}
5637 }
5638 
5639 enum latency_range {
5640 	lowest_latency = 0,
5641 	low_latency = 1,
5642 	bulk_latency = 2,
5643 	latency_invalid = 255
5644 };
5645 
5646 /**
5647  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5648  *  @q_vector: pointer to q_vector
5649  *
5650  *  Stores a new ITR value based on strictly on packet size.  This
5651  *  algorithm is less sophisticated than that used in igb_update_itr,
5652  *  due to the difficulty of synchronizing statistics across multiple
5653  *  receive rings.  The divisors and thresholds used by this function
5654  *  were determined based on theoretical maximum wire speed and testing
5655  *  data, in order to minimize response time while increasing bulk
5656  *  throughput.
5657  *  This functionality is controlled by ethtool's coalescing settings.
5658  *  NOTE:  This function is called only when operating in a multiqueue
5659  *         receive environment.
5660  **/
5661 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5662 {
5663 	int new_val = q_vector->itr_val;
5664 	int avg_wire_size = 0;
5665 	struct igb_adapter *adapter = q_vector->adapter;
5666 	unsigned int packets;
5667 
5668 	/* For non-gigabit speeds, just fix the interrupt rate at 4000
5669 	 * ints/sec - ITR timer value of 120 ticks.
5670 	 */
5671 	if (adapter->link_speed != SPEED_1000) {
5672 		new_val = IGB_4K_ITR;
5673 		goto set_itr_val;
5674 	}
5675 
5676 	packets = q_vector->rx.total_packets;
5677 	if (packets)
5678 		avg_wire_size = q_vector->rx.total_bytes / packets;
5679 
5680 	packets = q_vector->tx.total_packets;
5681 	if (packets)
5682 		avg_wire_size = max_t(u32, avg_wire_size,
5683 				      q_vector->tx.total_bytes / packets);
5684 
5685 	/* if avg_wire_size isn't set no work was done */
5686 	if (!avg_wire_size)
5687 		goto clear_counts;
5688 
5689 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
5690 	avg_wire_size += 24;
5691 
5692 	/* Don't starve jumbo frames */
5693 	avg_wire_size = min(avg_wire_size, 3000);
5694 
5695 	/* Give a little boost to mid-size frames */
5696 	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5697 		new_val = avg_wire_size / 3;
5698 	else
5699 		new_val = avg_wire_size / 2;
5700 
5701 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
5702 	if (new_val < IGB_20K_ITR &&
5703 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5704 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5705 		new_val = IGB_20K_ITR;
5706 
5707 set_itr_val:
5708 	if (new_val != q_vector->itr_val) {
5709 		q_vector->itr_val = new_val;
5710 		q_vector->set_itr = 1;
5711 	}
5712 clear_counts:
5713 	q_vector->rx.total_bytes = 0;
5714 	q_vector->rx.total_packets = 0;
5715 	q_vector->tx.total_bytes = 0;
5716 	q_vector->tx.total_packets = 0;
5717 }
5718 
5719 /**
5720  *  igb_update_itr - update the dynamic ITR value based on statistics
5721  *  @q_vector: pointer to q_vector
5722  *  @ring_container: ring info to update the itr for
5723  *
5724  *  Stores a new ITR value based on packets and byte
5725  *  counts during the last interrupt.  The advantage of per interrupt
5726  *  computation is faster updates and more accurate ITR for the current
5727  *  traffic pattern.  Constants in this function were computed
5728  *  based on theoretical maximum wire speed and thresholds were set based
5729  *  on testing data as well as attempting to minimize response time
5730  *  while increasing bulk throughput.
5731  *  This functionality is controlled by ethtool's coalescing settings.
5732  *  NOTE:  These calculations are only valid when operating in a single-
5733  *         queue environment.
5734  **/
5735 static void igb_update_itr(struct igb_q_vector *q_vector,
5736 			   struct igb_ring_container *ring_container)
5737 {
5738 	unsigned int packets = ring_container->total_packets;
5739 	unsigned int bytes = ring_container->total_bytes;
5740 	u8 itrval = ring_container->itr;
5741 
5742 	/* no packets, exit with status unchanged */
5743 	if (packets == 0)
5744 		return;
5745 
5746 	switch (itrval) {
5747 	case lowest_latency:
5748 		/* handle TSO and jumbo frames */
5749 		if (bytes/packets > 8000)
5750 			itrval = bulk_latency;
5751 		else if ((packets < 5) && (bytes > 512))
5752 			itrval = low_latency;
5753 		break;
5754 	case low_latency:  /* 50 usec aka 20000 ints/s */
5755 		if (bytes > 10000) {
5756 			/* this if handles the TSO accounting */
5757 			if (bytes/packets > 8000)
5758 				itrval = bulk_latency;
5759 			else if ((packets < 10) || ((bytes/packets) > 1200))
5760 				itrval = bulk_latency;
5761 			else if ((packets > 35))
5762 				itrval = lowest_latency;
5763 		} else if (bytes/packets > 2000) {
5764 			itrval = bulk_latency;
5765 		} else if (packets <= 2 && bytes < 512) {
5766 			itrval = lowest_latency;
5767 		}
5768 		break;
5769 	case bulk_latency: /* 250 usec aka 4000 ints/s */
5770 		if (bytes > 25000) {
5771 			if (packets > 35)
5772 				itrval = low_latency;
5773 		} else if (bytes < 1500) {
5774 			itrval = low_latency;
5775 		}
5776 		break;
5777 	}
5778 
5779 	/* clear work counters since we have the values we need */
5780 	ring_container->total_bytes = 0;
5781 	ring_container->total_packets = 0;
5782 
5783 	/* write updated itr to ring container */
5784 	ring_container->itr = itrval;
5785 }
5786 
5787 static void igb_set_itr(struct igb_q_vector *q_vector)
5788 {
5789 	struct igb_adapter *adapter = q_vector->adapter;
5790 	u32 new_itr = q_vector->itr_val;
5791 	u8 current_itr = 0;
5792 
5793 	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5794 	if (adapter->link_speed != SPEED_1000) {
5795 		current_itr = 0;
5796 		new_itr = IGB_4K_ITR;
5797 		goto set_itr_now;
5798 	}
5799 
5800 	igb_update_itr(q_vector, &q_vector->tx);
5801 	igb_update_itr(q_vector, &q_vector->rx);
5802 
5803 	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5804 
5805 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
5806 	if (current_itr == lowest_latency &&
5807 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5808 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5809 		current_itr = low_latency;
5810 
5811 	switch (current_itr) {
5812 	/* counts and packets in update_itr are dependent on these numbers */
5813 	case lowest_latency:
5814 		new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5815 		break;
5816 	case low_latency:
5817 		new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5818 		break;
5819 	case bulk_latency:
5820 		new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5821 		break;
5822 	default:
5823 		break;
5824 	}
5825 
5826 set_itr_now:
5827 	if (new_itr != q_vector->itr_val) {
5828 		/* this attempts to bias the interrupt rate towards Bulk
5829 		 * by adding intermediate steps when interrupt rate is
5830 		 * increasing
5831 		 */
5832 		new_itr = new_itr > q_vector->itr_val ?
5833 			  max((new_itr * q_vector->itr_val) /
5834 			  (new_itr + (q_vector->itr_val >> 2)),
5835 			  new_itr) : new_itr;
5836 		/* Don't write the value here; it resets the adapter's
5837 		 * internal timer, and causes us to delay far longer than
5838 		 * we should between interrupts.  Instead, we write the ITR
5839 		 * value at the beginning of the next interrupt so the timing
5840 		 * ends up being correct.
5841 		 */
5842 		q_vector->itr_val = new_itr;
5843 		q_vector->set_itr = 1;
5844 	}
5845 }
5846 
5847 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5848 			    struct igb_tx_buffer *first,
5849 			    u32 vlan_macip_lens, u32 type_tucmd,
5850 			    u32 mss_l4len_idx)
5851 {
5852 	struct e1000_adv_tx_context_desc *context_desc;
5853 	u16 i = tx_ring->next_to_use;
5854 	struct timespec64 ts;
5855 
5856 	context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5857 
5858 	i++;
5859 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5860 
5861 	/* set bits to identify this as an advanced context descriptor */
5862 	type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5863 
5864 	/* For 82575, context index must be unique per ring. */
5865 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5866 		mss_l4len_idx |= tx_ring->reg_idx << 4;
5867 
5868 	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
5869 	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
5870 	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);
5871 
5872 	/* We assume there is always a valid tx time available. Invalid times
5873 	 * should have been handled by the upper layers.
5874 	 */
5875 	if (tx_ring->launchtime_enable) {
5876 		ts = ktime_to_timespec64(first->skb->tstamp);
5877 		skb_txtime_consumed(first->skb);
5878 		context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5879 	} else {
5880 		context_desc->seqnum_seed = 0;
5881 	}
5882 }
5883 
5884 static int igb_tso(struct igb_ring *tx_ring,
5885 		   struct igb_tx_buffer *first,
5886 		   u8 *hdr_len)
5887 {
5888 	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5889 	struct sk_buff *skb = first->skb;
5890 	union {
5891 		struct iphdr *v4;
5892 		struct ipv6hdr *v6;
5893 		unsigned char *hdr;
5894 	} ip;
5895 	union {
5896 		struct tcphdr *tcp;
5897 		struct udphdr *udp;
5898 		unsigned char *hdr;
5899 	} l4;
5900 	u32 paylen, l4_offset;
5901 	int err;
5902 
5903 	if (skb->ip_summed != CHECKSUM_PARTIAL)
5904 		return 0;
5905 
5906 	if (!skb_is_gso(skb))
5907 		return 0;
5908 
5909 	err = skb_cow_head(skb, 0);
5910 	if (err < 0)
5911 		return err;
5912 
5913 	ip.hdr = skb_network_header(skb);
5914 	l4.hdr = skb_checksum_start(skb);
5915 
5916 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5917 	type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5918 		      E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
5919 
5920 	/* initialize outer IP header fields */
5921 	if (ip.v4->version == 4) {
5922 		unsigned char *csum_start = skb_checksum_start(skb);
5923 		unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5924 
5925 		/* IP header will have to cancel out any data that
5926 		 * is not a part of the outer IP header
5927 		 */
5928 		ip.v4->check = csum_fold(csum_partial(trans_start,
5929 						      csum_start - trans_start,
5930 						      0));
5931 		type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5932 
5933 		ip.v4->tot_len = 0;
5934 		first->tx_flags |= IGB_TX_FLAGS_TSO |
5935 				   IGB_TX_FLAGS_CSUM |
5936 				   IGB_TX_FLAGS_IPV4;
5937 	} else {
5938 		ip.v6->payload_len = 0;
5939 		first->tx_flags |= IGB_TX_FLAGS_TSO |
5940 				   IGB_TX_FLAGS_CSUM;
5941 	}
5942 
5943 	/* determine offset of inner transport header */
5944 	l4_offset = l4.hdr - skb->data;
5945 
5946 	/* remove payload length from inner checksum */
5947 	paylen = skb->len - l4_offset;
5948 	if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
5949 		/* compute length of segmentation header */
5950 		*hdr_len = (l4.tcp->doff * 4) + l4_offset;
5951 		csum_replace_by_diff(&l4.tcp->check,
5952 			(__force __wsum)htonl(paylen));
5953 	} else {
5954 		/* compute length of segmentation header */
5955 		*hdr_len = sizeof(*l4.udp) + l4_offset;
5956 		csum_replace_by_diff(&l4.udp->check,
5957 				     (__force __wsum)htonl(paylen));
5958 	}
5959 
5960 	/* update gso size and bytecount with header size */
5961 	first->gso_segs = skb_shinfo(skb)->gso_segs;
5962 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
5963 
5964 	/* MSS L4LEN IDX */
5965 	mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5966 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5967 
5968 	/* VLAN MACLEN IPLEN */
5969 	vlan_macip_lens = l4.hdr - ip.hdr;
5970 	vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5971 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5972 
5973 	igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5974 			type_tucmd, mss_l4len_idx);
5975 
5976 	return 1;
5977 }
5978 
5979 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5980 {
5981 	struct sk_buff *skb = first->skb;
5982 	u32 vlan_macip_lens = 0;
5983 	u32 type_tucmd = 0;
5984 
5985 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
5986 csum_failed:
5987 		if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5988 		    !tx_ring->launchtime_enable)
5989 			return;
5990 		goto no_csum;
5991 	}
5992 
5993 	switch (skb->csum_offset) {
5994 	case offsetof(struct tcphdr, check):
5995 		type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5996 		fallthrough;
5997 	case offsetof(struct udphdr, check):
5998 		break;
5999 	case offsetof(struct sctphdr, checksum):
6000 		/* validate that this is actually an SCTP request */
6001 		if (skb_csum_is_sctp(skb)) {
6002 			type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6003 			break;
6004 		}
6005 		fallthrough;
6006 	default:
6007 		skb_checksum_help(skb);
6008 		goto csum_failed;
6009 	}
6010 
6011 	/* update TX checksum flag */
6012 	first->tx_flags |= IGB_TX_FLAGS_CSUM;
6013 	vlan_macip_lens = skb_checksum_start_offset(skb) -
6014 			  skb_network_offset(skb);
6015 no_csum:
6016 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6017 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6018 
6019 	igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6020 }
6021 
6022 #define IGB_SET_FLAG(_input, _flag, _result) \
6023 	((_flag <= _result) ? \
6024 	 ((u32)(_input & _flag) * (_result / _flag)) : \
6025 	 ((u32)(_input & _flag) / (_flag / _result)))
6026 
6027 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6028 {
6029 	/* set type for advanced descriptor with frame checksum insertion */
6030 	u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6031 		       E1000_ADVTXD_DCMD_DEXT |
6032 		       E1000_ADVTXD_DCMD_IFCS;
6033 
6034 	/* set HW vlan bit if vlan is present */
6035 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6036 				 (E1000_ADVTXD_DCMD_VLE));
6037 
6038 	/* set segmentation bits for TSO */
6039 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6040 				 (E1000_ADVTXD_DCMD_TSE));
6041 
6042 	/* set timestamp bit if present */
6043 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6044 				 (E1000_ADVTXD_MAC_TSTAMP));
6045 
6046 	/* insert frame checksum */
6047 	cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6048 
6049 	return cmd_type;
6050 }
6051 
6052 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6053 				 union e1000_adv_tx_desc *tx_desc,
6054 				 u32 tx_flags, unsigned int paylen)
6055 {
6056 	u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6057 
6058 	/* 82575 requires a unique index per ring */
6059 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6060 		olinfo_status |= tx_ring->reg_idx << 4;
6061 
6062 	/* insert L4 checksum */
6063 	olinfo_status |= IGB_SET_FLAG(tx_flags,
6064 				      IGB_TX_FLAGS_CSUM,
6065 				      (E1000_TXD_POPTS_TXSM << 8));
6066 
6067 	/* insert IPv4 checksum */
6068 	olinfo_status |= IGB_SET_FLAG(tx_flags,
6069 				      IGB_TX_FLAGS_IPV4,
6070 				      (E1000_TXD_POPTS_IXSM << 8));
6071 
6072 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6073 }
6074 
6075 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6076 {
6077 	struct net_device *netdev = tx_ring->netdev;
6078 
6079 	netif_stop_subqueue(netdev, tx_ring->queue_index);
6080 
6081 	/* Herbert's original patch had:
6082 	 *  smp_mb__after_netif_stop_queue();
6083 	 * but since that doesn't exist yet, just open code it.
6084 	 */
6085 	smp_mb();
6086 
6087 	/* We need to check again in a case another CPU has just
6088 	 * made room available.
6089 	 */
6090 	if (igb_desc_unused(tx_ring) < size)
6091 		return -EBUSY;
6092 
6093 	/* A reprieve! */
6094 	netif_wake_subqueue(netdev, tx_ring->queue_index);
6095 
6096 	u64_stats_update_begin(&tx_ring->tx_syncp2);
6097 	tx_ring->tx_stats.restart_queue2++;
6098 	u64_stats_update_end(&tx_ring->tx_syncp2);
6099 
6100 	return 0;
6101 }
6102 
6103 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6104 {
6105 	if (igb_desc_unused(tx_ring) >= size)
6106 		return 0;
6107 	return __igb_maybe_stop_tx(tx_ring, size);
6108 }
6109 
6110 static int igb_tx_map(struct igb_ring *tx_ring,
6111 		      struct igb_tx_buffer *first,
6112 		      const u8 hdr_len)
6113 {
6114 	struct sk_buff *skb = first->skb;
6115 	struct igb_tx_buffer *tx_buffer;
6116 	union e1000_adv_tx_desc *tx_desc;
6117 	skb_frag_t *frag;
6118 	dma_addr_t dma;
6119 	unsigned int data_len, size;
6120 	u32 tx_flags = first->tx_flags;
6121 	u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6122 	u16 i = tx_ring->next_to_use;
6123 
6124 	tx_desc = IGB_TX_DESC(tx_ring, i);
6125 
6126 	igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6127 
6128 	size = skb_headlen(skb);
6129 	data_len = skb->data_len;
6130 
6131 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6132 
6133 	tx_buffer = first;
6134 
6135 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6136 		if (dma_mapping_error(tx_ring->dev, dma))
6137 			goto dma_error;
6138 
6139 		/* record length, and DMA address */
6140 		dma_unmap_len_set(tx_buffer, len, size);
6141 		dma_unmap_addr_set(tx_buffer, dma, dma);
6142 
6143 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
6144 
6145 		while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6146 			tx_desc->read.cmd_type_len =
6147 				cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6148 
6149 			i++;
6150 			tx_desc++;
6151 			if (i == tx_ring->count) {
6152 				tx_desc = IGB_TX_DESC(tx_ring, 0);
6153 				i = 0;
6154 			}
6155 			tx_desc->read.olinfo_status = 0;
6156 
6157 			dma += IGB_MAX_DATA_PER_TXD;
6158 			size -= IGB_MAX_DATA_PER_TXD;
6159 
6160 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
6161 		}
6162 
6163 		if (likely(!data_len))
6164 			break;
6165 
6166 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6167 
6168 		i++;
6169 		tx_desc++;
6170 		if (i == tx_ring->count) {
6171 			tx_desc = IGB_TX_DESC(tx_ring, 0);
6172 			i = 0;
6173 		}
6174 		tx_desc->read.olinfo_status = 0;
6175 
6176 		size = skb_frag_size(frag);
6177 		data_len -= size;
6178 
6179 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6180 				       size, DMA_TO_DEVICE);
6181 
6182 		tx_buffer = &tx_ring->tx_buffer_info[i];
6183 	}
6184 
6185 	/* write last descriptor with RS and EOP bits */
6186 	cmd_type |= size | IGB_TXD_DCMD;
6187 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6188 
6189 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6190 
6191 	/* set the timestamp */
6192 	first->time_stamp = jiffies;
6193 
6194 	skb_tx_timestamp(skb);
6195 
6196 	/* Force memory writes to complete before letting h/w know there
6197 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
6198 	 * memory model archs, such as IA-64).
6199 	 *
6200 	 * We also need this memory barrier to make certain all of the
6201 	 * status bits have been updated before next_to_watch is written.
6202 	 */
6203 	dma_wmb();
6204 
6205 	/* set next_to_watch value indicating a packet is present */
6206 	first->next_to_watch = tx_desc;
6207 
6208 	i++;
6209 	if (i == tx_ring->count)
6210 		i = 0;
6211 
6212 	tx_ring->next_to_use = i;
6213 
6214 	/* Make sure there is space in the ring for the next send. */
6215 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6216 
6217 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6218 		writel(i, tx_ring->tail);
6219 	}
6220 	return 0;
6221 
6222 dma_error:
6223 	dev_err(tx_ring->dev, "TX DMA map failed\n");
6224 	tx_buffer = &tx_ring->tx_buffer_info[i];
6225 
6226 	/* clear dma mappings for failed tx_buffer_info map */
6227 	while (tx_buffer != first) {
6228 		if (dma_unmap_len(tx_buffer, len))
6229 			dma_unmap_page(tx_ring->dev,
6230 				       dma_unmap_addr(tx_buffer, dma),
6231 				       dma_unmap_len(tx_buffer, len),
6232 				       DMA_TO_DEVICE);
6233 		dma_unmap_len_set(tx_buffer, len, 0);
6234 
6235 		if (i-- == 0)
6236 			i += tx_ring->count;
6237 		tx_buffer = &tx_ring->tx_buffer_info[i];
6238 	}
6239 
6240 	if (dma_unmap_len(tx_buffer, len))
6241 		dma_unmap_single(tx_ring->dev,
6242 				 dma_unmap_addr(tx_buffer, dma),
6243 				 dma_unmap_len(tx_buffer, len),
6244 				 DMA_TO_DEVICE);
6245 	dma_unmap_len_set(tx_buffer, len, 0);
6246 
6247 	dev_kfree_skb_any(tx_buffer->skb);
6248 	tx_buffer->skb = NULL;
6249 
6250 	tx_ring->next_to_use = i;
6251 
6252 	return -1;
6253 }
6254 
6255 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6256 		      struct igb_ring *tx_ring,
6257 		      struct xdp_frame *xdpf)
6258 {
6259 	union e1000_adv_tx_desc *tx_desc;
6260 	u32 len, cmd_type, olinfo_status;
6261 	struct igb_tx_buffer *tx_buffer;
6262 	dma_addr_t dma;
6263 	u16 i;
6264 
6265 	len = xdpf->len;
6266 
6267 	if (unlikely(!igb_desc_unused(tx_ring)))
6268 		return IGB_XDP_CONSUMED;
6269 
6270 	dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE);
6271 	if (dma_mapping_error(tx_ring->dev, dma))
6272 		return IGB_XDP_CONSUMED;
6273 
6274 	/* record the location of the first descriptor for this packet */
6275 	tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6276 	tx_buffer->bytecount = len;
6277 	tx_buffer->gso_segs = 1;
6278 	tx_buffer->protocol = 0;
6279 
6280 	i = tx_ring->next_to_use;
6281 	tx_desc = IGB_TX_DESC(tx_ring, i);
6282 
6283 	dma_unmap_len_set(tx_buffer, len, len);
6284 	dma_unmap_addr_set(tx_buffer, dma, dma);
6285 	tx_buffer->type = IGB_TYPE_XDP;
6286 	tx_buffer->xdpf = xdpf;
6287 
6288 	tx_desc->read.buffer_addr = cpu_to_le64(dma);
6289 
6290 	/* put descriptor type bits */
6291 	cmd_type = E1000_ADVTXD_DTYP_DATA |
6292 		   E1000_ADVTXD_DCMD_DEXT |
6293 		   E1000_ADVTXD_DCMD_IFCS;
6294 	cmd_type |= len | IGB_TXD_DCMD;
6295 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6296 
6297 	olinfo_status = len << E1000_ADVTXD_PAYLEN_SHIFT;
6298 	/* 82575 requires a unique index per ring */
6299 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6300 		olinfo_status |= tx_ring->reg_idx << 4;
6301 
6302 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6303 
6304 	netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount);
6305 
6306 	/* set the timestamp */
6307 	tx_buffer->time_stamp = jiffies;
6308 
6309 	/* Avoid any potential race with xdp_xmit and cleanup */
6310 	smp_wmb();
6311 
6312 	/* set next_to_watch value indicating a packet is present */
6313 	i++;
6314 	if (i == tx_ring->count)
6315 		i = 0;
6316 
6317 	tx_buffer->next_to_watch = tx_desc;
6318 	tx_ring->next_to_use = i;
6319 
6320 	/* Make sure there is space in the ring for the next send. */
6321 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6322 
6323 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6324 		writel(i, tx_ring->tail);
6325 
6326 	return IGB_XDP_TX;
6327 }
6328 
6329 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6330 				struct igb_ring *tx_ring)
6331 {
6332 	struct igb_tx_buffer *first;
6333 	int tso;
6334 	u32 tx_flags = 0;
6335 	unsigned short f;
6336 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
6337 	__be16 protocol = vlan_get_protocol(skb);
6338 	u8 hdr_len = 0;
6339 
6340 	/* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6341 	 *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6342 	 *       + 2 desc gap to keep tail from touching head,
6343 	 *       + 1 desc for context descriptor,
6344 	 * otherwise try next time
6345 	 */
6346 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6347 		count += TXD_USE_COUNT(skb_frag_size(
6348 						&skb_shinfo(skb)->frags[f]));
6349 
6350 	if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6351 		/* this is a hard error */
6352 		return NETDEV_TX_BUSY;
6353 	}
6354 
6355 	/* record the location of the first descriptor for this packet */
6356 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6357 	first->type = IGB_TYPE_SKB;
6358 	first->skb = skb;
6359 	first->bytecount = skb->len;
6360 	first->gso_segs = 1;
6361 
6362 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6363 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6364 
6365 		if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6366 		    !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6367 					   &adapter->state)) {
6368 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6369 			tx_flags |= IGB_TX_FLAGS_TSTAMP;
6370 
6371 			adapter->ptp_tx_skb = skb_get(skb);
6372 			adapter->ptp_tx_start = jiffies;
6373 			if (adapter->hw.mac.type == e1000_82576)
6374 				schedule_work(&adapter->ptp_tx_work);
6375 		} else {
6376 			adapter->tx_hwtstamp_skipped++;
6377 		}
6378 	}
6379 
6380 	if (skb_vlan_tag_present(skb)) {
6381 		tx_flags |= IGB_TX_FLAGS_VLAN;
6382 		tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6383 	}
6384 
6385 	/* record initial flags and protocol */
6386 	first->tx_flags = tx_flags;
6387 	first->protocol = protocol;
6388 
6389 	tso = igb_tso(tx_ring, first, &hdr_len);
6390 	if (tso < 0)
6391 		goto out_drop;
6392 	else if (!tso)
6393 		igb_tx_csum(tx_ring, first);
6394 
6395 	if (igb_tx_map(tx_ring, first, hdr_len))
6396 		goto cleanup_tx_tstamp;
6397 
6398 	return NETDEV_TX_OK;
6399 
6400 out_drop:
6401 	dev_kfree_skb_any(first->skb);
6402 	first->skb = NULL;
6403 cleanup_tx_tstamp:
6404 	if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6405 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6406 
6407 		dev_kfree_skb_any(adapter->ptp_tx_skb);
6408 		adapter->ptp_tx_skb = NULL;
6409 		if (adapter->hw.mac.type == e1000_82576)
6410 			cancel_work_sync(&adapter->ptp_tx_work);
6411 		clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6412 	}
6413 
6414 	return NETDEV_TX_OK;
6415 }
6416 
6417 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6418 						    struct sk_buff *skb)
6419 {
6420 	unsigned int r_idx = skb->queue_mapping;
6421 
6422 	if (r_idx >= adapter->num_tx_queues)
6423 		r_idx = r_idx % adapter->num_tx_queues;
6424 
6425 	return adapter->tx_ring[r_idx];
6426 }
6427 
6428 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6429 				  struct net_device *netdev)
6430 {
6431 	struct igb_adapter *adapter = netdev_priv(netdev);
6432 
6433 	/* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6434 	 * in order to meet this minimum size requirement.
6435 	 */
6436 	if (skb_put_padto(skb, 17))
6437 		return NETDEV_TX_OK;
6438 
6439 	return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6440 }
6441 
6442 /**
6443  *  igb_tx_timeout - Respond to a Tx Hang
6444  *  @netdev: network interface device structure
6445  *  @txqueue: number of the Tx queue that hung (unused)
6446  **/
6447 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6448 {
6449 	struct igb_adapter *adapter = netdev_priv(netdev);
6450 	struct e1000_hw *hw = &adapter->hw;
6451 
6452 	/* Do the reset outside of interrupt context */
6453 	adapter->tx_timeout_count++;
6454 
6455 	if (hw->mac.type >= e1000_82580)
6456 		hw->dev_spec._82575.global_device_reset = true;
6457 
6458 	schedule_work(&adapter->reset_task);
6459 	wr32(E1000_EICS,
6460 	     (adapter->eims_enable_mask & ~adapter->eims_other));
6461 }
6462 
6463 static void igb_reset_task(struct work_struct *work)
6464 {
6465 	struct igb_adapter *adapter;
6466 	adapter = container_of(work, struct igb_adapter, reset_task);
6467 
6468 	rtnl_lock();
6469 	/* If we're already down or resetting, just bail */
6470 	if (test_bit(__IGB_DOWN, &adapter->state) ||
6471 	    test_bit(__IGB_RESETTING, &adapter->state)) {
6472 		rtnl_unlock();
6473 		return;
6474 	}
6475 
6476 	igb_dump(adapter);
6477 	netdev_err(adapter->netdev, "Reset adapter\n");
6478 	igb_reinit_locked(adapter);
6479 	rtnl_unlock();
6480 }
6481 
6482 /**
6483  *  igb_get_stats64 - Get System Network Statistics
6484  *  @netdev: network interface device structure
6485  *  @stats: rtnl_link_stats64 pointer
6486  **/
6487 static void igb_get_stats64(struct net_device *netdev,
6488 			    struct rtnl_link_stats64 *stats)
6489 {
6490 	struct igb_adapter *adapter = netdev_priv(netdev);
6491 
6492 	spin_lock(&adapter->stats64_lock);
6493 	igb_update_stats(adapter);
6494 	memcpy(stats, &adapter->stats64, sizeof(*stats));
6495 	spin_unlock(&adapter->stats64_lock);
6496 }
6497 
6498 /**
6499  *  igb_change_mtu - Change the Maximum Transfer Unit
6500  *  @netdev: network interface device structure
6501  *  @new_mtu: new value for maximum frame size
6502  *
6503  *  Returns 0 on success, negative on failure
6504  **/
6505 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6506 {
6507 	struct igb_adapter *adapter = netdev_priv(netdev);
6508 	int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6509 
6510 	if (adapter->xdp_prog) {
6511 		int i;
6512 
6513 		for (i = 0; i < adapter->num_rx_queues; i++) {
6514 			struct igb_ring *ring = adapter->rx_ring[i];
6515 
6516 			if (max_frame > igb_rx_bufsz(ring)) {
6517 				netdev_warn(adapter->netdev,
6518 					    "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6519 					    max_frame);
6520 				return -EINVAL;
6521 			}
6522 		}
6523 	}
6524 
6525 	/* adjust max frame to be at least the size of a standard frame */
6526 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6527 		max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6528 
6529 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6530 		usleep_range(1000, 2000);
6531 
6532 	/* igb_down has a dependency on max_frame_size */
6533 	adapter->max_frame_size = max_frame;
6534 
6535 	if (netif_running(netdev))
6536 		igb_down(adapter);
6537 
6538 	netdev_dbg(netdev, "changing MTU from %d to %d\n",
6539 		   netdev->mtu, new_mtu);
6540 	netdev->mtu = new_mtu;
6541 
6542 	if (netif_running(netdev))
6543 		igb_up(adapter);
6544 	else
6545 		igb_reset(adapter);
6546 
6547 	clear_bit(__IGB_RESETTING, &adapter->state);
6548 
6549 	return 0;
6550 }
6551 
6552 /**
6553  *  igb_update_stats - Update the board statistics counters
6554  *  @adapter: board private structure
6555  **/
6556 void igb_update_stats(struct igb_adapter *adapter)
6557 {
6558 	struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6559 	struct e1000_hw *hw = &adapter->hw;
6560 	struct pci_dev *pdev = adapter->pdev;
6561 	u32 reg, mpc;
6562 	int i;
6563 	u64 bytes, packets;
6564 	unsigned int start;
6565 	u64 _bytes, _packets;
6566 
6567 	/* Prevent stats update while adapter is being reset, or if the pci
6568 	 * connection is down.
6569 	 */
6570 	if (adapter->link_speed == 0)
6571 		return;
6572 	if (pci_channel_offline(pdev))
6573 		return;
6574 
6575 	bytes = 0;
6576 	packets = 0;
6577 
6578 	rcu_read_lock();
6579 	for (i = 0; i < adapter->num_rx_queues; i++) {
6580 		struct igb_ring *ring = adapter->rx_ring[i];
6581 		u32 rqdpc = rd32(E1000_RQDPC(i));
6582 		if (hw->mac.type >= e1000_i210)
6583 			wr32(E1000_RQDPC(i), 0);
6584 
6585 		if (rqdpc) {
6586 			ring->rx_stats.drops += rqdpc;
6587 			net_stats->rx_fifo_errors += rqdpc;
6588 		}
6589 
6590 		do {
6591 			start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6592 			_bytes = ring->rx_stats.bytes;
6593 			_packets = ring->rx_stats.packets;
6594 		} while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6595 		bytes += _bytes;
6596 		packets += _packets;
6597 	}
6598 
6599 	net_stats->rx_bytes = bytes;
6600 	net_stats->rx_packets = packets;
6601 
6602 	bytes = 0;
6603 	packets = 0;
6604 	for (i = 0; i < adapter->num_tx_queues; i++) {
6605 		struct igb_ring *ring = adapter->tx_ring[i];
6606 		do {
6607 			start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6608 			_bytes = ring->tx_stats.bytes;
6609 			_packets = ring->tx_stats.packets;
6610 		} while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6611 		bytes += _bytes;
6612 		packets += _packets;
6613 	}
6614 	net_stats->tx_bytes = bytes;
6615 	net_stats->tx_packets = packets;
6616 	rcu_read_unlock();
6617 
6618 	/* read stats registers */
6619 	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6620 	adapter->stats.gprc += rd32(E1000_GPRC);
6621 	adapter->stats.gorc += rd32(E1000_GORCL);
6622 	rd32(E1000_GORCH); /* clear GORCL */
6623 	adapter->stats.bprc += rd32(E1000_BPRC);
6624 	adapter->stats.mprc += rd32(E1000_MPRC);
6625 	adapter->stats.roc += rd32(E1000_ROC);
6626 
6627 	adapter->stats.prc64 += rd32(E1000_PRC64);
6628 	adapter->stats.prc127 += rd32(E1000_PRC127);
6629 	adapter->stats.prc255 += rd32(E1000_PRC255);
6630 	adapter->stats.prc511 += rd32(E1000_PRC511);
6631 	adapter->stats.prc1023 += rd32(E1000_PRC1023);
6632 	adapter->stats.prc1522 += rd32(E1000_PRC1522);
6633 	adapter->stats.symerrs += rd32(E1000_SYMERRS);
6634 	adapter->stats.sec += rd32(E1000_SEC);
6635 
6636 	mpc = rd32(E1000_MPC);
6637 	adapter->stats.mpc += mpc;
6638 	net_stats->rx_fifo_errors += mpc;
6639 	adapter->stats.scc += rd32(E1000_SCC);
6640 	adapter->stats.ecol += rd32(E1000_ECOL);
6641 	adapter->stats.mcc += rd32(E1000_MCC);
6642 	adapter->stats.latecol += rd32(E1000_LATECOL);
6643 	adapter->stats.dc += rd32(E1000_DC);
6644 	adapter->stats.rlec += rd32(E1000_RLEC);
6645 	adapter->stats.xonrxc += rd32(E1000_XONRXC);
6646 	adapter->stats.xontxc += rd32(E1000_XONTXC);
6647 	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6648 	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6649 	adapter->stats.fcruc += rd32(E1000_FCRUC);
6650 	adapter->stats.gptc += rd32(E1000_GPTC);
6651 	adapter->stats.gotc += rd32(E1000_GOTCL);
6652 	rd32(E1000_GOTCH); /* clear GOTCL */
6653 	adapter->stats.rnbc += rd32(E1000_RNBC);
6654 	adapter->stats.ruc += rd32(E1000_RUC);
6655 	adapter->stats.rfc += rd32(E1000_RFC);
6656 	adapter->stats.rjc += rd32(E1000_RJC);
6657 	adapter->stats.tor += rd32(E1000_TORH);
6658 	adapter->stats.tot += rd32(E1000_TOTH);
6659 	adapter->stats.tpr += rd32(E1000_TPR);
6660 
6661 	adapter->stats.ptc64 += rd32(E1000_PTC64);
6662 	adapter->stats.ptc127 += rd32(E1000_PTC127);
6663 	adapter->stats.ptc255 += rd32(E1000_PTC255);
6664 	adapter->stats.ptc511 += rd32(E1000_PTC511);
6665 	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6666 	adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6667 
6668 	adapter->stats.mptc += rd32(E1000_MPTC);
6669 	adapter->stats.bptc += rd32(E1000_BPTC);
6670 
6671 	adapter->stats.tpt += rd32(E1000_TPT);
6672 	adapter->stats.colc += rd32(E1000_COLC);
6673 
6674 	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6675 	/* read internal phy specific stats */
6676 	reg = rd32(E1000_CTRL_EXT);
6677 	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6678 		adapter->stats.rxerrc += rd32(E1000_RXERRC);
6679 
6680 		/* this stat has invalid values on i210/i211 */
6681 		if ((hw->mac.type != e1000_i210) &&
6682 		    (hw->mac.type != e1000_i211))
6683 			adapter->stats.tncrs += rd32(E1000_TNCRS);
6684 	}
6685 
6686 	adapter->stats.tsctc += rd32(E1000_TSCTC);
6687 	adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6688 
6689 	adapter->stats.iac += rd32(E1000_IAC);
6690 	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6691 	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6692 	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6693 	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6694 	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6695 	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6696 	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6697 	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6698 
6699 	/* Fill out the OS statistics structure */
6700 	net_stats->multicast = adapter->stats.mprc;
6701 	net_stats->collisions = adapter->stats.colc;
6702 
6703 	/* Rx Errors */
6704 
6705 	/* RLEC on some newer hardware can be incorrect so build
6706 	 * our own version based on RUC and ROC
6707 	 */
6708 	net_stats->rx_errors = adapter->stats.rxerrc +
6709 		adapter->stats.crcerrs + adapter->stats.algnerrc +
6710 		adapter->stats.ruc + adapter->stats.roc +
6711 		adapter->stats.cexterr;
6712 	net_stats->rx_length_errors = adapter->stats.ruc +
6713 				      adapter->stats.roc;
6714 	net_stats->rx_crc_errors = adapter->stats.crcerrs;
6715 	net_stats->rx_frame_errors = adapter->stats.algnerrc;
6716 	net_stats->rx_missed_errors = adapter->stats.mpc;
6717 
6718 	/* Tx Errors */
6719 	net_stats->tx_errors = adapter->stats.ecol +
6720 			       adapter->stats.latecol;
6721 	net_stats->tx_aborted_errors = adapter->stats.ecol;
6722 	net_stats->tx_window_errors = adapter->stats.latecol;
6723 	net_stats->tx_carrier_errors = adapter->stats.tncrs;
6724 
6725 	/* Tx Dropped needs to be maintained elsewhere */
6726 
6727 	/* Management Stats */
6728 	adapter->stats.mgptc += rd32(E1000_MGTPTC);
6729 	adapter->stats.mgprc += rd32(E1000_MGTPRC);
6730 	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6731 
6732 	/* OS2BMC Stats */
6733 	reg = rd32(E1000_MANC);
6734 	if (reg & E1000_MANC_EN_BMC2OS) {
6735 		adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6736 		adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6737 		adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6738 		adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6739 	}
6740 }
6741 
6742 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt)
6743 {
6744 	int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt);
6745 	struct e1000_hw *hw = &adapter->hw;
6746 	struct timespec64 ts;
6747 	u32 tsauxc;
6748 
6749 	if (pin < 0 || pin >= IGB_N_PEROUT)
6750 		return;
6751 
6752 	spin_lock(&adapter->tmreg_lock);
6753 
6754 	if (hw->mac.type == e1000_82580 ||
6755 	    hw->mac.type == e1000_i354 ||
6756 	    hw->mac.type == e1000_i350) {
6757 		s64 ns = timespec64_to_ns(&adapter->perout[pin].period);
6758 		u32 systiml, systimh, level_mask, level, rem;
6759 		u64 systim, now;
6760 
6761 		/* read systim registers in sequence */
6762 		rd32(E1000_SYSTIMR);
6763 		systiml = rd32(E1000_SYSTIML);
6764 		systimh = rd32(E1000_SYSTIMH);
6765 		systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
6766 		now = timecounter_cyc2time(&adapter->tc, systim);
6767 
6768 		if (pin < 2) {
6769 			level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000;
6770 			level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
6771 		} else {
6772 			level_mask = (tsintr_tt == 1) ? 0x80 : 0x40;
6773 			level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
6774 		}
6775 
6776 		div_u64_rem(now, ns, &rem);
6777 		systim = systim + (ns - rem);
6778 
6779 		/* synchronize pin level with rising/falling edges */
6780 		div_u64_rem(now, ns << 1, &rem);
6781 		if (rem < ns) {
6782 			/* first half of period */
6783 			if (level == 0) {
6784 				/* output is already low, skip this period */
6785 				systim += ns;
6786 				pr_notice("igb: periodic output on %s missed falling edge\n",
6787 					  adapter->sdp_config[pin].name);
6788 			}
6789 		} else {
6790 			/* second half of period */
6791 			if (level == 1) {
6792 				/* output is already high, skip this period */
6793 				systim += ns;
6794 				pr_notice("igb: periodic output on %s missed rising edge\n",
6795 					  adapter->sdp_config[pin].name);
6796 			}
6797 		}
6798 
6799 		/* for this chip family tv_sec is the upper part of the binary value,
6800 		 * so not seconds
6801 		 */
6802 		ts.tv_nsec = (u32)systim;
6803 		ts.tv_sec  = ((u32)(systim >> 32)) & 0xFF;
6804 	} else {
6805 		ts = timespec64_add(adapter->perout[pin].start,
6806 				    adapter->perout[pin].period);
6807 	}
6808 
6809 	/* u32 conversion of tv_sec is safe until y2106 */
6810 	wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
6811 	wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec);
6812 	tsauxc = rd32(E1000_TSAUXC);
6813 	tsauxc |= TSAUXC_EN_TT0;
6814 	wr32(E1000_TSAUXC, tsauxc);
6815 	adapter->perout[pin].start = ts;
6816 
6817 	spin_unlock(&adapter->tmreg_lock);
6818 }
6819 
6820 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt)
6821 {
6822 	int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt);
6823 	int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0;
6824 	int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0;
6825 	struct e1000_hw *hw = &adapter->hw;
6826 	struct ptp_clock_event event;
6827 	struct timespec64 ts;
6828 
6829 	if (pin < 0 || pin >= IGB_N_EXTTS)
6830 		return;
6831 
6832 	if (hw->mac.type == e1000_82580 ||
6833 	    hw->mac.type == e1000_i354 ||
6834 	    hw->mac.type == e1000_i350) {
6835 		s64 ns = rd32(auxstmpl);
6836 
6837 		ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32;
6838 		ts = ns_to_timespec64(ns);
6839 	} else {
6840 		ts.tv_nsec = rd32(auxstmpl);
6841 		ts.tv_sec  = rd32(auxstmph);
6842 	}
6843 
6844 	event.type = PTP_CLOCK_EXTTS;
6845 	event.index = tsintr_tt;
6846 	event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec;
6847 	ptp_clock_event(adapter->ptp_clock, &event);
6848 }
6849 
6850 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6851 {
6852 	struct e1000_hw *hw = &adapter->hw;
6853 	u32 ack = 0, tsicr = rd32(E1000_TSICR);
6854 	struct ptp_clock_event event;
6855 
6856 	if (tsicr & TSINTR_SYS_WRAP) {
6857 		event.type = PTP_CLOCK_PPS;
6858 		if (adapter->ptp_caps.pps)
6859 			ptp_clock_event(adapter->ptp_clock, &event);
6860 		ack |= TSINTR_SYS_WRAP;
6861 	}
6862 
6863 	if (tsicr & E1000_TSICR_TXTS) {
6864 		/* retrieve hardware timestamp */
6865 		schedule_work(&adapter->ptp_tx_work);
6866 		ack |= E1000_TSICR_TXTS;
6867 	}
6868 
6869 	if (tsicr & TSINTR_TT0) {
6870 		igb_perout(adapter, 0);
6871 		ack |= TSINTR_TT0;
6872 	}
6873 
6874 	if (tsicr & TSINTR_TT1) {
6875 		igb_perout(adapter, 1);
6876 		ack |= TSINTR_TT1;
6877 	}
6878 
6879 	if (tsicr & TSINTR_AUTT0) {
6880 		igb_extts(adapter, 0);
6881 		ack |= TSINTR_AUTT0;
6882 	}
6883 
6884 	if (tsicr & TSINTR_AUTT1) {
6885 		igb_extts(adapter, 1);
6886 		ack |= TSINTR_AUTT1;
6887 	}
6888 
6889 	/* acknowledge the interrupts */
6890 	wr32(E1000_TSICR, ack);
6891 }
6892 
6893 static irqreturn_t igb_msix_other(int irq, void *data)
6894 {
6895 	struct igb_adapter *adapter = data;
6896 	struct e1000_hw *hw = &adapter->hw;
6897 	u32 icr = rd32(E1000_ICR);
6898 	/* reading ICR causes bit 31 of EICR to be cleared */
6899 
6900 	if (icr & E1000_ICR_DRSTA)
6901 		schedule_work(&adapter->reset_task);
6902 
6903 	if (icr & E1000_ICR_DOUTSYNC) {
6904 		/* HW is reporting DMA is out of sync */
6905 		adapter->stats.doosync++;
6906 		/* The DMA Out of Sync is also indication of a spoof event
6907 		 * in IOV mode. Check the Wrong VM Behavior register to
6908 		 * see if it is really a spoof event.
6909 		 */
6910 		igb_check_wvbr(adapter);
6911 	}
6912 
6913 	/* Check for a mailbox event */
6914 	if (icr & E1000_ICR_VMMB)
6915 		igb_msg_task(adapter);
6916 
6917 	if (icr & E1000_ICR_LSC) {
6918 		hw->mac.get_link_status = 1;
6919 		/* guard against interrupt when we're going down */
6920 		if (!test_bit(__IGB_DOWN, &adapter->state))
6921 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
6922 	}
6923 
6924 	if (icr & E1000_ICR_TS)
6925 		igb_tsync_interrupt(adapter);
6926 
6927 	wr32(E1000_EIMS, adapter->eims_other);
6928 
6929 	return IRQ_HANDLED;
6930 }
6931 
6932 static void igb_write_itr(struct igb_q_vector *q_vector)
6933 {
6934 	struct igb_adapter *adapter = q_vector->adapter;
6935 	u32 itr_val = q_vector->itr_val & 0x7FFC;
6936 
6937 	if (!q_vector->set_itr)
6938 		return;
6939 
6940 	if (!itr_val)
6941 		itr_val = 0x4;
6942 
6943 	if (adapter->hw.mac.type == e1000_82575)
6944 		itr_val |= itr_val << 16;
6945 	else
6946 		itr_val |= E1000_EITR_CNT_IGNR;
6947 
6948 	writel(itr_val, q_vector->itr_register);
6949 	q_vector->set_itr = 0;
6950 }
6951 
6952 static irqreturn_t igb_msix_ring(int irq, void *data)
6953 {
6954 	struct igb_q_vector *q_vector = data;
6955 
6956 	/* Write the ITR value calculated from the previous interrupt. */
6957 	igb_write_itr(q_vector);
6958 
6959 	napi_schedule(&q_vector->napi);
6960 
6961 	return IRQ_HANDLED;
6962 }
6963 
6964 #ifdef CONFIG_IGB_DCA
6965 static void igb_update_tx_dca(struct igb_adapter *adapter,
6966 			      struct igb_ring *tx_ring,
6967 			      int cpu)
6968 {
6969 	struct e1000_hw *hw = &adapter->hw;
6970 	u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6971 
6972 	if (hw->mac.type != e1000_82575)
6973 		txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6974 
6975 	/* We can enable relaxed ordering for reads, but not writes when
6976 	 * DCA is enabled.  This is due to a known issue in some chipsets
6977 	 * which will cause the DCA tag to be cleared.
6978 	 */
6979 	txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6980 		  E1000_DCA_TXCTRL_DATA_RRO_EN |
6981 		  E1000_DCA_TXCTRL_DESC_DCA_EN;
6982 
6983 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6984 }
6985 
6986 static void igb_update_rx_dca(struct igb_adapter *adapter,
6987 			      struct igb_ring *rx_ring,
6988 			      int cpu)
6989 {
6990 	struct e1000_hw *hw = &adapter->hw;
6991 	u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6992 
6993 	if (hw->mac.type != e1000_82575)
6994 		rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6995 
6996 	/* We can enable relaxed ordering for reads, but not writes when
6997 	 * DCA is enabled.  This is due to a known issue in some chipsets
6998 	 * which will cause the DCA tag to be cleared.
6999 	 */
7000 	rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
7001 		  E1000_DCA_RXCTRL_DESC_DCA_EN;
7002 
7003 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
7004 }
7005 
7006 static void igb_update_dca(struct igb_q_vector *q_vector)
7007 {
7008 	struct igb_adapter *adapter = q_vector->adapter;
7009 	int cpu = get_cpu();
7010 
7011 	if (q_vector->cpu == cpu)
7012 		goto out_no_update;
7013 
7014 	if (q_vector->tx.ring)
7015 		igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
7016 
7017 	if (q_vector->rx.ring)
7018 		igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
7019 
7020 	q_vector->cpu = cpu;
7021 out_no_update:
7022 	put_cpu();
7023 }
7024 
7025 static void igb_setup_dca(struct igb_adapter *adapter)
7026 {
7027 	struct e1000_hw *hw = &adapter->hw;
7028 	int i;
7029 
7030 	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
7031 		return;
7032 
7033 	/* Always use CB2 mode, difference is masked in the CB driver. */
7034 	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
7035 
7036 	for (i = 0; i < adapter->num_q_vectors; i++) {
7037 		adapter->q_vector[i]->cpu = -1;
7038 		igb_update_dca(adapter->q_vector[i]);
7039 	}
7040 }
7041 
7042 static int __igb_notify_dca(struct device *dev, void *data)
7043 {
7044 	struct net_device *netdev = dev_get_drvdata(dev);
7045 	struct igb_adapter *adapter = netdev_priv(netdev);
7046 	struct pci_dev *pdev = adapter->pdev;
7047 	struct e1000_hw *hw = &adapter->hw;
7048 	unsigned long event = *(unsigned long *)data;
7049 
7050 	switch (event) {
7051 	case DCA_PROVIDER_ADD:
7052 		/* if already enabled, don't do it again */
7053 		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
7054 			break;
7055 		if (dca_add_requester(dev) == 0) {
7056 			adapter->flags |= IGB_FLAG_DCA_ENABLED;
7057 			dev_info(&pdev->dev, "DCA enabled\n");
7058 			igb_setup_dca(adapter);
7059 			break;
7060 		}
7061 		fallthrough; /* since DCA is disabled. */
7062 	case DCA_PROVIDER_REMOVE:
7063 		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
7064 			/* without this a class_device is left
7065 			 * hanging around in the sysfs model
7066 			 */
7067 			dca_remove_requester(dev);
7068 			dev_info(&pdev->dev, "DCA disabled\n");
7069 			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
7070 			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
7071 		}
7072 		break;
7073 	}
7074 
7075 	return 0;
7076 }
7077 
7078 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
7079 			  void *p)
7080 {
7081 	int ret_val;
7082 
7083 	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7084 					 __igb_notify_dca);
7085 
7086 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7087 }
7088 #endif /* CONFIG_IGB_DCA */
7089 
7090 #ifdef CONFIG_PCI_IOV
7091 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7092 {
7093 	unsigned char mac_addr[ETH_ALEN];
7094 
7095 	eth_zero_addr(mac_addr);
7096 	igb_set_vf_mac(adapter, vf, mac_addr);
7097 
7098 	/* By default spoof check is enabled for all VFs */
7099 	adapter->vf_data[vf].spoofchk_enabled = true;
7100 
7101 	/* By default VFs are not trusted */
7102 	adapter->vf_data[vf].trusted = false;
7103 
7104 	return 0;
7105 }
7106 
7107 #endif
7108 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7109 {
7110 	struct e1000_hw *hw = &adapter->hw;
7111 	u32 ping;
7112 	int i;
7113 
7114 	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7115 		ping = E1000_PF_CONTROL_MSG;
7116 		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7117 			ping |= E1000_VT_MSGTYPE_CTS;
7118 		igb_write_mbx(hw, &ping, 1, i);
7119 	}
7120 }
7121 
7122 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7123 {
7124 	struct e1000_hw *hw = &adapter->hw;
7125 	u32 vmolr = rd32(E1000_VMOLR(vf));
7126 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7127 
7128 	vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7129 			    IGB_VF_FLAG_MULTI_PROMISC);
7130 	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7131 
7132 	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7133 		vmolr |= E1000_VMOLR_MPME;
7134 		vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7135 		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7136 	} else {
7137 		/* if we have hashes and we are clearing a multicast promisc
7138 		 * flag we need to write the hashes to the MTA as this step
7139 		 * was previously skipped
7140 		 */
7141 		if (vf_data->num_vf_mc_hashes > 30) {
7142 			vmolr |= E1000_VMOLR_MPME;
7143 		} else if (vf_data->num_vf_mc_hashes) {
7144 			int j;
7145 
7146 			vmolr |= E1000_VMOLR_ROMPE;
7147 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7148 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7149 		}
7150 	}
7151 
7152 	wr32(E1000_VMOLR(vf), vmolr);
7153 
7154 	/* there are flags left unprocessed, likely not supported */
7155 	if (*msgbuf & E1000_VT_MSGINFO_MASK)
7156 		return -EINVAL;
7157 
7158 	return 0;
7159 }
7160 
7161 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7162 				  u32 *msgbuf, u32 vf)
7163 {
7164 	int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7165 	u16 *hash_list = (u16 *)&msgbuf[1];
7166 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7167 	int i;
7168 
7169 	/* salt away the number of multicast addresses assigned
7170 	 * to this VF for later use to restore when the PF multi cast
7171 	 * list changes
7172 	 */
7173 	vf_data->num_vf_mc_hashes = n;
7174 
7175 	/* only up to 30 hash values supported */
7176 	if (n > 30)
7177 		n = 30;
7178 
7179 	/* store the hashes for later use */
7180 	for (i = 0; i < n; i++)
7181 		vf_data->vf_mc_hashes[i] = hash_list[i];
7182 
7183 	/* Flush and reset the mta with the new values */
7184 	igb_set_rx_mode(adapter->netdev);
7185 
7186 	return 0;
7187 }
7188 
7189 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7190 {
7191 	struct e1000_hw *hw = &adapter->hw;
7192 	struct vf_data_storage *vf_data;
7193 	int i, j;
7194 
7195 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
7196 		u32 vmolr = rd32(E1000_VMOLR(i));
7197 
7198 		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7199 
7200 		vf_data = &adapter->vf_data[i];
7201 
7202 		if ((vf_data->num_vf_mc_hashes > 30) ||
7203 		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7204 			vmolr |= E1000_VMOLR_MPME;
7205 		} else if (vf_data->num_vf_mc_hashes) {
7206 			vmolr |= E1000_VMOLR_ROMPE;
7207 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7208 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7209 		}
7210 		wr32(E1000_VMOLR(i), vmolr);
7211 	}
7212 }
7213 
7214 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7215 {
7216 	struct e1000_hw *hw = &adapter->hw;
7217 	u32 pool_mask, vlvf_mask, i;
7218 
7219 	/* create mask for VF and other pools */
7220 	pool_mask = E1000_VLVF_POOLSEL_MASK;
7221 	vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7222 
7223 	/* drop PF from pool bits */
7224 	pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7225 			     adapter->vfs_allocated_count);
7226 
7227 	/* Find the vlan filter for this id */
7228 	for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7229 		u32 vlvf = rd32(E1000_VLVF(i));
7230 		u32 vfta_mask, vid, vfta;
7231 
7232 		/* remove the vf from the pool */
7233 		if (!(vlvf & vlvf_mask))
7234 			continue;
7235 
7236 		/* clear out bit from VLVF */
7237 		vlvf ^= vlvf_mask;
7238 
7239 		/* if other pools are present, just remove ourselves */
7240 		if (vlvf & pool_mask)
7241 			goto update_vlvfb;
7242 
7243 		/* if PF is present, leave VFTA */
7244 		if (vlvf & E1000_VLVF_POOLSEL_MASK)
7245 			goto update_vlvf;
7246 
7247 		vid = vlvf & E1000_VLVF_VLANID_MASK;
7248 		vfta_mask = BIT(vid % 32);
7249 
7250 		/* clear bit from VFTA */
7251 		vfta = adapter->shadow_vfta[vid / 32];
7252 		if (vfta & vfta_mask)
7253 			hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7254 update_vlvf:
7255 		/* clear pool selection enable */
7256 		if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7257 			vlvf &= E1000_VLVF_POOLSEL_MASK;
7258 		else
7259 			vlvf = 0;
7260 update_vlvfb:
7261 		/* clear pool bits */
7262 		wr32(E1000_VLVF(i), vlvf);
7263 	}
7264 }
7265 
7266 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7267 {
7268 	u32 vlvf;
7269 	int idx;
7270 
7271 	/* short cut the special case */
7272 	if (vlan == 0)
7273 		return 0;
7274 
7275 	/* Search for the VLAN id in the VLVF entries */
7276 	for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7277 		vlvf = rd32(E1000_VLVF(idx));
7278 		if ((vlvf & VLAN_VID_MASK) == vlan)
7279 			break;
7280 	}
7281 
7282 	return idx;
7283 }
7284 
7285 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7286 {
7287 	struct e1000_hw *hw = &adapter->hw;
7288 	u32 bits, pf_id;
7289 	int idx;
7290 
7291 	idx = igb_find_vlvf_entry(hw, vid);
7292 	if (!idx)
7293 		return;
7294 
7295 	/* See if any other pools are set for this VLAN filter
7296 	 * entry other than the PF.
7297 	 */
7298 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7299 	bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7300 	bits &= rd32(E1000_VLVF(idx));
7301 
7302 	/* Disable the filter so this falls into the default pool. */
7303 	if (!bits) {
7304 		if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7305 			wr32(E1000_VLVF(idx), BIT(pf_id));
7306 		else
7307 			wr32(E1000_VLVF(idx), 0);
7308 	}
7309 }
7310 
7311 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7312 			   bool add, u32 vf)
7313 {
7314 	int pf_id = adapter->vfs_allocated_count;
7315 	struct e1000_hw *hw = &adapter->hw;
7316 	int err;
7317 
7318 	/* If VLAN overlaps with one the PF is currently monitoring make
7319 	 * sure that we are able to allocate a VLVF entry.  This may be
7320 	 * redundant but it guarantees PF will maintain visibility to
7321 	 * the VLAN.
7322 	 */
7323 	if (add && test_bit(vid, adapter->active_vlans)) {
7324 		err = igb_vfta_set(hw, vid, pf_id, true, false);
7325 		if (err)
7326 			return err;
7327 	}
7328 
7329 	err = igb_vfta_set(hw, vid, vf, add, false);
7330 
7331 	if (add && !err)
7332 		return err;
7333 
7334 	/* If we failed to add the VF VLAN or we are removing the VF VLAN
7335 	 * we may need to drop the PF pool bit in order to allow us to free
7336 	 * up the VLVF resources.
7337 	 */
7338 	if (test_bit(vid, adapter->active_vlans) ||
7339 	    (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7340 		igb_update_pf_vlvf(adapter, vid);
7341 
7342 	return err;
7343 }
7344 
7345 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7346 {
7347 	struct e1000_hw *hw = &adapter->hw;
7348 
7349 	if (vid)
7350 		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7351 	else
7352 		wr32(E1000_VMVIR(vf), 0);
7353 }
7354 
7355 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7356 				u16 vlan, u8 qos)
7357 {
7358 	int err;
7359 
7360 	err = igb_set_vf_vlan(adapter, vlan, true, vf);
7361 	if (err)
7362 		return err;
7363 
7364 	igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7365 	igb_set_vmolr(adapter, vf, !vlan);
7366 
7367 	/* revoke access to previous VLAN */
7368 	if (vlan != adapter->vf_data[vf].pf_vlan)
7369 		igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7370 				false, vf);
7371 
7372 	adapter->vf_data[vf].pf_vlan = vlan;
7373 	adapter->vf_data[vf].pf_qos = qos;
7374 	igb_set_vf_vlan_strip(adapter, vf, true);
7375 	dev_info(&adapter->pdev->dev,
7376 		 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7377 	if (test_bit(__IGB_DOWN, &adapter->state)) {
7378 		dev_warn(&adapter->pdev->dev,
7379 			 "The VF VLAN has been set, but the PF device is not up.\n");
7380 		dev_warn(&adapter->pdev->dev,
7381 			 "Bring the PF device up before attempting to use the VF device.\n");
7382 	}
7383 
7384 	return err;
7385 }
7386 
7387 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7388 {
7389 	/* Restore tagless access via VLAN 0 */
7390 	igb_set_vf_vlan(adapter, 0, true, vf);
7391 
7392 	igb_set_vmvir(adapter, 0, vf);
7393 	igb_set_vmolr(adapter, vf, true);
7394 
7395 	/* Remove any PF assigned VLAN */
7396 	if (adapter->vf_data[vf].pf_vlan)
7397 		igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7398 				false, vf);
7399 
7400 	adapter->vf_data[vf].pf_vlan = 0;
7401 	adapter->vf_data[vf].pf_qos = 0;
7402 	igb_set_vf_vlan_strip(adapter, vf, false);
7403 
7404 	return 0;
7405 }
7406 
7407 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7408 			       u16 vlan, u8 qos, __be16 vlan_proto)
7409 {
7410 	struct igb_adapter *adapter = netdev_priv(netdev);
7411 
7412 	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7413 		return -EINVAL;
7414 
7415 	if (vlan_proto != htons(ETH_P_8021Q))
7416 		return -EPROTONOSUPPORT;
7417 
7418 	return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7419 			       igb_disable_port_vlan(adapter, vf);
7420 }
7421 
7422 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7423 {
7424 	int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7425 	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7426 	int ret;
7427 
7428 	if (adapter->vf_data[vf].pf_vlan)
7429 		return -1;
7430 
7431 	/* VLAN 0 is a special case, don't allow it to be removed */
7432 	if (!vid && !add)
7433 		return 0;
7434 
7435 	ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7436 	if (!ret)
7437 		igb_set_vf_vlan_strip(adapter, vf, !!vid);
7438 	return ret;
7439 }
7440 
7441 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7442 {
7443 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7444 
7445 	/* clear flags - except flag that indicates PF has set the MAC */
7446 	vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7447 	vf_data->last_nack = jiffies;
7448 
7449 	/* reset vlans for device */
7450 	igb_clear_vf_vfta(adapter, vf);
7451 	igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7452 	igb_set_vmvir(adapter, vf_data->pf_vlan |
7453 			       (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7454 	igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7455 	igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7456 
7457 	/* reset multicast table array for vf */
7458 	adapter->vf_data[vf].num_vf_mc_hashes = 0;
7459 
7460 	/* Flush and reset the mta with the new values */
7461 	igb_set_rx_mode(adapter->netdev);
7462 }
7463 
7464 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7465 {
7466 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7467 
7468 	/* clear mac address as we were hotplug removed/added */
7469 	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7470 		eth_zero_addr(vf_mac);
7471 
7472 	/* process remaining reset events */
7473 	igb_vf_reset(adapter, vf);
7474 }
7475 
7476 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7477 {
7478 	struct e1000_hw *hw = &adapter->hw;
7479 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7480 	u32 reg, msgbuf[3];
7481 	u8 *addr = (u8 *)(&msgbuf[1]);
7482 
7483 	/* process all the same items cleared in a function level reset */
7484 	igb_vf_reset(adapter, vf);
7485 
7486 	/* set vf mac address */
7487 	igb_set_vf_mac(adapter, vf, vf_mac);
7488 
7489 	/* enable transmit and receive for vf */
7490 	reg = rd32(E1000_VFTE);
7491 	wr32(E1000_VFTE, reg | BIT(vf));
7492 	reg = rd32(E1000_VFRE);
7493 	wr32(E1000_VFRE, reg | BIT(vf));
7494 
7495 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7496 
7497 	/* reply to reset with ack and vf mac address */
7498 	if (!is_zero_ether_addr(vf_mac)) {
7499 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7500 		memcpy(addr, vf_mac, ETH_ALEN);
7501 	} else {
7502 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7503 	}
7504 	igb_write_mbx(hw, msgbuf, 3, vf);
7505 }
7506 
7507 static void igb_flush_mac_table(struct igb_adapter *adapter)
7508 {
7509 	struct e1000_hw *hw = &adapter->hw;
7510 	int i;
7511 
7512 	for (i = 0; i < hw->mac.rar_entry_count; i++) {
7513 		adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7514 		eth_zero_addr(adapter->mac_table[i].addr);
7515 		adapter->mac_table[i].queue = 0;
7516 		igb_rar_set_index(adapter, i);
7517 	}
7518 }
7519 
7520 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7521 {
7522 	struct e1000_hw *hw = &adapter->hw;
7523 	/* do not count rar entries reserved for VFs MAC addresses */
7524 	int rar_entries = hw->mac.rar_entry_count -
7525 			  adapter->vfs_allocated_count;
7526 	int i, count = 0;
7527 
7528 	for (i = 0; i < rar_entries; i++) {
7529 		/* do not count default entries */
7530 		if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7531 			continue;
7532 
7533 		/* do not count "in use" entries for different queues */
7534 		if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7535 		    (adapter->mac_table[i].queue != queue))
7536 			continue;
7537 
7538 		count++;
7539 	}
7540 
7541 	return count;
7542 }
7543 
7544 /* Set default MAC address for the PF in the first RAR entry */
7545 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7546 {
7547 	struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7548 
7549 	ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7550 	mac_table->queue = adapter->vfs_allocated_count;
7551 	mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7552 
7553 	igb_rar_set_index(adapter, 0);
7554 }
7555 
7556 /* If the filter to be added and an already existing filter express
7557  * the same address and address type, it should be possible to only
7558  * override the other configurations, for example the queue to steer
7559  * traffic.
7560  */
7561 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7562 				      const u8 *addr, const u8 flags)
7563 {
7564 	if (!(entry->state & IGB_MAC_STATE_IN_USE))
7565 		return true;
7566 
7567 	if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7568 	    (flags & IGB_MAC_STATE_SRC_ADDR))
7569 		return false;
7570 
7571 	if (!ether_addr_equal(addr, entry->addr))
7572 		return false;
7573 
7574 	return true;
7575 }
7576 
7577 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7578  * 'flags' is used to indicate what kind of match is made, match is by
7579  * default for the destination address, if matching by source address
7580  * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7581  */
7582 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7583 				    const u8 *addr, const u8 queue,
7584 				    const u8 flags)
7585 {
7586 	struct e1000_hw *hw = &adapter->hw;
7587 	int rar_entries = hw->mac.rar_entry_count -
7588 			  adapter->vfs_allocated_count;
7589 	int i;
7590 
7591 	if (is_zero_ether_addr(addr))
7592 		return -EINVAL;
7593 
7594 	/* Search for the first empty entry in the MAC table.
7595 	 * Do not touch entries at the end of the table reserved for the VF MAC
7596 	 * addresses.
7597 	 */
7598 	for (i = 0; i < rar_entries; i++) {
7599 		if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7600 					       addr, flags))
7601 			continue;
7602 
7603 		ether_addr_copy(adapter->mac_table[i].addr, addr);
7604 		adapter->mac_table[i].queue = queue;
7605 		adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7606 
7607 		igb_rar_set_index(adapter, i);
7608 		return i;
7609 	}
7610 
7611 	return -ENOSPC;
7612 }
7613 
7614 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7615 			      const u8 queue)
7616 {
7617 	return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7618 }
7619 
7620 /* Remove a MAC filter for 'addr' directing matching traffic to
7621  * 'queue', 'flags' is used to indicate what kind of match need to be
7622  * removed, match is by default for the destination address, if
7623  * matching by source address is to be removed the flag
7624  * IGB_MAC_STATE_SRC_ADDR can be used.
7625  */
7626 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7627 				    const u8 *addr, const u8 queue,
7628 				    const u8 flags)
7629 {
7630 	struct e1000_hw *hw = &adapter->hw;
7631 	int rar_entries = hw->mac.rar_entry_count -
7632 			  adapter->vfs_allocated_count;
7633 	int i;
7634 
7635 	if (is_zero_ether_addr(addr))
7636 		return -EINVAL;
7637 
7638 	/* Search for matching entry in the MAC table based on given address
7639 	 * and queue. Do not touch entries at the end of the table reserved
7640 	 * for the VF MAC addresses.
7641 	 */
7642 	for (i = 0; i < rar_entries; i++) {
7643 		if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7644 			continue;
7645 		if ((adapter->mac_table[i].state & flags) != flags)
7646 			continue;
7647 		if (adapter->mac_table[i].queue != queue)
7648 			continue;
7649 		if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7650 			continue;
7651 
7652 		/* When a filter for the default address is "deleted",
7653 		 * we return it to its initial configuration
7654 		 */
7655 		if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7656 			adapter->mac_table[i].state =
7657 				IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7658 			adapter->mac_table[i].queue =
7659 				adapter->vfs_allocated_count;
7660 		} else {
7661 			adapter->mac_table[i].state = 0;
7662 			adapter->mac_table[i].queue = 0;
7663 			eth_zero_addr(adapter->mac_table[i].addr);
7664 		}
7665 
7666 		igb_rar_set_index(adapter, i);
7667 		return 0;
7668 	}
7669 
7670 	return -ENOENT;
7671 }
7672 
7673 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7674 			      const u8 queue)
7675 {
7676 	return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7677 }
7678 
7679 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7680 				const u8 *addr, u8 queue, u8 flags)
7681 {
7682 	struct e1000_hw *hw = &adapter->hw;
7683 
7684 	/* In theory, this should be supported on 82575 as well, but
7685 	 * that part wasn't easily accessible during development.
7686 	 */
7687 	if (hw->mac.type != e1000_i210)
7688 		return -EOPNOTSUPP;
7689 
7690 	return igb_add_mac_filter_flags(adapter, addr, queue,
7691 					IGB_MAC_STATE_QUEUE_STEERING | flags);
7692 }
7693 
7694 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7695 				const u8 *addr, u8 queue, u8 flags)
7696 {
7697 	return igb_del_mac_filter_flags(adapter, addr, queue,
7698 					IGB_MAC_STATE_QUEUE_STEERING | flags);
7699 }
7700 
7701 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7702 {
7703 	struct igb_adapter *adapter = netdev_priv(netdev);
7704 	int ret;
7705 
7706 	ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7707 
7708 	return min_t(int, ret, 0);
7709 }
7710 
7711 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7712 {
7713 	struct igb_adapter *adapter = netdev_priv(netdev);
7714 
7715 	igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7716 
7717 	return 0;
7718 }
7719 
7720 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7721 				 const u32 info, const u8 *addr)
7722 {
7723 	struct pci_dev *pdev = adapter->pdev;
7724 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7725 	struct list_head *pos;
7726 	struct vf_mac_filter *entry = NULL;
7727 	int ret = 0;
7728 
7729 	if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7730 	    !vf_data->trusted) {
7731 		dev_warn(&pdev->dev,
7732 			 "VF %d requested MAC filter but is administratively denied\n",
7733 			  vf);
7734 		return -EINVAL;
7735 	}
7736 	if (!is_valid_ether_addr(addr)) {
7737 		dev_warn(&pdev->dev,
7738 			 "VF %d attempted to set invalid MAC filter\n",
7739 			  vf);
7740 		return -EINVAL;
7741 	}
7742 
7743 	switch (info) {
7744 	case E1000_VF_MAC_FILTER_CLR:
7745 		/* remove all unicast MAC filters related to the current VF */
7746 		list_for_each(pos, &adapter->vf_macs.l) {
7747 			entry = list_entry(pos, struct vf_mac_filter, l);
7748 			if (entry->vf == vf) {
7749 				entry->vf = -1;
7750 				entry->free = true;
7751 				igb_del_mac_filter(adapter, entry->vf_mac, vf);
7752 			}
7753 		}
7754 		break;
7755 	case E1000_VF_MAC_FILTER_ADD:
7756 		/* try to find empty slot in the list */
7757 		list_for_each(pos, &adapter->vf_macs.l) {
7758 			entry = list_entry(pos, struct vf_mac_filter, l);
7759 			if (entry->free)
7760 				break;
7761 		}
7762 
7763 		if (entry && entry->free) {
7764 			entry->free = false;
7765 			entry->vf = vf;
7766 			ether_addr_copy(entry->vf_mac, addr);
7767 
7768 			ret = igb_add_mac_filter(adapter, addr, vf);
7769 			ret = min_t(int, ret, 0);
7770 		} else {
7771 			ret = -ENOSPC;
7772 		}
7773 
7774 		if (ret == -ENOSPC)
7775 			dev_warn(&pdev->dev,
7776 				 "VF %d has requested MAC filter but there is no space for it\n",
7777 				 vf);
7778 		break;
7779 	default:
7780 		ret = -EINVAL;
7781 		break;
7782 	}
7783 
7784 	return ret;
7785 }
7786 
7787 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7788 {
7789 	struct pci_dev *pdev = adapter->pdev;
7790 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7791 	u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7792 
7793 	/* The VF MAC Address is stored in a packed array of bytes
7794 	 * starting at the second 32 bit word of the msg array
7795 	 */
7796 	unsigned char *addr = (unsigned char *)&msg[1];
7797 	int ret = 0;
7798 
7799 	if (!info) {
7800 		if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7801 		    !vf_data->trusted) {
7802 			dev_warn(&pdev->dev,
7803 				 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7804 				 vf);
7805 			return -EINVAL;
7806 		}
7807 
7808 		if (!is_valid_ether_addr(addr)) {
7809 			dev_warn(&pdev->dev,
7810 				 "VF %d attempted to set invalid MAC\n",
7811 				 vf);
7812 			return -EINVAL;
7813 		}
7814 
7815 		ret = igb_set_vf_mac(adapter, vf, addr);
7816 	} else {
7817 		ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7818 	}
7819 
7820 	return ret;
7821 }
7822 
7823 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7824 {
7825 	struct e1000_hw *hw = &adapter->hw;
7826 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7827 	u32 msg = E1000_VT_MSGTYPE_NACK;
7828 
7829 	/* if device isn't clear to send it shouldn't be reading either */
7830 	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7831 	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7832 		igb_write_mbx(hw, &msg, 1, vf);
7833 		vf_data->last_nack = jiffies;
7834 	}
7835 }
7836 
7837 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7838 {
7839 	struct pci_dev *pdev = adapter->pdev;
7840 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
7841 	struct e1000_hw *hw = &adapter->hw;
7842 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7843 	s32 retval;
7844 
7845 	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7846 
7847 	if (retval) {
7848 		/* if receive failed revoke VF CTS stats and restart init */
7849 		dev_err(&pdev->dev, "Error receiving message from VF\n");
7850 		vf_data->flags &= ~IGB_VF_FLAG_CTS;
7851 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7852 			goto unlock;
7853 		goto out;
7854 	}
7855 
7856 	/* this is a message we already processed, do nothing */
7857 	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7858 		goto unlock;
7859 
7860 	/* until the vf completes a reset it should not be
7861 	 * allowed to start any configuration.
7862 	 */
7863 	if (msgbuf[0] == E1000_VF_RESET) {
7864 		/* unlocks mailbox */
7865 		igb_vf_reset_msg(adapter, vf);
7866 		return;
7867 	}
7868 
7869 	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7870 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7871 			goto unlock;
7872 		retval = -1;
7873 		goto out;
7874 	}
7875 
7876 	switch ((msgbuf[0] & 0xFFFF)) {
7877 	case E1000_VF_SET_MAC_ADDR:
7878 		retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7879 		break;
7880 	case E1000_VF_SET_PROMISC:
7881 		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7882 		break;
7883 	case E1000_VF_SET_MULTICAST:
7884 		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7885 		break;
7886 	case E1000_VF_SET_LPE:
7887 		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7888 		break;
7889 	case E1000_VF_SET_VLAN:
7890 		retval = -1;
7891 		if (vf_data->pf_vlan)
7892 			dev_warn(&pdev->dev,
7893 				 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7894 				 vf);
7895 		else
7896 			retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7897 		break;
7898 	default:
7899 		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7900 		retval = -1;
7901 		break;
7902 	}
7903 
7904 	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7905 out:
7906 	/* notify the VF of the results of what it sent us */
7907 	if (retval)
7908 		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7909 	else
7910 		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7911 
7912 	/* unlocks mailbox */
7913 	igb_write_mbx(hw, msgbuf, 1, vf);
7914 	return;
7915 
7916 unlock:
7917 	igb_unlock_mbx(hw, vf);
7918 }
7919 
7920 static void igb_msg_task(struct igb_adapter *adapter)
7921 {
7922 	struct e1000_hw *hw = &adapter->hw;
7923 	u32 vf;
7924 
7925 	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7926 		/* process any reset requests */
7927 		if (!igb_check_for_rst(hw, vf))
7928 			igb_vf_reset_event(adapter, vf);
7929 
7930 		/* process any messages pending */
7931 		if (!igb_check_for_msg(hw, vf))
7932 			igb_rcv_msg_from_vf(adapter, vf);
7933 
7934 		/* process any acks */
7935 		if (!igb_check_for_ack(hw, vf))
7936 			igb_rcv_ack_from_vf(adapter, vf);
7937 	}
7938 }
7939 
7940 /**
7941  *  igb_set_uta - Set unicast filter table address
7942  *  @adapter: board private structure
7943  *  @set: boolean indicating if we are setting or clearing bits
7944  *
7945  *  The unicast table address is a register array of 32-bit registers.
7946  *  The table is meant to be used in a way similar to how the MTA is used
7947  *  however due to certain limitations in the hardware it is necessary to
7948  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7949  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
7950  **/
7951 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7952 {
7953 	struct e1000_hw *hw = &adapter->hw;
7954 	u32 uta = set ? ~0 : 0;
7955 	int i;
7956 
7957 	/* we only need to do this if VMDq is enabled */
7958 	if (!adapter->vfs_allocated_count)
7959 		return;
7960 
7961 	for (i = hw->mac.uta_reg_count; i--;)
7962 		array_wr32(E1000_UTA, i, uta);
7963 }
7964 
7965 /**
7966  *  igb_intr_msi - Interrupt Handler
7967  *  @irq: interrupt number
7968  *  @data: pointer to a network interface device structure
7969  **/
7970 static irqreturn_t igb_intr_msi(int irq, void *data)
7971 {
7972 	struct igb_adapter *adapter = data;
7973 	struct igb_q_vector *q_vector = adapter->q_vector[0];
7974 	struct e1000_hw *hw = &adapter->hw;
7975 	/* read ICR disables interrupts using IAM */
7976 	u32 icr = rd32(E1000_ICR);
7977 
7978 	igb_write_itr(q_vector);
7979 
7980 	if (icr & E1000_ICR_DRSTA)
7981 		schedule_work(&adapter->reset_task);
7982 
7983 	if (icr & E1000_ICR_DOUTSYNC) {
7984 		/* HW is reporting DMA is out of sync */
7985 		adapter->stats.doosync++;
7986 	}
7987 
7988 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7989 		hw->mac.get_link_status = 1;
7990 		if (!test_bit(__IGB_DOWN, &adapter->state))
7991 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
7992 	}
7993 
7994 	if (icr & E1000_ICR_TS)
7995 		igb_tsync_interrupt(adapter);
7996 
7997 	napi_schedule(&q_vector->napi);
7998 
7999 	return IRQ_HANDLED;
8000 }
8001 
8002 /**
8003  *  igb_intr - Legacy Interrupt Handler
8004  *  @irq: interrupt number
8005  *  @data: pointer to a network interface device structure
8006  **/
8007 static irqreturn_t igb_intr(int irq, void *data)
8008 {
8009 	struct igb_adapter *adapter = data;
8010 	struct igb_q_vector *q_vector = adapter->q_vector[0];
8011 	struct e1000_hw *hw = &adapter->hw;
8012 	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
8013 	 * need for the IMC write
8014 	 */
8015 	u32 icr = rd32(E1000_ICR);
8016 
8017 	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
8018 	 * not set, then the adapter didn't send an interrupt
8019 	 */
8020 	if (!(icr & E1000_ICR_INT_ASSERTED))
8021 		return IRQ_NONE;
8022 
8023 	igb_write_itr(q_vector);
8024 
8025 	if (icr & E1000_ICR_DRSTA)
8026 		schedule_work(&adapter->reset_task);
8027 
8028 	if (icr & E1000_ICR_DOUTSYNC) {
8029 		/* HW is reporting DMA is out of sync */
8030 		adapter->stats.doosync++;
8031 	}
8032 
8033 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8034 		hw->mac.get_link_status = 1;
8035 		/* guard against interrupt when we're going down */
8036 		if (!test_bit(__IGB_DOWN, &adapter->state))
8037 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
8038 	}
8039 
8040 	if (icr & E1000_ICR_TS)
8041 		igb_tsync_interrupt(adapter);
8042 
8043 	napi_schedule(&q_vector->napi);
8044 
8045 	return IRQ_HANDLED;
8046 }
8047 
8048 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
8049 {
8050 	struct igb_adapter *adapter = q_vector->adapter;
8051 	struct e1000_hw *hw = &adapter->hw;
8052 
8053 	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
8054 	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
8055 		if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
8056 			igb_set_itr(q_vector);
8057 		else
8058 			igb_update_ring_itr(q_vector);
8059 	}
8060 
8061 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
8062 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
8063 			wr32(E1000_EIMS, q_vector->eims_value);
8064 		else
8065 			igb_irq_enable(adapter);
8066 	}
8067 }
8068 
8069 /**
8070  *  igb_poll - NAPI Rx polling callback
8071  *  @napi: napi polling structure
8072  *  @budget: count of how many packets we should handle
8073  **/
8074 static int igb_poll(struct napi_struct *napi, int budget)
8075 {
8076 	struct igb_q_vector *q_vector = container_of(napi,
8077 						     struct igb_q_vector,
8078 						     napi);
8079 	bool clean_complete = true;
8080 	int work_done = 0;
8081 
8082 #ifdef CONFIG_IGB_DCA
8083 	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
8084 		igb_update_dca(q_vector);
8085 #endif
8086 	if (q_vector->tx.ring)
8087 		clean_complete = igb_clean_tx_irq(q_vector, budget);
8088 
8089 	if (q_vector->rx.ring) {
8090 		int cleaned = igb_clean_rx_irq(q_vector, budget);
8091 
8092 		work_done += cleaned;
8093 		if (cleaned >= budget)
8094 			clean_complete = false;
8095 	}
8096 
8097 	/* If all work not completed, return budget and keep polling */
8098 	if (!clean_complete)
8099 		return budget;
8100 
8101 	/* Exit the polling mode, but don't re-enable interrupts if stack might
8102 	 * poll us due to busy-polling
8103 	 */
8104 	if (likely(napi_complete_done(napi, work_done)))
8105 		igb_ring_irq_enable(q_vector);
8106 
8107 	return work_done;
8108 }
8109 
8110 /**
8111  *  igb_clean_tx_irq - Reclaim resources after transmit completes
8112  *  @q_vector: pointer to q_vector containing needed info
8113  *  @napi_budget: Used to determine if we are in netpoll
8114  *
8115  *  returns true if ring is completely cleaned
8116  **/
8117 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8118 {
8119 	struct igb_adapter *adapter = q_vector->adapter;
8120 	struct igb_ring *tx_ring = q_vector->tx.ring;
8121 	struct igb_tx_buffer *tx_buffer;
8122 	union e1000_adv_tx_desc *tx_desc;
8123 	unsigned int total_bytes = 0, total_packets = 0;
8124 	unsigned int budget = q_vector->tx.work_limit;
8125 	unsigned int i = tx_ring->next_to_clean;
8126 
8127 	if (test_bit(__IGB_DOWN, &adapter->state))
8128 		return true;
8129 
8130 	tx_buffer = &tx_ring->tx_buffer_info[i];
8131 	tx_desc = IGB_TX_DESC(tx_ring, i);
8132 	i -= tx_ring->count;
8133 
8134 	do {
8135 		union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8136 
8137 		/* if next_to_watch is not set then there is no work pending */
8138 		if (!eop_desc)
8139 			break;
8140 
8141 		/* prevent any other reads prior to eop_desc */
8142 		smp_rmb();
8143 
8144 		/* if DD is not set pending work has not been completed */
8145 		if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8146 			break;
8147 
8148 		/* clear next_to_watch to prevent false hangs */
8149 		tx_buffer->next_to_watch = NULL;
8150 
8151 		/* update the statistics for this packet */
8152 		total_bytes += tx_buffer->bytecount;
8153 		total_packets += tx_buffer->gso_segs;
8154 
8155 		/* free the skb */
8156 		if (tx_buffer->type == IGB_TYPE_SKB)
8157 			napi_consume_skb(tx_buffer->skb, napi_budget);
8158 		else
8159 			xdp_return_frame(tx_buffer->xdpf);
8160 
8161 		/* unmap skb header data */
8162 		dma_unmap_single(tx_ring->dev,
8163 				 dma_unmap_addr(tx_buffer, dma),
8164 				 dma_unmap_len(tx_buffer, len),
8165 				 DMA_TO_DEVICE);
8166 
8167 		/* clear tx_buffer data */
8168 		dma_unmap_len_set(tx_buffer, len, 0);
8169 
8170 		/* clear last DMA location and unmap remaining buffers */
8171 		while (tx_desc != eop_desc) {
8172 			tx_buffer++;
8173 			tx_desc++;
8174 			i++;
8175 			if (unlikely(!i)) {
8176 				i -= tx_ring->count;
8177 				tx_buffer = tx_ring->tx_buffer_info;
8178 				tx_desc = IGB_TX_DESC(tx_ring, 0);
8179 			}
8180 
8181 			/* unmap any remaining paged data */
8182 			if (dma_unmap_len(tx_buffer, len)) {
8183 				dma_unmap_page(tx_ring->dev,
8184 					       dma_unmap_addr(tx_buffer, dma),
8185 					       dma_unmap_len(tx_buffer, len),
8186 					       DMA_TO_DEVICE);
8187 				dma_unmap_len_set(tx_buffer, len, 0);
8188 			}
8189 		}
8190 
8191 		/* move us one more past the eop_desc for start of next pkt */
8192 		tx_buffer++;
8193 		tx_desc++;
8194 		i++;
8195 		if (unlikely(!i)) {
8196 			i -= tx_ring->count;
8197 			tx_buffer = tx_ring->tx_buffer_info;
8198 			tx_desc = IGB_TX_DESC(tx_ring, 0);
8199 		}
8200 
8201 		/* issue prefetch for next Tx descriptor */
8202 		prefetch(tx_desc);
8203 
8204 		/* update budget accounting */
8205 		budget--;
8206 	} while (likely(budget));
8207 
8208 	netdev_tx_completed_queue(txring_txq(tx_ring),
8209 				  total_packets, total_bytes);
8210 	i += tx_ring->count;
8211 	tx_ring->next_to_clean = i;
8212 	u64_stats_update_begin(&tx_ring->tx_syncp);
8213 	tx_ring->tx_stats.bytes += total_bytes;
8214 	tx_ring->tx_stats.packets += total_packets;
8215 	u64_stats_update_end(&tx_ring->tx_syncp);
8216 	q_vector->tx.total_bytes += total_bytes;
8217 	q_vector->tx.total_packets += total_packets;
8218 
8219 	if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8220 		struct e1000_hw *hw = &adapter->hw;
8221 
8222 		/* Detect a transmit hang in hardware, this serializes the
8223 		 * check with the clearing of time_stamp and movement of i
8224 		 */
8225 		clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8226 		if (tx_buffer->next_to_watch &&
8227 		    time_after(jiffies, tx_buffer->time_stamp +
8228 			       (adapter->tx_timeout_factor * HZ)) &&
8229 		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8230 
8231 			/* detected Tx unit hang */
8232 			dev_err(tx_ring->dev,
8233 				"Detected Tx Unit Hang\n"
8234 				"  Tx Queue             <%d>\n"
8235 				"  TDH                  <%x>\n"
8236 				"  TDT                  <%x>\n"
8237 				"  next_to_use          <%x>\n"
8238 				"  next_to_clean        <%x>\n"
8239 				"buffer_info[next_to_clean]\n"
8240 				"  time_stamp           <%lx>\n"
8241 				"  next_to_watch        <%p>\n"
8242 				"  jiffies              <%lx>\n"
8243 				"  desc.status          <%x>\n",
8244 				tx_ring->queue_index,
8245 				rd32(E1000_TDH(tx_ring->reg_idx)),
8246 				readl(tx_ring->tail),
8247 				tx_ring->next_to_use,
8248 				tx_ring->next_to_clean,
8249 				tx_buffer->time_stamp,
8250 				tx_buffer->next_to_watch,
8251 				jiffies,
8252 				tx_buffer->next_to_watch->wb.status);
8253 			netif_stop_subqueue(tx_ring->netdev,
8254 					    tx_ring->queue_index);
8255 
8256 			/* we are about to reset, no point in enabling stuff */
8257 			return true;
8258 		}
8259 	}
8260 
8261 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8262 	if (unlikely(total_packets &&
8263 	    netif_carrier_ok(tx_ring->netdev) &&
8264 	    igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8265 		/* Make sure that anybody stopping the queue after this
8266 		 * sees the new next_to_clean.
8267 		 */
8268 		smp_mb();
8269 		if (__netif_subqueue_stopped(tx_ring->netdev,
8270 					     tx_ring->queue_index) &&
8271 		    !(test_bit(__IGB_DOWN, &adapter->state))) {
8272 			netif_wake_subqueue(tx_ring->netdev,
8273 					    tx_ring->queue_index);
8274 
8275 			u64_stats_update_begin(&tx_ring->tx_syncp);
8276 			tx_ring->tx_stats.restart_queue++;
8277 			u64_stats_update_end(&tx_ring->tx_syncp);
8278 		}
8279 	}
8280 
8281 	return !!budget;
8282 }
8283 
8284 /**
8285  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
8286  *  @rx_ring: rx descriptor ring to store buffers on
8287  *  @old_buff: donor buffer to have page reused
8288  *
8289  *  Synchronizes page for reuse by the adapter
8290  **/
8291 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8292 			      struct igb_rx_buffer *old_buff)
8293 {
8294 	struct igb_rx_buffer *new_buff;
8295 	u16 nta = rx_ring->next_to_alloc;
8296 
8297 	new_buff = &rx_ring->rx_buffer_info[nta];
8298 
8299 	/* update, and store next to alloc */
8300 	nta++;
8301 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8302 
8303 	/* Transfer page from old buffer to new buffer.
8304 	 * Move each member individually to avoid possible store
8305 	 * forwarding stalls.
8306 	 */
8307 	new_buff->dma		= old_buff->dma;
8308 	new_buff->page		= old_buff->page;
8309 	new_buff->page_offset	= old_buff->page_offset;
8310 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
8311 }
8312 
8313 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8314 				  int rx_buf_pgcnt)
8315 {
8316 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8317 	struct page *page = rx_buffer->page;
8318 
8319 	/* avoid re-using remote and pfmemalloc pages */
8320 	if (!dev_page_is_reusable(page))
8321 		return false;
8322 
8323 #if (PAGE_SIZE < 8192)
8324 	/* if we are only owner of page we can reuse it */
8325 	if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8326 		return false;
8327 #else
8328 #define IGB_LAST_OFFSET \
8329 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8330 
8331 	if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8332 		return false;
8333 #endif
8334 
8335 	/* If we have drained the page fragment pool we need to update
8336 	 * the pagecnt_bias and page count so that we fully restock the
8337 	 * number of references the driver holds.
8338 	 */
8339 	if (unlikely(pagecnt_bias == 1)) {
8340 		page_ref_add(page, USHRT_MAX - 1);
8341 		rx_buffer->pagecnt_bias = USHRT_MAX;
8342 	}
8343 
8344 	return true;
8345 }
8346 
8347 /**
8348  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8349  *  @rx_ring: rx descriptor ring to transact packets on
8350  *  @rx_buffer: buffer containing page to add
8351  *  @skb: sk_buff to place the data into
8352  *  @size: size of buffer to be added
8353  *
8354  *  This function will add the data contained in rx_buffer->page to the skb.
8355  **/
8356 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8357 			    struct igb_rx_buffer *rx_buffer,
8358 			    struct sk_buff *skb,
8359 			    unsigned int size)
8360 {
8361 #if (PAGE_SIZE < 8192)
8362 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8363 #else
8364 	unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8365 				SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8366 				SKB_DATA_ALIGN(size);
8367 #endif
8368 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8369 			rx_buffer->page_offset, size, truesize);
8370 #if (PAGE_SIZE < 8192)
8371 	rx_buffer->page_offset ^= truesize;
8372 #else
8373 	rx_buffer->page_offset += truesize;
8374 #endif
8375 }
8376 
8377 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8378 					 struct igb_rx_buffer *rx_buffer,
8379 					 struct xdp_buff *xdp,
8380 					 ktime_t timestamp)
8381 {
8382 #if (PAGE_SIZE < 8192)
8383 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8384 #else
8385 	unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8386 					       xdp->data_hard_start);
8387 #endif
8388 	unsigned int size = xdp->data_end - xdp->data;
8389 	unsigned int headlen;
8390 	struct sk_buff *skb;
8391 
8392 	/* prefetch first cache line of first page */
8393 	net_prefetch(xdp->data);
8394 
8395 	/* allocate a skb to store the frags */
8396 	skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8397 	if (unlikely(!skb))
8398 		return NULL;
8399 
8400 	if (timestamp)
8401 		skb_hwtstamps(skb)->hwtstamp = timestamp;
8402 
8403 	/* Determine available headroom for copy */
8404 	headlen = size;
8405 	if (headlen > IGB_RX_HDR_LEN)
8406 		headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8407 
8408 	/* align pull length to size of long to optimize memcpy performance */
8409 	memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8410 
8411 	/* update all of the pointers */
8412 	size -= headlen;
8413 	if (size) {
8414 		skb_add_rx_frag(skb, 0, rx_buffer->page,
8415 				(xdp->data + headlen) - page_address(rx_buffer->page),
8416 				size, truesize);
8417 #if (PAGE_SIZE < 8192)
8418 		rx_buffer->page_offset ^= truesize;
8419 #else
8420 		rx_buffer->page_offset += truesize;
8421 #endif
8422 	} else {
8423 		rx_buffer->pagecnt_bias++;
8424 	}
8425 
8426 	return skb;
8427 }
8428 
8429 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8430 				     struct igb_rx_buffer *rx_buffer,
8431 				     struct xdp_buff *xdp,
8432 				     ktime_t timestamp)
8433 {
8434 #if (PAGE_SIZE < 8192)
8435 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8436 #else
8437 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8438 				SKB_DATA_ALIGN(xdp->data_end -
8439 					       xdp->data_hard_start);
8440 #endif
8441 	unsigned int metasize = xdp->data - xdp->data_meta;
8442 	struct sk_buff *skb;
8443 
8444 	/* prefetch first cache line of first page */
8445 	net_prefetch(xdp->data_meta);
8446 
8447 	/* build an skb around the page buffer */
8448 	skb = napi_build_skb(xdp->data_hard_start, truesize);
8449 	if (unlikely(!skb))
8450 		return NULL;
8451 
8452 	/* update pointers within the skb to store the data */
8453 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
8454 	__skb_put(skb, xdp->data_end - xdp->data);
8455 
8456 	if (metasize)
8457 		skb_metadata_set(skb, metasize);
8458 
8459 	if (timestamp)
8460 		skb_hwtstamps(skb)->hwtstamp = timestamp;
8461 
8462 	/* update buffer offset */
8463 #if (PAGE_SIZE < 8192)
8464 	rx_buffer->page_offset ^= truesize;
8465 #else
8466 	rx_buffer->page_offset += truesize;
8467 #endif
8468 
8469 	return skb;
8470 }
8471 
8472 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8473 				   struct igb_ring *rx_ring,
8474 				   struct xdp_buff *xdp)
8475 {
8476 	int err, result = IGB_XDP_PASS;
8477 	struct bpf_prog *xdp_prog;
8478 	u32 act;
8479 
8480 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8481 
8482 	if (!xdp_prog)
8483 		goto xdp_out;
8484 
8485 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
8486 
8487 	act = bpf_prog_run_xdp(xdp_prog, xdp);
8488 	switch (act) {
8489 	case XDP_PASS:
8490 		break;
8491 	case XDP_TX:
8492 		result = igb_xdp_xmit_back(adapter, xdp);
8493 		if (result == IGB_XDP_CONSUMED)
8494 			goto out_failure;
8495 		break;
8496 	case XDP_REDIRECT:
8497 		err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8498 		if (err)
8499 			goto out_failure;
8500 		result = IGB_XDP_REDIR;
8501 		break;
8502 	default:
8503 		bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act);
8504 		fallthrough;
8505 	case XDP_ABORTED:
8506 out_failure:
8507 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8508 		fallthrough;
8509 	case XDP_DROP:
8510 		result = IGB_XDP_CONSUMED;
8511 		break;
8512 	}
8513 xdp_out:
8514 	return ERR_PTR(-result);
8515 }
8516 
8517 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8518 					  unsigned int size)
8519 {
8520 	unsigned int truesize;
8521 
8522 #if (PAGE_SIZE < 8192)
8523 	truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8524 #else
8525 	truesize = ring_uses_build_skb(rx_ring) ?
8526 		SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8527 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8528 		SKB_DATA_ALIGN(size);
8529 #endif
8530 	return truesize;
8531 }
8532 
8533 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8534 			       struct igb_rx_buffer *rx_buffer,
8535 			       unsigned int size)
8536 {
8537 	unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8538 #if (PAGE_SIZE < 8192)
8539 	rx_buffer->page_offset ^= truesize;
8540 #else
8541 	rx_buffer->page_offset += truesize;
8542 #endif
8543 }
8544 
8545 static inline void igb_rx_checksum(struct igb_ring *ring,
8546 				   union e1000_adv_rx_desc *rx_desc,
8547 				   struct sk_buff *skb)
8548 {
8549 	skb_checksum_none_assert(skb);
8550 
8551 	/* Ignore Checksum bit is set */
8552 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8553 		return;
8554 
8555 	/* Rx checksum disabled via ethtool */
8556 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
8557 		return;
8558 
8559 	/* TCP/UDP checksum error bit is set */
8560 	if (igb_test_staterr(rx_desc,
8561 			     E1000_RXDEXT_STATERR_TCPE |
8562 			     E1000_RXDEXT_STATERR_IPE)) {
8563 		/* work around errata with sctp packets where the TCPE aka
8564 		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8565 		 * packets, (aka let the stack check the crc32c)
8566 		 */
8567 		if (!((skb->len == 60) &&
8568 		      test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8569 			u64_stats_update_begin(&ring->rx_syncp);
8570 			ring->rx_stats.csum_err++;
8571 			u64_stats_update_end(&ring->rx_syncp);
8572 		}
8573 		/* let the stack verify checksum errors */
8574 		return;
8575 	}
8576 	/* It must be a TCP or UDP packet with a valid checksum */
8577 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8578 				      E1000_RXD_STAT_UDPCS))
8579 		skb->ip_summed = CHECKSUM_UNNECESSARY;
8580 
8581 	dev_dbg(ring->dev, "cksum success: bits %08X\n",
8582 		le32_to_cpu(rx_desc->wb.upper.status_error));
8583 }
8584 
8585 static inline void igb_rx_hash(struct igb_ring *ring,
8586 			       union e1000_adv_rx_desc *rx_desc,
8587 			       struct sk_buff *skb)
8588 {
8589 	if (ring->netdev->features & NETIF_F_RXHASH)
8590 		skb_set_hash(skb,
8591 			     le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8592 			     PKT_HASH_TYPE_L3);
8593 }
8594 
8595 /**
8596  *  igb_is_non_eop - process handling of non-EOP buffers
8597  *  @rx_ring: Rx ring being processed
8598  *  @rx_desc: Rx descriptor for current buffer
8599  *
8600  *  This function updates next to clean.  If the buffer is an EOP buffer
8601  *  this function exits returning false, otherwise it will place the
8602  *  sk_buff in the next buffer to be chained and return true indicating
8603  *  that this is in fact a non-EOP buffer.
8604  **/
8605 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8606 			   union e1000_adv_rx_desc *rx_desc)
8607 {
8608 	u32 ntc = rx_ring->next_to_clean + 1;
8609 
8610 	/* fetch, update, and store next to clean */
8611 	ntc = (ntc < rx_ring->count) ? ntc : 0;
8612 	rx_ring->next_to_clean = ntc;
8613 
8614 	prefetch(IGB_RX_DESC(rx_ring, ntc));
8615 
8616 	if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8617 		return false;
8618 
8619 	return true;
8620 }
8621 
8622 /**
8623  *  igb_cleanup_headers - Correct corrupted or empty headers
8624  *  @rx_ring: rx descriptor ring packet is being transacted on
8625  *  @rx_desc: pointer to the EOP Rx descriptor
8626  *  @skb: pointer to current skb being fixed
8627  *
8628  *  Address the case where we are pulling data in on pages only
8629  *  and as such no data is present in the skb header.
8630  *
8631  *  In addition if skb is not at least 60 bytes we need to pad it so that
8632  *  it is large enough to qualify as a valid Ethernet frame.
8633  *
8634  *  Returns true if an error was encountered and skb was freed.
8635  **/
8636 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8637 				union e1000_adv_rx_desc *rx_desc,
8638 				struct sk_buff *skb)
8639 {
8640 	/* XDP packets use error pointer so abort at this point */
8641 	if (IS_ERR(skb))
8642 		return true;
8643 
8644 	if (unlikely((igb_test_staterr(rx_desc,
8645 				       E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8646 		struct net_device *netdev = rx_ring->netdev;
8647 		if (!(netdev->features & NETIF_F_RXALL)) {
8648 			dev_kfree_skb_any(skb);
8649 			return true;
8650 		}
8651 	}
8652 
8653 	/* if eth_skb_pad returns an error the skb was freed */
8654 	if (eth_skb_pad(skb))
8655 		return true;
8656 
8657 	return false;
8658 }
8659 
8660 /**
8661  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
8662  *  @rx_ring: rx descriptor ring packet is being transacted on
8663  *  @rx_desc: pointer to the EOP Rx descriptor
8664  *  @skb: pointer to current skb being populated
8665  *
8666  *  This function checks the ring, descriptor, and packet information in
8667  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
8668  *  other fields within the skb.
8669  **/
8670 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8671 				   union e1000_adv_rx_desc *rx_desc,
8672 				   struct sk_buff *skb)
8673 {
8674 	struct net_device *dev = rx_ring->netdev;
8675 
8676 	igb_rx_hash(rx_ring, rx_desc, skb);
8677 
8678 	igb_rx_checksum(rx_ring, rx_desc, skb);
8679 
8680 	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8681 	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8682 		igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8683 
8684 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8685 	    igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8686 		u16 vid;
8687 
8688 		if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8689 		    test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8690 			vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8691 		else
8692 			vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8693 
8694 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8695 	}
8696 
8697 	skb_record_rx_queue(skb, rx_ring->queue_index);
8698 
8699 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8700 }
8701 
8702 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8703 {
8704 	return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8705 }
8706 
8707 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8708 					       const unsigned int size, int *rx_buf_pgcnt)
8709 {
8710 	struct igb_rx_buffer *rx_buffer;
8711 
8712 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8713 	*rx_buf_pgcnt =
8714 #if (PAGE_SIZE < 8192)
8715 		page_count(rx_buffer->page);
8716 #else
8717 		0;
8718 #endif
8719 	prefetchw(rx_buffer->page);
8720 
8721 	/* we are reusing so sync this buffer for CPU use */
8722 	dma_sync_single_range_for_cpu(rx_ring->dev,
8723 				      rx_buffer->dma,
8724 				      rx_buffer->page_offset,
8725 				      size,
8726 				      DMA_FROM_DEVICE);
8727 
8728 	rx_buffer->pagecnt_bias--;
8729 
8730 	return rx_buffer;
8731 }
8732 
8733 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8734 			      struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8735 {
8736 	if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8737 		/* hand second half of page back to the ring */
8738 		igb_reuse_rx_page(rx_ring, rx_buffer);
8739 	} else {
8740 		/* We are not reusing the buffer so unmap it and free
8741 		 * any references we are holding to it
8742 		 */
8743 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8744 				     igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8745 				     IGB_RX_DMA_ATTR);
8746 		__page_frag_cache_drain(rx_buffer->page,
8747 					rx_buffer->pagecnt_bias);
8748 	}
8749 
8750 	/* clear contents of rx_buffer */
8751 	rx_buffer->page = NULL;
8752 }
8753 
8754 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8755 {
8756 	struct igb_adapter *adapter = q_vector->adapter;
8757 	struct igb_ring *rx_ring = q_vector->rx.ring;
8758 	struct sk_buff *skb = rx_ring->skb;
8759 	unsigned int total_bytes = 0, total_packets = 0;
8760 	u16 cleaned_count = igb_desc_unused(rx_ring);
8761 	unsigned int xdp_xmit = 0;
8762 	struct xdp_buff xdp;
8763 	u32 frame_sz = 0;
8764 	int rx_buf_pgcnt;
8765 
8766 	/* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8767 #if (PAGE_SIZE < 8192)
8768 	frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8769 #endif
8770 	xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8771 
8772 	while (likely(total_packets < budget)) {
8773 		union e1000_adv_rx_desc *rx_desc;
8774 		struct igb_rx_buffer *rx_buffer;
8775 		ktime_t timestamp = 0;
8776 		int pkt_offset = 0;
8777 		unsigned int size;
8778 		void *pktbuf;
8779 
8780 		/* return some buffers to hardware, one at a time is too slow */
8781 		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8782 			igb_alloc_rx_buffers(rx_ring, cleaned_count);
8783 			cleaned_count = 0;
8784 		}
8785 
8786 		rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8787 		size = le16_to_cpu(rx_desc->wb.upper.length);
8788 		if (!size)
8789 			break;
8790 
8791 		/* This memory barrier is needed to keep us from reading
8792 		 * any other fields out of the rx_desc until we know the
8793 		 * descriptor has been written back
8794 		 */
8795 		dma_rmb();
8796 
8797 		rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8798 		pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8799 
8800 		/* pull rx packet timestamp if available and valid */
8801 		if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8802 			int ts_hdr_len;
8803 
8804 			ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8805 							 pktbuf, &timestamp);
8806 
8807 			pkt_offset += ts_hdr_len;
8808 			size -= ts_hdr_len;
8809 		}
8810 
8811 		/* retrieve a buffer from the ring */
8812 		if (!skb) {
8813 			unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8814 			unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8815 
8816 			xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8817 #if (PAGE_SIZE > 4096)
8818 			/* At larger PAGE_SIZE, frame_sz depend on len size */
8819 			xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8820 #endif
8821 			skb = igb_run_xdp(adapter, rx_ring, &xdp);
8822 		}
8823 
8824 		if (IS_ERR(skb)) {
8825 			unsigned int xdp_res = -PTR_ERR(skb);
8826 
8827 			if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8828 				xdp_xmit |= xdp_res;
8829 				igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8830 			} else {
8831 				rx_buffer->pagecnt_bias++;
8832 			}
8833 			total_packets++;
8834 			total_bytes += size;
8835 		} else if (skb)
8836 			igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8837 		else if (ring_uses_build_skb(rx_ring))
8838 			skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8839 					    timestamp);
8840 		else
8841 			skb = igb_construct_skb(rx_ring, rx_buffer,
8842 						&xdp, timestamp);
8843 
8844 		/* exit if we failed to retrieve a buffer */
8845 		if (!skb) {
8846 			rx_ring->rx_stats.alloc_failed++;
8847 			rx_buffer->pagecnt_bias++;
8848 			break;
8849 		}
8850 
8851 		igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8852 		cleaned_count++;
8853 
8854 		/* fetch next buffer in frame if non-eop */
8855 		if (igb_is_non_eop(rx_ring, rx_desc))
8856 			continue;
8857 
8858 		/* verify the packet layout is correct */
8859 		if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8860 			skb = NULL;
8861 			continue;
8862 		}
8863 
8864 		/* probably a little skewed due to removing CRC */
8865 		total_bytes += skb->len;
8866 
8867 		/* populate checksum, timestamp, VLAN, and protocol */
8868 		igb_process_skb_fields(rx_ring, rx_desc, skb);
8869 
8870 		napi_gro_receive(&q_vector->napi, skb);
8871 
8872 		/* reset skb pointer */
8873 		skb = NULL;
8874 
8875 		/* update budget accounting */
8876 		total_packets++;
8877 	}
8878 
8879 	/* place incomplete frames back on ring for completion */
8880 	rx_ring->skb = skb;
8881 
8882 	if (xdp_xmit & IGB_XDP_REDIR)
8883 		xdp_do_flush();
8884 
8885 	if (xdp_xmit & IGB_XDP_TX) {
8886 		struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
8887 
8888 		igb_xdp_ring_update_tail(tx_ring);
8889 	}
8890 
8891 	u64_stats_update_begin(&rx_ring->rx_syncp);
8892 	rx_ring->rx_stats.packets += total_packets;
8893 	rx_ring->rx_stats.bytes += total_bytes;
8894 	u64_stats_update_end(&rx_ring->rx_syncp);
8895 	q_vector->rx.total_packets += total_packets;
8896 	q_vector->rx.total_bytes += total_bytes;
8897 
8898 	if (cleaned_count)
8899 		igb_alloc_rx_buffers(rx_ring, cleaned_count);
8900 
8901 	return total_packets;
8902 }
8903 
8904 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8905 				  struct igb_rx_buffer *bi)
8906 {
8907 	struct page *page = bi->page;
8908 	dma_addr_t dma;
8909 
8910 	/* since we are recycling buffers we should seldom need to alloc */
8911 	if (likely(page))
8912 		return true;
8913 
8914 	/* alloc new page for storage */
8915 	page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8916 	if (unlikely(!page)) {
8917 		rx_ring->rx_stats.alloc_failed++;
8918 		return false;
8919 	}
8920 
8921 	/* map page for use */
8922 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8923 				 igb_rx_pg_size(rx_ring),
8924 				 DMA_FROM_DEVICE,
8925 				 IGB_RX_DMA_ATTR);
8926 
8927 	/* if mapping failed free memory back to system since
8928 	 * there isn't much point in holding memory we can't use
8929 	 */
8930 	if (dma_mapping_error(rx_ring->dev, dma)) {
8931 		__free_pages(page, igb_rx_pg_order(rx_ring));
8932 
8933 		rx_ring->rx_stats.alloc_failed++;
8934 		return false;
8935 	}
8936 
8937 	bi->dma = dma;
8938 	bi->page = page;
8939 	bi->page_offset = igb_rx_offset(rx_ring);
8940 	page_ref_add(page, USHRT_MAX - 1);
8941 	bi->pagecnt_bias = USHRT_MAX;
8942 
8943 	return true;
8944 }
8945 
8946 /**
8947  *  igb_alloc_rx_buffers - Replace used receive buffers
8948  *  @rx_ring: rx descriptor ring to allocate new receive buffers
8949  *  @cleaned_count: count of buffers to allocate
8950  **/
8951 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8952 {
8953 	union e1000_adv_rx_desc *rx_desc;
8954 	struct igb_rx_buffer *bi;
8955 	u16 i = rx_ring->next_to_use;
8956 	u16 bufsz;
8957 
8958 	/* nothing to do */
8959 	if (!cleaned_count)
8960 		return;
8961 
8962 	rx_desc = IGB_RX_DESC(rx_ring, i);
8963 	bi = &rx_ring->rx_buffer_info[i];
8964 	i -= rx_ring->count;
8965 
8966 	bufsz = igb_rx_bufsz(rx_ring);
8967 
8968 	do {
8969 		if (!igb_alloc_mapped_page(rx_ring, bi))
8970 			break;
8971 
8972 		/* sync the buffer for use by the device */
8973 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8974 						 bi->page_offset, bufsz,
8975 						 DMA_FROM_DEVICE);
8976 
8977 		/* Refresh the desc even if buffer_addrs didn't change
8978 		 * because each write-back erases this info.
8979 		 */
8980 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8981 
8982 		rx_desc++;
8983 		bi++;
8984 		i++;
8985 		if (unlikely(!i)) {
8986 			rx_desc = IGB_RX_DESC(rx_ring, 0);
8987 			bi = rx_ring->rx_buffer_info;
8988 			i -= rx_ring->count;
8989 		}
8990 
8991 		/* clear the length for the next_to_use descriptor */
8992 		rx_desc->wb.upper.length = 0;
8993 
8994 		cleaned_count--;
8995 	} while (cleaned_count);
8996 
8997 	i += rx_ring->count;
8998 
8999 	if (rx_ring->next_to_use != i) {
9000 		/* record the next descriptor to use */
9001 		rx_ring->next_to_use = i;
9002 
9003 		/* update next to alloc since we have filled the ring */
9004 		rx_ring->next_to_alloc = i;
9005 
9006 		/* Force memory writes to complete before letting h/w
9007 		 * know there are new descriptors to fetch.  (Only
9008 		 * applicable for weak-ordered memory model archs,
9009 		 * such as IA-64).
9010 		 */
9011 		dma_wmb();
9012 		writel(i, rx_ring->tail);
9013 	}
9014 }
9015 
9016 /**
9017  * igb_mii_ioctl -
9018  * @netdev: pointer to netdev struct
9019  * @ifr: interface structure
9020  * @cmd: ioctl command to execute
9021  **/
9022 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9023 {
9024 	struct igb_adapter *adapter = netdev_priv(netdev);
9025 	struct mii_ioctl_data *data = if_mii(ifr);
9026 
9027 	if (adapter->hw.phy.media_type != e1000_media_type_copper)
9028 		return -EOPNOTSUPP;
9029 
9030 	switch (cmd) {
9031 	case SIOCGMIIPHY:
9032 		data->phy_id = adapter->hw.phy.addr;
9033 		break;
9034 	case SIOCGMIIREG:
9035 		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9036 				     &data->val_out))
9037 			return -EIO;
9038 		break;
9039 	case SIOCSMIIREG:
9040 	default:
9041 		return -EOPNOTSUPP;
9042 	}
9043 	return 0;
9044 }
9045 
9046 /**
9047  * igb_ioctl -
9048  * @netdev: pointer to netdev struct
9049  * @ifr: interface structure
9050  * @cmd: ioctl command to execute
9051  **/
9052 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9053 {
9054 	switch (cmd) {
9055 	case SIOCGMIIPHY:
9056 	case SIOCGMIIREG:
9057 	case SIOCSMIIREG:
9058 		return igb_mii_ioctl(netdev, ifr, cmd);
9059 	case SIOCGHWTSTAMP:
9060 		return igb_ptp_get_ts_config(netdev, ifr);
9061 	case SIOCSHWTSTAMP:
9062 		return igb_ptp_set_ts_config(netdev, ifr);
9063 	default:
9064 		return -EOPNOTSUPP;
9065 	}
9066 }
9067 
9068 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9069 {
9070 	struct igb_adapter *adapter = hw->back;
9071 
9072 	pci_read_config_word(adapter->pdev, reg, value);
9073 }
9074 
9075 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9076 {
9077 	struct igb_adapter *adapter = hw->back;
9078 
9079 	pci_write_config_word(adapter->pdev, reg, *value);
9080 }
9081 
9082 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9083 {
9084 	struct igb_adapter *adapter = hw->back;
9085 
9086 	if (pcie_capability_read_word(adapter->pdev, reg, value))
9087 		return -E1000_ERR_CONFIG;
9088 
9089 	return 0;
9090 }
9091 
9092 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9093 {
9094 	struct igb_adapter *adapter = hw->back;
9095 
9096 	if (pcie_capability_write_word(adapter->pdev, reg, *value))
9097 		return -E1000_ERR_CONFIG;
9098 
9099 	return 0;
9100 }
9101 
9102 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9103 {
9104 	struct igb_adapter *adapter = netdev_priv(netdev);
9105 	struct e1000_hw *hw = &adapter->hw;
9106 	u32 ctrl, rctl;
9107 	bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9108 
9109 	if (enable) {
9110 		/* enable VLAN tag insert/strip */
9111 		ctrl = rd32(E1000_CTRL);
9112 		ctrl |= E1000_CTRL_VME;
9113 		wr32(E1000_CTRL, ctrl);
9114 
9115 		/* Disable CFI check */
9116 		rctl = rd32(E1000_RCTL);
9117 		rctl &= ~E1000_RCTL_CFIEN;
9118 		wr32(E1000_RCTL, rctl);
9119 	} else {
9120 		/* disable VLAN tag insert/strip */
9121 		ctrl = rd32(E1000_CTRL);
9122 		ctrl &= ~E1000_CTRL_VME;
9123 		wr32(E1000_CTRL, ctrl);
9124 	}
9125 
9126 	igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9127 }
9128 
9129 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9130 			       __be16 proto, u16 vid)
9131 {
9132 	struct igb_adapter *adapter = netdev_priv(netdev);
9133 	struct e1000_hw *hw = &adapter->hw;
9134 	int pf_id = adapter->vfs_allocated_count;
9135 
9136 	/* add the filter since PF can receive vlans w/o entry in vlvf */
9137 	if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9138 		igb_vfta_set(hw, vid, pf_id, true, !!vid);
9139 
9140 	set_bit(vid, adapter->active_vlans);
9141 
9142 	return 0;
9143 }
9144 
9145 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9146 				__be16 proto, u16 vid)
9147 {
9148 	struct igb_adapter *adapter = netdev_priv(netdev);
9149 	int pf_id = adapter->vfs_allocated_count;
9150 	struct e1000_hw *hw = &adapter->hw;
9151 
9152 	/* remove VID from filter table */
9153 	if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9154 		igb_vfta_set(hw, vid, pf_id, false, true);
9155 
9156 	clear_bit(vid, adapter->active_vlans);
9157 
9158 	return 0;
9159 }
9160 
9161 static void igb_restore_vlan(struct igb_adapter *adapter)
9162 {
9163 	u16 vid = 1;
9164 
9165 	igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9166 	igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9167 
9168 	for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9169 		igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9170 }
9171 
9172 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9173 {
9174 	struct pci_dev *pdev = adapter->pdev;
9175 	struct e1000_mac_info *mac = &adapter->hw.mac;
9176 
9177 	mac->autoneg = 0;
9178 
9179 	/* Make sure dplx is at most 1 bit and lsb of speed is not set
9180 	 * for the switch() below to work
9181 	 */
9182 	if ((spd & 1) || (dplx & ~1))
9183 		goto err_inval;
9184 
9185 	/* Fiber NIC's only allow 1000 gbps Full duplex
9186 	 * and 100Mbps Full duplex for 100baseFx sfp
9187 	 */
9188 	if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9189 		switch (spd + dplx) {
9190 		case SPEED_10 + DUPLEX_HALF:
9191 		case SPEED_10 + DUPLEX_FULL:
9192 		case SPEED_100 + DUPLEX_HALF:
9193 			goto err_inval;
9194 		default:
9195 			break;
9196 		}
9197 	}
9198 
9199 	switch (spd + dplx) {
9200 	case SPEED_10 + DUPLEX_HALF:
9201 		mac->forced_speed_duplex = ADVERTISE_10_HALF;
9202 		break;
9203 	case SPEED_10 + DUPLEX_FULL:
9204 		mac->forced_speed_duplex = ADVERTISE_10_FULL;
9205 		break;
9206 	case SPEED_100 + DUPLEX_HALF:
9207 		mac->forced_speed_duplex = ADVERTISE_100_HALF;
9208 		break;
9209 	case SPEED_100 + DUPLEX_FULL:
9210 		mac->forced_speed_duplex = ADVERTISE_100_FULL;
9211 		break;
9212 	case SPEED_1000 + DUPLEX_FULL:
9213 		mac->autoneg = 1;
9214 		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9215 		break;
9216 	case SPEED_1000 + DUPLEX_HALF: /* not supported */
9217 	default:
9218 		goto err_inval;
9219 	}
9220 
9221 	/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9222 	adapter->hw.phy.mdix = AUTO_ALL_MODES;
9223 
9224 	return 0;
9225 
9226 err_inval:
9227 	dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9228 	return -EINVAL;
9229 }
9230 
9231 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9232 			  bool runtime)
9233 {
9234 	struct net_device *netdev = pci_get_drvdata(pdev);
9235 	struct igb_adapter *adapter = netdev_priv(netdev);
9236 	struct e1000_hw *hw = &adapter->hw;
9237 	u32 ctrl, rctl, status;
9238 	u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9239 	bool wake;
9240 
9241 	rtnl_lock();
9242 	netif_device_detach(netdev);
9243 
9244 	if (netif_running(netdev))
9245 		__igb_close(netdev, true);
9246 
9247 	igb_ptp_suspend(adapter);
9248 
9249 	igb_clear_interrupt_scheme(adapter);
9250 	rtnl_unlock();
9251 
9252 	status = rd32(E1000_STATUS);
9253 	if (status & E1000_STATUS_LU)
9254 		wufc &= ~E1000_WUFC_LNKC;
9255 
9256 	if (wufc) {
9257 		igb_setup_rctl(adapter);
9258 		igb_set_rx_mode(netdev);
9259 
9260 		/* turn on all-multi mode if wake on multicast is enabled */
9261 		if (wufc & E1000_WUFC_MC) {
9262 			rctl = rd32(E1000_RCTL);
9263 			rctl |= E1000_RCTL_MPE;
9264 			wr32(E1000_RCTL, rctl);
9265 		}
9266 
9267 		ctrl = rd32(E1000_CTRL);
9268 		ctrl |= E1000_CTRL_ADVD3WUC;
9269 		wr32(E1000_CTRL, ctrl);
9270 
9271 		/* Allow time for pending master requests to run */
9272 		igb_disable_pcie_master(hw);
9273 
9274 		wr32(E1000_WUC, E1000_WUC_PME_EN);
9275 		wr32(E1000_WUFC, wufc);
9276 	} else {
9277 		wr32(E1000_WUC, 0);
9278 		wr32(E1000_WUFC, 0);
9279 	}
9280 
9281 	wake = wufc || adapter->en_mng_pt;
9282 	if (!wake)
9283 		igb_power_down_link(adapter);
9284 	else
9285 		igb_power_up_link(adapter);
9286 
9287 	if (enable_wake)
9288 		*enable_wake = wake;
9289 
9290 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
9291 	 * would have already happened in close and is redundant.
9292 	 */
9293 	igb_release_hw_control(adapter);
9294 
9295 	pci_disable_device(pdev);
9296 
9297 	return 0;
9298 }
9299 
9300 static void igb_deliver_wake_packet(struct net_device *netdev)
9301 {
9302 	struct igb_adapter *adapter = netdev_priv(netdev);
9303 	struct e1000_hw *hw = &adapter->hw;
9304 	struct sk_buff *skb;
9305 	u32 wupl;
9306 
9307 	wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9308 
9309 	/* WUPM stores only the first 128 bytes of the wake packet.
9310 	 * Read the packet only if we have the whole thing.
9311 	 */
9312 	if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9313 		return;
9314 
9315 	skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9316 	if (!skb)
9317 		return;
9318 
9319 	skb_put(skb, wupl);
9320 
9321 	/* Ensure reads are 32-bit aligned */
9322 	wupl = roundup(wupl, 4);
9323 
9324 	memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9325 
9326 	skb->protocol = eth_type_trans(skb, netdev);
9327 	netif_rx(skb);
9328 }
9329 
9330 static int __maybe_unused igb_suspend(struct device *dev)
9331 {
9332 	return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9333 }
9334 
9335 static int __maybe_unused __igb_resume(struct device *dev, bool rpm)
9336 {
9337 	struct pci_dev *pdev = to_pci_dev(dev);
9338 	struct net_device *netdev = pci_get_drvdata(pdev);
9339 	struct igb_adapter *adapter = netdev_priv(netdev);
9340 	struct e1000_hw *hw = &adapter->hw;
9341 	u32 err, val;
9342 
9343 	pci_set_power_state(pdev, PCI_D0);
9344 	pci_restore_state(pdev);
9345 	pci_save_state(pdev);
9346 
9347 	if (!pci_device_is_present(pdev))
9348 		return -ENODEV;
9349 	err = pci_enable_device_mem(pdev);
9350 	if (err) {
9351 		dev_err(&pdev->dev,
9352 			"igb: Cannot enable PCI device from suspend\n");
9353 		return err;
9354 	}
9355 	pci_set_master(pdev);
9356 
9357 	pci_enable_wake(pdev, PCI_D3hot, 0);
9358 	pci_enable_wake(pdev, PCI_D3cold, 0);
9359 
9360 	if (igb_init_interrupt_scheme(adapter, true)) {
9361 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9362 		return -ENOMEM;
9363 	}
9364 
9365 	igb_reset(adapter);
9366 
9367 	/* let the f/w know that the h/w is now under the control of the
9368 	 * driver.
9369 	 */
9370 	igb_get_hw_control(adapter);
9371 
9372 	val = rd32(E1000_WUS);
9373 	if (val & WAKE_PKT_WUS)
9374 		igb_deliver_wake_packet(netdev);
9375 
9376 	wr32(E1000_WUS, ~0);
9377 
9378 	if (!rpm)
9379 		rtnl_lock();
9380 	if (!err && netif_running(netdev))
9381 		err = __igb_open(netdev, true);
9382 
9383 	if (!err)
9384 		netif_device_attach(netdev);
9385 	if (!rpm)
9386 		rtnl_unlock();
9387 
9388 	return err;
9389 }
9390 
9391 static int __maybe_unused igb_resume(struct device *dev)
9392 {
9393 	return __igb_resume(dev, false);
9394 }
9395 
9396 static int __maybe_unused igb_runtime_idle(struct device *dev)
9397 {
9398 	struct net_device *netdev = dev_get_drvdata(dev);
9399 	struct igb_adapter *adapter = netdev_priv(netdev);
9400 
9401 	if (!igb_has_link(adapter))
9402 		pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9403 
9404 	return -EBUSY;
9405 }
9406 
9407 static int __maybe_unused igb_runtime_suspend(struct device *dev)
9408 {
9409 	return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9410 }
9411 
9412 static int __maybe_unused igb_runtime_resume(struct device *dev)
9413 {
9414 	return __igb_resume(dev, true);
9415 }
9416 
9417 static void igb_shutdown(struct pci_dev *pdev)
9418 {
9419 	bool wake;
9420 
9421 	__igb_shutdown(pdev, &wake, 0);
9422 
9423 	if (system_state == SYSTEM_POWER_OFF) {
9424 		pci_wake_from_d3(pdev, wake);
9425 		pci_set_power_state(pdev, PCI_D3hot);
9426 	}
9427 }
9428 
9429 #ifdef CONFIG_PCI_IOV
9430 static int igb_sriov_reinit(struct pci_dev *dev)
9431 {
9432 	struct net_device *netdev = pci_get_drvdata(dev);
9433 	struct igb_adapter *adapter = netdev_priv(netdev);
9434 	struct pci_dev *pdev = adapter->pdev;
9435 
9436 	rtnl_lock();
9437 
9438 	if (netif_running(netdev))
9439 		igb_close(netdev);
9440 	else
9441 		igb_reset(adapter);
9442 
9443 	igb_clear_interrupt_scheme(adapter);
9444 
9445 	igb_init_queue_configuration(adapter);
9446 
9447 	if (igb_init_interrupt_scheme(adapter, true)) {
9448 		rtnl_unlock();
9449 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9450 		return -ENOMEM;
9451 	}
9452 
9453 	if (netif_running(netdev))
9454 		igb_open(netdev);
9455 
9456 	rtnl_unlock();
9457 
9458 	return 0;
9459 }
9460 
9461 static int igb_pci_disable_sriov(struct pci_dev *dev)
9462 {
9463 	int err = igb_disable_sriov(dev);
9464 
9465 	if (!err)
9466 		err = igb_sriov_reinit(dev);
9467 
9468 	return err;
9469 }
9470 
9471 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9472 {
9473 	int err = igb_enable_sriov(dev, num_vfs);
9474 
9475 	if (err)
9476 		goto out;
9477 
9478 	err = igb_sriov_reinit(dev);
9479 	if (!err)
9480 		return num_vfs;
9481 
9482 out:
9483 	return err;
9484 }
9485 
9486 #endif
9487 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9488 {
9489 #ifdef CONFIG_PCI_IOV
9490 	if (num_vfs == 0)
9491 		return igb_pci_disable_sriov(dev);
9492 	else
9493 		return igb_pci_enable_sriov(dev, num_vfs);
9494 #endif
9495 	return 0;
9496 }
9497 
9498 /**
9499  *  igb_io_error_detected - called when PCI error is detected
9500  *  @pdev: Pointer to PCI device
9501  *  @state: The current pci connection state
9502  *
9503  *  This function is called after a PCI bus error affecting
9504  *  this device has been detected.
9505  **/
9506 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9507 					      pci_channel_state_t state)
9508 {
9509 	struct net_device *netdev = pci_get_drvdata(pdev);
9510 	struct igb_adapter *adapter = netdev_priv(netdev);
9511 
9512 	netif_device_detach(netdev);
9513 
9514 	if (state == pci_channel_io_perm_failure)
9515 		return PCI_ERS_RESULT_DISCONNECT;
9516 
9517 	if (netif_running(netdev))
9518 		igb_down(adapter);
9519 	pci_disable_device(pdev);
9520 
9521 	/* Request a slot slot reset. */
9522 	return PCI_ERS_RESULT_NEED_RESET;
9523 }
9524 
9525 /**
9526  *  igb_io_slot_reset - called after the pci bus has been reset.
9527  *  @pdev: Pointer to PCI device
9528  *
9529  *  Restart the card from scratch, as if from a cold-boot. Implementation
9530  *  resembles the first-half of the __igb_resume routine.
9531  **/
9532 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9533 {
9534 	struct net_device *netdev = pci_get_drvdata(pdev);
9535 	struct igb_adapter *adapter = netdev_priv(netdev);
9536 	struct e1000_hw *hw = &adapter->hw;
9537 	pci_ers_result_t result;
9538 
9539 	if (pci_enable_device_mem(pdev)) {
9540 		dev_err(&pdev->dev,
9541 			"Cannot re-enable PCI device after reset.\n");
9542 		result = PCI_ERS_RESULT_DISCONNECT;
9543 	} else {
9544 		pci_set_master(pdev);
9545 		pci_restore_state(pdev);
9546 		pci_save_state(pdev);
9547 
9548 		pci_enable_wake(pdev, PCI_D3hot, 0);
9549 		pci_enable_wake(pdev, PCI_D3cold, 0);
9550 
9551 		/* In case of PCI error, adapter lose its HW address
9552 		 * so we should re-assign it here.
9553 		 */
9554 		hw->hw_addr = adapter->io_addr;
9555 
9556 		igb_reset(adapter);
9557 		wr32(E1000_WUS, ~0);
9558 		result = PCI_ERS_RESULT_RECOVERED;
9559 	}
9560 
9561 	return result;
9562 }
9563 
9564 /**
9565  *  igb_io_resume - called when traffic can start flowing again.
9566  *  @pdev: Pointer to PCI device
9567  *
9568  *  This callback is called when the error recovery driver tells us that
9569  *  its OK to resume normal operation. Implementation resembles the
9570  *  second-half of the __igb_resume routine.
9571  */
9572 static void igb_io_resume(struct pci_dev *pdev)
9573 {
9574 	struct net_device *netdev = pci_get_drvdata(pdev);
9575 	struct igb_adapter *adapter = netdev_priv(netdev);
9576 
9577 	if (netif_running(netdev)) {
9578 		if (igb_up(adapter)) {
9579 			dev_err(&pdev->dev, "igb_up failed after reset\n");
9580 			return;
9581 		}
9582 	}
9583 
9584 	netif_device_attach(netdev);
9585 
9586 	/* let the f/w know that the h/w is now under the control of the
9587 	 * driver.
9588 	 */
9589 	igb_get_hw_control(adapter);
9590 }
9591 
9592 /**
9593  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9594  *  @adapter: Pointer to adapter structure
9595  *  @index: Index of the RAR entry which need to be synced with MAC table
9596  **/
9597 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9598 {
9599 	struct e1000_hw *hw = &adapter->hw;
9600 	u32 rar_low, rar_high;
9601 	u8 *addr = adapter->mac_table[index].addr;
9602 
9603 	/* HW expects these to be in network order when they are plugged
9604 	 * into the registers which are little endian.  In order to guarantee
9605 	 * that ordering we need to do an leXX_to_cpup here in order to be
9606 	 * ready for the byteswap that occurs with writel
9607 	 */
9608 	rar_low = le32_to_cpup((__le32 *)(addr));
9609 	rar_high = le16_to_cpup((__le16 *)(addr + 4));
9610 
9611 	/* Indicate to hardware the Address is Valid. */
9612 	if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9613 		if (is_valid_ether_addr(addr))
9614 			rar_high |= E1000_RAH_AV;
9615 
9616 		if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9617 			rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9618 
9619 		switch (hw->mac.type) {
9620 		case e1000_82575:
9621 		case e1000_i210:
9622 			if (adapter->mac_table[index].state &
9623 			    IGB_MAC_STATE_QUEUE_STEERING)
9624 				rar_high |= E1000_RAH_QSEL_ENABLE;
9625 
9626 			rar_high |= E1000_RAH_POOL_1 *
9627 				    adapter->mac_table[index].queue;
9628 			break;
9629 		default:
9630 			rar_high |= E1000_RAH_POOL_1 <<
9631 				    adapter->mac_table[index].queue;
9632 			break;
9633 		}
9634 	}
9635 
9636 	wr32(E1000_RAL(index), rar_low);
9637 	wrfl();
9638 	wr32(E1000_RAH(index), rar_high);
9639 	wrfl();
9640 }
9641 
9642 static int igb_set_vf_mac(struct igb_adapter *adapter,
9643 			  int vf, unsigned char *mac_addr)
9644 {
9645 	struct e1000_hw *hw = &adapter->hw;
9646 	/* VF MAC addresses start at end of receive addresses and moves
9647 	 * towards the first, as a result a collision should not be possible
9648 	 */
9649 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9650 	unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9651 
9652 	ether_addr_copy(vf_mac_addr, mac_addr);
9653 	ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9654 	adapter->mac_table[rar_entry].queue = vf;
9655 	adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9656 	igb_rar_set_index(adapter, rar_entry);
9657 
9658 	return 0;
9659 }
9660 
9661 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9662 {
9663 	struct igb_adapter *adapter = netdev_priv(netdev);
9664 
9665 	if (vf >= adapter->vfs_allocated_count)
9666 		return -EINVAL;
9667 
9668 	/* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9669 	 * flag and allows to overwrite the MAC via VF netdev.  This
9670 	 * is necessary to allow libvirt a way to restore the original
9671 	 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9672 	 * down a VM.
9673 	 */
9674 	if (is_zero_ether_addr(mac)) {
9675 		adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9676 		dev_info(&adapter->pdev->dev,
9677 			 "remove administratively set MAC on VF %d\n",
9678 			 vf);
9679 	} else if (is_valid_ether_addr(mac)) {
9680 		adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9681 		dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9682 			 mac, vf);
9683 		dev_info(&adapter->pdev->dev,
9684 			 "Reload the VF driver to make this change effective.");
9685 		/* Generate additional warning if PF is down */
9686 		if (test_bit(__IGB_DOWN, &adapter->state)) {
9687 			dev_warn(&adapter->pdev->dev,
9688 				 "The VF MAC address has been set, but the PF device is not up.\n");
9689 			dev_warn(&adapter->pdev->dev,
9690 				 "Bring the PF device up before attempting to use the VF device.\n");
9691 		}
9692 	} else {
9693 		return -EINVAL;
9694 	}
9695 	return igb_set_vf_mac(adapter, vf, mac);
9696 }
9697 
9698 static int igb_link_mbps(int internal_link_speed)
9699 {
9700 	switch (internal_link_speed) {
9701 	case SPEED_100:
9702 		return 100;
9703 	case SPEED_1000:
9704 		return 1000;
9705 	default:
9706 		return 0;
9707 	}
9708 }
9709 
9710 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9711 				  int link_speed)
9712 {
9713 	int rf_dec, rf_int;
9714 	u32 bcnrc_val;
9715 
9716 	if (tx_rate != 0) {
9717 		/* Calculate the rate factor values to set */
9718 		rf_int = link_speed / tx_rate;
9719 		rf_dec = (link_speed - (rf_int * tx_rate));
9720 		rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9721 			 tx_rate;
9722 
9723 		bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9724 		bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9725 			      E1000_RTTBCNRC_RF_INT_MASK);
9726 		bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9727 	} else {
9728 		bcnrc_val = 0;
9729 	}
9730 
9731 	wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9732 	/* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9733 	 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9734 	 */
9735 	wr32(E1000_RTTBCNRM, 0x14);
9736 	wr32(E1000_RTTBCNRC, bcnrc_val);
9737 }
9738 
9739 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9740 {
9741 	int actual_link_speed, i;
9742 	bool reset_rate = false;
9743 
9744 	/* VF TX rate limit was not set or not supported */
9745 	if ((adapter->vf_rate_link_speed == 0) ||
9746 	    (adapter->hw.mac.type != e1000_82576))
9747 		return;
9748 
9749 	actual_link_speed = igb_link_mbps(adapter->link_speed);
9750 	if (actual_link_speed != adapter->vf_rate_link_speed) {
9751 		reset_rate = true;
9752 		adapter->vf_rate_link_speed = 0;
9753 		dev_info(&adapter->pdev->dev,
9754 			 "Link speed has been changed. VF Transmit rate is disabled\n");
9755 	}
9756 
9757 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
9758 		if (reset_rate)
9759 			adapter->vf_data[i].tx_rate = 0;
9760 
9761 		igb_set_vf_rate_limit(&adapter->hw, i,
9762 				      adapter->vf_data[i].tx_rate,
9763 				      actual_link_speed);
9764 	}
9765 }
9766 
9767 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9768 			     int min_tx_rate, int max_tx_rate)
9769 {
9770 	struct igb_adapter *adapter = netdev_priv(netdev);
9771 	struct e1000_hw *hw = &adapter->hw;
9772 	int actual_link_speed;
9773 
9774 	if (hw->mac.type != e1000_82576)
9775 		return -EOPNOTSUPP;
9776 
9777 	if (min_tx_rate)
9778 		return -EINVAL;
9779 
9780 	actual_link_speed = igb_link_mbps(adapter->link_speed);
9781 	if ((vf >= adapter->vfs_allocated_count) ||
9782 	    (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9783 	    (max_tx_rate < 0) ||
9784 	    (max_tx_rate > actual_link_speed))
9785 		return -EINVAL;
9786 
9787 	adapter->vf_rate_link_speed = actual_link_speed;
9788 	adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9789 	igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9790 
9791 	return 0;
9792 }
9793 
9794 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9795 				   bool setting)
9796 {
9797 	struct igb_adapter *adapter = netdev_priv(netdev);
9798 	struct e1000_hw *hw = &adapter->hw;
9799 	u32 reg_val, reg_offset;
9800 
9801 	if (!adapter->vfs_allocated_count)
9802 		return -EOPNOTSUPP;
9803 
9804 	if (vf >= adapter->vfs_allocated_count)
9805 		return -EINVAL;
9806 
9807 	reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9808 	reg_val = rd32(reg_offset);
9809 	if (setting)
9810 		reg_val |= (BIT(vf) |
9811 			    BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9812 	else
9813 		reg_val &= ~(BIT(vf) |
9814 			     BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9815 	wr32(reg_offset, reg_val);
9816 
9817 	adapter->vf_data[vf].spoofchk_enabled = setting;
9818 	return 0;
9819 }
9820 
9821 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9822 {
9823 	struct igb_adapter *adapter = netdev_priv(netdev);
9824 
9825 	if (vf >= adapter->vfs_allocated_count)
9826 		return -EINVAL;
9827 	if (adapter->vf_data[vf].trusted == setting)
9828 		return 0;
9829 
9830 	adapter->vf_data[vf].trusted = setting;
9831 
9832 	dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9833 		 vf, setting ? "" : "not ");
9834 	return 0;
9835 }
9836 
9837 static int igb_ndo_get_vf_config(struct net_device *netdev,
9838 				 int vf, struct ifla_vf_info *ivi)
9839 {
9840 	struct igb_adapter *adapter = netdev_priv(netdev);
9841 	if (vf >= adapter->vfs_allocated_count)
9842 		return -EINVAL;
9843 	ivi->vf = vf;
9844 	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9845 	ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9846 	ivi->min_tx_rate = 0;
9847 	ivi->vlan = adapter->vf_data[vf].pf_vlan;
9848 	ivi->qos = adapter->vf_data[vf].pf_qos;
9849 	ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9850 	ivi->trusted = adapter->vf_data[vf].trusted;
9851 	return 0;
9852 }
9853 
9854 static void igb_vmm_control(struct igb_adapter *adapter)
9855 {
9856 	struct e1000_hw *hw = &adapter->hw;
9857 	u32 reg;
9858 
9859 	switch (hw->mac.type) {
9860 	case e1000_82575:
9861 	case e1000_i210:
9862 	case e1000_i211:
9863 	case e1000_i354:
9864 	default:
9865 		/* replication is not supported for 82575 */
9866 		return;
9867 	case e1000_82576:
9868 		/* notify HW that the MAC is adding vlan tags */
9869 		reg = rd32(E1000_DTXCTL);
9870 		reg |= E1000_DTXCTL_VLAN_ADDED;
9871 		wr32(E1000_DTXCTL, reg);
9872 		fallthrough;
9873 	case e1000_82580:
9874 		/* enable replication vlan tag stripping */
9875 		reg = rd32(E1000_RPLOLR);
9876 		reg |= E1000_RPLOLR_STRVLAN;
9877 		wr32(E1000_RPLOLR, reg);
9878 		fallthrough;
9879 	case e1000_i350:
9880 		/* none of the above registers are supported by i350 */
9881 		break;
9882 	}
9883 
9884 	if (adapter->vfs_allocated_count) {
9885 		igb_vmdq_set_loopback_pf(hw, true);
9886 		igb_vmdq_set_replication_pf(hw, true);
9887 		igb_vmdq_set_anti_spoofing_pf(hw, true,
9888 					      adapter->vfs_allocated_count);
9889 	} else {
9890 		igb_vmdq_set_loopback_pf(hw, false);
9891 		igb_vmdq_set_replication_pf(hw, false);
9892 	}
9893 }
9894 
9895 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9896 {
9897 	struct e1000_hw *hw = &adapter->hw;
9898 	u32 dmac_thr;
9899 	u16 hwm;
9900 
9901 	if (hw->mac.type > e1000_82580) {
9902 		if (adapter->flags & IGB_FLAG_DMAC) {
9903 			u32 reg;
9904 
9905 			/* force threshold to 0. */
9906 			wr32(E1000_DMCTXTH, 0);
9907 
9908 			/* DMA Coalescing high water mark needs to be greater
9909 			 * than the Rx threshold. Set hwm to PBA - max frame
9910 			 * size in 16B units, capping it at PBA - 6KB.
9911 			 */
9912 			hwm = 64 * (pba - 6);
9913 			reg = rd32(E1000_FCRTC);
9914 			reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9915 			reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9916 				& E1000_FCRTC_RTH_COAL_MASK);
9917 			wr32(E1000_FCRTC, reg);
9918 
9919 			/* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9920 			 * frame size, capping it at PBA - 10KB.
9921 			 */
9922 			dmac_thr = pba - 10;
9923 			reg = rd32(E1000_DMACR);
9924 			reg &= ~E1000_DMACR_DMACTHR_MASK;
9925 			reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9926 				& E1000_DMACR_DMACTHR_MASK);
9927 
9928 			/* transition to L0x or L1 if available..*/
9929 			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9930 
9931 			/* watchdog timer= +-1000 usec in 32usec intervals */
9932 			reg |= (1000 >> 5);
9933 
9934 			/* Disable BMC-to-OS Watchdog Enable */
9935 			if (hw->mac.type != e1000_i354)
9936 				reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9937 
9938 			wr32(E1000_DMACR, reg);
9939 
9940 			/* no lower threshold to disable
9941 			 * coalescing(smart fifb)-UTRESH=0
9942 			 */
9943 			wr32(E1000_DMCRTRH, 0);
9944 
9945 			reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9946 
9947 			wr32(E1000_DMCTLX, reg);
9948 
9949 			/* free space in tx packet buffer to wake from
9950 			 * DMA coal
9951 			 */
9952 			wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9953 			     (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9954 
9955 			/* make low power state decision controlled
9956 			 * by DMA coal
9957 			 */
9958 			reg = rd32(E1000_PCIEMISC);
9959 			reg &= ~E1000_PCIEMISC_LX_DECISION;
9960 			wr32(E1000_PCIEMISC, reg);
9961 		} /* endif adapter->dmac is not disabled */
9962 	} else if (hw->mac.type == e1000_82580) {
9963 		u32 reg = rd32(E1000_PCIEMISC);
9964 
9965 		wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9966 		wr32(E1000_DMACR, 0);
9967 	}
9968 }
9969 
9970 /**
9971  *  igb_read_i2c_byte - Reads 8 bit word over I2C
9972  *  @hw: pointer to hardware structure
9973  *  @byte_offset: byte offset to read
9974  *  @dev_addr: device address
9975  *  @data: value read
9976  *
9977  *  Performs byte read operation over I2C interface at
9978  *  a specified device address.
9979  **/
9980 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9981 		      u8 dev_addr, u8 *data)
9982 {
9983 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9984 	struct i2c_client *this_client = adapter->i2c_client;
9985 	s32 status;
9986 	u16 swfw_mask = 0;
9987 
9988 	if (!this_client)
9989 		return E1000_ERR_I2C;
9990 
9991 	swfw_mask = E1000_SWFW_PHY0_SM;
9992 
9993 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9994 		return E1000_ERR_SWFW_SYNC;
9995 
9996 	status = i2c_smbus_read_byte_data(this_client, byte_offset);
9997 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9998 
9999 	if (status < 0)
10000 		return E1000_ERR_I2C;
10001 	else {
10002 		*data = status;
10003 		return 0;
10004 	}
10005 }
10006 
10007 /**
10008  *  igb_write_i2c_byte - Writes 8 bit word over I2C
10009  *  @hw: pointer to hardware structure
10010  *  @byte_offset: byte offset to write
10011  *  @dev_addr: device address
10012  *  @data: value to write
10013  *
10014  *  Performs byte write operation over I2C interface at
10015  *  a specified device address.
10016  **/
10017 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10018 		       u8 dev_addr, u8 data)
10019 {
10020 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10021 	struct i2c_client *this_client = adapter->i2c_client;
10022 	s32 status;
10023 	u16 swfw_mask = E1000_SWFW_PHY0_SM;
10024 
10025 	if (!this_client)
10026 		return E1000_ERR_I2C;
10027 
10028 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10029 		return E1000_ERR_SWFW_SYNC;
10030 	status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
10031 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10032 
10033 	if (status)
10034 		return E1000_ERR_I2C;
10035 	else
10036 		return 0;
10037 
10038 }
10039 
10040 int igb_reinit_queues(struct igb_adapter *adapter)
10041 {
10042 	struct net_device *netdev = adapter->netdev;
10043 	struct pci_dev *pdev = adapter->pdev;
10044 	int err = 0;
10045 
10046 	if (netif_running(netdev))
10047 		igb_close(netdev);
10048 
10049 	igb_reset_interrupt_capability(adapter);
10050 
10051 	if (igb_init_interrupt_scheme(adapter, true)) {
10052 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
10053 		return -ENOMEM;
10054 	}
10055 
10056 	if (netif_running(netdev))
10057 		err = igb_open(netdev);
10058 
10059 	return err;
10060 }
10061 
10062 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
10063 {
10064 	struct igb_nfc_filter *rule;
10065 
10066 	spin_lock(&adapter->nfc_lock);
10067 
10068 	hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10069 		igb_erase_filter(adapter, rule);
10070 
10071 	hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
10072 		igb_erase_filter(adapter, rule);
10073 
10074 	spin_unlock(&adapter->nfc_lock);
10075 }
10076 
10077 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
10078 {
10079 	struct igb_nfc_filter *rule;
10080 
10081 	spin_lock(&adapter->nfc_lock);
10082 
10083 	hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10084 		igb_add_filter(adapter, rule);
10085 
10086 	spin_unlock(&adapter->nfc_lock);
10087 }
10088 /* igb_main.c */
10089