1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/module.h> 31 #include <linux/types.h> 32 #include <linux/init.h> 33 #include <linux/bitops.h> 34 #include <linux/vmalloc.h> 35 #include <linux/pagemap.h> 36 #include <linux/netdevice.h> 37 #include <linux/ipv6.h> 38 #include <linux/slab.h> 39 #include <net/checksum.h> 40 #include <net/ip6_checksum.h> 41 #include <linux/net_tstamp.h> 42 #include <linux/mii.h> 43 #include <linux/ethtool.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/pci.h> 47 #include <linux/pci-aspm.h> 48 #include <linux/delay.h> 49 #include <linux/interrupt.h> 50 #include <linux/ip.h> 51 #include <linux/tcp.h> 52 #include <linux/sctp.h> 53 #include <linux/if_ether.h> 54 #include <linux/aer.h> 55 #include <linux/prefetch.h> 56 #include <linux/pm_runtime.h> 57 #ifdef CONFIG_IGB_DCA 58 #include <linux/dca.h> 59 #endif 60 #include "igb.h" 61 62 #define MAJ 4 63 #define MIN 1 64 #define BUILD 2 65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66 __stringify(BUILD) "-k" 67 char igb_driver_name[] = "igb"; 68 char igb_driver_version[] = DRV_VERSION; 69 static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71 static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; 72 73 static const struct e1000_info *igb_info_tbl[] = { 74 [board_82575] = &e1000_82575_info, 75 }; 76 77 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 108 /* required last entry */ 109 {0, } 110 }; 111 112 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 113 114 void igb_reset(struct igb_adapter *); 115 static int igb_setup_all_tx_resources(struct igb_adapter *); 116 static int igb_setup_all_rx_resources(struct igb_adapter *); 117 static void igb_free_all_tx_resources(struct igb_adapter *); 118 static void igb_free_all_rx_resources(struct igb_adapter *); 119 static void igb_setup_mrqc(struct igb_adapter *); 120 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 121 static void igb_remove(struct pci_dev *pdev); 122 static int igb_sw_init(struct igb_adapter *); 123 static int igb_open(struct net_device *); 124 static int igb_close(struct net_device *); 125 static void igb_configure(struct igb_adapter *); 126 static void igb_configure_tx(struct igb_adapter *); 127 static void igb_configure_rx(struct igb_adapter *); 128 static void igb_clean_all_tx_rings(struct igb_adapter *); 129 static void igb_clean_all_rx_rings(struct igb_adapter *); 130 static void igb_clean_tx_ring(struct igb_ring *); 131 static void igb_clean_rx_ring(struct igb_ring *); 132 static void igb_set_rx_mode(struct net_device *); 133 static void igb_update_phy_info(unsigned long); 134 static void igb_watchdog(unsigned long); 135 static void igb_watchdog_task(struct work_struct *); 136 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 137 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 138 struct rtnl_link_stats64 *stats); 139 static int igb_change_mtu(struct net_device *, int); 140 static int igb_set_mac(struct net_device *, void *); 141 static void igb_set_uta(struct igb_adapter *adapter); 142 static irqreturn_t igb_intr(int irq, void *); 143 static irqreturn_t igb_intr_msi(int irq, void *); 144 static irqreturn_t igb_msix_other(int irq, void *); 145 static irqreturn_t igb_msix_ring(int irq, void *); 146 #ifdef CONFIG_IGB_DCA 147 static void igb_update_dca(struct igb_q_vector *); 148 static void igb_setup_dca(struct igb_adapter *); 149 #endif /* CONFIG_IGB_DCA */ 150 static int igb_poll(struct napi_struct *, int); 151 static bool igb_clean_tx_irq(struct igb_q_vector *); 152 static bool igb_clean_rx_irq(struct igb_q_vector *, int); 153 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 154 static void igb_tx_timeout(struct net_device *); 155 static void igb_reset_task(struct work_struct *); 156 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 157 static int igb_vlan_rx_add_vid(struct net_device *, u16); 158 static int igb_vlan_rx_kill_vid(struct net_device *, u16); 159 static void igb_restore_vlan(struct igb_adapter *); 160 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 161 static void igb_ping_all_vfs(struct igb_adapter *); 162 static void igb_msg_task(struct igb_adapter *); 163 static void igb_vmm_control(struct igb_adapter *); 164 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 165 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 166 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 167 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 168 int vf, u16 vlan, u8 qos); 169 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 174 #ifdef CONFIG_PCI_IOV 175 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 176 static bool igb_vfs_are_assigned(struct igb_adapter *adapter); 177 #endif 178 179 #ifdef CONFIG_PM 180 #ifdef CONFIG_PM_SLEEP 181 static int igb_suspend(struct device *); 182 #endif 183 static int igb_resume(struct device *); 184 #ifdef CONFIG_PM_RUNTIME 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 #endif 189 static const struct dev_pm_ops igb_pm_ops = { 190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 192 igb_runtime_idle) 193 }; 194 #endif 195 static void igb_shutdown(struct pci_dev *); 196 #ifdef CONFIG_IGB_DCA 197 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 198 static struct notifier_block dca_notifier = { 199 .notifier_call = igb_notify_dca, 200 .next = NULL, 201 .priority = 0 202 }; 203 #endif 204 #ifdef CONFIG_NET_POLL_CONTROLLER 205 /* for netdump / net console */ 206 static void igb_netpoll(struct net_device *); 207 #endif 208 #ifdef CONFIG_PCI_IOV 209 static unsigned int max_vfs = 0; 210 module_param(max_vfs, uint, 0); 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 212 "per physical function"); 213 #endif /* CONFIG_PCI_IOV */ 214 215 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 216 pci_channel_state_t); 217 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 218 static void igb_io_resume(struct pci_dev *); 219 220 static const struct pci_error_handlers igb_err_handler = { 221 .error_detected = igb_io_error_detected, 222 .slot_reset = igb_io_slot_reset, 223 .resume = igb_io_resume, 224 }; 225 226 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 227 228 static struct pci_driver igb_driver = { 229 .name = igb_driver_name, 230 .id_table = igb_pci_tbl, 231 .probe = igb_probe, 232 .remove = igb_remove, 233 #ifdef CONFIG_PM 234 .driver.pm = &igb_pm_ops, 235 #endif 236 .shutdown = igb_shutdown, 237 .err_handler = &igb_err_handler 238 }; 239 240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 242 MODULE_LICENSE("GPL"); 243 MODULE_VERSION(DRV_VERSION); 244 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 246 static int debug = -1; 247 module_param(debug, int, 0); 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 249 250 struct igb_reg_info { 251 u32 ofs; 252 char *name; 253 }; 254 255 static const struct igb_reg_info igb_reg_info_tbl[] = { 256 257 /* General Registers */ 258 {E1000_CTRL, "CTRL"}, 259 {E1000_STATUS, "STATUS"}, 260 {E1000_CTRL_EXT, "CTRL_EXT"}, 261 262 /* Interrupt Registers */ 263 {E1000_ICR, "ICR"}, 264 265 /* RX Registers */ 266 {E1000_RCTL, "RCTL"}, 267 {E1000_RDLEN(0), "RDLEN"}, 268 {E1000_RDH(0), "RDH"}, 269 {E1000_RDT(0), "RDT"}, 270 {E1000_RXDCTL(0), "RXDCTL"}, 271 {E1000_RDBAL(0), "RDBAL"}, 272 {E1000_RDBAH(0), "RDBAH"}, 273 274 /* TX Registers */ 275 {E1000_TCTL, "TCTL"}, 276 {E1000_TDBAL(0), "TDBAL"}, 277 {E1000_TDBAH(0), "TDBAH"}, 278 {E1000_TDLEN(0), "TDLEN"}, 279 {E1000_TDH(0), "TDH"}, 280 {E1000_TDT(0), "TDT"}, 281 {E1000_TXDCTL(0), "TXDCTL"}, 282 {E1000_TDFH, "TDFH"}, 283 {E1000_TDFT, "TDFT"}, 284 {E1000_TDFHS, "TDFHS"}, 285 {E1000_TDFPC, "TDFPC"}, 286 287 /* List Terminator */ 288 {} 289 }; 290 291 /* 292 * igb_regdump - register printout routine 293 */ 294 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 295 { 296 int n = 0; 297 char rname[16]; 298 u32 regs[8]; 299 300 switch (reginfo->ofs) { 301 case E1000_RDLEN(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDLEN(n)); 304 break; 305 case E1000_RDH(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RDH(n)); 308 break; 309 case E1000_RDT(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDT(n)); 312 break; 313 case E1000_RXDCTL(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RXDCTL(n)); 316 break; 317 case E1000_RDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDBAL(n)); 320 break; 321 case E1000_RDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RDBAH(n)); 324 break; 325 case E1000_TDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_TDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDBAH(n)); 332 break; 333 case E1000_TDLEN(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDLEN(n)); 336 break; 337 case E1000_TDH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDH(n)); 340 break; 341 case E1000_TDT(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDT(n)); 344 break; 345 case E1000_TXDCTL(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TXDCTL(n)); 348 break; 349 default: 350 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 351 return; 352 } 353 354 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 355 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 356 regs[2], regs[3]); 357 } 358 359 /* 360 * igb_dump - Print registers, tx-rings and rx-rings 361 */ 362 static void igb_dump(struct igb_adapter *adapter) 363 { 364 struct net_device *netdev = adapter->netdev; 365 struct e1000_hw *hw = &adapter->hw; 366 struct igb_reg_info *reginfo; 367 struct igb_ring *tx_ring; 368 union e1000_adv_tx_desc *tx_desc; 369 struct my_u0 { u64 a; u64 b; } *u0; 370 struct igb_ring *rx_ring; 371 union e1000_adv_rx_desc *rx_desc; 372 u32 staterr; 373 u16 i, n; 374 375 if (!netif_msg_hw(adapter)) 376 return; 377 378 /* Print netdevice Info */ 379 if (netdev) { 380 dev_info(&adapter->pdev->dev, "Net device Info\n"); 381 pr_info("Device Name state trans_start " 382 "last_rx\n"); 383 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 384 netdev->state, netdev->trans_start, netdev->last_rx); 385 } 386 387 /* Print Registers */ 388 dev_info(&adapter->pdev->dev, "Register Dump\n"); 389 pr_info(" Register Name Value\n"); 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 391 reginfo->name; reginfo++) { 392 igb_regdump(hw, reginfo); 393 } 394 395 /* Print TX Ring Summary */ 396 if (!netdev || !netif_running(netdev)) 397 goto exit; 398 399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 401 for (n = 0; n < adapter->num_tx_queues; n++) { 402 struct igb_tx_buffer *buffer_info; 403 tx_ring = adapter->tx_ring[n]; 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 406 n, tx_ring->next_to_use, tx_ring->next_to_clean, 407 (u64)dma_unmap_addr(buffer_info, dma), 408 dma_unmap_len(buffer_info, len), 409 buffer_info->next_to_watch, 410 (u64)buffer_info->time_stamp); 411 } 412 413 /* Print TX Rings */ 414 if (!netif_msg_tx_done(adapter)) 415 goto rx_ring_summary; 416 417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 418 419 /* Transmit Descriptor Formats 420 * 421 * Advanced Transmit Descriptor 422 * +--------------------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +--------------------------------------------------------------+ 425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 426 * +--------------------------------------------------------------+ 427 * 63 46 45 40 39 38 36 35 32 31 24 15 0 428 */ 429 430 for (n = 0; n < adapter->num_tx_queues; n++) { 431 tx_ring = adapter->tx_ring[n]; 432 pr_info("------------------------------------\n"); 433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 434 pr_info("------------------------------------\n"); 435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 436 "[bi->dma ] leng ntw timestamp " 437 "bi->skb\n"); 438 439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 440 const char *next_desc; 441 struct igb_tx_buffer *buffer_info; 442 tx_desc = IGB_TX_DESC(tx_ring, i); 443 buffer_info = &tx_ring->tx_buffer_info[i]; 444 u0 = (struct my_u0 *)tx_desc; 445 if (i == tx_ring->next_to_use && 446 i == tx_ring->next_to_clean) 447 next_desc = " NTC/U"; 448 else if (i == tx_ring->next_to_use) 449 next_desc = " NTU"; 450 else if (i == tx_ring->next_to_clean) 451 next_desc = " NTC"; 452 else 453 next_desc = ""; 454 455 pr_info("T [0x%03X] %016llX %016llX %016llX" 456 " %04X %p %016llX %p%s\n", i, 457 le64_to_cpu(u0->a), 458 le64_to_cpu(u0->b), 459 (u64)dma_unmap_addr(buffer_info, dma), 460 dma_unmap_len(buffer_info, len), 461 buffer_info->next_to_watch, 462 (u64)buffer_info->time_stamp, 463 buffer_info->skb, next_desc); 464 465 if (netif_msg_pktdata(adapter) && buffer_info->skb) 466 print_hex_dump(KERN_INFO, "", 467 DUMP_PREFIX_ADDRESS, 468 16, 1, buffer_info->skb->data, 469 dma_unmap_len(buffer_info, len), 470 true); 471 } 472 } 473 474 /* Print RX Rings Summary */ 475 rx_ring_summary: 476 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 477 pr_info("Queue [NTU] [NTC]\n"); 478 for (n = 0; n < adapter->num_rx_queues; n++) { 479 rx_ring = adapter->rx_ring[n]; 480 pr_info(" %5d %5X %5X\n", 481 n, rx_ring->next_to_use, rx_ring->next_to_clean); 482 } 483 484 /* Print RX Rings */ 485 if (!netif_msg_rx_status(adapter)) 486 goto exit; 487 488 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 489 490 /* Advanced Receive Descriptor (Read) Format 491 * 63 1 0 492 * +-----------------------------------------------------+ 493 * 0 | Packet Buffer Address [63:1] |A0/NSE| 494 * +----------------------------------------------+------+ 495 * 8 | Header Buffer Address [63:1] | DD | 496 * +-----------------------------------------------------+ 497 * 498 * 499 * Advanced Receive Descriptor (Write-Back) Format 500 * 501 * 63 48 47 32 31 30 21 20 17 16 4 3 0 502 * +------------------------------------------------------+ 503 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 504 * | Checksum Ident | | | | Type | Type | 505 * +------------------------------------------------------+ 506 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 507 * +------------------------------------------------------+ 508 * 63 48 47 32 31 20 19 0 509 */ 510 511 for (n = 0; n < adapter->num_rx_queues; n++) { 512 rx_ring = adapter->rx_ring[n]; 513 pr_info("------------------------------------\n"); 514 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 515 pr_info("------------------------------------\n"); 516 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 517 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 519 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 520 521 for (i = 0; i < rx_ring->count; i++) { 522 const char *next_desc; 523 struct igb_rx_buffer *buffer_info; 524 buffer_info = &rx_ring->rx_buffer_info[i]; 525 rx_desc = IGB_RX_DESC(rx_ring, i); 526 u0 = (struct my_u0 *)rx_desc; 527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 528 529 if (i == rx_ring->next_to_use) 530 next_desc = " NTU"; 531 else if (i == rx_ring->next_to_clean) 532 next_desc = " NTC"; 533 else 534 next_desc = ""; 535 536 if (staterr & E1000_RXD_STAT_DD) { 537 /* Descriptor Done */ 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 539 "RWB", i, 540 le64_to_cpu(u0->a), 541 le64_to_cpu(u0->b), 542 next_desc); 543 } else { 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 545 "R ", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 (u64)buffer_info->dma, 549 next_desc); 550 551 if (netif_msg_pktdata(adapter) && 552 buffer_info->dma && buffer_info->page) { 553 print_hex_dump(KERN_INFO, "", 554 DUMP_PREFIX_ADDRESS, 555 16, 1, 556 page_address(buffer_info->page) + 557 buffer_info->page_offset, 558 IGB_RX_BUFSZ, true); 559 } 560 } 561 } 562 } 563 564 exit: 565 return; 566 } 567 568 /** 569 * igb_get_hw_dev - return device 570 * used by hardware layer to print debugging information 571 **/ 572 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 573 { 574 struct igb_adapter *adapter = hw->back; 575 return adapter->netdev; 576 } 577 578 /** 579 * igb_init_module - Driver Registration Routine 580 * 581 * igb_init_module is the first routine called when the driver is 582 * loaded. All it does is register with the PCI subsystem. 583 **/ 584 static int __init igb_init_module(void) 585 { 586 int ret; 587 pr_info("%s - version %s\n", 588 igb_driver_string, igb_driver_version); 589 590 pr_info("%s\n", igb_copyright); 591 592 #ifdef CONFIG_IGB_DCA 593 dca_register_notify(&dca_notifier); 594 #endif 595 ret = pci_register_driver(&igb_driver); 596 return ret; 597 } 598 599 module_init(igb_init_module); 600 601 /** 602 * igb_exit_module - Driver Exit Cleanup Routine 603 * 604 * igb_exit_module is called just before the driver is removed 605 * from memory. 606 **/ 607 static void __exit igb_exit_module(void) 608 { 609 #ifdef CONFIG_IGB_DCA 610 dca_unregister_notify(&dca_notifier); 611 #endif 612 pci_unregister_driver(&igb_driver); 613 } 614 615 module_exit(igb_exit_module); 616 617 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 618 /** 619 * igb_cache_ring_register - Descriptor ring to register mapping 620 * @adapter: board private structure to initialize 621 * 622 * Once we know the feature-set enabled for the device, we'll cache 623 * the register offset the descriptor ring is assigned to. 624 **/ 625 static void igb_cache_ring_register(struct igb_adapter *adapter) 626 { 627 int i = 0, j = 0; 628 u32 rbase_offset = adapter->vfs_allocated_count; 629 630 switch (adapter->hw.mac.type) { 631 case e1000_82576: 632 /* The queues are allocated for virtualization such that VF 0 633 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 634 * In order to avoid collision we start at the first free queue 635 * and continue consuming queues in the same sequence 636 */ 637 if (adapter->vfs_allocated_count) { 638 for (; i < adapter->rss_queues; i++) 639 adapter->rx_ring[i]->reg_idx = rbase_offset + 640 Q_IDX_82576(i); 641 } 642 case e1000_82575: 643 case e1000_82580: 644 case e1000_i350: 645 case e1000_i210: 646 case e1000_i211: 647 default: 648 for (; i < adapter->num_rx_queues; i++) 649 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 650 for (; j < adapter->num_tx_queues; j++) 651 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 652 break; 653 } 654 } 655 656 /** 657 * igb_write_ivar - configure ivar for given MSI-X vector 658 * @hw: pointer to the HW structure 659 * @msix_vector: vector number we are allocating to a given ring 660 * @index: row index of IVAR register to write within IVAR table 661 * @offset: column offset of in IVAR, should be multiple of 8 662 * 663 * This function is intended to handle the writing of the IVAR register 664 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 665 * each containing an cause allocation for an Rx and Tx ring, and a 666 * variable number of rows depending on the number of queues supported. 667 **/ 668 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 669 int index, int offset) 670 { 671 u32 ivar = array_rd32(E1000_IVAR0, index); 672 673 /* clear any bits that are currently set */ 674 ivar &= ~((u32)0xFF << offset); 675 676 /* write vector and valid bit */ 677 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 678 679 array_wr32(E1000_IVAR0, index, ivar); 680 } 681 682 #define IGB_N0_QUEUE -1 683 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 684 { 685 struct igb_adapter *adapter = q_vector->adapter; 686 struct e1000_hw *hw = &adapter->hw; 687 int rx_queue = IGB_N0_QUEUE; 688 int tx_queue = IGB_N0_QUEUE; 689 u32 msixbm = 0; 690 691 if (q_vector->rx.ring) 692 rx_queue = q_vector->rx.ring->reg_idx; 693 if (q_vector->tx.ring) 694 tx_queue = q_vector->tx.ring->reg_idx; 695 696 switch (hw->mac.type) { 697 case e1000_82575: 698 /* The 82575 assigns vectors using a bitmask, which matches the 699 bitmask for the EICR/EIMS/EIMC registers. To assign one 700 or more queues to a vector, we write the appropriate bits 701 into the MSIXBM register for that vector. */ 702 if (rx_queue > IGB_N0_QUEUE) 703 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 704 if (tx_queue > IGB_N0_QUEUE) 705 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 706 if (!adapter->msix_entries && msix_vector == 0) 707 msixbm |= E1000_EIMS_OTHER; 708 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 709 q_vector->eims_value = msixbm; 710 break; 711 case e1000_82576: 712 /* 713 * 82576 uses a table that essentially consists of 2 columns 714 * with 8 rows. The ordering is column-major so we use the 715 * lower 3 bits as the row index, and the 4th bit as the 716 * column offset. 717 */ 718 if (rx_queue > IGB_N0_QUEUE) 719 igb_write_ivar(hw, msix_vector, 720 rx_queue & 0x7, 721 (rx_queue & 0x8) << 1); 722 if (tx_queue > IGB_N0_QUEUE) 723 igb_write_ivar(hw, msix_vector, 724 tx_queue & 0x7, 725 ((tx_queue & 0x8) << 1) + 8); 726 q_vector->eims_value = 1 << msix_vector; 727 break; 728 case e1000_82580: 729 case e1000_i350: 730 case e1000_i210: 731 case e1000_i211: 732 /* 733 * On 82580 and newer adapters the scheme is similar to 82576 734 * however instead of ordering column-major we have things 735 * ordered row-major. So we traverse the table by using 736 * bit 0 as the column offset, and the remaining bits as the 737 * row index. 738 */ 739 if (rx_queue > IGB_N0_QUEUE) 740 igb_write_ivar(hw, msix_vector, 741 rx_queue >> 1, 742 (rx_queue & 0x1) << 4); 743 if (tx_queue > IGB_N0_QUEUE) 744 igb_write_ivar(hw, msix_vector, 745 tx_queue >> 1, 746 ((tx_queue & 0x1) << 4) + 8); 747 q_vector->eims_value = 1 << msix_vector; 748 break; 749 default: 750 BUG(); 751 break; 752 } 753 754 /* add q_vector eims value to global eims_enable_mask */ 755 adapter->eims_enable_mask |= q_vector->eims_value; 756 757 /* configure q_vector to set itr on first interrupt */ 758 q_vector->set_itr = 1; 759 } 760 761 /** 762 * igb_configure_msix - Configure MSI-X hardware 763 * 764 * igb_configure_msix sets up the hardware to properly 765 * generate MSI-X interrupts. 766 **/ 767 static void igb_configure_msix(struct igb_adapter *adapter) 768 { 769 u32 tmp; 770 int i, vector = 0; 771 struct e1000_hw *hw = &adapter->hw; 772 773 adapter->eims_enable_mask = 0; 774 775 /* set vector for other causes, i.e. link changes */ 776 switch (hw->mac.type) { 777 case e1000_82575: 778 tmp = rd32(E1000_CTRL_EXT); 779 /* enable MSI-X PBA support*/ 780 tmp |= E1000_CTRL_EXT_PBA_CLR; 781 782 /* Auto-Mask interrupts upon ICR read. */ 783 tmp |= E1000_CTRL_EXT_EIAME; 784 tmp |= E1000_CTRL_EXT_IRCA; 785 786 wr32(E1000_CTRL_EXT, tmp); 787 788 /* enable msix_other interrupt */ 789 array_wr32(E1000_MSIXBM(0), vector++, 790 E1000_EIMS_OTHER); 791 adapter->eims_other = E1000_EIMS_OTHER; 792 793 break; 794 795 case e1000_82576: 796 case e1000_82580: 797 case e1000_i350: 798 case e1000_i210: 799 case e1000_i211: 800 /* Turn on MSI-X capability first, or our settings 801 * won't stick. And it will take days to debug. */ 802 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 803 E1000_GPIE_PBA | E1000_GPIE_EIAME | 804 E1000_GPIE_NSICR); 805 806 /* enable msix_other interrupt */ 807 adapter->eims_other = 1 << vector; 808 tmp = (vector++ | E1000_IVAR_VALID) << 8; 809 810 wr32(E1000_IVAR_MISC, tmp); 811 break; 812 default: 813 /* do nothing, since nothing else supports MSI-X */ 814 break; 815 } /* switch (hw->mac.type) */ 816 817 adapter->eims_enable_mask |= adapter->eims_other; 818 819 for (i = 0; i < adapter->num_q_vectors; i++) 820 igb_assign_vector(adapter->q_vector[i], vector++); 821 822 wrfl(); 823 } 824 825 /** 826 * igb_request_msix - Initialize MSI-X interrupts 827 * 828 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 829 * kernel. 830 **/ 831 static int igb_request_msix(struct igb_adapter *adapter) 832 { 833 struct net_device *netdev = adapter->netdev; 834 struct e1000_hw *hw = &adapter->hw; 835 int i, err = 0, vector = 0, free_vector = 0; 836 837 err = request_irq(adapter->msix_entries[vector].vector, 838 igb_msix_other, 0, netdev->name, adapter); 839 if (err) 840 goto err_out; 841 842 for (i = 0; i < adapter->num_q_vectors; i++) { 843 struct igb_q_vector *q_vector = adapter->q_vector[i]; 844 845 vector++; 846 847 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 848 849 if (q_vector->rx.ring && q_vector->tx.ring) 850 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 851 q_vector->rx.ring->queue_index); 852 else if (q_vector->tx.ring) 853 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 854 q_vector->tx.ring->queue_index); 855 else if (q_vector->rx.ring) 856 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 857 q_vector->rx.ring->queue_index); 858 else 859 sprintf(q_vector->name, "%s-unused", netdev->name); 860 861 err = request_irq(adapter->msix_entries[vector].vector, 862 igb_msix_ring, 0, q_vector->name, 863 q_vector); 864 if (err) 865 goto err_free; 866 } 867 868 igb_configure_msix(adapter); 869 return 0; 870 871 err_free: 872 /* free already assigned IRQs */ 873 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 874 875 vector--; 876 for (i = 0; i < vector; i++) { 877 free_irq(adapter->msix_entries[free_vector++].vector, 878 adapter->q_vector[i]); 879 } 880 err_out: 881 return err; 882 } 883 884 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 885 { 886 if (adapter->msix_entries) { 887 pci_disable_msix(adapter->pdev); 888 kfree(adapter->msix_entries); 889 adapter->msix_entries = NULL; 890 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 891 pci_disable_msi(adapter->pdev); 892 } 893 } 894 895 /** 896 * igb_free_q_vector - Free memory allocated for specific interrupt vector 897 * @adapter: board private structure to initialize 898 * @v_idx: Index of vector to be freed 899 * 900 * This function frees the memory allocated to the q_vector. In addition if 901 * NAPI is enabled it will delete any references to the NAPI struct prior 902 * to freeing the q_vector. 903 **/ 904 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 905 { 906 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 907 908 if (q_vector->tx.ring) 909 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 910 911 if (q_vector->rx.ring) 912 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 913 914 adapter->q_vector[v_idx] = NULL; 915 netif_napi_del(&q_vector->napi); 916 917 /* 918 * ixgbe_get_stats64() might access the rings on this vector, 919 * we must wait a grace period before freeing it. 920 */ 921 kfree_rcu(q_vector, rcu); 922 } 923 924 /** 925 * igb_free_q_vectors - Free memory allocated for interrupt vectors 926 * @adapter: board private structure to initialize 927 * 928 * This function frees the memory allocated to the q_vectors. In addition if 929 * NAPI is enabled it will delete any references to the NAPI struct prior 930 * to freeing the q_vector. 931 **/ 932 static void igb_free_q_vectors(struct igb_adapter *adapter) 933 { 934 int v_idx = adapter->num_q_vectors; 935 936 adapter->num_tx_queues = 0; 937 adapter->num_rx_queues = 0; 938 adapter->num_q_vectors = 0; 939 940 while (v_idx--) 941 igb_free_q_vector(adapter, v_idx); 942 } 943 944 /** 945 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 946 * 947 * This function resets the device so that it has 0 rx queues, tx queues, and 948 * MSI-X interrupts allocated. 949 */ 950 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 951 { 952 igb_free_q_vectors(adapter); 953 igb_reset_interrupt_capability(adapter); 954 } 955 956 /** 957 * igb_set_interrupt_capability - set MSI or MSI-X if supported 958 * 959 * Attempt to configure interrupts using the best available 960 * capabilities of the hardware and kernel. 961 **/ 962 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 963 { 964 int err; 965 int numvecs, i; 966 967 if (!msix) 968 goto msi_only; 969 970 /* Number of supported queues. */ 971 adapter->num_rx_queues = adapter->rss_queues; 972 if (adapter->vfs_allocated_count) 973 adapter->num_tx_queues = 1; 974 else 975 adapter->num_tx_queues = adapter->rss_queues; 976 977 /* start with one vector for every rx queue */ 978 numvecs = adapter->num_rx_queues; 979 980 /* if tx handler is separate add 1 for every tx queue */ 981 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 982 numvecs += adapter->num_tx_queues; 983 984 /* store the number of vectors reserved for queues */ 985 adapter->num_q_vectors = numvecs; 986 987 /* add 1 vector for link status interrupts */ 988 numvecs++; 989 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 990 GFP_KERNEL); 991 992 if (!adapter->msix_entries) 993 goto msi_only; 994 995 for (i = 0; i < numvecs; i++) 996 adapter->msix_entries[i].entry = i; 997 998 err = pci_enable_msix(adapter->pdev, 999 adapter->msix_entries, 1000 numvecs); 1001 if (err == 0) 1002 return; 1003 1004 igb_reset_interrupt_capability(adapter); 1005 1006 /* If we can't do MSI-X, try MSI */ 1007 msi_only: 1008 #ifdef CONFIG_PCI_IOV 1009 /* disable SR-IOV for non MSI-X configurations */ 1010 if (adapter->vf_data) { 1011 struct e1000_hw *hw = &adapter->hw; 1012 /* disable iov and allow time for transactions to clear */ 1013 pci_disable_sriov(adapter->pdev); 1014 msleep(500); 1015 1016 kfree(adapter->vf_data); 1017 adapter->vf_data = NULL; 1018 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1019 wrfl(); 1020 msleep(100); 1021 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1022 } 1023 #endif 1024 adapter->vfs_allocated_count = 0; 1025 adapter->rss_queues = 1; 1026 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1027 adapter->num_rx_queues = 1; 1028 adapter->num_tx_queues = 1; 1029 adapter->num_q_vectors = 1; 1030 if (!pci_enable_msi(adapter->pdev)) 1031 adapter->flags |= IGB_FLAG_HAS_MSI; 1032 } 1033 1034 static void igb_add_ring(struct igb_ring *ring, 1035 struct igb_ring_container *head) 1036 { 1037 head->ring = ring; 1038 head->count++; 1039 } 1040 1041 /** 1042 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1043 * @adapter: board private structure to initialize 1044 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1045 * @v_idx: index of vector in adapter struct 1046 * @txr_count: total number of Tx rings to allocate 1047 * @txr_idx: index of first Tx ring to allocate 1048 * @rxr_count: total number of Rx rings to allocate 1049 * @rxr_idx: index of first Rx ring to allocate 1050 * 1051 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1052 **/ 1053 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1054 int v_count, int v_idx, 1055 int txr_count, int txr_idx, 1056 int rxr_count, int rxr_idx) 1057 { 1058 struct igb_q_vector *q_vector; 1059 struct igb_ring *ring; 1060 int ring_count, size; 1061 1062 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1063 if (txr_count > 1 || rxr_count > 1) 1064 return -ENOMEM; 1065 1066 ring_count = txr_count + rxr_count; 1067 size = sizeof(struct igb_q_vector) + 1068 (sizeof(struct igb_ring) * ring_count); 1069 1070 /* allocate q_vector and rings */ 1071 q_vector = kzalloc(size, GFP_KERNEL); 1072 if (!q_vector) 1073 return -ENOMEM; 1074 1075 /* initialize NAPI */ 1076 netif_napi_add(adapter->netdev, &q_vector->napi, 1077 igb_poll, 64); 1078 1079 /* tie q_vector and adapter together */ 1080 adapter->q_vector[v_idx] = q_vector; 1081 q_vector->adapter = adapter; 1082 1083 /* initialize work limits */ 1084 q_vector->tx.work_limit = adapter->tx_work_limit; 1085 1086 /* initialize ITR configuration */ 1087 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1088 q_vector->itr_val = IGB_START_ITR; 1089 1090 /* initialize pointer to rings */ 1091 ring = q_vector->ring; 1092 1093 if (txr_count) { 1094 /* assign generic ring traits */ 1095 ring->dev = &adapter->pdev->dev; 1096 ring->netdev = adapter->netdev; 1097 1098 /* configure backlink on ring */ 1099 ring->q_vector = q_vector; 1100 1101 /* update q_vector Tx values */ 1102 igb_add_ring(ring, &q_vector->tx); 1103 1104 /* For 82575, context index must be unique per ring. */ 1105 if (adapter->hw.mac.type == e1000_82575) 1106 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1107 1108 /* apply Tx specific ring traits */ 1109 ring->count = adapter->tx_ring_count; 1110 ring->queue_index = txr_idx; 1111 1112 /* assign ring to adapter */ 1113 adapter->tx_ring[txr_idx] = ring; 1114 1115 /* push pointer to next ring */ 1116 ring++; 1117 } 1118 1119 if (rxr_count) { 1120 /* assign generic ring traits */ 1121 ring->dev = &adapter->pdev->dev; 1122 ring->netdev = adapter->netdev; 1123 1124 /* configure backlink on ring */ 1125 ring->q_vector = q_vector; 1126 1127 /* update q_vector Rx values */ 1128 igb_add_ring(ring, &q_vector->rx); 1129 1130 /* set flag indicating ring supports SCTP checksum offload */ 1131 if (adapter->hw.mac.type >= e1000_82576) 1132 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1133 1134 /* 1135 * On i350, i210, and i211, loopback VLAN packets 1136 * have the tag byte-swapped. 1137 * */ 1138 if (adapter->hw.mac.type >= e1000_i350) 1139 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1140 1141 /* apply Rx specific ring traits */ 1142 ring->count = adapter->rx_ring_count; 1143 ring->queue_index = rxr_idx; 1144 1145 /* assign ring to adapter */ 1146 adapter->rx_ring[rxr_idx] = ring; 1147 } 1148 1149 return 0; 1150 } 1151 1152 1153 /** 1154 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1155 * @adapter: board private structure to initialize 1156 * 1157 * We allocate one q_vector per queue interrupt. If allocation fails we 1158 * return -ENOMEM. 1159 **/ 1160 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1161 { 1162 int q_vectors = adapter->num_q_vectors; 1163 int rxr_remaining = adapter->num_rx_queues; 1164 int txr_remaining = adapter->num_tx_queues; 1165 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1166 int err; 1167 1168 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1169 for (; rxr_remaining; v_idx++) { 1170 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1171 0, 0, 1, rxr_idx); 1172 1173 if (err) 1174 goto err_out; 1175 1176 /* update counts and index */ 1177 rxr_remaining--; 1178 rxr_idx++; 1179 } 1180 } 1181 1182 for (; v_idx < q_vectors; v_idx++) { 1183 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1184 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1185 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1186 tqpv, txr_idx, rqpv, rxr_idx); 1187 1188 if (err) 1189 goto err_out; 1190 1191 /* update counts and index */ 1192 rxr_remaining -= rqpv; 1193 txr_remaining -= tqpv; 1194 rxr_idx++; 1195 txr_idx++; 1196 } 1197 1198 return 0; 1199 1200 err_out: 1201 adapter->num_tx_queues = 0; 1202 adapter->num_rx_queues = 0; 1203 adapter->num_q_vectors = 0; 1204 1205 while (v_idx--) 1206 igb_free_q_vector(adapter, v_idx); 1207 1208 return -ENOMEM; 1209 } 1210 1211 /** 1212 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1213 * 1214 * This function initializes the interrupts and allocates all of the queues. 1215 **/ 1216 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1217 { 1218 struct pci_dev *pdev = adapter->pdev; 1219 int err; 1220 1221 igb_set_interrupt_capability(adapter, msix); 1222 1223 err = igb_alloc_q_vectors(adapter); 1224 if (err) { 1225 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1226 goto err_alloc_q_vectors; 1227 } 1228 1229 igb_cache_ring_register(adapter); 1230 1231 return 0; 1232 1233 err_alloc_q_vectors: 1234 igb_reset_interrupt_capability(adapter); 1235 return err; 1236 } 1237 1238 /** 1239 * igb_request_irq - initialize interrupts 1240 * 1241 * Attempts to configure interrupts using the best available 1242 * capabilities of the hardware and kernel. 1243 **/ 1244 static int igb_request_irq(struct igb_adapter *adapter) 1245 { 1246 struct net_device *netdev = adapter->netdev; 1247 struct pci_dev *pdev = adapter->pdev; 1248 int err = 0; 1249 1250 if (adapter->msix_entries) { 1251 err = igb_request_msix(adapter); 1252 if (!err) 1253 goto request_done; 1254 /* fall back to MSI */ 1255 igb_free_all_tx_resources(adapter); 1256 igb_free_all_rx_resources(adapter); 1257 1258 igb_clear_interrupt_scheme(adapter); 1259 err = igb_init_interrupt_scheme(adapter, false); 1260 if (err) 1261 goto request_done; 1262 1263 igb_setup_all_tx_resources(adapter); 1264 igb_setup_all_rx_resources(adapter); 1265 igb_configure(adapter); 1266 } 1267 1268 igb_assign_vector(adapter->q_vector[0], 0); 1269 1270 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1271 err = request_irq(pdev->irq, igb_intr_msi, 0, 1272 netdev->name, adapter); 1273 if (!err) 1274 goto request_done; 1275 1276 /* fall back to legacy interrupts */ 1277 igb_reset_interrupt_capability(adapter); 1278 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1279 } 1280 1281 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1282 netdev->name, adapter); 1283 1284 if (err) 1285 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1286 err); 1287 1288 request_done: 1289 return err; 1290 } 1291 1292 static void igb_free_irq(struct igb_adapter *adapter) 1293 { 1294 if (adapter->msix_entries) { 1295 int vector = 0, i; 1296 1297 free_irq(adapter->msix_entries[vector++].vector, adapter); 1298 1299 for (i = 0; i < adapter->num_q_vectors; i++) 1300 free_irq(adapter->msix_entries[vector++].vector, 1301 adapter->q_vector[i]); 1302 } else { 1303 free_irq(adapter->pdev->irq, adapter); 1304 } 1305 } 1306 1307 /** 1308 * igb_irq_disable - Mask off interrupt generation on the NIC 1309 * @adapter: board private structure 1310 **/ 1311 static void igb_irq_disable(struct igb_adapter *adapter) 1312 { 1313 struct e1000_hw *hw = &adapter->hw; 1314 1315 /* 1316 * we need to be careful when disabling interrupts. The VFs are also 1317 * mapped into these registers and so clearing the bits can cause 1318 * issues on the VF drivers so we only need to clear what we set 1319 */ 1320 if (adapter->msix_entries) { 1321 u32 regval = rd32(E1000_EIAM); 1322 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1323 wr32(E1000_EIMC, adapter->eims_enable_mask); 1324 regval = rd32(E1000_EIAC); 1325 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1326 } 1327 1328 wr32(E1000_IAM, 0); 1329 wr32(E1000_IMC, ~0); 1330 wrfl(); 1331 if (adapter->msix_entries) { 1332 int i; 1333 for (i = 0; i < adapter->num_q_vectors; i++) 1334 synchronize_irq(adapter->msix_entries[i].vector); 1335 } else { 1336 synchronize_irq(adapter->pdev->irq); 1337 } 1338 } 1339 1340 /** 1341 * igb_irq_enable - Enable default interrupt generation settings 1342 * @adapter: board private structure 1343 **/ 1344 static void igb_irq_enable(struct igb_adapter *adapter) 1345 { 1346 struct e1000_hw *hw = &adapter->hw; 1347 1348 if (adapter->msix_entries) { 1349 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1350 u32 regval = rd32(E1000_EIAC); 1351 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1352 regval = rd32(E1000_EIAM); 1353 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1354 wr32(E1000_EIMS, adapter->eims_enable_mask); 1355 if (adapter->vfs_allocated_count) { 1356 wr32(E1000_MBVFIMR, 0xFF); 1357 ims |= E1000_IMS_VMMB; 1358 } 1359 wr32(E1000_IMS, ims); 1360 } else { 1361 wr32(E1000_IMS, IMS_ENABLE_MASK | 1362 E1000_IMS_DRSTA); 1363 wr32(E1000_IAM, IMS_ENABLE_MASK | 1364 E1000_IMS_DRSTA); 1365 } 1366 } 1367 1368 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1369 { 1370 struct e1000_hw *hw = &adapter->hw; 1371 u16 vid = adapter->hw.mng_cookie.vlan_id; 1372 u16 old_vid = adapter->mng_vlan_id; 1373 1374 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1375 /* add VID to filter table */ 1376 igb_vfta_set(hw, vid, true); 1377 adapter->mng_vlan_id = vid; 1378 } else { 1379 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1380 } 1381 1382 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1383 (vid != old_vid) && 1384 !test_bit(old_vid, adapter->active_vlans)) { 1385 /* remove VID from filter table */ 1386 igb_vfta_set(hw, old_vid, false); 1387 } 1388 } 1389 1390 /** 1391 * igb_release_hw_control - release control of the h/w to f/w 1392 * @adapter: address of board private structure 1393 * 1394 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1395 * For ASF and Pass Through versions of f/w this means that the 1396 * driver is no longer loaded. 1397 * 1398 **/ 1399 static void igb_release_hw_control(struct igb_adapter *adapter) 1400 { 1401 struct e1000_hw *hw = &adapter->hw; 1402 u32 ctrl_ext; 1403 1404 /* Let firmware take over control of h/w */ 1405 ctrl_ext = rd32(E1000_CTRL_EXT); 1406 wr32(E1000_CTRL_EXT, 1407 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1408 } 1409 1410 /** 1411 * igb_get_hw_control - get control of the h/w from f/w 1412 * @adapter: address of board private structure 1413 * 1414 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1415 * For ASF and Pass Through versions of f/w this means that 1416 * the driver is loaded. 1417 * 1418 **/ 1419 static void igb_get_hw_control(struct igb_adapter *adapter) 1420 { 1421 struct e1000_hw *hw = &adapter->hw; 1422 u32 ctrl_ext; 1423 1424 /* Let firmware know the driver has taken over */ 1425 ctrl_ext = rd32(E1000_CTRL_EXT); 1426 wr32(E1000_CTRL_EXT, 1427 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1428 } 1429 1430 /** 1431 * igb_configure - configure the hardware for RX and TX 1432 * @adapter: private board structure 1433 **/ 1434 static void igb_configure(struct igb_adapter *adapter) 1435 { 1436 struct net_device *netdev = adapter->netdev; 1437 int i; 1438 1439 igb_get_hw_control(adapter); 1440 igb_set_rx_mode(netdev); 1441 1442 igb_restore_vlan(adapter); 1443 1444 igb_setup_tctl(adapter); 1445 igb_setup_mrqc(adapter); 1446 igb_setup_rctl(adapter); 1447 1448 igb_configure_tx(adapter); 1449 igb_configure_rx(adapter); 1450 1451 igb_rx_fifo_flush_82575(&adapter->hw); 1452 1453 /* call igb_desc_unused which always leaves 1454 * at least 1 descriptor unused to make sure 1455 * next_to_use != next_to_clean */ 1456 for (i = 0; i < adapter->num_rx_queues; i++) { 1457 struct igb_ring *ring = adapter->rx_ring[i]; 1458 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1459 } 1460 } 1461 1462 /** 1463 * igb_power_up_link - Power up the phy/serdes link 1464 * @adapter: address of board private structure 1465 **/ 1466 void igb_power_up_link(struct igb_adapter *adapter) 1467 { 1468 igb_reset_phy(&adapter->hw); 1469 1470 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1471 igb_power_up_phy_copper(&adapter->hw); 1472 else 1473 igb_power_up_serdes_link_82575(&adapter->hw); 1474 } 1475 1476 /** 1477 * igb_power_down_link - Power down the phy/serdes link 1478 * @adapter: address of board private structure 1479 */ 1480 static void igb_power_down_link(struct igb_adapter *adapter) 1481 { 1482 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1483 igb_power_down_phy_copper_82575(&adapter->hw); 1484 else 1485 igb_shutdown_serdes_link_82575(&adapter->hw); 1486 } 1487 1488 /** 1489 * igb_up - Open the interface and prepare it to handle traffic 1490 * @adapter: board private structure 1491 **/ 1492 int igb_up(struct igb_adapter *adapter) 1493 { 1494 struct e1000_hw *hw = &adapter->hw; 1495 int i; 1496 1497 /* hardware has been reset, we need to reload some things */ 1498 igb_configure(adapter); 1499 1500 clear_bit(__IGB_DOWN, &adapter->state); 1501 1502 for (i = 0; i < adapter->num_q_vectors; i++) 1503 napi_enable(&(adapter->q_vector[i]->napi)); 1504 1505 if (adapter->msix_entries) 1506 igb_configure_msix(adapter); 1507 else 1508 igb_assign_vector(adapter->q_vector[0], 0); 1509 1510 /* Clear any pending interrupts. */ 1511 rd32(E1000_ICR); 1512 igb_irq_enable(adapter); 1513 1514 /* notify VFs that reset has been completed */ 1515 if (adapter->vfs_allocated_count) { 1516 u32 reg_data = rd32(E1000_CTRL_EXT); 1517 reg_data |= E1000_CTRL_EXT_PFRSTD; 1518 wr32(E1000_CTRL_EXT, reg_data); 1519 } 1520 1521 netif_tx_start_all_queues(adapter->netdev); 1522 1523 /* start the watchdog. */ 1524 hw->mac.get_link_status = 1; 1525 schedule_work(&adapter->watchdog_task); 1526 1527 return 0; 1528 } 1529 1530 void igb_down(struct igb_adapter *adapter) 1531 { 1532 struct net_device *netdev = adapter->netdev; 1533 struct e1000_hw *hw = &adapter->hw; 1534 u32 tctl, rctl; 1535 int i; 1536 1537 /* signal that we're down so the interrupt handler does not 1538 * reschedule our watchdog timer */ 1539 set_bit(__IGB_DOWN, &adapter->state); 1540 1541 /* disable receives in the hardware */ 1542 rctl = rd32(E1000_RCTL); 1543 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1544 /* flush and sleep below */ 1545 1546 netif_tx_stop_all_queues(netdev); 1547 1548 /* disable transmits in the hardware */ 1549 tctl = rd32(E1000_TCTL); 1550 tctl &= ~E1000_TCTL_EN; 1551 wr32(E1000_TCTL, tctl); 1552 /* flush both disables and wait for them to finish */ 1553 wrfl(); 1554 msleep(10); 1555 1556 for (i = 0; i < adapter->num_q_vectors; i++) 1557 napi_disable(&(adapter->q_vector[i]->napi)); 1558 1559 igb_irq_disable(adapter); 1560 1561 del_timer_sync(&adapter->watchdog_timer); 1562 del_timer_sync(&adapter->phy_info_timer); 1563 1564 netif_carrier_off(netdev); 1565 1566 /* record the stats before reset*/ 1567 spin_lock(&adapter->stats64_lock); 1568 igb_update_stats(adapter, &adapter->stats64); 1569 spin_unlock(&adapter->stats64_lock); 1570 1571 adapter->link_speed = 0; 1572 adapter->link_duplex = 0; 1573 1574 if (!pci_channel_offline(adapter->pdev)) 1575 igb_reset(adapter); 1576 igb_clean_all_tx_rings(adapter); 1577 igb_clean_all_rx_rings(adapter); 1578 #ifdef CONFIG_IGB_DCA 1579 1580 /* since we reset the hardware DCA settings were cleared */ 1581 igb_setup_dca(adapter); 1582 #endif 1583 } 1584 1585 void igb_reinit_locked(struct igb_adapter *adapter) 1586 { 1587 WARN_ON(in_interrupt()); 1588 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1589 msleep(1); 1590 igb_down(adapter); 1591 igb_up(adapter); 1592 clear_bit(__IGB_RESETTING, &adapter->state); 1593 } 1594 1595 void igb_reset(struct igb_adapter *adapter) 1596 { 1597 struct pci_dev *pdev = adapter->pdev; 1598 struct e1000_hw *hw = &adapter->hw; 1599 struct e1000_mac_info *mac = &hw->mac; 1600 struct e1000_fc_info *fc = &hw->fc; 1601 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1602 1603 /* Repartition Pba for greater than 9k mtu 1604 * To take effect CTRL.RST is required. 1605 */ 1606 switch (mac->type) { 1607 case e1000_i350: 1608 case e1000_82580: 1609 pba = rd32(E1000_RXPBS); 1610 pba = igb_rxpbs_adjust_82580(pba); 1611 break; 1612 case e1000_82576: 1613 pba = rd32(E1000_RXPBS); 1614 pba &= E1000_RXPBS_SIZE_MASK_82576; 1615 break; 1616 case e1000_82575: 1617 case e1000_i210: 1618 case e1000_i211: 1619 default: 1620 pba = E1000_PBA_34K; 1621 break; 1622 } 1623 1624 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1625 (mac->type < e1000_82576)) { 1626 /* adjust PBA for jumbo frames */ 1627 wr32(E1000_PBA, pba); 1628 1629 /* To maintain wire speed transmits, the Tx FIFO should be 1630 * large enough to accommodate two full transmit packets, 1631 * rounded up to the next 1KB and expressed in KB. Likewise, 1632 * the Rx FIFO should be large enough to accommodate at least 1633 * one full receive packet and is similarly rounded up and 1634 * expressed in KB. */ 1635 pba = rd32(E1000_PBA); 1636 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1637 tx_space = pba >> 16; 1638 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1639 pba &= 0xffff; 1640 /* the tx fifo also stores 16 bytes of information about the tx 1641 * but don't include ethernet FCS because hardware appends it */ 1642 min_tx_space = (adapter->max_frame_size + 1643 sizeof(union e1000_adv_tx_desc) - 1644 ETH_FCS_LEN) * 2; 1645 min_tx_space = ALIGN(min_tx_space, 1024); 1646 min_tx_space >>= 10; 1647 /* software strips receive CRC, so leave room for it */ 1648 min_rx_space = adapter->max_frame_size; 1649 min_rx_space = ALIGN(min_rx_space, 1024); 1650 min_rx_space >>= 10; 1651 1652 /* If current Tx allocation is less than the min Tx FIFO size, 1653 * and the min Tx FIFO size is less than the current Rx FIFO 1654 * allocation, take space away from current Rx allocation */ 1655 if (tx_space < min_tx_space && 1656 ((min_tx_space - tx_space) < pba)) { 1657 pba = pba - (min_tx_space - tx_space); 1658 1659 /* if short on rx space, rx wins and must trump tx 1660 * adjustment */ 1661 if (pba < min_rx_space) 1662 pba = min_rx_space; 1663 } 1664 wr32(E1000_PBA, pba); 1665 } 1666 1667 /* flow control settings */ 1668 /* The high water mark must be low enough to fit one full frame 1669 * (or the size used for early receive) above it in the Rx FIFO. 1670 * Set it to the lower of: 1671 * - 90% of the Rx FIFO size, or 1672 * - the full Rx FIFO size minus one full frame */ 1673 hwm = min(((pba << 10) * 9 / 10), 1674 ((pba << 10) - 2 * adapter->max_frame_size)); 1675 1676 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1677 fc->low_water = fc->high_water - 16; 1678 fc->pause_time = 0xFFFF; 1679 fc->send_xon = 1; 1680 fc->current_mode = fc->requested_mode; 1681 1682 /* disable receive for all VFs and wait one second */ 1683 if (adapter->vfs_allocated_count) { 1684 int i; 1685 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1686 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1687 1688 /* ping all the active vfs to let them know we are going down */ 1689 igb_ping_all_vfs(adapter); 1690 1691 /* disable transmits and receives */ 1692 wr32(E1000_VFRE, 0); 1693 wr32(E1000_VFTE, 0); 1694 } 1695 1696 /* Allow time for pending master requests to run */ 1697 hw->mac.ops.reset_hw(hw); 1698 wr32(E1000_WUC, 0); 1699 1700 if (hw->mac.ops.init_hw(hw)) 1701 dev_err(&pdev->dev, "Hardware Error\n"); 1702 1703 /* 1704 * Flow control settings reset on hardware reset, so guarantee flow 1705 * control is off when forcing speed. 1706 */ 1707 if (!hw->mac.autoneg) 1708 igb_force_mac_fc(hw); 1709 1710 igb_init_dmac(adapter, pba); 1711 if (!netif_running(adapter->netdev)) 1712 igb_power_down_link(adapter); 1713 1714 igb_update_mng_vlan(adapter); 1715 1716 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1717 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1718 1719 /* Re-enable PTP, where applicable. */ 1720 igb_ptp_reset(adapter); 1721 1722 igb_get_phy_info(hw); 1723 } 1724 1725 static netdev_features_t igb_fix_features(struct net_device *netdev, 1726 netdev_features_t features) 1727 { 1728 /* 1729 * Since there is no support for separate rx/tx vlan accel 1730 * enable/disable make sure tx flag is always in same state as rx. 1731 */ 1732 if (features & NETIF_F_HW_VLAN_RX) 1733 features |= NETIF_F_HW_VLAN_TX; 1734 else 1735 features &= ~NETIF_F_HW_VLAN_TX; 1736 1737 return features; 1738 } 1739 1740 static int igb_set_features(struct net_device *netdev, 1741 netdev_features_t features) 1742 { 1743 netdev_features_t changed = netdev->features ^ features; 1744 struct igb_adapter *adapter = netdev_priv(netdev); 1745 1746 if (changed & NETIF_F_HW_VLAN_RX) 1747 igb_vlan_mode(netdev, features); 1748 1749 if (!(changed & NETIF_F_RXALL)) 1750 return 0; 1751 1752 netdev->features = features; 1753 1754 if (netif_running(netdev)) 1755 igb_reinit_locked(adapter); 1756 else 1757 igb_reset(adapter); 1758 1759 return 0; 1760 } 1761 1762 static const struct net_device_ops igb_netdev_ops = { 1763 .ndo_open = igb_open, 1764 .ndo_stop = igb_close, 1765 .ndo_start_xmit = igb_xmit_frame, 1766 .ndo_get_stats64 = igb_get_stats64, 1767 .ndo_set_rx_mode = igb_set_rx_mode, 1768 .ndo_set_mac_address = igb_set_mac, 1769 .ndo_change_mtu = igb_change_mtu, 1770 .ndo_do_ioctl = igb_ioctl, 1771 .ndo_tx_timeout = igb_tx_timeout, 1772 .ndo_validate_addr = eth_validate_addr, 1773 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 1774 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 1775 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 1776 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 1777 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 1778 .ndo_get_vf_config = igb_ndo_get_vf_config, 1779 #ifdef CONFIG_NET_POLL_CONTROLLER 1780 .ndo_poll_controller = igb_netpoll, 1781 #endif 1782 .ndo_fix_features = igb_fix_features, 1783 .ndo_set_features = igb_set_features, 1784 }; 1785 1786 /** 1787 * igb_set_fw_version - Configure version string for ethtool 1788 * @adapter: adapter struct 1789 * 1790 **/ 1791 void igb_set_fw_version(struct igb_adapter *adapter) 1792 { 1793 struct e1000_hw *hw = &adapter->hw; 1794 struct e1000_fw_version fw; 1795 1796 igb_get_fw_version(hw, &fw); 1797 1798 switch (hw->mac.type) { 1799 case e1000_i211: 1800 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1801 "%2d.%2d-%d", 1802 fw.invm_major, fw.invm_minor, fw.invm_img_type); 1803 break; 1804 1805 default: 1806 /* if option is rom valid, display its version too */ 1807 if (fw.or_valid) { 1808 snprintf(adapter->fw_version, 1809 sizeof(adapter->fw_version), 1810 "%d.%d, 0x%08x, %d.%d.%d", 1811 fw.eep_major, fw.eep_minor, fw.etrack_id, 1812 fw.or_major, fw.or_build, fw.or_patch); 1813 /* no option rom */ 1814 } else { 1815 snprintf(adapter->fw_version, 1816 sizeof(adapter->fw_version), 1817 "%d.%d, 0x%08x", 1818 fw.eep_major, fw.eep_minor, fw.etrack_id); 1819 } 1820 break; 1821 } 1822 return; 1823 } 1824 1825 /** 1826 * igb_probe - Device Initialization Routine 1827 * @pdev: PCI device information struct 1828 * @ent: entry in igb_pci_tbl 1829 * 1830 * Returns 0 on success, negative on failure 1831 * 1832 * igb_probe initializes an adapter identified by a pci_dev structure. 1833 * The OS initialization, configuring of the adapter private structure, 1834 * and a hardware reset occur. 1835 **/ 1836 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1837 { 1838 struct net_device *netdev; 1839 struct igb_adapter *adapter; 1840 struct e1000_hw *hw; 1841 u16 eeprom_data = 0; 1842 s32 ret_val; 1843 static int global_quad_port_a; /* global quad port a indication */ 1844 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 1845 unsigned long mmio_start, mmio_len; 1846 int err, pci_using_dac; 1847 u8 part_str[E1000_PBANUM_LENGTH]; 1848 1849 /* Catch broken hardware that put the wrong VF device ID in 1850 * the PCIe SR-IOV capability. 1851 */ 1852 if (pdev->is_virtfn) { 1853 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1854 pci_name(pdev), pdev->vendor, pdev->device); 1855 return -EINVAL; 1856 } 1857 1858 err = pci_enable_device_mem(pdev); 1859 if (err) 1860 return err; 1861 1862 pci_using_dac = 0; 1863 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1864 if (!err) { 1865 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 1866 if (!err) 1867 pci_using_dac = 1; 1868 } else { 1869 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1870 if (err) { 1871 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1872 if (err) { 1873 dev_err(&pdev->dev, "No usable DMA " 1874 "configuration, aborting\n"); 1875 goto err_dma; 1876 } 1877 } 1878 } 1879 1880 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 1881 IORESOURCE_MEM), 1882 igb_driver_name); 1883 if (err) 1884 goto err_pci_reg; 1885 1886 pci_enable_pcie_error_reporting(pdev); 1887 1888 pci_set_master(pdev); 1889 pci_save_state(pdev); 1890 1891 err = -ENOMEM; 1892 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 1893 IGB_MAX_TX_QUEUES); 1894 if (!netdev) 1895 goto err_alloc_etherdev; 1896 1897 SET_NETDEV_DEV(netdev, &pdev->dev); 1898 1899 pci_set_drvdata(pdev, netdev); 1900 adapter = netdev_priv(netdev); 1901 adapter->netdev = netdev; 1902 adapter->pdev = pdev; 1903 hw = &adapter->hw; 1904 hw->back = adapter; 1905 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1906 1907 mmio_start = pci_resource_start(pdev, 0); 1908 mmio_len = pci_resource_len(pdev, 0); 1909 1910 err = -EIO; 1911 hw->hw_addr = ioremap(mmio_start, mmio_len); 1912 if (!hw->hw_addr) 1913 goto err_ioremap; 1914 1915 netdev->netdev_ops = &igb_netdev_ops; 1916 igb_set_ethtool_ops(netdev); 1917 netdev->watchdog_timeo = 5 * HZ; 1918 1919 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1920 1921 netdev->mem_start = mmio_start; 1922 netdev->mem_end = mmio_start + mmio_len; 1923 1924 /* PCI config space info */ 1925 hw->vendor_id = pdev->vendor; 1926 hw->device_id = pdev->device; 1927 hw->revision_id = pdev->revision; 1928 hw->subsystem_vendor_id = pdev->subsystem_vendor; 1929 hw->subsystem_device_id = pdev->subsystem_device; 1930 1931 /* Copy the default MAC, PHY and NVM function pointers */ 1932 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 1933 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 1934 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 1935 /* Initialize skew-specific constants */ 1936 err = ei->get_invariants(hw); 1937 if (err) 1938 goto err_sw_init; 1939 1940 /* setup the private structure */ 1941 err = igb_sw_init(adapter); 1942 if (err) 1943 goto err_sw_init; 1944 1945 igb_get_bus_info_pcie(hw); 1946 1947 hw->phy.autoneg_wait_to_complete = false; 1948 1949 /* Copper options */ 1950 if (hw->phy.media_type == e1000_media_type_copper) { 1951 hw->phy.mdix = AUTO_ALL_MODES; 1952 hw->phy.disable_polarity_correction = false; 1953 hw->phy.ms_type = e1000_ms_hw_default; 1954 } 1955 1956 if (igb_check_reset_block(hw)) 1957 dev_info(&pdev->dev, 1958 "PHY reset is blocked due to SOL/IDER session.\n"); 1959 1960 /* 1961 * features is initialized to 0 in allocation, it might have bits 1962 * set by igb_sw_init so we should use an or instead of an 1963 * assignment. 1964 */ 1965 netdev->features |= NETIF_F_SG | 1966 NETIF_F_IP_CSUM | 1967 NETIF_F_IPV6_CSUM | 1968 NETIF_F_TSO | 1969 NETIF_F_TSO6 | 1970 NETIF_F_RXHASH | 1971 NETIF_F_RXCSUM | 1972 NETIF_F_HW_VLAN_RX | 1973 NETIF_F_HW_VLAN_TX; 1974 1975 /* copy netdev features into list of user selectable features */ 1976 netdev->hw_features |= netdev->features; 1977 netdev->hw_features |= NETIF_F_RXALL; 1978 1979 /* set this bit last since it cannot be part of hw_features */ 1980 netdev->features |= NETIF_F_HW_VLAN_FILTER; 1981 1982 netdev->vlan_features |= NETIF_F_TSO | 1983 NETIF_F_TSO6 | 1984 NETIF_F_IP_CSUM | 1985 NETIF_F_IPV6_CSUM | 1986 NETIF_F_SG; 1987 1988 netdev->priv_flags |= IFF_SUPP_NOFCS; 1989 1990 if (pci_using_dac) { 1991 netdev->features |= NETIF_F_HIGHDMA; 1992 netdev->vlan_features |= NETIF_F_HIGHDMA; 1993 } 1994 1995 if (hw->mac.type >= e1000_82576) { 1996 netdev->hw_features |= NETIF_F_SCTP_CSUM; 1997 netdev->features |= NETIF_F_SCTP_CSUM; 1998 } 1999 2000 netdev->priv_flags |= IFF_UNICAST_FLT; 2001 2002 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2003 2004 /* before reading the NVM, reset the controller to put the device in a 2005 * known good starting state */ 2006 hw->mac.ops.reset_hw(hw); 2007 2008 /* 2009 * make sure the NVM is good , i211 parts have special NVM that 2010 * doesn't contain a checksum 2011 */ 2012 if (hw->mac.type != e1000_i211) { 2013 if (hw->nvm.ops.validate(hw) < 0) { 2014 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2015 err = -EIO; 2016 goto err_eeprom; 2017 } 2018 } 2019 2020 /* copy the MAC address out of the NVM */ 2021 if (hw->mac.ops.read_mac_addr(hw)) 2022 dev_err(&pdev->dev, "NVM Read Error\n"); 2023 2024 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2025 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); 2026 2027 if (!is_valid_ether_addr(netdev->perm_addr)) { 2028 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2029 err = -EIO; 2030 goto err_eeprom; 2031 } 2032 2033 /* get firmware version for ethtool -i */ 2034 igb_set_fw_version(adapter); 2035 2036 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2037 (unsigned long) adapter); 2038 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2039 (unsigned long) adapter); 2040 2041 INIT_WORK(&adapter->reset_task, igb_reset_task); 2042 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2043 2044 /* Initialize link properties that are user-changeable */ 2045 adapter->fc_autoneg = true; 2046 hw->mac.autoneg = true; 2047 hw->phy.autoneg_advertised = 0x2f; 2048 2049 hw->fc.requested_mode = e1000_fc_default; 2050 hw->fc.current_mode = e1000_fc_default; 2051 2052 igb_validate_mdi_setting(hw); 2053 2054 /* By default, support wake on port A */ 2055 if (hw->bus.func == 0) 2056 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2057 2058 /* Check the NVM for wake support on non-port A ports */ 2059 if (hw->mac.type >= e1000_82580) 2060 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2061 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2062 &eeprom_data); 2063 else if (hw->bus.func == 1) 2064 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2065 2066 if (eeprom_data & IGB_EEPROM_APME) 2067 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2068 2069 /* now that we have the eeprom settings, apply the special cases where 2070 * the eeprom may be wrong or the board simply won't support wake on 2071 * lan on a particular port */ 2072 switch (pdev->device) { 2073 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2074 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2075 break; 2076 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2077 case E1000_DEV_ID_82576_FIBER: 2078 case E1000_DEV_ID_82576_SERDES: 2079 /* Wake events only supported on port A for dual fiber 2080 * regardless of eeprom setting */ 2081 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2082 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2083 break; 2084 case E1000_DEV_ID_82576_QUAD_COPPER: 2085 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2086 /* if quad port adapter, disable WoL on all but port A */ 2087 if (global_quad_port_a != 0) 2088 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2089 else 2090 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2091 /* Reset for multiple quad port adapters */ 2092 if (++global_quad_port_a == 4) 2093 global_quad_port_a = 0; 2094 break; 2095 default: 2096 /* If the device can't wake, don't set software support */ 2097 if (!device_can_wakeup(&adapter->pdev->dev)) 2098 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2099 } 2100 2101 /* initialize the wol settings based on the eeprom settings */ 2102 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2103 adapter->wol |= E1000_WUFC_MAG; 2104 2105 /* Some vendors want WoL disabled by default, but still supported */ 2106 if ((hw->mac.type == e1000_i350) && 2107 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2108 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2109 adapter->wol = 0; 2110 } 2111 2112 device_set_wakeup_enable(&adapter->pdev->dev, 2113 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2114 2115 /* reset the hardware with the new settings */ 2116 igb_reset(adapter); 2117 2118 /* let the f/w know that the h/w is now under the control of the 2119 * driver. */ 2120 igb_get_hw_control(adapter); 2121 2122 strcpy(netdev->name, "eth%d"); 2123 err = register_netdev(netdev); 2124 if (err) 2125 goto err_register; 2126 2127 /* carrier off reporting is important to ethtool even BEFORE open */ 2128 netif_carrier_off(netdev); 2129 2130 #ifdef CONFIG_IGB_DCA 2131 if (dca_add_requester(&pdev->dev) == 0) { 2132 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2133 dev_info(&pdev->dev, "DCA enabled\n"); 2134 igb_setup_dca(adapter); 2135 } 2136 2137 #endif 2138 2139 /* do hw tstamp init after resetting */ 2140 igb_ptp_init(adapter); 2141 2142 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2143 /* print bus type/speed/width info */ 2144 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2145 netdev->name, 2146 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2147 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2148 "unknown"), 2149 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 2150 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : 2151 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : 2152 "unknown"), 2153 netdev->dev_addr); 2154 2155 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); 2156 if (ret_val) 2157 strcpy(part_str, "Unknown"); 2158 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2159 dev_info(&pdev->dev, 2160 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2161 adapter->msix_entries ? "MSI-X" : 2162 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2163 adapter->num_rx_queues, adapter->num_tx_queues); 2164 switch (hw->mac.type) { 2165 case e1000_i350: 2166 case e1000_i210: 2167 case e1000_i211: 2168 igb_set_eee_i350(hw); 2169 break; 2170 default: 2171 break; 2172 } 2173 2174 pm_runtime_put_noidle(&pdev->dev); 2175 return 0; 2176 2177 err_register: 2178 igb_release_hw_control(adapter); 2179 err_eeprom: 2180 if (!igb_check_reset_block(hw)) 2181 igb_reset_phy(hw); 2182 2183 if (hw->flash_address) 2184 iounmap(hw->flash_address); 2185 err_sw_init: 2186 igb_clear_interrupt_scheme(adapter); 2187 iounmap(hw->hw_addr); 2188 err_ioremap: 2189 free_netdev(netdev); 2190 err_alloc_etherdev: 2191 pci_release_selected_regions(pdev, 2192 pci_select_bars(pdev, IORESOURCE_MEM)); 2193 err_pci_reg: 2194 err_dma: 2195 pci_disable_device(pdev); 2196 return err; 2197 } 2198 2199 /** 2200 * igb_remove - Device Removal Routine 2201 * @pdev: PCI device information struct 2202 * 2203 * igb_remove is called by the PCI subsystem to alert the driver 2204 * that it should release a PCI device. The could be caused by a 2205 * Hot-Plug event, or because the driver is going to be removed from 2206 * memory. 2207 **/ 2208 static void igb_remove(struct pci_dev *pdev) 2209 { 2210 struct net_device *netdev = pci_get_drvdata(pdev); 2211 struct igb_adapter *adapter = netdev_priv(netdev); 2212 struct e1000_hw *hw = &adapter->hw; 2213 2214 pm_runtime_get_noresume(&pdev->dev); 2215 igb_ptp_stop(adapter); 2216 2217 /* 2218 * The watchdog timer may be rescheduled, so explicitly 2219 * disable watchdog from being rescheduled. 2220 */ 2221 set_bit(__IGB_DOWN, &adapter->state); 2222 del_timer_sync(&adapter->watchdog_timer); 2223 del_timer_sync(&adapter->phy_info_timer); 2224 2225 cancel_work_sync(&adapter->reset_task); 2226 cancel_work_sync(&adapter->watchdog_task); 2227 2228 #ifdef CONFIG_IGB_DCA 2229 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2230 dev_info(&pdev->dev, "DCA disabled\n"); 2231 dca_remove_requester(&pdev->dev); 2232 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2233 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2234 } 2235 #endif 2236 2237 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2238 * would have already happened in close and is redundant. */ 2239 igb_release_hw_control(adapter); 2240 2241 unregister_netdev(netdev); 2242 2243 igb_clear_interrupt_scheme(adapter); 2244 2245 #ifdef CONFIG_PCI_IOV 2246 /* reclaim resources allocated to VFs */ 2247 if (adapter->vf_data) { 2248 /* disable iov and allow time for transactions to clear */ 2249 if (igb_vfs_are_assigned(adapter)) { 2250 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2251 } else { 2252 pci_disable_sriov(pdev); 2253 msleep(500); 2254 } 2255 2256 kfree(adapter->vf_data); 2257 adapter->vf_data = NULL; 2258 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2259 wrfl(); 2260 msleep(100); 2261 dev_info(&pdev->dev, "IOV Disabled\n"); 2262 } 2263 #endif 2264 2265 iounmap(hw->hw_addr); 2266 if (hw->flash_address) 2267 iounmap(hw->flash_address); 2268 pci_release_selected_regions(pdev, 2269 pci_select_bars(pdev, IORESOURCE_MEM)); 2270 2271 kfree(adapter->shadow_vfta); 2272 free_netdev(netdev); 2273 2274 pci_disable_pcie_error_reporting(pdev); 2275 2276 pci_disable_device(pdev); 2277 } 2278 2279 /** 2280 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2281 * @adapter: board private structure to initialize 2282 * 2283 * This function initializes the vf specific data storage and then attempts to 2284 * allocate the VFs. The reason for ordering it this way is because it is much 2285 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2286 * the memory for the VFs. 2287 **/ 2288 static void igb_probe_vfs(struct igb_adapter *adapter) 2289 { 2290 #ifdef CONFIG_PCI_IOV 2291 struct pci_dev *pdev = adapter->pdev; 2292 struct e1000_hw *hw = &adapter->hw; 2293 int old_vfs = pci_num_vf(adapter->pdev); 2294 int i; 2295 2296 /* Virtualization features not supported on i210 family. */ 2297 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2298 return; 2299 2300 if (old_vfs) { 2301 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2302 "max_vfs setting of %d\n", old_vfs, max_vfs); 2303 adapter->vfs_allocated_count = old_vfs; 2304 } 2305 2306 if (!adapter->vfs_allocated_count) 2307 return; 2308 2309 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2310 sizeof(struct vf_data_storage), GFP_KERNEL); 2311 2312 /* if allocation failed then we do not support SR-IOV */ 2313 if (!adapter->vf_data) { 2314 adapter->vfs_allocated_count = 0; 2315 dev_err(&pdev->dev, "Unable to allocate memory for VF " 2316 "Data Storage\n"); 2317 goto out; 2318 } 2319 2320 if (!old_vfs) { 2321 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) 2322 goto err_out; 2323 } 2324 dev_info(&pdev->dev, "%d VFs allocated\n", 2325 adapter->vfs_allocated_count); 2326 for (i = 0; i < adapter->vfs_allocated_count; i++) 2327 igb_vf_configure(adapter, i); 2328 2329 /* DMA Coalescing is not supported in IOV mode. */ 2330 adapter->flags &= ~IGB_FLAG_DMAC; 2331 goto out; 2332 err_out: 2333 kfree(adapter->vf_data); 2334 adapter->vf_data = NULL; 2335 adapter->vfs_allocated_count = 0; 2336 out: 2337 return; 2338 #endif /* CONFIG_PCI_IOV */ 2339 } 2340 2341 /** 2342 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2343 * @adapter: board private structure to initialize 2344 * 2345 * igb_sw_init initializes the Adapter private data structure. 2346 * Fields are initialized based on PCI device information and 2347 * OS network device settings (MTU size). 2348 **/ 2349 static int igb_sw_init(struct igb_adapter *adapter) 2350 { 2351 struct e1000_hw *hw = &adapter->hw; 2352 struct net_device *netdev = adapter->netdev; 2353 struct pci_dev *pdev = adapter->pdev; 2354 u32 max_rss_queues; 2355 2356 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2357 2358 /* set default ring sizes */ 2359 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2360 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2361 2362 /* set default ITR values */ 2363 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2364 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2365 2366 /* set default work limits */ 2367 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2368 2369 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2370 VLAN_HLEN; 2371 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2372 2373 spin_lock_init(&adapter->stats64_lock); 2374 #ifdef CONFIG_PCI_IOV 2375 switch (hw->mac.type) { 2376 case e1000_82576: 2377 case e1000_i350: 2378 if (max_vfs > 7) { 2379 dev_warn(&pdev->dev, 2380 "Maximum of 7 VFs per PF, using max\n"); 2381 adapter->vfs_allocated_count = 7; 2382 } else 2383 adapter->vfs_allocated_count = max_vfs; 2384 break; 2385 default: 2386 break; 2387 } 2388 #endif /* CONFIG_PCI_IOV */ 2389 2390 /* Determine the maximum number of RSS queues supported. */ 2391 switch (hw->mac.type) { 2392 case e1000_i211: 2393 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2394 break; 2395 case e1000_82575: 2396 case e1000_i210: 2397 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2398 break; 2399 case e1000_i350: 2400 /* I350 cannot do RSS and SR-IOV at the same time */ 2401 if (!!adapter->vfs_allocated_count) { 2402 max_rss_queues = 1; 2403 break; 2404 } 2405 /* fall through */ 2406 case e1000_82576: 2407 if (!!adapter->vfs_allocated_count) { 2408 max_rss_queues = 2; 2409 break; 2410 } 2411 /* fall through */ 2412 case e1000_82580: 2413 default: 2414 max_rss_queues = IGB_MAX_RX_QUEUES; 2415 break; 2416 } 2417 2418 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2419 2420 /* Determine if we need to pair queues. */ 2421 switch (hw->mac.type) { 2422 case e1000_82575: 2423 case e1000_i211: 2424 /* Device supports enough interrupts without queue pairing. */ 2425 break; 2426 case e1000_82576: 2427 /* 2428 * If VFs are going to be allocated with RSS queues then we 2429 * should pair the queues in order to conserve interrupts due 2430 * to limited supply. 2431 */ 2432 if ((adapter->rss_queues > 1) && 2433 (adapter->vfs_allocated_count > 6)) 2434 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2435 /* fall through */ 2436 case e1000_82580: 2437 case e1000_i350: 2438 case e1000_i210: 2439 default: 2440 /* 2441 * If rss_queues > half of max_rss_queues, pair the queues in 2442 * order to conserve interrupts due to limited supply. 2443 */ 2444 if (adapter->rss_queues > (max_rss_queues / 2)) 2445 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2446 break; 2447 } 2448 2449 /* Setup and initialize a copy of the hw vlan table array */ 2450 adapter->shadow_vfta = kzalloc(sizeof(u32) * 2451 E1000_VLAN_FILTER_TBL_SIZE, 2452 GFP_ATOMIC); 2453 2454 /* This call may decrease the number of queues */ 2455 if (igb_init_interrupt_scheme(adapter, true)) { 2456 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2457 return -ENOMEM; 2458 } 2459 2460 igb_probe_vfs(adapter); 2461 2462 /* Explicitly disable IRQ since the NIC can be in any state. */ 2463 igb_irq_disable(adapter); 2464 2465 if (hw->mac.type >= e1000_i350) 2466 adapter->flags &= ~IGB_FLAG_DMAC; 2467 2468 set_bit(__IGB_DOWN, &adapter->state); 2469 return 0; 2470 } 2471 2472 /** 2473 * igb_open - Called when a network interface is made active 2474 * @netdev: network interface device structure 2475 * 2476 * Returns 0 on success, negative value on failure 2477 * 2478 * The open entry point is called when a network interface is made 2479 * active by the system (IFF_UP). At this point all resources needed 2480 * for transmit and receive operations are allocated, the interrupt 2481 * handler is registered with the OS, the watchdog timer is started, 2482 * and the stack is notified that the interface is ready. 2483 **/ 2484 static int __igb_open(struct net_device *netdev, bool resuming) 2485 { 2486 struct igb_adapter *adapter = netdev_priv(netdev); 2487 struct e1000_hw *hw = &adapter->hw; 2488 struct pci_dev *pdev = adapter->pdev; 2489 int err; 2490 int i; 2491 2492 /* disallow open during test */ 2493 if (test_bit(__IGB_TESTING, &adapter->state)) { 2494 WARN_ON(resuming); 2495 return -EBUSY; 2496 } 2497 2498 if (!resuming) 2499 pm_runtime_get_sync(&pdev->dev); 2500 2501 netif_carrier_off(netdev); 2502 2503 /* allocate transmit descriptors */ 2504 err = igb_setup_all_tx_resources(adapter); 2505 if (err) 2506 goto err_setup_tx; 2507 2508 /* allocate receive descriptors */ 2509 err = igb_setup_all_rx_resources(adapter); 2510 if (err) 2511 goto err_setup_rx; 2512 2513 igb_power_up_link(adapter); 2514 2515 /* before we allocate an interrupt, we must be ready to handle it. 2516 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2517 * as soon as we call pci_request_irq, so we have to setup our 2518 * clean_rx handler before we do so. */ 2519 igb_configure(adapter); 2520 2521 err = igb_request_irq(adapter); 2522 if (err) 2523 goto err_req_irq; 2524 2525 /* Notify the stack of the actual queue counts. */ 2526 err = netif_set_real_num_tx_queues(adapter->netdev, 2527 adapter->num_tx_queues); 2528 if (err) 2529 goto err_set_queues; 2530 2531 err = netif_set_real_num_rx_queues(adapter->netdev, 2532 adapter->num_rx_queues); 2533 if (err) 2534 goto err_set_queues; 2535 2536 /* From here on the code is the same as igb_up() */ 2537 clear_bit(__IGB_DOWN, &adapter->state); 2538 2539 for (i = 0; i < adapter->num_q_vectors; i++) 2540 napi_enable(&(adapter->q_vector[i]->napi)); 2541 2542 /* Clear any pending interrupts. */ 2543 rd32(E1000_ICR); 2544 2545 igb_irq_enable(adapter); 2546 2547 /* notify VFs that reset has been completed */ 2548 if (adapter->vfs_allocated_count) { 2549 u32 reg_data = rd32(E1000_CTRL_EXT); 2550 reg_data |= E1000_CTRL_EXT_PFRSTD; 2551 wr32(E1000_CTRL_EXT, reg_data); 2552 } 2553 2554 netif_tx_start_all_queues(netdev); 2555 2556 if (!resuming) 2557 pm_runtime_put(&pdev->dev); 2558 2559 /* start the watchdog. */ 2560 hw->mac.get_link_status = 1; 2561 schedule_work(&adapter->watchdog_task); 2562 2563 return 0; 2564 2565 err_set_queues: 2566 igb_free_irq(adapter); 2567 err_req_irq: 2568 igb_release_hw_control(adapter); 2569 igb_power_down_link(adapter); 2570 igb_free_all_rx_resources(adapter); 2571 err_setup_rx: 2572 igb_free_all_tx_resources(adapter); 2573 err_setup_tx: 2574 igb_reset(adapter); 2575 if (!resuming) 2576 pm_runtime_put(&pdev->dev); 2577 2578 return err; 2579 } 2580 2581 static int igb_open(struct net_device *netdev) 2582 { 2583 return __igb_open(netdev, false); 2584 } 2585 2586 /** 2587 * igb_close - Disables a network interface 2588 * @netdev: network interface device structure 2589 * 2590 * Returns 0, this is not allowed to fail 2591 * 2592 * The close entry point is called when an interface is de-activated 2593 * by the OS. The hardware is still under the driver's control, but 2594 * needs to be disabled. A global MAC reset is issued to stop the 2595 * hardware, and all transmit and receive resources are freed. 2596 **/ 2597 static int __igb_close(struct net_device *netdev, bool suspending) 2598 { 2599 struct igb_adapter *adapter = netdev_priv(netdev); 2600 struct pci_dev *pdev = adapter->pdev; 2601 2602 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 2603 2604 if (!suspending) 2605 pm_runtime_get_sync(&pdev->dev); 2606 2607 igb_down(adapter); 2608 igb_free_irq(adapter); 2609 2610 igb_free_all_tx_resources(adapter); 2611 igb_free_all_rx_resources(adapter); 2612 2613 if (!suspending) 2614 pm_runtime_put_sync(&pdev->dev); 2615 return 0; 2616 } 2617 2618 static int igb_close(struct net_device *netdev) 2619 { 2620 return __igb_close(netdev, false); 2621 } 2622 2623 /** 2624 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 2625 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2626 * 2627 * Return 0 on success, negative on failure 2628 **/ 2629 int igb_setup_tx_resources(struct igb_ring *tx_ring) 2630 { 2631 struct device *dev = tx_ring->dev; 2632 int size; 2633 2634 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 2635 2636 tx_ring->tx_buffer_info = vzalloc(size); 2637 if (!tx_ring->tx_buffer_info) 2638 goto err; 2639 2640 /* round up to nearest 4K */ 2641 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 2642 tx_ring->size = ALIGN(tx_ring->size, 4096); 2643 2644 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2645 &tx_ring->dma, GFP_KERNEL); 2646 if (!tx_ring->desc) 2647 goto err; 2648 2649 tx_ring->next_to_use = 0; 2650 tx_ring->next_to_clean = 0; 2651 2652 return 0; 2653 2654 err: 2655 vfree(tx_ring->tx_buffer_info); 2656 tx_ring->tx_buffer_info = NULL; 2657 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2658 return -ENOMEM; 2659 } 2660 2661 /** 2662 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 2663 * (Descriptors) for all queues 2664 * @adapter: board private structure 2665 * 2666 * Return 0 on success, negative on failure 2667 **/ 2668 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 2669 { 2670 struct pci_dev *pdev = adapter->pdev; 2671 int i, err = 0; 2672 2673 for (i = 0; i < adapter->num_tx_queues; i++) { 2674 err = igb_setup_tx_resources(adapter->tx_ring[i]); 2675 if (err) { 2676 dev_err(&pdev->dev, 2677 "Allocation for Tx Queue %u failed\n", i); 2678 for (i--; i >= 0; i--) 2679 igb_free_tx_resources(adapter->tx_ring[i]); 2680 break; 2681 } 2682 } 2683 2684 return err; 2685 } 2686 2687 /** 2688 * igb_setup_tctl - configure the transmit control registers 2689 * @adapter: Board private structure 2690 **/ 2691 void igb_setup_tctl(struct igb_adapter *adapter) 2692 { 2693 struct e1000_hw *hw = &adapter->hw; 2694 u32 tctl; 2695 2696 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 2697 wr32(E1000_TXDCTL(0), 0); 2698 2699 /* Program the Transmit Control Register */ 2700 tctl = rd32(E1000_TCTL); 2701 tctl &= ~E1000_TCTL_CT; 2702 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2703 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2704 2705 igb_config_collision_dist(hw); 2706 2707 /* Enable transmits */ 2708 tctl |= E1000_TCTL_EN; 2709 2710 wr32(E1000_TCTL, tctl); 2711 } 2712 2713 /** 2714 * igb_configure_tx_ring - Configure transmit ring after Reset 2715 * @adapter: board private structure 2716 * @ring: tx ring to configure 2717 * 2718 * Configure a transmit ring after a reset. 2719 **/ 2720 void igb_configure_tx_ring(struct igb_adapter *adapter, 2721 struct igb_ring *ring) 2722 { 2723 struct e1000_hw *hw = &adapter->hw; 2724 u32 txdctl = 0; 2725 u64 tdba = ring->dma; 2726 int reg_idx = ring->reg_idx; 2727 2728 /* disable the queue */ 2729 wr32(E1000_TXDCTL(reg_idx), 0); 2730 wrfl(); 2731 mdelay(10); 2732 2733 wr32(E1000_TDLEN(reg_idx), 2734 ring->count * sizeof(union e1000_adv_tx_desc)); 2735 wr32(E1000_TDBAL(reg_idx), 2736 tdba & 0x00000000ffffffffULL); 2737 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2738 2739 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2740 wr32(E1000_TDH(reg_idx), 0); 2741 writel(0, ring->tail); 2742 2743 txdctl |= IGB_TX_PTHRESH; 2744 txdctl |= IGB_TX_HTHRESH << 8; 2745 txdctl |= IGB_TX_WTHRESH << 16; 2746 2747 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 2748 wr32(E1000_TXDCTL(reg_idx), txdctl); 2749 } 2750 2751 /** 2752 * igb_configure_tx - Configure transmit Unit after Reset 2753 * @adapter: board private structure 2754 * 2755 * Configure the Tx unit of the MAC after a reset. 2756 **/ 2757 static void igb_configure_tx(struct igb_adapter *adapter) 2758 { 2759 int i; 2760 2761 for (i = 0; i < adapter->num_tx_queues; i++) 2762 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 2763 } 2764 2765 /** 2766 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 2767 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2768 * 2769 * Returns 0 on success, negative on failure 2770 **/ 2771 int igb_setup_rx_resources(struct igb_ring *rx_ring) 2772 { 2773 struct device *dev = rx_ring->dev; 2774 int size; 2775 2776 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 2777 2778 rx_ring->rx_buffer_info = vzalloc(size); 2779 if (!rx_ring->rx_buffer_info) 2780 goto err; 2781 2782 /* Round up to nearest 4K */ 2783 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 2784 rx_ring->size = ALIGN(rx_ring->size, 4096); 2785 2786 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2787 &rx_ring->dma, GFP_KERNEL); 2788 if (!rx_ring->desc) 2789 goto err; 2790 2791 rx_ring->next_to_alloc = 0; 2792 rx_ring->next_to_clean = 0; 2793 rx_ring->next_to_use = 0; 2794 2795 return 0; 2796 2797 err: 2798 vfree(rx_ring->rx_buffer_info); 2799 rx_ring->rx_buffer_info = NULL; 2800 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2801 return -ENOMEM; 2802 } 2803 2804 /** 2805 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 2806 * (Descriptors) for all queues 2807 * @adapter: board private structure 2808 * 2809 * Return 0 on success, negative on failure 2810 **/ 2811 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 2812 { 2813 struct pci_dev *pdev = adapter->pdev; 2814 int i, err = 0; 2815 2816 for (i = 0; i < adapter->num_rx_queues; i++) { 2817 err = igb_setup_rx_resources(adapter->rx_ring[i]); 2818 if (err) { 2819 dev_err(&pdev->dev, 2820 "Allocation for Rx Queue %u failed\n", i); 2821 for (i--; i >= 0; i--) 2822 igb_free_rx_resources(adapter->rx_ring[i]); 2823 break; 2824 } 2825 } 2826 2827 return err; 2828 } 2829 2830 /** 2831 * igb_setup_mrqc - configure the multiple receive queue control registers 2832 * @adapter: Board private structure 2833 **/ 2834 static void igb_setup_mrqc(struct igb_adapter *adapter) 2835 { 2836 struct e1000_hw *hw = &adapter->hw; 2837 u32 mrqc, rxcsum; 2838 u32 j, num_rx_queues, shift = 0; 2839 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 2840 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 2841 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 2842 0xFA01ACBE }; 2843 2844 /* Fill out hash function seeds */ 2845 for (j = 0; j < 10; j++) 2846 wr32(E1000_RSSRK(j), rsskey[j]); 2847 2848 num_rx_queues = adapter->rss_queues; 2849 2850 switch (hw->mac.type) { 2851 case e1000_82575: 2852 shift = 6; 2853 break; 2854 case e1000_82576: 2855 /* 82576 supports 2 RSS queues for SR-IOV */ 2856 if (adapter->vfs_allocated_count) { 2857 shift = 3; 2858 num_rx_queues = 2; 2859 } 2860 break; 2861 default: 2862 break; 2863 } 2864 2865 /* 2866 * Populate the indirection table 4 entries at a time. To do this 2867 * we are generating the results for n and n+2 and then interleaving 2868 * those with the results with n+1 and n+3. 2869 */ 2870 for (j = 0; j < 32; j++) { 2871 /* first pass generates n and n+2 */ 2872 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; 2873 u32 reta = (base & 0x07800780) >> (7 - shift); 2874 2875 /* second pass generates n+1 and n+3 */ 2876 base += 0x00010001 * num_rx_queues; 2877 reta |= (base & 0x07800780) << (1 + shift); 2878 2879 wr32(E1000_RETA(j), reta); 2880 } 2881 2882 /* 2883 * Disable raw packet checksumming so that RSS hash is placed in 2884 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 2885 * offloads as they are enabled by default 2886 */ 2887 rxcsum = rd32(E1000_RXCSUM); 2888 rxcsum |= E1000_RXCSUM_PCSD; 2889 2890 if (adapter->hw.mac.type >= e1000_82576) 2891 /* Enable Receive Checksum Offload for SCTP */ 2892 rxcsum |= E1000_RXCSUM_CRCOFL; 2893 2894 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2895 wr32(E1000_RXCSUM, rxcsum); 2896 2897 /* Generate RSS hash based on packet types, TCP/UDP 2898 * port numbers and/or IPv4/v6 src and dst addresses 2899 */ 2900 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 2901 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2902 E1000_MRQC_RSS_FIELD_IPV6 | 2903 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2904 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 2905 2906 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2907 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2908 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2909 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2910 2911 /* If VMDq is enabled then we set the appropriate mode for that, else 2912 * we default to RSS so that an RSS hash is calculated per packet even 2913 * if we are only using one queue */ 2914 if (adapter->vfs_allocated_count) { 2915 if (hw->mac.type > e1000_82575) { 2916 /* Set the default pool for the PF's first queue */ 2917 u32 vtctl = rd32(E1000_VT_CTL); 2918 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 2919 E1000_VT_CTL_DISABLE_DEF_POOL); 2920 vtctl |= adapter->vfs_allocated_count << 2921 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 2922 wr32(E1000_VT_CTL, vtctl); 2923 } 2924 if (adapter->rss_queues > 1) 2925 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2926 else 2927 mrqc |= E1000_MRQC_ENABLE_VMDQ; 2928 } else { 2929 if (hw->mac.type != e1000_i211) 2930 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 2931 } 2932 igb_vmm_control(adapter); 2933 2934 wr32(E1000_MRQC, mrqc); 2935 } 2936 2937 /** 2938 * igb_setup_rctl - configure the receive control registers 2939 * @adapter: Board private structure 2940 **/ 2941 void igb_setup_rctl(struct igb_adapter *adapter) 2942 { 2943 struct e1000_hw *hw = &adapter->hw; 2944 u32 rctl; 2945 2946 rctl = rd32(E1000_RCTL); 2947 2948 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2949 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2950 2951 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 2952 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2953 2954 /* 2955 * enable stripping of CRC. It's unlikely this will break BMC 2956 * redirection as it did with e1000. Newer features require 2957 * that the HW strips the CRC. 2958 */ 2959 rctl |= E1000_RCTL_SECRC; 2960 2961 /* disable store bad packets and clear size bits. */ 2962 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 2963 2964 /* enable LPE to prevent packets larger than max_frame_size */ 2965 rctl |= E1000_RCTL_LPE; 2966 2967 /* disable queue 0 to prevent tail write w/o re-config */ 2968 wr32(E1000_RXDCTL(0), 0); 2969 2970 /* Attention!!! For SR-IOV PF driver operations you must enable 2971 * queue drop for all VF and PF queues to prevent head of line blocking 2972 * if an un-trusted VF does not provide descriptors to hardware. 2973 */ 2974 if (adapter->vfs_allocated_count) { 2975 /* set all queue drop enable bits */ 2976 wr32(E1000_QDE, ALL_QUEUES); 2977 } 2978 2979 /* This is useful for sniffing bad packets. */ 2980 if (adapter->netdev->features & NETIF_F_RXALL) { 2981 /* UPE and MPE will be handled by normal PROMISC logic 2982 * in e1000e_set_rx_mode */ 2983 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 2984 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 2985 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 2986 2987 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 2988 E1000_RCTL_DPF | /* Allow filtered pause */ 2989 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 2990 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 2991 * and that breaks VLANs. 2992 */ 2993 } 2994 2995 wr32(E1000_RCTL, rctl); 2996 } 2997 2998 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 2999 int vfn) 3000 { 3001 struct e1000_hw *hw = &adapter->hw; 3002 u32 vmolr; 3003 3004 /* if it isn't the PF check to see if VFs are enabled and 3005 * increase the size to support vlan tags */ 3006 if (vfn < adapter->vfs_allocated_count && 3007 adapter->vf_data[vfn].vlans_enabled) 3008 size += VLAN_TAG_SIZE; 3009 3010 vmolr = rd32(E1000_VMOLR(vfn)); 3011 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3012 vmolr |= size | E1000_VMOLR_LPE; 3013 wr32(E1000_VMOLR(vfn), vmolr); 3014 3015 return 0; 3016 } 3017 3018 /** 3019 * igb_rlpml_set - set maximum receive packet size 3020 * @adapter: board private structure 3021 * 3022 * Configure maximum receivable packet size. 3023 **/ 3024 static void igb_rlpml_set(struct igb_adapter *adapter) 3025 { 3026 u32 max_frame_size = adapter->max_frame_size; 3027 struct e1000_hw *hw = &adapter->hw; 3028 u16 pf_id = adapter->vfs_allocated_count; 3029 3030 if (pf_id) { 3031 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3032 /* 3033 * If we're in VMDQ or SR-IOV mode, then set global RLPML 3034 * to our max jumbo frame size, in case we need to enable 3035 * jumbo frames on one of the rings later. 3036 * This will not pass over-length frames into the default 3037 * queue because it's gated by the VMOLR.RLPML. 3038 */ 3039 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3040 } 3041 3042 wr32(E1000_RLPML, max_frame_size); 3043 } 3044 3045 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3046 int vfn, bool aupe) 3047 { 3048 struct e1000_hw *hw = &adapter->hw; 3049 u32 vmolr; 3050 3051 /* 3052 * This register exists only on 82576 and newer so if we are older then 3053 * we should exit and do nothing 3054 */ 3055 if (hw->mac.type < e1000_82576) 3056 return; 3057 3058 vmolr = rd32(E1000_VMOLR(vfn)); 3059 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3060 if (aupe) 3061 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3062 else 3063 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3064 3065 /* clear all bits that might not be set */ 3066 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3067 3068 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3069 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3070 /* 3071 * for VMDq only allow the VFs and pool 0 to accept broadcast and 3072 * multicast packets 3073 */ 3074 if (vfn <= adapter->vfs_allocated_count) 3075 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3076 3077 wr32(E1000_VMOLR(vfn), vmolr); 3078 } 3079 3080 /** 3081 * igb_configure_rx_ring - Configure a receive ring after Reset 3082 * @adapter: board private structure 3083 * @ring: receive ring to be configured 3084 * 3085 * Configure the Rx unit of the MAC after a reset. 3086 **/ 3087 void igb_configure_rx_ring(struct igb_adapter *adapter, 3088 struct igb_ring *ring) 3089 { 3090 struct e1000_hw *hw = &adapter->hw; 3091 u64 rdba = ring->dma; 3092 int reg_idx = ring->reg_idx; 3093 u32 srrctl = 0, rxdctl = 0; 3094 3095 /* disable the queue */ 3096 wr32(E1000_RXDCTL(reg_idx), 0); 3097 3098 /* Set DMA base address registers */ 3099 wr32(E1000_RDBAL(reg_idx), 3100 rdba & 0x00000000ffffffffULL); 3101 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3102 wr32(E1000_RDLEN(reg_idx), 3103 ring->count * sizeof(union e1000_adv_rx_desc)); 3104 3105 /* initialize head and tail */ 3106 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3107 wr32(E1000_RDH(reg_idx), 0); 3108 writel(0, ring->tail); 3109 3110 /* set descriptor configuration */ 3111 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3112 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3113 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3114 if (hw->mac.type >= e1000_82580) 3115 srrctl |= E1000_SRRCTL_TIMESTAMP; 3116 /* Only set Drop Enable if we are supporting multiple queues */ 3117 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3118 srrctl |= E1000_SRRCTL_DROP_EN; 3119 3120 wr32(E1000_SRRCTL(reg_idx), srrctl); 3121 3122 /* set filtering for VMDQ pools */ 3123 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3124 3125 rxdctl |= IGB_RX_PTHRESH; 3126 rxdctl |= IGB_RX_HTHRESH << 8; 3127 rxdctl |= IGB_RX_WTHRESH << 16; 3128 3129 /* enable receive descriptor fetching */ 3130 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3131 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3132 } 3133 3134 /** 3135 * igb_configure_rx - Configure receive Unit after Reset 3136 * @adapter: board private structure 3137 * 3138 * Configure the Rx unit of the MAC after a reset. 3139 **/ 3140 static void igb_configure_rx(struct igb_adapter *adapter) 3141 { 3142 int i; 3143 3144 /* set UTA to appropriate mode */ 3145 igb_set_uta(adapter); 3146 3147 /* set the correct pool for the PF default MAC address in entry 0 */ 3148 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3149 adapter->vfs_allocated_count); 3150 3151 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3152 * the Base and Length of the Rx Descriptor Ring */ 3153 for (i = 0; i < adapter->num_rx_queues; i++) 3154 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3155 } 3156 3157 /** 3158 * igb_free_tx_resources - Free Tx Resources per Queue 3159 * @tx_ring: Tx descriptor ring for a specific queue 3160 * 3161 * Free all transmit software resources 3162 **/ 3163 void igb_free_tx_resources(struct igb_ring *tx_ring) 3164 { 3165 igb_clean_tx_ring(tx_ring); 3166 3167 vfree(tx_ring->tx_buffer_info); 3168 tx_ring->tx_buffer_info = NULL; 3169 3170 /* if not set, then don't free */ 3171 if (!tx_ring->desc) 3172 return; 3173 3174 dma_free_coherent(tx_ring->dev, tx_ring->size, 3175 tx_ring->desc, tx_ring->dma); 3176 3177 tx_ring->desc = NULL; 3178 } 3179 3180 /** 3181 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3182 * @adapter: board private structure 3183 * 3184 * Free all transmit software resources 3185 **/ 3186 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3187 { 3188 int i; 3189 3190 for (i = 0; i < adapter->num_tx_queues; i++) 3191 igb_free_tx_resources(adapter->tx_ring[i]); 3192 } 3193 3194 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3195 struct igb_tx_buffer *tx_buffer) 3196 { 3197 if (tx_buffer->skb) { 3198 dev_kfree_skb_any(tx_buffer->skb); 3199 if (dma_unmap_len(tx_buffer, len)) 3200 dma_unmap_single(ring->dev, 3201 dma_unmap_addr(tx_buffer, dma), 3202 dma_unmap_len(tx_buffer, len), 3203 DMA_TO_DEVICE); 3204 } else if (dma_unmap_len(tx_buffer, len)) { 3205 dma_unmap_page(ring->dev, 3206 dma_unmap_addr(tx_buffer, dma), 3207 dma_unmap_len(tx_buffer, len), 3208 DMA_TO_DEVICE); 3209 } 3210 tx_buffer->next_to_watch = NULL; 3211 tx_buffer->skb = NULL; 3212 dma_unmap_len_set(tx_buffer, len, 0); 3213 /* buffer_info must be completely set up in the transmit path */ 3214 } 3215 3216 /** 3217 * igb_clean_tx_ring - Free Tx Buffers 3218 * @tx_ring: ring to be cleaned 3219 **/ 3220 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3221 { 3222 struct igb_tx_buffer *buffer_info; 3223 unsigned long size; 3224 u16 i; 3225 3226 if (!tx_ring->tx_buffer_info) 3227 return; 3228 /* Free all the Tx ring sk_buffs */ 3229 3230 for (i = 0; i < tx_ring->count; i++) { 3231 buffer_info = &tx_ring->tx_buffer_info[i]; 3232 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3233 } 3234 3235 netdev_tx_reset_queue(txring_txq(tx_ring)); 3236 3237 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3238 memset(tx_ring->tx_buffer_info, 0, size); 3239 3240 /* Zero out the descriptor ring */ 3241 memset(tx_ring->desc, 0, tx_ring->size); 3242 3243 tx_ring->next_to_use = 0; 3244 tx_ring->next_to_clean = 0; 3245 } 3246 3247 /** 3248 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3249 * @adapter: board private structure 3250 **/ 3251 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3252 { 3253 int i; 3254 3255 for (i = 0; i < adapter->num_tx_queues; i++) 3256 igb_clean_tx_ring(adapter->tx_ring[i]); 3257 } 3258 3259 /** 3260 * igb_free_rx_resources - Free Rx Resources 3261 * @rx_ring: ring to clean the resources from 3262 * 3263 * Free all receive software resources 3264 **/ 3265 void igb_free_rx_resources(struct igb_ring *rx_ring) 3266 { 3267 igb_clean_rx_ring(rx_ring); 3268 3269 vfree(rx_ring->rx_buffer_info); 3270 rx_ring->rx_buffer_info = NULL; 3271 3272 /* if not set, then don't free */ 3273 if (!rx_ring->desc) 3274 return; 3275 3276 dma_free_coherent(rx_ring->dev, rx_ring->size, 3277 rx_ring->desc, rx_ring->dma); 3278 3279 rx_ring->desc = NULL; 3280 } 3281 3282 /** 3283 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3284 * @adapter: board private structure 3285 * 3286 * Free all receive software resources 3287 **/ 3288 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3289 { 3290 int i; 3291 3292 for (i = 0; i < adapter->num_rx_queues; i++) 3293 igb_free_rx_resources(adapter->rx_ring[i]); 3294 } 3295 3296 /** 3297 * igb_clean_rx_ring - Free Rx Buffers per Queue 3298 * @rx_ring: ring to free buffers from 3299 **/ 3300 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3301 { 3302 unsigned long size; 3303 u16 i; 3304 3305 if (rx_ring->skb) 3306 dev_kfree_skb(rx_ring->skb); 3307 rx_ring->skb = NULL; 3308 3309 if (!rx_ring->rx_buffer_info) 3310 return; 3311 3312 /* Free all the Rx ring sk_buffs */ 3313 for (i = 0; i < rx_ring->count; i++) { 3314 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3315 3316 if (!buffer_info->page) 3317 continue; 3318 3319 dma_unmap_page(rx_ring->dev, 3320 buffer_info->dma, 3321 PAGE_SIZE, 3322 DMA_FROM_DEVICE); 3323 __free_page(buffer_info->page); 3324 3325 buffer_info->page = NULL; 3326 } 3327 3328 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3329 memset(rx_ring->rx_buffer_info, 0, size); 3330 3331 /* Zero out the descriptor ring */ 3332 memset(rx_ring->desc, 0, rx_ring->size); 3333 3334 rx_ring->next_to_alloc = 0; 3335 rx_ring->next_to_clean = 0; 3336 rx_ring->next_to_use = 0; 3337 } 3338 3339 /** 3340 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3341 * @adapter: board private structure 3342 **/ 3343 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3344 { 3345 int i; 3346 3347 for (i = 0; i < adapter->num_rx_queues; i++) 3348 igb_clean_rx_ring(adapter->rx_ring[i]); 3349 } 3350 3351 /** 3352 * igb_set_mac - Change the Ethernet Address of the NIC 3353 * @netdev: network interface device structure 3354 * @p: pointer to an address structure 3355 * 3356 * Returns 0 on success, negative on failure 3357 **/ 3358 static int igb_set_mac(struct net_device *netdev, void *p) 3359 { 3360 struct igb_adapter *adapter = netdev_priv(netdev); 3361 struct e1000_hw *hw = &adapter->hw; 3362 struct sockaddr *addr = p; 3363 3364 if (!is_valid_ether_addr(addr->sa_data)) 3365 return -EADDRNOTAVAIL; 3366 3367 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3368 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3369 3370 /* set the correct pool for the new PF MAC address in entry 0 */ 3371 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3372 adapter->vfs_allocated_count); 3373 3374 return 0; 3375 } 3376 3377 /** 3378 * igb_write_mc_addr_list - write multicast addresses to MTA 3379 * @netdev: network interface device structure 3380 * 3381 * Writes multicast address list to the MTA hash table. 3382 * Returns: -ENOMEM on failure 3383 * 0 on no addresses written 3384 * X on writing X addresses to MTA 3385 **/ 3386 static int igb_write_mc_addr_list(struct net_device *netdev) 3387 { 3388 struct igb_adapter *adapter = netdev_priv(netdev); 3389 struct e1000_hw *hw = &adapter->hw; 3390 struct netdev_hw_addr *ha; 3391 u8 *mta_list; 3392 int i; 3393 3394 if (netdev_mc_empty(netdev)) { 3395 /* nothing to program, so clear mc list */ 3396 igb_update_mc_addr_list(hw, NULL, 0); 3397 igb_restore_vf_multicasts(adapter); 3398 return 0; 3399 } 3400 3401 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3402 if (!mta_list) 3403 return -ENOMEM; 3404 3405 /* The shared function expects a packed array of only addresses. */ 3406 i = 0; 3407 netdev_for_each_mc_addr(ha, netdev) 3408 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3409 3410 igb_update_mc_addr_list(hw, mta_list, i); 3411 kfree(mta_list); 3412 3413 return netdev_mc_count(netdev); 3414 } 3415 3416 /** 3417 * igb_write_uc_addr_list - write unicast addresses to RAR table 3418 * @netdev: network interface device structure 3419 * 3420 * Writes unicast address list to the RAR table. 3421 * Returns: -ENOMEM on failure/insufficient address space 3422 * 0 on no addresses written 3423 * X on writing X addresses to the RAR table 3424 **/ 3425 static int igb_write_uc_addr_list(struct net_device *netdev) 3426 { 3427 struct igb_adapter *adapter = netdev_priv(netdev); 3428 struct e1000_hw *hw = &adapter->hw; 3429 unsigned int vfn = adapter->vfs_allocated_count; 3430 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3431 int count = 0; 3432 3433 /* return ENOMEM indicating insufficient memory for addresses */ 3434 if (netdev_uc_count(netdev) > rar_entries) 3435 return -ENOMEM; 3436 3437 if (!netdev_uc_empty(netdev) && rar_entries) { 3438 struct netdev_hw_addr *ha; 3439 3440 netdev_for_each_uc_addr(ha, netdev) { 3441 if (!rar_entries) 3442 break; 3443 igb_rar_set_qsel(adapter, ha->addr, 3444 rar_entries--, 3445 vfn); 3446 count++; 3447 } 3448 } 3449 /* write the addresses in reverse order to avoid write combining */ 3450 for (; rar_entries > 0 ; rar_entries--) { 3451 wr32(E1000_RAH(rar_entries), 0); 3452 wr32(E1000_RAL(rar_entries), 0); 3453 } 3454 wrfl(); 3455 3456 return count; 3457 } 3458 3459 /** 3460 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3461 * @netdev: network interface device structure 3462 * 3463 * The set_rx_mode entry point is called whenever the unicast or multicast 3464 * address lists or the network interface flags are updated. This routine is 3465 * responsible for configuring the hardware for proper unicast, multicast, 3466 * promiscuous mode, and all-multi behavior. 3467 **/ 3468 static void igb_set_rx_mode(struct net_device *netdev) 3469 { 3470 struct igb_adapter *adapter = netdev_priv(netdev); 3471 struct e1000_hw *hw = &adapter->hw; 3472 unsigned int vfn = adapter->vfs_allocated_count; 3473 u32 rctl, vmolr = 0; 3474 int count; 3475 3476 /* Check for Promiscuous and All Multicast modes */ 3477 rctl = rd32(E1000_RCTL); 3478 3479 /* clear the effected bits */ 3480 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3481 3482 if (netdev->flags & IFF_PROMISC) { 3483 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3484 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3485 } else { 3486 if (netdev->flags & IFF_ALLMULTI) { 3487 rctl |= E1000_RCTL_MPE; 3488 vmolr |= E1000_VMOLR_MPME; 3489 } else { 3490 /* 3491 * Write addresses to the MTA, if the attempt fails 3492 * then we should just turn on promiscuous mode so 3493 * that we can at least receive multicast traffic 3494 */ 3495 count = igb_write_mc_addr_list(netdev); 3496 if (count < 0) { 3497 rctl |= E1000_RCTL_MPE; 3498 vmolr |= E1000_VMOLR_MPME; 3499 } else if (count) { 3500 vmolr |= E1000_VMOLR_ROMPE; 3501 } 3502 } 3503 /* 3504 * Write addresses to available RAR registers, if there is not 3505 * sufficient space to store all the addresses then enable 3506 * unicast promiscuous mode 3507 */ 3508 count = igb_write_uc_addr_list(netdev); 3509 if (count < 0) { 3510 rctl |= E1000_RCTL_UPE; 3511 vmolr |= E1000_VMOLR_ROPE; 3512 } 3513 rctl |= E1000_RCTL_VFE; 3514 } 3515 wr32(E1000_RCTL, rctl); 3516 3517 /* 3518 * In order to support SR-IOV and eventually VMDq it is necessary to set 3519 * the VMOLR to enable the appropriate modes. Without this workaround 3520 * we will have issues with VLAN tag stripping not being done for frames 3521 * that are only arriving because we are the default pool 3522 */ 3523 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3524 return; 3525 3526 vmolr |= rd32(E1000_VMOLR(vfn)) & 3527 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3528 wr32(E1000_VMOLR(vfn), vmolr); 3529 igb_restore_vf_multicasts(adapter); 3530 } 3531 3532 static void igb_check_wvbr(struct igb_adapter *adapter) 3533 { 3534 struct e1000_hw *hw = &adapter->hw; 3535 u32 wvbr = 0; 3536 3537 switch (hw->mac.type) { 3538 case e1000_82576: 3539 case e1000_i350: 3540 if (!(wvbr = rd32(E1000_WVBR))) 3541 return; 3542 break; 3543 default: 3544 break; 3545 } 3546 3547 adapter->wvbr |= wvbr; 3548 } 3549 3550 #define IGB_STAGGERED_QUEUE_OFFSET 8 3551 3552 static void igb_spoof_check(struct igb_adapter *adapter) 3553 { 3554 int j; 3555 3556 if (!adapter->wvbr) 3557 return; 3558 3559 for(j = 0; j < adapter->vfs_allocated_count; j++) { 3560 if (adapter->wvbr & (1 << j) || 3561 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 3562 dev_warn(&adapter->pdev->dev, 3563 "Spoof event(s) detected on VF %d\n", j); 3564 adapter->wvbr &= 3565 ~((1 << j) | 3566 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 3567 } 3568 } 3569 } 3570 3571 /* Need to wait a few seconds after link up to get diagnostic information from 3572 * the phy */ 3573 static void igb_update_phy_info(unsigned long data) 3574 { 3575 struct igb_adapter *adapter = (struct igb_adapter *) data; 3576 igb_get_phy_info(&adapter->hw); 3577 } 3578 3579 /** 3580 * igb_has_link - check shared code for link and determine up/down 3581 * @adapter: pointer to driver private info 3582 **/ 3583 bool igb_has_link(struct igb_adapter *adapter) 3584 { 3585 struct e1000_hw *hw = &adapter->hw; 3586 bool link_active = false; 3587 s32 ret_val = 0; 3588 3589 /* get_link_status is set on LSC (link status) interrupt or 3590 * rx sequence error interrupt. get_link_status will stay 3591 * false until the e1000_check_for_link establishes link 3592 * for copper adapters ONLY 3593 */ 3594 switch (hw->phy.media_type) { 3595 case e1000_media_type_copper: 3596 if (hw->mac.get_link_status) { 3597 ret_val = hw->mac.ops.check_for_link(hw); 3598 link_active = !hw->mac.get_link_status; 3599 } else { 3600 link_active = true; 3601 } 3602 break; 3603 case e1000_media_type_internal_serdes: 3604 ret_val = hw->mac.ops.check_for_link(hw); 3605 link_active = hw->mac.serdes_has_link; 3606 break; 3607 default: 3608 case e1000_media_type_unknown: 3609 break; 3610 } 3611 3612 return link_active; 3613 } 3614 3615 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 3616 { 3617 bool ret = false; 3618 u32 ctrl_ext, thstat; 3619 3620 /* check for thermal sensor event on i350 copper only */ 3621 if (hw->mac.type == e1000_i350) { 3622 thstat = rd32(E1000_THSTAT); 3623 ctrl_ext = rd32(E1000_CTRL_EXT); 3624 3625 if ((hw->phy.media_type == e1000_media_type_copper) && 3626 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3627 ret = !!(thstat & event); 3628 } 3629 } 3630 3631 return ret; 3632 } 3633 3634 /** 3635 * igb_watchdog - Timer Call-back 3636 * @data: pointer to adapter cast into an unsigned long 3637 **/ 3638 static void igb_watchdog(unsigned long data) 3639 { 3640 struct igb_adapter *adapter = (struct igb_adapter *)data; 3641 /* Do the rest outside of interrupt context */ 3642 schedule_work(&adapter->watchdog_task); 3643 } 3644 3645 static void igb_watchdog_task(struct work_struct *work) 3646 { 3647 struct igb_adapter *adapter = container_of(work, 3648 struct igb_adapter, 3649 watchdog_task); 3650 struct e1000_hw *hw = &adapter->hw; 3651 struct net_device *netdev = adapter->netdev; 3652 u32 link; 3653 int i; 3654 3655 link = igb_has_link(adapter); 3656 if (link) { 3657 /* Cancel scheduled suspend requests. */ 3658 pm_runtime_resume(netdev->dev.parent); 3659 3660 if (!netif_carrier_ok(netdev)) { 3661 u32 ctrl; 3662 hw->mac.ops.get_speed_and_duplex(hw, 3663 &adapter->link_speed, 3664 &adapter->link_duplex); 3665 3666 ctrl = rd32(E1000_CTRL); 3667 /* Links status message must follow this format */ 3668 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 3669 "Duplex, Flow Control: %s\n", 3670 netdev->name, 3671 adapter->link_speed, 3672 adapter->link_duplex == FULL_DUPLEX ? 3673 "Full" : "Half", 3674 (ctrl & E1000_CTRL_TFCE) && 3675 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 3676 (ctrl & E1000_CTRL_RFCE) ? "RX" : 3677 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 3678 3679 /* check for thermal sensor event */ 3680 if (igb_thermal_sensor_event(hw, 3681 E1000_THSTAT_LINK_THROTTLE)) { 3682 netdev_info(netdev, "The network adapter link " 3683 "speed was downshifted because it " 3684 "overheated\n"); 3685 } 3686 3687 /* adjust timeout factor according to speed/duplex */ 3688 adapter->tx_timeout_factor = 1; 3689 switch (adapter->link_speed) { 3690 case SPEED_10: 3691 adapter->tx_timeout_factor = 14; 3692 break; 3693 case SPEED_100: 3694 /* maybe add some timeout factor ? */ 3695 break; 3696 } 3697 3698 netif_carrier_on(netdev); 3699 3700 igb_ping_all_vfs(adapter); 3701 igb_check_vf_rate_limit(adapter); 3702 3703 /* link state has changed, schedule phy info update */ 3704 if (!test_bit(__IGB_DOWN, &adapter->state)) 3705 mod_timer(&adapter->phy_info_timer, 3706 round_jiffies(jiffies + 2 * HZ)); 3707 } 3708 } else { 3709 if (netif_carrier_ok(netdev)) { 3710 adapter->link_speed = 0; 3711 adapter->link_duplex = 0; 3712 3713 /* check for thermal sensor event */ 3714 if (igb_thermal_sensor_event(hw, 3715 E1000_THSTAT_PWR_DOWN)) { 3716 netdev_err(netdev, "The network adapter was " 3717 "stopped because it overheated\n"); 3718 } 3719 3720 /* Links status message must follow this format */ 3721 printk(KERN_INFO "igb: %s NIC Link is Down\n", 3722 netdev->name); 3723 netif_carrier_off(netdev); 3724 3725 igb_ping_all_vfs(adapter); 3726 3727 /* link state has changed, schedule phy info update */ 3728 if (!test_bit(__IGB_DOWN, &adapter->state)) 3729 mod_timer(&adapter->phy_info_timer, 3730 round_jiffies(jiffies + 2 * HZ)); 3731 3732 pm_schedule_suspend(netdev->dev.parent, 3733 MSEC_PER_SEC * 5); 3734 } 3735 } 3736 3737 spin_lock(&adapter->stats64_lock); 3738 igb_update_stats(adapter, &adapter->stats64); 3739 spin_unlock(&adapter->stats64_lock); 3740 3741 for (i = 0; i < adapter->num_tx_queues; i++) { 3742 struct igb_ring *tx_ring = adapter->tx_ring[i]; 3743 if (!netif_carrier_ok(netdev)) { 3744 /* We've lost link, so the controller stops DMA, 3745 * but we've got queued Tx work that's never going 3746 * to get done, so reset controller to flush Tx. 3747 * (Do the reset outside of interrupt context). */ 3748 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 3749 adapter->tx_timeout_count++; 3750 schedule_work(&adapter->reset_task); 3751 /* return immediately since reset is imminent */ 3752 return; 3753 } 3754 } 3755 3756 /* Force detection of hung controller every watchdog period */ 3757 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3758 } 3759 3760 /* Cause software interrupt to ensure rx ring is cleaned */ 3761 if (adapter->msix_entries) { 3762 u32 eics = 0; 3763 for (i = 0; i < adapter->num_q_vectors; i++) 3764 eics |= adapter->q_vector[i]->eims_value; 3765 wr32(E1000_EICS, eics); 3766 } else { 3767 wr32(E1000_ICS, E1000_ICS_RXDMT0); 3768 } 3769 3770 igb_spoof_check(adapter); 3771 3772 /* Reset the timer */ 3773 if (!test_bit(__IGB_DOWN, &adapter->state)) 3774 mod_timer(&adapter->watchdog_timer, 3775 round_jiffies(jiffies + 2 * HZ)); 3776 } 3777 3778 enum latency_range { 3779 lowest_latency = 0, 3780 low_latency = 1, 3781 bulk_latency = 2, 3782 latency_invalid = 255 3783 }; 3784 3785 /** 3786 * igb_update_ring_itr - update the dynamic ITR value based on packet size 3787 * 3788 * Stores a new ITR value based on strictly on packet size. This 3789 * algorithm is less sophisticated than that used in igb_update_itr, 3790 * due to the difficulty of synchronizing statistics across multiple 3791 * receive rings. The divisors and thresholds used by this function 3792 * were determined based on theoretical maximum wire speed and testing 3793 * data, in order to minimize response time while increasing bulk 3794 * throughput. 3795 * This functionality is controlled by the InterruptThrottleRate module 3796 * parameter (see igb_param.c) 3797 * NOTE: This function is called only when operating in a multiqueue 3798 * receive environment. 3799 * @q_vector: pointer to q_vector 3800 **/ 3801 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 3802 { 3803 int new_val = q_vector->itr_val; 3804 int avg_wire_size = 0; 3805 struct igb_adapter *adapter = q_vector->adapter; 3806 unsigned int packets; 3807 3808 /* For non-gigabit speeds, just fix the interrupt rate at 4000 3809 * ints/sec - ITR timer value of 120 ticks. 3810 */ 3811 if (adapter->link_speed != SPEED_1000) { 3812 new_val = IGB_4K_ITR; 3813 goto set_itr_val; 3814 } 3815 3816 packets = q_vector->rx.total_packets; 3817 if (packets) 3818 avg_wire_size = q_vector->rx.total_bytes / packets; 3819 3820 packets = q_vector->tx.total_packets; 3821 if (packets) 3822 avg_wire_size = max_t(u32, avg_wire_size, 3823 q_vector->tx.total_bytes / packets); 3824 3825 /* if avg_wire_size isn't set no work was done */ 3826 if (!avg_wire_size) 3827 goto clear_counts; 3828 3829 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3830 avg_wire_size += 24; 3831 3832 /* Don't starve jumbo frames */ 3833 avg_wire_size = min(avg_wire_size, 3000); 3834 3835 /* Give a little boost to mid-size frames */ 3836 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 3837 new_val = avg_wire_size / 3; 3838 else 3839 new_val = avg_wire_size / 2; 3840 3841 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3842 if (new_val < IGB_20K_ITR && 3843 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3844 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3845 new_val = IGB_20K_ITR; 3846 3847 set_itr_val: 3848 if (new_val != q_vector->itr_val) { 3849 q_vector->itr_val = new_val; 3850 q_vector->set_itr = 1; 3851 } 3852 clear_counts: 3853 q_vector->rx.total_bytes = 0; 3854 q_vector->rx.total_packets = 0; 3855 q_vector->tx.total_bytes = 0; 3856 q_vector->tx.total_packets = 0; 3857 } 3858 3859 /** 3860 * igb_update_itr - update the dynamic ITR value based on statistics 3861 * Stores a new ITR value based on packets and byte 3862 * counts during the last interrupt. The advantage of per interrupt 3863 * computation is faster updates and more accurate ITR for the current 3864 * traffic pattern. Constants in this function were computed 3865 * based on theoretical maximum wire speed and thresholds were set based 3866 * on testing data as well as attempting to minimize response time 3867 * while increasing bulk throughput. 3868 * this functionality is controlled by the InterruptThrottleRate module 3869 * parameter (see igb_param.c) 3870 * NOTE: These calculations are only valid when operating in a single- 3871 * queue environment. 3872 * @q_vector: pointer to q_vector 3873 * @ring_container: ring info to update the itr for 3874 **/ 3875 static void igb_update_itr(struct igb_q_vector *q_vector, 3876 struct igb_ring_container *ring_container) 3877 { 3878 unsigned int packets = ring_container->total_packets; 3879 unsigned int bytes = ring_container->total_bytes; 3880 u8 itrval = ring_container->itr; 3881 3882 /* no packets, exit with status unchanged */ 3883 if (packets == 0) 3884 return; 3885 3886 switch (itrval) { 3887 case lowest_latency: 3888 /* handle TSO and jumbo frames */ 3889 if (bytes/packets > 8000) 3890 itrval = bulk_latency; 3891 else if ((packets < 5) && (bytes > 512)) 3892 itrval = low_latency; 3893 break; 3894 case low_latency: /* 50 usec aka 20000 ints/s */ 3895 if (bytes > 10000) { 3896 /* this if handles the TSO accounting */ 3897 if (bytes/packets > 8000) { 3898 itrval = bulk_latency; 3899 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 3900 itrval = bulk_latency; 3901 } else if ((packets > 35)) { 3902 itrval = lowest_latency; 3903 } 3904 } else if (bytes/packets > 2000) { 3905 itrval = bulk_latency; 3906 } else if (packets <= 2 && bytes < 512) { 3907 itrval = lowest_latency; 3908 } 3909 break; 3910 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3911 if (bytes > 25000) { 3912 if (packets > 35) 3913 itrval = low_latency; 3914 } else if (bytes < 1500) { 3915 itrval = low_latency; 3916 } 3917 break; 3918 } 3919 3920 /* clear work counters since we have the values we need */ 3921 ring_container->total_bytes = 0; 3922 ring_container->total_packets = 0; 3923 3924 /* write updated itr to ring container */ 3925 ring_container->itr = itrval; 3926 } 3927 3928 static void igb_set_itr(struct igb_q_vector *q_vector) 3929 { 3930 struct igb_adapter *adapter = q_vector->adapter; 3931 u32 new_itr = q_vector->itr_val; 3932 u8 current_itr = 0; 3933 3934 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3935 if (adapter->link_speed != SPEED_1000) { 3936 current_itr = 0; 3937 new_itr = IGB_4K_ITR; 3938 goto set_itr_now; 3939 } 3940 3941 igb_update_itr(q_vector, &q_vector->tx); 3942 igb_update_itr(q_vector, &q_vector->rx); 3943 3944 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3945 3946 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3947 if (current_itr == lowest_latency && 3948 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3949 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3950 current_itr = low_latency; 3951 3952 switch (current_itr) { 3953 /* counts and packets in update_itr are dependent on these numbers */ 3954 case lowest_latency: 3955 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 3956 break; 3957 case low_latency: 3958 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 3959 break; 3960 case bulk_latency: 3961 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 3962 break; 3963 default: 3964 break; 3965 } 3966 3967 set_itr_now: 3968 if (new_itr != q_vector->itr_val) { 3969 /* this attempts to bias the interrupt rate towards Bulk 3970 * by adding intermediate steps when interrupt rate is 3971 * increasing */ 3972 new_itr = new_itr > q_vector->itr_val ? 3973 max((new_itr * q_vector->itr_val) / 3974 (new_itr + (q_vector->itr_val >> 2)), 3975 new_itr) : 3976 new_itr; 3977 /* Don't write the value here; it resets the adapter's 3978 * internal timer, and causes us to delay far longer than 3979 * we should between interrupts. Instead, we write the ITR 3980 * value at the beginning of the next interrupt so the timing 3981 * ends up being correct. 3982 */ 3983 q_vector->itr_val = new_itr; 3984 q_vector->set_itr = 1; 3985 } 3986 } 3987 3988 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 3989 u32 type_tucmd, u32 mss_l4len_idx) 3990 { 3991 struct e1000_adv_tx_context_desc *context_desc; 3992 u16 i = tx_ring->next_to_use; 3993 3994 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 3995 3996 i++; 3997 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3998 3999 /* set bits to identify this as an advanced context descriptor */ 4000 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4001 4002 /* For 82575, context index must be unique per ring. */ 4003 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4004 mss_l4len_idx |= tx_ring->reg_idx << 4; 4005 4006 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4007 context_desc->seqnum_seed = 0; 4008 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4009 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4010 } 4011 4012 static int igb_tso(struct igb_ring *tx_ring, 4013 struct igb_tx_buffer *first, 4014 u8 *hdr_len) 4015 { 4016 struct sk_buff *skb = first->skb; 4017 u32 vlan_macip_lens, type_tucmd; 4018 u32 mss_l4len_idx, l4len; 4019 4020 if (skb->ip_summed != CHECKSUM_PARTIAL) 4021 return 0; 4022 4023 if (!skb_is_gso(skb)) 4024 return 0; 4025 4026 if (skb_header_cloned(skb)) { 4027 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4028 if (err) 4029 return err; 4030 } 4031 4032 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4033 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4034 4035 if (first->protocol == __constant_htons(ETH_P_IP)) { 4036 struct iphdr *iph = ip_hdr(skb); 4037 iph->tot_len = 0; 4038 iph->check = 0; 4039 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4040 iph->daddr, 0, 4041 IPPROTO_TCP, 4042 0); 4043 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4044 first->tx_flags |= IGB_TX_FLAGS_TSO | 4045 IGB_TX_FLAGS_CSUM | 4046 IGB_TX_FLAGS_IPV4; 4047 } else if (skb_is_gso_v6(skb)) { 4048 ipv6_hdr(skb)->payload_len = 0; 4049 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4050 &ipv6_hdr(skb)->daddr, 4051 0, IPPROTO_TCP, 0); 4052 first->tx_flags |= IGB_TX_FLAGS_TSO | 4053 IGB_TX_FLAGS_CSUM; 4054 } 4055 4056 /* compute header lengths */ 4057 l4len = tcp_hdrlen(skb); 4058 *hdr_len = skb_transport_offset(skb) + l4len; 4059 4060 /* update gso size and bytecount with header size */ 4061 first->gso_segs = skb_shinfo(skb)->gso_segs; 4062 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4063 4064 /* MSS L4LEN IDX */ 4065 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4066 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4067 4068 /* VLAN MACLEN IPLEN */ 4069 vlan_macip_lens = skb_network_header_len(skb); 4070 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4071 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4072 4073 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4074 4075 return 1; 4076 } 4077 4078 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4079 { 4080 struct sk_buff *skb = first->skb; 4081 u32 vlan_macip_lens = 0; 4082 u32 mss_l4len_idx = 0; 4083 u32 type_tucmd = 0; 4084 4085 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4086 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4087 return; 4088 } else { 4089 u8 l4_hdr = 0; 4090 switch (first->protocol) { 4091 case __constant_htons(ETH_P_IP): 4092 vlan_macip_lens |= skb_network_header_len(skb); 4093 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4094 l4_hdr = ip_hdr(skb)->protocol; 4095 break; 4096 case __constant_htons(ETH_P_IPV6): 4097 vlan_macip_lens |= skb_network_header_len(skb); 4098 l4_hdr = ipv6_hdr(skb)->nexthdr; 4099 break; 4100 default: 4101 if (unlikely(net_ratelimit())) { 4102 dev_warn(tx_ring->dev, 4103 "partial checksum but proto=%x!\n", 4104 first->protocol); 4105 } 4106 break; 4107 } 4108 4109 switch (l4_hdr) { 4110 case IPPROTO_TCP: 4111 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4112 mss_l4len_idx = tcp_hdrlen(skb) << 4113 E1000_ADVTXD_L4LEN_SHIFT; 4114 break; 4115 case IPPROTO_SCTP: 4116 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4117 mss_l4len_idx = sizeof(struct sctphdr) << 4118 E1000_ADVTXD_L4LEN_SHIFT; 4119 break; 4120 case IPPROTO_UDP: 4121 mss_l4len_idx = sizeof(struct udphdr) << 4122 E1000_ADVTXD_L4LEN_SHIFT; 4123 break; 4124 default: 4125 if (unlikely(net_ratelimit())) { 4126 dev_warn(tx_ring->dev, 4127 "partial checksum but l4 proto=%x!\n", 4128 l4_hdr); 4129 } 4130 break; 4131 } 4132 4133 /* update TX checksum flag */ 4134 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4135 } 4136 4137 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4138 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4139 4140 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4141 } 4142 4143 #define IGB_SET_FLAG(_input, _flag, _result) \ 4144 ((_flag <= _result) ? \ 4145 ((u32)(_input & _flag) * (_result / _flag)) : \ 4146 ((u32)(_input & _flag) / (_flag / _result))) 4147 4148 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4149 { 4150 /* set type for advanced descriptor with frame checksum insertion */ 4151 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4152 E1000_ADVTXD_DCMD_DEXT | 4153 E1000_ADVTXD_DCMD_IFCS; 4154 4155 /* set HW vlan bit if vlan is present */ 4156 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4157 (E1000_ADVTXD_DCMD_VLE)); 4158 4159 /* set segmentation bits for TSO */ 4160 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4161 (E1000_ADVTXD_DCMD_TSE)); 4162 4163 /* set timestamp bit if present */ 4164 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4165 (E1000_ADVTXD_MAC_TSTAMP)); 4166 4167 /* insert frame checksum */ 4168 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4169 4170 return cmd_type; 4171 } 4172 4173 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4174 union e1000_adv_tx_desc *tx_desc, 4175 u32 tx_flags, unsigned int paylen) 4176 { 4177 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4178 4179 /* 82575 requires a unique index per ring */ 4180 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4181 olinfo_status |= tx_ring->reg_idx << 4; 4182 4183 /* insert L4 checksum */ 4184 olinfo_status |= IGB_SET_FLAG(tx_flags, 4185 IGB_TX_FLAGS_CSUM, 4186 (E1000_TXD_POPTS_TXSM << 8)); 4187 4188 /* insert IPv4 checksum */ 4189 olinfo_status |= IGB_SET_FLAG(tx_flags, 4190 IGB_TX_FLAGS_IPV4, 4191 (E1000_TXD_POPTS_IXSM << 8)); 4192 4193 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4194 } 4195 4196 /* 4197 * The largest size we can write to the descriptor is 65535. In order to 4198 * maintain a power of two alignment we have to limit ourselves to 32K. 4199 */ 4200 #define IGB_MAX_TXD_PWR 15 4201 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) 4202 4203 static void igb_tx_map(struct igb_ring *tx_ring, 4204 struct igb_tx_buffer *first, 4205 const u8 hdr_len) 4206 { 4207 struct sk_buff *skb = first->skb; 4208 struct igb_tx_buffer *tx_buffer; 4209 union e1000_adv_tx_desc *tx_desc; 4210 struct skb_frag_struct *frag; 4211 dma_addr_t dma; 4212 unsigned int data_len, size; 4213 u32 tx_flags = first->tx_flags; 4214 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4215 u16 i = tx_ring->next_to_use; 4216 4217 tx_desc = IGB_TX_DESC(tx_ring, i); 4218 4219 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4220 4221 size = skb_headlen(skb); 4222 data_len = skb->data_len; 4223 4224 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4225 4226 tx_buffer = first; 4227 4228 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4229 if (dma_mapping_error(tx_ring->dev, dma)) 4230 goto dma_error; 4231 4232 /* record length, and DMA address */ 4233 dma_unmap_len_set(tx_buffer, len, size); 4234 dma_unmap_addr_set(tx_buffer, dma, dma); 4235 4236 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4237 4238 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4239 tx_desc->read.cmd_type_len = 4240 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4241 4242 i++; 4243 tx_desc++; 4244 if (i == tx_ring->count) { 4245 tx_desc = IGB_TX_DESC(tx_ring, 0); 4246 i = 0; 4247 } 4248 tx_desc->read.olinfo_status = 0; 4249 4250 dma += IGB_MAX_DATA_PER_TXD; 4251 size -= IGB_MAX_DATA_PER_TXD; 4252 4253 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4254 } 4255 4256 if (likely(!data_len)) 4257 break; 4258 4259 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4260 4261 i++; 4262 tx_desc++; 4263 if (i == tx_ring->count) { 4264 tx_desc = IGB_TX_DESC(tx_ring, 0); 4265 i = 0; 4266 } 4267 tx_desc->read.olinfo_status = 0; 4268 4269 size = skb_frag_size(frag); 4270 data_len -= size; 4271 4272 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4273 size, DMA_TO_DEVICE); 4274 4275 tx_buffer = &tx_ring->tx_buffer_info[i]; 4276 } 4277 4278 /* write last descriptor with RS and EOP bits */ 4279 cmd_type |= size | IGB_TXD_DCMD; 4280 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4281 4282 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4283 4284 /* set the timestamp */ 4285 first->time_stamp = jiffies; 4286 4287 /* 4288 * Force memory writes to complete before letting h/w know there 4289 * are new descriptors to fetch. (Only applicable for weak-ordered 4290 * memory model archs, such as IA-64). 4291 * 4292 * We also need this memory barrier to make certain all of the 4293 * status bits have been updated before next_to_watch is written. 4294 */ 4295 wmb(); 4296 4297 /* set next_to_watch value indicating a packet is present */ 4298 first->next_to_watch = tx_desc; 4299 4300 i++; 4301 if (i == tx_ring->count) 4302 i = 0; 4303 4304 tx_ring->next_to_use = i; 4305 4306 writel(i, tx_ring->tail); 4307 4308 /* we need this if more than one processor can write to our tail 4309 * at a time, it syncronizes IO on IA64/Altix systems */ 4310 mmiowb(); 4311 4312 return; 4313 4314 dma_error: 4315 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4316 4317 /* clear dma mappings for failed tx_buffer_info map */ 4318 for (;;) { 4319 tx_buffer = &tx_ring->tx_buffer_info[i]; 4320 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4321 if (tx_buffer == first) 4322 break; 4323 if (i == 0) 4324 i = tx_ring->count; 4325 i--; 4326 } 4327 4328 tx_ring->next_to_use = i; 4329 } 4330 4331 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4332 { 4333 struct net_device *netdev = tx_ring->netdev; 4334 4335 netif_stop_subqueue(netdev, tx_ring->queue_index); 4336 4337 /* Herbert's original patch had: 4338 * smp_mb__after_netif_stop_queue(); 4339 * but since that doesn't exist yet, just open code it. */ 4340 smp_mb(); 4341 4342 /* We need to check again in a case another CPU has just 4343 * made room available. */ 4344 if (igb_desc_unused(tx_ring) < size) 4345 return -EBUSY; 4346 4347 /* A reprieve! */ 4348 netif_wake_subqueue(netdev, tx_ring->queue_index); 4349 4350 u64_stats_update_begin(&tx_ring->tx_syncp2); 4351 tx_ring->tx_stats.restart_queue2++; 4352 u64_stats_update_end(&tx_ring->tx_syncp2); 4353 4354 return 0; 4355 } 4356 4357 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4358 { 4359 if (igb_desc_unused(tx_ring) >= size) 4360 return 0; 4361 return __igb_maybe_stop_tx(tx_ring, size); 4362 } 4363 4364 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4365 struct igb_ring *tx_ring) 4366 { 4367 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4368 struct igb_tx_buffer *first; 4369 int tso; 4370 u32 tx_flags = 0; 4371 __be16 protocol = vlan_get_protocol(skb); 4372 u8 hdr_len = 0; 4373 4374 /* need: 1 descriptor per page, 4375 * + 2 desc gap to keep tail from touching head, 4376 * + 1 desc for skb->data, 4377 * + 1 desc for context descriptor, 4378 * otherwise try next time */ 4379 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 4380 /* this is a hard error */ 4381 return NETDEV_TX_BUSY; 4382 } 4383 4384 /* record the location of the first descriptor for this packet */ 4385 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4386 first->skb = skb; 4387 first->bytecount = skb->len; 4388 first->gso_segs = 1; 4389 4390 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4391 !(adapter->ptp_tx_skb))) { 4392 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4393 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4394 4395 adapter->ptp_tx_skb = skb_get(skb); 4396 if (adapter->hw.mac.type == e1000_82576) 4397 schedule_work(&adapter->ptp_tx_work); 4398 } 4399 4400 if (vlan_tx_tag_present(skb)) { 4401 tx_flags |= IGB_TX_FLAGS_VLAN; 4402 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4403 } 4404 4405 /* record initial flags and protocol */ 4406 first->tx_flags = tx_flags; 4407 first->protocol = protocol; 4408 4409 tso = igb_tso(tx_ring, first, &hdr_len); 4410 if (tso < 0) 4411 goto out_drop; 4412 else if (!tso) 4413 igb_tx_csum(tx_ring, first); 4414 4415 igb_tx_map(tx_ring, first, hdr_len); 4416 4417 /* Make sure there is space in the ring for the next send. */ 4418 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); 4419 4420 return NETDEV_TX_OK; 4421 4422 out_drop: 4423 igb_unmap_and_free_tx_resource(tx_ring, first); 4424 4425 return NETDEV_TX_OK; 4426 } 4427 4428 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4429 struct sk_buff *skb) 4430 { 4431 unsigned int r_idx = skb->queue_mapping; 4432 4433 if (r_idx >= adapter->num_tx_queues) 4434 r_idx = r_idx % adapter->num_tx_queues; 4435 4436 return adapter->tx_ring[r_idx]; 4437 } 4438 4439 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4440 struct net_device *netdev) 4441 { 4442 struct igb_adapter *adapter = netdev_priv(netdev); 4443 4444 if (test_bit(__IGB_DOWN, &adapter->state)) { 4445 dev_kfree_skb_any(skb); 4446 return NETDEV_TX_OK; 4447 } 4448 4449 if (skb->len <= 0) { 4450 dev_kfree_skb_any(skb); 4451 return NETDEV_TX_OK; 4452 } 4453 4454 /* 4455 * The minimum packet size with TCTL.PSP set is 17 so pad the skb 4456 * in order to meet this minimum size requirement. 4457 */ 4458 if (unlikely(skb->len < 17)) { 4459 if (skb_pad(skb, 17 - skb->len)) 4460 return NETDEV_TX_OK; 4461 skb->len = 17; 4462 skb_set_tail_pointer(skb, 17); 4463 } 4464 4465 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4466 } 4467 4468 /** 4469 * igb_tx_timeout - Respond to a Tx Hang 4470 * @netdev: network interface device structure 4471 **/ 4472 static void igb_tx_timeout(struct net_device *netdev) 4473 { 4474 struct igb_adapter *adapter = netdev_priv(netdev); 4475 struct e1000_hw *hw = &adapter->hw; 4476 4477 /* Do the reset outside of interrupt context */ 4478 adapter->tx_timeout_count++; 4479 4480 if (hw->mac.type >= e1000_82580) 4481 hw->dev_spec._82575.global_device_reset = true; 4482 4483 schedule_work(&adapter->reset_task); 4484 wr32(E1000_EICS, 4485 (adapter->eims_enable_mask & ~adapter->eims_other)); 4486 } 4487 4488 static void igb_reset_task(struct work_struct *work) 4489 { 4490 struct igb_adapter *adapter; 4491 adapter = container_of(work, struct igb_adapter, reset_task); 4492 4493 igb_dump(adapter); 4494 netdev_err(adapter->netdev, "Reset adapter\n"); 4495 igb_reinit_locked(adapter); 4496 } 4497 4498 /** 4499 * igb_get_stats64 - Get System Network Statistics 4500 * @netdev: network interface device structure 4501 * @stats: rtnl_link_stats64 pointer 4502 * 4503 **/ 4504 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 4505 struct rtnl_link_stats64 *stats) 4506 { 4507 struct igb_adapter *adapter = netdev_priv(netdev); 4508 4509 spin_lock(&adapter->stats64_lock); 4510 igb_update_stats(adapter, &adapter->stats64); 4511 memcpy(stats, &adapter->stats64, sizeof(*stats)); 4512 spin_unlock(&adapter->stats64_lock); 4513 4514 return stats; 4515 } 4516 4517 /** 4518 * igb_change_mtu - Change the Maximum Transfer Unit 4519 * @netdev: network interface device structure 4520 * @new_mtu: new value for maximum frame size 4521 * 4522 * Returns 0 on success, negative on failure 4523 **/ 4524 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 4525 { 4526 struct igb_adapter *adapter = netdev_priv(netdev); 4527 struct pci_dev *pdev = adapter->pdev; 4528 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4529 4530 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 4531 dev_err(&pdev->dev, "Invalid MTU setting\n"); 4532 return -EINVAL; 4533 } 4534 4535 #define MAX_STD_JUMBO_FRAME_SIZE 9238 4536 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 4537 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 4538 return -EINVAL; 4539 } 4540 4541 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 4542 msleep(1); 4543 4544 /* igb_down has a dependency on max_frame_size */ 4545 adapter->max_frame_size = max_frame; 4546 4547 if (netif_running(netdev)) 4548 igb_down(adapter); 4549 4550 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 4551 netdev->mtu, new_mtu); 4552 netdev->mtu = new_mtu; 4553 4554 if (netif_running(netdev)) 4555 igb_up(adapter); 4556 else 4557 igb_reset(adapter); 4558 4559 clear_bit(__IGB_RESETTING, &adapter->state); 4560 4561 return 0; 4562 } 4563 4564 /** 4565 * igb_update_stats - Update the board statistics counters 4566 * @adapter: board private structure 4567 **/ 4568 4569 void igb_update_stats(struct igb_adapter *adapter, 4570 struct rtnl_link_stats64 *net_stats) 4571 { 4572 struct e1000_hw *hw = &adapter->hw; 4573 struct pci_dev *pdev = adapter->pdev; 4574 u32 reg, mpc; 4575 u16 phy_tmp; 4576 int i; 4577 u64 bytes, packets; 4578 unsigned int start; 4579 u64 _bytes, _packets; 4580 4581 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 4582 4583 /* 4584 * Prevent stats update while adapter is being reset, or if the pci 4585 * connection is down. 4586 */ 4587 if (adapter->link_speed == 0) 4588 return; 4589 if (pci_channel_offline(pdev)) 4590 return; 4591 4592 bytes = 0; 4593 packets = 0; 4594 for (i = 0; i < adapter->num_rx_queues; i++) { 4595 u32 rqdpc = rd32(E1000_RQDPC(i)); 4596 struct igb_ring *ring = adapter->rx_ring[i]; 4597 4598 if (rqdpc) { 4599 ring->rx_stats.drops += rqdpc; 4600 net_stats->rx_fifo_errors += rqdpc; 4601 } 4602 4603 do { 4604 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 4605 _bytes = ring->rx_stats.bytes; 4606 _packets = ring->rx_stats.packets; 4607 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 4608 bytes += _bytes; 4609 packets += _packets; 4610 } 4611 4612 net_stats->rx_bytes = bytes; 4613 net_stats->rx_packets = packets; 4614 4615 bytes = 0; 4616 packets = 0; 4617 for (i = 0; i < adapter->num_tx_queues; i++) { 4618 struct igb_ring *ring = adapter->tx_ring[i]; 4619 do { 4620 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 4621 _bytes = ring->tx_stats.bytes; 4622 _packets = ring->tx_stats.packets; 4623 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 4624 bytes += _bytes; 4625 packets += _packets; 4626 } 4627 net_stats->tx_bytes = bytes; 4628 net_stats->tx_packets = packets; 4629 4630 /* read stats registers */ 4631 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 4632 adapter->stats.gprc += rd32(E1000_GPRC); 4633 adapter->stats.gorc += rd32(E1000_GORCL); 4634 rd32(E1000_GORCH); /* clear GORCL */ 4635 adapter->stats.bprc += rd32(E1000_BPRC); 4636 adapter->stats.mprc += rd32(E1000_MPRC); 4637 adapter->stats.roc += rd32(E1000_ROC); 4638 4639 adapter->stats.prc64 += rd32(E1000_PRC64); 4640 adapter->stats.prc127 += rd32(E1000_PRC127); 4641 adapter->stats.prc255 += rd32(E1000_PRC255); 4642 adapter->stats.prc511 += rd32(E1000_PRC511); 4643 adapter->stats.prc1023 += rd32(E1000_PRC1023); 4644 adapter->stats.prc1522 += rd32(E1000_PRC1522); 4645 adapter->stats.symerrs += rd32(E1000_SYMERRS); 4646 adapter->stats.sec += rd32(E1000_SEC); 4647 4648 mpc = rd32(E1000_MPC); 4649 adapter->stats.mpc += mpc; 4650 net_stats->rx_fifo_errors += mpc; 4651 adapter->stats.scc += rd32(E1000_SCC); 4652 adapter->stats.ecol += rd32(E1000_ECOL); 4653 adapter->stats.mcc += rd32(E1000_MCC); 4654 adapter->stats.latecol += rd32(E1000_LATECOL); 4655 adapter->stats.dc += rd32(E1000_DC); 4656 adapter->stats.rlec += rd32(E1000_RLEC); 4657 adapter->stats.xonrxc += rd32(E1000_XONRXC); 4658 adapter->stats.xontxc += rd32(E1000_XONTXC); 4659 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 4660 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 4661 adapter->stats.fcruc += rd32(E1000_FCRUC); 4662 adapter->stats.gptc += rd32(E1000_GPTC); 4663 adapter->stats.gotc += rd32(E1000_GOTCL); 4664 rd32(E1000_GOTCH); /* clear GOTCL */ 4665 adapter->stats.rnbc += rd32(E1000_RNBC); 4666 adapter->stats.ruc += rd32(E1000_RUC); 4667 adapter->stats.rfc += rd32(E1000_RFC); 4668 adapter->stats.rjc += rd32(E1000_RJC); 4669 adapter->stats.tor += rd32(E1000_TORH); 4670 adapter->stats.tot += rd32(E1000_TOTH); 4671 adapter->stats.tpr += rd32(E1000_TPR); 4672 4673 adapter->stats.ptc64 += rd32(E1000_PTC64); 4674 adapter->stats.ptc127 += rd32(E1000_PTC127); 4675 adapter->stats.ptc255 += rd32(E1000_PTC255); 4676 adapter->stats.ptc511 += rd32(E1000_PTC511); 4677 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 4678 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 4679 4680 adapter->stats.mptc += rd32(E1000_MPTC); 4681 adapter->stats.bptc += rd32(E1000_BPTC); 4682 4683 adapter->stats.tpt += rd32(E1000_TPT); 4684 adapter->stats.colc += rd32(E1000_COLC); 4685 4686 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 4687 /* read internal phy specific stats */ 4688 reg = rd32(E1000_CTRL_EXT); 4689 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 4690 adapter->stats.rxerrc += rd32(E1000_RXERRC); 4691 4692 /* this stat has invalid values on i210/i211 */ 4693 if ((hw->mac.type != e1000_i210) && 4694 (hw->mac.type != e1000_i211)) 4695 adapter->stats.tncrs += rd32(E1000_TNCRS); 4696 } 4697 4698 adapter->stats.tsctc += rd32(E1000_TSCTC); 4699 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 4700 4701 adapter->stats.iac += rd32(E1000_IAC); 4702 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 4703 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 4704 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 4705 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 4706 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 4707 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 4708 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 4709 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 4710 4711 /* Fill out the OS statistics structure */ 4712 net_stats->multicast = adapter->stats.mprc; 4713 net_stats->collisions = adapter->stats.colc; 4714 4715 /* Rx Errors */ 4716 4717 /* RLEC on some newer hardware can be incorrect so build 4718 * our own version based on RUC and ROC */ 4719 net_stats->rx_errors = adapter->stats.rxerrc + 4720 adapter->stats.crcerrs + adapter->stats.algnerrc + 4721 adapter->stats.ruc + adapter->stats.roc + 4722 adapter->stats.cexterr; 4723 net_stats->rx_length_errors = adapter->stats.ruc + 4724 adapter->stats.roc; 4725 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4726 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4727 net_stats->rx_missed_errors = adapter->stats.mpc; 4728 4729 /* Tx Errors */ 4730 net_stats->tx_errors = adapter->stats.ecol + 4731 adapter->stats.latecol; 4732 net_stats->tx_aborted_errors = adapter->stats.ecol; 4733 net_stats->tx_window_errors = adapter->stats.latecol; 4734 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4735 4736 /* Tx Dropped needs to be maintained elsewhere */ 4737 4738 /* Phy Stats */ 4739 if (hw->phy.media_type == e1000_media_type_copper) { 4740 if ((adapter->link_speed == SPEED_1000) && 4741 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 4742 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 4743 adapter->phy_stats.idle_errors += phy_tmp; 4744 } 4745 } 4746 4747 /* Management Stats */ 4748 adapter->stats.mgptc += rd32(E1000_MGTPTC); 4749 adapter->stats.mgprc += rd32(E1000_MGTPRC); 4750 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 4751 4752 /* OS2BMC Stats */ 4753 reg = rd32(E1000_MANC); 4754 if (reg & E1000_MANC_EN_BMC2OS) { 4755 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 4756 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 4757 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 4758 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 4759 } 4760 } 4761 4762 static irqreturn_t igb_msix_other(int irq, void *data) 4763 { 4764 struct igb_adapter *adapter = data; 4765 struct e1000_hw *hw = &adapter->hw; 4766 u32 icr = rd32(E1000_ICR); 4767 /* reading ICR causes bit 31 of EICR to be cleared */ 4768 4769 if (icr & E1000_ICR_DRSTA) 4770 schedule_work(&adapter->reset_task); 4771 4772 if (icr & E1000_ICR_DOUTSYNC) { 4773 /* HW is reporting DMA is out of sync */ 4774 adapter->stats.doosync++; 4775 /* The DMA Out of Sync is also indication of a spoof event 4776 * in IOV mode. Check the Wrong VM Behavior register to 4777 * see if it is really a spoof event. */ 4778 igb_check_wvbr(adapter); 4779 } 4780 4781 /* Check for a mailbox event */ 4782 if (icr & E1000_ICR_VMMB) 4783 igb_msg_task(adapter); 4784 4785 if (icr & E1000_ICR_LSC) { 4786 hw->mac.get_link_status = 1; 4787 /* guard against interrupt when we're going down */ 4788 if (!test_bit(__IGB_DOWN, &adapter->state)) 4789 mod_timer(&adapter->watchdog_timer, jiffies + 1); 4790 } 4791 4792 if (icr & E1000_ICR_TS) { 4793 u32 tsicr = rd32(E1000_TSICR); 4794 4795 if (tsicr & E1000_TSICR_TXTS) { 4796 /* acknowledge the interrupt */ 4797 wr32(E1000_TSICR, E1000_TSICR_TXTS); 4798 /* retrieve hardware timestamp */ 4799 schedule_work(&adapter->ptp_tx_work); 4800 } 4801 } 4802 4803 wr32(E1000_EIMS, adapter->eims_other); 4804 4805 return IRQ_HANDLED; 4806 } 4807 4808 static void igb_write_itr(struct igb_q_vector *q_vector) 4809 { 4810 struct igb_adapter *adapter = q_vector->adapter; 4811 u32 itr_val = q_vector->itr_val & 0x7FFC; 4812 4813 if (!q_vector->set_itr) 4814 return; 4815 4816 if (!itr_val) 4817 itr_val = 0x4; 4818 4819 if (adapter->hw.mac.type == e1000_82575) 4820 itr_val |= itr_val << 16; 4821 else 4822 itr_val |= E1000_EITR_CNT_IGNR; 4823 4824 writel(itr_val, q_vector->itr_register); 4825 q_vector->set_itr = 0; 4826 } 4827 4828 static irqreturn_t igb_msix_ring(int irq, void *data) 4829 { 4830 struct igb_q_vector *q_vector = data; 4831 4832 /* Write the ITR value calculated from the previous interrupt. */ 4833 igb_write_itr(q_vector); 4834 4835 napi_schedule(&q_vector->napi); 4836 4837 return IRQ_HANDLED; 4838 } 4839 4840 #ifdef CONFIG_IGB_DCA 4841 static void igb_update_tx_dca(struct igb_adapter *adapter, 4842 struct igb_ring *tx_ring, 4843 int cpu) 4844 { 4845 struct e1000_hw *hw = &adapter->hw; 4846 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 4847 4848 if (hw->mac.type != e1000_82575) 4849 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 4850 4851 /* 4852 * We can enable relaxed ordering for reads, but not writes when 4853 * DCA is enabled. This is due to a known issue in some chipsets 4854 * which will cause the DCA tag to be cleared. 4855 */ 4856 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 4857 E1000_DCA_TXCTRL_DATA_RRO_EN | 4858 E1000_DCA_TXCTRL_DESC_DCA_EN; 4859 4860 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 4861 } 4862 4863 static void igb_update_rx_dca(struct igb_adapter *adapter, 4864 struct igb_ring *rx_ring, 4865 int cpu) 4866 { 4867 struct e1000_hw *hw = &adapter->hw; 4868 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 4869 4870 if (hw->mac.type != e1000_82575) 4871 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 4872 4873 /* 4874 * We can enable relaxed ordering for reads, but not writes when 4875 * DCA is enabled. This is due to a known issue in some chipsets 4876 * which will cause the DCA tag to be cleared. 4877 */ 4878 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 4879 E1000_DCA_RXCTRL_DESC_DCA_EN; 4880 4881 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 4882 } 4883 4884 static void igb_update_dca(struct igb_q_vector *q_vector) 4885 { 4886 struct igb_adapter *adapter = q_vector->adapter; 4887 int cpu = get_cpu(); 4888 4889 if (q_vector->cpu == cpu) 4890 goto out_no_update; 4891 4892 if (q_vector->tx.ring) 4893 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 4894 4895 if (q_vector->rx.ring) 4896 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 4897 4898 q_vector->cpu = cpu; 4899 out_no_update: 4900 put_cpu(); 4901 } 4902 4903 static void igb_setup_dca(struct igb_adapter *adapter) 4904 { 4905 struct e1000_hw *hw = &adapter->hw; 4906 int i; 4907 4908 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 4909 return; 4910 4911 /* Always use CB2 mode, difference is masked in the CB driver. */ 4912 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 4913 4914 for (i = 0; i < adapter->num_q_vectors; i++) { 4915 adapter->q_vector[i]->cpu = -1; 4916 igb_update_dca(adapter->q_vector[i]); 4917 } 4918 } 4919 4920 static int __igb_notify_dca(struct device *dev, void *data) 4921 { 4922 struct net_device *netdev = dev_get_drvdata(dev); 4923 struct igb_adapter *adapter = netdev_priv(netdev); 4924 struct pci_dev *pdev = adapter->pdev; 4925 struct e1000_hw *hw = &adapter->hw; 4926 unsigned long event = *(unsigned long *)data; 4927 4928 switch (event) { 4929 case DCA_PROVIDER_ADD: 4930 /* if already enabled, don't do it again */ 4931 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 4932 break; 4933 if (dca_add_requester(dev) == 0) { 4934 adapter->flags |= IGB_FLAG_DCA_ENABLED; 4935 dev_info(&pdev->dev, "DCA enabled\n"); 4936 igb_setup_dca(adapter); 4937 break; 4938 } 4939 /* Fall Through since DCA is disabled. */ 4940 case DCA_PROVIDER_REMOVE: 4941 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 4942 /* without this a class_device is left 4943 * hanging around in the sysfs model */ 4944 dca_remove_requester(dev); 4945 dev_info(&pdev->dev, "DCA disabled\n"); 4946 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 4947 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 4948 } 4949 break; 4950 } 4951 4952 return 0; 4953 } 4954 4955 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 4956 void *p) 4957 { 4958 int ret_val; 4959 4960 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 4961 __igb_notify_dca); 4962 4963 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 4964 } 4965 #endif /* CONFIG_IGB_DCA */ 4966 4967 #ifdef CONFIG_PCI_IOV 4968 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 4969 { 4970 unsigned char mac_addr[ETH_ALEN]; 4971 4972 eth_random_addr(mac_addr); 4973 igb_set_vf_mac(adapter, vf, mac_addr); 4974 4975 return 0; 4976 } 4977 4978 static bool igb_vfs_are_assigned(struct igb_adapter *adapter) 4979 { 4980 struct pci_dev *pdev = adapter->pdev; 4981 struct pci_dev *vfdev; 4982 int dev_id; 4983 4984 switch (adapter->hw.mac.type) { 4985 case e1000_82576: 4986 dev_id = IGB_82576_VF_DEV_ID; 4987 break; 4988 case e1000_i350: 4989 dev_id = IGB_I350_VF_DEV_ID; 4990 break; 4991 default: 4992 return false; 4993 } 4994 4995 /* loop through all the VFs to see if we own any that are assigned */ 4996 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); 4997 while (vfdev) { 4998 /* if we don't own it we don't care */ 4999 if (vfdev->is_virtfn && vfdev->physfn == pdev) { 5000 /* if it is assigned we cannot release it */ 5001 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) 5002 return true; 5003 } 5004 5005 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); 5006 } 5007 5008 return false; 5009 } 5010 5011 #endif 5012 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5013 { 5014 struct e1000_hw *hw = &adapter->hw; 5015 u32 ping; 5016 int i; 5017 5018 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5019 ping = E1000_PF_CONTROL_MSG; 5020 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5021 ping |= E1000_VT_MSGTYPE_CTS; 5022 igb_write_mbx(hw, &ping, 1, i); 5023 } 5024 } 5025 5026 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5027 { 5028 struct e1000_hw *hw = &adapter->hw; 5029 u32 vmolr = rd32(E1000_VMOLR(vf)); 5030 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5031 5032 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5033 IGB_VF_FLAG_MULTI_PROMISC); 5034 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5035 5036 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5037 vmolr |= E1000_VMOLR_MPME; 5038 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5039 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5040 } else { 5041 /* 5042 * if we have hashes and we are clearing a multicast promisc 5043 * flag we need to write the hashes to the MTA as this step 5044 * was previously skipped 5045 */ 5046 if (vf_data->num_vf_mc_hashes > 30) { 5047 vmolr |= E1000_VMOLR_MPME; 5048 } else if (vf_data->num_vf_mc_hashes) { 5049 int j; 5050 vmolr |= E1000_VMOLR_ROMPE; 5051 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5052 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5053 } 5054 } 5055 5056 wr32(E1000_VMOLR(vf), vmolr); 5057 5058 /* there are flags left unprocessed, likely not supported */ 5059 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5060 return -EINVAL; 5061 5062 return 0; 5063 5064 } 5065 5066 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5067 u32 *msgbuf, u32 vf) 5068 { 5069 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5070 u16 *hash_list = (u16 *)&msgbuf[1]; 5071 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5072 int i; 5073 5074 /* salt away the number of multicast addresses assigned 5075 * to this VF for later use to restore when the PF multi cast 5076 * list changes 5077 */ 5078 vf_data->num_vf_mc_hashes = n; 5079 5080 /* only up to 30 hash values supported */ 5081 if (n > 30) 5082 n = 30; 5083 5084 /* store the hashes for later use */ 5085 for (i = 0; i < n; i++) 5086 vf_data->vf_mc_hashes[i] = hash_list[i]; 5087 5088 /* Flush and reset the mta with the new values */ 5089 igb_set_rx_mode(adapter->netdev); 5090 5091 return 0; 5092 } 5093 5094 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5095 { 5096 struct e1000_hw *hw = &adapter->hw; 5097 struct vf_data_storage *vf_data; 5098 int i, j; 5099 5100 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5101 u32 vmolr = rd32(E1000_VMOLR(i)); 5102 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5103 5104 vf_data = &adapter->vf_data[i]; 5105 5106 if ((vf_data->num_vf_mc_hashes > 30) || 5107 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5108 vmolr |= E1000_VMOLR_MPME; 5109 } else if (vf_data->num_vf_mc_hashes) { 5110 vmolr |= E1000_VMOLR_ROMPE; 5111 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5112 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5113 } 5114 wr32(E1000_VMOLR(i), vmolr); 5115 } 5116 } 5117 5118 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5119 { 5120 struct e1000_hw *hw = &adapter->hw; 5121 u32 pool_mask, reg, vid; 5122 int i; 5123 5124 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5125 5126 /* Find the vlan filter for this id */ 5127 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5128 reg = rd32(E1000_VLVF(i)); 5129 5130 /* remove the vf from the pool */ 5131 reg &= ~pool_mask; 5132 5133 /* if pool is empty then remove entry from vfta */ 5134 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5135 (reg & E1000_VLVF_VLANID_ENABLE)) { 5136 reg = 0; 5137 vid = reg & E1000_VLVF_VLANID_MASK; 5138 igb_vfta_set(hw, vid, false); 5139 } 5140 5141 wr32(E1000_VLVF(i), reg); 5142 } 5143 5144 adapter->vf_data[vf].vlans_enabled = 0; 5145 } 5146 5147 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5148 { 5149 struct e1000_hw *hw = &adapter->hw; 5150 u32 reg, i; 5151 5152 /* The vlvf table only exists on 82576 hardware and newer */ 5153 if (hw->mac.type < e1000_82576) 5154 return -1; 5155 5156 /* we only need to do this if VMDq is enabled */ 5157 if (!adapter->vfs_allocated_count) 5158 return -1; 5159 5160 /* Find the vlan filter for this id */ 5161 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5162 reg = rd32(E1000_VLVF(i)); 5163 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5164 vid == (reg & E1000_VLVF_VLANID_MASK)) 5165 break; 5166 } 5167 5168 if (add) { 5169 if (i == E1000_VLVF_ARRAY_SIZE) { 5170 /* Did not find a matching VLAN ID entry that was 5171 * enabled. Search for a free filter entry, i.e. 5172 * one without the enable bit set 5173 */ 5174 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5175 reg = rd32(E1000_VLVF(i)); 5176 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5177 break; 5178 } 5179 } 5180 if (i < E1000_VLVF_ARRAY_SIZE) { 5181 /* Found an enabled/available entry */ 5182 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5183 5184 /* if !enabled we need to set this up in vfta */ 5185 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5186 /* add VID to filter table */ 5187 igb_vfta_set(hw, vid, true); 5188 reg |= E1000_VLVF_VLANID_ENABLE; 5189 } 5190 reg &= ~E1000_VLVF_VLANID_MASK; 5191 reg |= vid; 5192 wr32(E1000_VLVF(i), reg); 5193 5194 /* do not modify RLPML for PF devices */ 5195 if (vf >= adapter->vfs_allocated_count) 5196 return 0; 5197 5198 if (!adapter->vf_data[vf].vlans_enabled) { 5199 u32 size; 5200 reg = rd32(E1000_VMOLR(vf)); 5201 size = reg & E1000_VMOLR_RLPML_MASK; 5202 size += 4; 5203 reg &= ~E1000_VMOLR_RLPML_MASK; 5204 reg |= size; 5205 wr32(E1000_VMOLR(vf), reg); 5206 } 5207 5208 adapter->vf_data[vf].vlans_enabled++; 5209 } 5210 } else { 5211 if (i < E1000_VLVF_ARRAY_SIZE) { 5212 /* remove vf from the pool */ 5213 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5214 /* if pool is empty then remove entry from vfta */ 5215 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5216 reg = 0; 5217 igb_vfta_set(hw, vid, false); 5218 } 5219 wr32(E1000_VLVF(i), reg); 5220 5221 /* do not modify RLPML for PF devices */ 5222 if (vf >= adapter->vfs_allocated_count) 5223 return 0; 5224 5225 adapter->vf_data[vf].vlans_enabled--; 5226 if (!adapter->vf_data[vf].vlans_enabled) { 5227 u32 size; 5228 reg = rd32(E1000_VMOLR(vf)); 5229 size = reg & E1000_VMOLR_RLPML_MASK; 5230 size -= 4; 5231 reg &= ~E1000_VMOLR_RLPML_MASK; 5232 reg |= size; 5233 wr32(E1000_VMOLR(vf), reg); 5234 } 5235 } 5236 } 5237 return 0; 5238 } 5239 5240 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5241 { 5242 struct e1000_hw *hw = &adapter->hw; 5243 5244 if (vid) 5245 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5246 else 5247 wr32(E1000_VMVIR(vf), 0); 5248 } 5249 5250 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5251 int vf, u16 vlan, u8 qos) 5252 { 5253 int err = 0; 5254 struct igb_adapter *adapter = netdev_priv(netdev); 5255 5256 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5257 return -EINVAL; 5258 if (vlan || qos) { 5259 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5260 if (err) 5261 goto out; 5262 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5263 igb_set_vmolr(adapter, vf, !vlan); 5264 adapter->vf_data[vf].pf_vlan = vlan; 5265 adapter->vf_data[vf].pf_qos = qos; 5266 dev_info(&adapter->pdev->dev, 5267 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5268 if (test_bit(__IGB_DOWN, &adapter->state)) { 5269 dev_warn(&adapter->pdev->dev, 5270 "The VF VLAN has been set," 5271 " but the PF device is not up.\n"); 5272 dev_warn(&adapter->pdev->dev, 5273 "Bring the PF device up before" 5274 " attempting to use the VF device.\n"); 5275 } 5276 } else { 5277 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5278 false, vf); 5279 igb_set_vmvir(adapter, vlan, vf); 5280 igb_set_vmolr(adapter, vf, true); 5281 adapter->vf_data[vf].pf_vlan = 0; 5282 adapter->vf_data[vf].pf_qos = 0; 5283 } 5284 out: 5285 return err; 5286 } 5287 5288 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5289 { 5290 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5291 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5292 5293 return igb_vlvf_set(adapter, vid, add, vf); 5294 } 5295 5296 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5297 { 5298 /* clear flags - except flag that indicates PF has set the MAC */ 5299 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5300 adapter->vf_data[vf].last_nack = jiffies; 5301 5302 /* reset offloads to defaults */ 5303 igb_set_vmolr(adapter, vf, true); 5304 5305 /* reset vlans for device */ 5306 igb_clear_vf_vfta(adapter, vf); 5307 if (adapter->vf_data[vf].pf_vlan) 5308 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5309 adapter->vf_data[vf].pf_vlan, 5310 adapter->vf_data[vf].pf_qos); 5311 else 5312 igb_clear_vf_vfta(adapter, vf); 5313 5314 /* reset multicast table array for vf */ 5315 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5316 5317 /* Flush and reset the mta with the new values */ 5318 igb_set_rx_mode(adapter->netdev); 5319 } 5320 5321 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5322 { 5323 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5324 5325 /* generate a new mac address as we were hotplug removed/added */ 5326 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5327 eth_random_addr(vf_mac); 5328 5329 /* process remaining reset events */ 5330 igb_vf_reset(adapter, vf); 5331 } 5332 5333 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5334 { 5335 struct e1000_hw *hw = &adapter->hw; 5336 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5337 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5338 u32 reg, msgbuf[3]; 5339 u8 *addr = (u8 *)(&msgbuf[1]); 5340 5341 /* process all the same items cleared in a function level reset */ 5342 igb_vf_reset(adapter, vf); 5343 5344 /* set vf mac address */ 5345 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5346 5347 /* enable transmit and receive for vf */ 5348 reg = rd32(E1000_VFTE); 5349 wr32(E1000_VFTE, reg | (1 << vf)); 5350 reg = rd32(E1000_VFRE); 5351 wr32(E1000_VFRE, reg | (1 << vf)); 5352 5353 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5354 5355 /* reply to reset with ack and vf mac address */ 5356 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5357 memcpy(addr, vf_mac, 6); 5358 igb_write_mbx(hw, msgbuf, 3, vf); 5359 } 5360 5361 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5362 { 5363 /* 5364 * The VF MAC Address is stored in a packed array of bytes 5365 * starting at the second 32 bit word of the msg array 5366 */ 5367 unsigned char *addr = (char *)&msg[1]; 5368 int err = -1; 5369 5370 if (is_valid_ether_addr(addr)) 5371 err = igb_set_vf_mac(adapter, vf, addr); 5372 5373 return err; 5374 } 5375 5376 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5377 { 5378 struct e1000_hw *hw = &adapter->hw; 5379 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5380 u32 msg = E1000_VT_MSGTYPE_NACK; 5381 5382 /* if device isn't clear to send it shouldn't be reading either */ 5383 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5384 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5385 igb_write_mbx(hw, &msg, 1, vf); 5386 vf_data->last_nack = jiffies; 5387 } 5388 } 5389 5390 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5391 { 5392 struct pci_dev *pdev = adapter->pdev; 5393 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5394 struct e1000_hw *hw = &adapter->hw; 5395 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5396 s32 retval; 5397 5398 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5399 5400 if (retval) { 5401 /* if receive failed revoke VF CTS stats and restart init */ 5402 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5403 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5404 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5405 return; 5406 goto out; 5407 } 5408 5409 /* this is a message we already processed, do nothing */ 5410 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5411 return; 5412 5413 /* 5414 * until the vf completes a reset it should not be 5415 * allowed to start any configuration. 5416 */ 5417 5418 if (msgbuf[0] == E1000_VF_RESET) { 5419 igb_vf_reset_msg(adapter, vf); 5420 return; 5421 } 5422 5423 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5424 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5425 return; 5426 retval = -1; 5427 goto out; 5428 } 5429 5430 switch ((msgbuf[0] & 0xFFFF)) { 5431 case E1000_VF_SET_MAC_ADDR: 5432 retval = -EINVAL; 5433 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5434 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5435 else 5436 dev_warn(&pdev->dev, 5437 "VF %d attempted to override administratively " 5438 "set MAC address\nReload the VF driver to " 5439 "resume operations\n", vf); 5440 break; 5441 case E1000_VF_SET_PROMISC: 5442 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5443 break; 5444 case E1000_VF_SET_MULTICAST: 5445 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5446 break; 5447 case E1000_VF_SET_LPE: 5448 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 5449 break; 5450 case E1000_VF_SET_VLAN: 5451 retval = -1; 5452 if (vf_data->pf_vlan) 5453 dev_warn(&pdev->dev, 5454 "VF %d attempted to override administratively " 5455 "set VLAN tag\nReload the VF driver to " 5456 "resume operations\n", vf); 5457 else 5458 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 5459 break; 5460 default: 5461 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 5462 retval = -1; 5463 break; 5464 } 5465 5466 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 5467 out: 5468 /* notify the VF of the results of what it sent us */ 5469 if (retval) 5470 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 5471 else 5472 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 5473 5474 igb_write_mbx(hw, msgbuf, 1, vf); 5475 } 5476 5477 static void igb_msg_task(struct igb_adapter *adapter) 5478 { 5479 struct e1000_hw *hw = &adapter->hw; 5480 u32 vf; 5481 5482 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 5483 /* process any reset requests */ 5484 if (!igb_check_for_rst(hw, vf)) 5485 igb_vf_reset_event(adapter, vf); 5486 5487 /* process any messages pending */ 5488 if (!igb_check_for_msg(hw, vf)) 5489 igb_rcv_msg_from_vf(adapter, vf); 5490 5491 /* process any acks */ 5492 if (!igb_check_for_ack(hw, vf)) 5493 igb_rcv_ack_from_vf(adapter, vf); 5494 } 5495 } 5496 5497 /** 5498 * igb_set_uta - Set unicast filter table address 5499 * @adapter: board private structure 5500 * 5501 * The unicast table address is a register array of 32-bit registers. 5502 * The table is meant to be used in a way similar to how the MTA is used 5503 * however due to certain limitations in the hardware it is necessary to 5504 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 5505 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 5506 **/ 5507 static void igb_set_uta(struct igb_adapter *adapter) 5508 { 5509 struct e1000_hw *hw = &adapter->hw; 5510 int i; 5511 5512 /* The UTA table only exists on 82576 hardware and newer */ 5513 if (hw->mac.type < e1000_82576) 5514 return; 5515 5516 /* we only need to do this if VMDq is enabled */ 5517 if (!adapter->vfs_allocated_count) 5518 return; 5519 5520 for (i = 0; i < hw->mac.uta_reg_count; i++) 5521 array_wr32(E1000_UTA, i, ~0); 5522 } 5523 5524 /** 5525 * igb_intr_msi - Interrupt Handler 5526 * @irq: interrupt number 5527 * @data: pointer to a network interface device structure 5528 **/ 5529 static irqreturn_t igb_intr_msi(int irq, void *data) 5530 { 5531 struct igb_adapter *adapter = data; 5532 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5533 struct e1000_hw *hw = &adapter->hw; 5534 /* read ICR disables interrupts using IAM */ 5535 u32 icr = rd32(E1000_ICR); 5536 5537 igb_write_itr(q_vector); 5538 5539 if (icr & E1000_ICR_DRSTA) 5540 schedule_work(&adapter->reset_task); 5541 5542 if (icr & E1000_ICR_DOUTSYNC) { 5543 /* HW is reporting DMA is out of sync */ 5544 adapter->stats.doosync++; 5545 } 5546 5547 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5548 hw->mac.get_link_status = 1; 5549 if (!test_bit(__IGB_DOWN, &adapter->state)) 5550 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5551 } 5552 5553 if (icr & E1000_ICR_TS) { 5554 u32 tsicr = rd32(E1000_TSICR); 5555 5556 if (tsicr & E1000_TSICR_TXTS) { 5557 /* acknowledge the interrupt */ 5558 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5559 /* retrieve hardware timestamp */ 5560 schedule_work(&adapter->ptp_tx_work); 5561 } 5562 } 5563 5564 napi_schedule(&q_vector->napi); 5565 5566 return IRQ_HANDLED; 5567 } 5568 5569 /** 5570 * igb_intr - Legacy Interrupt Handler 5571 * @irq: interrupt number 5572 * @data: pointer to a network interface device structure 5573 **/ 5574 static irqreturn_t igb_intr(int irq, void *data) 5575 { 5576 struct igb_adapter *adapter = data; 5577 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5578 struct e1000_hw *hw = &adapter->hw; 5579 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5580 * need for the IMC write */ 5581 u32 icr = rd32(E1000_ICR); 5582 5583 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5584 * not set, then the adapter didn't send an interrupt */ 5585 if (!(icr & E1000_ICR_INT_ASSERTED)) 5586 return IRQ_NONE; 5587 5588 igb_write_itr(q_vector); 5589 5590 if (icr & E1000_ICR_DRSTA) 5591 schedule_work(&adapter->reset_task); 5592 5593 if (icr & E1000_ICR_DOUTSYNC) { 5594 /* HW is reporting DMA is out of sync */ 5595 adapter->stats.doosync++; 5596 } 5597 5598 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5599 hw->mac.get_link_status = 1; 5600 /* guard against interrupt when we're going down */ 5601 if (!test_bit(__IGB_DOWN, &adapter->state)) 5602 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5603 } 5604 5605 if (icr & E1000_ICR_TS) { 5606 u32 tsicr = rd32(E1000_TSICR); 5607 5608 if (tsicr & E1000_TSICR_TXTS) { 5609 /* acknowledge the interrupt */ 5610 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5611 /* retrieve hardware timestamp */ 5612 schedule_work(&adapter->ptp_tx_work); 5613 } 5614 } 5615 5616 napi_schedule(&q_vector->napi); 5617 5618 return IRQ_HANDLED; 5619 } 5620 5621 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 5622 { 5623 struct igb_adapter *adapter = q_vector->adapter; 5624 struct e1000_hw *hw = &adapter->hw; 5625 5626 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 5627 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 5628 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 5629 igb_set_itr(q_vector); 5630 else 5631 igb_update_ring_itr(q_vector); 5632 } 5633 5634 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5635 if (adapter->msix_entries) 5636 wr32(E1000_EIMS, q_vector->eims_value); 5637 else 5638 igb_irq_enable(adapter); 5639 } 5640 } 5641 5642 /** 5643 * igb_poll - NAPI Rx polling callback 5644 * @napi: napi polling structure 5645 * @budget: count of how many packets we should handle 5646 **/ 5647 static int igb_poll(struct napi_struct *napi, int budget) 5648 { 5649 struct igb_q_vector *q_vector = container_of(napi, 5650 struct igb_q_vector, 5651 napi); 5652 bool clean_complete = true; 5653 5654 #ifdef CONFIG_IGB_DCA 5655 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 5656 igb_update_dca(q_vector); 5657 #endif 5658 if (q_vector->tx.ring) 5659 clean_complete = igb_clean_tx_irq(q_vector); 5660 5661 if (q_vector->rx.ring) 5662 clean_complete &= igb_clean_rx_irq(q_vector, budget); 5663 5664 /* If all work not completed, return budget and keep polling */ 5665 if (!clean_complete) 5666 return budget; 5667 5668 /* If not enough Rx work done, exit the polling mode */ 5669 napi_complete(napi); 5670 igb_ring_irq_enable(q_vector); 5671 5672 return 0; 5673 } 5674 5675 /** 5676 * igb_clean_tx_irq - Reclaim resources after transmit completes 5677 * @q_vector: pointer to q_vector containing needed info 5678 * 5679 * returns true if ring is completely cleaned 5680 **/ 5681 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 5682 { 5683 struct igb_adapter *adapter = q_vector->adapter; 5684 struct igb_ring *tx_ring = q_vector->tx.ring; 5685 struct igb_tx_buffer *tx_buffer; 5686 union e1000_adv_tx_desc *tx_desc; 5687 unsigned int total_bytes = 0, total_packets = 0; 5688 unsigned int budget = q_vector->tx.work_limit; 5689 unsigned int i = tx_ring->next_to_clean; 5690 5691 if (test_bit(__IGB_DOWN, &adapter->state)) 5692 return true; 5693 5694 tx_buffer = &tx_ring->tx_buffer_info[i]; 5695 tx_desc = IGB_TX_DESC(tx_ring, i); 5696 i -= tx_ring->count; 5697 5698 do { 5699 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 5700 5701 /* if next_to_watch is not set then there is no work pending */ 5702 if (!eop_desc) 5703 break; 5704 5705 /* prevent any other reads prior to eop_desc */ 5706 rmb(); 5707 5708 /* if DD is not set pending work has not been completed */ 5709 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 5710 break; 5711 5712 /* clear next_to_watch to prevent false hangs */ 5713 tx_buffer->next_to_watch = NULL; 5714 5715 /* update the statistics for this packet */ 5716 total_bytes += tx_buffer->bytecount; 5717 total_packets += tx_buffer->gso_segs; 5718 5719 /* free the skb */ 5720 dev_kfree_skb_any(tx_buffer->skb); 5721 5722 /* unmap skb header data */ 5723 dma_unmap_single(tx_ring->dev, 5724 dma_unmap_addr(tx_buffer, dma), 5725 dma_unmap_len(tx_buffer, len), 5726 DMA_TO_DEVICE); 5727 5728 /* clear tx_buffer data */ 5729 tx_buffer->skb = NULL; 5730 dma_unmap_len_set(tx_buffer, len, 0); 5731 5732 /* clear last DMA location and unmap remaining buffers */ 5733 while (tx_desc != eop_desc) { 5734 tx_buffer++; 5735 tx_desc++; 5736 i++; 5737 if (unlikely(!i)) { 5738 i -= tx_ring->count; 5739 tx_buffer = tx_ring->tx_buffer_info; 5740 tx_desc = IGB_TX_DESC(tx_ring, 0); 5741 } 5742 5743 /* unmap any remaining paged data */ 5744 if (dma_unmap_len(tx_buffer, len)) { 5745 dma_unmap_page(tx_ring->dev, 5746 dma_unmap_addr(tx_buffer, dma), 5747 dma_unmap_len(tx_buffer, len), 5748 DMA_TO_DEVICE); 5749 dma_unmap_len_set(tx_buffer, len, 0); 5750 } 5751 } 5752 5753 /* move us one more past the eop_desc for start of next pkt */ 5754 tx_buffer++; 5755 tx_desc++; 5756 i++; 5757 if (unlikely(!i)) { 5758 i -= tx_ring->count; 5759 tx_buffer = tx_ring->tx_buffer_info; 5760 tx_desc = IGB_TX_DESC(tx_ring, 0); 5761 } 5762 5763 /* issue prefetch for next Tx descriptor */ 5764 prefetch(tx_desc); 5765 5766 /* update budget accounting */ 5767 budget--; 5768 } while (likely(budget)); 5769 5770 netdev_tx_completed_queue(txring_txq(tx_ring), 5771 total_packets, total_bytes); 5772 i += tx_ring->count; 5773 tx_ring->next_to_clean = i; 5774 u64_stats_update_begin(&tx_ring->tx_syncp); 5775 tx_ring->tx_stats.bytes += total_bytes; 5776 tx_ring->tx_stats.packets += total_packets; 5777 u64_stats_update_end(&tx_ring->tx_syncp); 5778 q_vector->tx.total_bytes += total_bytes; 5779 q_vector->tx.total_packets += total_packets; 5780 5781 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 5782 struct e1000_hw *hw = &adapter->hw; 5783 5784 /* Detect a transmit hang in hardware, this serializes the 5785 * check with the clearing of time_stamp and movement of i */ 5786 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5787 if (tx_buffer->next_to_watch && 5788 time_after(jiffies, tx_buffer->time_stamp + 5789 (adapter->tx_timeout_factor * HZ)) && 5790 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 5791 5792 /* detected Tx unit hang */ 5793 dev_err(tx_ring->dev, 5794 "Detected Tx Unit Hang\n" 5795 " Tx Queue <%d>\n" 5796 " TDH <%x>\n" 5797 " TDT <%x>\n" 5798 " next_to_use <%x>\n" 5799 " next_to_clean <%x>\n" 5800 "buffer_info[next_to_clean]\n" 5801 " time_stamp <%lx>\n" 5802 " next_to_watch <%p>\n" 5803 " jiffies <%lx>\n" 5804 " desc.status <%x>\n", 5805 tx_ring->queue_index, 5806 rd32(E1000_TDH(tx_ring->reg_idx)), 5807 readl(tx_ring->tail), 5808 tx_ring->next_to_use, 5809 tx_ring->next_to_clean, 5810 tx_buffer->time_stamp, 5811 tx_buffer->next_to_watch, 5812 jiffies, 5813 tx_buffer->next_to_watch->wb.status); 5814 netif_stop_subqueue(tx_ring->netdev, 5815 tx_ring->queue_index); 5816 5817 /* we are about to reset, no point in enabling stuff */ 5818 return true; 5819 } 5820 } 5821 5822 if (unlikely(total_packets && 5823 netif_carrier_ok(tx_ring->netdev) && 5824 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { 5825 /* Make sure that anybody stopping the queue after this 5826 * sees the new next_to_clean. 5827 */ 5828 smp_mb(); 5829 if (__netif_subqueue_stopped(tx_ring->netdev, 5830 tx_ring->queue_index) && 5831 !(test_bit(__IGB_DOWN, &adapter->state))) { 5832 netif_wake_subqueue(tx_ring->netdev, 5833 tx_ring->queue_index); 5834 5835 u64_stats_update_begin(&tx_ring->tx_syncp); 5836 tx_ring->tx_stats.restart_queue++; 5837 u64_stats_update_end(&tx_ring->tx_syncp); 5838 } 5839 } 5840 5841 return !!budget; 5842 } 5843 5844 /** 5845 * igb_reuse_rx_page - page flip buffer and store it back on the ring 5846 * @rx_ring: rx descriptor ring to store buffers on 5847 * @old_buff: donor buffer to have page reused 5848 * 5849 * Synchronizes page for reuse by the adapter 5850 **/ 5851 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 5852 struct igb_rx_buffer *old_buff) 5853 { 5854 struct igb_rx_buffer *new_buff; 5855 u16 nta = rx_ring->next_to_alloc; 5856 5857 new_buff = &rx_ring->rx_buffer_info[nta]; 5858 5859 /* update, and store next to alloc */ 5860 nta++; 5861 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 5862 5863 /* transfer page from old buffer to new buffer */ 5864 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 5865 5866 /* sync the buffer for use by the device */ 5867 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 5868 old_buff->page_offset, 5869 IGB_RX_BUFSZ, 5870 DMA_FROM_DEVICE); 5871 } 5872 5873 /** 5874 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 5875 * @rx_ring: rx descriptor ring to transact packets on 5876 * @rx_buffer: buffer containing page to add 5877 * @rx_desc: descriptor containing length of buffer written by hardware 5878 * @skb: sk_buff to place the data into 5879 * 5880 * This function will add the data contained in rx_buffer->page to the skb. 5881 * This is done either through a direct copy if the data in the buffer is 5882 * less than the skb header size, otherwise it will just attach the page as 5883 * a frag to the skb. 5884 * 5885 * The function will then update the page offset if necessary and return 5886 * true if the buffer can be reused by the adapter. 5887 **/ 5888 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 5889 struct igb_rx_buffer *rx_buffer, 5890 union e1000_adv_rx_desc *rx_desc, 5891 struct sk_buff *skb) 5892 { 5893 struct page *page = rx_buffer->page; 5894 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 5895 5896 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 5897 unsigned char *va = page_address(page) + rx_buffer->page_offset; 5898 5899 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 5900 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 5901 va += IGB_TS_HDR_LEN; 5902 size -= IGB_TS_HDR_LEN; 5903 } 5904 5905 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 5906 5907 /* we can reuse buffer as-is, just make sure it is local */ 5908 if (likely(page_to_nid(page) == numa_node_id())) 5909 return true; 5910 5911 /* this page cannot be reused so discard it */ 5912 put_page(page); 5913 return false; 5914 } 5915 5916 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 5917 rx_buffer->page_offset, size, IGB_RX_BUFSZ); 5918 5919 /* avoid re-using remote pages */ 5920 if (unlikely(page_to_nid(page) != numa_node_id())) 5921 return false; 5922 5923 #if (PAGE_SIZE < 8192) 5924 /* if we are only owner of page we can reuse it */ 5925 if (unlikely(page_count(page) != 1)) 5926 return false; 5927 5928 /* flip page offset to other buffer */ 5929 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 5930 5931 /* 5932 * since we are the only owner of the page and we need to 5933 * increment it, just set the value to 2 in order to avoid 5934 * an unnecessary locked operation 5935 */ 5936 atomic_set(&page->_count, 2); 5937 #else 5938 /* move offset up to the next cache line */ 5939 rx_buffer->page_offset += SKB_DATA_ALIGN(size); 5940 5941 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 5942 return false; 5943 5944 /* bump ref count on page before it is given to the stack */ 5945 get_page(page); 5946 #endif 5947 5948 return true; 5949 } 5950 5951 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 5952 union e1000_adv_rx_desc *rx_desc, 5953 struct sk_buff *skb) 5954 { 5955 struct igb_rx_buffer *rx_buffer; 5956 struct page *page; 5957 5958 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 5959 5960 /* 5961 * This memory barrier is needed to keep us from reading 5962 * any other fields out of the rx_desc until we know the 5963 * RXD_STAT_DD bit is set 5964 */ 5965 rmb(); 5966 5967 page = rx_buffer->page; 5968 prefetchw(page); 5969 5970 if (likely(!skb)) { 5971 void *page_addr = page_address(page) + 5972 rx_buffer->page_offset; 5973 5974 /* prefetch first cache line of first page */ 5975 prefetch(page_addr); 5976 #if L1_CACHE_BYTES < 128 5977 prefetch(page_addr + L1_CACHE_BYTES); 5978 #endif 5979 5980 /* allocate a skb to store the frags */ 5981 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 5982 IGB_RX_HDR_LEN); 5983 if (unlikely(!skb)) { 5984 rx_ring->rx_stats.alloc_failed++; 5985 return NULL; 5986 } 5987 5988 /* 5989 * we will be copying header into skb->data in 5990 * pskb_may_pull so it is in our interest to prefetch 5991 * it now to avoid a possible cache miss 5992 */ 5993 prefetchw(skb->data); 5994 } 5995 5996 /* we are reusing so sync this buffer for CPU use */ 5997 dma_sync_single_range_for_cpu(rx_ring->dev, 5998 rx_buffer->dma, 5999 rx_buffer->page_offset, 6000 IGB_RX_BUFSZ, 6001 DMA_FROM_DEVICE); 6002 6003 /* pull page into skb */ 6004 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6005 /* hand second half of page back to the ring */ 6006 igb_reuse_rx_page(rx_ring, rx_buffer); 6007 } else { 6008 /* we are not reusing the buffer so unmap it */ 6009 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6010 PAGE_SIZE, DMA_FROM_DEVICE); 6011 } 6012 6013 /* clear contents of rx_buffer */ 6014 rx_buffer->page = NULL; 6015 6016 return skb; 6017 } 6018 6019 static inline void igb_rx_checksum(struct igb_ring *ring, 6020 union e1000_adv_rx_desc *rx_desc, 6021 struct sk_buff *skb) 6022 { 6023 skb_checksum_none_assert(skb); 6024 6025 /* Ignore Checksum bit is set */ 6026 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6027 return; 6028 6029 /* Rx checksum disabled via ethtool */ 6030 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6031 return; 6032 6033 /* TCP/UDP checksum error bit is set */ 6034 if (igb_test_staterr(rx_desc, 6035 E1000_RXDEXT_STATERR_TCPE | 6036 E1000_RXDEXT_STATERR_IPE)) { 6037 /* 6038 * work around errata with sctp packets where the TCPE aka 6039 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6040 * packets, (aka let the stack check the crc32c) 6041 */ 6042 if (!((skb->len == 60) && 6043 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6044 u64_stats_update_begin(&ring->rx_syncp); 6045 ring->rx_stats.csum_err++; 6046 u64_stats_update_end(&ring->rx_syncp); 6047 } 6048 /* let the stack verify checksum errors */ 6049 return; 6050 } 6051 /* It must be a TCP or UDP packet with a valid checksum */ 6052 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6053 E1000_RXD_STAT_UDPCS)) 6054 skb->ip_summed = CHECKSUM_UNNECESSARY; 6055 6056 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6057 le32_to_cpu(rx_desc->wb.upper.status_error)); 6058 } 6059 6060 static inline void igb_rx_hash(struct igb_ring *ring, 6061 union e1000_adv_rx_desc *rx_desc, 6062 struct sk_buff *skb) 6063 { 6064 if (ring->netdev->features & NETIF_F_RXHASH) 6065 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 6066 } 6067 6068 /** 6069 * igb_is_non_eop - process handling of non-EOP buffers 6070 * @rx_ring: Rx ring being processed 6071 * @rx_desc: Rx descriptor for current buffer 6072 * @skb: current socket buffer containing buffer in progress 6073 * 6074 * This function updates next to clean. If the buffer is an EOP buffer 6075 * this function exits returning false, otherwise it will place the 6076 * sk_buff in the next buffer to be chained and return true indicating 6077 * that this is in fact a non-EOP buffer. 6078 **/ 6079 static bool igb_is_non_eop(struct igb_ring *rx_ring, 6080 union e1000_adv_rx_desc *rx_desc) 6081 { 6082 u32 ntc = rx_ring->next_to_clean + 1; 6083 6084 /* fetch, update, and store next to clean */ 6085 ntc = (ntc < rx_ring->count) ? ntc : 0; 6086 rx_ring->next_to_clean = ntc; 6087 6088 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6089 6090 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6091 return false; 6092 6093 return true; 6094 } 6095 6096 /** 6097 * igb_get_headlen - determine size of header for LRO/GRO 6098 * @data: pointer to the start of the headers 6099 * @max_len: total length of section to find headers in 6100 * 6101 * This function is meant to determine the length of headers that will 6102 * be recognized by hardware for LRO, and GRO offloads. The main 6103 * motivation of doing this is to only perform one pull for IPv4 TCP 6104 * packets so that we can do basic things like calculating the gso_size 6105 * based on the average data per packet. 6106 **/ 6107 static unsigned int igb_get_headlen(unsigned char *data, 6108 unsigned int max_len) 6109 { 6110 union { 6111 unsigned char *network; 6112 /* l2 headers */ 6113 struct ethhdr *eth; 6114 struct vlan_hdr *vlan; 6115 /* l3 headers */ 6116 struct iphdr *ipv4; 6117 struct ipv6hdr *ipv6; 6118 } hdr; 6119 __be16 protocol; 6120 u8 nexthdr = 0; /* default to not TCP */ 6121 u8 hlen; 6122 6123 /* this should never happen, but better safe than sorry */ 6124 if (max_len < ETH_HLEN) 6125 return max_len; 6126 6127 /* initialize network frame pointer */ 6128 hdr.network = data; 6129 6130 /* set first protocol and move network header forward */ 6131 protocol = hdr.eth->h_proto; 6132 hdr.network += ETH_HLEN; 6133 6134 /* handle any vlan tag if present */ 6135 if (protocol == __constant_htons(ETH_P_8021Q)) { 6136 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6137 return max_len; 6138 6139 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6140 hdr.network += VLAN_HLEN; 6141 } 6142 6143 /* handle L3 protocols */ 6144 if (protocol == __constant_htons(ETH_P_IP)) { 6145 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6146 return max_len; 6147 6148 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6149 hlen = (hdr.network[0] & 0x0F) << 2; 6150 6151 /* verify hlen meets minimum size requirements */ 6152 if (hlen < sizeof(struct iphdr)) 6153 return hdr.network - data; 6154 6155 /* record next protocol if header is present */ 6156 if (!hdr.ipv4->frag_off) 6157 nexthdr = hdr.ipv4->protocol; 6158 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6159 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6160 return max_len; 6161 6162 /* record next protocol */ 6163 nexthdr = hdr.ipv6->nexthdr; 6164 hlen = sizeof(struct ipv6hdr); 6165 } else { 6166 return hdr.network - data; 6167 } 6168 6169 /* relocate pointer to start of L4 header */ 6170 hdr.network += hlen; 6171 6172 /* finally sort out TCP */ 6173 if (nexthdr == IPPROTO_TCP) { 6174 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6175 return max_len; 6176 6177 /* access doff as a u8 to avoid unaligned access on ia64 */ 6178 hlen = (hdr.network[12] & 0xF0) >> 2; 6179 6180 /* verify hlen meets minimum size requirements */ 6181 if (hlen < sizeof(struct tcphdr)) 6182 return hdr.network - data; 6183 6184 hdr.network += hlen; 6185 } else if (nexthdr == IPPROTO_UDP) { 6186 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6187 return max_len; 6188 6189 hdr.network += sizeof(struct udphdr); 6190 } 6191 6192 /* 6193 * If everything has gone correctly hdr.network should be the 6194 * data section of the packet and will be the end of the header. 6195 * If not then it probably represents the end of the last recognized 6196 * header. 6197 */ 6198 if ((hdr.network - data) < max_len) 6199 return hdr.network - data; 6200 else 6201 return max_len; 6202 } 6203 6204 /** 6205 * igb_pull_tail - igb specific version of skb_pull_tail 6206 * @rx_ring: rx descriptor ring packet is being transacted on 6207 * @rx_desc: pointer to the EOP Rx descriptor 6208 * @skb: pointer to current skb being adjusted 6209 * 6210 * This function is an igb specific version of __pskb_pull_tail. The 6211 * main difference between this version and the original function is that 6212 * this function can make several assumptions about the state of things 6213 * that allow for significant optimizations versus the standard function. 6214 * As a result we can do things like drop a frag and maintain an accurate 6215 * truesize for the skb. 6216 */ 6217 static void igb_pull_tail(struct igb_ring *rx_ring, 6218 union e1000_adv_rx_desc *rx_desc, 6219 struct sk_buff *skb) 6220 { 6221 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6222 unsigned char *va; 6223 unsigned int pull_len; 6224 6225 /* 6226 * it is valid to use page_address instead of kmap since we are 6227 * working with pages allocated out of the lomem pool per 6228 * alloc_page(GFP_ATOMIC) 6229 */ 6230 va = skb_frag_address(frag); 6231 6232 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6233 /* retrieve timestamp from buffer */ 6234 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6235 6236 /* update pointers to remove timestamp header */ 6237 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6238 frag->page_offset += IGB_TS_HDR_LEN; 6239 skb->data_len -= IGB_TS_HDR_LEN; 6240 skb->len -= IGB_TS_HDR_LEN; 6241 6242 /* move va to start of packet data */ 6243 va += IGB_TS_HDR_LEN; 6244 } 6245 6246 /* 6247 * we need the header to contain the greater of either ETH_HLEN or 6248 * 60 bytes if the skb->len is less than 60 for skb_pad. 6249 */ 6250 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6251 6252 /* align pull length to size of long to optimize memcpy performance */ 6253 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6254 6255 /* update all of the pointers */ 6256 skb_frag_size_sub(frag, pull_len); 6257 frag->page_offset += pull_len; 6258 skb->data_len -= pull_len; 6259 skb->tail += pull_len; 6260 } 6261 6262 /** 6263 * igb_cleanup_headers - Correct corrupted or empty headers 6264 * @rx_ring: rx descriptor ring packet is being transacted on 6265 * @rx_desc: pointer to the EOP Rx descriptor 6266 * @skb: pointer to current skb being fixed 6267 * 6268 * Address the case where we are pulling data in on pages only 6269 * and as such no data is present in the skb header. 6270 * 6271 * In addition if skb is not at least 60 bytes we need to pad it so that 6272 * it is large enough to qualify as a valid Ethernet frame. 6273 * 6274 * Returns true if an error was encountered and skb was freed. 6275 **/ 6276 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6277 union e1000_adv_rx_desc *rx_desc, 6278 struct sk_buff *skb) 6279 { 6280 6281 if (unlikely((igb_test_staterr(rx_desc, 6282 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6283 struct net_device *netdev = rx_ring->netdev; 6284 if (!(netdev->features & NETIF_F_RXALL)) { 6285 dev_kfree_skb_any(skb); 6286 return true; 6287 } 6288 } 6289 6290 /* place header in linear portion of buffer */ 6291 if (skb_is_nonlinear(skb)) 6292 igb_pull_tail(rx_ring, rx_desc, skb); 6293 6294 /* if skb_pad returns an error the skb was freed */ 6295 if (unlikely(skb->len < 60)) { 6296 int pad_len = 60 - skb->len; 6297 6298 if (skb_pad(skb, pad_len)) 6299 return true; 6300 __skb_put(skb, pad_len); 6301 } 6302 6303 return false; 6304 } 6305 6306 /** 6307 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6308 * @rx_ring: rx descriptor ring packet is being transacted on 6309 * @rx_desc: pointer to the EOP Rx descriptor 6310 * @skb: pointer to current skb being populated 6311 * 6312 * This function checks the ring, descriptor, and packet information in 6313 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6314 * other fields within the skb. 6315 **/ 6316 static void igb_process_skb_fields(struct igb_ring *rx_ring, 6317 union e1000_adv_rx_desc *rx_desc, 6318 struct sk_buff *skb) 6319 { 6320 struct net_device *dev = rx_ring->netdev; 6321 6322 igb_rx_hash(rx_ring, rx_desc, skb); 6323 6324 igb_rx_checksum(rx_ring, rx_desc, skb); 6325 6326 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); 6327 6328 if ((dev->features & NETIF_F_HW_VLAN_RX) && 6329 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6330 u16 vid; 6331 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6332 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6333 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6334 else 6335 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6336 6337 __vlan_hwaccel_put_tag(skb, vid); 6338 } 6339 6340 skb_record_rx_queue(skb, rx_ring->queue_index); 6341 6342 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6343 } 6344 6345 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6346 { 6347 struct igb_ring *rx_ring = q_vector->rx.ring; 6348 struct sk_buff *skb = rx_ring->skb; 6349 unsigned int total_bytes = 0, total_packets = 0; 6350 u16 cleaned_count = igb_desc_unused(rx_ring); 6351 6352 do { 6353 union e1000_adv_rx_desc *rx_desc; 6354 6355 /* return some buffers to hardware, one at a time is too slow */ 6356 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6357 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6358 cleaned_count = 0; 6359 } 6360 6361 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6362 6363 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6364 break; 6365 6366 /* retrieve a buffer from the ring */ 6367 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6368 6369 /* exit if we failed to retrieve a buffer */ 6370 if (!skb) 6371 break; 6372 6373 cleaned_count++; 6374 6375 /* fetch next buffer in frame if non-eop */ 6376 if (igb_is_non_eop(rx_ring, rx_desc)) 6377 continue; 6378 6379 /* verify the packet layout is correct */ 6380 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6381 skb = NULL; 6382 continue; 6383 } 6384 6385 /* probably a little skewed due to removing CRC */ 6386 total_bytes += skb->len; 6387 6388 /* populate checksum, timestamp, VLAN, and protocol */ 6389 igb_process_skb_fields(rx_ring, rx_desc, skb); 6390 6391 napi_gro_receive(&q_vector->napi, skb); 6392 6393 /* reset skb pointer */ 6394 skb = NULL; 6395 6396 /* update budget accounting */ 6397 total_packets++; 6398 } while (likely(total_packets < budget)); 6399 6400 /* place incomplete frames back on ring for completion */ 6401 rx_ring->skb = skb; 6402 6403 u64_stats_update_begin(&rx_ring->rx_syncp); 6404 rx_ring->rx_stats.packets += total_packets; 6405 rx_ring->rx_stats.bytes += total_bytes; 6406 u64_stats_update_end(&rx_ring->rx_syncp); 6407 q_vector->rx.total_packets += total_packets; 6408 q_vector->rx.total_bytes += total_bytes; 6409 6410 if (cleaned_count) 6411 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6412 6413 return (total_packets < budget); 6414 } 6415 6416 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6417 struct igb_rx_buffer *bi) 6418 { 6419 struct page *page = bi->page; 6420 dma_addr_t dma; 6421 6422 /* since we are recycling buffers we should seldom need to alloc */ 6423 if (likely(page)) 6424 return true; 6425 6426 /* alloc new page for storage */ 6427 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 6428 if (unlikely(!page)) { 6429 rx_ring->rx_stats.alloc_failed++; 6430 return false; 6431 } 6432 6433 /* map page for use */ 6434 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 6435 6436 /* 6437 * if mapping failed free memory back to system since 6438 * there isn't much point in holding memory we can't use 6439 */ 6440 if (dma_mapping_error(rx_ring->dev, dma)) { 6441 __free_page(page); 6442 6443 rx_ring->rx_stats.alloc_failed++; 6444 return false; 6445 } 6446 6447 bi->dma = dma; 6448 bi->page = page; 6449 bi->page_offset = 0; 6450 6451 return true; 6452 } 6453 6454 /** 6455 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 6456 * @adapter: address of board private structure 6457 **/ 6458 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 6459 { 6460 union e1000_adv_rx_desc *rx_desc; 6461 struct igb_rx_buffer *bi; 6462 u16 i = rx_ring->next_to_use; 6463 6464 /* nothing to do */ 6465 if (!cleaned_count) 6466 return; 6467 6468 rx_desc = IGB_RX_DESC(rx_ring, i); 6469 bi = &rx_ring->rx_buffer_info[i]; 6470 i -= rx_ring->count; 6471 6472 do { 6473 if (!igb_alloc_mapped_page(rx_ring, bi)) 6474 break; 6475 6476 /* 6477 * Refresh the desc even if buffer_addrs didn't change 6478 * because each write-back erases this info. 6479 */ 6480 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 6481 6482 rx_desc++; 6483 bi++; 6484 i++; 6485 if (unlikely(!i)) { 6486 rx_desc = IGB_RX_DESC(rx_ring, 0); 6487 bi = rx_ring->rx_buffer_info; 6488 i -= rx_ring->count; 6489 } 6490 6491 /* clear the hdr_addr for the next_to_use descriptor */ 6492 rx_desc->read.hdr_addr = 0; 6493 6494 cleaned_count--; 6495 } while (cleaned_count); 6496 6497 i += rx_ring->count; 6498 6499 if (rx_ring->next_to_use != i) { 6500 /* record the next descriptor to use */ 6501 rx_ring->next_to_use = i; 6502 6503 /* update next to alloc since we have filled the ring */ 6504 rx_ring->next_to_alloc = i; 6505 6506 /* 6507 * Force memory writes to complete before letting h/w 6508 * know there are new descriptors to fetch. (Only 6509 * applicable for weak-ordered memory model archs, 6510 * such as IA-64). 6511 */ 6512 wmb(); 6513 writel(i, rx_ring->tail); 6514 } 6515 } 6516 6517 /** 6518 * igb_mii_ioctl - 6519 * @netdev: 6520 * @ifreq: 6521 * @cmd: 6522 **/ 6523 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6524 { 6525 struct igb_adapter *adapter = netdev_priv(netdev); 6526 struct mii_ioctl_data *data = if_mii(ifr); 6527 6528 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6529 return -EOPNOTSUPP; 6530 6531 switch (cmd) { 6532 case SIOCGMIIPHY: 6533 data->phy_id = adapter->hw.phy.addr; 6534 break; 6535 case SIOCGMIIREG: 6536 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 6537 &data->val_out)) 6538 return -EIO; 6539 break; 6540 case SIOCSMIIREG: 6541 default: 6542 return -EOPNOTSUPP; 6543 } 6544 return 0; 6545 } 6546 6547 /** 6548 * igb_ioctl - 6549 * @netdev: 6550 * @ifreq: 6551 * @cmd: 6552 **/ 6553 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6554 { 6555 switch (cmd) { 6556 case SIOCGMIIPHY: 6557 case SIOCGMIIREG: 6558 case SIOCSMIIREG: 6559 return igb_mii_ioctl(netdev, ifr, cmd); 6560 case SIOCSHWTSTAMP: 6561 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 6562 default: 6563 return -EOPNOTSUPP; 6564 } 6565 } 6566 6567 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6568 { 6569 struct igb_adapter *adapter = hw->back; 6570 6571 if (pcie_capability_read_word(adapter->pdev, reg, value)) 6572 return -E1000_ERR_CONFIG; 6573 6574 return 0; 6575 } 6576 6577 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6578 { 6579 struct igb_adapter *adapter = hw->back; 6580 6581 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 6582 return -E1000_ERR_CONFIG; 6583 6584 return 0; 6585 } 6586 6587 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 6588 { 6589 struct igb_adapter *adapter = netdev_priv(netdev); 6590 struct e1000_hw *hw = &adapter->hw; 6591 u32 ctrl, rctl; 6592 bool enable = !!(features & NETIF_F_HW_VLAN_RX); 6593 6594 if (enable) { 6595 /* enable VLAN tag insert/strip */ 6596 ctrl = rd32(E1000_CTRL); 6597 ctrl |= E1000_CTRL_VME; 6598 wr32(E1000_CTRL, ctrl); 6599 6600 /* Disable CFI check */ 6601 rctl = rd32(E1000_RCTL); 6602 rctl &= ~E1000_RCTL_CFIEN; 6603 wr32(E1000_RCTL, rctl); 6604 } else { 6605 /* disable VLAN tag insert/strip */ 6606 ctrl = rd32(E1000_CTRL); 6607 ctrl &= ~E1000_CTRL_VME; 6608 wr32(E1000_CTRL, ctrl); 6609 } 6610 6611 igb_rlpml_set(adapter); 6612 } 6613 6614 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 6615 { 6616 struct igb_adapter *adapter = netdev_priv(netdev); 6617 struct e1000_hw *hw = &adapter->hw; 6618 int pf_id = adapter->vfs_allocated_count; 6619 6620 /* attempt to add filter to vlvf array */ 6621 igb_vlvf_set(adapter, vid, true, pf_id); 6622 6623 /* add the filter since PF can receive vlans w/o entry in vlvf */ 6624 igb_vfta_set(hw, vid, true); 6625 6626 set_bit(vid, adapter->active_vlans); 6627 6628 return 0; 6629 } 6630 6631 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 6632 { 6633 struct igb_adapter *adapter = netdev_priv(netdev); 6634 struct e1000_hw *hw = &adapter->hw; 6635 int pf_id = adapter->vfs_allocated_count; 6636 s32 err; 6637 6638 /* remove vlan from VLVF table array */ 6639 err = igb_vlvf_set(adapter, vid, false, pf_id); 6640 6641 /* if vid was not present in VLVF just remove it from table */ 6642 if (err) 6643 igb_vfta_set(hw, vid, false); 6644 6645 clear_bit(vid, adapter->active_vlans); 6646 6647 return 0; 6648 } 6649 6650 static void igb_restore_vlan(struct igb_adapter *adapter) 6651 { 6652 u16 vid; 6653 6654 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 6655 6656 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 6657 igb_vlan_rx_add_vid(adapter->netdev, vid); 6658 } 6659 6660 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 6661 { 6662 struct pci_dev *pdev = adapter->pdev; 6663 struct e1000_mac_info *mac = &adapter->hw.mac; 6664 6665 mac->autoneg = 0; 6666 6667 /* Make sure dplx is at most 1 bit and lsb of speed is not set 6668 * for the switch() below to work */ 6669 if ((spd & 1) || (dplx & ~1)) 6670 goto err_inval; 6671 6672 /* Fiber NIC's only allow 1000 Gbps Full duplex */ 6673 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && 6674 spd != SPEED_1000 && 6675 dplx != DUPLEX_FULL) 6676 goto err_inval; 6677 6678 switch (spd + dplx) { 6679 case SPEED_10 + DUPLEX_HALF: 6680 mac->forced_speed_duplex = ADVERTISE_10_HALF; 6681 break; 6682 case SPEED_10 + DUPLEX_FULL: 6683 mac->forced_speed_duplex = ADVERTISE_10_FULL; 6684 break; 6685 case SPEED_100 + DUPLEX_HALF: 6686 mac->forced_speed_duplex = ADVERTISE_100_HALF; 6687 break; 6688 case SPEED_100 + DUPLEX_FULL: 6689 mac->forced_speed_duplex = ADVERTISE_100_FULL; 6690 break; 6691 case SPEED_1000 + DUPLEX_FULL: 6692 mac->autoneg = 1; 6693 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 6694 break; 6695 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 6696 default: 6697 goto err_inval; 6698 } 6699 6700 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 6701 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6702 6703 return 0; 6704 6705 err_inval: 6706 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 6707 return -EINVAL; 6708 } 6709 6710 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 6711 bool runtime) 6712 { 6713 struct net_device *netdev = pci_get_drvdata(pdev); 6714 struct igb_adapter *adapter = netdev_priv(netdev); 6715 struct e1000_hw *hw = &adapter->hw; 6716 u32 ctrl, rctl, status; 6717 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6718 #ifdef CONFIG_PM 6719 int retval = 0; 6720 #endif 6721 6722 netif_device_detach(netdev); 6723 6724 if (netif_running(netdev)) 6725 __igb_close(netdev, true); 6726 6727 igb_clear_interrupt_scheme(adapter); 6728 6729 #ifdef CONFIG_PM 6730 retval = pci_save_state(pdev); 6731 if (retval) 6732 return retval; 6733 #endif 6734 6735 status = rd32(E1000_STATUS); 6736 if (status & E1000_STATUS_LU) 6737 wufc &= ~E1000_WUFC_LNKC; 6738 6739 if (wufc) { 6740 igb_setup_rctl(adapter); 6741 igb_set_rx_mode(netdev); 6742 6743 /* turn on all-multi mode if wake on multicast is enabled */ 6744 if (wufc & E1000_WUFC_MC) { 6745 rctl = rd32(E1000_RCTL); 6746 rctl |= E1000_RCTL_MPE; 6747 wr32(E1000_RCTL, rctl); 6748 } 6749 6750 ctrl = rd32(E1000_CTRL); 6751 /* advertise wake from D3Cold */ 6752 #define E1000_CTRL_ADVD3WUC 0x00100000 6753 /* phy power management enable */ 6754 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 6755 ctrl |= E1000_CTRL_ADVD3WUC; 6756 wr32(E1000_CTRL, ctrl); 6757 6758 /* Allow time for pending master requests to run */ 6759 igb_disable_pcie_master(hw); 6760 6761 wr32(E1000_WUC, E1000_WUC_PME_EN); 6762 wr32(E1000_WUFC, wufc); 6763 } else { 6764 wr32(E1000_WUC, 0); 6765 wr32(E1000_WUFC, 0); 6766 } 6767 6768 *enable_wake = wufc || adapter->en_mng_pt; 6769 if (!*enable_wake) 6770 igb_power_down_link(adapter); 6771 else 6772 igb_power_up_link(adapter); 6773 6774 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6775 * would have already happened in close and is redundant. */ 6776 igb_release_hw_control(adapter); 6777 6778 pci_disable_device(pdev); 6779 6780 return 0; 6781 } 6782 6783 #ifdef CONFIG_PM 6784 #ifdef CONFIG_PM_SLEEP 6785 static int igb_suspend(struct device *dev) 6786 { 6787 int retval; 6788 bool wake; 6789 struct pci_dev *pdev = to_pci_dev(dev); 6790 6791 retval = __igb_shutdown(pdev, &wake, 0); 6792 if (retval) 6793 return retval; 6794 6795 if (wake) { 6796 pci_prepare_to_sleep(pdev); 6797 } else { 6798 pci_wake_from_d3(pdev, false); 6799 pci_set_power_state(pdev, PCI_D3hot); 6800 } 6801 6802 return 0; 6803 } 6804 #endif /* CONFIG_PM_SLEEP */ 6805 6806 static int igb_resume(struct device *dev) 6807 { 6808 struct pci_dev *pdev = to_pci_dev(dev); 6809 struct net_device *netdev = pci_get_drvdata(pdev); 6810 struct igb_adapter *adapter = netdev_priv(netdev); 6811 struct e1000_hw *hw = &adapter->hw; 6812 u32 err; 6813 6814 pci_set_power_state(pdev, PCI_D0); 6815 pci_restore_state(pdev); 6816 pci_save_state(pdev); 6817 6818 err = pci_enable_device_mem(pdev); 6819 if (err) { 6820 dev_err(&pdev->dev, 6821 "igb: Cannot enable PCI device from suspend\n"); 6822 return err; 6823 } 6824 pci_set_master(pdev); 6825 6826 pci_enable_wake(pdev, PCI_D3hot, 0); 6827 pci_enable_wake(pdev, PCI_D3cold, 0); 6828 6829 if (igb_init_interrupt_scheme(adapter, true)) { 6830 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 6831 return -ENOMEM; 6832 } 6833 6834 igb_reset(adapter); 6835 6836 /* let the f/w know that the h/w is now under the control of the 6837 * driver. */ 6838 igb_get_hw_control(adapter); 6839 6840 wr32(E1000_WUS, ~0); 6841 6842 if (netdev->flags & IFF_UP) { 6843 rtnl_lock(); 6844 err = __igb_open(netdev, true); 6845 rtnl_unlock(); 6846 if (err) 6847 return err; 6848 } 6849 6850 netif_device_attach(netdev); 6851 return 0; 6852 } 6853 6854 #ifdef CONFIG_PM_RUNTIME 6855 static int igb_runtime_idle(struct device *dev) 6856 { 6857 struct pci_dev *pdev = to_pci_dev(dev); 6858 struct net_device *netdev = pci_get_drvdata(pdev); 6859 struct igb_adapter *adapter = netdev_priv(netdev); 6860 6861 if (!igb_has_link(adapter)) 6862 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6863 6864 return -EBUSY; 6865 } 6866 6867 static int igb_runtime_suspend(struct device *dev) 6868 { 6869 struct pci_dev *pdev = to_pci_dev(dev); 6870 int retval; 6871 bool wake; 6872 6873 retval = __igb_shutdown(pdev, &wake, 1); 6874 if (retval) 6875 return retval; 6876 6877 if (wake) { 6878 pci_prepare_to_sleep(pdev); 6879 } else { 6880 pci_wake_from_d3(pdev, false); 6881 pci_set_power_state(pdev, PCI_D3hot); 6882 } 6883 6884 return 0; 6885 } 6886 6887 static int igb_runtime_resume(struct device *dev) 6888 { 6889 return igb_resume(dev); 6890 } 6891 #endif /* CONFIG_PM_RUNTIME */ 6892 #endif 6893 6894 static void igb_shutdown(struct pci_dev *pdev) 6895 { 6896 bool wake; 6897 6898 __igb_shutdown(pdev, &wake, 0); 6899 6900 if (system_state == SYSTEM_POWER_OFF) { 6901 pci_wake_from_d3(pdev, wake); 6902 pci_set_power_state(pdev, PCI_D3hot); 6903 } 6904 } 6905 6906 #ifdef CONFIG_NET_POLL_CONTROLLER 6907 /* 6908 * Polling 'interrupt' - used by things like netconsole to send skbs 6909 * without having to re-enable interrupts. It's not called while 6910 * the interrupt routine is executing. 6911 */ 6912 static void igb_netpoll(struct net_device *netdev) 6913 { 6914 struct igb_adapter *adapter = netdev_priv(netdev); 6915 struct e1000_hw *hw = &adapter->hw; 6916 struct igb_q_vector *q_vector; 6917 int i; 6918 6919 for (i = 0; i < adapter->num_q_vectors; i++) { 6920 q_vector = adapter->q_vector[i]; 6921 if (adapter->msix_entries) 6922 wr32(E1000_EIMC, q_vector->eims_value); 6923 else 6924 igb_irq_disable(adapter); 6925 napi_schedule(&q_vector->napi); 6926 } 6927 } 6928 #endif /* CONFIG_NET_POLL_CONTROLLER */ 6929 6930 /** 6931 * igb_io_error_detected - called when PCI error is detected 6932 * @pdev: Pointer to PCI device 6933 * @state: The current pci connection state 6934 * 6935 * This function is called after a PCI bus error affecting 6936 * this device has been detected. 6937 */ 6938 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 6939 pci_channel_state_t state) 6940 { 6941 struct net_device *netdev = pci_get_drvdata(pdev); 6942 struct igb_adapter *adapter = netdev_priv(netdev); 6943 6944 netif_device_detach(netdev); 6945 6946 if (state == pci_channel_io_perm_failure) 6947 return PCI_ERS_RESULT_DISCONNECT; 6948 6949 if (netif_running(netdev)) 6950 igb_down(adapter); 6951 pci_disable_device(pdev); 6952 6953 /* Request a slot slot reset. */ 6954 return PCI_ERS_RESULT_NEED_RESET; 6955 } 6956 6957 /** 6958 * igb_io_slot_reset - called after the pci bus has been reset. 6959 * @pdev: Pointer to PCI device 6960 * 6961 * Restart the card from scratch, as if from a cold-boot. Implementation 6962 * resembles the first-half of the igb_resume routine. 6963 */ 6964 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 6965 { 6966 struct net_device *netdev = pci_get_drvdata(pdev); 6967 struct igb_adapter *adapter = netdev_priv(netdev); 6968 struct e1000_hw *hw = &adapter->hw; 6969 pci_ers_result_t result; 6970 int err; 6971 6972 if (pci_enable_device_mem(pdev)) { 6973 dev_err(&pdev->dev, 6974 "Cannot re-enable PCI device after reset.\n"); 6975 result = PCI_ERS_RESULT_DISCONNECT; 6976 } else { 6977 pci_set_master(pdev); 6978 pci_restore_state(pdev); 6979 pci_save_state(pdev); 6980 6981 pci_enable_wake(pdev, PCI_D3hot, 0); 6982 pci_enable_wake(pdev, PCI_D3cold, 0); 6983 6984 igb_reset(adapter); 6985 wr32(E1000_WUS, ~0); 6986 result = PCI_ERS_RESULT_RECOVERED; 6987 } 6988 6989 err = pci_cleanup_aer_uncorrect_error_status(pdev); 6990 if (err) { 6991 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " 6992 "failed 0x%0x\n", err); 6993 /* non-fatal, continue */ 6994 } 6995 6996 return result; 6997 } 6998 6999 /** 7000 * igb_io_resume - called when traffic can start flowing again. 7001 * @pdev: Pointer to PCI device 7002 * 7003 * This callback is called when the error recovery driver tells us that 7004 * its OK to resume normal operation. Implementation resembles the 7005 * second-half of the igb_resume routine. 7006 */ 7007 static void igb_io_resume(struct pci_dev *pdev) 7008 { 7009 struct net_device *netdev = pci_get_drvdata(pdev); 7010 struct igb_adapter *adapter = netdev_priv(netdev); 7011 7012 if (netif_running(netdev)) { 7013 if (igb_up(adapter)) { 7014 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7015 return; 7016 } 7017 } 7018 7019 netif_device_attach(netdev); 7020 7021 /* let the f/w know that the h/w is now under the control of the 7022 * driver. */ 7023 igb_get_hw_control(adapter); 7024 } 7025 7026 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7027 u8 qsel) 7028 { 7029 u32 rar_low, rar_high; 7030 struct e1000_hw *hw = &adapter->hw; 7031 7032 /* HW expects these in little endian so we reverse the byte order 7033 * from network order (big endian) to little endian 7034 */ 7035 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7036 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7037 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7038 7039 /* Indicate to hardware the Address is Valid. */ 7040 rar_high |= E1000_RAH_AV; 7041 7042 if (hw->mac.type == e1000_82575) 7043 rar_high |= E1000_RAH_POOL_1 * qsel; 7044 else 7045 rar_high |= E1000_RAH_POOL_1 << qsel; 7046 7047 wr32(E1000_RAL(index), rar_low); 7048 wrfl(); 7049 wr32(E1000_RAH(index), rar_high); 7050 wrfl(); 7051 } 7052 7053 static int igb_set_vf_mac(struct igb_adapter *adapter, 7054 int vf, unsigned char *mac_addr) 7055 { 7056 struct e1000_hw *hw = &adapter->hw; 7057 /* VF MAC addresses start at end of receive addresses and moves 7058 * torwards the first, as a result a collision should not be possible */ 7059 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7060 7061 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7062 7063 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7064 7065 return 0; 7066 } 7067 7068 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7069 { 7070 struct igb_adapter *adapter = netdev_priv(netdev); 7071 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7072 return -EINVAL; 7073 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7074 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7075 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" 7076 " change effective."); 7077 if (test_bit(__IGB_DOWN, &adapter->state)) { 7078 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," 7079 " but the PF device is not up.\n"); 7080 dev_warn(&adapter->pdev->dev, "Bring the PF device up before" 7081 " attempting to use the VF device.\n"); 7082 } 7083 return igb_set_vf_mac(adapter, vf, mac); 7084 } 7085 7086 static int igb_link_mbps(int internal_link_speed) 7087 { 7088 switch (internal_link_speed) { 7089 case SPEED_100: 7090 return 100; 7091 case SPEED_1000: 7092 return 1000; 7093 default: 7094 return 0; 7095 } 7096 } 7097 7098 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7099 int link_speed) 7100 { 7101 int rf_dec, rf_int; 7102 u32 bcnrc_val; 7103 7104 if (tx_rate != 0) { 7105 /* Calculate the rate factor values to set */ 7106 rf_int = link_speed / tx_rate; 7107 rf_dec = (link_speed - (rf_int * tx_rate)); 7108 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; 7109 7110 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7111 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & 7112 E1000_RTTBCNRC_RF_INT_MASK); 7113 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7114 } else { 7115 bcnrc_val = 0; 7116 } 7117 7118 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7119 /* 7120 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7121 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7122 */ 7123 wr32(E1000_RTTBCNRM, 0x14); 7124 wr32(E1000_RTTBCNRC, bcnrc_val); 7125 } 7126 7127 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7128 { 7129 int actual_link_speed, i; 7130 bool reset_rate = false; 7131 7132 /* VF TX rate limit was not set or not supported */ 7133 if ((adapter->vf_rate_link_speed == 0) || 7134 (adapter->hw.mac.type != e1000_82576)) 7135 return; 7136 7137 actual_link_speed = igb_link_mbps(adapter->link_speed); 7138 if (actual_link_speed != adapter->vf_rate_link_speed) { 7139 reset_rate = true; 7140 adapter->vf_rate_link_speed = 0; 7141 dev_info(&adapter->pdev->dev, 7142 "Link speed has been changed. VF Transmit " 7143 "rate is disabled\n"); 7144 } 7145 7146 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7147 if (reset_rate) 7148 adapter->vf_data[i].tx_rate = 0; 7149 7150 igb_set_vf_rate_limit(&adapter->hw, i, 7151 adapter->vf_data[i].tx_rate, 7152 actual_link_speed); 7153 } 7154 } 7155 7156 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7157 { 7158 struct igb_adapter *adapter = netdev_priv(netdev); 7159 struct e1000_hw *hw = &adapter->hw; 7160 int actual_link_speed; 7161 7162 if (hw->mac.type != e1000_82576) 7163 return -EOPNOTSUPP; 7164 7165 actual_link_speed = igb_link_mbps(adapter->link_speed); 7166 if ((vf >= adapter->vfs_allocated_count) || 7167 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7168 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7169 return -EINVAL; 7170 7171 adapter->vf_rate_link_speed = actual_link_speed; 7172 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7173 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7174 7175 return 0; 7176 } 7177 7178 static int igb_ndo_get_vf_config(struct net_device *netdev, 7179 int vf, struct ifla_vf_info *ivi) 7180 { 7181 struct igb_adapter *adapter = netdev_priv(netdev); 7182 if (vf >= adapter->vfs_allocated_count) 7183 return -EINVAL; 7184 ivi->vf = vf; 7185 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7186 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7187 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7188 ivi->qos = adapter->vf_data[vf].pf_qos; 7189 return 0; 7190 } 7191 7192 static void igb_vmm_control(struct igb_adapter *adapter) 7193 { 7194 struct e1000_hw *hw = &adapter->hw; 7195 u32 reg; 7196 7197 switch (hw->mac.type) { 7198 case e1000_82575: 7199 case e1000_i210: 7200 case e1000_i211: 7201 default: 7202 /* replication is not supported for 82575 */ 7203 return; 7204 case e1000_82576: 7205 /* notify HW that the MAC is adding vlan tags */ 7206 reg = rd32(E1000_DTXCTL); 7207 reg |= E1000_DTXCTL_VLAN_ADDED; 7208 wr32(E1000_DTXCTL, reg); 7209 case e1000_82580: 7210 /* enable replication vlan tag stripping */ 7211 reg = rd32(E1000_RPLOLR); 7212 reg |= E1000_RPLOLR_STRVLAN; 7213 wr32(E1000_RPLOLR, reg); 7214 case e1000_i350: 7215 /* none of the above registers are supported by i350 */ 7216 break; 7217 } 7218 7219 if (adapter->vfs_allocated_count) { 7220 igb_vmdq_set_loopback_pf(hw, true); 7221 igb_vmdq_set_replication_pf(hw, true); 7222 igb_vmdq_set_anti_spoofing_pf(hw, true, 7223 adapter->vfs_allocated_count); 7224 } else { 7225 igb_vmdq_set_loopback_pf(hw, false); 7226 igb_vmdq_set_replication_pf(hw, false); 7227 } 7228 } 7229 7230 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7231 { 7232 struct e1000_hw *hw = &adapter->hw; 7233 u32 dmac_thr; 7234 u16 hwm; 7235 7236 if (hw->mac.type > e1000_82580) { 7237 if (adapter->flags & IGB_FLAG_DMAC) { 7238 u32 reg; 7239 7240 /* force threshold to 0. */ 7241 wr32(E1000_DMCTXTH, 0); 7242 7243 /* 7244 * DMA Coalescing high water mark needs to be greater 7245 * than the Rx threshold. Set hwm to PBA - max frame 7246 * size in 16B units, capping it at PBA - 6KB. 7247 */ 7248 hwm = 64 * pba - adapter->max_frame_size / 16; 7249 if (hwm < 64 * (pba - 6)) 7250 hwm = 64 * (pba - 6); 7251 reg = rd32(E1000_FCRTC); 7252 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7253 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7254 & E1000_FCRTC_RTH_COAL_MASK); 7255 wr32(E1000_FCRTC, reg); 7256 7257 /* 7258 * Set the DMA Coalescing Rx threshold to PBA - 2 * max 7259 * frame size, capping it at PBA - 10KB. 7260 */ 7261 dmac_thr = pba - adapter->max_frame_size / 512; 7262 if (dmac_thr < pba - 10) 7263 dmac_thr = pba - 10; 7264 reg = rd32(E1000_DMACR); 7265 reg &= ~E1000_DMACR_DMACTHR_MASK; 7266 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7267 & E1000_DMACR_DMACTHR_MASK); 7268 7269 /* transition to L0x or L1 if available..*/ 7270 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7271 7272 /* watchdog timer= +-1000 usec in 32usec intervals */ 7273 reg |= (1000 >> 5); 7274 7275 /* Disable BMC-to-OS Watchdog Enable */ 7276 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7277 wr32(E1000_DMACR, reg); 7278 7279 /* 7280 * no lower threshold to disable 7281 * coalescing(smart fifb)-UTRESH=0 7282 */ 7283 wr32(E1000_DMCRTRH, 0); 7284 7285 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7286 7287 wr32(E1000_DMCTLX, reg); 7288 7289 /* 7290 * free space in tx packet buffer to wake from 7291 * DMA coal 7292 */ 7293 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 7294 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 7295 7296 /* 7297 * make low power state decision controlled 7298 * by DMA coal 7299 */ 7300 reg = rd32(E1000_PCIEMISC); 7301 reg &= ~E1000_PCIEMISC_LX_DECISION; 7302 wr32(E1000_PCIEMISC, reg); 7303 } /* endif adapter->dmac is not disabled */ 7304 } else if (hw->mac.type == e1000_82580) { 7305 u32 reg = rd32(E1000_PCIEMISC); 7306 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 7307 wr32(E1000_DMACR, 0); 7308 } 7309 } 7310 7311 /* igb_main.c */ 7312