1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { u64 a; u64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) 581 i2cctl |= E1000_I2C_DATA_OUT; 582 else 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 585 i2cctl &= ~E1000_I2C_DATA_OE_N; 586 i2cctl |= E1000_I2C_CLK_OE_N; 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 590 } 591 592 /** 593 * igb_set_i2c_clk - Sets the I2C SCL clock 594 * @data: pointer to hardware structure 595 * @state: state to set clock 596 * 597 * Sets the I2C clock line to state 598 **/ 599 static void igb_set_i2c_clk(void *data, int state) 600 { 601 struct igb_adapter *adapter = (struct igb_adapter *)data; 602 struct e1000_hw *hw = &adapter->hw; 603 s32 i2cctl = rd32(E1000_I2CPARAMS); 604 605 if (state) { 606 i2cctl |= E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } else { 609 i2cctl &= ~E1000_I2C_CLK_OUT; 610 i2cctl &= ~E1000_I2C_CLK_OE_N; 611 } 612 wr32(E1000_I2CPARAMS, i2cctl); 613 wrfl(); 614 } 615 616 /** 617 * igb_get_i2c_clk - Gets the I2C SCL clock state 618 * @data: pointer to hardware structure 619 * 620 * Gets the I2C clock state 621 **/ 622 static int igb_get_i2c_clk(void *data) 623 { 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 return !!(i2cctl & E1000_I2C_CLK_IN); 629 } 630 631 static const struct i2c_algo_bit_data igb_i2c_algo = { 632 .setsda = igb_set_i2c_data, 633 .setscl = igb_set_i2c_clk, 634 .getsda = igb_get_i2c_data, 635 .getscl = igb_get_i2c_clk, 636 .udelay = 5, 637 .timeout = 20, 638 }; 639 640 /** 641 * igb_get_hw_dev - return device 642 * @hw: pointer to hardware structure 643 * 644 * used by hardware layer to print debugging information 645 **/ 646 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 647 { 648 struct igb_adapter *adapter = hw->back; 649 return adapter->netdev; 650 } 651 652 /** 653 * igb_init_module - Driver Registration Routine 654 * 655 * igb_init_module is the first routine called when the driver is 656 * loaded. All it does is register with the PCI subsystem. 657 **/ 658 static int __init igb_init_module(void) 659 { 660 int ret; 661 662 pr_info("%s\n", igb_driver_string); 663 pr_info("%s\n", igb_copyright); 664 665 #ifdef CONFIG_IGB_DCA 666 dca_register_notify(&dca_notifier); 667 #endif 668 ret = pci_register_driver(&igb_driver); 669 return ret; 670 } 671 672 module_init(igb_init_module); 673 674 /** 675 * igb_exit_module - Driver Exit Cleanup Routine 676 * 677 * igb_exit_module is called just before the driver is removed 678 * from memory. 679 **/ 680 static void __exit igb_exit_module(void) 681 { 682 #ifdef CONFIG_IGB_DCA 683 dca_unregister_notify(&dca_notifier); 684 #endif 685 pci_unregister_driver(&igb_driver); 686 } 687 688 module_exit(igb_exit_module); 689 690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 691 /** 692 * igb_cache_ring_register - Descriptor ring to register mapping 693 * @adapter: board private structure to initialize 694 * 695 * Once we know the feature-set enabled for the device, we'll cache 696 * the register offset the descriptor ring is assigned to. 697 **/ 698 static void igb_cache_ring_register(struct igb_adapter *adapter) 699 { 700 int i = 0, j = 0; 701 u32 rbase_offset = adapter->vfs_allocated_count; 702 703 switch (adapter->hw.mac.type) { 704 case e1000_82576: 705 /* The queues are allocated for virtualization such that VF 0 706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 707 * In order to avoid collision we start at the first free queue 708 * and continue consuming queues in the same sequence 709 */ 710 if (adapter->vfs_allocated_count) { 711 for (; i < adapter->rss_queues; i++) 712 adapter->rx_ring[i]->reg_idx = rbase_offset + 713 Q_IDX_82576(i); 714 } 715 fallthrough; 716 case e1000_82575: 717 case e1000_82580: 718 case e1000_i350: 719 case e1000_i354: 720 case e1000_i210: 721 case e1000_i211: 722 default: 723 for (; i < adapter->num_rx_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 725 for (; j < adapter->num_tx_queues; j++) 726 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 727 break; 728 } 729 } 730 731 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 732 { 733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 735 u32 value = 0; 736 737 if (E1000_REMOVED(hw_addr)) 738 return ~value; 739 740 value = readl(&hw_addr[reg]); 741 742 /* reads should not return all F's */ 743 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 744 struct net_device *netdev = igb->netdev; 745 hw->hw_addr = NULL; 746 netdev_err(netdev, "PCIe link lost\n"); 747 WARN(pci_device_is_present(igb->pdev), 748 "igb: Failed to read reg 0x%x!\n", reg); 749 } 750 751 return value; 752 } 753 754 /** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768 { 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778 } 779 780 #define IGB_N0_QUEUE -1 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782 { 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = BIT(msix_vector); 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = BIT(msix_vector); 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857 } 858 859 /** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866 static void igb_configure_msix(struct igb_adapter *adapter) 867 { 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = BIT(vector); 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923 } 924 925 /** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932 static int igb_request_msix(struct igb_adapter *adapter) 933 { 934 struct net_device *netdev = adapter->netdev; 935 int i, err = 0, vector = 0, free_vector = 0; 936 937 err = request_irq(adapter->msix_entries[vector].vector, 938 igb_msix_other, 0, netdev->name, adapter); 939 if (err) 940 goto err_out; 941 942 for (i = 0; i < adapter->num_q_vectors; i++) { 943 struct igb_q_vector *q_vector = adapter->q_vector[i]; 944 945 vector++; 946 947 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 948 949 if (q_vector->rx.ring && q_vector->tx.ring) 950 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 951 q_vector->rx.ring->queue_index); 952 else if (q_vector->tx.ring) 953 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 954 q_vector->tx.ring->queue_index); 955 else if (q_vector->rx.ring) 956 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 957 q_vector->rx.ring->queue_index); 958 else 959 sprintf(q_vector->name, "%s-unused", netdev->name); 960 961 err = request_irq(adapter->msix_entries[vector].vector, 962 igb_msix_ring, 0, q_vector->name, 963 q_vector); 964 if (err) 965 goto err_free; 966 } 967 968 igb_configure_msix(adapter); 969 return 0; 970 971 err_free: 972 /* free already assigned IRQs */ 973 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 974 975 vector--; 976 for (i = 0; i < vector; i++) { 977 free_irq(adapter->msix_entries[free_vector++].vector, 978 adapter->q_vector[i]); 979 } 980 err_out: 981 return err; 982 } 983 984 /** 985 * igb_free_q_vector - Free memory allocated for specific interrupt vector 986 * @adapter: board private structure to initialize 987 * @v_idx: Index of vector to be freed 988 * 989 * This function frees the memory allocated to the q_vector. 990 **/ 991 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 992 { 993 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 994 995 adapter->q_vector[v_idx] = NULL; 996 997 /* igb_get_stats64() might access the rings on this vector, 998 * we must wait a grace period before freeing it. 999 */ 1000 if (q_vector) 1001 kfree_rcu(q_vector, rcu); 1002 } 1003 1004 /** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013 { 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1017 * allocated. So, q_vector is NULL so we should stop here. 1018 */ 1019 if (!q_vector) 1020 return; 1021 1022 if (q_vector->tx.ring) 1023 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1024 1025 if (q_vector->rx.ring) 1026 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1027 1028 netif_napi_del(&q_vector->napi); 1029 1030 } 1031 1032 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1033 { 1034 int v_idx = adapter->num_q_vectors; 1035 1036 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1037 pci_disable_msix(adapter->pdev); 1038 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1039 pci_disable_msi(adapter->pdev); 1040 1041 while (v_idx--) 1042 igb_reset_q_vector(adapter, v_idx); 1043 } 1044 1045 /** 1046 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function frees the memory allocated to the q_vectors. In addition if 1050 * NAPI is enabled it will delete any references to the NAPI struct prior 1051 * to freeing the q_vector. 1052 **/ 1053 static void igb_free_q_vectors(struct igb_adapter *adapter) 1054 { 1055 int v_idx = adapter->num_q_vectors; 1056 1057 adapter->num_tx_queues = 0; 1058 adapter->num_rx_queues = 0; 1059 adapter->num_q_vectors = 0; 1060 1061 while (v_idx--) { 1062 igb_reset_q_vector(adapter, v_idx); 1063 igb_free_q_vector(adapter, v_idx); 1064 } 1065 } 1066 1067 /** 1068 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1072 * MSI-X interrupts allocated. 1073 */ 1074 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1075 { 1076 igb_free_q_vectors(adapter); 1077 igb_reset_interrupt_capability(adapter); 1078 } 1079 1080 /** 1081 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1082 * @adapter: board private structure to initialize 1083 * @msix: boolean value of MSIX capability 1084 * 1085 * Attempt to configure interrupts using the best available 1086 * capabilities of the hardware and kernel. 1087 **/ 1088 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1089 { 1090 int err; 1091 int numvecs, i; 1092 1093 if (!msix) 1094 goto msi_only; 1095 adapter->flags |= IGB_FLAG_HAS_MSIX; 1096 1097 /* Number of supported queues. */ 1098 adapter->num_rx_queues = adapter->rss_queues; 1099 if (adapter->vfs_allocated_count) 1100 adapter->num_tx_queues = 1; 1101 else 1102 adapter->num_tx_queues = adapter->rss_queues; 1103 1104 /* start with one vector for every Rx queue */ 1105 numvecs = adapter->num_rx_queues; 1106 1107 /* if Tx handler is separate add 1 for every Tx queue */ 1108 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1109 numvecs += adapter->num_tx_queues; 1110 1111 /* store the number of vectors reserved for queues */ 1112 adapter->num_q_vectors = numvecs; 1113 1114 /* add 1 vector for link status interrupts */ 1115 numvecs++; 1116 for (i = 0; i < numvecs; i++) 1117 adapter->msix_entries[i].entry = i; 1118 1119 err = pci_enable_msix_range(adapter->pdev, 1120 adapter->msix_entries, 1121 numvecs, 1122 numvecs); 1123 if (err > 0) 1124 return; 1125 1126 igb_reset_interrupt_capability(adapter); 1127 1128 /* If we can't do MSI-X, try MSI */ 1129 msi_only: 1130 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1131 #ifdef CONFIG_PCI_IOV 1132 /* disable SR-IOV for non MSI-X configurations */ 1133 if (adapter->vf_data) { 1134 struct e1000_hw *hw = &adapter->hw; 1135 /* disable iov and allow time for transactions to clear */ 1136 pci_disable_sriov(adapter->pdev); 1137 msleep(500); 1138 1139 kfree(adapter->vf_mac_list); 1140 adapter->vf_mac_list = NULL; 1141 kfree(adapter->vf_data); 1142 adapter->vf_data = NULL; 1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1144 wrfl(); 1145 msleep(100); 1146 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1147 } 1148 #endif 1149 adapter->vfs_allocated_count = 0; 1150 adapter->rss_queues = 1; 1151 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1152 adapter->num_rx_queues = 1; 1153 adapter->num_tx_queues = 1; 1154 adapter->num_q_vectors = 1; 1155 if (!pci_enable_msi(adapter->pdev)) 1156 adapter->flags |= IGB_FLAG_HAS_MSI; 1157 } 1158 1159 static void igb_add_ring(struct igb_ring *ring, 1160 struct igb_ring_container *head) 1161 { 1162 head->ring = ring; 1163 head->count++; 1164 } 1165 1166 /** 1167 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1168 * @adapter: board private structure to initialize 1169 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1170 * @v_idx: index of vector in adapter struct 1171 * @txr_count: total number of Tx rings to allocate 1172 * @txr_idx: index of first Tx ring to allocate 1173 * @rxr_count: total number of Rx rings to allocate 1174 * @rxr_idx: index of first Rx ring to allocate 1175 * 1176 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1177 **/ 1178 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1179 int v_count, int v_idx, 1180 int txr_count, int txr_idx, 1181 int rxr_count, int rxr_idx) 1182 { 1183 struct igb_q_vector *q_vector; 1184 struct igb_ring *ring; 1185 int ring_count; 1186 size_t size; 1187 1188 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1189 if (txr_count > 1 || rxr_count > 1) 1190 return -ENOMEM; 1191 1192 ring_count = txr_count + rxr_count; 1193 size = struct_size(q_vector, ring, ring_count); 1194 1195 /* allocate q_vector and rings */ 1196 q_vector = adapter->q_vector[v_idx]; 1197 if (!q_vector) { 1198 q_vector = kzalloc(size, GFP_KERNEL); 1199 } else if (size > ksize(q_vector)) { 1200 kfree_rcu(q_vector, rcu); 1201 q_vector = kzalloc(size, GFP_KERNEL); 1202 } else { 1203 memset(q_vector, 0, size); 1204 } 1205 if (!q_vector) 1206 return -ENOMEM; 1207 1208 /* initialize NAPI */ 1209 netif_napi_add(adapter->netdev, &q_vector->napi, 1210 igb_poll, 64); 1211 1212 /* tie q_vector and adapter together */ 1213 adapter->q_vector[v_idx] = q_vector; 1214 q_vector->adapter = adapter; 1215 1216 /* initialize work limits */ 1217 q_vector->tx.work_limit = adapter->tx_work_limit; 1218 1219 /* initialize ITR configuration */ 1220 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1221 q_vector->itr_val = IGB_START_ITR; 1222 1223 /* initialize pointer to rings */ 1224 ring = q_vector->ring; 1225 1226 /* intialize ITR */ 1227 if (rxr_count) { 1228 /* rx or rx/tx vector */ 1229 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1230 q_vector->itr_val = adapter->rx_itr_setting; 1231 } else { 1232 /* tx only vector */ 1233 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1234 q_vector->itr_val = adapter->tx_itr_setting; 1235 } 1236 1237 if (txr_count) { 1238 /* assign generic ring traits */ 1239 ring->dev = &adapter->pdev->dev; 1240 ring->netdev = adapter->netdev; 1241 1242 /* configure backlink on ring */ 1243 ring->q_vector = q_vector; 1244 1245 /* update q_vector Tx values */ 1246 igb_add_ring(ring, &q_vector->tx); 1247 1248 /* For 82575, context index must be unique per ring. */ 1249 if (adapter->hw.mac.type == e1000_82575) 1250 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1251 1252 /* apply Tx specific ring traits */ 1253 ring->count = adapter->tx_ring_count; 1254 ring->queue_index = txr_idx; 1255 1256 ring->cbs_enable = false; 1257 ring->idleslope = 0; 1258 ring->sendslope = 0; 1259 ring->hicredit = 0; 1260 ring->locredit = 0; 1261 1262 u64_stats_init(&ring->tx_syncp); 1263 u64_stats_init(&ring->tx_syncp2); 1264 1265 /* assign ring to adapter */ 1266 adapter->tx_ring[txr_idx] = ring; 1267 1268 /* push pointer to next ring */ 1269 ring++; 1270 } 1271 1272 if (rxr_count) { 1273 /* assign generic ring traits */ 1274 ring->dev = &adapter->pdev->dev; 1275 ring->netdev = adapter->netdev; 1276 1277 /* configure backlink on ring */ 1278 ring->q_vector = q_vector; 1279 1280 /* update q_vector Rx values */ 1281 igb_add_ring(ring, &q_vector->rx); 1282 1283 /* set flag indicating ring supports SCTP checksum offload */ 1284 if (adapter->hw.mac.type >= e1000_82576) 1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1286 1287 /* On i350, i354, i210, and i211, loopback VLAN packets 1288 * have the tag byte-swapped. 1289 */ 1290 if (adapter->hw.mac.type >= e1000_i350) 1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1292 1293 /* apply Rx specific ring traits */ 1294 ring->count = adapter->rx_ring_count; 1295 ring->queue_index = rxr_idx; 1296 1297 u64_stats_init(&ring->rx_syncp); 1298 1299 /* assign ring to adapter */ 1300 adapter->rx_ring[rxr_idx] = ring; 1301 } 1302 1303 return 0; 1304 } 1305 1306 1307 /** 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1309 * @adapter: board private structure to initialize 1310 * 1311 * We allocate one q_vector per queue interrupt. If allocation fails we 1312 * return -ENOMEM. 1313 **/ 1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1315 { 1316 int q_vectors = adapter->num_q_vectors; 1317 int rxr_remaining = adapter->num_rx_queues; 1318 int txr_remaining = adapter->num_tx_queues; 1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1320 int err; 1321 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1323 for (; rxr_remaining; v_idx++) { 1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1325 0, 0, 1, rxr_idx); 1326 1327 if (err) 1328 goto err_out; 1329 1330 /* update counts and index */ 1331 rxr_remaining--; 1332 rxr_idx++; 1333 } 1334 } 1335 1336 for (; v_idx < q_vectors; v_idx++) { 1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1339 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1341 tqpv, txr_idx, rqpv, rxr_idx); 1342 1343 if (err) 1344 goto err_out; 1345 1346 /* update counts and index */ 1347 rxr_remaining -= rqpv; 1348 txr_remaining -= tqpv; 1349 rxr_idx++; 1350 txr_idx++; 1351 } 1352 1353 return 0; 1354 1355 err_out: 1356 adapter->num_tx_queues = 0; 1357 adapter->num_rx_queues = 0; 1358 adapter->num_q_vectors = 0; 1359 1360 while (v_idx--) 1361 igb_free_q_vector(adapter, v_idx); 1362 1363 return -ENOMEM; 1364 } 1365 1366 /** 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1368 * @adapter: board private structure to initialize 1369 * @msix: boolean value of MSIX capability 1370 * 1371 * This function initializes the interrupts and allocates all of the queues. 1372 **/ 1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1374 { 1375 struct pci_dev *pdev = adapter->pdev; 1376 int err; 1377 1378 igb_set_interrupt_capability(adapter, msix); 1379 1380 err = igb_alloc_q_vectors(adapter); 1381 if (err) { 1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1383 goto err_alloc_q_vectors; 1384 } 1385 1386 igb_cache_ring_register(adapter); 1387 1388 return 0; 1389 1390 err_alloc_q_vectors: 1391 igb_reset_interrupt_capability(adapter); 1392 return err; 1393 } 1394 1395 /** 1396 * igb_request_irq - initialize interrupts 1397 * @adapter: board private structure to initialize 1398 * 1399 * Attempts to configure interrupts using the best available 1400 * capabilities of the hardware and kernel. 1401 **/ 1402 static int igb_request_irq(struct igb_adapter *adapter) 1403 { 1404 struct net_device *netdev = adapter->netdev; 1405 struct pci_dev *pdev = adapter->pdev; 1406 int err = 0; 1407 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1409 err = igb_request_msix(adapter); 1410 if (!err) 1411 goto request_done; 1412 /* fall back to MSI */ 1413 igb_free_all_tx_resources(adapter); 1414 igb_free_all_rx_resources(adapter); 1415 1416 igb_clear_interrupt_scheme(adapter); 1417 err = igb_init_interrupt_scheme(adapter, false); 1418 if (err) 1419 goto request_done; 1420 1421 igb_setup_all_tx_resources(adapter); 1422 igb_setup_all_rx_resources(adapter); 1423 igb_configure(adapter); 1424 } 1425 1426 igb_assign_vector(adapter->q_vector[0], 0); 1427 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1429 err = request_irq(pdev->irq, igb_intr_msi, 0, 1430 netdev->name, adapter); 1431 if (!err) 1432 goto request_done; 1433 1434 /* fall back to legacy interrupts */ 1435 igb_reset_interrupt_capability(adapter); 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1437 } 1438 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1440 netdev->name, adapter); 1441 1442 if (err) 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1444 err); 1445 1446 request_done: 1447 return err; 1448 } 1449 1450 static void igb_free_irq(struct igb_adapter *adapter) 1451 { 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1453 int vector = 0, i; 1454 1455 free_irq(adapter->msix_entries[vector++].vector, adapter); 1456 1457 for (i = 0; i < adapter->num_q_vectors; i++) 1458 free_irq(adapter->msix_entries[vector++].vector, 1459 adapter->q_vector[i]); 1460 } else { 1461 free_irq(adapter->pdev->irq, adapter); 1462 } 1463 } 1464 1465 /** 1466 * igb_irq_disable - Mask off interrupt generation on the NIC 1467 * @adapter: board private structure 1468 **/ 1469 static void igb_irq_disable(struct igb_adapter *adapter) 1470 { 1471 struct e1000_hw *hw = &adapter->hw; 1472 1473 /* we need to be careful when disabling interrupts. The VFs are also 1474 * mapped into these registers and so clearing the bits can cause 1475 * issues on the VF drivers so we only need to clear what we set 1476 */ 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1478 u32 regval = rd32(E1000_EIAM); 1479 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 1492 for (i = 0; i < adapter->num_q_vectors; i++) 1493 synchronize_irq(adapter->msix_entries[i].vector); 1494 } else { 1495 synchronize_irq(adapter->pdev->irq); 1496 } 1497 } 1498 1499 /** 1500 * igb_irq_enable - Enable default interrupt generation settings 1501 * @adapter: board private structure 1502 **/ 1503 static void igb_irq_enable(struct igb_adapter *adapter) 1504 { 1505 struct e1000_hw *hw = &adapter->hw; 1506 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1509 u32 regval = rd32(E1000_EIAC); 1510 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1512 regval = rd32(E1000_EIAM); 1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1514 wr32(E1000_EIMS, adapter->eims_enable_mask); 1515 if (adapter->vfs_allocated_count) { 1516 wr32(E1000_MBVFIMR, 0xFF); 1517 ims |= E1000_IMS_VMMB; 1518 } 1519 wr32(E1000_IMS, ims); 1520 } else { 1521 wr32(E1000_IMS, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 wr32(E1000_IAM, IMS_ENABLE_MASK | 1524 E1000_IMS_DRSTA); 1525 } 1526 } 1527 1528 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1529 { 1530 struct e1000_hw *hw = &adapter->hw; 1531 u16 pf_id = adapter->vfs_allocated_count; 1532 u16 vid = adapter->hw.mng_cookie.vlan_id; 1533 u16 old_vid = adapter->mng_vlan_id; 1534 1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1536 /* add VID to filter table */ 1537 igb_vfta_set(hw, vid, pf_id, true, true); 1538 adapter->mng_vlan_id = vid; 1539 } else { 1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1541 } 1542 1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1544 (vid != old_vid) && 1545 !test_bit(old_vid, adapter->active_vlans)) { 1546 /* remove VID from filter table */ 1547 igb_vfta_set(hw, vid, pf_id, false, true); 1548 } 1549 } 1550 1551 /** 1552 * igb_release_hw_control - release control of the h/w to f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that the 1557 * driver is no longer loaded. 1558 **/ 1559 static void igb_release_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware take over control of h/w */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 /** 1571 * igb_get_hw_control - get control of the h/w from f/w 1572 * @adapter: address of board private structure 1573 * 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1575 * For ASF and Pass Through versions of f/w this means that 1576 * the driver is loaded. 1577 **/ 1578 static void igb_get_hw_control(struct igb_adapter *adapter) 1579 { 1580 struct e1000_hw *hw = &adapter->hw; 1581 u32 ctrl_ext; 1582 1583 /* Let firmware know the driver has taken over */ 1584 ctrl_ext = rd32(E1000_CTRL_EXT); 1585 wr32(E1000_CTRL_EXT, 1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1587 } 1588 1589 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1590 { 1591 struct net_device *netdev = adapter->netdev; 1592 struct e1000_hw *hw = &adapter->hw; 1593 1594 WARN_ON(hw->mac.type != e1000_i210); 1595 1596 if (enable) 1597 adapter->flags |= IGB_FLAG_FQTSS; 1598 else 1599 adapter->flags &= ~IGB_FLAG_FQTSS; 1600 1601 if (netif_running(netdev)) 1602 schedule_work(&adapter->reset_task); 1603 } 1604 1605 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1606 { 1607 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1608 } 1609 1610 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1611 enum tx_queue_prio prio) 1612 { 1613 u32 val; 1614 1615 WARN_ON(hw->mac.type != e1000_i210); 1616 WARN_ON(queue < 0 || queue > 4); 1617 1618 val = rd32(E1000_I210_TXDCTL(queue)); 1619 1620 if (prio == TX_QUEUE_PRIO_HIGH) 1621 val |= E1000_TXDCTL_PRIORITY; 1622 else 1623 val &= ~E1000_TXDCTL_PRIORITY; 1624 1625 wr32(E1000_I210_TXDCTL(queue), val); 1626 } 1627 1628 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1629 { 1630 u32 val; 1631 1632 WARN_ON(hw->mac.type != e1000_i210); 1633 WARN_ON(queue < 0 || queue > 1); 1634 1635 val = rd32(E1000_I210_TQAVCC(queue)); 1636 1637 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1638 val |= E1000_TQAVCC_QUEUEMODE; 1639 else 1640 val &= ~E1000_TQAVCC_QUEUEMODE; 1641 1642 wr32(E1000_I210_TQAVCC(queue), val); 1643 } 1644 1645 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1646 { 1647 int i; 1648 1649 for (i = 0; i < adapter->num_tx_queues; i++) { 1650 if (adapter->tx_ring[i]->cbs_enable) 1651 return true; 1652 } 1653 1654 return false; 1655 } 1656 1657 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1658 { 1659 int i; 1660 1661 for (i = 0; i < adapter->num_tx_queues; i++) { 1662 if (adapter->tx_ring[i]->launchtime_enable) 1663 return true; 1664 } 1665 1666 return false; 1667 } 1668 1669 /** 1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1671 * @adapter: pointer to adapter struct 1672 * @queue: queue number 1673 * 1674 * Configure CBS and Launchtime for a given hardware queue. 1675 * Parameters are retrieved from the correct Tx ring, so 1676 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1677 * for setting those correctly prior to this function being called. 1678 **/ 1679 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1680 { 1681 struct igb_ring *ring = adapter->tx_ring[queue]; 1682 struct net_device *netdev = adapter->netdev; 1683 struct e1000_hw *hw = &adapter->hw; 1684 u32 tqavcc, tqavctrl; 1685 u16 value; 1686 1687 WARN_ON(hw->mac.type != e1000_i210); 1688 WARN_ON(queue < 0 || queue > 1); 1689 1690 /* If any of the Qav features is enabled, configure queues as SR and 1691 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1692 * as SP. 1693 */ 1694 if (ring->cbs_enable || ring->launchtime_enable) { 1695 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1696 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1697 } else { 1698 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1699 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1700 } 1701 1702 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1703 if (ring->cbs_enable || queue == 0) { 1704 /* i210 does not allow the queue 0 to be in the Strict 1705 * Priority mode while the Qav mode is enabled, so, 1706 * instead of disabling strict priority mode, we give 1707 * queue 0 the maximum of credits possible. 1708 * 1709 * See section 8.12.19 of the i210 datasheet, "Note: 1710 * Queue0 QueueMode must be set to 1b when 1711 * TransmitMode is set to Qav." 1712 */ 1713 if (queue == 0 && !ring->cbs_enable) { 1714 /* max "linkspeed" idleslope in kbps */ 1715 ring->idleslope = 1000000; 1716 ring->hicredit = ETH_FRAME_LEN; 1717 } 1718 1719 /* Always set data transfer arbitration to credit-based 1720 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1721 * the queues. 1722 */ 1723 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1724 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1725 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1726 1727 /* According to i210 datasheet section 7.2.7.7, we should set 1728 * the 'idleSlope' field from TQAVCC register following the 1729 * equation: 1730 * 1731 * For 100 Mbps link speed: 1732 * 1733 * value = BW * 0x7735 * 0.2 (E1) 1734 * 1735 * For 1000Mbps link speed: 1736 * 1737 * value = BW * 0x7735 * 2 (E2) 1738 * 1739 * E1 and E2 can be merged into one equation as shown below. 1740 * Note that 'link-speed' is in Mbps. 1741 * 1742 * value = BW * 0x7735 * 2 * link-speed 1743 * -------------- (E3) 1744 * 1000 1745 * 1746 * 'BW' is the percentage bandwidth out of full link speed 1747 * which can be found with the following equation. Note that 1748 * idleSlope here is the parameter from this function which 1749 * is in kbps. 1750 * 1751 * BW = idleSlope 1752 * ----------------- (E4) 1753 * link-speed * 1000 1754 * 1755 * That said, we can come up with a generic equation to 1756 * calculate the value we should set it TQAVCC register by 1757 * replacing 'BW' in E3 by E4. The resulting equation is: 1758 * 1759 * value = idleSlope * 0x7735 * 2 * link-speed 1760 * ----------------- -------------- (E5) 1761 * link-speed * 1000 1000 1762 * 1763 * 'link-speed' is present in both sides of the fraction so 1764 * it is canceled out. The final equation is the following: 1765 * 1766 * value = idleSlope * 61034 1767 * ----------------- (E6) 1768 * 1000000 1769 * 1770 * NOTE: For i210, given the above, we can see that idleslope 1771 * is represented in 16.38431 kbps units by the value at 1772 * the TQAVCC register (1Gbps / 61034), which reduces 1773 * the granularity for idleslope increments. 1774 * For instance, if you want to configure a 2576kbps 1775 * idleslope, the value to be written on the register 1776 * would have to be 157.23. If rounded down, you end 1777 * up with less bandwidth available than originally 1778 * required (~2572 kbps). If rounded up, you end up 1779 * with a higher bandwidth (~2589 kbps). Below the 1780 * approach we take is to always round up the 1781 * calculated value, so the resulting bandwidth might 1782 * be slightly higher for some configurations. 1783 */ 1784 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1785 1786 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1787 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1788 tqavcc |= value; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 wr32(E1000_I210_TQAVHC(queue), 1792 0x80000000 + ring->hicredit * 0x7735); 1793 } else { 1794 1795 /* Set idleSlope to zero. */ 1796 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1797 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 /* Set hiCredit to zero. */ 1801 wr32(E1000_I210_TQAVHC(queue), 0); 1802 1803 /* If CBS is not enabled for any queues anymore, then return to 1804 * the default state of Data Transmission Arbitration on 1805 * TQAVCTRL. 1806 */ 1807 if (!is_any_cbs_enabled(adapter)) { 1808 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1809 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1810 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1811 } 1812 } 1813 1814 /* If LaunchTime is enabled, set DataTranTIM. */ 1815 if (ring->launchtime_enable) { 1816 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1817 * for any of the SR queues, and configure fetchtime delta. 1818 * XXX NOTE: 1819 * - LaunchTime will be enabled for all SR queues. 1820 * - A fixed offset can be added relative to the launch 1821 * time of all packets if configured at reg LAUNCH_OS0. 1822 * We are keeping it as 0 for now (default value). 1823 */ 1824 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1825 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1826 E1000_TQAVCTRL_FETCHTIME_DELTA; 1827 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1828 } else { 1829 /* If Launchtime is not enabled for any SR queues anymore, 1830 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1831 * effectively disabling Launchtime. 1832 */ 1833 if (!is_any_txtime_enabled(adapter)) { 1834 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1835 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1836 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1837 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1838 } 1839 } 1840 1841 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1842 * CBS are not configurable by software so we don't do any 'controller 1843 * configuration' in respect to these parameters. 1844 */ 1845 1846 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1847 ring->cbs_enable ? "enabled" : "disabled", 1848 ring->launchtime_enable ? "enabled" : "disabled", 1849 queue, 1850 ring->idleslope, ring->sendslope, 1851 ring->hicredit, ring->locredit); 1852 } 1853 1854 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1855 bool enable) 1856 { 1857 struct igb_ring *ring; 1858 1859 if (queue < 0 || queue > adapter->num_tx_queues) 1860 return -EINVAL; 1861 1862 ring = adapter->tx_ring[queue]; 1863 ring->launchtime_enable = enable; 1864 1865 return 0; 1866 } 1867 1868 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1869 bool enable, int idleslope, int sendslope, 1870 int hicredit, int locredit) 1871 { 1872 struct igb_ring *ring; 1873 1874 if (queue < 0 || queue > adapter->num_tx_queues) 1875 return -EINVAL; 1876 1877 ring = adapter->tx_ring[queue]; 1878 1879 ring->cbs_enable = enable; 1880 ring->idleslope = idleslope; 1881 ring->sendslope = sendslope; 1882 ring->hicredit = hicredit; 1883 ring->locredit = locredit; 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1890 * @adapter: pointer to adapter struct 1891 * 1892 * Configure TQAVCTRL register switching the controller's Tx mode 1893 * if FQTSS mode is enabled or disabled. Additionally, will issue 1894 * a call to igb_config_tx_modes() per queue so any previously saved 1895 * Tx parameters are applied. 1896 **/ 1897 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1898 { 1899 struct net_device *netdev = adapter->netdev; 1900 struct e1000_hw *hw = &adapter->hw; 1901 u32 val; 1902 1903 /* Only i210 controller supports changing the transmission mode. */ 1904 if (hw->mac.type != e1000_i210) 1905 return; 1906 1907 if (is_fqtss_enabled(adapter)) { 1908 int i, max_queue; 1909 1910 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1911 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1912 * so SP queues wait for SR ones. 1913 */ 1914 val = rd32(E1000_I210_TQAVCTRL); 1915 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1916 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1917 wr32(E1000_I210_TQAVCTRL, val); 1918 1919 /* Configure Tx and Rx packet buffers sizes as described in 1920 * i210 datasheet section 7.2.7.7. 1921 */ 1922 val = rd32(E1000_TXPBS); 1923 val &= ~I210_TXPBSIZE_MASK; 1924 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1925 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1926 wr32(E1000_TXPBS, val); 1927 1928 val = rd32(E1000_RXPBS); 1929 val &= ~I210_RXPBSIZE_MASK; 1930 val |= I210_RXPBSIZE_PB_30KB; 1931 wr32(E1000_RXPBS, val); 1932 1933 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1934 * register should not exceed the buffer size programmed in 1935 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1936 * so according to the datasheet we should set MAX_TPKT_SIZE to 1937 * 4kB / 64. 1938 * 1939 * However, when we do so, no frame from queue 2 and 3 are 1940 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1941 * or _equal_ to the buffer size programmed in TXPBS. For this 1942 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1943 */ 1944 val = (4096 - 1) / 64; 1945 wr32(E1000_I210_DTXMXPKTSZ, val); 1946 1947 /* Since FQTSS mode is enabled, apply any CBS configuration 1948 * previously set. If no previous CBS configuration has been 1949 * done, then the initial configuration is applied, which means 1950 * CBS is disabled. 1951 */ 1952 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1953 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1954 1955 for (i = 0; i < max_queue; i++) { 1956 igb_config_tx_modes(adapter, i); 1957 } 1958 } else { 1959 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1960 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1961 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1962 1963 val = rd32(E1000_I210_TQAVCTRL); 1964 /* According to Section 8.12.21, the other flags we've set when 1965 * enabling FQTSS are not relevant when disabling FQTSS so we 1966 * don't set they here. 1967 */ 1968 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1969 wr32(E1000_I210_TQAVCTRL, val); 1970 } 1971 1972 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1973 "enabled" : "disabled"); 1974 } 1975 1976 /** 1977 * igb_configure - configure the hardware for RX and TX 1978 * @adapter: private board structure 1979 **/ 1980 static void igb_configure(struct igb_adapter *adapter) 1981 { 1982 struct net_device *netdev = adapter->netdev; 1983 int i; 1984 1985 igb_get_hw_control(adapter); 1986 igb_set_rx_mode(netdev); 1987 igb_setup_tx_mode(adapter); 1988 1989 igb_restore_vlan(adapter); 1990 1991 igb_setup_tctl(adapter); 1992 igb_setup_mrqc(adapter); 1993 igb_setup_rctl(adapter); 1994 1995 igb_nfc_filter_restore(adapter); 1996 igb_configure_tx(adapter); 1997 igb_configure_rx(adapter); 1998 1999 igb_rx_fifo_flush_82575(&adapter->hw); 2000 2001 /* call igb_desc_unused which always leaves 2002 * at least 1 descriptor unused to make sure 2003 * next_to_use != next_to_clean 2004 */ 2005 for (i = 0; i < adapter->num_rx_queues; i++) { 2006 struct igb_ring *ring = adapter->rx_ring[i]; 2007 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2008 } 2009 } 2010 2011 /** 2012 * igb_power_up_link - Power up the phy/serdes link 2013 * @adapter: address of board private structure 2014 **/ 2015 void igb_power_up_link(struct igb_adapter *adapter) 2016 { 2017 igb_reset_phy(&adapter->hw); 2018 2019 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2020 igb_power_up_phy_copper(&adapter->hw); 2021 else 2022 igb_power_up_serdes_link_82575(&adapter->hw); 2023 2024 igb_setup_link(&adapter->hw); 2025 } 2026 2027 /** 2028 * igb_power_down_link - Power down the phy/serdes link 2029 * @adapter: address of board private structure 2030 */ 2031 static void igb_power_down_link(struct igb_adapter *adapter) 2032 { 2033 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2034 igb_power_down_phy_copper_82575(&adapter->hw); 2035 else 2036 igb_shutdown_serdes_link_82575(&adapter->hw); 2037 } 2038 2039 /** 2040 * Detect and switch function for Media Auto Sense 2041 * @adapter: address of the board private structure 2042 **/ 2043 static void igb_check_swap_media(struct igb_adapter *adapter) 2044 { 2045 struct e1000_hw *hw = &adapter->hw; 2046 u32 ctrl_ext, connsw; 2047 bool swap_now = false; 2048 2049 ctrl_ext = rd32(E1000_CTRL_EXT); 2050 connsw = rd32(E1000_CONNSW); 2051 2052 /* need to live swap if current media is copper and we have fiber/serdes 2053 * to go to. 2054 */ 2055 2056 if ((hw->phy.media_type == e1000_media_type_copper) && 2057 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2058 swap_now = true; 2059 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2060 !(connsw & E1000_CONNSW_SERDESD)) { 2061 /* copper signal takes time to appear */ 2062 if (adapter->copper_tries < 4) { 2063 adapter->copper_tries++; 2064 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2065 wr32(E1000_CONNSW, connsw); 2066 return; 2067 } else { 2068 adapter->copper_tries = 0; 2069 if ((connsw & E1000_CONNSW_PHYSD) && 2070 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2071 swap_now = true; 2072 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 } 2075 } 2076 } 2077 2078 if (!swap_now) 2079 return; 2080 2081 switch (hw->phy.media_type) { 2082 case e1000_media_type_copper: 2083 netdev_info(adapter->netdev, 2084 "MAS: changing media to fiber/serdes\n"); 2085 ctrl_ext |= 2086 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2087 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2088 adapter->copper_tries = 0; 2089 break; 2090 case e1000_media_type_internal_serdes: 2091 case e1000_media_type_fiber: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to copper\n"); 2094 ctrl_ext &= 2095 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 break; 2098 default: 2099 /* shouldn't get here during regular operation */ 2100 netdev_err(adapter->netdev, 2101 "AMS: Invalid media type found, returning\n"); 2102 break; 2103 } 2104 wr32(E1000_CTRL_EXT, ctrl_ext); 2105 } 2106 2107 /** 2108 * igb_up - Open the interface and prepare it to handle traffic 2109 * @adapter: board private structure 2110 **/ 2111 int igb_up(struct igb_adapter *adapter) 2112 { 2113 struct e1000_hw *hw = &adapter->hw; 2114 int i; 2115 2116 /* hardware has been reset, we need to reload some things */ 2117 igb_configure(adapter); 2118 2119 clear_bit(__IGB_DOWN, &adapter->state); 2120 2121 for (i = 0; i < adapter->num_q_vectors; i++) 2122 napi_enable(&(adapter->q_vector[i]->napi)); 2123 2124 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2125 igb_configure_msix(adapter); 2126 else 2127 igb_assign_vector(adapter->q_vector[0], 0); 2128 2129 /* Clear any pending interrupts. */ 2130 rd32(E1000_TSICR); 2131 rd32(E1000_ICR); 2132 igb_irq_enable(adapter); 2133 2134 /* notify VFs that reset has been completed */ 2135 if (adapter->vfs_allocated_count) { 2136 u32 reg_data = rd32(E1000_CTRL_EXT); 2137 2138 reg_data |= E1000_CTRL_EXT_PFRSTD; 2139 wr32(E1000_CTRL_EXT, reg_data); 2140 } 2141 2142 netif_tx_start_all_queues(adapter->netdev); 2143 2144 /* start the watchdog. */ 2145 hw->mac.get_link_status = 1; 2146 schedule_work(&adapter->watchdog_task); 2147 2148 if ((adapter->flags & IGB_FLAG_EEE) && 2149 (!hw->dev_spec._82575.eee_disable)) 2150 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2151 2152 return 0; 2153 } 2154 2155 void igb_down(struct igb_adapter *adapter) 2156 { 2157 struct net_device *netdev = adapter->netdev; 2158 struct e1000_hw *hw = &adapter->hw; 2159 u32 tctl, rctl; 2160 int i; 2161 2162 /* signal that we're down so the interrupt handler does not 2163 * reschedule our watchdog timer 2164 */ 2165 set_bit(__IGB_DOWN, &adapter->state); 2166 2167 /* disable receives in the hardware */ 2168 rctl = rd32(E1000_RCTL); 2169 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2170 /* flush and sleep below */ 2171 2172 igb_nfc_filter_exit(adapter); 2173 2174 netif_carrier_off(netdev); 2175 netif_tx_stop_all_queues(netdev); 2176 2177 /* disable transmits in the hardware */ 2178 tctl = rd32(E1000_TCTL); 2179 tctl &= ~E1000_TCTL_EN; 2180 wr32(E1000_TCTL, tctl); 2181 /* flush both disables and wait for them to finish */ 2182 wrfl(); 2183 usleep_range(10000, 11000); 2184 2185 igb_irq_disable(adapter); 2186 2187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2188 2189 for (i = 0; i < adapter->num_q_vectors; i++) { 2190 if (adapter->q_vector[i]) { 2191 napi_synchronize(&adapter->q_vector[i]->napi); 2192 napi_disable(&adapter->q_vector[i]->napi); 2193 } 2194 } 2195 2196 del_timer_sync(&adapter->watchdog_timer); 2197 del_timer_sync(&adapter->phy_info_timer); 2198 2199 /* record the stats before reset*/ 2200 spin_lock(&adapter->stats64_lock); 2201 igb_update_stats(adapter); 2202 spin_unlock(&adapter->stats64_lock); 2203 2204 adapter->link_speed = 0; 2205 adapter->link_duplex = 0; 2206 2207 if (!pci_channel_offline(adapter->pdev)) 2208 igb_reset(adapter); 2209 2210 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2211 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2212 2213 igb_clean_all_tx_rings(adapter); 2214 igb_clean_all_rx_rings(adapter); 2215 #ifdef CONFIG_IGB_DCA 2216 2217 /* since we reset the hardware DCA settings were cleared */ 2218 igb_setup_dca(adapter); 2219 #endif 2220 } 2221 2222 void igb_reinit_locked(struct igb_adapter *adapter) 2223 { 2224 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2225 usleep_range(1000, 2000); 2226 igb_down(adapter); 2227 igb_up(adapter); 2228 clear_bit(__IGB_RESETTING, &adapter->state); 2229 } 2230 2231 /** igb_enable_mas - Media Autosense re-enable after swap 2232 * 2233 * @adapter: adapter struct 2234 **/ 2235 static void igb_enable_mas(struct igb_adapter *adapter) 2236 { 2237 struct e1000_hw *hw = &adapter->hw; 2238 u32 connsw = rd32(E1000_CONNSW); 2239 2240 /* configure for SerDes media detect */ 2241 if ((hw->phy.media_type == e1000_media_type_copper) && 2242 (!(connsw & E1000_CONNSW_SERDESD))) { 2243 connsw |= E1000_CONNSW_ENRGSRC; 2244 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2245 wr32(E1000_CONNSW, connsw); 2246 wrfl(); 2247 } 2248 } 2249 2250 void igb_reset(struct igb_adapter *adapter) 2251 { 2252 struct pci_dev *pdev = adapter->pdev; 2253 struct e1000_hw *hw = &adapter->hw; 2254 struct e1000_mac_info *mac = &hw->mac; 2255 struct e1000_fc_info *fc = &hw->fc; 2256 u32 pba, hwm; 2257 2258 /* Repartition Pba for greater than 9k mtu 2259 * To take effect CTRL.RST is required. 2260 */ 2261 switch (mac->type) { 2262 case e1000_i350: 2263 case e1000_i354: 2264 case e1000_82580: 2265 pba = rd32(E1000_RXPBS); 2266 pba = igb_rxpbs_adjust_82580(pba); 2267 break; 2268 case e1000_82576: 2269 pba = rd32(E1000_RXPBS); 2270 pba &= E1000_RXPBS_SIZE_MASK_82576; 2271 break; 2272 case e1000_82575: 2273 case e1000_i210: 2274 case e1000_i211: 2275 default: 2276 pba = E1000_PBA_34K; 2277 break; 2278 } 2279 2280 if (mac->type == e1000_82575) { 2281 u32 min_rx_space, min_tx_space, needed_tx_space; 2282 2283 /* write Rx PBA so that hardware can report correct Tx PBA */ 2284 wr32(E1000_PBA, pba); 2285 2286 /* To maintain wire speed transmits, the Tx FIFO should be 2287 * large enough to accommodate two full transmit packets, 2288 * rounded up to the next 1KB and expressed in KB. Likewise, 2289 * the Rx FIFO should be large enough to accommodate at least 2290 * one full receive packet and is similarly rounded up and 2291 * expressed in KB. 2292 */ 2293 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2294 2295 /* The Tx FIFO also stores 16 bytes of information about the Tx 2296 * but don't include Ethernet FCS because hardware appends it. 2297 * We only need to round down to the nearest 512 byte block 2298 * count since the value we care about is 2 frames, not 1. 2299 */ 2300 min_tx_space = adapter->max_frame_size; 2301 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2302 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2303 2304 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2305 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2306 2307 /* If current Tx allocation is less than the min Tx FIFO size, 2308 * and the min Tx FIFO size is less than the current Rx FIFO 2309 * allocation, take space away from current Rx allocation. 2310 */ 2311 if (needed_tx_space < pba) { 2312 pba -= needed_tx_space; 2313 2314 /* if short on Rx space, Rx wins and must trump Tx 2315 * adjustment 2316 */ 2317 if (pba < min_rx_space) 2318 pba = min_rx_space; 2319 } 2320 2321 /* adjust PBA for jumbo frames */ 2322 wr32(E1000_PBA, pba); 2323 } 2324 2325 /* flow control settings 2326 * The high water mark must be low enough to fit one full frame 2327 * after transmitting the pause frame. As such we must have enough 2328 * space to allow for us to complete our current transmit and then 2329 * receive the frame that is in progress from the link partner. 2330 * Set it to: 2331 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2332 */ 2333 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2334 2335 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2336 fc->low_water = fc->high_water - 16; 2337 fc->pause_time = 0xFFFF; 2338 fc->send_xon = 1; 2339 fc->current_mode = fc->requested_mode; 2340 2341 /* disable receive for all VFs and wait one second */ 2342 if (adapter->vfs_allocated_count) { 2343 int i; 2344 2345 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2346 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2347 2348 /* ping all the active vfs to let them know we are going down */ 2349 igb_ping_all_vfs(adapter); 2350 2351 /* disable transmits and receives */ 2352 wr32(E1000_VFRE, 0); 2353 wr32(E1000_VFTE, 0); 2354 } 2355 2356 /* Allow time for pending master requests to run */ 2357 hw->mac.ops.reset_hw(hw); 2358 wr32(E1000_WUC, 0); 2359 2360 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2361 /* need to resetup here after media swap */ 2362 adapter->ei.get_invariants(hw); 2363 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2364 } 2365 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2366 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2367 igb_enable_mas(adapter); 2368 } 2369 if (hw->mac.ops.init_hw(hw)) 2370 dev_err(&pdev->dev, "Hardware Error\n"); 2371 2372 /* RAR registers were cleared during init_hw, clear mac table */ 2373 igb_flush_mac_table(adapter); 2374 __dev_uc_unsync(adapter->netdev, NULL); 2375 2376 /* Recover default RAR entry */ 2377 igb_set_default_mac_filter(adapter); 2378 2379 /* Flow control settings reset on hardware reset, so guarantee flow 2380 * control is off when forcing speed. 2381 */ 2382 if (!hw->mac.autoneg) 2383 igb_force_mac_fc(hw); 2384 2385 igb_init_dmac(adapter, pba); 2386 #ifdef CONFIG_IGB_HWMON 2387 /* Re-initialize the thermal sensor on i350 devices. */ 2388 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2389 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2390 /* If present, re-initialize the external thermal sensor 2391 * interface. 2392 */ 2393 if (adapter->ets) 2394 mac->ops.init_thermal_sensor_thresh(hw); 2395 } 2396 } 2397 #endif 2398 /* Re-establish EEE setting */ 2399 if (hw->phy.media_type == e1000_media_type_copper) { 2400 switch (mac->type) { 2401 case e1000_i350: 2402 case e1000_i210: 2403 case e1000_i211: 2404 igb_set_eee_i350(hw, true, true); 2405 break; 2406 case e1000_i354: 2407 igb_set_eee_i354(hw, true, true); 2408 break; 2409 default: 2410 break; 2411 } 2412 } 2413 if (!netif_running(adapter->netdev)) 2414 igb_power_down_link(adapter); 2415 2416 igb_update_mng_vlan(adapter); 2417 2418 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2419 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2420 2421 /* Re-enable PTP, where applicable. */ 2422 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2423 igb_ptp_reset(adapter); 2424 2425 igb_get_phy_info(hw); 2426 } 2427 2428 static netdev_features_t igb_fix_features(struct net_device *netdev, 2429 netdev_features_t features) 2430 { 2431 /* Since there is no support for separate Rx/Tx vlan accel 2432 * enable/disable make sure Tx flag is always in same state as Rx. 2433 */ 2434 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2435 features |= NETIF_F_HW_VLAN_CTAG_TX; 2436 else 2437 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2438 2439 return features; 2440 } 2441 2442 static int igb_set_features(struct net_device *netdev, 2443 netdev_features_t features) 2444 { 2445 netdev_features_t changed = netdev->features ^ features; 2446 struct igb_adapter *adapter = netdev_priv(netdev); 2447 2448 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2449 igb_vlan_mode(netdev, features); 2450 2451 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2452 return 0; 2453 2454 if (!(features & NETIF_F_NTUPLE)) { 2455 struct hlist_node *node2; 2456 struct igb_nfc_filter *rule; 2457 2458 spin_lock(&adapter->nfc_lock); 2459 hlist_for_each_entry_safe(rule, node2, 2460 &adapter->nfc_filter_list, nfc_node) { 2461 igb_erase_filter(adapter, rule); 2462 hlist_del(&rule->nfc_node); 2463 kfree(rule); 2464 } 2465 spin_unlock(&adapter->nfc_lock); 2466 adapter->nfc_filter_count = 0; 2467 } 2468 2469 netdev->features = features; 2470 2471 if (netif_running(netdev)) 2472 igb_reinit_locked(adapter); 2473 else 2474 igb_reset(adapter); 2475 2476 return 1; 2477 } 2478 2479 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2480 struct net_device *dev, 2481 const unsigned char *addr, u16 vid, 2482 u16 flags, 2483 struct netlink_ext_ack *extack) 2484 { 2485 /* guarantee we can provide a unique filter for the unicast address */ 2486 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2487 struct igb_adapter *adapter = netdev_priv(dev); 2488 int vfn = adapter->vfs_allocated_count; 2489 2490 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2491 return -ENOMEM; 2492 } 2493 2494 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2495 } 2496 2497 #define IGB_MAX_MAC_HDR_LEN 127 2498 #define IGB_MAX_NETWORK_HDR_LEN 511 2499 2500 static netdev_features_t 2501 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2502 netdev_features_t features) 2503 { 2504 unsigned int network_hdr_len, mac_hdr_len; 2505 2506 /* Make certain the headers can be described by a context descriptor */ 2507 mac_hdr_len = skb_network_header(skb) - skb->data; 2508 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2509 return features & ~(NETIF_F_HW_CSUM | 2510 NETIF_F_SCTP_CRC | 2511 NETIF_F_GSO_UDP_L4 | 2512 NETIF_F_HW_VLAN_CTAG_TX | 2513 NETIF_F_TSO | 2514 NETIF_F_TSO6); 2515 2516 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2517 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_TSO | 2522 NETIF_F_TSO6); 2523 2524 /* We can only support IPV4 TSO in tunnels if we can mangle the 2525 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2526 */ 2527 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2528 features &= ~NETIF_F_TSO; 2529 2530 return features; 2531 } 2532 2533 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2534 { 2535 if (!is_fqtss_enabled(adapter)) { 2536 enable_fqtss(adapter, true); 2537 return; 2538 } 2539 2540 igb_config_tx_modes(adapter, queue); 2541 2542 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2543 enable_fqtss(adapter, false); 2544 } 2545 2546 static int igb_offload_cbs(struct igb_adapter *adapter, 2547 struct tc_cbs_qopt_offload *qopt) 2548 { 2549 struct e1000_hw *hw = &adapter->hw; 2550 int err; 2551 2552 /* CBS offloading is only supported by i210 controller. */ 2553 if (hw->mac.type != e1000_i210) 2554 return -EOPNOTSUPP; 2555 2556 /* CBS offloading is only supported by queue 0 and queue 1. */ 2557 if (qopt->queue < 0 || qopt->queue > 1) 2558 return -EINVAL; 2559 2560 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2561 qopt->idleslope, qopt->sendslope, 2562 qopt->hicredit, qopt->locredit); 2563 if (err) 2564 return err; 2565 2566 igb_offload_apply(adapter, qopt->queue); 2567 2568 return 0; 2569 } 2570 2571 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2572 #define VLAN_PRIO_FULL_MASK (0x07) 2573 2574 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2575 struct flow_cls_offload *f, 2576 int traffic_class, 2577 struct igb_nfc_filter *input) 2578 { 2579 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2580 struct flow_dissector *dissector = rule->match.dissector; 2581 struct netlink_ext_ack *extack = f->common.extack; 2582 2583 if (dissector->used_keys & 2584 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2585 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2586 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2587 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2588 NL_SET_ERR_MSG_MOD(extack, 2589 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2590 return -EOPNOTSUPP; 2591 } 2592 2593 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2594 struct flow_match_eth_addrs match; 2595 2596 flow_rule_match_eth_addrs(rule, &match); 2597 if (!is_zero_ether_addr(match.mask->dst)) { 2598 if (!is_broadcast_ether_addr(match.mask->dst)) { 2599 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2600 return -EINVAL; 2601 } 2602 2603 input->filter.match_flags |= 2604 IGB_FILTER_FLAG_DST_MAC_ADDR; 2605 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2606 } 2607 2608 if (!is_zero_ether_addr(match.mask->src)) { 2609 if (!is_broadcast_ether_addr(match.mask->src)) { 2610 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2611 return -EINVAL; 2612 } 2613 2614 input->filter.match_flags |= 2615 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2616 ether_addr_copy(input->filter.src_addr, match.key->src); 2617 } 2618 } 2619 2620 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2621 struct flow_match_basic match; 2622 2623 flow_rule_match_basic(rule, &match); 2624 if (match.mask->n_proto) { 2625 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2626 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2627 return -EINVAL; 2628 } 2629 2630 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2631 input->filter.etype = match.key->n_proto; 2632 } 2633 } 2634 2635 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2636 struct flow_match_vlan match; 2637 2638 flow_rule_match_vlan(rule, &match); 2639 if (match.mask->vlan_priority) { 2640 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2641 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2642 return -EINVAL; 2643 } 2644 2645 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2646 input->filter.vlan_tci = match.key->vlan_priority; 2647 } 2648 } 2649 2650 input->action = traffic_class; 2651 input->cookie = f->cookie; 2652 2653 return 0; 2654 } 2655 2656 static int igb_configure_clsflower(struct igb_adapter *adapter, 2657 struct flow_cls_offload *cls_flower) 2658 { 2659 struct netlink_ext_ack *extack = cls_flower->common.extack; 2660 struct igb_nfc_filter *filter, *f; 2661 int err, tc; 2662 2663 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2664 if (tc < 0) { 2665 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2666 return -EINVAL; 2667 } 2668 2669 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2670 if (!filter) 2671 return -ENOMEM; 2672 2673 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2674 if (err < 0) 2675 goto err_parse; 2676 2677 spin_lock(&adapter->nfc_lock); 2678 2679 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2680 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2681 err = -EEXIST; 2682 NL_SET_ERR_MSG_MOD(extack, 2683 "This filter is already set in ethtool"); 2684 goto err_locked; 2685 } 2686 } 2687 2688 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2690 err = -EEXIST; 2691 NL_SET_ERR_MSG_MOD(extack, 2692 "This filter is already set in cls_flower"); 2693 goto err_locked; 2694 } 2695 } 2696 2697 err = igb_add_filter(adapter, filter); 2698 if (err < 0) { 2699 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2700 goto err_locked; 2701 } 2702 2703 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2704 2705 spin_unlock(&adapter->nfc_lock); 2706 2707 return 0; 2708 2709 err_locked: 2710 spin_unlock(&adapter->nfc_lock); 2711 2712 err_parse: 2713 kfree(filter); 2714 2715 return err; 2716 } 2717 2718 static int igb_delete_clsflower(struct igb_adapter *adapter, 2719 struct flow_cls_offload *cls_flower) 2720 { 2721 struct igb_nfc_filter *filter; 2722 int err; 2723 2724 spin_lock(&adapter->nfc_lock); 2725 2726 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2727 if (filter->cookie == cls_flower->cookie) 2728 break; 2729 2730 if (!filter) { 2731 err = -ENOENT; 2732 goto out; 2733 } 2734 2735 err = igb_erase_filter(adapter, filter); 2736 if (err < 0) 2737 goto out; 2738 2739 hlist_del(&filter->nfc_node); 2740 kfree(filter); 2741 2742 out: 2743 spin_unlock(&adapter->nfc_lock); 2744 2745 return err; 2746 } 2747 2748 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2749 struct flow_cls_offload *cls_flower) 2750 { 2751 switch (cls_flower->command) { 2752 case FLOW_CLS_REPLACE: 2753 return igb_configure_clsflower(adapter, cls_flower); 2754 case FLOW_CLS_DESTROY: 2755 return igb_delete_clsflower(adapter, cls_flower); 2756 case FLOW_CLS_STATS: 2757 return -EOPNOTSUPP; 2758 default: 2759 return -EOPNOTSUPP; 2760 } 2761 } 2762 2763 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2764 void *cb_priv) 2765 { 2766 struct igb_adapter *adapter = cb_priv; 2767 2768 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2769 return -EOPNOTSUPP; 2770 2771 switch (type) { 2772 case TC_SETUP_CLSFLOWER: 2773 return igb_setup_tc_cls_flower(adapter, type_data); 2774 2775 default: 2776 return -EOPNOTSUPP; 2777 } 2778 } 2779 2780 static int igb_offload_txtime(struct igb_adapter *adapter, 2781 struct tc_etf_qopt_offload *qopt) 2782 { 2783 struct e1000_hw *hw = &adapter->hw; 2784 int err; 2785 2786 /* Launchtime offloading is only supported by i210 controller. */ 2787 if (hw->mac.type != e1000_i210) 2788 return -EOPNOTSUPP; 2789 2790 /* Launchtime offloading is only supported by queues 0 and 1. */ 2791 if (qopt->queue < 0 || qopt->queue > 1) 2792 return -EINVAL; 2793 2794 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2795 if (err) 2796 return err; 2797 2798 igb_offload_apply(adapter, qopt->queue); 2799 2800 return 0; 2801 } 2802 2803 static LIST_HEAD(igb_block_cb_list); 2804 2805 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2806 void *type_data) 2807 { 2808 struct igb_adapter *adapter = netdev_priv(dev); 2809 2810 switch (type) { 2811 case TC_SETUP_QDISC_CBS: 2812 return igb_offload_cbs(adapter, type_data); 2813 case TC_SETUP_BLOCK: 2814 return flow_block_cb_setup_simple(type_data, 2815 &igb_block_cb_list, 2816 igb_setup_tc_block_cb, 2817 adapter, adapter, true); 2818 2819 case TC_SETUP_QDISC_ETF: 2820 return igb_offload_txtime(adapter, type_data); 2821 2822 default: 2823 return -EOPNOTSUPP; 2824 } 2825 } 2826 2827 static int igb_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 2828 { 2829 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2830 struct igb_adapter *adapter = netdev_priv(dev); 2831 bool running = netif_running(dev); 2832 struct bpf_prog *old_prog; 2833 bool need_reset; 2834 2835 /* verify igb ring attributes are sufficient for XDP */ 2836 for (i = 0; i < adapter->num_rx_queues; i++) { 2837 struct igb_ring *ring = adapter->rx_ring[i]; 2838 2839 if (frame_size > igb_rx_bufsz(ring)) 2840 return -EINVAL; 2841 } 2842 2843 old_prog = xchg(&adapter->xdp_prog, prog); 2844 need_reset = (!!prog != !!old_prog); 2845 2846 /* device is up and bpf is added/removed, must setup the RX queues */ 2847 if (need_reset && running) { 2848 igb_close(dev); 2849 } else { 2850 for (i = 0; i < adapter->num_rx_queues; i++) 2851 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2852 adapter->xdp_prog); 2853 } 2854 2855 if (old_prog) 2856 bpf_prog_put(old_prog); 2857 2858 /* bpf is just replaced, RXQ and MTU are already setup */ 2859 if (!need_reset) 2860 return 0; 2861 2862 if (running) 2863 igb_open(dev); 2864 2865 return 0; 2866 } 2867 2868 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2869 { 2870 switch (xdp->command) { 2871 case XDP_SETUP_PROG: 2872 return igb_xdp_setup(dev, xdp->prog); 2873 default: 2874 return -EINVAL; 2875 } 2876 } 2877 2878 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2879 { 2880 /* Force memory writes to complete before letting h/w know there 2881 * are new descriptors to fetch. 2882 */ 2883 wmb(); 2884 writel(ring->next_to_use, ring->tail); 2885 } 2886 2887 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2888 { 2889 unsigned int r_idx = smp_processor_id(); 2890 2891 if (r_idx >= adapter->num_tx_queues) 2892 r_idx = r_idx % adapter->num_tx_queues; 2893 2894 return adapter->tx_ring[r_idx]; 2895 } 2896 2897 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2898 { 2899 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2900 int cpu = smp_processor_id(); 2901 struct igb_ring *tx_ring; 2902 struct netdev_queue *nq; 2903 u32 ret; 2904 2905 if (unlikely(!xdpf)) 2906 return IGB_XDP_CONSUMED; 2907 2908 /* During program transitions its possible adapter->xdp_prog is assigned 2909 * but ring has not been configured yet. In this case simply abort xmit. 2910 */ 2911 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2912 if (unlikely(!tx_ring)) 2913 return -ENXIO; 2914 2915 nq = txring_txq(tx_ring); 2916 __netif_tx_lock(nq, cpu); 2917 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2918 __netif_tx_unlock(nq); 2919 2920 return ret; 2921 } 2922 2923 static int igb_xdp_xmit(struct net_device *dev, int n, 2924 struct xdp_frame **frames, u32 flags) 2925 { 2926 struct igb_adapter *adapter = netdev_priv(dev); 2927 int cpu = smp_processor_id(); 2928 struct igb_ring *tx_ring; 2929 struct netdev_queue *nq; 2930 int drops = 0; 2931 int i; 2932 2933 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2934 return -ENETDOWN; 2935 2936 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2937 return -EINVAL; 2938 2939 /* During program transitions its possible adapter->xdp_prog is assigned 2940 * but ring has not been configured yet. In this case simply abort xmit. 2941 */ 2942 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2943 if (unlikely(!tx_ring)) 2944 return -ENXIO; 2945 2946 nq = txring_txq(tx_ring); 2947 __netif_tx_lock(nq, cpu); 2948 2949 for (i = 0; i < n; i++) { 2950 struct xdp_frame *xdpf = frames[i]; 2951 int err; 2952 2953 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2954 if (err != IGB_XDP_TX) { 2955 xdp_return_frame_rx_napi(xdpf); 2956 drops++; 2957 } 2958 } 2959 2960 __netif_tx_unlock(nq); 2961 2962 if (unlikely(flags & XDP_XMIT_FLUSH)) 2963 igb_xdp_ring_update_tail(tx_ring); 2964 2965 return n - drops; 2966 } 2967 2968 static const struct net_device_ops igb_netdev_ops = { 2969 .ndo_open = igb_open, 2970 .ndo_stop = igb_close, 2971 .ndo_start_xmit = igb_xmit_frame, 2972 .ndo_get_stats64 = igb_get_stats64, 2973 .ndo_set_rx_mode = igb_set_rx_mode, 2974 .ndo_set_mac_address = igb_set_mac, 2975 .ndo_change_mtu = igb_change_mtu, 2976 .ndo_do_ioctl = igb_ioctl, 2977 .ndo_tx_timeout = igb_tx_timeout, 2978 .ndo_validate_addr = eth_validate_addr, 2979 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2980 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2981 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2982 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2983 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2984 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2985 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2986 .ndo_get_vf_config = igb_ndo_get_vf_config, 2987 .ndo_fix_features = igb_fix_features, 2988 .ndo_set_features = igb_set_features, 2989 .ndo_fdb_add = igb_ndo_fdb_add, 2990 .ndo_features_check = igb_features_check, 2991 .ndo_setup_tc = igb_setup_tc, 2992 .ndo_bpf = igb_xdp, 2993 .ndo_xdp_xmit = igb_xdp_xmit, 2994 }; 2995 2996 /** 2997 * igb_set_fw_version - Configure version string for ethtool 2998 * @adapter: adapter struct 2999 **/ 3000 void igb_set_fw_version(struct igb_adapter *adapter) 3001 { 3002 struct e1000_hw *hw = &adapter->hw; 3003 struct e1000_fw_version fw; 3004 3005 igb_get_fw_version(hw, &fw); 3006 3007 switch (hw->mac.type) { 3008 case e1000_i210: 3009 case e1000_i211: 3010 if (!(igb_get_flash_presence_i210(hw))) { 3011 snprintf(adapter->fw_version, 3012 sizeof(adapter->fw_version), 3013 "%2d.%2d-%d", 3014 fw.invm_major, fw.invm_minor, 3015 fw.invm_img_type); 3016 break; 3017 } 3018 fallthrough; 3019 default: 3020 /* if option is rom valid, display its version too */ 3021 if (fw.or_valid) { 3022 snprintf(adapter->fw_version, 3023 sizeof(adapter->fw_version), 3024 "%d.%d, 0x%08x, %d.%d.%d", 3025 fw.eep_major, fw.eep_minor, fw.etrack_id, 3026 fw.or_major, fw.or_build, fw.or_patch); 3027 /* no option rom */ 3028 } else if (fw.etrack_id != 0X0000) { 3029 snprintf(adapter->fw_version, 3030 sizeof(adapter->fw_version), 3031 "%d.%d, 0x%08x", 3032 fw.eep_major, fw.eep_minor, fw.etrack_id); 3033 } else { 3034 snprintf(adapter->fw_version, 3035 sizeof(adapter->fw_version), 3036 "%d.%d.%d", 3037 fw.eep_major, fw.eep_minor, fw.eep_build); 3038 } 3039 break; 3040 } 3041 } 3042 3043 /** 3044 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3045 * 3046 * @adapter: adapter struct 3047 **/ 3048 static void igb_init_mas(struct igb_adapter *adapter) 3049 { 3050 struct e1000_hw *hw = &adapter->hw; 3051 u16 eeprom_data; 3052 3053 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3054 switch (hw->bus.func) { 3055 case E1000_FUNC_0: 3056 if (eeprom_data & IGB_MAS_ENABLE_0) { 3057 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3058 netdev_info(adapter->netdev, 3059 "MAS: Enabling Media Autosense for port %d\n", 3060 hw->bus.func); 3061 } 3062 break; 3063 case E1000_FUNC_1: 3064 if (eeprom_data & IGB_MAS_ENABLE_1) { 3065 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3066 netdev_info(adapter->netdev, 3067 "MAS: Enabling Media Autosense for port %d\n", 3068 hw->bus.func); 3069 } 3070 break; 3071 case E1000_FUNC_2: 3072 if (eeprom_data & IGB_MAS_ENABLE_2) { 3073 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3074 netdev_info(adapter->netdev, 3075 "MAS: Enabling Media Autosense for port %d\n", 3076 hw->bus.func); 3077 } 3078 break; 3079 case E1000_FUNC_3: 3080 if (eeprom_data & IGB_MAS_ENABLE_3) { 3081 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3082 netdev_info(adapter->netdev, 3083 "MAS: Enabling Media Autosense for port %d\n", 3084 hw->bus.func); 3085 } 3086 break; 3087 default: 3088 /* Shouldn't get here */ 3089 netdev_err(adapter->netdev, 3090 "MAS: Invalid port configuration, returning\n"); 3091 break; 3092 } 3093 } 3094 3095 /** 3096 * igb_init_i2c - Init I2C interface 3097 * @adapter: pointer to adapter structure 3098 **/ 3099 static s32 igb_init_i2c(struct igb_adapter *adapter) 3100 { 3101 s32 status = 0; 3102 3103 /* I2C interface supported on i350 devices */ 3104 if (adapter->hw.mac.type != e1000_i350) 3105 return 0; 3106 3107 /* Initialize the i2c bus which is controlled by the registers. 3108 * This bus will use the i2c_algo_bit structue that implements 3109 * the protocol through toggling of the 4 bits in the register. 3110 */ 3111 adapter->i2c_adap.owner = THIS_MODULE; 3112 adapter->i2c_algo = igb_i2c_algo; 3113 adapter->i2c_algo.data = adapter; 3114 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3115 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3116 strlcpy(adapter->i2c_adap.name, "igb BB", 3117 sizeof(adapter->i2c_adap.name)); 3118 status = i2c_bit_add_bus(&adapter->i2c_adap); 3119 return status; 3120 } 3121 3122 /** 3123 * igb_probe - Device Initialization Routine 3124 * @pdev: PCI device information struct 3125 * @ent: entry in igb_pci_tbl 3126 * 3127 * Returns 0 on success, negative on failure 3128 * 3129 * igb_probe initializes an adapter identified by a pci_dev structure. 3130 * The OS initialization, configuring of the adapter private structure, 3131 * and a hardware reset occur. 3132 **/ 3133 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3134 { 3135 struct net_device *netdev; 3136 struct igb_adapter *adapter; 3137 struct e1000_hw *hw; 3138 u16 eeprom_data = 0; 3139 s32 ret_val; 3140 static int global_quad_port_a; /* global quad port a indication */ 3141 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3142 int err, pci_using_dac; 3143 u8 part_str[E1000_PBANUM_LENGTH]; 3144 3145 /* Catch broken hardware that put the wrong VF device ID in 3146 * the PCIe SR-IOV capability. 3147 */ 3148 if (pdev->is_virtfn) { 3149 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3150 pci_name(pdev), pdev->vendor, pdev->device); 3151 return -EINVAL; 3152 } 3153 3154 err = pci_enable_device_mem(pdev); 3155 if (err) 3156 return err; 3157 3158 pci_using_dac = 0; 3159 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3160 if (!err) { 3161 pci_using_dac = 1; 3162 } else { 3163 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3164 if (err) { 3165 dev_err(&pdev->dev, 3166 "No usable DMA configuration, aborting\n"); 3167 goto err_dma; 3168 } 3169 } 3170 3171 err = pci_request_mem_regions(pdev, igb_driver_name); 3172 if (err) 3173 goto err_pci_reg; 3174 3175 pci_enable_pcie_error_reporting(pdev); 3176 3177 pci_set_master(pdev); 3178 pci_save_state(pdev); 3179 3180 err = -ENOMEM; 3181 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3182 IGB_MAX_TX_QUEUES); 3183 if (!netdev) 3184 goto err_alloc_etherdev; 3185 3186 SET_NETDEV_DEV(netdev, &pdev->dev); 3187 3188 pci_set_drvdata(pdev, netdev); 3189 adapter = netdev_priv(netdev); 3190 adapter->netdev = netdev; 3191 adapter->pdev = pdev; 3192 hw = &adapter->hw; 3193 hw->back = adapter; 3194 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3195 3196 err = -EIO; 3197 adapter->io_addr = pci_iomap(pdev, 0, 0); 3198 if (!adapter->io_addr) 3199 goto err_ioremap; 3200 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3201 hw->hw_addr = adapter->io_addr; 3202 3203 netdev->netdev_ops = &igb_netdev_ops; 3204 igb_set_ethtool_ops(netdev); 3205 netdev->watchdog_timeo = 5 * HZ; 3206 3207 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3208 3209 netdev->mem_start = pci_resource_start(pdev, 0); 3210 netdev->mem_end = pci_resource_end(pdev, 0); 3211 3212 /* PCI config space info */ 3213 hw->vendor_id = pdev->vendor; 3214 hw->device_id = pdev->device; 3215 hw->revision_id = pdev->revision; 3216 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3217 hw->subsystem_device_id = pdev->subsystem_device; 3218 3219 /* Copy the default MAC, PHY and NVM function pointers */ 3220 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3221 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3222 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3223 /* Initialize skew-specific constants */ 3224 err = ei->get_invariants(hw); 3225 if (err) 3226 goto err_sw_init; 3227 3228 /* setup the private structure */ 3229 err = igb_sw_init(adapter); 3230 if (err) 3231 goto err_sw_init; 3232 3233 igb_get_bus_info_pcie(hw); 3234 3235 hw->phy.autoneg_wait_to_complete = false; 3236 3237 /* Copper options */ 3238 if (hw->phy.media_type == e1000_media_type_copper) { 3239 hw->phy.mdix = AUTO_ALL_MODES; 3240 hw->phy.disable_polarity_correction = false; 3241 hw->phy.ms_type = e1000_ms_hw_default; 3242 } 3243 3244 if (igb_check_reset_block(hw)) 3245 dev_info(&pdev->dev, 3246 "PHY reset is blocked due to SOL/IDER session.\n"); 3247 3248 /* features is initialized to 0 in allocation, it might have bits 3249 * set by igb_sw_init so we should use an or instead of an 3250 * assignment. 3251 */ 3252 netdev->features |= NETIF_F_SG | 3253 NETIF_F_TSO | 3254 NETIF_F_TSO6 | 3255 NETIF_F_RXHASH | 3256 NETIF_F_RXCSUM | 3257 NETIF_F_HW_CSUM; 3258 3259 if (hw->mac.type >= e1000_82576) 3260 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3261 3262 if (hw->mac.type >= e1000_i350) 3263 netdev->features |= NETIF_F_HW_TC; 3264 3265 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3266 NETIF_F_GSO_GRE_CSUM | \ 3267 NETIF_F_GSO_IPXIP4 | \ 3268 NETIF_F_GSO_IPXIP6 | \ 3269 NETIF_F_GSO_UDP_TUNNEL | \ 3270 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3271 3272 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3273 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3274 3275 /* copy netdev features into list of user selectable features */ 3276 netdev->hw_features |= netdev->features | 3277 NETIF_F_HW_VLAN_CTAG_RX | 3278 NETIF_F_HW_VLAN_CTAG_TX | 3279 NETIF_F_RXALL; 3280 3281 if (hw->mac.type >= e1000_i350) 3282 netdev->hw_features |= NETIF_F_NTUPLE; 3283 3284 if (pci_using_dac) 3285 netdev->features |= NETIF_F_HIGHDMA; 3286 3287 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3288 netdev->mpls_features |= NETIF_F_HW_CSUM; 3289 netdev->hw_enc_features |= netdev->vlan_features; 3290 3291 /* set this bit last since it cannot be part of vlan_features */ 3292 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3293 NETIF_F_HW_VLAN_CTAG_RX | 3294 NETIF_F_HW_VLAN_CTAG_TX; 3295 3296 netdev->priv_flags |= IFF_SUPP_NOFCS; 3297 3298 netdev->priv_flags |= IFF_UNICAST_FLT; 3299 3300 /* MTU range: 68 - 9216 */ 3301 netdev->min_mtu = ETH_MIN_MTU; 3302 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3303 3304 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3305 3306 /* before reading the NVM, reset the controller to put the device in a 3307 * known good starting state 3308 */ 3309 hw->mac.ops.reset_hw(hw); 3310 3311 /* make sure the NVM is good , i211/i210 parts can have special NVM 3312 * that doesn't contain a checksum 3313 */ 3314 switch (hw->mac.type) { 3315 case e1000_i210: 3316 case e1000_i211: 3317 if (igb_get_flash_presence_i210(hw)) { 3318 if (hw->nvm.ops.validate(hw) < 0) { 3319 dev_err(&pdev->dev, 3320 "The NVM Checksum Is Not Valid\n"); 3321 err = -EIO; 3322 goto err_eeprom; 3323 } 3324 } 3325 break; 3326 default: 3327 if (hw->nvm.ops.validate(hw) < 0) { 3328 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3329 err = -EIO; 3330 goto err_eeprom; 3331 } 3332 break; 3333 } 3334 3335 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3336 /* copy the MAC address out of the NVM */ 3337 if (hw->mac.ops.read_mac_addr(hw)) 3338 dev_err(&pdev->dev, "NVM Read Error\n"); 3339 } 3340 3341 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3342 3343 if (!is_valid_ether_addr(netdev->dev_addr)) { 3344 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3345 err = -EIO; 3346 goto err_eeprom; 3347 } 3348 3349 igb_set_default_mac_filter(adapter); 3350 3351 /* get firmware version for ethtool -i */ 3352 igb_set_fw_version(adapter); 3353 3354 /* configure RXPBSIZE and TXPBSIZE */ 3355 if (hw->mac.type == e1000_i210) { 3356 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3357 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3358 } 3359 3360 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3361 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3362 3363 INIT_WORK(&adapter->reset_task, igb_reset_task); 3364 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3365 3366 /* Initialize link properties that are user-changeable */ 3367 adapter->fc_autoneg = true; 3368 hw->mac.autoneg = true; 3369 hw->phy.autoneg_advertised = 0x2f; 3370 3371 hw->fc.requested_mode = e1000_fc_default; 3372 hw->fc.current_mode = e1000_fc_default; 3373 3374 igb_validate_mdi_setting(hw); 3375 3376 /* By default, support wake on port A */ 3377 if (hw->bus.func == 0) 3378 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3379 3380 /* Check the NVM for wake support on non-port A ports */ 3381 if (hw->mac.type >= e1000_82580) 3382 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3383 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3384 &eeprom_data); 3385 else if (hw->bus.func == 1) 3386 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3387 3388 if (eeprom_data & IGB_EEPROM_APME) 3389 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3390 3391 /* now that we have the eeprom settings, apply the special cases where 3392 * the eeprom may be wrong or the board simply won't support wake on 3393 * lan on a particular port 3394 */ 3395 switch (pdev->device) { 3396 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3397 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3398 break; 3399 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3400 case E1000_DEV_ID_82576_FIBER: 3401 case E1000_DEV_ID_82576_SERDES: 3402 /* Wake events only supported on port A for dual fiber 3403 * regardless of eeprom setting 3404 */ 3405 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3406 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3407 break; 3408 case E1000_DEV_ID_82576_QUAD_COPPER: 3409 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3410 /* if quad port adapter, disable WoL on all but port A */ 3411 if (global_quad_port_a != 0) 3412 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3413 else 3414 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3415 /* Reset for multiple quad port adapters */ 3416 if (++global_quad_port_a == 4) 3417 global_quad_port_a = 0; 3418 break; 3419 default: 3420 /* If the device can't wake, don't set software support */ 3421 if (!device_can_wakeup(&adapter->pdev->dev)) 3422 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3423 } 3424 3425 /* initialize the wol settings based on the eeprom settings */ 3426 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3427 adapter->wol |= E1000_WUFC_MAG; 3428 3429 /* Some vendors want WoL disabled by default, but still supported */ 3430 if ((hw->mac.type == e1000_i350) && 3431 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3432 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3433 adapter->wol = 0; 3434 } 3435 3436 /* Some vendors want the ability to Use the EEPROM setting as 3437 * enable/disable only, and not for capability 3438 */ 3439 if (((hw->mac.type == e1000_i350) || 3440 (hw->mac.type == e1000_i354)) && 3441 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3443 adapter->wol = 0; 3444 } 3445 if (hw->mac.type == e1000_i350) { 3446 if (((pdev->subsystem_device == 0x5001) || 3447 (pdev->subsystem_device == 0x5002)) && 3448 (hw->bus.func == 0)) { 3449 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3450 adapter->wol = 0; 3451 } 3452 if (pdev->subsystem_device == 0x1F52) 3453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3454 } 3455 3456 device_set_wakeup_enable(&adapter->pdev->dev, 3457 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3458 3459 /* reset the hardware with the new settings */ 3460 igb_reset(adapter); 3461 3462 /* Init the I2C interface */ 3463 err = igb_init_i2c(adapter); 3464 if (err) { 3465 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3466 goto err_eeprom; 3467 } 3468 3469 /* let the f/w know that the h/w is now under the control of the 3470 * driver. 3471 */ 3472 igb_get_hw_control(adapter); 3473 3474 strcpy(netdev->name, "eth%d"); 3475 err = register_netdev(netdev); 3476 if (err) 3477 goto err_register; 3478 3479 /* carrier off reporting is important to ethtool even BEFORE open */ 3480 netif_carrier_off(netdev); 3481 3482 #ifdef CONFIG_IGB_DCA 3483 if (dca_add_requester(&pdev->dev) == 0) { 3484 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3485 dev_info(&pdev->dev, "DCA enabled\n"); 3486 igb_setup_dca(adapter); 3487 } 3488 3489 #endif 3490 #ifdef CONFIG_IGB_HWMON 3491 /* Initialize the thermal sensor on i350 devices. */ 3492 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3493 u16 ets_word; 3494 3495 /* Read the NVM to determine if this i350 device supports an 3496 * external thermal sensor. 3497 */ 3498 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3499 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3500 adapter->ets = true; 3501 else 3502 adapter->ets = false; 3503 if (igb_sysfs_init(adapter)) 3504 dev_err(&pdev->dev, 3505 "failed to allocate sysfs resources\n"); 3506 } else { 3507 adapter->ets = false; 3508 } 3509 #endif 3510 /* Check if Media Autosense is enabled */ 3511 adapter->ei = *ei; 3512 if (hw->dev_spec._82575.mas_capable) 3513 igb_init_mas(adapter); 3514 3515 /* do hw tstamp init after resetting */ 3516 igb_ptp_init(adapter); 3517 3518 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3519 /* print bus type/speed/width info, not applicable to i354 */ 3520 if (hw->mac.type != e1000_i354) { 3521 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3522 netdev->name, 3523 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3524 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3525 "unknown"), 3526 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3527 "Width x4" : 3528 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3529 "Width x2" : 3530 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3531 "Width x1" : "unknown"), netdev->dev_addr); 3532 } 3533 3534 if ((hw->mac.type == e1000_82576 && 3535 rd32(E1000_EECD) & E1000_EECD_PRES) || 3536 (hw->mac.type >= e1000_i210 || 3537 igb_get_flash_presence_i210(hw))) { 3538 ret_val = igb_read_part_string(hw, part_str, 3539 E1000_PBANUM_LENGTH); 3540 } else { 3541 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3542 } 3543 3544 if (ret_val) 3545 strcpy(part_str, "Unknown"); 3546 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3547 dev_info(&pdev->dev, 3548 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3549 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3550 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3551 adapter->num_rx_queues, adapter->num_tx_queues); 3552 if (hw->phy.media_type == e1000_media_type_copper) { 3553 switch (hw->mac.type) { 3554 case e1000_i350: 3555 case e1000_i210: 3556 case e1000_i211: 3557 /* Enable EEE for internal copper PHY devices */ 3558 err = igb_set_eee_i350(hw, true, true); 3559 if ((!err) && 3560 (!hw->dev_spec._82575.eee_disable)) { 3561 adapter->eee_advert = 3562 MDIO_EEE_100TX | MDIO_EEE_1000T; 3563 adapter->flags |= IGB_FLAG_EEE; 3564 } 3565 break; 3566 case e1000_i354: 3567 if ((rd32(E1000_CTRL_EXT) & 3568 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3569 err = igb_set_eee_i354(hw, true, true); 3570 if ((!err) && 3571 (!hw->dev_spec._82575.eee_disable)) { 3572 adapter->eee_advert = 3573 MDIO_EEE_100TX | MDIO_EEE_1000T; 3574 adapter->flags |= IGB_FLAG_EEE; 3575 } 3576 } 3577 break; 3578 default: 3579 break; 3580 } 3581 } 3582 3583 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3584 3585 pm_runtime_put_noidle(&pdev->dev); 3586 return 0; 3587 3588 err_register: 3589 igb_release_hw_control(adapter); 3590 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3591 err_eeprom: 3592 if (!igb_check_reset_block(hw)) 3593 igb_reset_phy(hw); 3594 3595 if (hw->flash_address) 3596 iounmap(hw->flash_address); 3597 err_sw_init: 3598 kfree(adapter->mac_table); 3599 kfree(adapter->shadow_vfta); 3600 igb_clear_interrupt_scheme(adapter); 3601 #ifdef CONFIG_PCI_IOV 3602 igb_disable_sriov(pdev); 3603 #endif 3604 pci_iounmap(pdev, adapter->io_addr); 3605 err_ioremap: 3606 free_netdev(netdev); 3607 err_alloc_etherdev: 3608 pci_release_mem_regions(pdev); 3609 err_pci_reg: 3610 err_dma: 3611 pci_disable_device(pdev); 3612 return err; 3613 } 3614 3615 #ifdef CONFIG_PCI_IOV 3616 static int igb_disable_sriov(struct pci_dev *pdev) 3617 { 3618 struct net_device *netdev = pci_get_drvdata(pdev); 3619 struct igb_adapter *adapter = netdev_priv(netdev); 3620 struct e1000_hw *hw = &adapter->hw; 3621 3622 /* reclaim resources allocated to VFs */ 3623 if (adapter->vf_data) { 3624 /* disable iov and allow time for transactions to clear */ 3625 if (pci_vfs_assigned(pdev)) { 3626 dev_warn(&pdev->dev, 3627 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3628 return -EPERM; 3629 } else { 3630 pci_disable_sriov(pdev); 3631 msleep(500); 3632 } 3633 3634 kfree(adapter->vf_mac_list); 3635 adapter->vf_mac_list = NULL; 3636 kfree(adapter->vf_data); 3637 adapter->vf_data = NULL; 3638 adapter->vfs_allocated_count = 0; 3639 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3640 wrfl(); 3641 msleep(100); 3642 dev_info(&pdev->dev, "IOV Disabled\n"); 3643 3644 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3645 adapter->flags |= IGB_FLAG_DMAC; 3646 } 3647 3648 return 0; 3649 } 3650 3651 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3652 { 3653 struct net_device *netdev = pci_get_drvdata(pdev); 3654 struct igb_adapter *adapter = netdev_priv(netdev); 3655 int old_vfs = pci_num_vf(pdev); 3656 struct vf_mac_filter *mac_list; 3657 int err = 0; 3658 int num_vf_mac_filters, i; 3659 3660 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3661 err = -EPERM; 3662 goto out; 3663 } 3664 if (!num_vfs) 3665 goto out; 3666 3667 if (old_vfs) { 3668 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3669 old_vfs, max_vfs); 3670 adapter->vfs_allocated_count = old_vfs; 3671 } else 3672 adapter->vfs_allocated_count = num_vfs; 3673 3674 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3675 sizeof(struct vf_data_storage), GFP_KERNEL); 3676 3677 /* if allocation failed then we do not support SR-IOV */ 3678 if (!adapter->vf_data) { 3679 adapter->vfs_allocated_count = 0; 3680 err = -ENOMEM; 3681 goto out; 3682 } 3683 3684 /* Due to the limited number of RAR entries calculate potential 3685 * number of MAC filters available for the VFs. Reserve entries 3686 * for PF default MAC, PF MAC filters and at least one RAR entry 3687 * for each VF for VF MAC. 3688 */ 3689 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3690 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3691 adapter->vfs_allocated_count); 3692 3693 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3694 sizeof(struct vf_mac_filter), 3695 GFP_KERNEL); 3696 3697 mac_list = adapter->vf_mac_list; 3698 INIT_LIST_HEAD(&adapter->vf_macs.l); 3699 3700 if (adapter->vf_mac_list) { 3701 /* Initialize list of VF MAC filters */ 3702 for (i = 0; i < num_vf_mac_filters; i++) { 3703 mac_list->vf = -1; 3704 mac_list->free = true; 3705 list_add(&mac_list->l, &adapter->vf_macs.l); 3706 mac_list++; 3707 } 3708 } else { 3709 /* If we could not allocate memory for the VF MAC filters 3710 * we can continue without this feature but warn user. 3711 */ 3712 dev_err(&pdev->dev, 3713 "Unable to allocate memory for VF MAC filter list\n"); 3714 } 3715 3716 /* only call pci_enable_sriov() if no VFs are allocated already */ 3717 if (!old_vfs) { 3718 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3719 if (err) 3720 goto err_out; 3721 } 3722 dev_info(&pdev->dev, "%d VFs allocated\n", 3723 adapter->vfs_allocated_count); 3724 for (i = 0; i < adapter->vfs_allocated_count; i++) 3725 igb_vf_configure(adapter, i); 3726 3727 /* DMA Coalescing is not supported in IOV mode. */ 3728 adapter->flags &= ~IGB_FLAG_DMAC; 3729 goto out; 3730 3731 err_out: 3732 kfree(adapter->vf_mac_list); 3733 adapter->vf_mac_list = NULL; 3734 kfree(adapter->vf_data); 3735 adapter->vf_data = NULL; 3736 adapter->vfs_allocated_count = 0; 3737 out: 3738 return err; 3739 } 3740 3741 #endif 3742 /** 3743 * igb_remove_i2c - Cleanup I2C interface 3744 * @adapter: pointer to adapter structure 3745 **/ 3746 static void igb_remove_i2c(struct igb_adapter *adapter) 3747 { 3748 /* free the adapter bus structure */ 3749 i2c_del_adapter(&adapter->i2c_adap); 3750 } 3751 3752 /** 3753 * igb_remove - Device Removal Routine 3754 * @pdev: PCI device information struct 3755 * 3756 * igb_remove is called by the PCI subsystem to alert the driver 3757 * that it should release a PCI device. The could be caused by a 3758 * Hot-Plug event, or because the driver is going to be removed from 3759 * memory. 3760 **/ 3761 static void igb_remove(struct pci_dev *pdev) 3762 { 3763 struct net_device *netdev = pci_get_drvdata(pdev); 3764 struct igb_adapter *adapter = netdev_priv(netdev); 3765 struct e1000_hw *hw = &adapter->hw; 3766 3767 pm_runtime_get_noresume(&pdev->dev); 3768 #ifdef CONFIG_IGB_HWMON 3769 igb_sysfs_exit(adapter); 3770 #endif 3771 igb_remove_i2c(adapter); 3772 igb_ptp_stop(adapter); 3773 /* The watchdog timer may be rescheduled, so explicitly 3774 * disable watchdog from being rescheduled. 3775 */ 3776 set_bit(__IGB_DOWN, &adapter->state); 3777 del_timer_sync(&adapter->watchdog_timer); 3778 del_timer_sync(&adapter->phy_info_timer); 3779 3780 cancel_work_sync(&adapter->reset_task); 3781 cancel_work_sync(&adapter->watchdog_task); 3782 3783 #ifdef CONFIG_IGB_DCA 3784 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3785 dev_info(&pdev->dev, "DCA disabled\n"); 3786 dca_remove_requester(&pdev->dev); 3787 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3788 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3789 } 3790 #endif 3791 3792 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3793 * would have already happened in close and is redundant. 3794 */ 3795 igb_release_hw_control(adapter); 3796 3797 #ifdef CONFIG_PCI_IOV 3798 igb_disable_sriov(pdev); 3799 #endif 3800 3801 unregister_netdev(netdev); 3802 3803 igb_clear_interrupt_scheme(adapter); 3804 3805 pci_iounmap(pdev, adapter->io_addr); 3806 if (hw->flash_address) 3807 iounmap(hw->flash_address); 3808 pci_release_mem_regions(pdev); 3809 3810 kfree(adapter->mac_table); 3811 kfree(adapter->shadow_vfta); 3812 free_netdev(netdev); 3813 3814 pci_disable_pcie_error_reporting(pdev); 3815 3816 pci_disable_device(pdev); 3817 } 3818 3819 /** 3820 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3821 * @adapter: board private structure to initialize 3822 * 3823 * This function initializes the vf specific data storage and then attempts to 3824 * allocate the VFs. The reason for ordering it this way is because it is much 3825 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3826 * the memory for the VFs. 3827 **/ 3828 static void igb_probe_vfs(struct igb_adapter *adapter) 3829 { 3830 #ifdef CONFIG_PCI_IOV 3831 struct pci_dev *pdev = adapter->pdev; 3832 struct e1000_hw *hw = &adapter->hw; 3833 3834 /* Virtualization features not supported on i210 family. */ 3835 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3836 return; 3837 3838 /* Of the below we really only want the effect of getting 3839 * IGB_FLAG_HAS_MSIX set (if available), without which 3840 * igb_enable_sriov() has no effect. 3841 */ 3842 igb_set_interrupt_capability(adapter, true); 3843 igb_reset_interrupt_capability(adapter); 3844 3845 pci_sriov_set_totalvfs(pdev, 7); 3846 igb_enable_sriov(pdev, max_vfs); 3847 3848 #endif /* CONFIG_PCI_IOV */ 3849 } 3850 3851 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3852 { 3853 struct e1000_hw *hw = &adapter->hw; 3854 unsigned int max_rss_queues; 3855 3856 /* Determine the maximum number of RSS queues supported. */ 3857 switch (hw->mac.type) { 3858 case e1000_i211: 3859 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3860 break; 3861 case e1000_82575: 3862 case e1000_i210: 3863 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3864 break; 3865 case e1000_i350: 3866 /* I350 cannot do RSS and SR-IOV at the same time */ 3867 if (!!adapter->vfs_allocated_count) { 3868 max_rss_queues = 1; 3869 break; 3870 } 3871 fallthrough; 3872 case e1000_82576: 3873 if (!!adapter->vfs_allocated_count) { 3874 max_rss_queues = 2; 3875 break; 3876 } 3877 fallthrough; 3878 case e1000_82580: 3879 case e1000_i354: 3880 default: 3881 max_rss_queues = IGB_MAX_RX_QUEUES; 3882 break; 3883 } 3884 3885 return max_rss_queues; 3886 } 3887 3888 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3889 { 3890 u32 max_rss_queues; 3891 3892 max_rss_queues = igb_get_max_rss_queues(adapter); 3893 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3894 3895 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3896 } 3897 3898 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3899 const u32 max_rss_queues) 3900 { 3901 struct e1000_hw *hw = &adapter->hw; 3902 3903 /* Determine if we need to pair queues. */ 3904 switch (hw->mac.type) { 3905 case e1000_82575: 3906 case e1000_i211: 3907 /* Device supports enough interrupts without queue pairing. */ 3908 break; 3909 case e1000_82576: 3910 case e1000_82580: 3911 case e1000_i350: 3912 case e1000_i354: 3913 case e1000_i210: 3914 default: 3915 /* If rss_queues > half of max_rss_queues, pair the queues in 3916 * order to conserve interrupts due to limited supply. 3917 */ 3918 if (adapter->rss_queues > (max_rss_queues / 2)) 3919 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3920 else 3921 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3922 break; 3923 } 3924 } 3925 3926 /** 3927 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3928 * @adapter: board private structure to initialize 3929 * 3930 * igb_sw_init initializes the Adapter private data structure. 3931 * Fields are initialized based on PCI device information and 3932 * OS network device settings (MTU size). 3933 **/ 3934 static int igb_sw_init(struct igb_adapter *adapter) 3935 { 3936 struct e1000_hw *hw = &adapter->hw; 3937 struct net_device *netdev = adapter->netdev; 3938 struct pci_dev *pdev = adapter->pdev; 3939 3940 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3941 3942 /* set default ring sizes */ 3943 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3944 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3945 3946 /* set default ITR values */ 3947 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3948 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3949 3950 /* set default work limits */ 3951 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3952 3953 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3954 VLAN_HLEN; 3955 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3956 3957 spin_lock_init(&adapter->nfc_lock); 3958 spin_lock_init(&adapter->stats64_lock); 3959 #ifdef CONFIG_PCI_IOV 3960 switch (hw->mac.type) { 3961 case e1000_82576: 3962 case e1000_i350: 3963 if (max_vfs > 7) { 3964 dev_warn(&pdev->dev, 3965 "Maximum of 7 VFs per PF, using max\n"); 3966 max_vfs = adapter->vfs_allocated_count = 7; 3967 } else 3968 adapter->vfs_allocated_count = max_vfs; 3969 if (adapter->vfs_allocated_count) 3970 dev_warn(&pdev->dev, 3971 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3972 break; 3973 default: 3974 break; 3975 } 3976 #endif /* CONFIG_PCI_IOV */ 3977 3978 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3979 adapter->flags |= IGB_FLAG_HAS_MSIX; 3980 3981 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3982 sizeof(struct igb_mac_addr), 3983 GFP_KERNEL); 3984 if (!adapter->mac_table) 3985 return -ENOMEM; 3986 3987 igb_probe_vfs(adapter); 3988 3989 igb_init_queue_configuration(adapter); 3990 3991 /* Setup and initialize a copy of the hw vlan table array */ 3992 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3993 GFP_KERNEL); 3994 if (!adapter->shadow_vfta) 3995 return -ENOMEM; 3996 3997 /* This call may decrease the number of queues */ 3998 if (igb_init_interrupt_scheme(adapter, true)) { 3999 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4000 return -ENOMEM; 4001 } 4002 4003 /* Explicitly disable IRQ since the NIC can be in any state. */ 4004 igb_irq_disable(adapter); 4005 4006 if (hw->mac.type >= e1000_i350) 4007 adapter->flags &= ~IGB_FLAG_DMAC; 4008 4009 set_bit(__IGB_DOWN, &adapter->state); 4010 return 0; 4011 } 4012 4013 /** 4014 * igb_open - Called when a network interface is made active 4015 * @netdev: network interface device structure 4016 * @resuming: indicates whether we are in a resume call 4017 * 4018 * Returns 0 on success, negative value on failure 4019 * 4020 * The open entry point is called when a network interface is made 4021 * active by the system (IFF_UP). At this point all resources needed 4022 * for transmit and receive operations are allocated, the interrupt 4023 * handler is registered with the OS, the watchdog timer is started, 4024 * and the stack is notified that the interface is ready. 4025 **/ 4026 static int __igb_open(struct net_device *netdev, bool resuming) 4027 { 4028 struct igb_adapter *adapter = netdev_priv(netdev); 4029 struct e1000_hw *hw = &adapter->hw; 4030 struct pci_dev *pdev = adapter->pdev; 4031 int err; 4032 int i; 4033 4034 /* disallow open during test */ 4035 if (test_bit(__IGB_TESTING, &adapter->state)) { 4036 WARN_ON(resuming); 4037 return -EBUSY; 4038 } 4039 4040 if (!resuming) 4041 pm_runtime_get_sync(&pdev->dev); 4042 4043 netif_carrier_off(netdev); 4044 4045 /* allocate transmit descriptors */ 4046 err = igb_setup_all_tx_resources(adapter); 4047 if (err) 4048 goto err_setup_tx; 4049 4050 /* allocate receive descriptors */ 4051 err = igb_setup_all_rx_resources(adapter); 4052 if (err) 4053 goto err_setup_rx; 4054 4055 igb_power_up_link(adapter); 4056 4057 /* before we allocate an interrupt, we must be ready to handle it. 4058 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4059 * as soon as we call pci_request_irq, so we have to setup our 4060 * clean_rx handler before we do so. 4061 */ 4062 igb_configure(adapter); 4063 4064 err = igb_request_irq(adapter); 4065 if (err) 4066 goto err_req_irq; 4067 4068 /* Notify the stack of the actual queue counts. */ 4069 err = netif_set_real_num_tx_queues(adapter->netdev, 4070 adapter->num_tx_queues); 4071 if (err) 4072 goto err_set_queues; 4073 4074 err = netif_set_real_num_rx_queues(adapter->netdev, 4075 adapter->num_rx_queues); 4076 if (err) 4077 goto err_set_queues; 4078 4079 /* From here on the code is the same as igb_up() */ 4080 clear_bit(__IGB_DOWN, &adapter->state); 4081 4082 for (i = 0; i < adapter->num_q_vectors; i++) 4083 napi_enable(&(adapter->q_vector[i]->napi)); 4084 4085 /* Clear any pending interrupts. */ 4086 rd32(E1000_TSICR); 4087 rd32(E1000_ICR); 4088 4089 igb_irq_enable(adapter); 4090 4091 /* notify VFs that reset has been completed */ 4092 if (adapter->vfs_allocated_count) { 4093 u32 reg_data = rd32(E1000_CTRL_EXT); 4094 4095 reg_data |= E1000_CTRL_EXT_PFRSTD; 4096 wr32(E1000_CTRL_EXT, reg_data); 4097 } 4098 4099 netif_tx_start_all_queues(netdev); 4100 4101 if (!resuming) 4102 pm_runtime_put(&pdev->dev); 4103 4104 /* start the watchdog. */ 4105 hw->mac.get_link_status = 1; 4106 schedule_work(&adapter->watchdog_task); 4107 4108 return 0; 4109 4110 err_set_queues: 4111 igb_free_irq(adapter); 4112 err_req_irq: 4113 igb_release_hw_control(adapter); 4114 igb_power_down_link(adapter); 4115 igb_free_all_rx_resources(adapter); 4116 err_setup_rx: 4117 igb_free_all_tx_resources(adapter); 4118 err_setup_tx: 4119 igb_reset(adapter); 4120 if (!resuming) 4121 pm_runtime_put(&pdev->dev); 4122 4123 return err; 4124 } 4125 4126 int igb_open(struct net_device *netdev) 4127 { 4128 return __igb_open(netdev, false); 4129 } 4130 4131 /** 4132 * igb_close - Disables a network interface 4133 * @netdev: network interface device structure 4134 * @suspending: indicates we are in a suspend call 4135 * 4136 * Returns 0, this is not allowed to fail 4137 * 4138 * The close entry point is called when an interface is de-activated 4139 * by the OS. The hardware is still under the driver's control, but 4140 * needs to be disabled. A global MAC reset is issued to stop the 4141 * hardware, and all transmit and receive resources are freed. 4142 **/ 4143 static int __igb_close(struct net_device *netdev, bool suspending) 4144 { 4145 struct igb_adapter *adapter = netdev_priv(netdev); 4146 struct pci_dev *pdev = adapter->pdev; 4147 4148 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4149 4150 if (!suspending) 4151 pm_runtime_get_sync(&pdev->dev); 4152 4153 igb_down(adapter); 4154 igb_free_irq(adapter); 4155 4156 igb_free_all_tx_resources(adapter); 4157 igb_free_all_rx_resources(adapter); 4158 4159 if (!suspending) 4160 pm_runtime_put_sync(&pdev->dev); 4161 return 0; 4162 } 4163 4164 int igb_close(struct net_device *netdev) 4165 { 4166 if (netif_device_present(netdev) || netdev->dismantle) 4167 return __igb_close(netdev, false); 4168 return 0; 4169 } 4170 4171 /** 4172 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4173 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4174 * 4175 * Return 0 on success, negative on failure 4176 **/ 4177 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4178 { 4179 struct device *dev = tx_ring->dev; 4180 int size; 4181 4182 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4183 4184 tx_ring->tx_buffer_info = vmalloc(size); 4185 if (!tx_ring->tx_buffer_info) 4186 goto err; 4187 4188 /* round up to nearest 4K */ 4189 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4190 tx_ring->size = ALIGN(tx_ring->size, 4096); 4191 4192 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4193 &tx_ring->dma, GFP_KERNEL); 4194 if (!tx_ring->desc) 4195 goto err; 4196 4197 tx_ring->next_to_use = 0; 4198 tx_ring->next_to_clean = 0; 4199 4200 return 0; 4201 4202 err: 4203 vfree(tx_ring->tx_buffer_info); 4204 tx_ring->tx_buffer_info = NULL; 4205 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4206 return -ENOMEM; 4207 } 4208 4209 /** 4210 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4211 * (Descriptors) for all queues 4212 * @adapter: board private structure 4213 * 4214 * Return 0 on success, negative on failure 4215 **/ 4216 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4217 { 4218 struct pci_dev *pdev = adapter->pdev; 4219 int i, err = 0; 4220 4221 for (i = 0; i < adapter->num_tx_queues; i++) { 4222 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4223 if (err) { 4224 dev_err(&pdev->dev, 4225 "Allocation for Tx Queue %u failed\n", i); 4226 for (i--; i >= 0; i--) 4227 igb_free_tx_resources(adapter->tx_ring[i]); 4228 break; 4229 } 4230 } 4231 4232 return err; 4233 } 4234 4235 /** 4236 * igb_setup_tctl - configure the transmit control registers 4237 * @adapter: Board private structure 4238 **/ 4239 void igb_setup_tctl(struct igb_adapter *adapter) 4240 { 4241 struct e1000_hw *hw = &adapter->hw; 4242 u32 tctl; 4243 4244 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4245 wr32(E1000_TXDCTL(0), 0); 4246 4247 /* Program the Transmit Control Register */ 4248 tctl = rd32(E1000_TCTL); 4249 tctl &= ~E1000_TCTL_CT; 4250 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4251 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4252 4253 igb_config_collision_dist(hw); 4254 4255 /* Enable transmits */ 4256 tctl |= E1000_TCTL_EN; 4257 4258 wr32(E1000_TCTL, tctl); 4259 } 4260 4261 /** 4262 * igb_configure_tx_ring - Configure transmit ring after Reset 4263 * @adapter: board private structure 4264 * @ring: tx ring to configure 4265 * 4266 * Configure a transmit ring after a reset. 4267 **/ 4268 void igb_configure_tx_ring(struct igb_adapter *adapter, 4269 struct igb_ring *ring) 4270 { 4271 struct e1000_hw *hw = &adapter->hw; 4272 u32 txdctl = 0; 4273 u64 tdba = ring->dma; 4274 int reg_idx = ring->reg_idx; 4275 4276 wr32(E1000_TDLEN(reg_idx), 4277 ring->count * sizeof(union e1000_adv_tx_desc)); 4278 wr32(E1000_TDBAL(reg_idx), 4279 tdba & 0x00000000ffffffffULL); 4280 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4281 4282 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4283 wr32(E1000_TDH(reg_idx), 0); 4284 writel(0, ring->tail); 4285 4286 txdctl |= IGB_TX_PTHRESH; 4287 txdctl |= IGB_TX_HTHRESH << 8; 4288 txdctl |= IGB_TX_WTHRESH << 16; 4289 4290 /* reinitialize tx_buffer_info */ 4291 memset(ring->tx_buffer_info, 0, 4292 sizeof(struct igb_tx_buffer) * ring->count); 4293 4294 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4295 wr32(E1000_TXDCTL(reg_idx), txdctl); 4296 } 4297 4298 /** 4299 * igb_configure_tx - Configure transmit Unit after Reset 4300 * @adapter: board private structure 4301 * 4302 * Configure the Tx unit of the MAC after a reset. 4303 **/ 4304 static void igb_configure_tx(struct igb_adapter *adapter) 4305 { 4306 struct e1000_hw *hw = &adapter->hw; 4307 int i; 4308 4309 /* disable the queues */ 4310 for (i = 0; i < adapter->num_tx_queues; i++) 4311 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4312 4313 wrfl(); 4314 usleep_range(10000, 20000); 4315 4316 for (i = 0; i < adapter->num_tx_queues; i++) 4317 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4318 } 4319 4320 /** 4321 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4322 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4323 * 4324 * Returns 0 on success, negative on failure 4325 **/ 4326 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4327 { 4328 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4329 struct device *dev = rx_ring->dev; 4330 int size; 4331 4332 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4333 4334 rx_ring->rx_buffer_info = vmalloc(size); 4335 if (!rx_ring->rx_buffer_info) 4336 goto err; 4337 4338 /* Round up to nearest 4K */ 4339 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4340 rx_ring->size = ALIGN(rx_ring->size, 4096); 4341 4342 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4343 &rx_ring->dma, GFP_KERNEL); 4344 if (!rx_ring->desc) 4345 goto err; 4346 4347 rx_ring->next_to_alloc = 0; 4348 rx_ring->next_to_clean = 0; 4349 rx_ring->next_to_use = 0; 4350 4351 rx_ring->xdp_prog = adapter->xdp_prog; 4352 4353 /* XDP RX-queue info */ 4354 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4355 rx_ring->queue_index) < 0) 4356 goto err; 4357 4358 return 0; 4359 4360 err: 4361 vfree(rx_ring->rx_buffer_info); 4362 rx_ring->rx_buffer_info = NULL; 4363 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4364 return -ENOMEM; 4365 } 4366 4367 /** 4368 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4369 * (Descriptors) for all queues 4370 * @adapter: board private structure 4371 * 4372 * Return 0 on success, negative on failure 4373 **/ 4374 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4375 { 4376 struct pci_dev *pdev = adapter->pdev; 4377 int i, err = 0; 4378 4379 for (i = 0; i < adapter->num_rx_queues; i++) { 4380 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4381 if (err) { 4382 dev_err(&pdev->dev, 4383 "Allocation for Rx Queue %u failed\n", i); 4384 for (i--; i >= 0; i--) 4385 igb_free_rx_resources(adapter->rx_ring[i]); 4386 break; 4387 } 4388 } 4389 4390 return err; 4391 } 4392 4393 /** 4394 * igb_setup_mrqc - configure the multiple receive queue control registers 4395 * @adapter: Board private structure 4396 **/ 4397 static void igb_setup_mrqc(struct igb_adapter *adapter) 4398 { 4399 struct e1000_hw *hw = &adapter->hw; 4400 u32 mrqc, rxcsum; 4401 u32 j, num_rx_queues; 4402 u32 rss_key[10]; 4403 4404 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4405 for (j = 0; j < 10; j++) 4406 wr32(E1000_RSSRK(j), rss_key[j]); 4407 4408 num_rx_queues = adapter->rss_queues; 4409 4410 switch (hw->mac.type) { 4411 case e1000_82576: 4412 /* 82576 supports 2 RSS queues for SR-IOV */ 4413 if (adapter->vfs_allocated_count) 4414 num_rx_queues = 2; 4415 break; 4416 default: 4417 break; 4418 } 4419 4420 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4421 for (j = 0; j < IGB_RETA_SIZE; j++) 4422 adapter->rss_indir_tbl[j] = 4423 (j * num_rx_queues) / IGB_RETA_SIZE; 4424 adapter->rss_indir_tbl_init = num_rx_queues; 4425 } 4426 igb_write_rss_indir_tbl(adapter); 4427 4428 /* Disable raw packet checksumming so that RSS hash is placed in 4429 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4430 * offloads as they are enabled by default 4431 */ 4432 rxcsum = rd32(E1000_RXCSUM); 4433 rxcsum |= E1000_RXCSUM_PCSD; 4434 4435 if (adapter->hw.mac.type >= e1000_82576) 4436 /* Enable Receive Checksum Offload for SCTP */ 4437 rxcsum |= E1000_RXCSUM_CRCOFL; 4438 4439 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4440 wr32(E1000_RXCSUM, rxcsum); 4441 4442 /* Generate RSS hash based on packet types, TCP/UDP 4443 * port numbers and/or IPv4/v6 src and dst addresses 4444 */ 4445 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4446 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4447 E1000_MRQC_RSS_FIELD_IPV6 | 4448 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4449 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4450 4451 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4452 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4453 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4454 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4455 4456 /* If VMDq is enabled then we set the appropriate mode for that, else 4457 * we default to RSS so that an RSS hash is calculated per packet even 4458 * if we are only using one queue 4459 */ 4460 if (adapter->vfs_allocated_count) { 4461 if (hw->mac.type > e1000_82575) { 4462 /* Set the default pool for the PF's first queue */ 4463 u32 vtctl = rd32(E1000_VT_CTL); 4464 4465 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4466 E1000_VT_CTL_DISABLE_DEF_POOL); 4467 vtctl |= adapter->vfs_allocated_count << 4468 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4469 wr32(E1000_VT_CTL, vtctl); 4470 } 4471 if (adapter->rss_queues > 1) 4472 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4473 else 4474 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4475 } else { 4476 if (hw->mac.type != e1000_i211) 4477 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4478 } 4479 igb_vmm_control(adapter); 4480 4481 wr32(E1000_MRQC, mrqc); 4482 } 4483 4484 /** 4485 * igb_setup_rctl - configure the receive control registers 4486 * @adapter: Board private structure 4487 **/ 4488 void igb_setup_rctl(struct igb_adapter *adapter) 4489 { 4490 struct e1000_hw *hw = &adapter->hw; 4491 u32 rctl; 4492 4493 rctl = rd32(E1000_RCTL); 4494 4495 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4496 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4497 4498 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4499 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4500 4501 /* enable stripping of CRC. It's unlikely this will break BMC 4502 * redirection as it did with e1000. Newer features require 4503 * that the HW strips the CRC. 4504 */ 4505 rctl |= E1000_RCTL_SECRC; 4506 4507 /* disable store bad packets and clear size bits. */ 4508 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4509 4510 /* enable LPE to allow for reception of jumbo frames */ 4511 rctl |= E1000_RCTL_LPE; 4512 4513 /* disable queue 0 to prevent tail write w/o re-config */ 4514 wr32(E1000_RXDCTL(0), 0); 4515 4516 /* Attention!!! For SR-IOV PF driver operations you must enable 4517 * queue drop for all VF and PF queues to prevent head of line blocking 4518 * if an un-trusted VF does not provide descriptors to hardware. 4519 */ 4520 if (adapter->vfs_allocated_count) { 4521 /* set all queue drop enable bits */ 4522 wr32(E1000_QDE, ALL_QUEUES); 4523 } 4524 4525 /* This is useful for sniffing bad packets. */ 4526 if (adapter->netdev->features & NETIF_F_RXALL) { 4527 /* UPE and MPE will be handled by normal PROMISC logic 4528 * in e1000e_set_rx_mode 4529 */ 4530 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4531 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4532 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4533 4534 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4535 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4536 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4537 * and that breaks VLANs. 4538 */ 4539 } 4540 4541 wr32(E1000_RCTL, rctl); 4542 } 4543 4544 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4545 int vfn) 4546 { 4547 struct e1000_hw *hw = &adapter->hw; 4548 u32 vmolr; 4549 4550 if (size > MAX_JUMBO_FRAME_SIZE) 4551 size = MAX_JUMBO_FRAME_SIZE; 4552 4553 vmolr = rd32(E1000_VMOLR(vfn)); 4554 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4555 vmolr |= size | E1000_VMOLR_LPE; 4556 wr32(E1000_VMOLR(vfn), vmolr); 4557 4558 return 0; 4559 } 4560 4561 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4562 int vfn, bool enable) 4563 { 4564 struct e1000_hw *hw = &adapter->hw; 4565 u32 val, reg; 4566 4567 if (hw->mac.type < e1000_82576) 4568 return; 4569 4570 if (hw->mac.type == e1000_i350) 4571 reg = E1000_DVMOLR(vfn); 4572 else 4573 reg = E1000_VMOLR(vfn); 4574 4575 val = rd32(reg); 4576 if (enable) 4577 val |= E1000_VMOLR_STRVLAN; 4578 else 4579 val &= ~(E1000_VMOLR_STRVLAN); 4580 wr32(reg, val); 4581 } 4582 4583 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4584 int vfn, bool aupe) 4585 { 4586 struct e1000_hw *hw = &adapter->hw; 4587 u32 vmolr; 4588 4589 /* This register exists only on 82576 and newer so if we are older then 4590 * we should exit and do nothing 4591 */ 4592 if (hw->mac.type < e1000_82576) 4593 return; 4594 4595 vmolr = rd32(E1000_VMOLR(vfn)); 4596 if (aupe) 4597 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4598 else 4599 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4600 4601 /* clear all bits that might not be set */ 4602 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4603 4604 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4605 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4606 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4607 * multicast packets 4608 */ 4609 if (vfn <= adapter->vfs_allocated_count) 4610 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4611 4612 wr32(E1000_VMOLR(vfn), vmolr); 4613 } 4614 4615 /** 4616 * igb_setup_srrctl - configure the split and replication receive control 4617 * registers 4618 * @adapter: Board private structure 4619 * @ring: receive ring to be configured 4620 **/ 4621 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4622 { 4623 struct e1000_hw *hw = &adapter->hw; 4624 int reg_idx = ring->reg_idx; 4625 u32 srrctl = 0; 4626 4627 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4628 if (ring_uses_large_buffer(ring)) 4629 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4630 else 4631 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4632 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4633 if (hw->mac.type >= e1000_82580) 4634 srrctl |= E1000_SRRCTL_TIMESTAMP; 4635 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4636 * queues and rx flow control is disabled 4637 */ 4638 if (adapter->vfs_allocated_count || 4639 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4640 adapter->num_rx_queues > 1)) 4641 srrctl |= E1000_SRRCTL_DROP_EN; 4642 4643 wr32(E1000_SRRCTL(reg_idx), srrctl); 4644 } 4645 4646 /** 4647 * igb_configure_rx_ring - Configure a receive ring after Reset 4648 * @adapter: board private structure 4649 * @ring: receive ring to be configured 4650 * 4651 * Configure the Rx unit of the MAC after a reset. 4652 **/ 4653 void igb_configure_rx_ring(struct igb_adapter *adapter, 4654 struct igb_ring *ring) 4655 { 4656 struct e1000_hw *hw = &adapter->hw; 4657 union e1000_adv_rx_desc *rx_desc; 4658 u64 rdba = ring->dma; 4659 int reg_idx = ring->reg_idx; 4660 u32 rxdctl = 0; 4661 4662 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4663 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4664 MEM_TYPE_PAGE_SHARED, NULL)); 4665 4666 /* disable the queue */ 4667 wr32(E1000_RXDCTL(reg_idx), 0); 4668 4669 /* Set DMA base address registers */ 4670 wr32(E1000_RDBAL(reg_idx), 4671 rdba & 0x00000000ffffffffULL); 4672 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4673 wr32(E1000_RDLEN(reg_idx), 4674 ring->count * sizeof(union e1000_adv_rx_desc)); 4675 4676 /* initialize head and tail */ 4677 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4678 wr32(E1000_RDH(reg_idx), 0); 4679 writel(0, ring->tail); 4680 4681 /* set descriptor configuration */ 4682 igb_setup_srrctl(adapter, ring); 4683 4684 /* set filtering for VMDQ pools */ 4685 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4686 4687 rxdctl |= IGB_RX_PTHRESH; 4688 rxdctl |= IGB_RX_HTHRESH << 8; 4689 rxdctl |= IGB_RX_WTHRESH << 16; 4690 4691 /* initialize rx_buffer_info */ 4692 memset(ring->rx_buffer_info, 0, 4693 sizeof(struct igb_rx_buffer) * ring->count); 4694 4695 /* initialize Rx descriptor 0 */ 4696 rx_desc = IGB_RX_DESC(ring, 0); 4697 rx_desc->wb.upper.length = 0; 4698 4699 /* enable receive descriptor fetching */ 4700 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4701 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4702 } 4703 4704 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4705 struct igb_ring *rx_ring) 4706 { 4707 /* set build_skb and buffer size flags */ 4708 clear_ring_build_skb_enabled(rx_ring); 4709 clear_ring_uses_large_buffer(rx_ring); 4710 4711 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4712 return; 4713 4714 set_ring_build_skb_enabled(rx_ring); 4715 4716 #if (PAGE_SIZE < 8192) 4717 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4718 return; 4719 4720 set_ring_uses_large_buffer(rx_ring); 4721 #endif 4722 } 4723 4724 /** 4725 * igb_configure_rx - Configure receive Unit after Reset 4726 * @adapter: board private structure 4727 * 4728 * Configure the Rx unit of the MAC after a reset. 4729 **/ 4730 static void igb_configure_rx(struct igb_adapter *adapter) 4731 { 4732 int i; 4733 4734 /* set the correct pool for the PF default MAC address in entry 0 */ 4735 igb_set_default_mac_filter(adapter); 4736 4737 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4738 * the Base and Length of the Rx Descriptor Ring 4739 */ 4740 for (i = 0; i < adapter->num_rx_queues; i++) { 4741 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4742 4743 igb_set_rx_buffer_len(adapter, rx_ring); 4744 igb_configure_rx_ring(adapter, rx_ring); 4745 } 4746 } 4747 4748 /** 4749 * igb_free_tx_resources - Free Tx Resources per Queue 4750 * @tx_ring: Tx descriptor ring for a specific queue 4751 * 4752 * Free all transmit software resources 4753 **/ 4754 void igb_free_tx_resources(struct igb_ring *tx_ring) 4755 { 4756 igb_clean_tx_ring(tx_ring); 4757 4758 vfree(tx_ring->tx_buffer_info); 4759 tx_ring->tx_buffer_info = NULL; 4760 4761 /* if not set, then don't free */ 4762 if (!tx_ring->desc) 4763 return; 4764 4765 dma_free_coherent(tx_ring->dev, tx_ring->size, 4766 tx_ring->desc, tx_ring->dma); 4767 4768 tx_ring->desc = NULL; 4769 } 4770 4771 /** 4772 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4773 * @adapter: board private structure 4774 * 4775 * Free all transmit software resources 4776 **/ 4777 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4778 { 4779 int i; 4780 4781 for (i = 0; i < adapter->num_tx_queues; i++) 4782 if (adapter->tx_ring[i]) 4783 igb_free_tx_resources(adapter->tx_ring[i]); 4784 } 4785 4786 /** 4787 * igb_clean_tx_ring - Free Tx Buffers 4788 * @tx_ring: ring to be cleaned 4789 **/ 4790 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4791 { 4792 u16 i = tx_ring->next_to_clean; 4793 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4794 4795 while (i != tx_ring->next_to_use) { 4796 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4797 4798 /* Free all the Tx ring sk_buffs */ 4799 dev_kfree_skb_any(tx_buffer->skb); 4800 4801 /* unmap skb header data */ 4802 dma_unmap_single(tx_ring->dev, 4803 dma_unmap_addr(tx_buffer, dma), 4804 dma_unmap_len(tx_buffer, len), 4805 DMA_TO_DEVICE); 4806 4807 /* check for eop_desc to determine the end of the packet */ 4808 eop_desc = tx_buffer->next_to_watch; 4809 tx_desc = IGB_TX_DESC(tx_ring, i); 4810 4811 /* unmap remaining buffers */ 4812 while (tx_desc != eop_desc) { 4813 tx_buffer++; 4814 tx_desc++; 4815 i++; 4816 if (unlikely(i == tx_ring->count)) { 4817 i = 0; 4818 tx_buffer = tx_ring->tx_buffer_info; 4819 tx_desc = IGB_TX_DESC(tx_ring, 0); 4820 } 4821 4822 /* unmap any remaining paged data */ 4823 if (dma_unmap_len(tx_buffer, len)) 4824 dma_unmap_page(tx_ring->dev, 4825 dma_unmap_addr(tx_buffer, dma), 4826 dma_unmap_len(tx_buffer, len), 4827 DMA_TO_DEVICE); 4828 } 4829 4830 /* move us one more past the eop_desc for start of next pkt */ 4831 tx_buffer++; 4832 i++; 4833 if (unlikely(i == tx_ring->count)) { 4834 i = 0; 4835 tx_buffer = tx_ring->tx_buffer_info; 4836 } 4837 } 4838 4839 /* reset BQL for queue */ 4840 netdev_tx_reset_queue(txring_txq(tx_ring)); 4841 4842 /* reset next_to_use and next_to_clean */ 4843 tx_ring->next_to_use = 0; 4844 tx_ring->next_to_clean = 0; 4845 } 4846 4847 /** 4848 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4849 * @adapter: board private structure 4850 **/ 4851 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4852 { 4853 int i; 4854 4855 for (i = 0; i < adapter->num_tx_queues; i++) 4856 if (adapter->tx_ring[i]) 4857 igb_clean_tx_ring(adapter->tx_ring[i]); 4858 } 4859 4860 /** 4861 * igb_free_rx_resources - Free Rx Resources 4862 * @rx_ring: ring to clean the resources from 4863 * 4864 * Free all receive software resources 4865 **/ 4866 void igb_free_rx_resources(struct igb_ring *rx_ring) 4867 { 4868 igb_clean_rx_ring(rx_ring); 4869 4870 rx_ring->xdp_prog = NULL; 4871 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4872 vfree(rx_ring->rx_buffer_info); 4873 rx_ring->rx_buffer_info = NULL; 4874 4875 /* if not set, then don't free */ 4876 if (!rx_ring->desc) 4877 return; 4878 4879 dma_free_coherent(rx_ring->dev, rx_ring->size, 4880 rx_ring->desc, rx_ring->dma); 4881 4882 rx_ring->desc = NULL; 4883 } 4884 4885 /** 4886 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4887 * @adapter: board private structure 4888 * 4889 * Free all receive software resources 4890 **/ 4891 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4892 { 4893 int i; 4894 4895 for (i = 0; i < adapter->num_rx_queues; i++) 4896 if (adapter->rx_ring[i]) 4897 igb_free_rx_resources(adapter->rx_ring[i]); 4898 } 4899 4900 /** 4901 * igb_clean_rx_ring - Free Rx Buffers per Queue 4902 * @rx_ring: ring to free buffers from 4903 **/ 4904 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4905 { 4906 u16 i = rx_ring->next_to_clean; 4907 4908 dev_kfree_skb(rx_ring->skb); 4909 rx_ring->skb = NULL; 4910 4911 /* Free all the Rx ring sk_buffs */ 4912 while (i != rx_ring->next_to_alloc) { 4913 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4914 4915 /* Invalidate cache lines that may have been written to by 4916 * device so that we avoid corrupting memory. 4917 */ 4918 dma_sync_single_range_for_cpu(rx_ring->dev, 4919 buffer_info->dma, 4920 buffer_info->page_offset, 4921 igb_rx_bufsz(rx_ring), 4922 DMA_FROM_DEVICE); 4923 4924 /* free resources associated with mapping */ 4925 dma_unmap_page_attrs(rx_ring->dev, 4926 buffer_info->dma, 4927 igb_rx_pg_size(rx_ring), 4928 DMA_FROM_DEVICE, 4929 IGB_RX_DMA_ATTR); 4930 __page_frag_cache_drain(buffer_info->page, 4931 buffer_info->pagecnt_bias); 4932 4933 i++; 4934 if (i == rx_ring->count) 4935 i = 0; 4936 } 4937 4938 rx_ring->next_to_alloc = 0; 4939 rx_ring->next_to_clean = 0; 4940 rx_ring->next_to_use = 0; 4941 } 4942 4943 /** 4944 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4945 * @adapter: board private structure 4946 **/ 4947 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4948 { 4949 int i; 4950 4951 for (i = 0; i < adapter->num_rx_queues; i++) 4952 if (adapter->rx_ring[i]) 4953 igb_clean_rx_ring(adapter->rx_ring[i]); 4954 } 4955 4956 /** 4957 * igb_set_mac - Change the Ethernet Address of the NIC 4958 * @netdev: network interface device structure 4959 * @p: pointer to an address structure 4960 * 4961 * Returns 0 on success, negative on failure 4962 **/ 4963 static int igb_set_mac(struct net_device *netdev, void *p) 4964 { 4965 struct igb_adapter *adapter = netdev_priv(netdev); 4966 struct e1000_hw *hw = &adapter->hw; 4967 struct sockaddr *addr = p; 4968 4969 if (!is_valid_ether_addr(addr->sa_data)) 4970 return -EADDRNOTAVAIL; 4971 4972 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4973 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4974 4975 /* set the correct pool for the new PF MAC address in entry 0 */ 4976 igb_set_default_mac_filter(adapter); 4977 4978 return 0; 4979 } 4980 4981 /** 4982 * igb_write_mc_addr_list - write multicast addresses to MTA 4983 * @netdev: network interface device structure 4984 * 4985 * Writes multicast address list to the MTA hash table. 4986 * Returns: -ENOMEM on failure 4987 * 0 on no addresses written 4988 * X on writing X addresses to MTA 4989 **/ 4990 static int igb_write_mc_addr_list(struct net_device *netdev) 4991 { 4992 struct igb_adapter *adapter = netdev_priv(netdev); 4993 struct e1000_hw *hw = &adapter->hw; 4994 struct netdev_hw_addr *ha; 4995 u8 *mta_list; 4996 int i; 4997 4998 if (netdev_mc_empty(netdev)) { 4999 /* nothing to program, so clear mc list */ 5000 igb_update_mc_addr_list(hw, NULL, 0); 5001 igb_restore_vf_multicasts(adapter); 5002 return 0; 5003 } 5004 5005 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5006 if (!mta_list) 5007 return -ENOMEM; 5008 5009 /* The shared function expects a packed array of only addresses. */ 5010 i = 0; 5011 netdev_for_each_mc_addr(ha, netdev) 5012 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5013 5014 igb_update_mc_addr_list(hw, mta_list, i); 5015 kfree(mta_list); 5016 5017 return netdev_mc_count(netdev); 5018 } 5019 5020 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5021 { 5022 struct e1000_hw *hw = &adapter->hw; 5023 u32 i, pf_id; 5024 5025 switch (hw->mac.type) { 5026 case e1000_i210: 5027 case e1000_i211: 5028 case e1000_i350: 5029 /* VLAN filtering needed for VLAN prio filter */ 5030 if (adapter->netdev->features & NETIF_F_NTUPLE) 5031 break; 5032 fallthrough; 5033 case e1000_82576: 5034 case e1000_82580: 5035 case e1000_i354: 5036 /* VLAN filtering needed for pool filtering */ 5037 if (adapter->vfs_allocated_count) 5038 break; 5039 fallthrough; 5040 default: 5041 return 1; 5042 } 5043 5044 /* We are already in VLAN promisc, nothing to do */ 5045 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5046 return 0; 5047 5048 if (!adapter->vfs_allocated_count) 5049 goto set_vfta; 5050 5051 /* Add PF to all active pools */ 5052 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5053 5054 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5055 u32 vlvf = rd32(E1000_VLVF(i)); 5056 5057 vlvf |= BIT(pf_id); 5058 wr32(E1000_VLVF(i), vlvf); 5059 } 5060 5061 set_vfta: 5062 /* Set all bits in the VLAN filter table array */ 5063 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5064 hw->mac.ops.write_vfta(hw, i, ~0U); 5065 5066 /* Set flag so we don't redo unnecessary work */ 5067 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5068 5069 return 0; 5070 } 5071 5072 #define VFTA_BLOCK_SIZE 8 5073 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5074 { 5075 struct e1000_hw *hw = &adapter->hw; 5076 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5077 u32 vid_start = vfta_offset * 32; 5078 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5079 u32 i, vid, word, bits, pf_id; 5080 5081 /* guarantee that we don't scrub out management VLAN */ 5082 vid = adapter->mng_vlan_id; 5083 if (vid >= vid_start && vid < vid_end) 5084 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5085 5086 if (!adapter->vfs_allocated_count) 5087 goto set_vfta; 5088 5089 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5090 5091 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5092 u32 vlvf = rd32(E1000_VLVF(i)); 5093 5094 /* pull VLAN ID from VLVF */ 5095 vid = vlvf & VLAN_VID_MASK; 5096 5097 /* only concern ourselves with a certain range */ 5098 if (vid < vid_start || vid >= vid_end) 5099 continue; 5100 5101 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5102 /* record VLAN ID in VFTA */ 5103 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5104 5105 /* if PF is part of this then continue */ 5106 if (test_bit(vid, adapter->active_vlans)) 5107 continue; 5108 } 5109 5110 /* remove PF from the pool */ 5111 bits = ~BIT(pf_id); 5112 bits &= rd32(E1000_VLVF(i)); 5113 wr32(E1000_VLVF(i), bits); 5114 } 5115 5116 set_vfta: 5117 /* extract values from active_vlans and write back to VFTA */ 5118 for (i = VFTA_BLOCK_SIZE; i--;) { 5119 vid = (vfta_offset + i) * 32; 5120 word = vid / BITS_PER_LONG; 5121 bits = vid % BITS_PER_LONG; 5122 5123 vfta[i] |= adapter->active_vlans[word] >> bits; 5124 5125 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5126 } 5127 } 5128 5129 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5130 { 5131 u32 i; 5132 5133 /* We are not in VLAN promisc, nothing to do */ 5134 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5135 return; 5136 5137 /* Set flag so we don't redo unnecessary work */ 5138 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5139 5140 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5141 igb_scrub_vfta(adapter, i); 5142 } 5143 5144 /** 5145 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5146 * @netdev: network interface device structure 5147 * 5148 * The set_rx_mode entry point is called whenever the unicast or multicast 5149 * address lists or the network interface flags are updated. This routine is 5150 * responsible for configuring the hardware for proper unicast, multicast, 5151 * promiscuous mode, and all-multi behavior. 5152 **/ 5153 static void igb_set_rx_mode(struct net_device *netdev) 5154 { 5155 struct igb_adapter *adapter = netdev_priv(netdev); 5156 struct e1000_hw *hw = &adapter->hw; 5157 unsigned int vfn = adapter->vfs_allocated_count; 5158 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5159 int count; 5160 5161 /* Check for Promiscuous and All Multicast modes */ 5162 if (netdev->flags & IFF_PROMISC) { 5163 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5164 vmolr |= E1000_VMOLR_MPME; 5165 5166 /* enable use of UTA filter to force packets to default pool */ 5167 if (hw->mac.type == e1000_82576) 5168 vmolr |= E1000_VMOLR_ROPE; 5169 } else { 5170 if (netdev->flags & IFF_ALLMULTI) { 5171 rctl |= E1000_RCTL_MPE; 5172 vmolr |= E1000_VMOLR_MPME; 5173 } else { 5174 /* Write addresses to the MTA, if the attempt fails 5175 * then we should just turn on promiscuous mode so 5176 * that we can at least receive multicast traffic 5177 */ 5178 count = igb_write_mc_addr_list(netdev); 5179 if (count < 0) { 5180 rctl |= E1000_RCTL_MPE; 5181 vmolr |= E1000_VMOLR_MPME; 5182 } else if (count) { 5183 vmolr |= E1000_VMOLR_ROMPE; 5184 } 5185 } 5186 } 5187 5188 /* Write addresses to available RAR registers, if there is not 5189 * sufficient space to store all the addresses then enable 5190 * unicast promiscuous mode 5191 */ 5192 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5193 rctl |= E1000_RCTL_UPE; 5194 vmolr |= E1000_VMOLR_ROPE; 5195 } 5196 5197 /* enable VLAN filtering by default */ 5198 rctl |= E1000_RCTL_VFE; 5199 5200 /* disable VLAN filtering for modes that require it */ 5201 if ((netdev->flags & IFF_PROMISC) || 5202 (netdev->features & NETIF_F_RXALL)) { 5203 /* if we fail to set all rules then just clear VFE */ 5204 if (igb_vlan_promisc_enable(adapter)) 5205 rctl &= ~E1000_RCTL_VFE; 5206 } else { 5207 igb_vlan_promisc_disable(adapter); 5208 } 5209 5210 /* update state of unicast, multicast, and VLAN filtering modes */ 5211 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5212 E1000_RCTL_VFE); 5213 wr32(E1000_RCTL, rctl); 5214 5215 #if (PAGE_SIZE < 8192) 5216 if (!adapter->vfs_allocated_count) { 5217 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5218 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5219 } 5220 #endif 5221 wr32(E1000_RLPML, rlpml); 5222 5223 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5224 * the VMOLR to enable the appropriate modes. Without this workaround 5225 * we will have issues with VLAN tag stripping not being done for frames 5226 * that are only arriving because we are the default pool 5227 */ 5228 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5229 return; 5230 5231 /* set UTA to appropriate mode */ 5232 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5233 5234 vmolr |= rd32(E1000_VMOLR(vfn)) & 5235 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5236 5237 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5238 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5239 #if (PAGE_SIZE < 8192) 5240 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5241 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5242 else 5243 #endif 5244 vmolr |= MAX_JUMBO_FRAME_SIZE; 5245 vmolr |= E1000_VMOLR_LPE; 5246 5247 wr32(E1000_VMOLR(vfn), vmolr); 5248 5249 igb_restore_vf_multicasts(adapter); 5250 } 5251 5252 static void igb_check_wvbr(struct igb_adapter *adapter) 5253 { 5254 struct e1000_hw *hw = &adapter->hw; 5255 u32 wvbr = 0; 5256 5257 switch (hw->mac.type) { 5258 case e1000_82576: 5259 case e1000_i350: 5260 wvbr = rd32(E1000_WVBR); 5261 if (!wvbr) 5262 return; 5263 break; 5264 default: 5265 break; 5266 } 5267 5268 adapter->wvbr |= wvbr; 5269 } 5270 5271 #define IGB_STAGGERED_QUEUE_OFFSET 8 5272 5273 static void igb_spoof_check(struct igb_adapter *adapter) 5274 { 5275 int j; 5276 5277 if (!adapter->wvbr) 5278 return; 5279 5280 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5281 if (adapter->wvbr & BIT(j) || 5282 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5283 dev_warn(&adapter->pdev->dev, 5284 "Spoof event(s) detected on VF %d\n", j); 5285 adapter->wvbr &= 5286 ~(BIT(j) | 5287 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5288 } 5289 } 5290 } 5291 5292 /* Need to wait a few seconds after link up to get diagnostic information from 5293 * the phy 5294 */ 5295 static void igb_update_phy_info(struct timer_list *t) 5296 { 5297 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5298 igb_get_phy_info(&adapter->hw); 5299 } 5300 5301 /** 5302 * igb_has_link - check shared code for link and determine up/down 5303 * @adapter: pointer to driver private info 5304 **/ 5305 bool igb_has_link(struct igb_adapter *adapter) 5306 { 5307 struct e1000_hw *hw = &adapter->hw; 5308 bool link_active = false; 5309 5310 /* get_link_status is set on LSC (link status) interrupt or 5311 * rx sequence error interrupt. get_link_status will stay 5312 * false until the e1000_check_for_link establishes link 5313 * for copper adapters ONLY 5314 */ 5315 switch (hw->phy.media_type) { 5316 case e1000_media_type_copper: 5317 if (!hw->mac.get_link_status) 5318 return true; 5319 fallthrough; 5320 case e1000_media_type_internal_serdes: 5321 hw->mac.ops.check_for_link(hw); 5322 link_active = !hw->mac.get_link_status; 5323 break; 5324 default: 5325 case e1000_media_type_unknown: 5326 break; 5327 } 5328 5329 if (((hw->mac.type == e1000_i210) || 5330 (hw->mac.type == e1000_i211)) && 5331 (hw->phy.id == I210_I_PHY_ID)) { 5332 if (!netif_carrier_ok(adapter->netdev)) { 5333 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5334 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5335 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5336 adapter->link_check_timeout = jiffies; 5337 } 5338 } 5339 5340 return link_active; 5341 } 5342 5343 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5344 { 5345 bool ret = false; 5346 u32 ctrl_ext, thstat; 5347 5348 /* check for thermal sensor event on i350 copper only */ 5349 if (hw->mac.type == e1000_i350) { 5350 thstat = rd32(E1000_THSTAT); 5351 ctrl_ext = rd32(E1000_CTRL_EXT); 5352 5353 if ((hw->phy.media_type == e1000_media_type_copper) && 5354 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5355 ret = !!(thstat & event); 5356 } 5357 5358 return ret; 5359 } 5360 5361 /** 5362 * igb_check_lvmmc - check for malformed packets received 5363 * and indicated in LVMMC register 5364 * @adapter: pointer to adapter 5365 **/ 5366 static void igb_check_lvmmc(struct igb_adapter *adapter) 5367 { 5368 struct e1000_hw *hw = &adapter->hw; 5369 u32 lvmmc; 5370 5371 lvmmc = rd32(E1000_LVMMC); 5372 if (lvmmc) { 5373 if (unlikely(net_ratelimit())) { 5374 netdev_warn(adapter->netdev, 5375 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5376 lvmmc); 5377 } 5378 } 5379 } 5380 5381 /** 5382 * igb_watchdog - Timer Call-back 5383 * @t: pointer to timer_list containing our private info pointer 5384 **/ 5385 static void igb_watchdog(struct timer_list *t) 5386 { 5387 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5388 /* Do the rest outside of interrupt context */ 5389 schedule_work(&adapter->watchdog_task); 5390 } 5391 5392 static void igb_watchdog_task(struct work_struct *work) 5393 { 5394 struct igb_adapter *adapter = container_of(work, 5395 struct igb_adapter, 5396 watchdog_task); 5397 struct e1000_hw *hw = &adapter->hw; 5398 struct e1000_phy_info *phy = &hw->phy; 5399 struct net_device *netdev = adapter->netdev; 5400 u32 link; 5401 int i; 5402 u32 connsw; 5403 u16 phy_data, retry_count = 20; 5404 5405 link = igb_has_link(adapter); 5406 5407 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5408 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5409 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5410 else 5411 link = false; 5412 } 5413 5414 /* Force link down if we have fiber to swap to */ 5415 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5416 if (hw->phy.media_type == e1000_media_type_copper) { 5417 connsw = rd32(E1000_CONNSW); 5418 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5419 link = 0; 5420 } 5421 } 5422 if (link) { 5423 /* Perform a reset if the media type changed. */ 5424 if (hw->dev_spec._82575.media_changed) { 5425 hw->dev_spec._82575.media_changed = false; 5426 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5427 igb_reset(adapter); 5428 } 5429 /* Cancel scheduled suspend requests. */ 5430 pm_runtime_resume(netdev->dev.parent); 5431 5432 if (!netif_carrier_ok(netdev)) { 5433 u32 ctrl; 5434 5435 hw->mac.ops.get_speed_and_duplex(hw, 5436 &adapter->link_speed, 5437 &adapter->link_duplex); 5438 5439 ctrl = rd32(E1000_CTRL); 5440 /* Links status message must follow this format */ 5441 netdev_info(netdev, 5442 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5443 netdev->name, 5444 adapter->link_speed, 5445 adapter->link_duplex == FULL_DUPLEX ? 5446 "Full" : "Half", 5447 (ctrl & E1000_CTRL_TFCE) && 5448 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5449 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5450 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5451 5452 /* disable EEE if enabled */ 5453 if ((adapter->flags & IGB_FLAG_EEE) && 5454 (adapter->link_duplex == HALF_DUPLEX)) { 5455 dev_info(&adapter->pdev->dev, 5456 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5457 adapter->hw.dev_spec._82575.eee_disable = true; 5458 adapter->flags &= ~IGB_FLAG_EEE; 5459 } 5460 5461 /* check if SmartSpeed worked */ 5462 igb_check_downshift(hw); 5463 if (phy->speed_downgraded) 5464 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5465 5466 /* check for thermal sensor event */ 5467 if (igb_thermal_sensor_event(hw, 5468 E1000_THSTAT_LINK_THROTTLE)) 5469 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5470 5471 /* adjust timeout factor according to speed/duplex */ 5472 adapter->tx_timeout_factor = 1; 5473 switch (adapter->link_speed) { 5474 case SPEED_10: 5475 adapter->tx_timeout_factor = 14; 5476 break; 5477 case SPEED_100: 5478 /* maybe add some timeout factor ? */ 5479 break; 5480 } 5481 5482 if (adapter->link_speed != SPEED_1000) 5483 goto no_wait; 5484 5485 /* wait for Remote receiver status OK */ 5486 retry_read_status: 5487 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5488 &phy_data)) { 5489 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5490 retry_count) { 5491 msleep(100); 5492 retry_count--; 5493 goto retry_read_status; 5494 } else if (!retry_count) { 5495 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5496 } 5497 } else { 5498 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5499 } 5500 no_wait: 5501 netif_carrier_on(netdev); 5502 5503 igb_ping_all_vfs(adapter); 5504 igb_check_vf_rate_limit(adapter); 5505 5506 /* link state has changed, schedule phy info update */ 5507 if (!test_bit(__IGB_DOWN, &adapter->state)) 5508 mod_timer(&adapter->phy_info_timer, 5509 round_jiffies(jiffies + 2 * HZ)); 5510 } 5511 } else { 5512 if (netif_carrier_ok(netdev)) { 5513 adapter->link_speed = 0; 5514 adapter->link_duplex = 0; 5515 5516 /* check for thermal sensor event */ 5517 if (igb_thermal_sensor_event(hw, 5518 E1000_THSTAT_PWR_DOWN)) { 5519 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5520 } 5521 5522 /* Links status message must follow this format */ 5523 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5524 netdev->name); 5525 netif_carrier_off(netdev); 5526 5527 igb_ping_all_vfs(adapter); 5528 5529 /* link state has changed, schedule phy info update */ 5530 if (!test_bit(__IGB_DOWN, &adapter->state)) 5531 mod_timer(&adapter->phy_info_timer, 5532 round_jiffies(jiffies + 2 * HZ)); 5533 5534 /* link is down, time to check for alternate media */ 5535 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5536 igb_check_swap_media(adapter); 5537 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5538 schedule_work(&adapter->reset_task); 5539 /* return immediately */ 5540 return; 5541 } 5542 } 5543 pm_schedule_suspend(netdev->dev.parent, 5544 MSEC_PER_SEC * 5); 5545 5546 /* also check for alternate media here */ 5547 } else if (!netif_carrier_ok(netdev) && 5548 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5549 igb_check_swap_media(adapter); 5550 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5551 schedule_work(&adapter->reset_task); 5552 /* return immediately */ 5553 return; 5554 } 5555 } 5556 } 5557 5558 spin_lock(&adapter->stats64_lock); 5559 igb_update_stats(adapter); 5560 spin_unlock(&adapter->stats64_lock); 5561 5562 for (i = 0; i < adapter->num_tx_queues; i++) { 5563 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5564 if (!netif_carrier_ok(netdev)) { 5565 /* We've lost link, so the controller stops DMA, 5566 * but we've got queued Tx work that's never going 5567 * to get done, so reset controller to flush Tx. 5568 * (Do the reset outside of interrupt context). 5569 */ 5570 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5571 adapter->tx_timeout_count++; 5572 schedule_work(&adapter->reset_task); 5573 /* return immediately since reset is imminent */ 5574 return; 5575 } 5576 } 5577 5578 /* Force detection of hung controller every watchdog period */ 5579 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5580 } 5581 5582 /* Cause software interrupt to ensure Rx ring is cleaned */ 5583 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5584 u32 eics = 0; 5585 5586 for (i = 0; i < adapter->num_q_vectors; i++) 5587 eics |= adapter->q_vector[i]->eims_value; 5588 wr32(E1000_EICS, eics); 5589 } else { 5590 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5591 } 5592 5593 igb_spoof_check(adapter); 5594 igb_ptp_rx_hang(adapter); 5595 igb_ptp_tx_hang(adapter); 5596 5597 /* Check LVMMC register on i350/i354 only */ 5598 if ((adapter->hw.mac.type == e1000_i350) || 5599 (adapter->hw.mac.type == e1000_i354)) 5600 igb_check_lvmmc(adapter); 5601 5602 /* Reset the timer */ 5603 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5604 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5605 mod_timer(&adapter->watchdog_timer, 5606 round_jiffies(jiffies + HZ)); 5607 else 5608 mod_timer(&adapter->watchdog_timer, 5609 round_jiffies(jiffies + 2 * HZ)); 5610 } 5611 } 5612 5613 enum latency_range { 5614 lowest_latency = 0, 5615 low_latency = 1, 5616 bulk_latency = 2, 5617 latency_invalid = 255 5618 }; 5619 5620 /** 5621 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5622 * @q_vector: pointer to q_vector 5623 * 5624 * Stores a new ITR value based on strictly on packet size. This 5625 * algorithm is less sophisticated than that used in igb_update_itr, 5626 * due to the difficulty of synchronizing statistics across multiple 5627 * receive rings. The divisors and thresholds used by this function 5628 * were determined based on theoretical maximum wire speed and testing 5629 * data, in order to minimize response time while increasing bulk 5630 * throughput. 5631 * This functionality is controlled by ethtool's coalescing settings. 5632 * NOTE: This function is called only when operating in a multiqueue 5633 * receive environment. 5634 **/ 5635 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5636 { 5637 int new_val = q_vector->itr_val; 5638 int avg_wire_size = 0; 5639 struct igb_adapter *adapter = q_vector->adapter; 5640 unsigned int packets; 5641 5642 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5643 * ints/sec - ITR timer value of 120 ticks. 5644 */ 5645 if (adapter->link_speed != SPEED_1000) { 5646 new_val = IGB_4K_ITR; 5647 goto set_itr_val; 5648 } 5649 5650 packets = q_vector->rx.total_packets; 5651 if (packets) 5652 avg_wire_size = q_vector->rx.total_bytes / packets; 5653 5654 packets = q_vector->tx.total_packets; 5655 if (packets) 5656 avg_wire_size = max_t(u32, avg_wire_size, 5657 q_vector->tx.total_bytes / packets); 5658 5659 /* if avg_wire_size isn't set no work was done */ 5660 if (!avg_wire_size) 5661 goto clear_counts; 5662 5663 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5664 avg_wire_size += 24; 5665 5666 /* Don't starve jumbo frames */ 5667 avg_wire_size = min(avg_wire_size, 3000); 5668 5669 /* Give a little boost to mid-size frames */ 5670 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5671 new_val = avg_wire_size / 3; 5672 else 5673 new_val = avg_wire_size / 2; 5674 5675 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5676 if (new_val < IGB_20K_ITR && 5677 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5678 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5679 new_val = IGB_20K_ITR; 5680 5681 set_itr_val: 5682 if (new_val != q_vector->itr_val) { 5683 q_vector->itr_val = new_val; 5684 q_vector->set_itr = 1; 5685 } 5686 clear_counts: 5687 q_vector->rx.total_bytes = 0; 5688 q_vector->rx.total_packets = 0; 5689 q_vector->tx.total_bytes = 0; 5690 q_vector->tx.total_packets = 0; 5691 } 5692 5693 /** 5694 * igb_update_itr - update the dynamic ITR value based on statistics 5695 * @q_vector: pointer to q_vector 5696 * @ring_container: ring info to update the itr for 5697 * 5698 * Stores a new ITR value based on packets and byte 5699 * counts during the last interrupt. The advantage of per interrupt 5700 * computation is faster updates and more accurate ITR for the current 5701 * traffic pattern. Constants in this function were computed 5702 * based on theoretical maximum wire speed and thresholds were set based 5703 * on testing data as well as attempting to minimize response time 5704 * while increasing bulk throughput. 5705 * This functionality is controlled by ethtool's coalescing settings. 5706 * NOTE: These calculations are only valid when operating in a single- 5707 * queue environment. 5708 **/ 5709 static void igb_update_itr(struct igb_q_vector *q_vector, 5710 struct igb_ring_container *ring_container) 5711 { 5712 unsigned int packets = ring_container->total_packets; 5713 unsigned int bytes = ring_container->total_bytes; 5714 u8 itrval = ring_container->itr; 5715 5716 /* no packets, exit with status unchanged */ 5717 if (packets == 0) 5718 return; 5719 5720 switch (itrval) { 5721 case lowest_latency: 5722 /* handle TSO and jumbo frames */ 5723 if (bytes/packets > 8000) 5724 itrval = bulk_latency; 5725 else if ((packets < 5) && (bytes > 512)) 5726 itrval = low_latency; 5727 break; 5728 case low_latency: /* 50 usec aka 20000 ints/s */ 5729 if (bytes > 10000) { 5730 /* this if handles the TSO accounting */ 5731 if (bytes/packets > 8000) 5732 itrval = bulk_latency; 5733 else if ((packets < 10) || ((bytes/packets) > 1200)) 5734 itrval = bulk_latency; 5735 else if ((packets > 35)) 5736 itrval = lowest_latency; 5737 } else if (bytes/packets > 2000) { 5738 itrval = bulk_latency; 5739 } else if (packets <= 2 && bytes < 512) { 5740 itrval = lowest_latency; 5741 } 5742 break; 5743 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5744 if (bytes > 25000) { 5745 if (packets > 35) 5746 itrval = low_latency; 5747 } else if (bytes < 1500) { 5748 itrval = low_latency; 5749 } 5750 break; 5751 } 5752 5753 /* clear work counters since we have the values we need */ 5754 ring_container->total_bytes = 0; 5755 ring_container->total_packets = 0; 5756 5757 /* write updated itr to ring container */ 5758 ring_container->itr = itrval; 5759 } 5760 5761 static void igb_set_itr(struct igb_q_vector *q_vector) 5762 { 5763 struct igb_adapter *adapter = q_vector->adapter; 5764 u32 new_itr = q_vector->itr_val; 5765 u8 current_itr = 0; 5766 5767 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5768 if (adapter->link_speed != SPEED_1000) { 5769 current_itr = 0; 5770 new_itr = IGB_4K_ITR; 5771 goto set_itr_now; 5772 } 5773 5774 igb_update_itr(q_vector, &q_vector->tx); 5775 igb_update_itr(q_vector, &q_vector->rx); 5776 5777 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5778 5779 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5780 if (current_itr == lowest_latency && 5781 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5782 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5783 current_itr = low_latency; 5784 5785 switch (current_itr) { 5786 /* counts and packets in update_itr are dependent on these numbers */ 5787 case lowest_latency: 5788 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5789 break; 5790 case low_latency: 5791 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5792 break; 5793 case bulk_latency: 5794 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5795 break; 5796 default: 5797 break; 5798 } 5799 5800 set_itr_now: 5801 if (new_itr != q_vector->itr_val) { 5802 /* this attempts to bias the interrupt rate towards Bulk 5803 * by adding intermediate steps when interrupt rate is 5804 * increasing 5805 */ 5806 new_itr = new_itr > q_vector->itr_val ? 5807 max((new_itr * q_vector->itr_val) / 5808 (new_itr + (q_vector->itr_val >> 2)), 5809 new_itr) : new_itr; 5810 /* Don't write the value here; it resets the adapter's 5811 * internal timer, and causes us to delay far longer than 5812 * we should between interrupts. Instead, we write the ITR 5813 * value at the beginning of the next interrupt so the timing 5814 * ends up being correct. 5815 */ 5816 q_vector->itr_val = new_itr; 5817 q_vector->set_itr = 1; 5818 } 5819 } 5820 5821 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5822 struct igb_tx_buffer *first, 5823 u32 vlan_macip_lens, u32 type_tucmd, 5824 u32 mss_l4len_idx) 5825 { 5826 struct e1000_adv_tx_context_desc *context_desc; 5827 u16 i = tx_ring->next_to_use; 5828 struct timespec64 ts; 5829 5830 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5831 5832 i++; 5833 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5834 5835 /* set bits to identify this as an advanced context descriptor */ 5836 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5837 5838 /* For 82575, context index must be unique per ring. */ 5839 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5840 mss_l4len_idx |= tx_ring->reg_idx << 4; 5841 5842 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5843 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5844 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5845 5846 /* We assume there is always a valid tx time available. Invalid times 5847 * should have been handled by the upper layers. 5848 */ 5849 if (tx_ring->launchtime_enable) { 5850 ts = ktime_to_timespec64(first->skb->tstamp); 5851 first->skb->tstamp = ktime_set(0, 0); 5852 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5853 } else { 5854 context_desc->seqnum_seed = 0; 5855 } 5856 } 5857 5858 static int igb_tso(struct igb_ring *tx_ring, 5859 struct igb_tx_buffer *first, 5860 u8 *hdr_len) 5861 { 5862 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5863 struct sk_buff *skb = first->skb; 5864 union { 5865 struct iphdr *v4; 5866 struct ipv6hdr *v6; 5867 unsigned char *hdr; 5868 } ip; 5869 union { 5870 struct tcphdr *tcp; 5871 struct udphdr *udp; 5872 unsigned char *hdr; 5873 } l4; 5874 u32 paylen, l4_offset; 5875 int err; 5876 5877 if (skb->ip_summed != CHECKSUM_PARTIAL) 5878 return 0; 5879 5880 if (!skb_is_gso(skb)) 5881 return 0; 5882 5883 err = skb_cow_head(skb, 0); 5884 if (err < 0) 5885 return err; 5886 5887 ip.hdr = skb_network_header(skb); 5888 l4.hdr = skb_checksum_start(skb); 5889 5890 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5891 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5892 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5893 5894 /* initialize outer IP header fields */ 5895 if (ip.v4->version == 4) { 5896 unsigned char *csum_start = skb_checksum_start(skb); 5897 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5898 5899 /* IP header will have to cancel out any data that 5900 * is not a part of the outer IP header 5901 */ 5902 ip.v4->check = csum_fold(csum_partial(trans_start, 5903 csum_start - trans_start, 5904 0)); 5905 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5906 5907 ip.v4->tot_len = 0; 5908 first->tx_flags |= IGB_TX_FLAGS_TSO | 5909 IGB_TX_FLAGS_CSUM | 5910 IGB_TX_FLAGS_IPV4; 5911 } else { 5912 ip.v6->payload_len = 0; 5913 first->tx_flags |= IGB_TX_FLAGS_TSO | 5914 IGB_TX_FLAGS_CSUM; 5915 } 5916 5917 /* determine offset of inner transport header */ 5918 l4_offset = l4.hdr - skb->data; 5919 5920 /* remove payload length from inner checksum */ 5921 paylen = skb->len - l4_offset; 5922 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5923 /* compute length of segmentation header */ 5924 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5925 csum_replace_by_diff(&l4.tcp->check, 5926 (__force __wsum)htonl(paylen)); 5927 } else { 5928 /* compute length of segmentation header */ 5929 *hdr_len = sizeof(*l4.udp) + l4_offset; 5930 csum_replace_by_diff(&l4.udp->check, 5931 (__force __wsum)htonl(paylen)); 5932 } 5933 5934 /* update gso size and bytecount with header size */ 5935 first->gso_segs = skb_shinfo(skb)->gso_segs; 5936 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5937 5938 /* MSS L4LEN IDX */ 5939 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5940 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5941 5942 /* VLAN MACLEN IPLEN */ 5943 vlan_macip_lens = l4.hdr - ip.hdr; 5944 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5945 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5946 5947 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5948 type_tucmd, mss_l4len_idx); 5949 5950 return 1; 5951 } 5952 5953 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5954 { 5955 unsigned int offset = 0; 5956 5957 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5958 5959 return offset == skb_checksum_start_offset(skb); 5960 } 5961 5962 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5963 { 5964 struct sk_buff *skb = first->skb; 5965 u32 vlan_macip_lens = 0; 5966 u32 type_tucmd = 0; 5967 5968 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5969 csum_failed: 5970 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5971 !tx_ring->launchtime_enable) 5972 return; 5973 goto no_csum; 5974 } 5975 5976 switch (skb->csum_offset) { 5977 case offsetof(struct tcphdr, check): 5978 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5979 fallthrough; 5980 case offsetof(struct udphdr, check): 5981 break; 5982 case offsetof(struct sctphdr, checksum): 5983 /* validate that this is actually an SCTP request */ 5984 if (((first->protocol == htons(ETH_P_IP)) && 5985 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5986 ((first->protocol == htons(ETH_P_IPV6)) && 5987 igb_ipv6_csum_is_sctp(skb))) { 5988 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5989 break; 5990 } 5991 fallthrough; 5992 default: 5993 skb_checksum_help(skb); 5994 goto csum_failed; 5995 } 5996 5997 /* update TX checksum flag */ 5998 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5999 vlan_macip_lens = skb_checksum_start_offset(skb) - 6000 skb_network_offset(skb); 6001 no_csum: 6002 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6003 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6004 6005 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6006 } 6007 6008 #define IGB_SET_FLAG(_input, _flag, _result) \ 6009 ((_flag <= _result) ? \ 6010 ((u32)(_input & _flag) * (_result / _flag)) : \ 6011 ((u32)(_input & _flag) / (_flag / _result))) 6012 6013 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6014 { 6015 /* set type for advanced descriptor with frame checksum insertion */ 6016 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6017 E1000_ADVTXD_DCMD_DEXT | 6018 E1000_ADVTXD_DCMD_IFCS; 6019 6020 /* set HW vlan bit if vlan is present */ 6021 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6022 (E1000_ADVTXD_DCMD_VLE)); 6023 6024 /* set segmentation bits for TSO */ 6025 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6026 (E1000_ADVTXD_DCMD_TSE)); 6027 6028 /* set timestamp bit if present */ 6029 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6030 (E1000_ADVTXD_MAC_TSTAMP)); 6031 6032 /* insert frame checksum */ 6033 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6034 6035 return cmd_type; 6036 } 6037 6038 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6039 union e1000_adv_tx_desc *tx_desc, 6040 u32 tx_flags, unsigned int paylen) 6041 { 6042 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6043 6044 /* 82575 requires a unique index per ring */ 6045 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6046 olinfo_status |= tx_ring->reg_idx << 4; 6047 6048 /* insert L4 checksum */ 6049 olinfo_status |= IGB_SET_FLAG(tx_flags, 6050 IGB_TX_FLAGS_CSUM, 6051 (E1000_TXD_POPTS_TXSM << 8)); 6052 6053 /* insert IPv4 checksum */ 6054 olinfo_status |= IGB_SET_FLAG(tx_flags, 6055 IGB_TX_FLAGS_IPV4, 6056 (E1000_TXD_POPTS_IXSM << 8)); 6057 6058 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6059 } 6060 6061 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6062 { 6063 struct net_device *netdev = tx_ring->netdev; 6064 6065 netif_stop_subqueue(netdev, tx_ring->queue_index); 6066 6067 /* Herbert's original patch had: 6068 * smp_mb__after_netif_stop_queue(); 6069 * but since that doesn't exist yet, just open code it. 6070 */ 6071 smp_mb(); 6072 6073 /* We need to check again in a case another CPU has just 6074 * made room available. 6075 */ 6076 if (igb_desc_unused(tx_ring) < size) 6077 return -EBUSY; 6078 6079 /* A reprieve! */ 6080 netif_wake_subqueue(netdev, tx_ring->queue_index); 6081 6082 u64_stats_update_begin(&tx_ring->tx_syncp2); 6083 tx_ring->tx_stats.restart_queue2++; 6084 u64_stats_update_end(&tx_ring->tx_syncp2); 6085 6086 return 0; 6087 } 6088 6089 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6090 { 6091 if (igb_desc_unused(tx_ring) >= size) 6092 return 0; 6093 return __igb_maybe_stop_tx(tx_ring, size); 6094 } 6095 6096 static int igb_tx_map(struct igb_ring *tx_ring, 6097 struct igb_tx_buffer *first, 6098 const u8 hdr_len) 6099 { 6100 struct sk_buff *skb = first->skb; 6101 struct igb_tx_buffer *tx_buffer; 6102 union e1000_adv_tx_desc *tx_desc; 6103 skb_frag_t *frag; 6104 dma_addr_t dma; 6105 unsigned int data_len, size; 6106 u32 tx_flags = first->tx_flags; 6107 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6108 u16 i = tx_ring->next_to_use; 6109 6110 tx_desc = IGB_TX_DESC(tx_ring, i); 6111 6112 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6113 6114 size = skb_headlen(skb); 6115 data_len = skb->data_len; 6116 6117 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6118 6119 tx_buffer = first; 6120 6121 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6122 if (dma_mapping_error(tx_ring->dev, dma)) 6123 goto dma_error; 6124 6125 /* record length, and DMA address */ 6126 dma_unmap_len_set(tx_buffer, len, size); 6127 dma_unmap_addr_set(tx_buffer, dma, dma); 6128 6129 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6130 6131 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6132 tx_desc->read.cmd_type_len = 6133 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6134 6135 i++; 6136 tx_desc++; 6137 if (i == tx_ring->count) { 6138 tx_desc = IGB_TX_DESC(tx_ring, 0); 6139 i = 0; 6140 } 6141 tx_desc->read.olinfo_status = 0; 6142 6143 dma += IGB_MAX_DATA_PER_TXD; 6144 size -= IGB_MAX_DATA_PER_TXD; 6145 6146 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6147 } 6148 6149 if (likely(!data_len)) 6150 break; 6151 6152 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6153 6154 i++; 6155 tx_desc++; 6156 if (i == tx_ring->count) { 6157 tx_desc = IGB_TX_DESC(tx_ring, 0); 6158 i = 0; 6159 } 6160 tx_desc->read.olinfo_status = 0; 6161 6162 size = skb_frag_size(frag); 6163 data_len -= size; 6164 6165 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6166 size, DMA_TO_DEVICE); 6167 6168 tx_buffer = &tx_ring->tx_buffer_info[i]; 6169 } 6170 6171 /* write last descriptor with RS and EOP bits */ 6172 cmd_type |= size | IGB_TXD_DCMD; 6173 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6174 6175 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6176 6177 /* set the timestamp */ 6178 first->time_stamp = jiffies; 6179 6180 skb_tx_timestamp(skb); 6181 6182 /* Force memory writes to complete before letting h/w know there 6183 * are new descriptors to fetch. (Only applicable for weak-ordered 6184 * memory model archs, such as IA-64). 6185 * 6186 * We also need this memory barrier to make certain all of the 6187 * status bits have been updated before next_to_watch is written. 6188 */ 6189 dma_wmb(); 6190 6191 /* set next_to_watch value indicating a packet is present */ 6192 first->next_to_watch = tx_desc; 6193 6194 i++; 6195 if (i == tx_ring->count) 6196 i = 0; 6197 6198 tx_ring->next_to_use = i; 6199 6200 /* Make sure there is space in the ring for the next send. */ 6201 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6202 6203 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6204 writel(i, tx_ring->tail); 6205 } 6206 return 0; 6207 6208 dma_error: 6209 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6210 tx_buffer = &tx_ring->tx_buffer_info[i]; 6211 6212 /* clear dma mappings for failed tx_buffer_info map */ 6213 while (tx_buffer != first) { 6214 if (dma_unmap_len(tx_buffer, len)) 6215 dma_unmap_page(tx_ring->dev, 6216 dma_unmap_addr(tx_buffer, dma), 6217 dma_unmap_len(tx_buffer, len), 6218 DMA_TO_DEVICE); 6219 dma_unmap_len_set(tx_buffer, len, 0); 6220 6221 if (i-- == 0) 6222 i += tx_ring->count; 6223 tx_buffer = &tx_ring->tx_buffer_info[i]; 6224 } 6225 6226 if (dma_unmap_len(tx_buffer, len)) 6227 dma_unmap_single(tx_ring->dev, 6228 dma_unmap_addr(tx_buffer, dma), 6229 dma_unmap_len(tx_buffer, len), 6230 DMA_TO_DEVICE); 6231 dma_unmap_len_set(tx_buffer, len, 0); 6232 6233 dev_kfree_skb_any(tx_buffer->skb); 6234 tx_buffer->skb = NULL; 6235 6236 tx_ring->next_to_use = i; 6237 6238 return -1; 6239 } 6240 6241 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6242 struct igb_ring *tx_ring, 6243 struct xdp_frame *xdpf) 6244 { 6245 union e1000_adv_tx_desc *tx_desc; 6246 u32 len, cmd_type, olinfo_status; 6247 struct igb_tx_buffer *tx_buffer; 6248 dma_addr_t dma; 6249 u16 i; 6250 6251 len = xdpf->len; 6252 6253 if (unlikely(!igb_desc_unused(tx_ring))) 6254 return IGB_XDP_CONSUMED; 6255 6256 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE); 6257 if (dma_mapping_error(tx_ring->dev, dma)) 6258 return IGB_XDP_CONSUMED; 6259 6260 /* record the location of the first descriptor for this packet */ 6261 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6262 tx_buffer->bytecount = len; 6263 tx_buffer->gso_segs = 1; 6264 tx_buffer->protocol = 0; 6265 6266 i = tx_ring->next_to_use; 6267 tx_desc = IGB_TX_DESC(tx_ring, i); 6268 6269 dma_unmap_len_set(tx_buffer, len, len); 6270 dma_unmap_addr_set(tx_buffer, dma, dma); 6271 tx_buffer->type = IGB_TYPE_XDP; 6272 tx_buffer->xdpf = xdpf; 6273 6274 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6275 6276 /* put descriptor type bits */ 6277 cmd_type = E1000_ADVTXD_DTYP_DATA | 6278 E1000_ADVTXD_DCMD_DEXT | 6279 E1000_ADVTXD_DCMD_IFCS; 6280 cmd_type |= len | IGB_TXD_DCMD; 6281 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6282 6283 olinfo_status = cpu_to_le32(len << E1000_ADVTXD_PAYLEN_SHIFT); 6284 /* 82575 requires a unique index per ring */ 6285 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6286 olinfo_status |= tx_ring->reg_idx << 4; 6287 6288 tx_desc->read.olinfo_status = olinfo_status; 6289 6290 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount); 6291 6292 /* set the timestamp */ 6293 tx_buffer->time_stamp = jiffies; 6294 6295 /* Avoid any potential race with xdp_xmit and cleanup */ 6296 smp_wmb(); 6297 6298 /* set next_to_watch value indicating a packet is present */ 6299 i++; 6300 if (i == tx_ring->count) 6301 i = 0; 6302 6303 tx_buffer->next_to_watch = tx_desc; 6304 tx_ring->next_to_use = i; 6305 6306 /* Make sure there is space in the ring for the next send. */ 6307 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6308 6309 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6310 writel(i, tx_ring->tail); 6311 6312 return IGB_XDP_TX; 6313 } 6314 6315 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6316 struct igb_ring *tx_ring) 6317 { 6318 struct igb_tx_buffer *first; 6319 int tso; 6320 u32 tx_flags = 0; 6321 unsigned short f; 6322 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6323 __be16 protocol = vlan_get_protocol(skb); 6324 u8 hdr_len = 0; 6325 6326 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6327 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6328 * + 2 desc gap to keep tail from touching head, 6329 * + 1 desc for context descriptor, 6330 * otherwise try next time 6331 */ 6332 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6333 count += TXD_USE_COUNT(skb_frag_size( 6334 &skb_shinfo(skb)->frags[f])); 6335 6336 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6337 /* this is a hard error */ 6338 return NETDEV_TX_BUSY; 6339 } 6340 6341 /* record the location of the first descriptor for this packet */ 6342 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6343 first->type = IGB_TYPE_SKB; 6344 first->skb = skb; 6345 first->bytecount = skb->len; 6346 first->gso_segs = 1; 6347 6348 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6349 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6350 6351 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6352 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6353 &adapter->state)) { 6354 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6355 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6356 6357 adapter->ptp_tx_skb = skb_get(skb); 6358 adapter->ptp_tx_start = jiffies; 6359 if (adapter->hw.mac.type == e1000_82576) 6360 schedule_work(&adapter->ptp_tx_work); 6361 } else { 6362 adapter->tx_hwtstamp_skipped++; 6363 } 6364 } 6365 6366 if (skb_vlan_tag_present(skb)) { 6367 tx_flags |= IGB_TX_FLAGS_VLAN; 6368 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6369 } 6370 6371 /* record initial flags and protocol */ 6372 first->tx_flags = tx_flags; 6373 first->protocol = protocol; 6374 6375 tso = igb_tso(tx_ring, first, &hdr_len); 6376 if (tso < 0) 6377 goto out_drop; 6378 else if (!tso) 6379 igb_tx_csum(tx_ring, first); 6380 6381 if (igb_tx_map(tx_ring, first, hdr_len)) 6382 goto cleanup_tx_tstamp; 6383 6384 return NETDEV_TX_OK; 6385 6386 out_drop: 6387 dev_kfree_skb_any(first->skb); 6388 first->skb = NULL; 6389 cleanup_tx_tstamp: 6390 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6391 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6392 6393 dev_kfree_skb_any(adapter->ptp_tx_skb); 6394 adapter->ptp_tx_skb = NULL; 6395 if (adapter->hw.mac.type == e1000_82576) 6396 cancel_work_sync(&adapter->ptp_tx_work); 6397 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6398 } 6399 6400 return NETDEV_TX_OK; 6401 } 6402 6403 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6404 struct sk_buff *skb) 6405 { 6406 unsigned int r_idx = skb->queue_mapping; 6407 6408 if (r_idx >= adapter->num_tx_queues) 6409 r_idx = r_idx % adapter->num_tx_queues; 6410 6411 return adapter->tx_ring[r_idx]; 6412 } 6413 6414 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6415 struct net_device *netdev) 6416 { 6417 struct igb_adapter *adapter = netdev_priv(netdev); 6418 6419 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6420 * in order to meet this minimum size requirement. 6421 */ 6422 if (skb_put_padto(skb, 17)) 6423 return NETDEV_TX_OK; 6424 6425 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6426 } 6427 6428 /** 6429 * igb_tx_timeout - Respond to a Tx Hang 6430 * @netdev: network interface device structure 6431 * @txqueue: number of the Tx queue that hung (unused) 6432 **/ 6433 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6434 { 6435 struct igb_adapter *adapter = netdev_priv(netdev); 6436 struct e1000_hw *hw = &adapter->hw; 6437 6438 /* Do the reset outside of interrupt context */ 6439 adapter->tx_timeout_count++; 6440 6441 if (hw->mac.type >= e1000_82580) 6442 hw->dev_spec._82575.global_device_reset = true; 6443 6444 schedule_work(&adapter->reset_task); 6445 wr32(E1000_EICS, 6446 (adapter->eims_enable_mask & ~adapter->eims_other)); 6447 } 6448 6449 static void igb_reset_task(struct work_struct *work) 6450 { 6451 struct igb_adapter *adapter; 6452 adapter = container_of(work, struct igb_adapter, reset_task); 6453 6454 rtnl_lock(); 6455 /* If we're already down or resetting, just bail */ 6456 if (test_bit(__IGB_DOWN, &adapter->state) || 6457 test_bit(__IGB_RESETTING, &adapter->state)) { 6458 rtnl_unlock(); 6459 return; 6460 } 6461 6462 igb_dump(adapter); 6463 netdev_err(adapter->netdev, "Reset adapter\n"); 6464 igb_reinit_locked(adapter); 6465 rtnl_unlock(); 6466 } 6467 6468 /** 6469 * igb_get_stats64 - Get System Network Statistics 6470 * @netdev: network interface device structure 6471 * @stats: rtnl_link_stats64 pointer 6472 **/ 6473 static void igb_get_stats64(struct net_device *netdev, 6474 struct rtnl_link_stats64 *stats) 6475 { 6476 struct igb_adapter *adapter = netdev_priv(netdev); 6477 6478 spin_lock(&adapter->stats64_lock); 6479 igb_update_stats(adapter); 6480 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6481 spin_unlock(&adapter->stats64_lock); 6482 } 6483 6484 /** 6485 * igb_change_mtu - Change the Maximum Transfer Unit 6486 * @netdev: network interface device structure 6487 * @new_mtu: new value for maximum frame size 6488 * 6489 * Returns 0 on success, negative on failure 6490 **/ 6491 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6492 { 6493 struct igb_adapter *adapter = netdev_priv(netdev); 6494 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6495 6496 if (adapter->xdp_prog) { 6497 int i; 6498 6499 for (i = 0; i < adapter->num_rx_queues; i++) { 6500 struct igb_ring *ring = adapter->rx_ring[i]; 6501 6502 if (max_frame > igb_rx_bufsz(ring)) { 6503 netdev_warn(adapter->netdev, "Requested MTU size is not supported with XDP\n"); 6504 return -EINVAL; 6505 } 6506 } 6507 } 6508 6509 /* adjust max frame to be at least the size of a standard frame */ 6510 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6511 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6512 6513 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6514 usleep_range(1000, 2000); 6515 6516 /* igb_down has a dependency on max_frame_size */ 6517 adapter->max_frame_size = max_frame; 6518 6519 if (netif_running(netdev)) 6520 igb_down(adapter); 6521 6522 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6523 netdev->mtu, new_mtu); 6524 netdev->mtu = new_mtu; 6525 6526 if (netif_running(netdev)) 6527 igb_up(adapter); 6528 else 6529 igb_reset(adapter); 6530 6531 clear_bit(__IGB_RESETTING, &adapter->state); 6532 6533 return 0; 6534 } 6535 6536 /** 6537 * igb_update_stats - Update the board statistics counters 6538 * @adapter: board private structure 6539 **/ 6540 void igb_update_stats(struct igb_adapter *adapter) 6541 { 6542 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6543 struct e1000_hw *hw = &adapter->hw; 6544 struct pci_dev *pdev = adapter->pdev; 6545 u32 reg, mpc; 6546 int i; 6547 u64 bytes, packets; 6548 unsigned int start; 6549 u64 _bytes, _packets; 6550 6551 /* Prevent stats update while adapter is being reset, or if the pci 6552 * connection is down. 6553 */ 6554 if (adapter->link_speed == 0) 6555 return; 6556 if (pci_channel_offline(pdev)) 6557 return; 6558 6559 bytes = 0; 6560 packets = 0; 6561 6562 rcu_read_lock(); 6563 for (i = 0; i < adapter->num_rx_queues; i++) { 6564 struct igb_ring *ring = adapter->rx_ring[i]; 6565 u32 rqdpc = rd32(E1000_RQDPC(i)); 6566 if (hw->mac.type >= e1000_i210) 6567 wr32(E1000_RQDPC(i), 0); 6568 6569 if (rqdpc) { 6570 ring->rx_stats.drops += rqdpc; 6571 net_stats->rx_fifo_errors += rqdpc; 6572 } 6573 6574 do { 6575 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6576 _bytes = ring->rx_stats.bytes; 6577 _packets = ring->rx_stats.packets; 6578 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6579 bytes += _bytes; 6580 packets += _packets; 6581 } 6582 6583 net_stats->rx_bytes = bytes; 6584 net_stats->rx_packets = packets; 6585 6586 bytes = 0; 6587 packets = 0; 6588 for (i = 0; i < adapter->num_tx_queues; i++) { 6589 struct igb_ring *ring = adapter->tx_ring[i]; 6590 do { 6591 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6592 _bytes = ring->tx_stats.bytes; 6593 _packets = ring->tx_stats.packets; 6594 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6595 bytes += _bytes; 6596 packets += _packets; 6597 } 6598 net_stats->tx_bytes = bytes; 6599 net_stats->tx_packets = packets; 6600 rcu_read_unlock(); 6601 6602 /* read stats registers */ 6603 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6604 adapter->stats.gprc += rd32(E1000_GPRC); 6605 adapter->stats.gorc += rd32(E1000_GORCL); 6606 rd32(E1000_GORCH); /* clear GORCL */ 6607 adapter->stats.bprc += rd32(E1000_BPRC); 6608 adapter->stats.mprc += rd32(E1000_MPRC); 6609 adapter->stats.roc += rd32(E1000_ROC); 6610 6611 adapter->stats.prc64 += rd32(E1000_PRC64); 6612 adapter->stats.prc127 += rd32(E1000_PRC127); 6613 adapter->stats.prc255 += rd32(E1000_PRC255); 6614 adapter->stats.prc511 += rd32(E1000_PRC511); 6615 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6616 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6617 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6618 adapter->stats.sec += rd32(E1000_SEC); 6619 6620 mpc = rd32(E1000_MPC); 6621 adapter->stats.mpc += mpc; 6622 net_stats->rx_fifo_errors += mpc; 6623 adapter->stats.scc += rd32(E1000_SCC); 6624 adapter->stats.ecol += rd32(E1000_ECOL); 6625 adapter->stats.mcc += rd32(E1000_MCC); 6626 adapter->stats.latecol += rd32(E1000_LATECOL); 6627 adapter->stats.dc += rd32(E1000_DC); 6628 adapter->stats.rlec += rd32(E1000_RLEC); 6629 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6630 adapter->stats.xontxc += rd32(E1000_XONTXC); 6631 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6632 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6633 adapter->stats.fcruc += rd32(E1000_FCRUC); 6634 adapter->stats.gptc += rd32(E1000_GPTC); 6635 adapter->stats.gotc += rd32(E1000_GOTCL); 6636 rd32(E1000_GOTCH); /* clear GOTCL */ 6637 adapter->stats.rnbc += rd32(E1000_RNBC); 6638 adapter->stats.ruc += rd32(E1000_RUC); 6639 adapter->stats.rfc += rd32(E1000_RFC); 6640 adapter->stats.rjc += rd32(E1000_RJC); 6641 adapter->stats.tor += rd32(E1000_TORH); 6642 adapter->stats.tot += rd32(E1000_TOTH); 6643 adapter->stats.tpr += rd32(E1000_TPR); 6644 6645 adapter->stats.ptc64 += rd32(E1000_PTC64); 6646 adapter->stats.ptc127 += rd32(E1000_PTC127); 6647 adapter->stats.ptc255 += rd32(E1000_PTC255); 6648 adapter->stats.ptc511 += rd32(E1000_PTC511); 6649 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6650 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6651 6652 adapter->stats.mptc += rd32(E1000_MPTC); 6653 adapter->stats.bptc += rd32(E1000_BPTC); 6654 6655 adapter->stats.tpt += rd32(E1000_TPT); 6656 adapter->stats.colc += rd32(E1000_COLC); 6657 6658 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6659 /* read internal phy specific stats */ 6660 reg = rd32(E1000_CTRL_EXT); 6661 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6662 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6663 6664 /* this stat has invalid values on i210/i211 */ 6665 if ((hw->mac.type != e1000_i210) && 6666 (hw->mac.type != e1000_i211)) 6667 adapter->stats.tncrs += rd32(E1000_TNCRS); 6668 } 6669 6670 adapter->stats.tsctc += rd32(E1000_TSCTC); 6671 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6672 6673 adapter->stats.iac += rd32(E1000_IAC); 6674 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6675 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6676 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6677 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6678 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6679 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6680 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6681 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6682 6683 /* Fill out the OS statistics structure */ 6684 net_stats->multicast = adapter->stats.mprc; 6685 net_stats->collisions = adapter->stats.colc; 6686 6687 /* Rx Errors */ 6688 6689 /* RLEC on some newer hardware can be incorrect so build 6690 * our own version based on RUC and ROC 6691 */ 6692 net_stats->rx_errors = adapter->stats.rxerrc + 6693 adapter->stats.crcerrs + adapter->stats.algnerrc + 6694 adapter->stats.ruc + adapter->stats.roc + 6695 adapter->stats.cexterr; 6696 net_stats->rx_length_errors = adapter->stats.ruc + 6697 adapter->stats.roc; 6698 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6699 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6700 net_stats->rx_missed_errors = adapter->stats.mpc; 6701 6702 /* Tx Errors */ 6703 net_stats->tx_errors = adapter->stats.ecol + 6704 adapter->stats.latecol; 6705 net_stats->tx_aborted_errors = adapter->stats.ecol; 6706 net_stats->tx_window_errors = adapter->stats.latecol; 6707 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6708 6709 /* Tx Dropped needs to be maintained elsewhere */ 6710 6711 /* Management Stats */ 6712 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6713 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6714 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6715 6716 /* OS2BMC Stats */ 6717 reg = rd32(E1000_MANC); 6718 if (reg & E1000_MANC_EN_BMC2OS) { 6719 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6720 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6721 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6722 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6723 } 6724 } 6725 6726 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6727 { 6728 struct e1000_hw *hw = &adapter->hw; 6729 struct ptp_clock_event event; 6730 struct timespec64 ts; 6731 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6732 6733 if (tsicr & TSINTR_SYS_WRAP) { 6734 event.type = PTP_CLOCK_PPS; 6735 if (adapter->ptp_caps.pps) 6736 ptp_clock_event(adapter->ptp_clock, &event); 6737 ack |= TSINTR_SYS_WRAP; 6738 } 6739 6740 if (tsicr & E1000_TSICR_TXTS) { 6741 /* retrieve hardware timestamp */ 6742 schedule_work(&adapter->ptp_tx_work); 6743 ack |= E1000_TSICR_TXTS; 6744 } 6745 6746 if (tsicr & TSINTR_TT0) { 6747 spin_lock(&adapter->tmreg_lock); 6748 ts = timespec64_add(adapter->perout[0].start, 6749 adapter->perout[0].period); 6750 /* u32 conversion of tv_sec is safe until y2106 */ 6751 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6752 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6753 tsauxc = rd32(E1000_TSAUXC); 6754 tsauxc |= TSAUXC_EN_TT0; 6755 wr32(E1000_TSAUXC, tsauxc); 6756 adapter->perout[0].start = ts; 6757 spin_unlock(&adapter->tmreg_lock); 6758 ack |= TSINTR_TT0; 6759 } 6760 6761 if (tsicr & TSINTR_TT1) { 6762 spin_lock(&adapter->tmreg_lock); 6763 ts = timespec64_add(adapter->perout[1].start, 6764 adapter->perout[1].period); 6765 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6766 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6767 tsauxc = rd32(E1000_TSAUXC); 6768 tsauxc |= TSAUXC_EN_TT1; 6769 wr32(E1000_TSAUXC, tsauxc); 6770 adapter->perout[1].start = ts; 6771 spin_unlock(&adapter->tmreg_lock); 6772 ack |= TSINTR_TT1; 6773 } 6774 6775 if (tsicr & TSINTR_AUTT0) { 6776 nsec = rd32(E1000_AUXSTMPL0); 6777 sec = rd32(E1000_AUXSTMPH0); 6778 event.type = PTP_CLOCK_EXTTS; 6779 event.index = 0; 6780 event.timestamp = sec * 1000000000ULL + nsec; 6781 ptp_clock_event(adapter->ptp_clock, &event); 6782 ack |= TSINTR_AUTT0; 6783 } 6784 6785 if (tsicr & TSINTR_AUTT1) { 6786 nsec = rd32(E1000_AUXSTMPL1); 6787 sec = rd32(E1000_AUXSTMPH1); 6788 event.type = PTP_CLOCK_EXTTS; 6789 event.index = 1; 6790 event.timestamp = sec * 1000000000ULL + nsec; 6791 ptp_clock_event(adapter->ptp_clock, &event); 6792 ack |= TSINTR_AUTT1; 6793 } 6794 6795 /* acknowledge the interrupts */ 6796 wr32(E1000_TSICR, ack); 6797 } 6798 6799 static irqreturn_t igb_msix_other(int irq, void *data) 6800 { 6801 struct igb_adapter *adapter = data; 6802 struct e1000_hw *hw = &adapter->hw; 6803 u32 icr = rd32(E1000_ICR); 6804 /* reading ICR causes bit 31 of EICR to be cleared */ 6805 6806 if (icr & E1000_ICR_DRSTA) 6807 schedule_work(&adapter->reset_task); 6808 6809 if (icr & E1000_ICR_DOUTSYNC) { 6810 /* HW is reporting DMA is out of sync */ 6811 adapter->stats.doosync++; 6812 /* The DMA Out of Sync is also indication of a spoof event 6813 * in IOV mode. Check the Wrong VM Behavior register to 6814 * see if it is really a spoof event. 6815 */ 6816 igb_check_wvbr(adapter); 6817 } 6818 6819 /* Check for a mailbox event */ 6820 if (icr & E1000_ICR_VMMB) 6821 igb_msg_task(adapter); 6822 6823 if (icr & E1000_ICR_LSC) { 6824 hw->mac.get_link_status = 1; 6825 /* guard against interrupt when we're going down */ 6826 if (!test_bit(__IGB_DOWN, &adapter->state)) 6827 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6828 } 6829 6830 if (icr & E1000_ICR_TS) 6831 igb_tsync_interrupt(adapter); 6832 6833 wr32(E1000_EIMS, adapter->eims_other); 6834 6835 return IRQ_HANDLED; 6836 } 6837 6838 static void igb_write_itr(struct igb_q_vector *q_vector) 6839 { 6840 struct igb_adapter *adapter = q_vector->adapter; 6841 u32 itr_val = q_vector->itr_val & 0x7FFC; 6842 6843 if (!q_vector->set_itr) 6844 return; 6845 6846 if (!itr_val) 6847 itr_val = 0x4; 6848 6849 if (adapter->hw.mac.type == e1000_82575) 6850 itr_val |= itr_val << 16; 6851 else 6852 itr_val |= E1000_EITR_CNT_IGNR; 6853 6854 writel(itr_val, q_vector->itr_register); 6855 q_vector->set_itr = 0; 6856 } 6857 6858 static irqreturn_t igb_msix_ring(int irq, void *data) 6859 { 6860 struct igb_q_vector *q_vector = data; 6861 6862 /* Write the ITR value calculated from the previous interrupt. */ 6863 igb_write_itr(q_vector); 6864 6865 napi_schedule(&q_vector->napi); 6866 6867 return IRQ_HANDLED; 6868 } 6869 6870 #ifdef CONFIG_IGB_DCA 6871 static void igb_update_tx_dca(struct igb_adapter *adapter, 6872 struct igb_ring *tx_ring, 6873 int cpu) 6874 { 6875 struct e1000_hw *hw = &adapter->hw; 6876 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6877 6878 if (hw->mac.type != e1000_82575) 6879 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6880 6881 /* We can enable relaxed ordering for reads, but not writes when 6882 * DCA is enabled. This is due to a known issue in some chipsets 6883 * which will cause the DCA tag to be cleared. 6884 */ 6885 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6886 E1000_DCA_TXCTRL_DATA_RRO_EN | 6887 E1000_DCA_TXCTRL_DESC_DCA_EN; 6888 6889 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6890 } 6891 6892 static void igb_update_rx_dca(struct igb_adapter *adapter, 6893 struct igb_ring *rx_ring, 6894 int cpu) 6895 { 6896 struct e1000_hw *hw = &adapter->hw; 6897 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6898 6899 if (hw->mac.type != e1000_82575) 6900 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6901 6902 /* We can enable relaxed ordering for reads, but not writes when 6903 * DCA is enabled. This is due to a known issue in some chipsets 6904 * which will cause the DCA tag to be cleared. 6905 */ 6906 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6907 E1000_DCA_RXCTRL_DESC_DCA_EN; 6908 6909 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6910 } 6911 6912 static void igb_update_dca(struct igb_q_vector *q_vector) 6913 { 6914 struct igb_adapter *adapter = q_vector->adapter; 6915 int cpu = get_cpu(); 6916 6917 if (q_vector->cpu == cpu) 6918 goto out_no_update; 6919 6920 if (q_vector->tx.ring) 6921 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6922 6923 if (q_vector->rx.ring) 6924 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6925 6926 q_vector->cpu = cpu; 6927 out_no_update: 6928 put_cpu(); 6929 } 6930 6931 static void igb_setup_dca(struct igb_adapter *adapter) 6932 { 6933 struct e1000_hw *hw = &adapter->hw; 6934 int i; 6935 6936 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6937 return; 6938 6939 /* Always use CB2 mode, difference is masked in the CB driver. */ 6940 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6941 6942 for (i = 0; i < adapter->num_q_vectors; i++) { 6943 adapter->q_vector[i]->cpu = -1; 6944 igb_update_dca(adapter->q_vector[i]); 6945 } 6946 } 6947 6948 static int __igb_notify_dca(struct device *dev, void *data) 6949 { 6950 struct net_device *netdev = dev_get_drvdata(dev); 6951 struct igb_adapter *adapter = netdev_priv(netdev); 6952 struct pci_dev *pdev = adapter->pdev; 6953 struct e1000_hw *hw = &adapter->hw; 6954 unsigned long event = *(unsigned long *)data; 6955 6956 switch (event) { 6957 case DCA_PROVIDER_ADD: 6958 /* if already enabled, don't do it again */ 6959 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6960 break; 6961 if (dca_add_requester(dev) == 0) { 6962 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6963 dev_info(&pdev->dev, "DCA enabled\n"); 6964 igb_setup_dca(adapter); 6965 break; 6966 } 6967 fallthrough; /* since DCA is disabled. */ 6968 case DCA_PROVIDER_REMOVE: 6969 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6970 /* without this a class_device is left 6971 * hanging around in the sysfs model 6972 */ 6973 dca_remove_requester(dev); 6974 dev_info(&pdev->dev, "DCA disabled\n"); 6975 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6976 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6977 } 6978 break; 6979 } 6980 6981 return 0; 6982 } 6983 6984 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6985 void *p) 6986 { 6987 int ret_val; 6988 6989 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6990 __igb_notify_dca); 6991 6992 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6993 } 6994 #endif /* CONFIG_IGB_DCA */ 6995 6996 #ifdef CONFIG_PCI_IOV 6997 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6998 { 6999 unsigned char mac_addr[ETH_ALEN]; 7000 7001 eth_zero_addr(mac_addr); 7002 igb_set_vf_mac(adapter, vf, mac_addr); 7003 7004 /* By default spoof check is enabled for all VFs */ 7005 adapter->vf_data[vf].spoofchk_enabled = true; 7006 7007 /* By default VFs are not trusted */ 7008 adapter->vf_data[vf].trusted = false; 7009 7010 return 0; 7011 } 7012 7013 #endif 7014 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7015 { 7016 struct e1000_hw *hw = &adapter->hw; 7017 u32 ping; 7018 int i; 7019 7020 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7021 ping = E1000_PF_CONTROL_MSG; 7022 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7023 ping |= E1000_VT_MSGTYPE_CTS; 7024 igb_write_mbx(hw, &ping, 1, i); 7025 } 7026 } 7027 7028 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7029 { 7030 struct e1000_hw *hw = &adapter->hw; 7031 u32 vmolr = rd32(E1000_VMOLR(vf)); 7032 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7033 7034 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7035 IGB_VF_FLAG_MULTI_PROMISC); 7036 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7037 7038 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7039 vmolr |= E1000_VMOLR_MPME; 7040 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7041 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7042 } else { 7043 /* if we have hashes and we are clearing a multicast promisc 7044 * flag we need to write the hashes to the MTA as this step 7045 * was previously skipped 7046 */ 7047 if (vf_data->num_vf_mc_hashes > 30) { 7048 vmolr |= E1000_VMOLR_MPME; 7049 } else if (vf_data->num_vf_mc_hashes) { 7050 int j; 7051 7052 vmolr |= E1000_VMOLR_ROMPE; 7053 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7054 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7055 } 7056 } 7057 7058 wr32(E1000_VMOLR(vf), vmolr); 7059 7060 /* there are flags left unprocessed, likely not supported */ 7061 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7062 return -EINVAL; 7063 7064 return 0; 7065 } 7066 7067 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7068 u32 *msgbuf, u32 vf) 7069 { 7070 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7071 u16 *hash_list = (u16 *)&msgbuf[1]; 7072 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7073 int i; 7074 7075 /* salt away the number of multicast addresses assigned 7076 * to this VF for later use to restore when the PF multi cast 7077 * list changes 7078 */ 7079 vf_data->num_vf_mc_hashes = n; 7080 7081 /* only up to 30 hash values supported */ 7082 if (n > 30) 7083 n = 30; 7084 7085 /* store the hashes for later use */ 7086 for (i = 0; i < n; i++) 7087 vf_data->vf_mc_hashes[i] = hash_list[i]; 7088 7089 /* Flush and reset the mta with the new values */ 7090 igb_set_rx_mode(adapter->netdev); 7091 7092 return 0; 7093 } 7094 7095 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7096 { 7097 struct e1000_hw *hw = &adapter->hw; 7098 struct vf_data_storage *vf_data; 7099 int i, j; 7100 7101 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7102 u32 vmolr = rd32(E1000_VMOLR(i)); 7103 7104 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7105 7106 vf_data = &adapter->vf_data[i]; 7107 7108 if ((vf_data->num_vf_mc_hashes > 30) || 7109 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7110 vmolr |= E1000_VMOLR_MPME; 7111 } else if (vf_data->num_vf_mc_hashes) { 7112 vmolr |= E1000_VMOLR_ROMPE; 7113 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7114 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7115 } 7116 wr32(E1000_VMOLR(i), vmolr); 7117 } 7118 } 7119 7120 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7121 { 7122 struct e1000_hw *hw = &adapter->hw; 7123 u32 pool_mask, vlvf_mask, i; 7124 7125 /* create mask for VF and other pools */ 7126 pool_mask = E1000_VLVF_POOLSEL_MASK; 7127 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7128 7129 /* drop PF from pool bits */ 7130 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7131 adapter->vfs_allocated_count); 7132 7133 /* Find the vlan filter for this id */ 7134 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7135 u32 vlvf = rd32(E1000_VLVF(i)); 7136 u32 vfta_mask, vid, vfta; 7137 7138 /* remove the vf from the pool */ 7139 if (!(vlvf & vlvf_mask)) 7140 continue; 7141 7142 /* clear out bit from VLVF */ 7143 vlvf ^= vlvf_mask; 7144 7145 /* if other pools are present, just remove ourselves */ 7146 if (vlvf & pool_mask) 7147 goto update_vlvfb; 7148 7149 /* if PF is present, leave VFTA */ 7150 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7151 goto update_vlvf; 7152 7153 vid = vlvf & E1000_VLVF_VLANID_MASK; 7154 vfta_mask = BIT(vid % 32); 7155 7156 /* clear bit from VFTA */ 7157 vfta = adapter->shadow_vfta[vid / 32]; 7158 if (vfta & vfta_mask) 7159 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7160 update_vlvf: 7161 /* clear pool selection enable */ 7162 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7163 vlvf &= E1000_VLVF_POOLSEL_MASK; 7164 else 7165 vlvf = 0; 7166 update_vlvfb: 7167 /* clear pool bits */ 7168 wr32(E1000_VLVF(i), vlvf); 7169 } 7170 } 7171 7172 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7173 { 7174 u32 vlvf; 7175 int idx; 7176 7177 /* short cut the special case */ 7178 if (vlan == 0) 7179 return 0; 7180 7181 /* Search for the VLAN id in the VLVF entries */ 7182 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7183 vlvf = rd32(E1000_VLVF(idx)); 7184 if ((vlvf & VLAN_VID_MASK) == vlan) 7185 break; 7186 } 7187 7188 return idx; 7189 } 7190 7191 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7192 { 7193 struct e1000_hw *hw = &adapter->hw; 7194 u32 bits, pf_id; 7195 int idx; 7196 7197 idx = igb_find_vlvf_entry(hw, vid); 7198 if (!idx) 7199 return; 7200 7201 /* See if any other pools are set for this VLAN filter 7202 * entry other than the PF. 7203 */ 7204 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7205 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7206 bits &= rd32(E1000_VLVF(idx)); 7207 7208 /* Disable the filter so this falls into the default pool. */ 7209 if (!bits) { 7210 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7211 wr32(E1000_VLVF(idx), BIT(pf_id)); 7212 else 7213 wr32(E1000_VLVF(idx), 0); 7214 } 7215 } 7216 7217 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7218 bool add, u32 vf) 7219 { 7220 int pf_id = adapter->vfs_allocated_count; 7221 struct e1000_hw *hw = &adapter->hw; 7222 int err; 7223 7224 /* If VLAN overlaps with one the PF is currently monitoring make 7225 * sure that we are able to allocate a VLVF entry. This may be 7226 * redundant but it guarantees PF will maintain visibility to 7227 * the VLAN. 7228 */ 7229 if (add && test_bit(vid, adapter->active_vlans)) { 7230 err = igb_vfta_set(hw, vid, pf_id, true, false); 7231 if (err) 7232 return err; 7233 } 7234 7235 err = igb_vfta_set(hw, vid, vf, add, false); 7236 7237 if (add && !err) 7238 return err; 7239 7240 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7241 * we may need to drop the PF pool bit in order to allow us to free 7242 * up the VLVF resources. 7243 */ 7244 if (test_bit(vid, adapter->active_vlans) || 7245 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7246 igb_update_pf_vlvf(adapter, vid); 7247 7248 return err; 7249 } 7250 7251 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7252 { 7253 struct e1000_hw *hw = &adapter->hw; 7254 7255 if (vid) 7256 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7257 else 7258 wr32(E1000_VMVIR(vf), 0); 7259 } 7260 7261 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7262 u16 vlan, u8 qos) 7263 { 7264 int err; 7265 7266 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7267 if (err) 7268 return err; 7269 7270 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7271 igb_set_vmolr(adapter, vf, !vlan); 7272 7273 /* revoke access to previous VLAN */ 7274 if (vlan != adapter->vf_data[vf].pf_vlan) 7275 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7276 false, vf); 7277 7278 adapter->vf_data[vf].pf_vlan = vlan; 7279 adapter->vf_data[vf].pf_qos = qos; 7280 igb_set_vf_vlan_strip(adapter, vf, true); 7281 dev_info(&adapter->pdev->dev, 7282 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7283 if (test_bit(__IGB_DOWN, &adapter->state)) { 7284 dev_warn(&adapter->pdev->dev, 7285 "The VF VLAN has been set, but the PF device is not up.\n"); 7286 dev_warn(&adapter->pdev->dev, 7287 "Bring the PF device up before attempting to use the VF device.\n"); 7288 } 7289 7290 return err; 7291 } 7292 7293 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7294 { 7295 /* Restore tagless access via VLAN 0 */ 7296 igb_set_vf_vlan(adapter, 0, true, vf); 7297 7298 igb_set_vmvir(adapter, 0, vf); 7299 igb_set_vmolr(adapter, vf, true); 7300 7301 /* Remove any PF assigned VLAN */ 7302 if (adapter->vf_data[vf].pf_vlan) 7303 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7304 false, vf); 7305 7306 adapter->vf_data[vf].pf_vlan = 0; 7307 adapter->vf_data[vf].pf_qos = 0; 7308 igb_set_vf_vlan_strip(adapter, vf, false); 7309 7310 return 0; 7311 } 7312 7313 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7314 u16 vlan, u8 qos, __be16 vlan_proto) 7315 { 7316 struct igb_adapter *adapter = netdev_priv(netdev); 7317 7318 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7319 return -EINVAL; 7320 7321 if (vlan_proto != htons(ETH_P_8021Q)) 7322 return -EPROTONOSUPPORT; 7323 7324 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7325 igb_disable_port_vlan(adapter, vf); 7326 } 7327 7328 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7329 { 7330 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7331 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7332 int ret; 7333 7334 if (adapter->vf_data[vf].pf_vlan) 7335 return -1; 7336 7337 /* VLAN 0 is a special case, don't allow it to be removed */ 7338 if (!vid && !add) 7339 return 0; 7340 7341 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7342 if (!ret) 7343 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7344 return ret; 7345 } 7346 7347 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7348 { 7349 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7350 7351 /* clear flags - except flag that indicates PF has set the MAC */ 7352 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7353 vf_data->last_nack = jiffies; 7354 7355 /* reset vlans for device */ 7356 igb_clear_vf_vfta(adapter, vf); 7357 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7358 igb_set_vmvir(adapter, vf_data->pf_vlan | 7359 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7360 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7361 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7362 7363 /* reset multicast table array for vf */ 7364 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7365 7366 /* Flush and reset the mta with the new values */ 7367 igb_set_rx_mode(adapter->netdev); 7368 } 7369 7370 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7371 { 7372 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7373 7374 /* clear mac address as we were hotplug removed/added */ 7375 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7376 eth_zero_addr(vf_mac); 7377 7378 /* process remaining reset events */ 7379 igb_vf_reset(adapter, vf); 7380 } 7381 7382 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7383 { 7384 struct e1000_hw *hw = &adapter->hw; 7385 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7386 u32 reg, msgbuf[3]; 7387 u8 *addr = (u8 *)(&msgbuf[1]); 7388 7389 /* process all the same items cleared in a function level reset */ 7390 igb_vf_reset(adapter, vf); 7391 7392 /* set vf mac address */ 7393 igb_set_vf_mac(adapter, vf, vf_mac); 7394 7395 /* enable transmit and receive for vf */ 7396 reg = rd32(E1000_VFTE); 7397 wr32(E1000_VFTE, reg | BIT(vf)); 7398 reg = rd32(E1000_VFRE); 7399 wr32(E1000_VFRE, reg | BIT(vf)); 7400 7401 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7402 7403 /* reply to reset with ack and vf mac address */ 7404 if (!is_zero_ether_addr(vf_mac)) { 7405 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7406 memcpy(addr, vf_mac, ETH_ALEN); 7407 } else { 7408 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7409 } 7410 igb_write_mbx(hw, msgbuf, 3, vf); 7411 } 7412 7413 static void igb_flush_mac_table(struct igb_adapter *adapter) 7414 { 7415 struct e1000_hw *hw = &adapter->hw; 7416 int i; 7417 7418 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7419 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7420 eth_zero_addr(adapter->mac_table[i].addr); 7421 adapter->mac_table[i].queue = 0; 7422 igb_rar_set_index(adapter, i); 7423 } 7424 } 7425 7426 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7427 { 7428 struct e1000_hw *hw = &adapter->hw; 7429 /* do not count rar entries reserved for VFs MAC addresses */ 7430 int rar_entries = hw->mac.rar_entry_count - 7431 adapter->vfs_allocated_count; 7432 int i, count = 0; 7433 7434 for (i = 0; i < rar_entries; i++) { 7435 /* do not count default entries */ 7436 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7437 continue; 7438 7439 /* do not count "in use" entries for different queues */ 7440 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7441 (adapter->mac_table[i].queue != queue)) 7442 continue; 7443 7444 count++; 7445 } 7446 7447 return count; 7448 } 7449 7450 /* Set default MAC address for the PF in the first RAR entry */ 7451 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7452 { 7453 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7454 7455 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7456 mac_table->queue = adapter->vfs_allocated_count; 7457 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7458 7459 igb_rar_set_index(adapter, 0); 7460 } 7461 7462 /* If the filter to be added and an already existing filter express 7463 * the same address and address type, it should be possible to only 7464 * override the other configurations, for example the queue to steer 7465 * traffic. 7466 */ 7467 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7468 const u8 *addr, const u8 flags) 7469 { 7470 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7471 return true; 7472 7473 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7474 (flags & IGB_MAC_STATE_SRC_ADDR)) 7475 return false; 7476 7477 if (!ether_addr_equal(addr, entry->addr)) 7478 return false; 7479 7480 return true; 7481 } 7482 7483 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7484 * 'flags' is used to indicate what kind of match is made, match is by 7485 * default for the destination address, if matching by source address 7486 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7487 */ 7488 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7489 const u8 *addr, const u8 queue, 7490 const u8 flags) 7491 { 7492 struct e1000_hw *hw = &adapter->hw; 7493 int rar_entries = hw->mac.rar_entry_count - 7494 adapter->vfs_allocated_count; 7495 int i; 7496 7497 if (is_zero_ether_addr(addr)) 7498 return -EINVAL; 7499 7500 /* Search for the first empty entry in the MAC table. 7501 * Do not touch entries at the end of the table reserved for the VF MAC 7502 * addresses. 7503 */ 7504 for (i = 0; i < rar_entries; i++) { 7505 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7506 addr, flags)) 7507 continue; 7508 7509 ether_addr_copy(adapter->mac_table[i].addr, addr); 7510 adapter->mac_table[i].queue = queue; 7511 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7512 7513 igb_rar_set_index(adapter, i); 7514 return i; 7515 } 7516 7517 return -ENOSPC; 7518 } 7519 7520 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7521 const u8 queue) 7522 { 7523 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7524 } 7525 7526 /* Remove a MAC filter for 'addr' directing matching traffic to 7527 * 'queue', 'flags' is used to indicate what kind of match need to be 7528 * removed, match is by default for the destination address, if 7529 * matching by source address is to be removed the flag 7530 * IGB_MAC_STATE_SRC_ADDR can be used. 7531 */ 7532 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7533 const u8 *addr, const u8 queue, 7534 const u8 flags) 7535 { 7536 struct e1000_hw *hw = &adapter->hw; 7537 int rar_entries = hw->mac.rar_entry_count - 7538 adapter->vfs_allocated_count; 7539 int i; 7540 7541 if (is_zero_ether_addr(addr)) 7542 return -EINVAL; 7543 7544 /* Search for matching entry in the MAC table based on given address 7545 * and queue. Do not touch entries at the end of the table reserved 7546 * for the VF MAC addresses. 7547 */ 7548 for (i = 0; i < rar_entries; i++) { 7549 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7550 continue; 7551 if ((adapter->mac_table[i].state & flags) != flags) 7552 continue; 7553 if (adapter->mac_table[i].queue != queue) 7554 continue; 7555 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7556 continue; 7557 7558 /* When a filter for the default address is "deleted", 7559 * we return it to its initial configuration 7560 */ 7561 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7562 adapter->mac_table[i].state = 7563 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7564 adapter->mac_table[i].queue = 7565 adapter->vfs_allocated_count; 7566 } else { 7567 adapter->mac_table[i].state = 0; 7568 adapter->mac_table[i].queue = 0; 7569 eth_zero_addr(adapter->mac_table[i].addr); 7570 } 7571 7572 igb_rar_set_index(adapter, i); 7573 return 0; 7574 } 7575 7576 return -ENOENT; 7577 } 7578 7579 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7580 const u8 queue) 7581 { 7582 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7583 } 7584 7585 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7586 const u8 *addr, u8 queue, u8 flags) 7587 { 7588 struct e1000_hw *hw = &adapter->hw; 7589 7590 /* In theory, this should be supported on 82575 as well, but 7591 * that part wasn't easily accessible during development. 7592 */ 7593 if (hw->mac.type != e1000_i210) 7594 return -EOPNOTSUPP; 7595 7596 return igb_add_mac_filter_flags(adapter, addr, queue, 7597 IGB_MAC_STATE_QUEUE_STEERING | flags); 7598 } 7599 7600 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7601 const u8 *addr, u8 queue, u8 flags) 7602 { 7603 return igb_del_mac_filter_flags(adapter, addr, queue, 7604 IGB_MAC_STATE_QUEUE_STEERING | flags); 7605 } 7606 7607 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7608 { 7609 struct igb_adapter *adapter = netdev_priv(netdev); 7610 int ret; 7611 7612 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7613 7614 return min_t(int, ret, 0); 7615 } 7616 7617 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7618 { 7619 struct igb_adapter *adapter = netdev_priv(netdev); 7620 7621 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7622 7623 return 0; 7624 } 7625 7626 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7627 const u32 info, const u8 *addr) 7628 { 7629 struct pci_dev *pdev = adapter->pdev; 7630 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7631 struct list_head *pos; 7632 struct vf_mac_filter *entry = NULL; 7633 int ret = 0; 7634 7635 switch (info) { 7636 case E1000_VF_MAC_FILTER_CLR: 7637 /* remove all unicast MAC filters related to the current VF */ 7638 list_for_each(pos, &adapter->vf_macs.l) { 7639 entry = list_entry(pos, struct vf_mac_filter, l); 7640 if (entry->vf == vf) { 7641 entry->vf = -1; 7642 entry->free = true; 7643 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7644 } 7645 } 7646 break; 7647 case E1000_VF_MAC_FILTER_ADD: 7648 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7649 !vf_data->trusted) { 7650 dev_warn(&pdev->dev, 7651 "VF %d requested MAC filter but is administratively denied\n", 7652 vf); 7653 return -EINVAL; 7654 } 7655 if (!is_valid_ether_addr(addr)) { 7656 dev_warn(&pdev->dev, 7657 "VF %d attempted to set invalid MAC filter\n", 7658 vf); 7659 return -EINVAL; 7660 } 7661 7662 /* try to find empty slot in the list */ 7663 list_for_each(pos, &adapter->vf_macs.l) { 7664 entry = list_entry(pos, struct vf_mac_filter, l); 7665 if (entry->free) 7666 break; 7667 } 7668 7669 if (entry && entry->free) { 7670 entry->free = false; 7671 entry->vf = vf; 7672 ether_addr_copy(entry->vf_mac, addr); 7673 7674 ret = igb_add_mac_filter(adapter, addr, vf); 7675 ret = min_t(int, ret, 0); 7676 } else { 7677 ret = -ENOSPC; 7678 } 7679 7680 if (ret == -ENOSPC) 7681 dev_warn(&pdev->dev, 7682 "VF %d has requested MAC filter but there is no space for it\n", 7683 vf); 7684 break; 7685 default: 7686 ret = -EINVAL; 7687 break; 7688 } 7689 7690 return ret; 7691 } 7692 7693 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7694 { 7695 struct pci_dev *pdev = adapter->pdev; 7696 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7697 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7698 7699 /* The VF MAC Address is stored in a packed array of bytes 7700 * starting at the second 32 bit word of the msg array 7701 */ 7702 unsigned char *addr = (unsigned char *)&msg[1]; 7703 int ret = 0; 7704 7705 if (!info) { 7706 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7707 !vf_data->trusted) { 7708 dev_warn(&pdev->dev, 7709 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7710 vf); 7711 return -EINVAL; 7712 } 7713 7714 if (!is_valid_ether_addr(addr)) { 7715 dev_warn(&pdev->dev, 7716 "VF %d attempted to set invalid MAC\n", 7717 vf); 7718 return -EINVAL; 7719 } 7720 7721 ret = igb_set_vf_mac(adapter, vf, addr); 7722 } else { 7723 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7724 } 7725 7726 return ret; 7727 } 7728 7729 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7730 { 7731 struct e1000_hw *hw = &adapter->hw; 7732 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7733 u32 msg = E1000_VT_MSGTYPE_NACK; 7734 7735 /* if device isn't clear to send it shouldn't be reading either */ 7736 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7737 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7738 igb_write_mbx(hw, &msg, 1, vf); 7739 vf_data->last_nack = jiffies; 7740 } 7741 } 7742 7743 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7744 { 7745 struct pci_dev *pdev = adapter->pdev; 7746 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7747 struct e1000_hw *hw = &adapter->hw; 7748 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7749 s32 retval; 7750 7751 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7752 7753 if (retval) { 7754 /* if receive failed revoke VF CTS stats and restart init */ 7755 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7756 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7757 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7758 goto unlock; 7759 goto out; 7760 } 7761 7762 /* this is a message we already processed, do nothing */ 7763 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7764 goto unlock; 7765 7766 /* until the vf completes a reset it should not be 7767 * allowed to start any configuration. 7768 */ 7769 if (msgbuf[0] == E1000_VF_RESET) { 7770 /* unlocks mailbox */ 7771 igb_vf_reset_msg(adapter, vf); 7772 return; 7773 } 7774 7775 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7776 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7777 goto unlock; 7778 retval = -1; 7779 goto out; 7780 } 7781 7782 switch ((msgbuf[0] & 0xFFFF)) { 7783 case E1000_VF_SET_MAC_ADDR: 7784 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7785 break; 7786 case E1000_VF_SET_PROMISC: 7787 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7788 break; 7789 case E1000_VF_SET_MULTICAST: 7790 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7791 break; 7792 case E1000_VF_SET_LPE: 7793 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7794 break; 7795 case E1000_VF_SET_VLAN: 7796 retval = -1; 7797 if (vf_data->pf_vlan) 7798 dev_warn(&pdev->dev, 7799 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7800 vf); 7801 else 7802 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7803 break; 7804 default: 7805 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7806 retval = -1; 7807 break; 7808 } 7809 7810 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7811 out: 7812 /* notify the VF of the results of what it sent us */ 7813 if (retval) 7814 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7815 else 7816 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7817 7818 /* unlocks mailbox */ 7819 igb_write_mbx(hw, msgbuf, 1, vf); 7820 return; 7821 7822 unlock: 7823 igb_unlock_mbx(hw, vf); 7824 } 7825 7826 static void igb_msg_task(struct igb_adapter *adapter) 7827 { 7828 struct e1000_hw *hw = &adapter->hw; 7829 u32 vf; 7830 7831 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7832 /* process any reset requests */ 7833 if (!igb_check_for_rst(hw, vf)) 7834 igb_vf_reset_event(adapter, vf); 7835 7836 /* process any messages pending */ 7837 if (!igb_check_for_msg(hw, vf)) 7838 igb_rcv_msg_from_vf(adapter, vf); 7839 7840 /* process any acks */ 7841 if (!igb_check_for_ack(hw, vf)) 7842 igb_rcv_ack_from_vf(adapter, vf); 7843 } 7844 } 7845 7846 /** 7847 * igb_set_uta - Set unicast filter table address 7848 * @adapter: board private structure 7849 * @set: boolean indicating if we are setting or clearing bits 7850 * 7851 * The unicast table address is a register array of 32-bit registers. 7852 * The table is meant to be used in a way similar to how the MTA is used 7853 * however due to certain limitations in the hardware it is necessary to 7854 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7855 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7856 **/ 7857 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7858 { 7859 struct e1000_hw *hw = &adapter->hw; 7860 u32 uta = set ? ~0 : 0; 7861 int i; 7862 7863 /* we only need to do this if VMDq is enabled */ 7864 if (!adapter->vfs_allocated_count) 7865 return; 7866 7867 for (i = hw->mac.uta_reg_count; i--;) 7868 array_wr32(E1000_UTA, i, uta); 7869 } 7870 7871 /** 7872 * igb_intr_msi - Interrupt Handler 7873 * @irq: interrupt number 7874 * @data: pointer to a network interface device structure 7875 **/ 7876 static irqreturn_t igb_intr_msi(int irq, void *data) 7877 { 7878 struct igb_adapter *adapter = data; 7879 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7880 struct e1000_hw *hw = &adapter->hw; 7881 /* read ICR disables interrupts using IAM */ 7882 u32 icr = rd32(E1000_ICR); 7883 7884 igb_write_itr(q_vector); 7885 7886 if (icr & E1000_ICR_DRSTA) 7887 schedule_work(&adapter->reset_task); 7888 7889 if (icr & E1000_ICR_DOUTSYNC) { 7890 /* HW is reporting DMA is out of sync */ 7891 adapter->stats.doosync++; 7892 } 7893 7894 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7895 hw->mac.get_link_status = 1; 7896 if (!test_bit(__IGB_DOWN, &adapter->state)) 7897 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7898 } 7899 7900 if (icr & E1000_ICR_TS) 7901 igb_tsync_interrupt(adapter); 7902 7903 napi_schedule(&q_vector->napi); 7904 7905 return IRQ_HANDLED; 7906 } 7907 7908 /** 7909 * igb_intr - Legacy Interrupt Handler 7910 * @irq: interrupt number 7911 * @data: pointer to a network interface device structure 7912 **/ 7913 static irqreturn_t igb_intr(int irq, void *data) 7914 { 7915 struct igb_adapter *adapter = data; 7916 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7917 struct e1000_hw *hw = &adapter->hw; 7918 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7919 * need for the IMC write 7920 */ 7921 u32 icr = rd32(E1000_ICR); 7922 7923 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7924 * not set, then the adapter didn't send an interrupt 7925 */ 7926 if (!(icr & E1000_ICR_INT_ASSERTED)) 7927 return IRQ_NONE; 7928 7929 igb_write_itr(q_vector); 7930 7931 if (icr & E1000_ICR_DRSTA) 7932 schedule_work(&adapter->reset_task); 7933 7934 if (icr & E1000_ICR_DOUTSYNC) { 7935 /* HW is reporting DMA is out of sync */ 7936 adapter->stats.doosync++; 7937 } 7938 7939 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7940 hw->mac.get_link_status = 1; 7941 /* guard against interrupt when we're going down */ 7942 if (!test_bit(__IGB_DOWN, &adapter->state)) 7943 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7944 } 7945 7946 if (icr & E1000_ICR_TS) 7947 igb_tsync_interrupt(adapter); 7948 7949 napi_schedule(&q_vector->napi); 7950 7951 return IRQ_HANDLED; 7952 } 7953 7954 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7955 { 7956 struct igb_adapter *adapter = q_vector->adapter; 7957 struct e1000_hw *hw = &adapter->hw; 7958 7959 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7960 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7961 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7962 igb_set_itr(q_vector); 7963 else 7964 igb_update_ring_itr(q_vector); 7965 } 7966 7967 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7968 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7969 wr32(E1000_EIMS, q_vector->eims_value); 7970 else 7971 igb_irq_enable(adapter); 7972 } 7973 } 7974 7975 /** 7976 * igb_poll - NAPI Rx polling callback 7977 * @napi: napi polling structure 7978 * @budget: count of how many packets we should handle 7979 **/ 7980 static int igb_poll(struct napi_struct *napi, int budget) 7981 { 7982 struct igb_q_vector *q_vector = container_of(napi, 7983 struct igb_q_vector, 7984 napi); 7985 bool clean_complete = true; 7986 int work_done = 0; 7987 7988 #ifdef CONFIG_IGB_DCA 7989 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7990 igb_update_dca(q_vector); 7991 #endif 7992 if (q_vector->tx.ring) 7993 clean_complete = igb_clean_tx_irq(q_vector, budget); 7994 7995 if (q_vector->rx.ring) { 7996 int cleaned = igb_clean_rx_irq(q_vector, budget); 7997 7998 work_done += cleaned; 7999 if (cleaned >= budget) 8000 clean_complete = false; 8001 } 8002 8003 /* If all work not completed, return budget and keep polling */ 8004 if (!clean_complete) 8005 return budget; 8006 8007 /* Exit the polling mode, but don't re-enable interrupts if stack might 8008 * poll us due to busy-polling 8009 */ 8010 if (likely(napi_complete_done(napi, work_done))) 8011 igb_ring_irq_enable(q_vector); 8012 8013 return min(work_done, budget - 1); 8014 } 8015 8016 /** 8017 * igb_clean_tx_irq - Reclaim resources after transmit completes 8018 * @q_vector: pointer to q_vector containing needed info 8019 * @napi_budget: Used to determine if we are in netpoll 8020 * 8021 * returns true if ring is completely cleaned 8022 **/ 8023 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8024 { 8025 struct igb_adapter *adapter = q_vector->adapter; 8026 struct igb_ring *tx_ring = q_vector->tx.ring; 8027 struct igb_tx_buffer *tx_buffer; 8028 union e1000_adv_tx_desc *tx_desc; 8029 unsigned int total_bytes = 0, total_packets = 0; 8030 unsigned int budget = q_vector->tx.work_limit; 8031 unsigned int i = tx_ring->next_to_clean; 8032 8033 if (test_bit(__IGB_DOWN, &adapter->state)) 8034 return true; 8035 8036 tx_buffer = &tx_ring->tx_buffer_info[i]; 8037 tx_desc = IGB_TX_DESC(tx_ring, i); 8038 i -= tx_ring->count; 8039 8040 do { 8041 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8042 8043 /* if next_to_watch is not set then there is no work pending */ 8044 if (!eop_desc) 8045 break; 8046 8047 /* prevent any other reads prior to eop_desc */ 8048 smp_rmb(); 8049 8050 /* if DD is not set pending work has not been completed */ 8051 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8052 break; 8053 8054 /* clear next_to_watch to prevent false hangs */ 8055 tx_buffer->next_to_watch = NULL; 8056 8057 /* update the statistics for this packet */ 8058 total_bytes += tx_buffer->bytecount; 8059 total_packets += tx_buffer->gso_segs; 8060 8061 /* free the skb */ 8062 if (tx_buffer->type == IGB_TYPE_SKB) 8063 napi_consume_skb(tx_buffer->skb, napi_budget); 8064 else 8065 xdp_return_frame(tx_buffer->xdpf); 8066 8067 /* unmap skb header data */ 8068 dma_unmap_single(tx_ring->dev, 8069 dma_unmap_addr(tx_buffer, dma), 8070 dma_unmap_len(tx_buffer, len), 8071 DMA_TO_DEVICE); 8072 8073 /* clear tx_buffer data */ 8074 dma_unmap_len_set(tx_buffer, len, 0); 8075 8076 /* clear last DMA location and unmap remaining buffers */ 8077 while (tx_desc != eop_desc) { 8078 tx_buffer++; 8079 tx_desc++; 8080 i++; 8081 if (unlikely(!i)) { 8082 i -= tx_ring->count; 8083 tx_buffer = tx_ring->tx_buffer_info; 8084 tx_desc = IGB_TX_DESC(tx_ring, 0); 8085 } 8086 8087 /* unmap any remaining paged data */ 8088 if (dma_unmap_len(tx_buffer, len)) { 8089 dma_unmap_page(tx_ring->dev, 8090 dma_unmap_addr(tx_buffer, dma), 8091 dma_unmap_len(tx_buffer, len), 8092 DMA_TO_DEVICE); 8093 dma_unmap_len_set(tx_buffer, len, 0); 8094 } 8095 } 8096 8097 /* move us one more past the eop_desc for start of next pkt */ 8098 tx_buffer++; 8099 tx_desc++; 8100 i++; 8101 if (unlikely(!i)) { 8102 i -= tx_ring->count; 8103 tx_buffer = tx_ring->tx_buffer_info; 8104 tx_desc = IGB_TX_DESC(tx_ring, 0); 8105 } 8106 8107 /* issue prefetch for next Tx descriptor */ 8108 prefetch(tx_desc); 8109 8110 /* update budget accounting */ 8111 budget--; 8112 } while (likely(budget)); 8113 8114 netdev_tx_completed_queue(txring_txq(tx_ring), 8115 total_packets, total_bytes); 8116 i += tx_ring->count; 8117 tx_ring->next_to_clean = i; 8118 u64_stats_update_begin(&tx_ring->tx_syncp); 8119 tx_ring->tx_stats.bytes += total_bytes; 8120 tx_ring->tx_stats.packets += total_packets; 8121 u64_stats_update_end(&tx_ring->tx_syncp); 8122 q_vector->tx.total_bytes += total_bytes; 8123 q_vector->tx.total_packets += total_packets; 8124 8125 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8126 struct e1000_hw *hw = &adapter->hw; 8127 8128 /* Detect a transmit hang in hardware, this serializes the 8129 * check with the clearing of time_stamp and movement of i 8130 */ 8131 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8132 if (tx_buffer->next_to_watch && 8133 time_after(jiffies, tx_buffer->time_stamp + 8134 (adapter->tx_timeout_factor * HZ)) && 8135 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8136 8137 /* detected Tx unit hang */ 8138 dev_err(tx_ring->dev, 8139 "Detected Tx Unit Hang\n" 8140 " Tx Queue <%d>\n" 8141 " TDH <%x>\n" 8142 " TDT <%x>\n" 8143 " next_to_use <%x>\n" 8144 " next_to_clean <%x>\n" 8145 "buffer_info[next_to_clean]\n" 8146 " time_stamp <%lx>\n" 8147 " next_to_watch <%p>\n" 8148 " jiffies <%lx>\n" 8149 " desc.status <%x>\n", 8150 tx_ring->queue_index, 8151 rd32(E1000_TDH(tx_ring->reg_idx)), 8152 readl(tx_ring->tail), 8153 tx_ring->next_to_use, 8154 tx_ring->next_to_clean, 8155 tx_buffer->time_stamp, 8156 tx_buffer->next_to_watch, 8157 jiffies, 8158 tx_buffer->next_to_watch->wb.status); 8159 netif_stop_subqueue(tx_ring->netdev, 8160 tx_ring->queue_index); 8161 8162 /* we are about to reset, no point in enabling stuff */ 8163 return true; 8164 } 8165 } 8166 8167 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8168 if (unlikely(total_packets && 8169 netif_carrier_ok(tx_ring->netdev) && 8170 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8171 /* Make sure that anybody stopping the queue after this 8172 * sees the new next_to_clean. 8173 */ 8174 smp_mb(); 8175 if (__netif_subqueue_stopped(tx_ring->netdev, 8176 tx_ring->queue_index) && 8177 !(test_bit(__IGB_DOWN, &adapter->state))) { 8178 netif_wake_subqueue(tx_ring->netdev, 8179 tx_ring->queue_index); 8180 8181 u64_stats_update_begin(&tx_ring->tx_syncp); 8182 tx_ring->tx_stats.restart_queue++; 8183 u64_stats_update_end(&tx_ring->tx_syncp); 8184 } 8185 } 8186 8187 return !!budget; 8188 } 8189 8190 /** 8191 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8192 * @rx_ring: rx descriptor ring to store buffers on 8193 * @old_buff: donor buffer to have page reused 8194 * 8195 * Synchronizes page for reuse by the adapter 8196 **/ 8197 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8198 struct igb_rx_buffer *old_buff) 8199 { 8200 struct igb_rx_buffer *new_buff; 8201 u16 nta = rx_ring->next_to_alloc; 8202 8203 new_buff = &rx_ring->rx_buffer_info[nta]; 8204 8205 /* update, and store next to alloc */ 8206 nta++; 8207 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8208 8209 /* Transfer page from old buffer to new buffer. 8210 * Move each member individually to avoid possible store 8211 * forwarding stalls. 8212 */ 8213 new_buff->dma = old_buff->dma; 8214 new_buff->page = old_buff->page; 8215 new_buff->page_offset = old_buff->page_offset; 8216 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8217 } 8218 8219 static inline bool igb_page_is_reserved(struct page *page) 8220 { 8221 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 8222 } 8223 8224 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 8225 { 8226 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8227 struct page *page = rx_buffer->page; 8228 8229 /* avoid re-using remote pages */ 8230 if (unlikely(igb_page_is_reserved(page))) 8231 return false; 8232 8233 #if (PAGE_SIZE < 8192) 8234 /* if we are only owner of page we can reuse it */ 8235 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 8236 return false; 8237 #else 8238 #define IGB_LAST_OFFSET \ 8239 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8240 8241 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8242 return false; 8243 #endif 8244 8245 /* If we have drained the page fragment pool we need to update 8246 * the pagecnt_bias and page count so that we fully restock the 8247 * number of references the driver holds. 8248 */ 8249 if (unlikely(pagecnt_bias == 1)) { 8250 page_ref_add(page, USHRT_MAX - 1); 8251 rx_buffer->pagecnt_bias = USHRT_MAX; 8252 } 8253 8254 return true; 8255 } 8256 8257 /** 8258 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8259 * @rx_ring: rx descriptor ring to transact packets on 8260 * @rx_buffer: buffer containing page to add 8261 * @skb: sk_buff to place the data into 8262 * @size: size of buffer to be added 8263 * 8264 * This function will add the data contained in rx_buffer->page to the skb. 8265 **/ 8266 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8267 struct igb_rx_buffer *rx_buffer, 8268 struct sk_buff *skb, 8269 unsigned int size) 8270 { 8271 #if (PAGE_SIZE < 8192) 8272 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8273 #else 8274 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8275 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8276 SKB_DATA_ALIGN(size); 8277 #endif 8278 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8279 rx_buffer->page_offset, size, truesize); 8280 #if (PAGE_SIZE < 8192) 8281 rx_buffer->page_offset ^= truesize; 8282 #else 8283 rx_buffer->page_offset += truesize; 8284 #endif 8285 } 8286 8287 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8288 struct igb_rx_buffer *rx_buffer, 8289 struct xdp_buff *xdp, 8290 union e1000_adv_rx_desc *rx_desc) 8291 { 8292 #if (PAGE_SIZE < 8192) 8293 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8294 #else 8295 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8296 xdp->data_hard_start); 8297 #endif 8298 unsigned int size = xdp->data_end - xdp->data; 8299 unsigned int headlen; 8300 struct sk_buff *skb; 8301 8302 /* prefetch first cache line of first page */ 8303 net_prefetch(xdp->data); 8304 8305 /* allocate a skb to store the frags */ 8306 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8307 if (unlikely(!skb)) 8308 return NULL; 8309 8310 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8311 igb_ptp_rx_pktstamp(rx_ring->q_vector, xdp->data, skb); 8312 xdp->data += IGB_TS_HDR_LEN; 8313 size -= IGB_TS_HDR_LEN; 8314 } 8315 8316 /* Determine available headroom for copy */ 8317 headlen = size; 8318 if (headlen > IGB_RX_HDR_LEN) 8319 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8320 8321 /* align pull length to size of long to optimize memcpy performance */ 8322 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8323 8324 /* update all of the pointers */ 8325 size -= headlen; 8326 if (size) { 8327 skb_add_rx_frag(skb, 0, rx_buffer->page, 8328 (xdp->data + headlen) - page_address(rx_buffer->page), 8329 size, truesize); 8330 #if (PAGE_SIZE < 8192) 8331 rx_buffer->page_offset ^= truesize; 8332 #else 8333 rx_buffer->page_offset += truesize; 8334 #endif 8335 } else { 8336 rx_buffer->pagecnt_bias++; 8337 } 8338 8339 return skb; 8340 } 8341 8342 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8343 struct igb_rx_buffer *rx_buffer, 8344 struct xdp_buff *xdp, 8345 union e1000_adv_rx_desc *rx_desc) 8346 { 8347 #if (PAGE_SIZE < 8192) 8348 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8349 #else 8350 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8351 SKB_DATA_ALIGN(xdp->data_end - 8352 xdp->data_hard_start); 8353 #endif 8354 struct sk_buff *skb; 8355 8356 /* prefetch first cache line of first page */ 8357 net_prefetch(xdp->data_meta); 8358 8359 /* build an skb around the page buffer */ 8360 skb = build_skb(xdp->data_hard_start, truesize); 8361 if (unlikely(!skb)) 8362 return NULL; 8363 8364 /* update pointers within the skb to store the data */ 8365 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8366 __skb_put(skb, xdp->data_end - xdp->data); 8367 8368 /* pull timestamp out of packet data */ 8369 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8370 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8371 __skb_pull(skb, IGB_TS_HDR_LEN); 8372 } 8373 8374 /* update buffer offset */ 8375 #if (PAGE_SIZE < 8192) 8376 rx_buffer->page_offset ^= truesize; 8377 #else 8378 rx_buffer->page_offset += truesize; 8379 #endif 8380 8381 return skb; 8382 } 8383 8384 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8385 struct igb_ring *rx_ring, 8386 struct xdp_buff *xdp) 8387 { 8388 int err, result = IGB_XDP_PASS; 8389 struct bpf_prog *xdp_prog; 8390 u32 act; 8391 8392 rcu_read_lock(); 8393 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8394 8395 if (!xdp_prog) 8396 goto xdp_out; 8397 8398 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8399 8400 act = bpf_prog_run_xdp(xdp_prog, xdp); 8401 switch (act) { 8402 case XDP_PASS: 8403 break; 8404 case XDP_TX: 8405 result = igb_xdp_xmit_back(adapter, xdp); 8406 break; 8407 case XDP_REDIRECT: 8408 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8409 if (!err) 8410 result = IGB_XDP_REDIR; 8411 else 8412 result = IGB_XDP_CONSUMED; 8413 break; 8414 default: 8415 bpf_warn_invalid_xdp_action(act); 8416 fallthrough; 8417 case XDP_ABORTED: 8418 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8419 fallthrough; 8420 case XDP_DROP: 8421 result = IGB_XDP_CONSUMED; 8422 break; 8423 } 8424 xdp_out: 8425 rcu_read_unlock(); 8426 return ERR_PTR(-result); 8427 } 8428 8429 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8430 unsigned int size) 8431 { 8432 unsigned int truesize; 8433 8434 #if (PAGE_SIZE < 8192) 8435 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8436 #else 8437 truesize = ring_uses_build_skb(rx_ring) ? 8438 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8439 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8440 SKB_DATA_ALIGN(size); 8441 #endif 8442 return truesize; 8443 } 8444 8445 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8446 struct igb_rx_buffer *rx_buffer, 8447 unsigned int size) 8448 { 8449 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8450 #if (PAGE_SIZE < 8192) 8451 rx_buffer->page_offset ^= truesize; 8452 #else 8453 rx_buffer->page_offset += truesize; 8454 #endif 8455 } 8456 8457 static inline void igb_rx_checksum(struct igb_ring *ring, 8458 union e1000_adv_rx_desc *rx_desc, 8459 struct sk_buff *skb) 8460 { 8461 skb_checksum_none_assert(skb); 8462 8463 /* Ignore Checksum bit is set */ 8464 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8465 return; 8466 8467 /* Rx checksum disabled via ethtool */ 8468 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8469 return; 8470 8471 /* TCP/UDP checksum error bit is set */ 8472 if (igb_test_staterr(rx_desc, 8473 E1000_RXDEXT_STATERR_TCPE | 8474 E1000_RXDEXT_STATERR_IPE)) { 8475 /* work around errata with sctp packets where the TCPE aka 8476 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8477 * packets, (aka let the stack check the crc32c) 8478 */ 8479 if (!((skb->len == 60) && 8480 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8481 u64_stats_update_begin(&ring->rx_syncp); 8482 ring->rx_stats.csum_err++; 8483 u64_stats_update_end(&ring->rx_syncp); 8484 } 8485 /* let the stack verify checksum errors */ 8486 return; 8487 } 8488 /* It must be a TCP or UDP packet with a valid checksum */ 8489 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8490 E1000_RXD_STAT_UDPCS)) 8491 skb->ip_summed = CHECKSUM_UNNECESSARY; 8492 8493 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8494 le32_to_cpu(rx_desc->wb.upper.status_error)); 8495 } 8496 8497 static inline void igb_rx_hash(struct igb_ring *ring, 8498 union e1000_adv_rx_desc *rx_desc, 8499 struct sk_buff *skb) 8500 { 8501 if (ring->netdev->features & NETIF_F_RXHASH) 8502 skb_set_hash(skb, 8503 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8504 PKT_HASH_TYPE_L3); 8505 } 8506 8507 /** 8508 * igb_is_non_eop - process handling of non-EOP buffers 8509 * @rx_ring: Rx ring being processed 8510 * @rx_desc: Rx descriptor for current buffer 8511 * 8512 * This function updates next to clean. If the buffer is an EOP buffer 8513 * this function exits returning false, otherwise it will place the 8514 * sk_buff in the next buffer to be chained and return true indicating 8515 * that this is in fact a non-EOP buffer. 8516 **/ 8517 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8518 union e1000_adv_rx_desc *rx_desc) 8519 { 8520 u32 ntc = rx_ring->next_to_clean + 1; 8521 8522 /* fetch, update, and store next to clean */ 8523 ntc = (ntc < rx_ring->count) ? ntc : 0; 8524 rx_ring->next_to_clean = ntc; 8525 8526 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8527 8528 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8529 return false; 8530 8531 return true; 8532 } 8533 8534 /** 8535 * igb_cleanup_headers - Correct corrupted or empty headers 8536 * @rx_ring: rx descriptor ring packet is being transacted on 8537 * @rx_desc: pointer to the EOP Rx descriptor 8538 * @skb: pointer to current skb being fixed 8539 * 8540 * Address the case where we are pulling data in on pages only 8541 * and as such no data is present in the skb header. 8542 * 8543 * In addition if skb is not at least 60 bytes we need to pad it so that 8544 * it is large enough to qualify as a valid Ethernet frame. 8545 * 8546 * Returns true if an error was encountered and skb was freed. 8547 **/ 8548 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8549 union e1000_adv_rx_desc *rx_desc, 8550 struct sk_buff *skb) 8551 { 8552 /* XDP packets use error pointer so abort at this point */ 8553 if (IS_ERR(skb)) 8554 return true; 8555 8556 if (unlikely((igb_test_staterr(rx_desc, 8557 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8558 struct net_device *netdev = rx_ring->netdev; 8559 if (!(netdev->features & NETIF_F_RXALL)) { 8560 dev_kfree_skb_any(skb); 8561 return true; 8562 } 8563 } 8564 8565 /* if eth_skb_pad returns an error the skb was freed */ 8566 if (eth_skb_pad(skb)) 8567 return true; 8568 8569 return false; 8570 } 8571 8572 /** 8573 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8574 * @rx_ring: rx descriptor ring packet is being transacted on 8575 * @rx_desc: pointer to the EOP Rx descriptor 8576 * @skb: pointer to current skb being populated 8577 * 8578 * This function checks the ring, descriptor, and packet information in 8579 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8580 * other fields within the skb. 8581 **/ 8582 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8583 union e1000_adv_rx_desc *rx_desc, 8584 struct sk_buff *skb) 8585 { 8586 struct net_device *dev = rx_ring->netdev; 8587 8588 igb_rx_hash(rx_ring, rx_desc, skb); 8589 8590 igb_rx_checksum(rx_ring, rx_desc, skb); 8591 8592 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8593 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8594 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8595 8596 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8597 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8598 u16 vid; 8599 8600 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8601 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8602 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8603 else 8604 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8605 8606 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8607 } 8608 8609 skb_record_rx_queue(skb, rx_ring->queue_index); 8610 8611 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8612 } 8613 8614 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8615 { 8616 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8617 } 8618 8619 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8620 const unsigned int size) 8621 { 8622 struct igb_rx_buffer *rx_buffer; 8623 8624 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8625 prefetchw(rx_buffer->page); 8626 8627 /* we are reusing so sync this buffer for CPU use */ 8628 dma_sync_single_range_for_cpu(rx_ring->dev, 8629 rx_buffer->dma, 8630 rx_buffer->page_offset, 8631 size, 8632 DMA_FROM_DEVICE); 8633 8634 rx_buffer->pagecnt_bias--; 8635 8636 return rx_buffer; 8637 } 8638 8639 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8640 struct igb_rx_buffer *rx_buffer) 8641 { 8642 if (igb_can_reuse_rx_page(rx_buffer)) { 8643 /* hand second half of page back to the ring */ 8644 igb_reuse_rx_page(rx_ring, rx_buffer); 8645 } else { 8646 /* We are not reusing the buffer so unmap it and free 8647 * any references we are holding to it 8648 */ 8649 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8650 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8651 IGB_RX_DMA_ATTR); 8652 __page_frag_cache_drain(rx_buffer->page, 8653 rx_buffer->pagecnt_bias); 8654 } 8655 8656 /* clear contents of rx_buffer */ 8657 rx_buffer->page = NULL; 8658 } 8659 8660 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8661 { 8662 struct igb_adapter *adapter = q_vector->adapter; 8663 struct igb_ring *rx_ring = q_vector->rx.ring; 8664 struct sk_buff *skb = rx_ring->skb; 8665 unsigned int total_bytes = 0, total_packets = 0; 8666 u16 cleaned_count = igb_desc_unused(rx_ring); 8667 unsigned int xdp_xmit = 0; 8668 struct xdp_buff xdp; 8669 8670 xdp.rxq = &rx_ring->xdp_rxq; 8671 8672 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8673 #if (PAGE_SIZE < 8192) 8674 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8675 #endif 8676 8677 while (likely(total_packets < budget)) { 8678 union e1000_adv_rx_desc *rx_desc; 8679 struct igb_rx_buffer *rx_buffer; 8680 unsigned int size; 8681 8682 /* return some buffers to hardware, one at a time is too slow */ 8683 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8684 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8685 cleaned_count = 0; 8686 } 8687 8688 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8689 size = le16_to_cpu(rx_desc->wb.upper.length); 8690 if (!size) 8691 break; 8692 8693 /* This memory barrier is needed to keep us from reading 8694 * any other fields out of the rx_desc until we know the 8695 * descriptor has been written back 8696 */ 8697 dma_rmb(); 8698 8699 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8700 8701 /* retrieve a buffer from the ring */ 8702 if (!skb) { 8703 xdp.data = page_address(rx_buffer->page) + 8704 rx_buffer->page_offset; 8705 xdp.data_meta = xdp.data; 8706 xdp.data_hard_start = xdp.data - 8707 igb_rx_offset(rx_ring); 8708 xdp.data_end = xdp.data + size; 8709 #if (PAGE_SIZE > 4096) 8710 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8711 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8712 #endif 8713 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8714 } 8715 8716 if (IS_ERR(skb)) { 8717 unsigned int xdp_res = -PTR_ERR(skb); 8718 8719 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8720 xdp_xmit |= xdp_res; 8721 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8722 } else { 8723 rx_buffer->pagecnt_bias++; 8724 } 8725 total_packets++; 8726 total_bytes += size; 8727 } else if (skb) 8728 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8729 else if (ring_uses_build_skb(rx_ring)) 8730 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, rx_desc); 8731 else 8732 skb = igb_construct_skb(rx_ring, rx_buffer, 8733 &xdp, rx_desc); 8734 8735 /* exit if we failed to retrieve a buffer */ 8736 if (!skb) { 8737 rx_ring->rx_stats.alloc_failed++; 8738 rx_buffer->pagecnt_bias++; 8739 break; 8740 } 8741 8742 igb_put_rx_buffer(rx_ring, rx_buffer); 8743 cleaned_count++; 8744 8745 /* fetch next buffer in frame if non-eop */ 8746 if (igb_is_non_eop(rx_ring, rx_desc)) 8747 continue; 8748 8749 /* verify the packet layout is correct */ 8750 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8751 skb = NULL; 8752 continue; 8753 } 8754 8755 /* probably a little skewed due to removing CRC */ 8756 total_bytes += skb->len; 8757 8758 /* populate checksum, timestamp, VLAN, and protocol */ 8759 igb_process_skb_fields(rx_ring, rx_desc, skb); 8760 8761 napi_gro_receive(&q_vector->napi, skb); 8762 8763 /* reset skb pointer */ 8764 skb = NULL; 8765 8766 /* update budget accounting */ 8767 total_packets++; 8768 } 8769 8770 /* place incomplete frames back on ring for completion */ 8771 rx_ring->skb = skb; 8772 8773 if (xdp_xmit & IGB_XDP_REDIR) 8774 xdp_do_flush_map(); 8775 8776 if (xdp_xmit & IGB_XDP_TX) { 8777 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8778 8779 igb_xdp_ring_update_tail(tx_ring); 8780 } 8781 8782 u64_stats_update_begin(&rx_ring->rx_syncp); 8783 rx_ring->rx_stats.packets += total_packets; 8784 rx_ring->rx_stats.bytes += total_bytes; 8785 u64_stats_update_end(&rx_ring->rx_syncp); 8786 q_vector->rx.total_packets += total_packets; 8787 q_vector->rx.total_bytes += total_bytes; 8788 8789 if (cleaned_count) 8790 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8791 8792 return total_packets; 8793 } 8794 8795 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8796 struct igb_rx_buffer *bi) 8797 { 8798 struct page *page = bi->page; 8799 dma_addr_t dma; 8800 8801 /* since we are recycling buffers we should seldom need to alloc */ 8802 if (likely(page)) 8803 return true; 8804 8805 /* alloc new page for storage */ 8806 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8807 if (unlikely(!page)) { 8808 rx_ring->rx_stats.alloc_failed++; 8809 return false; 8810 } 8811 8812 /* map page for use */ 8813 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8814 igb_rx_pg_size(rx_ring), 8815 DMA_FROM_DEVICE, 8816 IGB_RX_DMA_ATTR); 8817 8818 /* if mapping failed free memory back to system since 8819 * there isn't much point in holding memory we can't use 8820 */ 8821 if (dma_mapping_error(rx_ring->dev, dma)) { 8822 __free_pages(page, igb_rx_pg_order(rx_ring)); 8823 8824 rx_ring->rx_stats.alloc_failed++; 8825 return false; 8826 } 8827 8828 bi->dma = dma; 8829 bi->page = page; 8830 bi->page_offset = igb_rx_offset(rx_ring); 8831 page_ref_add(page, USHRT_MAX - 1); 8832 bi->pagecnt_bias = USHRT_MAX; 8833 8834 return true; 8835 } 8836 8837 /** 8838 * igb_alloc_rx_buffers - Replace used receive buffers 8839 * @rx_ring: rx descriptor ring to allocate new receive buffers 8840 * @cleaned_count: count of buffers to allocate 8841 **/ 8842 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8843 { 8844 union e1000_adv_rx_desc *rx_desc; 8845 struct igb_rx_buffer *bi; 8846 u16 i = rx_ring->next_to_use; 8847 u16 bufsz; 8848 8849 /* nothing to do */ 8850 if (!cleaned_count) 8851 return; 8852 8853 rx_desc = IGB_RX_DESC(rx_ring, i); 8854 bi = &rx_ring->rx_buffer_info[i]; 8855 i -= rx_ring->count; 8856 8857 bufsz = igb_rx_bufsz(rx_ring); 8858 8859 do { 8860 if (!igb_alloc_mapped_page(rx_ring, bi)) 8861 break; 8862 8863 /* sync the buffer for use by the device */ 8864 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8865 bi->page_offset, bufsz, 8866 DMA_FROM_DEVICE); 8867 8868 /* Refresh the desc even if buffer_addrs didn't change 8869 * because each write-back erases this info. 8870 */ 8871 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8872 8873 rx_desc++; 8874 bi++; 8875 i++; 8876 if (unlikely(!i)) { 8877 rx_desc = IGB_RX_DESC(rx_ring, 0); 8878 bi = rx_ring->rx_buffer_info; 8879 i -= rx_ring->count; 8880 } 8881 8882 /* clear the length for the next_to_use descriptor */ 8883 rx_desc->wb.upper.length = 0; 8884 8885 cleaned_count--; 8886 } while (cleaned_count); 8887 8888 i += rx_ring->count; 8889 8890 if (rx_ring->next_to_use != i) { 8891 /* record the next descriptor to use */ 8892 rx_ring->next_to_use = i; 8893 8894 /* update next to alloc since we have filled the ring */ 8895 rx_ring->next_to_alloc = i; 8896 8897 /* Force memory writes to complete before letting h/w 8898 * know there are new descriptors to fetch. (Only 8899 * applicable for weak-ordered memory model archs, 8900 * such as IA-64). 8901 */ 8902 dma_wmb(); 8903 writel(i, rx_ring->tail); 8904 } 8905 } 8906 8907 /** 8908 * igb_mii_ioctl - 8909 * @netdev: pointer to netdev struct 8910 * @ifr: interface structure 8911 * @cmd: ioctl command to execute 8912 **/ 8913 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8914 { 8915 struct igb_adapter *adapter = netdev_priv(netdev); 8916 struct mii_ioctl_data *data = if_mii(ifr); 8917 8918 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8919 return -EOPNOTSUPP; 8920 8921 switch (cmd) { 8922 case SIOCGMIIPHY: 8923 data->phy_id = adapter->hw.phy.addr; 8924 break; 8925 case SIOCGMIIREG: 8926 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8927 &data->val_out)) 8928 return -EIO; 8929 break; 8930 case SIOCSMIIREG: 8931 default: 8932 return -EOPNOTSUPP; 8933 } 8934 return 0; 8935 } 8936 8937 /** 8938 * igb_ioctl - 8939 * @netdev: pointer to netdev struct 8940 * @ifr: interface structure 8941 * @cmd: ioctl command to execute 8942 **/ 8943 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8944 { 8945 switch (cmd) { 8946 case SIOCGMIIPHY: 8947 case SIOCGMIIREG: 8948 case SIOCSMIIREG: 8949 return igb_mii_ioctl(netdev, ifr, cmd); 8950 case SIOCGHWTSTAMP: 8951 return igb_ptp_get_ts_config(netdev, ifr); 8952 case SIOCSHWTSTAMP: 8953 return igb_ptp_set_ts_config(netdev, ifr); 8954 default: 8955 return -EOPNOTSUPP; 8956 } 8957 } 8958 8959 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8960 { 8961 struct igb_adapter *adapter = hw->back; 8962 8963 pci_read_config_word(adapter->pdev, reg, value); 8964 } 8965 8966 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8967 { 8968 struct igb_adapter *adapter = hw->back; 8969 8970 pci_write_config_word(adapter->pdev, reg, *value); 8971 } 8972 8973 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8974 { 8975 struct igb_adapter *adapter = hw->back; 8976 8977 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8978 return -E1000_ERR_CONFIG; 8979 8980 return 0; 8981 } 8982 8983 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8984 { 8985 struct igb_adapter *adapter = hw->back; 8986 8987 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8988 return -E1000_ERR_CONFIG; 8989 8990 return 0; 8991 } 8992 8993 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8994 { 8995 struct igb_adapter *adapter = netdev_priv(netdev); 8996 struct e1000_hw *hw = &adapter->hw; 8997 u32 ctrl, rctl; 8998 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8999 9000 if (enable) { 9001 /* enable VLAN tag insert/strip */ 9002 ctrl = rd32(E1000_CTRL); 9003 ctrl |= E1000_CTRL_VME; 9004 wr32(E1000_CTRL, ctrl); 9005 9006 /* Disable CFI check */ 9007 rctl = rd32(E1000_RCTL); 9008 rctl &= ~E1000_RCTL_CFIEN; 9009 wr32(E1000_RCTL, rctl); 9010 } else { 9011 /* disable VLAN tag insert/strip */ 9012 ctrl = rd32(E1000_CTRL); 9013 ctrl &= ~E1000_CTRL_VME; 9014 wr32(E1000_CTRL, ctrl); 9015 } 9016 9017 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9018 } 9019 9020 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9021 __be16 proto, u16 vid) 9022 { 9023 struct igb_adapter *adapter = netdev_priv(netdev); 9024 struct e1000_hw *hw = &adapter->hw; 9025 int pf_id = adapter->vfs_allocated_count; 9026 9027 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9028 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9029 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9030 9031 set_bit(vid, adapter->active_vlans); 9032 9033 return 0; 9034 } 9035 9036 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9037 __be16 proto, u16 vid) 9038 { 9039 struct igb_adapter *adapter = netdev_priv(netdev); 9040 int pf_id = adapter->vfs_allocated_count; 9041 struct e1000_hw *hw = &adapter->hw; 9042 9043 /* remove VID from filter table */ 9044 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9045 igb_vfta_set(hw, vid, pf_id, false, true); 9046 9047 clear_bit(vid, adapter->active_vlans); 9048 9049 return 0; 9050 } 9051 9052 static void igb_restore_vlan(struct igb_adapter *adapter) 9053 { 9054 u16 vid = 1; 9055 9056 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9057 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9058 9059 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9060 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9061 } 9062 9063 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9064 { 9065 struct pci_dev *pdev = adapter->pdev; 9066 struct e1000_mac_info *mac = &adapter->hw.mac; 9067 9068 mac->autoneg = 0; 9069 9070 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9071 * for the switch() below to work 9072 */ 9073 if ((spd & 1) || (dplx & ~1)) 9074 goto err_inval; 9075 9076 /* Fiber NIC's only allow 1000 gbps Full duplex 9077 * and 100Mbps Full duplex for 100baseFx sfp 9078 */ 9079 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9080 switch (spd + dplx) { 9081 case SPEED_10 + DUPLEX_HALF: 9082 case SPEED_10 + DUPLEX_FULL: 9083 case SPEED_100 + DUPLEX_HALF: 9084 goto err_inval; 9085 default: 9086 break; 9087 } 9088 } 9089 9090 switch (spd + dplx) { 9091 case SPEED_10 + DUPLEX_HALF: 9092 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9093 break; 9094 case SPEED_10 + DUPLEX_FULL: 9095 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9096 break; 9097 case SPEED_100 + DUPLEX_HALF: 9098 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9099 break; 9100 case SPEED_100 + DUPLEX_FULL: 9101 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9102 break; 9103 case SPEED_1000 + DUPLEX_FULL: 9104 mac->autoneg = 1; 9105 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9106 break; 9107 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9108 default: 9109 goto err_inval; 9110 } 9111 9112 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9113 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9114 9115 return 0; 9116 9117 err_inval: 9118 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9119 return -EINVAL; 9120 } 9121 9122 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9123 bool runtime) 9124 { 9125 struct net_device *netdev = pci_get_drvdata(pdev); 9126 struct igb_adapter *adapter = netdev_priv(netdev); 9127 struct e1000_hw *hw = &adapter->hw; 9128 u32 ctrl, rctl, status; 9129 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9130 bool wake; 9131 9132 rtnl_lock(); 9133 netif_device_detach(netdev); 9134 9135 if (netif_running(netdev)) 9136 __igb_close(netdev, true); 9137 9138 igb_ptp_suspend(adapter); 9139 9140 igb_clear_interrupt_scheme(adapter); 9141 rtnl_unlock(); 9142 9143 status = rd32(E1000_STATUS); 9144 if (status & E1000_STATUS_LU) 9145 wufc &= ~E1000_WUFC_LNKC; 9146 9147 if (wufc) { 9148 igb_setup_rctl(adapter); 9149 igb_set_rx_mode(netdev); 9150 9151 /* turn on all-multi mode if wake on multicast is enabled */ 9152 if (wufc & E1000_WUFC_MC) { 9153 rctl = rd32(E1000_RCTL); 9154 rctl |= E1000_RCTL_MPE; 9155 wr32(E1000_RCTL, rctl); 9156 } 9157 9158 ctrl = rd32(E1000_CTRL); 9159 ctrl |= E1000_CTRL_ADVD3WUC; 9160 wr32(E1000_CTRL, ctrl); 9161 9162 /* Allow time for pending master requests to run */ 9163 igb_disable_pcie_master(hw); 9164 9165 wr32(E1000_WUC, E1000_WUC_PME_EN); 9166 wr32(E1000_WUFC, wufc); 9167 } else { 9168 wr32(E1000_WUC, 0); 9169 wr32(E1000_WUFC, 0); 9170 } 9171 9172 wake = wufc || adapter->en_mng_pt; 9173 if (!wake) 9174 igb_power_down_link(adapter); 9175 else 9176 igb_power_up_link(adapter); 9177 9178 if (enable_wake) 9179 *enable_wake = wake; 9180 9181 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9182 * would have already happened in close and is redundant. 9183 */ 9184 igb_release_hw_control(adapter); 9185 9186 pci_disable_device(pdev); 9187 9188 return 0; 9189 } 9190 9191 static void igb_deliver_wake_packet(struct net_device *netdev) 9192 { 9193 struct igb_adapter *adapter = netdev_priv(netdev); 9194 struct e1000_hw *hw = &adapter->hw; 9195 struct sk_buff *skb; 9196 u32 wupl; 9197 9198 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9199 9200 /* WUPM stores only the first 128 bytes of the wake packet. 9201 * Read the packet only if we have the whole thing. 9202 */ 9203 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9204 return; 9205 9206 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9207 if (!skb) 9208 return; 9209 9210 skb_put(skb, wupl); 9211 9212 /* Ensure reads are 32-bit aligned */ 9213 wupl = roundup(wupl, 4); 9214 9215 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9216 9217 skb->protocol = eth_type_trans(skb, netdev); 9218 netif_rx(skb); 9219 } 9220 9221 static int __maybe_unused igb_suspend(struct device *dev) 9222 { 9223 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9224 } 9225 9226 static int __maybe_unused igb_resume(struct device *dev) 9227 { 9228 struct pci_dev *pdev = to_pci_dev(dev); 9229 struct net_device *netdev = pci_get_drvdata(pdev); 9230 struct igb_adapter *adapter = netdev_priv(netdev); 9231 struct e1000_hw *hw = &adapter->hw; 9232 u32 err, val; 9233 9234 pci_set_power_state(pdev, PCI_D0); 9235 pci_restore_state(pdev); 9236 pci_save_state(pdev); 9237 9238 if (!pci_device_is_present(pdev)) 9239 return -ENODEV; 9240 err = pci_enable_device_mem(pdev); 9241 if (err) { 9242 dev_err(&pdev->dev, 9243 "igb: Cannot enable PCI device from suspend\n"); 9244 return err; 9245 } 9246 pci_set_master(pdev); 9247 9248 pci_enable_wake(pdev, PCI_D3hot, 0); 9249 pci_enable_wake(pdev, PCI_D3cold, 0); 9250 9251 if (igb_init_interrupt_scheme(adapter, true)) { 9252 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9253 return -ENOMEM; 9254 } 9255 9256 igb_reset(adapter); 9257 9258 /* let the f/w know that the h/w is now under the control of the 9259 * driver. 9260 */ 9261 igb_get_hw_control(adapter); 9262 9263 val = rd32(E1000_WUS); 9264 if (val & WAKE_PKT_WUS) 9265 igb_deliver_wake_packet(netdev); 9266 9267 wr32(E1000_WUS, ~0); 9268 9269 rtnl_lock(); 9270 if (!err && netif_running(netdev)) 9271 err = __igb_open(netdev, true); 9272 9273 if (!err) 9274 netif_device_attach(netdev); 9275 rtnl_unlock(); 9276 9277 return err; 9278 } 9279 9280 static int __maybe_unused igb_runtime_idle(struct device *dev) 9281 { 9282 struct net_device *netdev = dev_get_drvdata(dev); 9283 struct igb_adapter *adapter = netdev_priv(netdev); 9284 9285 if (!igb_has_link(adapter)) 9286 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9287 9288 return -EBUSY; 9289 } 9290 9291 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9292 { 9293 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9294 } 9295 9296 static int __maybe_unused igb_runtime_resume(struct device *dev) 9297 { 9298 return igb_resume(dev); 9299 } 9300 9301 static void igb_shutdown(struct pci_dev *pdev) 9302 { 9303 bool wake; 9304 9305 __igb_shutdown(pdev, &wake, 0); 9306 9307 if (system_state == SYSTEM_POWER_OFF) { 9308 pci_wake_from_d3(pdev, wake); 9309 pci_set_power_state(pdev, PCI_D3hot); 9310 } 9311 } 9312 9313 #ifdef CONFIG_PCI_IOV 9314 static int igb_sriov_reinit(struct pci_dev *dev) 9315 { 9316 struct net_device *netdev = pci_get_drvdata(dev); 9317 struct igb_adapter *adapter = netdev_priv(netdev); 9318 struct pci_dev *pdev = adapter->pdev; 9319 9320 rtnl_lock(); 9321 9322 if (netif_running(netdev)) 9323 igb_close(netdev); 9324 else 9325 igb_reset(adapter); 9326 9327 igb_clear_interrupt_scheme(adapter); 9328 9329 igb_init_queue_configuration(adapter); 9330 9331 if (igb_init_interrupt_scheme(adapter, true)) { 9332 rtnl_unlock(); 9333 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9334 return -ENOMEM; 9335 } 9336 9337 if (netif_running(netdev)) 9338 igb_open(netdev); 9339 9340 rtnl_unlock(); 9341 9342 return 0; 9343 } 9344 9345 static int igb_pci_disable_sriov(struct pci_dev *dev) 9346 { 9347 int err = igb_disable_sriov(dev); 9348 9349 if (!err) 9350 err = igb_sriov_reinit(dev); 9351 9352 return err; 9353 } 9354 9355 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9356 { 9357 int err = igb_enable_sriov(dev, num_vfs); 9358 9359 if (err) 9360 goto out; 9361 9362 err = igb_sriov_reinit(dev); 9363 if (!err) 9364 return num_vfs; 9365 9366 out: 9367 return err; 9368 } 9369 9370 #endif 9371 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9372 { 9373 #ifdef CONFIG_PCI_IOV 9374 if (num_vfs == 0) 9375 return igb_pci_disable_sriov(dev); 9376 else 9377 return igb_pci_enable_sriov(dev, num_vfs); 9378 #endif 9379 return 0; 9380 } 9381 9382 /** 9383 * igb_io_error_detected - called when PCI error is detected 9384 * @pdev: Pointer to PCI device 9385 * @state: The current pci connection state 9386 * 9387 * This function is called after a PCI bus error affecting 9388 * this device has been detected. 9389 **/ 9390 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9391 pci_channel_state_t state) 9392 { 9393 struct net_device *netdev = pci_get_drvdata(pdev); 9394 struct igb_adapter *adapter = netdev_priv(netdev); 9395 9396 netif_device_detach(netdev); 9397 9398 if (state == pci_channel_io_perm_failure) 9399 return PCI_ERS_RESULT_DISCONNECT; 9400 9401 if (netif_running(netdev)) 9402 igb_down(adapter); 9403 pci_disable_device(pdev); 9404 9405 /* Request a slot slot reset. */ 9406 return PCI_ERS_RESULT_NEED_RESET; 9407 } 9408 9409 /** 9410 * igb_io_slot_reset - called after the pci bus has been reset. 9411 * @pdev: Pointer to PCI device 9412 * 9413 * Restart the card from scratch, as if from a cold-boot. Implementation 9414 * resembles the first-half of the igb_resume routine. 9415 **/ 9416 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9417 { 9418 struct net_device *netdev = pci_get_drvdata(pdev); 9419 struct igb_adapter *adapter = netdev_priv(netdev); 9420 struct e1000_hw *hw = &adapter->hw; 9421 pci_ers_result_t result; 9422 9423 if (pci_enable_device_mem(pdev)) { 9424 dev_err(&pdev->dev, 9425 "Cannot re-enable PCI device after reset.\n"); 9426 result = PCI_ERS_RESULT_DISCONNECT; 9427 } else { 9428 pci_set_master(pdev); 9429 pci_restore_state(pdev); 9430 pci_save_state(pdev); 9431 9432 pci_enable_wake(pdev, PCI_D3hot, 0); 9433 pci_enable_wake(pdev, PCI_D3cold, 0); 9434 9435 /* In case of PCI error, adapter lose its HW address 9436 * so we should re-assign it here. 9437 */ 9438 hw->hw_addr = adapter->io_addr; 9439 9440 igb_reset(adapter); 9441 wr32(E1000_WUS, ~0); 9442 result = PCI_ERS_RESULT_RECOVERED; 9443 } 9444 9445 return result; 9446 } 9447 9448 /** 9449 * igb_io_resume - called when traffic can start flowing again. 9450 * @pdev: Pointer to PCI device 9451 * 9452 * This callback is called when the error recovery driver tells us that 9453 * its OK to resume normal operation. Implementation resembles the 9454 * second-half of the igb_resume routine. 9455 */ 9456 static void igb_io_resume(struct pci_dev *pdev) 9457 { 9458 struct net_device *netdev = pci_get_drvdata(pdev); 9459 struct igb_adapter *adapter = netdev_priv(netdev); 9460 9461 if (netif_running(netdev)) { 9462 if (igb_up(adapter)) { 9463 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9464 return; 9465 } 9466 } 9467 9468 netif_device_attach(netdev); 9469 9470 /* let the f/w know that the h/w is now under the control of the 9471 * driver. 9472 */ 9473 igb_get_hw_control(adapter); 9474 } 9475 9476 /** 9477 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9478 * @adapter: Pointer to adapter structure 9479 * @index: Index of the RAR entry which need to be synced with MAC table 9480 **/ 9481 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9482 { 9483 struct e1000_hw *hw = &adapter->hw; 9484 u32 rar_low, rar_high; 9485 u8 *addr = adapter->mac_table[index].addr; 9486 9487 /* HW expects these to be in network order when they are plugged 9488 * into the registers which are little endian. In order to guarantee 9489 * that ordering we need to do an leXX_to_cpup here in order to be 9490 * ready for the byteswap that occurs with writel 9491 */ 9492 rar_low = le32_to_cpup((__le32 *)(addr)); 9493 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9494 9495 /* Indicate to hardware the Address is Valid. */ 9496 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9497 if (is_valid_ether_addr(addr)) 9498 rar_high |= E1000_RAH_AV; 9499 9500 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9501 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9502 9503 switch (hw->mac.type) { 9504 case e1000_82575: 9505 case e1000_i210: 9506 if (adapter->mac_table[index].state & 9507 IGB_MAC_STATE_QUEUE_STEERING) 9508 rar_high |= E1000_RAH_QSEL_ENABLE; 9509 9510 rar_high |= E1000_RAH_POOL_1 * 9511 adapter->mac_table[index].queue; 9512 break; 9513 default: 9514 rar_high |= E1000_RAH_POOL_1 << 9515 adapter->mac_table[index].queue; 9516 break; 9517 } 9518 } 9519 9520 wr32(E1000_RAL(index), rar_low); 9521 wrfl(); 9522 wr32(E1000_RAH(index), rar_high); 9523 wrfl(); 9524 } 9525 9526 static int igb_set_vf_mac(struct igb_adapter *adapter, 9527 int vf, unsigned char *mac_addr) 9528 { 9529 struct e1000_hw *hw = &adapter->hw; 9530 /* VF MAC addresses start at end of receive addresses and moves 9531 * towards the first, as a result a collision should not be possible 9532 */ 9533 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9534 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9535 9536 ether_addr_copy(vf_mac_addr, mac_addr); 9537 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9538 adapter->mac_table[rar_entry].queue = vf; 9539 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9540 igb_rar_set_index(adapter, rar_entry); 9541 9542 return 0; 9543 } 9544 9545 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9546 { 9547 struct igb_adapter *adapter = netdev_priv(netdev); 9548 9549 if (vf >= adapter->vfs_allocated_count) 9550 return -EINVAL; 9551 9552 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9553 * flag and allows to overwrite the MAC via VF netdev. This 9554 * is necessary to allow libvirt a way to restore the original 9555 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9556 * down a VM. 9557 */ 9558 if (is_zero_ether_addr(mac)) { 9559 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9560 dev_info(&adapter->pdev->dev, 9561 "remove administratively set MAC on VF %d\n", 9562 vf); 9563 } else if (is_valid_ether_addr(mac)) { 9564 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9565 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9566 mac, vf); 9567 dev_info(&adapter->pdev->dev, 9568 "Reload the VF driver to make this change effective."); 9569 /* Generate additional warning if PF is down */ 9570 if (test_bit(__IGB_DOWN, &adapter->state)) { 9571 dev_warn(&adapter->pdev->dev, 9572 "The VF MAC address has been set, but the PF device is not up.\n"); 9573 dev_warn(&adapter->pdev->dev, 9574 "Bring the PF device up before attempting to use the VF device.\n"); 9575 } 9576 } else { 9577 return -EINVAL; 9578 } 9579 return igb_set_vf_mac(adapter, vf, mac); 9580 } 9581 9582 static int igb_link_mbps(int internal_link_speed) 9583 { 9584 switch (internal_link_speed) { 9585 case SPEED_100: 9586 return 100; 9587 case SPEED_1000: 9588 return 1000; 9589 default: 9590 return 0; 9591 } 9592 } 9593 9594 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9595 int link_speed) 9596 { 9597 int rf_dec, rf_int; 9598 u32 bcnrc_val; 9599 9600 if (tx_rate != 0) { 9601 /* Calculate the rate factor values to set */ 9602 rf_int = link_speed / tx_rate; 9603 rf_dec = (link_speed - (rf_int * tx_rate)); 9604 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9605 tx_rate; 9606 9607 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9608 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9609 E1000_RTTBCNRC_RF_INT_MASK); 9610 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9611 } else { 9612 bcnrc_val = 0; 9613 } 9614 9615 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9616 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9617 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9618 */ 9619 wr32(E1000_RTTBCNRM, 0x14); 9620 wr32(E1000_RTTBCNRC, bcnrc_val); 9621 } 9622 9623 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9624 { 9625 int actual_link_speed, i; 9626 bool reset_rate = false; 9627 9628 /* VF TX rate limit was not set or not supported */ 9629 if ((adapter->vf_rate_link_speed == 0) || 9630 (adapter->hw.mac.type != e1000_82576)) 9631 return; 9632 9633 actual_link_speed = igb_link_mbps(adapter->link_speed); 9634 if (actual_link_speed != adapter->vf_rate_link_speed) { 9635 reset_rate = true; 9636 adapter->vf_rate_link_speed = 0; 9637 dev_info(&adapter->pdev->dev, 9638 "Link speed has been changed. VF Transmit rate is disabled\n"); 9639 } 9640 9641 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9642 if (reset_rate) 9643 adapter->vf_data[i].tx_rate = 0; 9644 9645 igb_set_vf_rate_limit(&adapter->hw, i, 9646 adapter->vf_data[i].tx_rate, 9647 actual_link_speed); 9648 } 9649 } 9650 9651 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9652 int min_tx_rate, int max_tx_rate) 9653 { 9654 struct igb_adapter *adapter = netdev_priv(netdev); 9655 struct e1000_hw *hw = &adapter->hw; 9656 int actual_link_speed; 9657 9658 if (hw->mac.type != e1000_82576) 9659 return -EOPNOTSUPP; 9660 9661 if (min_tx_rate) 9662 return -EINVAL; 9663 9664 actual_link_speed = igb_link_mbps(adapter->link_speed); 9665 if ((vf >= adapter->vfs_allocated_count) || 9666 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9667 (max_tx_rate < 0) || 9668 (max_tx_rate > actual_link_speed)) 9669 return -EINVAL; 9670 9671 adapter->vf_rate_link_speed = actual_link_speed; 9672 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9673 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9674 9675 return 0; 9676 } 9677 9678 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9679 bool setting) 9680 { 9681 struct igb_adapter *adapter = netdev_priv(netdev); 9682 struct e1000_hw *hw = &adapter->hw; 9683 u32 reg_val, reg_offset; 9684 9685 if (!adapter->vfs_allocated_count) 9686 return -EOPNOTSUPP; 9687 9688 if (vf >= adapter->vfs_allocated_count) 9689 return -EINVAL; 9690 9691 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9692 reg_val = rd32(reg_offset); 9693 if (setting) 9694 reg_val |= (BIT(vf) | 9695 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9696 else 9697 reg_val &= ~(BIT(vf) | 9698 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9699 wr32(reg_offset, reg_val); 9700 9701 adapter->vf_data[vf].spoofchk_enabled = setting; 9702 return 0; 9703 } 9704 9705 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9706 { 9707 struct igb_adapter *adapter = netdev_priv(netdev); 9708 9709 if (vf >= adapter->vfs_allocated_count) 9710 return -EINVAL; 9711 if (adapter->vf_data[vf].trusted == setting) 9712 return 0; 9713 9714 adapter->vf_data[vf].trusted = setting; 9715 9716 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9717 vf, setting ? "" : "not "); 9718 return 0; 9719 } 9720 9721 static int igb_ndo_get_vf_config(struct net_device *netdev, 9722 int vf, struct ifla_vf_info *ivi) 9723 { 9724 struct igb_adapter *adapter = netdev_priv(netdev); 9725 if (vf >= adapter->vfs_allocated_count) 9726 return -EINVAL; 9727 ivi->vf = vf; 9728 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9729 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9730 ivi->min_tx_rate = 0; 9731 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9732 ivi->qos = adapter->vf_data[vf].pf_qos; 9733 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9734 ivi->trusted = adapter->vf_data[vf].trusted; 9735 return 0; 9736 } 9737 9738 static void igb_vmm_control(struct igb_adapter *adapter) 9739 { 9740 struct e1000_hw *hw = &adapter->hw; 9741 u32 reg; 9742 9743 switch (hw->mac.type) { 9744 case e1000_82575: 9745 case e1000_i210: 9746 case e1000_i211: 9747 case e1000_i354: 9748 default: 9749 /* replication is not supported for 82575 */ 9750 return; 9751 case e1000_82576: 9752 /* notify HW that the MAC is adding vlan tags */ 9753 reg = rd32(E1000_DTXCTL); 9754 reg |= E1000_DTXCTL_VLAN_ADDED; 9755 wr32(E1000_DTXCTL, reg); 9756 fallthrough; 9757 case e1000_82580: 9758 /* enable replication vlan tag stripping */ 9759 reg = rd32(E1000_RPLOLR); 9760 reg |= E1000_RPLOLR_STRVLAN; 9761 wr32(E1000_RPLOLR, reg); 9762 fallthrough; 9763 case e1000_i350: 9764 /* none of the above registers are supported by i350 */ 9765 break; 9766 } 9767 9768 if (adapter->vfs_allocated_count) { 9769 igb_vmdq_set_loopback_pf(hw, true); 9770 igb_vmdq_set_replication_pf(hw, true); 9771 igb_vmdq_set_anti_spoofing_pf(hw, true, 9772 adapter->vfs_allocated_count); 9773 } else { 9774 igb_vmdq_set_loopback_pf(hw, false); 9775 igb_vmdq_set_replication_pf(hw, false); 9776 } 9777 } 9778 9779 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9780 { 9781 struct e1000_hw *hw = &adapter->hw; 9782 u32 dmac_thr; 9783 u16 hwm; 9784 9785 if (hw->mac.type > e1000_82580) { 9786 if (adapter->flags & IGB_FLAG_DMAC) { 9787 u32 reg; 9788 9789 /* force threshold to 0. */ 9790 wr32(E1000_DMCTXTH, 0); 9791 9792 /* DMA Coalescing high water mark needs to be greater 9793 * than the Rx threshold. Set hwm to PBA - max frame 9794 * size in 16B units, capping it at PBA - 6KB. 9795 */ 9796 hwm = 64 * (pba - 6); 9797 reg = rd32(E1000_FCRTC); 9798 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9799 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9800 & E1000_FCRTC_RTH_COAL_MASK); 9801 wr32(E1000_FCRTC, reg); 9802 9803 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9804 * frame size, capping it at PBA - 10KB. 9805 */ 9806 dmac_thr = pba - 10; 9807 reg = rd32(E1000_DMACR); 9808 reg &= ~E1000_DMACR_DMACTHR_MASK; 9809 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9810 & E1000_DMACR_DMACTHR_MASK); 9811 9812 /* transition to L0x or L1 if available..*/ 9813 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9814 9815 /* watchdog timer= +-1000 usec in 32usec intervals */ 9816 reg |= (1000 >> 5); 9817 9818 /* Disable BMC-to-OS Watchdog Enable */ 9819 if (hw->mac.type != e1000_i354) 9820 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9821 9822 wr32(E1000_DMACR, reg); 9823 9824 /* no lower threshold to disable 9825 * coalescing(smart fifb)-UTRESH=0 9826 */ 9827 wr32(E1000_DMCRTRH, 0); 9828 9829 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9830 9831 wr32(E1000_DMCTLX, reg); 9832 9833 /* free space in tx packet buffer to wake from 9834 * DMA coal 9835 */ 9836 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9837 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9838 9839 /* make low power state decision controlled 9840 * by DMA coal 9841 */ 9842 reg = rd32(E1000_PCIEMISC); 9843 reg &= ~E1000_PCIEMISC_LX_DECISION; 9844 wr32(E1000_PCIEMISC, reg); 9845 } /* endif adapter->dmac is not disabled */ 9846 } else if (hw->mac.type == e1000_82580) { 9847 u32 reg = rd32(E1000_PCIEMISC); 9848 9849 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9850 wr32(E1000_DMACR, 0); 9851 } 9852 } 9853 9854 /** 9855 * igb_read_i2c_byte - Reads 8 bit word over I2C 9856 * @hw: pointer to hardware structure 9857 * @byte_offset: byte offset to read 9858 * @dev_addr: device address 9859 * @data: value read 9860 * 9861 * Performs byte read operation over I2C interface at 9862 * a specified device address. 9863 **/ 9864 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9865 u8 dev_addr, u8 *data) 9866 { 9867 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9868 struct i2c_client *this_client = adapter->i2c_client; 9869 s32 status; 9870 u16 swfw_mask = 0; 9871 9872 if (!this_client) 9873 return E1000_ERR_I2C; 9874 9875 swfw_mask = E1000_SWFW_PHY0_SM; 9876 9877 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9878 return E1000_ERR_SWFW_SYNC; 9879 9880 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9881 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9882 9883 if (status < 0) 9884 return E1000_ERR_I2C; 9885 else { 9886 *data = status; 9887 return 0; 9888 } 9889 } 9890 9891 /** 9892 * igb_write_i2c_byte - Writes 8 bit word over I2C 9893 * @hw: pointer to hardware structure 9894 * @byte_offset: byte offset to write 9895 * @dev_addr: device address 9896 * @data: value to write 9897 * 9898 * Performs byte write operation over I2C interface at 9899 * a specified device address. 9900 **/ 9901 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9902 u8 dev_addr, u8 data) 9903 { 9904 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9905 struct i2c_client *this_client = adapter->i2c_client; 9906 s32 status; 9907 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9908 9909 if (!this_client) 9910 return E1000_ERR_I2C; 9911 9912 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9913 return E1000_ERR_SWFW_SYNC; 9914 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9915 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9916 9917 if (status) 9918 return E1000_ERR_I2C; 9919 else 9920 return 0; 9921 9922 } 9923 9924 int igb_reinit_queues(struct igb_adapter *adapter) 9925 { 9926 struct net_device *netdev = adapter->netdev; 9927 struct pci_dev *pdev = adapter->pdev; 9928 int err = 0; 9929 9930 if (netif_running(netdev)) 9931 igb_close(netdev); 9932 9933 igb_reset_interrupt_capability(adapter); 9934 9935 if (igb_init_interrupt_scheme(adapter, true)) { 9936 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9937 return -ENOMEM; 9938 } 9939 9940 if (netif_running(netdev)) 9941 err = igb_open(netdev); 9942 9943 return err; 9944 } 9945 9946 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9947 { 9948 struct igb_nfc_filter *rule; 9949 9950 spin_lock(&adapter->nfc_lock); 9951 9952 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9953 igb_erase_filter(adapter, rule); 9954 9955 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9956 igb_erase_filter(adapter, rule); 9957 9958 spin_unlock(&adapter->nfc_lock); 9959 } 9960 9961 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9962 { 9963 struct igb_nfc_filter *rule; 9964 9965 spin_lock(&adapter->nfc_lock); 9966 9967 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9968 igb_add_filter(adapter, rule); 9969 9970 spin_unlock(&adapter->nfc_lock); 9971 } 9972 /* igb_main.c */ 9973