1 /* Intel(R) Gigabit Ethernet Linux driver
2  * Copyright(c) 2007-2014 Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, see <http://www.gnu.org/licenses/>.
15  *
16  * The full GNU General Public License is included in this distribution in
17  * the file called "COPYING".
18  *
19  * Contact Information:
20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22  */
23 
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58 
59 #define MAJ 5
60 #define MIN 3
61 #define BUILD 0
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 				"Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 				"Copyright (c) 2007-2014 Intel Corporation.";
70 
71 static const struct e1000_info *igb_info_tbl[] = {
72 	[board_82575] = &e1000_82575_info,
73 };
74 
75 static const struct pci_device_id igb_pci_tbl[] = {
76 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 	/* required last entry */
112 	{0, }
113 };
114 
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116 
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 					  struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 			  netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 			       int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 				   bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 				 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178 
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 static int igb_disable_sriov(struct pci_dev *dev);
183 static int igb_pci_disable_sriov(struct pci_dev *dev);
184 #endif
185 
186 #ifdef CONFIG_PM
187 #ifdef CONFIG_PM_SLEEP
188 static int igb_suspend(struct device *);
189 #endif
190 static int igb_resume(struct device *);
191 static int igb_runtime_suspend(struct device *dev);
192 static int igb_runtime_resume(struct device *dev);
193 static int igb_runtime_idle(struct device *dev);
194 static const struct dev_pm_ops igb_pm_ops = {
195 	SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 	SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 			igb_runtime_idle)
198 };
199 #endif
200 static void igb_shutdown(struct pci_dev *);
201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202 #ifdef CONFIG_IGB_DCA
203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204 static struct notifier_block dca_notifier = {
205 	.notifier_call	= igb_notify_dca,
206 	.next		= NULL,
207 	.priority	= 0
208 };
209 #endif
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
212 static void igb_netpoll(struct net_device *);
213 #endif
214 #ifdef CONFIG_PCI_IOV
215 static unsigned int max_vfs;
216 module_param(max_vfs, uint, 0);
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218 #endif /* CONFIG_PCI_IOV */
219 
220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 		     pci_channel_state_t);
222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223 static void igb_io_resume(struct pci_dev *);
224 
225 static const struct pci_error_handlers igb_err_handler = {
226 	.error_detected = igb_io_error_detected,
227 	.slot_reset = igb_io_slot_reset,
228 	.resume = igb_io_resume,
229 };
230 
231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
232 
233 static struct pci_driver igb_driver = {
234 	.name     = igb_driver_name,
235 	.id_table = igb_pci_tbl,
236 	.probe    = igb_probe,
237 	.remove   = igb_remove,
238 #ifdef CONFIG_PM
239 	.driver.pm = &igb_pm_ops,
240 #endif
241 	.shutdown = igb_shutdown,
242 	.sriov_configure = igb_pci_sriov_configure,
243 	.err_handler = &igb_err_handler
244 };
245 
246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248 MODULE_LICENSE("GPL");
249 MODULE_VERSION(DRV_VERSION);
250 
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252 static int debug = -1;
253 module_param(debug, int, 0);
254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255 
256 struct igb_reg_info {
257 	u32 ofs;
258 	char *name;
259 };
260 
261 static const struct igb_reg_info igb_reg_info_tbl[] = {
262 
263 	/* General Registers */
264 	{E1000_CTRL, "CTRL"},
265 	{E1000_STATUS, "STATUS"},
266 	{E1000_CTRL_EXT, "CTRL_EXT"},
267 
268 	/* Interrupt Registers */
269 	{E1000_ICR, "ICR"},
270 
271 	/* RX Registers */
272 	{E1000_RCTL, "RCTL"},
273 	{E1000_RDLEN(0), "RDLEN"},
274 	{E1000_RDH(0), "RDH"},
275 	{E1000_RDT(0), "RDT"},
276 	{E1000_RXDCTL(0), "RXDCTL"},
277 	{E1000_RDBAL(0), "RDBAL"},
278 	{E1000_RDBAH(0), "RDBAH"},
279 
280 	/* TX Registers */
281 	{E1000_TCTL, "TCTL"},
282 	{E1000_TDBAL(0), "TDBAL"},
283 	{E1000_TDBAH(0), "TDBAH"},
284 	{E1000_TDLEN(0), "TDLEN"},
285 	{E1000_TDH(0), "TDH"},
286 	{E1000_TDT(0), "TDT"},
287 	{E1000_TXDCTL(0), "TXDCTL"},
288 	{E1000_TDFH, "TDFH"},
289 	{E1000_TDFT, "TDFT"},
290 	{E1000_TDFHS, "TDFHS"},
291 	{E1000_TDFPC, "TDFPC"},
292 
293 	/* List Terminator */
294 	{}
295 };
296 
297 /* igb_regdump - register printout routine */
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299 {
300 	int n = 0;
301 	char rname[16];
302 	u32 regs[8];
303 
304 	switch (reginfo->ofs) {
305 	case E1000_RDLEN(0):
306 		for (n = 0; n < 4; n++)
307 			regs[n] = rd32(E1000_RDLEN(n));
308 		break;
309 	case E1000_RDH(0):
310 		for (n = 0; n < 4; n++)
311 			regs[n] = rd32(E1000_RDH(n));
312 		break;
313 	case E1000_RDT(0):
314 		for (n = 0; n < 4; n++)
315 			regs[n] = rd32(E1000_RDT(n));
316 		break;
317 	case E1000_RXDCTL(0):
318 		for (n = 0; n < 4; n++)
319 			regs[n] = rd32(E1000_RXDCTL(n));
320 		break;
321 	case E1000_RDBAL(0):
322 		for (n = 0; n < 4; n++)
323 			regs[n] = rd32(E1000_RDBAL(n));
324 		break;
325 	case E1000_RDBAH(0):
326 		for (n = 0; n < 4; n++)
327 			regs[n] = rd32(E1000_RDBAH(n));
328 		break;
329 	case E1000_TDBAL(0):
330 		for (n = 0; n < 4; n++)
331 			regs[n] = rd32(E1000_RDBAL(n));
332 		break;
333 	case E1000_TDBAH(0):
334 		for (n = 0; n < 4; n++)
335 			regs[n] = rd32(E1000_TDBAH(n));
336 		break;
337 	case E1000_TDLEN(0):
338 		for (n = 0; n < 4; n++)
339 			regs[n] = rd32(E1000_TDLEN(n));
340 		break;
341 	case E1000_TDH(0):
342 		for (n = 0; n < 4; n++)
343 			regs[n] = rd32(E1000_TDH(n));
344 		break;
345 	case E1000_TDT(0):
346 		for (n = 0; n < 4; n++)
347 			regs[n] = rd32(E1000_TDT(n));
348 		break;
349 	case E1000_TXDCTL(0):
350 		for (n = 0; n < 4; n++)
351 			regs[n] = rd32(E1000_TXDCTL(n));
352 		break;
353 	default:
354 		pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
355 		return;
356 	}
357 
358 	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 	pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 		regs[2], regs[3]);
361 }
362 
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
364 static void igb_dump(struct igb_adapter *adapter)
365 {
366 	struct net_device *netdev = adapter->netdev;
367 	struct e1000_hw *hw = &adapter->hw;
368 	struct igb_reg_info *reginfo;
369 	struct igb_ring *tx_ring;
370 	union e1000_adv_tx_desc *tx_desc;
371 	struct my_u0 { u64 a; u64 b; } *u0;
372 	struct igb_ring *rx_ring;
373 	union e1000_adv_rx_desc *rx_desc;
374 	u32 staterr;
375 	u16 i, n;
376 
377 	if (!netif_msg_hw(adapter))
378 		return;
379 
380 	/* Print netdevice Info */
381 	if (netdev) {
382 		dev_info(&adapter->pdev->dev, "Net device Info\n");
383 		pr_info("Device Name     state            trans_start      last_rx\n");
384 		pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 			netdev->state, netdev->trans_start, netdev->last_rx);
386 	}
387 
388 	/* Print Registers */
389 	dev_info(&adapter->pdev->dev, "Register Dump\n");
390 	pr_info(" Register Name   Value\n");
391 	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 	     reginfo->name; reginfo++) {
393 		igb_regdump(hw, reginfo);
394 	}
395 
396 	/* Print TX Ring Summary */
397 	if (!netdev || !netif_running(netdev))
398 		goto exit;
399 
400 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 	pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
402 	for (n = 0; n < adapter->num_tx_queues; n++) {
403 		struct igb_tx_buffer *buffer_info;
404 		tx_ring = adapter->tx_ring[n];
405 		buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 		pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 			n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 			(u64)dma_unmap_addr(buffer_info, dma),
409 			dma_unmap_len(buffer_info, len),
410 			buffer_info->next_to_watch,
411 			(u64)buffer_info->time_stamp);
412 	}
413 
414 	/* Print TX Rings */
415 	if (!netif_msg_tx_done(adapter))
416 		goto rx_ring_summary;
417 
418 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419 
420 	/* Transmit Descriptor Formats
421 	 *
422 	 * Advanced Transmit Descriptor
423 	 *   +--------------------------------------------------------------+
424 	 * 0 |         Buffer Address [63:0]                                |
425 	 *   +--------------------------------------------------------------+
426 	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
427 	 *   +--------------------------------------------------------------+
428 	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
429 	 */
430 
431 	for (n = 0; n < adapter->num_tx_queues; n++) {
432 		tx_ring = adapter->tx_ring[n];
433 		pr_info("------------------------------------\n");
434 		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 		pr_info("------------------------------------\n");
436 		pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
437 
438 		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 			const char *next_desc;
440 			struct igb_tx_buffer *buffer_info;
441 			tx_desc = IGB_TX_DESC(tx_ring, i);
442 			buffer_info = &tx_ring->tx_buffer_info[i];
443 			u0 = (struct my_u0 *)tx_desc;
444 			if (i == tx_ring->next_to_use &&
445 			    i == tx_ring->next_to_clean)
446 				next_desc = " NTC/U";
447 			else if (i == tx_ring->next_to_use)
448 				next_desc = " NTU";
449 			else if (i == tx_ring->next_to_clean)
450 				next_desc = " NTC";
451 			else
452 				next_desc = "";
453 
454 			pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
455 				i, le64_to_cpu(u0->a),
456 				le64_to_cpu(u0->b),
457 				(u64)dma_unmap_addr(buffer_info, dma),
458 				dma_unmap_len(buffer_info, len),
459 				buffer_info->next_to_watch,
460 				(u64)buffer_info->time_stamp,
461 				buffer_info->skb, next_desc);
462 
463 			if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 				print_hex_dump(KERN_INFO, "",
465 					DUMP_PREFIX_ADDRESS,
466 					16, 1, buffer_info->skb->data,
467 					dma_unmap_len(buffer_info, len),
468 					true);
469 		}
470 	}
471 
472 	/* Print RX Rings Summary */
473 rx_ring_summary:
474 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 	pr_info("Queue [NTU] [NTC]\n");
476 	for (n = 0; n < adapter->num_rx_queues; n++) {
477 		rx_ring = adapter->rx_ring[n];
478 		pr_info(" %5d %5X %5X\n",
479 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
480 	}
481 
482 	/* Print RX Rings */
483 	if (!netif_msg_rx_status(adapter))
484 		goto exit;
485 
486 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487 
488 	/* Advanced Receive Descriptor (Read) Format
489 	 *    63                                           1        0
490 	 *    +-----------------------------------------------------+
491 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
492 	 *    +----------------------------------------------+------+
493 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
494 	 *    +-----------------------------------------------------+
495 	 *
496 	 *
497 	 * Advanced Receive Descriptor (Write-Back) Format
498 	 *
499 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
500 	 *   +------------------------------------------------------+
501 	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
502 	 *   | Checksum   Ident  |   |           |    | Type | Type |
503 	 *   +------------------------------------------------------+
504 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 	 *   +------------------------------------------------------+
506 	 *   63       48 47    32 31            20 19               0
507 	 */
508 
509 	for (n = 0; n < adapter->num_rx_queues; n++) {
510 		rx_ring = adapter->rx_ring[n];
511 		pr_info("------------------------------------\n");
512 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 		pr_info("------------------------------------\n");
514 		pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
515 		pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
516 
517 		for (i = 0; i < rx_ring->count; i++) {
518 			const char *next_desc;
519 			struct igb_rx_buffer *buffer_info;
520 			buffer_info = &rx_ring->rx_buffer_info[i];
521 			rx_desc = IGB_RX_DESC(rx_ring, i);
522 			u0 = (struct my_u0 *)rx_desc;
523 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
524 
525 			if (i == rx_ring->next_to_use)
526 				next_desc = " NTU";
527 			else if (i == rx_ring->next_to_clean)
528 				next_desc = " NTC";
529 			else
530 				next_desc = "";
531 
532 			if (staterr & E1000_RXD_STAT_DD) {
533 				/* Descriptor Done */
534 				pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
535 					"RWB", i,
536 					le64_to_cpu(u0->a),
537 					le64_to_cpu(u0->b),
538 					next_desc);
539 			} else {
540 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
541 					"R  ", i,
542 					le64_to_cpu(u0->a),
543 					le64_to_cpu(u0->b),
544 					(u64)buffer_info->dma,
545 					next_desc);
546 
547 				if (netif_msg_pktdata(adapter) &&
548 				    buffer_info->dma && buffer_info->page) {
549 					print_hex_dump(KERN_INFO, "",
550 					  DUMP_PREFIX_ADDRESS,
551 					  16, 1,
552 					  page_address(buffer_info->page) +
553 						      buffer_info->page_offset,
554 					  IGB_RX_BUFSZ, true);
555 				}
556 			}
557 		}
558 	}
559 
560 exit:
561 	return;
562 }
563 
564 /**
565  *  igb_get_i2c_data - Reads the I2C SDA data bit
566  *  @hw: pointer to hardware structure
567  *  @i2cctl: Current value of I2CCTL register
568  *
569  *  Returns the I2C data bit value
570  **/
571 static int igb_get_i2c_data(void *data)
572 {
573 	struct igb_adapter *adapter = (struct igb_adapter *)data;
574 	struct e1000_hw *hw = &adapter->hw;
575 	s32 i2cctl = rd32(E1000_I2CPARAMS);
576 
577 	return !!(i2cctl & E1000_I2C_DATA_IN);
578 }
579 
580 /**
581  *  igb_set_i2c_data - Sets the I2C data bit
582  *  @data: pointer to hardware structure
583  *  @state: I2C data value (0 or 1) to set
584  *
585  *  Sets the I2C data bit
586  **/
587 static void igb_set_i2c_data(void *data, int state)
588 {
589 	struct igb_adapter *adapter = (struct igb_adapter *)data;
590 	struct e1000_hw *hw = &adapter->hw;
591 	s32 i2cctl = rd32(E1000_I2CPARAMS);
592 
593 	if (state)
594 		i2cctl |= E1000_I2C_DATA_OUT;
595 	else
596 		i2cctl &= ~E1000_I2C_DATA_OUT;
597 
598 	i2cctl &= ~E1000_I2C_DATA_OE_N;
599 	i2cctl |= E1000_I2C_CLK_OE_N;
600 	wr32(E1000_I2CPARAMS, i2cctl);
601 	wrfl();
602 
603 }
604 
605 /**
606  *  igb_set_i2c_clk - Sets the I2C SCL clock
607  *  @data: pointer to hardware structure
608  *  @state: state to set clock
609  *
610  *  Sets the I2C clock line to state
611  **/
612 static void igb_set_i2c_clk(void *data, int state)
613 {
614 	struct igb_adapter *adapter = (struct igb_adapter *)data;
615 	struct e1000_hw *hw = &adapter->hw;
616 	s32 i2cctl = rd32(E1000_I2CPARAMS);
617 
618 	if (state) {
619 		i2cctl |= E1000_I2C_CLK_OUT;
620 		i2cctl &= ~E1000_I2C_CLK_OE_N;
621 	} else {
622 		i2cctl &= ~E1000_I2C_CLK_OUT;
623 		i2cctl &= ~E1000_I2C_CLK_OE_N;
624 	}
625 	wr32(E1000_I2CPARAMS, i2cctl);
626 	wrfl();
627 }
628 
629 /**
630  *  igb_get_i2c_clk - Gets the I2C SCL clock state
631  *  @data: pointer to hardware structure
632  *
633  *  Gets the I2C clock state
634  **/
635 static int igb_get_i2c_clk(void *data)
636 {
637 	struct igb_adapter *adapter = (struct igb_adapter *)data;
638 	struct e1000_hw *hw = &adapter->hw;
639 	s32 i2cctl = rd32(E1000_I2CPARAMS);
640 
641 	return !!(i2cctl & E1000_I2C_CLK_IN);
642 }
643 
644 static const struct i2c_algo_bit_data igb_i2c_algo = {
645 	.setsda		= igb_set_i2c_data,
646 	.setscl		= igb_set_i2c_clk,
647 	.getsda		= igb_get_i2c_data,
648 	.getscl		= igb_get_i2c_clk,
649 	.udelay		= 5,
650 	.timeout	= 20,
651 };
652 
653 /**
654  *  igb_get_hw_dev - return device
655  *  @hw: pointer to hardware structure
656  *
657  *  used by hardware layer to print debugging information
658  **/
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
660 {
661 	struct igb_adapter *adapter = hw->back;
662 	return adapter->netdev;
663 }
664 
665 /**
666  *  igb_init_module - Driver Registration Routine
667  *
668  *  igb_init_module is the first routine called when the driver is
669  *  loaded. All it does is register with the PCI subsystem.
670  **/
671 static int __init igb_init_module(void)
672 {
673 	int ret;
674 
675 	pr_info("%s - version %s\n",
676 	       igb_driver_string, igb_driver_version);
677 	pr_info("%s\n", igb_copyright);
678 
679 #ifdef CONFIG_IGB_DCA
680 	dca_register_notify(&dca_notifier);
681 #endif
682 	ret = pci_register_driver(&igb_driver);
683 	return ret;
684 }
685 
686 module_init(igb_init_module);
687 
688 /**
689  *  igb_exit_module - Driver Exit Cleanup Routine
690  *
691  *  igb_exit_module is called just before the driver is removed
692  *  from memory.
693  **/
694 static void __exit igb_exit_module(void)
695 {
696 #ifdef CONFIG_IGB_DCA
697 	dca_unregister_notify(&dca_notifier);
698 #endif
699 	pci_unregister_driver(&igb_driver);
700 }
701 
702 module_exit(igb_exit_module);
703 
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705 /**
706  *  igb_cache_ring_register - Descriptor ring to register mapping
707  *  @adapter: board private structure to initialize
708  *
709  *  Once we know the feature-set enabled for the device, we'll cache
710  *  the register offset the descriptor ring is assigned to.
711  **/
712 static void igb_cache_ring_register(struct igb_adapter *adapter)
713 {
714 	int i = 0, j = 0;
715 	u32 rbase_offset = adapter->vfs_allocated_count;
716 
717 	switch (adapter->hw.mac.type) {
718 	case e1000_82576:
719 		/* The queues are allocated for virtualization such that VF 0
720 		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 		 * In order to avoid collision we start at the first free queue
722 		 * and continue consuming queues in the same sequence
723 		 */
724 		if (adapter->vfs_allocated_count) {
725 			for (; i < adapter->rss_queues; i++)
726 				adapter->rx_ring[i]->reg_idx = rbase_offset +
727 							       Q_IDX_82576(i);
728 		}
729 		/* Fall through */
730 	case e1000_82575:
731 	case e1000_82580:
732 	case e1000_i350:
733 	case e1000_i354:
734 	case e1000_i210:
735 	case e1000_i211:
736 		/* Fall through */
737 	default:
738 		for (; i < adapter->num_rx_queues; i++)
739 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 		for (; j < adapter->num_tx_queues; j++)
741 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
742 		break;
743 	}
744 }
745 
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747 {
748 	struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 	u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 	u32 value = 0;
751 
752 	if (E1000_REMOVED(hw_addr))
753 		return ~value;
754 
755 	value = readl(&hw_addr[reg]);
756 
757 	/* reads should not return all F's */
758 	if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 		struct net_device *netdev = igb->netdev;
760 		hw->hw_addr = NULL;
761 		netif_device_detach(netdev);
762 		netdev_err(netdev, "PCIe link lost, device now detached\n");
763 	}
764 
765 	return value;
766 }
767 
768 /**
769  *  igb_write_ivar - configure ivar for given MSI-X vector
770  *  @hw: pointer to the HW structure
771  *  @msix_vector: vector number we are allocating to a given ring
772  *  @index: row index of IVAR register to write within IVAR table
773  *  @offset: column offset of in IVAR, should be multiple of 8
774  *
775  *  This function is intended to handle the writing of the IVAR register
776  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
777  *  each containing an cause allocation for an Rx and Tx ring, and a
778  *  variable number of rows depending on the number of queues supported.
779  **/
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 			   int index, int offset)
782 {
783 	u32 ivar = array_rd32(E1000_IVAR0, index);
784 
785 	/* clear any bits that are currently set */
786 	ivar &= ~((u32)0xFF << offset);
787 
788 	/* write vector and valid bit */
789 	ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790 
791 	array_wr32(E1000_IVAR0, index, ivar);
792 }
793 
794 #define IGB_N0_QUEUE -1
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
796 {
797 	struct igb_adapter *adapter = q_vector->adapter;
798 	struct e1000_hw *hw = &adapter->hw;
799 	int rx_queue = IGB_N0_QUEUE;
800 	int tx_queue = IGB_N0_QUEUE;
801 	u32 msixbm = 0;
802 
803 	if (q_vector->rx.ring)
804 		rx_queue = q_vector->rx.ring->reg_idx;
805 	if (q_vector->tx.ring)
806 		tx_queue = q_vector->tx.ring->reg_idx;
807 
808 	switch (hw->mac.type) {
809 	case e1000_82575:
810 		/* The 82575 assigns vectors using a bitmask, which matches the
811 		 * bitmask for the EICR/EIMS/EIMC registers.  To assign one
812 		 * or more queues to a vector, we write the appropriate bits
813 		 * into the MSIXBM register for that vector.
814 		 */
815 		if (rx_queue > IGB_N0_QUEUE)
816 			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 		if (tx_queue > IGB_N0_QUEUE)
818 			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 		if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 			msixbm |= E1000_EIMS_OTHER;
821 		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 		q_vector->eims_value = msixbm;
823 		break;
824 	case e1000_82576:
825 		/* 82576 uses a table that essentially consists of 2 columns
826 		 * with 8 rows.  The ordering is column-major so we use the
827 		 * lower 3 bits as the row index, and the 4th bit as the
828 		 * column offset.
829 		 */
830 		if (rx_queue > IGB_N0_QUEUE)
831 			igb_write_ivar(hw, msix_vector,
832 				       rx_queue & 0x7,
833 				       (rx_queue & 0x8) << 1);
834 		if (tx_queue > IGB_N0_QUEUE)
835 			igb_write_ivar(hw, msix_vector,
836 				       tx_queue & 0x7,
837 				       ((tx_queue & 0x8) << 1) + 8);
838 		q_vector->eims_value = 1 << msix_vector;
839 		break;
840 	case e1000_82580:
841 	case e1000_i350:
842 	case e1000_i354:
843 	case e1000_i210:
844 	case e1000_i211:
845 		/* On 82580 and newer adapters the scheme is similar to 82576
846 		 * however instead of ordering column-major we have things
847 		 * ordered row-major.  So we traverse the table by using
848 		 * bit 0 as the column offset, and the remaining bits as the
849 		 * row index.
850 		 */
851 		if (rx_queue > IGB_N0_QUEUE)
852 			igb_write_ivar(hw, msix_vector,
853 				       rx_queue >> 1,
854 				       (rx_queue & 0x1) << 4);
855 		if (tx_queue > IGB_N0_QUEUE)
856 			igb_write_ivar(hw, msix_vector,
857 				       tx_queue >> 1,
858 				       ((tx_queue & 0x1) << 4) + 8);
859 		q_vector->eims_value = 1 << msix_vector;
860 		break;
861 	default:
862 		BUG();
863 		break;
864 	}
865 
866 	/* add q_vector eims value to global eims_enable_mask */
867 	adapter->eims_enable_mask |= q_vector->eims_value;
868 
869 	/* configure q_vector to set itr on first interrupt */
870 	q_vector->set_itr = 1;
871 }
872 
873 /**
874  *  igb_configure_msix - Configure MSI-X hardware
875  *  @adapter: board private structure to initialize
876  *
877  *  igb_configure_msix sets up the hardware to properly
878  *  generate MSI-X interrupts.
879  **/
880 static void igb_configure_msix(struct igb_adapter *adapter)
881 {
882 	u32 tmp;
883 	int i, vector = 0;
884 	struct e1000_hw *hw = &adapter->hw;
885 
886 	adapter->eims_enable_mask = 0;
887 
888 	/* set vector for other causes, i.e. link changes */
889 	switch (hw->mac.type) {
890 	case e1000_82575:
891 		tmp = rd32(E1000_CTRL_EXT);
892 		/* enable MSI-X PBA support*/
893 		tmp |= E1000_CTRL_EXT_PBA_CLR;
894 
895 		/* Auto-Mask interrupts upon ICR read. */
896 		tmp |= E1000_CTRL_EXT_EIAME;
897 		tmp |= E1000_CTRL_EXT_IRCA;
898 
899 		wr32(E1000_CTRL_EXT, tmp);
900 
901 		/* enable msix_other interrupt */
902 		array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 		adapter->eims_other = E1000_EIMS_OTHER;
904 
905 		break;
906 
907 	case e1000_82576:
908 	case e1000_82580:
909 	case e1000_i350:
910 	case e1000_i354:
911 	case e1000_i210:
912 	case e1000_i211:
913 		/* Turn on MSI-X capability first, or our settings
914 		 * won't stick.  And it will take days to debug.
915 		 */
916 		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 		     E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 		     E1000_GPIE_NSICR);
919 
920 		/* enable msix_other interrupt */
921 		adapter->eims_other = 1 << vector;
922 		tmp = (vector++ | E1000_IVAR_VALID) << 8;
923 
924 		wr32(E1000_IVAR_MISC, tmp);
925 		break;
926 	default:
927 		/* do nothing, since nothing else supports MSI-X */
928 		break;
929 	} /* switch (hw->mac.type) */
930 
931 	adapter->eims_enable_mask |= adapter->eims_other;
932 
933 	for (i = 0; i < adapter->num_q_vectors; i++)
934 		igb_assign_vector(adapter->q_vector[i], vector++);
935 
936 	wrfl();
937 }
938 
939 /**
940  *  igb_request_msix - Initialize MSI-X interrupts
941  *  @adapter: board private structure to initialize
942  *
943  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
944  *  kernel.
945  **/
946 static int igb_request_msix(struct igb_adapter *adapter)
947 {
948 	struct net_device *netdev = adapter->netdev;
949 	struct e1000_hw *hw = &adapter->hw;
950 	int i, err = 0, vector = 0, free_vector = 0;
951 
952 	err = request_irq(adapter->msix_entries[vector].vector,
953 			  igb_msix_other, 0, netdev->name, adapter);
954 	if (err)
955 		goto err_out;
956 
957 	for (i = 0; i < adapter->num_q_vectors; i++) {
958 		struct igb_q_vector *q_vector = adapter->q_vector[i];
959 
960 		vector++;
961 
962 		q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963 
964 		if (q_vector->rx.ring && q_vector->tx.ring)
965 			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
966 				q_vector->rx.ring->queue_index);
967 		else if (q_vector->tx.ring)
968 			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
969 				q_vector->tx.ring->queue_index);
970 		else if (q_vector->rx.ring)
971 			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
972 				q_vector->rx.ring->queue_index);
973 		else
974 			sprintf(q_vector->name, "%s-unused", netdev->name);
975 
976 		err = request_irq(adapter->msix_entries[vector].vector,
977 				  igb_msix_ring, 0, q_vector->name,
978 				  q_vector);
979 		if (err)
980 			goto err_free;
981 	}
982 
983 	igb_configure_msix(adapter);
984 	return 0;
985 
986 err_free:
987 	/* free already assigned IRQs */
988 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989 
990 	vector--;
991 	for (i = 0; i < vector; i++) {
992 		free_irq(adapter->msix_entries[free_vector++].vector,
993 			 adapter->q_vector[i]);
994 	}
995 err_out:
996 	return err;
997 }
998 
999 /**
1000  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
1001  *  @adapter: board private structure to initialize
1002  *  @v_idx: Index of vector to be freed
1003  *
1004  *  This function frees the memory allocated to the q_vector.
1005  **/
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007 {
1008 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009 
1010 	adapter->q_vector[v_idx] = NULL;
1011 
1012 	/* igb_get_stats64() might access the rings on this vector,
1013 	 * we must wait a grace period before freeing it.
1014 	 */
1015 	if (q_vector)
1016 		kfree_rcu(q_vector, rcu);
1017 }
1018 
1019 /**
1020  *  igb_reset_q_vector - Reset config for interrupt vector
1021  *  @adapter: board private structure to initialize
1022  *  @v_idx: Index of vector to be reset
1023  *
1024  *  If NAPI is enabled it will delete any references to the
1025  *  NAPI struct. This is preparation for igb_free_q_vector.
1026  **/
1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028 {
1029 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030 
1031 	/* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 	 * allocated. So, q_vector is NULL so we should stop here.
1033 	 */
1034 	if (!q_vector)
1035 		return;
1036 
1037 	if (q_vector->tx.ring)
1038 		adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039 
1040 	if (q_vector->rx.ring)
1041 		adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1042 
1043 	netif_napi_del(&q_vector->napi);
1044 
1045 }
1046 
1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048 {
1049 	int v_idx = adapter->num_q_vectors;
1050 
1051 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1052 		pci_disable_msix(adapter->pdev);
1053 	else if (adapter->flags & IGB_FLAG_HAS_MSI)
1054 		pci_disable_msi(adapter->pdev);
1055 
1056 	while (v_idx--)
1057 		igb_reset_q_vector(adapter, v_idx);
1058 }
1059 
1060 /**
1061  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1062  *  @adapter: board private structure to initialize
1063  *
1064  *  This function frees the memory allocated to the q_vectors.  In addition if
1065  *  NAPI is enabled it will delete any references to the NAPI struct prior
1066  *  to freeing the q_vector.
1067  **/
1068 static void igb_free_q_vectors(struct igb_adapter *adapter)
1069 {
1070 	int v_idx = adapter->num_q_vectors;
1071 
1072 	adapter->num_tx_queues = 0;
1073 	adapter->num_rx_queues = 0;
1074 	adapter->num_q_vectors = 0;
1075 
1076 	while (v_idx--) {
1077 		igb_reset_q_vector(adapter, v_idx);
1078 		igb_free_q_vector(adapter, v_idx);
1079 	}
1080 }
1081 
1082 /**
1083  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084  *  @adapter: board private structure to initialize
1085  *
1086  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1087  *  MSI-X interrupts allocated.
1088  */
1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090 {
1091 	igb_free_q_vectors(adapter);
1092 	igb_reset_interrupt_capability(adapter);
1093 }
1094 
1095 /**
1096  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1097  *  @adapter: board private structure to initialize
1098  *  @msix: boolean value of MSIX capability
1099  *
1100  *  Attempt to configure interrupts using the best available
1101  *  capabilities of the hardware and kernel.
1102  **/
1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1104 {
1105 	int err;
1106 	int numvecs, i;
1107 
1108 	if (!msix)
1109 		goto msi_only;
1110 	adapter->flags |= IGB_FLAG_HAS_MSIX;
1111 
1112 	/* Number of supported queues. */
1113 	adapter->num_rx_queues = adapter->rss_queues;
1114 	if (adapter->vfs_allocated_count)
1115 		adapter->num_tx_queues = 1;
1116 	else
1117 		adapter->num_tx_queues = adapter->rss_queues;
1118 
1119 	/* start with one vector for every Rx queue */
1120 	numvecs = adapter->num_rx_queues;
1121 
1122 	/* if Tx handler is separate add 1 for every Tx queue */
1123 	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 		numvecs += adapter->num_tx_queues;
1125 
1126 	/* store the number of vectors reserved for queues */
1127 	adapter->num_q_vectors = numvecs;
1128 
1129 	/* add 1 vector for link status interrupts */
1130 	numvecs++;
1131 	for (i = 0; i < numvecs; i++)
1132 		adapter->msix_entries[i].entry = i;
1133 
1134 	err = pci_enable_msix_range(adapter->pdev,
1135 				    adapter->msix_entries,
1136 				    numvecs,
1137 				    numvecs);
1138 	if (err > 0)
1139 		return;
1140 
1141 	igb_reset_interrupt_capability(adapter);
1142 
1143 	/* If we can't do MSI-X, try MSI */
1144 msi_only:
1145 	adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1146 #ifdef CONFIG_PCI_IOV
1147 	/* disable SR-IOV for non MSI-X configurations */
1148 	if (adapter->vf_data) {
1149 		struct e1000_hw *hw = &adapter->hw;
1150 		/* disable iov and allow time for transactions to clear */
1151 		pci_disable_sriov(adapter->pdev);
1152 		msleep(500);
1153 
1154 		kfree(adapter->vf_data);
1155 		adapter->vf_data = NULL;
1156 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1157 		wrfl();
1158 		msleep(100);
1159 		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 	}
1161 #endif
1162 	adapter->vfs_allocated_count = 0;
1163 	adapter->rss_queues = 1;
1164 	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1165 	adapter->num_rx_queues = 1;
1166 	adapter->num_tx_queues = 1;
1167 	adapter->num_q_vectors = 1;
1168 	if (!pci_enable_msi(adapter->pdev))
1169 		adapter->flags |= IGB_FLAG_HAS_MSI;
1170 }
1171 
1172 static void igb_add_ring(struct igb_ring *ring,
1173 			 struct igb_ring_container *head)
1174 {
1175 	head->ring = ring;
1176 	head->count++;
1177 }
1178 
1179 /**
1180  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181  *  @adapter: board private structure to initialize
1182  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1183  *  @v_idx: index of vector in adapter struct
1184  *  @txr_count: total number of Tx rings to allocate
1185  *  @txr_idx: index of first Tx ring to allocate
1186  *  @rxr_count: total number of Rx rings to allocate
1187  *  @rxr_idx: index of first Rx ring to allocate
1188  *
1189  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1190  **/
1191 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 			      int v_count, int v_idx,
1193 			      int txr_count, int txr_idx,
1194 			      int rxr_count, int rxr_idx)
1195 {
1196 	struct igb_q_vector *q_vector;
1197 	struct igb_ring *ring;
1198 	int ring_count, size;
1199 
1200 	/* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 	if (txr_count > 1 || rxr_count > 1)
1202 		return -ENOMEM;
1203 
1204 	ring_count = txr_count + rxr_count;
1205 	size = sizeof(struct igb_q_vector) +
1206 	       (sizeof(struct igb_ring) * ring_count);
1207 
1208 	/* allocate q_vector and rings */
1209 	q_vector = adapter->q_vector[v_idx];
1210 	if (!q_vector) {
1211 		q_vector = kzalloc(size, GFP_KERNEL);
1212 	} else if (size > ksize(q_vector)) {
1213 		kfree_rcu(q_vector, rcu);
1214 		q_vector = kzalloc(size, GFP_KERNEL);
1215 	} else {
1216 		memset(q_vector, 0, size);
1217 	}
1218 	if (!q_vector)
1219 		return -ENOMEM;
1220 
1221 	/* initialize NAPI */
1222 	netif_napi_add(adapter->netdev, &q_vector->napi,
1223 		       igb_poll, 64);
1224 
1225 	/* tie q_vector and adapter together */
1226 	adapter->q_vector[v_idx] = q_vector;
1227 	q_vector->adapter = adapter;
1228 
1229 	/* initialize work limits */
1230 	q_vector->tx.work_limit = adapter->tx_work_limit;
1231 
1232 	/* initialize ITR configuration */
1233 	q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 	q_vector->itr_val = IGB_START_ITR;
1235 
1236 	/* initialize pointer to rings */
1237 	ring = q_vector->ring;
1238 
1239 	/* intialize ITR */
1240 	if (rxr_count) {
1241 		/* rx or rx/tx vector */
1242 		if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 			q_vector->itr_val = adapter->rx_itr_setting;
1244 	} else {
1245 		/* tx only vector */
1246 		if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 			q_vector->itr_val = adapter->tx_itr_setting;
1248 	}
1249 
1250 	if (txr_count) {
1251 		/* assign generic ring traits */
1252 		ring->dev = &adapter->pdev->dev;
1253 		ring->netdev = adapter->netdev;
1254 
1255 		/* configure backlink on ring */
1256 		ring->q_vector = q_vector;
1257 
1258 		/* update q_vector Tx values */
1259 		igb_add_ring(ring, &q_vector->tx);
1260 
1261 		/* For 82575, context index must be unique per ring. */
1262 		if (adapter->hw.mac.type == e1000_82575)
1263 			set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264 
1265 		/* apply Tx specific ring traits */
1266 		ring->count = adapter->tx_ring_count;
1267 		ring->queue_index = txr_idx;
1268 
1269 		u64_stats_init(&ring->tx_syncp);
1270 		u64_stats_init(&ring->tx_syncp2);
1271 
1272 		/* assign ring to adapter */
1273 		adapter->tx_ring[txr_idx] = ring;
1274 
1275 		/* push pointer to next ring */
1276 		ring++;
1277 	}
1278 
1279 	if (rxr_count) {
1280 		/* assign generic ring traits */
1281 		ring->dev = &adapter->pdev->dev;
1282 		ring->netdev = adapter->netdev;
1283 
1284 		/* configure backlink on ring */
1285 		ring->q_vector = q_vector;
1286 
1287 		/* update q_vector Rx values */
1288 		igb_add_ring(ring, &q_vector->rx);
1289 
1290 		/* set flag indicating ring supports SCTP checksum offload */
1291 		if (adapter->hw.mac.type >= e1000_82576)
1292 			set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293 
1294 		/* On i350, i354, i210, and i211, loopback VLAN packets
1295 		 * have the tag byte-swapped.
1296 		 */
1297 		if (adapter->hw.mac.type >= e1000_i350)
1298 			set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299 
1300 		/* apply Rx specific ring traits */
1301 		ring->count = adapter->rx_ring_count;
1302 		ring->queue_index = rxr_idx;
1303 
1304 		u64_stats_init(&ring->rx_syncp);
1305 
1306 		/* assign ring to adapter */
1307 		adapter->rx_ring[rxr_idx] = ring;
1308 	}
1309 
1310 	return 0;
1311 }
1312 
1313 
1314 /**
1315  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316  *  @adapter: board private structure to initialize
1317  *
1318  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1319  *  return -ENOMEM.
1320  **/
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322 {
1323 	int q_vectors = adapter->num_q_vectors;
1324 	int rxr_remaining = adapter->num_rx_queues;
1325 	int txr_remaining = adapter->num_tx_queues;
1326 	int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 	int err;
1328 
1329 	if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 		for (; rxr_remaining; v_idx++) {
1331 			err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 						 0, 0, 1, rxr_idx);
1333 
1334 			if (err)
1335 				goto err_out;
1336 
1337 			/* update counts and index */
1338 			rxr_remaining--;
1339 			rxr_idx++;
1340 		}
1341 	}
1342 
1343 	for (; v_idx < q_vectors; v_idx++) {
1344 		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346 
1347 		err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 					 tqpv, txr_idx, rqpv, rxr_idx);
1349 
1350 		if (err)
1351 			goto err_out;
1352 
1353 		/* update counts and index */
1354 		rxr_remaining -= rqpv;
1355 		txr_remaining -= tqpv;
1356 		rxr_idx++;
1357 		txr_idx++;
1358 	}
1359 
1360 	return 0;
1361 
1362 err_out:
1363 	adapter->num_tx_queues = 0;
1364 	adapter->num_rx_queues = 0;
1365 	adapter->num_q_vectors = 0;
1366 
1367 	while (v_idx--)
1368 		igb_free_q_vector(adapter, v_idx);
1369 
1370 	return -ENOMEM;
1371 }
1372 
1373 /**
1374  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375  *  @adapter: board private structure to initialize
1376  *  @msix: boolean value of MSIX capability
1377  *
1378  *  This function initializes the interrupts and allocates all of the queues.
1379  **/
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381 {
1382 	struct pci_dev *pdev = adapter->pdev;
1383 	int err;
1384 
1385 	igb_set_interrupt_capability(adapter, msix);
1386 
1387 	err = igb_alloc_q_vectors(adapter);
1388 	if (err) {
1389 		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 		goto err_alloc_q_vectors;
1391 	}
1392 
1393 	igb_cache_ring_register(adapter);
1394 
1395 	return 0;
1396 
1397 err_alloc_q_vectors:
1398 	igb_reset_interrupt_capability(adapter);
1399 	return err;
1400 }
1401 
1402 /**
1403  *  igb_request_irq - initialize interrupts
1404  *  @adapter: board private structure to initialize
1405  *
1406  *  Attempts to configure interrupts using the best available
1407  *  capabilities of the hardware and kernel.
1408  **/
1409 static int igb_request_irq(struct igb_adapter *adapter)
1410 {
1411 	struct net_device *netdev = adapter->netdev;
1412 	struct pci_dev *pdev = adapter->pdev;
1413 	int err = 0;
1414 
1415 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 		err = igb_request_msix(adapter);
1417 		if (!err)
1418 			goto request_done;
1419 		/* fall back to MSI */
1420 		igb_free_all_tx_resources(adapter);
1421 		igb_free_all_rx_resources(adapter);
1422 
1423 		igb_clear_interrupt_scheme(adapter);
1424 		err = igb_init_interrupt_scheme(adapter, false);
1425 		if (err)
1426 			goto request_done;
1427 
1428 		igb_setup_all_tx_resources(adapter);
1429 		igb_setup_all_rx_resources(adapter);
1430 		igb_configure(adapter);
1431 	}
1432 
1433 	igb_assign_vector(adapter->q_vector[0], 0);
1434 
1435 	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 		err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 				  netdev->name, adapter);
1438 		if (!err)
1439 			goto request_done;
1440 
1441 		/* fall back to legacy interrupts */
1442 		igb_reset_interrupt_capability(adapter);
1443 		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444 	}
1445 
1446 	err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 			  netdev->name, adapter);
1448 
1449 	if (err)
1450 		dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451 			err);
1452 
1453 request_done:
1454 	return err;
1455 }
1456 
1457 static void igb_free_irq(struct igb_adapter *adapter)
1458 {
1459 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460 		int vector = 0, i;
1461 
1462 		free_irq(adapter->msix_entries[vector++].vector, adapter);
1463 
1464 		for (i = 0; i < adapter->num_q_vectors; i++)
1465 			free_irq(adapter->msix_entries[vector++].vector,
1466 				 adapter->q_vector[i]);
1467 	} else {
1468 		free_irq(adapter->pdev->irq, adapter);
1469 	}
1470 }
1471 
1472 /**
1473  *  igb_irq_disable - Mask off interrupt generation on the NIC
1474  *  @adapter: board private structure
1475  **/
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1477 {
1478 	struct e1000_hw *hw = &adapter->hw;
1479 
1480 	/* we need to be careful when disabling interrupts.  The VFs are also
1481 	 * mapped into these registers and so clearing the bits can cause
1482 	 * issues on the VF drivers so we only need to clear what we set
1483 	 */
1484 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 		u32 regval = rd32(E1000_EIAM);
1486 
1487 		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 		wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 		regval = rd32(E1000_EIAC);
1490 		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491 	}
1492 
1493 	wr32(E1000_IAM, 0);
1494 	wr32(E1000_IMC, ~0);
1495 	wrfl();
1496 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497 		int i;
1498 
1499 		for (i = 0; i < adapter->num_q_vectors; i++)
1500 			synchronize_irq(adapter->msix_entries[i].vector);
1501 	} else {
1502 		synchronize_irq(adapter->pdev->irq);
1503 	}
1504 }
1505 
1506 /**
1507  *  igb_irq_enable - Enable default interrupt generation settings
1508  *  @adapter: board private structure
1509  **/
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1511 {
1512 	struct e1000_hw *hw = &adapter->hw;
1513 
1514 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 		u32 regval = rd32(E1000_EIAC);
1517 
1518 		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 		regval = rd32(E1000_EIAM);
1520 		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 		wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 		if (adapter->vfs_allocated_count) {
1523 			wr32(E1000_MBVFIMR, 0xFF);
1524 			ims |= E1000_IMS_VMMB;
1525 		}
1526 		wr32(E1000_IMS, ims);
1527 	} else {
1528 		wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 				E1000_IMS_DRSTA);
1530 		wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 				E1000_IMS_DRSTA);
1532 	}
1533 }
1534 
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536 {
1537 	struct e1000_hw *hw = &adapter->hw;
1538 	u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 	u16 old_vid = adapter->mng_vlan_id;
1540 
1541 	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 		/* add VID to filter table */
1543 		igb_vfta_set(hw, vid, true);
1544 		adapter->mng_vlan_id = vid;
1545 	} else {
1546 		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 	}
1548 
1549 	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 	    (vid != old_vid) &&
1551 	    !test_bit(old_vid, adapter->active_vlans)) {
1552 		/* remove VID from filter table */
1553 		igb_vfta_set(hw, old_vid, false);
1554 	}
1555 }
1556 
1557 /**
1558  *  igb_release_hw_control - release control of the h/w to f/w
1559  *  @adapter: address of board private structure
1560  *
1561  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562  *  For ASF and Pass Through versions of f/w this means that the
1563  *  driver is no longer loaded.
1564  **/
1565 static void igb_release_hw_control(struct igb_adapter *adapter)
1566 {
1567 	struct e1000_hw *hw = &adapter->hw;
1568 	u32 ctrl_ext;
1569 
1570 	/* Let firmware take over control of h/w */
1571 	ctrl_ext = rd32(E1000_CTRL_EXT);
1572 	wr32(E1000_CTRL_EXT,
1573 			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574 }
1575 
1576 /**
1577  *  igb_get_hw_control - get control of the h/w from f/w
1578  *  @adapter: address of board private structure
1579  *
1580  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581  *  For ASF and Pass Through versions of f/w this means that
1582  *  the driver is loaded.
1583  **/
1584 static void igb_get_hw_control(struct igb_adapter *adapter)
1585 {
1586 	struct e1000_hw *hw = &adapter->hw;
1587 	u32 ctrl_ext;
1588 
1589 	/* Let firmware know the driver has taken over */
1590 	ctrl_ext = rd32(E1000_CTRL_EXT);
1591 	wr32(E1000_CTRL_EXT,
1592 			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593 }
1594 
1595 /**
1596  *  igb_configure - configure the hardware for RX and TX
1597  *  @adapter: private board structure
1598  **/
1599 static void igb_configure(struct igb_adapter *adapter)
1600 {
1601 	struct net_device *netdev = adapter->netdev;
1602 	int i;
1603 
1604 	igb_get_hw_control(adapter);
1605 	igb_set_rx_mode(netdev);
1606 
1607 	igb_restore_vlan(adapter);
1608 
1609 	igb_setup_tctl(adapter);
1610 	igb_setup_mrqc(adapter);
1611 	igb_setup_rctl(adapter);
1612 
1613 	igb_configure_tx(adapter);
1614 	igb_configure_rx(adapter);
1615 
1616 	igb_rx_fifo_flush_82575(&adapter->hw);
1617 
1618 	/* call igb_desc_unused which always leaves
1619 	 * at least 1 descriptor unused to make sure
1620 	 * next_to_use != next_to_clean
1621 	 */
1622 	for (i = 0; i < adapter->num_rx_queues; i++) {
1623 		struct igb_ring *ring = adapter->rx_ring[i];
1624 		igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1625 	}
1626 }
1627 
1628 /**
1629  *  igb_power_up_link - Power up the phy/serdes link
1630  *  @adapter: address of board private structure
1631  **/
1632 void igb_power_up_link(struct igb_adapter *adapter)
1633 {
1634 	igb_reset_phy(&adapter->hw);
1635 
1636 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 		igb_power_up_phy_copper(&adapter->hw);
1638 	else
1639 		igb_power_up_serdes_link_82575(&adapter->hw);
1640 
1641 	igb_setup_link(&adapter->hw);
1642 }
1643 
1644 /**
1645  *  igb_power_down_link - Power down the phy/serdes link
1646  *  @adapter: address of board private structure
1647  */
1648 static void igb_power_down_link(struct igb_adapter *adapter)
1649 {
1650 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 		igb_power_down_phy_copper_82575(&adapter->hw);
1652 	else
1653 		igb_shutdown_serdes_link_82575(&adapter->hw);
1654 }
1655 
1656 /**
1657  * Detect and switch function for Media Auto Sense
1658  * @adapter: address of the board private structure
1659  **/
1660 static void igb_check_swap_media(struct igb_adapter *adapter)
1661 {
1662 	struct e1000_hw *hw = &adapter->hw;
1663 	u32 ctrl_ext, connsw;
1664 	bool swap_now = false;
1665 
1666 	ctrl_ext = rd32(E1000_CTRL_EXT);
1667 	connsw = rd32(E1000_CONNSW);
1668 
1669 	/* need to live swap if current media is copper and we have fiber/serdes
1670 	 * to go to.
1671 	 */
1672 
1673 	if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 	    (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 		swap_now = true;
1676 	} else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 		/* copper signal takes time to appear */
1678 		if (adapter->copper_tries < 4) {
1679 			adapter->copper_tries++;
1680 			connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 			wr32(E1000_CONNSW, connsw);
1682 			return;
1683 		} else {
1684 			adapter->copper_tries = 0;
1685 			if ((connsw & E1000_CONNSW_PHYSD) &&
1686 			    (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 				swap_now = true;
1688 				connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 				wr32(E1000_CONNSW, connsw);
1690 			}
1691 		}
1692 	}
1693 
1694 	if (!swap_now)
1695 		return;
1696 
1697 	switch (hw->phy.media_type) {
1698 	case e1000_media_type_copper:
1699 		netdev_info(adapter->netdev,
1700 			"MAS: changing media to fiber/serdes\n");
1701 		ctrl_ext |=
1702 			E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 		adapter->copper_tries = 0;
1705 		break;
1706 	case e1000_media_type_internal_serdes:
1707 	case e1000_media_type_fiber:
1708 		netdev_info(adapter->netdev,
1709 			"MAS: changing media to copper\n");
1710 		ctrl_ext &=
1711 			~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 		break;
1714 	default:
1715 		/* shouldn't get here during regular operation */
1716 		netdev_err(adapter->netdev,
1717 			"AMS: Invalid media type found, returning\n");
1718 		break;
1719 	}
1720 	wr32(E1000_CTRL_EXT, ctrl_ext);
1721 }
1722 
1723 /**
1724  *  igb_up - Open the interface and prepare it to handle traffic
1725  *  @adapter: board private structure
1726  **/
1727 int igb_up(struct igb_adapter *adapter)
1728 {
1729 	struct e1000_hw *hw = &adapter->hw;
1730 	int i;
1731 
1732 	/* hardware has been reset, we need to reload some things */
1733 	igb_configure(adapter);
1734 
1735 	clear_bit(__IGB_DOWN, &adapter->state);
1736 
1737 	for (i = 0; i < adapter->num_q_vectors; i++)
1738 		napi_enable(&(adapter->q_vector[i]->napi));
1739 
1740 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 		igb_configure_msix(adapter);
1742 	else
1743 		igb_assign_vector(adapter->q_vector[0], 0);
1744 
1745 	/* Clear any pending interrupts. */
1746 	rd32(E1000_ICR);
1747 	igb_irq_enable(adapter);
1748 
1749 	/* notify VFs that reset has been completed */
1750 	if (adapter->vfs_allocated_count) {
1751 		u32 reg_data = rd32(E1000_CTRL_EXT);
1752 
1753 		reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 		wr32(E1000_CTRL_EXT, reg_data);
1755 	}
1756 
1757 	netif_tx_start_all_queues(adapter->netdev);
1758 
1759 	/* start the watchdog. */
1760 	hw->mac.get_link_status = 1;
1761 	schedule_work(&adapter->watchdog_task);
1762 
1763 	if ((adapter->flags & IGB_FLAG_EEE) &&
1764 	    (!hw->dev_spec._82575.eee_disable))
1765 		adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766 
1767 	return 0;
1768 }
1769 
1770 void igb_down(struct igb_adapter *adapter)
1771 {
1772 	struct net_device *netdev = adapter->netdev;
1773 	struct e1000_hw *hw = &adapter->hw;
1774 	u32 tctl, rctl;
1775 	int i;
1776 
1777 	/* signal that we're down so the interrupt handler does not
1778 	 * reschedule our watchdog timer
1779 	 */
1780 	set_bit(__IGB_DOWN, &adapter->state);
1781 
1782 	/* disable receives in the hardware */
1783 	rctl = rd32(E1000_RCTL);
1784 	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 	/* flush and sleep below */
1786 
1787 	netif_carrier_off(netdev);
1788 	netif_tx_stop_all_queues(netdev);
1789 
1790 	/* disable transmits in the hardware */
1791 	tctl = rd32(E1000_TCTL);
1792 	tctl &= ~E1000_TCTL_EN;
1793 	wr32(E1000_TCTL, tctl);
1794 	/* flush both disables and wait for them to finish */
1795 	wrfl();
1796 	usleep_range(10000, 11000);
1797 
1798 	igb_irq_disable(adapter);
1799 
1800 	adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801 
1802 	for (i = 0; i < adapter->num_q_vectors; i++) {
1803 		if (adapter->q_vector[i]) {
1804 			napi_synchronize(&adapter->q_vector[i]->napi);
1805 			napi_disable(&adapter->q_vector[i]->napi);
1806 		}
1807 	}
1808 
1809 	del_timer_sync(&adapter->watchdog_timer);
1810 	del_timer_sync(&adapter->phy_info_timer);
1811 
1812 	/* record the stats before reset*/
1813 	spin_lock(&adapter->stats64_lock);
1814 	igb_update_stats(adapter, &adapter->stats64);
1815 	spin_unlock(&adapter->stats64_lock);
1816 
1817 	adapter->link_speed = 0;
1818 	adapter->link_duplex = 0;
1819 
1820 	if (!pci_channel_offline(adapter->pdev))
1821 		igb_reset(adapter);
1822 	igb_clean_all_tx_rings(adapter);
1823 	igb_clean_all_rx_rings(adapter);
1824 #ifdef CONFIG_IGB_DCA
1825 
1826 	/* since we reset the hardware DCA settings were cleared */
1827 	igb_setup_dca(adapter);
1828 #endif
1829 }
1830 
1831 void igb_reinit_locked(struct igb_adapter *adapter)
1832 {
1833 	WARN_ON(in_interrupt());
1834 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1835 		usleep_range(1000, 2000);
1836 	igb_down(adapter);
1837 	igb_up(adapter);
1838 	clear_bit(__IGB_RESETTING, &adapter->state);
1839 }
1840 
1841 /** igb_enable_mas - Media Autosense re-enable after swap
1842  *
1843  * @adapter: adapter struct
1844  **/
1845 static void igb_enable_mas(struct igb_adapter *adapter)
1846 {
1847 	struct e1000_hw *hw = &adapter->hw;
1848 	u32 connsw = rd32(E1000_CONNSW);
1849 
1850 	/* configure for SerDes media detect */
1851 	if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 	    (!(connsw & E1000_CONNSW_SERDESD))) {
1853 		connsw |= E1000_CONNSW_ENRGSRC;
1854 		connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 		wr32(E1000_CONNSW, connsw);
1856 		wrfl();
1857 	}
1858 }
1859 
1860 void igb_reset(struct igb_adapter *adapter)
1861 {
1862 	struct pci_dev *pdev = adapter->pdev;
1863 	struct e1000_hw *hw = &adapter->hw;
1864 	struct e1000_mac_info *mac = &hw->mac;
1865 	struct e1000_fc_info *fc = &hw->fc;
1866 	u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1867 
1868 	/* Repartition Pba for greater than 9k mtu
1869 	 * To take effect CTRL.RST is required.
1870 	 */
1871 	switch (mac->type) {
1872 	case e1000_i350:
1873 	case e1000_i354:
1874 	case e1000_82580:
1875 		pba = rd32(E1000_RXPBS);
1876 		pba = igb_rxpbs_adjust_82580(pba);
1877 		break;
1878 	case e1000_82576:
1879 		pba = rd32(E1000_RXPBS);
1880 		pba &= E1000_RXPBS_SIZE_MASK_82576;
1881 		break;
1882 	case e1000_82575:
1883 	case e1000_i210:
1884 	case e1000_i211:
1885 	default:
1886 		pba = E1000_PBA_34K;
1887 		break;
1888 	}
1889 
1890 	if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 	    (mac->type < e1000_82576)) {
1892 		/* adjust PBA for jumbo frames */
1893 		wr32(E1000_PBA, pba);
1894 
1895 		/* To maintain wire speed transmits, the Tx FIFO should be
1896 		 * large enough to accommodate two full transmit packets,
1897 		 * rounded up to the next 1KB and expressed in KB.  Likewise,
1898 		 * the Rx FIFO should be large enough to accommodate at least
1899 		 * one full receive packet and is similarly rounded up and
1900 		 * expressed in KB.
1901 		 */
1902 		pba = rd32(E1000_PBA);
1903 		/* upper 16 bits has Tx packet buffer allocation size in KB */
1904 		tx_space = pba >> 16;
1905 		/* lower 16 bits has Rx packet buffer allocation size in KB */
1906 		pba &= 0xffff;
1907 		/* the Tx fifo also stores 16 bytes of information about the Tx
1908 		 * but don't include ethernet FCS because hardware appends it
1909 		 */
1910 		min_tx_space = (adapter->max_frame_size +
1911 				sizeof(union e1000_adv_tx_desc) -
1912 				ETH_FCS_LEN) * 2;
1913 		min_tx_space = ALIGN(min_tx_space, 1024);
1914 		min_tx_space >>= 10;
1915 		/* software strips receive CRC, so leave room for it */
1916 		min_rx_space = adapter->max_frame_size;
1917 		min_rx_space = ALIGN(min_rx_space, 1024);
1918 		min_rx_space >>= 10;
1919 
1920 		/* If current Tx allocation is less than the min Tx FIFO size,
1921 		 * and the min Tx FIFO size is less than the current Rx FIFO
1922 		 * allocation, take space away from current Rx allocation
1923 		 */
1924 		if (tx_space < min_tx_space &&
1925 		    ((min_tx_space - tx_space) < pba)) {
1926 			pba = pba - (min_tx_space - tx_space);
1927 
1928 			/* if short on Rx space, Rx wins and must trump Tx
1929 			 * adjustment
1930 			 */
1931 			if (pba < min_rx_space)
1932 				pba = min_rx_space;
1933 		}
1934 		wr32(E1000_PBA, pba);
1935 	}
1936 
1937 	/* flow control settings */
1938 	/* The high water mark must be low enough to fit one full frame
1939 	 * (or the size used for early receive) above it in the Rx FIFO.
1940 	 * Set it to the lower of:
1941 	 * - 90% of the Rx FIFO size, or
1942 	 * - the full Rx FIFO size minus one full frame
1943 	 */
1944 	hwm = min(((pba << 10) * 9 / 10),
1945 			((pba << 10) - 2 * adapter->max_frame_size));
1946 
1947 	fc->high_water = hwm & 0xFFFFFFF0;	/* 16-byte granularity */
1948 	fc->low_water = fc->high_water - 16;
1949 	fc->pause_time = 0xFFFF;
1950 	fc->send_xon = 1;
1951 	fc->current_mode = fc->requested_mode;
1952 
1953 	/* disable receive for all VFs and wait one second */
1954 	if (adapter->vfs_allocated_count) {
1955 		int i;
1956 
1957 		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1958 			adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1959 
1960 		/* ping all the active vfs to let them know we are going down */
1961 		igb_ping_all_vfs(adapter);
1962 
1963 		/* disable transmits and receives */
1964 		wr32(E1000_VFRE, 0);
1965 		wr32(E1000_VFTE, 0);
1966 	}
1967 
1968 	/* Allow time for pending master requests to run */
1969 	hw->mac.ops.reset_hw(hw);
1970 	wr32(E1000_WUC, 0);
1971 
1972 	if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1973 		/* need to resetup here after media swap */
1974 		adapter->ei.get_invariants(hw);
1975 		adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1976 	}
1977 	if ((mac->type == e1000_82575) &&
1978 	    (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1979 		igb_enable_mas(adapter);
1980 	}
1981 	if (hw->mac.ops.init_hw(hw))
1982 		dev_err(&pdev->dev, "Hardware Error\n");
1983 
1984 	/* Flow control settings reset on hardware reset, so guarantee flow
1985 	 * control is off when forcing speed.
1986 	 */
1987 	if (!hw->mac.autoneg)
1988 		igb_force_mac_fc(hw);
1989 
1990 	igb_init_dmac(adapter, pba);
1991 #ifdef CONFIG_IGB_HWMON
1992 	/* Re-initialize the thermal sensor on i350 devices. */
1993 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 		if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995 			/* If present, re-initialize the external thermal sensor
1996 			 * interface.
1997 			 */
1998 			if (adapter->ets)
1999 				mac->ops.init_thermal_sensor_thresh(hw);
2000 		}
2001 	}
2002 #endif
2003 	/* Re-establish EEE setting */
2004 	if (hw->phy.media_type == e1000_media_type_copper) {
2005 		switch (mac->type) {
2006 		case e1000_i350:
2007 		case e1000_i210:
2008 		case e1000_i211:
2009 			igb_set_eee_i350(hw, true, true);
2010 			break;
2011 		case e1000_i354:
2012 			igb_set_eee_i354(hw, true, true);
2013 			break;
2014 		default:
2015 			break;
2016 		}
2017 	}
2018 	if (!netif_running(adapter->netdev))
2019 		igb_power_down_link(adapter);
2020 
2021 	igb_update_mng_vlan(adapter);
2022 
2023 	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2024 	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2025 
2026 	/* Re-enable PTP, where applicable. */
2027 	igb_ptp_reset(adapter);
2028 
2029 	igb_get_phy_info(hw);
2030 }
2031 
2032 static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 	netdev_features_t features)
2034 {
2035 	/* Since there is no support for separate Rx/Tx vlan accel
2036 	 * enable/disable make sure Tx flag is always in same state as Rx.
2037 	 */
2038 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 		features |= NETIF_F_HW_VLAN_CTAG_TX;
2040 	else
2041 		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2042 
2043 	return features;
2044 }
2045 
2046 static int igb_set_features(struct net_device *netdev,
2047 	netdev_features_t features)
2048 {
2049 	netdev_features_t changed = netdev->features ^ features;
2050 	struct igb_adapter *adapter = netdev_priv(netdev);
2051 
2052 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2053 		igb_vlan_mode(netdev, features);
2054 
2055 	if (!(changed & NETIF_F_RXALL))
2056 		return 0;
2057 
2058 	netdev->features = features;
2059 
2060 	if (netif_running(netdev))
2061 		igb_reinit_locked(adapter);
2062 	else
2063 		igb_reset(adapter);
2064 
2065 	return 0;
2066 }
2067 
2068 static const struct net_device_ops igb_netdev_ops = {
2069 	.ndo_open		= igb_open,
2070 	.ndo_stop		= igb_close,
2071 	.ndo_start_xmit		= igb_xmit_frame,
2072 	.ndo_get_stats64	= igb_get_stats64,
2073 	.ndo_set_rx_mode	= igb_set_rx_mode,
2074 	.ndo_set_mac_address	= igb_set_mac,
2075 	.ndo_change_mtu		= igb_change_mtu,
2076 	.ndo_do_ioctl		= igb_ioctl,
2077 	.ndo_tx_timeout		= igb_tx_timeout,
2078 	.ndo_validate_addr	= eth_validate_addr,
2079 	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
2080 	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
2081 	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
2082 	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
2083 	.ndo_set_vf_rate	= igb_ndo_set_vf_bw,
2084 	.ndo_set_vf_spoofchk	= igb_ndo_set_vf_spoofchk,
2085 	.ndo_get_vf_config	= igb_ndo_get_vf_config,
2086 #ifdef CONFIG_NET_POLL_CONTROLLER
2087 	.ndo_poll_controller	= igb_netpoll,
2088 #endif
2089 	.ndo_fix_features	= igb_fix_features,
2090 	.ndo_set_features	= igb_set_features,
2091 	.ndo_features_check	= passthru_features_check,
2092 };
2093 
2094 /**
2095  * igb_set_fw_version - Configure version string for ethtool
2096  * @adapter: adapter struct
2097  **/
2098 void igb_set_fw_version(struct igb_adapter *adapter)
2099 {
2100 	struct e1000_hw *hw = &adapter->hw;
2101 	struct e1000_fw_version fw;
2102 
2103 	igb_get_fw_version(hw, &fw);
2104 
2105 	switch (hw->mac.type) {
2106 	case e1000_i210:
2107 	case e1000_i211:
2108 		if (!(igb_get_flash_presence_i210(hw))) {
2109 			snprintf(adapter->fw_version,
2110 				 sizeof(adapter->fw_version),
2111 				 "%2d.%2d-%d",
2112 				 fw.invm_major, fw.invm_minor,
2113 				 fw.invm_img_type);
2114 			break;
2115 		}
2116 		/* fall through */
2117 	default:
2118 		/* if option is rom valid, display its version too */
2119 		if (fw.or_valid) {
2120 			snprintf(adapter->fw_version,
2121 				 sizeof(adapter->fw_version),
2122 				 "%d.%d, 0x%08x, %d.%d.%d",
2123 				 fw.eep_major, fw.eep_minor, fw.etrack_id,
2124 				 fw.or_major, fw.or_build, fw.or_patch);
2125 		/* no option rom */
2126 		} else if (fw.etrack_id != 0X0000) {
2127 			snprintf(adapter->fw_version,
2128 			    sizeof(adapter->fw_version),
2129 			    "%d.%d, 0x%08x",
2130 			    fw.eep_major, fw.eep_minor, fw.etrack_id);
2131 		} else {
2132 		snprintf(adapter->fw_version,
2133 		    sizeof(adapter->fw_version),
2134 		    "%d.%d.%d",
2135 		    fw.eep_major, fw.eep_minor, fw.eep_build);
2136 		}
2137 		break;
2138 	}
2139 }
2140 
2141 /**
2142  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2143  *
2144  * @adapter: adapter struct
2145  **/
2146 static void igb_init_mas(struct igb_adapter *adapter)
2147 {
2148 	struct e1000_hw *hw = &adapter->hw;
2149 	u16 eeprom_data;
2150 
2151 	hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 	switch (hw->bus.func) {
2153 	case E1000_FUNC_0:
2154 		if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 			netdev_info(adapter->netdev,
2157 				"MAS: Enabling Media Autosense for port %d\n",
2158 				hw->bus.func);
2159 		}
2160 		break;
2161 	case E1000_FUNC_1:
2162 		if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 			netdev_info(adapter->netdev,
2165 				"MAS: Enabling Media Autosense for port %d\n",
2166 				hw->bus.func);
2167 		}
2168 		break;
2169 	case E1000_FUNC_2:
2170 		if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 			netdev_info(adapter->netdev,
2173 				"MAS: Enabling Media Autosense for port %d\n",
2174 				hw->bus.func);
2175 		}
2176 		break;
2177 	case E1000_FUNC_3:
2178 		if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 			netdev_info(adapter->netdev,
2181 				"MAS: Enabling Media Autosense for port %d\n",
2182 				hw->bus.func);
2183 		}
2184 		break;
2185 	default:
2186 		/* Shouldn't get here */
2187 		netdev_err(adapter->netdev,
2188 			"MAS: Invalid port configuration, returning\n");
2189 		break;
2190 	}
2191 }
2192 
2193 /**
2194  *  igb_init_i2c - Init I2C interface
2195  *  @adapter: pointer to adapter structure
2196  **/
2197 static s32 igb_init_i2c(struct igb_adapter *adapter)
2198 {
2199 	s32 status = 0;
2200 
2201 	/* I2C interface supported on i350 devices */
2202 	if (adapter->hw.mac.type != e1000_i350)
2203 		return 0;
2204 
2205 	/* Initialize the i2c bus which is controlled by the registers.
2206 	 * This bus will use the i2c_algo_bit structue that implements
2207 	 * the protocol through toggling of the 4 bits in the register.
2208 	 */
2209 	adapter->i2c_adap.owner = THIS_MODULE;
2210 	adapter->i2c_algo = igb_i2c_algo;
2211 	adapter->i2c_algo.data = adapter;
2212 	adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 	adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 	strlcpy(adapter->i2c_adap.name, "igb BB",
2215 		sizeof(adapter->i2c_adap.name));
2216 	status = i2c_bit_add_bus(&adapter->i2c_adap);
2217 	return status;
2218 }
2219 
2220 /**
2221  *  igb_probe - Device Initialization Routine
2222  *  @pdev: PCI device information struct
2223  *  @ent: entry in igb_pci_tbl
2224  *
2225  *  Returns 0 on success, negative on failure
2226  *
2227  *  igb_probe initializes an adapter identified by a pci_dev structure.
2228  *  The OS initialization, configuring of the adapter private structure,
2229  *  and a hardware reset occur.
2230  **/
2231 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2232 {
2233 	struct net_device *netdev;
2234 	struct igb_adapter *adapter;
2235 	struct e1000_hw *hw;
2236 	u16 eeprom_data = 0;
2237 	s32 ret_val;
2238 	static int global_quad_port_a; /* global quad port a indication */
2239 	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2240 	int err, pci_using_dac;
2241 	u8 part_str[E1000_PBANUM_LENGTH];
2242 
2243 	/* Catch broken hardware that put the wrong VF device ID in
2244 	 * the PCIe SR-IOV capability.
2245 	 */
2246 	if (pdev->is_virtfn) {
2247 		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2248 			pci_name(pdev), pdev->vendor, pdev->device);
2249 		return -EINVAL;
2250 	}
2251 
2252 	err = pci_enable_device_mem(pdev);
2253 	if (err)
2254 		return err;
2255 
2256 	pci_using_dac = 0;
2257 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2258 	if (!err) {
2259 		pci_using_dac = 1;
2260 	} else {
2261 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2262 		if (err) {
2263 			dev_err(&pdev->dev,
2264 				"No usable DMA configuration, aborting\n");
2265 			goto err_dma;
2266 		}
2267 	}
2268 
2269 	err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2270 					   IORESOURCE_MEM),
2271 					   igb_driver_name);
2272 	if (err)
2273 		goto err_pci_reg;
2274 
2275 	pci_enable_pcie_error_reporting(pdev);
2276 
2277 	pci_set_master(pdev);
2278 	pci_save_state(pdev);
2279 
2280 	err = -ENOMEM;
2281 	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2282 				   IGB_MAX_TX_QUEUES);
2283 	if (!netdev)
2284 		goto err_alloc_etherdev;
2285 
2286 	SET_NETDEV_DEV(netdev, &pdev->dev);
2287 
2288 	pci_set_drvdata(pdev, netdev);
2289 	adapter = netdev_priv(netdev);
2290 	adapter->netdev = netdev;
2291 	adapter->pdev = pdev;
2292 	hw = &adapter->hw;
2293 	hw->back = adapter;
2294 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2295 
2296 	err = -EIO;
2297 	hw->hw_addr = pci_iomap(pdev, 0, 0);
2298 	if (!hw->hw_addr)
2299 		goto err_ioremap;
2300 
2301 	netdev->netdev_ops = &igb_netdev_ops;
2302 	igb_set_ethtool_ops(netdev);
2303 	netdev->watchdog_timeo = 5 * HZ;
2304 
2305 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2306 
2307 	netdev->mem_start = pci_resource_start(pdev, 0);
2308 	netdev->mem_end = pci_resource_end(pdev, 0);
2309 
2310 	/* PCI config space info */
2311 	hw->vendor_id = pdev->vendor;
2312 	hw->device_id = pdev->device;
2313 	hw->revision_id = pdev->revision;
2314 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
2315 	hw->subsystem_device_id = pdev->subsystem_device;
2316 
2317 	/* Copy the default MAC, PHY and NVM function pointers */
2318 	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2319 	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2320 	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2321 	/* Initialize skew-specific constants */
2322 	err = ei->get_invariants(hw);
2323 	if (err)
2324 		goto err_sw_init;
2325 
2326 	/* setup the private structure */
2327 	err = igb_sw_init(adapter);
2328 	if (err)
2329 		goto err_sw_init;
2330 
2331 	igb_get_bus_info_pcie(hw);
2332 
2333 	hw->phy.autoneg_wait_to_complete = false;
2334 
2335 	/* Copper options */
2336 	if (hw->phy.media_type == e1000_media_type_copper) {
2337 		hw->phy.mdix = AUTO_ALL_MODES;
2338 		hw->phy.disable_polarity_correction = false;
2339 		hw->phy.ms_type = e1000_ms_hw_default;
2340 	}
2341 
2342 	if (igb_check_reset_block(hw))
2343 		dev_info(&pdev->dev,
2344 			"PHY reset is blocked due to SOL/IDER session.\n");
2345 
2346 	/* features is initialized to 0 in allocation, it might have bits
2347 	 * set by igb_sw_init so we should use an or instead of an
2348 	 * assignment.
2349 	 */
2350 	netdev->features |= NETIF_F_SG |
2351 			    NETIF_F_IP_CSUM |
2352 			    NETIF_F_IPV6_CSUM |
2353 			    NETIF_F_TSO |
2354 			    NETIF_F_TSO6 |
2355 			    NETIF_F_RXHASH |
2356 			    NETIF_F_RXCSUM |
2357 			    NETIF_F_HW_VLAN_CTAG_RX |
2358 			    NETIF_F_HW_VLAN_CTAG_TX;
2359 
2360 	/* copy netdev features into list of user selectable features */
2361 	netdev->hw_features |= netdev->features;
2362 	netdev->hw_features |= NETIF_F_RXALL;
2363 
2364 	/* set this bit last since it cannot be part of hw_features */
2365 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2366 
2367 	netdev->vlan_features |= NETIF_F_TSO |
2368 				 NETIF_F_TSO6 |
2369 				 NETIF_F_IP_CSUM |
2370 				 NETIF_F_IPV6_CSUM |
2371 				 NETIF_F_SG;
2372 
2373 	netdev->priv_flags |= IFF_SUPP_NOFCS;
2374 
2375 	if (pci_using_dac) {
2376 		netdev->features |= NETIF_F_HIGHDMA;
2377 		netdev->vlan_features |= NETIF_F_HIGHDMA;
2378 	}
2379 
2380 	if (hw->mac.type >= e1000_82576) {
2381 		netdev->hw_features |= NETIF_F_SCTP_CSUM;
2382 		netdev->features |= NETIF_F_SCTP_CSUM;
2383 	}
2384 
2385 	netdev->priv_flags |= IFF_UNICAST_FLT;
2386 
2387 	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2388 
2389 	/* before reading the NVM, reset the controller to put the device in a
2390 	 * known good starting state
2391 	 */
2392 	hw->mac.ops.reset_hw(hw);
2393 
2394 	/* make sure the NVM is good , i211/i210 parts can have special NVM
2395 	 * that doesn't contain a checksum
2396 	 */
2397 	switch (hw->mac.type) {
2398 	case e1000_i210:
2399 	case e1000_i211:
2400 		if (igb_get_flash_presence_i210(hw)) {
2401 			if (hw->nvm.ops.validate(hw) < 0) {
2402 				dev_err(&pdev->dev,
2403 					"The NVM Checksum Is Not Valid\n");
2404 				err = -EIO;
2405 				goto err_eeprom;
2406 			}
2407 		}
2408 		break;
2409 	default:
2410 		if (hw->nvm.ops.validate(hw) < 0) {
2411 			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2412 			err = -EIO;
2413 			goto err_eeprom;
2414 		}
2415 		break;
2416 	}
2417 
2418 	/* copy the MAC address out of the NVM */
2419 	if (hw->mac.ops.read_mac_addr(hw))
2420 		dev_err(&pdev->dev, "NVM Read Error\n");
2421 
2422 	memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2423 
2424 	if (!is_valid_ether_addr(netdev->dev_addr)) {
2425 		dev_err(&pdev->dev, "Invalid MAC Address\n");
2426 		err = -EIO;
2427 		goto err_eeprom;
2428 	}
2429 
2430 	/* get firmware version for ethtool -i */
2431 	igb_set_fw_version(adapter);
2432 
2433 	/* configure RXPBSIZE and TXPBSIZE */
2434 	if (hw->mac.type == e1000_i210) {
2435 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2436 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2437 	}
2438 
2439 	setup_timer(&adapter->watchdog_timer, igb_watchdog,
2440 		    (unsigned long) adapter);
2441 	setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2442 		    (unsigned long) adapter);
2443 
2444 	INIT_WORK(&adapter->reset_task, igb_reset_task);
2445 	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2446 
2447 	/* Initialize link properties that are user-changeable */
2448 	adapter->fc_autoneg = true;
2449 	hw->mac.autoneg = true;
2450 	hw->phy.autoneg_advertised = 0x2f;
2451 
2452 	hw->fc.requested_mode = e1000_fc_default;
2453 	hw->fc.current_mode = e1000_fc_default;
2454 
2455 	igb_validate_mdi_setting(hw);
2456 
2457 	/* By default, support wake on port A */
2458 	if (hw->bus.func == 0)
2459 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2460 
2461 	/* Check the NVM for wake support on non-port A ports */
2462 	if (hw->mac.type >= e1000_82580)
2463 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2464 				 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2465 				 &eeprom_data);
2466 	else if (hw->bus.func == 1)
2467 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2468 
2469 	if (eeprom_data & IGB_EEPROM_APME)
2470 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2471 
2472 	/* now that we have the eeprom settings, apply the special cases where
2473 	 * the eeprom may be wrong or the board simply won't support wake on
2474 	 * lan on a particular port
2475 	 */
2476 	switch (pdev->device) {
2477 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
2478 		adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2479 		break;
2480 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
2481 	case E1000_DEV_ID_82576_FIBER:
2482 	case E1000_DEV_ID_82576_SERDES:
2483 		/* Wake events only supported on port A for dual fiber
2484 		 * regardless of eeprom setting
2485 		 */
2486 		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2487 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2488 		break;
2489 	case E1000_DEV_ID_82576_QUAD_COPPER:
2490 	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2491 		/* if quad port adapter, disable WoL on all but port A */
2492 		if (global_quad_port_a != 0)
2493 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2494 		else
2495 			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2496 		/* Reset for multiple quad port adapters */
2497 		if (++global_quad_port_a == 4)
2498 			global_quad_port_a = 0;
2499 		break;
2500 	default:
2501 		/* If the device can't wake, don't set software support */
2502 		if (!device_can_wakeup(&adapter->pdev->dev))
2503 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2504 	}
2505 
2506 	/* initialize the wol settings based on the eeprom settings */
2507 	if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2508 		adapter->wol |= E1000_WUFC_MAG;
2509 
2510 	/* Some vendors want WoL disabled by default, but still supported */
2511 	if ((hw->mac.type == e1000_i350) &&
2512 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2513 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2514 		adapter->wol = 0;
2515 	}
2516 
2517 	device_set_wakeup_enable(&adapter->pdev->dev,
2518 				 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2519 
2520 	/* reset the hardware with the new settings */
2521 	igb_reset(adapter);
2522 
2523 	/* Init the I2C interface */
2524 	err = igb_init_i2c(adapter);
2525 	if (err) {
2526 		dev_err(&pdev->dev, "failed to init i2c interface\n");
2527 		goto err_eeprom;
2528 	}
2529 
2530 	/* let the f/w know that the h/w is now under the control of the
2531 	 * driver.
2532 	 */
2533 	igb_get_hw_control(adapter);
2534 
2535 	strcpy(netdev->name, "eth%d");
2536 	err = register_netdev(netdev);
2537 	if (err)
2538 		goto err_register;
2539 
2540 	/* carrier off reporting is important to ethtool even BEFORE open */
2541 	netif_carrier_off(netdev);
2542 
2543 #ifdef CONFIG_IGB_DCA
2544 	if (dca_add_requester(&pdev->dev) == 0) {
2545 		adapter->flags |= IGB_FLAG_DCA_ENABLED;
2546 		dev_info(&pdev->dev, "DCA enabled\n");
2547 		igb_setup_dca(adapter);
2548 	}
2549 
2550 #endif
2551 #ifdef CONFIG_IGB_HWMON
2552 	/* Initialize the thermal sensor on i350 devices. */
2553 	if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2554 		u16 ets_word;
2555 
2556 		/* Read the NVM to determine if this i350 device supports an
2557 		 * external thermal sensor.
2558 		 */
2559 		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2560 		if (ets_word != 0x0000 && ets_word != 0xFFFF)
2561 			adapter->ets = true;
2562 		else
2563 			adapter->ets = false;
2564 		if (igb_sysfs_init(adapter))
2565 			dev_err(&pdev->dev,
2566 				"failed to allocate sysfs resources\n");
2567 	} else {
2568 		adapter->ets = false;
2569 	}
2570 #endif
2571 	/* Check if Media Autosense is enabled */
2572 	adapter->ei = *ei;
2573 	if (hw->dev_spec._82575.mas_capable)
2574 		igb_init_mas(adapter);
2575 
2576 	/* do hw tstamp init after resetting */
2577 	igb_ptp_init(adapter);
2578 
2579 	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2580 	/* print bus type/speed/width info, not applicable to i354 */
2581 	if (hw->mac.type != e1000_i354) {
2582 		dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2583 			 netdev->name,
2584 			 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2585 			  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2586 			   "unknown"),
2587 			 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2588 			  "Width x4" :
2589 			  (hw->bus.width == e1000_bus_width_pcie_x2) ?
2590 			  "Width x2" :
2591 			  (hw->bus.width == e1000_bus_width_pcie_x1) ?
2592 			  "Width x1" : "unknown"), netdev->dev_addr);
2593 	}
2594 
2595 	if ((hw->mac.type >= e1000_i210 ||
2596 	     igb_get_flash_presence_i210(hw))) {
2597 		ret_val = igb_read_part_string(hw, part_str,
2598 					       E1000_PBANUM_LENGTH);
2599 	} else {
2600 		ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2601 	}
2602 
2603 	if (ret_val)
2604 		strcpy(part_str, "Unknown");
2605 	dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2606 	dev_info(&pdev->dev,
2607 		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2608 		(adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2609 		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2610 		adapter->num_rx_queues, adapter->num_tx_queues);
2611 	if (hw->phy.media_type == e1000_media_type_copper) {
2612 		switch (hw->mac.type) {
2613 		case e1000_i350:
2614 		case e1000_i210:
2615 		case e1000_i211:
2616 			/* Enable EEE for internal copper PHY devices */
2617 			err = igb_set_eee_i350(hw, true, true);
2618 			if ((!err) &&
2619 			    (!hw->dev_spec._82575.eee_disable)) {
2620 				adapter->eee_advert =
2621 					MDIO_EEE_100TX | MDIO_EEE_1000T;
2622 				adapter->flags |= IGB_FLAG_EEE;
2623 			}
2624 			break;
2625 		case e1000_i354:
2626 			if ((rd32(E1000_CTRL_EXT) &
2627 			    E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2628 				err = igb_set_eee_i354(hw, true, true);
2629 				if ((!err) &&
2630 					(!hw->dev_spec._82575.eee_disable)) {
2631 					adapter->eee_advert =
2632 					   MDIO_EEE_100TX | MDIO_EEE_1000T;
2633 					adapter->flags |= IGB_FLAG_EEE;
2634 				}
2635 			}
2636 			break;
2637 		default:
2638 			break;
2639 		}
2640 	}
2641 	pm_runtime_put_noidle(&pdev->dev);
2642 	return 0;
2643 
2644 err_register:
2645 	igb_release_hw_control(adapter);
2646 	memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2647 err_eeprom:
2648 	if (!igb_check_reset_block(hw))
2649 		igb_reset_phy(hw);
2650 
2651 	if (hw->flash_address)
2652 		iounmap(hw->flash_address);
2653 err_sw_init:
2654 	kfree(adapter->shadow_vfta);
2655 	igb_clear_interrupt_scheme(adapter);
2656 #ifdef CONFIG_PCI_IOV
2657 	igb_disable_sriov(pdev);
2658 #endif
2659 	pci_iounmap(pdev, hw->hw_addr);
2660 err_ioremap:
2661 	free_netdev(netdev);
2662 err_alloc_etherdev:
2663 	pci_release_selected_regions(pdev,
2664 				     pci_select_bars(pdev, IORESOURCE_MEM));
2665 err_pci_reg:
2666 err_dma:
2667 	pci_disable_device(pdev);
2668 	return err;
2669 }
2670 
2671 #ifdef CONFIG_PCI_IOV
2672 static int igb_disable_sriov(struct pci_dev *pdev)
2673 {
2674 	struct net_device *netdev = pci_get_drvdata(pdev);
2675 	struct igb_adapter *adapter = netdev_priv(netdev);
2676 	struct e1000_hw *hw = &adapter->hw;
2677 
2678 	/* reclaim resources allocated to VFs */
2679 	if (adapter->vf_data) {
2680 		/* disable iov and allow time for transactions to clear */
2681 		if (pci_vfs_assigned(pdev)) {
2682 			dev_warn(&pdev->dev,
2683 				 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2684 			return -EPERM;
2685 		} else {
2686 			pci_disable_sriov(pdev);
2687 			msleep(500);
2688 		}
2689 
2690 		kfree(adapter->vf_data);
2691 		adapter->vf_data = NULL;
2692 		adapter->vfs_allocated_count = 0;
2693 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2694 		wrfl();
2695 		msleep(100);
2696 		dev_info(&pdev->dev, "IOV Disabled\n");
2697 
2698 		/* Re-enable DMA Coalescing flag since IOV is turned off */
2699 		adapter->flags |= IGB_FLAG_DMAC;
2700 	}
2701 
2702 	return 0;
2703 }
2704 
2705 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2706 {
2707 	struct net_device *netdev = pci_get_drvdata(pdev);
2708 	struct igb_adapter *adapter = netdev_priv(netdev);
2709 	int old_vfs = pci_num_vf(pdev);
2710 	int err = 0;
2711 	int i;
2712 
2713 	if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2714 		err = -EPERM;
2715 		goto out;
2716 	}
2717 	if (!num_vfs)
2718 		goto out;
2719 
2720 	if (old_vfs) {
2721 		dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2722 			 old_vfs, max_vfs);
2723 		adapter->vfs_allocated_count = old_vfs;
2724 	} else
2725 		adapter->vfs_allocated_count = num_vfs;
2726 
2727 	adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2728 				sizeof(struct vf_data_storage), GFP_KERNEL);
2729 
2730 	/* if allocation failed then we do not support SR-IOV */
2731 	if (!adapter->vf_data) {
2732 		adapter->vfs_allocated_count = 0;
2733 		dev_err(&pdev->dev,
2734 			"Unable to allocate memory for VF Data Storage\n");
2735 		err = -ENOMEM;
2736 		goto out;
2737 	}
2738 
2739 	/* only call pci_enable_sriov() if no VFs are allocated already */
2740 	if (!old_vfs) {
2741 		err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2742 		if (err)
2743 			goto err_out;
2744 	}
2745 	dev_info(&pdev->dev, "%d VFs allocated\n",
2746 		 adapter->vfs_allocated_count);
2747 	for (i = 0; i < adapter->vfs_allocated_count; i++)
2748 		igb_vf_configure(adapter, i);
2749 
2750 	/* DMA Coalescing is not supported in IOV mode. */
2751 	adapter->flags &= ~IGB_FLAG_DMAC;
2752 	goto out;
2753 
2754 err_out:
2755 	kfree(adapter->vf_data);
2756 	adapter->vf_data = NULL;
2757 	adapter->vfs_allocated_count = 0;
2758 out:
2759 	return err;
2760 }
2761 
2762 #endif
2763 /**
2764  *  igb_remove_i2c - Cleanup  I2C interface
2765  *  @adapter: pointer to adapter structure
2766  **/
2767 static void igb_remove_i2c(struct igb_adapter *adapter)
2768 {
2769 	/* free the adapter bus structure */
2770 	i2c_del_adapter(&adapter->i2c_adap);
2771 }
2772 
2773 /**
2774  *  igb_remove - Device Removal Routine
2775  *  @pdev: PCI device information struct
2776  *
2777  *  igb_remove is called by the PCI subsystem to alert the driver
2778  *  that it should release a PCI device.  The could be caused by a
2779  *  Hot-Plug event, or because the driver is going to be removed from
2780  *  memory.
2781  **/
2782 static void igb_remove(struct pci_dev *pdev)
2783 {
2784 	struct net_device *netdev = pci_get_drvdata(pdev);
2785 	struct igb_adapter *adapter = netdev_priv(netdev);
2786 	struct e1000_hw *hw = &adapter->hw;
2787 
2788 	pm_runtime_get_noresume(&pdev->dev);
2789 #ifdef CONFIG_IGB_HWMON
2790 	igb_sysfs_exit(adapter);
2791 #endif
2792 	igb_remove_i2c(adapter);
2793 	igb_ptp_stop(adapter);
2794 	/* The watchdog timer may be rescheduled, so explicitly
2795 	 * disable watchdog from being rescheduled.
2796 	 */
2797 	set_bit(__IGB_DOWN, &adapter->state);
2798 	del_timer_sync(&adapter->watchdog_timer);
2799 	del_timer_sync(&adapter->phy_info_timer);
2800 
2801 	cancel_work_sync(&adapter->reset_task);
2802 	cancel_work_sync(&adapter->watchdog_task);
2803 
2804 #ifdef CONFIG_IGB_DCA
2805 	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2806 		dev_info(&pdev->dev, "DCA disabled\n");
2807 		dca_remove_requester(&pdev->dev);
2808 		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2809 		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2810 	}
2811 #endif
2812 
2813 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
2814 	 * would have already happened in close and is redundant.
2815 	 */
2816 	igb_release_hw_control(adapter);
2817 
2818 #ifdef CONFIG_PCI_IOV
2819 	igb_disable_sriov(pdev);
2820 #endif
2821 
2822 	unregister_netdev(netdev);
2823 
2824 	igb_clear_interrupt_scheme(adapter);
2825 
2826 	pci_iounmap(pdev, hw->hw_addr);
2827 	if (hw->flash_address)
2828 		iounmap(hw->flash_address);
2829 	pci_release_selected_regions(pdev,
2830 				     pci_select_bars(pdev, IORESOURCE_MEM));
2831 
2832 	kfree(adapter->shadow_vfta);
2833 	free_netdev(netdev);
2834 
2835 	pci_disable_pcie_error_reporting(pdev);
2836 
2837 	pci_disable_device(pdev);
2838 }
2839 
2840 /**
2841  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2842  *  @adapter: board private structure to initialize
2843  *
2844  *  This function initializes the vf specific data storage and then attempts to
2845  *  allocate the VFs.  The reason for ordering it this way is because it is much
2846  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2847  *  the memory for the VFs.
2848  **/
2849 static void igb_probe_vfs(struct igb_adapter *adapter)
2850 {
2851 #ifdef CONFIG_PCI_IOV
2852 	struct pci_dev *pdev = adapter->pdev;
2853 	struct e1000_hw *hw = &adapter->hw;
2854 
2855 	/* Virtualization features not supported on i210 family. */
2856 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2857 		return;
2858 
2859 	pci_sriov_set_totalvfs(pdev, 7);
2860 	igb_enable_sriov(pdev, max_vfs);
2861 
2862 #endif /* CONFIG_PCI_IOV */
2863 }
2864 
2865 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2866 {
2867 	struct e1000_hw *hw = &adapter->hw;
2868 	u32 max_rss_queues;
2869 
2870 	/* Determine the maximum number of RSS queues supported. */
2871 	switch (hw->mac.type) {
2872 	case e1000_i211:
2873 		max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2874 		break;
2875 	case e1000_82575:
2876 	case e1000_i210:
2877 		max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2878 		break;
2879 	case e1000_i350:
2880 		/* I350 cannot do RSS and SR-IOV at the same time */
2881 		if (!!adapter->vfs_allocated_count) {
2882 			max_rss_queues = 1;
2883 			break;
2884 		}
2885 		/* fall through */
2886 	case e1000_82576:
2887 		if (!!adapter->vfs_allocated_count) {
2888 			max_rss_queues = 2;
2889 			break;
2890 		}
2891 		/* fall through */
2892 	case e1000_82580:
2893 	case e1000_i354:
2894 	default:
2895 		max_rss_queues = IGB_MAX_RX_QUEUES;
2896 		break;
2897 	}
2898 
2899 	adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2900 
2901 	igb_set_flag_queue_pairs(adapter, max_rss_queues);
2902 }
2903 
2904 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2905 			      const u32 max_rss_queues)
2906 {
2907 	struct e1000_hw *hw = &adapter->hw;
2908 
2909 	/* Determine if we need to pair queues. */
2910 	switch (hw->mac.type) {
2911 	case e1000_82575:
2912 	case e1000_i211:
2913 		/* Device supports enough interrupts without queue pairing. */
2914 		break;
2915 	case e1000_82576:
2916 		/* If VFs are going to be allocated with RSS queues then we
2917 		 * should pair the queues in order to conserve interrupts due
2918 		 * to limited supply.
2919 		 */
2920 		if ((adapter->rss_queues > 1) &&
2921 		    (adapter->vfs_allocated_count > 6))
2922 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2923 		/* fall through */
2924 	case e1000_82580:
2925 	case e1000_i350:
2926 	case e1000_i354:
2927 	case e1000_i210:
2928 	default:
2929 		/* If rss_queues > half of max_rss_queues, pair the queues in
2930 		 * order to conserve interrupts due to limited supply.
2931 		 */
2932 		if (adapter->rss_queues > (max_rss_queues / 2))
2933 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2934 		break;
2935 	}
2936 }
2937 
2938 /**
2939  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2940  *  @adapter: board private structure to initialize
2941  *
2942  *  igb_sw_init initializes the Adapter private data structure.
2943  *  Fields are initialized based on PCI device information and
2944  *  OS network device settings (MTU size).
2945  **/
2946 static int igb_sw_init(struct igb_adapter *adapter)
2947 {
2948 	struct e1000_hw *hw = &adapter->hw;
2949 	struct net_device *netdev = adapter->netdev;
2950 	struct pci_dev *pdev = adapter->pdev;
2951 
2952 	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2953 
2954 	/* set default ring sizes */
2955 	adapter->tx_ring_count = IGB_DEFAULT_TXD;
2956 	adapter->rx_ring_count = IGB_DEFAULT_RXD;
2957 
2958 	/* set default ITR values */
2959 	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2960 	adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2961 
2962 	/* set default work limits */
2963 	adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2964 
2965 	adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2966 				  VLAN_HLEN;
2967 	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2968 
2969 	spin_lock_init(&adapter->stats64_lock);
2970 #ifdef CONFIG_PCI_IOV
2971 	switch (hw->mac.type) {
2972 	case e1000_82576:
2973 	case e1000_i350:
2974 		if (max_vfs > 7) {
2975 			dev_warn(&pdev->dev,
2976 				 "Maximum of 7 VFs per PF, using max\n");
2977 			max_vfs = adapter->vfs_allocated_count = 7;
2978 		} else
2979 			adapter->vfs_allocated_count = max_vfs;
2980 		if (adapter->vfs_allocated_count)
2981 			dev_warn(&pdev->dev,
2982 				 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2983 		break;
2984 	default:
2985 		break;
2986 	}
2987 #endif /* CONFIG_PCI_IOV */
2988 
2989 	igb_probe_vfs(adapter);
2990 
2991 	igb_init_queue_configuration(adapter);
2992 
2993 	/* Setup and initialize a copy of the hw vlan table array */
2994 	adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2995 				       GFP_ATOMIC);
2996 
2997 	/* This call may decrease the number of queues */
2998 	if (igb_init_interrupt_scheme(adapter, true)) {
2999 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3000 		return -ENOMEM;
3001 	}
3002 
3003 	/* Explicitly disable IRQ since the NIC can be in any state. */
3004 	igb_irq_disable(adapter);
3005 
3006 	if (hw->mac.type >= e1000_i350)
3007 		adapter->flags &= ~IGB_FLAG_DMAC;
3008 
3009 	set_bit(__IGB_DOWN, &adapter->state);
3010 	return 0;
3011 }
3012 
3013 /**
3014  *  igb_open - Called when a network interface is made active
3015  *  @netdev: network interface device structure
3016  *
3017  *  Returns 0 on success, negative value on failure
3018  *
3019  *  The open entry point is called when a network interface is made
3020  *  active by the system (IFF_UP).  At this point all resources needed
3021  *  for transmit and receive operations are allocated, the interrupt
3022  *  handler is registered with the OS, the watchdog timer is started,
3023  *  and the stack is notified that the interface is ready.
3024  **/
3025 static int __igb_open(struct net_device *netdev, bool resuming)
3026 {
3027 	struct igb_adapter *adapter = netdev_priv(netdev);
3028 	struct e1000_hw *hw = &adapter->hw;
3029 	struct pci_dev *pdev = adapter->pdev;
3030 	int err;
3031 	int i;
3032 
3033 	/* disallow open during test */
3034 	if (test_bit(__IGB_TESTING, &adapter->state)) {
3035 		WARN_ON(resuming);
3036 		return -EBUSY;
3037 	}
3038 
3039 	if (!resuming)
3040 		pm_runtime_get_sync(&pdev->dev);
3041 
3042 	netif_carrier_off(netdev);
3043 
3044 	/* allocate transmit descriptors */
3045 	err = igb_setup_all_tx_resources(adapter);
3046 	if (err)
3047 		goto err_setup_tx;
3048 
3049 	/* allocate receive descriptors */
3050 	err = igb_setup_all_rx_resources(adapter);
3051 	if (err)
3052 		goto err_setup_rx;
3053 
3054 	igb_power_up_link(adapter);
3055 
3056 	/* before we allocate an interrupt, we must be ready to handle it.
3057 	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3058 	 * as soon as we call pci_request_irq, so we have to setup our
3059 	 * clean_rx handler before we do so.
3060 	 */
3061 	igb_configure(adapter);
3062 
3063 	err = igb_request_irq(adapter);
3064 	if (err)
3065 		goto err_req_irq;
3066 
3067 	/* Notify the stack of the actual queue counts. */
3068 	err = netif_set_real_num_tx_queues(adapter->netdev,
3069 					   adapter->num_tx_queues);
3070 	if (err)
3071 		goto err_set_queues;
3072 
3073 	err = netif_set_real_num_rx_queues(adapter->netdev,
3074 					   adapter->num_rx_queues);
3075 	if (err)
3076 		goto err_set_queues;
3077 
3078 	/* From here on the code is the same as igb_up() */
3079 	clear_bit(__IGB_DOWN, &adapter->state);
3080 
3081 	for (i = 0; i < adapter->num_q_vectors; i++)
3082 		napi_enable(&(adapter->q_vector[i]->napi));
3083 
3084 	/* Clear any pending interrupts. */
3085 	rd32(E1000_ICR);
3086 
3087 	igb_irq_enable(adapter);
3088 
3089 	/* notify VFs that reset has been completed */
3090 	if (adapter->vfs_allocated_count) {
3091 		u32 reg_data = rd32(E1000_CTRL_EXT);
3092 
3093 		reg_data |= E1000_CTRL_EXT_PFRSTD;
3094 		wr32(E1000_CTRL_EXT, reg_data);
3095 	}
3096 
3097 	netif_tx_start_all_queues(netdev);
3098 
3099 	if (!resuming)
3100 		pm_runtime_put(&pdev->dev);
3101 
3102 	/* start the watchdog. */
3103 	hw->mac.get_link_status = 1;
3104 	schedule_work(&adapter->watchdog_task);
3105 
3106 	return 0;
3107 
3108 err_set_queues:
3109 	igb_free_irq(adapter);
3110 err_req_irq:
3111 	igb_release_hw_control(adapter);
3112 	igb_power_down_link(adapter);
3113 	igb_free_all_rx_resources(adapter);
3114 err_setup_rx:
3115 	igb_free_all_tx_resources(adapter);
3116 err_setup_tx:
3117 	igb_reset(adapter);
3118 	if (!resuming)
3119 		pm_runtime_put(&pdev->dev);
3120 
3121 	return err;
3122 }
3123 
3124 static int igb_open(struct net_device *netdev)
3125 {
3126 	return __igb_open(netdev, false);
3127 }
3128 
3129 /**
3130  *  igb_close - Disables a network interface
3131  *  @netdev: network interface device structure
3132  *
3133  *  Returns 0, this is not allowed to fail
3134  *
3135  *  The close entry point is called when an interface is de-activated
3136  *  by the OS.  The hardware is still under the driver's control, but
3137  *  needs to be disabled.  A global MAC reset is issued to stop the
3138  *  hardware, and all transmit and receive resources are freed.
3139  **/
3140 static int __igb_close(struct net_device *netdev, bool suspending)
3141 {
3142 	struct igb_adapter *adapter = netdev_priv(netdev);
3143 	struct pci_dev *pdev = adapter->pdev;
3144 
3145 	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3146 
3147 	if (!suspending)
3148 		pm_runtime_get_sync(&pdev->dev);
3149 
3150 	igb_down(adapter);
3151 	igb_free_irq(adapter);
3152 
3153 	igb_free_all_tx_resources(adapter);
3154 	igb_free_all_rx_resources(adapter);
3155 
3156 	if (!suspending)
3157 		pm_runtime_put_sync(&pdev->dev);
3158 	return 0;
3159 }
3160 
3161 static int igb_close(struct net_device *netdev)
3162 {
3163 	return __igb_close(netdev, false);
3164 }
3165 
3166 /**
3167  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
3168  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
3169  *
3170  *  Return 0 on success, negative on failure
3171  **/
3172 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3173 {
3174 	struct device *dev = tx_ring->dev;
3175 	int size;
3176 
3177 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3178 
3179 	tx_ring->tx_buffer_info = vzalloc(size);
3180 	if (!tx_ring->tx_buffer_info)
3181 		goto err;
3182 
3183 	/* round up to nearest 4K */
3184 	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3185 	tx_ring->size = ALIGN(tx_ring->size, 4096);
3186 
3187 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3188 					   &tx_ring->dma, GFP_KERNEL);
3189 	if (!tx_ring->desc)
3190 		goto err;
3191 
3192 	tx_ring->next_to_use = 0;
3193 	tx_ring->next_to_clean = 0;
3194 
3195 	return 0;
3196 
3197 err:
3198 	vfree(tx_ring->tx_buffer_info);
3199 	tx_ring->tx_buffer_info = NULL;
3200 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3201 	return -ENOMEM;
3202 }
3203 
3204 /**
3205  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
3206  *				 (Descriptors) for all queues
3207  *  @adapter: board private structure
3208  *
3209  *  Return 0 on success, negative on failure
3210  **/
3211 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3212 {
3213 	struct pci_dev *pdev = adapter->pdev;
3214 	int i, err = 0;
3215 
3216 	for (i = 0; i < adapter->num_tx_queues; i++) {
3217 		err = igb_setup_tx_resources(adapter->tx_ring[i]);
3218 		if (err) {
3219 			dev_err(&pdev->dev,
3220 				"Allocation for Tx Queue %u failed\n", i);
3221 			for (i--; i >= 0; i--)
3222 				igb_free_tx_resources(adapter->tx_ring[i]);
3223 			break;
3224 		}
3225 	}
3226 
3227 	return err;
3228 }
3229 
3230 /**
3231  *  igb_setup_tctl - configure the transmit control registers
3232  *  @adapter: Board private structure
3233  **/
3234 void igb_setup_tctl(struct igb_adapter *adapter)
3235 {
3236 	struct e1000_hw *hw = &adapter->hw;
3237 	u32 tctl;
3238 
3239 	/* disable queue 0 which is enabled by default on 82575 and 82576 */
3240 	wr32(E1000_TXDCTL(0), 0);
3241 
3242 	/* Program the Transmit Control Register */
3243 	tctl = rd32(E1000_TCTL);
3244 	tctl &= ~E1000_TCTL_CT;
3245 	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3246 		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3247 
3248 	igb_config_collision_dist(hw);
3249 
3250 	/* Enable transmits */
3251 	tctl |= E1000_TCTL_EN;
3252 
3253 	wr32(E1000_TCTL, tctl);
3254 }
3255 
3256 /**
3257  *  igb_configure_tx_ring - Configure transmit ring after Reset
3258  *  @adapter: board private structure
3259  *  @ring: tx ring to configure
3260  *
3261  *  Configure a transmit ring after a reset.
3262  **/
3263 void igb_configure_tx_ring(struct igb_adapter *adapter,
3264 			   struct igb_ring *ring)
3265 {
3266 	struct e1000_hw *hw = &adapter->hw;
3267 	u32 txdctl = 0;
3268 	u64 tdba = ring->dma;
3269 	int reg_idx = ring->reg_idx;
3270 
3271 	/* disable the queue */
3272 	wr32(E1000_TXDCTL(reg_idx), 0);
3273 	wrfl();
3274 	mdelay(10);
3275 
3276 	wr32(E1000_TDLEN(reg_idx),
3277 	     ring->count * sizeof(union e1000_adv_tx_desc));
3278 	wr32(E1000_TDBAL(reg_idx),
3279 	     tdba & 0x00000000ffffffffULL);
3280 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3281 
3282 	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3283 	wr32(E1000_TDH(reg_idx), 0);
3284 	writel(0, ring->tail);
3285 
3286 	txdctl |= IGB_TX_PTHRESH;
3287 	txdctl |= IGB_TX_HTHRESH << 8;
3288 	txdctl |= IGB_TX_WTHRESH << 16;
3289 
3290 	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3291 	wr32(E1000_TXDCTL(reg_idx), txdctl);
3292 }
3293 
3294 /**
3295  *  igb_configure_tx - Configure transmit Unit after Reset
3296  *  @adapter: board private structure
3297  *
3298  *  Configure the Tx unit of the MAC after a reset.
3299  **/
3300 static void igb_configure_tx(struct igb_adapter *adapter)
3301 {
3302 	int i;
3303 
3304 	for (i = 0; i < adapter->num_tx_queues; i++)
3305 		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3306 }
3307 
3308 /**
3309  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3310  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3311  *
3312  *  Returns 0 on success, negative on failure
3313  **/
3314 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3315 {
3316 	struct device *dev = rx_ring->dev;
3317 	int size;
3318 
3319 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3320 
3321 	rx_ring->rx_buffer_info = vzalloc(size);
3322 	if (!rx_ring->rx_buffer_info)
3323 		goto err;
3324 
3325 	/* Round up to nearest 4K */
3326 	rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3327 	rx_ring->size = ALIGN(rx_ring->size, 4096);
3328 
3329 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3330 					   &rx_ring->dma, GFP_KERNEL);
3331 	if (!rx_ring->desc)
3332 		goto err;
3333 
3334 	rx_ring->next_to_alloc = 0;
3335 	rx_ring->next_to_clean = 0;
3336 	rx_ring->next_to_use = 0;
3337 
3338 	return 0;
3339 
3340 err:
3341 	vfree(rx_ring->rx_buffer_info);
3342 	rx_ring->rx_buffer_info = NULL;
3343 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3344 	return -ENOMEM;
3345 }
3346 
3347 /**
3348  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3349  *				 (Descriptors) for all queues
3350  *  @adapter: board private structure
3351  *
3352  *  Return 0 on success, negative on failure
3353  **/
3354 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3355 {
3356 	struct pci_dev *pdev = adapter->pdev;
3357 	int i, err = 0;
3358 
3359 	for (i = 0; i < adapter->num_rx_queues; i++) {
3360 		err = igb_setup_rx_resources(adapter->rx_ring[i]);
3361 		if (err) {
3362 			dev_err(&pdev->dev,
3363 				"Allocation for Rx Queue %u failed\n", i);
3364 			for (i--; i >= 0; i--)
3365 				igb_free_rx_resources(adapter->rx_ring[i]);
3366 			break;
3367 		}
3368 	}
3369 
3370 	return err;
3371 }
3372 
3373 /**
3374  *  igb_setup_mrqc - configure the multiple receive queue control registers
3375  *  @adapter: Board private structure
3376  **/
3377 static void igb_setup_mrqc(struct igb_adapter *adapter)
3378 {
3379 	struct e1000_hw *hw = &adapter->hw;
3380 	u32 mrqc, rxcsum;
3381 	u32 j, num_rx_queues;
3382 	u32 rss_key[10];
3383 
3384 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
3385 	for (j = 0; j < 10; j++)
3386 		wr32(E1000_RSSRK(j), rss_key[j]);
3387 
3388 	num_rx_queues = adapter->rss_queues;
3389 
3390 	switch (hw->mac.type) {
3391 	case e1000_82576:
3392 		/* 82576 supports 2 RSS queues for SR-IOV */
3393 		if (adapter->vfs_allocated_count)
3394 			num_rx_queues = 2;
3395 		break;
3396 	default:
3397 		break;
3398 	}
3399 
3400 	if (adapter->rss_indir_tbl_init != num_rx_queues) {
3401 		for (j = 0; j < IGB_RETA_SIZE; j++)
3402 			adapter->rss_indir_tbl[j] =
3403 			(j * num_rx_queues) / IGB_RETA_SIZE;
3404 		adapter->rss_indir_tbl_init = num_rx_queues;
3405 	}
3406 	igb_write_rss_indir_tbl(adapter);
3407 
3408 	/* Disable raw packet checksumming so that RSS hash is placed in
3409 	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3410 	 * offloads as they are enabled by default
3411 	 */
3412 	rxcsum = rd32(E1000_RXCSUM);
3413 	rxcsum |= E1000_RXCSUM_PCSD;
3414 
3415 	if (adapter->hw.mac.type >= e1000_82576)
3416 		/* Enable Receive Checksum Offload for SCTP */
3417 		rxcsum |= E1000_RXCSUM_CRCOFL;
3418 
3419 	/* Don't need to set TUOFL or IPOFL, they default to 1 */
3420 	wr32(E1000_RXCSUM, rxcsum);
3421 
3422 	/* Generate RSS hash based on packet types, TCP/UDP
3423 	 * port numbers and/or IPv4/v6 src and dst addresses
3424 	 */
3425 	mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3426 	       E1000_MRQC_RSS_FIELD_IPV4_TCP |
3427 	       E1000_MRQC_RSS_FIELD_IPV6 |
3428 	       E1000_MRQC_RSS_FIELD_IPV6_TCP |
3429 	       E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3430 
3431 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3432 		mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3433 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3434 		mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3435 
3436 	/* If VMDq is enabled then we set the appropriate mode for that, else
3437 	 * we default to RSS so that an RSS hash is calculated per packet even
3438 	 * if we are only using one queue
3439 	 */
3440 	if (adapter->vfs_allocated_count) {
3441 		if (hw->mac.type > e1000_82575) {
3442 			/* Set the default pool for the PF's first queue */
3443 			u32 vtctl = rd32(E1000_VT_CTL);
3444 
3445 			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3446 				   E1000_VT_CTL_DISABLE_DEF_POOL);
3447 			vtctl |= adapter->vfs_allocated_count <<
3448 				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3449 			wr32(E1000_VT_CTL, vtctl);
3450 		}
3451 		if (adapter->rss_queues > 1)
3452 			mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3453 		else
3454 			mrqc |= E1000_MRQC_ENABLE_VMDQ;
3455 	} else {
3456 		if (hw->mac.type != e1000_i211)
3457 			mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3458 	}
3459 	igb_vmm_control(adapter);
3460 
3461 	wr32(E1000_MRQC, mrqc);
3462 }
3463 
3464 /**
3465  *  igb_setup_rctl - configure the receive control registers
3466  *  @adapter: Board private structure
3467  **/
3468 void igb_setup_rctl(struct igb_adapter *adapter)
3469 {
3470 	struct e1000_hw *hw = &adapter->hw;
3471 	u32 rctl;
3472 
3473 	rctl = rd32(E1000_RCTL);
3474 
3475 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3476 	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3477 
3478 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3479 		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3480 
3481 	/* enable stripping of CRC. It's unlikely this will break BMC
3482 	 * redirection as it did with e1000. Newer features require
3483 	 * that the HW strips the CRC.
3484 	 */
3485 	rctl |= E1000_RCTL_SECRC;
3486 
3487 	/* disable store bad packets and clear size bits. */
3488 	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3489 
3490 	/* enable LPE to prevent packets larger than max_frame_size */
3491 	rctl |= E1000_RCTL_LPE;
3492 
3493 	/* disable queue 0 to prevent tail write w/o re-config */
3494 	wr32(E1000_RXDCTL(0), 0);
3495 
3496 	/* Attention!!!  For SR-IOV PF driver operations you must enable
3497 	 * queue drop for all VF and PF queues to prevent head of line blocking
3498 	 * if an un-trusted VF does not provide descriptors to hardware.
3499 	 */
3500 	if (adapter->vfs_allocated_count) {
3501 		/* set all queue drop enable bits */
3502 		wr32(E1000_QDE, ALL_QUEUES);
3503 	}
3504 
3505 	/* This is useful for sniffing bad packets. */
3506 	if (adapter->netdev->features & NETIF_F_RXALL) {
3507 		/* UPE and MPE will be handled by normal PROMISC logic
3508 		 * in e1000e_set_rx_mode
3509 		 */
3510 		rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3511 			 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3512 			 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3513 
3514 		rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3515 			  E1000_RCTL_DPF | /* Allow filtered pause */
3516 			  E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3517 		/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3518 		 * and that breaks VLANs.
3519 		 */
3520 	}
3521 
3522 	wr32(E1000_RCTL, rctl);
3523 }
3524 
3525 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3526 				   int vfn)
3527 {
3528 	struct e1000_hw *hw = &adapter->hw;
3529 	u32 vmolr;
3530 
3531 	/* if it isn't the PF check to see if VFs are enabled and
3532 	 * increase the size to support vlan tags
3533 	 */
3534 	if (vfn < adapter->vfs_allocated_count &&
3535 	    adapter->vf_data[vfn].vlans_enabled)
3536 		size += VLAN_TAG_SIZE;
3537 
3538 	vmolr = rd32(E1000_VMOLR(vfn));
3539 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
3540 	vmolr |= size | E1000_VMOLR_LPE;
3541 	wr32(E1000_VMOLR(vfn), vmolr);
3542 
3543 	return 0;
3544 }
3545 
3546 /**
3547  *  igb_rlpml_set - set maximum receive packet size
3548  *  @adapter: board private structure
3549  *
3550  *  Configure maximum receivable packet size.
3551  **/
3552 static void igb_rlpml_set(struct igb_adapter *adapter)
3553 {
3554 	u32 max_frame_size = adapter->max_frame_size;
3555 	struct e1000_hw *hw = &adapter->hw;
3556 	u16 pf_id = adapter->vfs_allocated_count;
3557 
3558 	if (pf_id) {
3559 		igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3560 		/* If we're in VMDQ or SR-IOV mode, then set global RLPML
3561 		 * to our max jumbo frame size, in case we need to enable
3562 		 * jumbo frames on one of the rings later.
3563 		 * This will not pass over-length frames into the default
3564 		 * queue because it's gated by the VMOLR.RLPML.
3565 		 */
3566 		max_frame_size = MAX_JUMBO_FRAME_SIZE;
3567 	}
3568 
3569 	wr32(E1000_RLPML, max_frame_size);
3570 }
3571 
3572 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3573 				 int vfn, bool aupe)
3574 {
3575 	struct e1000_hw *hw = &adapter->hw;
3576 	u32 vmolr;
3577 
3578 	/* This register exists only on 82576 and newer so if we are older then
3579 	 * we should exit and do nothing
3580 	 */
3581 	if (hw->mac.type < e1000_82576)
3582 		return;
3583 
3584 	vmolr = rd32(E1000_VMOLR(vfn));
3585 	vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3586 	if (hw->mac.type == e1000_i350) {
3587 		u32 dvmolr;
3588 
3589 		dvmolr = rd32(E1000_DVMOLR(vfn));
3590 		dvmolr |= E1000_DVMOLR_STRVLAN;
3591 		wr32(E1000_DVMOLR(vfn), dvmolr);
3592 	}
3593 	if (aupe)
3594 		vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3595 	else
3596 		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3597 
3598 	/* clear all bits that might not be set */
3599 	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3600 
3601 	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3602 		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3603 	/* for VMDq only allow the VFs and pool 0 to accept broadcast and
3604 	 * multicast packets
3605 	 */
3606 	if (vfn <= adapter->vfs_allocated_count)
3607 		vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3608 
3609 	wr32(E1000_VMOLR(vfn), vmolr);
3610 }
3611 
3612 /**
3613  *  igb_configure_rx_ring - Configure a receive ring after Reset
3614  *  @adapter: board private structure
3615  *  @ring: receive ring to be configured
3616  *
3617  *  Configure the Rx unit of the MAC after a reset.
3618  **/
3619 void igb_configure_rx_ring(struct igb_adapter *adapter,
3620 			   struct igb_ring *ring)
3621 {
3622 	struct e1000_hw *hw = &adapter->hw;
3623 	u64 rdba = ring->dma;
3624 	int reg_idx = ring->reg_idx;
3625 	u32 srrctl = 0, rxdctl = 0;
3626 
3627 	/* disable the queue */
3628 	wr32(E1000_RXDCTL(reg_idx), 0);
3629 
3630 	/* Set DMA base address registers */
3631 	wr32(E1000_RDBAL(reg_idx),
3632 	     rdba & 0x00000000ffffffffULL);
3633 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3634 	wr32(E1000_RDLEN(reg_idx),
3635 	     ring->count * sizeof(union e1000_adv_rx_desc));
3636 
3637 	/* initialize head and tail */
3638 	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3639 	wr32(E1000_RDH(reg_idx), 0);
3640 	writel(0, ring->tail);
3641 
3642 	/* set descriptor configuration */
3643 	srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3644 	srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3645 	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3646 	if (hw->mac.type >= e1000_82580)
3647 		srrctl |= E1000_SRRCTL_TIMESTAMP;
3648 	/* Only set Drop Enable if we are supporting multiple queues */
3649 	if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3650 		srrctl |= E1000_SRRCTL_DROP_EN;
3651 
3652 	wr32(E1000_SRRCTL(reg_idx), srrctl);
3653 
3654 	/* set filtering for VMDQ pools */
3655 	igb_set_vmolr(adapter, reg_idx & 0x7, true);
3656 
3657 	rxdctl |= IGB_RX_PTHRESH;
3658 	rxdctl |= IGB_RX_HTHRESH << 8;
3659 	rxdctl |= IGB_RX_WTHRESH << 16;
3660 
3661 	/* enable receive descriptor fetching */
3662 	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3663 	wr32(E1000_RXDCTL(reg_idx), rxdctl);
3664 }
3665 
3666 /**
3667  *  igb_configure_rx - Configure receive Unit after Reset
3668  *  @adapter: board private structure
3669  *
3670  *  Configure the Rx unit of the MAC after a reset.
3671  **/
3672 static void igb_configure_rx(struct igb_adapter *adapter)
3673 {
3674 	int i;
3675 
3676 	/* set UTA to appropriate mode */
3677 	igb_set_uta(adapter);
3678 
3679 	/* set the correct pool for the PF default MAC address in entry 0 */
3680 	igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3681 			 adapter->vfs_allocated_count);
3682 
3683 	/* Setup the HW Rx Head and Tail Descriptor Pointers and
3684 	 * the Base and Length of the Rx Descriptor Ring
3685 	 */
3686 	for (i = 0; i < adapter->num_rx_queues; i++)
3687 		igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3688 }
3689 
3690 /**
3691  *  igb_free_tx_resources - Free Tx Resources per Queue
3692  *  @tx_ring: Tx descriptor ring for a specific queue
3693  *
3694  *  Free all transmit software resources
3695  **/
3696 void igb_free_tx_resources(struct igb_ring *tx_ring)
3697 {
3698 	igb_clean_tx_ring(tx_ring);
3699 
3700 	vfree(tx_ring->tx_buffer_info);
3701 	tx_ring->tx_buffer_info = NULL;
3702 
3703 	/* if not set, then don't free */
3704 	if (!tx_ring->desc)
3705 		return;
3706 
3707 	dma_free_coherent(tx_ring->dev, tx_ring->size,
3708 			  tx_ring->desc, tx_ring->dma);
3709 
3710 	tx_ring->desc = NULL;
3711 }
3712 
3713 /**
3714  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3715  *  @adapter: board private structure
3716  *
3717  *  Free all transmit software resources
3718  **/
3719 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3720 {
3721 	int i;
3722 
3723 	for (i = 0; i < adapter->num_tx_queues; i++)
3724 		if (adapter->tx_ring[i])
3725 			igb_free_tx_resources(adapter->tx_ring[i]);
3726 }
3727 
3728 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3729 				    struct igb_tx_buffer *tx_buffer)
3730 {
3731 	if (tx_buffer->skb) {
3732 		dev_kfree_skb_any(tx_buffer->skb);
3733 		if (dma_unmap_len(tx_buffer, len))
3734 			dma_unmap_single(ring->dev,
3735 					 dma_unmap_addr(tx_buffer, dma),
3736 					 dma_unmap_len(tx_buffer, len),
3737 					 DMA_TO_DEVICE);
3738 	} else if (dma_unmap_len(tx_buffer, len)) {
3739 		dma_unmap_page(ring->dev,
3740 			       dma_unmap_addr(tx_buffer, dma),
3741 			       dma_unmap_len(tx_buffer, len),
3742 			       DMA_TO_DEVICE);
3743 	}
3744 	tx_buffer->next_to_watch = NULL;
3745 	tx_buffer->skb = NULL;
3746 	dma_unmap_len_set(tx_buffer, len, 0);
3747 	/* buffer_info must be completely set up in the transmit path */
3748 }
3749 
3750 /**
3751  *  igb_clean_tx_ring - Free Tx Buffers
3752  *  @tx_ring: ring to be cleaned
3753  **/
3754 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3755 {
3756 	struct igb_tx_buffer *buffer_info;
3757 	unsigned long size;
3758 	u16 i;
3759 
3760 	if (!tx_ring->tx_buffer_info)
3761 		return;
3762 	/* Free all the Tx ring sk_buffs */
3763 
3764 	for (i = 0; i < tx_ring->count; i++) {
3765 		buffer_info = &tx_ring->tx_buffer_info[i];
3766 		igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3767 	}
3768 
3769 	netdev_tx_reset_queue(txring_txq(tx_ring));
3770 
3771 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3772 	memset(tx_ring->tx_buffer_info, 0, size);
3773 
3774 	/* Zero out the descriptor ring */
3775 	memset(tx_ring->desc, 0, tx_ring->size);
3776 
3777 	tx_ring->next_to_use = 0;
3778 	tx_ring->next_to_clean = 0;
3779 }
3780 
3781 /**
3782  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3783  *  @adapter: board private structure
3784  **/
3785 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3786 {
3787 	int i;
3788 
3789 	for (i = 0; i < adapter->num_tx_queues; i++)
3790 		if (adapter->tx_ring[i])
3791 			igb_clean_tx_ring(adapter->tx_ring[i]);
3792 }
3793 
3794 /**
3795  *  igb_free_rx_resources - Free Rx Resources
3796  *  @rx_ring: ring to clean the resources from
3797  *
3798  *  Free all receive software resources
3799  **/
3800 void igb_free_rx_resources(struct igb_ring *rx_ring)
3801 {
3802 	igb_clean_rx_ring(rx_ring);
3803 
3804 	vfree(rx_ring->rx_buffer_info);
3805 	rx_ring->rx_buffer_info = NULL;
3806 
3807 	/* if not set, then don't free */
3808 	if (!rx_ring->desc)
3809 		return;
3810 
3811 	dma_free_coherent(rx_ring->dev, rx_ring->size,
3812 			  rx_ring->desc, rx_ring->dma);
3813 
3814 	rx_ring->desc = NULL;
3815 }
3816 
3817 /**
3818  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3819  *  @adapter: board private structure
3820  *
3821  *  Free all receive software resources
3822  **/
3823 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3824 {
3825 	int i;
3826 
3827 	for (i = 0; i < adapter->num_rx_queues; i++)
3828 		if (adapter->rx_ring[i])
3829 			igb_free_rx_resources(adapter->rx_ring[i]);
3830 }
3831 
3832 /**
3833  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3834  *  @rx_ring: ring to free buffers from
3835  **/
3836 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3837 {
3838 	unsigned long size;
3839 	u16 i;
3840 
3841 	if (rx_ring->skb)
3842 		dev_kfree_skb(rx_ring->skb);
3843 	rx_ring->skb = NULL;
3844 
3845 	if (!rx_ring->rx_buffer_info)
3846 		return;
3847 
3848 	/* Free all the Rx ring sk_buffs */
3849 	for (i = 0; i < rx_ring->count; i++) {
3850 		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3851 
3852 		if (!buffer_info->page)
3853 			continue;
3854 
3855 		dma_unmap_page(rx_ring->dev,
3856 			       buffer_info->dma,
3857 			       PAGE_SIZE,
3858 			       DMA_FROM_DEVICE);
3859 		__free_page(buffer_info->page);
3860 
3861 		buffer_info->page = NULL;
3862 	}
3863 
3864 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3865 	memset(rx_ring->rx_buffer_info, 0, size);
3866 
3867 	/* Zero out the descriptor ring */
3868 	memset(rx_ring->desc, 0, rx_ring->size);
3869 
3870 	rx_ring->next_to_alloc = 0;
3871 	rx_ring->next_to_clean = 0;
3872 	rx_ring->next_to_use = 0;
3873 }
3874 
3875 /**
3876  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3877  *  @adapter: board private structure
3878  **/
3879 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3880 {
3881 	int i;
3882 
3883 	for (i = 0; i < adapter->num_rx_queues; i++)
3884 		if (adapter->rx_ring[i])
3885 			igb_clean_rx_ring(adapter->rx_ring[i]);
3886 }
3887 
3888 /**
3889  *  igb_set_mac - Change the Ethernet Address of the NIC
3890  *  @netdev: network interface device structure
3891  *  @p: pointer to an address structure
3892  *
3893  *  Returns 0 on success, negative on failure
3894  **/
3895 static int igb_set_mac(struct net_device *netdev, void *p)
3896 {
3897 	struct igb_adapter *adapter = netdev_priv(netdev);
3898 	struct e1000_hw *hw = &adapter->hw;
3899 	struct sockaddr *addr = p;
3900 
3901 	if (!is_valid_ether_addr(addr->sa_data))
3902 		return -EADDRNOTAVAIL;
3903 
3904 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3905 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3906 
3907 	/* set the correct pool for the new PF MAC address in entry 0 */
3908 	igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3909 			 adapter->vfs_allocated_count);
3910 
3911 	return 0;
3912 }
3913 
3914 /**
3915  *  igb_write_mc_addr_list - write multicast addresses to MTA
3916  *  @netdev: network interface device structure
3917  *
3918  *  Writes multicast address list to the MTA hash table.
3919  *  Returns: -ENOMEM on failure
3920  *           0 on no addresses written
3921  *           X on writing X addresses to MTA
3922  **/
3923 static int igb_write_mc_addr_list(struct net_device *netdev)
3924 {
3925 	struct igb_adapter *adapter = netdev_priv(netdev);
3926 	struct e1000_hw *hw = &adapter->hw;
3927 	struct netdev_hw_addr *ha;
3928 	u8  *mta_list;
3929 	int i;
3930 
3931 	if (netdev_mc_empty(netdev)) {
3932 		/* nothing to program, so clear mc list */
3933 		igb_update_mc_addr_list(hw, NULL, 0);
3934 		igb_restore_vf_multicasts(adapter);
3935 		return 0;
3936 	}
3937 
3938 	mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3939 	if (!mta_list)
3940 		return -ENOMEM;
3941 
3942 	/* The shared function expects a packed array of only addresses. */
3943 	i = 0;
3944 	netdev_for_each_mc_addr(ha, netdev)
3945 		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3946 
3947 	igb_update_mc_addr_list(hw, mta_list, i);
3948 	kfree(mta_list);
3949 
3950 	return netdev_mc_count(netdev);
3951 }
3952 
3953 /**
3954  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3955  *  @netdev: network interface device structure
3956  *
3957  *  Writes unicast address list to the RAR table.
3958  *  Returns: -ENOMEM on failure/insufficient address space
3959  *           0 on no addresses written
3960  *           X on writing X addresses to the RAR table
3961  **/
3962 static int igb_write_uc_addr_list(struct net_device *netdev)
3963 {
3964 	struct igb_adapter *adapter = netdev_priv(netdev);
3965 	struct e1000_hw *hw = &adapter->hw;
3966 	unsigned int vfn = adapter->vfs_allocated_count;
3967 	unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3968 	int count = 0;
3969 
3970 	/* return ENOMEM indicating insufficient memory for addresses */
3971 	if (netdev_uc_count(netdev) > rar_entries)
3972 		return -ENOMEM;
3973 
3974 	if (!netdev_uc_empty(netdev) && rar_entries) {
3975 		struct netdev_hw_addr *ha;
3976 
3977 		netdev_for_each_uc_addr(ha, netdev) {
3978 			if (!rar_entries)
3979 				break;
3980 			igb_rar_set_qsel(adapter, ha->addr,
3981 					 rar_entries--,
3982 					 vfn);
3983 			count++;
3984 		}
3985 	}
3986 	/* write the addresses in reverse order to avoid write combining */
3987 	for (; rar_entries > 0 ; rar_entries--) {
3988 		wr32(E1000_RAH(rar_entries), 0);
3989 		wr32(E1000_RAL(rar_entries), 0);
3990 	}
3991 	wrfl();
3992 
3993 	return count;
3994 }
3995 
3996 /**
3997  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3998  *  @netdev: network interface device structure
3999  *
4000  *  The set_rx_mode entry point is called whenever the unicast or multicast
4001  *  address lists or the network interface flags are updated.  This routine is
4002  *  responsible for configuring the hardware for proper unicast, multicast,
4003  *  promiscuous mode, and all-multi behavior.
4004  **/
4005 static void igb_set_rx_mode(struct net_device *netdev)
4006 {
4007 	struct igb_adapter *adapter = netdev_priv(netdev);
4008 	struct e1000_hw *hw = &adapter->hw;
4009 	unsigned int vfn = adapter->vfs_allocated_count;
4010 	u32 rctl, vmolr = 0;
4011 	int count;
4012 
4013 	/* Check for Promiscuous and All Multicast modes */
4014 	rctl = rd32(E1000_RCTL);
4015 
4016 	/* clear the effected bits */
4017 	rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4018 
4019 	if (netdev->flags & IFF_PROMISC) {
4020 		/* retain VLAN HW filtering if in VT mode */
4021 		if (adapter->vfs_allocated_count)
4022 			rctl |= E1000_RCTL_VFE;
4023 		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4024 		vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4025 	} else {
4026 		if (netdev->flags & IFF_ALLMULTI) {
4027 			rctl |= E1000_RCTL_MPE;
4028 			vmolr |= E1000_VMOLR_MPME;
4029 		} else {
4030 			/* Write addresses to the MTA, if the attempt fails
4031 			 * then we should just turn on promiscuous mode so
4032 			 * that we can at least receive multicast traffic
4033 			 */
4034 			count = igb_write_mc_addr_list(netdev);
4035 			if (count < 0) {
4036 				rctl |= E1000_RCTL_MPE;
4037 				vmolr |= E1000_VMOLR_MPME;
4038 			} else if (count) {
4039 				vmolr |= E1000_VMOLR_ROMPE;
4040 			}
4041 		}
4042 		/* Write addresses to available RAR registers, if there is not
4043 		 * sufficient space to store all the addresses then enable
4044 		 * unicast promiscuous mode
4045 		 */
4046 		count = igb_write_uc_addr_list(netdev);
4047 		if (count < 0) {
4048 			rctl |= E1000_RCTL_UPE;
4049 			vmolr |= E1000_VMOLR_ROPE;
4050 		}
4051 		rctl |= E1000_RCTL_VFE;
4052 	}
4053 	wr32(E1000_RCTL, rctl);
4054 
4055 	/* In order to support SR-IOV and eventually VMDq it is necessary to set
4056 	 * the VMOLR to enable the appropriate modes.  Without this workaround
4057 	 * we will have issues with VLAN tag stripping not being done for frames
4058 	 * that are only arriving because we are the default pool
4059 	 */
4060 	if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4061 		return;
4062 
4063 	vmolr |= rd32(E1000_VMOLR(vfn)) &
4064 		 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4065 	wr32(E1000_VMOLR(vfn), vmolr);
4066 	igb_restore_vf_multicasts(adapter);
4067 }
4068 
4069 static void igb_check_wvbr(struct igb_adapter *adapter)
4070 {
4071 	struct e1000_hw *hw = &adapter->hw;
4072 	u32 wvbr = 0;
4073 
4074 	switch (hw->mac.type) {
4075 	case e1000_82576:
4076 	case e1000_i350:
4077 		wvbr = rd32(E1000_WVBR);
4078 		if (!wvbr)
4079 			return;
4080 		break;
4081 	default:
4082 		break;
4083 	}
4084 
4085 	adapter->wvbr |= wvbr;
4086 }
4087 
4088 #define IGB_STAGGERED_QUEUE_OFFSET 8
4089 
4090 static void igb_spoof_check(struct igb_adapter *adapter)
4091 {
4092 	int j;
4093 
4094 	if (!adapter->wvbr)
4095 		return;
4096 
4097 	for (j = 0; j < adapter->vfs_allocated_count; j++) {
4098 		if (adapter->wvbr & (1 << j) ||
4099 		    adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4100 			dev_warn(&adapter->pdev->dev,
4101 				"Spoof event(s) detected on VF %d\n", j);
4102 			adapter->wvbr &=
4103 				~((1 << j) |
4104 				  (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4105 		}
4106 	}
4107 }
4108 
4109 /* Need to wait a few seconds after link up to get diagnostic information from
4110  * the phy
4111  */
4112 static void igb_update_phy_info(unsigned long data)
4113 {
4114 	struct igb_adapter *adapter = (struct igb_adapter *) data;
4115 	igb_get_phy_info(&adapter->hw);
4116 }
4117 
4118 /**
4119  *  igb_has_link - check shared code for link and determine up/down
4120  *  @adapter: pointer to driver private info
4121  **/
4122 bool igb_has_link(struct igb_adapter *adapter)
4123 {
4124 	struct e1000_hw *hw = &adapter->hw;
4125 	bool link_active = false;
4126 
4127 	/* get_link_status is set on LSC (link status) interrupt or
4128 	 * rx sequence error interrupt.  get_link_status will stay
4129 	 * false until the e1000_check_for_link establishes link
4130 	 * for copper adapters ONLY
4131 	 */
4132 	switch (hw->phy.media_type) {
4133 	case e1000_media_type_copper:
4134 		if (!hw->mac.get_link_status)
4135 			return true;
4136 	case e1000_media_type_internal_serdes:
4137 		hw->mac.ops.check_for_link(hw);
4138 		link_active = !hw->mac.get_link_status;
4139 		break;
4140 	default:
4141 	case e1000_media_type_unknown:
4142 		break;
4143 	}
4144 
4145 	if (((hw->mac.type == e1000_i210) ||
4146 	     (hw->mac.type == e1000_i211)) &&
4147 	     (hw->phy.id == I210_I_PHY_ID)) {
4148 		if (!netif_carrier_ok(adapter->netdev)) {
4149 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4150 		} else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4151 			adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4152 			adapter->link_check_timeout = jiffies;
4153 		}
4154 	}
4155 
4156 	return link_active;
4157 }
4158 
4159 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4160 {
4161 	bool ret = false;
4162 	u32 ctrl_ext, thstat;
4163 
4164 	/* check for thermal sensor event on i350 copper only */
4165 	if (hw->mac.type == e1000_i350) {
4166 		thstat = rd32(E1000_THSTAT);
4167 		ctrl_ext = rd32(E1000_CTRL_EXT);
4168 
4169 		if ((hw->phy.media_type == e1000_media_type_copper) &&
4170 		    !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4171 			ret = !!(thstat & event);
4172 	}
4173 
4174 	return ret;
4175 }
4176 
4177 /**
4178  *  igb_check_lvmmc - check for malformed packets received
4179  *  and indicated in LVMMC register
4180  *  @adapter: pointer to adapter
4181  **/
4182 static void igb_check_lvmmc(struct igb_adapter *adapter)
4183 {
4184 	struct e1000_hw *hw = &adapter->hw;
4185 	u32 lvmmc;
4186 
4187 	lvmmc = rd32(E1000_LVMMC);
4188 	if (lvmmc) {
4189 		if (unlikely(net_ratelimit())) {
4190 			netdev_warn(adapter->netdev,
4191 				    "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4192 				    lvmmc);
4193 		}
4194 	}
4195 }
4196 
4197 /**
4198  *  igb_watchdog - Timer Call-back
4199  *  @data: pointer to adapter cast into an unsigned long
4200  **/
4201 static void igb_watchdog(unsigned long data)
4202 {
4203 	struct igb_adapter *adapter = (struct igb_adapter *)data;
4204 	/* Do the rest outside of interrupt context */
4205 	schedule_work(&adapter->watchdog_task);
4206 }
4207 
4208 static void igb_watchdog_task(struct work_struct *work)
4209 {
4210 	struct igb_adapter *adapter = container_of(work,
4211 						   struct igb_adapter,
4212 						   watchdog_task);
4213 	struct e1000_hw *hw = &adapter->hw;
4214 	struct e1000_phy_info *phy = &hw->phy;
4215 	struct net_device *netdev = adapter->netdev;
4216 	u32 link;
4217 	int i;
4218 	u32 connsw;
4219 
4220 	link = igb_has_link(adapter);
4221 
4222 	if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4223 		if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4224 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4225 		else
4226 			link = false;
4227 	}
4228 
4229 	/* Force link down if we have fiber to swap to */
4230 	if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4231 		if (hw->phy.media_type == e1000_media_type_copper) {
4232 			connsw = rd32(E1000_CONNSW);
4233 			if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4234 				link = 0;
4235 		}
4236 	}
4237 	if (link) {
4238 		/* Perform a reset if the media type changed. */
4239 		if (hw->dev_spec._82575.media_changed) {
4240 			hw->dev_spec._82575.media_changed = false;
4241 			adapter->flags |= IGB_FLAG_MEDIA_RESET;
4242 			igb_reset(adapter);
4243 		}
4244 		/* Cancel scheduled suspend requests. */
4245 		pm_runtime_resume(netdev->dev.parent);
4246 
4247 		if (!netif_carrier_ok(netdev)) {
4248 			u32 ctrl;
4249 
4250 			hw->mac.ops.get_speed_and_duplex(hw,
4251 							 &adapter->link_speed,
4252 							 &adapter->link_duplex);
4253 
4254 			ctrl = rd32(E1000_CTRL);
4255 			/* Links status message must follow this format */
4256 			netdev_info(netdev,
4257 			       "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4258 			       netdev->name,
4259 			       adapter->link_speed,
4260 			       adapter->link_duplex == FULL_DUPLEX ?
4261 			       "Full" : "Half",
4262 			       (ctrl & E1000_CTRL_TFCE) &&
4263 			       (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4264 			       (ctrl & E1000_CTRL_RFCE) ?  "RX" :
4265 			       (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
4266 
4267 			/* disable EEE if enabled */
4268 			if ((adapter->flags & IGB_FLAG_EEE) &&
4269 				(adapter->link_duplex == HALF_DUPLEX)) {
4270 				dev_info(&adapter->pdev->dev,
4271 				"EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4272 				adapter->hw.dev_spec._82575.eee_disable = true;
4273 				adapter->flags &= ~IGB_FLAG_EEE;
4274 			}
4275 
4276 			/* check if SmartSpeed worked */
4277 			igb_check_downshift(hw);
4278 			if (phy->speed_downgraded)
4279 				netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4280 
4281 			/* check for thermal sensor event */
4282 			if (igb_thermal_sensor_event(hw,
4283 			    E1000_THSTAT_LINK_THROTTLE))
4284 				netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4285 
4286 			/* adjust timeout factor according to speed/duplex */
4287 			adapter->tx_timeout_factor = 1;
4288 			switch (adapter->link_speed) {
4289 			case SPEED_10:
4290 				adapter->tx_timeout_factor = 14;
4291 				break;
4292 			case SPEED_100:
4293 				/* maybe add some timeout factor ? */
4294 				break;
4295 			}
4296 
4297 			netif_carrier_on(netdev);
4298 
4299 			igb_ping_all_vfs(adapter);
4300 			igb_check_vf_rate_limit(adapter);
4301 
4302 			/* link state has changed, schedule phy info update */
4303 			if (!test_bit(__IGB_DOWN, &adapter->state))
4304 				mod_timer(&adapter->phy_info_timer,
4305 					  round_jiffies(jiffies + 2 * HZ));
4306 		}
4307 	} else {
4308 		if (netif_carrier_ok(netdev)) {
4309 			adapter->link_speed = 0;
4310 			adapter->link_duplex = 0;
4311 
4312 			/* check for thermal sensor event */
4313 			if (igb_thermal_sensor_event(hw,
4314 			    E1000_THSTAT_PWR_DOWN)) {
4315 				netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4316 			}
4317 
4318 			/* Links status message must follow this format */
4319 			netdev_info(netdev, "igb: %s NIC Link is Down\n",
4320 			       netdev->name);
4321 			netif_carrier_off(netdev);
4322 
4323 			igb_ping_all_vfs(adapter);
4324 
4325 			/* link state has changed, schedule phy info update */
4326 			if (!test_bit(__IGB_DOWN, &adapter->state))
4327 				mod_timer(&adapter->phy_info_timer,
4328 					  round_jiffies(jiffies + 2 * HZ));
4329 
4330 			/* link is down, time to check for alternate media */
4331 			if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4332 				igb_check_swap_media(adapter);
4333 				if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4334 					schedule_work(&adapter->reset_task);
4335 					/* return immediately */
4336 					return;
4337 				}
4338 			}
4339 			pm_schedule_suspend(netdev->dev.parent,
4340 					    MSEC_PER_SEC * 5);
4341 
4342 		/* also check for alternate media here */
4343 		} else if (!netif_carrier_ok(netdev) &&
4344 			   (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4345 			igb_check_swap_media(adapter);
4346 			if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4347 				schedule_work(&adapter->reset_task);
4348 				/* return immediately */
4349 				return;
4350 			}
4351 		}
4352 	}
4353 
4354 	spin_lock(&adapter->stats64_lock);
4355 	igb_update_stats(adapter, &adapter->stats64);
4356 	spin_unlock(&adapter->stats64_lock);
4357 
4358 	for (i = 0; i < adapter->num_tx_queues; i++) {
4359 		struct igb_ring *tx_ring = adapter->tx_ring[i];
4360 		if (!netif_carrier_ok(netdev)) {
4361 			/* We've lost link, so the controller stops DMA,
4362 			 * but we've got queued Tx work that's never going
4363 			 * to get done, so reset controller to flush Tx.
4364 			 * (Do the reset outside of interrupt context).
4365 			 */
4366 			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4367 				adapter->tx_timeout_count++;
4368 				schedule_work(&adapter->reset_task);
4369 				/* return immediately since reset is imminent */
4370 				return;
4371 			}
4372 		}
4373 
4374 		/* Force detection of hung controller every watchdog period */
4375 		set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4376 	}
4377 
4378 	/* Cause software interrupt to ensure Rx ring is cleaned */
4379 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4380 		u32 eics = 0;
4381 
4382 		for (i = 0; i < adapter->num_q_vectors; i++)
4383 			eics |= adapter->q_vector[i]->eims_value;
4384 		wr32(E1000_EICS, eics);
4385 	} else {
4386 		wr32(E1000_ICS, E1000_ICS_RXDMT0);
4387 	}
4388 
4389 	igb_spoof_check(adapter);
4390 	igb_ptp_rx_hang(adapter);
4391 
4392 	/* Check LVMMC register on i350/i354 only */
4393 	if ((adapter->hw.mac.type == e1000_i350) ||
4394 	    (adapter->hw.mac.type == e1000_i354))
4395 		igb_check_lvmmc(adapter);
4396 
4397 	/* Reset the timer */
4398 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
4399 		if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4400 			mod_timer(&adapter->watchdog_timer,
4401 				  round_jiffies(jiffies +  HZ));
4402 		else
4403 			mod_timer(&adapter->watchdog_timer,
4404 				  round_jiffies(jiffies + 2 * HZ));
4405 	}
4406 }
4407 
4408 enum latency_range {
4409 	lowest_latency = 0,
4410 	low_latency = 1,
4411 	bulk_latency = 2,
4412 	latency_invalid = 255
4413 };
4414 
4415 /**
4416  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4417  *  @q_vector: pointer to q_vector
4418  *
4419  *  Stores a new ITR value based on strictly on packet size.  This
4420  *  algorithm is less sophisticated than that used in igb_update_itr,
4421  *  due to the difficulty of synchronizing statistics across multiple
4422  *  receive rings.  The divisors and thresholds used by this function
4423  *  were determined based on theoretical maximum wire speed and testing
4424  *  data, in order to minimize response time while increasing bulk
4425  *  throughput.
4426  *  This functionality is controlled by ethtool's coalescing settings.
4427  *  NOTE:  This function is called only when operating in a multiqueue
4428  *         receive environment.
4429  **/
4430 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4431 {
4432 	int new_val = q_vector->itr_val;
4433 	int avg_wire_size = 0;
4434 	struct igb_adapter *adapter = q_vector->adapter;
4435 	unsigned int packets;
4436 
4437 	/* For non-gigabit speeds, just fix the interrupt rate at 4000
4438 	 * ints/sec - ITR timer value of 120 ticks.
4439 	 */
4440 	if (adapter->link_speed != SPEED_1000) {
4441 		new_val = IGB_4K_ITR;
4442 		goto set_itr_val;
4443 	}
4444 
4445 	packets = q_vector->rx.total_packets;
4446 	if (packets)
4447 		avg_wire_size = q_vector->rx.total_bytes / packets;
4448 
4449 	packets = q_vector->tx.total_packets;
4450 	if (packets)
4451 		avg_wire_size = max_t(u32, avg_wire_size,
4452 				      q_vector->tx.total_bytes / packets);
4453 
4454 	/* if avg_wire_size isn't set no work was done */
4455 	if (!avg_wire_size)
4456 		goto clear_counts;
4457 
4458 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
4459 	avg_wire_size += 24;
4460 
4461 	/* Don't starve jumbo frames */
4462 	avg_wire_size = min(avg_wire_size, 3000);
4463 
4464 	/* Give a little boost to mid-size frames */
4465 	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4466 		new_val = avg_wire_size / 3;
4467 	else
4468 		new_val = avg_wire_size / 2;
4469 
4470 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
4471 	if (new_val < IGB_20K_ITR &&
4472 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4473 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4474 		new_val = IGB_20K_ITR;
4475 
4476 set_itr_val:
4477 	if (new_val != q_vector->itr_val) {
4478 		q_vector->itr_val = new_val;
4479 		q_vector->set_itr = 1;
4480 	}
4481 clear_counts:
4482 	q_vector->rx.total_bytes = 0;
4483 	q_vector->rx.total_packets = 0;
4484 	q_vector->tx.total_bytes = 0;
4485 	q_vector->tx.total_packets = 0;
4486 }
4487 
4488 /**
4489  *  igb_update_itr - update the dynamic ITR value based on statistics
4490  *  @q_vector: pointer to q_vector
4491  *  @ring_container: ring info to update the itr for
4492  *
4493  *  Stores a new ITR value based on packets and byte
4494  *  counts during the last interrupt.  The advantage of per interrupt
4495  *  computation is faster updates and more accurate ITR for the current
4496  *  traffic pattern.  Constants in this function were computed
4497  *  based on theoretical maximum wire speed and thresholds were set based
4498  *  on testing data as well as attempting to minimize response time
4499  *  while increasing bulk throughput.
4500  *  This functionality is controlled by ethtool's coalescing settings.
4501  *  NOTE:  These calculations are only valid when operating in a single-
4502  *         queue environment.
4503  **/
4504 static void igb_update_itr(struct igb_q_vector *q_vector,
4505 			   struct igb_ring_container *ring_container)
4506 {
4507 	unsigned int packets = ring_container->total_packets;
4508 	unsigned int bytes = ring_container->total_bytes;
4509 	u8 itrval = ring_container->itr;
4510 
4511 	/* no packets, exit with status unchanged */
4512 	if (packets == 0)
4513 		return;
4514 
4515 	switch (itrval) {
4516 	case lowest_latency:
4517 		/* handle TSO and jumbo frames */
4518 		if (bytes/packets > 8000)
4519 			itrval = bulk_latency;
4520 		else if ((packets < 5) && (bytes > 512))
4521 			itrval = low_latency;
4522 		break;
4523 	case low_latency:  /* 50 usec aka 20000 ints/s */
4524 		if (bytes > 10000) {
4525 			/* this if handles the TSO accounting */
4526 			if (bytes/packets > 8000)
4527 				itrval = bulk_latency;
4528 			else if ((packets < 10) || ((bytes/packets) > 1200))
4529 				itrval = bulk_latency;
4530 			else if ((packets > 35))
4531 				itrval = lowest_latency;
4532 		} else if (bytes/packets > 2000) {
4533 			itrval = bulk_latency;
4534 		} else if (packets <= 2 && bytes < 512) {
4535 			itrval = lowest_latency;
4536 		}
4537 		break;
4538 	case bulk_latency: /* 250 usec aka 4000 ints/s */
4539 		if (bytes > 25000) {
4540 			if (packets > 35)
4541 				itrval = low_latency;
4542 		} else if (bytes < 1500) {
4543 			itrval = low_latency;
4544 		}
4545 		break;
4546 	}
4547 
4548 	/* clear work counters since we have the values we need */
4549 	ring_container->total_bytes = 0;
4550 	ring_container->total_packets = 0;
4551 
4552 	/* write updated itr to ring container */
4553 	ring_container->itr = itrval;
4554 }
4555 
4556 static void igb_set_itr(struct igb_q_vector *q_vector)
4557 {
4558 	struct igb_adapter *adapter = q_vector->adapter;
4559 	u32 new_itr = q_vector->itr_val;
4560 	u8 current_itr = 0;
4561 
4562 	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4563 	if (adapter->link_speed != SPEED_1000) {
4564 		current_itr = 0;
4565 		new_itr = IGB_4K_ITR;
4566 		goto set_itr_now;
4567 	}
4568 
4569 	igb_update_itr(q_vector, &q_vector->tx);
4570 	igb_update_itr(q_vector, &q_vector->rx);
4571 
4572 	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4573 
4574 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
4575 	if (current_itr == lowest_latency &&
4576 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4577 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4578 		current_itr = low_latency;
4579 
4580 	switch (current_itr) {
4581 	/* counts and packets in update_itr are dependent on these numbers */
4582 	case lowest_latency:
4583 		new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4584 		break;
4585 	case low_latency:
4586 		new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4587 		break;
4588 	case bulk_latency:
4589 		new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4590 		break;
4591 	default:
4592 		break;
4593 	}
4594 
4595 set_itr_now:
4596 	if (new_itr != q_vector->itr_val) {
4597 		/* this attempts to bias the interrupt rate towards Bulk
4598 		 * by adding intermediate steps when interrupt rate is
4599 		 * increasing
4600 		 */
4601 		new_itr = new_itr > q_vector->itr_val ?
4602 			  max((new_itr * q_vector->itr_val) /
4603 			  (new_itr + (q_vector->itr_val >> 2)),
4604 			  new_itr) : new_itr;
4605 		/* Don't write the value here; it resets the adapter's
4606 		 * internal timer, and causes us to delay far longer than
4607 		 * we should between interrupts.  Instead, we write the ITR
4608 		 * value at the beginning of the next interrupt so the timing
4609 		 * ends up being correct.
4610 		 */
4611 		q_vector->itr_val = new_itr;
4612 		q_vector->set_itr = 1;
4613 	}
4614 }
4615 
4616 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4617 			    u32 type_tucmd, u32 mss_l4len_idx)
4618 {
4619 	struct e1000_adv_tx_context_desc *context_desc;
4620 	u16 i = tx_ring->next_to_use;
4621 
4622 	context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4623 
4624 	i++;
4625 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4626 
4627 	/* set bits to identify this as an advanced context descriptor */
4628 	type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4629 
4630 	/* For 82575, context index must be unique per ring. */
4631 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4632 		mss_l4len_idx |= tx_ring->reg_idx << 4;
4633 
4634 	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
4635 	context_desc->seqnum_seed	= 0;
4636 	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
4637 	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);
4638 }
4639 
4640 static int igb_tso(struct igb_ring *tx_ring,
4641 		   struct igb_tx_buffer *first,
4642 		   u8 *hdr_len)
4643 {
4644 	struct sk_buff *skb = first->skb;
4645 	u32 vlan_macip_lens, type_tucmd;
4646 	u32 mss_l4len_idx, l4len;
4647 	int err;
4648 
4649 	if (skb->ip_summed != CHECKSUM_PARTIAL)
4650 		return 0;
4651 
4652 	if (!skb_is_gso(skb))
4653 		return 0;
4654 
4655 	err = skb_cow_head(skb, 0);
4656 	if (err < 0)
4657 		return err;
4658 
4659 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4660 	type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4661 
4662 	if (first->protocol == htons(ETH_P_IP)) {
4663 		struct iphdr *iph = ip_hdr(skb);
4664 		iph->tot_len = 0;
4665 		iph->check = 0;
4666 		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4667 							 iph->daddr, 0,
4668 							 IPPROTO_TCP,
4669 							 0);
4670 		type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4671 		first->tx_flags |= IGB_TX_FLAGS_TSO |
4672 				   IGB_TX_FLAGS_CSUM |
4673 				   IGB_TX_FLAGS_IPV4;
4674 	} else if (skb_is_gso_v6(skb)) {
4675 		ipv6_hdr(skb)->payload_len = 0;
4676 		tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4677 						       &ipv6_hdr(skb)->daddr,
4678 						       0, IPPROTO_TCP, 0);
4679 		first->tx_flags |= IGB_TX_FLAGS_TSO |
4680 				   IGB_TX_FLAGS_CSUM;
4681 	}
4682 
4683 	/* compute header lengths */
4684 	l4len = tcp_hdrlen(skb);
4685 	*hdr_len = skb_transport_offset(skb) + l4len;
4686 
4687 	/* update gso size and bytecount with header size */
4688 	first->gso_segs = skb_shinfo(skb)->gso_segs;
4689 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
4690 
4691 	/* MSS L4LEN IDX */
4692 	mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4693 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4694 
4695 	/* VLAN MACLEN IPLEN */
4696 	vlan_macip_lens = skb_network_header_len(skb);
4697 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4698 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4699 
4700 	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4701 
4702 	return 1;
4703 }
4704 
4705 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4706 {
4707 	struct sk_buff *skb = first->skb;
4708 	u32 vlan_macip_lens = 0;
4709 	u32 mss_l4len_idx = 0;
4710 	u32 type_tucmd = 0;
4711 
4712 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
4713 		if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4714 			return;
4715 	} else {
4716 		u8 l4_hdr = 0;
4717 
4718 		switch (first->protocol) {
4719 		case htons(ETH_P_IP):
4720 			vlan_macip_lens |= skb_network_header_len(skb);
4721 			type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4722 			l4_hdr = ip_hdr(skb)->protocol;
4723 			break;
4724 		case htons(ETH_P_IPV6):
4725 			vlan_macip_lens |= skb_network_header_len(skb);
4726 			l4_hdr = ipv6_hdr(skb)->nexthdr;
4727 			break;
4728 		default:
4729 			if (unlikely(net_ratelimit())) {
4730 				dev_warn(tx_ring->dev,
4731 					 "partial checksum but proto=%x!\n",
4732 					 first->protocol);
4733 			}
4734 			break;
4735 		}
4736 
4737 		switch (l4_hdr) {
4738 		case IPPROTO_TCP:
4739 			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4740 			mss_l4len_idx = tcp_hdrlen(skb) <<
4741 					E1000_ADVTXD_L4LEN_SHIFT;
4742 			break;
4743 		case IPPROTO_SCTP:
4744 			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4745 			mss_l4len_idx = sizeof(struct sctphdr) <<
4746 					E1000_ADVTXD_L4LEN_SHIFT;
4747 			break;
4748 		case IPPROTO_UDP:
4749 			mss_l4len_idx = sizeof(struct udphdr) <<
4750 					E1000_ADVTXD_L4LEN_SHIFT;
4751 			break;
4752 		default:
4753 			if (unlikely(net_ratelimit())) {
4754 				dev_warn(tx_ring->dev,
4755 					 "partial checksum but l4 proto=%x!\n",
4756 					 l4_hdr);
4757 			}
4758 			break;
4759 		}
4760 
4761 		/* update TX checksum flag */
4762 		first->tx_flags |= IGB_TX_FLAGS_CSUM;
4763 	}
4764 
4765 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4766 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4767 
4768 	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4769 }
4770 
4771 #define IGB_SET_FLAG(_input, _flag, _result) \
4772 	((_flag <= _result) ? \
4773 	 ((u32)(_input & _flag) * (_result / _flag)) : \
4774 	 ((u32)(_input & _flag) / (_flag / _result)))
4775 
4776 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4777 {
4778 	/* set type for advanced descriptor with frame checksum insertion */
4779 	u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4780 		       E1000_ADVTXD_DCMD_DEXT |
4781 		       E1000_ADVTXD_DCMD_IFCS;
4782 
4783 	/* set HW vlan bit if vlan is present */
4784 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4785 				 (E1000_ADVTXD_DCMD_VLE));
4786 
4787 	/* set segmentation bits for TSO */
4788 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4789 				 (E1000_ADVTXD_DCMD_TSE));
4790 
4791 	/* set timestamp bit if present */
4792 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4793 				 (E1000_ADVTXD_MAC_TSTAMP));
4794 
4795 	/* insert frame checksum */
4796 	cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4797 
4798 	return cmd_type;
4799 }
4800 
4801 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4802 				 union e1000_adv_tx_desc *tx_desc,
4803 				 u32 tx_flags, unsigned int paylen)
4804 {
4805 	u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4806 
4807 	/* 82575 requires a unique index per ring */
4808 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4809 		olinfo_status |= tx_ring->reg_idx << 4;
4810 
4811 	/* insert L4 checksum */
4812 	olinfo_status |= IGB_SET_FLAG(tx_flags,
4813 				      IGB_TX_FLAGS_CSUM,
4814 				      (E1000_TXD_POPTS_TXSM << 8));
4815 
4816 	/* insert IPv4 checksum */
4817 	olinfo_status |= IGB_SET_FLAG(tx_flags,
4818 				      IGB_TX_FLAGS_IPV4,
4819 				      (E1000_TXD_POPTS_IXSM << 8));
4820 
4821 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4822 }
4823 
4824 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4825 {
4826 	struct net_device *netdev = tx_ring->netdev;
4827 
4828 	netif_stop_subqueue(netdev, tx_ring->queue_index);
4829 
4830 	/* Herbert's original patch had:
4831 	 *  smp_mb__after_netif_stop_queue();
4832 	 * but since that doesn't exist yet, just open code it.
4833 	 */
4834 	smp_mb();
4835 
4836 	/* We need to check again in a case another CPU has just
4837 	 * made room available.
4838 	 */
4839 	if (igb_desc_unused(tx_ring) < size)
4840 		return -EBUSY;
4841 
4842 	/* A reprieve! */
4843 	netif_wake_subqueue(netdev, tx_ring->queue_index);
4844 
4845 	u64_stats_update_begin(&tx_ring->tx_syncp2);
4846 	tx_ring->tx_stats.restart_queue2++;
4847 	u64_stats_update_end(&tx_ring->tx_syncp2);
4848 
4849 	return 0;
4850 }
4851 
4852 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4853 {
4854 	if (igb_desc_unused(tx_ring) >= size)
4855 		return 0;
4856 	return __igb_maybe_stop_tx(tx_ring, size);
4857 }
4858 
4859 static void igb_tx_map(struct igb_ring *tx_ring,
4860 		       struct igb_tx_buffer *first,
4861 		       const u8 hdr_len)
4862 {
4863 	struct sk_buff *skb = first->skb;
4864 	struct igb_tx_buffer *tx_buffer;
4865 	union e1000_adv_tx_desc *tx_desc;
4866 	struct skb_frag_struct *frag;
4867 	dma_addr_t dma;
4868 	unsigned int data_len, size;
4869 	u32 tx_flags = first->tx_flags;
4870 	u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4871 	u16 i = tx_ring->next_to_use;
4872 
4873 	tx_desc = IGB_TX_DESC(tx_ring, i);
4874 
4875 	igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4876 
4877 	size = skb_headlen(skb);
4878 	data_len = skb->data_len;
4879 
4880 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4881 
4882 	tx_buffer = first;
4883 
4884 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4885 		if (dma_mapping_error(tx_ring->dev, dma))
4886 			goto dma_error;
4887 
4888 		/* record length, and DMA address */
4889 		dma_unmap_len_set(tx_buffer, len, size);
4890 		dma_unmap_addr_set(tx_buffer, dma, dma);
4891 
4892 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
4893 
4894 		while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4895 			tx_desc->read.cmd_type_len =
4896 				cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4897 
4898 			i++;
4899 			tx_desc++;
4900 			if (i == tx_ring->count) {
4901 				tx_desc = IGB_TX_DESC(tx_ring, 0);
4902 				i = 0;
4903 			}
4904 			tx_desc->read.olinfo_status = 0;
4905 
4906 			dma += IGB_MAX_DATA_PER_TXD;
4907 			size -= IGB_MAX_DATA_PER_TXD;
4908 
4909 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
4910 		}
4911 
4912 		if (likely(!data_len))
4913 			break;
4914 
4915 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4916 
4917 		i++;
4918 		tx_desc++;
4919 		if (i == tx_ring->count) {
4920 			tx_desc = IGB_TX_DESC(tx_ring, 0);
4921 			i = 0;
4922 		}
4923 		tx_desc->read.olinfo_status = 0;
4924 
4925 		size = skb_frag_size(frag);
4926 		data_len -= size;
4927 
4928 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4929 				       size, DMA_TO_DEVICE);
4930 
4931 		tx_buffer = &tx_ring->tx_buffer_info[i];
4932 	}
4933 
4934 	/* write last descriptor with RS and EOP bits */
4935 	cmd_type |= size | IGB_TXD_DCMD;
4936 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4937 
4938 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4939 
4940 	/* set the timestamp */
4941 	first->time_stamp = jiffies;
4942 
4943 	/* Force memory writes to complete before letting h/w know there
4944 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
4945 	 * memory model archs, such as IA-64).
4946 	 *
4947 	 * We also need this memory barrier to make certain all of the
4948 	 * status bits have been updated before next_to_watch is written.
4949 	 */
4950 	wmb();
4951 
4952 	/* set next_to_watch value indicating a packet is present */
4953 	first->next_to_watch = tx_desc;
4954 
4955 	i++;
4956 	if (i == tx_ring->count)
4957 		i = 0;
4958 
4959 	tx_ring->next_to_use = i;
4960 
4961 	/* Make sure there is space in the ring for the next send. */
4962 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4963 
4964 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4965 		writel(i, tx_ring->tail);
4966 
4967 		/* we need this if more than one processor can write to our tail
4968 		 * at a time, it synchronizes IO on IA64/Altix systems
4969 		 */
4970 		mmiowb();
4971 	}
4972 	return;
4973 
4974 dma_error:
4975 	dev_err(tx_ring->dev, "TX DMA map failed\n");
4976 
4977 	/* clear dma mappings for failed tx_buffer_info map */
4978 	for (;;) {
4979 		tx_buffer = &tx_ring->tx_buffer_info[i];
4980 		igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4981 		if (tx_buffer == first)
4982 			break;
4983 		if (i == 0)
4984 			i = tx_ring->count;
4985 		i--;
4986 	}
4987 
4988 	tx_ring->next_to_use = i;
4989 }
4990 
4991 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4992 				struct igb_ring *tx_ring)
4993 {
4994 	struct igb_tx_buffer *first;
4995 	int tso;
4996 	u32 tx_flags = 0;
4997 	unsigned short f;
4998 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
4999 	__be16 protocol = vlan_get_protocol(skb);
5000 	u8 hdr_len = 0;
5001 
5002 	/* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5003 	 *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5004 	 *       + 2 desc gap to keep tail from touching head,
5005 	 *       + 1 desc for context descriptor,
5006 	 * otherwise try next time
5007 	 */
5008 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5009 		count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5010 
5011 	if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5012 		/* this is a hard error */
5013 		return NETDEV_TX_BUSY;
5014 	}
5015 
5016 	/* record the location of the first descriptor for this packet */
5017 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5018 	first->skb = skb;
5019 	first->bytecount = skb->len;
5020 	first->gso_segs = 1;
5021 
5022 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5023 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5024 
5025 		if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5026 					   &adapter->state)) {
5027 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5028 			tx_flags |= IGB_TX_FLAGS_TSTAMP;
5029 
5030 			adapter->ptp_tx_skb = skb_get(skb);
5031 			adapter->ptp_tx_start = jiffies;
5032 			if (adapter->hw.mac.type == e1000_82576)
5033 				schedule_work(&adapter->ptp_tx_work);
5034 		}
5035 	}
5036 
5037 	skb_tx_timestamp(skb);
5038 
5039 	if (skb_vlan_tag_present(skb)) {
5040 		tx_flags |= IGB_TX_FLAGS_VLAN;
5041 		tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5042 	}
5043 
5044 	/* record initial flags and protocol */
5045 	first->tx_flags = tx_flags;
5046 	first->protocol = protocol;
5047 
5048 	tso = igb_tso(tx_ring, first, &hdr_len);
5049 	if (tso < 0)
5050 		goto out_drop;
5051 	else if (!tso)
5052 		igb_tx_csum(tx_ring, first);
5053 
5054 	igb_tx_map(tx_ring, first, hdr_len);
5055 
5056 	return NETDEV_TX_OK;
5057 
5058 out_drop:
5059 	igb_unmap_and_free_tx_resource(tx_ring, first);
5060 
5061 	return NETDEV_TX_OK;
5062 }
5063 
5064 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5065 						    struct sk_buff *skb)
5066 {
5067 	unsigned int r_idx = skb->queue_mapping;
5068 
5069 	if (r_idx >= adapter->num_tx_queues)
5070 		r_idx = r_idx % adapter->num_tx_queues;
5071 
5072 	return adapter->tx_ring[r_idx];
5073 }
5074 
5075 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5076 				  struct net_device *netdev)
5077 {
5078 	struct igb_adapter *adapter = netdev_priv(netdev);
5079 
5080 	if (test_bit(__IGB_DOWN, &adapter->state)) {
5081 		dev_kfree_skb_any(skb);
5082 		return NETDEV_TX_OK;
5083 	}
5084 
5085 	if (skb->len <= 0) {
5086 		dev_kfree_skb_any(skb);
5087 		return NETDEV_TX_OK;
5088 	}
5089 
5090 	/* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5091 	 * in order to meet this minimum size requirement.
5092 	 */
5093 	if (skb_put_padto(skb, 17))
5094 		return NETDEV_TX_OK;
5095 
5096 	return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5097 }
5098 
5099 /**
5100  *  igb_tx_timeout - Respond to a Tx Hang
5101  *  @netdev: network interface device structure
5102  **/
5103 static void igb_tx_timeout(struct net_device *netdev)
5104 {
5105 	struct igb_adapter *adapter = netdev_priv(netdev);
5106 	struct e1000_hw *hw = &adapter->hw;
5107 
5108 	/* Do the reset outside of interrupt context */
5109 	adapter->tx_timeout_count++;
5110 
5111 	if (hw->mac.type >= e1000_82580)
5112 		hw->dev_spec._82575.global_device_reset = true;
5113 
5114 	schedule_work(&adapter->reset_task);
5115 	wr32(E1000_EICS,
5116 	     (adapter->eims_enable_mask & ~adapter->eims_other));
5117 }
5118 
5119 static void igb_reset_task(struct work_struct *work)
5120 {
5121 	struct igb_adapter *adapter;
5122 	adapter = container_of(work, struct igb_adapter, reset_task);
5123 
5124 	igb_dump(adapter);
5125 	netdev_err(adapter->netdev, "Reset adapter\n");
5126 	igb_reinit_locked(adapter);
5127 }
5128 
5129 /**
5130  *  igb_get_stats64 - Get System Network Statistics
5131  *  @netdev: network interface device structure
5132  *  @stats: rtnl_link_stats64 pointer
5133  **/
5134 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5135 						struct rtnl_link_stats64 *stats)
5136 {
5137 	struct igb_adapter *adapter = netdev_priv(netdev);
5138 
5139 	spin_lock(&adapter->stats64_lock);
5140 	igb_update_stats(adapter, &adapter->stats64);
5141 	memcpy(stats, &adapter->stats64, sizeof(*stats));
5142 	spin_unlock(&adapter->stats64_lock);
5143 
5144 	return stats;
5145 }
5146 
5147 /**
5148  *  igb_change_mtu - Change the Maximum Transfer Unit
5149  *  @netdev: network interface device structure
5150  *  @new_mtu: new value for maximum frame size
5151  *
5152  *  Returns 0 on success, negative on failure
5153  **/
5154 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5155 {
5156 	struct igb_adapter *adapter = netdev_priv(netdev);
5157 	struct pci_dev *pdev = adapter->pdev;
5158 	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5159 
5160 	if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5161 		dev_err(&pdev->dev, "Invalid MTU setting\n");
5162 		return -EINVAL;
5163 	}
5164 
5165 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5166 	if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5167 		dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5168 		return -EINVAL;
5169 	}
5170 
5171 	/* adjust max frame to be at least the size of a standard frame */
5172 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5173 		max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5174 
5175 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5176 		usleep_range(1000, 2000);
5177 
5178 	/* igb_down has a dependency on max_frame_size */
5179 	adapter->max_frame_size = max_frame;
5180 
5181 	if (netif_running(netdev))
5182 		igb_down(adapter);
5183 
5184 	dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5185 		 netdev->mtu, new_mtu);
5186 	netdev->mtu = new_mtu;
5187 
5188 	if (netif_running(netdev))
5189 		igb_up(adapter);
5190 	else
5191 		igb_reset(adapter);
5192 
5193 	clear_bit(__IGB_RESETTING, &adapter->state);
5194 
5195 	return 0;
5196 }
5197 
5198 /**
5199  *  igb_update_stats - Update the board statistics counters
5200  *  @adapter: board private structure
5201  **/
5202 void igb_update_stats(struct igb_adapter *adapter,
5203 		      struct rtnl_link_stats64 *net_stats)
5204 {
5205 	struct e1000_hw *hw = &adapter->hw;
5206 	struct pci_dev *pdev = adapter->pdev;
5207 	u32 reg, mpc;
5208 	int i;
5209 	u64 bytes, packets;
5210 	unsigned int start;
5211 	u64 _bytes, _packets;
5212 
5213 	/* Prevent stats update while adapter is being reset, or if the pci
5214 	 * connection is down.
5215 	 */
5216 	if (adapter->link_speed == 0)
5217 		return;
5218 	if (pci_channel_offline(pdev))
5219 		return;
5220 
5221 	bytes = 0;
5222 	packets = 0;
5223 
5224 	rcu_read_lock();
5225 	for (i = 0; i < adapter->num_rx_queues; i++) {
5226 		struct igb_ring *ring = adapter->rx_ring[i];
5227 		u32 rqdpc = rd32(E1000_RQDPC(i));
5228 		if (hw->mac.type >= e1000_i210)
5229 			wr32(E1000_RQDPC(i), 0);
5230 
5231 		if (rqdpc) {
5232 			ring->rx_stats.drops += rqdpc;
5233 			net_stats->rx_fifo_errors += rqdpc;
5234 		}
5235 
5236 		do {
5237 			start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5238 			_bytes = ring->rx_stats.bytes;
5239 			_packets = ring->rx_stats.packets;
5240 		} while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5241 		bytes += _bytes;
5242 		packets += _packets;
5243 	}
5244 
5245 	net_stats->rx_bytes = bytes;
5246 	net_stats->rx_packets = packets;
5247 
5248 	bytes = 0;
5249 	packets = 0;
5250 	for (i = 0; i < adapter->num_tx_queues; i++) {
5251 		struct igb_ring *ring = adapter->tx_ring[i];
5252 		do {
5253 			start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5254 			_bytes = ring->tx_stats.bytes;
5255 			_packets = ring->tx_stats.packets;
5256 		} while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5257 		bytes += _bytes;
5258 		packets += _packets;
5259 	}
5260 	net_stats->tx_bytes = bytes;
5261 	net_stats->tx_packets = packets;
5262 	rcu_read_unlock();
5263 
5264 	/* read stats registers */
5265 	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5266 	adapter->stats.gprc += rd32(E1000_GPRC);
5267 	adapter->stats.gorc += rd32(E1000_GORCL);
5268 	rd32(E1000_GORCH); /* clear GORCL */
5269 	adapter->stats.bprc += rd32(E1000_BPRC);
5270 	adapter->stats.mprc += rd32(E1000_MPRC);
5271 	adapter->stats.roc += rd32(E1000_ROC);
5272 
5273 	adapter->stats.prc64 += rd32(E1000_PRC64);
5274 	adapter->stats.prc127 += rd32(E1000_PRC127);
5275 	adapter->stats.prc255 += rd32(E1000_PRC255);
5276 	adapter->stats.prc511 += rd32(E1000_PRC511);
5277 	adapter->stats.prc1023 += rd32(E1000_PRC1023);
5278 	adapter->stats.prc1522 += rd32(E1000_PRC1522);
5279 	adapter->stats.symerrs += rd32(E1000_SYMERRS);
5280 	adapter->stats.sec += rd32(E1000_SEC);
5281 
5282 	mpc = rd32(E1000_MPC);
5283 	adapter->stats.mpc += mpc;
5284 	net_stats->rx_fifo_errors += mpc;
5285 	adapter->stats.scc += rd32(E1000_SCC);
5286 	adapter->stats.ecol += rd32(E1000_ECOL);
5287 	adapter->stats.mcc += rd32(E1000_MCC);
5288 	adapter->stats.latecol += rd32(E1000_LATECOL);
5289 	adapter->stats.dc += rd32(E1000_DC);
5290 	adapter->stats.rlec += rd32(E1000_RLEC);
5291 	adapter->stats.xonrxc += rd32(E1000_XONRXC);
5292 	adapter->stats.xontxc += rd32(E1000_XONTXC);
5293 	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5294 	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5295 	adapter->stats.fcruc += rd32(E1000_FCRUC);
5296 	adapter->stats.gptc += rd32(E1000_GPTC);
5297 	adapter->stats.gotc += rd32(E1000_GOTCL);
5298 	rd32(E1000_GOTCH); /* clear GOTCL */
5299 	adapter->stats.rnbc += rd32(E1000_RNBC);
5300 	adapter->stats.ruc += rd32(E1000_RUC);
5301 	adapter->stats.rfc += rd32(E1000_RFC);
5302 	adapter->stats.rjc += rd32(E1000_RJC);
5303 	adapter->stats.tor += rd32(E1000_TORH);
5304 	adapter->stats.tot += rd32(E1000_TOTH);
5305 	adapter->stats.tpr += rd32(E1000_TPR);
5306 
5307 	adapter->stats.ptc64 += rd32(E1000_PTC64);
5308 	adapter->stats.ptc127 += rd32(E1000_PTC127);
5309 	adapter->stats.ptc255 += rd32(E1000_PTC255);
5310 	adapter->stats.ptc511 += rd32(E1000_PTC511);
5311 	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5312 	adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5313 
5314 	adapter->stats.mptc += rd32(E1000_MPTC);
5315 	adapter->stats.bptc += rd32(E1000_BPTC);
5316 
5317 	adapter->stats.tpt += rd32(E1000_TPT);
5318 	adapter->stats.colc += rd32(E1000_COLC);
5319 
5320 	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5321 	/* read internal phy specific stats */
5322 	reg = rd32(E1000_CTRL_EXT);
5323 	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5324 		adapter->stats.rxerrc += rd32(E1000_RXERRC);
5325 
5326 		/* this stat has invalid values on i210/i211 */
5327 		if ((hw->mac.type != e1000_i210) &&
5328 		    (hw->mac.type != e1000_i211))
5329 			adapter->stats.tncrs += rd32(E1000_TNCRS);
5330 	}
5331 
5332 	adapter->stats.tsctc += rd32(E1000_TSCTC);
5333 	adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5334 
5335 	adapter->stats.iac += rd32(E1000_IAC);
5336 	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5337 	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5338 	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5339 	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5340 	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5341 	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5342 	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5343 	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5344 
5345 	/* Fill out the OS statistics structure */
5346 	net_stats->multicast = adapter->stats.mprc;
5347 	net_stats->collisions = adapter->stats.colc;
5348 
5349 	/* Rx Errors */
5350 
5351 	/* RLEC on some newer hardware can be incorrect so build
5352 	 * our own version based on RUC and ROC
5353 	 */
5354 	net_stats->rx_errors = adapter->stats.rxerrc +
5355 		adapter->stats.crcerrs + adapter->stats.algnerrc +
5356 		adapter->stats.ruc + adapter->stats.roc +
5357 		adapter->stats.cexterr;
5358 	net_stats->rx_length_errors = adapter->stats.ruc +
5359 				      adapter->stats.roc;
5360 	net_stats->rx_crc_errors = adapter->stats.crcerrs;
5361 	net_stats->rx_frame_errors = adapter->stats.algnerrc;
5362 	net_stats->rx_missed_errors = adapter->stats.mpc;
5363 
5364 	/* Tx Errors */
5365 	net_stats->tx_errors = adapter->stats.ecol +
5366 			       adapter->stats.latecol;
5367 	net_stats->tx_aborted_errors = adapter->stats.ecol;
5368 	net_stats->tx_window_errors = adapter->stats.latecol;
5369 	net_stats->tx_carrier_errors = adapter->stats.tncrs;
5370 
5371 	/* Tx Dropped needs to be maintained elsewhere */
5372 
5373 	/* Management Stats */
5374 	adapter->stats.mgptc += rd32(E1000_MGTPTC);
5375 	adapter->stats.mgprc += rd32(E1000_MGTPRC);
5376 	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5377 
5378 	/* OS2BMC Stats */
5379 	reg = rd32(E1000_MANC);
5380 	if (reg & E1000_MANC_EN_BMC2OS) {
5381 		adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5382 		adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5383 		adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5384 		adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5385 	}
5386 }
5387 
5388 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5389 {
5390 	struct e1000_hw *hw = &adapter->hw;
5391 	struct ptp_clock_event event;
5392 	struct timespec ts;
5393 	u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5394 
5395 	if (tsicr & TSINTR_SYS_WRAP) {
5396 		event.type = PTP_CLOCK_PPS;
5397 		if (adapter->ptp_caps.pps)
5398 			ptp_clock_event(adapter->ptp_clock, &event);
5399 		else
5400 			dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5401 		ack |= TSINTR_SYS_WRAP;
5402 	}
5403 
5404 	if (tsicr & E1000_TSICR_TXTS) {
5405 		/* retrieve hardware timestamp */
5406 		schedule_work(&adapter->ptp_tx_work);
5407 		ack |= E1000_TSICR_TXTS;
5408 	}
5409 
5410 	if (tsicr & TSINTR_TT0) {
5411 		spin_lock(&adapter->tmreg_lock);
5412 		ts = timespec_add(adapter->perout[0].start,
5413 				  adapter->perout[0].period);
5414 		wr32(E1000_TRGTTIML0, ts.tv_nsec);
5415 		wr32(E1000_TRGTTIMH0, ts.tv_sec);
5416 		tsauxc = rd32(E1000_TSAUXC);
5417 		tsauxc |= TSAUXC_EN_TT0;
5418 		wr32(E1000_TSAUXC, tsauxc);
5419 		adapter->perout[0].start = ts;
5420 		spin_unlock(&adapter->tmreg_lock);
5421 		ack |= TSINTR_TT0;
5422 	}
5423 
5424 	if (tsicr & TSINTR_TT1) {
5425 		spin_lock(&adapter->tmreg_lock);
5426 		ts = timespec_add(adapter->perout[1].start,
5427 				  adapter->perout[1].period);
5428 		wr32(E1000_TRGTTIML1, ts.tv_nsec);
5429 		wr32(E1000_TRGTTIMH1, ts.tv_sec);
5430 		tsauxc = rd32(E1000_TSAUXC);
5431 		tsauxc |= TSAUXC_EN_TT1;
5432 		wr32(E1000_TSAUXC, tsauxc);
5433 		adapter->perout[1].start = ts;
5434 		spin_unlock(&adapter->tmreg_lock);
5435 		ack |= TSINTR_TT1;
5436 	}
5437 
5438 	if (tsicr & TSINTR_AUTT0) {
5439 		nsec = rd32(E1000_AUXSTMPL0);
5440 		sec  = rd32(E1000_AUXSTMPH0);
5441 		event.type = PTP_CLOCK_EXTTS;
5442 		event.index = 0;
5443 		event.timestamp = sec * 1000000000ULL + nsec;
5444 		ptp_clock_event(adapter->ptp_clock, &event);
5445 		ack |= TSINTR_AUTT0;
5446 	}
5447 
5448 	if (tsicr & TSINTR_AUTT1) {
5449 		nsec = rd32(E1000_AUXSTMPL1);
5450 		sec  = rd32(E1000_AUXSTMPH1);
5451 		event.type = PTP_CLOCK_EXTTS;
5452 		event.index = 1;
5453 		event.timestamp = sec * 1000000000ULL + nsec;
5454 		ptp_clock_event(adapter->ptp_clock, &event);
5455 		ack |= TSINTR_AUTT1;
5456 	}
5457 
5458 	/* acknowledge the interrupts */
5459 	wr32(E1000_TSICR, ack);
5460 }
5461 
5462 static irqreturn_t igb_msix_other(int irq, void *data)
5463 {
5464 	struct igb_adapter *adapter = data;
5465 	struct e1000_hw *hw = &adapter->hw;
5466 	u32 icr = rd32(E1000_ICR);
5467 	/* reading ICR causes bit 31 of EICR to be cleared */
5468 
5469 	if (icr & E1000_ICR_DRSTA)
5470 		schedule_work(&adapter->reset_task);
5471 
5472 	if (icr & E1000_ICR_DOUTSYNC) {
5473 		/* HW is reporting DMA is out of sync */
5474 		adapter->stats.doosync++;
5475 		/* The DMA Out of Sync is also indication of a spoof event
5476 		 * in IOV mode. Check the Wrong VM Behavior register to
5477 		 * see if it is really a spoof event.
5478 		 */
5479 		igb_check_wvbr(adapter);
5480 	}
5481 
5482 	/* Check for a mailbox event */
5483 	if (icr & E1000_ICR_VMMB)
5484 		igb_msg_task(adapter);
5485 
5486 	if (icr & E1000_ICR_LSC) {
5487 		hw->mac.get_link_status = 1;
5488 		/* guard against interrupt when we're going down */
5489 		if (!test_bit(__IGB_DOWN, &adapter->state))
5490 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
5491 	}
5492 
5493 	if (icr & E1000_ICR_TS)
5494 		igb_tsync_interrupt(adapter);
5495 
5496 	wr32(E1000_EIMS, adapter->eims_other);
5497 
5498 	return IRQ_HANDLED;
5499 }
5500 
5501 static void igb_write_itr(struct igb_q_vector *q_vector)
5502 {
5503 	struct igb_adapter *adapter = q_vector->adapter;
5504 	u32 itr_val = q_vector->itr_val & 0x7FFC;
5505 
5506 	if (!q_vector->set_itr)
5507 		return;
5508 
5509 	if (!itr_val)
5510 		itr_val = 0x4;
5511 
5512 	if (adapter->hw.mac.type == e1000_82575)
5513 		itr_val |= itr_val << 16;
5514 	else
5515 		itr_val |= E1000_EITR_CNT_IGNR;
5516 
5517 	writel(itr_val, q_vector->itr_register);
5518 	q_vector->set_itr = 0;
5519 }
5520 
5521 static irqreturn_t igb_msix_ring(int irq, void *data)
5522 {
5523 	struct igb_q_vector *q_vector = data;
5524 
5525 	/* Write the ITR value calculated from the previous interrupt. */
5526 	igb_write_itr(q_vector);
5527 
5528 	napi_schedule(&q_vector->napi);
5529 
5530 	return IRQ_HANDLED;
5531 }
5532 
5533 #ifdef CONFIG_IGB_DCA
5534 static void igb_update_tx_dca(struct igb_adapter *adapter,
5535 			      struct igb_ring *tx_ring,
5536 			      int cpu)
5537 {
5538 	struct e1000_hw *hw = &adapter->hw;
5539 	u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5540 
5541 	if (hw->mac.type != e1000_82575)
5542 		txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5543 
5544 	/* We can enable relaxed ordering for reads, but not writes when
5545 	 * DCA is enabled.  This is due to a known issue in some chipsets
5546 	 * which will cause the DCA tag to be cleared.
5547 	 */
5548 	txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5549 		  E1000_DCA_TXCTRL_DATA_RRO_EN |
5550 		  E1000_DCA_TXCTRL_DESC_DCA_EN;
5551 
5552 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5553 }
5554 
5555 static void igb_update_rx_dca(struct igb_adapter *adapter,
5556 			      struct igb_ring *rx_ring,
5557 			      int cpu)
5558 {
5559 	struct e1000_hw *hw = &adapter->hw;
5560 	u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5561 
5562 	if (hw->mac.type != e1000_82575)
5563 		rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5564 
5565 	/* We can enable relaxed ordering for reads, but not writes when
5566 	 * DCA is enabled.  This is due to a known issue in some chipsets
5567 	 * which will cause the DCA tag to be cleared.
5568 	 */
5569 	rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5570 		  E1000_DCA_RXCTRL_DESC_DCA_EN;
5571 
5572 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5573 }
5574 
5575 static void igb_update_dca(struct igb_q_vector *q_vector)
5576 {
5577 	struct igb_adapter *adapter = q_vector->adapter;
5578 	int cpu = get_cpu();
5579 
5580 	if (q_vector->cpu == cpu)
5581 		goto out_no_update;
5582 
5583 	if (q_vector->tx.ring)
5584 		igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5585 
5586 	if (q_vector->rx.ring)
5587 		igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5588 
5589 	q_vector->cpu = cpu;
5590 out_no_update:
5591 	put_cpu();
5592 }
5593 
5594 static void igb_setup_dca(struct igb_adapter *adapter)
5595 {
5596 	struct e1000_hw *hw = &adapter->hw;
5597 	int i;
5598 
5599 	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5600 		return;
5601 
5602 	/* Always use CB2 mode, difference is masked in the CB driver. */
5603 	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5604 
5605 	for (i = 0; i < adapter->num_q_vectors; i++) {
5606 		adapter->q_vector[i]->cpu = -1;
5607 		igb_update_dca(adapter->q_vector[i]);
5608 	}
5609 }
5610 
5611 static int __igb_notify_dca(struct device *dev, void *data)
5612 {
5613 	struct net_device *netdev = dev_get_drvdata(dev);
5614 	struct igb_adapter *adapter = netdev_priv(netdev);
5615 	struct pci_dev *pdev = adapter->pdev;
5616 	struct e1000_hw *hw = &adapter->hw;
5617 	unsigned long event = *(unsigned long *)data;
5618 
5619 	switch (event) {
5620 	case DCA_PROVIDER_ADD:
5621 		/* if already enabled, don't do it again */
5622 		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5623 			break;
5624 		if (dca_add_requester(dev) == 0) {
5625 			adapter->flags |= IGB_FLAG_DCA_ENABLED;
5626 			dev_info(&pdev->dev, "DCA enabled\n");
5627 			igb_setup_dca(adapter);
5628 			break;
5629 		}
5630 		/* Fall Through since DCA is disabled. */
5631 	case DCA_PROVIDER_REMOVE:
5632 		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5633 			/* without this a class_device is left
5634 			 * hanging around in the sysfs model
5635 			 */
5636 			dca_remove_requester(dev);
5637 			dev_info(&pdev->dev, "DCA disabled\n");
5638 			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5639 			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5640 		}
5641 		break;
5642 	}
5643 
5644 	return 0;
5645 }
5646 
5647 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5648 			  void *p)
5649 {
5650 	int ret_val;
5651 
5652 	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5653 					 __igb_notify_dca);
5654 
5655 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5656 }
5657 #endif /* CONFIG_IGB_DCA */
5658 
5659 #ifdef CONFIG_PCI_IOV
5660 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5661 {
5662 	unsigned char mac_addr[ETH_ALEN];
5663 
5664 	eth_zero_addr(mac_addr);
5665 	igb_set_vf_mac(adapter, vf, mac_addr);
5666 
5667 	/* By default spoof check is enabled for all VFs */
5668 	adapter->vf_data[vf].spoofchk_enabled = true;
5669 
5670 	return 0;
5671 }
5672 
5673 #endif
5674 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5675 {
5676 	struct e1000_hw *hw = &adapter->hw;
5677 	u32 ping;
5678 	int i;
5679 
5680 	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5681 		ping = E1000_PF_CONTROL_MSG;
5682 		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5683 			ping |= E1000_VT_MSGTYPE_CTS;
5684 		igb_write_mbx(hw, &ping, 1, i);
5685 	}
5686 }
5687 
5688 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5689 {
5690 	struct e1000_hw *hw = &adapter->hw;
5691 	u32 vmolr = rd32(E1000_VMOLR(vf));
5692 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5693 
5694 	vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5695 			    IGB_VF_FLAG_MULTI_PROMISC);
5696 	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5697 
5698 	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5699 		vmolr |= E1000_VMOLR_MPME;
5700 		vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5701 		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5702 	} else {
5703 		/* if we have hashes and we are clearing a multicast promisc
5704 		 * flag we need to write the hashes to the MTA as this step
5705 		 * was previously skipped
5706 		 */
5707 		if (vf_data->num_vf_mc_hashes > 30) {
5708 			vmolr |= E1000_VMOLR_MPME;
5709 		} else if (vf_data->num_vf_mc_hashes) {
5710 			int j;
5711 
5712 			vmolr |= E1000_VMOLR_ROMPE;
5713 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5714 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5715 		}
5716 	}
5717 
5718 	wr32(E1000_VMOLR(vf), vmolr);
5719 
5720 	/* there are flags left unprocessed, likely not supported */
5721 	if (*msgbuf & E1000_VT_MSGINFO_MASK)
5722 		return -EINVAL;
5723 
5724 	return 0;
5725 }
5726 
5727 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5728 				  u32 *msgbuf, u32 vf)
5729 {
5730 	int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5731 	u16 *hash_list = (u16 *)&msgbuf[1];
5732 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5733 	int i;
5734 
5735 	/* salt away the number of multicast addresses assigned
5736 	 * to this VF for later use to restore when the PF multi cast
5737 	 * list changes
5738 	 */
5739 	vf_data->num_vf_mc_hashes = n;
5740 
5741 	/* only up to 30 hash values supported */
5742 	if (n > 30)
5743 		n = 30;
5744 
5745 	/* store the hashes for later use */
5746 	for (i = 0; i < n; i++)
5747 		vf_data->vf_mc_hashes[i] = hash_list[i];
5748 
5749 	/* Flush and reset the mta with the new values */
5750 	igb_set_rx_mode(adapter->netdev);
5751 
5752 	return 0;
5753 }
5754 
5755 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5756 {
5757 	struct e1000_hw *hw = &adapter->hw;
5758 	struct vf_data_storage *vf_data;
5759 	int i, j;
5760 
5761 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
5762 		u32 vmolr = rd32(E1000_VMOLR(i));
5763 
5764 		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5765 
5766 		vf_data = &adapter->vf_data[i];
5767 
5768 		if ((vf_data->num_vf_mc_hashes > 30) ||
5769 		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5770 			vmolr |= E1000_VMOLR_MPME;
5771 		} else if (vf_data->num_vf_mc_hashes) {
5772 			vmolr |= E1000_VMOLR_ROMPE;
5773 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5774 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5775 		}
5776 		wr32(E1000_VMOLR(i), vmolr);
5777 	}
5778 }
5779 
5780 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5781 {
5782 	struct e1000_hw *hw = &adapter->hw;
5783 	u32 pool_mask, reg, vid;
5784 	int i;
5785 
5786 	pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5787 
5788 	/* Find the vlan filter for this id */
5789 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5790 		reg = rd32(E1000_VLVF(i));
5791 
5792 		/* remove the vf from the pool */
5793 		reg &= ~pool_mask;
5794 
5795 		/* if pool is empty then remove entry from vfta */
5796 		if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5797 		    (reg & E1000_VLVF_VLANID_ENABLE)) {
5798 			reg = 0;
5799 			vid = reg & E1000_VLVF_VLANID_MASK;
5800 			igb_vfta_set(hw, vid, false);
5801 		}
5802 
5803 		wr32(E1000_VLVF(i), reg);
5804 	}
5805 
5806 	adapter->vf_data[vf].vlans_enabled = 0;
5807 }
5808 
5809 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5810 {
5811 	struct e1000_hw *hw = &adapter->hw;
5812 	u32 reg, i;
5813 
5814 	/* The vlvf table only exists on 82576 hardware and newer */
5815 	if (hw->mac.type < e1000_82576)
5816 		return -1;
5817 
5818 	/* we only need to do this if VMDq is enabled */
5819 	if (!adapter->vfs_allocated_count)
5820 		return -1;
5821 
5822 	/* Find the vlan filter for this id */
5823 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5824 		reg = rd32(E1000_VLVF(i));
5825 		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5826 		    vid == (reg & E1000_VLVF_VLANID_MASK))
5827 			break;
5828 	}
5829 
5830 	if (add) {
5831 		if (i == E1000_VLVF_ARRAY_SIZE) {
5832 			/* Did not find a matching VLAN ID entry that was
5833 			 * enabled.  Search for a free filter entry, i.e.
5834 			 * one without the enable bit set
5835 			 */
5836 			for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5837 				reg = rd32(E1000_VLVF(i));
5838 				if (!(reg & E1000_VLVF_VLANID_ENABLE))
5839 					break;
5840 			}
5841 		}
5842 		if (i < E1000_VLVF_ARRAY_SIZE) {
5843 			/* Found an enabled/available entry */
5844 			reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5845 
5846 			/* if !enabled we need to set this up in vfta */
5847 			if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5848 				/* add VID to filter table */
5849 				igb_vfta_set(hw, vid, true);
5850 				reg |= E1000_VLVF_VLANID_ENABLE;
5851 			}
5852 			reg &= ~E1000_VLVF_VLANID_MASK;
5853 			reg |= vid;
5854 			wr32(E1000_VLVF(i), reg);
5855 
5856 			/* do not modify RLPML for PF devices */
5857 			if (vf >= adapter->vfs_allocated_count)
5858 				return 0;
5859 
5860 			if (!adapter->vf_data[vf].vlans_enabled) {
5861 				u32 size;
5862 
5863 				reg = rd32(E1000_VMOLR(vf));
5864 				size = reg & E1000_VMOLR_RLPML_MASK;
5865 				size += 4;
5866 				reg &= ~E1000_VMOLR_RLPML_MASK;
5867 				reg |= size;
5868 				wr32(E1000_VMOLR(vf), reg);
5869 			}
5870 
5871 			adapter->vf_data[vf].vlans_enabled++;
5872 		}
5873 	} else {
5874 		if (i < E1000_VLVF_ARRAY_SIZE) {
5875 			/* remove vf from the pool */
5876 			reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5877 			/* if pool is empty then remove entry from vfta */
5878 			if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5879 				reg = 0;
5880 				igb_vfta_set(hw, vid, false);
5881 			}
5882 			wr32(E1000_VLVF(i), reg);
5883 
5884 			/* do not modify RLPML for PF devices */
5885 			if (vf >= adapter->vfs_allocated_count)
5886 				return 0;
5887 
5888 			adapter->vf_data[vf].vlans_enabled--;
5889 			if (!adapter->vf_data[vf].vlans_enabled) {
5890 				u32 size;
5891 
5892 				reg = rd32(E1000_VMOLR(vf));
5893 				size = reg & E1000_VMOLR_RLPML_MASK;
5894 				size -= 4;
5895 				reg &= ~E1000_VMOLR_RLPML_MASK;
5896 				reg |= size;
5897 				wr32(E1000_VMOLR(vf), reg);
5898 			}
5899 		}
5900 	}
5901 	return 0;
5902 }
5903 
5904 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5905 {
5906 	struct e1000_hw *hw = &adapter->hw;
5907 
5908 	if (vid)
5909 		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5910 	else
5911 		wr32(E1000_VMVIR(vf), 0);
5912 }
5913 
5914 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5915 			       int vf, u16 vlan, u8 qos)
5916 {
5917 	int err = 0;
5918 	struct igb_adapter *adapter = netdev_priv(netdev);
5919 
5920 	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5921 		return -EINVAL;
5922 	if (vlan || qos) {
5923 		err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5924 		if (err)
5925 			goto out;
5926 		igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5927 		igb_set_vmolr(adapter, vf, !vlan);
5928 		adapter->vf_data[vf].pf_vlan = vlan;
5929 		adapter->vf_data[vf].pf_qos = qos;
5930 		dev_info(&adapter->pdev->dev,
5931 			 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5932 		if (test_bit(__IGB_DOWN, &adapter->state)) {
5933 			dev_warn(&adapter->pdev->dev,
5934 				 "The VF VLAN has been set, but the PF device is not up.\n");
5935 			dev_warn(&adapter->pdev->dev,
5936 				 "Bring the PF device up before attempting to use the VF device.\n");
5937 		}
5938 	} else {
5939 		igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5940 			     false, vf);
5941 		igb_set_vmvir(adapter, vlan, vf);
5942 		igb_set_vmolr(adapter, vf, true);
5943 		adapter->vf_data[vf].pf_vlan = 0;
5944 		adapter->vf_data[vf].pf_qos = 0;
5945 	}
5946 out:
5947 	return err;
5948 }
5949 
5950 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5951 {
5952 	struct e1000_hw *hw = &adapter->hw;
5953 	int i;
5954 	u32 reg;
5955 
5956 	/* Find the vlan filter for this id */
5957 	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5958 		reg = rd32(E1000_VLVF(i));
5959 		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5960 		    vid == (reg & E1000_VLVF_VLANID_MASK))
5961 			break;
5962 	}
5963 
5964 	if (i >= E1000_VLVF_ARRAY_SIZE)
5965 		i = -1;
5966 
5967 	return i;
5968 }
5969 
5970 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5971 {
5972 	struct e1000_hw *hw = &adapter->hw;
5973 	int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5974 	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5975 	int err = 0;
5976 
5977 	/* If in promiscuous mode we need to make sure the PF also has
5978 	 * the VLAN filter set.
5979 	 */
5980 	if (add && (adapter->netdev->flags & IFF_PROMISC))
5981 		err = igb_vlvf_set(adapter, vid, add,
5982 				   adapter->vfs_allocated_count);
5983 	if (err)
5984 		goto out;
5985 
5986 	err = igb_vlvf_set(adapter, vid, add, vf);
5987 
5988 	if (err)
5989 		goto out;
5990 
5991 	/* Go through all the checks to see if the VLAN filter should
5992 	 * be wiped completely.
5993 	 */
5994 	if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5995 		u32 vlvf, bits;
5996 		int regndx = igb_find_vlvf_entry(adapter, vid);
5997 
5998 		if (regndx < 0)
5999 			goto out;
6000 		/* See if any other pools are set for this VLAN filter
6001 		 * entry other than the PF.
6002 		 */
6003 		vlvf = bits = rd32(E1000_VLVF(regndx));
6004 		bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6005 			      adapter->vfs_allocated_count);
6006 		/* If the filter was removed then ensure PF pool bit
6007 		 * is cleared if the PF only added itself to the pool
6008 		 * because the PF is in promiscuous mode.
6009 		 */
6010 		if ((vlvf & VLAN_VID_MASK) == vid &&
6011 		    !test_bit(vid, adapter->active_vlans) &&
6012 		    !bits)
6013 			igb_vlvf_set(adapter, vid, add,
6014 				     adapter->vfs_allocated_count);
6015 	}
6016 
6017 out:
6018 	return err;
6019 }
6020 
6021 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6022 {
6023 	/* clear flags - except flag that indicates PF has set the MAC */
6024 	adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6025 	adapter->vf_data[vf].last_nack = jiffies;
6026 
6027 	/* reset offloads to defaults */
6028 	igb_set_vmolr(adapter, vf, true);
6029 
6030 	/* reset vlans for device */
6031 	igb_clear_vf_vfta(adapter, vf);
6032 	if (adapter->vf_data[vf].pf_vlan)
6033 		igb_ndo_set_vf_vlan(adapter->netdev, vf,
6034 				    adapter->vf_data[vf].pf_vlan,
6035 				    adapter->vf_data[vf].pf_qos);
6036 	else
6037 		igb_clear_vf_vfta(adapter, vf);
6038 
6039 	/* reset multicast table array for vf */
6040 	adapter->vf_data[vf].num_vf_mc_hashes = 0;
6041 
6042 	/* Flush and reset the mta with the new values */
6043 	igb_set_rx_mode(adapter->netdev);
6044 }
6045 
6046 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6047 {
6048 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6049 
6050 	/* clear mac address as we were hotplug removed/added */
6051 	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6052 		eth_zero_addr(vf_mac);
6053 
6054 	/* process remaining reset events */
6055 	igb_vf_reset(adapter, vf);
6056 }
6057 
6058 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6059 {
6060 	struct e1000_hw *hw = &adapter->hw;
6061 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6062 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6063 	u32 reg, msgbuf[3];
6064 	u8 *addr = (u8 *)(&msgbuf[1]);
6065 
6066 	/* process all the same items cleared in a function level reset */
6067 	igb_vf_reset(adapter, vf);
6068 
6069 	/* set vf mac address */
6070 	igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6071 
6072 	/* enable transmit and receive for vf */
6073 	reg = rd32(E1000_VFTE);
6074 	wr32(E1000_VFTE, reg | (1 << vf));
6075 	reg = rd32(E1000_VFRE);
6076 	wr32(E1000_VFRE, reg | (1 << vf));
6077 
6078 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6079 
6080 	/* reply to reset with ack and vf mac address */
6081 	if (!is_zero_ether_addr(vf_mac)) {
6082 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6083 		memcpy(addr, vf_mac, ETH_ALEN);
6084 	} else {
6085 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6086 	}
6087 	igb_write_mbx(hw, msgbuf, 3, vf);
6088 }
6089 
6090 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6091 {
6092 	/* The VF MAC Address is stored in a packed array of bytes
6093 	 * starting at the second 32 bit word of the msg array
6094 	 */
6095 	unsigned char *addr = (char *)&msg[1];
6096 	int err = -1;
6097 
6098 	if (is_valid_ether_addr(addr))
6099 		err = igb_set_vf_mac(adapter, vf, addr);
6100 
6101 	return err;
6102 }
6103 
6104 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6105 {
6106 	struct e1000_hw *hw = &adapter->hw;
6107 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6108 	u32 msg = E1000_VT_MSGTYPE_NACK;
6109 
6110 	/* if device isn't clear to send it shouldn't be reading either */
6111 	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6112 	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6113 		igb_write_mbx(hw, &msg, 1, vf);
6114 		vf_data->last_nack = jiffies;
6115 	}
6116 }
6117 
6118 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6119 {
6120 	struct pci_dev *pdev = adapter->pdev;
6121 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
6122 	struct e1000_hw *hw = &adapter->hw;
6123 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6124 	s32 retval;
6125 
6126 	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6127 
6128 	if (retval) {
6129 		/* if receive failed revoke VF CTS stats and restart init */
6130 		dev_err(&pdev->dev, "Error receiving message from VF\n");
6131 		vf_data->flags &= ~IGB_VF_FLAG_CTS;
6132 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6133 			return;
6134 		goto out;
6135 	}
6136 
6137 	/* this is a message we already processed, do nothing */
6138 	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6139 		return;
6140 
6141 	/* until the vf completes a reset it should not be
6142 	 * allowed to start any configuration.
6143 	 */
6144 	if (msgbuf[0] == E1000_VF_RESET) {
6145 		igb_vf_reset_msg(adapter, vf);
6146 		return;
6147 	}
6148 
6149 	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6150 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6151 			return;
6152 		retval = -1;
6153 		goto out;
6154 	}
6155 
6156 	switch ((msgbuf[0] & 0xFFFF)) {
6157 	case E1000_VF_SET_MAC_ADDR:
6158 		retval = -EINVAL;
6159 		if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6160 			retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6161 		else
6162 			dev_warn(&pdev->dev,
6163 				 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6164 				 vf);
6165 		break;
6166 	case E1000_VF_SET_PROMISC:
6167 		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6168 		break;
6169 	case E1000_VF_SET_MULTICAST:
6170 		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6171 		break;
6172 	case E1000_VF_SET_LPE:
6173 		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6174 		break;
6175 	case E1000_VF_SET_VLAN:
6176 		retval = -1;
6177 		if (vf_data->pf_vlan)
6178 			dev_warn(&pdev->dev,
6179 				 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6180 				 vf);
6181 		else
6182 			retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6183 		break;
6184 	default:
6185 		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6186 		retval = -1;
6187 		break;
6188 	}
6189 
6190 	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6191 out:
6192 	/* notify the VF of the results of what it sent us */
6193 	if (retval)
6194 		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6195 	else
6196 		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6197 
6198 	igb_write_mbx(hw, msgbuf, 1, vf);
6199 }
6200 
6201 static void igb_msg_task(struct igb_adapter *adapter)
6202 {
6203 	struct e1000_hw *hw = &adapter->hw;
6204 	u32 vf;
6205 
6206 	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6207 		/* process any reset requests */
6208 		if (!igb_check_for_rst(hw, vf))
6209 			igb_vf_reset_event(adapter, vf);
6210 
6211 		/* process any messages pending */
6212 		if (!igb_check_for_msg(hw, vf))
6213 			igb_rcv_msg_from_vf(adapter, vf);
6214 
6215 		/* process any acks */
6216 		if (!igb_check_for_ack(hw, vf))
6217 			igb_rcv_ack_from_vf(adapter, vf);
6218 	}
6219 }
6220 
6221 /**
6222  *  igb_set_uta - Set unicast filter table address
6223  *  @adapter: board private structure
6224  *
6225  *  The unicast table address is a register array of 32-bit registers.
6226  *  The table is meant to be used in a way similar to how the MTA is used
6227  *  however due to certain limitations in the hardware it is necessary to
6228  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6229  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
6230  **/
6231 static void igb_set_uta(struct igb_adapter *adapter)
6232 {
6233 	struct e1000_hw *hw = &adapter->hw;
6234 	int i;
6235 
6236 	/* The UTA table only exists on 82576 hardware and newer */
6237 	if (hw->mac.type < e1000_82576)
6238 		return;
6239 
6240 	/* we only need to do this if VMDq is enabled */
6241 	if (!adapter->vfs_allocated_count)
6242 		return;
6243 
6244 	for (i = 0; i < hw->mac.uta_reg_count; i++)
6245 		array_wr32(E1000_UTA, i, ~0);
6246 }
6247 
6248 /**
6249  *  igb_intr_msi - Interrupt Handler
6250  *  @irq: interrupt number
6251  *  @data: pointer to a network interface device structure
6252  **/
6253 static irqreturn_t igb_intr_msi(int irq, void *data)
6254 {
6255 	struct igb_adapter *adapter = data;
6256 	struct igb_q_vector *q_vector = adapter->q_vector[0];
6257 	struct e1000_hw *hw = &adapter->hw;
6258 	/* read ICR disables interrupts using IAM */
6259 	u32 icr = rd32(E1000_ICR);
6260 
6261 	igb_write_itr(q_vector);
6262 
6263 	if (icr & E1000_ICR_DRSTA)
6264 		schedule_work(&adapter->reset_task);
6265 
6266 	if (icr & E1000_ICR_DOUTSYNC) {
6267 		/* HW is reporting DMA is out of sync */
6268 		adapter->stats.doosync++;
6269 	}
6270 
6271 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6272 		hw->mac.get_link_status = 1;
6273 		if (!test_bit(__IGB_DOWN, &adapter->state))
6274 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
6275 	}
6276 
6277 	if (icr & E1000_ICR_TS)
6278 		igb_tsync_interrupt(adapter);
6279 
6280 	napi_schedule(&q_vector->napi);
6281 
6282 	return IRQ_HANDLED;
6283 }
6284 
6285 /**
6286  *  igb_intr - Legacy Interrupt Handler
6287  *  @irq: interrupt number
6288  *  @data: pointer to a network interface device structure
6289  **/
6290 static irqreturn_t igb_intr(int irq, void *data)
6291 {
6292 	struct igb_adapter *adapter = data;
6293 	struct igb_q_vector *q_vector = adapter->q_vector[0];
6294 	struct e1000_hw *hw = &adapter->hw;
6295 	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
6296 	 * need for the IMC write
6297 	 */
6298 	u32 icr = rd32(E1000_ICR);
6299 
6300 	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6301 	 * not set, then the adapter didn't send an interrupt
6302 	 */
6303 	if (!(icr & E1000_ICR_INT_ASSERTED))
6304 		return IRQ_NONE;
6305 
6306 	igb_write_itr(q_vector);
6307 
6308 	if (icr & E1000_ICR_DRSTA)
6309 		schedule_work(&adapter->reset_task);
6310 
6311 	if (icr & E1000_ICR_DOUTSYNC) {
6312 		/* HW is reporting DMA is out of sync */
6313 		adapter->stats.doosync++;
6314 	}
6315 
6316 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6317 		hw->mac.get_link_status = 1;
6318 		/* guard against interrupt when we're going down */
6319 		if (!test_bit(__IGB_DOWN, &adapter->state))
6320 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
6321 	}
6322 
6323 	if (icr & E1000_ICR_TS)
6324 		igb_tsync_interrupt(adapter);
6325 
6326 	napi_schedule(&q_vector->napi);
6327 
6328 	return IRQ_HANDLED;
6329 }
6330 
6331 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6332 {
6333 	struct igb_adapter *adapter = q_vector->adapter;
6334 	struct e1000_hw *hw = &adapter->hw;
6335 
6336 	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6337 	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6338 		if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6339 			igb_set_itr(q_vector);
6340 		else
6341 			igb_update_ring_itr(q_vector);
6342 	}
6343 
6344 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
6345 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
6346 			wr32(E1000_EIMS, q_vector->eims_value);
6347 		else
6348 			igb_irq_enable(adapter);
6349 	}
6350 }
6351 
6352 /**
6353  *  igb_poll - NAPI Rx polling callback
6354  *  @napi: napi polling structure
6355  *  @budget: count of how many packets we should handle
6356  **/
6357 static int igb_poll(struct napi_struct *napi, int budget)
6358 {
6359 	struct igb_q_vector *q_vector = container_of(napi,
6360 						     struct igb_q_vector,
6361 						     napi);
6362 	bool clean_complete = true;
6363 
6364 #ifdef CONFIG_IGB_DCA
6365 	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6366 		igb_update_dca(q_vector);
6367 #endif
6368 	if (q_vector->tx.ring)
6369 		clean_complete = igb_clean_tx_irq(q_vector);
6370 
6371 	if (q_vector->rx.ring)
6372 		clean_complete &= igb_clean_rx_irq(q_vector, budget);
6373 
6374 	/* If all work not completed, return budget and keep polling */
6375 	if (!clean_complete)
6376 		return budget;
6377 
6378 	/* If not enough Rx work done, exit the polling mode */
6379 	napi_complete(napi);
6380 	igb_ring_irq_enable(q_vector);
6381 
6382 	return 0;
6383 }
6384 
6385 /**
6386  *  igb_clean_tx_irq - Reclaim resources after transmit completes
6387  *  @q_vector: pointer to q_vector containing needed info
6388  *
6389  *  returns true if ring is completely cleaned
6390  **/
6391 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6392 {
6393 	struct igb_adapter *adapter = q_vector->adapter;
6394 	struct igb_ring *tx_ring = q_vector->tx.ring;
6395 	struct igb_tx_buffer *tx_buffer;
6396 	union e1000_adv_tx_desc *tx_desc;
6397 	unsigned int total_bytes = 0, total_packets = 0;
6398 	unsigned int budget = q_vector->tx.work_limit;
6399 	unsigned int i = tx_ring->next_to_clean;
6400 
6401 	if (test_bit(__IGB_DOWN, &adapter->state))
6402 		return true;
6403 
6404 	tx_buffer = &tx_ring->tx_buffer_info[i];
6405 	tx_desc = IGB_TX_DESC(tx_ring, i);
6406 	i -= tx_ring->count;
6407 
6408 	do {
6409 		union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6410 
6411 		/* if next_to_watch is not set then there is no work pending */
6412 		if (!eop_desc)
6413 			break;
6414 
6415 		/* prevent any other reads prior to eop_desc */
6416 		read_barrier_depends();
6417 
6418 		/* if DD is not set pending work has not been completed */
6419 		if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6420 			break;
6421 
6422 		/* clear next_to_watch to prevent false hangs */
6423 		tx_buffer->next_to_watch = NULL;
6424 
6425 		/* update the statistics for this packet */
6426 		total_bytes += tx_buffer->bytecount;
6427 		total_packets += tx_buffer->gso_segs;
6428 
6429 		/* free the skb */
6430 		dev_consume_skb_any(tx_buffer->skb);
6431 
6432 		/* unmap skb header data */
6433 		dma_unmap_single(tx_ring->dev,
6434 				 dma_unmap_addr(tx_buffer, dma),
6435 				 dma_unmap_len(tx_buffer, len),
6436 				 DMA_TO_DEVICE);
6437 
6438 		/* clear tx_buffer data */
6439 		tx_buffer->skb = NULL;
6440 		dma_unmap_len_set(tx_buffer, len, 0);
6441 
6442 		/* clear last DMA location and unmap remaining buffers */
6443 		while (tx_desc != eop_desc) {
6444 			tx_buffer++;
6445 			tx_desc++;
6446 			i++;
6447 			if (unlikely(!i)) {
6448 				i -= tx_ring->count;
6449 				tx_buffer = tx_ring->tx_buffer_info;
6450 				tx_desc = IGB_TX_DESC(tx_ring, 0);
6451 			}
6452 
6453 			/* unmap any remaining paged data */
6454 			if (dma_unmap_len(tx_buffer, len)) {
6455 				dma_unmap_page(tx_ring->dev,
6456 					       dma_unmap_addr(tx_buffer, dma),
6457 					       dma_unmap_len(tx_buffer, len),
6458 					       DMA_TO_DEVICE);
6459 				dma_unmap_len_set(tx_buffer, len, 0);
6460 			}
6461 		}
6462 
6463 		/* move us one more past the eop_desc for start of next pkt */
6464 		tx_buffer++;
6465 		tx_desc++;
6466 		i++;
6467 		if (unlikely(!i)) {
6468 			i -= tx_ring->count;
6469 			tx_buffer = tx_ring->tx_buffer_info;
6470 			tx_desc = IGB_TX_DESC(tx_ring, 0);
6471 		}
6472 
6473 		/* issue prefetch for next Tx descriptor */
6474 		prefetch(tx_desc);
6475 
6476 		/* update budget accounting */
6477 		budget--;
6478 	} while (likely(budget));
6479 
6480 	netdev_tx_completed_queue(txring_txq(tx_ring),
6481 				  total_packets, total_bytes);
6482 	i += tx_ring->count;
6483 	tx_ring->next_to_clean = i;
6484 	u64_stats_update_begin(&tx_ring->tx_syncp);
6485 	tx_ring->tx_stats.bytes += total_bytes;
6486 	tx_ring->tx_stats.packets += total_packets;
6487 	u64_stats_update_end(&tx_ring->tx_syncp);
6488 	q_vector->tx.total_bytes += total_bytes;
6489 	q_vector->tx.total_packets += total_packets;
6490 
6491 	if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6492 		struct e1000_hw *hw = &adapter->hw;
6493 
6494 		/* Detect a transmit hang in hardware, this serializes the
6495 		 * check with the clearing of time_stamp and movement of i
6496 		 */
6497 		clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6498 		if (tx_buffer->next_to_watch &&
6499 		    time_after(jiffies, tx_buffer->time_stamp +
6500 			       (adapter->tx_timeout_factor * HZ)) &&
6501 		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6502 
6503 			/* detected Tx unit hang */
6504 			dev_err(tx_ring->dev,
6505 				"Detected Tx Unit Hang\n"
6506 				"  Tx Queue             <%d>\n"
6507 				"  TDH                  <%x>\n"
6508 				"  TDT                  <%x>\n"
6509 				"  next_to_use          <%x>\n"
6510 				"  next_to_clean        <%x>\n"
6511 				"buffer_info[next_to_clean]\n"
6512 				"  time_stamp           <%lx>\n"
6513 				"  next_to_watch        <%p>\n"
6514 				"  jiffies              <%lx>\n"
6515 				"  desc.status          <%x>\n",
6516 				tx_ring->queue_index,
6517 				rd32(E1000_TDH(tx_ring->reg_idx)),
6518 				readl(tx_ring->tail),
6519 				tx_ring->next_to_use,
6520 				tx_ring->next_to_clean,
6521 				tx_buffer->time_stamp,
6522 				tx_buffer->next_to_watch,
6523 				jiffies,
6524 				tx_buffer->next_to_watch->wb.status);
6525 			netif_stop_subqueue(tx_ring->netdev,
6526 					    tx_ring->queue_index);
6527 
6528 			/* we are about to reset, no point in enabling stuff */
6529 			return true;
6530 		}
6531 	}
6532 
6533 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6534 	if (unlikely(total_packets &&
6535 	    netif_carrier_ok(tx_ring->netdev) &&
6536 	    igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6537 		/* Make sure that anybody stopping the queue after this
6538 		 * sees the new next_to_clean.
6539 		 */
6540 		smp_mb();
6541 		if (__netif_subqueue_stopped(tx_ring->netdev,
6542 					     tx_ring->queue_index) &&
6543 		    !(test_bit(__IGB_DOWN, &adapter->state))) {
6544 			netif_wake_subqueue(tx_ring->netdev,
6545 					    tx_ring->queue_index);
6546 
6547 			u64_stats_update_begin(&tx_ring->tx_syncp);
6548 			tx_ring->tx_stats.restart_queue++;
6549 			u64_stats_update_end(&tx_ring->tx_syncp);
6550 		}
6551 	}
6552 
6553 	return !!budget;
6554 }
6555 
6556 /**
6557  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6558  *  @rx_ring: rx descriptor ring to store buffers on
6559  *  @old_buff: donor buffer to have page reused
6560  *
6561  *  Synchronizes page for reuse by the adapter
6562  **/
6563 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6564 			      struct igb_rx_buffer *old_buff)
6565 {
6566 	struct igb_rx_buffer *new_buff;
6567 	u16 nta = rx_ring->next_to_alloc;
6568 
6569 	new_buff = &rx_ring->rx_buffer_info[nta];
6570 
6571 	/* update, and store next to alloc */
6572 	nta++;
6573 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6574 
6575 	/* transfer page from old buffer to new buffer */
6576 	*new_buff = *old_buff;
6577 
6578 	/* sync the buffer for use by the device */
6579 	dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6580 					 old_buff->page_offset,
6581 					 IGB_RX_BUFSZ,
6582 					 DMA_FROM_DEVICE);
6583 }
6584 
6585 static inline bool igb_page_is_reserved(struct page *page)
6586 {
6587 	return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6588 }
6589 
6590 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6591 				  struct page *page,
6592 				  unsigned int truesize)
6593 {
6594 	/* avoid re-using remote pages */
6595 	if (unlikely(igb_page_is_reserved(page)))
6596 		return false;
6597 
6598 #if (PAGE_SIZE < 8192)
6599 	/* if we are only owner of page we can reuse it */
6600 	if (unlikely(page_count(page) != 1))
6601 		return false;
6602 
6603 	/* flip page offset to other buffer */
6604 	rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6605 #else
6606 	/* move offset up to the next cache line */
6607 	rx_buffer->page_offset += truesize;
6608 
6609 	if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6610 		return false;
6611 #endif
6612 
6613 	/* Even if we own the page, we are not allowed to use atomic_set()
6614 	 * This would break get_page_unless_zero() users.
6615 	 */
6616 	atomic_inc(&page->_count);
6617 
6618 	return true;
6619 }
6620 
6621 /**
6622  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6623  *  @rx_ring: rx descriptor ring to transact packets on
6624  *  @rx_buffer: buffer containing page to add
6625  *  @rx_desc: descriptor containing length of buffer written by hardware
6626  *  @skb: sk_buff to place the data into
6627  *
6628  *  This function will add the data contained in rx_buffer->page to the skb.
6629  *  This is done either through a direct copy if the data in the buffer is
6630  *  less than the skb header size, otherwise it will just attach the page as
6631  *  a frag to the skb.
6632  *
6633  *  The function will then update the page offset if necessary and return
6634  *  true if the buffer can be reused by the adapter.
6635  **/
6636 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6637 			    struct igb_rx_buffer *rx_buffer,
6638 			    union e1000_adv_rx_desc *rx_desc,
6639 			    struct sk_buff *skb)
6640 {
6641 	struct page *page = rx_buffer->page;
6642 	unsigned char *va = page_address(page) + rx_buffer->page_offset;
6643 	unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6644 #if (PAGE_SIZE < 8192)
6645 	unsigned int truesize = IGB_RX_BUFSZ;
6646 #else
6647 	unsigned int truesize = SKB_DATA_ALIGN(size);
6648 #endif
6649 	unsigned int pull_len;
6650 
6651 	if (unlikely(skb_is_nonlinear(skb)))
6652 		goto add_tail_frag;
6653 
6654 	if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6655 		igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6656 		va += IGB_TS_HDR_LEN;
6657 		size -= IGB_TS_HDR_LEN;
6658 	}
6659 
6660 	if (likely(size <= IGB_RX_HDR_LEN)) {
6661 		memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6662 
6663 		/* page is not reserved, we can reuse buffer as-is */
6664 		if (likely(!igb_page_is_reserved(page)))
6665 			return true;
6666 
6667 		/* this page cannot be reused so discard it */
6668 		__free_page(page);
6669 		return false;
6670 	}
6671 
6672 	/* we need the header to contain the greater of either ETH_HLEN or
6673 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
6674 	 */
6675 	pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6676 
6677 	/* align pull length to size of long to optimize memcpy performance */
6678 	memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6679 
6680 	/* update all of the pointers */
6681 	va += pull_len;
6682 	size -= pull_len;
6683 
6684 add_tail_frag:
6685 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6686 			(unsigned long)va & ~PAGE_MASK, size, truesize);
6687 
6688 	return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6689 }
6690 
6691 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6692 					   union e1000_adv_rx_desc *rx_desc,
6693 					   struct sk_buff *skb)
6694 {
6695 	struct igb_rx_buffer *rx_buffer;
6696 	struct page *page;
6697 
6698 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6699 	page = rx_buffer->page;
6700 	prefetchw(page);
6701 
6702 	if (likely(!skb)) {
6703 		void *page_addr = page_address(page) +
6704 				  rx_buffer->page_offset;
6705 
6706 		/* prefetch first cache line of first page */
6707 		prefetch(page_addr);
6708 #if L1_CACHE_BYTES < 128
6709 		prefetch(page_addr + L1_CACHE_BYTES);
6710 #endif
6711 
6712 		/* allocate a skb to store the frags */
6713 		skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6714 		if (unlikely(!skb)) {
6715 			rx_ring->rx_stats.alloc_failed++;
6716 			return NULL;
6717 		}
6718 
6719 		/* we will be copying header into skb->data in
6720 		 * pskb_may_pull so it is in our interest to prefetch
6721 		 * it now to avoid a possible cache miss
6722 		 */
6723 		prefetchw(skb->data);
6724 	}
6725 
6726 	/* we are reusing so sync this buffer for CPU use */
6727 	dma_sync_single_range_for_cpu(rx_ring->dev,
6728 				      rx_buffer->dma,
6729 				      rx_buffer->page_offset,
6730 				      IGB_RX_BUFSZ,
6731 				      DMA_FROM_DEVICE);
6732 
6733 	/* pull page into skb */
6734 	if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6735 		/* hand second half of page back to the ring */
6736 		igb_reuse_rx_page(rx_ring, rx_buffer);
6737 	} else {
6738 		/* we are not reusing the buffer so unmap it */
6739 		dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6740 			       PAGE_SIZE, DMA_FROM_DEVICE);
6741 	}
6742 
6743 	/* clear contents of rx_buffer */
6744 	rx_buffer->page = NULL;
6745 
6746 	return skb;
6747 }
6748 
6749 static inline void igb_rx_checksum(struct igb_ring *ring,
6750 				   union e1000_adv_rx_desc *rx_desc,
6751 				   struct sk_buff *skb)
6752 {
6753 	skb_checksum_none_assert(skb);
6754 
6755 	/* Ignore Checksum bit is set */
6756 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6757 		return;
6758 
6759 	/* Rx checksum disabled via ethtool */
6760 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
6761 		return;
6762 
6763 	/* TCP/UDP checksum error bit is set */
6764 	if (igb_test_staterr(rx_desc,
6765 			     E1000_RXDEXT_STATERR_TCPE |
6766 			     E1000_RXDEXT_STATERR_IPE)) {
6767 		/* work around errata with sctp packets where the TCPE aka
6768 		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6769 		 * packets, (aka let the stack check the crc32c)
6770 		 */
6771 		if (!((skb->len == 60) &&
6772 		      test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6773 			u64_stats_update_begin(&ring->rx_syncp);
6774 			ring->rx_stats.csum_err++;
6775 			u64_stats_update_end(&ring->rx_syncp);
6776 		}
6777 		/* let the stack verify checksum errors */
6778 		return;
6779 	}
6780 	/* It must be a TCP or UDP packet with a valid checksum */
6781 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6782 				      E1000_RXD_STAT_UDPCS))
6783 		skb->ip_summed = CHECKSUM_UNNECESSARY;
6784 
6785 	dev_dbg(ring->dev, "cksum success: bits %08X\n",
6786 		le32_to_cpu(rx_desc->wb.upper.status_error));
6787 }
6788 
6789 static inline void igb_rx_hash(struct igb_ring *ring,
6790 			       union e1000_adv_rx_desc *rx_desc,
6791 			       struct sk_buff *skb)
6792 {
6793 	if (ring->netdev->features & NETIF_F_RXHASH)
6794 		skb_set_hash(skb,
6795 			     le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6796 			     PKT_HASH_TYPE_L3);
6797 }
6798 
6799 /**
6800  *  igb_is_non_eop - process handling of non-EOP buffers
6801  *  @rx_ring: Rx ring being processed
6802  *  @rx_desc: Rx descriptor for current buffer
6803  *  @skb: current socket buffer containing buffer in progress
6804  *
6805  *  This function updates next to clean.  If the buffer is an EOP buffer
6806  *  this function exits returning false, otherwise it will place the
6807  *  sk_buff in the next buffer to be chained and return true indicating
6808  *  that this is in fact a non-EOP buffer.
6809  **/
6810 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6811 			   union e1000_adv_rx_desc *rx_desc)
6812 {
6813 	u32 ntc = rx_ring->next_to_clean + 1;
6814 
6815 	/* fetch, update, and store next to clean */
6816 	ntc = (ntc < rx_ring->count) ? ntc : 0;
6817 	rx_ring->next_to_clean = ntc;
6818 
6819 	prefetch(IGB_RX_DESC(rx_ring, ntc));
6820 
6821 	if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6822 		return false;
6823 
6824 	return true;
6825 }
6826 
6827 /**
6828  *  igb_cleanup_headers - Correct corrupted or empty headers
6829  *  @rx_ring: rx descriptor ring packet is being transacted on
6830  *  @rx_desc: pointer to the EOP Rx descriptor
6831  *  @skb: pointer to current skb being fixed
6832  *
6833  *  Address the case where we are pulling data in on pages only
6834  *  and as such no data is present in the skb header.
6835  *
6836  *  In addition if skb is not at least 60 bytes we need to pad it so that
6837  *  it is large enough to qualify as a valid Ethernet frame.
6838  *
6839  *  Returns true if an error was encountered and skb was freed.
6840  **/
6841 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6842 				union e1000_adv_rx_desc *rx_desc,
6843 				struct sk_buff *skb)
6844 {
6845 	if (unlikely((igb_test_staterr(rx_desc,
6846 				       E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6847 		struct net_device *netdev = rx_ring->netdev;
6848 		if (!(netdev->features & NETIF_F_RXALL)) {
6849 			dev_kfree_skb_any(skb);
6850 			return true;
6851 		}
6852 	}
6853 
6854 	/* if eth_skb_pad returns an error the skb was freed */
6855 	if (eth_skb_pad(skb))
6856 		return true;
6857 
6858 	return false;
6859 }
6860 
6861 /**
6862  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6863  *  @rx_ring: rx descriptor ring packet is being transacted on
6864  *  @rx_desc: pointer to the EOP Rx descriptor
6865  *  @skb: pointer to current skb being populated
6866  *
6867  *  This function checks the ring, descriptor, and packet information in
6868  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6869  *  other fields within the skb.
6870  **/
6871 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6872 				   union e1000_adv_rx_desc *rx_desc,
6873 				   struct sk_buff *skb)
6874 {
6875 	struct net_device *dev = rx_ring->netdev;
6876 
6877 	igb_rx_hash(rx_ring, rx_desc, skb);
6878 
6879 	igb_rx_checksum(rx_ring, rx_desc, skb);
6880 
6881 	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6882 	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6883 		igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6884 
6885 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6886 	    igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6887 		u16 vid;
6888 
6889 		if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6890 		    test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6891 			vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6892 		else
6893 			vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6894 
6895 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6896 	}
6897 
6898 	skb_record_rx_queue(skb, rx_ring->queue_index);
6899 
6900 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6901 }
6902 
6903 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6904 {
6905 	struct igb_ring *rx_ring = q_vector->rx.ring;
6906 	struct sk_buff *skb = rx_ring->skb;
6907 	unsigned int total_bytes = 0, total_packets = 0;
6908 	u16 cleaned_count = igb_desc_unused(rx_ring);
6909 
6910 	while (likely(total_packets < budget)) {
6911 		union e1000_adv_rx_desc *rx_desc;
6912 
6913 		/* return some buffers to hardware, one at a time is too slow */
6914 		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6915 			igb_alloc_rx_buffers(rx_ring, cleaned_count);
6916 			cleaned_count = 0;
6917 		}
6918 
6919 		rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6920 
6921 		if (!rx_desc->wb.upper.status_error)
6922 			break;
6923 
6924 		/* This memory barrier is needed to keep us from reading
6925 		 * any other fields out of the rx_desc until we know the
6926 		 * descriptor has been written back
6927 		 */
6928 		dma_rmb();
6929 
6930 		/* retrieve a buffer from the ring */
6931 		skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6932 
6933 		/* exit if we failed to retrieve a buffer */
6934 		if (!skb)
6935 			break;
6936 
6937 		cleaned_count++;
6938 
6939 		/* fetch next buffer in frame if non-eop */
6940 		if (igb_is_non_eop(rx_ring, rx_desc))
6941 			continue;
6942 
6943 		/* verify the packet layout is correct */
6944 		if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6945 			skb = NULL;
6946 			continue;
6947 		}
6948 
6949 		/* probably a little skewed due to removing CRC */
6950 		total_bytes += skb->len;
6951 
6952 		/* populate checksum, timestamp, VLAN, and protocol */
6953 		igb_process_skb_fields(rx_ring, rx_desc, skb);
6954 
6955 		napi_gro_receive(&q_vector->napi, skb);
6956 
6957 		/* reset skb pointer */
6958 		skb = NULL;
6959 
6960 		/* update budget accounting */
6961 		total_packets++;
6962 	}
6963 
6964 	/* place incomplete frames back on ring for completion */
6965 	rx_ring->skb = skb;
6966 
6967 	u64_stats_update_begin(&rx_ring->rx_syncp);
6968 	rx_ring->rx_stats.packets += total_packets;
6969 	rx_ring->rx_stats.bytes += total_bytes;
6970 	u64_stats_update_end(&rx_ring->rx_syncp);
6971 	q_vector->rx.total_packets += total_packets;
6972 	q_vector->rx.total_bytes += total_bytes;
6973 
6974 	if (cleaned_count)
6975 		igb_alloc_rx_buffers(rx_ring, cleaned_count);
6976 
6977 	return total_packets < budget;
6978 }
6979 
6980 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6981 				  struct igb_rx_buffer *bi)
6982 {
6983 	struct page *page = bi->page;
6984 	dma_addr_t dma;
6985 
6986 	/* since we are recycling buffers we should seldom need to alloc */
6987 	if (likely(page))
6988 		return true;
6989 
6990 	/* alloc new page for storage */
6991 	page = dev_alloc_page();
6992 	if (unlikely(!page)) {
6993 		rx_ring->rx_stats.alloc_failed++;
6994 		return false;
6995 	}
6996 
6997 	/* map page for use */
6998 	dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6999 
7000 	/* if mapping failed free memory back to system since
7001 	 * there isn't much point in holding memory we can't use
7002 	 */
7003 	if (dma_mapping_error(rx_ring->dev, dma)) {
7004 		__free_page(page);
7005 
7006 		rx_ring->rx_stats.alloc_failed++;
7007 		return false;
7008 	}
7009 
7010 	bi->dma = dma;
7011 	bi->page = page;
7012 	bi->page_offset = 0;
7013 
7014 	return true;
7015 }
7016 
7017 /**
7018  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
7019  *  @adapter: address of board private structure
7020  **/
7021 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7022 {
7023 	union e1000_adv_rx_desc *rx_desc;
7024 	struct igb_rx_buffer *bi;
7025 	u16 i = rx_ring->next_to_use;
7026 
7027 	/* nothing to do */
7028 	if (!cleaned_count)
7029 		return;
7030 
7031 	rx_desc = IGB_RX_DESC(rx_ring, i);
7032 	bi = &rx_ring->rx_buffer_info[i];
7033 	i -= rx_ring->count;
7034 
7035 	do {
7036 		if (!igb_alloc_mapped_page(rx_ring, bi))
7037 			break;
7038 
7039 		/* Refresh the desc even if buffer_addrs didn't change
7040 		 * because each write-back erases this info.
7041 		 */
7042 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7043 
7044 		rx_desc++;
7045 		bi++;
7046 		i++;
7047 		if (unlikely(!i)) {
7048 			rx_desc = IGB_RX_DESC(rx_ring, 0);
7049 			bi = rx_ring->rx_buffer_info;
7050 			i -= rx_ring->count;
7051 		}
7052 
7053 		/* clear the status bits for the next_to_use descriptor */
7054 		rx_desc->wb.upper.status_error = 0;
7055 
7056 		cleaned_count--;
7057 	} while (cleaned_count);
7058 
7059 	i += rx_ring->count;
7060 
7061 	if (rx_ring->next_to_use != i) {
7062 		/* record the next descriptor to use */
7063 		rx_ring->next_to_use = i;
7064 
7065 		/* update next to alloc since we have filled the ring */
7066 		rx_ring->next_to_alloc = i;
7067 
7068 		/* Force memory writes to complete before letting h/w
7069 		 * know there are new descriptors to fetch.  (Only
7070 		 * applicable for weak-ordered memory model archs,
7071 		 * such as IA-64).
7072 		 */
7073 		wmb();
7074 		writel(i, rx_ring->tail);
7075 	}
7076 }
7077 
7078 /**
7079  * igb_mii_ioctl -
7080  * @netdev:
7081  * @ifreq:
7082  * @cmd:
7083  **/
7084 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7085 {
7086 	struct igb_adapter *adapter = netdev_priv(netdev);
7087 	struct mii_ioctl_data *data = if_mii(ifr);
7088 
7089 	if (adapter->hw.phy.media_type != e1000_media_type_copper)
7090 		return -EOPNOTSUPP;
7091 
7092 	switch (cmd) {
7093 	case SIOCGMIIPHY:
7094 		data->phy_id = adapter->hw.phy.addr;
7095 		break;
7096 	case SIOCGMIIREG:
7097 		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7098 				     &data->val_out))
7099 			return -EIO;
7100 		break;
7101 	case SIOCSMIIREG:
7102 	default:
7103 		return -EOPNOTSUPP;
7104 	}
7105 	return 0;
7106 }
7107 
7108 /**
7109  * igb_ioctl -
7110  * @netdev:
7111  * @ifreq:
7112  * @cmd:
7113  **/
7114 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7115 {
7116 	switch (cmd) {
7117 	case SIOCGMIIPHY:
7118 	case SIOCGMIIREG:
7119 	case SIOCSMIIREG:
7120 		return igb_mii_ioctl(netdev, ifr, cmd);
7121 	case SIOCGHWTSTAMP:
7122 		return igb_ptp_get_ts_config(netdev, ifr);
7123 	case SIOCSHWTSTAMP:
7124 		return igb_ptp_set_ts_config(netdev, ifr);
7125 	default:
7126 		return -EOPNOTSUPP;
7127 	}
7128 }
7129 
7130 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7131 {
7132 	struct igb_adapter *adapter = hw->back;
7133 
7134 	pci_read_config_word(adapter->pdev, reg, value);
7135 }
7136 
7137 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7138 {
7139 	struct igb_adapter *adapter = hw->back;
7140 
7141 	pci_write_config_word(adapter->pdev, reg, *value);
7142 }
7143 
7144 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7145 {
7146 	struct igb_adapter *adapter = hw->back;
7147 
7148 	if (pcie_capability_read_word(adapter->pdev, reg, value))
7149 		return -E1000_ERR_CONFIG;
7150 
7151 	return 0;
7152 }
7153 
7154 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7155 {
7156 	struct igb_adapter *adapter = hw->back;
7157 
7158 	if (pcie_capability_write_word(adapter->pdev, reg, *value))
7159 		return -E1000_ERR_CONFIG;
7160 
7161 	return 0;
7162 }
7163 
7164 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7165 {
7166 	struct igb_adapter *adapter = netdev_priv(netdev);
7167 	struct e1000_hw *hw = &adapter->hw;
7168 	u32 ctrl, rctl;
7169 	bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7170 
7171 	if (enable) {
7172 		/* enable VLAN tag insert/strip */
7173 		ctrl = rd32(E1000_CTRL);
7174 		ctrl |= E1000_CTRL_VME;
7175 		wr32(E1000_CTRL, ctrl);
7176 
7177 		/* Disable CFI check */
7178 		rctl = rd32(E1000_RCTL);
7179 		rctl &= ~E1000_RCTL_CFIEN;
7180 		wr32(E1000_RCTL, rctl);
7181 	} else {
7182 		/* disable VLAN tag insert/strip */
7183 		ctrl = rd32(E1000_CTRL);
7184 		ctrl &= ~E1000_CTRL_VME;
7185 		wr32(E1000_CTRL, ctrl);
7186 	}
7187 
7188 	igb_rlpml_set(adapter);
7189 }
7190 
7191 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7192 			       __be16 proto, u16 vid)
7193 {
7194 	struct igb_adapter *adapter = netdev_priv(netdev);
7195 	struct e1000_hw *hw = &adapter->hw;
7196 	int pf_id = adapter->vfs_allocated_count;
7197 
7198 	/* attempt to add filter to vlvf array */
7199 	igb_vlvf_set(adapter, vid, true, pf_id);
7200 
7201 	/* add the filter since PF can receive vlans w/o entry in vlvf */
7202 	igb_vfta_set(hw, vid, true);
7203 
7204 	set_bit(vid, adapter->active_vlans);
7205 
7206 	return 0;
7207 }
7208 
7209 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7210 				__be16 proto, u16 vid)
7211 {
7212 	struct igb_adapter *adapter = netdev_priv(netdev);
7213 	struct e1000_hw *hw = &adapter->hw;
7214 	int pf_id = adapter->vfs_allocated_count;
7215 	s32 err;
7216 
7217 	/* remove vlan from VLVF table array */
7218 	err = igb_vlvf_set(adapter, vid, false, pf_id);
7219 
7220 	/* if vid was not present in VLVF just remove it from table */
7221 	if (err)
7222 		igb_vfta_set(hw, vid, false);
7223 
7224 	clear_bit(vid, adapter->active_vlans);
7225 
7226 	return 0;
7227 }
7228 
7229 static void igb_restore_vlan(struct igb_adapter *adapter)
7230 {
7231 	u16 vid;
7232 
7233 	igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7234 
7235 	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7236 		igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7237 }
7238 
7239 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7240 {
7241 	struct pci_dev *pdev = adapter->pdev;
7242 	struct e1000_mac_info *mac = &adapter->hw.mac;
7243 
7244 	mac->autoneg = 0;
7245 
7246 	/* Make sure dplx is at most 1 bit and lsb of speed is not set
7247 	 * for the switch() below to work
7248 	 */
7249 	if ((spd & 1) || (dplx & ~1))
7250 		goto err_inval;
7251 
7252 	/* Fiber NIC's only allow 1000 gbps Full duplex
7253 	 * and 100Mbps Full duplex for 100baseFx sfp
7254 	 */
7255 	if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7256 		switch (spd + dplx) {
7257 		case SPEED_10 + DUPLEX_HALF:
7258 		case SPEED_10 + DUPLEX_FULL:
7259 		case SPEED_100 + DUPLEX_HALF:
7260 			goto err_inval;
7261 		default:
7262 			break;
7263 		}
7264 	}
7265 
7266 	switch (spd + dplx) {
7267 	case SPEED_10 + DUPLEX_HALF:
7268 		mac->forced_speed_duplex = ADVERTISE_10_HALF;
7269 		break;
7270 	case SPEED_10 + DUPLEX_FULL:
7271 		mac->forced_speed_duplex = ADVERTISE_10_FULL;
7272 		break;
7273 	case SPEED_100 + DUPLEX_HALF:
7274 		mac->forced_speed_duplex = ADVERTISE_100_HALF;
7275 		break;
7276 	case SPEED_100 + DUPLEX_FULL:
7277 		mac->forced_speed_duplex = ADVERTISE_100_FULL;
7278 		break;
7279 	case SPEED_1000 + DUPLEX_FULL:
7280 		mac->autoneg = 1;
7281 		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7282 		break;
7283 	case SPEED_1000 + DUPLEX_HALF: /* not supported */
7284 	default:
7285 		goto err_inval;
7286 	}
7287 
7288 	/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7289 	adapter->hw.phy.mdix = AUTO_ALL_MODES;
7290 
7291 	return 0;
7292 
7293 err_inval:
7294 	dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7295 	return -EINVAL;
7296 }
7297 
7298 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7299 			  bool runtime)
7300 {
7301 	struct net_device *netdev = pci_get_drvdata(pdev);
7302 	struct igb_adapter *adapter = netdev_priv(netdev);
7303 	struct e1000_hw *hw = &adapter->hw;
7304 	u32 ctrl, rctl, status;
7305 	u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7306 #ifdef CONFIG_PM
7307 	int retval = 0;
7308 #endif
7309 
7310 	netif_device_detach(netdev);
7311 
7312 	if (netif_running(netdev))
7313 		__igb_close(netdev, true);
7314 
7315 	igb_clear_interrupt_scheme(adapter);
7316 
7317 #ifdef CONFIG_PM
7318 	retval = pci_save_state(pdev);
7319 	if (retval)
7320 		return retval;
7321 #endif
7322 
7323 	status = rd32(E1000_STATUS);
7324 	if (status & E1000_STATUS_LU)
7325 		wufc &= ~E1000_WUFC_LNKC;
7326 
7327 	if (wufc) {
7328 		igb_setup_rctl(adapter);
7329 		igb_set_rx_mode(netdev);
7330 
7331 		/* turn on all-multi mode if wake on multicast is enabled */
7332 		if (wufc & E1000_WUFC_MC) {
7333 			rctl = rd32(E1000_RCTL);
7334 			rctl |= E1000_RCTL_MPE;
7335 			wr32(E1000_RCTL, rctl);
7336 		}
7337 
7338 		ctrl = rd32(E1000_CTRL);
7339 		/* advertise wake from D3Cold */
7340 		#define E1000_CTRL_ADVD3WUC 0x00100000
7341 		/* phy power management enable */
7342 		#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7343 		ctrl |= E1000_CTRL_ADVD3WUC;
7344 		wr32(E1000_CTRL, ctrl);
7345 
7346 		/* Allow time for pending master requests to run */
7347 		igb_disable_pcie_master(hw);
7348 
7349 		wr32(E1000_WUC, E1000_WUC_PME_EN);
7350 		wr32(E1000_WUFC, wufc);
7351 	} else {
7352 		wr32(E1000_WUC, 0);
7353 		wr32(E1000_WUFC, 0);
7354 	}
7355 
7356 	*enable_wake = wufc || adapter->en_mng_pt;
7357 	if (!*enable_wake)
7358 		igb_power_down_link(adapter);
7359 	else
7360 		igb_power_up_link(adapter);
7361 
7362 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
7363 	 * would have already happened in close and is redundant.
7364 	 */
7365 	igb_release_hw_control(adapter);
7366 
7367 	pci_disable_device(pdev);
7368 
7369 	return 0;
7370 }
7371 
7372 #ifdef CONFIG_PM
7373 #ifdef CONFIG_PM_SLEEP
7374 static int igb_suspend(struct device *dev)
7375 {
7376 	int retval;
7377 	bool wake;
7378 	struct pci_dev *pdev = to_pci_dev(dev);
7379 
7380 	retval = __igb_shutdown(pdev, &wake, 0);
7381 	if (retval)
7382 		return retval;
7383 
7384 	if (wake) {
7385 		pci_prepare_to_sleep(pdev);
7386 	} else {
7387 		pci_wake_from_d3(pdev, false);
7388 		pci_set_power_state(pdev, PCI_D3hot);
7389 	}
7390 
7391 	return 0;
7392 }
7393 #endif /* CONFIG_PM_SLEEP */
7394 
7395 static int igb_resume(struct device *dev)
7396 {
7397 	struct pci_dev *pdev = to_pci_dev(dev);
7398 	struct net_device *netdev = pci_get_drvdata(pdev);
7399 	struct igb_adapter *adapter = netdev_priv(netdev);
7400 	struct e1000_hw *hw = &adapter->hw;
7401 	u32 err;
7402 
7403 	pci_set_power_state(pdev, PCI_D0);
7404 	pci_restore_state(pdev);
7405 	pci_save_state(pdev);
7406 
7407 	if (!pci_device_is_present(pdev))
7408 		return -ENODEV;
7409 	err = pci_enable_device_mem(pdev);
7410 	if (err) {
7411 		dev_err(&pdev->dev,
7412 			"igb: Cannot enable PCI device from suspend\n");
7413 		return err;
7414 	}
7415 	pci_set_master(pdev);
7416 
7417 	pci_enable_wake(pdev, PCI_D3hot, 0);
7418 	pci_enable_wake(pdev, PCI_D3cold, 0);
7419 
7420 	if (igb_init_interrupt_scheme(adapter, true)) {
7421 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7422 		rtnl_unlock();
7423 		return -ENOMEM;
7424 	}
7425 
7426 	igb_reset(adapter);
7427 
7428 	/* let the f/w know that the h/w is now under the control of the
7429 	 * driver.
7430 	 */
7431 	igb_get_hw_control(adapter);
7432 
7433 	wr32(E1000_WUS, ~0);
7434 
7435 	if (netdev->flags & IFF_UP) {
7436 		rtnl_lock();
7437 		err = __igb_open(netdev, true);
7438 		rtnl_unlock();
7439 		if (err)
7440 			return err;
7441 	}
7442 
7443 	netif_device_attach(netdev);
7444 	return 0;
7445 }
7446 
7447 static int igb_runtime_idle(struct device *dev)
7448 {
7449 	struct pci_dev *pdev = to_pci_dev(dev);
7450 	struct net_device *netdev = pci_get_drvdata(pdev);
7451 	struct igb_adapter *adapter = netdev_priv(netdev);
7452 
7453 	if (!igb_has_link(adapter))
7454 		pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7455 
7456 	return -EBUSY;
7457 }
7458 
7459 static int igb_runtime_suspend(struct device *dev)
7460 {
7461 	struct pci_dev *pdev = to_pci_dev(dev);
7462 	int retval;
7463 	bool wake;
7464 
7465 	retval = __igb_shutdown(pdev, &wake, 1);
7466 	if (retval)
7467 		return retval;
7468 
7469 	if (wake) {
7470 		pci_prepare_to_sleep(pdev);
7471 	} else {
7472 		pci_wake_from_d3(pdev, false);
7473 		pci_set_power_state(pdev, PCI_D3hot);
7474 	}
7475 
7476 	return 0;
7477 }
7478 
7479 static int igb_runtime_resume(struct device *dev)
7480 {
7481 	return igb_resume(dev);
7482 }
7483 #endif /* CONFIG_PM */
7484 
7485 static void igb_shutdown(struct pci_dev *pdev)
7486 {
7487 	bool wake;
7488 
7489 	__igb_shutdown(pdev, &wake, 0);
7490 
7491 	if (system_state == SYSTEM_POWER_OFF) {
7492 		pci_wake_from_d3(pdev, wake);
7493 		pci_set_power_state(pdev, PCI_D3hot);
7494 	}
7495 }
7496 
7497 #ifdef CONFIG_PCI_IOV
7498 static int igb_sriov_reinit(struct pci_dev *dev)
7499 {
7500 	struct net_device *netdev = pci_get_drvdata(dev);
7501 	struct igb_adapter *adapter = netdev_priv(netdev);
7502 	struct pci_dev *pdev = adapter->pdev;
7503 
7504 	rtnl_lock();
7505 
7506 	if (netif_running(netdev))
7507 		igb_close(netdev);
7508 	else
7509 		igb_reset(adapter);
7510 
7511 	igb_clear_interrupt_scheme(adapter);
7512 
7513 	igb_init_queue_configuration(adapter);
7514 
7515 	if (igb_init_interrupt_scheme(adapter, true)) {
7516 		rtnl_unlock();
7517 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7518 		return -ENOMEM;
7519 	}
7520 
7521 	if (netif_running(netdev))
7522 		igb_open(netdev);
7523 
7524 	rtnl_unlock();
7525 
7526 	return 0;
7527 }
7528 
7529 static int igb_pci_disable_sriov(struct pci_dev *dev)
7530 {
7531 	int err = igb_disable_sriov(dev);
7532 
7533 	if (!err)
7534 		err = igb_sriov_reinit(dev);
7535 
7536 	return err;
7537 }
7538 
7539 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7540 {
7541 	int err = igb_enable_sriov(dev, num_vfs);
7542 
7543 	if (err)
7544 		goto out;
7545 
7546 	err = igb_sriov_reinit(dev);
7547 	if (!err)
7548 		return num_vfs;
7549 
7550 out:
7551 	return err;
7552 }
7553 
7554 #endif
7555 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7556 {
7557 #ifdef CONFIG_PCI_IOV
7558 	if (num_vfs == 0)
7559 		return igb_pci_disable_sriov(dev);
7560 	else
7561 		return igb_pci_enable_sriov(dev, num_vfs);
7562 #endif
7563 	return 0;
7564 }
7565 
7566 #ifdef CONFIG_NET_POLL_CONTROLLER
7567 /* Polling 'interrupt' - used by things like netconsole to send skbs
7568  * without having to re-enable interrupts. It's not called while
7569  * the interrupt routine is executing.
7570  */
7571 static void igb_netpoll(struct net_device *netdev)
7572 {
7573 	struct igb_adapter *adapter = netdev_priv(netdev);
7574 	struct e1000_hw *hw = &adapter->hw;
7575 	struct igb_q_vector *q_vector;
7576 	int i;
7577 
7578 	for (i = 0; i < adapter->num_q_vectors; i++) {
7579 		q_vector = adapter->q_vector[i];
7580 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
7581 			wr32(E1000_EIMC, q_vector->eims_value);
7582 		else
7583 			igb_irq_disable(adapter);
7584 		napi_schedule(&q_vector->napi);
7585 	}
7586 }
7587 #endif /* CONFIG_NET_POLL_CONTROLLER */
7588 
7589 /**
7590  *  igb_io_error_detected - called when PCI error is detected
7591  *  @pdev: Pointer to PCI device
7592  *  @state: The current pci connection state
7593  *
7594  *  This function is called after a PCI bus error affecting
7595  *  this device has been detected.
7596  **/
7597 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7598 					      pci_channel_state_t state)
7599 {
7600 	struct net_device *netdev = pci_get_drvdata(pdev);
7601 	struct igb_adapter *adapter = netdev_priv(netdev);
7602 
7603 	netif_device_detach(netdev);
7604 
7605 	if (state == pci_channel_io_perm_failure)
7606 		return PCI_ERS_RESULT_DISCONNECT;
7607 
7608 	if (netif_running(netdev))
7609 		igb_down(adapter);
7610 	pci_disable_device(pdev);
7611 
7612 	/* Request a slot slot reset. */
7613 	return PCI_ERS_RESULT_NEED_RESET;
7614 }
7615 
7616 /**
7617  *  igb_io_slot_reset - called after the pci bus has been reset.
7618  *  @pdev: Pointer to PCI device
7619  *
7620  *  Restart the card from scratch, as if from a cold-boot. Implementation
7621  *  resembles the first-half of the igb_resume routine.
7622  **/
7623 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7624 {
7625 	struct net_device *netdev = pci_get_drvdata(pdev);
7626 	struct igb_adapter *adapter = netdev_priv(netdev);
7627 	struct e1000_hw *hw = &adapter->hw;
7628 	pci_ers_result_t result;
7629 	int err;
7630 
7631 	if (pci_enable_device_mem(pdev)) {
7632 		dev_err(&pdev->dev,
7633 			"Cannot re-enable PCI device after reset.\n");
7634 		result = PCI_ERS_RESULT_DISCONNECT;
7635 	} else {
7636 		pci_set_master(pdev);
7637 		pci_restore_state(pdev);
7638 		pci_save_state(pdev);
7639 
7640 		pci_enable_wake(pdev, PCI_D3hot, 0);
7641 		pci_enable_wake(pdev, PCI_D3cold, 0);
7642 
7643 		igb_reset(adapter);
7644 		wr32(E1000_WUS, ~0);
7645 		result = PCI_ERS_RESULT_RECOVERED;
7646 	}
7647 
7648 	err = pci_cleanup_aer_uncorrect_error_status(pdev);
7649 	if (err) {
7650 		dev_err(&pdev->dev,
7651 			"pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7652 			err);
7653 		/* non-fatal, continue */
7654 	}
7655 
7656 	return result;
7657 }
7658 
7659 /**
7660  *  igb_io_resume - called when traffic can start flowing again.
7661  *  @pdev: Pointer to PCI device
7662  *
7663  *  This callback is called when the error recovery driver tells us that
7664  *  its OK to resume normal operation. Implementation resembles the
7665  *  second-half of the igb_resume routine.
7666  */
7667 static void igb_io_resume(struct pci_dev *pdev)
7668 {
7669 	struct net_device *netdev = pci_get_drvdata(pdev);
7670 	struct igb_adapter *adapter = netdev_priv(netdev);
7671 
7672 	if (netif_running(netdev)) {
7673 		if (igb_up(adapter)) {
7674 			dev_err(&pdev->dev, "igb_up failed after reset\n");
7675 			return;
7676 		}
7677 	}
7678 
7679 	netif_device_attach(netdev);
7680 
7681 	/* let the f/w know that the h/w is now under the control of the
7682 	 * driver.
7683 	 */
7684 	igb_get_hw_control(adapter);
7685 }
7686 
7687 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7688 			     u8 qsel)
7689 {
7690 	u32 rar_low, rar_high;
7691 	struct e1000_hw *hw = &adapter->hw;
7692 
7693 	/* HW expects these in little endian so we reverse the byte order
7694 	 * from network order (big endian) to little endian
7695 	 */
7696 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7697 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7698 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7699 
7700 	/* Indicate to hardware the Address is Valid. */
7701 	rar_high |= E1000_RAH_AV;
7702 
7703 	if (hw->mac.type == e1000_82575)
7704 		rar_high |= E1000_RAH_POOL_1 * qsel;
7705 	else
7706 		rar_high |= E1000_RAH_POOL_1 << qsel;
7707 
7708 	wr32(E1000_RAL(index), rar_low);
7709 	wrfl();
7710 	wr32(E1000_RAH(index), rar_high);
7711 	wrfl();
7712 }
7713 
7714 static int igb_set_vf_mac(struct igb_adapter *adapter,
7715 			  int vf, unsigned char *mac_addr)
7716 {
7717 	struct e1000_hw *hw = &adapter->hw;
7718 	/* VF MAC addresses start at end of receive addresses and moves
7719 	 * towards the first, as a result a collision should not be possible
7720 	 */
7721 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7722 
7723 	memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7724 
7725 	igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7726 
7727 	return 0;
7728 }
7729 
7730 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7731 {
7732 	struct igb_adapter *adapter = netdev_priv(netdev);
7733 	if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7734 		return -EINVAL;
7735 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7736 	dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7737 	dev_info(&adapter->pdev->dev,
7738 		 "Reload the VF driver to make this change effective.");
7739 	if (test_bit(__IGB_DOWN, &adapter->state)) {
7740 		dev_warn(&adapter->pdev->dev,
7741 			 "The VF MAC address has been set, but the PF device is not up.\n");
7742 		dev_warn(&adapter->pdev->dev,
7743 			 "Bring the PF device up before attempting to use the VF device.\n");
7744 	}
7745 	return igb_set_vf_mac(adapter, vf, mac);
7746 }
7747 
7748 static int igb_link_mbps(int internal_link_speed)
7749 {
7750 	switch (internal_link_speed) {
7751 	case SPEED_100:
7752 		return 100;
7753 	case SPEED_1000:
7754 		return 1000;
7755 	default:
7756 		return 0;
7757 	}
7758 }
7759 
7760 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7761 				  int link_speed)
7762 {
7763 	int rf_dec, rf_int;
7764 	u32 bcnrc_val;
7765 
7766 	if (tx_rate != 0) {
7767 		/* Calculate the rate factor values to set */
7768 		rf_int = link_speed / tx_rate;
7769 		rf_dec = (link_speed - (rf_int * tx_rate));
7770 		rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7771 			 tx_rate;
7772 
7773 		bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7774 		bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7775 			      E1000_RTTBCNRC_RF_INT_MASK);
7776 		bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7777 	} else {
7778 		bcnrc_val = 0;
7779 	}
7780 
7781 	wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7782 	/* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7783 	 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7784 	 */
7785 	wr32(E1000_RTTBCNRM, 0x14);
7786 	wr32(E1000_RTTBCNRC, bcnrc_val);
7787 }
7788 
7789 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7790 {
7791 	int actual_link_speed, i;
7792 	bool reset_rate = false;
7793 
7794 	/* VF TX rate limit was not set or not supported */
7795 	if ((adapter->vf_rate_link_speed == 0) ||
7796 	    (adapter->hw.mac.type != e1000_82576))
7797 		return;
7798 
7799 	actual_link_speed = igb_link_mbps(adapter->link_speed);
7800 	if (actual_link_speed != adapter->vf_rate_link_speed) {
7801 		reset_rate = true;
7802 		adapter->vf_rate_link_speed = 0;
7803 		dev_info(&adapter->pdev->dev,
7804 			 "Link speed has been changed. VF Transmit rate is disabled\n");
7805 	}
7806 
7807 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
7808 		if (reset_rate)
7809 			adapter->vf_data[i].tx_rate = 0;
7810 
7811 		igb_set_vf_rate_limit(&adapter->hw, i,
7812 				      adapter->vf_data[i].tx_rate,
7813 				      actual_link_speed);
7814 	}
7815 }
7816 
7817 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7818 			     int min_tx_rate, int max_tx_rate)
7819 {
7820 	struct igb_adapter *adapter = netdev_priv(netdev);
7821 	struct e1000_hw *hw = &adapter->hw;
7822 	int actual_link_speed;
7823 
7824 	if (hw->mac.type != e1000_82576)
7825 		return -EOPNOTSUPP;
7826 
7827 	if (min_tx_rate)
7828 		return -EINVAL;
7829 
7830 	actual_link_speed = igb_link_mbps(adapter->link_speed);
7831 	if ((vf >= adapter->vfs_allocated_count) ||
7832 	    (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7833 	    (max_tx_rate < 0) ||
7834 	    (max_tx_rate > actual_link_speed))
7835 		return -EINVAL;
7836 
7837 	adapter->vf_rate_link_speed = actual_link_speed;
7838 	adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7839 	igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7840 
7841 	return 0;
7842 }
7843 
7844 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7845 				   bool setting)
7846 {
7847 	struct igb_adapter *adapter = netdev_priv(netdev);
7848 	struct e1000_hw *hw = &adapter->hw;
7849 	u32 reg_val, reg_offset;
7850 
7851 	if (!adapter->vfs_allocated_count)
7852 		return -EOPNOTSUPP;
7853 
7854 	if (vf >= adapter->vfs_allocated_count)
7855 		return -EINVAL;
7856 
7857 	reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7858 	reg_val = rd32(reg_offset);
7859 	if (setting)
7860 		reg_val |= ((1 << vf) |
7861 			    (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7862 	else
7863 		reg_val &= ~((1 << vf) |
7864 			     (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7865 	wr32(reg_offset, reg_val);
7866 
7867 	adapter->vf_data[vf].spoofchk_enabled = setting;
7868 	return 0;
7869 }
7870 
7871 static int igb_ndo_get_vf_config(struct net_device *netdev,
7872 				 int vf, struct ifla_vf_info *ivi)
7873 {
7874 	struct igb_adapter *adapter = netdev_priv(netdev);
7875 	if (vf >= adapter->vfs_allocated_count)
7876 		return -EINVAL;
7877 	ivi->vf = vf;
7878 	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7879 	ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7880 	ivi->min_tx_rate = 0;
7881 	ivi->vlan = adapter->vf_data[vf].pf_vlan;
7882 	ivi->qos = adapter->vf_data[vf].pf_qos;
7883 	ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7884 	return 0;
7885 }
7886 
7887 static void igb_vmm_control(struct igb_adapter *adapter)
7888 {
7889 	struct e1000_hw *hw = &adapter->hw;
7890 	u32 reg;
7891 
7892 	switch (hw->mac.type) {
7893 	case e1000_82575:
7894 	case e1000_i210:
7895 	case e1000_i211:
7896 	case e1000_i354:
7897 	default:
7898 		/* replication is not supported for 82575 */
7899 		return;
7900 	case e1000_82576:
7901 		/* notify HW that the MAC is adding vlan tags */
7902 		reg = rd32(E1000_DTXCTL);
7903 		reg |= E1000_DTXCTL_VLAN_ADDED;
7904 		wr32(E1000_DTXCTL, reg);
7905 		/* Fall through */
7906 	case e1000_82580:
7907 		/* enable replication vlan tag stripping */
7908 		reg = rd32(E1000_RPLOLR);
7909 		reg |= E1000_RPLOLR_STRVLAN;
7910 		wr32(E1000_RPLOLR, reg);
7911 		/* Fall through */
7912 	case e1000_i350:
7913 		/* none of the above registers are supported by i350 */
7914 		break;
7915 	}
7916 
7917 	if (adapter->vfs_allocated_count) {
7918 		igb_vmdq_set_loopback_pf(hw, true);
7919 		igb_vmdq_set_replication_pf(hw, true);
7920 		igb_vmdq_set_anti_spoofing_pf(hw, true,
7921 					      adapter->vfs_allocated_count);
7922 	} else {
7923 		igb_vmdq_set_loopback_pf(hw, false);
7924 		igb_vmdq_set_replication_pf(hw, false);
7925 	}
7926 }
7927 
7928 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7929 {
7930 	struct e1000_hw *hw = &adapter->hw;
7931 	u32 dmac_thr;
7932 	u16 hwm;
7933 
7934 	if (hw->mac.type > e1000_82580) {
7935 		if (adapter->flags & IGB_FLAG_DMAC) {
7936 			u32 reg;
7937 
7938 			/* force threshold to 0. */
7939 			wr32(E1000_DMCTXTH, 0);
7940 
7941 			/* DMA Coalescing high water mark needs to be greater
7942 			 * than the Rx threshold. Set hwm to PBA - max frame
7943 			 * size in 16B units, capping it at PBA - 6KB.
7944 			 */
7945 			hwm = 64 * pba - adapter->max_frame_size / 16;
7946 			if (hwm < 64 * (pba - 6))
7947 				hwm = 64 * (pba - 6);
7948 			reg = rd32(E1000_FCRTC);
7949 			reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7950 			reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7951 				& E1000_FCRTC_RTH_COAL_MASK);
7952 			wr32(E1000_FCRTC, reg);
7953 
7954 			/* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7955 			 * frame size, capping it at PBA - 10KB.
7956 			 */
7957 			dmac_thr = pba - adapter->max_frame_size / 512;
7958 			if (dmac_thr < pba - 10)
7959 				dmac_thr = pba - 10;
7960 			reg = rd32(E1000_DMACR);
7961 			reg &= ~E1000_DMACR_DMACTHR_MASK;
7962 			reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7963 				& E1000_DMACR_DMACTHR_MASK);
7964 
7965 			/* transition to L0x or L1 if available..*/
7966 			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7967 
7968 			/* watchdog timer= +-1000 usec in 32usec intervals */
7969 			reg |= (1000 >> 5);
7970 
7971 			/* Disable BMC-to-OS Watchdog Enable */
7972 			if (hw->mac.type != e1000_i354)
7973 				reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7974 
7975 			wr32(E1000_DMACR, reg);
7976 
7977 			/* no lower threshold to disable
7978 			 * coalescing(smart fifb)-UTRESH=0
7979 			 */
7980 			wr32(E1000_DMCRTRH, 0);
7981 
7982 			reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7983 
7984 			wr32(E1000_DMCTLX, reg);
7985 
7986 			/* free space in tx packet buffer to wake from
7987 			 * DMA coal
7988 			 */
7989 			wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7990 			     (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7991 
7992 			/* make low power state decision controlled
7993 			 * by DMA coal
7994 			 */
7995 			reg = rd32(E1000_PCIEMISC);
7996 			reg &= ~E1000_PCIEMISC_LX_DECISION;
7997 			wr32(E1000_PCIEMISC, reg);
7998 		} /* endif adapter->dmac is not disabled */
7999 	} else if (hw->mac.type == e1000_82580) {
8000 		u32 reg = rd32(E1000_PCIEMISC);
8001 
8002 		wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8003 		wr32(E1000_DMACR, 0);
8004 	}
8005 }
8006 
8007 /**
8008  *  igb_read_i2c_byte - Reads 8 bit word over I2C
8009  *  @hw: pointer to hardware structure
8010  *  @byte_offset: byte offset to read
8011  *  @dev_addr: device address
8012  *  @data: value read
8013  *
8014  *  Performs byte read operation over I2C interface at
8015  *  a specified device address.
8016  **/
8017 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8018 		      u8 dev_addr, u8 *data)
8019 {
8020 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8021 	struct i2c_client *this_client = adapter->i2c_client;
8022 	s32 status;
8023 	u16 swfw_mask = 0;
8024 
8025 	if (!this_client)
8026 		return E1000_ERR_I2C;
8027 
8028 	swfw_mask = E1000_SWFW_PHY0_SM;
8029 
8030 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8031 		return E1000_ERR_SWFW_SYNC;
8032 
8033 	status = i2c_smbus_read_byte_data(this_client, byte_offset);
8034 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8035 
8036 	if (status < 0)
8037 		return E1000_ERR_I2C;
8038 	else {
8039 		*data = status;
8040 		return 0;
8041 	}
8042 }
8043 
8044 /**
8045  *  igb_write_i2c_byte - Writes 8 bit word over I2C
8046  *  @hw: pointer to hardware structure
8047  *  @byte_offset: byte offset to write
8048  *  @dev_addr: device address
8049  *  @data: value to write
8050  *
8051  *  Performs byte write operation over I2C interface at
8052  *  a specified device address.
8053  **/
8054 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8055 		       u8 dev_addr, u8 data)
8056 {
8057 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8058 	struct i2c_client *this_client = adapter->i2c_client;
8059 	s32 status;
8060 	u16 swfw_mask = E1000_SWFW_PHY0_SM;
8061 
8062 	if (!this_client)
8063 		return E1000_ERR_I2C;
8064 
8065 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8066 		return E1000_ERR_SWFW_SYNC;
8067 	status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8068 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8069 
8070 	if (status)
8071 		return E1000_ERR_I2C;
8072 	else
8073 		return 0;
8074 
8075 }
8076 
8077 int igb_reinit_queues(struct igb_adapter *adapter)
8078 {
8079 	struct net_device *netdev = adapter->netdev;
8080 	struct pci_dev *pdev = adapter->pdev;
8081 	int err = 0;
8082 
8083 	if (netif_running(netdev))
8084 		igb_close(netdev);
8085 
8086 	igb_reset_interrupt_capability(adapter);
8087 
8088 	if (igb_init_interrupt_scheme(adapter, true)) {
8089 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8090 		return -ENOMEM;
8091 	}
8092 
8093 	if (netif_running(netdev))
8094 		err = igb_open(netdev);
8095 
8096 	return err;
8097 }
8098 /* igb_main.c */
8099