1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/etherdevice.h> 35 #ifdef CONFIG_IGB_DCA 36 #include <linux/dca.h> 37 #endif 38 #include <linux/i2c.h> 39 #include "igb.h" 40 41 #define MAJ 5 42 #define MIN 6 43 #define BUILD 0 44 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 45 __stringify(BUILD) "-k" 46 47 enum queue_mode { 48 QUEUE_MODE_STRICT_PRIORITY, 49 QUEUE_MODE_STREAM_RESERVATION, 50 }; 51 52 enum tx_queue_prio { 53 TX_QUEUE_PRIO_HIGH, 54 TX_QUEUE_PRIO_LOW, 55 }; 56 57 char igb_driver_name[] = "igb"; 58 char igb_driver_version[] = DRV_VERSION; 59 static const char igb_driver_string[] = 60 "Intel(R) Gigabit Ethernet Network Driver"; 61 static const char igb_copyright[] = 62 "Copyright (c) 2007-2014 Intel Corporation."; 63 64 static const struct e1000_info *igb_info_tbl[] = { 65 [board_82575] = &e1000_82575_info, 66 }; 67 68 static const struct pci_device_id igb_pci_tbl[] = { 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 104 /* required last entry */ 105 {0, } 106 }; 107 108 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 109 110 static int igb_setup_all_tx_resources(struct igb_adapter *); 111 static int igb_setup_all_rx_resources(struct igb_adapter *); 112 static void igb_free_all_tx_resources(struct igb_adapter *); 113 static void igb_free_all_rx_resources(struct igb_adapter *); 114 static void igb_setup_mrqc(struct igb_adapter *); 115 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 116 static void igb_remove(struct pci_dev *pdev); 117 static int igb_sw_init(struct igb_adapter *); 118 int igb_open(struct net_device *); 119 int igb_close(struct net_device *); 120 static void igb_configure(struct igb_adapter *); 121 static void igb_configure_tx(struct igb_adapter *); 122 static void igb_configure_rx(struct igb_adapter *); 123 static void igb_clean_all_tx_rings(struct igb_adapter *); 124 static void igb_clean_all_rx_rings(struct igb_adapter *); 125 static void igb_clean_tx_ring(struct igb_ring *); 126 static void igb_clean_rx_ring(struct igb_ring *); 127 static void igb_set_rx_mode(struct net_device *); 128 static void igb_update_phy_info(struct timer_list *); 129 static void igb_watchdog(struct timer_list *); 130 static void igb_watchdog_task(struct work_struct *); 131 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 132 static void igb_get_stats64(struct net_device *dev, 133 struct rtnl_link_stats64 *stats); 134 static int igb_change_mtu(struct net_device *, int); 135 static int igb_set_mac(struct net_device *, void *); 136 static void igb_set_uta(struct igb_adapter *adapter, bool set); 137 static irqreturn_t igb_intr(int irq, void *); 138 static irqreturn_t igb_intr_msi(int irq, void *); 139 static irqreturn_t igb_msix_other(int irq, void *); 140 static irqreturn_t igb_msix_ring(int irq, void *); 141 #ifdef CONFIG_IGB_DCA 142 static void igb_update_dca(struct igb_q_vector *); 143 static void igb_setup_dca(struct igb_adapter *); 144 #endif /* CONFIG_IGB_DCA */ 145 static int igb_poll(struct napi_struct *, int); 146 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 147 static int igb_clean_rx_irq(struct igb_q_vector *, int); 148 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 149 static void igb_tx_timeout(struct net_device *); 150 static void igb_reset_task(struct work_struct *); 151 static void igb_vlan_mode(struct net_device *netdev, 152 netdev_features_t features); 153 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 154 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 155 static void igb_restore_vlan(struct igb_adapter *); 156 static void igb_rar_set_index(struct igb_adapter *, u32); 157 static void igb_ping_all_vfs(struct igb_adapter *); 158 static void igb_msg_task(struct igb_adapter *); 159 static void igb_vmm_control(struct igb_adapter *); 160 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 161 static void igb_flush_mac_table(struct igb_adapter *); 162 static int igb_available_rars(struct igb_adapter *, u8); 163 static void igb_set_default_mac_filter(struct igb_adapter *); 164 static int igb_uc_sync(struct net_device *, const unsigned char *); 165 static int igb_uc_unsync(struct net_device *, const unsigned char *); 166 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 168 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 169 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 170 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 171 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 172 bool setting); 173 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 174 bool setting); 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177 static void igb_check_vf_rate_limit(struct igb_adapter *); 178 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 179 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 180 181 #ifdef CONFIG_PCI_IOV 182 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 183 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 184 static int igb_disable_sriov(struct pci_dev *dev); 185 static int igb_pci_disable_sriov(struct pci_dev *dev); 186 #endif 187 188 static int igb_suspend(struct device *); 189 static int igb_resume(struct device *); 190 static int igb_runtime_suspend(struct device *dev); 191 static int igb_runtime_resume(struct device *dev); 192 static int igb_runtime_idle(struct device *dev); 193 static const struct dev_pm_ops igb_pm_ops = { 194 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 195 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 196 igb_runtime_idle) 197 }; 198 static void igb_shutdown(struct pci_dev *); 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 200 #ifdef CONFIG_IGB_DCA 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 202 static struct notifier_block dca_notifier = { 203 .notifier_call = igb_notify_dca, 204 .next = NULL, 205 .priority = 0 206 }; 207 #endif 208 #ifdef CONFIG_PCI_IOV 209 static unsigned int max_vfs; 210 module_param(max_vfs, uint, 0); 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 212 #endif /* CONFIG_PCI_IOV */ 213 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217 static void igb_io_resume(struct pci_dev *); 218 219 static const struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223 }; 224 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227 static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = igb_remove, 232 #ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234 #endif 235 .shutdown = igb_shutdown, 236 .sriov_configure = igb_pci_sriov_configure, 237 .err_handler = &igb_err_handler 238 }; 239 240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 242 MODULE_LICENSE("GPL v2"); 243 MODULE_VERSION(DRV_VERSION); 244 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 246 static int debug = -1; 247 module_param(debug, int, 0); 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 249 250 struct igb_reg_info { 251 u32 ofs; 252 char *name; 253 }; 254 255 static const struct igb_reg_info igb_reg_info_tbl[] = { 256 257 /* General Registers */ 258 {E1000_CTRL, "CTRL"}, 259 {E1000_STATUS, "STATUS"}, 260 {E1000_CTRL_EXT, "CTRL_EXT"}, 261 262 /* Interrupt Registers */ 263 {E1000_ICR, "ICR"}, 264 265 /* RX Registers */ 266 {E1000_RCTL, "RCTL"}, 267 {E1000_RDLEN(0), "RDLEN"}, 268 {E1000_RDH(0), "RDH"}, 269 {E1000_RDT(0), "RDT"}, 270 {E1000_RXDCTL(0), "RXDCTL"}, 271 {E1000_RDBAL(0), "RDBAL"}, 272 {E1000_RDBAH(0), "RDBAH"}, 273 274 /* TX Registers */ 275 {E1000_TCTL, "TCTL"}, 276 {E1000_TDBAL(0), "TDBAL"}, 277 {E1000_TDBAH(0), "TDBAH"}, 278 {E1000_TDLEN(0), "TDLEN"}, 279 {E1000_TDH(0), "TDH"}, 280 {E1000_TDT(0), "TDT"}, 281 {E1000_TXDCTL(0), "TXDCTL"}, 282 {E1000_TDFH, "TDFH"}, 283 {E1000_TDFT, "TDFT"}, 284 {E1000_TDFHS, "TDFHS"}, 285 {E1000_TDFPC, "TDFPC"}, 286 287 /* List Terminator */ 288 {} 289 }; 290 291 /* igb_regdump - register printout routine */ 292 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 293 { 294 int n = 0; 295 char rname[16]; 296 u32 regs[8]; 297 298 switch (reginfo->ofs) { 299 case E1000_RDLEN(0): 300 for (n = 0; n < 4; n++) 301 regs[n] = rd32(E1000_RDLEN(n)); 302 break; 303 case E1000_RDH(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RDH(n)); 306 break; 307 case E1000_RDT(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDT(n)); 310 break; 311 case E1000_RXDCTL(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RXDCTL(n)); 314 break; 315 case E1000_RDBAL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_RDBAL(n)); 318 break; 319 case E1000_RDBAH(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_RDBAH(n)); 322 break; 323 case E1000_TDBAL(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_RDBAL(n)); 326 break; 327 case E1000_TDBAH(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_TDBAH(n)); 330 break; 331 case E1000_TDLEN(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDLEN(n)); 334 break; 335 case E1000_TDH(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TDH(n)); 338 break; 339 case E1000_TDT(0): 340 for (n = 0; n < 4; n++) 341 regs[n] = rd32(E1000_TDT(n)); 342 break; 343 case E1000_TXDCTL(0): 344 for (n = 0; n < 4; n++) 345 regs[n] = rd32(E1000_TXDCTL(n)); 346 break; 347 default: 348 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 349 return; 350 } 351 352 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 353 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 354 regs[2], regs[3]); 355 } 356 357 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 358 static void igb_dump(struct igb_adapter *adapter) 359 { 360 struct net_device *netdev = adapter->netdev; 361 struct e1000_hw *hw = &adapter->hw; 362 struct igb_reg_info *reginfo; 363 struct igb_ring *tx_ring; 364 union e1000_adv_tx_desc *tx_desc; 365 struct my_u0 { u64 a; u64 b; } *u0; 366 struct igb_ring *rx_ring; 367 union e1000_adv_rx_desc *rx_desc; 368 u32 staterr; 369 u16 i, n; 370 371 if (!netif_msg_hw(adapter)) 372 return; 373 374 /* Print netdevice Info */ 375 if (netdev) { 376 dev_info(&adapter->pdev->dev, "Net device Info\n"); 377 pr_info("Device Name state trans_start\n"); 378 pr_info("%-15s %016lX %016lX\n", netdev->name, 379 netdev->state, dev_trans_start(netdev)); 380 } 381 382 /* Print Registers */ 383 dev_info(&adapter->pdev->dev, "Register Dump\n"); 384 pr_info(" Register Name Value\n"); 385 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 386 reginfo->name; reginfo++) { 387 igb_regdump(hw, reginfo); 388 } 389 390 /* Print TX Ring Summary */ 391 if (!netdev || !netif_running(netdev)) 392 goto exit; 393 394 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 395 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 396 for (n = 0; n < adapter->num_tx_queues; n++) { 397 struct igb_tx_buffer *buffer_info; 398 tx_ring = adapter->tx_ring[n]; 399 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 400 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 401 n, tx_ring->next_to_use, tx_ring->next_to_clean, 402 (u64)dma_unmap_addr(buffer_info, dma), 403 dma_unmap_len(buffer_info, len), 404 buffer_info->next_to_watch, 405 (u64)buffer_info->time_stamp); 406 } 407 408 /* Print TX Rings */ 409 if (!netif_msg_tx_done(adapter)) 410 goto rx_ring_summary; 411 412 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 413 414 /* Transmit Descriptor Formats 415 * 416 * Advanced Transmit Descriptor 417 * +--------------------------------------------------------------+ 418 * 0 | Buffer Address [63:0] | 419 * +--------------------------------------------------------------+ 420 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 421 * +--------------------------------------------------------------+ 422 * 63 46 45 40 39 38 36 35 32 31 24 15 0 423 */ 424 425 for (n = 0; n < adapter->num_tx_queues; n++) { 426 tx_ring = adapter->tx_ring[n]; 427 pr_info("------------------------------------\n"); 428 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 429 pr_info("------------------------------------\n"); 430 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 431 432 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 433 const char *next_desc; 434 struct igb_tx_buffer *buffer_info; 435 tx_desc = IGB_TX_DESC(tx_ring, i); 436 buffer_info = &tx_ring->tx_buffer_info[i]; 437 u0 = (struct my_u0 *)tx_desc; 438 if (i == tx_ring->next_to_use && 439 i == tx_ring->next_to_clean) 440 next_desc = " NTC/U"; 441 else if (i == tx_ring->next_to_use) 442 next_desc = " NTU"; 443 else if (i == tx_ring->next_to_clean) 444 next_desc = " NTC"; 445 else 446 next_desc = ""; 447 448 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 449 i, le64_to_cpu(u0->a), 450 le64_to_cpu(u0->b), 451 (u64)dma_unmap_addr(buffer_info, dma), 452 dma_unmap_len(buffer_info, len), 453 buffer_info->next_to_watch, 454 (u64)buffer_info->time_stamp, 455 buffer_info->skb, next_desc); 456 457 if (netif_msg_pktdata(adapter) && buffer_info->skb) 458 print_hex_dump(KERN_INFO, "", 459 DUMP_PREFIX_ADDRESS, 460 16, 1, buffer_info->skb->data, 461 dma_unmap_len(buffer_info, len), 462 true); 463 } 464 } 465 466 /* Print RX Rings Summary */ 467 rx_ring_summary: 468 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 469 pr_info("Queue [NTU] [NTC]\n"); 470 for (n = 0; n < adapter->num_rx_queues; n++) { 471 rx_ring = adapter->rx_ring[n]; 472 pr_info(" %5d %5X %5X\n", 473 n, rx_ring->next_to_use, rx_ring->next_to_clean); 474 } 475 476 /* Print RX Rings */ 477 if (!netif_msg_rx_status(adapter)) 478 goto exit; 479 480 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 481 482 /* Advanced Receive Descriptor (Read) Format 483 * 63 1 0 484 * +-----------------------------------------------------+ 485 * 0 | Packet Buffer Address [63:1] |A0/NSE| 486 * +----------------------------------------------+------+ 487 * 8 | Header Buffer Address [63:1] | DD | 488 * +-----------------------------------------------------+ 489 * 490 * 491 * Advanced Receive Descriptor (Write-Back) Format 492 * 493 * 63 48 47 32 31 30 21 20 17 16 4 3 0 494 * +------------------------------------------------------+ 495 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 496 * | Checksum Ident | | | | Type | Type | 497 * +------------------------------------------------------+ 498 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 499 * +------------------------------------------------------+ 500 * 63 48 47 32 31 20 19 0 501 */ 502 503 for (n = 0; n < adapter->num_rx_queues; n++) { 504 rx_ring = adapter->rx_ring[n]; 505 pr_info("------------------------------------\n"); 506 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 507 pr_info("------------------------------------\n"); 508 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 509 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 510 511 for (i = 0; i < rx_ring->count; i++) { 512 const char *next_desc; 513 struct igb_rx_buffer *buffer_info; 514 buffer_info = &rx_ring->rx_buffer_info[i]; 515 rx_desc = IGB_RX_DESC(rx_ring, i); 516 u0 = (struct my_u0 *)rx_desc; 517 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 518 519 if (i == rx_ring->next_to_use) 520 next_desc = " NTU"; 521 else if (i == rx_ring->next_to_clean) 522 next_desc = " NTC"; 523 else 524 next_desc = ""; 525 526 if (staterr & E1000_RXD_STAT_DD) { 527 /* Descriptor Done */ 528 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 529 "RWB", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 next_desc); 533 } else { 534 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 535 "R ", i, 536 le64_to_cpu(u0->a), 537 le64_to_cpu(u0->b), 538 (u64)buffer_info->dma, 539 next_desc); 540 541 if (netif_msg_pktdata(adapter) && 542 buffer_info->dma && buffer_info->page) { 543 print_hex_dump(KERN_INFO, "", 544 DUMP_PREFIX_ADDRESS, 545 16, 1, 546 page_address(buffer_info->page) + 547 buffer_info->page_offset, 548 igb_rx_bufsz(rx_ring), true); 549 } 550 } 551 } 552 } 553 554 exit: 555 return; 556 } 557 558 /** 559 * igb_get_i2c_data - Reads the I2C SDA data bit 560 * @hw: pointer to hardware structure 561 * @i2cctl: Current value of I2CCTL register 562 * 563 * Returns the I2C data bit value 564 **/ 565 static int igb_get_i2c_data(void *data) 566 { 567 struct igb_adapter *adapter = (struct igb_adapter *)data; 568 struct e1000_hw *hw = &adapter->hw; 569 s32 i2cctl = rd32(E1000_I2CPARAMS); 570 571 return !!(i2cctl & E1000_I2C_DATA_IN); 572 } 573 574 /** 575 * igb_set_i2c_data - Sets the I2C data bit 576 * @data: pointer to hardware structure 577 * @state: I2C data value (0 or 1) to set 578 * 579 * Sets the I2C data bit 580 **/ 581 static void igb_set_i2c_data(void *data, int state) 582 { 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 if (state) 588 i2cctl |= E1000_I2C_DATA_OUT; 589 else 590 i2cctl &= ~E1000_I2C_DATA_OUT; 591 592 i2cctl &= ~E1000_I2C_DATA_OE_N; 593 i2cctl |= E1000_I2C_CLK_OE_N; 594 wr32(E1000_I2CPARAMS, i2cctl); 595 wrfl(); 596 597 } 598 599 /** 600 * igb_set_i2c_clk - Sets the I2C SCL clock 601 * @data: pointer to hardware structure 602 * @state: state to set clock 603 * 604 * Sets the I2C clock line to state 605 **/ 606 static void igb_set_i2c_clk(void *data, int state) 607 { 608 struct igb_adapter *adapter = (struct igb_adapter *)data; 609 struct e1000_hw *hw = &adapter->hw; 610 s32 i2cctl = rd32(E1000_I2CPARAMS); 611 612 if (state) { 613 i2cctl |= E1000_I2C_CLK_OUT; 614 i2cctl &= ~E1000_I2C_CLK_OE_N; 615 } else { 616 i2cctl &= ~E1000_I2C_CLK_OUT; 617 i2cctl &= ~E1000_I2C_CLK_OE_N; 618 } 619 wr32(E1000_I2CPARAMS, i2cctl); 620 wrfl(); 621 } 622 623 /** 624 * igb_get_i2c_clk - Gets the I2C SCL clock state 625 * @data: pointer to hardware structure 626 * 627 * Gets the I2C clock state 628 **/ 629 static int igb_get_i2c_clk(void *data) 630 { 631 struct igb_adapter *adapter = (struct igb_adapter *)data; 632 struct e1000_hw *hw = &adapter->hw; 633 s32 i2cctl = rd32(E1000_I2CPARAMS); 634 635 return !!(i2cctl & E1000_I2C_CLK_IN); 636 } 637 638 static const struct i2c_algo_bit_data igb_i2c_algo = { 639 .setsda = igb_set_i2c_data, 640 .setscl = igb_set_i2c_clk, 641 .getsda = igb_get_i2c_data, 642 .getscl = igb_get_i2c_clk, 643 .udelay = 5, 644 .timeout = 20, 645 }; 646 647 /** 648 * igb_get_hw_dev - return device 649 * @hw: pointer to hardware structure 650 * 651 * used by hardware layer to print debugging information 652 **/ 653 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 654 { 655 struct igb_adapter *adapter = hw->back; 656 return adapter->netdev; 657 } 658 659 /** 660 * igb_init_module - Driver Registration Routine 661 * 662 * igb_init_module is the first routine called when the driver is 663 * loaded. All it does is register with the PCI subsystem. 664 **/ 665 static int __init igb_init_module(void) 666 { 667 int ret; 668 669 pr_info("%s - version %s\n", 670 igb_driver_string, igb_driver_version); 671 pr_info("%s\n", igb_copyright); 672 673 #ifdef CONFIG_IGB_DCA 674 dca_register_notify(&dca_notifier); 675 #endif 676 ret = pci_register_driver(&igb_driver); 677 return ret; 678 } 679 680 module_init(igb_init_module); 681 682 /** 683 * igb_exit_module - Driver Exit Cleanup Routine 684 * 685 * igb_exit_module is called just before the driver is removed 686 * from memory. 687 **/ 688 static void __exit igb_exit_module(void) 689 { 690 #ifdef CONFIG_IGB_DCA 691 dca_unregister_notify(&dca_notifier); 692 #endif 693 pci_unregister_driver(&igb_driver); 694 } 695 696 module_exit(igb_exit_module); 697 698 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 699 /** 700 * igb_cache_ring_register - Descriptor ring to register mapping 701 * @adapter: board private structure to initialize 702 * 703 * Once we know the feature-set enabled for the device, we'll cache 704 * the register offset the descriptor ring is assigned to. 705 **/ 706 static void igb_cache_ring_register(struct igb_adapter *adapter) 707 { 708 int i = 0, j = 0; 709 u32 rbase_offset = adapter->vfs_allocated_count; 710 711 switch (adapter->hw.mac.type) { 712 case e1000_82576: 713 /* The queues are allocated for virtualization such that VF 0 714 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 715 * In order to avoid collision we start at the first free queue 716 * and continue consuming queues in the same sequence 717 */ 718 if (adapter->vfs_allocated_count) { 719 for (; i < adapter->rss_queues; i++) 720 adapter->rx_ring[i]->reg_idx = rbase_offset + 721 Q_IDX_82576(i); 722 } 723 /* Fall through */ 724 case e1000_82575: 725 case e1000_82580: 726 case e1000_i350: 727 case e1000_i354: 728 case e1000_i210: 729 case e1000_i211: 730 /* Fall through */ 731 default: 732 for (; i < adapter->num_rx_queues; i++) 733 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 734 for (; j < adapter->num_tx_queues; j++) 735 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 736 break; 737 } 738 } 739 740 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 741 { 742 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 743 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 744 u32 value = 0; 745 746 if (E1000_REMOVED(hw_addr)) 747 return ~value; 748 749 value = readl(&hw_addr[reg]); 750 751 /* reads should not return all F's */ 752 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 753 struct net_device *netdev = igb->netdev; 754 hw->hw_addr = NULL; 755 netdev_err(netdev, "PCIe link lost\n"); 756 WARN(1, "igb: Failed to read reg 0x%x!\n", reg); 757 } 758 759 return value; 760 } 761 762 /** 763 * igb_write_ivar - configure ivar for given MSI-X vector 764 * @hw: pointer to the HW structure 765 * @msix_vector: vector number we are allocating to a given ring 766 * @index: row index of IVAR register to write within IVAR table 767 * @offset: column offset of in IVAR, should be multiple of 8 768 * 769 * This function is intended to handle the writing of the IVAR register 770 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 771 * each containing an cause allocation for an Rx and Tx ring, and a 772 * variable number of rows depending on the number of queues supported. 773 **/ 774 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 775 int index, int offset) 776 { 777 u32 ivar = array_rd32(E1000_IVAR0, index); 778 779 /* clear any bits that are currently set */ 780 ivar &= ~((u32)0xFF << offset); 781 782 /* write vector and valid bit */ 783 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 784 785 array_wr32(E1000_IVAR0, index, ivar); 786 } 787 788 #define IGB_N0_QUEUE -1 789 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 790 { 791 struct igb_adapter *adapter = q_vector->adapter; 792 struct e1000_hw *hw = &adapter->hw; 793 int rx_queue = IGB_N0_QUEUE; 794 int tx_queue = IGB_N0_QUEUE; 795 u32 msixbm = 0; 796 797 if (q_vector->rx.ring) 798 rx_queue = q_vector->rx.ring->reg_idx; 799 if (q_vector->tx.ring) 800 tx_queue = q_vector->tx.ring->reg_idx; 801 802 switch (hw->mac.type) { 803 case e1000_82575: 804 /* The 82575 assigns vectors using a bitmask, which matches the 805 * bitmask for the EICR/EIMS/EIMC registers. To assign one 806 * or more queues to a vector, we write the appropriate bits 807 * into the MSIXBM register for that vector. 808 */ 809 if (rx_queue > IGB_N0_QUEUE) 810 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 811 if (tx_queue > IGB_N0_QUEUE) 812 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 813 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 814 msixbm |= E1000_EIMS_OTHER; 815 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 816 q_vector->eims_value = msixbm; 817 break; 818 case e1000_82576: 819 /* 82576 uses a table that essentially consists of 2 columns 820 * with 8 rows. The ordering is column-major so we use the 821 * lower 3 bits as the row index, and the 4th bit as the 822 * column offset. 823 */ 824 if (rx_queue > IGB_N0_QUEUE) 825 igb_write_ivar(hw, msix_vector, 826 rx_queue & 0x7, 827 (rx_queue & 0x8) << 1); 828 if (tx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 tx_queue & 0x7, 831 ((tx_queue & 0x8) << 1) + 8); 832 q_vector->eims_value = BIT(msix_vector); 833 break; 834 case e1000_82580: 835 case e1000_i350: 836 case e1000_i354: 837 case e1000_i210: 838 case e1000_i211: 839 /* On 82580 and newer adapters the scheme is similar to 82576 840 * however instead of ordering column-major we have things 841 * ordered row-major. So we traverse the table by using 842 * bit 0 as the column offset, and the remaining bits as the 843 * row index. 844 */ 845 if (rx_queue > IGB_N0_QUEUE) 846 igb_write_ivar(hw, msix_vector, 847 rx_queue >> 1, 848 (rx_queue & 0x1) << 4); 849 if (tx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 tx_queue >> 1, 852 ((tx_queue & 0x1) << 4) + 8); 853 q_vector->eims_value = BIT(msix_vector); 854 break; 855 default: 856 BUG(); 857 break; 858 } 859 860 /* add q_vector eims value to global eims_enable_mask */ 861 adapter->eims_enable_mask |= q_vector->eims_value; 862 863 /* configure q_vector to set itr on first interrupt */ 864 q_vector->set_itr = 1; 865 } 866 867 /** 868 * igb_configure_msix - Configure MSI-X hardware 869 * @adapter: board private structure to initialize 870 * 871 * igb_configure_msix sets up the hardware to properly 872 * generate MSI-X interrupts. 873 **/ 874 static void igb_configure_msix(struct igb_adapter *adapter) 875 { 876 u32 tmp; 877 int i, vector = 0; 878 struct e1000_hw *hw = &adapter->hw; 879 880 adapter->eims_enable_mask = 0; 881 882 /* set vector for other causes, i.e. link changes */ 883 switch (hw->mac.type) { 884 case e1000_82575: 885 tmp = rd32(E1000_CTRL_EXT); 886 /* enable MSI-X PBA support*/ 887 tmp |= E1000_CTRL_EXT_PBA_CLR; 888 889 /* Auto-Mask interrupts upon ICR read. */ 890 tmp |= E1000_CTRL_EXT_EIAME; 891 tmp |= E1000_CTRL_EXT_IRCA; 892 893 wr32(E1000_CTRL_EXT, tmp); 894 895 /* enable msix_other interrupt */ 896 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 897 adapter->eims_other = E1000_EIMS_OTHER; 898 899 break; 900 901 case e1000_82576: 902 case e1000_82580: 903 case e1000_i350: 904 case e1000_i354: 905 case e1000_i210: 906 case e1000_i211: 907 /* Turn on MSI-X capability first, or our settings 908 * won't stick. And it will take days to debug. 909 */ 910 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 911 E1000_GPIE_PBA | E1000_GPIE_EIAME | 912 E1000_GPIE_NSICR); 913 914 /* enable msix_other interrupt */ 915 adapter->eims_other = BIT(vector); 916 tmp = (vector++ | E1000_IVAR_VALID) << 8; 917 918 wr32(E1000_IVAR_MISC, tmp); 919 break; 920 default: 921 /* do nothing, since nothing else supports MSI-X */ 922 break; 923 } /* switch (hw->mac.type) */ 924 925 adapter->eims_enable_mask |= adapter->eims_other; 926 927 for (i = 0; i < adapter->num_q_vectors; i++) 928 igb_assign_vector(adapter->q_vector[i], vector++); 929 930 wrfl(); 931 } 932 933 /** 934 * igb_request_msix - Initialize MSI-X interrupts 935 * @adapter: board private structure to initialize 936 * 937 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 938 * kernel. 939 **/ 940 static int igb_request_msix(struct igb_adapter *adapter) 941 { 942 struct net_device *netdev = adapter->netdev; 943 int i, err = 0, vector = 0, free_vector = 0; 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_other, 0, netdev->name, adapter); 947 if (err) 948 goto err_out; 949 950 for (i = 0; i < adapter->num_q_vectors; i++) { 951 struct igb_q_vector *q_vector = adapter->q_vector[i]; 952 953 vector++; 954 955 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 956 957 if (q_vector->rx.ring && q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 959 q_vector->rx.ring->queue_index); 960 else if (q_vector->tx.ring) 961 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 962 q_vector->tx.ring->queue_index); 963 else if (q_vector->rx.ring) 964 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 965 q_vector->rx.ring->queue_index); 966 else 967 sprintf(q_vector->name, "%s-unused", netdev->name); 968 969 err = request_irq(adapter->msix_entries[vector].vector, 970 igb_msix_ring, 0, q_vector->name, 971 q_vector); 972 if (err) 973 goto err_free; 974 } 975 976 igb_configure_msix(adapter); 977 return 0; 978 979 err_free: 980 /* free already assigned IRQs */ 981 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 982 983 vector--; 984 for (i = 0; i < vector; i++) { 985 free_irq(adapter->msix_entries[free_vector++].vector, 986 adapter->q_vector[i]); 987 } 988 err_out: 989 return err; 990 } 991 992 /** 993 * igb_free_q_vector - Free memory allocated for specific interrupt vector 994 * @adapter: board private structure to initialize 995 * @v_idx: Index of vector to be freed 996 * 997 * This function frees the memory allocated to the q_vector. 998 **/ 999 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 adapter->q_vector[v_idx] = NULL; 1004 1005 /* igb_get_stats64() might access the rings on this vector, 1006 * we must wait a grace period before freeing it. 1007 */ 1008 if (q_vector) 1009 kfree_rcu(q_vector, rcu); 1010 } 1011 1012 /** 1013 * igb_reset_q_vector - Reset config for interrupt vector 1014 * @adapter: board private structure to initialize 1015 * @v_idx: Index of vector to be reset 1016 * 1017 * If NAPI is enabled it will delete any references to the 1018 * NAPI struct. This is preparation for igb_free_q_vector. 1019 **/ 1020 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1021 { 1022 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1023 1024 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1025 * allocated. So, q_vector is NULL so we should stop here. 1026 */ 1027 if (!q_vector) 1028 return; 1029 1030 if (q_vector->tx.ring) 1031 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1032 1033 if (q_vector->rx.ring) 1034 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1035 1036 netif_napi_del(&q_vector->napi); 1037 1038 } 1039 1040 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1045 pci_disable_msix(adapter->pdev); 1046 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1047 pci_disable_msi(adapter->pdev); 1048 1049 while (v_idx--) 1050 igb_reset_q_vector(adapter, v_idx); 1051 } 1052 1053 /** 1054 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1055 * @adapter: board private structure to initialize 1056 * 1057 * This function frees the memory allocated to the q_vectors. In addition if 1058 * NAPI is enabled it will delete any references to the NAPI struct prior 1059 * to freeing the q_vector. 1060 **/ 1061 static void igb_free_q_vectors(struct igb_adapter *adapter) 1062 { 1063 int v_idx = adapter->num_q_vectors; 1064 1065 adapter->num_tx_queues = 0; 1066 adapter->num_rx_queues = 0; 1067 adapter->num_q_vectors = 0; 1068 1069 while (v_idx--) { 1070 igb_reset_q_vector(adapter, v_idx); 1071 igb_free_q_vector(adapter, v_idx); 1072 } 1073 } 1074 1075 /** 1076 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1077 * @adapter: board private structure to initialize 1078 * 1079 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1080 * MSI-X interrupts allocated. 1081 */ 1082 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1083 { 1084 igb_free_q_vectors(adapter); 1085 igb_reset_interrupt_capability(adapter); 1086 } 1087 1088 /** 1089 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1090 * @adapter: board private structure to initialize 1091 * @msix: boolean value of MSIX capability 1092 * 1093 * Attempt to configure interrupts using the best available 1094 * capabilities of the hardware and kernel. 1095 **/ 1096 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1097 { 1098 int err; 1099 int numvecs, i; 1100 1101 if (!msix) 1102 goto msi_only; 1103 adapter->flags |= IGB_FLAG_HAS_MSIX; 1104 1105 /* Number of supported queues. */ 1106 adapter->num_rx_queues = adapter->rss_queues; 1107 if (adapter->vfs_allocated_count) 1108 adapter->num_tx_queues = 1; 1109 else 1110 adapter->num_tx_queues = adapter->rss_queues; 1111 1112 /* start with one vector for every Rx queue */ 1113 numvecs = adapter->num_rx_queues; 1114 1115 /* if Tx handler is separate add 1 for every Tx queue */ 1116 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1117 numvecs += adapter->num_tx_queues; 1118 1119 /* store the number of vectors reserved for queues */ 1120 adapter->num_q_vectors = numvecs; 1121 1122 /* add 1 vector for link status interrupts */ 1123 numvecs++; 1124 for (i = 0; i < numvecs; i++) 1125 adapter->msix_entries[i].entry = i; 1126 1127 err = pci_enable_msix_range(adapter->pdev, 1128 adapter->msix_entries, 1129 numvecs, 1130 numvecs); 1131 if (err > 0) 1132 return; 1133 1134 igb_reset_interrupt_capability(adapter); 1135 1136 /* If we can't do MSI-X, try MSI */ 1137 msi_only: 1138 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1139 #ifdef CONFIG_PCI_IOV 1140 /* disable SR-IOV for non MSI-X configurations */ 1141 if (adapter->vf_data) { 1142 struct e1000_hw *hw = &adapter->hw; 1143 /* disable iov and allow time for transactions to clear */ 1144 pci_disable_sriov(adapter->pdev); 1145 msleep(500); 1146 1147 kfree(adapter->vf_mac_list); 1148 adapter->vf_mac_list = NULL; 1149 kfree(adapter->vf_data); 1150 adapter->vf_data = NULL; 1151 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1152 wrfl(); 1153 msleep(100); 1154 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1155 } 1156 #endif 1157 adapter->vfs_allocated_count = 0; 1158 adapter->rss_queues = 1; 1159 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1160 adapter->num_rx_queues = 1; 1161 adapter->num_tx_queues = 1; 1162 adapter->num_q_vectors = 1; 1163 if (!pci_enable_msi(adapter->pdev)) 1164 adapter->flags |= IGB_FLAG_HAS_MSI; 1165 } 1166 1167 static void igb_add_ring(struct igb_ring *ring, 1168 struct igb_ring_container *head) 1169 { 1170 head->ring = ring; 1171 head->count++; 1172 } 1173 1174 /** 1175 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1176 * @adapter: board private structure to initialize 1177 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1178 * @v_idx: index of vector in adapter struct 1179 * @txr_count: total number of Tx rings to allocate 1180 * @txr_idx: index of first Tx ring to allocate 1181 * @rxr_count: total number of Rx rings to allocate 1182 * @rxr_idx: index of first Rx ring to allocate 1183 * 1184 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1185 **/ 1186 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1187 int v_count, int v_idx, 1188 int txr_count, int txr_idx, 1189 int rxr_count, int rxr_idx) 1190 { 1191 struct igb_q_vector *q_vector; 1192 struct igb_ring *ring; 1193 int ring_count; 1194 size_t size; 1195 1196 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1197 if (txr_count > 1 || rxr_count > 1) 1198 return -ENOMEM; 1199 1200 ring_count = txr_count + rxr_count; 1201 size = struct_size(q_vector, ring, ring_count); 1202 1203 /* allocate q_vector and rings */ 1204 q_vector = adapter->q_vector[v_idx]; 1205 if (!q_vector) { 1206 q_vector = kzalloc(size, GFP_KERNEL); 1207 } else if (size > ksize(q_vector)) { 1208 kfree_rcu(q_vector, rcu); 1209 q_vector = kzalloc(size, GFP_KERNEL); 1210 } else { 1211 memset(q_vector, 0, size); 1212 } 1213 if (!q_vector) 1214 return -ENOMEM; 1215 1216 /* initialize NAPI */ 1217 netif_napi_add(adapter->netdev, &q_vector->napi, 1218 igb_poll, 64); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct igb_ring *ring = adapter->tx_ring[queue]; 1690 struct net_device *netdev = adapter->netdev; 1691 struct e1000_hw *hw = &adapter->hw; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 1698 /* If any of the Qav features is enabled, configure queues as SR and 1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1700 * as SP. 1701 */ 1702 if (ring->cbs_enable || ring->launchtime_enable) { 1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1705 } else { 1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1708 } 1709 1710 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1711 if (ring->cbs_enable || queue == 0) { 1712 /* i210 does not allow the queue 0 to be in the Strict 1713 * Priority mode while the Qav mode is enabled, so, 1714 * instead of disabling strict priority mode, we give 1715 * queue 0 the maximum of credits possible. 1716 * 1717 * See section 8.12.19 of the i210 datasheet, "Note: 1718 * Queue0 QueueMode must be set to 1b when 1719 * TransmitMode is set to Qav." 1720 */ 1721 if (queue == 0 && !ring->cbs_enable) { 1722 /* max "linkspeed" idleslope in kbps */ 1723 ring->idleslope = 1000000; 1724 ring->hicredit = ETH_FRAME_LEN; 1725 } 1726 1727 /* Always set data transfer arbitration to credit-based 1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1729 * the queues. 1730 */ 1731 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1733 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1734 1735 /* According to i210 datasheet section 7.2.7.7, we should set 1736 * the 'idleSlope' field from TQAVCC register following the 1737 * equation: 1738 * 1739 * For 100 Mbps link speed: 1740 * 1741 * value = BW * 0x7735 * 0.2 (E1) 1742 * 1743 * For 1000Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 2 (E2) 1746 * 1747 * E1 and E2 can be merged into one equation as shown below. 1748 * Note that 'link-speed' is in Mbps. 1749 * 1750 * value = BW * 0x7735 * 2 * link-speed 1751 * -------------- (E3) 1752 * 1000 1753 * 1754 * 'BW' is the percentage bandwidth out of full link speed 1755 * which can be found with the following equation. Note that 1756 * idleSlope here is the parameter from this function which 1757 * is in kbps. 1758 * 1759 * BW = idleSlope 1760 * ----------------- (E4) 1761 * link-speed * 1000 1762 * 1763 * That said, we can come up with a generic equation to 1764 * calculate the value we should set it TQAVCC register by 1765 * replacing 'BW' in E3 by E4. The resulting equation is: 1766 * 1767 * value = idleSlope * 0x7735 * 2 * link-speed 1768 * ----------------- -------------- (E5) 1769 * link-speed * 1000 1000 1770 * 1771 * 'link-speed' is present in both sides of the fraction so 1772 * it is canceled out. The final equation is the following: 1773 * 1774 * value = idleSlope * 61034 1775 * ----------------- (E6) 1776 * 1000000 1777 * 1778 * NOTE: For i210, given the above, we can see that idleslope 1779 * is represented in 16.38431 kbps units by the value at 1780 * the TQAVCC register (1Gbps / 61034), which reduces 1781 * the granularity for idleslope increments. 1782 * For instance, if you want to configure a 2576kbps 1783 * idleslope, the value to be written on the register 1784 * would have to be 157.23. If rounded down, you end 1785 * up with less bandwidth available than originally 1786 * required (~2572 kbps). If rounded up, you end up 1787 * with a higher bandwidth (~2589 kbps). Below the 1788 * approach we take is to always round up the 1789 * calculated value, so the resulting bandwidth might 1790 * be slightly higher for some configurations. 1791 */ 1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1793 1794 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1796 tqavcc |= value; 1797 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1798 1799 wr32(E1000_I210_TQAVHC(queue), 1800 0x80000000 + ring->hicredit * 0x7735); 1801 } else { 1802 1803 /* Set idleSlope to zero. */ 1804 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1806 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1807 1808 /* Set hiCredit to zero. */ 1809 wr32(E1000_I210_TQAVHC(queue), 0); 1810 1811 /* If CBS is not enabled for any queues anymore, then return to 1812 * the default state of Data Transmission Arbitration on 1813 * TQAVCTRL. 1814 */ 1815 if (!is_any_cbs_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } 1820 } 1821 1822 /* If LaunchTime is enabled, set DataTranTIM. */ 1823 if (ring->launchtime_enable) { 1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1825 * for any of the SR queues, and configure fetchtime delta. 1826 * XXX NOTE: 1827 * - LaunchTime will be enabled for all SR queues. 1828 * - A fixed offset can be added relative to the launch 1829 * time of all packets if configured at reg LAUNCH_OS0. 1830 * We are keeping it as 0 for now (default value). 1831 */ 1832 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1834 E1000_TQAVCTRL_FETCHTIME_DELTA; 1835 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1836 } else { 1837 /* If Launchtime is not enabled for any SR queues anymore, 1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1839 * effectively disabling Launchtime. 1840 */ 1841 if (!is_any_txtime_enabled(adapter)) { 1842 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1845 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1846 } 1847 } 1848 1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1850 * CBS are not configurable by software so we don't do any 'controller 1851 * configuration' in respect to these parameters. 1852 */ 1853 1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1855 ring->cbs_enable ? "enabled" : "disabled", 1856 ring->launchtime_enable ? "enabled" : "disabled", 1857 queue, 1858 ring->idleslope, ring->sendslope, 1859 ring->hicredit, ring->locredit); 1860 } 1861 1862 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1863 bool enable) 1864 { 1865 struct igb_ring *ring; 1866 1867 if (queue < 0 || queue > adapter->num_tx_queues) 1868 return -EINVAL; 1869 1870 ring = adapter->tx_ring[queue]; 1871 ring->launchtime_enable = enable; 1872 1873 return 0; 1874 } 1875 1876 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1877 bool enable, int idleslope, int sendslope, 1878 int hicredit, int locredit) 1879 { 1880 struct igb_ring *ring; 1881 1882 if (queue < 0 || queue > adapter->num_tx_queues) 1883 return -EINVAL; 1884 1885 ring = adapter->tx_ring[queue]; 1886 1887 ring->cbs_enable = enable; 1888 ring->idleslope = idleslope; 1889 ring->sendslope = sendslope; 1890 ring->hicredit = hicredit; 1891 ring->locredit = locredit; 1892 1893 return 0; 1894 } 1895 1896 /** 1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1898 * @adapter: pointer to adapter struct 1899 * 1900 * Configure TQAVCTRL register switching the controller's Tx mode 1901 * if FQTSS mode is enabled or disabled. Additionally, will issue 1902 * a call to igb_config_tx_modes() per queue so any previously saved 1903 * Tx parameters are applied. 1904 **/ 1905 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1906 { 1907 struct net_device *netdev = adapter->netdev; 1908 struct e1000_hw *hw = &adapter->hw; 1909 u32 val; 1910 1911 /* Only i210 controller supports changing the transmission mode. */ 1912 if (hw->mac.type != e1000_i210) 1913 return; 1914 1915 if (is_fqtss_enabled(adapter)) { 1916 int i, max_queue; 1917 1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1920 * so SP queues wait for SR ones. 1921 */ 1922 val = rd32(E1000_I210_TQAVCTRL); 1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1925 wr32(E1000_I210_TQAVCTRL, val); 1926 1927 /* Configure Tx and Rx packet buffers sizes as described in 1928 * i210 datasheet section 7.2.7.7. 1929 */ 1930 val = rd32(E1000_TXPBS); 1931 val &= ~I210_TXPBSIZE_MASK; 1932 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1933 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1934 wr32(E1000_TXPBS, val); 1935 1936 val = rd32(E1000_RXPBS); 1937 val &= ~I210_RXPBSIZE_MASK; 1938 val |= I210_RXPBSIZE_PB_30KB; 1939 wr32(E1000_RXPBS, val); 1940 1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1942 * register should not exceed the buffer size programmed in 1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1944 * so according to the datasheet we should set MAX_TPKT_SIZE to 1945 * 4kB / 64. 1946 * 1947 * However, when we do so, no frame from queue 2 and 3 are 1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1949 * or _equal_ to the buffer size programmed in TXPBS. For this 1950 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1951 */ 1952 val = (4096 - 1) / 64; 1953 wr32(E1000_I210_DTXMXPKTSZ, val); 1954 1955 /* Since FQTSS mode is enabled, apply any CBS configuration 1956 * previously set. If no previous CBS configuration has been 1957 * done, then the initial configuration is applied, which means 1958 * CBS is disabled. 1959 */ 1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1962 1963 for (i = 0; i < max_queue; i++) { 1964 igb_config_tx_modes(adapter, i); 1965 } 1966 } else { 1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1970 1971 val = rd32(E1000_I210_TQAVCTRL); 1972 /* According to Section 8.12.21, the other flags we've set when 1973 * enabling FQTSS are not relevant when disabling FQTSS so we 1974 * don't set they here. 1975 */ 1976 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1977 wr32(E1000_I210_TQAVCTRL, val); 1978 } 1979 1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1981 "enabled" : "disabled"); 1982 } 1983 1984 /** 1985 * igb_configure - configure the hardware for RX and TX 1986 * @adapter: private board structure 1987 **/ 1988 static void igb_configure(struct igb_adapter *adapter) 1989 { 1990 struct net_device *netdev = adapter->netdev; 1991 int i; 1992 1993 igb_get_hw_control(adapter); 1994 igb_set_rx_mode(netdev); 1995 igb_setup_tx_mode(adapter); 1996 1997 igb_restore_vlan(adapter); 1998 1999 igb_setup_tctl(adapter); 2000 igb_setup_mrqc(adapter); 2001 igb_setup_rctl(adapter); 2002 2003 igb_nfc_filter_restore(adapter); 2004 igb_configure_tx(adapter); 2005 igb_configure_rx(adapter); 2006 2007 igb_rx_fifo_flush_82575(&adapter->hw); 2008 2009 /* call igb_desc_unused which always leaves 2010 * at least 1 descriptor unused to make sure 2011 * next_to_use != next_to_clean 2012 */ 2013 for (i = 0; i < adapter->num_rx_queues; i++) { 2014 struct igb_ring *ring = adapter->rx_ring[i]; 2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2016 } 2017 } 2018 2019 /** 2020 * igb_power_up_link - Power up the phy/serdes link 2021 * @adapter: address of board private structure 2022 **/ 2023 void igb_power_up_link(struct igb_adapter *adapter) 2024 { 2025 igb_reset_phy(&adapter->hw); 2026 2027 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2028 igb_power_up_phy_copper(&adapter->hw); 2029 else 2030 igb_power_up_serdes_link_82575(&adapter->hw); 2031 2032 igb_setup_link(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_power_down_link - Power down the phy/serdes link 2037 * @adapter: address of board private structure 2038 */ 2039 static void igb_power_down_link(struct igb_adapter *adapter) 2040 { 2041 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2042 igb_power_down_phy_copper_82575(&adapter->hw); 2043 else 2044 igb_shutdown_serdes_link_82575(&adapter->hw); 2045 } 2046 2047 /** 2048 * Detect and switch function for Media Auto Sense 2049 * @adapter: address of the board private structure 2050 **/ 2051 static void igb_check_swap_media(struct igb_adapter *adapter) 2052 { 2053 struct e1000_hw *hw = &adapter->hw; 2054 u32 ctrl_ext, connsw; 2055 bool swap_now = false; 2056 2057 ctrl_ext = rd32(E1000_CTRL_EXT); 2058 connsw = rd32(E1000_CONNSW); 2059 2060 /* need to live swap if current media is copper and we have fiber/serdes 2061 * to go to. 2062 */ 2063 2064 if ((hw->phy.media_type == e1000_media_type_copper) && 2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2066 swap_now = true; 2067 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 2068 /* copper signal takes time to appear */ 2069 if (adapter->copper_tries < 4) { 2070 adapter->copper_tries++; 2071 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2072 wr32(E1000_CONNSW, connsw); 2073 return; 2074 } else { 2075 adapter->copper_tries = 0; 2076 if ((connsw & E1000_CONNSW_PHYSD) && 2077 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2078 swap_now = true; 2079 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2080 wr32(E1000_CONNSW, connsw); 2081 } 2082 } 2083 } 2084 2085 if (!swap_now) 2086 return; 2087 2088 switch (hw->phy.media_type) { 2089 case e1000_media_type_copper: 2090 netdev_info(adapter->netdev, 2091 "MAS: changing media to fiber/serdes\n"); 2092 ctrl_ext |= 2093 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2094 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2095 adapter->copper_tries = 0; 2096 break; 2097 case e1000_media_type_internal_serdes: 2098 case e1000_media_type_fiber: 2099 netdev_info(adapter->netdev, 2100 "MAS: changing media to copper\n"); 2101 ctrl_ext &= 2102 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2103 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2104 break; 2105 default: 2106 /* shouldn't get here during regular operation */ 2107 netdev_err(adapter->netdev, 2108 "AMS: Invalid media type found, returning\n"); 2109 break; 2110 } 2111 wr32(E1000_CTRL_EXT, ctrl_ext); 2112 } 2113 2114 /** 2115 * igb_up - Open the interface and prepare it to handle traffic 2116 * @adapter: board private structure 2117 **/ 2118 int igb_up(struct igb_adapter *adapter) 2119 { 2120 struct e1000_hw *hw = &adapter->hw; 2121 int i; 2122 2123 /* hardware has been reset, we need to reload some things */ 2124 igb_configure(adapter); 2125 2126 clear_bit(__IGB_DOWN, &adapter->state); 2127 2128 for (i = 0; i < adapter->num_q_vectors; i++) 2129 napi_enable(&(adapter->q_vector[i]->napi)); 2130 2131 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2132 igb_configure_msix(adapter); 2133 else 2134 igb_assign_vector(adapter->q_vector[0], 0); 2135 2136 /* Clear any pending interrupts. */ 2137 rd32(E1000_TSICR); 2138 rd32(E1000_ICR); 2139 igb_irq_enable(adapter); 2140 2141 /* notify VFs that reset has been completed */ 2142 if (adapter->vfs_allocated_count) { 2143 u32 reg_data = rd32(E1000_CTRL_EXT); 2144 2145 reg_data |= E1000_CTRL_EXT_PFRSTD; 2146 wr32(E1000_CTRL_EXT, reg_data); 2147 } 2148 2149 netif_tx_start_all_queues(adapter->netdev); 2150 2151 /* start the watchdog. */ 2152 hw->mac.get_link_status = 1; 2153 schedule_work(&adapter->watchdog_task); 2154 2155 if ((adapter->flags & IGB_FLAG_EEE) && 2156 (!hw->dev_spec._82575.eee_disable)) 2157 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2158 2159 return 0; 2160 } 2161 2162 void igb_down(struct igb_adapter *adapter) 2163 { 2164 struct net_device *netdev = adapter->netdev; 2165 struct e1000_hw *hw = &adapter->hw; 2166 u32 tctl, rctl; 2167 int i; 2168 2169 /* signal that we're down so the interrupt handler does not 2170 * reschedule our watchdog timer 2171 */ 2172 set_bit(__IGB_DOWN, &adapter->state); 2173 2174 /* disable receives in the hardware */ 2175 rctl = rd32(E1000_RCTL); 2176 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2177 /* flush and sleep below */ 2178 2179 igb_nfc_filter_exit(adapter); 2180 2181 netif_carrier_off(netdev); 2182 netif_tx_stop_all_queues(netdev); 2183 2184 /* disable transmits in the hardware */ 2185 tctl = rd32(E1000_TCTL); 2186 tctl &= ~E1000_TCTL_EN; 2187 wr32(E1000_TCTL, tctl); 2188 /* flush both disables and wait for them to finish */ 2189 wrfl(); 2190 usleep_range(10000, 11000); 2191 2192 igb_irq_disable(adapter); 2193 2194 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2195 2196 for (i = 0; i < adapter->num_q_vectors; i++) { 2197 if (adapter->q_vector[i]) { 2198 napi_synchronize(&adapter->q_vector[i]->napi); 2199 napi_disable(&adapter->q_vector[i]->napi); 2200 } 2201 } 2202 2203 del_timer_sync(&adapter->watchdog_timer); 2204 del_timer_sync(&adapter->phy_info_timer); 2205 2206 /* record the stats before reset*/ 2207 spin_lock(&adapter->stats64_lock); 2208 igb_update_stats(adapter); 2209 spin_unlock(&adapter->stats64_lock); 2210 2211 adapter->link_speed = 0; 2212 adapter->link_duplex = 0; 2213 2214 if (!pci_channel_offline(adapter->pdev)) 2215 igb_reset(adapter); 2216 2217 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2218 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2219 2220 igb_clean_all_tx_rings(adapter); 2221 igb_clean_all_rx_rings(adapter); 2222 #ifdef CONFIG_IGB_DCA 2223 2224 /* since we reset the hardware DCA settings were cleared */ 2225 igb_setup_dca(adapter); 2226 #endif 2227 } 2228 2229 void igb_reinit_locked(struct igb_adapter *adapter) 2230 { 2231 WARN_ON(in_interrupt()); 2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2233 usleep_range(1000, 2000); 2234 igb_down(adapter); 2235 igb_up(adapter); 2236 clear_bit(__IGB_RESETTING, &adapter->state); 2237 } 2238 2239 /** igb_enable_mas - Media Autosense re-enable after swap 2240 * 2241 * @adapter: adapter struct 2242 **/ 2243 static void igb_enable_mas(struct igb_adapter *adapter) 2244 { 2245 struct e1000_hw *hw = &adapter->hw; 2246 u32 connsw = rd32(E1000_CONNSW); 2247 2248 /* configure for SerDes media detect */ 2249 if ((hw->phy.media_type == e1000_media_type_copper) && 2250 (!(connsw & E1000_CONNSW_SERDESD))) { 2251 connsw |= E1000_CONNSW_ENRGSRC; 2252 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2253 wr32(E1000_CONNSW, connsw); 2254 wrfl(); 2255 } 2256 } 2257 2258 void igb_reset(struct igb_adapter *adapter) 2259 { 2260 struct pci_dev *pdev = adapter->pdev; 2261 struct e1000_hw *hw = &adapter->hw; 2262 struct e1000_mac_info *mac = &hw->mac; 2263 struct e1000_fc_info *fc = &hw->fc; 2264 u32 pba, hwm; 2265 2266 /* Repartition Pba for greater than 9k mtu 2267 * To take effect CTRL.RST is required. 2268 */ 2269 switch (mac->type) { 2270 case e1000_i350: 2271 case e1000_i354: 2272 case e1000_82580: 2273 pba = rd32(E1000_RXPBS); 2274 pba = igb_rxpbs_adjust_82580(pba); 2275 break; 2276 case e1000_82576: 2277 pba = rd32(E1000_RXPBS); 2278 pba &= E1000_RXPBS_SIZE_MASK_82576; 2279 break; 2280 case e1000_82575: 2281 case e1000_i210: 2282 case e1000_i211: 2283 default: 2284 pba = E1000_PBA_34K; 2285 break; 2286 } 2287 2288 if (mac->type == e1000_82575) { 2289 u32 min_rx_space, min_tx_space, needed_tx_space; 2290 2291 /* write Rx PBA so that hardware can report correct Tx PBA */ 2292 wr32(E1000_PBA, pba); 2293 2294 /* To maintain wire speed transmits, the Tx FIFO should be 2295 * large enough to accommodate two full transmit packets, 2296 * rounded up to the next 1KB and expressed in KB. Likewise, 2297 * the Rx FIFO should be large enough to accommodate at least 2298 * one full receive packet and is similarly rounded up and 2299 * expressed in KB. 2300 */ 2301 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2302 2303 /* The Tx FIFO also stores 16 bytes of information about the Tx 2304 * but don't include Ethernet FCS because hardware appends it. 2305 * We only need to round down to the nearest 512 byte block 2306 * count since the value we care about is 2 frames, not 1. 2307 */ 2308 min_tx_space = adapter->max_frame_size; 2309 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2310 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2311 2312 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2313 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2314 2315 /* If current Tx allocation is less than the min Tx FIFO size, 2316 * and the min Tx FIFO size is less than the current Rx FIFO 2317 * allocation, take space away from current Rx allocation. 2318 */ 2319 if (needed_tx_space < pba) { 2320 pba -= needed_tx_space; 2321 2322 /* if short on Rx space, Rx wins and must trump Tx 2323 * adjustment 2324 */ 2325 if (pba < min_rx_space) 2326 pba = min_rx_space; 2327 } 2328 2329 /* adjust PBA for jumbo frames */ 2330 wr32(E1000_PBA, pba); 2331 } 2332 2333 /* flow control settings 2334 * The high water mark must be low enough to fit one full frame 2335 * after transmitting the pause frame. As such we must have enough 2336 * space to allow for us to complete our current transmit and then 2337 * receive the frame that is in progress from the link partner. 2338 * Set it to: 2339 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2340 */ 2341 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2342 2343 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2344 fc->low_water = fc->high_water - 16; 2345 fc->pause_time = 0xFFFF; 2346 fc->send_xon = 1; 2347 fc->current_mode = fc->requested_mode; 2348 2349 /* disable receive for all VFs and wait one second */ 2350 if (adapter->vfs_allocated_count) { 2351 int i; 2352 2353 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2354 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2355 2356 /* ping all the active vfs to let them know we are going down */ 2357 igb_ping_all_vfs(adapter); 2358 2359 /* disable transmits and receives */ 2360 wr32(E1000_VFRE, 0); 2361 wr32(E1000_VFTE, 0); 2362 } 2363 2364 /* Allow time for pending master requests to run */ 2365 hw->mac.ops.reset_hw(hw); 2366 wr32(E1000_WUC, 0); 2367 2368 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2369 /* need to resetup here after media swap */ 2370 adapter->ei.get_invariants(hw); 2371 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2372 } 2373 if ((mac->type == e1000_82575) && 2374 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2375 igb_enable_mas(adapter); 2376 } 2377 if (hw->mac.ops.init_hw(hw)) 2378 dev_err(&pdev->dev, "Hardware Error\n"); 2379 2380 /* RAR registers were cleared during init_hw, clear mac table */ 2381 igb_flush_mac_table(adapter); 2382 __dev_uc_unsync(adapter->netdev, NULL); 2383 2384 /* Recover default RAR entry */ 2385 igb_set_default_mac_filter(adapter); 2386 2387 /* Flow control settings reset on hardware reset, so guarantee flow 2388 * control is off when forcing speed. 2389 */ 2390 if (!hw->mac.autoneg) 2391 igb_force_mac_fc(hw); 2392 2393 igb_init_dmac(adapter, pba); 2394 #ifdef CONFIG_IGB_HWMON 2395 /* Re-initialize the thermal sensor on i350 devices. */ 2396 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2397 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2398 /* If present, re-initialize the external thermal sensor 2399 * interface. 2400 */ 2401 if (adapter->ets) 2402 mac->ops.init_thermal_sensor_thresh(hw); 2403 } 2404 } 2405 #endif 2406 /* Re-establish EEE setting */ 2407 if (hw->phy.media_type == e1000_media_type_copper) { 2408 switch (mac->type) { 2409 case e1000_i350: 2410 case e1000_i210: 2411 case e1000_i211: 2412 igb_set_eee_i350(hw, true, true); 2413 break; 2414 case e1000_i354: 2415 igb_set_eee_i354(hw, true, true); 2416 break; 2417 default: 2418 break; 2419 } 2420 } 2421 if (!netif_running(adapter->netdev)) 2422 igb_power_down_link(adapter); 2423 2424 igb_update_mng_vlan(adapter); 2425 2426 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2427 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2428 2429 /* Re-enable PTP, where applicable. */ 2430 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2431 igb_ptp_reset(adapter); 2432 2433 igb_get_phy_info(hw); 2434 } 2435 2436 static netdev_features_t igb_fix_features(struct net_device *netdev, 2437 netdev_features_t features) 2438 { 2439 /* Since there is no support for separate Rx/Tx vlan accel 2440 * enable/disable make sure Tx flag is always in same state as Rx. 2441 */ 2442 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2443 features |= NETIF_F_HW_VLAN_CTAG_TX; 2444 else 2445 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2446 2447 return features; 2448 } 2449 2450 static int igb_set_features(struct net_device *netdev, 2451 netdev_features_t features) 2452 { 2453 netdev_features_t changed = netdev->features ^ features; 2454 struct igb_adapter *adapter = netdev_priv(netdev); 2455 2456 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2457 igb_vlan_mode(netdev, features); 2458 2459 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2460 return 0; 2461 2462 if (!(features & NETIF_F_NTUPLE)) { 2463 struct hlist_node *node2; 2464 struct igb_nfc_filter *rule; 2465 2466 spin_lock(&adapter->nfc_lock); 2467 hlist_for_each_entry_safe(rule, node2, 2468 &adapter->nfc_filter_list, nfc_node) { 2469 igb_erase_filter(adapter, rule); 2470 hlist_del(&rule->nfc_node); 2471 kfree(rule); 2472 } 2473 spin_unlock(&adapter->nfc_lock); 2474 adapter->nfc_filter_count = 0; 2475 } 2476 2477 netdev->features = features; 2478 2479 if (netif_running(netdev)) 2480 igb_reinit_locked(adapter); 2481 else 2482 igb_reset(adapter); 2483 2484 return 1; 2485 } 2486 2487 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2488 struct net_device *dev, 2489 const unsigned char *addr, u16 vid, 2490 u16 flags, 2491 struct netlink_ext_ack *extack) 2492 { 2493 /* guarantee we can provide a unique filter for the unicast address */ 2494 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2495 struct igb_adapter *adapter = netdev_priv(dev); 2496 int vfn = adapter->vfs_allocated_count; 2497 2498 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2499 return -ENOMEM; 2500 } 2501 2502 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2503 } 2504 2505 #define IGB_MAX_MAC_HDR_LEN 127 2506 #define IGB_MAX_NETWORK_HDR_LEN 511 2507 2508 static netdev_features_t 2509 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2510 netdev_features_t features) 2511 { 2512 unsigned int network_hdr_len, mac_hdr_len; 2513 2514 /* Make certain the headers can be described by a context descriptor */ 2515 mac_hdr_len = skb_network_header(skb) - skb->data; 2516 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2517 return features & ~(NETIF_F_HW_CSUM | 2518 NETIF_F_SCTP_CRC | 2519 NETIF_F_HW_VLAN_CTAG_TX | 2520 NETIF_F_TSO | 2521 NETIF_F_TSO6); 2522 2523 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2524 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2525 return features & ~(NETIF_F_HW_CSUM | 2526 NETIF_F_SCTP_CRC | 2527 NETIF_F_TSO | 2528 NETIF_F_TSO6); 2529 2530 /* We can only support IPV4 TSO in tunnels if we can mangle the 2531 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2532 */ 2533 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2534 features &= ~NETIF_F_TSO; 2535 2536 return features; 2537 } 2538 2539 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2540 { 2541 if (!is_fqtss_enabled(adapter)) { 2542 enable_fqtss(adapter, true); 2543 return; 2544 } 2545 2546 igb_config_tx_modes(adapter, queue); 2547 2548 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2549 enable_fqtss(adapter, false); 2550 } 2551 2552 static int igb_offload_cbs(struct igb_adapter *adapter, 2553 struct tc_cbs_qopt_offload *qopt) 2554 { 2555 struct e1000_hw *hw = &adapter->hw; 2556 int err; 2557 2558 /* CBS offloading is only supported by i210 controller. */ 2559 if (hw->mac.type != e1000_i210) 2560 return -EOPNOTSUPP; 2561 2562 /* CBS offloading is only supported by queue 0 and queue 1. */ 2563 if (qopt->queue < 0 || qopt->queue > 1) 2564 return -EINVAL; 2565 2566 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2567 qopt->idleslope, qopt->sendslope, 2568 qopt->hicredit, qopt->locredit); 2569 if (err) 2570 return err; 2571 2572 igb_offload_apply(adapter, qopt->queue); 2573 2574 return 0; 2575 } 2576 2577 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2578 #define VLAN_PRIO_FULL_MASK (0x07) 2579 2580 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2581 struct flow_cls_offload *f, 2582 int traffic_class, 2583 struct igb_nfc_filter *input) 2584 { 2585 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2586 struct flow_dissector *dissector = rule->match.dissector; 2587 struct netlink_ext_ack *extack = f->common.extack; 2588 2589 if (dissector->used_keys & 2590 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2591 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2592 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2593 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2594 NL_SET_ERR_MSG_MOD(extack, 2595 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2600 struct flow_match_eth_addrs match; 2601 2602 flow_rule_match_eth_addrs(rule, &match); 2603 if (!is_zero_ether_addr(match.mask->dst)) { 2604 if (!is_broadcast_ether_addr(match.mask->dst)) { 2605 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2606 return -EINVAL; 2607 } 2608 2609 input->filter.match_flags |= 2610 IGB_FILTER_FLAG_DST_MAC_ADDR; 2611 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2612 } 2613 2614 if (!is_zero_ether_addr(match.mask->src)) { 2615 if (!is_broadcast_ether_addr(match.mask->src)) { 2616 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2617 return -EINVAL; 2618 } 2619 2620 input->filter.match_flags |= 2621 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2622 ether_addr_copy(input->filter.src_addr, match.key->src); 2623 } 2624 } 2625 2626 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2627 struct flow_match_basic match; 2628 2629 flow_rule_match_basic(rule, &match); 2630 if (match.mask->n_proto) { 2631 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2632 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2633 return -EINVAL; 2634 } 2635 2636 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2637 input->filter.etype = match.key->n_proto; 2638 } 2639 } 2640 2641 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2642 struct flow_match_vlan match; 2643 2644 flow_rule_match_vlan(rule, &match); 2645 if (match.mask->vlan_priority) { 2646 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2647 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2648 return -EINVAL; 2649 } 2650 2651 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2652 input->filter.vlan_tci = match.key->vlan_priority; 2653 } 2654 } 2655 2656 input->action = traffic_class; 2657 input->cookie = f->cookie; 2658 2659 return 0; 2660 } 2661 2662 static int igb_configure_clsflower(struct igb_adapter *adapter, 2663 struct flow_cls_offload *cls_flower) 2664 { 2665 struct netlink_ext_ack *extack = cls_flower->common.extack; 2666 struct igb_nfc_filter *filter, *f; 2667 int err, tc; 2668 2669 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2670 if (tc < 0) { 2671 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2672 return -EINVAL; 2673 } 2674 2675 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2676 if (!filter) 2677 return -ENOMEM; 2678 2679 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2680 if (err < 0) 2681 goto err_parse; 2682 2683 spin_lock(&adapter->nfc_lock); 2684 2685 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2686 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2687 err = -EEXIST; 2688 NL_SET_ERR_MSG_MOD(extack, 2689 "This filter is already set in ethtool"); 2690 goto err_locked; 2691 } 2692 } 2693 2694 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2695 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2696 err = -EEXIST; 2697 NL_SET_ERR_MSG_MOD(extack, 2698 "This filter is already set in cls_flower"); 2699 goto err_locked; 2700 } 2701 } 2702 2703 err = igb_add_filter(adapter, filter); 2704 if (err < 0) { 2705 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2706 goto err_locked; 2707 } 2708 2709 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2710 2711 spin_unlock(&adapter->nfc_lock); 2712 2713 return 0; 2714 2715 err_locked: 2716 spin_unlock(&adapter->nfc_lock); 2717 2718 err_parse: 2719 kfree(filter); 2720 2721 return err; 2722 } 2723 2724 static int igb_delete_clsflower(struct igb_adapter *adapter, 2725 struct flow_cls_offload *cls_flower) 2726 { 2727 struct igb_nfc_filter *filter; 2728 int err; 2729 2730 spin_lock(&adapter->nfc_lock); 2731 2732 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2733 if (filter->cookie == cls_flower->cookie) 2734 break; 2735 2736 if (!filter) { 2737 err = -ENOENT; 2738 goto out; 2739 } 2740 2741 err = igb_erase_filter(adapter, filter); 2742 if (err < 0) 2743 goto out; 2744 2745 hlist_del(&filter->nfc_node); 2746 kfree(filter); 2747 2748 out: 2749 spin_unlock(&adapter->nfc_lock); 2750 2751 return err; 2752 } 2753 2754 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2755 struct flow_cls_offload *cls_flower) 2756 { 2757 switch (cls_flower->command) { 2758 case FLOW_CLS_REPLACE: 2759 return igb_configure_clsflower(adapter, cls_flower); 2760 case FLOW_CLS_DESTROY: 2761 return igb_delete_clsflower(adapter, cls_flower); 2762 case FLOW_CLS_STATS: 2763 return -EOPNOTSUPP; 2764 default: 2765 return -EOPNOTSUPP; 2766 } 2767 } 2768 2769 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2770 void *cb_priv) 2771 { 2772 struct igb_adapter *adapter = cb_priv; 2773 2774 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2775 return -EOPNOTSUPP; 2776 2777 switch (type) { 2778 case TC_SETUP_CLSFLOWER: 2779 return igb_setup_tc_cls_flower(adapter, type_data); 2780 2781 default: 2782 return -EOPNOTSUPP; 2783 } 2784 } 2785 2786 static int igb_offload_txtime(struct igb_adapter *adapter, 2787 struct tc_etf_qopt_offload *qopt) 2788 { 2789 struct e1000_hw *hw = &adapter->hw; 2790 int err; 2791 2792 /* Launchtime offloading is only supported by i210 controller. */ 2793 if (hw->mac.type != e1000_i210) 2794 return -EOPNOTSUPP; 2795 2796 /* Launchtime offloading is only supported by queues 0 and 1. */ 2797 if (qopt->queue < 0 || qopt->queue > 1) 2798 return -EINVAL; 2799 2800 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2801 if (err) 2802 return err; 2803 2804 igb_offload_apply(adapter, qopt->queue); 2805 2806 return 0; 2807 } 2808 2809 static LIST_HEAD(igb_block_cb_list); 2810 2811 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2812 void *type_data) 2813 { 2814 struct igb_adapter *adapter = netdev_priv(dev); 2815 2816 switch (type) { 2817 case TC_SETUP_QDISC_CBS: 2818 return igb_offload_cbs(adapter, type_data); 2819 case TC_SETUP_BLOCK: 2820 return flow_block_cb_setup_simple(type_data, 2821 &igb_block_cb_list, 2822 igb_setup_tc_block_cb, 2823 adapter, adapter, true); 2824 2825 case TC_SETUP_QDISC_ETF: 2826 return igb_offload_txtime(adapter, type_data); 2827 2828 default: 2829 return -EOPNOTSUPP; 2830 } 2831 } 2832 2833 static const struct net_device_ops igb_netdev_ops = { 2834 .ndo_open = igb_open, 2835 .ndo_stop = igb_close, 2836 .ndo_start_xmit = igb_xmit_frame, 2837 .ndo_get_stats64 = igb_get_stats64, 2838 .ndo_set_rx_mode = igb_set_rx_mode, 2839 .ndo_set_mac_address = igb_set_mac, 2840 .ndo_change_mtu = igb_change_mtu, 2841 .ndo_do_ioctl = igb_ioctl, 2842 .ndo_tx_timeout = igb_tx_timeout, 2843 .ndo_validate_addr = eth_validate_addr, 2844 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2845 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2846 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2847 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2848 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2849 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2850 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2851 .ndo_get_vf_config = igb_ndo_get_vf_config, 2852 .ndo_fix_features = igb_fix_features, 2853 .ndo_set_features = igb_set_features, 2854 .ndo_fdb_add = igb_ndo_fdb_add, 2855 .ndo_features_check = igb_features_check, 2856 .ndo_setup_tc = igb_setup_tc, 2857 }; 2858 2859 /** 2860 * igb_set_fw_version - Configure version string for ethtool 2861 * @adapter: adapter struct 2862 **/ 2863 void igb_set_fw_version(struct igb_adapter *adapter) 2864 { 2865 struct e1000_hw *hw = &adapter->hw; 2866 struct e1000_fw_version fw; 2867 2868 igb_get_fw_version(hw, &fw); 2869 2870 switch (hw->mac.type) { 2871 case e1000_i210: 2872 case e1000_i211: 2873 if (!(igb_get_flash_presence_i210(hw))) { 2874 snprintf(adapter->fw_version, 2875 sizeof(adapter->fw_version), 2876 "%2d.%2d-%d", 2877 fw.invm_major, fw.invm_minor, 2878 fw.invm_img_type); 2879 break; 2880 } 2881 /* fall through */ 2882 default: 2883 /* if option is rom valid, display its version too */ 2884 if (fw.or_valid) { 2885 snprintf(adapter->fw_version, 2886 sizeof(adapter->fw_version), 2887 "%d.%d, 0x%08x, %d.%d.%d", 2888 fw.eep_major, fw.eep_minor, fw.etrack_id, 2889 fw.or_major, fw.or_build, fw.or_patch); 2890 /* no option rom */ 2891 } else if (fw.etrack_id != 0X0000) { 2892 snprintf(adapter->fw_version, 2893 sizeof(adapter->fw_version), 2894 "%d.%d, 0x%08x", 2895 fw.eep_major, fw.eep_minor, fw.etrack_id); 2896 } else { 2897 snprintf(adapter->fw_version, 2898 sizeof(adapter->fw_version), 2899 "%d.%d.%d", 2900 fw.eep_major, fw.eep_minor, fw.eep_build); 2901 } 2902 break; 2903 } 2904 } 2905 2906 /** 2907 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2908 * 2909 * @adapter: adapter struct 2910 **/ 2911 static void igb_init_mas(struct igb_adapter *adapter) 2912 { 2913 struct e1000_hw *hw = &adapter->hw; 2914 u16 eeprom_data; 2915 2916 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2917 switch (hw->bus.func) { 2918 case E1000_FUNC_0: 2919 if (eeprom_data & IGB_MAS_ENABLE_0) { 2920 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2921 netdev_info(adapter->netdev, 2922 "MAS: Enabling Media Autosense for port %d\n", 2923 hw->bus.func); 2924 } 2925 break; 2926 case E1000_FUNC_1: 2927 if (eeprom_data & IGB_MAS_ENABLE_1) { 2928 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2929 netdev_info(adapter->netdev, 2930 "MAS: Enabling Media Autosense for port %d\n", 2931 hw->bus.func); 2932 } 2933 break; 2934 case E1000_FUNC_2: 2935 if (eeprom_data & IGB_MAS_ENABLE_2) { 2936 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2937 netdev_info(adapter->netdev, 2938 "MAS: Enabling Media Autosense for port %d\n", 2939 hw->bus.func); 2940 } 2941 break; 2942 case E1000_FUNC_3: 2943 if (eeprom_data & IGB_MAS_ENABLE_3) { 2944 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2945 netdev_info(adapter->netdev, 2946 "MAS: Enabling Media Autosense for port %d\n", 2947 hw->bus.func); 2948 } 2949 break; 2950 default: 2951 /* Shouldn't get here */ 2952 netdev_err(adapter->netdev, 2953 "MAS: Invalid port configuration, returning\n"); 2954 break; 2955 } 2956 } 2957 2958 /** 2959 * igb_init_i2c - Init I2C interface 2960 * @adapter: pointer to adapter structure 2961 **/ 2962 static s32 igb_init_i2c(struct igb_adapter *adapter) 2963 { 2964 s32 status = 0; 2965 2966 /* I2C interface supported on i350 devices */ 2967 if (adapter->hw.mac.type != e1000_i350) 2968 return 0; 2969 2970 /* Initialize the i2c bus which is controlled by the registers. 2971 * This bus will use the i2c_algo_bit structue that implements 2972 * the protocol through toggling of the 4 bits in the register. 2973 */ 2974 adapter->i2c_adap.owner = THIS_MODULE; 2975 adapter->i2c_algo = igb_i2c_algo; 2976 adapter->i2c_algo.data = adapter; 2977 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2978 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2979 strlcpy(adapter->i2c_adap.name, "igb BB", 2980 sizeof(adapter->i2c_adap.name)); 2981 status = i2c_bit_add_bus(&adapter->i2c_adap); 2982 return status; 2983 } 2984 2985 /** 2986 * igb_probe - Device Initialization Routine 2987 * @pdev: PCI device information struct 2988 * @ent: entry in igb_pci_tbl 2989 * 2990 * Returns 0 on success, negative on failure 2991 * 2992 * igb_probe initializes an adapter identified by a pci_dev structure. 2993 * The OS initialization, configuring of the adapter private structure, 2994 * and a hardware reset occur. 2995 **/ 2996 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2997 { 2998 struct net_device *netdev; 2999 struct igb_adapter *adapter; 3000 struct e1000_hw *hw; 3001 u16 eeprom_data = 0; 3002 s32 ret_val; 3003 static int global_quad_port_a; /* global quad port a indication */ 3004 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3005 int err, pci_using_dac; 3006 u8 part_str[E1000_PBANUM_LENGTH]; 3007 3008 /* Catch broken hardware that put the wrong VF device ID in 3009 * the PCIe SR-IOV capability. 3010 */ 3011 if (pdev->is_virtfn) { 3012 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3013 pci_name(pdev), pdev->vendor, pdev->device); 3014 return -EINVAL; 3015 } 3016 3017 err = pci_enable_device_mem(pdev); 3018 if (err) 3019 return err; 3020 3021 pci_using_dac = 0; 3022 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3023 if (!err) { 3024 pci_using_dac = 1; 3025 } else { 3026 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3027 if (err) { 3028 dev_err(&pdev->dev, 3029 "No usable DMA configuration, aborting\n"); 3030 goto err_dma; 3031 } 3032 } 3033 3034 err = pci_request_mem_regions(pdev, igb_driver_name); 3035 if (err) 3036 goto err_pci_reg; 3037 3038 pci_enable_pcie_error_reporting(pdev); 3039 3040 pci_set_master(pdev); 3041 pci_save_state(pdev); 3042 3043 err = -ENOMEM; 3044 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3045 IGB_MAX_TX_QUEUES); 3046 if (!netdev) 3047 goto err_alloc_etherdev; 3048 3049 SET_NETDEV_DEV(netdev, &pdev->dev); 3050 3051 pci_set_drvdata(pdev, netdev); 3052 adapter = netdev_priv(netdev); 3053 adapter->netdev = netdev; 3054 adapter->pdev = pdev; 3055 hw = &adapter->hw; 3056 hw->back = adapter; 3057 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3058 3059 err = -EIO; 3060 adapter->io_addr = pci_iomap(pdev, 0, 0); 3061 if (!adapter->io_addr) 3062 goto err_ioremap; 3063 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3064 hw->hw_addr = adapter->io_addr; 3065 3066 netdev->netdev_ops = &igb_netdev_ops; 3067 igb_set_ethtool_ops(netdev); 3068 netdev->watchdog_timeo = 5 * HZ; 3069 3070 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3071 3072 netdev->mem_start = pci_resource_start(pdev, 0); 3073 netdev->mem_end = pci_resource_end(pdev, 0); 3074 3075 /* PCI config space info */ 3076 hw->vendor_id = pdev->vendor; 3077 hw->device_id = pdev->device; 3078 hw->revision_id = pdev->revision; 3079 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3080 hw->subsystem_device_id = pdev->subsystem_device; 3081 3082 /* Copy the default MAC, PHY and NVM function pointers */ 3083 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3084 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3085 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3086 /* Initialize skew-specific constants */ 3087 err = ei->get_invariants(hw); 3088 if (err) 3089 goto err_sw_init; 3090 3091 /* setup the private structure */ 3092 err = igb_sw_init(adapter); 3093 if (err) 3094 goto err_sw_init; 3095 3096 igb_get_bus_info_pcie(hw); 3097 3098 hw->phy.autoneg_wait_to_complete = false; 3099 3100 /* Copper options */ 3101 if (hw->phy.media_type == e1000_media_type_copper) { 3102 hw->phy.mdix = AUTO_ALL_MODES; 3103 hw->phy.disable_polarity_correction = false; 3104 hw->phy.ms_type = e1000_ms_hw_default; 3105 } 3106 3107 if (igb_check_reset_block(hw)) 3108 dev_info(&pdev->dev, 3109 "PHY reset is blocked due to SOL/IDER session.\n"); 3110 3111 /* features is initialized to 0 in allocation, it might have bits 3112 * set by igb_sw_init so we should use an or instead of an 3113 * assignment. 3114 */ 3115 netdev->features |= NETIF_F_SG | 3116 NETIF_F_TSO | 3117 NETIF_F_TSO6 | 3118 NETIF_F_RXHASH | 3119 NETIF_F_RXCSUM | 3120 NETIF_F_HW_CSUM; 3121 3122 if (hw->mac.type >= e1000_82576) 3123 netdev->features |= NETIF_F_SCTP_CRC; 3124 3125 if (hw->mac.type >= e1000_i350) 3126 netdev->features |= NETIF_F_HW_TC; 3127 3128 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3129 NETIF_F_GSO_GRE_CSUM | \ 3130 NETIF_F_GSO_IPXIP4 | \ 3131 NETIF_F_GSO_IPXIP6 | \ 3132 NETIF_F_GSO_UDP_TUNNEL | \ 3133 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3134 3135 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3136 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3137 3138 /* copy netdev features into list of user selectable features */ 3139 netdev->hw_features |= netdev->features | 3140 NETIF_F_HW_VLAN_CTAG_RX | 3141 NETIF_F_HW_VLAN_CTAG_TX | 3142 NETIF_F_RXALL; 3143 3144 if (hw->mac.type >= e1000_i350) 3145 netdev->hw_features |= NETIF_F_NTUPLE; 3146 3147 if (pci_using_dac) 3148 netdev->features |= NETIF_F_HIGHDMA; 3149 3150 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3151 netdev->mpls_features |= NETIF_F_HW_CSUM; 3152 netdev->hw_enc_features |= netdev->vlan_features; 3153 3154 /* set this bit last since it cannot be part of vlan_features */ 3155 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3156 NETIF_F_HW_VLAN_CTAG_RX | 3157 NETIF_F_HW_VLAN_CTAG_TX; 3158 3159 netdev->priv_flags |= IFF_SUPP_NOFCS; 3160 3161 netdev->priv_flags |= IFF_UNICAST_FLT; 3162 3163 /* MTU range: 68 - 9216 */ 3164 netdev->min_mtu = ETH_MIN_MTU; 3165 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3166 3167 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3168 3169 /* before reading the NVM, reset the controller to put the device in a 3170 * known good starting state 3171 */ 3172 hw->mac.ops.reset_hw(hw); 3173 3174 /* make sure the NVM is good , i211/i210 parts can have special NVM 3175 * that doesn't contain a checksum 3176 */ 3177 switch (hw->mac.type) { 3178 case e1000_i210: 3179 case e1000_i211: 3180 if (igb_get_flash_presence_i210(hw)) { 3181 if (hw->nvm.ops.validate(hw) < 0) { 3182 dev_err(&pdev->dev, 3183 "The NVM Checksum Is Not Valid\n"); 3184 err = -EIO; 3185 goto err_eeprom; 3186 } 3187 } 3188 break; 3189 default: 3190 if (hw->nvm.ops.validate(hw) < 0) { 3191 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3192 err = -EIO; 3193 goto err_eeprom; 3194 } 3195 break; 3196 } 3197 3198 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3199 /* copy the MAC address out of the NVM */ 3200 if (hw->mac.ops.read_mac_addr(hw)) 3201 dev_err(&pdev->dev, "NVM Read Error\n"); 3202 } 3203 3204 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3205 3206 if (!is_valid_ether_addr(netdev->dev_addr)) { 3207 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3208 err = -EIO; 3209 goto err_eeprom; 3210 } 3211 3212 igb_set_default_mac_filter(adapter); 3213 3214 /* get firmware version for ethtool -i */ 3215 igb_set_fw_version(adapter); 3216 3217 /* configure RXPBSIZE and TXPBSIZE */ 3218 if (hw->mac.type == e1000_i210) { 3219 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3220 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3221 } 3222 3223 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3224 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3225 3226 INIT_WORK(&adapter->reset_task, igb_reset_task); 3227 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3228 3229 /* Initialize link properties that are user-changeable */ 3230 adapter->fc_autoneg = true; 3231 hw->mac.autoneg = true; 3232 hw->phy.autoneg_advertised = 0x2f; 3233 3234 hw->fc.requested_mode = e1000_fc_default; 3235 hw->fc.current_mode = e1000_fc_default; 3236 3237 igb_validate_mdi_setting(hw); 3238 3239 /* By default, support wake on port A */ 3240 if (hw->bus.func == 0) 3241 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3242 3243 /* Check the NVM for wake support on non-port A ports */ 3244 if (hw->mac.type >= e1000_82580) 3245 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3246 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3247 &eeprom_data); 3248 else if (hw->bus.func == 1) 3249 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3250 3251 if (eeprom_data & IGB_EEPROM_APME) 3252 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3253 3254 /* now that we have the eeprom settings, apply the special cases where 3255 * the eeprom may be wrong or the board simply won't support wake on 3256 * lan on a particular port 3257 */ 3258 switch (pdev->device) { 3259 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3260 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3261 break; 3262 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3263 case E1000_DEV_ID_82576_FIBER: 3264 case E1000_DEV_ID_82576_SERDES: 3265 /* Wake events only supported on port A for dual fiber 3266 * regardless of eeprom setting 3267 */ 3268 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3269 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3270 break; 3271 case E1000_DEV_ID_82576_QUAD_COPPER: 3272 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3273 /* if quad port adapter, disable WoL on all but port A */ 3274 if (global_quad_port_a != 0) 3275 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3276 else 3277 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3278 /* Reset for multiple quad port adapters */ 3279 if (++global_quad_port_a == 4) 3280 global_quad_port_a = 0; 3281 break; 3282 default: 3283 /* If the device can't wake, don't set software support */ 3284 if (!device_can_wakeup(&adapter->pdev->dev)) 3285 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3286 } 3287 3288 /* initialize the wol settings based on the eeprom settings */ 3289 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3290 adapter->wol |= E1000_WUFC_MAG; 3291 3292 /* Some vendors want WoL disabled by default, but still supported */ 3293 if ((hw->mac.type == e1000_i350) && 3294 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3295 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3296 adapter->wol = 0; 3297 } 3298 3299 /* Some vendors want the ability to Use the EEPROM setting as 3300 * enable/disable only, and not for capability 3301 */ 3302 if (((hw->mac.type == e1000_i350) || 3303 (hw->mac.type == e1000_i354)) && 3304 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3305 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3306 adapter->wol = 0; 3307 } 3308 if (hw->mac.type == e1000_i350) { 3309 if (((pdev->subsystem_device == 0x5001) || 3310 (pdev->subsystem_device == 0x5002)) && 3311 (hw->bus.func == 0)) { 3312 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3313 adapter->wol = 0; 3314 } 3315 if (pdev->subsystem_device == 0x1F52) 3316 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3317 } 3318 3319 device_set_wakeup_enable(&adapter->pdev->dev, 3320 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3321 3322 /* reset the hardware with the new settings */ 3323 igb_reset(adapter); 3324 3325 /* Init the I2C interface */ 3326 err = igb_init_i2c(adapter); 3327 if (err) { 3328 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3329 goto err_eeprom; 3330 } 3331 3332 /* let the f/w know that the h/w is now under the control of the 3333 * driver. 3334 */ 3335 igb_get_hw_control(adapter); 3336 3337 strcpy(netdev->name, "eth%d"); 3338 err = register_netdev(netdev); 3339 if (err) 3340 goto err_register; 3341 3342 /* carrier off reporting is important to ethtool even BEFORE open */ 3343 netif_carrier_off(netdev); 3344 3345 #ifdef CONFIG_IGB_DCA 3346 if (dca_add_requester(&pdev->dev) == 0) { 3347 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3348 dev_info(&pdev->dev, "DCA enabled\n"); 3349 igb_setup_dca(adapter); 3350 } 3351 3352 #endif 3353 #ifdef CONFIG_IGB_HWMON 3354 /* Initialize the thermal sensor on i350 devices. */ 3355 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3356 u16 ets_word; 3357 3358 /* Read the NVM to determine if this i350 device supports an 3359 * external thermal sensor. 3360 */ 3361 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3362 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3363 adapter->ets = true; 3364 else 3365 adapter->ets = false; 3366 if (igb_sysfs_init(adapter)) 3367 dev_err(&pdev->dev, 3368 "failed to allocate sysfs resources\n"); 3369 } else { 3370 adapter->ets = false; 3371 } 3372 #endif 3373 /* Check if Media Autosense is enabled */ 3374 adapter->ei = *ei; 3375 if (hw->dev_spec._82575.mas_capable) 3376 igb_init_mas(adapter); 3377 3378 /* do hw tstamp init after resetting */ 3379 igb_ptp_init(adapter); 3380 3381 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3382 /* print bus type/speed/width info, not applicable to i354 */ 3383 if (hw->mac.type != e1000_i354) { 3384 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3385 netdev->name, 3386 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3387 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3388 "unknown"), 3389 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3390 "Width x4" : 3391 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3392 "Width x2" : 3393 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3394 "Width x1" : "unknown"), netdev->dev_addr); 3395 } 3396 3397 if ((hw->mac.type >= e1000_i210 || 3398 igb_get_flash_presence_i210(hw))) { 3399 ret_val = igb_read_part_string(hw, part_str, 3400 E1000_PBANUM_LENGTH); 3401 } else { 3402 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3403 } 3404 3405 if (ret_val) 3406 strcpy(part_str, "Unknown"); 3407 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3408 dev_info(&pdev->dev, 3409 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3410 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3411 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3412 adapter->num_rx_queues, adapter->num_tx_queues); 3413 if (hw->phy.media_type == e1000_media_type_copper) { 3414 switch (hw->mac.type) { 3415 case e1000_i350: 3416 case e1000_i210: 3417 case e1000_i211: 3418 /* Enable EEE for internal copper PHY devices */ 3419 err = igb_set_eee_i350(hw, true, true); 3420 if ((!err) && 3421 (!hw->dev_spec._82575.eee_disable)) { 3422 adapter->eee_advert = 3423 MDIO_EEE_100TX | MDIO_EEE_1000T; 3424 adapter->flags |= IGB_FLAG_EEE; 3425 } 3426 break; 3427 case e1000_i354: 3428 if ((rd32(E1000_CTRL_EXT) & 3429 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3430 err = igb_set_eee_i354(hw, true, true); 3431 if ((!err) && 3432 (!hw->dev_spec._82575.eee_disable)) { 3433 adapter->eee_advert = 3434 MDIO_EEE_100TX | MDIO_EEE_1000T; 3435 adapter->flags |= IGB_FLAG_EEE; 3436 } 3437 } 3438 break; 3439 default: 3440 break; 3441 } 3442 } 3443 3444 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 3445 3446 pm_runtime_put_noidle(&pdev->dev); 3447 return 0; 3448 3449 err_register: 3450 igb_release_hw_control(adapter); 3451 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3452 err_eeprom: 3453 if (!igb_check_reset_block(hw)) 3454 igb_reset_phy(hw); 3455 3456 if (hw->flash_address) 3457 iounmap(hw->flash_address); 3458 err_sw_init: 3459 kfree(adapter->mac_table); 3460 kfree(adapter->shadow_vfta); 3461 igb_clear_interrupt_scheme(adapter); 3462 #ifdef CONFIG_PCI_IOV 3463 igb_disable_sriov(pdev); 3464 #endif 3465 pci_iounmap(pdev, adapter->io_addr); 3466 err_ioremap: 3467 free_netdev(netdev); 3468 err_alloc_etherdev: 3469 pci_release_mem_regions(pdev); 3470 err_pci_reg: 3471 err_dma: 3472 pci_disable_device(pdev); 3473 return err; 3474 } 3475 3476 #ifdef CONFIG_PCI_IOV 3477 static int igb_disable_sriov(struct pci_dev *pdev) 3478 { 3479 struct net_device *netdev = pci_get_drvdata(pdev); 3480 struct igb_adapter *adapter = netdev_priv(netdev); 3481 struct e1000_hw *hw = &adapter->hw; 3482 3483 /* reclaim resources allocated to VFs */ 3484 if (adapter->vf_data) { 3485 /* disable iov and allow time for transactions to clear */ 3486 if (pci_vfs_assigned(pdev)) { 3487 dev_warn(&pdev->dev, 3488 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3489 return -EPERM; 3490 } else { 3491 pci_disable_sriov(pdev); 3492 msleep(500); 3493 } 3494 3495 kfree(adapter->vf_mac_list); 3496 adapter->vf_mac_list = NULL; 3497 kfree(adapter->vf_data); 3498 adapter->vf_data = NULL; 3499 adapter->vfs_allocated_count = 0; 3500 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3501 wrfl(); 3502 msleep(100); 3503 dev_info(&pdev->dev, "IOV Disabled\n"); 3504 3505 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3506 adapter->flags |= IGB_FLAG_DMAC; 3507 } 3508 3509 return 0; 3510 } 3511 3512 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3513 { 3514 struct net_device *netdev = pci_get_drvdata(pdev); 3515 struct igb_adapter *adapter = netdev_priv(netdev); 3516 int old_vfs = pci_num_vf(pdev); 3517 struct vf_mac_filter *mac_list; 3518 int err = 0; 3519 int num_vf_mac_filters, i; 3520 3521 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3522 err = -EPERM; 3523 goto out; 3524 } 3525 if (!num_vfs) 3526 goto out; 3527 3528 if (old_vfs) { 3529 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3530 old_vfs, max_vfs); 3531 adapter->vfs_allocated_count = old_vfs; 3532 } else 3533 adapter->vfs_allocated_count = num_vfs; 3534 3535 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3536 sizeof(struct vf_data_storage), GFP_KERNEL); 3537 3538 /* if allocation failed then we do not support SR-IOV */ 3539 if (!adapter->vf_data) { 3540 adapter->vfs_allocated_count = 0; 3541 err = -ENOMEM; 3542 goto out; 3543 } 3544 3545 /* Due to the limited number of RAR entries calculate potential 3546 * number of MAC filters available for the VFs. Reserve entries 3547 * for PF default MAC, PF MAC filters and at least one RAR entry 3548 * for each VF for VF MAC. 3549 */ 3550 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3551 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3552 adapter->vfs_allocated_count); 3553 3554 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3555 sizeof(struct vf_mac_filter), 3556 GFP_KERNEL); 3557 3558 mac_list = adapter->vf_mac_list; 3559 INIT_LIST_HEAD(&adapter->vf_macs.l); 3560 3561 if (adapter->vf_mac_list) { 3562 /* Initialize list of VF MAC filters */ 3563 for (i = 0; i < num_vf_mac_filters; i++) { 3564 mac_list->vf = -1; 3565 mac_list->free = true; 3566 list_add(&mac_list->l, &adapter->vf_macs.l); 3567 mac_list++; 3568 } 3569 } else { 3570 /* If we could not allocate memory for the VF MAC filters 3571 * we can continue without this feature but warn user. 3572 */ 3573 dev_err(&pdev->dev, 3574 "Unable to allocate memory for VF MAC filter list\n"); 3575 } 3576 3577 /* only call pci_enable_sriov() if no VFs are allocated already */ 3578 if (!old_vfs) { 3579 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3580 if (err) 3581 goto err_out; 3582 } 3583 dev_info(&pdev->dev, "%d VFs allocated\n", 3584 adapter->vfs_allocated_count); 3585 for (i = 0; i < adapter->vfs_allocated_count; i++) 3586 igb_vf_configure(adapter, i); 3587 3588 /* DMA Coalescing is not supported in IOV mode. */ 3589 adapter->flags &= ~IGB_FLAG_DMAC; 3590 goto out; 3591 3592 err_out: 3593 kfree(adapter->vf_mac_list); 3594 adapter->vf_mac_list = NULL; 3595 kfree(adapter->vf_data); 3596 adapter->vf_data = NULL; 3597 adapter->vfs_allocated_count = 0; 3598 out: 3599 return err; 3600 } 3601 3602 #endif 3603 /** 3604 * igb_remove_i2c - Cleanup I2C interface 3605 * @adapter: pointer to adapter structure 3606 **/ 3607 static void igb_remove_i2c(struct igb_adapter *adapter) 3608 { 3609 /* free the adapter bus structure */ 3610 i2c_del_adapter(&adapter->i2c_adap); 3611 } 3612 3613 /** 3614 * igb_remove - Device Removal Routine 3615 * @pdev: PCI device information struct 3616 * 3617 * igb_remove is called by the PCI subsystem to alert the driver 3618 * that it should release a PCI device. The could be caused by a 3619 * Hot-Plug event, or because the driver is going to be removed from 3620 * memory. 3621 **/ 3622 static void igb_remove(struct pci_dev *pdev) 3623 { 3624 struct net_device *netdev = pci_get_drvdata(pdev); 3625 struct igb_adapter *adapter = netdev_priv(netdev); 3626 struct e1000_hw *hw = &adapter->hw; 3627 3628 pm_runtime_get_noresume(&pdev->dev); 3629 #ifdef CONFIG_IGB_HWMON 3630 igb_sysfs_exit(adapter); 3631 #endif 3632 igb_remove_i2c(adapter); 3633 igb_ptp_stop(adapter); 3634 /* The watchdog timer may be rescheduled, so explicitly 3635 * disable watchdog from being rescheduled. 3636 */ 3637 set_bit(__IGB_DOWN, &adapter->state); 3638 del_timer_sync(&adapter->watchdog_timer); 3639 del_timer_sync(&adapter->phy_info_timer); 3640 3641 cancel_work_sync(&adapter->reset_task); 3642 cancel_work_sync(&adapter->watchdog_task); 3643 3644 #ifdef CONFIG_IGB_DCA 3645 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3646 dev_info(&pdev->dev, "DCA disabled\n"); 3647 dca_remove_requester(&pdev->dev); 3648 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3649 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3650 } 3651 #endif 3652 3653 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3654 * would have already happened in close and is redundant. 3655 */ 3656 igb_release_hw_control(adapter); 3657 3658 #ifdef CONFIG_PCI_IOV 3659 igb_disable_sriov(pdev); 3660 #endif 3661 3662 unregister_netdev(netdev); 3663 3664 igb_clear_interrupt_scheme(adapter); 3665 3666 pci_iounmap(pdev, adapter->io_addr); 3667 if (hw->flash_address) 3668 iounmap(hw->flash_address); 3669 pci_release_mem_regions(pdev); 3670 3671 kfree(adapter->mac_table); 3672 kfree(adapter->shadow_vfta); 3673 free_netdev(netdev); 3674 3675 pci_disable_pcie_error_reporting(pdev); 3676 3677 pci_disable_device(pdev); 3678 } 3679 3680 /** 3681 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3682 * @adapter: board private structure to initialize 3683 * 3684 * This function initializes the vf specific data storage and then attempts to 3685 * allocate the VFs. The reason for ordering it this way is because it is much 3686 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3687 * the memory for the VFs. 3688 **/ 3689 static void igb_probe_vfs(struct igb_adapter *adapter) 3690 { 3691 #ifdef CONFIG_PCI_IOV 3692 struct pci_dev *pdev = adapter->pdev; 3693 struct e1000_hw *hw = &adapter->hw; 3694 3695 /* Virtualization features not supported on i210 family. */ 3696 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3697 return; 3698 3699 /* Of the below we really only want the effect of getting 3700 * IGB_FLAG_HAS_MSIX set (if available), without which 3701 * igb_enable_sriov() has no effect. 3702 */ 3703 igb_set_interrupt_capability(adapter, true); 3704 igb_reset_interrupt_capability(adapter); 3705 3706 pci_sriov_set_totalvfs(pdev, 7); 3707 igb_enable_sriov(pdev, max_vfs); 3708 3709 #endif /* CONFIG_PCI_IOV */ 3710 } 3711 3712 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3713 { 3714 struct e1000_hw *hw = &adapter->hw; 3715 unsigned int max_rss_queues; 3716 3717 /* Determine the maximum number of RSS queues supported. */ 3718 switch (hw->mac.type) { 3719 case e1000_i211: 3720 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3721 break; 3722 case e1000_82575: 3723 case e1000_i210: 3724 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3725 break; 3726 case e1000_i350: 3727 /* I350 cannot do RSS and SR-IOV at the same time */ 3728 if (!!adapter->vfs_allocated_count) { 3729 max_rss_queues = 1; 3730 break; 3731 } 3732 /* fall through */ 3733 case e1000_82576: 3734 if (!!adapter->vfs_allocated_count) { 3735 max_rss_queues = 2; 3736 break; 3737 } 3738 /* fall through */ 3739 case e1000_82580: 3740 case e1000_i354: 3741 default: 3742 max_rss_queues = IGB_MAX_RX_QUEUES; 3743 break; 3744 } 3745 3746 return max_rss_queues; 3747 } 3748 3749 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3750 { 3751 u32 max_rss_queues; 3752 3753 max_rss_queues = igb_get_max_rss_queues(adapter); 3754 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3755 3756 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3757 } 3758 3759 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3760 const u32 max_rss_queues) 3761 { 3762 struct e1000_hw *hw = &adapter->hw; 3763 3764 /* Determine if we need to pair queues. */ 3765 switch (hw->mac.type) { 3766 case e1000_82575: 3767 case e1000_i211: 3768 /* Device supports enough interrupts without queue pairing. */ 3769 break; 3770 case e1000_82576: 3771 case e1000_82580: 3772 case e1000_i350: 3773 case e1000_i354: 3774 case e1000_i210: 3775 default: 3776 /* If rss_queues > half of max_rss_queues, pair the queues in 3777 * order to conserve interrupts due to limited supply. 3778 */ 3779 if (adapter->rss_queues > (max_rss_queues / 2)) 3780 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3781 else 3782 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3783 break; 3784 } 3785 } 3786 3787 /** 3788 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3789 * @adapter: board private structure to initialize 3790 * 3791 * igb_sw_init initializes the Adapter private data structure. 3792 * Fields are initialized based on PCI device information and 3793 * OS network device settings (MTU size). 3794 **/ 3795 static int igb_sw_init(struct igb_adapter *adapter) 3796 { 3797 struct e1000_hw *hw = &adapter->hw; 3798 struct net_device *netdev = adapter->netdev; 3799 struct pci_dev *pdev = adapter->pdev; 3800 3801 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3802 3803 /* set default ring sizes */ 3804 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3805 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3806 3807 /* set default ITR values */ 3808 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3809 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3810 3811 /* set default work limits */ 3812 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3813 3814 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3815 VLAN_HLEN; 3816 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3817 3818 spin_lock_init(&adapter->nfc_lock); 3819 spin_lock_init(&adapter->stats64_lock); 3820 #ifdef CONFIG_PCI_IOV 3821 switch (hw->mac.type) { 3822 case e1000_82576: 3823 case e1000_i350: 3824 if (max_vfs > 7) { 3825 dev_warn(&pdev->dev, 3826 "Maximum of 7 VFs per PF, using max\n"); 3827 max_vfs = adapter->vfs_allocated_count = 7; 3828 } else 3829 adapter->vfs_allocated_count = max_vfs; 3830 if (adapter->vfs_allocated_count) 3831 dev_warn(&pdev->dev, 3832 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3833 break; 3834 default: 3835 break; 3836 } 3837 #endif /* CONFIG_PCI_IOV */ 3838 3839 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3840 adapter->flags |= IGB_FLAG_HAS_MSIX; 3841 3842 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3843 sizeof(struct igb_mac_addr), 3844 GFP_KERNEL); 3845 if (!adapter->mac_table) 3846 return -ENOMEM; 3847 3848 igb_probe_vfs(adapter); 3849 3850 igb_init_queue_configuration(adapter); 3851 3852 /* Setup and initialize a copy of the hw vlan table array */ 3853 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3854 GFP_KERNEL); 3855 if (!adapter->shadow_vfta) 3856 return -ENOMEM; 3857 3858 /* This call may decrease the number of queues */ 3859 if (igb_init_interrupt_scheme(adapter, true)) { 3860 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3861 return -ENOMEM; 3862 } 3863 3864 /* Explicitly disable IRQ since the NIC can be in any state. */ 3865 igb_irq_disable(adapter); 3866 3867 if (hw->mac.type >= e1000_i350) 3868 adapter->flags &= ~IGB_FLAG_DMAC; 3869 3870 set_bit(__IGB_DOWN, &adapter->state); 3871 return 0; 3872 } 3873 3874 /** 3875 * igb_open - Called when a network interface is made active 3876 * @netdev: network interface device structure 3877 * 3878 * Returns 0 on success, negative value on failure 3879 * 3880 * The open entry point is called when a network interface is made 3881 * active by the system (IFF_UP). At this point all resources needed 3882 * for transmit and receive operations are allocated, the interrupt 3883 * handler is registered with the OS, the watchdog timer is started, 3884 * and the stack is notified that the interface is ready. 3885 **/ 3886 static int __igb_open(struct net_device *netdev, bool resuming) 3887 { 3888 struct igb_adapter *adapter = netdev_priv(netdev); 3889 struct e1000_hw *hw = &adapter->hw; 3890 struct pci_dev *pdev = adapter->pdev; 3891 int err; 3892 int i; 3893 3894 /* disallow open during test */ 3895 if (test_bit(__IGB_TESTING, &adapter->state)) { 3896 WARN_ON(resuming); 3897 return -EBUSY; 3898 } 3899 3900 if (!resuming) 3901 pm_runtime_get_sync(&pdev->dev); 3902 3903 netif_carrier_off(netdev); 3904 3905 /* allocate transmit descriptors */ 3906 err = igb_setup_all_tx_resources(adapter); 3907 if (err) 3908 goto err_setup_tx; 3909 3910 /* allocate receive descriptors */ 3911 err = igb_setup_all_rx_resources(adapter); 3912 if (err) 3913 goto err_setup_rx; 3914 3915 igb_power_up_link(adapter); 3916 3917 /* before we allocate an interrupt, we must be ready to handle it. 3918 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3919 * as soon as we call pci_request_irq, so we have to setup our 3920 * clean_rx handler before we do so. 3921 */ 3922 igb_configure(adapter); 3923 3924 err = igb_request_irq(adapter); 3925 if (err) 3926 goto err_req_irq; 3927 3928 /* Notify the stack of the actual queue counts. */ 3929 err = netif_set_real_num_tx_queues(adapter->netdev, 3930 adapter->num_tx_queues); 3931 if (err) 3932 goto err_set_queues; 3933 3934 err = netif_set_real_num_rx_queues(adapter->netdev, 3935 adapter->num_rx_queues); 3936 if (err) 3937 goto err_set_queues; 3938 3939 /* From here on the code is the same as igb_up() */ 3940 clear_bit(__IGB_DOWN, &adapter->state); 3941 3942 for (i = 0; i < adapter->num_q_vectors; i++) 3943 napi_enable(&(adapter->q_vector[i]->napi)); 3944 3945 /* Clear any pending interrupts. */ 3946 rd32(E1000_TSICR); 3947 rd32(E1000_ICR); 3948 3949 igb_irq_enable(adapter); 3950 3951 /* notify VFs that reset has been completed */ 3952 if (adapter->vfs_allocated_count) { 3953 u32 reg_data = rd32(E1000_CTRL_EXT); 3954 3955 reg_data |= E1000_CTRL_EXT_PFRSTD; 3956 wr32(E1000_CTRL_EXT, reg_data); 3957 } 3958 3959 netif_tx_start_all_queues(netdev); 3960 3961 if (!resuming) 3962 pm_runtime_put(&pdev->dev); 3963 3964 /* start the watchdog. */ 3965 hw->mac.get_link_status = 1; 3966 schedule_work(&adapter->watchdog_task); 3967 3968 return 0; 3969 3970 err_set_queues: 3971 igb_free_irq(adapter); 3972 err_req_irq: 3973 igb_release_hw_control(adapter); 3974 igb_power_down_link(adapter); 3975 igb_free_all_rx_resources(adapter); 3976 err_setup_rx: 3977 igb_free_all_tx_resources(adapter); 3978 err_setup_tx: 3979 igb_reset(adapter); 3980 if (!resuming) 3981 pm_runtime_put(&pdev->dev); 3982 3983 return err; 3984 } 3985 3986 int igb_open(struct net_device *netdev) 3987 { 3988 return __igb_open(netdev, false); 3989 } 3990 3991 /** 3992 * igb_close - Disables a network interface 3993 * @netdev: network interface device structure 3994 * 3995 * Returns 0, this is not allowed to fail 3996 * 3997 * The close entry point is called when an interface is de-activated 3998 * by the OS. The hardware is still under the driver's control, but 3999 * needs to be disabled. A global MAC reset is issued to stop the 4000 * hardware, and all transmit and receive resources are freed. 4001 **/ 4002 static int __igb_close(struct net_device *netdev, bool suspending) 4003 { 4004 struct igb_adapter *adapter = netdev_priv(netdev); 4005 struct pci_dev *pdev = adapter->pdev; 4006 4007 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4008 4009 if (!suspending) 4010 pm_runtime_get_sync(&pdev->dev); 4011 4012 igb_down(adapter); 4013 igb_free_irq(adapter); 4014 4015 igb_free_all_tx_resources(adapter); 4016 igb_free_all_rx_resources(adapter); 4017 4018 if (!suspending) 4019 pm_runtime_put_sync(&pdev->dev); 4020 return 0; 4021 } 4022 4023 int igb_close(struct net_device *netdev) 4024 { 4025 if (netif_device_present(netdev) || netdev->dismantle) 4026 return __igb_close(netdev, false); 4027 return 0; 4028 } 4029 4030 /** 4031 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4032 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4033 * 4034 * Return 0 on success, negative on failure 4035 **/ 4036 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4037 { 4038 struct device *dev = tx_ring->dev; 4039 int size; 4040 4041 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4042 4043 tx_ring->tx_buffer_info = vmalloc(size); 4044 if (!tx_ring->tx_buffer_info) 4045 goto err; 4046 4047 /* round up to nearest 4K */ 4048 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4049 tx_ring->size = ALIGN(tx_ring->size, 4096); 4050 4051 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4052 &tx_ring->dma, GFP_KERNEL); 4053 if (!tx_ring->desc) 4054 goto err; 4055 4056 tx_ring->next_to_use = 0; 4057 tx_ring->next_to_clean = 0; 4058 4059 return 0; 4060 4061 err: 4062 vfree(tx_ring->tx_buffer_info); 4063 tx_ring->tx_buffer_info = NULL; 4064 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4065 return -ENOMEM; 4066 } 4067 4068 /** 4069 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4070 * (Descriptors) for all queues 4071 * @adapter: board private structure 4072 * 4073 * Return 0 on success, negative on failure 4074 **/ 4075 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4076 { 4077 struct pci_dev *pdev = adapter->pdev; 4078 int i, err = 0; 4079 4080 for (i = 0; i < adapter->num_tx_queues; i++) { 4081 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4082 if (err) { 4083 dev_err(&pdev->dev, 4084 "Allocation for Tx Queue %u failed\n", i); 4085 for (i--; i >= 0; i--) 4086 igb_free_tx_resources(adapter->tx_ring[i]); 4087 break; 4088 } 4089 } 4090 4091 return err; 4092 } 4093 4094 /** 4095 * igb_setup_tctl - configure the transmit control registers 4096 * @adapter: Board private structure 4097 **/ 4098 void igb_setup_tctl(struct igb_adapter *adapter) 4099 { 4100 struct e1000_hw *hw = &adapter->hw; 4101 u32 tctl; 4102 4103 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4104 wr32(E1000_TXDCTL(0), 0); 4105 4106 /* Program the Transmit Control Register */ 4107 tctl = rd32(E1000_TCTL); 4108 tctl &= ~E1000_TCTL_CT; 4109 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4110 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4111 4112 igb_config_collision_dist(hw); 4113 4114 /* Enable transmits */ 4115 tctl |= E1000_TCTL_EN; 4116 4117 wr32(E1000_TCTL, tctl); 4118 } 4119 4120 /** 4121 * igb_configure_tx_ring - Configure transmit ring after Reset 4122 * @adapter: board private structure 4123 * @ring: tx ring to configure 4124 * 4125 * Configure a transmit ring after a reset. 4126 **/ 4127 void igb_configure_tx_ring(struct igb_adapter *adapter, 4128 struct igb_ring *ring) 4129 { 4130 struct e1000_hw *hw = &adapter->hw; 4131 u32 txdctl = 0; 4132 u64 tdba = ring->dma; 4133 int reg_idx = ring->reg_idx; 4134 4135 wr32(E1000_TDLEN(reg_idx), 4136 ring->count * sizeof(union e1000_adv_tx_desc)); 4137 wr32(E1000_TDBAL(reg_idx), 4138 tdba & 0x00000000ffffffffULL); 4139 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4140 4141 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4142 wr32(E1000_TDH(reg_idx), 0); 4143 writel(0, ring->tail); 4144 4145 txdctl |= IGB_TX_PTHRESH; 4146 txdctl |= IGB_TX_HTHRESH << 8; 4147 txdctl |= IGB_TX_WTHRESH << 16; 4148 4149 /* reinitialize tx_buffer_info */ 4150 memset(ring->tx_buffer_info, 0, 4151 sizeof(struct igb_tx_buffer) * ring->count); 4152 4153 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4154 wr32(E1000_TXDCTL(reg_idx), txdctl); 4155 } 4156 4157 /** 4158 * igb_configure_tx - Configure transmit Unit after Reset 4159 * @adapter: board private structure 4160 * 4161 * Configure the Tx unit of the MAC after a reset. 4162 **/ 4163 static void igb_configure_tx(struct igb_adapter *adapter) 4164 { 4165 struct e1000_hw *hw = &adapter->hw; 4166 int i; 4167 4168 /* disable the queues */ 4169 for (i = 0; i < adapter->num_tx_queues; i++) 4170 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4171 4172 wrfl(); 4173 usleep_range(10000, 20000); 4174 4175 for (i = 0; i < adapter->num_tx_queues; i++) 4176 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4177 } 4178 4179 /** 4180 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4181 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4182 * 4183 * Returns 0 on success, negative on failure 4184 **/ 4185 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4186 { 4187 struct device *dev = rx_ring->dev; 4188 int size; 4189 4190 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4191 4192 rx_ring->rx_buffer_info = vmalloc(size); 4193 if (!rx_ring->rx_buffer_info) 4194 goto err; 4195 4196 /* Round up to nearest 4K */ 4197 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4198 rx_ring->size = ALIGN(rx_ring->size, 4096); 4199 4200 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4201 &rx_ring->dma, GFP_KERNEL); 4202 if (!rx_ring->desc) 4203 goto err; 4204 4205 rx_ring->next_to_alloc = 0; 4206 rx_ring->next_to_clean = 0; 4207 rx_ring->next_to_use = 0; 4208 4209 return 0; 4210 4211 err: 4212 vfree(rx_ring->rx_buffer_info); 4213 rx_ring->rx_buffer_info = NULL; 4214 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4215 return -ENOMEM; 4216 } 4217 4218 /** 4219 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4220 * (Descriptors) for all queues 4221 * @adapter: board private structure 4222 * 4223 * Return 0 on success, negative on failure 4224 **/ 4225 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4226 { 4227 struct pci_dev *pdev = adapter->pdev; 4228 int i, err = 0; 4229 4230 for (i = 0; i < adapter->num_rx_queues; i++) { 4231 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4232 if (err) { 4233 dev_err(&pdev->dev, 4234 "Allocation for Rx Queue %u failed\n", i); 4235 for (i--; i >= 0; i--) 4236 igb_free_rx_resources(adapter->rx_ring[i]); 4237 break; 4238 } 4239 } 4240 4241 return err; 4242 } 4243 4244 /** 4245 * igb_setup_mrqc - configure the multiple receive queue control registers 4246 * @adapter: Board private structure 4247 **/ 4248 static void igb_setup_mrqc(struct igb_adapter *adapter) 4249 { 4250 struct e1000_hw *hw = &adapter->hw; 4251 u32 mrqc, rxcsum; 4252 u32 j, num_rx_queues; 4253 u32 rss_key[10]; 4254 4255 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4256 for (j = 0; j < 10; j++) 4257 wr32(E1000_RSSRK(j), rss_key[j]); 4258 4259 num_rx_queues = adapter->rss_queues; 4260 4261 switch (hw->mac.type) { 4262 case e1000_82576: 4263 /* 82576 supports 2 RSS queues for SR-IOV */ 4264 if (adapter->vfs_allocated_count) 4265 num_rx_queues = 2; 4266 break; 4267 default: 4268 break; 4269 } 4270 4271 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4272 for (j = 0; j < IGB_RETA_SIZE; j++) 4273 adapter->rss_indir_tbl[j] = 4274 (j * num_rx_queues) / IGB_RETA_SIZE; 4275 adapter->rss_indir_tbl_init = num_rx_queues; 4276 } 4277 igb_write_rss_indir_tbl(adapter); 4278 4279 /* Disable raw packet checksumming so that RSS hash is placed in 4280 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4281 * offloads as they are enabled by default 4282 */ 4283 rxcsum = rd32(E1000_RXCSUM); 4284 rxcsum |= E1000_RXCSUM_PCSD; 4285 4286 if (adapter->hw.mac.type >= e1000_82576) 4287 /* Enable Receive Checksum Offload for SCTP */ 4288 rxcsum |= E1000_RXCSUM_CRCOFL; 4289 4290 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4291 wr32(E1000_RXCSUM, rxcsum); 4292 4293 /* Generate RSS hash based on packet types, TCP/UDP 4294 * port numbers and/or IPv4/v6 src and dst addresses 4295 */ 4296 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4297 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4298 E1000_MRQC_RSS_FIELD_IPV6 | 4299 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4300 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4301 4302 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4303 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4304 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4305 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4306 4307 /* If VMDq is enabled then we set the appropriate mode for that, else 4308 * we default to RSS so that an RSS hash is calculated per packet even 4309 * if we are only using one queue 4310 */ 4311 if (adapter->vfs_allocated_count) { 4312 if (hw->mac.type > e1000_82575) { 4313 /* Set the default pool for the PF's first queue */ 4314 u32 vtctl = rd32(E1000_VT_CTL); 4315 4316 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4317 E1000_VT_CTL_DISABLE_DEF_POOL); 4318 vtctl |= adapter->vfs_allocated_count << 4319 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4320 wr32(E1000_VT_CTL, vtctl); 4321 } 4322 if (adapter->rss_queues > 1) 4323 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4324 else 4325 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4326 } else { 4327 if (hw->mac.type != e1000_i211) 4328 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4329 } 4330 igb_vmm_control(adapter); 4331 4332 wr32(E1000_MRQC, mrqc); 4333 } 4334 4335 /** 4336 * igb_setup_rctl - configure the receive control registers 4337 * @adapter: Board private structure 4338 **/ 4339 void igb_setup_rctl(struct igb_adapter *adapter) 4340 { 4341 struct e1000_hw *hw = &adapter->hw; 4342 u32 rctl; 4343 4344 rctl = rd32(E1000_RCTL); 4345 4346 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4347 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4348 4349 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4350 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4351 4352 /* enable stripping of CRC. It's unlikely this will break BMC 4353 * redirection as it did with e1000. Newer features require 4354 * that the HW strips the CRC. 4355 */ 4356 rctl |= E1000_RCTL_SECRC; 4357 4358 /* disable store bad packets and clear size bits. */ 4359 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4360 4361 /* enable LPE to allow for reception of jumbo frames */ 4362 rctl |= E1000_RCTL_LPE; 4363 4364 /* disable queue 0 to prevent tail write w/o re-config */ 4365 wr32(E1000_RXDCTL(0), 0); 4366 4367 /* Attention!!! For SR-IOV PF driver operations you must enable 4368 * queue drop for all VF and PF queues to prevent head of line blocking 4369 * if an un-trusted VF does not provide descriptors to hardware. 4370 */ 4371 if (adapter->vfs_allocated_count) { 4372 /* set all queue drop enable bits */ 4373 wr32(E1000_QDE, ALL_QUEUES); 4374 } 4375 4376 /* This is useful for sniffing bad packets. */ 4377 if (adapter->netdev->features & NETIF_F_RXALL) { 4378 /* UPE and MPE will be handled by normal PROMISC logic 4379 * in e1000e_set_rx_mode 4380 */ 4381 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4382 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4383 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4384 4385 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4386 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4387 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4388 * and that breaks VLANs. 4389 */ 4390 } 4391 4392 wr32(E1000_RCTL, rctl); 4393 } 4394 4395 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4396 int vfn) 4397 { 4398 struct e1000_hw *hw = &adapter->hw; 4399 u32 vmolr; 4400 4401 if (size > MAX_JUMBO_FRAME_SIZE) 4402 size = MAX_JUMBO_FRAME_SIZE; 4403 4404 vmolr = rd32(E1000_VMOLR(vfn)); 4405 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4406 vmolr |= size | E1000_VMOLR_LPE; 4407 wr32(E1000_VMOLR(vfn), vmolr); 4408 4409 return 0; 4410 } 4411 4412 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4413 int vfn, bool enable) 4414 { 4415 struct e1000_hw *hw = &adapter->hw; 4416 u32 val, reg; 4417 4418 if (hw->mac.type < e1000_82576) 4419 return; 4420 4421 if (hw->mac.type == e1000_i350) 4422 reg = E1000_DVMOLR(vfn); 4423 else 4424 reg = E1000_VMOLR(vfn); 4425 4426 val = rd32(reg); 4427 if (enable) 4428 val |= E1000_VMOLR_STRVLAN; 4429 else 4430 val &= ~(E1000_VMOLR_STRVLAN); 4431 wr32(reg, val); 4432 } 4433 4434 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4435 int vfn, bool aupe) 4436 { 4437 struct e1000_hw *hw = &adapter->hw; 4438 u32 vmolr; 4439 4440 /* This register exists only on 82576 and newer so if we are older then 4441 * we should exit and do nothing 4442 */ 4443 if (hw->mac.type < e1000_82576) 4444 return; 4445 4446 vmolr = rd32(E1000_VMOLR(vfn)); 4447 if (aupe) 4448 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4449 else 4450 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4451 4452 /* clear all bits that might not be set */ 4453 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4454 4455 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4456 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4457 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4458 * multicast packets 4459 */ 4460 if (vfn <= adapter->vfs_allocated_count) 4461 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4462 4463 wr32(E1000_VMOLR(vfn), vmolr); 4464 } 4465 4466 /** 4467 * igb_configure_rx_ring - Configure a receive ring after Reset 4468 * @adapter: board private structure 4469 * @ring: receive ring to be configured 4470 * 4471 * Configure the Rx unit of the MAC after a reset. 4472 **/ 4473 void igb_configure_rx_ring(struct igb_adapter *adapter, 4474 struct igb_ring *ring) 4475 { 4476 struct e1000_hw *hw = &adapter->hw; 4477 union e1000_adv_rx_desc *rx_desc; 4478 u64 rdba = ring->dma; 4479 int reg_idx = ring->reg_idx; 4480 u32 srrctl = 0, rxdctl = 0; 4481 4482 /* disable the queue */ 4483 wr32(E1000_RXDCTL(reg_idx), 0); 4484 4485 /* Set DMA base address registers */ 4486 wr32(E1000_RDBAL(reg_idx), 4487 rdba & 0x00000000ffffffffULL); 4488 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4489 wr32(E1000_RDLEN(reg_idx), 4490 ring->count * sizeof(union e1000_adv_rx_desc)); 4491 4492 /* initialize head and tail */ 4493 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4494 wr32(E1000_RDH(reg_idx), 0); 4495 writel(0, ring->tail); 4496 4497 /* set descriptor configuration */ 4498 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4499 if (ring_uses_large_buffer(ring)) 4500 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4501 else 4502 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4503 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4504 if (hw->mac.type >= e1000_82580) 4505 srrctl |= E1000_SRRCTL_TIMESTAMP; 4506 /* Only set Drop Enable if we are supporting multiple queues */ 4507 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 4508 srrctl |= E1000_SRRCTL_DROP_EN; 4509 4510 wr32(E1000_SRRCTL(reg_idx), srrctl); 4511 4512 /* set filtering for VMDQ pools */ 4513 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4514 4515 rxdctl |= IGB_RX_PTHRESH; 4516 rxdctl |= IGB_RX_HTHRESH << 8; 4517 rxdctl |= IGB_RX_WTHRESH << 16; 4518 4519 /* initialize rx_buffer_info */ 4520 memset(ring->rx_buffer_info, 0, 4521 sizeof(struct igb_rx_buffer) * ring->count); 4522 4523 /* initialize Rx descriptor 0 */ 4524 rx_desc = IGB_RX_DESC(ring, 0); 4525 rx_desc->wb.upper.length = 0; 4526 4527 /* enable receive descriptor fetching */ 4528 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4529 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4530 } 4531 4532 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4533 struct igb_ring *rx_ring) 4534 { 4535 /* set build_skb and buffer size flags */ 4536 clear_ring_build_skb_enabled(rx_ring); 4537 clear_ring_uses_large_buffer(rx_ring); 4538 4539 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4540 return; 4541 4542 set_ring_build_skb_enabled(rx_ring); 4543 4544 #if (PAGE_SIZE < 8192) 4545 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4546 return; 4547 4548 set_ring_uses_large_buffer(rx_ring); 4549 #endif 4550 } 4551 4552 /** 4553 * igb_configure_rx - Configure receive Unit after Reset 4554 * @adapter: board private structure 4555 * 4556 * Configure the Rx unit of the MAC after a reset. 4557 **/ 4558 static void igb_configure_rx(struct igb_adapter *adapter) 4559 { 4560 int i; 4561 4562 /* set the correct pool for the PF default MAC address in entry 0 */ 4563 igb_set_default_mac_filter(adapter); 4564 4565 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4566 * the Base and Length of the Rx Descriptor Ring 4567 */ 4568 for (i = 0; i < adapter->num_rx_queues; i++) { 4569 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4570 4571 igb_set_rx_buffer_len(adapter, rx_ring); 4572 igb_configure_rx_ring(adapter, rx_ring); 4573 } 4574 } 4575 4576 /** 4577 * igb_free_tx_resources - Free Tx Resources per Queue 4578 * @tx_ring: Tx descriptor ring for a specific queue 4579 * 4580 * Free all transmit software resources 4581 **/ 4582 void igb_free_tx_resources(struct igb_ring *tx_ring) 4583 { 4584 igb_clean_tx_ring(tx_ring); 4585 4586 vfree(tx_ring->tx_buffer_info); 4587 tx_ring->tx_buffer_info = NULL; 4588 4589 /* if not set, then don't free */ 4590 if (!tx_ring->desc) 4591 return; 4592 4593 dma_free_coherent(tx_ring->dev, tx_ring->size, 4594 tx_ring->desc, tx_ring->dma); 4595 4596 tx_ring->desc = NULL; 4597 } 4598 4599 /** 4600 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4601 * @adapter: board private structure 4602 * 4603 * Free all transmit software resources 4604 **/ 4605 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4606 { 4607 int i; 4608 4609 for (i = 0; i < adapter->num_tx_queues; i++) 4610 if (adapter->tx_ring[i]) 4611 igb_free_tx_resources(adapter->tx_ring[i]); 4612 } 4613 4614 /** 4615 * igb_clean_tx_ring - Free Tx Buffers 4616 * @tx_ring: ring to be cleaned 4617 **/ 4618 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4619 { 4620 u16 i = tx_ring->next_to_clean; 4621 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4622 4623 while (i != tx_ring->next_to_use) { 4624 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4625 4626 /* Free all the Tx ring sk_buffs */ 4627 dev_kfree_skb_any(tx_buffer->skb); 4628 4629 /* unmap skb header data */ 4630 dma_unmap_single(tx_ring->dev, 4631 dma_unmap_addr(tx_buffer, dma), 4632 dma_unmap_len(tx_buffer, len), 4633 DMA_TO_DEVICE); 4634 4635 /* check for eop_desc to determine the end of the packet */ 4636 eop_desc = tx_buffer->next_to_watch; 4637 tx_desc = IGB_TX_DESC(tx_ring, i); 4638 4639 /* unmap remaining buffers */ 4640 while (tx_desc != eop_desc) { 4641 tx_buffer++; 4642 tx_desc++; 4643 i++; 4644 if (unlikely(i == tx_ring->count)) { 4645 i = 0; 4646 tx_buffer = tx_ring->tx_buffer_info; 4647 tx_desc = IGB_TX_DESC(tx_ring, 0); 4648 } 4649 4650 /* unmap any remaining paged data */ 4651 if (dma_unmap_len(tx_buffer, len)) 4652 dma_unmap_page(tx_ring->dev, 4653 dma_unmap_addr(tx_buffer, dma), 4654 dma_unmap_len(tx_buffer, len), 4655 DMA_TO_DEVICE); 4656 } 4657 4658 /* move us one more past the eop_desc for start of next pkt */ 4659 tx_buffer++; 4660 i++; 4661 if (unlikely(i == tx_ring->count)) { 4662 i = 0; 4663 tx_buffer = tx_ring->tx_buffer_info; 4664 } 4665 } 4666 4667 /* reset BQL for queue */ 4668 netdev_tx_reset_queue(txring_txq(tx_ring)); 4669 4670 /* reset next_to_use and next_to_clean */ 4671 tx_ring->next_to_use = 0; 4672 tx_ring->next_to_clean = 0; 4673 } 4674 4675 /** 4676 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4677 * @adapter: board private structure 4678 **/ 4679 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4680 { 4681 int i; 4682 4683 for (i = 0; i < adapter->num_tx_queues; i++) 4684 if (adapter->tx_ring[i]) 4685 igb_clean_tx_ring(adapter->tx_ring[i]); 4686 } 4687 4688 /** 4689 * igb_free_rx_resources - Free Rx Resources 4690 * @rx_ring: ring to clean the resources from 4691 * 4692 * Free all receive software resources 4693 **/ 4694 void igb_free_rx_resources(struct igb_ring *rx_ring) 4695 { 4696 igb_clean_rx_ring(rx_ring); 4697 4698 vfree(rx_ring->rx_buffer_info); 4699 rx_ring->rx_buffer_info = NULL; 4700 4701 /* if not set, then don't free */ 4702 if (!rx_ring->desc) 4703 return; 4704 4705 dma_free_coherent(rx_ring->dev, rx_ring->size, 4706 rx_ring->desc, rx_ring->dma); 4707 4708 rx_ring->desc = NULL; 4709 } 4710 4711 /** 4712 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4713 * @adapter: board private structure 4714 * 4715 * Free all receive software resources 4716 **/ 4717 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4718 { 4719 int i; 4720 4721 for (i = 0; i < adapter->num_rx_queues; i++) 4722 if (adapter->rx_ring[i]) 4723 igb_free_rx_resources(adapter->rx_ring[i]); 4724 } 4725 4726 /** 4727 * igb_clean_rx_ring - Free Rx Buffers per Queue 4728 * @rx_ring: ring to free buffers from 4729 **/ 4730 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4731 { 4732 u16 i = rx_ring->next_to_clean; 4733 4734 if (rx_ring->skb) 4735 dev_kfree_skb(rx_ring->skb); 4736 rx_ring->skb = NULL; 4737 4738 /* Free all the Rx ring sk_buffs */ 4739 while (i != rx_ring->next_to_alloc) { 4740 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4741 4742 /* Invalidate cache lines that may have been written to by 4743 * device so that we avoid corrupting memory. 4744 */ 4745 dma_sync_single_range_for_cpu(rx_ring->dev, 4746 buffer_info->dma, 4747 buffer_info->page_offset, 4748 igb_rx_bufsz(rx_ring), 4749 DMA_FROM_DEVICE); 4750 4751 /* free resources associated with mapping */ 4752 dma_unmap_page_attrs(rx_ring->dev, 4753 buffer_info->dma, 4754 igb_rx_pg_size(rx_ring), 4755 DMA_FROM_DEVICE, 4756 IGB_RX_DMA_ATTR); 4757 __page_frag_cache_drain(buffer_info->page, 4758 buffer_info->pagecnt_bias); 4759 4760 i++; 4761 if (i == rx_ring->count) 4762 i = 0; 4763 } 4764 4765 rx_ring->next_to_alloc = 0; 4766 rx_ring->next_to_clean = 0; 4767 rx_ring->next_to_use = 0; 4768 } 4769 4770 /** 4771 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4772 * @adapter: board private structure 4773 **/ 4774 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4775 { 4776 int i; 4777 4778 for (i = 0; i < adapter->num_rx_queues; i++) 4779 if (adapter->rx_ring[i]) 4780 igb_clean_rx_ring(adapter->rx_ring[i]); 4781 } 4782 4783 /** 4784 * igb_set_mac - Change the Ethernet Address of the NIC 4785 * @netdev: network interface device structure 4786 * @p: pointer to an address structure 4787 * 4788 * Returns 0 on success, negative on failure 4789 **/ 4790 static int igb_set_mac(struct net_device *netdev, void *p) 4791 { 4792 struct igb_adapter *adapter = netdev_priv(netdev); 4793 struct e1000_hw *hw = &adapter->hw; 4794 struct sockaddr *addr = p; 4795 4796 if (!is_valid_ether_addr(addr->sa_data)) 4797 return -EADDRNOTAVAIL; 4798 4799 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4800 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4801 4802 /* set the correct pool for the new PF MAC address in entry 0 */ 4803 igb_set_default_mac_filter(adapter); 4804 4805 return 0; 4806 } 4807 4808 /** 4809 * igb_write_mc_addr_list - write multicast addresses to MTA 4810 * @netdev: network interface device structure 4811 * 4812 * Writes multicast address list to the MTA hash table. 4813 * Returns: -ENOMEM on failure 4814 * 0 on no addresses written 4815 * X on writing X addresses to MTA 4816 **/ 4817 static int igb_write_mc_addr_list(struct net_device *netdev) 4818 { 4819 struct igb_adapter *adapter = netdev_priv(netdev); 4820 struct e1000_hw *hw = &adapter->hw; 4821 struct netdev_hw_addr *ha; 4822 u8 *mta_list; 4823 int i; 4824 4825 if (netdev_mc_empty(netdev)) { 4826 /* nothing to program, so clear mc list */ 4827 igb_update_mc_addr_list(hw, NULL, 0); 4828 igb_restore_vf_multicasts(adapter); 4829 return 0; 4830 } 4831 4832 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 4833 if (!mta_list) 4834 return -ENOMEM; 4835 4836 /* The shared function expects a packed array of only addresses. */ 4837 i = 0; 4838 netdev_for_each_mc_addr(ha, netdev) 4839 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4840 4841 igb_update_mc_addr_list(hw, mta_list, i); 4842 kfree(mta_list); 4843 4844 return netdev_mc_count(netdev); 4845 } 4846 4847 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4848 { 4849 struct e1000_hw *hw = &adapter->hw; 4850 u32 i, pf_id; 4851 4852 switch (hw->mac.type) { 4853 case e1000_i210: 4854 case e1000_i211: 4855 case e1000_i350: 4856 /* VLAN filtering needed for VLAN prio filter */ 4857 if (adapter->netdev->features & NETIF_F_NTUPLE) 4858 break; 4859 /* fall through */ 4860 case e1000_82576: 4861 case e1000_82580: 4862 case e1000_i354: 4863 /* VLAN filtering needed for pool filtering */ 4864 if (adapter->vfs_allocated_count) 4865 break; 4866 /* fall through */ 4867 default: 4868 return 1; 4869 } 4870 4871 /* We are already in VLAN promisc, nothing to do */ 4872 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4873 return 0; 4874 4875 if (!adapter->vfs_allocated_count) 4876 goto set_vfta; 4877 4878 /* Add PF to all active pools */ 4879 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4880 4881 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4882 u32 vlvf = rd32(E1000_VLVF(i)); 4883 4884 vlvf |= BIT(pf_id); 4885 wr32(E1000_VLVF(i), vlvf); 4886 } 4887 4888 set_vfta: 4889 /* Set all bits in the VLAN filter table array */ 4890 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4891 hw->mac.ops.write_vfta(hw, i, ~0U); 4892 4893 /* Set flag so we don't redo unnecessary work */ 4894 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4895 4896 return 0; 4897 } 4898 4899 #define VFTA_BLOCK_SIZE 8 4900 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4901 { 4902 struct e1000_hw *hw = &adapter->hw; 4903 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4904 u32 vid_start = vfta_offset * 32; 4905 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4906 u32 i, vid, word, bits, pf_id; 4907 4908 /* guarantee that we don't scrub out management VLAN */ 4909 vid = adapter->mng_vlan_id; 4910 if (vid >= vid_start && vid < vid_end) 4911 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4912 4913 if (!adapter->vfs_allocated_count) 4914 goto set_vfta; 4915 4916 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4917 4918 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4919 u32 vlvf = rd32(E1000_VLVF(i)); 4920 4921 /* pull VLAN ID from VLVF */ 4922 vid = vlvf & VLAN_VID_MASK; 4923 4924 /* only concern ourselves with a certain range */ 4925 if (vid < vid_start || vid >= vid_end) 4926 continue; 4927 4928 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4929 /* record VLAN ID in VFTA */ 4930 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4931 4932 /* if PF is part of this then continue */ 4933 if (test_bit(vid, adapter->active_vlans)) 4934 continue; 4935 } 4936 4937 /* remove PF from the pool */ 4938 bits = ~BIT(pf_id); 4939 bits &= rd32(E1000_VLVF(i)); 4940 wr32(E1000_VLVF(i), bits); 4941 } 4942 4943 set_vfta: 4944 /* extract values from active_vlans and write back to VFTA */ 4945 for (i = VFTA_BLOCK_SIZE; i--;) { 4946 vid = (vfta_offset + i) * 32; 4947 word = vid / BITS_PER_LONG; 4948 bits = vid % BITS_PER_LONG; 4949 4950 vfta[i] |= adapter->active_vlans[word] >> bits; 4951 4952 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4953 } 4954 } 4955 4956 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4957 { 4958 u32 i; 4959 4960 /* We are not in VLAN promisc, nothing to do */ 4961 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4962 return; 4963 4964 /* Set flag so we don't redo unnecessary work */ 4965 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4966 4967 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4968 igb_scrub_vfta(adapter, i); 4969 } 4970 4971 /** 4972 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4973 * @netdev: network interface device structure 4974 * 4975 * The set_rx_mode entry point is called whenever the unicast or multicast 4976 * address lists or the network interface flags are updated. This routine is 4977 * responsible for configuring the hardware for proper unicast, multicast, 4978 * promiscuous mode, and all-multi behavior. 4979 **/ 4980 static void igb_set_rx_mode(struct net_device *netdev) 4981 { 4982 struct igb_adapter *adapter = netdev_priv(netdev); 4983 struct e1000_hw *hw = &adapter->hw; 4984 unsigned int vfn = adapter->vfs_allocated_count; 4985 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4986 int count; 4987 4988 /* Check for Promiscuous and All Multicast modes */ 4989 if (netdev->flags & IFF_PROMISC) { 4990 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4991 vmolr |= E1000_VMOLR_MPME; 4992 4993 /* enable use of UTA filter to force packets to default pool */ 4994 if (hw->mac.type == e1000_82576) 4995 vmolr |= E1000_VMOLR_ROPE; 4996 } else { 4997 if (netdev->flags & IFF_ALLMULTI) { 4998 rctl |= E1000_RCTL_MPE; 4999 vmolr |= E1000_VMOLR_MPME; 5000 } else { 5001 /* Write addresses to the MTA, if the attempt fails 5002 * then we should just turn on promiscuous mode so 5003 * that we can at least receive multicast traffic 5004 */ 5005 count = igb_write_mc_addr_list(netdev); 5006 if (count < 0) { 5007 rctl |= E1000_RCTL_MPE; 5008 vmolr |= E1000_VMOLR_MPME; 5009 } else if (count) { 5010 vmolr |= E1000_VMOLR_ROMPE; 5011 } 5012 } 5013 } 5014 5015 /* Write addresses to available RAR registers, if there is not 5016 * sufficient space to store all the addresses then enable 5017 * unicast promiscuous mode 5018 */ 5019 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5020 rctl |= E1000_RCTL_UPE; 5021 vmolr |= E1000_VMOLR_ROPE; 5022 } 5023 5024 /* enable VLAN filtering by default */ 5025 rctl |= E1000_RCTL_VFE; 5026 5027 /* disable VLAN filtering for modes that require it */ 5028 if ((netdev->flags & IFF_PROMISC) || 5029 (netdev->features & NETIF_F_RXALL)) { 5030 /* if we fail to set all rules then just clear VFE */ 5031 if (igb_vlan_promisc_enable(adapter)) 5032 rctl &= ~E1000_RCTL_VFE; 5033 } else { 5034 igb_vlan_promisc_disable(adapter); 5035 } 5036 5037 /* update state of unicast, multicast, and VLAN filtering modes */ 5038 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5039 E1000_RCTL_VFE); 5040 wr32(E1000_RCTL, rctl); 5041 5042 #if (PAGE_SIZE < 8192) 5043 if (!adapter->vfs_allocated_count) { 5044 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5045 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5046 } 5047 #endif 5048 wr32(E1000_RLPML, rlpml); 5049 5050 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5051 * the VMOLR to enable the appropriate modes. Without this workaround 5052 * we will have issues with VLAN tag stripping not being done for frames 5053 * that are only arriving because we are the default pool 5054 */ 5055 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5056 return; 5057 5058 /* set UTA to appropriate mode */ 5059 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5060 5061 vmolr |= rd32(E1000_VMOLR(vfn)) & 5062 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5063 5064 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5065 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5066 #if (PAGE_SIZE < 8192) 5067 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5068 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5069 else 5070 #endif 5071 vmolr |= MAX_JUMBO_FRAME_SIZE; 5072 vmolr |= E1000_VMOLR_LPE; 5073 5074 wr32(E1000_VMOLR(vfn), vmolr); 5075 5076 igb_restore_vf_multicasts(adapter); 5077 } 5078 5079 static void igb_check_wvbr(struct igb_adapter *adapter) 5080 { 5081 struct e1000_hw *hw = &adapter->hw; 5082 u32 wvbr = 0; 5083 5084 switch (hw->mac.type) { 5085 case e1000_82576: 5086 case e1000_i350: 5087 wvbr = rd32(E1000_WVBR); 5088 if (!wvbr) 5089 return; 5090 break; 5091 default: 5092 break; 5093 } 5094 5095 adapter->wvbr |= wvbr; 5096 } 5097 5098 #define IGB_STAGGERED_QUEUE_OFFSET 8 5099 5100 static void igb_spoof_check(struct igb_adapter *adapter) 5101 { 5102 int j; 5103 5104 if (!adapter->wvbr) 5105 return; 5106 5107 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5108 if (adapter->wvbr & BIT(j) || 5109 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5110 dev_warn(&adapter->pdev->dev, 5111 "Spoof event(s) detected on VF %d\n", j); 5112 adapter->wvbr &= 5113 ~(BIT(j) | 5114 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5115 } 5116 } 5117 } 5118 5119 /* Need to wait a few seconds after link up to get diagnostic information from 5120 * the phy 5121 */ 5122 static void igb_update_phy_info(struct timer_list *t) 5123 { 5124 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5125 igb_get_phy_info(&adapter->hw); 5126 } 5127 5128 /** 5129 * igb_has_link - check shared code for link and determine up/down 5130 * @adapter: pointer to driver private info 5131 **/ 5132 bool igb_has_link(struct igb_adapter *adapter) 5133 { 5134 struct e1000_hw *hw = &adapter->hw; 5135 bool link_active = false; 5136 5137 /* get_link_status is set on LSC (link status) interrupt or 5138 * rx sequence error interrupt. get_link_status will stay 5139 * false until the e1000_check_for_link establishes link 5140 * for copper adapters ONLY 5141 */ 5142 switch (hw->phy.media_type) { 5143 case e1000_media_type_copper: 5144 if (!hw->mac.get_link_status) 5145 return true; 5146 /* fall through */ 5147 case e1000_media_type_internal_serdes: 5148 hw->mac.ops.check_for_link(hw); 5149 link_active = !hw->mac.get_link_status; 5150 break; 5151 default: 5152 case e1000_media_type_unknown: 5153 break; 5154 } 5155 5156 if (((hw->mac.type == e1000_i210) || 5157 (hw->mac.type == e1000_i211)) && 5158 (hw->phy.id == I210_I_PHY_ID)) { 5159 if (!netif_carrier_ok(adapter->netdev)) { 5160 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5161 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5162 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5163 adapter->link_check_timeout = jiffies; 5164 } 5165 } 5166 5167 return link_active; 5168 } 5169 5170 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5171 { 5172 bool ret = false; 5173 u32 ctrl_ext, thstat; 5174 5175 /* check for thermal sensor event on i350 copper only */ 5176 if (hw->mac.type == e1000_i350) { 5177 thstat = rd32(E1000_THSTAT); 5178 ctrl_ext = rd32(E1000_CTRL_EXT); 5179 5180 if ((hw->phy.media_type == e1000_media_type_copper) && 5181 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5182 ret = !!(thstat & event); 5183 } 5184 5185 return ret; 5186 } 5187 5188 /** 5189 * igb_check_lvmmc - check for malformed packets received 5190 * and indicated in LVMMC register 5191 * @adapter: pointer to adapter 5192 **/ 5193 static void igb_check_lvmmc(struct igb_adapter *adapter) 5194 { 5195 struct e1000_hw *hw = &adapter->hw; 5196 u32 lvmmc; 5197 5198 lvmmc = rd32(E1000_LVMMC); 5199 if (lvmmc) { 5200 if (unlikely(net_ratelimit())) { 5201 netdev_warn(adapter->netdev, 5202 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5203 lvmmc); 5204 } 5205 } 5206 } 5207 5208 /** 5209 * igb_watchdog - Timer Call-back 5210 * @data: pointer to adapter cast into an unsigned long 5211 **/ 5212 static void igb_watchdog(struct timer_list *t) 5213 { 5214 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5215 /* Do the rest outside of interrupt context */ 5216 schedule_work(&adapter->watchdog_task); 5217 } 5218 5219 static void igb_watchdog_task(struct work_struct *work) 5220 { 5221 struct igb_adapter *adapter = container_of(work, 5222 struct igb_adapter, 5223 watchdog_task); 5224 struct e1000_hw *hw = &adapter->hw; 5225 struct e1000_phy_info *phy = &hw->phy; 5226 struct net_device *netdev = adapter->netdev; 5227 u32 link; 5228 int i; 5229 u32 connsw; 5230 u16 phy_data, retry_count = 20; 5231 5232 link = igb_has_link(adapter); 5233 5234 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5235 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5236 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5237 else 5238 link = false; 5239 } 5240 5241 /* Force link down if we have fiber to swap to */ 5242 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5243 if (hw->phy.media_type == e1000_media_type_copper) { 5244 connsw = rd32(E1000_CONNSW); 5245 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5246 link = 0; 5247 } 5248 } 5249 if (link) { 5250 /* Perform a reset if the media type changed. */ 5251 if (hw->dev_spec._82575.media_changed) { 5252 hw->dev_spec._82575.media_changed = false; 5253 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5254 igb_reset(adapter); 5255 } 5256 /* Cancel scheduled suspend requests. */ 5257 pm_runtime_resume(netdev->dev.parent); 5258 5259 if (!netif_carrier_ok(netdev)) { 5260 u32 ctrl; 5261 5262 hw->mac.ops.get_speed_and_duplex(hw, 5263 &adapter->link_speed, 5264 &adapter->link_duplex); 5265 5266 ctrl = rd32(E1000_CTRL); 5267 /* Links status message must follow this format */ 5268 netdev_info(netdev, 5269 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5270 netdev->name, 5271 adapter->link_speed, 5272 adapter->link_duplex == FULL_DUPLEX ? 5273 "Full" : "Half", 5274 (ctrl & E1000_CTRL_TFCE) && 5275 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5276 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5277 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5278 5279 /* disable EEE if enabled */ 5280 if ((adapter->flags & IGB_FLAG_EEE) && 5281 (adapter->link_duplex == HALF_DUPLEX)) { 5282 dev_info(&adapter->pdev->dev, 5283 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5284 adapter->hw.dev_spec._82575.eee_disable = true; 5285 adapter->flags &= ~IGB_FLAG_EEE; 5286 } 5287 5288 /* check if SmartSpeed worked */ 5289 igb_check_downshift(hw); 5290 if (phy->speed_downgraded) 5291 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5292 5293 /* check for thermal sensor event */ 5294 if (igb_thermal_sensor_event(hw, 5295 E1000_THSTAT_LINK_THROTTLE)) 5296 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5297 5298 /* adjust timeout factor according to speed/duplex */ 5299 adapter->tx_timeout_factor = 1; 5300 switch (adapter->link_speed) { 5301 case SPEED_10: 5302 adapter->tx_timeout_factor = 14; 5303 break; 5304 case SPEED_100: 5305 /* maybe add some timeout factor ? */ 5306 break; 5307 } 5308 5309 if (adapter->link_speed != SPEED_1000) 5310 goto no_wait; 5311 5312 /* wait for Remote receiver status OK */ 5313 retry_read_status: 5314 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5315 &phy_data)) { 5316 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5317 retry_count) { 5318 msleep(100); 5319 retry_count--; 5320 goto retry_read_status; 5321 } else if (!retry_count) { 5322 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5323 } 5324 } else { 5325 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5326 } 5327 no_wait: 5328 netif_carrier_on(netdev); 5329 5330 igb_ping_all_vfs(adapter); 5331 igb_check_vf_rate_limit(adapter); 5332 5333 /* link state has changed, schedule phy info update */ 5334 if (!test_bit(__IGB_DOWN, &adapter->state)) 5335 mod_timer(&adapter->phy_info_timer, 5336 round_jiffies(jiffies + 2 * HZ)); 5337 } 5338 } else { 5339 if (netif_carrier_ok(netdev)) { 5340 adapter->link_speed = 0; 5341 adapter->link_duplex = 0; 5342 5343 /* check for thermal sensor event */ 5344 if (igb_thermal_sensor_event(hw, 5345 E1000_THSTAT_PWR_DOWN)) { 5346 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5347 } 5348 5349 /* Links status message must follow this format */ 5350 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5351 netdev->name); 5352 netif_carrier_off(netdev); 5353 5354 igb_ping_all_vfs(adapter); 5355 5356 /* link state has changed, schedule phy info update */ 5357 if (!test_bit(__IGB_DOWN, &adapter->state)) 5358 mod_timer(&adapter->phy_info_timer, 5359 round_jiffies(jiffies + 2 * HZ)); 5360 5361 /* link is down, time to check for alternate media */ 5362 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5363 igb_check_swap_media(adapter); 5364 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5365 schedule_work(&adapter->reset_task); 5366 /* return immediately */ 5367 return; 5368 } 5369 } 5370 pm_schedule_suspend(netdev->dev.parent, 5371 MSEC_PER_SEC * 5); 5372 5373 /* also check for alternate media here */ 5374 } else if (!netif_carrier_ok(netdev) && 5375 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5376 igb_check_swap_media(adapter); 5377 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5378 schedule_work(&adapter->reset_task); 5379 /* return immediately */ 5380 return; 5381 } 5382 } 5383 } 5384 5385 spin_lock(&adapter->stats64_lock); 5386 igb_update_stats(adapter); 5387 spin_unlock(&adapter->stats64_lock); 5388 5389 for (i = 0; i < adapter->num_tx_queues; i++) { 5390 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5391 if (!netif_carrier_ok(netdev)) { 5392 /* We've lost link, so the controller stops DMA, 5393 * but we've got queued Tx work that's never going 5394 * to get done, so reset controller to flush Tx. 5395 * (Do the reset outside of interrupt context). 5396 */ 5397 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5398 adapter->tx_timeout_count++; 5399 schedule_work(&adapter->reset_task); 5400 /* return immediately since reset is imminent */ 5401 return; 5402 } 5403 } 5404 5405 /* Force detection of hung controller every watchdog period */ 5406 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5407 } 5408 5409 /* Cause software interrupt to ensure Rx ring is cleaned */ 5410 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5411 u32 eics = 0; 5412 5413 for (i = 0; i < adapter->num_q_vectors; i++) 5414 eics |= adapter->q_vector[i]->eims_value; 5415 wr32(E1000_EICS, eics); 5416 } else { 5417 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5418 } 5419 5420 igb_spoof_check(adapter); 5421 igb_ptp_rx_hang(adapter); 5422 igb_ptp_tx_hang(adapter); 5423 5424 /* Check LVMMC register on i350/i354 only */ 5425 if ((adapter->hw.mac.type == e1000_i350) || 5426 (adapter->hw.mac.type == e1000_i354)) 5427 igb_check_lvmmc(adapter); 5428 5429 /* Reset the timer */ 5430 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5431 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5432 mod_timer(&adapter->watchdog_timer, 5433 round_jiffies(jiffies + HZ)); 5434 else 5435 mod_timer(&adapter->watchdog_timer, 5436 round_jiffies(jiffies + 2 * HZ)); 5437 } 5438 } 5439 5440 enum latency_range { 5441 lowest_latency = 0, 5442 low_latency = 1, 5443 bulk_latency = 2, 5444 latency_invalid = 255 5445 }; 5446 5447 /** 5448 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5449 * @q_vector: pointer to q_vector 5450 * 5451 * Stores a new ITR value based on strictly on packet size. This 5452 * algorithm is less sophisticated than that used in igb_update_itr, 5453 * due to the difficulty of synchronizing statistics across multiple 5454 * receive rings. The divisors and thresholds used by this function 5455 * were determined based on theoretical maximum wire speed and testing 5456 * data, in order to minimize response time while increasing bulk 5457 * throughput. 5458 * This functionality is controlled by ethtool's coalescing settings. 5459 * NOTE: This function is called only when operating in a multiqueue 5460 * receive environment. 5461 **/ 5462 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5463 { 5464 int new_val = q_vector->itr_val; 5465 int avg_wire_size = 0; 5466 struct igb_adapter *adapter = q_vector->adapter; 5467 unsigned int packets; 5468 5469 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5470 * ints/sec - ITR timer value of 120 ticks. 5471 */ 5472 if (adapter->link_speed != SPEED_1000) { 5473 new_val = IGB_4K_ITR; 5474 goto set_itr_val; 5475 } 5476 5477 packets = q_vector->rx.total_packets; 5478 if (packets) 5479 avg_wire_size = q_vector->rx.total_bytes / packets; 5480 5481 packets = q_vector->tx.total_packets; 5482 if (packets) 5483 avg_wire_size = max_t(u32, avg_wire_size, 5484 q_vector->tx.total_bytes / packets); 5485 5486 /* if avg_wire_size isn't set no work was done */ 5487 if (!avg_wire_size) 5488 goto clear_counts; 5489 5490 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5491 avg_wire_size += 24; 5492 5493 /* Don't starve jumbo frames */ 5494 avg_wire_size = min(avg_wire_size, 3000); 5495 5496 /* Give a little boost to mid-size frames */ 5497 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5498 new_val = avg_wire_size / 3; 5499 else 5500 new_val = avg_wire_size / 2; 5501 5502 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5503 if (new_val < IGB_20K_ITR && 5504 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5505 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5506 new_val = IGB_20K_ITR; 5507 5508 set_itr_val: 5509 if (new_val != q_vector->itr_val) { 5510 q_vector->itr_val = new_val; 5511 q_vector->set_itr = 1; 5512 } 5513 clear_counts: 5514 q_vector->rx.total_bytes = 0; 5515 q_vector->rx.total_packets = 0; 5516 q_vector->tx.total_bytes = 0; 5517 q_vector->tx.total_packets = 0; 5518 } 5519 5520 /** 5521 * igb_update_itr - update the dynamic ITR value based on statistics 5522 * @q_vector: pointer to q_vector 5523 * @ring_container: ring info to update the itr for 5524 * 5525 * Stores a new ITR value based on packets and byte 5526 * counts during the last interrupt. The advantage of per interrupt 5527 * computation is faster updates and more accurate ITR for the current 5528 * traffic pattern. Constants in this function were computed 5529 * based on theoretical maximum wire speed and thresholds were set based 5530 * on testing data as well as attempting to minimize response time 5531 * while increasing bulk throughput. 5532 * This functionality is controlled by ethtool's coalescing settings. 5533 * NOTE: These calculations are only valid when operating in a single- 5534 * queue environment. 5535 **/ 5536 static void igb_update_itr(struct igb_q_vector *q_vector, 5537 struct igb_ring_container *ring_container) 5538 { 5539 unsigned int packets = ring_container->total_packets; 5540 unsigned int bytes = ring_container->total_bytes; 5541 u8 itrval = ring_container->itr; 5542 5543 /* no packets, exit with status unchanged */ 5544 if (packets == 0) 5545 return; 5546 5547 switch (itrval) { 5548 case lowest_latency: 5549 /* handle TSO and jumbo frames */ 5550 if (bytes/packets > 8000) 5551 itrval = bulk_latency; 5552 else if ((packets < 5) && (bytes > 512)) 5553 itrval = low_latency; 5554 break; 5555 case low_latency: /* 50 usec aka 20000 ints/s */ 5556 if (bytes > 10000) { 5557 /* this if handles the TSO accounting */ 5558 if (bytes/packets > 8000) 5559 itrval = bulk_latency; 5560 else if ((packets < 10) || ((bytes/packets) > 1200)) 5561 itrval = bulk_latency; 5562 else if ((packets > 35)) 5563 itrval = lowest_latency; 5564 } else if (bytes/packets > 2000) { 5565 itrval = bulk_latency; 5566 } else if (packets <= 2 && bytes < 512) { 5567 itrval = lowest_latency; 5568 } 5569 break; 5570 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5571 if (bytes > 25000) { 5572 if (packets > 35) 5573 itrval = low_latency; 5574 } else if (bytes < 1500) { 5575 itrval = low_latency; 5576 } 5577 break; 5578 } 5579 5580 /* clear work counters since we have the values we need */ 5581 ring_container->total_bytes = 0; 5582 ring_container->total_packets = 0; 5583 5584 /* write updated itr to ring container */ 5585 ring_container->itr = itrval; 5586 } 5587 5588 static void igb_set_itr(struct igb_q_vector *q_vector) 5589 { 5590 struct igb_adapter *adapter = q_vector->adapter; 5591 u32 new_itr = q_vector->itr_val; 5592 u8 current_itr = 0; 5593 5594 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5595 if (adapter->link_speed != SPEED_1000) { 5596 current_itr = 0; 5597 new_itr = IGB_4K_ITR; 5598 goto set_itr_now; 5599 } 5600 5601 igb_update_itr(q_vector, &q_vector->tx); 5602 igb_update_itr(q_vector, &q_vector->rx); 5603 5604 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5605 5606 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5607 if (current_itr == lowest_latency && 5608 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5609 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5610 current_itr = low_latency; 5611 5612 switch (current_itr) { 5613 /* counts and packets in update_itr are dependent on these numbers */ 5614 case lowest_latency: 5615 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5616 break; 5617 case low_latency: 5618 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5619 break; 5620 case bulk_latency: 5621 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5622 break; 5623 default: 5624 break; 5625 } 5626 5627 set_itr_now: 5628 if (new_itr != q_vector->itr_val) { 5629 /* this attempts to bias the interrupt rate towards Bulk 5630 * by adding intermediate steps when interrupt rate is 5631 * increasing 5632 */ 5633 new_itr = new_itr > q_vector->itr_val ? 5634 max((new_itr * q_vector->itr_val) / 5635 (new_itr + (q_vector->itr_val >> 2)), 5636 new_itr) : new_itr; 5637 /* Don't write the value here; it resets the adapter's 5638 * internal timer, and causes us to delay far longer than 5639 * we should between interrupts. Instead, we write the ITR 5640 * value at the beginning of the next interrupt so the timing 5641 * ends up being correct. 5642 */ 5643 q_vector->itr_val = new_itr; 5644 q_vector->set_itr = 1; 5645 } 5646 } 5647 5648 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5649 struct igb_tx_buffer *first, 5650 u32 vlan_macip_lens, u32 type_tucmd, 5651 u32 mss_l4len_idx) 5652 { 5653 struct e1000_adv_tx_context_desc *context_desc; 5654 u16 i = tx_ring->next_to_use; 5655 struct timespec64 ts; 5656 5657 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5658 5659 i++; 5660 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5661 5662 /* set bits to identify this as an advanced context descriptor */ 5663 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5664 5665 /* For 82575, context index must be unique per ring. */ 5666 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5667 mss_l4len_idx |= tx_ring->reg_idx << 4; 5668 5669 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5670 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5671 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5672 5673 /* We assume there is always a valid tx time available. Invalid times 5674 * should have been handled by the upper layers. 5675 */ 5676 if (tx_ring->launchtime_enable) { 5677 ts = ns_to_timespec64(first->skb->tstamp); 5678 first->skb->tstamp = 0; 5679 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5680 } else { 5681 context_desc->seqnum_seed = 0; 5682 } 5683 } 5684 5685 static int igb_tso(struct igb_ring *tx_ring, 5686 struct igb_tx_buffer *first, 5687 u8 *hdr_len) 5688 { 5689 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5690 struct sk_buff *skb = first->skb; 5691 union { 5692 struct iphdr *v4; 5693 struct ipv6hdr *v6; 5694 unsigned char *hdr; 5695 } ip; 5696 union { 5697 struct tcphdr *tcp; 5698 unsigned char *hdr; 5699 } l4; 5700 u32 paylen, l4_offset; 5701 int err; 5702 5703 if (skb->ip_summed != CHECKSUM_PARTIAL) 5704 return 0; 5705 5706 if (!skb_is_gso(skb)) 5707 return 0; 5708 5709 err = skb_cow_head(skb, 0); 5710 if (err < 0) 5711 return err; 5712 5713 ip.hdr = skb_network_header(skb); 5714 l4.hdr = skb_checksum_start(skb); 5715 5716 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5717 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5718 5719 /* initialize outer IP header fields */ 5720 if (ip.v4->version == 4) { 5721 unsigned char *csum_start = skb_checksum_start(skb); 5722 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5723 5724 /* IP header will have to cancel out any data that 5725 * is not a part of the outer IP header 5726 */ 5727 ip.v4->check = csum_fold(csum_partial(trans_start, 5728 csum_start - trans_start, 5729 0)); 5730 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5731 5732 ip.v4->tot_len = 0; 5733 first->tx_flags |= IGB_TX_FLAGS_TSO | 5734 IGB_TX_FLAGS_CSUM | 5735 IGB_TX_FLAGS_IPV4; 5736 } else { 5737 ip.v6->payload_len = 0; 5738 first->tx_flags |= IGB_TX_FLAGS_TSO | 5739 IGB_TX_FLAGS_CSUM; 5740 } 5741 5742 /* determine offset of inner transport header */ 5743 l4_offset = l4.hdr - skb->data; 5744 5745 /* compute length of segmentation header */ 5746 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5747 5748 /* remove payload length from inner checksum */ 5749 paylen = skb->len - l4_offset; 5750 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5751 5752 /* update gso size and bytecount with header size */ 5753 first->gso_segs = skb_shinfo(skb)->gso_segs; 5754 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5755 5756 /* MSS L4LEN IDX */ 5757 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5758 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5759 5760 /* VLAN MACLEN IPLEN */ 5761 vlan_macip_lens = l4.hdr - ip.hdr; 5762 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5763 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5764 5765 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5766 type_tucmd, mss_l4len_idx); 5767 5768 return 1; 5769 } 5770 5771 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5772 { 5773 unsigned int offset = 0; 5774 5775 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5776 5777 return offset == skb_checksum_start_offset(skb); 5778 } 5779 5780 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5781 { 5782 struct sk_buff *skb = first->skb; 5783 u32 vlan_macip_lens = 0; 5784 u32 type_tucmd = 0; 5785 5786 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5787 csum_failed: 5788 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5789 !tx_ring->launchtime_enable) 5790 return; 5791 goto no_csum; 5792 } 5793 5794 switch (skb->csum_offset) { 5795 case offsetof(struct tcphdr, check): 5796 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5797 /* fall through */ 5798 case offsetof(struct udphdr, check): 5799 break; 5800 case offsetof(struct sctphdr, checksum): 5801 /* validate that this is actually an SCTP request */ 5802 if (((first->protocol == htons(ETH_P_IP)) && 5803 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5804 ((first->protocol == htons(ETH_P_IPV6)) && 5805 igb_ipv6_csum_is_sctp(skb))) { 5806 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5807 break; 5808 } 5809 /* fall through */ 5810 default: 5811 skb_checksum_help(skb); 5812 goto csum_failed; 5813 } 5814 5815 /* update TX checksum flag */ 5816 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5817 vlan_macip_lens = skb_checksum_start_offset(skb) - 5818 skb_network_offset(skb); 5819 no_csum: 5820 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5821 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5822 5823 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 5824 } 5825 5826 #define IGB_SET_FLAG(_input, _flag, _result) \ 5827 ((_flag <= _result) ? \ 5828 ((u32)(_input & _flag) * (_result / _flag)) : \ 5829 ((u32)(_input & _flag) / (_flag / _result))) 5830 5831 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5832 { 5833 /* set type for advanced descriptor with frame checksum insertion */ 5834 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5835 E1000_ADVTXD_DCMD_DEXT | 5836 E1000_ADVTXD_DCMD_IFCS; 5837 5838 /* set HW vlan bit if vlan is present */ 5839 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5840 (E1000_ADVTXD_DCMD_VLE)); 5841 5842 /* set segmentation bits for TSO */ 5843 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5844 (E1000_ADVTXD_DCMD_TSE)); 5845 5846 /* set timestamp bit if present */ 5847 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5848 (E1000_ADVTXD_MAC_TSTAMP)); 5849 5850 /* insert frame checksum */ 5851 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5852 5853 return cmd_type; 5854 } 5855 5856 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5857 union e1000_adv_tx_desc *tx_desc, 5858 u32 tx_flags, unsigned int paylen) 5859 { 5860 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5861 5862 /* 82575 requires a unique index per ring */ 5863 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5864 olinfo_status |= tx_ring->reg_idx << 4; 5865 5866 /* insert L4 checksum */ 5867 olinfo_status |= IGB_SET_FLAG(tx_flags, 5868 IGB_TX_FLAGS_CSUM, 5869 (E1000_TXD_POPTS_TXSM << 8)); 5870 5871 /* insert IPv4 checksum */ 5872 olinfo_status |= IGB_SET_FLAG(tx_flags, 5873 IGB_TX_FLAGS_IPV4, 5874 (E1000_TXD_POPTS_IXSM << 8)); 5875 5876 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5877 } 5878 5879 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5880 { 5881 struct net_device *netdev = tx_ring->netdev; 5882 5883 netif_stop_subqueue(netdev, tx_ring->queue_index); 5884 5885 /* Herbert's original patch had: 5886 * smp_mb__after_netif_stop_queue(); 5887 * but since that doesn't exist yet, just open code it. 5888 */ 5889 smp_mb(); 5890 5891 /* We need to check again in a case another CPU has just 5892 * made room available. 5893 */ 5894 if (igb_desc_unused(tx_ring) < size) 5895 return -EBUSY; 5896 5897 /* A reprieve! */ 5898 netif_wake_subqueue(netdev, tx_ring->queue_index); 5899 5900 u64_stats_update_begin(&tx_ring->tx_syncp2); 5901 tx_ring->tx_stats.restart_queue2++; 5902 u64_stats_update_end(&tx_ring->tx_syncp2); 5903 5904 return 0; 5905 } 5906 5907 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5908 { 5909 if (igb_desc_unused(tx_ring) >= size) 5910 return 0; 5911 return __igb_maybe_stop_tx(tx_ring, size); 5912 } 5913 5914 static int igb_tx_map(struct igb_ring *tx_ring, 5915 struct igb_tx_buffer *first, 5916 const u8 hdr_len) 5917 { 5918 struct sk_buff *skb = first->skb; 5919 struct igb_tx_buffer *tx_buffer; 5920 union e1000_adv_tx_desc *tx_desc; 5921 skb_frag_t *frag; 5922 dma_addr_t dma; 5923 unsigned int data_len, size; 5924 u32 tx_flags = first->tx_flags; 5925 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5926 u16 i = tx_ring->next_to_use; 5927 5928 tx_desc = IGB_TX_DESC(tx_ring, i); 5929 5930 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5931 5932 size = skb_headlen(skb); 5933 data_len = skb->data_len; 5934 5935 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5936 5937 tx_buffer = first; 5938 5939 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5940 if (dma_mapping_error(tx_ring->dev, dma)) 5941 goto dma_error; 5942 5943 /* record length, and DMA address */ 5944 dma_unmap_len_set(tx_buffer, len, size); 5945 dma_unmap_addr_set(tx_buffer, dma, dma); 5946 5947 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5948 5949 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5950 tx_desc->read.cmd_type_len = 5951 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5952 5953 i++; 5954 tx_desc++; 5955 if (i == tx_ring->count) { 5956 tx_desc = IGB_TX_DESC(tx_ring, 0); 5957 i = 0; 5958 } 5959 tx_desc->read.olinfo_status = 0; 5960 5961 dma += IGB_MAX_DATA_PER_TXD; 5962 size -= IGB_MAX_DATA_PER_TXD; 5963 5964 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5965 } 5966 5967 if (likely(!data_len)) 5968 break; 5969 5970 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5971 5972 i++; 5973 tx_desc++; 5974 if (i == tx_ring->count) { 5975 tx_desc = IGB_TX_DESC(tx_ring, 0); 5976 i = 0; 5977 } 5978 tx_desc->read.olinfo_status = 0; 5979 5980 size = skb_frag_size(frag); 5981 data_len -= size; 5982 5983 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5984 size, DMA_TO_DEVICE); 5985 5986 tx_buffer = &tx_ring->tx_buffer_info[i]; 5987 } 5988 5989 /* write last descriptor with RS and EOP bits */ 5990 cmd_type |= size | IGB_TXD_DCMD; 5991 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5992 5993 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5994 5995 /* set the timestamp */ 5996 first->time_stamp = jiffies; 5997 5998 skb_tx_timestamp(skb); 5999 6000 /* Force memory writes to complete before letting h/w know there 6001 * are new descriptors to fetch. (Only applicable for weak-ordered 6002 * memory model archs, such as IA-64). 6003 * 6004 * We also need this memory barrier to make certain all of the 6005 * status bits have been updated before next_to_watch is written. 6006 */ 6007 dma_wmb(); 6008 6009 /* set next_to_watch value indicating a packet is present */ 6010 first->next_to_watch = tx_desc; 6011 6012 i++; 6013 if (i == tx_ring->count) 6014 i = 0; 6015 6016 tx_ring->next_to_use = i; 6017 6018 /* Make sure there is space in the ring for the next send. */ 6019 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6020 6021 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6022 writel(i, tx_ring->tail); 6023 } 6024 return 0; 6025 6026 dma_error: 6027 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6028 tx_buffer = &tx_ring->tx_buffer_info[i]; 6029 6030 /* clear dma mappings for failed tx_buffer_info map */ 6031 while (tx_buffer != first) { 6032 if (dma_unmap_len(tx_buffer, len)) 6033 dma_unmap_page(tx_ring->dev, 6034 dma_unmap_addr(tx_buffer, dma), 6035 dma_unmap_len(tx_buffer, len), 6036 DMA_TO_DEVICE); 6037 dma_unmap_len_set(tx_buffer, len, 0); 6038 6039 if (i-- == 0) 6040 i += tx_ring->count; 6041 tx_buffer = &tx_ring->tx_buffer_info[i]; 6042 } 6043 6044 if (dma_unmap_len(tx_buffer, len)) 6045 dma_unmap_single(tx_ring->dev, 6046 dma_unmap_addr(tx_buffer, dma), 6047 dma_unmap_len(tx_buffer, len), 6048 DMA_TO_DEVICE); 6049 dma_unmap_len_set(tx_buffer, len, 0); 6050 6051 dev_kfree_skb_any(tx_buffer->skb); 6052 tx_buffer->skb = NULL; 6053 6054 tx_ring->next_to_use = i; 6055 6056 return -1; 6057 } 6058 6059 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6060 struct igb_ring *tx_ring) 6061 { 6062 struct igb_tx_buffer *first; 6063 int tso; 6064 u32 tx_flags = 0; 6065 unsigned short f; 6066 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6067 __be16 protocol = vlan_get_protocol(skb); 6068 u8 hdr_len = 0; 6069 6070 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6071 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6072 * + 2 desc gap to keep tail from touching head, 6073 * + 1 desc for context descriptor, 6074 * otherwise try next time 6075 */ 6076 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6077 count += TXD_USE_COUNT(skb_frag_size( 6078 &skb_shinfo(skb)->frags[f])); 6079 6080 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6081 /* this is a hard error */ 6082 return NETDEV_TX_BUSY; 6083 } 6084 6085 /* record the location of the first descriptor for this packet */ 6086 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6087 first->skb = skb; 6088 first->bytecount = skb->len; 6089 first->gso_segs = 1; 6090 6091 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6092 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6093 6094 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6095 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6096 &adapter->state)) { 6097 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6098 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6099 6100 adapter->ptp_tx_skb = skb_get(skb); 6101 adapter->ptp_tx_start = jiffies; 6102 if (adapter->hw.mac.type == e1000_82576) 6103 schedule_work(&adapter->ptp_tx_work); 6104 } else { 6105 adapter->tx_hwtstamp_skipped++; 6106 } 6107 } 6108 6109 if (skb_vlan_tag_present(skb)) { 6110 tx_flags |= IGB_TX_FLAGS_VLAN; 6111 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6112 } 6113 6114 /* record initial flags and protocol */ 6115 first->tx_flags = tx_flags; 6116 first->protocol = protocol; 6117 6118 tso = igb_tso(tx_ring, first, &hdr_len); 6119 if (tso < 0) 6120 goto out_drop; 6121 else if (!tso) 6122 igb_tx_csum(tx_ring, first); 6123 6124 if (igb_tx_map(tx_ring, first, hdr_len)) 6125 goto cleanup_tx_tstamp; 6126 6127 return NETDEV_TX_OK; 6128 6129 out_drop: 6130 dev_kfree_skb_any(first->skb); 6131 first->skb = NULL; 6132 cleanup_tx_tstamp: 6133 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6134 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6135 6136 dev_kfree_skb_any(adapter->ptp_tx_skb); 6137 adapter->ptp_tx_skb = NULL; 6138 if (adapter->hw.mac.type == e1000_82576) 6139 cancel_work_sync(&adapter->ptp_tx_work); 6140 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6141 } 6142 6143 return NETDEV_TX_OK; 6144 } 6145 6146 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6147 struct sk_buff *skb) 6148 { 6149 unsigned int r_idx = skb->queue_mapping; 6150 6151 if (r_idx >= adapter->num_tx_queues) 6152 r_idx = r_idx % adapter->num_tx_queues; 6153 6154 return adapter->tx_ring[r_idx]; 6155 } 6156 6157 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6158 struct net_device *netdev) 6159 { 6160 struct igb_adapter *adapter = netdev_priv(netdev); 6161 6162 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6163 * in order to meet this minimum size requirement. 6164 */ 6165 if (skb_put_padto(skb, 17)) 6166 return NETDEV_TX_OK; 6167 6168 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6169 } 6170 6171 /** 6172 * igb_tx_timeout - Respond to a Tx Hang 6173 * @netdev: network interface device structure 6174 **/ 6175 static void igb_tx_timeout(struct net_device *netdev) 6176 { 6177 struct igb_adapter *adapter = netdev_priv(netdev); 6178 struct e1000_hw *hw = &adapter->hw; 6179 6180 /* Do the reset outside of interrupt context */ 6181 adapter->tx_timeout_count++; 6182 6183 if (hw->mac.type >= e1000_82580) 6184 hw->dev_spec._82575.global_device_reset = true; 6185 6186 schedule_work(&adapter->reset_task); 6187 wr32(E1000_EICS, 6188 (adapter->eims_enable_mask & ~adapter->eims_other)); 6189 } 6190 6191 static void igb_reset_task(struct work_struct *work) 6192 { 6193 struct igb_adapter *adapter; 6194 adapter = container_of(work, struct igb_adapter, reset_task); 6195 6196 igb_dump(adapter); 6197 netdev_err(adapter->netdev, "Reset adapter\n"); 6198 igb_reinit_locked(adapter); 6199 } 6200 6201 /** 6202 * igb_get_stats64 - Get System Network Statistics 6203 * @netdev: network interface device structure 6204 * @stats: rtnl_link_stats64 pointer 6205 **/ 6206 static void igb_get_stats64(struct net_device *netdev, 6207 struct rtnl_link_stats64 *stats) 6208 { 6209 struct igb_adapter *adapter = netdev_priv(netdev); 6210 6211 spin_lock(&adapter->stats64_lock); 6212 igb_update_stats(adapter); 6213 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6214 spin_unlock(&adapter->stats64_lock); 6215 } 6216 6217 /** 6218 * igb_change_mtu - Change the Maximum Transfer Unit 6219 * @netdev: network interface device structure 6220 * @new_mtu: new value for maximum frame size 6221 * 6222 * Returns 0 on success, negative on failure 6223 **/ 6224 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6225 { 6226 struct igb_adapter *adapter = netdev_priv(netdev); 6227 struct pci_dev *pdev = adapter->pdev; 6228 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6229 6230 /* adjust max frame to be at least the size of a standard frame */ 6231 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6232 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6233 6234 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6235 usleep_range(1000, 2000); 6236 6237 /* igb_down has a dependency on max_frame_size */ 6238 adapter->max_frame_size = max_frame; 6239 6240 if (netif_running(netdev)) 6241 igb_down(adapter); 6242 6243 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 6244 netdev->mtu, new_mtu); 6245 netdev->mtu = new_mtu; 6246 6247 if (netif_running(netdev)) 6248 igb_up(adapter); 6249 else 6250 igb_reset(adapter); 6251 6252 clear_bit(__IGB_RESETTING, &adapter->state); 6253 6254 return 0; 6255 } 6256 6257 /** 6258 * igb_update_stats - Update the board statistics counters 6259 * @adapter: board private structure 6260 **/ 6261 void igb_update_stats(struct igb_adapter *adapter) 6262 { 6263 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6264 struct e1000_hw *hw = &adapter->hw; 6265 struct pci_dev *pdev = adapter->pdev; 6266 u32 reg, mpc; 6267 int i; 6268 u64 bytes, packets; 6269 unsigned int start; 6270 u64 _bytes, _packets; 6271 6272 /* Prevent stats update while adapter is being reset, or if the pci 6273 * connection is down. 6274 */ 6275 if (adapter->link_speed == 0) 6276 return; 6277 if (pci_channel_offline(pdev)) 6278 return; 6279 6280 bytes = 0; 6281 packets = 0; 6282 6283 rcu_read_lock(); 6284 for (i = 0; i < adapter->num_rx_queues; i++) { 6285 struct igb_ring *ring = adapter->rx_ring[i]; 6286 u32 rqdpc = rd32(E1000_RQDPC(i)); 6287 if (hw->mac.type >= e1000_i210) 6288 wr32(E1000_RQDPC(i), 0); 6289 6290 if (rqdpc) { 6291 ring->rx_stats.drops += rqdpc; 6292 net_stats->rx_fifo_errors += rqdpc; 6293 } 6294 6295 do { 6296 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6297 _bytes = ring->rx_stats.bytes; 6298 _packets = ring->rx_stats.packets; 6299 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6300 bytes += _bytes; 6301 packets += _packets; 6302 } 6303 6304 net_stats->rx_bytes = bytes; 6305 net_stats->rx_packets = packets; 6306 6307 bytes = 0; 6308 packets = 0; 6309 for (i = 0; i < adapter->num_tx_queues; i++) { 6310 struct igb_ring *ring = adapter->tx_ring[i]; 6311 do { 6312 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6313 _bytes = ring->tx_stats.bytes; 6314 _packets = ring->tx_stats.packets; 6315 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6316 bytes += _bytes; 6317 packets += _packets; 6318 } 6319 net_stats->tx_bytes = bytes; 6320 net_stats->tx_packets = packets; 6321 rcu_read_unlock(); 6322 6323 /* read stats registers */ 6324 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6325 adapter->stats.gprc += rd32(E1000_GPRC); 6326 adapter->stats.gorc += rd32(E1000_GORCL); 6327 rd32(E1000_GORCH); /* clear GORCL */ 6328 adapter->stats.bprc += rd32(E1000_BPRC); 6329 adapter->stats.mprc += rd32(E1000_MPRC); 6330 adapter->stats.roc += rd32(E1000_ROC); 6331 6332 adapter->stats.prc64 += rd32(E1000_PRC64); 6333 adapter->stats.prc127 += rd32(E1000_PRC127); 6334 adapter->stats.prc255 += rd32(E1000_PRC255); 6335 adapter->stats.prc511 += rd32(E1000_PRC511); 6336 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6337 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6338 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6339 adapter->stats.sec += rd32(E1000_SEC); 6340 6341 mpc = rd32(E1000_MPC); 6342 adapter->stats.mpc += mpc; 6343 net_stats->rx_fifo_errors += mpc; 6344 adapter->stats.scc += rd32(E1000_SCC); 6345 adapter->stats.ecol += rd32(E1000_ECOL); 6346 adapter->stats.mcc += rd32(E1000_MCC); 6347 adapter->stats.latecol += rd32(E1000_LATECOL); 6348 adapter->stats.dc += rd32(E1000_DC); 6349 adapter->stats.rlec += rd32(E1000_RLEC); 6350 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6351 adapter->stats.xontxc += rd32(E1000_XONTXC); 6352 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6353 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6354 adapter->stats.fcruc += rd32(E1000_FCRUC); 6355 adapter->stats.gptc += rd32(E1000_GPTC); 6356 adapter->stats.gotc += rd32(E1000_GOTCL); 6357 rd32(E1000_GOTCH); /* clear GOTCL */ 6358 adapter->stats.rnbc += rd32(E1000_RNBC); 6359 adapter->stats.ruc += rd32(E1000_RUC); 6360 adapter->stats.rfc += rd32(E1000_RFC); 6361 adapter->stats.rjc += rd32(E1000_RJC); 6362 adapter->stats.tor += rd32(E1000_TORH); 6363 adapter->stats.tot += rd32(E1000_TOTH); 6364 adapter->stats.tpr += rd32(E1000_TPR); 6365 6366 adapter->stats.ptc64 += rd32(E1000_PTC64); 6367 adapter->stats.ptc127 += rd32(E1000_PTC127); 6368 adapter->stats.ptc255 += rd32(E1000_PTC255); 6369 adapter->stats.ptc511 += rd32(E1000_PTC511); 6370 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6371 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6372 6373 adapter->stats.mptc += rd32(E1000_MPTC); 6374 adapter->stats.bptc += rd32(E1000_BPTC); 6375 6376 adapter->stats.tpt += rd32(E1000_TPT); 6377 adapter->stats.colc += rd32(E1000_COLC); 6378 6379 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6380 /* read internal phy specific stats */ 6381 reg = rd32(E1000_CTRL_EXT); 6382 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6383 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6384 6385 /* this stat has invalid values on i210/i211 */ 6386 if ((hw->mac.type != e1000_i210) && 6387 (hw->mac.type != e1000_i211)) 6388 adapter->stats.tncrs += rd32(E1000_TNCRS); 6389 } 6390 6391 adapter->stats.tsctc += rd32(E1000_TSCTC); 6392 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6393 6394 adapter->stats.iac += rd32(E1000_IAC); 6395 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6396 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6397 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6398 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6399 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6400 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6401 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6402 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6403 6404 /* Fill out the OS statistics structure */ 6405 net_stats->multicast = adapter->stats.mprc; 6406 net_stats->collisions = adapter->stats.colc; 6407 6408 /* Rx Errors */ 6409 6410 /* RLEC on some newer hardware can be incorrect so build 6411 * our own version based on RUC and ROC 6412 */ 6413 net_stats->rx_errors = adapter->stats.rxerrc + 6414 adapter->stats.crcerrs + adapter->stats.algnerrc + 6415 adapter->stats.ruc + adapter->stats.roc + 6416 adapter->stats.cexterr; 6417 net_stats->rx_length_errors = adapter->stats.ruc + 6418 adapter->stats.roc; 6419 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6420 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6421 net_stats->rx_missed_errors = adapter->stats.mpc; 6422 6423 /* Tx Errors */ 6424 net_stats->tx_errors = adapter->stats.ecol + 6425 adapter->stats.latecol; 6426 net_stats->tx_aborted_errors = adapter->stats.ecol; 6427 net_stats->tx_window_errors = adapter->stats.latecol; 6428 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6429 6430 /* Tx Dropped needs to be maintained elsewhere */ 6431 6432 /* Management Stats */ 6433 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6434 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6435 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6436 6437 /* OS2BMC Stats */ 6438 reg = rd32(E1000_MANC); 6439 if (reg & E1000_MANC_EN_BMC2OS) { 6440 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6441 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6442 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6443 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6444 } 6445 } 6446 6447 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6448 { 6449 struct e1000_hw *hw = &adapter->hw; 6450 struct ptp_clock_event event; 6451 struct timespec64 ts; 6452 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6453 6454 if (tsicr & TSINTR_SYS_WRAP) { 6455 event.type = PTP_CLOCK_PPS; 6456 if (adapter->ptp_caps.pps) 6457 ptp_clock_event(adapter->ptp_clock, &event); 6458 ack |= TSINTR_SYS_WRAP; 6459 } 6460 6461 if (tsicr & E1000_TSICR_TXTS) { 6462 /* retrieve hardware timestamp */ 6463 schedule_work(&adapter->ptp_tx_work); 6464 ack |= E1000_TSICR_TXTS; 6465 } 6466 6467 if (tsicr & TSINTR_TT0) { 6468 spin_lock(&adapter->tmreg_lock); 6469 ts = timespec64_add(adapter->perout[0].start, 6470 adapter->perout[0].period); 6471 /* u32 conversion of tv_sec is safe until y2106 */ 6472 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6473 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6474 tsauxc = rd32(E1000_TSAUXC); 6475 tsauxc |= TSAUXC_EN_TT0; 6476 wr32(E1000_TSAUXC, tsauxc); 6477 adapter->perout[0].start = ts; 6478 spin_unlock(&adapter->tmreg_lock); 6479 ack |= TSINTR_TT0; 6480 } 6481 6482 if (tsicr & TSINTR_TT1) { 6483 spin_lock(&adapter->tmreg_lock); 6484 ts = timespec64_add(adapter->perout[1].start, 6485 adapter->perout[1].period); 6486 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6487 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6488 tsauxc = rd32(E1000_TSAUXC); 6489 tsauxc |= TSAUXC_EN_TT1; 6490 wr32(E1000_TSAUXC, tsauxc); 6491 adapter->perout[1].start = ts; 6492 spin_unlock(&adapter->tmreg_lock); 6493 ack |= TSINTR_TT1; 6494 } 6495 6496 if (tsicr & TSINTR_AUTT0) { 6497 nsec = rd32(E1000_AUXSTMPL0); 6498 sec = rd32(E1000_AUXSTMPH0); 6499 event.type = PTP_CLOCK_EXTTS; 6500 event.index = 0; 6501 event.timestamp = sec * 1000000000ULL + nsec; 6502 ptp_clock_event(adapter->ptp_clock, &event); 6503 ack |= TSINTR_AUTT0; 6504 } 6505 6506 if (tsicr & TSINTR_AUTT1) { 6507 nsec = rd32(E1000_AUXSTMPL1); 6508 sec = rd32(E1000_AUXSTMPH1); 6509 event.type = PTP_CLOCK_EXTTS; 6510 event.index = 1; 6511 event.timestamp = sec * 1000000000ULL + nsec; 6512 ptp_clock_event(adapter->ptp_clock, &event); 6513 ack |= TSINTR_AUTT1; 6514 } 6515 6516 /* acknowledge the interrupts */ 6517 wr32(E1000_TSICR, ack); 6518 } 6519 6520 static irqreturn_t igb_msix_other(int irq, void *data) 6521 { 6522 struct igb_adapter *adapter = data; 6523 struct e1000_hw *hw = &adapter->hw; 6524 u32 icr = rd32(E1000_ICR); 6525 /* reading ICR causes bit 31 of EICR to be cleared */ 6526 6527 if (icr & E1000_ICR_DRSTA) 6528 schedule_work(&adapter->reset_task); 6529 6530 if (icr & E1000_ICR_DOUTSYNC) { 6531 /* HW is reporting DMA is out of sync */ 6532 adapter->stats.doosync++; 6533 /* The DMA Out of Sync is also indication of a spoof event 6534 * in IOV mode. Check the Wrong VM Behavior register to 6535 * see if it is really a spoof event. 6536 */ 6537 igb_check_wvbr(adapter); 6538 } 6539 6540 /* Check for a mailbox event */ 6541 if (icr & E1000_ICR_VMMB) 6542 igb_msg_task(adapter); 6543 6544 if (icr & E1000_ICR_LSC) { 6545 hw->mac.get_link_status = 1; 6546 /* guard against interrupt when we're going down */ 6547 if (!test_bit(__IGB_DOWN, &adapter->state)) 6548 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6549 } 6550 6551 if (icr & E1000_ICR_TS) 6552 igb_tsync_interrupt(adapter); 6553 6554 wr32(E1000_EIMS, adapter->eims_other); 6555 6556 return IRQ_HANDLED; 6557 } 6558 6559 static void igb_write_itr(struct igb_q_vector *q_vector) 6560 { 6561 struct igb_adapter *adapter = q_vector->adapter; 6562 u32 itr_val = q_vector->itr_val & 0x7FFC; 6563 6564 if (!q_vector->set_itr) 6565 return; 6566 6567 if (!itr_val) 6568 itr_val = 0x4; 6569 6570 if (adapter->hw.mac.type == e1000_82575) 6571 itr_val |= itr_val << 16; 6572 else 6573 itr_val |= E1000_EITR_CNT_IGNR; 6574 6575 writel(itr_val, q_vector->itr_register); 6576 q_vector->set_itr = 0; 6577 } 6578 6579 static irqreturn_t igb_msix_ring(int irq, void *data) 6580 { 6581 struct igb_q_vector *q_vector = data; 6582 6583 /* Write the ITR value calculated from the previous interrupt. */ 6584 igb_write_itr(q_vector); 6585 6586 napi_schedule(&q_vector->napi); 6587 6588 return IRQ_HANDLED; 6589 } 6590 6591 #ifdef CONFIG_IGB_DCA 6592 static void igb_update_tx_dca(struct igb_adapter *adapter, 6593 struct igb_ring *tx_ring, 6594 int cpu) 6595 { 6596 struct e1000_hw *hw = &adapter->hw; 6597 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6598 6599 if (hw->mac.type != e1000_82575) 6600 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6601 6602 /* We can enable relaxed ordering for reads, but not writes when 6603 * DCA is enabled. This is due to a known issue in some chipsets 6604 * which will cause the DCA tag to be cleared. 6605 */ 6606 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6607 E1000_DCA_TXCTRL_DATA_RRO_EN | 6608 E1000_DCA_TXCTRL_DESC_DCA_EN; 6609 6610 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6611 } 6612 6613 static void igb_update_rx_dca(struct igb_adapter *adapter, 6614 struct igb_ring *rx_ring, 6615 int cpu) 6616 { 6617 struct e1000_hw *hw = &adapter->hw; 6618 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6619 6620 if (hw->mac.type != e1000_82575) 6621 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6622 6623 /* We can enable relaxed ordering for reads, but not writes when 6624 * DCA is enabled. This is due to a known issue in some chipsets 6625 * which will cause the DCA tag to be cleared. 6626 */ 6627 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6628 E1000_DCA_RXCTRL_DESC_DCA_EN; 6629 6630 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6631 } 6632 6633 static void igb_update_dca(struct igb_q_vector *q_vector) 6634 { 6635 struct igb_adapter *adapter = q_vector->adapter; 6636 int cpu = get_cpu(); 6637 6638 if (q_vector->cpu == cpu) 6639 goto out_no_update; 6640 6641 if (q_vector->tx.ring) 6642 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6643 6644 if (q_vector->rx.ring) 6645 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6646 6647 q_vector->cpu = cpu; 6648 out_no_update: 6649 put_cpu(); 6650 } 6651 6652 static void igb_setup_dca(struct igb_adapter *adapter) 6653 { 6654 struct e1000_hw *hw = &adapter->hw; 6655 int i; 6656 6657 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6658 return; 6659 6660 /* Always use CB2 mode, difference is masked in the CB driver. */ 6661 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6662 6663 for (i = 0; i < adapter->num_q_vectors; i++) { 6664 adapter->q_vector[i]->cpu = -1; 6665 igb_update_dca(adapter->q_vector[i]); 6666 } 6667 } 6668 6669 static int __igb_notify_dca(struct device *dev, void *data) 6670 { 6671 struct net_device *netdev = dev_get_drvdata(dev); 6672 struct igb_adapter *adapter = netdev_priv(netdev); 6673 struct pci_dev *pdev = adapter->pdev; 6674 struct e1000_hw *hw = &adapter->hw; 6675 unsigned long event = *(unsigned long *)data; 6676 6677 switch (event) { 6678 case DCA_PROVIDER_ADD: 6679 /* if already enabled, don't do it again */ 6680 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6681 break; 6682 if (dca_add_requester(dev) == 0) { 6683 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6684 dev_info(&pdev->dev, "DCA enabled\n"); 6685 igb_setup_dca(adapter); 6686 break; 6687 } 6688 /* Fall Through - since DCA is disabled. */ 6689 case DCA_PROVIDER_REMOVE: 6690 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6691 /* without this a class_device is left 6692 * hanging around in the sysfs model 6693 */ 6694 dca_remove_requester(dev); 6695 dev_info(&pdev->dev, "DCA disabled\n"); 6696 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6697 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6698 } 6699 break; 6700 } 6701 6702 return 0; 6703 } 6704 6705 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6706 void *p) 6707 { 6708 int ret_val; 6709 6710 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6711 __igb_notify_dca); 6712 6713 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6714 } 6715 #endif /* CONFIG_IGB_DCA */ 6716 6717 #ifdef CONFIG_PCI_IOV 6718 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6719 { 6720 unsigned char mac_addr[ETH_ALEN]; 6721 6722 eth_zero_addr(mac_addr); 6723 igb_set_vf_mac(adapter, vf, mac_addr); 6724 6725 /* By default spoof check is enabled for all VFs */ 6726 adapter->vf_data[vf].spoofchk_enabled = true; 6727 6728 /* By default VFs are not trusted */ 6729 adapter->vf_data[vf].trusted = false; 6730 6731 return 0; 6732 } 6733 6734 #endif 6735 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6736 { 6737 struct e1000_hw *hw = &adapter->hw; 6738 u32 ping; 6739 int i; 6740 6741 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6742 ping = E1000_PF_CONTROL_MSG; 6743 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6744 ping |= E1000_VT_MSGTYPE_CTS; 6745 igb_write_mbx(hw, &ping, 1, i); 6746 } 6747 } 6748 6749 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6750 { 6751 struct e1000_hw *hw = &adapter->hw; 6752 u32 vmolr = rd32(E1000_VMOLR(vf)); 6753 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6754 6755 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6756 IGB_VF_FLAG_MULTI_PROMISC); 6757 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6758 6759 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6760 vmolr |= E1000_VMOLR_MPME; 6761 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6762 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6763 } else { 6764 /* if we have hashes and we are clearing a multicast promisc 6765 * flag we need to write the hashes to the MTA as this step 6766 * was previously skipped 6767 */ 6768 if (vf_data->num_vf_mc_hashes > 30) { 6769 vmolr |= E1000_VMOLR_MPME; 6770 } else if (vf_data->num_vf_mc_hashes) { 6771 int j; 6772 6773 vmolr |= E1000_VMOLR_ROMPE; 6774 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6775 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6776 } 6777 } 6778 6779 wr32(E1000_VMOLR(vf), vmolr); 6780 6781 /* there are flags left unprocessed, likely not supported */ 6782 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6783 return -EINVAL; 6784 6785 return 0; 6786 } 6787 6788 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6789 u32 *msgbuf, u32 vf) 6790 { 6791 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6792 u16 *hash_list = (u16 *)&msgbuf[1]; 6793 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6794 int i; 6795 6796 /* salt away the number of multicast addresses assigned 6797 * to this VF for later use to restore when the PF multi cast 6798 * list changes 6799 */ 6800 vf_data->num_vf_mc_hashes = n; 6801 6802 /* only up to 30 hash values supported */ 6803 if (n > 30) 6804 n = 30; 6805 6806 /* store the hashes for later use */ 6807 for (i = 0; i < n; i++) 6808 vf_data->vf_mc_hashes[i] = hash_list[i]; 6809 6810 /* Flush and reset the mta with the new values */ 6811 igb_set_rx_mode(adapter->netdev); 6812 6813 return 0; 6814 } 6815 6816 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6817 { 6818 struct e1000_hw *hw = &adapter->hw; 6819 struct vf_data_storage *vf_data; 6820 int i, j; 6821 6822 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6823 u32 vmolr = rd32(E1000_VMOLR(i)); 6824 6825 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6826 6827 vf_data = &adapter->vf_data[i]; 6828 6829 if ((vf_data->num_vf_mc_hashes > 30) || 6830 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6831 vmolr |= E1000_VMOLR_MPME; 6832 } else if (vf_data->num_vf_mc_hashes) { 6833 vmolr |= E1000_VMOLR_ROMPE; 6834 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6835 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6836 } 6837 wr32(E1000_VMOLR(i), vmolr); 6838 } 6839 } 6840 6841 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6842 { 6843 struct e1000_hw *hw = &adapter->hw; 6844 u32 pool_mask, vlvf_mask, i; 6845 6846 /* create mask for VF and other pools */ 6847 pool_mask = E1000_VLVF_POOLSEL_MASK; 6848 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6849 6850 /* drop PF from pool bits */ 6851 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6852 adapter->vfs_allocated_count); 6853 6854 /* Find the vlan filter for this id */ 6855 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6856 u32 vlvf = rd32(E1000_VLVF(i)); 6857 u32 vfta_mask, vid, vfta; 6858 6859 /* remove the vf from the pool */ 6860 if (!(vlvf & vlvf_mask)) 6861 continue; 6862 6863 /* clear out bit from VLVF */ 6864 vlvf ^= vlvf_mask; 6865 6866 /* if other pools are present, just remove ourselves */ 6867 if (vlvf & pool_mask) 6868 goto update_vlvfb; 6869 6870 /* if PF is present, leave VFTA */ 6871 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6872 goto update_vlvf; 6873 6874 vid = vlvf & E1000_VLVF_VLANID_MASK; 6875 vfta_mask = BIT(vid % 32); 6876 6877 /* clear bit from VFTA */ 6878 vfta = adapter->shadow_vfta[vid / 32]; 6879 if (vfta & vfta_mask) 6880 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6881 update_vlvf: 6882 /* clear pool selection enable */ 6883 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6884 vlvf &= E1000_VLVF_POOLSEL_MASK; 6885 else 6886 vlvf = 0; 6887 update_vlvfb: 6888 /* clear pool bits */ 6889 wr32(E1000_VLVF(i), vlvf); 6890 } 6891 } 6892 6893 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6894 { 6895 u32 vlvf; 6896 int idx; 6897 6898 /* short cut the special case */ 6899 if (vlan == 0) 6900 return 0; 6901 6902 /* Search for the VLAN id in the VLVF entries */ 6903 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6904 vlvf = rd32(E1000_VLVF(idx)); 6905 if ((vlvf & VLAN_VID_MASK) == vlan) 6906 break; 6907 } 6908 6909 return idx; 6910 } 6911 6912 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6913 { 6914 struct e1000_hw *hw = &adapter->hw; 6915 u32 bits, pf_id; 6916 int idx; 6917 6918 idx = igb_find_vlvf_entry(hw, vid); 6919 if (!idx) 6920 return; 6921 6922 /* See if any other pools are set for this VLAN filter 6923 * entry other than the PF. 6924 */ 6925 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6926 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6927 bits &= rd32(E1000_VLVF(idx)); 6928 6929 /* Disable the filter so this falls into the default pool. */ 6930 if (!bits) { 6931 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6932 wr32(E1000_VLVF(idx), BIT(pf_id)); 6933 else 6934 wr32(E1000_VLVF(idx), 0); 6935 } 6936 } 6937 6938 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6939 bool add, u32 vf) 6940 { 6941 int pf_id = adapter->vfs_allocated_count; 6942 struct e1000_hw *hw = &adapter->hw; 6943 int err; 6944 6945 /* If VLAN overlaps with one the PF is currently monitoring make 6946 * sure that we are able to allocate a VLVF entry. This may be 6947 * redundant but it guarantees PF will maintain visibility to 6948 * the VLAN. 6949 */ 6950 if (add && test_bit(vid, adapter->active_vlans)) { 6951 err = igb_vfta_set(hw, vid, pf_id, true, false); 6952 if (err) 6953 return err; 6954 } 6955 6956 err = igb_vfta_set(hw, vid, vf, add, false); 6957 6958 if (add && !err) 6959 return err; 6960 6961 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6962 * we may need to drop the PF pool bit in order to allow us to free 6963 * up the VLVF resources. 6964 */ 6965 if (test_bit(vid, adapter->active_vlans) || 6966 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6967 igb_update_pf_vlvf(adapter, vid); 6968 6969 return err; 6970 } 6971 6972 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6973 { 6974 struct e1000_hw *hw = &adapter->hw; 6975 6976 if (vid) 6977 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6978 else 6979 wr32(E1000_VMVIR(vf), 0); 6980 } 6981 6982 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6983 u16 vlan, u8 qos) 6984 { 6985 int err; 6986 6987 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6988 if (err) 6989 return err; 6990 6991 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6992 igb_set_vmolr(adapter, vf, !vlan); 6993 6994 /* revoke access to previous VLAN */ 6995 if (vlan != adapter->vf_data[vf].pf_vlan) 6996 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6997 false, vf); 6998 6999 adapter->vf_data[vf].pf_vlan = vlan; 7000 adapter->vf_data[vf].pf_qos = qos; 7001 igb_set_vf_vlan_strip(adapter, vf, true); 7002 dev_info(&adapter->pdev->dev, 7003 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7004 if (test_bit(__IGB_DOWN, &adapter->state)) { 7005 dev_warn(&adapter->pdev->dev, 7006 "The VF VLAN has been set, but the PF device is not up.\n"); 7007 dev_warn(&adapter->pdev->dev, 7008 "Bring the PF device up before attempting to use the VF device.\n"); 7009 } 7010 7011 return err; 7012 } 7013 7014 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7015 { 7016 /* Restore tagless access via VLAN 0 */ 7017 igb_set_vf_vlan(adapter, 0, true, vf); 7018 7019 igb_set_vmvir(adapter, 0, vf); 7020 igb_set_vmolr(adapter, vf, true); 7021 7022 /* Remove any PF assigned VLAN */ 7023 if (adapter->vf_data[vf].pf_vlan) 7024 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7025 false, vf); 7026 7027 adapter->vf_data[vf].pf_vlan = 0; 7028 adapter->vf_data[vf].pf_qos = 0; 7029 igb_set_vf_vlan_strip(adapter, vf, false); 7030 7031 return 0; 7032 } 7033 7034 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7035 u16 vlan, u8 qos, __be16 vlan_proto) 7036 { 7037 struct igb_adapter *adapter = netdev_priv(netdev); 7038 7039 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7040 return -EINVAL; 7041 7042 if (vlan_proto != htons(ETH_P_8021Q)) 7043 return -EPROTONOSUPPORT; 7044 7045 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7046 igb_disable_port_vlan(adapter, vf); 7047 } 7048 7049 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7050 { 7051 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7052 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7053 int ret; 7054 7055 if (adapter->vf_data[vf].pf_vlan) 7056 return -1; 7057 7058 /* VLAN 0 is a special case, don't allow it to be removed */ 7059 if (!vid && !add) 7060 return 0; 7061 7062 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7063 if (!ret) 7064 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7065 return ret; 7066 } 7067 7068 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7069 { 7070 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7071 7072 /* clear flags - except flag that indicates PF has set the MAC */ 7073 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7074 vf_data->last_nack = jiffies; 7075 7076 /* reset vlans for device */ 7077 igb_clear_vf_vfta(adapter, vf); 7078 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7079 igb_set_vmvir(adapter, vf_data->pf_vlan | 7080 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7081 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7082 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7083 7084 /* reset multicast table array for vf */ 7085 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7086 7087 /* Flush and reset the mta with the new values */ 7088 igb_set_rx_mode(adapter->netdev); 7089 } 7090 7091 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7092 { 7093 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7094 7095 /* clear mac address as we were hotplug removed/added */ 7096 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7097 eth_zero_addr(vf_mac); 7098 7099 /* process remaining reset events */ 7100 igb_vf_reset(adapter, vf); 7101 } 7102 7103 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7104 { 7105 struct e1000_hw *hw = &adapter->hw; 7106 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7107 u32 reg, msgbuf[3]; 7108 u8 *addr = (u8 *)(&msgbuf[1]); 7109 7110 /* process all the same items cleared in a function level reset */ 7111 igb_vf_reset(adapter, vf); 7112 7113 /* set vf mac address */ 7114 igb_set_vf_mac(adapter, vf, vf_mac); 7115 7116 /* enable transmit and receive for vf */ 7117 reg = rd32(E1000_VFTE); 7118 wr32(E1000_VFTE, reg | BIT(vf)); 7119 reg = rd32(E1000_VFRE); 7120 wr32(E1000_VFRE, reg | BIT(vf)); 7121 7122 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7123 7124 /* reply to reset with ack and vf mac address */ 7125 if (!is_zero_ether_addr(vf_mac)) { 7126 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7127 memcpy(addr, vf_mac, ETH_ALEN); 7128 } else { 7129 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7130 } 7131 igb_write_mbx(hw, msgbuf, 3, vf); 7132 } 7133 7134 static void igb_flush_mac_table(struct igb_adapter *adapter) 7135 { 7136 struct e1000_hw *hw = &adapter->hw; 7137 int i; 7138 7139 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7140 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7141 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7142 adapter->mac_table[i].queue = 0; 7143 igb_rar_set_index(adapter, i); 7144 } 7145 } 7146 7147 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7148 { 7149 struct e1000_hw *hw = &adapter->hw; 7150 /* do not count rar entries reserved for VFs MAC addresses */ 7151 int rar_entries = hw->mac.rar_entry_count - 7152 adapter->vfs_allocated_count; 7153 int i, count = 0; 7154 7155 for (i = 0; i < rar_entries; i++) { 7156 /* do not count default entries */ 7157 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7158 continue; 7159 7160 /* do not count "in use" entries for different queues */ 7161 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7162 (adapter->mac_table[i].queue != queue)) 7163 continue; 7164 7165 count++; 7166 } 7167 7168 return count; 7169 } 7170 7171 /* Set default MAC address for the PF in the first RAR entry */ 7172 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7173 { 7174 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7175 7176 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7177 mac_table->queue = adapter->vfs_allocated_count; 7178 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7179 7180 igb_rar_set_index(adapter, 0); 7181 } 7182 7183 /* If the filter to be added and an already existing filter express 7184 * the same address and address type, it should be possible to only 7185 * override the other configurations, for example the queue to steer 7186 * traffic. 7187 */ 7188 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7189 const u8 *addr, const u8 flags) 7190 { 7191 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7192 return true; 7193 7194 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7195 (flags & IGB_MAC_STATE_SRC_ADDR)) 7196 return false; 7197 7198 if (!ether_addr_equal(addr, entry->addr)) 7199 return false; 7200 7201 return true; 7202 } 7203 7204 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7205 * 'flags' is used to indicate what kind of match is made, match is by 7206 * default for the destination address, if matching by source address 7207 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7208 */ 7209 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7210 const u8 *addr, const u8 queue, 7211 const u8 flags) 7212 { 7213 struct e1000_hw *hw = &adapter->hw; 7214 int rar_entries = hw->mac.rar_entry_count - 7215 adapter->vfs_allocated_count; 7216 int i; 7217 7218 if (is_zero_ether_addr(addr)) 7219 return -EINVAL; 7220 7221 /* Search for the first empty entry in the MAC table. 7222 * Do not touch entries at the end of the table reserved for the VF MAC 7223 * addresses. 7224 */ 7225 for (i = 0; i < rar_entries; i++) { 7226 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7227 addr, flags)) 7228 continue; 7229 7230 ether_addr_copy(adapter->mac_table[i].addr, addr); 7231 adapter->mac_table[i].queue = queue; 7232 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7233 7234 igb_rar_set_index(adapter, i); 7235 return i; 7236 } 7237 7238 return -ENOSPC; 7239 } 7240 7241 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7242 const u8 queue) 7243 { 7244 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7245 } 7246 7247 /* Remove a MAC filter for 'addr' directing matching traffic to 7248 * 'queue', 'flags' is used to indicate what kind of match need to be 7249 * removed, match is by default for the destination address, if 7250 * matching by source address is to be removed the flag 7251 * IGB_MAC_STATE_SRC_ADDR can be used. 7252 */ 7253 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7254 const u8 *addr, const u8 queue, 7255 const u8 flags) 7256 { 7257 struct e1000_hw *hw = &adapter->hw; 7258 int rar_entries = hw->mac.rar_entry_count - 7259 adapter->vfs_allocated_count; 7260 int i; 7261 7262 if (is_zero_ether_addr(addr)) 7263 return -EINVAL; 7264 7265 /* Search for matching entry in the MAC table based on given address 7266 * and queue. Do not touch entries at the end of the table reserved 7267 * for the VF MAC addresses. 7268 */ 7269 for (i = 0; i < rar_entries; i++) { 7270 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7271 continue; 7272 if ((adapter->mac_table[i].state & flags) != flags) 7273 continue; 7274 if (adapter->mac_table[i].queue != queue) 7275 continue; 7276 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7277 continue; 7278 7279 /* When a filter for the default address is "deleted", 7280 * we return it to its initial configuration 7281 */ 7282 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7283 adapter->mac_table[i].state = 7284 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7285 adapter->mac_table[i].queue = 7286 adapter->vfs_allocated_count; 7287 } else { 7288 adapter->mac_table[i].state = 0; 7289 adapter->mac_table[i].queue = 0; 7290 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7291 } 7292 7293 igb_rar_set_index(adapter, i); 7294 return 0; 7295 } 7296 7297 return -ENOENT; 7298 } 7299 7300 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7301 const u8 queue) 7302 { 7303 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7304 } 7305 7306 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7307 const u8 *addr, u8 queue, u8 flags) 7308 { 7309 struct e1000_hw *hw = &adapter->hw; 7310 7311 /* In theory, this should be supported on 82575 as well, but 7312 * that part wasn't easily accessible during development. 7313 */ 7314 if (hw->mac.type != e1000_i210) 7315 return -EOPNOTSUPP; 7316 7317 return igb_add_mac_filter_flags(adapter, addr, queue, 7318 IGB_MAC_STATE_QUEUE_STEERING | flags); 7319 } 7320 7321 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7322 const u8 *addr, u8 queue, u8 flags) 7323 { 7324 return igb_del_mac_filter_flags(adapter, addr, queue, 7325 IGB_MAC_STATE_QUEUE_STEERING | flags); 7326 } 7327 7328 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7329 { 7330 struct igb_adapter *adapter = netdev_priv(netdev); 7331 int ret; 7332 7333 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7334 7335 return min_t(int, ret, 0); 7336 } 7337 7338 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7339 { 7340 struct igb_adapter *adapter = netdev_priv(netdev); 7341 7342 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7343 7344 return 0; 7345 } 7346 7347 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7348 const u32 info, const u8 *addr) 7349 { 7350 struct pci_dev *pdev = adapter->pdev; 7351 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7352 struct list_head *pos; 7353 struct vf_mac_filter *entry = NULL; 7354 int ret = 0; 7355 7356 switch (info) { 7357 case E1000_VF_MAC_FILTER_CLR: 7358 /* remove all unicast MAC filters related to the current VF */ 7359 list_for_each(pos, &adapter->vf_macs.l) { 7360 entry = list_entry(pos, struct vf_mac_filter, l); 7361 if (entry->vf == vf) { 7362 entry->vf = -1; 7363 entry->free = true; 7364 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7365 } 7366 } 7367 break; 7368 case E1000_VF_MAC_FILTER_ADD: 7369 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7370 !vf_data->trusted) { 7371 dev_warn(&pdev->dev, 7372 "VF %d requested MAC filter but is administratively denied\n", 7373 vf); 7374 return -EINVAL; 7375 } 7376 if (!is_valid_ether_addr(addr)) { 7377 dev_warn(&pdev->dev, 7378 "VF %d attempted to set invalid MAC filter\n", 7379 vf); 7380 return -EINVAL; 7381 } 7382 7383 /* try to find empty slot in the list */ 7384 list_for_each(pos, &adapter->vf_macs.l) { 7385 entry = list_entry(pos, struct vf_mac_filter, l); 7386 if (entry->free) 7387 break; 7388 } 7389 7390 if (entry && entry->free) { 7391 entry->free = false; 7392 entry->vf = vf; 7393 ether_addr_copy(entry->vf_mac, addr); 7394 7395 ret = igb_add_mac_filter(adapter, addr, vf); 7396 ret = min_t(int, ret, 0); 7397 } else { 7398 ret = -ENOSPC; 7399 } 7400 7401 if (ret == -ENOSPC) 7402 dev_warn(&pdev->dev, 7403 "VF %d has requested MAC filter but there is no space for it\n", 7404 vf); 7405 break; 7406 default: 7407 ret = -EINVAL; 7408 break; 7409 } 7410 7411 return ret; 7412 } 7413 7414 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7415 { 7416 struct pci_dev *pdev = adapter->pdev; 7417 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7418 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7419 7420 /* The VF MAC Address is stored in a packed array of bytes 7421 * starting at the second 32 bit word of the msg array 7422 */ 7423 unsigned char *addr = (unsigned char *)&msg[1]; 7424 int ret = 0; 7425 7426 if (!info) { 7427 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7428 !vf_data->trusted) { 7429 dev_warn(&pdev->dev, 7430 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7431 vf); 7432 return -EINVAL; 7433 } 7434 7435 if (!is_valid_ether_addr(addr)) { 7436 dev_warn(&pdev->dev, 7437 "VF %d attempted to set invalid MAC\n", 7438 vf); 7439 return -EINVAL; 7440 } 7441 7442 ret = igb_set_vf_mac(adapter, vf, addr); 7443 } else { 7444 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7445 } 7446 7447 return ret; 7448 } 7449 7450 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7451 { 7452 struct e1000_hw *hw = &adapter->hw; 7453 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7454 u32 msg = E1000_VT_MSGTYPE_NACK; 7455 7456 /* if device isn't clear to send it shouldn't be reading either */ 7457 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7458 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7459 igb_write_mbx(hw, &msg, 1, vf); 7460 vf_data->last_nack = jiffies; 7461 } 7462 } 7463 7464 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7465 { 7466 struct pci_dev *pdev = adapter->pdev; 7467 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7468 struct e1000_hw *hw = &adapter->hw; 7469 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7470 s32 retval; 7471 7472 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7473 7474 if (retval) { 7475 /* if receive failed revoke VF CTS stats and restart init */ 7476 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7477 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7478 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7479 goto unlock; 7480 goto out; 7481 } 7482 7483 /* this is a message we already processed, do nothing */ 7484 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7485 goto unlock; 7486 7487 /* until the vf completes a reset it should not be 7488 * allowed to start any configuration. 7489 */ 7490 if (msgbuf[0] == E1000_VF_RESET) { 7491 /* unlocks mailbox */ 7492 igb_vf_reset_msg(adapter, vf); 7493 return; 7494 } 7495 7496 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7497 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7498 goto unlock; 7499 retval = -1; 7500 goto out; 7501 } 7502 7503 switch ((msgbuf[0] & 0xFFFF)) { 7504 case E1000_VF_SET_MAC_ADDR: 7505 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7506 break; 7507 case E1000_VF_SET_PROMISC: 7508 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7509 break; 7510 case E1000_VF_SET_MULTICAST: 7511 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7512 break; 7513 case E1000_VF_SET_LPE: 7514 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7515 break; 7516 case E1000_VF_SET_VLAN: 7517 retval = -1; 7518 if (vf_data->pf_vlan) 7519 dev_warn(&pdev->dev, 7520 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7521 vf); 7522 else 7523 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7524 break; 7525 default: 7526 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7527 retval = -1; 7528 break; 7529 } 7530 7531 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7532 out: 7533 /* notify the VF of the results of what it sent us */ 7534 if (retval) 7535 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7536 else 7537 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7538 7539 /* unlocks mailbox */ 7540 igb_write_mbx(hw, msgbuf, 1, vf); 7541 return; 7542 7543 unlock: 7544 igb_unlock_mbx(hw, vf); 7545 } 7546 7547 static void igb_msg_task(struct igb_adapter *adapter) 7548 { 7549 struct e1000_hw *hw = &adapter->hw; 7550 u32 vf; 7551 7552 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7553 /* process any reset requests */ 7554 if (!igb_check_for_rst(hw, vf)) 7555 igb_vf_reset_event(adapter, vf); 7556 7557 /* process any messages pending */ 7558 if (!igb_check_for_msg(hw, vf)) 7559 igb_rcv_msg_from_vf(adapter, vf); 7560 7561 /* process any acks */ 7562 if (!igb_check_for_ack(hw, vf)) 7563 igb_rcv_ack_from_vf(adapter, vf); 7564 } 7565 } 7566 7567 /** 7568 * igb_set_uta - Set unicast filter table address 7569 * @adapter: board private structure 7570 * @set: boolean indicating if we are setting or clearing bits 7571 * 7572 * The unicast table address is a register array of 32-bit registers. 7573 * The table is meant to be used in a way similar to how the MTA is used 7574 * however due to certain limitations in the hardware it is necessary to 7575 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7576 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7577 **/ 7578 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7579 { 7580 struct e1000_hw *hw = &adapter->hw; 7581 u32 uta = set ? ~0 : 0; 7582 int i; 7583 7584 /* we only need to do this if VMDq is enabled */ 7585 if (!adapter->vfs_allocated_count) 7586 return; 7587 7588 for (i = hw->mac.uta_reg_count; i--;) 7589 array_wr32(E1000_UTA, i, uta); 7590 } 7591 7592 /** 7593 * igb_intr_msi - Interrupt Handler 7594 * @irq: interrupt number 7595 * @data: pointer to a network interface device structure 7596 **/ 7597 static irqreturn_t igb_intr_msi(int irq, void *data) 7598 { 7599 struct igb_adapter *adapter = data; 7600 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7601 struct e1000_hw *hw = &adapter->hw; 7602 /* read ICR disables interrupts using IAM */ 7603 u32 icr = rd32(E1000_ICR); 7604 7605 igb_write_itr(q_vector); 7606 7607 if (icr & E1000_ICR_DRSTA) 7608 schedule_work(&adapter->reset_task); 7609 7610 if (icr & E1000_ICR_DOUTSYNC) { 7611 /* HW is reporting DMA is out of sync */ 7612 adapter->stats.doosync++; 7613 } 7614 7615 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7616 hw->mac.get_link_status = 1; 7617 if (!test_bit(__IGB_DOWN, &adapter->state)) 7618 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7619 } 7620 7621 if (icr & E1000_ICR_TS) 7622 igb_tsync_interrupt(adapter); 7623 7624 napi_schedule(&q_vector->napi); 7625 7626 return IRQ_HANDLED; 7627 } 7628 7629 /** 7630 * igb_intr - Legacy Interrupt Handler 7631 * @irq: interrupt number 7632 * @data: pointer to a network interface device structure 7633 **/ 7634 static irqreturn_t igb_intr(int irq, void *data) 7635 { 7636 struct igb_adapter *adapter = data; 7637 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7638 struct e1000_hw *hw = &adapter->hw; 7639 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7640 * need for the IMC write 7641 */ 7642 u32 icr = rd32(E1000_ICR); 7643 7644 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7645 * not set, then the adapter didn't send an interrupt 7646 */ 7647 if (!(icr & E1000_ICR_INT_ASSERTED)) 7648 return IRQ_NONE; 7649 7650 igb_write_itr(q_vector); 7651 7652 if (icr & E1000_ICR_DRSTA) 7653 schedule_work(&adapter->reset_task); 7654 7655 if (icr & E1000_ICR_DOUTSYNC) { 7656 /* HW is reporting DMA is out of sync */ 7657 adapter->stats.doosync++; 7658 } 7659 7660 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7661 hw->mac.get_link_status = 1; 7662 /* guard against interrupt when we're going down */ 7663 if (!test_bit(__IGB_DOWN, &adapter->state)) 7664 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7665 } 7666 7667 if (icr & E1000_ICR_TS) 7668 igb_tsync_interrupt(adapter); 7669 7670 napi_schedule(&q_vector->napi); 7671 7672 return IRQ_HANDLED; 7673 } 7674 7675 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7676 { 7677 struct igb_adapter *adapter = q_vector->adapter; 7678 struct e1000_hw *hw = &adapter->hw; 7679 7680 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7681 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7682 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7683 igb_set_itr(q_vector); 7684 else 7685 igb_update_ring_itr(q_vector); 7686 } 7687 7688 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7689 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7690 wr32(E1000_EIMS, q_vector->eims_value); 7691 else 7692 igb_irq_enable(adapter); 7693 } 7694 } 7695 7696 /** 7697 * igb_poll - NAPI Rx polling callback 7698 * @napi: napi polling structure 7699 * @budget: count of how many packets we should handle 7700 **/ 7701 static int igb_poll(struct napi_struct *napi, int budget) 7702 { 7703 struct igb_q_vector *q_vector = container_of(napi, 7704 struct igb_q_vector, 7705 napi); 7706 bool clean_complete = true; 7707 int work_done = 0; 7708 7709 #ifdef CONFIG_IGB_DCA 7710 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7711 igb_update_dca(q_vector); 7712 #endif 7713 if (q_vector->tx.ring) 7714 clean_complete = igb_clean_tx_irq(q_vector, budget); 7715 7716 if (q_vector->rx.ring) { 7717 int cleaned = igb_clean_rx_irq(q_vector, budget); 7718 7719 work_done += cleaned; 7720 if (cleaned >= budget) 7721 clean_complete = false; 7722 } 7723 7724 /* If all work not completed, return budget and keep polling */ 7725 if (!clean_complete) 7726 return budget; 7727 7728 /* Exit the polling mode, but don't re-enable interrupts if stack might 7729 * poll us due to busy-polling 7730 */ 7731 if (likely(napi_complete_done(napi, work_done))) 7732 igb_ring_irq_enable(q_vector); 7733 7734 return min(work_done, budget - 1); 7735 } 7736 7737 /** 7738 * igb_clean_tx_irq - Reclaim resources after transmit completes 7739 * @q_vector: pointer to q_vector containing needed info 7740 * @napi_budget: Used to determine if we are in netpoll 7741 * 7742 * returns true if ring is completely cleaned 7743 **/ 7744 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7745 { 7746 struct igb_adapter *adapter = q_vector->adapter; 7747 struct igb_ring *tx_ring = q_vector->tx.ring; 7748 struct igb_tx_buffer *tx_buffer; 7749 union e1000_adv_tx_desc *tx_desc; 7750 unsigned int total_bytes = 0, total_packets = 0; 7751 unsigned int budget = q_vector->tx.work_limit; 7752 unsigned int i = tx_ring->next_to_clean; 7753 7754 if (test_bit(__IGB_DOWN, &adapter->state)) 7755 return true; 7756 7757 tx_buffer = &tx_ring->tx_buffer_info[i]; 7758 tx_desc = IGB_TX_DESC(tx_ring, i); 7759 i -= tx_ring->count; 7760 7761 do { 7762 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7763 7764 /* if next_to_watch is not set then there is no work pending */ 7765 if (!eop_desc) 7766 break; 7767 7768 /* prevent any other reads prior to eop_desc */ 7769 smp_rmb(); 7770 7771 /* if DD is not set pending work has not been completed */ 7772 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7773 break; 7774 7775 /* clear next_to_watch to prevent false hangs */ 7776 tx_buffer->next_to_watch = NULL; 7777 7778 /* update the statistics for this packet */ 7779 total_bytes += tx_buffer->bytecount; 7780 total_packets += tx_buffer->gso_segs; 7781 7782 /* free the skb */ 7783 napi_consume_skb(tx_buffer->skb, napi_budget); 7784 7785 /* unmap skb header data */ 7786 dma_unmap_single(tx_ring->dev, 7787 dma_unmap_addr(tx_buffer, dma), 7788 dma_unmap_len(tx_buffer, len), 7789 DMA_TO_DEVICE); 7790 7791 /* clear tx_buffer data */ 7792 dma_unmap_len_set(tx_buffer, len, 0); 7793 7794 /* clear last DMA location and unmap remaining buffers */ 7795 while (tx_desc != eop_desc) { 7796 tx_buffer++; 7797 tx_desc++; 7798 i++; 7799 if (unlikely(!i)) { 7800 i -= tx_ring->count; 7801 tx_buffer = tx_ring->tx_buffer_info; 7802 tx_desc = IGB_TX_DESC(tx_ring, 0); 7803 } 7804 7805 /* unmap any remaining paged data */ 7806 if (dma_unmap_len(tx_buffer, len)) { 7807 dma_unmap_page(tx_ring->dev, 7808 dma_unmap_addr(tx_buffer, dma), 7809 dma_unmap_len(tx_buffer, len), 7810 DMA_TO_DEVICE); 7811 dma_unmap_len_set(tx_buffer, len, 0); 7812 } 7813 } 7814 7815 /* move us one more past the eop_desc for start of next pkt */ 7816 tx_buffer++; 7817 tx_desc++; 7818 i++; 7819 if (unlikely(!i)) { 7820 i -= tx_ring->count; 7821 tx_buffer = tx_ring->tx_buffer_info; 7822 tx_desc = IGB_TX_DESC(tx_ring, 0); 7823 } 7824 7825 /* issue prefetch for next Tx descriptor */ 7826 prefetch(tx_desc); 7827 7828 /* update budget accounting */ 7829 budget--; 7830 } while (likely(budget)); 7831 7832 netdev_tx_completed_queue(txring_txq(tx_ring), 7833 total_packets, total_bytes); 7834 i += tx_ring->count; 7835 tx_ring->next_to_clean = i; 7836 u64_stats_update_begin(&tx_ring->tx_syncp); 7837 tx_ring->tx_stats.bytes += total_bytes; 7838 tx_ring->tx_stats.packets += total_packets; 7839 u64_stats_update_end(&tx_ring->tx_syncp); 7840 q_vector->tx.total_bytes += total_bytes; 7841 q_vector->tx.total_packets += total_packets; 7842 7843 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7844 struct e1000_hw *hw = &adapter->hw; 7845 7846 /* Detect a transmit hang in hardware, this serializes the 7847 * check with the clearing of time_stamp and movement of i 7848 */ 7849 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7850 if (tx_buffer->next_to_watch && 7851 time_after(jiffies, tx_buffer->time_stamp + 7852 (adapter->tx_timeout_factor * HZ)) && 7853 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7854 7855 /* detected Tx unit hang */ 7856 dev_err(tx_ring->dev, 7857 "Detected Tx Unit Hang\n" 7858 " Tx Queue <%d>\n" 7859 " TDH <%x>\n" 7860 " TDT <%x>\n" 7861 " next_to_use <%x>\n" 7862 " next_to_clean <%x>\n" 7863 "buffer_info[next_to_clean]\n" 7864 " time_stamp <%lx>\n" 7865 " next_to_watch <%p>\n" 7866 " jiffies <%lx>\n" 7867 " desc.status <%x>\n", 7868 tx_ring->queue_index, 7869 rd32(E1000_TDH(tx_ring->reg_idx)), 7870 readl(tx_ring->tail), 7871 tx_ring->next_to_use, 7872 tx_ring->next_to_clean, 7873 tx_buffer->time_stamp, 7874 tx_buffer->next_to_watch, 7875 jiffies, 7876 tx_buffer->next_to_watch->wb.status); 7877 netif_stop_subqueue(tx_ring->netdev, 7878 tx_ring->queue_index); 7879 7880 /* we are about to reset, no point in enabling stuff */ 7881 return true; 7882 } 7883 } 7884 7885 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7886 if (unlikely(total_packets && 7887 netif_carrier_ok(tx_ring->netdev) && 7888 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7889 /* Make sure that anybody stopping the queue after this 7890 * sees the new next_to_clean. 7891 */ 7892 smp_mb(); 7893 if (__netif_subqueue_stopped(tx_ring->netdev, 7894 tx_ring->queue_index) && 7895 !(test_bit(__IGB_DOWN, &adapter->state))) { 7896 netif_wake_subqueue(tx_ring->netdev, 7897 tx_ring->queue_index); 7898 7899 u64_stats_update_begin(&tx_ring->tx_syncp); 7900 tx_ring->tx_stats.restart_queue++; 7901 u64_stats_update_end(&tx_ring->tx_syncp); 7902 } 7903 } 7904 7905 return !!budget; 7906 } 7907 7908 /** 7909 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7910 * @rx_ring: rx descriptor ring to store buffers on 7911 * @old_buff: donor buffer to have page reused 7912 * 7913 * Synchronizes page for reuse by the adapter 7914 **/ 7915 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7916 struct igb_rx_buffer *old_buff) 7917 { 7918 struct igb_rx_buffer *new_buff; 7919 u16 nta = rx_ring->next_to_alloc; 7920 7921 new_buff = &rx_ring->rx_buffer_info[nta]; 7922 7923 /* update, and store next to alloc */ 7924 nta++; 7925 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7926 7927 /* Transfer page from old buffer to new buffer. 7928 * Move each member individually to avoid possible store 7929 * forwarding stalls. 7930 */ 7931 new_buff->dma = old_buff->dma; 7932 new_buff->page = old_buff->page; 7933 new_buff->page_offset = old_buff->page_offset; 7934 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7935 } 7936 7937 static inline bool igb_page_is_reserved(struct page *page) 7938 { 7939 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7940 } 7941 7942 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7943 { 7944 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7945 struct page *page = rx_buffer->page; 7946 7947 /* avoid re-using remote pages */ 7948 if (unlikely(igb_page_is_reserved(page))) 7949 return false; 7950 7951 #if (PAGE_SIZE < 8192) 7952 /* if we are only owner of page we can reuse it */ 7953 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7954 return false; 7955 #else 7956 #define IGB_LAST_OFFSET \ 7957 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7958 7959 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7960 return false; 7961 #endif 7962 7963 /* If we have drained the page fragment pool we need to update 7964 * the pagecnt_bias and page count so that we fully restock the 7965 * number of references the driver holds. 7966 */ 7967 if (unlikely(!pagecnt_bias)) { 7968 page_ref_add(page, USHRT_MAX); 7969 rx_buffer->pagecnt_bias = USHRT_MAX; 7970 } 7971 7972 return true; 7973 } 7974 7975 /** 7976 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7977 * @rx_ring: rx descriptor ring to transact packets on 7978 * @rx_buffer: buffer containing page to add 7979 * @skb: sk_buff to place the data into 7980 * @size: size of buffer to be added 7981 * 7982 * This function will add the data contained in rx_buffer->page to the skb. 7983 **/ 7984 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7985 struct igb_rx_buffer *rx_buffer, 7986 struct sk_buff *skb, 7987 unsigned int size) 7988 { 7989 #if (PAGE_SIZE < 8192) 7990 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7991 #else 7992 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7993 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7994 SKB_DATA_ALIGN(size); 7995 #endif 7996 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7997 rx_buffer->page_offset, size, truesize); 7998 #if (PAGE_SIZE < 8192) 7999 rx_buffer->page_offset ^= truesize; 8000 #else 8001 rx_buffer->page_offset += truesize; 8002 #endif 8003 } 8004 8005 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8006 struct igb_rx_buffer *rx_buffer, 8007 union e1000_adv_rx_desc *rx_desc, 8008 unsigned int size) 8009 { 8010 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8011 #if (PAGE_SIZE < 8192) 8012 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8013 #else 8014 unsigned int truesize = SKB_DATA_ALIGN(size); 8015 #endif 8016 unsigned int headlen; 8017 struct sk_buff *skb; 8018 8019 /* prefetch first cache line of first page */ 8020 prefetch(va); 8021 #if L1_CACHE_BYTES < 128 8022 prefetch(va + L1_CACHE_BYTES); 8023 #endif 8024 8025 /* allocate a skb to store the frags */ 8026 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8027 if (unlikely(!skb)) 8028 return NULL; 8029 8030 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8031 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 8032 va += IGB_TS_HDR_LEN; 8033 size -= IGB_TS_HDR_LEN; 8034 } 8035 8036 /* Determine available headroom for copy */ 8037 headlen = size; 8038 if (headlen > IGB_RX_HDR_LEN) 8039 headlen = eth_get_headlen(skb->dev, va, IGB_RX_HDR_LEN); 8040 8041 /* align pull length to size of long to optimize memcpy performance */ 8042 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 8043 8044 /* update all of the pointers */ 8045 size -= headlen; 8046 if (size) { 8047 skb_add_rx_frag(skb, 0, rx_buffer->page, 8048 (va + headlen) - page_address(rx_buffer->page), 8049 size, truesize); 8050 #if (PAGE_SIZE < 8192) 8051 rx_buffer->page_offset ^= truesize; 8052 #else 8053 rx_buffer->page_offset += truesize; 8054 #endif 8055 } else { 8056 rx_buffer->pagecnt_bias++; 8057 } 8058 8059 return skb; 8060 } 8061 8062 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8063 struct igb_rx_buffer *rx_buffer, 8064 union e1000_adv_rx_desc *rx_desc, 8065 unsigned int size) 8066 { 8067 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8068 #if (PAGE_SIZE < 8192) 8069 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8070 #else 8071 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8072 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 8073 #endif 8074 struct sk_buff *skb; 8075 8076 /* prefetch first cache line of first page */ 8077 prefetch(va); 8078 #if L1_CACHE_BYTES < 128 8079 prefetch(va + L1_CACHE_BYTES); 8080 #endif 8081 8082 /* build an skb around the page buffer */ 8083 skb = build_skb(va - IGB_SKB_PAD, truesize); 8084 if (unlikely(!skb)) 8085 return NULL; 8086 8087 /* update pointers within the skb to store the data */ 8088 skb_reserve(skb, IGB_SKB_PAD); 8089 __skb_put(skb, size); 8090 8091 /* pull timestamp out of packet data */ 8092 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8093 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8094 __skb_pull(skb, IGB_TS_HDR_LEN); 8095 } 8096 8097 /* update buffer offset */ 8098 #if (PAGE_SIZE < 8192) 8099 rx_buffer->page_offset ^= truesize; 8100 #else 8101 rx_buffer->page_offset += truesize; 8102 #endif 8103 8104 return skb; 8105 } 8106 8107 static inline void igb_rx_checksum(struct igb_ring *ring, 8108 union e1000_adv_rx_desc *rx_desc, 8109 struct sk_buff *skb) 8110 { 8111 skb_checksum_none_assert(skb); 8112 8113 /* Ignore Checksum bit is set */ 8114 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8115 return; 8116 8117 /* Rx checksum disabled via ethtool */ 8118 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8119 return; 8120 8121 /* TCP/UDP checksum error bit is set */ 8122 if (igb_test_staterr(rx_desc, 8123 E1000_RXDEXT_STATERR_TCPE | 8124 E1000_RXDEXT_STATERR_IPE)) { 8125 /* work around errata with sctp packets where the TCPE aka 8126 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8127 * packets, (aka let the stack check the crc32c) 8128 */ 8129 if (!((skb->len == 60) && 8130 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8131 u64_stats_update_begin(&ring->rx_syncp); 8132 ring->rx_stats.csum_err++; 8133 u64_stats_update_end(&ring->rx_syncp); 8134 } 8135 /* let the stack verify checksum errors */ 8136 return; 8137 } 8138 /* It must be a TCP or UDP packet with a valid checksum */ 8139 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8140 E1000_RXD_STAT_UDPCS)) 8141 skb->ip_summed = CHECKSUM_UNNECESSARY; 8142 8143 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8144 le32_to_cpu(rx_desc->wb.upper.status_error)); 8145 } 8146 8147 static inline void igb_rx_hash(struct igb_ring *ring, 8148 union e1000_adv_rx_desc *rx_desc, 8149 struct sk_buff *skb) 8150 { 8151 if (ring->netdev->features & NETIF_F_RXHASH) 8152 skb_set_hash(skb, 8153 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8154 PKT_HASH_TYPE_L3); 8155 } 8156 8157 /** 8158 * igb_is_non_eop - process handling of non-EOP buffers 8159 * @rx_ring: Rx ring being processed 8160 * @rx_desc: Rx descriptor for current buffer 8161 * @skb: current socket buffer containing buffer in progress 8162 * 8163 * This function updates next to clean. If the buffer is an EOP buffer 8164 * this function exits returning false, otherwise it will place the 8165 * sk_buff in the next buffer to be chained and return true indicating 8166 * that this is in fact a non-EOP buffer. 8167 **/ 8168 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8169 union e1000_adv_rx_desc *rx_desc) 8170 { 8171 u32 ntc = rx_ring->next_to_clean + 1; 8172 8173 /* fetch, update, and store next to clean */ 8174 ntc = (ntc < rx_ring->count) ? ntc : 0; 8175 rx_ring->next_to_clean = ntc; 8176 8177 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8178 8179 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8180 return false; 8181 8182 return true; 8183 } 8184 8185 /** 8186 * igb_cleanup_headers - Correct corrupted or empty headers 8187 * @rx_ring: rx descriptor ring packet is being transacted on 8188 * @rx_desc: pointer to the EOP Rx descriptor 8189 * @skb: pointer to current skb being fixed 8190 * 8191 * Address the case where we are pulling data in on pages only 8192 * and as such no data is present in the skb header. 8193 * 8194 * In addition if skb is not at least 60 bytes we need to pad it so that 8195 * it is large enough to qualify as a valid Ethernet frame. 8196 * 8197 * Returns true if an error was encountered and skb was freed. 8198 **/ 8199 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8200 union e1000_adv_rx_desc *rx_desc, 8201 struct sk_buff *skb) 8202 { 8203 if (unlikely((igb_test_staterr(rx_desc, 8204 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8205 struct net_device *netdev = rx_ring->netdev; 8206 if (!(netdev->features & NETIF_F_RXALL)) { 8207 dev_kfree_skb_any(skb); 8208 return true; 8209 } 8210 } 8211 8212 /* if eth_skb_pad returns an error the skb was freed */ 8213 if (eth_skb_pad(skb)) 8214 return true; 8215 8216 return false; 8217 } 8218 8219 /** 8220 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8221 * @rx_ring: rx descriptor ring packet is being transacted on 8222 * @rx_desc: pointer to the EOP Rx descriptor 8223 * @skb: pointer to current skb being populated 8224 * 8225 * This function checks the ring, descriptor, and packet information in 8226 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8227 * other fields within the skb. 8228 **/ 8229 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8230 union e1000_adv_rx_desc *rx_desc, 8231 struct sk_buff *skb) 8232 { 8233 struct net_device *dev = rx_ring->netdev; 8234 8235 igb_rx_hash(rx_ring, rx_desc, skb); 8236 8237 igb_rx_checksum(rx_ring, rx_desc, skb); 8238 8239 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8240 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8241 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8242 8243 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8244 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8245 u16 vid; 8246 8247 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8248 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8249 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8250 else 8251 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8252 8253 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8254 } 8255 8256 skb_record_rx_queue(skb, rx_ring->queue_index); 8257 8258 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8259 } 8260 8261 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8262 const unsigned int size) 8263 { 8264 struct igb_rx_buffer *rx_buffer; 8265 8266 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8267 prefetchw(rx_buffer->page); 8268 8269 /* we are reusing so sync this buffer for CPU use */ 8270 dma_sync_single_range_for_cpu(rx_ring->dev, 8271 rx_buffer->dma, 8272 rx_buffer->page_offset, 8273 size, 8274 DMA_FROM_DEVICE); 8275 8276 rx_buffer->pagecnt_bias--; 8277 8278 return rx_buffer; 8279 } 8280 8281 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8282 struct igb_rx_buffer *rx_buffer) 8283 { 8284 if (igb_can_reuse_rx_page(rx_buffer)) { 8285 /* hand second half of page back to the ring */ 8286 igb_reuse_rx_page(rx_ring, rx_buffer); 8287 } else { 8288 /* We are not reusing the buffer so unmap it and free 8289 * any references we are holding to it 8290 */ 8291 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8292 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8293 IGB_RX_DMA_ATTR); 8294 __page_frag_cache_drain(rx_buffer->page, 8295 rx_buffer->pagecnt_bias); 8296 } 8297 8298 /* clear contents of rx_buffer */ 8299 rx_buffer->page = NULL; 8300 } 8301 8302 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8303 { 8304 struct igb_ring *rx_ring = q_vector->rx.ring; 8305 struct sk_buff *skb = rx_ring->skb; 8306 unsigned int total_bytes = 0, total_packets = 0; 8307 u16 cleaned_count = igb_desc_unused(rx_ring); 8308 8309 while (likely(total_packets < budget)) { 8310 union e1000_adv_rx_desc *rx_desc; 8311 struct igb_rx_buffer *rx_buffer; 8312 unsigned int size; 8313 8314 /* return some buffers to hardware, one at a time is too slow */ 8315 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8316 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8317 cleaned_count = 0; 8318 } 8319 8320 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8321 size = le16_to_cpu(rx_desc->wb.upper.length); 8322 if (!size) 8323 break; 8324 8325 /* This memory barrier is needed to keep us from reading 8326 * any other fields out of the rx_desc until we know the 8327 * descriptor has been written back 8328 */ 8329 dma_rmb(); 8330 8331 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8332 8333 /* retrieve a buffer from the ring */ 8334 if (skb) 8335 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8336 else if (ring_uses_build_skb(rx_ring)) 8337 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 8338 else 8339 skb = igb_construct_skb(rx_ring, rx_buffer, 8340 rx_desc, size); 8341 8342 /* exit if we failed to retrieve a buffer */ 8343 if (!skb) { 8344 rx_ring->rx_stats.alloc_failed++; 8345 rx_buffer->pagecnt_bias++; 8346 break; 8347 } 8348 8349 igb_put_rx_buffer(rx_ring, rx_buffer); 8350 cleaned_count++; 8351 8352 /* fetch next buffer in frame if non-eop */ 8353 if (igb_is_non_eop(rx_ring, rx_desc)) 8354 continue; 8355 8356 /* verify the packet layout is correct */ 8357 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8358 skb = NULL; 8359 continue; 8360 } 8361 8362 /* probably a little skewed due to removing CRC */ 8363 total_bytes += skb->len; 8364 8365 /* populate checksum, timestamp, VLAN, and protocol */ 8366 igb_process_skb_fields(rx_ring, rx_desc, skb); 8367 8368 napi_gro_receive(&q_vector->napi, skb); 8369 8370 /* reset skb pointer */ 8371 skb = NULL; 8372 8373 /* update budget accounting */ 8374 total_packets++; 8375 } 8376 8377 /* place incomplete frames back on ring for completion */ 8378 rx_ring->skb = skb; 8379 8380 u64_stats_update_begin(&rx_ring->rx_syncp); 8381 rx_ring->rx_stats.packets += total_packets; 8382 rx_ring->rx_stats.bytes += total_bytes; 8383 u64_stats_update_end(&rx_ring->rx_syncp); 8384 q_vector->rx.total_packets += total_packets; 8385 q_vector->rx.total_bytes += total_bytes; 8386 8387 if (cleaned_count) 8388 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8389 8390 return total_packets; 8391 } 8392 8393 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8394 { 8395 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8396 } 8397 8398 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8399 struct igb_rx_buffer *bi) 8400 { 8401 struct page *page = bi->page; 8402 dma_addr_t dma; 8403 8404 /* since we are recycling buffers we should seldom need to alloc */ 8405 if (likely(page)) 8406 return true; 8407 8408 /* alloc new page for storage */ 8409 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8410 if (unlikely(!page)) { 8411 rx_ring->rx_stats.alloc_failed++; 8412 return false; 8413 } 8414 8415 /* map page for use */ 8416 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8417 igb_rx_pg_size(rx_ring), 8418 DMA_FROM_DEVICE, 8419 IGB_RX_DMA_ATTR); 8420 8421 /* if mapping failed free memory back to system since 8422 * there isn't much point in holding memory we can't use 8423 */ 8424 if (dma_mapping_error(rx_ring->dev, dma)) { 8425 __free_pages(page, igb_rx_pg_order(rx_ring)); 8426 8427 rx_ring->rx_stats.alloc_failed++; 8428 return false; 8429 } 8430 8431 bi->dma = dma; 8432 bi->page = page; 8433 bi->page_offset = igb_rx_offset(rx_ring); 8434 bi->pagecnt_bias = 1; 8435 8436 return true; 8437 } 8438 8439 /** 8440 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8441 * @adapter: address of board private structure 8442 **/ 8443 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8444 { 8445 union e1000_adv_rx_desc *rx_desc; 8446 struct igb_rx_buffer *bi; 8447 u16 i = rx_ring->next_to_use; 8448 u16 bufsz; 8449 8450 /* nothing to do */ 8451 if (!cleaned_count) 8452 return; 8453 8454 rx_desc = IGB_RX_DESC(rx_ring, i); 8455 bi = &rx_ring->rx_buffer_info[i]; 8456 i -= rx_ring->count; 8457 8458 bufsz = igb_rx_bufsz(rx_ring); 8459 8460 do { 8461 if (!igb_alloc_mapped_page(rx_ring, bi)) 8462 break; 8463 8464 /* sync the buffer for use by the device */ 8465 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8466 bi->page_offset, bufsz, 8467 DMA_FROM_DEVICE); 8468 8469 /* Refresh the desc even if buffer_addrs didn't change 8470 * because each write-back erases this info. 8471 */ 8472 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8473 8474 rx_desc++; 8475 bi++; 8476 i++; 8477 if (unlikely(!i)) { 8478 rx_desc = IGB_RX_DESC(rx_ring, 0); 8479 bi = rx_ring->rx_buffer_info; 8480 i -= rx_ring->count; 8481 } 8482 8483 /* clear the length for the next_to_use descriptor */ 8484 rx_desc->wb.upper.length = 0; 8485 8486 cleaned_count--; 8487 } while (cleaned_count); 8488 8489 i += rx_ring->count; 8490 8491 if (rx_ring->next_to_use != i) { 8492 /* record the next descriptor to use */ 8493 rx_ring->next_to_use = i; 8494 8495 /* update next to alloc since we have filled the ring */ 8496 rx_ring->next_to_alloc = i; 8497 8498 /* Force memory writes to complete before letting h/w 8499 * know there are new descriptors to fetch. (Only 8500 * applicable for weak-ordered memory model archs, 8501 * such as IA-64). 8502 */ 8503 dma_wmb(); 8504 writel(i, rx_ring->tail); 8505 } 8506 } 8507 8508 /** 8509 * igb_mii_ioctl - 8510 * @netdev: 8511 * @ifreq: 8512 * @cmd: 8513 **/ 8514 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8515 { 8516 struct igb_adapter *adapter = netdev_priv(netdev); 8517 struct mii_ioctl_data *data = if_mii(ifr); 8518 8519 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8520 return -EOPNOTSUPP; 8521 8522 switch (cmd) { 8523 case SIOCGMIIPHY: 8524 data->phy_id = adapter->hw.phy.addr; 8525 break; 8526 case SIOCGMIIREG: 8527 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8528 &data->val_out)) 8529 return -EIO; 8530 break; 8531 case SIOCSMIIREG: 8532 default: 8533 return -EOPNOTSUPP; 8534 } 8535 return 0; 8536 } 8537 8538 /** 8539 * igb_ioctl - 8540 * @netdev: 8541 * @ifreq: 8542 * @cmd: 8543 **/ 8544 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8545 { 8546 switch (cmd) { 8547 case SIOCGMIIPHY: 8548 case SIOCGMIIREG: 8549 case SIOCSMIIREG: 8550 return igb_mii_ioctl(netdev, ifr, cmd); 8551 case SIOCGHWTSTAMP: 8552 return igb_ptp_get_ts_config(netdev, ifr); 8553 case SIOCSHWTSTAMP: 8554 return igb_ptp_set_ts_config(netdev, ifr); 8555 default: 8556 return -EOPNOTSUPP; 8557 } 8558 } 8559 8560 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8561 { 8562 struct igb_adapter *adapter = hw->back; 8563 8564 pci_read_config_word(adapter->pdev, reg, value); 8565 } 8566 8567 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8568 { 8569 struct igb_adapter *adapter = hw->back; 8570 8571 pci_write_config_word(adapter->pdev, reg, *value); 8572 } 8573 8574 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8575 { 8576 struct igb_adapter *adapter = hw->back; 8577 8578 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8579 return -E1000_ERR_CONFIG; 8580 8581 return 0; 8582 } 8583 8584 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8585 { 8586 struct igb_adapter *adapter = hw->back; 8587 8588 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8589 return -E1000_ERR_CONFIG; 8590 8591 return 0; 8592 } 8593 8594 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8595 { 8596 struct igb_adapter *adapter = netdev_priv(netdev); 8597 struct e1000_hw *hw = &adapter->hw; 8598 u32 ctrl, rctl; 8599 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8600 8601 if (enable) { 8602 /* enable VLAN tag insert/strip */ 8603 ctrl = rd32(E1000_CTRL); 8604 ctrl |= E1000_CTRL_VME; 8605 wr32(E1000_CTRL, ctrl); 8606 8607 /* Disable CFI check */ 8608 rctl = rd32(E1000_RCTL); 8609 rctl &= ~E1000_RCTL_CFIEN; 8610 wr32(E1000_RCTL, rctl); 8611 } else { 8612 /* disable VLAN tag insert/strip */ 8613 ctrl = rd32(E1000_CTRL); 8614 ctrl &= ~E1000_CTRL_VME; 8615 wr32(E1000_CTRL, ctrl); 8616 } 8617 8618 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8619 } 8620 8621 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8622 __be16 proto, u16 vid) 8623 { 8624 struct igb_adapter *adapter = netdev_priv(netdev); 8625 struct e1000_hw *hw = &adapter->hw; 8626 int pf_id = adapter->vfs_allocated_count; 8627 8628 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8629 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8630 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8631 8632 set_bit(vid, adapter->active_vlans); 8633 8634 return 0; 8635 } 8636 8637 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8638 __be16 proto, u16 vid) 8639 { 8640 struct igb_adapter *adapter = netdev_priv(netdev); 8641 int pf_id = adapter->vfs_allocated_count; 8642 struct e1000_hw *hw = &adapter->hw; 8643 8644 /* remove VID from filter table */ 8645 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8646 igb_vfta_set(hw, vid, pf_id, false, true); 8647 8648 clear_bit(vid, adapter->active_vlans); 8649 8650 return 0; 8651 } 8652 8653 static void igb_restore_vlan(struct igb_adapter *adapter) 8654 { 8655 u16 vid = 1; 8656 8657 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8658 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8659 8660 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8661 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8662 } 8663 8664 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8665 { 8666 struct pci_dev *pdev = adapter->pdev; 8667 struct e1000_mac_info *mac = &adapter->hw.mac; 8668 8669 mac->autoneg = 0; 8670 8671 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8672 * for the switch() below to work 8673 */ 8674 if ((spd & 1) || (dplx & ~1)) 8675 goto err_inval; 8676 8677 /* Fiber NIC's only allow 1000 gbps Full duplex 8678 * and 100Mbps Full duplex for 100baseFx sfp 8679 */ 8680 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8681 switch (spd + dplx) { 8682 case SPEED_10 + DUPLEX_HALF: 8683 case SPEED_10 + DUPLEX_FULL: 8684 case SPEED_100 + DUPLEX_HALF: 8685 goto err_inval; 8686 default: 8687 break; 8688 } 8689 } 8690 8691 switch (spd + dplx) { 8692 case SPEED_10 + DUPLEX_HALF: 8693 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8694 break; 8695 case SPEED_10 + DUPLEX_FULL: 8696 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8697 break; 8698 case SPEED_100 + DUPLEX_HALF: 8699 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8700 break; 8701 case SPEED_100 + DUPLEX_FULL: 8702 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8703 break; 8704 case SPEED_1000 + DUPLEX_FULL: 8705 mac->autoneg = 1; 8706 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8707 break; 8708 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8709 default: 8710 goto err_inval; 8711 } 8712 8713 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8714 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8715 8716 return 0; 8717 8718 err_inval: 8719 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8720 return -EINVAL; 8721 } 8722 8723 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8724 bool runtime) 8725 { 8726 struct net_device *netdev = pci_get_drvdata(pdev); 8727 struct igb_adapter *adapter = netdev_priv(netdev); 8728 struct e1000_hw *hw = &adapter->hw; 8729 u32 ctrl, rctl, status; 8730 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8731 bool wake; 8732 8733 rtnl_lock(); 8734 netif_device_detach(netdev); 8735 8736 if (netif_running(netdev)) 8737 __igb_close(netdev, true); 8738 8739 igb_ptp_suspend(adapter); 8740 8741 igb_clear_interrupt_scheme(adapter); 8742 rtnl_unlock(); 8743 8744 status = rd32(E1000_STATUS); 8745 if (status & E1000_STATUS_LU) 8746 wufc &= ~E1000_WUFC_LNKC; 8747 8748 if (wufc) { 8749 igb_setup_rctl(adapter); 8750 igb_set_rx_mode(netdev); 8751 8752 /* turn on all-multi mode if wake on multicast is enabled */ 8753 if (wufc & E1000_WUFC_MC) { 8754 rctl = rd32(E1000_RCTL); 8755 rctl |= E1000_RCTL_MPE; 8756 wr32(E1000_RCTL, rctl); 8757 } 8758 8759 ctrl = rd32(E1000_CTRL); 8760 ctrl |= E1000_CTRL_ADVD3WUC; 8761 wr32(E1000_CTRL, ctrl); 8762 8763 /* Allow time for pending master requests to run */ 8764 igb_disable_pcie_master(hw); 8765 8766 wr32(E1000_WUC, E1000_WUC_PME_EN); 8767 wr32(E1000_WUFC, wufc); 8768 } else { 8769 wr32(E1000_WUC, 0); 8770 wr32(E1000_WUFC, 0); 8771 } 8772 8773 wake = wufc || adapter->en_mng_pt; 8774 if (!wake) 8775 igb_power_down_link(adapter); 8776 else 8777 igb_power_up_link(adapter); 8778 8779 if (enable_wake) 8780 *enable_wake = wake; 8781 8782 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8783 * would have already happened in close and is redundant. 8784 */ 8785 igb_release_hw_control(adapter); 8786 8787 pci_disable_device(pdev); 8788 8789 return 0; 8790 } 8791 8792 static void igb_deliver_wake_packet(struct net_device *netdev) 8793 { 8794 struct igb_adapter *adapter = netdev_priv(netdev); 8795 struct e1000_hw *hw = &adapter->hw; 8796 struct sk_buff *skb; 8797 u32 wupl; 8798 8799 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8800 8801 /* WUPM stores only the first 128 bytes of the wake packet. 8802 * Read the packet only if we have the whole thing. 8803 */ 8804 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8805 return; 8806 8807 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8808 if (!skb) 8809 return; 8810 8811 skb_put(skb, wupl); 8812 8813 /* Ensure reads are 32-bit aligned */ 8814 wupl = roundup(wupl, 4); 8815 8816 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8817 8818 skb->protocol = eth_type_trans(skb, netdev); 8819 netif_rx(skb); 8820 } 8821 8822 static int __maybe_unused igb_suspend(struct device *dev) 8823 { 8824 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 8825 } 8826 8827 static int __maybe_unused igb_resume(struct device *dev) 8828 { 8829 struct pci_dev *pdev = to_pci_dev(dev); 8830 struct net_device *netdev = pci_get_drvdata(pdev); 8831 struct igb_adapter *adapter = netdev_priv(netdev); 8832 struct e1000_hw *hw = &adapter->hw; 8833 u32 err, val; 8834 8835 pci_set_power_state(pdev, PCI_D0); 8836 pci_restore_state(pdev); 8837 pci_save_state(pdev); 8838 8839 if (!pci_device_is_present(pdev)) 8840 return -ENODEV; 8841 err = pci_enable_device_mem(pdev); 8842 if (err) { 8843 dev_err(&pdev->dev, 8844 "igb: Cannot enable PCI device from suspend\n"); 8845 return err; 8846 } 8847 pci_set_master(pdev); 8848 8849 pci_enable_wake(pdev, PCI_D3hot, 0); 8850 pci_enable_wake(pdev, PCI_D3cold, 0); 8851 8852 if (igb_init_interrupt_scheme(adapter, true)) { 8853 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8854 return -ENOMEM; 8855 } 8856 8857 igb_reset(adapter); 8858 8859 /* let the f/w know that the h/w is now under the control of the 8860 * driver. 8861 */ 8862 igb_get_hw_control(adapter); 8863 8864 val = rd32(E1000_WUS); 8865 if (val & WAKE_PKT_WUS) 8866 igb_deliver_wake_packet(netdev); 8867 8868 wr32(E1000_WUS, ~0); 8869 8870 rtnl_lock(); 8871 if (!err && netif_running(netdev)) 8872 err = __igb_open(netdev, true); 8873 8874 if (!err) 8875 netif_device_attach(netdev); 8876 rtnl_unlock(); 8877 8878 return err; 8879 } 8880 8881 static int __maybe_unused igb_runtime_idle(struct device *dev) 8882 { 8883 struct net_device *netdev = dev_get_drvdata(dev); 8884 struct igb_adapter *adapter = netdev_priv(netdev); 8885 8886 if (!igb_has_link(adapter)) 8887 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8888 8889 return -EBUSY; 8890 } 8891 8892 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8893 { 8894 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 8895 } 8896 8897 static int __maybe_unused igb_runtime_resume(struct device *dev) 8898 { 8899 return igb_resume(dev); 8900 } 8901 8902 static void igb_shutdown(struct pci_dev *pdev) 8903 { 8904 bool wake; 8905 8906 __igb_shutdown(pdev, &wake, 0); 8907 8908 if (system_state == SYSTEM_POWER_OFF) { 8909 pci_wake_from_d3(pdev, wake); 8910 pci_set_power_state(pdev, PCI_D3hot); 8911 } 8912 } 8913 8914 #ifdef CONFIG_PCI_IOV 8915 static int igb_sriov_reinit(struct pci_dev *dev) 8916 { 8917 struct net_device *netdev = pci_get_drvdata(dev); 8918 struct igb_adapter *adapter = netdev_priv(netdev); 8919 struct pci_dev *pdev = adapter->pdev; 8920 8921 rtnl_lock(); 8922 8923 if (netif_running(netdev)) 8924 igb_close(netdev); 8925 else 8926 igb_reset(adapter); 8927 8928 igb_clear_interrupt_scheme(adapter); 8929 8930 igb_init_queue_configuration(adapter); 8931 8932 if (igb_init_interrupt_scheme(adapter, true)) { 8933 rtnl_unlock(); 8934 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8935 return -ENOMEM; 8936 } 8937 8938 if (netif_running(netdev)) 8939 igb_open(netdev); 8940 8941 rtnl_unlock(); 8942 8943 return 0; 8944 } 8945 8946 static int igb_pci_disable_sriov(struct pci_dev *dev) 8947 { 8948 int err = igb_disable_sriov(dev); 8949 8950 if (!err) 8951 err = igb_sriov_reinit(dev); 8952 8953 return err; 8954 } 8955 8956 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8957 { 8958 int err = igb_enable_sriov(dev, num_vfs); 8959 8960 if (err) 8961 goto out; 8962 8963 err = igb_sriov_reinit(dev); 8964 if (!err) 8965 return num_vfs; 8966 8967 out: 8968 return err; 8969 } 8970 8971 #endif 8972 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8973 { 8974 #ifdef CONFIG_PCI_IOV 8975 if (num_vfs == 0) 8976 return igb_pci_disable_sriov(dev); 8977 else 8978 return igb_pci_enable_sriov(dev, num_vfs); 8979 #endif 8980 return 0; 8981 } 8982 8983 /** 8984 * igb_io_error_detected - called when PCI error is detected 8985 * @pdev: Pointer to PCI device 8986 * @state: The current pci connection state 8987 * 8988 * This function is called after a PCI bus error affecting 8989 * this device has been detected. 8990 **/ 8991 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8992 pci_channel_state_t state) 8993 { 8994 struct net_device *netdev = pci_get_drvdata(pdev); 8995 struct igb_adapter *adapter = netdev_priv(netdev); 8996 8997 netif_device_detach(netdev); 8998 8999 if (state == pci_channel_io_perm_failure) 9000 return PCI_ERS_RESULT_DISCONNECT; 9001 9002 if (netif_running(netdev)) 9003 igb_down(adapter); 9004 pci_disable_device(pdev); 9005 9006 /* Request a slot slot reset. */ 9007 return PCI_ERS_RESULT_NEED_RESET; 9008 } 9009 9010 /** 9011 * igb_io_slot_reset - called after the pci bus has been reset. 9012 * @pdev: Pointer to PCI device 9013 * 9014 * Restart the card from scratch, as if from a cold-boot. Implementation 9015 * resembles the first-half of the igb_resume routine. 9016 **/ 9017 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9018 { 9019 struct net_device *netdev = pci_get_drvdata(pdev); 9020 struct igb_adapter *adapter = netdev_priv(netdev); 9021 struct e1000_hw *hw = &adapter->hw; 9022 pci_ers_result_t result; 9023 9024 if (pci_enable_device_mem(pdev)) { 9025 dev_err(&pdev->dev, 9026 "Cannot re-enable PCI device after reset.\n"); 9027 result = PCI_ERS_RESULT_DISCONNECT; 9028 } else { 9029 pci_set_master(pdev); 9030 pci_restore_state(pdev); 9031 pci_save_state(pdev); 9032 9033 pci_enable_wake(pdev, PCI_D3hot, 0); 9034 pci_enable_wake(pdev, PCI_D3cold, 0); 9035 9036 /* In case of PCI error, adapter lose its HW address 9037 * so we should re-assign it here. 9038 */ 9039 hw->hw_addr = adapter->io_addr; 9040 9041 igb_reset(adapter); 9042 wr32(E1000_WUS, ~0); 9043 result = PCI_ERS_RESULT_RECOVERED; 9044 } 9045 9046 return result; 9047 } 9048 9049 /** 9050 * igb_io_resume - called when traffic can start flowing again. 9051 * @pdev: Pointer to PCI device 9052 * 9053 * This callback is called when the error recovery driver tells us that 9054 * its OK to resume normal operation. Implementation resembles the 9055 * second-half of the igb_resume routine. 9056 */ 9057 static void igb_io_resume(struct pci_dev *pdev) 9058 { 9059 struct net_device *netdev = pci_get_drvdata(pdev); 9060 struct igb_adapter *adapter = netdev_priv(netdev); 9061 9062 if (netif_running(netdev)) { 9063 if (igb_up(adapter)) { 9064 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9065 return; 9066 } 9067 } 9068 9069 netif_device_attach(netdev); 9070 9071 /* let the f/w know that the h/w is now under the control of the 9072 * driver. 9073 */ 9074 igb_get_hw_control(adapter); 9075 } 9076 9077 /** 9078 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9079 * @adapter: Pointer to adapter structure 9080 * @index: Index of the RAR entry which need to be synced with MAC table 9081 **/ 9082 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9083 { 9084 struct e1000_hw *hw = &adapter->hw; 9085 u32 rar_low, rar_high; 9086 u8 *addr = adapter->mac_table[index].addr; 9087 9088 /* HW expects these to be in network order when they are plugged 9089 * into the registers which are little endian. In order to guarantee 9090 * that ordering we need to do an leXX_to_cpup here in order to be 9091 * ready for the byteswap that occurs with writel 9092 */ 9093 rar_low = le32_to_cpup((__le32 *)(addr)); 9094 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9095 9096 /* Indicate to hardware the Address is Valid. */ 9097 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9098 if (is_valid_ether_addr(addr)) 9099 rar_high |= E1000_RAH_AV; 9100 9101 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9102 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9103 9104 switch (hw->mac.type) { 9105 case e1000_82575: 9106 case e1000_i210: 9107 if (adapter->mac_table[index].state & 9108 IGB_MAC_STATE_QUEUE_STEERING) 9109 rar_high |= E1000_RAH_QSEL_ENABLE; 9110 9111 rar_high |= E1000_RAH_POOL_1 * 9112 adapter->mac_table[index].queue; 9113 break; 9114 default: 9115 rar_high |= E1000_RAH_POOL_1 << 9116 adapter->mac_table[index].queue; 9117 break; 9118 } 9119 } 9120 9121 wr32(E1000_RAL(index), rar_low); 9122 wrfl(); 9123 wr32(E1000_RAH(index), rar_high); 9124 wrfl(); 9125 } 9126 9127 static int igb_set_vf_mac(struct igb_adapter *adapter, 9128 int vf, unsigned char *mac_addr) 9129 { 9130 struct e1000_hw *hw = &adapter->hw; 9131 /* VF MAC addresses start at end of receive addresses and moves 9132 * towards the first, as a result a collision should not be possible 9133 */ 9134 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9135 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9136 9137 ether_addr_copy(vf_mac_addr, mac_addr); 9138 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9139 adapter->mac_table[rar_entry].queue = vf; 9140 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9141 igb_rar_set_index(adapter, rar_entry); 9142 9143 return 0; 9144 } 9145 9146 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9147 { 9148 struct igb_adapter *adapter = netdev_priv(netdev); 9149 9150 if (vf >= adapter->vfs_allocated_count) 9151 return -EINVAL; 9152 9153 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9154 * flag and allows to overwrite the MAC via VF netdev. This 9155 * is necessary to allow libvirt a way to restore the original 9156 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9157 * down a VM. 9158 */ 9159 if (is_zero_ether_addr(mac)) { 9160 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9161 dev_info(&adapter->pdev->dev, 9162 "remove administratively set MAC on VF %d\n", 9163 vf); 9164 } else if (is_valid_ether_addr(mac)) { 9165 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9166 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9167 mac, vf); 9168 dev_info(&adapter->pdev->dev, 9169 "Reload the VF driver to make this change effective."); 9170 /* Generate additional warning if PF is down */ 9171 if (test_bit(__IGB_DOWN, &adapter->state)) { 9172 dev_warn(&adapter->pdev->dev, 9173 "The VF MAC address has been set, but the PF device is not up.\n"); 9174 dev_warn(&adapter->pdev->dev, 9175 "Bring the PF device up before attempting to use the VF device.\n"); 9176 } 9177 } else { 9178 return -EINVAL; 9179 } 9180 return igb_set_vf_mac(adapter, vf, mac); 9181 } 9182 9183 static int igb_link_mbps(int internal_link_speed) 9184 { 9185 switch (internal_link_speed) { 9186 case SPEED_100: 9187 return 100; 9188 case SPEED_1000: 9189 return 1000; 9190 default: 9191 return 0; 9192 } 9193 } 9194 9195 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9196 int link_speed) 9197 { 9198 int rf_dec, rf_int; 9199 u32 bcnrc_val; 9200 9201 if (tx_rate != 0) { 9202 /* Calculate the rate factor values to set */ 9203 rf_int = link_speed / tx_rate; 9204 rf_dec = (link_speed - (rf_int * tx_rate)); 9205 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9206 tx_rate; 9207 9208 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9209 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9210 E1000_RTTBCNRC_RF_INT_MASK); 9211 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9212 } else { 9213 bcnrc_val = 0; 9214 } 9215 9216 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9217 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9218 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9219 */ 9220 wr32(E1000_RTTBCNRM, 0x14); 9221 wr32(E1000_RTTBCNRC, bcnrc_val); 9222 } 9223 9224 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9225 { 9226 int actual_link_speed, i; 9227 bool reset_rate = false; 9228 9229 /* VF TX rate limit was not set or not supported */ 9230 if ((adapter->vf_rate_link_speed == 0) || 9231 (adapter->hw.mac.type != e1000_82576)) 9232 return; 9233 9234 actual_link_speed = igb_link_mbps(adapter->link_speed); 9235 if (actual_link_speed != adapter->vf_rate_link_speed) { 9236 reset_rate = true; 9237 adapter->vf_rate_link_speed = 0; 9238 dev_info(&adapter->pdev->dev, 9239 "Link speed has been changed. VF Transmit rate is disabled\n"); 9240 } 9241 9242 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9243 if (reset_rate) 9244 adapter->vf_data[i].tx_rate = 0; 9245 9246 igb_set_vf_rate_limit(&adapter->hw, i, 9247 adapter->vf_data[i].tx_rate, 9248 actual_link_speed); 9249 } 9250 } 9251 9252 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9253 int min_tx_rate, int max_tx_rate) 9254 { 9255 struct igb_adapter *adapter = netdev_priv(netdev); 9256 struct e1000_hw *hw = &adapter->hw; 9257 int actual_link_speed; 9258 9259 if (hw->mac.type != e1000_82576) 9260 return -EOPNOTSUPP; 9261 9262 if (min_tx_rate) 9263 return -EINVAL; 9264 9265 actual_link_speed = igb_link_mbps(adapter->link_speed); 9266 if ((vf >= adapter->vfs_allocated_count) || 9267 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9268 (max_tx_rate < 0) || 9269 (max_tx_rate > actual_link_speed)) 9270 return -EINVAL; 9271 9272 adapter->vf_rate_link_speed = actual_link_speed; 9273 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9274 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9275 9276 return 0; 9277 } 9278 9279 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9280 bool setting) 9281 { 9282 struct igb_adapter *adapter = netdev_priv(netdev); 9283 struct e1000_hw *hw = &adapter->hw; 9284 u32 reg_val, reg_offset; 9285 9286 if (!adapter->vfs_allocated_count) 9287 return -EOPNOTSUPP; 9288 9289 if (vf >= adapter->vfs_allocated_count) 9290 return -EINVAL; 9291 9292 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9293 reg_val = rd32(reg_offset); 9294 if (setting) 9295 reg_val |= (BIT(vf) | 9296 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9297 else 9298 reg_val &= ~(BIT(vf) | 9299 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9300 wr32(reg_offset, reg_val); 9301 9302 adapter->vf_data[vf].spoofchk_enabled = setting; 9303 return 0; 9304 } 9305 9306 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9307 { 9308 struct igb_adapter *adapter = netdev_priv(netdev); 9309 9310 if (vf >= adapter->vfs_allocated_count) 9311 return -EINVAL; 9312 if (adapter->vf_data[vf].trusted == setting) 9313 return 0; 9314 9315 adapter->vf_data[vf].trusted = setting; 9316 9317 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9318 vf, setting ? "" : "not "); 9319 return 0; 9320 } 9321 9322 static int igb_ndo_get_vf_config(struct net_device *netdev, 9323 int vf, struct ifla_vf_info *ivi) 9324 { 9325 struct igb_adapter *adapter = netdev_priv(netdev); 9326 if (vf >= adapter->vfs_allocated_count) 9327 return -EINVAL; 9328 ivi->vf = vf; 9329 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9330 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9331 ivi->min_tx_rate = 0; 9332 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9333 ivi->qos = adapter->vf_data[vf].pf_qos; 9334 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9335 ivi->trusted = adapter->vf_data[vf].trusted; 9336 return 0; 9337 } 9338 9339 static void igb_vmm_control(struct igb_adapter *adapter) 9340 { 9341 struct e1000_hw *hw = &adapter->hw; 9342 u32 reg; 9343 9344 switch (hw->mac.type) { 9345 case e1000_82575: 9346 case e1000_i210: 9347 case e1000_i211: 9348 case e1000_i354: 9349 default: 9350 /* replication is not supported for 82575 */ 9351 return; 9352 case e1000_82576: 9353 /* notify HW that the MAC is adding vlan tags */ 9354 reg = rd32(E1000_DTXCTL); 9355 reg |= E1000_DTXCTL_VLAN_ADDED; 9356 wr32(E1000_DTXCTL, reg); 9357 /* Fall through */ 9358 case e1000_82580: 9359 /* enable replication vlan tag stripping */ 9360 reg = rd32(E1000_RPLOLR); 9361 reg |= E1000_RPLOLR_STRVLAN; 9362 wr32(E1000_RPLOLR, reg); 9363 /* Fall through */ 9364 case e1000_i350: 9365 /* none of the above registers are supported by i350 */ 9366 break; 9367 } 9368 9369 if (adapter->vfs_allocated_count) { 9370 igb_vmdq_set_loopback_pf(hw, true); 9371 igb_vmdq_set_replication_pf(hw, true); 9372 igb_vmdq_set_anti_spoofing_pf(hw, true, 9373 adapter->vfs_allocated_count); 9374 } else { 9375 igb_vmdq_set_loopback_pf(hw, false); 9376 igb_vmdq_set_replication_pf(hw, false); 9377 } 9378 } 9379 9380 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9381 { 9382 struct e1000_hw *hw = &adapter->hw; 9383 u32 dmac_thr; 9384 u16 hwm; 9385 9386 if (hw->mac.type > e1000_82580) { 9387 if (adapter->flags & IGB_FLAG_DMAC) { 9388 u32 reg; 9389 9390 /* force threshold to 0. */ 9391 wr32(E1000_DMCTXTH, 0); 9392 9393 /* DMA Coalescing high water mark needs to be greater 9394 * than the Rx threshold. Set hwm to PBA - max frame 9395 * size in 16B units, capping it at PBA - 6KB. 9396 */ 9397 hwm = 64 * (pba - 6); 9398 reg = rd32(E1000_FCRTC); 9399 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9400 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9401 & E1000_FCRTC_RTH_COAL_MASK); 9402 wr32(E1000_FCRTC, reg); 9403 9404 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9405 * frame size, capping it at PBA - 10KB. 9406 */ 9407 dmac_thr = pba - 10; 9408 reg = rd32(E1000_DMACR); 9409 reg &= ~E1000_DMACR_DMACTHR_MASK; 9410 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9411 & E1000_DMACR_DMACTHR_MASK); 9412 9413 /* transition to L0x or L1 if available..*/ 9414 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9415 9416 /* watchdog timer= +-1000 usec in 32usec intervals */ 9417 reg |= (1000 >> 5); 9418 9419 /* Disable BMC-to-OS Watchdog Enable */ 9420 if (hw->mac.type != e1000_i354) 9421 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9422 9423 wr32(E1000_DMACR, reg); 9424 9425 /* no lower threshold to disable 9426 * coalescing(smart fifb)-UTRESH=0 9427 */ 9428 wr32(E1000_DMCRTRH, 0); 9429 9430 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9431 9432 wr32(E1000_DMCTLX, reg); 9433 9434 /* free space in tx packet buffer to wake from 9435 * DMA coal 9436 */ 9437 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9438 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9439 9440 /* make low power state decision controlled 9441 * by DMA coal 9442 */ 9443 reg = rd32(E1000_PCIEMISC); 9444 reg &= ~E1000_PCIEMISC_LX_DECISION; 9445 wr32(E1000_PCIEMISC, reg); 9446 } /* endif adapter->dmac is not disabled */ 9447 } else if (hw->mac.type == e1000_82580) { 9448 u32 reg = rd32(E1000_PCIEMISC); 9449 9450 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9451 wr32(E1000_DMACR, 0); 9452 } 9453 } 9454 9455 /** 9456 * igb_read_i2c_byte - Reads 8 bit word over I2C 9457 * @hw: pointer to hardware structure 9458 * @byte_offset: byte offset to read 9459 * @dev_addr: device address 9460 * @data: value read 9461 * 9462 * Performs byte read operation over I2C interface at 9463 * a specified device address. 9464 **/ 9465 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9466 u8 dev_addr, u8 *data) 9467 { 9468 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9469 struct i2c_client *this_client = adapter->i2c_client; 9470 s32 status; 9471 u16 swfw_mask = 0; 9472 9473 if (!this_client) 9474 return E1000_ERR_I2C; 9475 9476 swfw_mask = E1000_SWFW_PHY0_SM; 9477 9478 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9479 return E1000_ERR_SWFW_SYNC; 9480 9481 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9482 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9483 9484 if (status < 0) 9485 return E1000_ERR_I2C; 9486 else { 9487 *data = status; 9488 return 0; 9489 } 9490 } 9491 9492 /** 9493 * igb_write_i2c_byte - Writes 8 bit word over I2C 9494 * @hw: pointer to hardware structure 9495 * @byte_offset: byte offset to write 9496 * @dev_addr: device address 9497 * @data: value to write 9498 * 9499 * Performs byte write operation over I2C interface at 9500 * a specified device address. 9501 **/ 9502 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9503 u8 dev_addr, u8 data) 9504 { 9505 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9506 struct i2c_client *this_client = adapter->i2c_client; 9507 s32 status; 9508 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9509 9510 if (!this_client) 9511 return E1000_ERR_I2C; 9512 9513 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9514 return E1000_ERR_SWFW_SYNC; 9515 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9516 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9517 9518 if (status) 9519 return E1000_ERR_I2C; 9520 else 9521 return 0; 9522 9523 } 9524 9525 int igb_reinit_queues(struct igb_adapter *adapter) 9526 { 9527 struct net_device *netdev = adapter->netdev; 9528 struct pci_dev *pdev = adapter->pdev; 9529 int err = 0; 9530 9531 if (netif_running(netdev)) 9532 igb_close(netdev); 9533 9534 igb_reset_interrupt_capability(adapter); 9535 9536 if (igb_init_interrupt_scheme(adapter, true)) { 9537 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9538 return -ENOMEM; 9539 } 9540 9541 if (netif_running(netdev)) 9542 err = igb_open(netdev); 9543 9544 return err; 9545 } 9546 9547 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9548 { 9549 struct igb_nfc_filter *rule; 9550 9551 spin_lock(&adapter->nfc_lock); 9552 9553 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9554 igb_erase_filter(adapter, rule); 9555 9556 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9557 igb_erase_filter(adapter, rule); 9558 9559 spin_unlock(&adapter->nfc_lock); 9560 } 9561 9562 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9563 { 9564 struct igb_nfc_filter *rule; 9565 9566 spin_lock(&adapter->nfc_lock); 9567 9568 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9569 igb_add_filter(adapter, rule); 9570 9571 spin_unlock(&adapter->nfc_lock); 9572 } 9573 /* igb_main.c */ 9574