1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/pci-aspm.h> 26 #include <linux/delay.h> 27 #include <linux/interrupt.h> 28 #include <linux/ip.h> 29 #include <linux/tcp.h> 30 #include <linux/sctp.h> 31 #include <linux/if_ether.h> 32 #include <linux/aer.h> 33 #include <linux/prefetch.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 #define MAJ 5 43 #define MIN 4 44 #define BUILD 0 45 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 46 __stringify(BUILD) "-k" 47 48 enum queue_mode { 49 QUEUE_MODE_STRICT_PRIORITY, 50 QUEUE_MODE_STREAM_RESERVATION, 51 }; 52 53 enum tx_queue_prio { 54 TX_QUEUE_PRIO_HIGH, 55 TX_QUEUE_PRIO_LOW, 56 }; 57 58 char igb_driver_name[] = "igb"; 59 char igb_driver_version[] = DRV_VERSION; 60 static const char igb_driver_string[] = 61 "Intel(R) Gigabit Ethernet Network Driver"; 62 static const char igb_copyright[] = 63 "Copyright (c) 2007-2014 Intel Corporation."; 64 65 static const struct e1000_info *igb_info_tbl[] = { 66 [board_82575] = &e1000_82575_info, 67 }; 68 69 static const struct pci_device_id igb_pci_tbl[] = { 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 105 /* required last entry */ 106 {0, } 107 }; 108 109 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 110 111 static int igb_setup_all_tx_resources(struct igb_adapter *); 112 static int igb_setup_all_rx_resources(struct igb_adapter *); 113 static void igb_free_all_tx_resources(struct igb_adapter *); 114 static void igb_free_all_rx_resources(struct igb_adapter *); 115 static void igb_setup_mrqc(struct igb_adapter *); 116 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 117 static void igb_remove(struct pci_dev *pdev); 118 static int igb_sw_init(struct igb_adapter *); 119 int igb_open(struct net_device *); 120 int igb_close(struct net_device *); 121 static void igb_configure(struct igb_adapter *); 122 static void igb_configure_tx(struct igb_adapter *); 123 static void igb_configure_rx(struct igb_adapter *); 124 static void igb_clean_all_tx_rings(struct igb_adapter *); 125 static void igb_clean_all_rx_rings(struct igb_adapter *); 126 static void igb_clean_tx_ring(struct igb_ring *); 127 static void igb_clean_rx_ring(struct igb_ring *); 128 static void igb_set_rx_mode(struct net_device *); 129 static void igb_update_phy_info(struct timer_list *); 130 static void igb_watchdog(struct timer_list *); 131 static void igb_watchdog_task(struct work_struct *); 132 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 133 static void igb_get_stats64(struct net_device *dev, 134 struct rtnl_link_stats64 *stats); 135 static int igb_change_mtu(struct net_device *, int); 136 static int igb_set_mac(struct net_device *, void *); 137 static void igb_set_uta(struct igb_adapter *adapter, bool set); 138 static irqreturn_t igb_intr(int irq, void *); 139 static irqreturn_t igb_intr_msi(int irq, void *); 140 static irqreturn_t igb_msix_other(int irq, void *); 141 static irqreturn_t igb_msix_ring(int irq, void *); 142 #ifdef CONFIG_IGB_DCA 143 static void igb_update_dca(struct igb_q_vector *); 144 static void igb_setup_dca(struct igb_adapter *); 145 #endif /* CONFIG_IGB_DCA */ 146 static int igb_poll(struct napi_struct *, int); 147 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 148 static int igb_clean_rx_irq(struct igb_q_vector *, int); 149 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 150 static void igb_tx_timeout(struct net_device *); 151 static void igb_reset_task(struct work_struct *); 152 static void igb_vlan_mode(struct net_device *netdev, 153 netdev_features_t features); 154 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 155 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 156 static void igb_restore_vlan(struct igb_adapter *); 157 static void igb_rar_set_index(struct igb_adapter *, u32); 158 static void igb_ping_all_vfs(struct igb_adapter *); 159 static void igb_msg_task(struct igb_adapter *); 160 static void igb_vmm_control(struct igb_adapter *); 161 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 162 static void igb_flush_mac_table(struct igb_adapter *); 163 static int igb_available_rars(struct igb_adapter *, u8); 164 static void igb_set_default_mac_filter(struct igb_adapter *); 165 static int igb_uc_sync(struct net_device *, const unsigned char *); 166 static int igb_uc_unsync(struct net_device *, const unsigned char *); 167 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 168 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 169 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 170 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 171 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 172 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 173 bool setting); 174 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 180 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 181 182 #ifdef CONFIG_PCI_IOV 183 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185 static int igb_disable_sriov(struct pci_dev *dev); 186 static int igb_pci_disable_sriov(struct pci_dev *dev); 187 #endif 188 189 static int igb_suspend(struct device *); 190 static int igb_resume(struct device *); 191 static int igb_runtime_suspend(struct device *dev); 192 static int igb_runtime_resume(struct device *dev); 193 static int igb_runtime_idle(struct device *dev); 194 static const struct dev_pm_ops igb_pm_ops = { 195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 197 igb_runtime_idle) 198 }; 199 static void igb_shutdown(struct pci_dev *); 200 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 201 #ifdef CONFIG_IGB_DCA 202 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 203 static struct notifier_block dca_notifier = { 204 .notifier_call = igb_notify_dca, 205 .next = NULL, 206 .priority = 0 207 }; 208 #endif 209 #ifdef CONFIG_NET_POLL_CONTROLLER 210 /* for netdump / net console */ 211 static void igb_netpoll(struct net_device *); 212 #endif 213 #ifdef CONFIG_PCI_IOV 214 static unsigned int max_vfs; 215 module_param(max_vfs, uint, 0); 216 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 217 #endif /* CONFIG_PCI_IOV */ 218 219 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 220 pci_channel_state_t); 221 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 222 static void igb_io_resume(struct pci_dev *); 223 224 static const struct pci_error_handlers igb_err_handler = { 225 .error_detected = igb_io_error_detected, 226 .slot_reset = igb_io_slot_reset, 227 .resume = igb_io_resume, 228 }; 229 230 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 231 232 static struct pci_driver igb_driver = { 233 .name = igb_driver_name, 234 .id_table = igb_pci_tbl, 235 .probe = igb_probe, 236 .remove = igb_remove, 237 #ifdef CONFIG_PM 238 .driver.pm = &igb_pm_ops, 239 #endif 240 .shutdown = igb_shutdown, 241 .sriov_configure = igb_pci_sriov_configure, 242 .err_handler = &igb_err_handler 243 }; 244 245 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 246 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 247 MODULE_LICENSE("GPL"); 248 MODULE_VERSION(DRV_VERSION); 249 250 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 251 static int debug = -1; 252 module_param(debug, int, 0); 253 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 254 255 struct igb_reg_info { 256 u32 ofs; 257 char *name; 258 }; 259 260 static const struct igb_reg_info igb_reg_info_tbl[] = { 261 262 /* General Registers */ 263 {E1000_CTRL, "CTRL"}, 264 {E1000_STATUS, "STATUS"}, 265 {E1000_CTRL_EXT, "CTRL_EXT"}, 266 267 /* Interrupt Registers */ 268 {E1000_ICR, "ICR"}, 269 270 /* RX Registers */ 271 {E1000_RCTL, "RCTL"}, 272 {E1000_RDLEN(0), "RDLEN"}, 273 {E1000_RDH(0), "RDH"}, 274 {E1000_RDT(0), "RDT"}, 275 {E1000_RXDCTL(0), "RXDCTL"}, 276 {E1000_RDBAL(0), "RDBAL"}, 277 {E1000_RDBAH(0), "RDBAH"}, 278 279 /* TX Registers */ 280 {E1000_TCTL, "TCTL"}, 281 {E1000_TDBAL(0), "TDBAL"}, 282 {E1000_TDBAH(0), "TDBAH"}, 283 {E1000_TDLEN(0), "TDLEN"}, 284 {E1000_TDH(0), "TDH"}, 285 {E1000_TDT(0), "TDT"}, 286 {E1000_TXDCTL(0), "TXDCTL"}, 287 {E1000_TDFH, "TDFH"}, 288 {E1000_TDFT, "TDFT"}, 289 {E1000_TDFHS, "TDFHS"}, 290 {E1000_TDFPC, "TDFPC"}, 291 292 /* List Terminator */ 293 {} 294 }; 295 296 /* igb_regdump - register printout routine */ 297 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 298 { 299 int n = 0; 300 char rname[16]; 301 u32 regs[8]; 302 303 switch (reginfo->ofs) { 304 case E1000_RDLEN(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDLEN(n)); 307 break; 308 case E1000_RDH(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDH(n)); 311 break; 312 case E1000_RDT(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDT(n)); 315 break; 316 case E1000_RXDCTL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RXDCTL(n)); 319 break; 320 case E1000_RDBAL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAL(n)); 323 break; 324 case E1000_RDBAH(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAH(n)); 327 break; 328 case E1000_TDBAL(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAL(n)); 331 break; 332 case E1000_TDBAH(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDBAH(n)); 335 break; 336 case E1000_TDLEN(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDLEN(n)); 339 break; 340 case E1000_TDH(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDH(n)); 343 break; 344 case E1000_TDT(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDT(n)); 347 break; 348 case E1000_TXDCTL(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TXDCTL(n)); 351 break; 352 default: 353 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 354 return; 355 } 356 357 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 358 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 359 regs[2], regs[3]); 360 } 361 362 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 363 static void igb_dump(struct igb_adapter *adapter) 364 { 365 struct net_device *netdev = adapter->netdev; 366 struct e1000_hw *hw = &adapter->hw; 367 struct igb_reg_info *reginfo; 368 struct igb_ring *tx_ring; 369 union e1000_adv_tx_desc *tx_desc; 370 struct my_u0 { u64 a; u64 b; } *u0; 371 struct igb_ring *rx_ring; 372 union e1000_adv_rx_desc *rx_desc; 373 u32 staterr; 374 u16 i, n; 375 376 if (!netif_msg_hw(adapter)) 377 return; 378 379 /* Print netdevice Info */ 380 if (netdev) { 381 dev_info(&adapter->pdev->dev, "Net device Info\n"); 382 pr_info("Device Name state trans_start\n"); 383 pr_info("%-15s %016lX %016lX\n", netdev->name, 384 netdev->state, dev_trans_start(netdev)); 385 } 386 387 /* Print Registers */ 388 dev_info(&adapter->pdev->dev, "Register Dump\n"); 389 pr_info(" Register Name Value\n"); 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 391 reginfo->name; reginfo++) { 392 igb_regdump(hw, reginfo); 393 } 394 395 /* Print TX Ring Summary */ 396 if (!netdev || !netif_running(netdev)) 397 goto exit; 398 399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 401 for (n = 0; n < adapter->num_tx_queues; n++) { 402 struct igb_tx_buffer *buffer_info; 403 tx_ring = adapter->tx_ring[n]; 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 406 n, tx_ring->next_to_use, tx_ring->next_to_clean, 407 (u64)dma_unmap_addr(buffer_info, dma), 408 dma_unmap_len(buffer_info, len), 409 buffer_info->next_to_watch, 410 (u64)buffer_info->time_stamp); 411 } 412 413 /* Print TX Rings */ 414 if (!netif_msg_tx_done(adapter)) 415 goto rx_ring_summary; 416 417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 418 419 /* Transmit Descriptor Formats 420 * 421 * Advanced Transmit Descriptor 422 * +--------------------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +--------------------------------------------------------------+ 425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 426 * +--------------------------------------------------------------+ 427 * 63 46 45 40 39 38 36 35 32 31 24 15 0 428 */ 429 430 for (n = 0; n < adapter->num_tx_queues; n++) { 431 tx_ring = adapter->tx_ring[n]; 432 pr_info("------------------------------------\n"); 433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 434 pr_info("------------------------------------\n"); 435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 436 437 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 438 const char *next_desc; 439 struct igb_tx_buffer *buffer_info; 440 tx_desc = IGB_TX_DESC(tx_ring, i); 441 buffer_info = &tx_ring->tx_buffer_info[i]; 442 u0 = (struct my_u0 *)tx_desc; 443 if (i == tx_ring->next_to_use && 444 i == tx_ring->next_to_clean) 445 next_desc = " NTC/U"; 446 else if (i == tx_ring->next_to_use) 447 next_desc = " NTU"; 448 else if (i == tx_ring->next_to_clean) 449 next_desc = " NTC"; 450 else 451 next_desc = ""; 452 453 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 454 i, le64_to_cpu(u0->a), 455 le64_to_cpu(u0->b), 456 (u64)dma_unmap_addr(buffer_info, dma), 457 dma_unmap_len(buffer_info, len), 458 buffer_info->next_to_watch, 459 (u64)buffer_info->time_stamp, 460 buffer_info->skb, next_desc); 461 462 if (netif_msg_pktdata(adapter) && buffer_info->skb) 463 print_hex_dump(KERN_INFO, "", 464 DUMP_PREFIX_ADDRESS, 465 16, 1, buffer_info->skb->data, 466 dma_unmap_len(buffer_info, len), 467 true); 468 } 469 } 470 471 /* Print RX Rings Summary */ 472 rx_ring_summary: 473 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 474 pr_info("Queue [NTU] [NTC]\n"); 475 for (n = 0; n < adapter->num_rx_queues; n++) { 476 rx_ring = adapter->rx_ring[n]; 477 pr_info(" %5d %5X %5X\n", 478 n, rx_ring->next_to_use, rx_ring->next_to_clean); 479 } 480 481 /* Print RX Rings */ 482 if (!netif_msg_rx_status(adapter)) 483 goto exit; 484 485 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 486 487 /* Advanced Receive Descriptor (Read) Format 488 * 63 1 0 489 * +-----------------------------------------------------+ 490 * 0 | Packet Buffer Address [63:1] |A0/NSE| 491 * +----------------------------------------------+------+ 492 * 8 | Header Buffer Address [63:1] | DD | 493 * +-----------------------------------------------------+ 494 * 495 * 496 * Advanced Receive Descriptor (Write-Back) Format 497 * 498 * 63 48 47 32 31 30 21 20 17 16 4 3 0 499 * +------------------------------------------------------+ 500 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 501 * | Checksum Ident | | | | Type | Type | 502 * +------------------------------------------------------+ 503 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 504 * +------------------------------------------------------+ 505 * 63 48 47 32 31 20 19 0 506 */ 507 508 for (n = 0; n < adapter->num_rx_queues; n++) { 509 rx_ring = adapter->rx_ring[n]; 510 pr_info("------------------------------------\n"); 511 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 512 pr_info("------------------------------------\n"); 513 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 514 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 515 516 for (i = 0; i < rx_ring->count; i++) { 517 const char *next_desc; 518 struct igb_rx_buffer *buffer_info; 519 buffer_info = &rx_ring->rx_buffer_info[i]; 520 rx_desc = IGB_RX_DESC(rx_ring, i); 521 u0 = (struct my_u0 *)rx_desc; 522 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 523 524 if (i == rx_ring->next_to_use) 525 next_desc = " NTU"; 526 else if (i == rx_ring->next_to_clean) 527 next_desc = " NTC"; 528 else 529 next_desc = ""; 530 531 if (staterr & E1000_RXD_STAT_DD) { 532 /* Descriptor Done */ 533 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 534 "RWB", i, 535 le64_to_cpu(u0->a), 536 le64_to_cpu(u0->b), 537 next_desc); 538 } else { 539 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 540 "R ", i, 541 le64_to_cpu(u0->a), 542 le64_to_cpu(u0->b), 543 (u64)buffer_info->dma, 544 next_desc); 545 546 if (netif_msg_pktdata(adapter) && 547 buffer_info->dma && buffer_info->page) { 548 print_hex_dump(KERN_INFO, "", 549 DUMP_PREFIX_ADDRESS, 550 16, 1, 551 page_address(buffer_info->page) + 552 buffer_info->page_offset, 553 igb_rx_bufsz(rx_ring), true); 554 } 555 } 556 } 557 } 558 559 exit: 560 return; 561 } 562 563 /** 564 * igb_get_i2c_data - Reads the I2C SDA data bit 565 * @hw: pointer to hardware structure 566 * @i2cctl: Current value of I2CCTL register 567 * 568 * Returns the I2C data bit value 569 **/ 570 static int igb_get_i2c_data(void *data) 571 { 572 struct igb_adapter *adapter = (struct igb_adapter *)data; 573 struct e1000_hw *hw = &adapter->hw; 574 s32 i2cctl = rd32(E1000_I2CPARAMS); 575 576 return !!(i2cctl & E1000_I2C_DATA_IN); 577 } 578 579 /** 580 * igb_set_i2c_data - Sets the I2C data bit 581 * @data: pointer to hardware structure 582 * @state: I2C data value (0 or 1) to set 583 * 584 * Sets the I2C data bit 585 **/ 586 static void igb_set_i2c_data(void *data, int state) 587 { 588 struct igb_adapter *adapter = (struct igb_adapter *)data; 589 struct e1000_hw *hw = &adapter->hw; 590 s32 i2cctl = rd32(E1000_I2CPARAMS); 591 592 if (state) 593 i2cctl |= E1000_I2C_DATA_OUT; 594 else 595 i2cctl &= ~E1000_I2C_DATA_OUT; 596 597 i2cctl &= ~E1000_I2C_DATA_OE_N; 598 i2cctl |= E1000_I2C_CLK_OE_N; 599 wr32(E1000_I2CPARAMS, i2cctl); 600 wrfl(); 601 602 } 603 604 /** 605 * igb_set_i2c_clk - Sets the I2C SCL clock 606 * @data: pointer to hardware structure 607 * @state: state to set clock 608 * 609 * Sets the I2C clock line to state 610 **/ 611 static void igb_set_i2c_clk(void *data, int state) 612 { 613 struct igb_adapter *adapter = (struct igb_adapter *)data; 614 struct e1000_hw *hw = &adapter->hw; 615 s32 i2cctl = rd32(E1000_I2CPARAMS); 616 617 if (state) { 618 i2cctl |= E1000_I2C_CLK_OUT; 619 i2cctl &= ~E1000_I2C_CLK_OE_N; 620 } else { 621 i2cctl &= ~E1000_I2C_CLK_OUT; 622 i2cctl &= ~E1000_I2C_CLK_OE_N; 623 } 624 wr32(E1000_I2CPARAMS, i2cctl); 625 wrfl(); 626 } 627 628 /** 629 * igb_get_i2c_clk - Gets the I2C SCL clock state 630 * @data: pointer to hardware structure 631 * 632 * Gets the I2C clock state 633 **/ 634 static int igb_get_i2c_clk(void *data) 635 { 636 struct igb_adapter *adapter = (struct igb_adapter *)data; 637 struct e1000_hw *hw = &adapter->hw; 638 s32 i2cctl = rd32(E1000_I2CPARAMS); 639 640 return !!(i2cctl & E1000_I2C_CLK_IN); 641 } 642 643 static const struct i2c_algo_bit_data igb_i2c_algo = { 644 .setsda = igb_set_i2c_data, 645 .setscl = igb_set_i2c_clk, 646 .getsda = igb_get_i2c_data, 647 .getscl = igb_get_i2c_clk, 648 .udelay = 5, 649 .timeout = 20, 650 }; 651 652 /** 653 * igb_get_hw_dev - return device 654 * @hw: pointer to hardware structure 655 * 656 * used by hardware layer to print debugging information 657 **/ 658 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 659 { 660 struct igb_adapter *adapter = hw->back; 661 return adapter->netdev; 662 } 663 664 /** 665 * igb_init_module - Driver Registration Routine 666 * 667 * igb_init_module is the first routine called when the driver is 668 * loaded. All it does is register with the PCI subsystem. 669 **/ 670 static int __init igb_init_module(void) 671 { 672 int ret; 673 674 pr_info("%s - version %s\n", 675 igb_driver_string, igb_driver_version); 676 pr_info("%s\n", igb_copyright); 677 678 #ifdef CONFIG_IGB_DCA 679 dca_register_notify(&dca_notifier); 680 #endif 681 ret = pci_register_driver(&igb_driver); 682 return ret; 683 } 684 685 module_init(igb_init_module); 686 687 /** 688 * igb_exit_module - Driver Exit Cleanup Routine 689 * 690 * igb_exit_module is called just before the driver is removed 691 * from memory. 692 **/ 693 static void __exit igb_exit_module(void) 694 { 695 #ifdef CONFIG_IGB_DCA 696 dca_unregister_notify(&dca_notifier); 697 #endif 698 pci_unregister_driver(&igb_driver); 699 } 700 701 module_exit(igb_exit_module); 702 703 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 704 /** 705 * igb_cache_ring_register - Descriptor ring to register mapping 706 * @adapter: board private structure to initialize 707 * 708 * Once we know the feature-set enabled for the device, we'll cache 709 * the register offset the descriptor ring is assigned to. 710 **/ 711 static void igb_cache_ring_register(struct igb_adapter *adapter) 712 { 713 int i = 0, j = 0; 714 u32 rbase_offset = adapter->vfs_allocated_count; 715 716 switch (adapter->hw.mac.type) { 717 case e1000_82576: 718 /* The queues are allocated for virtualization such that VF 0 719 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 720 * In order to avoid collision we start at the first free queue 721 * and continue consuming queues in the same sequence 722 */ 723 if (adapter->vfs_allocated_count) { 724 for (; i < adapter->rss_queues; i++) 725 adapter->rx_ring[i]->reg_idx = rbase_offset + 726 Q_IDX_82576(i); 727 } 728 /* Fall through */ 729 case e1000_82575: 730 case e1000_82580: 731 case e1000_i350: 732 case e1000_i354: 733 case e1000_i210: 734 case e1000_i211: 735 /* Fall through */ 736 default: 737 for (; i < adapter->num_rx_queues; i++) 738 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 739 for (; j < adapter->num_tx_queues; j++) 740 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 741 break; 742 } 743 } 744 745 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 746 { 747 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 748 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 749 u32 value = 0; 750 751 if (E1000_REMOVED(hw_addr)) 752 return ~value; 753 754 value = readl(&hw_addr[reg]); 755 756 /* reads should not return all F's */ 757 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 758 struct net_device *netdev = igb->netdev; 759 hw->hw_addr = NULL; 760 netdev_err(netdev, "PCIe link lost\n"); 761 } 762 763 return value; 764 } 765 766 /** 767 * igb_write_ivar - configure ivar for given MSI-X vector 768 * @hw: pointer to the HW structure 769 * @msix_vector: vector number we are allocating to a given ring 770 * @index: row index of IVAR register to write within IVAR table 771 * @offset: column offset of in IVAR, should be multiple of 8 772 * 773 * This function is intended to handle the writing of the IVAR register 774 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 775 * each containing an cause allocation for an Rx and Tx ring, and a 776 * variable number of rows depending on the number of queues supported. 777 **/ 778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 779 int index, int offset) 780 { 781 u32 ivar = array_rd32(E1000_IVAR0, index); 782 783 /* clear any bits that are currently set */ 784 ivar &= ~((u32)0xFF << offset); 785 786 /* write vector and valid bit */ 787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 788 789 array_wr32(E1000_IVAR0, index, ivar); 790 } 791 792 #define IGB_N0_QUEUE -1 793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 794 { 795 struct igb_adapter *adapter = q_vector->adapter; 796 struct e1000_hw *hw = &adapter->hw; 797 int rx_queue = IGB_N0_QUEUE; 798 int tx_queue = IGB_N0_QUEUE; 799 u32 msixbm = 0; 800 801 if (q_vector->rx.ring) 802 rx_queue = q_vector->rx.ring->reg_idx; 803 if (q_vector->tx.ring) 804 tx_queue = q_vector->tx.ring->reg_idx; 805 806 switch (hw->mac.type) { 807 case e1000_82575: 808 /* The 82575 assigns vectors using a bitmask, which matches the 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one 810 * or more queues to a vector, we write the appropriate bits 811 * into the MSIXBM register for that vector. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 815 if (tx_queue > IGB_N0_QUEUE) 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 818 msixbm |= E1000_EIMS_OTHER; 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 820 q_vector->eims_value = msixbm; 821 break; 822 case e1000_82576: 823 /* 82576 uses a table that essentially consists of 2 columns 824 * with 8 rows. The ordering is column-major so we use the 825 * lower 3 bits as the row index, and the 4th bit as the 826 * column offset. 827 */ 828 if (rx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 rx_queue & 0x7, 831 (rx_queue & 0x8) << 1); 832 if (tx_queue > IGB_N0_QUEUE) 833 igb_write_ivar(hw, msix_vector, 834 tx_queue & 0x7, 835 ((tx_queue & 0x8) << 1) + 8); 836 q_vector->eims_value = BIT(msix_vector); 837 break; 838 case e1000_82580: 839 case e1000_i350: 840 case e1000_i354: 841 case e1000_i210: 842 case e1000_i211: 843 /* On 82580 and newer adapters the scheme is similar to 82576 844 * however instead of ordering column-major we have things 845 * ordered row-major. So we traverse the table by using 846 * bit 0 as the column offset, and the remaining bits as the 847 * row index. 848 */ 849 if (rx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 rx_queue >> 1, 852 (rx_queue & 0x1) << 4); 853 if (tx_queue > IGB_N0_QUEUE) 854 igb_write_ivar(hw, msix_vector, 855 tx_queue >> 1, 856 ((tx_queue & 0x1) << 4) + 8); 857 q_vector->eims_value = BIT(msix_vector); 858 break; 859 default: 860 BUG(); 861 break; 862 } 863 864 /* add q_vector eims value to global eims_enable_mask */ 865 adapter->eims_enable_mask |= q_vector->eims_value; 866 867 /* configure q_vector to set itr on first interrupt */ 868 q_vector->set_itr = 1; 869 } 870 871 /** 872 * igb_configure_msix - Configure MSI-X hardware 873 * @adapter: board private structure to initialize 874 * 875 * igb_configure_msix sets up the hardware to properly 876 * generate MSI-X interrupts. 877 **/ 878 static void igb_configure_msix(struct igb_adapter *adapter) 879 { 880 u32 tmp; 881 int i, vector = 0; 882 struct e1000_hw *hw = &adapter->hw; 883 884 adapter->eims_enable_mask = 0; 885 886 /* set vector for other causes, i.e. link changes */ 887 switch (hw->mac.type) { 888 case e1000_82575: 889 tmp = rd32(E1000_CTRL_EXT); 890 /* enable MSI-X PBA support*/ 891 tmp |= E1000_CTRL_EXT_PBA_CLR; 892 893 /* Auto-Mask interrupts upon ICR read. */ 894 tmp |= E1000_CTRL_EXT_EIAME; 895 tmp |= E1000_CTRL_EXT_IRCA; 896 897 wr32(E1000_CTRL_EXT, tmp); 898 899 /* enable msix_other interrupt */ 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 901 adapter->eims_other = E1000_EIMS_OTHER; 902 903 break; 904 905 case e1000_82576: 906 case e1000_82580: 907 case e1000_i350: 908 case e1000_i354: 909 case e1000_i210: 910 case e1000_i211: 911 /* Turn on MSI-X capability first, or our settings 912 * won't stick. And it will take days to debug. 913 */ 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 915 E1000_GPIE_PBA | E1000_GPIE_EIAME | 916 E1000_GPIE_NSICR); 917 918 /* enable msix_other interrupt */ 919 adapter->eims_other = BIT(vector); 920 tmp = (vector++ | E1000_IVAR_VALID) << 8; 921 922 wr32(E1000_IVAR_MISC, tmp); 923 break; 924 default: 925 /* do nothing, since nothing else supports MSI-X */ 926 break; 927 } /* switch (hw->mac.type) */ 928 929 adapter->eims_enable_mask |= adapter->eims_other; 930 931 for (i = 0; i < adapter->num_q_vectors; i++) 932 igb_assign_vector(adapter->q_vector[i], vector++); 933 934 wrfl(); 935 } 936 937 /** 938 * igb_request_msix - Initialize MSI-X interrupts 939 * @adapter: board private structure to initialize 940 * 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 942 * kernel. 943 **/ 944 static int igb_request_msix(struct igb_adapter *adapter) 945 { 946 struct net_device *netdev = adapter->netdev; 947 int i, err = 0, vector = 0, free_vector = 0; 948 949 err = request_irq(adapter->msix_entries[vector].vector, 950 igb_msix_other, 0, netdev->name, adapter); 951 if (err) 952 goto err_out; 953 954 for (i = 0; i < adapter->num_q_vectors; i++) { 955 struct igb_q_vector *q_vector = adapter->q_vector[i]; 956 957 vector++; 958 959 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 960 961 if (q_vector->rx.ring && q_vector->tx.ring) 962 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 963 q_vector->rx.ring->queue_index); 964 else if (q_vector->tx.ring) 965 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 966 q_vector->tx.ring->queue_index); 967 else if (q_vector->rx.ring) 968 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 969 q_vector->rx.ring->queue_index); 970 else 971 sprintf(q_vector->name, "%s-unused", netdev->name); 972 973 err = request_irq(adapter->msix_entries[vector].vector, 974 igb_msix_ring, 0, q_vector->name, 975 q_vector); 976 if (err) 977 goto err_free; 978 } 979 980 igb_configure_msix(adapter); 981 return 0; 982 983 err_free: 984 /* free already assigned IRQs */ 985 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 986 987 vector--; 988 for (i = 0; i < vector; i++) { 989 free_irq(adapter->msix_entries[free_vector++].vector, 990 adapter->q_vector[i]); 991 } 992 err_out: 993 return err; 994 } 995 996 /** 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector 998 * @adapter: board private structure to initialize 999 * @v_idx: Index of vector to be freed 1000 * 1001 * This function frees the memory allocated to the q_vector. 1002 **/ 1003 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1004 { 1005 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1006 1007 adapter->q_vector[v_idx] = NULL; 1008 1009 /* igb_get_stats64() might access the rings on this vector, 1010 * we must wait a grace period before freeing it. 1011 */ 1012 if (q_vector) 1013 kfree_rcu(q_vector, rcu); 1014 } 1015 1016 /** 1017 * igb_reset_q_vector - Reset config for interrupt vector 1018 * @adapter: board private structure to initialize 1019 * @v_idx: Index of vector to be reset 1020 * 1021 * If NAPI is enabled it will delete any references to the 1022 * NAPI struct. This is preparation for igb_free_q_vector. 1023 **/ 1024 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1025 { 1026 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1027 1028 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1029 * allocated. So, q_vector is NULL so we should stop here. 1030 */ 1031 if (!q_vector) 1032 return; 1033 1034 if (q_vector->tx.ring) 1035 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1036 1037 if (q_vector->rx.ring) 1038 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1039 1040 netif_napi_del(&q_vector->napi); 1041 1042 } 1043 1044 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1045 { 1046 int v_idx = adapter->num_q_vectors; 1047 1048 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1049 pci_disable_msix(adapter->pdev); 1050 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1051 pci_disable_msi(adapter->pdev); 1052 1053 while (v_idx--) 1054 igb_reset_q_vector(adapter, v_idx); 1055 } 1056 1057 /** 1058 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1059 * @adapter: board private structure to initialize 1060 * 1061 * This function frees the memory allocated to the q_vectors. In addition if 1062 * NAPI is enabled it will delete any references to the NAPI struct prior 1063 * to freeing the q_vector. 1064 **/ 1065 static void igb_free_q_vectors(struct igb_adapter *adapter) 1066 { 1067 int v_idx = adapter->num_q_vectors; 1068 1069 adapter->num_tx_queues = 0; 1070 adapter->num_rx_queues = 0; 1071 adapter->num_q_vectors = 0; 1072 1073 while (v_idx--) { 1074 igb_reset_q_vector(adapter, v_idx); 1075 igb_free_q_vector(adapter, v_idx); 1076 } 1077 } 1078 1079 /** 1080 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1081 * @adapter: board private structure to initialize 1082 * 1083 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1084 * MSI-X interrupts allocated. 1085 */ 1086 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1087 { 1088 igb_free_q_vectors(adapter); 1089 igb_reset_interrupt_capability(adapter); 1090 } 1091 1092 /** 1093 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1094 * @adapter: board private structure to initialize 1095 * @msix: boolean value of MSIX capability 1096 * 1097 * Attempt to configure interrupts using the best available 1098 * capabilities of the hardware and kernel. 1099 **/ 1100 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1101 { 1102 int err; 1103 int numvecs, i; 1104 1105 if (!msix) 1106 goto msi_only; 1107 adapter->flags |= IGB_FLAG_HAS_MSIX; 1108 1109 /* Number of supported queues. */ 1110 adapter->num_rx_queues = adapter->rss_queues; 1111 if (adapter->vfs_allocated_count) 1112 adapter->num_tx_queues = 1; 1113 else 1114 adapter->num_tx_queues = adapter->rss_queues; 1115 1116 /* start with one vector for every Rx queue */ 1117 numvecs = adapter->num_rx_queues; 1118 1119 /* if Tx handler is separate add 1 for every Tx queue */ 1120 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1121 numvecs += adapter->num_tx_queues; 1122 1123 /* store the number of vectors reserved for queues */ 1124 adapter->num_q_vectors = numvecs; 1125 1126 /* add 1 vector for link status interrupts */ 1127 numvecs++; 1128 for (i = 0; i < numvecs; i++) 1129 adapter->msix_entries[i].entry = i; 1130 1131 err = pci_enable_msix_range(adapter->pdev, 1132 adapter->msix_entries, 1133 numvecs, 1134 numvecs); 1135 if (err > 0) 1136 return; 1137 1138 igb_reset_interrupt_capability(adapter); 1139 1140 /* If we can't do MSI-X, try MSI */ 1141 msi_only: 1142 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1143 #ifdef CONFIG_PCI_IOV 1144 /* disable SR-IOV for non MSI-X configurations */ 1145 if (adapter->vf_data) { 1146 struct e1000_hw *hw = &adapter->hw; 1147 /* disable iov and allow time for transactions to clear */ 1148 pci_disable_sriov(adapter->pdev); 1149 msleep(500); 1150 1151 kfree(adapter->vf_mac_list); 1152 adapter->vf_mac_list = NULL; 1153 kfree(adapter->vf_data); 1154 adapter->vf_data = NULL; 1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1156 wrfl(); 1157 msleep(100); 1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1159 } 1160 #endif 1161 adapter->vfs_allocated_count = 0; 1162 adapter->rss_queues = 1; 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1164 adapter->num_rx_queues = 1; 1165 adapter->num_tx_queues = 1; 1166 adapter->num_q_vectors = 1; 1167 if (!pci_enable_msi(adapter->pdev)) 1168 adapter->flags |= IGB_FLAG_HAS_MSI; 1169 } 1170 1171 static void igb_add_ring(struct igb_ring *ring, 1172 struct igb_ring_container *head) 1173 { 1174 head->ring = ring; 1175 head->count++; 1176 } 1177 1178 /** 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1180 * @adapter: board private structure to initialize 1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1182 * @v_idx: index of vector in adapter struct 1183 * @txr_count: total number of Tx rings to allocate 1184 * @txr_idx: index of first Tx ring to allocate 1185 * @rxr_count: total number of Rx rings to allocate 1186 * @rxr_idx: index of first Rx ring to allocate 1187 * 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1189 **/ 1190 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1191 int v_count, int v_idx, 1192 int txr_count, int txr_idx, 1193 int rxr_count, int rxr_idx) 1194 { 1195 struct igb_q_vector *q_vector; 1196 struct igb_ring *ring; 1197 int ring_count, size; 1198 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1200 if (txr_count > 1 || rxr_count > 1) 1201 return -ENOMEM; 1202 1203 ring_count = txr_count + rxr_count; 1204 size = sizeof(struct igb_q_vector) + 1205 (sizeof(struct igb_ring) * ring_count); 1206 1207 /* allocate q_vector and rings */ 1208 q_vector = adapter->q_vector[v_idx]; 1209 if (!q_vector) { 1210 q_vector = kzalloc(size, GFP_KERNEL); 1211 } else if (size > ksize(q_vector)) { 1212 kfree_rcu(q_vector, rcu); 1213 q_vector = kzalloc(size, GFP_KERNEL); 1214 } else { 1215 memset(q_vector, 0, size); 1216 } 1217 if (!q_vector) 1218 return -ENOMEM; 1219 1220 /* initialize NAPI */ 1221 netif_napi_add(adapter->netdev, &q_vector->napi, 1222 igb_poll, 64); 1223 1224 /* tie q_vector and adapter together */ 1225 adapter->q_vector[v_idx] = q_vector; 1226 q_vector->adapter = adapter; 1227 1228 /* initialize work limits */ 1229 q_vector->tx.work_limit = adapter->tx_work_limit; 1230 1231 /* initialize ITR configuration */ 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1233 q_vector->itr_val = IGB_START_ITR; 1234 1235 /* initialize pointer to rings */ 1236 ring = q_vector->ring; 1237 1238 /* intialize ITR */ 1239 if (rxr_count) { 1240 /* rx or rx/tx vector */ 1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1242 q_vector->itr_val = adapter->rx_itr_setting; 1243 } else { 1244 /* tx only vector */ 1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1246 q_vector->itr_val = adapter->tx_itr_setting; 1247 } 1248 1249 if (txr_count) { 1250 /* assign generic ring traits */ 1251 ring->dev = &adapter->pdev->dev; 1252 ring->netdev = adapter->netdev; 1253 1254 /* configure backlink on ring */ 1255 ring->q_vector = q_vector; 1256 1257 /* update q_vector Tx values */ 1258 igb_add_ring(ring, &q_vector->tx); 1259 1260 /* For 82575, context index must be unique per ring. */ 1261 if (adapter->hw.mac.type == e1000_82575) 1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1263 1264 /* apply Tx specific ring traits */ 1265 ring->count = adapter->tx_ring_count; 1266 ring->queue_index = txr_idx; 1267 1268 ring->cbs_enable = false; 1269 ring->idleslope = 0; 1270 ring->sendslope = 0; 1271 ring->hicredit = 0; 1272 ring->locredit = 0; 1273 1274 u64_stats_init(&ring->tx_syncp); 1275 u64_stats_init(&ring->tx_syncp2); 1276 1277 /* assign ring to adapter */ 1278 adapter->tx_ring[txr_idx] = ring; 1279 1280 /* push pointer to next ring */ 1281 ring++; 1282 } 1283 1284 if (rxr_count) { 1285 /* assign generic ring traits */ 1286 ring->dev = &adapter->pdev->dev; 1287 ring->netdev = adapter->netdev; 1288 1289 /* configure backlink on ring */ 1290 ring->q_vector = q_vector; 1291 1292 /* update q_vector Rx values */ 1293 igb_add_ring(ring, &q_vector->rx); 1294 1295 /* set flag indicating ring supports SCTP checksum offload */ 1296 if (adapter->hw.mac.type >= e1000_82576) 1297 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1298 1299 /* On i350, i354, i210, and i211, loopback VLAN packets 1300 * have the tag byte-swapped. 1301 */ 1302 if (adapter->hw.mac.type >= e1000_i350) 1303 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1304 1305 /* apply Rx specific ring traits */ 1306 ring->count = adapter->rx_ring_count; 1307 ring->queue_index = rxr_idx; 1308 1309 u64_stats_init(&ring->rx_syncp); 1310 1311 /* assign ring to adapter */ 1312 adapter->rx_ring[rxr_idx] = ring; 1313 } 1314 1315 return 0; 1316 } 1317 1318 1319 /** 1320 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1321 * @adapter: board private structure to initialize 1322 * 1323 * We allocate one q_vector per queue interrupt. If allocation fails we 1324 * return -ENOMEM. 1325 **/ 1326 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1327 { 1328 int q_vectors = adapter->num_q_vectors; 1329 int rxr_remaining = adapter->num_rx_queues; 1330 int txr_remaining = adapter->num_tx_queues; 1331 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1332 int err; 1333 1334 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1335 for (; rxr_remaining; v_idx++) { 1336 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1337 0, 0, 1, rxr_idx); 1338 1339 if (err) 1340 goto err_out; 1341 1342 /* update counts and index */ 1343 rxr_remaining--; 1344 rxr_idx++; 1345 } 1346 } 1347 1348 for (; v_idx < q_vectors; v_idx++) { 1349 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1350 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1351 1352 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1353 tqpv, txr_idx, rqpv, rxr_idx); 1354 1355 if (err) 1356 goto err_out; 1357 1358 /* update counts and index */ 1359 rxr_remaining -= rqpv; 1360 txr_remaining -= tqpv; 1361 rxr_idx++; 1362 txr_idx++; 1363 } 1364 1365 return 0; 1366 1367 err_out: 1368 adapter->num_tx_queues = 0; 1369 adapter->num_rx_queues = 0; 1370 adapter->num_q_vectors = 0; 1371 1372 while (v_idx--) 1373 igb_free_q_vector(adapter, v_idx); 1374 1375 return -ENOMEM; 1376 } 1377 1378 /** 1379 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1380 * @adapter: board private structure to initialize 1381 * @msix: boolean value of MSIX capability 1382 * 1383 * This function initializes the interrupts and allocates all of the queues. 1384 **/ 1385 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1386 { 1387 struct pci_dev *pdev = adapter->pdev; 1388 int err; 1389 1390 igb_set_interrupt_capability(adapter, msix); 1391 1392 err = igb_alloc_q_vectors(adapter); 1393 if (err) { 1394 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1395 goto err_alloc_q_vectors; 1396 } 1397 1398 igb_cache_ring_register(adapter); 1399 1400 return 0; 1401 1402 err_alloc_q_vectors: 1403 igb_reset_interrupt_capability(adapter); 1404 return err; 1405 } 1406 1407 /** 1408 * igb_request_irq - initialize interrupts 1409 * @adapter: board private structure to initialize 1410 * 1411 * Attempts to configure interrupts using the best available 1412 * capabilities of the hardware and kernel. 1413 **/ 1414 static int igb_request_irq(struct igb_adapter *adapter) 1415 { 1416 struct net_device *netdev = adapter->netdev; 1417 struct pci_dev *pdev = adapter->pdev; 1418 int err = 0; 1419 1420 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1421 err = igb_request_msix(adapter); 1422 if (!err) 1423 goto request_done; 1424 /* fall back to MSI */ 1425 igb_free_all_tx_resources(adapter); 1426 igb_free_all_rx_resources(adapter); 1427 1428 igb_clear_interrupt_scheme(adapter); 1429 err = igb_init_interrupt_scheme(adapter, false); 1430 if (err) 1431 goto request_done; 1432 1433 igb_setup_all_tx_resources(adapter); 1434 igb_setup_all_rx_resources(adapter); 1435 igb_configure(adapter); 1436 } 1437 1438 igb_assign_vector(adapter->q_vector[0], 0); 1439 1440 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1441 err = request_irq(pdev->irq, igb_intr_msi, 0, 1442 netdev->name, adapter); 1443 if (!err) 1444 goto request_done; 1445 1446 /* fall back to legacy interrupts */ 1447 igb_reset_interrupt_capability(adapter); 1448 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1449 } 1450 1451 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1452 netdev->name, adapter); 1453 1454 if (err) 1455 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1456 err); 1457 1458 request_done: 1459 return err; 1460 } 1461 1462 static void igb_free_irq(struct igb_adapter *adapter) 1463 { 1464 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1465 int vector = 0, i; 1466 1467 free_irq(adapter->msix_entries[vector++].vector, adapter); 1468 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 free_irq(adapter->msix_entries[vector++].vector, 1471 adapter->q_vector[i]); 1472 } else { 1473 free_irq(adapter->pdev->irq, adapter); 1474 } 1475 } 1476 1477 /** 1478 * igb_irq_disable - Mask off interrupt generation on the NIC 1479 * @adapter: board private structure 1480 **/ 1481 static void igb_irq_disable(struct igb_adapter *adapter) 1482 { 1483 struct e1000_hw *hw = &adapter->hw; 1484 1485 /* we need to be careful when disabling interrupts. The VFs are also 1486 * mapped into these registers and so clearing the bits can cause 1487 * issues on the VF drivers so we only need to clear what we set 1488 */ 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 u32 regval = rd32(E1000_EIAM); 1491 1492 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1493 wr32(E1000_EIMC, adapter->eims_enable_mask); 1494 regval = rd32(E1000_EIAC); 1495 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1496 } 1497 1498 wr32(E1000_IAM, 0); 1499 wr32(E1000_IMC, ~0); 1500 wrfl(); 1501 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1502 int i; 1503 1504 for (i = 0; i < adapter->num_q_vectors; i++) 1505 synchronize_irq(adapter->msix_entries[i].vector); 1506 } else { 1507 synchronize_irq(adapter->pdev->irq); 1508 } 1509 } 1510 1511 /** 1512 * igb_irq_enable - Enable default interrupt generation settings 1513 * @adapter: board private structure 1514 **/ 1515 static void igb_irq_enable(struct igb_adapter *adapter) 1516 { 1517 struct e1000_hw *hw = &adapter->hw; 1518 1519 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1520 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1521 u32 regval = rd32(E1000_EIAC); 1522 1523 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1524 regval = rd32(E1000_EIAM); 1525 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1526 wr32(E1000_EIMS, adapter->eims_enable_mask); 1527 if (adapter->vfs_allocated_count) { 1528 wr32(E1000_MBVFIMR, 0xFF); 1529 ims |= E1000_IMS_VMMB; 1530 } 1531 wr32(E1000_IMS, ims); 1532 } else { 1533 wr32(E1000_IMS, IMS_ENABLE_MASK | 1534 E1000_IMS_DRSTA); 1535 wr32(E1000_IAM, IMS_ENABLE_MASK | 1536 E1000_IMS_DRSTA); 1537 } 1538 } 1539 1540 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u16 pf_id = adapter->vfs_allocated_count; 1544 u16 vid = adapter->hw.mng_cookie.vlan_id; 1545 u16 old_vid = adapter->mng_vlan_id; 1546 1547 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1548 /* add VID to filter table */ 1549 igb_vfta_set(hw, vid, pf_id, true, true); 1550 adapter->mng_vlan_id = vid; 1551 } else { 1552 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1553 } 1554 1555 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1556 (vid != old_vid) && 1557 !test_bit(old_vid, adapter->active_vlans)) { 1558 /* remove VID from filter table */ 1559 igb_vfta_set(hw, vid, pf_id, false, true); 1560 } 1561 } 1562 1563 /** 1564 * igb_release_hw_control - release control of the h/w to f/w 1565 * @adapter: address of board private structure 1566 * 1567 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1568 * For ASF and Pass Through versions of f/w this means that the 1569 * driver is no longer loaded. 1570 **/ 1571 static void igb_release_hw_control(struct igb_adapter *adapter) 1572 { 1573 struct e1000_hw *hw = &adapter->hw; 1574 u32 ctrl_ext; 1575 1576 /* Let firmware take over control of h/w */ 1577 ctrl_ext = rd32(E1000_CTRL_EXT); 1578 wr32(E1000_CTRL_EXT, 1579 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1580 } 1581 1582 /** 1583 * igb_get_hw_control - get control of the h/w from f/w 1584 * @adapter: address of board private structure 1585 * 1586 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1587 * For ASF and Pass Through versions of f/w this means that 1588 * the driver is loaded. 1589 **/ 1590 static void igb_get_hw_control(struct igb_adapter *adapter) 1591 { 1592 struct e1000_hw *hw = &adapter->hw; 1593 u32 ctrl_ext; 1594 1595 /* Let firmware know the driver has taken over */ 1596 ctrl_ext = rd32(E1000_CTRL_EXT); 1597 wr32(E1000_CTRL_EXT, 1598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1599 } 1600 1601 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1602 { 1603 struct net_device *netdev = adapter->netdev; 1604 struct e1000_hw *hw = &adapter->hw; 1605 1606 WARN_ON(hw->mac.type != e1000_i210); 1607 1608 if (enable) 1609 adapter->flags |= IGB_FLAG_FQTSS; 1610 else 1611 adapter->flags &= ~IGB_FLAG_FQTSS; 1612 1613 if (netif_running(netdev)) 1614 schedule_work(&adapter->reset_task); 1615 } 1616 1617 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1618 { 1619 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1620 } 1621 1622 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1623 enum tx_queue_prio prio) 1624 { 1625 u32 val; 1626 1627 WARN_ON(hw->mac.type != e1000_i210); 1628 WARN_ON(queue < 0 || queue > 4); 1629 1630 val = rd32(E1000_I210_TXDCTL(queue)); 1631 1632 if (prio == TX_QUEUE_PRIO_HIGH) 1633 val |= E1000_TXDCTL_PRIORITY; 1634 else 1635 val &= ~E1000_TXDCTL_PRIORITY; 1636 1637 wr32(E1000_I210_TXDCTL(queue), val); 1638 } 1639 1640 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1641 { 1642 u32 val; 1643 1644 WARN_ON(hw->mac.type != e1000_i210); 1645 WARN_ON(queue < 0 || queue > 1); 1646 1647 val = rd32(E1000_I210_TQAVCC(queue)); 1648 1649 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1650 val |= E1000_TQAVCC_QUEUEMODE; 1651 else 1652 val &= ~E1000_TQAVCC_QUEUEMODE; 1653 1654 wr32(E1000_I210_TQAVCC(queue), val); 1655 } 1656 1657 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1658 { 1659 int i; 1660 1661 for (i = 0; i < adapter->num_tx_queues; i++) { 1662 if (adapter->tx_ring[i]->cbs_enable) 1663 return true; 1664 } 1665 1666 return false; 1667 } 1668 1669 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1670 { 1671 int i; 1672 1673 for (i = 0; i < adapter->num_tx_queues; i++) { 1674 if (adapter->tx_ring[i]->launchtime_enable) 1675 return true; 1676 } 1677 1678 return false; 1679 } 1680 1681 /** 1682 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1683 * @adapter: pointer to adapter struct 1684 * @queue: queue number 1685 * 1686 * Configure CBS and Launchtime for a given hardware queue. 1687 * Parameters are retrieved from the correct Tx ring, so 1688 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1689 * for setting those correctly prior to this function being called. 1690 **/ 1691 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1692 { 1693 struct igb_ring *ring = adapter->tx_ring[queue]; 1694 struct net_device *netdev = adapter->netdev; 1695 struct e1000_hw *hw = &adapter->hw; 1696 u32 tqavcc, tqavctrl; 1697 u16 value; 1698 1699 WARN_ON(hw->mac.type != e1000_i210); 1700 WARN_ON(queue < 0 || queue > 1); 1701 1702 /* If any of the Qav features is enabled, configure queues as SR and 1703 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1704 * as SP. 1705 */ 1706 if (ring->cbs_enable || ring->launchtime_enable) { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1709 } else { 1710 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1711 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1712 } 1713 1714 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1715 if (ring->cbs_enable || queue == 0) { 1716 /* i210 does not allow the queue 0 to be in the Strict 1717 * Priority mode while the Qav mode is enabled, so, 1718 * instead of disabling strict priority mode, we give 1719 * queue 0 the maximum of credits possible. 1720 * 1721 * See section 8.12.19 of the i210 datasheet, "Note: 1722 * Queue0 QueueMode must be set to 1b when 1723 * TransmitMode is set to Qav." 1724 */ 1725 if (queue == 0 && !ring->cbs_enable) { 1726 /* max "linkspeed" idleslope in kbps */ 1727 ring->idleslope = 1000000; 1728 ring->hicredit = ETH_FRAME_LEN; 1729 } 1730 1731 /* Always set data transfer arbitration to credit-based 1732 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1733 * the queues. 1734 */ 1735 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1736 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1737 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1738 1739 /* According to i210 datasheet section 7.2.7.7, we should set 1740 * the 'idleSlope' field from TQAVCC register following the 1741 * equation: 1742 * 1743 * For 100 Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 0.2 (E1) 1746 * 1747 * For 1000Mbps link speed: 1748 * 1749 * value = BW * 0x7735 * 2 (E2) 1750 * 1751 * E1 and E2 can be merged into one equation as shown below. 1752 * Note that 'link-speed' is in Mbps. 1753 * 1754 * value = BW * 0x7735 * 2 * link-speed 1755 * -------------- (E3) 1756 * 1000 1757 * 1758 * 'BW' is the percentage bandwidth out of full link speed 1759 * which can be found with the following equation. Note that 1760 * idleSlope here is the parameter from this function which 1761 * is in kbps. 1762 * 1763 * BW = idleSlope 1764 * ----------------- (E4) 1765 * link-speed * 1000 1766 * 1767 * That said, we can come up with a generic equation to 1768 * calculate the value we should set it TQAVCC register by 1769 * replacing 'BW' in E3 by E4. The resulting equation is: 1770 * 1771 * value = idleSlope * 0x7735 * 2 * link-speed 1772 * ----------------- -------------- (E5) 1773 * link-speed * 1000 1000 1774 * 1775 * 'link-speed' is present in both sides of the fraction so 1776 * it is canceled out. The final equation is the following: 1777 * 1778 * value = idleSlope * 61034 1779 * ----------------- (E6) 1780 * 1000000 1781 * 1782 * NOTE: For i210, given the above, we can see that idleslope 1783 * is represented in 16.38431 kbps units by the value at 1784 * the TQAVCC register (1Gbps / 61034), which reduces 1785 * the granularity for idleslope increments. 1786 * For instance, if you want to configure a 2576kbps 1787 * idleslope, the value to be written on the register 1788 * would have to be 157.23. If rounded down, you end 1789 * up with less bandwidth available than originally 1790 * required (~2572 kbps). If rounded up, you end up 1791 * with a higher bandwidth (~2589 kbps). Below the 1792 * approach we take is to always round up the 1793 * calculated value, so the resulting bandwidth might 1794 * be slightly higher for some configurations. 1795 */ 1796 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1797 1798 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1799 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1800 tqavcc |= value; 1801 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1802 1803 wr32(E1000_I210_TQAVHC(queue), 1804 0x80000000 + ring->hicredit * 0x7735); 1805 } else { 1806 1807 /* Set idleSlope to zero. */ 1808 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1809 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1810 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1811 1812 /* Set hiCredit to zero. */ 1813 wr32(E1000_I210_TQAVHC(queue), 0); 1814 1815 /* If CBS is not enabled for any queues anymore, then return to 1816 * the default state of Data Transmission Arbitration on 1817 * TQAVCTRL. 1818 */ 1819 if (!is_any_cbs_enabled(adapter)) { 1820 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1821 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1822 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1823 } 1824 } 1825 1826 /* If LaunchTime is enabled, set DataTranTIM. */ 1827 if (ring->launchtime_enable) { 1828 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1829 * for any of the SR queues, and configure fetchtime delta. 1830 * XXX NOTE: 1831 * - LaunchTime will be enabled for all SR queues. 1832 * - A fixed offset can be added relative to the launch 1833 * time of all packets if configured at reg LAUNCH_OS0. 1834 * We are keeping it as 0 for now (default value). 1835 */ 1836 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1837 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1838 E1000_TQAVCTRL_FETCHTIME_DELTA; 1839 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1840 } else { 1841 /* If Launchtime is not enabled for any SR queues anymore, 1842 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1843 * effectively disabling Launchtime. 1844 */ 1845 if (!is_any_txtime_enabled(adapter)) { 1846 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1847 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1848 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1849 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1850 } 1851 } 1852 1853 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1854 * CBS are not configurable by software so we don't do any 'controller 1855 * configuration' in respect to these parameters. 1856 */ 1857 1858 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d \ 1859 idleslope %d sendslope %d hiCredit %d \ 1860 locredit %d\n", 1861 (ring->cbs_enable) ? "enabled" : "disabled", 1862 (ring->launchtime_enable) ? "enabled" : "disabled", queue, 1863 ring->idleslope, ring->sendslope, ring->hicredit, 1864 ring->locredit); 1865 } 1866 1867 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1868 bool enable) 1869 { 1870 struct igb_ring *ring; 1871 1872 if (queue < 0 || queue > adapter->num_tx_queues) 1873 return -EINVAL; 1874 1875 ring = adapter->tx_ring[queue]; 1876 ring->launchtime_enable = enable; 1877 1878 return 0; 1879 } 1880 1881 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1882 bool enable, int idleslope, int sendslope, 1883 int hicredit, int locredit) 1884 { 1885 struct igb_ring *ring; 1886 1887 if (queue < 0 || queue > adapter->num_tx_queues) 1888 return -EINVAL; 1889 1890 ring = adapter->tx_ring[queue]; 1891 1892 ring->cbs_enable = enable; 1893 ring->idleslope = idleslope; 1894 ring->sendslope = sendslope; 1895 ring->hicredit = hicredit; 1896 ring->locredit = locredit; 1897 1898 return 0; 1899 } 1900 1901 /** 1902 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1903 * @adapter: pointer to adapter struct 1904 * 1905 * Configure TQAVCTRL register switching the controller's Tx mode 1906 * if FQTSS mode is enabled or disabled. Additionally, will issue 1907 * a call to igb_config_tx_modes() per queue so any previously saved 1908 * Tx parameters are applied. 1909 **/ 1910 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1911 { 1912 struct net_device *netdev = adapter->netdev; 1913 struct e1000_hw *hw = &adapter->hw; 1914 u32 val; 1915 1916 /* Only i210 controller supports changing the transmission mode. */ 1917 if (hw->mac.type != e1000_i210) 1918 return; 1919 1920 if (is_fqtss_enabled(adapter)) { 1921 int i, max_queue; 1922 1923 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1924 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1925 * so SP queues wait for SR ones. 1926 */ 1927 val = rd32(E1000_I210_TQAVCTRL); 1928 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1929 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1930 wr32(E1000_I210_TQAVCTRL, val); 1931 1932 /* Configure Tx and Rx packet buffers sizes as described in 1933 * i210 datasheet section 7.2.7.7. 1934 */ 1935 val = rd32(E1000_TXPBS); 1936 val &= ~I210_TXPBSIZE_MASK; 1937 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1938 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1939 wr32(E1000_TXPBS, val); 1940 1941 val = rd32(E1000_RXPBS); 1942 val &= ~I210_RXPBSIZE_MASK; 1943 val |= I210_RXPBSIZE_PB_32KB; 1944 wr32(E1000_RXPBS, val); 1945 1946 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1947 * register should not exceed the buffer size programmed in 1948 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1949 * so according to the datasheet we should set MAX_TPKT_SIZE to 1950 * 4kB / 64. 1951 * 1952 * However, when we do so, no frame from queue 2 and 3 are 1953 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1954 * or _equal_ to the buffer size programmed in TXPBS. For this 1955 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1956 */ 1957 val = (4096 - 1) / 64; 1958 wr32(E1000_I210_DTXMXPKTSZ, val); 1959 1960 /* Since FQTSS mode is enabled, apply any CBS configuration 1961 * previously set. If no previous CBS configuration has been 1962 * done, then the initial configuration is applied, which means 1963 * CBS is disabled. 1964 */ 1965 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1966 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1967 1968 for (i = 0; i < max_queue; i++) { 1969 igb_config_tx_modes(adapter, i); 1970 } 1971 } else { 1972 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1973 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1974 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1975 1976 val = rd32(E1000_I210_TQAVCTRL); 1977 /* According to Section 8.12.21, the other flags we've set when 1978 * enabling FQTSS are not relevant when disabling FQTSS so we 1979 * don't set they here. 1980 */ 1981 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1982 wr32(E1000_I210_TQAVCTRL, val); 1983 } 1984 1985 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1986 "enabled" : "disabled"); 1987 } 1988 1989 /** 1990 * igb_configure - configure the hardware for RX and TX 1991 * @adapter: private board structure 1992 **/ 1993 static void igb_configure(struct igb_adapter *adapter) 1994 { 1995 struct net_device *netdev = adapter->netdev; 1996 int i; 1997 1998 igb_get_hw_control(adapter); 1999 igb_set_rx_mode(netdev); 2000 igb_setup_tx_mode(adapter); 2001 2002 igb_restore_vlan(adapter); 2003 2004 igb_setup_tctl(adapter); 2005 igb_setup_mrqc(adapter); 2006 igb_setup_rctl(adapter); 2007 2008 igb_nfc_filter_restore(adapter); 2009 igb_configure_tx(adapter); 2010 igb_configure_rx(adapter); 2011 2012 igb_rx_fifo_flush_82575(&adapter->hw); 2013 2014 /* call igb_desc_unused which always leaves 2015 * at least 1 descriptor unused to make sure 2016 * next_to_use != next_to_clean 2017 */ 2018 for (i = 0; i < adapter->num_rx_queues; i++) { 2019 struct igb_ring *ring = adapter->rx_ring[i]; 2020 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2021 } 2022 } 2023 2024 /** 2025 * igb_power_up_link - Power up the phy/serdes link 2026 * @adapter: address of board private structure 2027 **/ 2028 void igb_power_up_link(struct igb_adapter *adapter) 2029 { 2030 igb_reset_phy(&adapter->hw); 2031 2032 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2033 igb_power_up_phy_copper(&adapter->hw); 2034 else 2035 igb_power_up_serdes_link_82575(&adapter->hw); 2036 2037 igb_setup_link(&adapter->hw); 2038 } 2039 2040 /** 2041 * igb_power_down_link - Power down the phy/serdes link 2042 * @adapter: address of board private structure 2043 */ 2044 static void igb_power_down_link(struct igb_adapter *adapter) 2045 { 2046 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2047 igb_power_down_phy_copper_82575(&adapter->hw); 2048 else 2049 igb_shutdown_serdes_link_82575(&adapter->hw); 2050 } 2051 2052 /** 2053 * Detect and switch function for Media Auto Sense 2054 * @adapter: address of the board private structure 2055 **/ 2056 static void igb_check_swap_media(struct igb_adapter *adapter) 2057 { 2058 struct e1000_hw *hw = &adapter->hw; 2059 u32 ctrl_ext, connsw; 2060 bool swap_now = false; 2061 2062 ctrl_ext = rd32(E1000_CTRL_EXT); 2063 connsw = rd32(E1000_CONNSW); 2064 2065 /* need to live swap if current media is copper and we have fiber/serdes 2066 * to go to. 2067 */ 2068 2069 if ((hw->phy.media_type == e1000_media_type_copper) && 2070 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2071 swap_now = true; 2072 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 2073 /* copper signal takes time to appear */ 2074 if (adapter->copper_tries < 4) { 2075 adapter->copper_tries++; 2076 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2077 wr32(E1000_CONNSW, connsw); 2078 return; 2079 } else { 2080 adapter->copper_tries = 0; 2081 if ((connsw & E1000_CONNSW_PHYSD) && 2082 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2083 swap_now = true; 2084 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2085 wr32(E1000_CONNSW, connsw); 2086 } 2087 } 2088 } 2089 2090 if (!swap_now) 2091 return; 2092 2093 switch (hw->phy.media_type) { 2094 case e1000_media_type_copper: 2095 netdev_info(adapter->netdev, 2096 "MAS: changing media to fiber/serdes\n"); 2097 ctrl_ext |= 2098 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2099 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2100 adapter->copper_tries = 0; 2101 break; 2102 case e1000_media_type_internal_serdes: 2103 case e1000_media_type_fiber: 2104 netdev_info(adapter->netdev, 2105 "MAS: changing media to copper\n"); 2106 ctrl_ext &= 2107 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2108 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2109 break; 2110 default: 2111 /* shouldn't get here during regular operation */ 2112 netdev_err(adapter->netdev, 2113 "AMS: Invalid media type found, returning\n"); 2114 break; 2115 } 2116 wr32(E1000_CTRL_EXT, ctrl_ext); 2117 } 2118 2119 /** 2120 * igb_up - Open the interface and prepare it to handle traffic 2121 * @adapter: board private structure 2122 **/ 2123 int igb_up(struct igb_adapter *adapter) 2124 { 2125 struct e1000_hw *hw = &adapter->hw; 2126 int i; 2127 2128 /* hardware has been reset, we need to reload some things */ 2129 igb_configure(adapter); 2130 2131 clear_bit(__IGB_DOWN, &adapter->state); 2132 2133 for (i = 0; i < adapter->num_q_vectors; i++) 2134 napi_enable(&(adapter->q_vector[i]->napi)); 2135 2136 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2137 igb_configure_msix(adapter); 2138 else 2139 igb_assign_vector(adapter->q_vector[0], 0); 2140 2141 /* Clear any pending interrupts. */ 2142 rd32(E1000_TSICR); 2143 rd32(E1000_ICR); 2144 igb_irq_enable(adapter); 2145 2146 /* notify VFs that reset has been completed */ 2147 if (adapter->vfs_allocated_count) { 2148 u32 reg_data = rd32(E1000_CTRL_EXT); 2149 2150 reg_data |= E1000_CTRL_EXT_PFRSTD; 2151 wr32(E1000_CTRL_EXT, reg_data); 2152 } 2153 2154 netif_tx_start_all_queues(adapter->netdev); 2155 2156 /* start the watchdog. */ 2157 hw->mac.get_link_status = 1; 2158 schedule_work(&adapter->watchdog_task); 2159 2160 if ((adapter->flags & IGB_FLAG_EEE) && 2161 (!hw->dev_spec._82575.eee_disable)) 2162 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2163 2164 return 0; 2165 } 2166 2167 void igb_down(struct igb_adapter *adapter) 2168 { 2169 struct net_device *netdev = adapter->netdev; 2170 struct e1000_hw *hw = &adapter->hw; 2171 u32 tctl, rctl; 2172 int i; 2173 2174 /* signal that we're down so the interrupt handler does not 2175 * reschedule our watchdog timer 2176 */ 2177 set_bit(__IGB_DOWN, &adapter->state); 2178 2179 /* disable receives in the hardware */ 2180 rctl = rd32(E1000_RCTL); 2181 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2182 /* flush and sleep below */ 2183 2184 igb_nfc_filter_exit(adapter); 2185 2186 netif_carrier_off(netdev); 2187 netif_tx_stop_all_queues(netdev); 2188 2189 /* disable transmits in the hardware */ 2190 tctl = rd32(E1000_TCTL); 2191 tctl &= ~E1000_TCTL_EN; 2192 wr32(E1000_TCTL, tctl); 2193 /* flush both disables and wait for them to finish */ 2194 wrfl(); 2195 usleep_range(10000, 11000); 2196 2197 igb_irq_disable(adapter); 2198 2199 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2200 2201 for (i = 0; i < adapter->num_q_vectors; i++) { 2202 if (adapter->q_vector[i]) { 2203 napi_synchronize(&adapter->q_vector[i]->napi); 2204 napi_disable(&adapter->q_vector[i]->napi); 2205 } 2206 } 2207 2208 del_timer_sync(&adapter->watchdog_timer); 2209 del_timer_sync(&adapter->phy_info_timer); 2210 2211 /* record the stats before reset*/ 2212 spin_lock(&adapter->stats64_lock); 2213 igb_update_stats(adapter); 2214 spin_unlock(&adapter->stats64_lock); 2215 2216 adapter->link_speed = 0; 2217 adapter->link_duplex = 0; 2218 2219 if (!pci_channel_offline(adapter->pdev)) 2220 igb_reset(adapter); 2221 2222 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2223 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2224 2225 igb_clean_all_tx_rings(adapter); 2226 igb_clean_all_rx_rings(adapter); 2227 #ifdef CONFIG_IGB_DCA 2228 2229 /* since we reset the hardware DCA settings were cleared */ 2230 igb_setup_dca(adapter); 2231 #endif 2232 } 2233 2234 void igb_reinit_locked(struct igb_adapter *adapter) 2235 { 2236 WARN_ON(in_interrupt()); 2237 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2238 usleep_range(1000, 2000); 2239 igb_down(adapter); 2240 igb_up(adapter); 2241 clear_bit(__IGB_RESETTING, &adapter->state); 2242 } 2243 2244 /** igb_enable_mas - Media Autosense re-enable after swap 2245 * 2246 * @adapter: adapter struct 2247 **/ 2248 static void igb_enable_mas(struct igb_adapter *adapter) 2249 { 2250 struct e1000_hw *hw = &adapter->hw; 2251 u32 connsw = rd32(E1000_CONNSW); 2252 2253 /* configure for SerDes media detect */ 2254 if ((hw->phy.media_type == e1000_media_type_copper) && 2255 (!(connsw & E1000_CONNSW_SERDESD))) { 2256 connsw |= E1000_CONNSW_ENRGSRC; 2257 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2258 wr32(E1000_CONNSW, connsw); 2259 wrfl(); 2260 } 2261 } 2262 2263 void igb_reset(struct igb_adapter *adapter) 2264 { 2265 struct pci_dev *pdev = adapter->pdev; 2266 struct e1000_hw *hw = &adapter->hw; 2267 struct e1000_mac_info *mac = &hw->mac; 2268 struct e1000_fc_info *fc = &hw->fc; 2269 u32 pba, hwm; 2270 2271 /* Repartition Pba for greater than 9k mtu 2272 * To take effect CTRL.RST is required. 2273 */ 2274 switch (mac->type) { 2275 case e1000_i350: 2276 case e1000_i354: 2277 case e1000_82580: 2278 pba = rd32(E1000_RXPBS); 2279 pba = igb_rxpbs_adjust_82580(pba); 2280 break; 2281 case e1000_82576: 2282 pba = rd32(E1000_RXPBS); 2283 pba &= E1000_RXPBS_SIZE_MASK_82576; 2284 break; 2285 case e1000_82575: 2286 case e1000_i210: 2287 case e1000_i211: 2288 default: 2289 pba = E1000_PBA_34K; 2290 break; 2291 } 2292 2293 if (mac->type == e1000_82575) { 2294 u32 min_rx_space, min_tx_space, needed_tx_space; 2295 2296 /* write Rx PBA so that hardware can report correct Tx PBA */ 2297 wr32(E1000_PBA, pba); 2298 2299 /* To maintain wire speed transmits, the Tx FIFO should be 2300 * large enough to accommodate two full transmit packets, 2301 * rounded up to the next 1KB and expressed in KB. Likewise, 2302 * the Rx FIFO should be large enough to accommodate at least 2303 * one full receive packet and is similarly rounded up and 2304 * expressed in KB. 2305 */ 2306 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2307 2308 /* The Tx FIFO also stores 16 bytes of information about the Tx 2309 * but don't include Ethernet FCS because hardware appends it. 2310 * We only need to round down to the nearest 512 byte block 2311 * count since the value we care about is 2 frames, not 1. 2312 */ 2313 min_tx_space = adapter->max_frame_size; 2314 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2315 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2316 2317 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2318 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2319 2320 /* If current Tx allocation is less than the min Tx FIFO size, 2321 * and the min Tx FIFO size is less than the current Rx FIFO 2322 * allocation, take space away from current Rx allocation. 2323 */ 2324 if (needed_tx_space < pba) { 2325 pba -= needed_tx_space; 2326 2327 /* if short on Rx space, Rx wins and must trump Tx 2328 * adjustment 2329 */ 2330 if (pba < min_rx_space) 2331 pba = min_rx_space; 2332 } 2333 2334 /* adjust PBA for jumbo frames */ 2335 wr32(E1000_PBA, pba); 2336 } 2337 2338 /* flow control settings 2339 * The high water mark must be low enough to fit one full frame 2340 * after transmitting the pause frame. As such we must have enough 2341 * space to allow for us to complete our current transmit and then 2342 * receive the frame that is in progress from the link partner. 2343 * Set it to: 2344 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2345 */ 2346 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2347 2348 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2349 fc->low_water = fc->high_water - 16; 2350 fc->pause_time = 0xFFFF; 2351 fc->send_xon = 1; 2352 fc->current_mode = fc->requested_mode; 2353 2354 /* disable receive for all VFs and wait one second */ 2355 if (adapter->vfs_allocated_count) { 2356 int i; 2357 2358 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2359 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2360 2361 /* ping all the active vfs to let them know we are going down */ 2362 igb_ping_all_vfs(adapter); 2363 2364 /* disable transmits and receives */ 2365 wr32(E1000_VFRE, 0); 2366 wr32(E1000_VFTE, 0); 2367 } 2368 2369 /* Allow time for pending master requests to run */ 2370 hw->mac.ops.reset_hw(hw); 2371 wr32(E1000_WUC, 0); 2372 2373 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2374 /* need to resetup here after media swap */ 2375 adapter->ei.get_invariants(hw); 2376 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2377 } 2378 if ((mac->type == e1000_82575) && 2379 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2380 igb_enable_mas(adapter); 2381 } 2382 if (hw->mac.ops.init_hw(hw)) 2383 dev_err(&pdev->dev, "Hardware Error\n"); 2384 2385 /* RAR registers were cleared during init_hw, clear mac table */ 2386 igb_flush_mac_table(adapter); 2387 __dev_uc_unsync(adapter->netdev, NULL); 2388 2389 /* Recover default RAR entry */ 2390 igb_set_default_mac_filter(adapter); 2391 2392 /* Flow control settings reset on hardware reset, so guarantee flow 2393 * control is off when forcing speed. 2394 */ 2395 if (!hw->mac.autoneg) 2396 igb_force_mac_fc(hw); 2397 2398 igb_init_dmac(adapter, pba); 2399 #ifdef CONFIG_IGB_HWMON 2400 /* Re-initialize the thermal sensor on i350 devices. */ 2401 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2402 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2403 /* If present, re-initialize the external thermal sensor 2404 * interface. 2405 */ 2406 if (adapter->ets) 2407 mac->ops.init_thermal_sensor_thresh(hw); 2408 } 2409 } 2410 #endif 2411 /* Re-establish EEE setting */ 2412 if (hw->phy.media_type == e1000_media_type_copper) { 2413 switch (mac->type) { 2414 case e1000_i350: 2415 case e1000_i210: 2416 case e1000_i211: 2417 igb_set_eee_i350(hw, true, true); 2418 break; 2419 case e1000_i354: 2420 igb_set_eee_i354(hw, true, true); 2421 break; 2422 default: 2423 break; 2424 } 2425 } 2426 if (!netif_running(adapter->netdev)) 2427 igb_power_down_link(adapter); 2428 2429 igb_update_mng_vlan(adapter); 2430 2431 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2432 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2433 2434 /* Re-enable PTP, where applicable. */ 2435 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2436 igb_ptp_reset(adapter); 2437 2438 igb_get_phy_info(hw); 2439 } 2440 2441 static netdev_features_t igb_fix_features(struct net_device *netdev, 2442 netdev_features_t features) 2443 { 2444 /* Since there is no support for separate Rx/Tx vlan accel 2445 * enable/disable make sure Tx flag is always in same state as Rx. 2446 */ 2447 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2448 features |= NETIF_F_HW_VLAN_CTAG_TX; 2449 else 2450 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2451 2452 return features; 2453 } 2454 2455 static int igb_set_features(struct net_device *netdev, 2456 netdev_features_t features) 2457 { 2458 netdev_features_t changed = netdev->features ^ features; 2459 struct igb_adapter *adapter = netdev_priv(netdev); 2460 2461 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2462 igb_vlan_mode(netdev, features); 2463 2464 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2465 return 0; 2466 2467 if (!(features & NETIF_F_NTUPLE)) { 2468 struct hlist_node *node2; 2469 struct igb_nfc_filter *rule; 2470 2471 spin_lock(&adapter->nfc_lock); 2472 hlist_for_each_entry_safe(rule, node2, 2473 &adapter->nfc_filter_list, nfc_node) { 2474 igb_erase_filter(adapter, rule); 2475 hlist_del(&rule->nfc_node); 2476 kfree(rule); 2477 } 2478 spin_unlock(&adapter->nfc_lock); 2479 adapter->nfc_filter_count = 0; 2480 } 2481 2482 netdev->features = features; 2483 2484 if (netif_running(netdev)) 2485 igb_reinit_locked(adapter); 2486 else 2487 igb_reset(adapter); 2488 2489 return 0; 2490 } 2491 2492 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2493 struct net_device *dev, 2494 const unsigned char *addr, u16 vid, 2495 u16 flags) 2496 { 2497 /* guarantee we can provide a unique filter for the unicast address */ 2498 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2499 struct igb_adapter *adapter = netdev_priv(dev); 2500 int vfn = adapter->vfs_allocated_count; 2501 2502 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2503 return -ENOMEM; 2504 } 2505 2506 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2507 } 2508 2509 #define IGB_MAX_MAC_HDR_LEN 127 2510 #define IGB_MAX_NETWORK_HDR_LEN 511 2511 2512 static netdev_features_t 2513 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2514 netdev_features_t features) 2515 { 2516 unsigned int network_hdr_len, mac_hdr_len; 2517 2518 /* Make certain the headers can be described by a context descriptor */ 2519 mac_hdr_len = skb_network_header(skb) - skb->data; 2520 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2521 return features & ~(NETIF_F_HW_CSUM | 2522 NETIF_F_SCTP_CRC | 2523 NETIF_F_HW_VLAN_CTAG_TX | 2524 NETIF_F_TSO | 2525 NETIF_F_TSO6); 2526 2527 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2528 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2529 return features & ~(NETIF_F_HW_CSUM | 2530 NETIF_F_SCTP_CRC | 2531 NETIF_F_TSO | 2532 NETIF_F_TSO6); 2533 2534 /* We can only support IPV4 TSO in tunnels if we can mangle the 2535 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2536 */ 2537 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2538 features &= ~NETIF_F_TSO; 2539 2540 return features; 2541 } 2542 2543 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2544 { 2545 if (!is_fqtss_enabled(adapter)) { 2546 enable_fqtss(adapter, true); 2547 return; 2548 } 2549 2550 igb_config_tx_modes(adapter, queue); 2551 2552 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2553 enable_fqtss(adapter, false); 2554 } 2555 2556 static int igb_offload_cbs(struct igb_adapter *adapter, 2557 struct tc_cbs_qopt_offload *qopt) 2558 { 2559 struct e1000_hw *hw = &adapter->hw; 2560 int err; 2561 2562 /* CBS offloading is only supported by i210 controller. */ 2563 if (hw->mac.type != e1000_i210) 2564 return -EOPNOTSUPP; 2565 2566 /* CBS offloading is only supported by queue 0 and queue 1. */ 2567 if (qopt->queue < 0 || qopt->queue > 1) 2568 return -EINVAL; 2569 2570 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2571 qopt->idleslope, qopt->sendslope, 2572 qopt->hicredit, qopt->locredit); 2573 if (err) 2574 return err; 2575 2576 igb_offload_apply(adapter, qopt->queue); 2577 2578 return 0; 2579 } 2580 2581 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2582 #define VLAN_PRIO_FULL_MASK (0x07) 2583 2584 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2585 struct tc_cls_flower_offload *f, 2586 int traffic_class, 2587 struct igb_nfc_filter *input) 2588 { 2589 struct netlink_ext_ack *extack = f->common.extack; 2590 2591 if (f->dissector->used_keys & 2592 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2593 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2594 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2595 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2596 NL_SET_ERR_MSG_MOD(extack, 2597 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2598 return -EOPNOTSUPP; 2599 } 2600 2601 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2602 struct flow_dissector_key_eth_addrs *key, *mask; 2603 2604 key = skb_flow_dissector_target(f->dissector, 2605 FLOW_DISSECTOR_KEY_ETH_ADDRS, 2606 f->key); 2607 mask = skb_flow_dissector_target(f->dissector, 2608 FLOW_DISSECTOR_KEY_ETH_ADDRS, 2609 f->mask); 2610 2611 if (!is_zero_ether_addr(mask->dst)) { 2612 if (!is_broadcast_ether_addr(mask->dst)) { 2613 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2614 return -EINVAL; 2615 } 2616 2617 input->filter.match_flags |= 2618 IGB_FILTER_FLAG_DST_MAC_ADDR; 2619 ether_addr_copy(input->filter.dst_addr, key->dst); 2620 } 2621 2622 if (!is_zero_ether_addr(mask->src)) { 2623 if (!is_broadcast_ether_addr(mask->src)) { 2624 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2625 return -EINVAL; 2626 } 2627 2628 input->filter.match_flags |= 2629 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2630 ether_addr_copy(input->filter.src_addr, key->src); 2631 } 2632 } 2633 2634 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) { 2635 struct flow_dissector_key_basic *key, *mask; 2636 2637 key = skb_flow_dissector_target(f->dissector, 2638 FLOW_DISSECTOR_KEY_BASIC, 2639 f->key); 2640 mask = skb_flow_dissector_target(f->dissector, 2641 FLOW_DISSECTOR_KEY_BASIC, 2642 f->mask); 2643 2644 if (mask->n_proto) { 2645 if (mask->n_proto != ETHER_TYPE_FULL_MASK) { 2646 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2647 return -EINVAL; 2648 } 2649 2650 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2651 input->filter.etype = key->n_proto; 2652 } 2653 } 2654 2655 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) { 2656 struct flow_dissector_key_vlan *key, *mask; 2657 2658 key = skb_flow_dissector_target(f->dissector, 2659 FLOW_DISSECTOR_KEY_VLAN, 2660 f->key); 2661 mask = skb_flow_dissector_target(f->dissector, 2662 FLOW_DISSECTOR_KEY_VLAN, 2663 f->mask); 2664 2665 if (mask->vlan_priority) { 2666 if (mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2667 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2668 return -EINVAL; 2669 } 2670 2671 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2672 input->filter.vlan_tci = key->vlan_priority; 2673 } 2674 } 2675 2676 input->action = traffic_class; 2677 input->cookie = f->cookie; 2678 2679 return 0; 2680 } 2681 2682 static int igb_configure_clsflower(struct igb_adapter *adapter, 2683 struct tc_cls_flower_offload *cls_flower) 2684 { 2685 struct netlink_ext_ack *extack = cls_flower->common.extack; 2686 struct igb_nfc_filter *filter, *f; 2687 int err, tc; 2688 2689 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2690 if (tc < 0) { 2691 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2692 return -EINVAL; 2693 } 2694 2695 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2696 if (!filter) 2697 return -ENOMEM; 2698 2699 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2700 if (err < 0) 2701 goto err_parse; 2702 2703 spin_lock(&adapter->nfc_lock); 2704 2705 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2706 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2707 err = -EEXIST; 2708 NL_SET_ERR_MSG_MOD(extack, 2709 "This filter is already set in ethtool"); 2710 goto err_locked; 2711 } 2712 } 2713 2714 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2715 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2716 err = -EEXIST; 2717 NL_SET_ERR_MSG_MOD(extack, 2718 "This filter is already set in cls_flower"); 2719 goto err_locked; 2720 } 2721 } 2722 2723 err = igb_add_filter(adapter, filter); 2724 if (err < 0) { 2725 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2726 goto err_locked; 2727 } 2728 2729 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2730 2731 spin_unlock(&adapter->nfc_lock); 2732 2733 return 0; 2734 2735 err_locked: 2736 spin_unlock(&adapter->nfc_lock); 2737 2738 err_parse: 2739 kfree(filter); 2740 2741 return err; 2742 } 2743 2744 static int igb_delete_clsflower(struct igb_adapter *adapter, 2745 struct tc_cls_flower_offload *cls_flower) 2746 { 2747 struct igb_nfc_filter *filter; 2748 int err; 2749 2750 spin_lock(&adapter->nfc_lock); 2751 2752 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2753 if (filter->cookie == cls_flower->cookie) 2754 break; 2755 2756 if (!filter) { 2757 err = -ENOENT; 2758 goto out; 2759 } 2760 2761 err = igb_erase_filter(adapter, filter); 2762 if (err < 0) 2763 goto out; 2764 2765 hlist_del(&filter->nfc_node); 2766 kfree(filter); 2767 2768 out: 2769 spin_unlock(&adapter->nfc_lock); 2770 2771 return err; 2772 } 2773 2774 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2775 struct tc_cls_flower_offload *cls_flower) 2776 { 2777 switch (cls_flower->command) { 2778 case TC_CLSFLOWER_REPLACE: 2779 return igb_configure_clsflower(adapter, cls_flower); 2780 case TC_CLSFLOWER_DESTROY: 2781 return igb_delete_clsflower(adapter, cls_flower); 2782 case TC_CLSFLOWER_STATS: 2783 return -EOPNOTSUPP; 2784 default: 2785 return -EOPNOTSUPP; 2786 } 2787 } 2788 2789 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2790 void *cb_priv) 2791 { 2792 struct igb_adapter *adapter = cb_priv; 2793 2794 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2795 return -EOPNOTSUPP; 2796 2797 switch (type) { 2798 case TC_SETUP_CLSFLOWER: 2799 return igb_setup_tc_cls_flower(adapter, type_data); 2800 2801 default: 2802 return -EOPNOTSUPP; 2803 } 2804 } 2805 2806 static int igb_setup_tc_block(struct igb_adapter *adapter, 2807 struct tc_block_offload *f) 2808 { 2809 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2810 return -EOPNOTSUPP; 2811 2812 switch (f->command) { 2813 case TC_BLOCK_BIND: 2814 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb, 2815 adapter, adapter, f->extack); 2816 case TC_BLOCK_UNBIND: 2817 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb, 2818 adapter); 2819 return 0; 2820 default: 2821 return -EOPNOTSUPP; 2822 } 2823 } 2824 2825 static int igb_offload_txtime(struct igb_adapter *adapter, 2826 struct tc_etf_qopt_offload *qopt) 2827 { 2828 struct e1000_hw *hw = &adapter->hw; 2829 int err; 2830 2831 /* Launchtime offloading is only supported by i210 controller. */ 2832 if (hw->mac.type != e1000_i210) 2833 return -EOPNOTSUPP; 2834 2835 /* Launchtime offloading is only supported by queues 0 and 1. */ 2836 if (qopt->queue < 0 || qopt->queue > 1) 2837 return -EINVAL; 2838 2839 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2840 if (err) 2841 return err; 2842 2843 igb_offload_apply(adapter, qopt->queue); 2844 2845 return 0; 2846 } 2847 2848 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2849 void *type_data) 2850 { 2851 struct igb_adapter *adapter = netdev_priv(dev); 2852 2853 switch (type) { 2854 case TC_SETUP_QDISC_CBS: 2855 return igb_offload_cbs(adapter, type_data); 2856 case TC_SETUP_BLOCK: 2857 return igb_setup_tc_block(adapter, type_data); 2858 case TC_SETUP_QDISC_ETF: 2859 return igb_offload_txtime(adapter, type_data); 2860 2861 default: 2862 return -EOPNOTSUPP; 2863 } 2864 } 2865 2866 static const struct net_device_ops igb_netdev_ops = { 2867 .ndo_open = igb_open, 2868 .ndo_stop = igb_close, 2869 .ndo_start_xmit = igb_xmit_frame, 2870 .ndo_get_stats64 = igb_get_stats64, 2871 .ndo_set_rx_mode = igb_set_rx_mode, 2872 .ndo_set_mac_address = igb_set_mac, 2873 .ndo_change_mtu = igb_change_mtu, 2874 .ndo_do_ioctl = igb_ioctl, 2875 .ndo_tx_timeout = igb_tx_timeout, 2876 .ndo_validate_addr = eth_validate_addr, 2877 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2878 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2879 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2880 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2881 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2882 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2883 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2884 .ndo_get_vf_config = igb_ndo_get_vf_config, 2885 #ifdef CONFIG_NET_POLL_CONTROLLER 2886 .ndo_poll_controller = igb_netpoll, 2887 #endif 2888 .ndo_fix_features = igb_fix_features, 2889 .ndo_set_features = igb_set_features, 2890 .ndo_fdb_add = igb_ndo_fdb_add, 2891 .ndo_features_check = igb_features_check, 2892 .ndo_setup_tc = igb_setup_tc, 2893 }; 2894 2895 /** 2896 * igb_set_fw_version - Configure version string for ethtool 2897 * @adapter: adapter struct 2898 **/ 2899 void igb_set_fw_version(struct igb_adapter *adapter) 2900 { 2901 struct e1000_hw *hw = &adapter->hw; 2902 struct e1000_fw_version fw; 2903 2904 igb_get_fw_version(hw, &fw); 2905 2906 switch (hw->mac.type) { 2907 case e1000_i210: 2908 case e1000_i211: 2909 if (!(igb_get_flash_presence_i210(hw))) { 2910 snprintf(adapter->fw_version, 2911 sizeof(adapter->fw_version), 2912 "%2d.%2d-%d", 2913 fw.invm_major, fw.invm_minor, 2914 fw.invm_img_type); 2915 break; 2916 } 2917 /* fall through */ 2918 default: 2919 /* if option is rom valid, display its version too */ 2920 if (fw.or_valid) { 2921 snprintf(adapter->fw_version, 2922 sizeof(adapter->fw_version), 2923 "%d.%d, 0x%08x, %d.%d.%d", 2924 fw.eep_major, fw.eep_minor, fw.etrack_id, 2925 fw.or_major, fw.or_build, fw.or_patch); 2926 /* no option rom */ 2927 } else if (fw.etrack_id != 0X0000) { 2928 snprintf(adapter->fw_version, 2929 sizeof(adapter->fw_version), 2930 "%d.%d, 0x%08x", 2931 fw.eep_major, fw.eep_minor, fw.etrack_id); 2932 } else { 2933 snprintf(adapter->fw_version, 2934 sizeof(adapter->fw_version), 2935 "%d.%d.%d", 2936 fw.eep_major, fw.eep_minor, fw.eep_build); 2937 } 2938 break; 2939 } 2940 } 2941 2942 /** 2943 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2944 * 2945 * @adapter: adapter struct 2946 **/ 2947 static void igb_init_mas(struct igb_adapter *adapter) 2948 { 2949 struct e1000_hw *hw = &adapter->hw; 2950 u16 eeprom_data; 2951 2952 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2953 switch (hw->bus.func) { 2954 case E1000_FUNC_0: 2955 if (eeprom_data & IGB_MAS_ENABLE_0) { 2956 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2957 netdev_info(adapter->netdev, 2958 "MAS: Enabling Media Autosense for port %d\n", 2959 hw->bus.func); 2960 } 2961 break; 2962 case E1000_FUNC_1: 2963 if (eeprom_data & IGB_MAS_ENABLE_1) { 2964 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2965 netdev_info(adapter->netdev, 2966 "MAS: Enabling Media Autosense for port %d\n", 2967 hw->bus.func); 2968 } 2969 break; 2970 case E1000_FUNC_2: 2971 if (eeprom_data & IGB_MAS_ENABLE_2) { 2972 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2973 netdev_info(adapter->netdev, 2974 "MAS: Enabling Media Autosense for port %d\n", 2975 hw->bus.func); 2976 } 2977 break; 2978 case E1000_FUNC_3: 2979 if (eeprom_data & IGB_MAS_ENABLE_3) { 2980 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2981 netdev_info(adapter->netdev, 2982 "MAS: Enabling Media Autosense for port %d\n", 2983 hw->bus.func); 2984 } 2985 break; 2986 default: 2987 /* Shouldn't get here */ 2988 netdev_err(adapter->netdev, 2989 "MAS: Invalid port configuration, returning\n"); 2990 break; 2991 } 2992 } 2993 2994 /** 2995 * igb_init_i2c - Init I2C interface 2996 * @adapter: pointer to adapter structure 2997 **/ 2998 static s32 igb_init_i2c(struct igb_adapter *adapter) 2999 { 3000 s32 status = 0; 3001 3002 /* I2C interface supported on i350 devices */ 3003 if (adapter->hw.mac.type != e1000_i350) 3004 return 0; 3005 3006 /* Initialize the i2c bus which is controlled by the registers. 3007 * This bus will use the i2c_algo_bit structue that implements 3008 * the protocol through toggling of the 4 bits in the register. 3009 */ 3010 adapter->i2c_adap.owner = THIS_MODULE; 3011 adapter->i2c_algo = igb_i2c_algo; 3012 adapter->i2c_algo.data = adapter; 3013 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3014 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3015 strlcpy(adapter->i2c_adap.name, "igb BB", 3016 sizeof(adapter->i2c_adap.name)); 3017 status = i2c_bit_add_bus(&adapter->i2c_adap); 3018 return status; 3019 } 3020 3021 /** 3022 * igb_probe - Device Initialization Routine 3023 * @pdev: PCI device information struct 3024 * @ent: entry in igb_pci_tbl 3025 * 3026 * Returns 0 on success, negative on failure 3027 * 3028 * igb_probe initializes an adapter identified by a pci_dev structure. 3029 * The OS initialization, configuring of the adapter private structure, 3030 * and a hardware reset occur. 3031 **/ 3032 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3033 { 3034 struct net_device *netdev; 3035 struct igb_adapter *adapter; 3036 struct e1000_hw *hw; 3037 u16 eeprom_data = 0; 3038 s32 ret_val; 3039 static int global_quad_port_a; /* global quad port a indication */ 3040 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3041 int err, pci_using_dac; 3042 u8 part_str[E1000_PBANUM_LENGTH]; 3043 3044 /* Catch broken hardware that put the wrong VF device ID in 3045 * the PCIe SR-IOV capability. 3046 */ 3047 if (pdev->is_virtfn) { 3048 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3049 pci_name(pdev), pdev->vendor, pdev->device); 3050 return -EINVAL; 3051 } 3052 3053 err = pci_enable_device_mem(pdev); 3054 if (err) 3055 return err; 3056 3057 pci_using_dac = 0; 3058 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3059 if (!err) { 3060 pci_using_dac = 1; 3061 } else { 3062 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3063 if (err) { 3064 dev_err(&pdev->dev, 3065 "No usable DMA configuration, aborting\n"); 3066 goto err_dma; 3067 } 3068 } 3069 3070 err = pci_request_mem_regions(pdev, igb_driver_name); 3071 if (err) 3072 goto err_pci_reg; 3073 3074 pci_enable_pcie_error_reporting(pdev); 3075 3076 pci_set_master(pdev); 3077 pci_save_state(pdev); 3078 3079 err = -ENOMEM; 3080 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3081 IGB_MAX_TX_QUEUES); 3082 if (!netdev) 3083 goto err_alloc_etherdev; 3084 3085 SET_NETDEV_DEV(netdev, &pdev->dev); 3086 3087 pci_set_drvdata(pdev, netdev); 3088 adapter = netdev_priv(netdev); 3089 adapter->netdev = netdev; 3090 adapter->pdev = pdev; 3091 hw = &adapter->hw; 3092 hw->back = adapter; 3093 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3094 3095 err = -EIO; 3096 adapter->io_addr = pci_iomap(pdev, 0, 0); 3097 if (!adapter->io_addr) 3098 goto err_ioremap; 3099 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3100 hw->hw_addr = adapter->io_addr; 3101 3102 netdev->netdev_ops = &igb_netdev_ops; 3103 igb_set_ethtool_ops(netdev); 3104 netdev->watchdog_timeo = 5 * HZ; 3105 3106 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3107 3108 netdev->mem_start = pci_resource_start(pdev, 0); 3109 netdev->mem_end = pci_resource_end(pdev, 0); 3110 3111 /* PCI config space info */ 3112 hw->vendor_id = pdev->vendor; 3113 hw->device_id = pdev->device; 3114 hw->revision_id = pdev->revision; 3115 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3116 hw->subsystem_device_id = pdev->subsystem_device; 3117 3118 /* Copy the default MAC, PHY and NVM function pointers */ 3119 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3120 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3121 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3122 /* Initialize skew-specific constants */ 3123 err = ei->get_invariants(hw); 3124 if (err) 3125 goto err_sw_init; 3126 3127 /* setup the private structure */ 3128 err = igb_sw_init(adapter); 3129 if (err) 3130 goto err_sw_init; 3131 3132 igb_get_bus_info_pcie(hw); 3133 3134 hw->phy.autoneg_wait_to_complete = false; 3135 3136 /* Copper options */ 3137 if (hw->phy.media_type == e1000_media_type_copper) { 3138 hw->phy.mdix = AUTO_ALL_MODES; 3139 hw->phy.disable_polarity_correction = false; 3140 hw->phy.ms_type = e1000_ms_hw_default; 3141 } 3142 3143 if (igb_check_reset_block(hw)) 3144 dev_info(&pdev->dev, 3145 "PHY reset is blocked due to SOL/IDER session.\n"); 3146 3147 /* features is initialized to 0 in allocation, it might have bits 3148 * set by igb_sw_init so we should use an or instead of an 3149 * assignment. 3150 */ 3151 netdev->features |= NETIF_F_SG | 3152 NETIF_F_TSO | 3153 NETIF_F_TSO6 | 3154 NETIF_F_RXHASH | 3155 NETIF_F_RXCSUM | 3156 NETIF_F_HW_CSUM; 3157 3158 if (hw->mac.type >= e1000_82576) 3159 netdev->features |= NETIF_F_SCTP_CRC; 3160 3161 if (hw->mac.type >= e1000_i350) 3162 netdev->features |= NETIF_F_HW_TC; 3163 3164 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3165 NETIF_F_GSO_GRE_CSUM | \ 3166 NETIF_F_GSO_IPXIP4 | \ 3167 NETIF_F_GSO_IPXIP6 | \ 3168 NETIF_F_GSO_UDP_TUNNEL | \ 3169 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3170 3171 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3172 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3173 3174 /* copy netdev features into list of user selectable features */ 3175 netdev->hw_features |= netdev->features | 3176 NETIF_F_HW_VLAN_CTAG_RX | 3177 NETIF_F_HW_VLAN_CTAG_TX | 3178 NETIF_F_RXALL; 3179 3180 if (hw->mac.type >= e1000_i350) 3181 netdev->hw_features |= NETIF_F_NTUPLE; 3182 3183 if (pci_using_dac) 3184 netdev->features |= NETIF_F_HIGHDMA; 3185 3186 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3187 netdev->mpls_features |= NETIF_F_HW_CSUM; 3188 netdev->hw_enc_features |= netdev->vlan_features; 3189 3190 /* set this bit last since it cannot be part of vlan_features */ 3191 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3192 NETIF_F_HW_VLAN_CTAG_RX | 3193 NETIF_F_HW_VLAN_CTAG_TX; 3194 3195 netdev->priv_flags |= IFF_SUPP_NOFCS; 3196 3197 netdev->priv_flags |= IFF_UNICAST_FLT; 3198 3199 /* MTU range: 68 - 9216 */ 3200 netdev->min_mtu = ETH_MIN_MTU; 3201 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3202 3203 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3204 3205 /* before reading the NVM, reset the controller to put the device in a 3206 * known good starting state 3207 */ 3208 hw->mac.ops.reset_hw(hw); 3209 3210 /* make sure the NVM is good , i211/i210 parts can have special NVM 3211 * that doesn't contain a checksum 3212 */ 3213 switch (hw->mac.type) { 3214 case e1000_i210: 3215 case e1000_i211: 3216 if (igb_get_flash_presence_i210(hw)) { 3217 if (hw->nvm.ops.validate(hw) < 0) { 3218 dev_err(&pdev->dev, 3219 "The NVM Checksum Is Not Valid\n"); 3220 err = -EIO; 3221 goto err_eeprom; 3222 } 3223 } 3224 break; 3225 default: 3226 if (hw->nvm.ops.validate(hw) < 0) { 3227 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3228 err = -EIO; 3229 goto err_eeprom; 3230 } 3231 break; 3232 } 3233 3234 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3235 /* copy the MAC address out of the NVM */ 3236 if (hw->mac.ops.read_mac_addr(hw)) 3237 dev_err(&pdev->dev, "NVM Read Error\n"); 3238 } 3239 3240 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3241 3242 if (!is_valid_ether_addr(netdev->dev_addr)) { 3243 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3244 err = -EIO; 3245 goto err_eeprom; 3246 } 3247 3248 igb_set_default_mac_filter(adapter); 3249 3250 /* get firmware version for ethtool -i */ 3251 igb_set_fw_version(adapter); 3252 3253 /* configure RXPBSIZE and TXPBSIZE */ 3254 if (hw->mac.type == e1000_i210) { 3255 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3256 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3257 } 3258 3259 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3260 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3261 3262 INIT_WORK(&adapter->reset_task, igb_reset_task); 3263 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3264 3265 /* Initialize link properties that are user-changeable */ 3266 adapter->fc_autoneg = true; 3267 hw->mac.autoneg = true; 3268 hw->phy.autoneg_advertised = 0x2f; 3269 3270 hw->fc.requested_mode = e1000_fc_default; 3271 hw->fc.current_mode = e1000_fc_default; 3272 3273 igb_validate_mdi_setting(hw); 3274 3275 /* By default, support wake on port A */ 3276 if (hw->bus.func == 0) 3277 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3278 3279 /* Check the NVM for wake support on non-port A ports */ 3280 if (hw->mac.type >= e1000_82580) 3281 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3282 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3283 &eeprom_data); 3284 else if (hw->bus.func == 1) 3285 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3286 3287 if (eeprom_data & IGB_EEPROM_APME) 3288 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3289 3290 /* now that we have the eeprom settings, apply the special cases where 3291 * the eeprom may be wrong or the board simply won't support wake on 3292 * lan on a particular port 3293 */ 3294 switch (pdev->device) { 3295 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3296 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3297 break; 3298 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3299 case E1000_DEV_ID_82576_FIBER: 3300 case E1000_DEV_ID_82576_SERDES: 3301 /* Wake events only supported on port A for dual fiber 3302 * regardless of eeprom setting 3303 */ 3304 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3305 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3306 break; 3307 case E1000_DEV_ID_82576_QUAD_COPPER: 3308 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3309 /* if quad port adapter, disable WoL on all but port A */ 3310 if (global_quad_port_a != 0) 3311 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3312 else 3313 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3314 /* Reset for multiple quad port adapters */ 3315 if (++global_quad_port_a == 4) 3316 global_quad_port_a = 0; 3317 break; 3318 default: 3319 /* If the device can't wake, don't set software support */ 3320 if (!device_can_wakeup(&adapter->pdev->dev)) 3321 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3322 } 3323 3324 /* initialize the wol settings based on the eeprom settings */ 3325 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3326 adapter->wol |= E1000_WUFC_MAG; 3327 3328 /* Some vendors want WoL disabled by default, but still supported */ 3329 if ((hw->mac.type == e1000_i350) && 3330 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3331 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3332 adapter->wol = 0; 3333 } 3334 3335 /* Some vendors want the ability to Use the EEPROM setting as 3336 * enable/disable only, and not for capability 3337 */ 3338 if (((hw->mac.type == e1000_i350) || 3339 (hw->mac.type == e1000_i354)) && 3340 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3341 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3342 adapter->wol = 0; 3343 } 3344 if (hw->mac.type == e1000_i350) { 3345 if (((pdev->subsystem_device == 0x5001) || 3346 (pdev->subsystem_device == 0x5002)) && 3347 (hw->bus.func == 0)) { 3348 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3349 adapter->wol = 0; 3350 } 3351 if (pdev->subsystem_device == 0x1F52) 3352 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3353 } 3354 3355 device_set_wakeup_enable(&adapter->pdev->dev, 3356 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3357 3358 /* reset the hardware with the new settings */ 3359 igb_reset(adapter); 3360 3361 /* Init the I2C interface */ 3362 err = igb_init_i2c(adapter); 3363 if (err) { 3364 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3365 goto err_eeprom; 3366 } 3367 3368 /* let the f/w know that the h/w is now under the control of the 3369 * driver. 3370 */ 3371 igb_get_hw_control(adapter); 3372 3373 strcpy(netdev->name, "eth%d"); 3374 err = register_netdev(netdev); 3375 if (err) 3376 goto err_register; 3377 3378 /* carrier off reporting is important to ethtool even BEFORE open */ 3379 netif_carrier_off(netdev); 3380 3381 #ifdef CONFIG_IGB_DCA 3382 if (dca_add_requester(&pdev->dev) == 0) { 3383 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3384 dev_info(&pdev->dev, "DCA enabled\n"); 3385 igb_setup_dca(adapter); 3386 } 3387 3388 #endif 3389 #ifdef CONFIG_IGB_HWMON 3390 /* Initialize the thermal sensor on i350 devices. */ 3391 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3392 u16 ets_word; 3393 3394 /* Read the NVM to determine if this i350 device supports an 3395 * external thermal sensor. 3396 */ 3397 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3398 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3399 adapter->ets = true; 3400 else 3401 adapter->ets = false; 3402 if (igb_sysfs_init(adapter)) 3403 dev_err(&pdev->dev, 3404 "failed to allocate sysfs resources\n"); 3405 } else { 3406 adapter->ets = false; 3407 } 3408 #endif 3409 /* Check if Media Autosense is enabled */ 3410 adapter->ei = *ei; 3411 if (hw->dev_spec._82575.mas_capable) 3412 igb_init_mas(adapter); 3413 3414 /* do hw tstamp init after resetting */ 3415 igb_ptp_init(adapter); 3416 3417 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3418 /* print bus type/speed/width info, not applicable to i354 */ 3419 if (hw->mac.type != e1000_i354) { 3420 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3421 netdev->name, 3422 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3423 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3424 "unknown"), 3425 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3426 "Width x4" : 3427 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3428 "Width x2" : 3429 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3430 "Width x1" : "unknown"), netdev->dev_addr); 3431 } 3432 3433 if ((hw->mac.type >= e1000_i210 || 3434 igb_get_flash_presence_i210(hw))) { 3435 ret_val = igb_read_part_string(hw, part_str, 3436 E1000_PBANUM_LENGTH); 3437 } else { 3438 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3439 } 3440 3441 if (ret_val) 3442 strcpy(part_str, "Unknown"); 3443 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3444 dev_info(&pdev->dev, 3445 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3446 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3447 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3448 adapter->num_rx_queues, adapter->num_tx_queues); 3449 if (hw->phy.media_type == e1000_media_type_copper) { 3450 switch (hw->mac.type) { 3451 case e1000_i350: 3452 case e1000_i210: 3453 case e1000_i211: 3454 /* Enable EEE for internal copper PHY devices */ 3455 err = igb_set_eee_i350(hw, true, true); 3456 if ((!err) && 3457 (!hw->dev_spec._82575.eee_disable)) { 3458 adapter->eee_advert = 3459 MDIO_EEE_100TX | MDIO_EEE_1000T; 3460 adapter->flags |= IGB_FLAG_EEE; 3461 } 3462 break; 3463 case e1000_i354: 3464 if ((rd32(E1000_CTRL_EXT) & 3465 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3466 err = igb_set_eee_i354(hw, true, true); 3467 if ((!err) && 3468 (!hw->dev_spec._82575.eee_disable)) { 3469 adapter->eee_advert = 3470 MDIO_EEE_100TX | MDIO_EEE_1000T; 3471 adapter->flags |= IGB_FLAG_EEE; 3472 } 3473 } 3474 break; 3475 default: 3476 break; 3477 } 3478 } 3479 pm_runtime_put_noidle(&pdev->dev); 3480 return 0; 3481 3482 err_register: 3483 igb_release_hw_control(adapter); 3484 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3485 err_eeprom: 3486 if (!igb_check_reset_block(hw)) 3487 igb_reset_phy(hw); 3488 3489 if (hw->flash_address) 3490 iounmap(hw->flash_address); 3491 err_sw_init: 3492 kfree(adapter->mac_table); 3493 kfree(adapter->shadow_vfta); 3494 igb_clear_interrupt_scheme(adapter); 3495 #ifdef CONFIG_PCI_IOV 3496 igb_disable_sriov(pdev); 3497 #endif 3498 pci_iounmap(pdev, adapter->io_addr); 3499 err_ioremap: 3500 free_netdev(netdev); 3501 err_alloc_etherdev: 3502 pci_release_mem_regions(pdev); 3503 err_pci_reg: 3504 err_dma: 3505 pci_disable_device(pdev); 3506 return err; 3507 } 3508 3509 #ifdef CONFIG_PCI_IOV 3510 static int igb_disable_sriov(struct pci_dev *pdev) 3511 { 3512 struct net_device *netdev = pci_get_drvdata(pdev); 3513 struct igb_adapter *adapter = netdev_priv(netdev); 3514 struct e1000_hw *hw = &adapter->hw; 3515 3516 /* reclaim resources allocated to VFs */ 3517 if (adapter->vf_data) { 3518 /* disable iov and allow time for transactions to clear */ 3519 if (pci_vfs_assigned(pdev)) { 3520 dev_warn(&pdev->dev, 3521 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3522 return -EPERM; 3523 } else { 3524 pci_disable_sriov(pdev); 3525 msleep(500); 3526 } 3527 3528 kfree(adapter->vf_mac_list); 3529 adapter->vf_mac_list = NULL; 3530 kfree(adapter->vf_data); 3531 adapter->vf_data = NULL; 3532 adapter->vfs_allocated_count = 0; 3533 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3534 wrfl(); 3535 msleep(100); 3536 dev_info(&pdev->dev, "IOV Disabled\n"); 3537 3538 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3539 adapter->flags |= IGB_FLAG_DMAC; 3540 } 3541 3542 return 0; 3543 } 3544 3545 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3546 { 3547 struct net_device *netdev = pci_get_drvdata(pdev); 3548 struct igb_adapter *adapter = netdev_priv(netdev); 3549 int old_vfs = pci_num_vf(pdev); 3550 struct vf_mac_filter *mac_list; 3551 int err = 0; 3552 int num_vf_mac_filters, i; 3553 3554 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3555 err = -EPERM; 3556 goto out; 3557 } 3558 if (!num_vfs) 3559 goto out; 3560 3561 if (old_vfs) { 3562 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3563 old_vfs, max_vfs); 3564 adapter->vfs_allocated_count = old_vfs; 3565 } else 3566 adapter->vfs_allocated_count = num_vfs; 3567 3568 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3569 sizeof(struct vf_data_storage), GFP_KERNEL); 3570 3571 /* if allocation failed then we do not support SR-IOV */ 3572 if (!adapter->vf_data) { 3573 adapter->vfs_allocated_count = 0; 3574 err = -ENOMEM; 3575 goto out; 3576 } 3577 3578 /* Due to the limited number of RAR entries calculate potential 3579 * number of MAC filters available for the VFs. Reserve entries 3580 * for PF default MAC, PF MAC filters and at least one RAR entry 3581 * for each VF for VF MAC. 3582 */ 3583 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3584 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3585 adapter->vfs_allocated_count); 3586 3587 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3588 sizeof(struct vf_mac_filter), 3589 GFP_KERNEL); 3590 3591 mac_list = adapter->vf_mac_list; 3592 INIT_LIST_HEAD(&adapter->vf_macs.l); 3593 3594 if (adapter->vf_mac_list) { 3595 /* Initialize list of VF MAC filters */ 3596 for (i = 0; i < num_vf_mac_filters; i++) { 3597 mac_list->vf = -1; 3598 mac_list->free = true; 3599 list_add(&mac_list->l, &adapter->vf_macs.l); 3600 mac_list++; 3601 } 3602 } else { 3603 /* If we could not allocate memory for the VF MAC filters 3604 * we can continue without this feature but warn user. 3605 */ 3606 dev_err(&pdev->dev, 3607 "Unable to allocate memory for VF MAC filter list\n"); 3608 } 3609 3610 /* only call pci_enable_sriov() if no VFs are allocated already */ 3611 if (!old_vfs) { 3612 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3613 if (err) 3614 goto err_out; 3615 } 3616 dev_info(&pdev->dev, "%d VFs allocated\n", 3617 adapter->vfs_allocated_count); 3618 for (i = 0; i < adapter->vfs_allocated_count; i++) 3619 igb_vf_configure(adapter, i); 3620 3621 /* DMA Coalescing is not supported in IOV mode. */ 3622 adapter->flags &= ~IGB_FLAG_DMAC; 3623 goto out; 3624 3625 err_out: 3626 kfree(adapter->vf_mac_list); 3627 adapter->vf_mac_list = NULL; 3628 kfree(adapter->vf_data); 3629 adapter->vf_data = NULL; 3630 adapter->vfs_allocated_count = 0; 3631 out: 3632 return err; 3633 } 3634 3635 #endif 3636 /** 3637 * igb_remove_i2c - Cleanup I2C interface 3638 * @adapter: pointer to adapter structure 3639 **/ 3640 static void igb_remove_i2c(struct igb_adapter *adapter) 3641 { 3642 /* free the adapter bus structure */ 3643 i2c_del_adapter(&adapter->i2c_adap); 3644 } 3645 3646 /** 3647 * igb_remove - Device Removal Routine 3648 * @pdev: PCI device information struct 3649 * 3650 * igb_remove is called by the PCI subsystem to alert the driver 3651 * that it should release a PCI device. The could be caused by a 3652 * Hot-Plug event, or because the driver is going to be removed from 3653 * memory. 3654 **/ 3655 static void igb_remove(struct pci_dev *pdev) 3656 { 3657 struct net_device *netdev = pci_get_drvdata(pdev); 3658 struct igb_adapter *adapter = netdev_priv(netdev); 3659 struct e1000_hw *hw = &adapter->hw; 3660 3661 pm_runtime_get_noresume(&pdev->dev); 3662 #ifdef CONFIG_IGB_HWMON 3663 igb_sysfs_exit(adapter); 3664 #endif 3665 igb_remove_i2c(adapter); 3666 igb_ptp_stop(adapter); 3667 /* The watchdog timer may be rescheduled, so explicitly 3668 * disable watchdog from being rescheduled. 3669 */ 3670 set_bit(__IGB_DOWN, &adapter->state); 3671 del_timer_sync(&adapter->watchdog_timer); 3672 del_timer_sync(&adapter->phy_info_timer); 3673 3674 cancel_work_sync(&adapter->reset_task); 3675 cancel_work_sync(&adapter->watchdog_task); 3676 3677 #ifdef CONFIG_IGB_DCA 3678 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3679 dev_info(&pdev->dev, "DCA disabled\n"); 3680 dca_remove_requester(&pdev->dev); 3681 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3682 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3683 } 3684 #endif 3685 3686 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3687 * would have already happened in close and is redundant. 3688 */ 3689 igb_release_hw_control(adapter); 3690 3691 #ifdef CONFIG_PCI_IOV 3692 igb_disable_sriov(pdev); 3693 #endif 3694 3695 unregister_netdev(netdev); 3696 3697 igb_clear_interrupt_scheme(adapter); 3698 3699 pci_iounmap(pdev, adapter->io_addr); 3700 if (hw->flash_address) 3701 iounmap(hw->flash_address); 3702 pci_release_mem_regions(pdev); 3703 3704 kfree(adapter->mac_table); 3705 kfree(adapter->shadow_vfta); 3706 free_netdev(netdev); 3707 3708 pci_disable_pcie_error_reporting(pdev); 3709 3710 pci_disable_device(pdev); 3711 } 3712 3713 /** 3714 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3715 * @adapter: board private structure to initialize 3716 * 3717 * This function initializes the vf specific data storage and then attempts to 3718 * allocate the VFs. The reason for ordering it this way is because it is much 3719 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3720 * the memory for the VFs. 3721 **/ 3722 static void igb_probe_vfs(struct igb_adapter *adapter) 3723 { 3724 #ifdef CONFIG_PCI_IOV 3725 struct pci_dev *pdev = adapter->pdev; 3726 struct e1000_hw *hw = &adapter->hw; 3727 3728 /* Virtualization features not supported on i210 family. */ 3729 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3730 return; 3731 3732 /* Of the below we really only want the effect of getting 3733 * IGB_FLAG_HAS_MSIX set (if available), without which 3734 * igb_enable_sriov() has no effect. 3735 */ 3736 igb_set_interrupt_capability(adapter, true); 3737 igb_reset_interrupt_capability(adapter); 3738 3739 pci_sriov_set_totalvfs(pdev, 7); 3740 igb_enable_sriov(pdev, max_vfs); 3741 3742 #endif /* CONFIG_PCI_IOV */ 3743 } 3744 3745 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3746 { 3747 struct e1000_hw *hw = &adapter->hw; 3748 unsigned int max_rss_queues; 3749 3750 /* Determine the maximum number of RSS queues supported. */ 3751 switch (hw->mac.type) { 3752 case e1000_i211: 3753 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3754 break; 3755 case e1000_82575: 3756 case e1000_i210: 3757 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3758 break; 3759 case e1000_i350: 3760 /* I350 cannot do RSS and SR-IOV at the same time */ 3761 if (!!adapter->vfs_allocated_count) { 3762 max_rss_queues = 1; 3763 break; 3764 } 3765 /* fall through */ 3766 case e1000_82576: 3767 if (!!adapter->vfs_allocated_count) { 3768 max_rss_queues = 2; 3769 break; 3770 } 3771 /* fall through */ 3772 case e1000_82580: 3773 case e1000_i354: 3774 default: 3775 max_rss_queues = IGB_MAX_RX_QUEUES; 3776 break; 3777 } 3778 3779 return max_rss_queues; 3780 } 3781 3782 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3783 { 3784 u32 max_rss_queues; 3785 3786 max_rss_queues = igb_get_max_rss_queues(adapter); 3787 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3788 3789 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3790 } 3791 3792 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3793 const u32 max_rss_queues) 3794 { 3795 struct e1000_hw *hw = &adapter->hw; 3796 3797 /* Determine if we need to pair queues. */ 3798 switch (hw->mac.type) { 3799 case e1000_82575: 3800 case e1000_i211: 3801 /* Device supports enough interrupts without queue pairing. */ 3802 break; 3803 case e1000_82576: 3804 case e1000_82580: 3805 case e1000_i350: 3806 case e1000_i354: 3807 case e1000_i210: 3808 default: 3809 /* If rss_queues > half of max_rss_queues, pair the queues in 3810 * order to conserve interrupts due to limited supply. 3811 */ 3812 if (adapter->rss_queues > (max_rss_queues / 2)) 3813 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3814 else 3815 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3816 break; 3817 } 3818 } 3819 3820 /** 3821 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3822 * @adapter: board private structure to initialize 3823 * 3824 * igb_sw_init initializes the Adapter private data structure. 3825 * Fields are initialized based on PCI device information and 3826 * OS network device settings (MTU size). 3827 **/ 3828 static int igb_sw_init(struct igb_adapter *adapter) 3829 { 3830 struct e1000_hw *hw = &adapter->hw; 3831 struct net_device *netdev = adapter->netdev; 3832 struct pci_dev *pdev = adapter->pdev; 3833 3834 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3835 3836 /* set default ring sizes */ 3837 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3838 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3839 3840 /* set default ITR values */ 3841 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3842 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3843 3844 /* set default work limits */ 3845 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3846 3847 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3848 VLAN_HLEN; 3849 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3850 3851 spin_lock_init(&adapter->nfc_lock); 3852 spin_lock_init(&adapter->stats64_lock); 3853 #ifdef CONFIG_PCI_IOV 3854 switch (hw->mac.type) { 3855 case e1000_82576: 3856 case e1000_i350: 3857 if (max_vfs > 7) { 3858 dev_warn(&pdev->dev, 3859 "Maximum of 7 VFs per PF, using max\n"); 3860 max_vfs = adapter->vfs_allocated_count = 7; 3861 } else 3862 adapter->vfs_allocated_count = max_vfs; 3863 if (adapter->vfs_allocated_count) 3864 dev_warn(&pdev->dev, 3865 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3866 break; 3867 default: 3868 break; 3869 } 3870 #endif /* CONFIG_PCI_IOV */ 3871 3872 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3873 adapter->flags |= IGB_FLAG_HAS_MSIX; 3874 3875 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3876 sizeof(struct igb_mac_addr), 3877 GFP_ATOMIC); 3878 if (!adapter->mac_table) 3879 return -ENOMEM; 3880 3881 igb_probe_vfs(adapter); 3882 3883 igb_init_queue_configuration(adapter); 3884 3885 /* Setup and initialize a copy of the hw vlan table array */ 3886 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3887 GFP_ATOMIC); 3888 if (!adapter->shadow_vfta) 3889 return -ENOMEM; 3890 3891 /* This call may decrease the number of queues */ 3892 if (igb_init_interrupt_scheme(adapter, true)) { 3893 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3894 return -ENOMEM; 3895 } 3896 3897 /* Explicitly disable IRQ since the NIC can be in any state. */ 3898 igb_irq_disable(adapter); 3899 3900 if (hw->mac.type >= e1000_i350) 3901 adapter->flags &= ~IGB_FLAG_DMAC; 3902 3903 set_bit(__IGB_DOWN, &adapter->state); 3904 return 0; 3905 } 3906 3907 /** 3908 * igb_open - Called when a network interface is made active 3909 * @netdev: network interface device structure 3910 * 3911 * Returns 0 on success, negative value on failure 3912 * 3913 * The open entry point is called when a network interface is made 3914 * active by the system (IFF_UP). At this point all resources needed 3915 * for transmit and receive operations are allocated, the interrupt 3916 * handler is registered with the OS, the watchdog timer is started, 3917 * and the stack is notified that the interface is ready. 3918 **/ 3919 static int __igb_open(struct net_device *netdev, bool resuming) 3920 { 3921 struct igb_adapter *adapter = netdev_priv(netdev); 3922 struct e1000_hw *hw = &adapter->hw; 3923 struct pci_dev *pdev = adapter->pdev; 3924 int err; 3925 int i; 3926 3927 /* disallow open during test */ 3928 if (test_bit(__IGB_TESTING, &adapter->state)) { 3929 WARN_ON(resuming); 3930 return -EBUSY; 3931 } 3932 3933 if (!resuming) 3934 pm_runtime_get_sync(&pdev->dev); 3935 3936 netif_carrier_off(netdev); 3937 3938 /* allocate transmit descriptors */ 3939 err = igb_setup_all_tx_resources(adapter); 3940 if (err) 3941 goto err_setup_tx; 3942 3943 /* allocate receive descriptors */ 3944 err = igb_setup_all_rx_resources(adapter); 3945 if (err) 3946 goto err_setup_rx; 3947 3948 igb_power_up_link(adapter); 3949 3950 /* before we allocate an interrupt, we must be ready to handle it. 3951 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3952 * as soon as we call pci_request_irq, so we have to setup our 3953 * clean_rx handler before we do so. 3954 */ 3955 igb_configure(adapter); 3956 3957 err = igb_request_irq(adapter); 3958 if (err) 3959 goto err_req_irq; 3960 3961 /* Notify the stack of the actual queue counts. */ 3962 err = netif_set_real_num_tx_queues(adapter->netdev, 3963 adapter->num_tx_queues); 3964 if (err) 3965 goto err_set_queues; 3966 3967 err = netif_set_real_num_rx_queues(adapter->netdev, 3968 adapter->num_rx_queues); 3969 if (err) 3970 goto err_set_queues; 3971 3972 /* From here on the code is the same as igb_up() */ 3973 clear_bit(__IGB_DOWN, &adapter->state); 3974 3975 for (i = 0; i < adapter->num_q_vectors; i++) 3976 napi_enable(&(adapter->q_vector[i]->napi)); 3977 3978 /* Clear any pending interrupts. */ 3979 rd32(E1000_TSICR); 3980 rd32(E1000_ICR); 3981 3982 igb_irq_enable(adapter); 3983 3984 /* notify VFs that reset has been completed */ 3985 if (adapter->vfs_allocated_count) { 3986 u32 reg_data = rd32(E1000_CTRL_EXT); 3987 3988 reg_data |= E1000_CTRL_EXT_PFRSTD; 3989 wr32(E1000_CTRL_EXT, reg_data); 3990 } 3991 3992 netif_tx_start_all_queues(netdev); 3993 3994 if (!resuming) 3995 pm_runtime_put(&pdev->dev); 3996 3997 /* start the watchdog. */ 3998 hw->mac.get_link_status = 1; 3999 schedule_work(&adapter->watchdog_task); 4000 4001 return 0; 4002 4003 err_set_queues: 4004 igb_free_irq(adapter); 4005 err_req_irq: 4006 igb_release_hw_control(adapter); 4007 igb_power_down_link(adapter); 4008 igb_free_all_rx_resources(adapter); 4009 err_setup_rx: 4010 igb_free_all_tx_resources(adapter); 4011 err_setup_tx: 4012 igb_reset(adapter); 4013 if (!resuming) 4014 pm_runtime_put(&pdev->dev); 4015 4016 return err; 4017 } 4018 4019 int igb_open(struct net_device *netdev) 4020 { 4021 return __igb_open(netdev, false); 4022 } 4023 4024 /** 4025 * igb_close - Disables a network interface 4026 * @netdev: network interface device structure 4027 * 4028 * Returns 0, this is not allowed to fail 4029 * 4030 * The close entry point is called when an interface is de-activated 4031 * by the OS. The hardware is still under the driver's control, but 4032 * needs to be disabled. A global MAC reset is issued to stop the 4033 * hardware, and all transmit and receive resources are freed. 4034 **/ 4035 static int __igb_close(struct net_device *netdev, bool suspending) 4036 { 4037 struct igb_adapter *adapter = netdev_priv(netdev); 4038 struct pci_dev *pdev = adapter->pdev; 4039 4040 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4041 4042 if (!suspending) 4043 pm_runtime_get_sync(&pdev->dev); 4044 4045 igb_down(adapter); 4046 igb_free_irq(adapter); 4047 4048 igb_free_all_tx_resources(adapter); 4049 igb_free_all_rx_resources(adapter); 4050 4051 if (!suspending) 4052 pm_runtime_put_sync(&pdev->dev); 4053 return 0; 4054 } 4055 4056 int igb_close(struct net_device *netdev) 4057 { 4058 if (netif_device_present(netdev) || netdev->dismantle) 4059 return __igb_close(netdev, false); 4060 return 0; 4061 } 4062 4063 /** 4064 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4065 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4066 * 4067 * Return 0 on success, negative on failure 4068 **/ 4069 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4070 { 4071 struct device *dev = tx_ring->dev; 4072 int size; 4073 4074 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4075 4076 tx_ring->tx_buffer_info = vmalloc(size); 4077 if (!tx_ring->tx_buffer_info) 4078 goto err; 4079 4080 /* round up to nearest 4K */ 4081 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4082 tx_ring->size = ALIGN(tx_ring->size, 4096); 4083 4084 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4085 &tx_ring->dma, GFP_KERNEL); 4086 if (!tx_ring->desc) 4087 goto err; 4088 4089 tx_ring->next_to_use = 0; 4090 tx_ring->next_to_clean = 0; 4091 4092 return 0; 4093 4094 err: 4095 vfree(tx_ring->tx_buffer_info); 4096 tx_ring->tx_buffer_info = NULL; 4097 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4098 return -ENOMEM; 4099 } 4100 4101 /** 4102 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4103 * (Descriptors) for all queues 4104 * @adapter: board private structure 4105 * 4106 * Return 0 on success, negative on failure 4107 **/ 4108 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4109 { 4110 struct pci_dev *pdev = adapter->pdev; 4111 int i, err = 0; 4112 4113 for (i = 0; i < adapter->num_tx_queues; i++) { 4114 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4115 if (err) { 4116 dev_err(&pdev->dev, 4117 "Allocation for Tx Queue %u failed\n", i); 4118 for (i--; i >= 0; i--) 4119 igb_free_tx_resources(adapter->tx_ring[i]); 4120 break; 4121 } 4122 } 4123 4124 return err; 4125 } 4126 4127 /** 4128 * igb_setup_tctl - configure the transmit control registers 4129 * @adapter: Board private structure 4130 **/ 4131 void igb_setup_tctl(struct igb_adapter *adapter) 4132 { 4133 struct e1000_hw *hw = &adapter->hw; 4134 u32 tctl; 4135 4136 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4137 wr32(E1000_TXDCTL(0), 0); 4138 4139 /* Program the Transmit Control Register */ 4140 tctl = rd32(E1000_TCTL); 4141 tctl &= ~E1000_TCTL_CT; 4142 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4143 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4144 4145 igb_config_collision_dist(hw); 4146 4147 /* Enable transmits */ 4148 tctl |= E1000_TCTL_EN; 4149 4150 wr32(E1000_TCTL, tctl); 4151 } 4152 4153 /** 4154 * igb_configure_tx_ring - Configure transmit ring after Reset 4155 * @adapter: board private structure 4156 * @ring: tx ring to configure 4157 * 4158 * Configure a transmit ring after a reset. 4159 **/ 4160 void igb_configure_tx_ring(struct igb_adapter *adapter, 4161 struct igb_ring *ring) 4162 { 4163 struct e1000_hw *hw = &adapter->hw; 4164 u32 txdctl = 0; 4165 u64 tdba = ring->dma; 4166 int reg_idx = ring->reg_idx; 4167 4168 wr32(E1000_TDLEN(reg_idx), 4169 ring->count * sizeof(union e1000_adv_tx_desc)); 4170 wr32(E1000_TDBAL(reg_idx), 4171 tdba & 0x00000000ffffffffULL); 4172 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4173 4174 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4175 wr32(E1000_TDH(reg_idx), 0); 4176 writel(0, ring->tail); 4177 4178 txdctl |= IGB_TX_PTHRESH; 4179 txdctl |= IGB_TX_HTHRESH << 8; 4180 txdctl |= IGB_TX_WTHRESH << 16; 4181 4182 /* reinitialize tx_buffer_info */ 4183 memset(ring->tx_buffer_info, 0, 4184 sizeof(struct igb_tx_buffer) * ring->count); 4185 4186 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4187 wr32(E1000_TXDCTL(reg_idx), txdctl); 4188 } 4189 4190 /** 4191 * igb_configure_tx - Configure transmit Unit after Reset 4192 * @adapter: board private structure 4193 * 4194 * Configure the Tx unit of the MAC after a reset. 4195 **/ 4196 static void igb_configure_tx(struct igb_adapter *adapter) 4197 { 4198 struct e1000_hw *hw = &adapter->hw; 4199 int i; 4200 4201 /* disable the queues */ 4202 for (i = 0; i < adapter->num_tx_queues; i++) 4203 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4204 4205 wrfl(); 4206 usleep_range(10000, 20000); 4207 4208 for (i = 0; i < adapter->num_tx_queues; i++) 4209 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4210 } 4211 4212 /** 4213 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4214 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4215 * 4216 * Returns 0 on success, negative on failure 4217 **/ 4218 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4219 { 4220 struct device *dev = rx_ring->dev; 4221 int size; 4222 4223 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4224 4225 rx_ring->rx_buffer_info = vmalloc(size); 4226 if (!rx_ring->rx_buffer_info) 4227 goto err; 4228 4229 /* Round up to nearest 4K */ 4230 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4231 rx_ring->size = ALIGN(rx_ring->size, 4096); 4232 4233 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4234 &rx_ring->dma, GFP_KERNEL); 4235 if (!rx_ring->desc) 4236 goto err; 4237 4238 rx_ring->next_to_alloc = 0; 4239 rx_ring->next_to_clean = 0; 4240 rx_ring->next_to_use = 0; 4241 4242 return 0; 4243 4244 err: 4245 vfree(rx_ring->rx_buffer_info); 4246 rx_ring->rx_buffer_info = NULL; 4247 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4248 return -ENOMEM; 4249 } 4250 4251 /** 4252 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4253 * (Descriptors) for all queues 4254 * @adapter: board private structure 4255 * 4256 * Return 0 on success, negative on failure 4257 **/ 4258 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4259 { 4260 struct pci_dev *pdev = adapter->pdev; 4261 int i, err = 0; 4262 4263 for (i = 0; i < adapter->num_rx_queues; i++) { 4264 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4265 if (err) { 4266 dev_err(&pdev->dev, 4267 "Allocation for Rx Queue %u failed\n", i); 4268 for (i--; i >= 0; i--) 4269 igb_free_rx_resources(adapter->rx_ring[i]); 4270 break; 4271 } 4272 } 4273 4274 return err; 4275 } 4276 4277 /** 4278 * igb_setup_mrqc - configure the multiple receive queue control registers 4279 * @adapter: Board private structure 4280 **/ 4281 static void igb_setup_mrqc(struct igb_adapter *adapter) 4282 { 4283 struct e1000_hw *hw = &adapter->hw; 4284 u32 mrqc, rxcsum; 4285 u32 j, num_rx_queues; 4286 u32 rss_key[10]; 4287 4288 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4289 for (j = 0; j < 10; j++) 4290 wr32(E1000_RSSRK(j), rss_key[j]); 4291 4292 num_rx_queues = adapter->rss_queues; 4293 4294 switch (hw->mac.type) { 4295 case e1000_82576: 4296 /* 82576 supports 2 RSS queues for SR-IOV */ 4297 if (adapter->vfs_allocated_count) 4298 num_rx_queues = 2; 4299 break; 4300 default: 4301 break; 4302 } 4303 4304 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4305 for (j = 0; j < IGB_RETA_SIZE; j++) 4306 adapter->rss_indir_tbl[j] = 4307 (j * num_rx_queues) / IGB_RETA_SIZE; 4308 adapter->rss_indir_tbl_init = num_rx_queues; 4309 } 4310 igb_write_rss_indir_tbl(adapter); 4311 4312 /* Disable raw packet checksumming so that RSS hash is placed in 4313 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4314 * offloads as they are enabled by default 4315 */ 4316 rxcsum = rd32(E1000_RXCSUM); 4317 rxcsum |= E1000_RXCSUM_PCSD; 4318 4319 if (adapter->hw.mac.type >= e1000_82576) 4320 /* Enable Receive Checksum Offload for SCTP */ 4321 rxcsum |= E1000_RXCSUM_CRCOFL; 4322 4323 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4324 wr32(E1000_RXCSUM, rxcsum); 4325 4326 /* Generate RSS hash based on packet types, TCP/UDP 4327 * port numbers and/or IPv4/v6 src and dst addresses 4328 */ 4329 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4330 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4331 E1000_MRQC_RSS_FIELD_IPV6 | 4332 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4333 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4334 4335 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4336 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4337 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4338 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4339 4340 /* If VMDq is enabled then we set the appropriate mode for that, else 4341 * we default to RSS so that an RSS hash is calculated per packet even 4342 * if we are only using one queue 4343 */ 4344 if (adapter->vfs_allocated_count) { 4345 if (hw->mac.type > e1000_82575) { 4346 /* Set the default pool for the PF's first queue */ 4347 u32 vtctl = rd32(E1000_VT_CTL); 4348 4349 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4350 E1000_VT_CTL_DISABLE_DEF_POOL); 4351 vtctl |= adapter->vfs_allocated_count << 4352 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4353 wr32(E1000_VT_CTL, vtctl); 4354 } 4355 if (adapter->rss_queues > 1) 4356 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4357 else 4358 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4359 } else { 4360 if (hw->mac.type != e1000_i211) 4361 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4362 } 4363 igb_vmm_control(adapter); 4364 4365 wr32(E1000_MRQC, mrqc); 4366 } 4367 4368 /** 4369 * igb_setup_rctl - configure the receive control registers 4370 * @adapter: Board private structure 4371 **/ 4372 void igb_setup_rctl(struct igb_adapter *adapter) 4373 { 4374 struct e1000_hw *hw = &adapter->hw; 4375 u32 rctl; 4376 4377 rctl = rd32(E1000_RCTL); 4378 4379 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4380 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4381 4382 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4383 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4384 4385 /* enable stripping of CRC. It's unlikely this will break BMC 4386 * redirection as it did with e1000. Newer features require 4387 * that the HW strips the CRC. 4388 */ 4389 rctl |= E1000_RCTL_SECRC; 4390 4391 /* disable store bad packets and clear size bits. */ 4392 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4393 4394 /* enable LPE to allow for reception of jumbo frames */ 4395 rctl |= E1000_RCTL_LPE; 4396 4397 /* disable queue 0 to prevent tail write w/o re-config */ 4398 wr32(E1000_RXDCTL(0), 0); 4399 4400 /* Attention!!! For SR-IOV PF driver operations you must enable 4401 * queue drop for all VF and PF queues to prevent head of line blocking 4402 * if an un-trusted VF does not provide descriptors to hardware. 4403 */ 4404 if (adapter->vfs_allocated_count) { 4405 /* set all queue drop enable bits */ 4406 wr32(E1000_QDE, ALL_QUEUES); 4407 } 4408 4409 /* This is useful for sniffing bad packets. */ 4410 if (adapter->netdev->features & NETIF_F_RXALL) { 4411 /* UPE and MPE will be handled by normal PROMISC logic 4412 * in e1000e_set_rx_mode 4413 */ 4414 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4415 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4416 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4417 4418 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4419 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4420 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4421 * and that breaks VLANs. 4422 */ 4423 } 4424 4425 wr32(E1000_RCTL, rctl); 4426 } 4427 4428 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4429 int vfn) 4430 { 4431 struct e1000_hw *hw = &adapter->hw; 4432 u32 vmolr; 4433 4434 if (size > MAX_JUMBO_FRAME_SIZE) 4435 size = MAX_JUMBO_FRAME_SIZE; 4436 4437 vmolr = rd32(E1000_VMOLR(vfn)); 4438 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4439 vmolr |= size | E1000_VMOLR_LPE; 4440 wr32(E1000_VMOLR(vfn), vmolr); 4441 4442 return 0; 4443 } 4444 4445 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4446 int vfn, bool enable) 4447 { 4448 struct e1000_hw *hw = &adapter->hw; 4449 u32 val, reg; 4450 4451 if (hw->mac.type < e1000_82576) 4452 return; 4453 4454 if (hw->mac.type == e1000_i350) 4455 reg = E1000_DVMOLR(vfn); 4456 else 4457 reg = E1000_VMOLR(vfn); 4458 4459 val = rd32(reg); 4460 if (enable) 4461 val |= E1000_VMOLR_STRVLAN; 4462 else 4463 val &= ~(E1000_VMOLR_STRVLAN); 4464 wr32(reg, val); 4465 } 4466 4467 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4468 int vfn, bool aupe) 4469 { 4470 struct e1000_hw *hw = &adapter->hw; 4471 u32 vmolr; 4472 4473 /* This register exists only on 82576 and newer so if we are older then 4474 * we should exit and do nothing 4475 */ 4476 if (hw->mac.type < e1000_82576) 4477 return; 4478 4479 vmolr = rd32(E1000_VMOLR(vfn)); 4480 if (aupe) 4481 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4482 else 4483 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4484 4485 /* clear all bits that might not be set */ 4486 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4487 4488 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4489 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4490 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4491 * multicast packets 4492 */ 4493 if (vfn <= adapter->vfs_allocated_count) 4494 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4495 4496 wr32(E1000_VMOLR(vfn), vmolr); 4497 } 4498 4499 /** 4500 * igb_configure_rx_ring - Configure a receive ring after Reset 4501 * @adapter: board private structure 4502 * @ring: receive ring to be configured 4503 * 4504 * Configure the Rx unit of the MAC after a reset. 4505 **/ 4506 void igb_configure_rx_ring(struct igb_adapter *adapter, 4507 struct igb_ring *ring) 4508 { 4509 struct e1000_hw *hw = &adapter->hw; 4510 union e1000_adv_rx_desc *rx_desc; 4511 u64 rdba = ring->dma; 4512 int reg_idx = ring->reg_idx; 4513 u32 srrctl = 0, rxdctl = 0; 4514 4515 /* disable the queue */ 4516 wr32(E1000_RXDCTL(reg_idx), 0); 4517 4518 /* Set DMA base address registers */ 4519 wr32(E1000_RDBAL(reg_idx), 4520 rdba & 0x00000000ffffffffULL); 4521 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4522 wr32(E1000_RDLEN(reg_idx), 4523 ring->count * sizeof(union e1000_adv_rx_desc)); 4524 4525 /* initialize head and tail */ 4526 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4527 wr32(E1000_RDH(reg_idx), 0); 4528 writel(0, ring->tail); 4529 4530 /* set descriptor configuration */ 4531 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4532 if (ring_uses_large_buffer(ring)) 4533 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4534 else 4535 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4536 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4537 if (hw->mac.type >= e1000_82580) 4538 srrctl |= E1000_SRRCTL_TIMESTAMP; 4539 /* Only set Drop Enable if we are supporting multiple queues */ 4540 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 4541 srrctl |= E1000_SRRCTL_DROP_EN; 4542 4543 wr32(E1000_SRRCTL(reg_idx), srrctl); 4544 4545 /* set filtering for VMDQ pools */ 4546 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4547 4548 rxdctl |= IGB_RX_PTHRESH; 4549 rxdctl |= IGB_RX_HTHRESH << 8; 4550 rxdctl |= IGB_RX_WTHRESH << 16; 4551 4552 /* initialize rx_buffer_info */ 4553 memset(ring->rx_buffer_info, 0, 4554 sizeof(struct igb_rx_buffer) * ring->count); 4555 4556 /* initialize Rx descriptor 0 */ 4557 rx_desc = IGB_RX_DESC(ring, 0); 4558 rx_desc->wb.upper.length = 0; 4559 4560 /* enable receive descriptor fetching */ 4561 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4562 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4563 } 4564 4565 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4566 struct igb_ring *rx_ring) 4567 { 4568 /* set build_skb and buffer size flags */ 4569 clear_ring_build_skb_enabled(rx_ring); 4570 clear_ring_uses_large_buffer(rx_ring); 4571 4572 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4573 return; 4574 4575 set_ring_build_skb_enabled(rx_ring); 4576 4577 #if (PAGE_SIZE < 8192) 4578 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4579 return; 4580 4581 set_ring_uses_large_buffer(rx_ring); 4582 #endif 4583 } 4584 4585 /** 4586 * igb_configure_rx - Configure receive Unit after Reset 4587 * @adapter: board private structure 4588 * 4589 * Configure the Rx unit of the MAC after a reset. 4590 **/ 4591 static void igb_configure_rx(struct igb_adapter *adapter) 4592 { 4593 int i; 4594 4595 /* set the correct pool for the PF default MAC address in entry 0 */ 4596 igb_set_default_mac_filter(adapter); 4597 4598 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4599 * the Base and Length of the Rx Descriptor Ring 4600 */ 4601 for (i = 0; i < adapter->num_rx_queues; i++) { 4602 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4603 4604 igb_set_rx_buffer_len(adapter, rx_ring); 4605 igb_configure_rx_ring(adapter, rx_ring); 4606 } 4607 } 4608 4609 /** 4610 * igb_free_tx_resources - Free Tx Resources per Queue 4611 * @tx_ring: Tx descriptor ring for a specific queue 4612 * 4613 * Free all transmit software resources 4614 **/ 4615 void igb_free_tx_resources(struct igb_ring *tx_ring) 4616 { 4617 igb_clean_tx_ring(tx_ring); 4618 4619 vfree(tx_ring->tx_buffer_info); 4620 tx_ring->tx_buffer_info = NULL; 4621 4622 /* if not set, then don't free */ 4623 if (!tx_ring->desc) 4624 return; 4625 4626 dma_free_coherent(tx_ring->dev, tx_ring->size, 4627 tx_ring->desc, tx_ring->dma); 4628 4629 tx_ring->desc = NULL; 4630 } 4631 4632 /** 4633 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4634 * @adapter: board private structure 4635 * 4636 * Free all transmit software resources 4637 **/ 4638 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4639 { 4640 int i; 4641 4642 for (i = 0; i < adapter->num_tx_queues; i++) 4643 if (adapter->tx_ring[i]) 4644 igb_free_tx_resources(adapter->tx_ring[i]); 4645 } 4646 4647 /** 4648 * igb_clean_tx_ring - Free Tx Buffers 4649 * @tx_ring: ring to be cleaned 4650 **/ 4651 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4652 { 4653 u16 i = tx_ring->next_to_clean; 4654 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4655 4656 while (i != tx_ring->next_to_use) { 4657 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4658 4659 /* Free all the Tx ring sk_buffs */ 4660 dev_kfree_skb_any(tx_buffer->skb); 4661 4662 /* unmap skb header data */ 4663 dma_unmap_single(tx_ring->dev, 4664 dma_unmap_addr(tx_buffer, dma), 4665 dma_unmap_len(tx_buffer, len), 4666 DMA_TO_DEVICE); 4667 4668 /* check for eop_desc to determine the end of the packet */ 4669 eop_desc = tx_buffer->next_to_watch; 4670 tx_desc = IGB_TX_DESC(tx_ring, i); 4671 4672 /* unmap remaining buffers */ 4673 while (tx_desc != eop_desc) { 4674 tx_buffer++; 4675 tx_desc++; 4676 i++; 4677 if (unlikely(i == tx_ring->count)) { 4678 i = 0; 4679 tx_buffer = tx_ring->tx_buffer_info; 4680 tx_desc = IGB_TX_DESC(tx_ring, 0); 4681 } 4682 4683 /* unmap any remaining paged data */ 4684 if (dma_unmap_len(tx_buffer, len)) 4685 dma_unmap_page(tx_ring->dev, 4686 dma_unmap_addr(tx_buffer, dma), 4687 dma_unmap_len(tx_buffer, len), 4688 DMA_TO_DEVICE); 4689 } 4690 4691 /* move us one more past the eop_desc for start of next pkt */ 4692 tx_buffer++; 4693 i++; 4694 if (unlikely(i == tx_ring->count)) { 4695 i = 0; 4696 tx_buffer = tx_ring->tx_buffer_info; 4697 } 4698 } 4699 4700 /* reset BQL for queue */ 4701 netdev_tx_reset_queue(txring_txq(tx_ring)); 4702 4703 /* reset next_to_use and next_to_clean */ 4704 tx_ring->next_to_use = 0; 4705 tx_ring->next_to_clean = 0; 4706 } 4707 4708 /** 4709 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4710 * @adapter: board private structure 4711 **/ 4712 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4713 { 4714 int i; 4715 4716 for (i = 0; i < adapter->num_tx_queues; i++) 4717 if (adapter->tx_ring[i]) 4718 igb_clean_tx_ring(adapter->tx_ring[i]); 4719 } 4720 4721 /** 4722 * igb_free_rx_resources - Free Rx Resources 4723 * @rx_ring: ring to clean the resources from 4724 * 4725 * Free all receive software resources 4726 **/ 4727 void igb_free_rx_resources(struct igb_ring *rx_ring) 4728 { 4729 igb_clean_rx_ring(rx_ring); 4730 4731 vfree(rx_ring->rx_buffer_info); 4732 rx_ring->rx_buffer_info = NULL; 4733 4734 /* if not set, then don't free */ 4735 if (!rx_ring->desc) 4736 return; 4737 4738 dma_free_coherent(rx_ring->dev, rx_ring->size, 4739 rx_ring->desc, rx_ring->dma); 4740 4741 rx_ring->desc = NULL; 4742 } 4743 4744 /** 4745 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4746 * @adapter: board private structure 4747 * 4748 * Free all receive software resources 4749 **/ 4750 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4751 { 4752 int i; 4753 4754 for (i = 0; i < adapter->num_rx_queues; i++) 4755 if (adapter->rx_ring[i]) 4756 igb_free_rx_resources(adapter->rx_ring[i]); 4757 } 4758 4759 /** 4760 * igb_clean_rx_ring - Free Rx Buffers per Queue 4761 * @rx_ring: ring to free buffers from 4762 **/ 4763 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4764 { 4765 u16 i = rx_ring->next_to_clean; 4766 4767 if (rx_ring->skb) 4768 dev_kfree_skb(rx_ring->skb); 4769 rx_ring->skb = NULL; 4770 4771 /* Free all the Rx ring sk_buffs */ 4772 while (i != rx_ring->next_to_alloc) { 4773 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4774 4775 /* Invalidate cache lines that may have been written to by 4776 * device so that we avoid corrupting memory. 4777 */ 4778 dma_sync_single_range_for_cpu(rx_ring->dev, 4779 buffer_info->dma, 4780 buffer_info->page_offset, 4781 igb_rx_bufsz(rx_ring), 4782 DMA_FROM_DEVICE); 4783 4784 /* free resources associated with mapping */ 4785 dma_unmap_page_attrs(rx_ring->dev, 4786 buffer_info->dma, 4787 igb_rx_pg_size(rx_ring), 4788 DMA_FROM_DEVICE, 4789 IGB_RX_DMA_ATTR); 4790 __page_frag_cache_drain(buffer_info->page, 4791 buffer_info->pagecnt_bias); 4792 4793 i++; 4794 if (i == rx_ring->count) 4795 i = 0; 4796 } 4797 4798 rx_ring->next_to_alloc = 0; 4799 rx_ring->next_to_clean = 0; 4800 rx_ring->next_to_use = 0; 4801 } 4802 4803 /** 4804 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4805 * @adapter: board private structure 4806 **/ 4807 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4808 { 4809 int i; 4810 4811 for (i = 0; i < adapter->num_rx_queues; i++) 4812 if (adapter->rx_ring[i]) 4813 igb_clean_rx_ring(adapter->rx_ring[i]); 4814 } 4815 4816 /** 4817 * igb_set_mac - Change the Ethernet Address of the NIC 4818 * @netdev: network interface device structure 4819 * @p: pointer to an address structure 4820 * 4821 * Returns 0 on success, negative on failure 4822 **/ 4823 static int igb_set_mac(struct net_device *netdev, void *p) 4824 { 4825 struct igb_adapter *adapter = netdev_priv(netdev); 4826 struct e1000_hw *hw = &adapter->hw; 4827 struct sockaddr *addr = p; 4828 4829 if (!is_valid_ether_addr(addr->sa_data)) 4830 return -EADDRNOTAVAIL; 4831 4832 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4833 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4834 4835 /* set the correct pool for the new PF MAC address in entry 0 */ 4836 igb_set_default_mac_filter(adapter); 4837 4838 return 0; 4839 } 4840 4841 /** 4842 * igb_write_mc_addr_list - write multicast addresses to MTA 4843 * @netdev: network interface device structure 4844 * 4845 * Writes multicast address list to the MTA hash table. 4846 * Returns: -ENOMEM on failure 4847 * 0 on no addresses written 4848 * X on writing X addresses to MTA 4849 **/ 4850 static int igb_write_mc_addr_list(struct net_device *netdev) 4851 { 4852 struct igb_adapter *adapter = netdev_priv(netdev); 4853 struct e1000_hw *hw = &adapter->hw; 4854 struct netdev_hw_addr *ha; 4855 u8 *mta_list; 4856 int i; 4857 4858 if (netdev_mc_empty(netdev)) { 4859 /* nothing to program, so clear mc list */ 4860 igb_update_mc_addr_list(hw, NULL, 0); 4861 igb_restore_vf_multicasts(adapter); 4862 return 0; 4863 } 4864 4865 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 4866 if (!mta_list) 4867 return -ENOMEM; 4868 4869 /* The shared function expects a packed array of only addresses. */ 4870 i = 0; 4871 netdev_for_each_mc_addr(ha, netdev) 4872 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4873 4874 igb_update_mc_addr_list(hw, mta_list, i); 4875 kfree(mta_list); 4876 4877 return netdev_mc_count(netdev); 4878 } 4879 4880 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4881 { 4882 struct e1000_hw *hw = &adapter->hw; 4883 u32 i, pf_id; 4884 4885 switch (hw->mac.type) { 4886 case e1000_i210: 4887 case e1000_i211: 4888 case e1000_i350: 4889 /* VLAN filtering needed for VLAN prio filter */ 4890 if (adapter->netdev->features & NETIF_F_NTUPLE) 4891 break; 4892 /* fall through */ 4893 case e1000_82576: 4894 case e1000_82580: 4895 case e1000_i354: 4896 /* VLAN filtering needed for pool filtering */ 4897 if (adapter->vfs_allocated_count) 4898 break; 4899 /* fall through */ 4900 default: 4901 return 1; 4902 } 4903 4904 /* We are already in VLAN promisc, nothing to do */ 4905 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4906 return 0; 4907 4908 if (!adapter->vfs_allocated_count) 4909 goto set_vfta; 4910 4911 /* Add PF to all active pools */ 4912 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4913 4914 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4915 u32 vlvf = rd32(E1000_VLVF(i)); 4916 4917 vlvf |= BIT(pf_id); 4918 wr32(E1000_VLVF(i), vlvf); 4919 } 4920 4921 set_vfta: 4922 /* Set all bits in the VLAN filter table array */ 4923 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4924 hw->mac.ops.write_vfta(hw, i, ~0U); 4925 4926 /* Set flag so we don't redo unnecessary work */ 4927 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4928 4929 return 0; 4930 } 4931 4932 #define VFTA_BLOCK_SIZE 8 4933 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4934 { 4935 struct e1000_hw *hw = &adapter->hw; 4936 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4937 u32 vid_start = vfta_offset * 32; 4938 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4939 u32 i, vid, word, bits, pf_id; 4940 4941 /* guarantee that we don't scrub out management VLAN */ 4942 vid = adapter->mng_vlan_id; 4943 if (vid >= vid_start && vid < vid_end) 4944 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4945 4946 if (!adapter->vfs_allocated_count) 4947 goto set_vfta; 4948 4949 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4950 4951 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4952 u32 vlvf = rd32(E1000_VLVF(i)); 4953 4954 /* pull VLAN ID from VLVF */ 4955 vid = vlvf & VLAN_VID_MASK; 4956 4957 /* only concern ourselves with a certain range */ 4958 if (vid < vid_start || vid >= vid_end) 4959 continue; 4960 4961 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4962 /* record VLAN ID in VFTA */ 4963 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4964 4965 /* if PF is part of this then continue */ 4966 if (test_bit(vid, adapter->active_vlans)) 4967 continue; 4968 } 4969 4970 /* remove PF from the pool */ 4971 bits = ~BIT(pf_id); 4972 bits &= rd32(E1000_VLVF(i)); 4973 wr32(E1000_VLVF(i), bits); 4974 } 4975 4976 set_vfta: 4977 /* extract values from active_vlans and write back to VFTA */ 4978 for (i = VFTA_BLOCK_SIZE; i--;) { 4979 vid = (vfta_offset + i) * 32; 4980 word = vid / BITS_PER_LONG; 4981 bits = vid % BITS_PER_LONG; 4982 4983 vfta[i] |= adapter->active_vlans[word] >> bits; 4984 4985 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4986 } 4987 } 4988 4989 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4990 { 4991 u32 i; 4992 4993 /* We are not in VLAN promisc, nothing to do */ 4994 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4995 return; 4996 4997 /* Set flag so we don't redo unnecessary work */ 4998 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4999 5000 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5001 igb_scrub_vfta(adapter, i); 5002 } 5003 5004 /** 5005 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5006 * @netdev: network interface device structure 5007 * 5008 * The set_rx_mode entry point is called whenever the unicast or multicast 5009 * address lists or the network interface flags are updated. This routine is 5010 * responsible for configuring the hardware for proper unicast, multicast, 5011 * promiscuous mode, and all-multi behavior. 5012 **/ 5013 static void igb_set_rx_mode(struct net_device *netdev) 5014 { 5015 struct igb_adapter *adapter = netdev_priv(netdev); 5016 struct e1000_hw *hw = &adapter->hw; 5017 unsigned int vfn = adapter->vfs_allocated_count; 5018 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5019 int count; 5020 5021 /* Check for Promiscuous and All Multicast modes */ 5022 if (netdev->flags & IFF_PROMISC) { 5023 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5024 vmolr |= E1000_VMOLR_MPME; 5025 5026 /* enable use of UTA filter to force packets to default pool */ 5027 if (hw->mac.type == e1000_82576) 5028 vmolr |= E1000_VMOLR_ROPE; 5029 } else { 5030 if (netdev->flags & IFF_ALLMULTI) { 5031 rctl |= E1000_RCTL_MPE; 5032 vmolr |= E1000_VMOLR_MPME; 5033 } else { 5034 /* Write addresses to the MTA, if the attempt fails 5035 * then we should just turn on promiscuous mode so 5036 * that we can at least receive multicast traffic 5037 */ 5038 count = igb_write_mc_addr_list(netdev); 5039 if (count < 0) { 5040 rctl |= E1000_RCTL_MPE; 5041 vmolr |= E1000_VMOLR_MPME; 5042 } else if (count) { 5043 vmolr |= E1000_VMOLR_ROMPE; 5044 } 5045 } 5046 } 5047 5048 /* Write addresses to available RAR registers, if there is not 5049 * sufficient space to store all the addresses then enable 5050 * unicast promiscuous mode 5051 */ 5052 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5053 rctl |= E1000_RCTL_UPE; 5054 vmolr |= E1000_VMOLR_ROPE; 5055 } 5056 5057 /* enable VLAN filtering by default */ 5058 rctl |= E1000_RCTL_VFE; 5059 5060 /* disable VLAN filtering for modes that require it */ 5061 if ((netdev->flags & IFF_PROMISC) || 5062 (netdev->features & NETIF_F_RXALL)) { 5063 /* if we fail to set all rules then just clear VFE */ 5064 if (igb_vlan_promisc_enable(adapter)) 5065 rctl &= ~E1000_RCTL_VFE; 5066 } else { 5067 igb_vlan_promisc_disable(adapter); 5068 } 5069 5070 /* update state of unicast, multicast, and VLAN filtering modes */ 5071 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5072 E1000_RCTL_VFE); 5073 wr32(E1000_RCTL, rctl); 5074 5075 #if (PAGE_SIZE < 8192) 5076 if (!adapter->vfs_allocated_count) { 5077 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5078 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5079 } 5080 #endif 5081 wr32(E1000_RLPML, rlpml); 5082 5083 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5084 * the VMOLR to enable the appropriate modes. Without this workaround 5085 * we will have issues with VLAN tag stripping not being done for frames 5086 * that are only arriving because we are the default pool 5087 */ 5088 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5089 return; 5090 5091 /* set UTA to appropriate mode */ 5092 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5093 5094 vmolr |= rd32(E1000_VMOLR(vfn)) & 5095 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5096 5097 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5098 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5099 #if (PAGE_SIZE < 8192) 5100 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5101 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5102 else 5103 #endif 5104 vmolr |= MAX_JUMBO_FRAME_SIZE; 5105 vmolr |= E1000_VMOLR_LPE; 5106 5107 wr32(E1000_VMOLR(vfn), vmolr); 5108 5109 igb_restore_vf_multicasts(adapter); 5110 } 5111 5112 static void igb_check_wvbr(struct igb_adapter *adapter) 5113 { 5114 struct e1000_hw *hw = &adapter->hw; 5115 u32 wvbr = 0; 5116 5117 switch (hw->mac.type) { 5118 case e1000_82576: 5119 case e1000_i350: 5120 wvbr = rd32(E1000_WVBR); 5121 if (!wvbr) 5122 return; 5123 break; 5124 default: 5125 break; 5126 } 5127 5128 adapter->wvbr |= wvbr; 5129 } 5130 5131 #define IGB_STAGGERED_QUEUE_OFFSET 8 5132 5133 static void igb_spoof_check(struct igb_adapter *adapter) 5134 { 5135 int j; 5136 5137 if (!adapter->wvbr) 5138 return; 5139 5140 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5141 if (adapter->wvbr & BIT(j) || 5142 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5143 dev_warn(&adapter->pdev->dev, 5144 "Spoof event(s) detected on VF %d\n", j); 5145 adapter->wvbr &= 5146 ~(BIT(j) | 5147 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5148 } 5149 } 5150 } 5151 5152 /* Need to wait a few seconds after link up to get diagnostic information from 5153 * the phy 5154 */ 5155 static void igb_update_phy_info(struct timer_list *t) 5156 { 5157 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5158 igb_get_phy_info(&adapter->hw); 5159 } 5160 5161 /** 5162 * igb_has_link - check shared code for link and determine up/down 5163 * @adapter: pointer to driver private info 5164 **/ 5165 bool igb_has_link(struct igb_adapter *adapter) 5166 { 5167 struct e1000_hw *hw = &adapter->hw; 5168 bool link_active = false; 5169 5170 /* get_link_status is set on LSC (link status) interrupt or 5171 * rx sequence error interrupt. get_link_status will stay 5172 * false until the e1000_check_for_link establishes link 5173 * for copper adapters ONLY 5174 */ 5175 switch (hw->phy.media_type) { 5176 case e1000_media_type_copper: 5177 if (!hw->mac.get_link_status) 5178 return true; 5179 case e1000_media_type_internal_serdes: 5180 hw->mac.ops.check_for_link(hw); 5181 link_active = !hw->mac.get_link_status; 5182 break; 5183 default: 5184 case e1000_media_type_unknown: 5185 break; 5186 } 5187 5188 if (((hw->mac.type == e1000_i210) || 5189 (hw->mac.type == e1000_i211)) && 5190 (hw->phy.id == I210_I_PHY_ID)) { 5191 if (!netif_carrier_ok(adapter->netdev)) { 5192 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5193 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5194 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5195 adapter->link_check_timeout = jiffies; 5196 } 5197 } 5198 5199 return link_active; 5200 } 5201 5202 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5203 { 5204 bool ret = false; 5205 u32 ctrl_ext, thstat; 5206 5207 /* check for thermal sensor event on i350 copper only */ 5208 if (hw->mac.type == e1000_i350) { 5209 thstat = rd32(E1000_THSTAT); 5210 ctrl_ext = rd32(E1000_CTRL_EXT); 5211 5212 if ((hw->phy.media_type == e1000_media_type_copper) && 5213 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5214 ret = !!(thstat & event); 5215 } 5216 5217 return ret; 5218 } 5219 5220 /** 5221 * igb_check_lvmmc - check for malformed packets received 5222 * and indicated in LVMMC register 5223 * @adapter: pointer to adapter 5224 **/ 5225 static void igb_check_lvmmc(struct igb_adapter *adapter) 5226 { 5227 struct e1000_hw *hw = &adapter->hw; 5228 u32 lvmmc; 5229 5230 lvmmc = rd32(E1000_LVMMC); 5231 if (lvmmc) { 5232 if (unlikely(net_ratelimit())) { 5233 netdev_warn(adapter->netdev, 5234 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5235 lvmmc); 5236 } 5237 } 5238 } 5239 5240 /** 5241 * igb_watchdog - Timer Call-back 5242 * @data: pointer to adapter cast into an unsigned long 5243 **/ 5244 static void igb_watchdog(struct timer_list *t) 5245 { 5246 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5247 /* Do the rest outside of interrupt context */ 5248 schedule_work(&adapter->watchdog_task); 5249 } 5250 5251 static void igb_watchdog_task(struct work_struct *work) 5252 { 5253 struct igb_adapter *adapter = container_of(work, 5254 struct igb_adapter, 5255 watchdog_task); 5256 struct e1000_hw *hw = &adapter->hw; 5257 struct e1000_phy_info *phy = &hw->phy; 5258 struct net_device *netdev = adapter->netdev; 5259 u32 link; 5260 int i; 5261 u32 connsw; 5262 u16 phy_data, retry_count = 20; 5263 5264 link = igb_has_link(adapter); 5265 5266 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5267 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5268 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5269 else 5270 link = false; 5271 } 5272 5273 /* Force link down if we have fiber to swap to */ 5274 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5275 if (hw->phy.media_type == e1000_media_type_copper) { 5276 connsw = rd32(E1000_CONNSW); 5277 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5278 link = 0; 5279 } 5280 } 5281 if (link) { 5282 /* Perform a reset if the media type changed. */ 5283 if (hw->dev_spec._82575.media_changed) { 5284 hw->dev_spec._82575.media_changed = false; 5285 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5286 igb_reset(adapter); 5287 } 5288 /* Cancel scheduled suspend requests. */ 5289 pm_runtime_resume(netdev->dev.parent); 5290 5291 if (!netif_carrier_ok(netdev)) { 5292 u32 ctrl; 5293 5294 hw->mac.ops.get_speed_and_duplex(hw, 5295 &adapter->link_speed, 5296 &adapter->link_duplex); 5297 5298 ctrl = rd32(E1000_CTRL); 5299 /* Links status message must follow this format */ 5300 netdev_info(netdev, 5301 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5302 netdev->name, 5303 adapter->link_speed, 5304 adapter->link_duplex == FULL_DUPLEX ? 5305 "Full" : "Half", 5306 (ctrl & E1000_CTRL_TFCE) && 5307 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5308 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5309 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5310 5311 /* disable EEE if enabled */ 5312 if ((adapter->flags & IGB_FLAG_EEE) && 5313 (adapter->link_duplex == HALF_DUPLEX)) { 5314 dev_info(&adapter->pdev->dev, 5315 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5316 adapter->hw.dev_spec._82575.eee_disable = true; 5317 adapter->flags &= ~IGB_FLAG_EEE; 5318 } 5319 5320 /* check if SmartSpeed worked */ 5321 igb_check_downshift(hw); 5322 if (phy->speed_downgraded) 5323 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5324 5325 /* check for thermal sensor event */ 5326 if (igb_thermal_sensor_event(hw, 5327 E1000_THSTAT_LINK_THROTTLE)) 5328 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5329 5330 /* adjust timeout factor according to speed/duplex */ 5331 adapter->tx_timeout_factor = 1; 5332 switch (adapter->link_speed) { 5333 case SPEED_10: 5334 adapter->tx_timeout_factor = 14; 5335 break; 5336 case SPEED_100: 5337 /* maybe add some timeout factor ? */ 5338 break; 5339 } 5340 5341 if (adapter->link_speed != SPEED_1000) 5342 goto no_wait; 5343 5344 /* wait for Remote receiver status OK */ 5345 retry_read_status: 5346 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5347 &phy_data)) { 5348 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5349 retry_count) { 5350 msleep(100); 5351 retry_count--; 5352 goto retry_read_status; 5353 } else if (!retry_count) { 5354 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5355 } 5356 } else { 5357 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5358 } 5359 no_wait: 5360 netif_carrier_on(netdev); 5361 5362 igb_ping_all_vfs(adapter); 5363 igb_check_vf_rate_limit(adapter); 5364 5365 /* link state has changed, schedule phy info update */ 5366 if (!test_bit(__IGB_DOWN, &adapter->state)) 5367 mod_timer(&adapter->phy_info_timer, 5368 round_jiffies(jiffies + 2 * HZ)); 5369 } 5370 } else { 5371 if (netif_carrier_ok(netdev)) { 5372 adapter->link_speed = 0; 5373 adapter->link_duplex = 0; 5374 5375 /* check for thermal sensor event */ 5376 if (igb_thermal_sensor_event(hw, 5377 E1000_THSTAT_PWR_DOWN)) { 5378 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5379 } 5380 5381 /* Links status message must follow this format */ 5382 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5383 netdev->name); 5384 netif_carrier_off(netdev); 5385 5386 igb_ping_all_vfs(adapter); 5387 5388 /* link state has changed, schedule phy info update */ 5389 if (!test_bit(__IGB_DOWN, &adapter->state)) 5390 mod_timer(&adapter->phy_info_timer, 5391 round_jiffies(jiffies + 2 * HZ)); 5392 5393 /* link is down, time to check for alternate media */ 5394 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5395 igb_check_swap_media(adapter); 5396 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5397 schedule_work(&adapter->reset_task); 5398 /* return immediately */ 5399 return; 5400 } 5401 } 5402 pm_schedule_suspend(netdev->dev.parent, 5403 MSEC_PER_SEC * 5); 5404 5405 /* also check for alternate media here */ 5406 } else if (!netif_carrier_ok(netdev) && 5407 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5408 igb_check_swap_media(adapter); 5409 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5410 schedule_work(&adapter->reset_task); 5411 /* return immediately */ 5412 return; 5413 } 5414 } 5415 } 5416 5417 spin_lock(&adapter->stats64_lock); 5418 igb_update_stats(adapter); 5419 spin_unlock(&adapter->stats64_lock); 5420 5421 for (i = 0; i < adapter->num_tx_queues; i++) { 5422 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5423 if (!netif_carrier_ok(netdev)) { 5424 /* We've lost link, so the controller stops DMA, 5425 * but we've got queued Tx work that's never going 5426 * to get done, so reset controller to flush Tx. 5427 * (Do the reset outside of interrupt context). 5428 */ 5429 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5430 adapter->tx_timeout_count++; 5431 schedule_work(&adapter->reset_task); 5432 /* return immediately since reset is imminent */ 5433 return; 5434 } 5435 } 5436 5437 /* Force detection of hung controller every watchdog period */ 5438 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5439 } 5440 5441 /* Cause software interrupt to ensure Rx ring is cleaned */ 5442 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5443 u32 eics = 0; 5444 5445 for (i = 0; i < adapter->num_q_vectors; i++) 5446 eics |= adapter->q_vector[i]->eims_value; 5447 wr32(E1000_EICS, eics); 5448 } else { 5449 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5450 } 5451 5452 igb_spoof_check(adapter); 5453 igb_ptp_rx_hang(adapter); 5454 igb_ptp_tx_hang(adapter); 5455 5456 /* Check LVMMC register on i350/i354 only */ 5457 if ((adapter->hw.mac.type == e1000_i350) || 5458 (adapter->hw.mac.type == e1000_i354)) 5459 igb_check_lvmmc(adapter); 5460 5461 /* Reset the timer */ 5462 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5463 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5464 mod_timer(&adapter->watchdog_timer, 5465 round_jiffies(jiffies + HZ)); 5466 else 5467 mod_timer(&adapter->watchdog_timer, 5468 round_jiffies(jiffies + 2 * HZ)); 5469 } 5470 } 5471 5472 enum latency_range { 5473 lowest_latency = 0, 5474 low_latency = 1, 5475 bulk_latency = 2, 5476 latency_invalid = 255 5477 }; 5478 5479 /** 5480 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5481 * @q_vector: pointer to q_vector 5482 * 5483 * Stores a new ITR value based on strictly on packet size. This 5484 * algorithm is less sophisticated than that used in igb_update_itr, 5485 * due to the difficulty of synchronizing statistics across multiple 5486 * receive rings. The divisors and thresholds used by this function 5487 * were determined based on theoretical maximum wire speed and testing 5488 * data, in order to minimize response time while increasing bulk 5489 * throughput. 5490 * This functionality is controlled by ethtool's coalescing settings. 5491 * NOTE: This function is called only when operating in a multiqueue 5492 * receive environment. 5493 **/ 5494 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5495 { 5496 int new_val = q_vector->itr_val; 5497 int avg_wire_size = 0; 5498 struct igb_adapter *adapter = q_vector->adapter; 5499 unsigned int packets; 5500 5501 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5502 * ints/sec - ITR timer value of 120 ticks. 5503 */ 5504 if (adapter->link_speed != SPEED_1000) { 5505 new_val = IGB_4K_ITR; 5506 goto set_itr_val; 5507 } 5508 5509 packets = q_vector->rx.total_packets; 5510 if (packets) 5511 avg_wire_size = q_vector->rx.total_bytes / packets; 5512 5513 packets = q_vector->tx.total_packets; 5514 if (packets) 5515 avg_wire_size = max_t(u32, avg_wire_size, 5516 q_vector->tx.total_bytes / packets); 5517 5518 /* if avg_wire_size isn't set no work was done */ 5519 if (!avg_wire_size) 5520 goto clear_counts; 5521 5522 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5523 avg_wire_size += 24; 5524 5525 /* Don't starve jumbo frames */ 5526 avg_wire_size = min(avg_wire_size, 3000); 5527 5528 /* Give a little boost to mid-size frames */ 5529 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5530 new_val = avg_wire_size / 3; 5531 else 5532 new_val = avg_wire_size / 2; 5533 5534 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5535 if (new_val < IGB_20K_ITR && 5536 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5537 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5538 new_val = IGB_20K_ITR; 5539 5540 set_itr_val: 5541 if (new_val != q_vector->itr_val) { 5542 q_vector->itr_val = new_val; 5543 q_vector->set_itr = 1; 5544 } 5545 clear_counts: 5546 q_vector->rx.total_bytes = 0; 5547 q_vector->rx.total_packets = 0; 5548 q_vector->tx.total_bytes = 0; 5549 q_vector->tx.total_packets = 0; 5550 } 5551 5552 /** 5553 * igb_update_itr - update the dynamic ITR value based on statistics 5554 * @q_vector: pointer to q_vector 5555 * @ring_container: ring info to update the itr for 5556 * 5557 * Stores a new ITR value based on packets and byte 5558 * counts during the last interrupt. The advantage of per interrupt 5559 * computation is faster updates and more accurate ITR for the current 5560 * traffic pattern. Constants in this function were computed 5561 * based on theoretical maximum wire speed and thresholds were set based 5562 * on testing data as well as attempting to minimize response time 5563 * while increasing bulk throughput. 5564 * This functionality is controlled by ethtool's coalescing settings. 5565 * NOTE: These calculations are only valid when operating in a single- 5566 * queue environment. 5567 **/ 5568 static void igb_update_itr(struct igb_q_vector *q_vector, 5569 struct igb_ring_container *ring_container) 5570 { 5571 unsigned int packets = ring_container->total_packets; 5572 unsigned int bytes = ring_container->total_bytes; 5573 u8 itrval = ring_container->itr; 5574 5575 /* no packets, exit with status unchanged */ 5576 if (packets == 0) 5577 return; 5578 5579 switch (itrval) { 5580 case lowest_latency: 5581 /* handle TSO and jumbo frames */ 5582 if (bytes/packets > 8000) 5583 itrval = bulk_latency; 5584 else if ((packets < 5) && (bytes > 512)) 5585 itrval = low_latency; 5586 break; 5587 case low_latency: /* 50 usec aka 20000 ints/s */ 5588 if (bytes > 10000) { 5589 /* this if handles the TSO accounting */ 5590 if (bytes/packets > 8000) 5591 itrval = bulk_latency; 5592 else if ((packets < 10) || ((bytes/packets) > 1200)) 5593 itrval = bulk_latency; 5594 else if ((packets > 35)) 5595 itrval = lowest_latency; 5596 } else if (bytes/packets > 2000) { 5597 itrval = bulk_latency; 5598 } else if (packets <= 2 && bytes < 512) { 5599 itrval = lowest_latency; 5600 } 5601 break; 5602 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5603 if (bytes > 25000) { 5604 if (packets > 35) 5605 itrval = low_latency; 5606 } else if (bytes < 1500) { 5607 itrval = low_latency; 5608 } 5609 break; 5610 } 5611 5612 /* clear work counters since we have the values we need */ 5613 ring_container->total_bytes = 0; 5614 ring_container->total_packets = 0; 5615 5616 /* write updated itr to ring container */ 5617 ring_container->itr = itrval; 5618 } 5619 5620 static void igb_set_itr(struct igb_q_vector *q_vector) 5621 { 5622 struct igb_adapter *adapter = q_vector->adapter; 5623 u32 new_itr = q_vector->itr_val; 5624 u8 current_itr = 0; 5625 5626 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5627 if (adapter->link_speed != SPEED_1000) { 5628 current_itr = 0; 5629 new_itr = IGB_4K_ITR; 5630 goto set_itr_now; 5631 } 5632 5633 igb_update_itr(q_vector, &q_vector->tx); 5634 igb_update_itr(q_vector, &q_vector->rx); 5635 5636 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5637 5638 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5639 if (current_itr == lowest_latency && 5640 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5641 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5642 current_itr = low_latency; 5643 5644 switch (current_itr) { 5645 /* counts and packets in update_itr are dependent on these numbers */ 5646 case lowest_latency: 5647 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5648 break; 5649 case low_latency: 5650 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5651 break; 5652 case bulk_latency: 5653 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5654 break; 5655 default: 5656 break; 5657 } 5658 5659 set_itr_now: 5660 if (new_itr != q_vector->itr_val) { 5661 /* this attempts to bias the interrupt rate towards Bulk 5662 * by adding intermediate steps when interrupt rate is 5663 * increasing 5664 */ 5665 new_itr = new_itr > q_vector->itr_val ? 5666 max((new_itr * q_vector->itr_val) / 5667 (new_itr + (q_vector->itr_val >> 2)), 5668 new_itr) : new_itr; 5669 /* Don't write the value here; it resets the adapter's 5670 * internal timer, and causes us to delay far longer than 5671 * we should between interrupts. Instead, we write the ITR 5672 * value at the beginning of the next interrupt so the timing 5673 * ends up being correct. 5674 */ 5675 q_vector->itr_val = new_itr; 5676 q_vector->set_itr = 1; 5677 } 5678 } 5679 5680 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5681 struct igb_tx_buffer *first, 5682 u32 vlan_macip_lens, u32 type_tucmd, 5683 u32 mss_l4len_idx) 5684 { 5685 struct e1000_adv_tx_context_desc *context_desc; 5686 u16 i = tx_ring->next_to_use; 5687 struct timespec64 ts; 5688 5689 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5690 5691 i++; 5692 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5693 5694 /* set bits to identify this as an advanced context descriptor */ 5695 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5696 5697 /* For 82575, context index must be unique per ring. */ 5698 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5699 mss_l4len_idx |= tx_ring->reg_idx << 4; 5700 5701 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5702 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5703 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5704 5705 /* We assume there is always a valid tx time available. Invalid times 5706 * should have been handled by the upper layers. 5707 */ 5708 if (tx_ring->launchtime_enable) { 5709 ts = ns_to_timespec64(first->skb->tstamp); 5710 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5711 } else { 5712 context_desc->seqnum_seed = 0; 5713 } 5714 } 5715 5716 static int igb_tso(struct igb_ring *tx_ring, 5717 struct igb_tx_buffer *first, 5718 u8 *hdr_len) 5719 { 5720 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5721 struct sk_buff *skb = first->skb; 5722 union { 5723 struct iphdr *v4; 5724 struct ipv6hdr *v6; 5725 unsigned char *hdr; 5726 } ip; 5727 union { 5728 struct tcphdr *tcp; 5729 unsigned char *hdr; 5730 } l4; 5731 u32 paylen, l4_offset; 5732 int err; 5733 5734 if (skb->ip_summed != CHECKSUM_PARTIAL) 5735 return 0; 5736 5737 if (!skb_is_gso(skb)) 5738 return 0; 5739 5740 err = skb_cow_head(skb, 0); 5741 if (err < 0) 5742 return err; 5743 5744 ip.hdr = skb_network_header(skb); 5745 l4.hdr = skb_checksum_start(skb); 5746 5747 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5748 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5749 5750 /* initialize outer IP header fields */ 5751 if (ip.v4->version == 4) { 5752 unsigned char *csum_start = skb_checksum_start(skb); 5753 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5754 5755 /* IP header will have to cancel out any data that 5756 * is not a part of the outer IP header 5757 */ 5758 ip.v4->check = csum_fold(csum_partial(trans_start, 5759 csum_start - trans_start, 5760 0)); 5761 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5762 5763 ip.v4->tot_len = 0; 5764 first->tx_flags |= IGB_TX_FLAGS_TSO | 5765 IGB_TX_FLAGS_CSUM | 5766 IGB_TX_FLAGS_IPV4; 5767 } else { 5768 ip.v6->payload_len = 0; 5769 first->tx_flags |= IGB_TX_FLAGS_TSO | 5770 IGB_TX_FLAGS_CSUM; 5771 } 5772 5773 /* determine offset of inner transport header */ 5774 l4_offset = l4.hdr - skb->data; 5775 5776 /* compute length of segmentation header */ 5777 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5778 5779 /* remove payload length from inner checksum */ 5780 paylen = skb->len - l4_offset; 5781 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5782 5783 /* update gso size and bytecount with header size */ 5784 first->gso_segs = skb_shinfo(skb)->gso_segs; 5785 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5786 5787 /* MSS L4LEN IDX */ 5788 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5789 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5790 5791 /* VLAN MACLEN IPLEN */ 5792 vlan_macip_lens = l4.hdr - ip.hdr; 5793 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5794 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5795 5796 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5797 type_tucmd, mss_l4len_idx); 5798 5799 return 1; 5800 } 5801 5802 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5803 { 5804 unsigned int offset = 0; 5805 5806 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5807 5808 return offset == skb_checksum_start_offset(skb); 5809 } 5810 5811 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5812 { 5813 struct sk_buff *skb = first->skb; 5814 u32 vlan_macip_lens = 0; 5815 u32 type_tucmd = 0; 5816 5817 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5818 csum_failed: 5819 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5820 return; 5821 goto no_csum; 5822 } 5823 5824 switch (skb->csum_offset) { 5825 case offsetof(struct tcphdr, check): 5826 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5827 /* fall through */ 5828 case offsetof(struct udphdr, check): 5829 break; 5830 case offsetof(struct sctphdr, checksum): 5831 /* validate that this is actually an SCTP request */ 5832 if (((first->protocol == htons(ETH_P_IP)) && 5833 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5834 ((first->protocol == htons(ETH_P_IPV6)) && 5835 igb_ipv6_csum_is_sctp(skb))) { 5836 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5837 break; 5838 } 5839 default: 5840 skb_checksum_help(skb); 5841 goto csum_failed; 5842 } 5843 5844 /* update TX checksum flag */ 5845 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5846 vlan_macip_lens = skb_checksum_start_offset(skb) - 5847 skb_network_offset(skb); 5848 no_csum: 5849 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5850 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5851 5852 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 5853 } 5854 5855 #define IGB_SET_FLAG(_input, _flag, _result) \ 5856 ((_flag <= _result) ? \ 5857 ((u32)(_input & _flag) * (_result / _flag)) : \ 5858 ((u32)(_input & _flag) / (_flag / _result))) 5859 5860 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5861 { 5862 /* set type for advanced descriptor with frame checksum insertion */ 5863 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5864 E1000_ADVTXD_DCMD_DEXT | 5865 E1000_ADVTXD_DCMD_IFCS; 5866 5867 /* set HW vlan bit if vlan is present */ 5868 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5869 (E1000_ADVTXD_DCMD_VLE)); 5870 5871 /* set segmentation bits for TSO */ 5872 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5873 (E1000_ADVTXD_DCMD_TSE)); 5874 5875 /* set timestamp bit if present */ 5876 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5877 (E1000_ADVTXD_MAC_TSTAMP)); 5878 5879 /* insert frame checksum */ 5880 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5881 5882 return cmd_type; 5883 } 5884 5885 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5886 union e1000_adv_tx_desc *tx_desc, 5887 u32 tx_flags, unsigned int paylen) 5888 { 5889 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5890 5891 /* 82575 requires a unique index per ring */ 5892 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5893 olinfo_status |= tx_ring->reg_idx << 4; 5894 5895 /* insert L4 checksum */ 5896 olinfo_status |= IGB_SET_FLAG(tx_flags, 5897 IGB_TX_FLAGS_CSUM, 5898 (E1000_TXD_POPTS_TXSM << 8)); 5899 5900 /* insert IPv4 checksum */ 5901 olinfo_status |= IGB_SET_FLAG(tx_flags, 5902 IGB_TX_FLAGS_IPV4, 5903 (E1000_TXD_POPTS_IXSM << 8)); 5904 5905 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5906 } 5907 5908 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5909 { 5910 struct net_device *netdev = tx_ring->netdev; 5911 5912 netif_stop_subqueue(netdev, tx_ring->queue_index); 5913 5914 /* Herbert's original patch had: 5915 * smp_mb__after_netif_stop_queue(); 5916 * but since that doesn't exist yet, just open code it. 5917 */ 5918 smp_mb(); 5919 5920 /* We need to check again in a case another CPU has just 5921 * made room available. 5922 */ 5923 if (igb_desc_unused(tx_ring) < size) 5924 return -EBUSY; 5925 5926 /* A reprieve! */ 5927 netif_wake_subqueue(netdev, tx_ring->queue_index); 5928 5929 u64_stats_update_begin(&tx_ring->tx_syncp2); 5930 tx_ring->tx_stats.restart_queue2++; 5931 u64_stats_update_end(&tx_ring->tx_syncp2); 5932 5933 return 0; 5934 } 5935 5936 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5937 { 5938 if (igb_desc_unused(tx_ring) >= size) 5939 return 0; 5940 return __igb_maybe_stop_tx(tx_ring, size); 5941 } 5942 5943 static int igb_tx_map(struct igb_ring *tx_ring, 5944 struct igb_tx_buffer *first, 5945 const u8 hdr_len) 5946 { 5947 struct sk_buff *skb = first->skb; 5948 struct igb_tx_buffer *tx_buffer; 5949 union e1000_adv_tx_desc *tx_desc; 5950 struct skb_frag_struct *frag; 5951 dma_addr_t dma; 5952 unsigned int data_len, size; 5953 u32 tx_flags = first->tx_flags; 5954 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5955 u16 i = tx_ring->next_to_use; 5956 5957 tx_desc = IGB_TX_DESC(tx_ring, i); 5958 5959 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5960 5961 size = skb_headlen(skb); 5962 data_len = skb->data_len; 5963 5964 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5965 5966 tx_buffer = first; 5967 5968 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5969 if (dma_mapping_error(tx_ring->dev, dma)) 5970 goto dma_error; 5971 5972 /* record length, and DMA address */ 5973 dma_unmap_len_set(tx_buffer, len, size); 5974 dma_unmap_addr_set(tx_buffer, dma, dma); 5975 5976 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5977 5978 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5979 tx_desc->read.cmd_type_len = 5980 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5981 5982 i++; 5983 tx_desc++; 5984 if (i == tx_ring->count) { 5985 tx_desc = IGB_TX_DESC(tx_ring, 0); 5986 i = 0; 5987 } 5988 tx_desc->read.olinfo_status = 0; 5989 5990 dma += IGB_MAX_DATA_PER_TXD; 5991 size -= IGB_MAX_DATA_PER_TXD; 5992 5993 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5994 } 5995 5996 if (likely(!data_len)) 5997 break; 5998 5999 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6000 6001 i++; 6002 tx_desc++; 6003 if (i == tx_ring->count) { 6004 tx_desc = IGB_TX_DESC(tx_ring, 0); 6005 i = 0; 6006 } 6007 tx_desc->read.olinfo_status = 0; 6008 6009 size = skb_frag_size(frag); 6010 data_len -= size; 6011 6012 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6013 size, DMA_TO_DEVICE); 6014 6015 tx_buffer = &tx_ring->tx_buffer_info[i]; 6016 } 6017 6018 /* write last descriptor with RS and EOP bits */ 6019 cmd_type |= size | IGB_TXD_DCMD; 6020 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6021 6022 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6023 6024 /* set the timestamp */ 6025 first->time_stamp = jiffies; 6026 6027 /* Force memory writes to complete before letting h/w know there 6028 * are new descriptors to fetch. (Only applicable for weak-ordered 6029 * memory model archs, such as IA-64). 6030 * 6031 * We also need this memory barrier to make certain all of the 6032 * status bits have been updated before next_to_watch is written. 6033 */ 6034 wmb(); 6035 6036 /* set next_to_watch value indicating a packet is present */ 6037 first->next_to_watch = tx_desc; 6038 6039 i++; 6040 if (i == tx_ring->count) 6041 i = 0; 6042 6043 tx_ring->next_to_use = i; 6044 6045 /* Make sure there is space in the ring for the next send. */ 6046 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6047 6048 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 6049 writel(i, tx_ring->tail); 6050 6051 /* we need this if more than one processor can write to our tail 6052 * at a time, it synchronizes IO on IA64/Altix systems 6053 */ 6054 mmiowb(); 6055 } 6056 return 0; 6057 6058 dma_error: 6059 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6060 tx_buffer = &tx_ring->tx_buffer_info[i]; 6061 6062 /* clear dma mappings for failed tx_buffer_info map */ 6063 while (tx_buffer != first) { 6064 if (dma_unmap_len(tx_buffer, len)) 6065 dma_unmap_page(tx_ring->dev, 6066 dma_unmap_addr(tx_buffer, dma), 6067 dma_unmap_len(tx_buffer, len), 6068 DMA_TO_DEVICE); 6069 dma_unmap_len_set(tx_buffer, len, 0); 6070 6071 if (i-- == 0) 6072 i += tx_ring->count; 6073 tx_buffer = &tx_ring->tx_buffer_info[i]; 6074 } 6075 6076 if (dma_unmap_len(tx_buffer, len)) 6077 dma_unmap_single(tx_ring->dev, 6078 dma_unmap_addr(tx_buffer, dma), 6079 dma_unmap_len(tx_buffer, len), 6080 DMA_TO_DEVICE); 6081 dma_unmap_len_set(tx_buffer, len, 0); 6082 6083 dev_kfree_skb_any(tx_buffer->skb); 6084 tx_buffer->skb = NULL; 6085 6086 tx_ring->next_to_use = i; 6087 6088 return -1; 6089 } 6090 6091 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6092 struct igb_ring *tx_ring) 6093 { 6094 struct igb_tx_buffer *first; 6095 int tso; 6096 u32 tx_flags = 0; 6097 unsigned short f; 6098 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6099 __be16 protocol = vlan_get_protocol(skb); 6100 u8 hdr_len = 0; 6101 6102 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6103 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6104 * + 2 desc gap to keep tail from touching head, 6105 * + 1 desc for context descriptor, 6106 * otherwise try next time 6107 */ 6108 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6109 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 6110 6111 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6112 /* this is a hard error */ 6113 return NETDEV_TX_BUSY; 6114 } 6115 6116 /* record the location of the first descriptor for this packet */ 6117 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6118 first->skb = skb; 6119 first->bytecount = skb->len; 6120 first->gso_segs = 1; 6121 6122 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6123 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6124 6125 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6126 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6127 &adapter->state)) { 6128 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6129 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6130 6131 adapter->ptp_tx_skb = skb_get(skb); 6132 adapter->ptp_tx_start = jiffies; 6133 if (adapter->hw.mac.type == e1000_82576) 6134 schedule_work(&adapter->ptp_tx_work); 6135 } else { 6136 adapter->tx_hwtstamp_skipped++; 6137 } 6138 } 6139 6140 if (skb_vlan_tag_present(skb)) { 6141 tx_flags |= IGB_TX_FLAGS_VLAN; 6142 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6143 } 6144 6145 /* record initial flags and protocol */ 6146 first->tx_flags = tx_flags; 6147 first->protocol = protocol; 6148 6149 tso = igb_tso(tx_ring, first, &hdr_len); 6150 if (tso < 0) 6151 goto out_drop; 6152 else if (!tso) 6153 igb_tx_csum(tx_ring, first); 6154 6155 skb_tx_timestamp(skb); 6156 6157 if (igb_tx_map(tx_ring, first, hdr_len)) 6158 goto cleanup_tx_tstamp; 6159 6160 return NETDEV_TX_OK; 6161 6162 out_drop: 6163 dev_kfree_skb_any(first->skb); 6164 first->skb = NULL; 6165 cleanup_tx_tstamp: 6166 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6167 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6168 6169 dev_kfree_skb_any(adapter->ptp_tx_skb); 6170 adapter->ptp_tx_skb = NULL; 6171 if (adapter->hw.mac.type == e1000_82576) 6172 cancel_work_sync(&adapter->ptp_tx_work); 6173 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6174 } 6175 6176 return NETDEV_TX_OK; 6177 } 6178 6179 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6180 struct sk_buff *skb) 6181 { 6182 unsigned int r_idx = skb->queue_mapping; 6183 6184 if (r_idx >= adapter->num_tx_queues) 6185 r_idx = r_idx % adapter->num_tx_queues; 6186 6187 return adapter->tx_ring[r_idx]; 6188 } 6189 6190 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6191 struct net_device *netdev) 6192 { 6193 struct igb_adapter *adapter = netdev_priv(netdev); 6194 6195 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6196 * in order to meet this minimum size requirement. 6197 */ 6198 if (skb_put_padto(skb, 17)) 6199 return NETDEV_TX_OK; 6200 6201 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6202 } 6203 6204 /** 6205 * igb_tx_timeout - Respond to a Tx Hang 6206 * @netdev: network interface device structure 6207 **/ 6208 static void igb_tx_timeout(struct net_device *netdev) 6209 { 6210 struct igb_adapter *adapter = netdev_priv(netdev); 6211 struct e1000_hw *hw = &adapter->hw; 6212 6213 /* Do the reset outside of interrupt context */ 6214 adapter->tx_timeout_count++; 6215 6216 if (hw->mac.type >= e1000_82580) 6217 hw->dev_spec._82575.global_device_reset = true; 6218 6219 schedule_work(&adapter->reset_task); 6220 wr32(E1000_EICS, 6221 (adapter->eims_enable_mask & ~adapter->eims_other)); 6222 } 6223 6224 static void igb_reset_task(struct work_struct *work) 6225 { 6226 struct igb_adapter *adapter; 6227 adapter = container_of(work, struct igb_adapter, reset_task); 6228 6229 igb_dump(adapter); 6230 netdev_err(adapter->netdev, "Reset adapter\n"); 6231 igb_reinit_locked(adapter); 6232 } 6233 6234 /** 6235 * igb_get_stats64 - Get System Network Statistics 6236 * @netdev: network interface device structure 6237 * @stats: rtnl_link_stats64 pointer 6238 **/ 6239 static void igb_get_stats64(struct net_device *netdev, 6240 struct rtnl_link_stats64 *stats) 6241 { 6242 struct igb_adapter *adapter = netdev_priv(netdev); 6243 6244 spin_lock(&adapter->stats64_lock); 6245 igb_update_stats(adapter); 6246 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6247 spin_unlock(&adapter->stats64_lock); 6248 } 6249 6250 /** 6251 * igb_change_mtu - Change the Maximum Transfer Unit 6252 * @netdev: network interface device structure 6253 * @new_mtu: new value for maximum frame size 6254 * 6255 * Returns 0 on success, negative on failure 6256 **/ 6257 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6258 { 6259 struct igb_adapter *adapter = netdev_priv(netdev); 6260 struct pci_dev *pdev = adapter->pdev; 6261 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6262 6263 /* adjust max frame to be at least the size of a standard frame */ 6264 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6265 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6266 6267 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6268 usleep_range(1000, 2000); 6269 6270 /* igb_down has a dependency on max_frame_size */ 6271 adapter->max_frame_size = max_frame; 6272 6273 if (netif_running(netdev)) 6274 igb_down(adapter); 6275 6276 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 6277 netdev->mtu, new_mtu); 6278 netdev->mtu = new_mtu; 6279 6280 if (netif_running(netdev)) 6281 igb_up(adapter); 6282 else 6283 igb_reset(adapter); 6284 6285 clear_bit(__IGB_RESETTING, &adapter->state); 6286 6287 return 0; 6288 } 6289 6290 /** 6291 * igb_update_stats - Update the board statistics counters 6292 * @adapter: board private structure 6293 **/ 6294 void igb_update_stats(struct igb_adapter *adapter) 6295 { 6296 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6297 struct e1000_hw *hw = &adapter->hw; 6298 struct pci_dev *pdev = adapter->pdev; 6299 u32 reg, mpc; 6300 int i; 6301 u64 bytes, packets; 6302 unsigned int start; 6303 u64 _bytes, _packets; 6304 6305 /* Prevent stats update while adapter is being reset, or if the pci 6306 * connection is down. 6307 */ 6308 if (adapter->link_speed == 0) 6309 return; 6310 if (pci_channel_offline(pdev)) 6311 return; 6312 6313 bytes = 0; 6314 packets = 0; 6315 6316 rcu_read_lock(); 6317 for (i = 0; i < adapter->num_rx_queues; i++) { 6318 struct igb_ring *ring = adapter->rx_ring[i]; 6319 u32 rqdpc = rd32(E1000_RQDPC(i)); 6320 if (hw->mac.type >= e1000_i210) 6321 wr32(E1000_RQDPC(i), 0); 6322 6323 if (rqdpc) { 6324 ring->rx_stats.drops += rqdpc; 6325 net_stats->rx_fifo_errors += rqdpc; 6326 } 6327 6328 do { 6329 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6330 _bytes = ring->rx_stats.bytes; 6331 _packets = ring->rx_stats.packets; 6332 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6333 bytes += _bytes; 6334 packets += _packets; 6335 } 6336 6337 net_stats->rx_bytes = bytes; 6338 net_stats->rx_packets = packets; 6339 6340 bytes = 0; 6341 packets = 0; 6342 for (i = 0; i < adapter->num_tx_queues; i++) { 6343 struct igb_ring *ring = adapter->tx_ring[i]; 6344 do { 6345 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6346 _bytes = ring->tx_stats.bytes; 6347 _packets = ring->tx_stats.packets; 6348 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6349 bytes += _bytes; 6350 packets += _packets; 6351 } 6352 net_stats->tx_bytes = bytes; 6353 net_stats->tx_packets = packets; 6354 rcu_read_unlock(); 6355 6356 /* read stats registers */ 6357 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6358 adapter->stats.gprc += rd32(E1000_GPRC); 6359 adapter->stats.gorc += rd32(E1000_GORCL); 6360 rd32(E1000_GORCH); /* clear GORCL */ 6361 adapter->stats.bprc += rd32(E1000_BPRC); 6362 adapter->stats.mprc += rd32(E1000_MPRC); 6363 adapter->stats.roc += rd32(E1000_ROC); 6364 6365 adapter->stats.prc64 += rd32(E1000_PRC64); 6366 adapter->stats.prc127 += rd32(E1000_PRC127); 6367 adapter->stats.prc255 += rd32(E1000_PRC255); 6368 adapter->stats.prc511 += rd32(E1000_PRC511); 6369 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6370 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6371 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6372 adapter->stats.sec += rd32(E1000_SEC); 6373 6374 mpc = rd32(E1000_MPC); 6375 adapter->stats.mpc += mpc; 6376 net_stats->rx_fifo_errors += mpc; 6377 adapter->stats.scc += rd32(E1000_SCC); 6378 adapter->stats.ecol += rd32(E1000_ECOL); 6379 adapter->stats.mcc += rd32(E1000_MCC); 6380 adapter->stats.latecol += rd32(E1000_LATECOL); 6381 adapter->stats.dc += rd32(E1000_DC); 6382 adapter->stats.rlec += rd32(E1000_RLEC); 6383 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6384 adapter->stats.xontxc += rd32(E1000_XONTXC); 6385 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6386 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6387 adapter->stats.fcruc += rd32(E1000_FCRUC); 6388 adapter->stats.gptc += rd32(E1000_GPTC); 6389 adapter->stats.gotc += rd32(E1000_GOTCL); 6390 rd32(E1000_GOTCH); /* clear GOTCL */ 6391 adapter->stats.rnbc += rd32(E1000_RNBC); 6392 adapter->stats.ruc += rd32(E1000_RUC); 6393 adapter->stats.rfc += rd32(E1000_RFC); 6394 adapter->stats.rjc += rd32(E1000_RJC); 6395 adapter->stats.tor += rd32(E1000_TORH); 6396 adapter->stats.tot += rd32(E1000_TOTH); 6397 adapter->stats.tpr += rd32(E1000_TPR); 6398 6399 adapter->stats.ptc64 += rd32(E1000_PTC64); 6400 adapter->stats.ptc127 += rd32(E1000_PTC127); 6401 adapter->stats.ptc255 += rd32(E1000_PTC255); 6402 adapter->stats.ptc511 += rd32(E1000_PTC511); 6403 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6404 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6405 6406 adapter->stats.mptc += rd32(E1000_MPTC); 6407 adapter->stats.bptc += rd32(E1000_BPTC); 6408 6409 adapter->stats.tpt += rd32(E1000_TPT); 6410 adapter->stats.colc += rd32(E1000_COLC); 6411 6412 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6413 /* read internal phy specific stats */ 6414 reg = rd32(E1000_CTRL_EXT); 6415 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6416 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6417 6418 /* this stat has invalid values on i210/i211 */ 6419 if ((hw->mac.type != e1000_i210) && 6420 (hw->mac.type != e1000_i211)) 6421 adapter->stats.tncrs += rd32(E1000_TNCRS); 6422 } 6423 6424 adapter->stats.tsctc += rd32(E1000_TSCTC); 6425 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6426 6427 adapter->stats.iac += rd32(E1000_IAC); 6428 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6429 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6430 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6431 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6432 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6433 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6434 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6435 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6436 6437 /* Fill out the OS statistics structure */ 6438 net_stats->multicast = adapter->stats.mprc; 6439 net_stats->collisions = adapter->stats.colc; 6440 6441 /* Rx Errors */ 6442 6443 /* RLEC on some newer hardware can be incorrect so build 6444 * our own version based on RUC and ROC 6445 */ 6446 net_stats->rx_errors = adapter->stats.rxerrc + 6447 adapter->stats.crcerrs + adapter->stats.algnerrc + 6448 adapter->stats.ruc + adapter->stats.roc + 6449 adapter->stats.cexterr; 6450 net_stats->rx_length_errors = adapter->stats.ruc + 6451 adapter->stats.roc; 6452 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6453 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6454 net_stats->rx_missed_errors = adapter->stats.mpc; 6455 6456 /* Tx Errors */ 6457 net_stats->tx_errors = adapter->stats.ecol + 6458 adapter->stats.latecol; 6459 net_stats->tx_aborted_errors = adapter->stats.ecol; 6460 net_stats->tx_window_errors = adapter->stats.latecol; 6461 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6462 6463 /* Tx Dropped needs to be maintained elsewhere */ 6464 6465 /* Management Stats */ 6466 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6467 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6468 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6469 6470 /* OS2BMC Stats */ 6471 reg = rd32(E1000_MANC); 6472 if (reg & E1000_MANC_EN_BMC2OS) { 6473 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6474 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6475 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6476 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6477 } 6478 } 6479 6480 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6481 { 6482 struct e1000_hw *hw = &adapter->hw; 6483 struct ptp_clock_event event; 6484 struct timespec64 ts; 6485 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6486 6487 if (tsicr & TSINTR_SYS_WRAP) { 6488 event.type = PTP_CLOCK_PPS; 6489 if (adapter->ptp_caps.pps) 6490 ptp_clock_event(adapter->ptp_clock, &event); 6491 ack |= TSINTR_SYS_WRAP; 6492 } 6493 6494 if (tsicr & E1000_TSICR_TXTS) { 6495 /* retrieve hardware timestamp */ 6496 schedule_work(&adapter->ptp_tx_work); 6497 ack |= E1000_TSICR_TXTS; 6498 } 6499 6500 if (tsicr & TSINTR_TT0) { 6501 spin_lock(&adapter->tmreg_lock); 6502 ts = timespec64_add(adapter->perout[0].start, 6503 adapter->perout[0].period); 6504 /* u32 conversion of tv_sec is safe until y2106 */ 6505 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6506 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6507 tsauxc = rd32(E1000_TSAUXC); 6508 tsauxc |= TSAUXC_EN_TT0; 6509 wr32(E1000_TSAUXC, tsauxc); 6510 adapter->perout[0].start = ts; 6511 spin_unlock(&adapter->tmreg_lock); 6512 ack |= TSINTR_TT0; 6513 } 6514 6515 if (tsicr & TSINTR_TT1) { 6516 spin_lock(&adapter->tmreg_lock); 6517 ts = timespec64_add(adapter->perout[1].start, 6518 adapter->perout[1].period); 6519 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6520 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6521 tsauxc = rd32(E1000_TSAUXC); 6522 tsauxc |= TSAUXC_EN_TT1; 6523 wr32(E1000_TSAUXC, tsauxc); 6524 adapter->perout[1].start = ts; 6525 spin_unlock(&adapter->tmreg_lock); 6526 ack |= TSINTR_TT1; 6527 } 6528 6529 if (tsicr & TSINTR_AUTT0) { 6530 nsec = rd32(E1000_AUXSTMPL0); 6531 sec = rd32(E1000_AUXSTMPH0); 6532 event.type = PTP_CLOCK_EXTTS; 6533 event.index = 0; 6534 event.timestamp = sec * 1000000000ULL + nsec; 6535 ptp_clock_event(adapter->ptp_clock, &event); 6536 ack |= TSINTR_AUTT0; 6537 } 6538 6539 if (tsicr & TSINTR_AUTT1) { 6540 nsec = rd32(E1000_AUXSTMPL1); 6541 sec = rd32(E1000_AUXSTMPH1); 6542 event.type = PTP_CLOCK_EXTTS; 6543 event.index = 1; 6544 event.timestamp = sec * 1000000000ULL + nsec; 6545 ptp_clock_event(adapter->ptp_clock, &event); 6546 ack |= TSINTR_AUTT1; 6547 } 6548 6549 /* acknowledge the interrupts */ 6550 wr32(E1000_TSICR, ack); 6551 } 6552 6553 static irqreturn_t igb_msix_other(int irq, void *data) 6554 { 6555 struct igb_adapter *adapter = data; 6556 struct e1000_hw *hw = &adapter->hw; 6557 u32 icr = rd32(E1000_ICR); 6558 /* reading ICR causes bit 31 of EICR to be cleared */ 6559 6560 if (icr & E1000_ICR_DRSTA) 6561 schedule_work(&adapter->reset_task); 6562 6563 if (icr & E1000_ICR_DOUTSYNC) { 6564 /* HW is reporting DMA is out of sync */ 6565 adapter->stats.doosync++; 6566 /* The DMA Out of Sync is also indication of a spoof event 6567 * in IOV mode. Check the Wrong VM Behavior register to 6568 * see if it is really a spoof event. 6569 */ 6570 igb_check_wvbr(adapter); 6571 } 6572 6573 /* Check for a mailbox event */ 6574 if (icr & E1000_ICR_VMMB) 6575 igb_msg_task(adapter); 6576 6577 if (icr & E1000_ICR_LSC) { 6578 hw->mac.get_link_status = 1; 6579 /* guard against interrupt when we're going down */ 6580 if (!test_bit(__IGB_DOWN, &adapter->state)) 6581 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6582 } 6583 6584 if (icr & E1000_ICR_TS) 6585 igb_tsync_interrupt(adapter); 6586 6587 wr32(E1000_EIMS, adapter->eims_other); 6588 6589 return IRQ_HANDLED; 6590 } 6591 6592 static void igb_write_itr(struct igb_q_vector *q_vector) 6593 { 6594 struct igb_adapter *adapter = q_vector->adapter; 6595 u32 itr_val = q_vector->itr_val & 0x7FFC; 6596 6597 if (!q_vector->set_itr) 6598 return; 6599 6600 if (!itr_val) 6601 itr_val = 0x4; 6602 6603 if (adapter->hw.mac.type == e1000_82575) 6604 itr_val |= itr_val << 16; 6605 else 6606 itr_val |= E1000_EITR_CNT_IGNR; 6607 6608 writel(itr_val, q_vector->itr_register); 6609 q_vector->set_itr = 0; 6610 } 6611 6612 static irqreturn_t igb_msix_ring(int irq, void *data) 6613 { 6614 struct igb_q_vector *q_vector = data; 6615 6616 /* Write the ITR value calculated from the previous interrupt. */ 6617 igb_write_itr(q_vector); 6618 6619 napi_schedule(&q_vector->napi); 6620 6621 return IRQ_HANDLED; 6622 } 6623 6624 #ifdef CONFIG_IGB_DCA 6625 static void igb_update_tx_dca(struct igb_adapter *adapter, 6626 struct igb_ring *tx_ring, 6627 int cpu) 6628 { 6629 struct e1000_hw *hw = &adapter->hw; 6630 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6631 6632 if (hw->mac.type != e1000_82575) 6633 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6634 6635 /* We can enable relaxed ordering for reads, but not writes when 6636 * DCA is enabled. This is due to a known issue in some chipsets 6637 * which will cause the DCA tag to be cleared. 6638 */ 6639 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6640 E1000_DCA_TXCTRL_DATA_RRO_EN | 6641 E1000_DCA_TXCTRL_DESC_DCA_EN; 6642 6643 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6644 } 6645 6646 static void igb_update_rx_dca(struct igb_adapter *adapter, 6647 struct igb_ring *rx_ring, 6648 int cpu) 6649 { 6650 struct e1000_hw *hw = &adapter->hw; 6651 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6652 6653 if (hw->mac.type != e1000_82575) 6654 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6655 6656 /* We can enable relaxed ordering for reads, but not writes when 6657 * DCA is enabled. This is due to a known issue in some chipsets 6658 * which will cause the DCA tag to be cleared. 6659 */ 6660 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6661 E1000_DCA_RXCTRL_DESC_DCA_EN; 6662 6663 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6664 } 6665 6666 static void igb_update_dca(struct igb_q_vector *q_vector) 6667 { 6668 struct igb_adapter *adapter = q_vector->adapter; 6669 int cpu = get_cpu(); 6670 6671 if (q_vector->cpu == cpu) 6672 goto out_no_update; 6673 6674 if (q_vector->tx.ring) 6675 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6676 6677 if (q_vector->rx.ring) 6678 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6679 6680 q_vector->cpu = cpu; 6681 out_no_update: 6682 put_cpu(); 6683 } 6684 6685 static void igb_setup_dca(struct igb_adapter *adapter) 6686 { 6687 struct e1000_hw *hw = &adapter->hw; 6688 int i; 6689 6690 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6691 return; 6692 6693 /* Always use CB2 mode, difference is masked in the CB driver. */ 6694 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6695 6696 for (i = 0; i < adapter->num_q_vectors; i++) { 6697 adapter->q_vector[i]->cpu = -1; 6698 igb_update_dca(adapter->q_vector[i]); 6699 } 6700 } 6701 6702 static int __igb_notify_dca(struct device *dev, void *data) 6703 { 6704 struct net_device *netdev = dev_get_drvdata(dev); 6705 struct igb_adapter *adapter = netdev_priv(netdev); 6706 struct pci_dev *pdev = adapter->pdev; 6707 struct e1000_hw *hw = &adapter->hw; 6708 unsigned long event = *(unsigned long *)data; 6709 6710 switch (event) { 6711 case DCA_PROVIDER_ADD: 6712 /* if already enabled, don't do it again */ 6713 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6714 break; 6715 if (dca_add_requester(dev) == 0) { 6716 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6717 dev_info(&pdev->dev, "DCA enabled\n"); 6718 igb_setup_dca(adapter); 6719 break; 6720 } 6721 /* Fall Through since DCA is disabled. */ 6722 case DCA_PROVIDER_REMOVE: 6723 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6724 /* without this a class_device is left 6725 * hanging around in the sysfs model 6726 */ 6727 dca_remove_requester(dev); 6728 dev_info(&pdev->dev, "DCA disabled\n"); 6729 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6730 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6731 } 6732 break; 6733 } 6734 6735 return 0; 6736 } 6737 6738 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6739 void *p) 6740 { 6741 int ret_val; 6742 6743 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6744 __igb_notify_dca); 6745 6746 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6747 } 6748 #endif /* CONFIG_IGB_DCA */ 6749 6750 #ifdef CONFIG_PCI_IOV 6751 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6752 { 6753 unsigned char mac_addr[ETH_ALEN]; 6754 6755 eth_zero_addr(mac_addr); 6756 igb_set_vf_mac(adapter, vf, mac_addr); 6757 6758 /* By default spoof check is enabled for all VFs */ 6759 adapter->vf_data[vf].spoofchk_enabled = true; 6760 6761 /* By default VFs are not trusted */ 6762 adapter->vf_data[vf].trusted = false; 6763 6764 return 0; 6765 } 6766 6767 #endif 6768 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6769 { 6770 struct e1000_hw *hw = &adapter->hw; 6771 u32 ping; 6772 int i; 6773 6774 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6775 ping = E1000_PF_CONTROL_MSG; 6776 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6777 ping |= E1000_VT_MSGTYPE_CTS; 6778 igb_write_mbx(hw, &ping, 1, i); 6779 } 6780 } 6781 6782 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6783 { 6784 struct e1000_hw *hw = &adapter->hw; 6785 u32 vmolr = rd32(E1000_VMOLR(vf)); 6786 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6787 6788 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6789 IGB_VF_FLAG_MULTI_PROMISC); 6790 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6791 6792 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6793 vmolr |= E1000_VMOLR_MPME; 6794 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6795 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6796 } else { 6797 /* if we have hashes and we are clearing a multicast promisc 6798 * flag we need to write the hashes to the MTA as this step 6799 * was previously skipped 6800 */ 6801 if (vf_data->num_vf_mc_hashes > 30) { 6802 vmolr |= E1000_VMOLR_MPME; 6803 } else if (vf_data->num_vf_mc_hashes) { 6804 int j; 6805 6806 vmolr |= E1000_VMOLR_ROMPE; 6807 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6808 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6809 } 6810 } 6811 6812 wr32(E1000_VMOLR(vf), vmolr); 6813 6814 /* there are flags left unprocessed, likely not supported */ 6815 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6816 return -EINVAL; 6817 6818 return 0; 6819 } 6820 6821 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6822 u32 *msgbuf, u32 vf) 6823 { 6824 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6825 u16 *hash_list = (u16 *)&msgbuf[1]; 6826 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6827 int i; 6828 6829 /* salt away the number of multicast addresses assigned 6830 * to this VF for later use to restore when the PF multi cast 6831 * list changes 6832 */ 6833 vf_data->num_vf_mc_hashes = n; 6834 6835 /* only up to 30 hash values supported */ 6836 if (n > 30) 6837 n = 30; 6838 6839 /* store the hashes for later use */ 6840 for (i = 0; i < n; i++) 6841 vf_data->vf_mc_hashes[i] = hash_list[i]; 6842 6843 /* Flush and reset the mta with the new values */ 6844 igb_set_rx_mode(adapter->netdev); 6845 6846 return 0; 6847 } 6848 6849 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6850 { 6851 struct e1000_hw *hw = &adapter->hw; 6852 struct vf_data_storage *vf_data; 6853 int i, j; 6854 6855 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6856 u32 vmolr = rd32(E1000_VMOLR(i)); 6857 6858 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6859 6860 vf_data = &adapter->vf_data[i]; 6861 6862 if ((vf_data->num_vf_mc_hashes > 30) || 6863 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6864 vmolr |= E1000_VMOLR_MPME; 6865 } else if (vf_data->num_vf_mc_hashes) { 6866 vmolr |= E1000_VMOLR_ROMPE; 6867 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6868 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6869 } 6870 wr32(E1000_VMOLR(i), vmolr); 6871 } 6872 } 6873 6874 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6875 { 6876 struct e1000_hw *hw = &adapter->hw; 6877 u32 pool_mask, vlvf_mask, i; 6878 6879 /* create mask for VF and other pools */ 6880 pool_mask = E1000_VLVF_POOLSEL_MASK; 6881 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6882 6883 /* drop PF from pool bits */ 6884 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6885 adapter->vfs_allocated_count); 6886 6887 /* Find the vlan filter for this id */ 6888 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6889 u32 vlvf = rd32(E1000_VLVF(i)); 6890 u32 vfta_mask, vid, vfta; 6891 6892 /* remove the vf from the pool */ 6893 if (!(vlvf & vlvf_mask)) 6894 continue; 6895 6896 /* clear out bit from VLVF */ 6897 vlvf ^= vlvf_mask; 6898 6899 /* if other pools are present, just remove ourselves */ 6900 if (vlvf & pool_mask) 6901 goto update_vlvfb; 6902 6903 /* if PF is present, leave VFTA */ 6904 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6905 goto update_vlvf; 6906 6907 vid = vlvf & E1000_VLVF_VLANID_MASK; 6908 vfta_mask = BIT(vid % 32); 6909 6910 /* clear bit from VFTA */ 6911 vfta = adapter->shadow_vfta[vid / 32]; 6912 if (vfta & vfta_mask) 6913 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6914 update_vlvf: 6915 /* clear pool selection enable */ 6916 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6917 vlvf &= E1000_VLVF_POOLSEL_MASK; 6918 else 6919 vlvf = 0; 6920 update_vlvfb: 6921 /* clear pool bits */ 6922 wr32(E1000_VLVF(i), vlvf); 6923 } 6924 } 6925 6926 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6927 { 6928 u32 vlvf; 6929 int idx; 6930 6931 /* short cut the special case */ 6932 if (vlan == 0) 6933 return 0; 6934 6935 /* Search for the VLAN id in the VLVF entries */ 6936 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6937 vlvf = rd32(E1000_VLVF(idx)); 6938 if ((vlvf & VLAN_VID_MASK) == vlan) 6939 break; 6940 } 6941 6942 return idx; 6943 } 6944 6945 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6946 { 6947 struct e1000_hw *hw = &adapter->hw; 6948 u32 bits, pf_id; 6949 int idx; 6950 6951 idx = igb_find_vlvf_entry(hw, vid); 6952 if (!idx) 6953 return; 6954 6955 /* See if any other pools are set for this VLAN filter 6956 * entry other than the PF. 6957 */ 6958 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6959 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6960 bits &= rd32(E1000_VLVF(idx)); 6961 6962 /* Disable the filter so this falls into the default pool. */ 6963 if (!bits) { 6964 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6965 wr32(E1000_VLVF(idx), BIT(pf_id)); 6966 else 6967 wr32(E1000_VLVF(idx), 0); 6968 } 6969 } 6970 6971 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6972 bool add, u32 vf) 6973 { 6974 int pf_id = adapter->vfs_allocated_count; 6975 struct e1000_hw *hw = &adapter->hw; 6976 int err; 6977 6978 /* If VLAN overlaps with one the PF is currently monitoring make 6979 * sure that we are able to allocate a VLVF entry. This may be 6980 * redundant but it guarantees PF will maintain visibility to 6981 * the VLAN. 6982 */ 6983 if (add && test_bit(vid, adapter->active_vlans)) { 6984 err = igb_vfta_set(hw, vid, pf_id, true, false); 6985 if (err) 6986 return err; 6987 } 6988 6989 err = igb_vfta_set(hw, vid, vf, add, false); 6990 6991 if (add && !err) 6992 return err; 6993 6994 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6995 * we may need to drop the PF pool bit in order to allow us to free 6996 * up the VLVF resources. 6997 */ 6998 if (test_bit(vid, adapter->active_vlans) || 6999 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7000 igb_update_pf_vlvf(adapter, vid); 7001 7002 return err; 7003 } 7004 7005 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7006 { 7007 struct e1000_hw *hw = &adapter->hw; 7008 7009 if (vid) 7010 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7011 else 7012 wr32(E1000_VMVIR(vf), 0); 7013 } 7014 7015 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7016 u16 vlan, u8 qos) 7017 { 7018 int err; 7019 7020 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7021 if (err) 7022 return err; 7023 7024 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7025 igb_set_vmolr(adapter, vf, !vlan); 7026 7027 /* revoke access to previous VLAN */ 7028 if (vlan != adapter->vf_data[vf].pf_vlan) 7029 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7030 false, vf); 7031 7032 adapter->vf_data[vf].pf_vlan = vlan; 7033 adapter->vf_data[vf].pf_qos = qos; 7034 igb_set_vf_vlan_strip(adapter, vf, true); 7035 dev_info(&adapter->pdev->dev, 7036 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7037 if (test_bit(__IGB_DOWN, &adapter->state)) { 7038 dev_warn(&adapter->pdev->dev, 7039 "The VF VLAN has been set, but the PF device is not up.\n"); 7040 dev_warn(&adapter->pdev->dev, 7041 "Bring the PF device up before attempting to use the VF device.\n"); 7042 } 7043 7044 return err; 7045 } 7046 7047 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7048 { 7049 /* Restore tagless access via VLAN 0 */ 7050 igb_set_vf_vlan(adapter, 0, true, vf); 7051 7052 igb_set_vmvir(adapter, 0, vf); 7053 igb_set_vmolr(adapter, vf, true); 7054 7055 /* Remove any PF assigned VLAN */ 7056 if (adapter->vf_data[vf].pf_vlan) 7057 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7058 false, vf); 7059 7060 adapter->vf_data[vf].pf_vlan = 0; 7061 adapter->vf_data[vf].pf_qos = 0; 7062 igb_set_vf_vlan_strip(adapter, vf, false); 7063 7064 return 0; 7065 } 7066 7067 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7068 u16 vlan, u8 qos, __be16 vlan_proto) 7069 { 7070 struct igb_adapter *adapter = netdev_priv(netdev); 7071 7072 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7073 return -EINVAL; 7074 7075 if (vlan_proto != htons(ETH_P_8021Q)) 7076 return -EPROTONOSUPPORT; 7077 7078 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7079 igb_disable_port_vlan(adapter, vf); 7080 } 7081 7082 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7083 { 7084 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7085 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7086 int ret; 7087 7088 if (adapter->vf_data[vf].pf_vlan) 7089 return -1; 7090 7091 /* VLAN 0 is a special case, don't allow it to be removed */ 7092 if (!vid && !add) 7093 return 0; 7094 7095 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7096 if (!ret) 7097 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7098 return ret; 7099 } 7100 7101 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7102 { 7103 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7104 7105 /* clear flags - except flag that indicates PF has set the MAC */ 7106 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7107 vf_data->last_nack = jiffies; 7108 7109 /* reset vlans for device */ 7110 igb_clear_vf_vfta(adapter, vf); 7111 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7112 igb_set_vmvir(adapter, vf_data->pf_vlan | 7113 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7114 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7115 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7116 7117 /* reset multicast table array for vf */ 7118 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7119 7120 /* Flush and reset the mta with the new values */ 7121 igb_set_rx_mode(adapter->netdev); 7122 } 7123 7124 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7125 { 7126 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7127 7128 /* clear mac address as we were hotplug removed/added */ 7129 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7130 eth_zero_addr(vf_mac); 7131 7132 /* process remaining reset events */ 7133 igb_vf_reset(adapter, vf); 7134 } 7135 7136 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7137 { 7138 struct e1000_hw *hw = &adapter->hw; 7139 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7140 u32 reg, msgbuf[3]; 7141 u8 *addr = (u8 *)(&msgbuf[1]); 7142 7143 /* process all the same items cleared in a function level reset */ 7144 igb_vf_reset(adapter, vf); 7145 7146 /* set vf mac address */ 7147 igb_set_vf_mac(adapter, vf, vf_mac); 7148 7149 /* enable transmit and receive for vf */ 7150 reg = rd32(E1000_VFTE); 7151 wr32(E1000_VFTE, reg | BIT(vf)); 7152 reg = rd32(E1000_VFRE); 7153 wr32(E1000_VFRE, reg | BIT(vf)); 7154 7155 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7156 7157 /* reply to reset with ack and vf mac address */ 7158 if (!is_zero_ether_addr(vf_mac)) { 7159 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7160 memcpy(addr, vf_mac, ETH_ALEN); 7161 } else { 7162 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7163 } 7164 igb_write_mbx(hw, msgbuf, 3, vf); 7165 } 7166 7167 static void igb_flush_mac_table(struct igb_adapter *adapter) 7168 { 7169 struct e1000_hw *hw = &adapter->hw; 7170 int i; 7171 7172 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7173 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7174 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7175 adapter->mac_table[i].queue = 0; 7176 igb_rar_set_index(adapter, i); 7177 } 7178 } 7179 7180 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7181 { 7182 struct e1000_hw *hw = &adapter->hw; 7183 /* do not count rar entries reserved for VFs MAC addresses */ 7184 int rar_entries = hw->mac.rar_entry_count - 7185 adapter->vfs_allocated_count; 7186 int i, count = 0; 7187 7188 for (i = 0; i < rar_entries; i++) { 7189 /* do not count default entries */ 7190 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7191 continue; 7192 7193 /* do not count "in use" entries for different queues */ 7194 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7195 (adapter->mac_table[i].queue != queue)) 7196 continue; 7197 7198 count++; 7199 } 7200 7201 return count; 7202 } 7203 7204 /* Set default MAC address for the PF in the first RAR entry */ 7205 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7206 { 7207 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7208 7209 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7210 mac_table->queue = adapter->vfs_allocated_count; 7211 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7212 7213 igb_rar_set_index(adapter, 0); 7214 } 7215 7216 /* If the filter to be added and an already existing filter express 7217 * the same address and address type, it should be possible to only 7218 * override the other configurations, for example the queue to steer 7219 * traffic. 7220 */ 7221 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7222 const u8 *addr, const u8 flags) 7223 { 7224 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7225 return true; 7226 7227 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7228 (flags & IGB_MAC_STATE_SRC_ADDR)) 7229 return false; 7230 7231 if (!ether_addr_equal(addr, entry->addr)) 7232 return false; 7233 7234 return true; 7235 } 7236 7237 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7238 * 'flags' is used to indicate what kind of match is made, match is by 7239 * default for the destination address, if matching by source address 7240 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7241 */ 7242 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7243 const u8 *addr, const u8 queue, 7244 const u8 flags) 7245 { 7246 struct e1000_hw *hw = &adapter->hw; 7247 int rar_entries = hw->mac.rar_entry_count - 7248 adapter->vfs_allocated_count; 7249 int i; 7250 7251 if (is_zero_ether_addr(addr)) 7252 return -EINVAL; 7253 7254 /* Search for the first empty entry in the MAC table. 7255 * Do not touch entries at the end of the table reserved for the VF MAC 7256 * addresses. 7257 */ 7258 for (i = 0; i < rar_entries; i++) { 7259 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7260 addr, flags)) 7261 continue; 7262 7263 ether_addr_copy(adapter->mac_table[i].addr, addr); 7264 adapter->mac_table[i].queue = queue; 7265 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7266 7267 igb_rar_set_index(adapter, i); 7268 return i; 7269 } 7270 7271 return -ENOSPC; 7272 } 7273 7274 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7275 const u8 queue) 7276 { 7277 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7278 } 7279 7280 /* Remove a MAC filter for 'addr' directing matching traffic to 7281 * 'queue', 'flags' is used to indicate what kind of match need to be 7282 * removed, match is by default for the destination address, if 7283 * matching by source address is to be removed the flag 7284 * IGB_MAC_STATE_SRC_ADDR can be used. 7285 */ 7286 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7287 const u8 *addr, const u8 queue, 7288 const u8 flags) 7289 { 7290 struct e1000_hw *hw = &adapter->hw; 7291 int rar_entries = hw->mac.rar_entry_count - 7292 adapter->vfs_allocated_count; 7293 int i; 7294 7295 if (is_zero_ether_addr(addr)) 7296 return -EINVAL; 7297 7298 /* Search for matching entry in the MAC table based on given address 7299 * and queue. Do not touch entries at the end of the table reserved 7300 * for the VF MAC addresses. 7301 */ 7302 for (i = 0; i < rar_entries; i++) { 7303 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7304 continue; 7305 if ((adapter->mac_table[i].state & flags) != flags) 7306 continue; 7307 if (adapter->mac_table[i].queue != queue) 7308 continue; 7309 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7310 continue; 7311 7312 /* When a filter for the default address is "deleted", 7313 * we return it to its initial configuration 7314 */ 7315 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7316 adapter->mac_table[i].state = 7317 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7318 adapter->mac_table[i].queue = 7319 adapter->vfs_allocated_count; 7320 } else { 7321 adapter->mac_table[i].state = 0; 7322 adapter->mac_table[i].queue = 0; 7323 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 7324 } 7325 7326 igb_rar_set_index(adapter, i); 7327 return 0; 7328 } 7329 7330 return -ENOENT; 7331 } 7332 7333 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7334 const u8 queue) 7335 { 7336 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7337 } 7338 7339 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7340 const u8 *addr, u8 queue, u8 flags) 7341 { 7342 struct e1000_hw *hw = &adapter->hw; 7343 7344 /* In theory, this should be supported on 82575 as well, but 7345 * that part wasn't easily accessible during development. 7346 */ 7347 if (hw->mac.type != e1000_i210) 7348 return -EOPNOTSUPP; 7349 7350 return igb_add_mac_filter_flags(adapter, addr, queue, 7351 IGB_MAC_STATE_QUEUE_STEERING | flags); 7352 } 7353 7354 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7355 const u8 *addr, u8 queue, u8 flags) 7356 { 7357 return igb_del_mac_filter_flags(adapter, addr, queue, 7358 IGB_MAC_STATE_QUEUE_STEERING | flags); 7359 } 7360 7361 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7362 { 7363 struct igb_adapter *adapter = netdev_priv(netdev); 7364 int ret; 7365 7366 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7367 7368 return min_t(int, ret, 0); 7369 } 7370 7371 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7372 { 7373 struct igb_adapter *adapter = netdev_priv(netdev); 7374 7375 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7376 7377 return 0; 7378 } 7379 7380 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7381 const u32 info, const u8 *addr) 7382 { 7383 struct pci_dev *pdev = adapter->pdev; 7384 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7385 struct list_head *pos; 7386 struct vf_mac_filter *entry = NULL; 7387 int ret = 0; 7388 7389 switch (info) { 7390 case E1000_VF_MAC_FILTER_CLR: 7391 /* remove all unicast MAC filters related to the current VF */ 7392 list_for_each(pos, &adapter->vf_macs.l) { 7393 entry = list_entry(pos, struct vf_mac_filter, l); 7394 if (entry->vf == vf) { 7395 entry->vf = -1; 7396 entry->free = true; 7397 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7398 } 7399 } 7400 break; 7401 case E1000_VF_MAC_FILTER_ADD: 7402 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7403 !vf_data->trusted) { 7404 dev_warn(&pdev->dev, 7405 "VF %d requested MAC filter but is administratively denied\n", 7406 vf); 7407 return -EINVAL; 7408 } 7409 if (!is_valid_ether_addr(addr)) { 7410 dev_warn(&pdev->dev, 7411 "VF %d attempted to set invalid MAC filter\n", 7412 vf); 7413 return -EINVAL; 7414 } 7415 7416 /* try to find empty slot in the list */ 7417 list_for_each(pos, &adapter->vf_macs.l) { 7418 entry = list_entry(pos, struct vf_mac_filter, l); 7419 if (entry->free) 7420 break; 7421 } 7422 7423 if (entry && entry->free) { 7424 entry->free = false; 7425 entry->vf = vf; 7426 ether_addr_copy(entry->vf_mac, addr); 7427 7428 ret = igb_add_mac_filter(adapter, addr, vf); 7429 ret = min_t(int, ret, 0); 7430 } else { 7431 ret = -ENOSPC; 7432 } 7433 7434 if (ret == -ENOSPC) 7435 dev_warn(&pdev->dev, 7436 "VF %d has requested MAC filter but there is no space for it\n", 7437 vf); 7438 break; 7439 default: 7440 ret = -EINVAL; 7441 break; 7442 } 7443 7444 return ret; 7445 } 7446 7447 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7448 { 7449 struct pci_dev *pdev = adapter->pdev; 7450 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7451 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7452 7453 /* The VF MAC Address is stored in a packed array of bytes 7454 * starting at the second 32 bit word of the msg array 7455 */ 7456 unsigned char *addr = (unsigned char *)&msg[1]; 7457 int ret = 0; 7458 7459 if (!info) { 7460 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7461 !vf_data->trusted) { 7462 dev_warn(&pdev->dev, 7463 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7464 vf); 7465 return -EINVAL; 7466 } 7467 7468 if (!is_valid_ether_addr(addr)) { 7469 dev_warn(&pdev->dev, 7470 "VF %d attempted to set invalid MAC\n", 7471 vf); 7472 return -EINVAL; 7473 } 7474 7475 ret = igb_set_vf_mac(adapter, vf, addr); 7476 } else { 7477 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7478 } 7479 7480 return ret; 7481 } 7482 7483 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7484 { 7485 struct e1000_hw *hw = &adapter->hw; 7486 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7487 u32 msg = E1000_VT_MSGTYPE_NACK; 7488 7489 /* if device isn't clear to send it shouldn't be reading either */ 7490 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7491 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7492 igb_write_mbx(hw, &msg, 1, vf); 7493 vf_data->last_nack = jiffies; 7494 } 7495 } 7496 7497 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7498 { 7499 struct pci_dev *pdev = adapter->pdev; 7500 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7501 struct e1000_hw *hw = &adapter->hw; 7502 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7503 s32 retval; 7504 7505 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7506 7507 if (retval) { 7508 /* if receive failed revoke VF CTS stats and restart init */ 7509 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7510 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7511 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7512 goto unlock; 7513 goto out; 7514 } 7515 7516 /* this is a message we already processed, do nothing */ 7517 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7518 goto unlock; 7519 7520 /* until the vf completes a reset it should not be 7521 * allowed to start any configuration. 7522 */ 7523 if (msgbuf[0] == E1000_VF_RESET) { 7524 /* unlocks mailbox */ 7525 igb_vf_reset_msg(adapter, vf); 7526 return; 7527 } 7528 7529 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7530 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7531 goto unlock; 7532 retval = -1; 7533 goto out; 7534 } 7535 7536 switch ((msgbuf[0] & 0xFFFF)) { 7537 case E1000_VF_SET_MAC_ADDR: 7538 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7539 break; 7540 case E1000_VF_SET_PROMISC: 7541 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7542 break; 7543 case E1000_VF_SET_MULTICAST: 7544 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7545 break; 7546 case E1000_VF_SET_LPE: 7547 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7548 break; 7549 case E1000_VF_SET_VLAN: 7550 retval = -1; 7551 if (vf_data->pf_vlan) 7552 dev_warn(&pdev->dev, 7553 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7554 vf); 7555 else 7556 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7557 break; 7558 default: 7559 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7560 retval = -1; 7561 break; 7562 } 7563 7564 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7565 out: 7566 /* notify the VF of the results of what it sent us */ 7567 if (retval) 7568 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7569 else 7570 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7571 7572 /* unlocks mailbox */ 7573 igb_write_mbx(hw, msgbuf, 1, vf); 7574 return; 7575 7576 unlock: 7577 igb_unlock_mbx(hw, vf); 7578 } 7579 7580 static void igb_msg_task(struct igb_adapter *adapter) 7581 { 7582 struct e1000_hw *hw = &adapter->hw; 7583 u32 vf; 7584 7585 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7586 /* process any reset requests */ 7587 if (!igb_check_for_rst(hw, vf)) 7588 igb_vf_reset_event(adapter, vf); 7589 7590 /* process any messages pending */ 7591 if (!igb_check_for_msg(hw, vf)) 7592 igb_rcv_msg_from_vf(adapter, vf); 7593 7594 /* process any acks */ 7595 if (!igb_check_for_ack(hw, vf)) 7596 igb_rcv_ack_from_vf(adapter, vf); 7597 } 7598 } 7599 7600 /** 7601 * igb_set_uta - Set unicast filter table address 7602 * @adapter: board private structure 7603 * @set: boolean indicating if we are setting or clearing bits 7604 * 7605 * The unicast table address is a register array of 32-bit registers. 7606 * The table is meant to be used in a way similar to how the MTA is used 7607 * however due to certain limitations in the hardware it is necessary to 7608 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7609 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7610 **/ 7611 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7612 { 7613 struct e1000_hw *hw = &adapter->hw; 7614 u32 uta = set ? ~0 : 0; 7615 int i; 7616 7617 /* we only need to do this if VMDq is enabled */ 7618 if (!adapter->vfs_allocated_count) 7619 return; 7620 7621 for (i = hw->mac.uta_reg_count; i--;) 7622 array_wr32(E1000_UTA, i, uta); 7623 } 7624 7625 /** 7626 * igb_intr_msi - Interrupt Handler 7627 * @irq: interrupt number 7628 * @data: pointer to a network interface device structure 7629 **/ 7630 static irqreturn_t igb_intr_msi(int irq, void *data) 7631 { 7632 struct igb_adapter *adapter = data; 7633 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7634 struct e1000_hw *hw = &adapter->hw; 7635 /* read ICR disables interrupts using IAM */ 7636 u32 icr = rd32(E1000_ICR); 7637 7638 igb_write_itr(q_vector); 7639 7640 if (icr & E1000_ICR_DRSTA) 7641 schedule_work(&adapter->reset_task); 7642 7643 if (icr & E1000_ICR_DOUTSYNC) { 7644 /* HW is reporting DMA is out of sync */ 7645 adapter->stats.doosync++; 7646 } 7647 7648 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7649 hw->mac.get_link_status = 1; 7650 if (!test_bit(__IGB_DOWN, &adapter->state)) 7651 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7652 } 7653 7654 if (icr & E1000_ICR_TS) 7655 igb_tsync_interrupt(adapter); 7656 7657 napi_schedule(&q_vector->napi); 7658 7659 return IRQ_HANDLED; 7660 } 7661 7662 /** 7663 * igb_intr - Legacy Interrupt Handler 7664 * @irq: interrupt number 7665 * @data: pointer to a network interface device structure 7666 **/ 7667 static irqreturn_t igb_intr(int irq, void *data) 7668 { 7669 struct igb_adapter *adapter = data; 7670 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7671 struct e1000_hw *hw = &adapter->hw; 7672 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7673 * need for the IMC write 7674 */ 7675 u32 icr = rd32(E1000_ICR); 7676 7677 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7678 * not set, then the adapter didn't send an interrupt 7679 */ 7680 if (!(icr & E1000_ICR_INT_ASSERTED)) 7681 return IRQ_NONE; 7682 7683 igb_write_itr(q_vector); 7684 7685 if (icr & E1000_ICR_DRSTA) 7686 schedule_work(&adapter->reset_task); 7687 7688 if (icr & E1000_ICR_DOUTSYNC) { 7689 /* HW is reporting DMA is out of sync */ 7690 adapter->stats.doosync++; 7691 } 7692 7693 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7694 hw->mac.get_link_status = 1; 7695 /* guard against interrupt when we're going down */ 7696 if (!test_bit(__IGB_DOWN, &adapter->state)) 7697 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7698 } 7699 7700 if (icr & E1000_ICR_TS) 7701 igb_tsync_interrupt(adapter); 7702 7703 napi_schedule(&q_vector->napi); 7704 7705 return IRQ_HANDLED; 7706 } 7707 7708 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7709 { 7710 struct igb_adapter *adapter = q_vector->adapter; 7711 struct e1000_hw *hw = &adapter->hw; 7712 7713 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7714 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7715 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7716 igb_set_itr(q_vector); 7717 else 7718 igb_update_ring_itr(q_vector); 7719 } 7720 7721 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7722 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7723 wr32(E1000_EIMS, q_vector->eims_value); 7724 else 7725 igb_irq_enable(adapter); 7726 } 7727 } 7728 7729 /** 7730 * igb_poll - NAPI Rx polling callback 7731 * @napi: napi polling structure 7732 * @budget: count of how many packets we should handle 7733 **/ 7734 static int igb_poll(struct napi_struct *napi, int budget) 7735 { 7736 struct igb_q_vector *q_vector = container_of(napi, 7737 struct igb_q_vector, 7738 napi); 7739 bool clean_complete = true; 7740 int work_done = 0; 7741 7742 #ifdef CONFIG_IGB_DCA 7743 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7744 igb_update_dca(q_vector); 7745 #endif 7746 if (q_vector->tx.ring) 7747 clean_complete = igb_clean_tx_irq(q_vector, budget); 7748 7749 if (q_vector->rx.ring) { 7750 int cleaned = igb_clean_rx_irq(q_vector, budget); 7751 7752 work_done += cleaned; 7753 if (cleaned >= budget) 7754 clean_complete = false; 7755 } 7756 7757 /* If all work not completed, return budget and keep polling */ 7758 if (!clean_complete) 7759 return budget; 7760 7761 /* If not enough Rx work done, exit the polling mode */ 7762 napi_complete_done(napi, work_done); 7763 igb_ring_irq_enable(q_vector); 7764 7765 return 0; 7766 } 7767 7768 /** 7769 * igb_clean_tx_irq - Reclaim resources after transmit completes 7770 * @q_vector: pointer to q_vector containing needed info 7771 * @napi_budget: Used to determine if we are in netpoll 7772 * 7773 * returns true if ring is completely cleaned 7774 **/ 7775 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7776 { 7777 struct igb_adapter *adapter = q_vector->adapter; 7778 struct igb_ring *tx_ring = q_vector->tx.ring; 7779 struct igb_tx_buffer *tx_buffer; 7780 union e1000_adv_tx_desc *tx_desc; 7781 unsigned int total_bytes = 0, total_packets = 0; 7782 unsigned int budget = q_vector->tx.work_limit; 7783 unsigned int i = tx_ring->next_to_clean; 7784 7785 if (test_bit(__IGB_DOWN, &adapter->state)) 7786 return true; 7787 7788 tx_buffer = &tx_ring->tx_buffer_info[i]; 7789 tx_desc = IGB_TX_DESC(tx_ring, i); 7790 i -= tx_ring->count; 7791 7792 do { 7793 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7794 7795 /* if next_to_watch is not set then there is no work pending */ 7796 if (!eop_desc) 7797 break; 7798 7799 /* prevent any other reads prior to eop_desc */ 7800 smp_rmb(); 7801 7802 /* if DD is not set pending work has not been completed */ 7803 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7804 break; 7805 7806 /* clear next_to_watch to prevent false hangs */ 7807 tx_buffer->next_to_watch = NULL; 7808 7809 /* update the statistics for this packet */ 7810 total_bytes += tx_buffer->bytecount; 7811 total_packets += tx_buffer->gso_segs; 7812 7813 /* free the skb */ 7814 napi_consume_skb(tx_buffer->skb, napi_budget); 7815 7816 /* unmap skb header data */ 7817 dma_unmap_single(tx_ring->dev, 7818 dma_unmap_addr(tx_buffer, dma), 7819 dma_unmap_len(tx_buffer, len), 7820 DMA_TO_DEVICE); 7821 7822 /* clear tx_buffer data */ 7823 dma_unmap_len_set(tx_buffer, len, 0); 7824 7825 /* clear last DMA location and unmap remaining buffers */ 7826 while (tx_desc != eop_desc) { 7827 tx_buffer++; 7828 tx_desc++; 7829 i++; 7830 if (unlikely(!i)) { 7831 i -= tx_ring->count; 7832 tx_buffer = tx_ring->tx_buffer_info; 7833 tx_desc = IGB_TX_DESC(tx_ring, 0); 7834 } 7835 7836 /* unmap any remaining paged data */ 7837 if (dma_unmap_len(tx_buffer, len)) { 7838 dma_unmap_page(tx_ring->dev, 7839 dma_unmap_addr(tx_buffer, dma), 7840 dma_unmap_len(tx_buffer, len), 7841 DMA_TO_DEVICE); 7842 dma_unmap_len_set(tx_buffer, len, 0); 7843 } 7844 } 7845 7846 /* move us one more past the eop_desc for start of next pkt */ 7847 tx_buffer++; 7848 tx_desc++; 7849 i++; 7850 if (unlikely(!i)) { 7851 i -= tx_ring->count; 7852 tx_buffer = tx_ring->tx_buffer_info; 7853 tx_desc = IGB_TX_DESC(tx_ring, 0); 7854 } 7855 7856 /* issue prefetch for next Tx descriptor */ 7857 prefetch(tx_desc); 7858 7859 /* update budget accounting */ 7860 budget--; 7861 } while (likely(budget)); 7862 7863 netdev_tx_completed_queue(txring_txq(tx_ring), 7864 total_packets, total_bytes); 7865 i += tx_ring->count; 7866 tx_ring->next_to_clean = i; 7867 u64_stats_update_begin(&tx_ring->tx_syncp); 7868 tx_ring->tx_stats.bytes += total_bytes; 7869 tx_ring->tx_stats.packets += total_packets; 7870 u64_stats_update_end(&tx_ring->tx_syncp); 7871 q_vector->tx.total_bytes += total_bytes; 7872 q_vector->tx.total_packets += total_packets; 7873 7874 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7875 struct e1000_hw *hw = &adapter->hw; 7876 7877 /* Detect a transmit hang in hardware, this serializes the 7878 * check with the clearing of time_stamp and movement of i 7879 */ 7880 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7881 if (tx_buffer->next_to_watch && 7882 time_after(jiffies, tx_buffer->time_stamp + 7883 (adapter->tx_timeout_factor * HZ)) && 7884 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7885 7886 /* detected Tx unit hang */ 7887 dev_err(tx_ring->dev, 7888 "Detected Tx Unit Hang\n" 7889 " Tx Queue <%d>\n" 7890 " TDH <%x>\n" 7891 " TDT <%x>\n" 7892 " next_to_use <%x>\n" 7893 " next_to_clean <%x>\n" 7894 "buffer_info[next_to_clean]\n" 7895 " time_stamp <%lx>\n" 7896 " next_to_watch <%p>\n" 7897 " jiffies <%lx>\n" 7898 " desc.status <%x>\n", 7899 tx_ring->queue_index, 7900 rd32(E1000_TDH(tx_ring->reg_idx)), 7901 readl(tx_ring->tail), 7902 tx_ring->next_to_use, 7903 tx_ring->next_to_clean, 7904 tx_buffer->time_stamp, 7905 tx_buffer->next_to_watch, 7906 jiffies, 7907 tx_buffer->next_to_watch->wb.status); 7908 netif_stop_subqueue(tx_ring->netdev, 7909 tx_ring->queue_index); 7910 7911 /* we are about to reset, no point in enabling stuff */ 7912 return true; 7913 } 7914 } 7915 7916 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7917 if (unlikely(total_packets && 7918 netif_carrier_ok(tx_ring->netdev) && 7919 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7920 /* Make sure that anybody stopping the queue after this 7921 * sees the new next_to_clean. 7922 */ 7923 smp_mb(); 7924 if (__netif_subqueue_stopped(tx_ring->netdev, 7925 tx_ring->queue_index) && 7926 !(test_bit(__IGB_DOWN, &adapter->state))) { 7927 netif_wake_subqueue(tx_ring->netdev, 7928 tx_ring->queue_index); 7929 7930 u64_stats_update_begin(&tx_ring->tx_syncp); 7931 tx_ring->tx_stats.restart_queue++; 7932 u64_stats_update_end(&tx_ring->tx_syncp); 7933 } 7934 } 7935 7936 return !!budget; 7937 } 7938 7939 /** 7940 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7941 * @rx_ring: rx descriptor ring to store buffers on 7942 * @old_buff: donor buffer to have page reused 7943 * 7944 * Synchronizes page for reuse by the adapter 7945 **/ 7946 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7947 struct igb_rx_buffer *old_buff) 7948 { 7949 struct igb_rx_buffer *new_buff; 7950 u16 nta = rx_ring->next_to_alloc; 7951 7952 new_buff = &rx_ring->rx_buffer_info[nta]; 7953 7954 /* update, and store next to alloc */ 7955 nta++; 7956 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7957 7958 /* Transfer page from old buffer to new buffer. 7959 * Move each member individually to avoid possible store 7960 * forwarding stalls. 7961 */ 7962 new_buff->dma = old_buff->dma; 7963 new_buff->page = old_buff->page; 7964 new_buff->page_offset = old_buff->page_offset; 7965 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7966 } 7967 7968 static inline bool igb_page_is_reserved(struct page *page) 7969 { 7970 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7971 } 7972 7973 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7974 { 7975 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7976 struct page *page = rx_buffer->page; 7977 7978 /* avoid re-using remote pages */ 7979 if (unlikely(igb_page_is_reserved(page))) 7980 return false; 7981 7982 #if (PAGE_SIZE < 8192) 7983 /* if we are only owner of page we can reuse it */ 7984 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7985 return false; 7986 #else 7987 #define IGB_LAST_OFFSET \ 7988 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7989 7990 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7991 return false; 7992 #endif 7993 7994 /* If we have drained the page fragment pool we need to update 7995 * the pagecnt_bias and page count so that we fully restock the 7996 * number of references the driver holds. 7997 */ 7998 if (unlikely(!pagecnt_bias)) { 7999 page_ref_add(page, USHRT_MAX); 8000 rx_buffer->pagecnt_bias = USHRT_MAX; 8001 } 8002 8003 return true; 8004 } 8005 8006 /** 8007 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8008 * @rx_ring: rx descriptor ring to transact packets on 8009 * @rx_buffer: buffer containing page to add 8010 * @skb: sk_buff to place the data into 8011 * @size: size of buffer to be added 8012 * 8013 * This function will add the data contained in rx_buffer->page to the skb. 8014 **/ 8015 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8016 struct igb_rx_buffer *rx_buffer, 8017 struct sk_buff *skb, 8018 unsigned int size) 8019 { 8020 #if (PAGE_SIZE < 8192) 8021 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8022 #else 8023 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8024 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8025 SKB_DATA_ALIGN(size); 8026 #endif 8027 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8028 rx_buffer->page_offset, size, truesize); 8029 #if (PAGE_SIZE < 8192) 8030 rx_buffer->page_offset ^= truesize; 8031 #else 8032 rx_buffer->page_offset += truesize; 8033 #endif 8034 } 8035 8036 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8037 struct igb_rx_buffer *rx_buffer, 8038 union e1000_adv_rx_desc *rx_desc, 8039 unsigned int size) 8040 { 8041 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8042 #if (PAGE_SIZE < 8192) 8043 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8044 #else 8045 unsigned int truesize = SKB_DATA_ALIGN(size); 8046 #endif 8047 unsigned int headlen; 8048 struct sk_buff *skb; 8049 8050 /* prefetch first cache line of first page */ 8051 prefetch(va); 8052 #if L1_CACHE_BYTES < 128 8053 prefetch(va + L1_CACHE_BYTES); 8054 #endif 8055 8056 /* allocate a skb to store the frags */ 8057 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8058 if (unlikely(!skb)) 8059 return NULL; 8060 8061 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8062 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 8063 va += IGB_TS_HDR_LEN; 8064 size -= IGB_TS_HDR_LEN; 8065 } 8066 8067 /* Determine available headroom for copy */ 8068 headlen = size; 8069 if (headlen > IGB_RX_HDR_LEN) 8070 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 8071 8072 /* align pull length to size of long to optimize memcpy performance */ 8073 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 8074 8075 /* update all of the pointers */ 8076 size -= headlen; 8077 if (size) { 8078 skb_add_rx_frag(skb, 0, rx_buffer->page, 8079 (va + headlen) - page_address(rx_buffer->page), 8080 size, truesize); 8081 #if (PAGE_SIZE < 8192) 8082 rx_buffer->page_offset ^= truesize; 8083 #else 8084 rx_buffer->page_offset += truesize; 8085 #endif 8086 } else { 8087 rx_buffer->pagecnt_bias++; 8088 } 8089 8090 return skb; 8091 } 8092 8093 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8094 struct igb_rx_buffer *rx_buffer, 8095 union e1000_adv_rx_desc *rx_desc, 8096 unsigned int size) 8097 { 8098 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 8099 #if (PAGE_SIZE < 8192) 8100 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8101 #else 8102 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8103 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 8104 #endif 8105 struct sk_buff *skb; 8106 8107 /* prefetch first cache line of first page */ 8108 prefetch(va); 8109 #if L1_CACHE_BYTES < 128 8110 prefetch(va + L1_CACHE_BYTES); 8111 #endif 8112 8113 /* build an skb around the page buffer */ 8114 skb = build_skb(va - IGB_SKB_PAD, truesize); 8115 if (unlikely(!skb)) 8116 return NULL; 8117 8118 /* update pointers within the skb to store the data */ 8119 skb_reserve(skb, IGB_SKB_PAD); 8120 __skb_put(skb, size); 8121 8122 /* pull timestamp out of packet data */ 8123 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8124 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8125 __skb_pull(skb, IGB_TS_HDR_LEN); 8126 } 8127 8128 /* update buffer offset */ 8129 #if (PAGE_SIZE < 8192) 8130 rx_buffer->page_offset ^= truesize; 8131 #else 8132 rx_buffer->page_offset += truesize; 8133 #endif 8134 8135 return skb; 8136 } 8137 8138 static inline void igb_rx_checksum(struct igb_ring *ring, 8139 union e1000_adv_rx_desc *rx_desc, 8140 struct sk_buff *skb) 8141 { 8142 skb_checksum_none_assert(skb); 8143 8144 /* Ignore Checksum bit is set */ 8145 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8146 return; 8147 8148 /* Rx checksum disabled via ethtool */ 8149 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8150 return; 8151 8152 /* TCP/UDP checksum error bit is set */ 8153 if (igb_test_staterr(rx_desc, 8154 E1000_RXDEXT_STATERR_TCPE | 8155 E1000_RXDEXT_STATERR_IPE)) { 8156 /* work around errata with sctp packets where the TCPE aka 8157 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8158 * packets, (aka let the stack check the crc32c) 8159 */ 8160 if (!((skb->len == 60) && 8161 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8162 u64_stats_update_begin(&ring->rx_syncp); 8163 ring->rx_stats.csum_err++; 8164 u64_stats_update_end(&ring->rx_syncp); 8165 } 8166 /* let the stack verify checksum errors */ 8167 return; 8168 } 8169 /* It must be a TCP or UDP packet with a valid checksum */ 8170 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8171 E1000_RXD_STAT_UDPCS)) 8172 skb->ip_summed = CHECKSUM_UNNECESSARY; 8173 8174 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8175 le32_to_cpu(rx_desc->wb.upper.status_error)); 8176 } 8177 8178 static inline void igb_rx_hash(struct igb_ring *ring, 8179 union e1000_adv_rx_desc *rx_desc, 8180 struct sk_buff *skb) 8181 { 8182 if (ring->netdev->features & NETIF_F_RXHASH) 8183 skb_set_hash(skb, 8184 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8185 PKT_HASH_TYPE_L3); 8186 } 8187 8188 /** 8189 * igb_is_non_eop - process handling of non-EOP buffers 8190 * @rx_ring: Rx ring being processed 8191 * @rx_desc: Rx descriptor for current buffer 8192 * @skb: current socket buffer containing buffer in progress 8193 * 8194 * This function updates next to clean. If the buffer is an EOP buffer 8195 * this function exits returning false, otherwise it will place the 8196 * sk_buff in the next buffer to be chained and return true indicating 8197 * that this is in fact a non-EOP buffer. 8198 **/ 8199 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8200 union e1000_adv_rx_desc *rx_desc) 8201 { 8202 u32 ntc = rx_ring->next_to_clean + 1; 8203 8204 /* fetch, update, and store next to clean */ 8205 ntc = (ntc < rx_ring->count) ? ntc : 0; 8206 rx_ring->next_to_clean = ntc; 8207 8208 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8209 8210 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8211 return false; 8212 8213 return true; 8214 } 8215 8216 /** 8217 * igb_cleanup_headers - Correct corrupted or empty headers 8218 * @rx_ring: rx descriptor ring packet is being transacted on 8219 * @rx_desc: pointer to the EOP Rx descriptor 8220 * @skb: pointer to current skb being fixed 8221 * 8222 * Address the case where we are pulling data in on pages only 8223 * and as such no data is present in the skb header. 8224 * 8225 * In addition if skb is not at least 60 bytes we need to pad it so that 8226 * it is large enough to qualify as a valid Ethernet frame. 8227 * 8228 * Returns true if an error was encountered and skb was freed. 8229 **/ 8230 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8231 union e1000_adv_rx_desc *rx_desc, 8232 struct sk_buff *skb) 8233 { 8234 if (unlikely((igb_test_staterr(rx_desc, 8235 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8236 struct net_device *netdev = rx_ring->netdev; 8237 if (!(netdev->features & NETIF_F_RXALL)) { 8238 dev_kfree_skb_any(skb); 8239 return true; 8240 } 8241 } 8242 8243 /* if eth_skb_pad returns an error the skb was freed */ 8244 if (eth_skb_pad(skb)) 8245 return true; 8246 8247 return false; 8248 } 8249 8250 /** 8251 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8252 * @rx_ring: rx descriptor ring packet is being transacted on 8253 * @rx_desc: pointer to the EOP Rx descriptor 8254 * @skb: pointer to current skb being populated 8255 * 8256 * This function checks the ring, descriptor, and packet information in 8257 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8258 * other fields within the skb. 8259 **/ 8260 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8261 union e1000_adv_rx_desc *rx_desc, 8262 struct sk_buff *skb) 8263 { 8264 struct net_device *dev = rx_ring->netdev; 8265 8266 igb_rx_hash(rx_ring, rx_desc, skb); 8267 8268 igb_rx_checksum(rx_ring, rx_desc, skb); 8269 8270 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8271 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8272 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8273 8274 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8275 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8276 u16 vid; 8277 8278 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8279 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8280 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8281 else 8282 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8283 8284 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8285 } 8286 8287 skb_record_rx_queue(skb, rx_ring->queue_index); 8288 8289 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8290 } 8291 8292 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8293 const unsigned int size) 8294 { 8295 struct igb_rx_buffer *rx_buffer; 8296 8297 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8298 prefetchw(rx_buffer->page); 8299 8300 /* we are reusing so sync this buffer for CPU use */ 8301 dma_sync_single_range_for_cpu(rx_ring->dev, 8302 rx_buffer->dma, 8303 rx_buffer->page_offset, 8304 size, 8305 DMA_FROM_DEVICE); 8306 8307 rx_buffer->pagecnt_bias--; 8308 8309 return rx_buffer; 8310 } 8311 8312 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8313 struct igb_rx_buffer *rx_buffer) 8314 { 8315 if (igb_can_reuse_rx_page(rx_buffer)) { 8316 /* hand second half of page back to the ring */ 8317 igb_reuse_rx_page(rx_ring, rx_buffer); 8318 } else { 8319 /* We are not reusing the buffer so unmap it and free 8320 * any references we are holding to it 8321 */ 8322 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8323 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8324 IGB_RX_DMA_ATTR); 8325 __page_frag_cache_drain(rx_buffer->page, 8326 rx_buffer->pagecnt_bias); 8327 } 8328 8329 /* clear contents of rx_buffer */ 8330 rx_buffer->page = NULL; 8331 } 8332 8333 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8334 { 8335 struct igb_ring *rx_ring = q_vector->rx.ring; 8336 struct sk_buff *skb = rx_ring->skb; 8337 unsigned int total_bytes = 0, total_packets = 0; 8338 u16 cleaned_count = igb_desc_unused(rx_ring); 8339 8340 while (likely(total_packets < budget)) { 8341 union e1000_adv_rx_desc *rx_desc; 8342 struct igb_rx_buffer *rx_buffer; 8343 unsigned int size; 8344 8345 /* return some buffers to hardware, one at a time is too slow */ 8346 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8347 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8348 cleaned_count = 0; 8349 } 8350 8351 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8352 size = le16_to_cpu(rx_desc->wb.upper.length); 8353 if (!size) 8354 break; 8355 8356 /* This memory barrier is needed to keep us from reading 8357 * any other fields out of the rx_desc until we know the 8358 * descriptor has been written back 8359 */ 8360 dma_rmb(); 8361 8362 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8363 8364 /* retrieve a buffer from the ring */ 8365 if (skb) 8366 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8367 else if (ring_uses_build_skb(rx_ring)) 8368 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 8369 else 8370 skb = igb_construct_skb(rx_ring, rx_buffer, 8371 rx_desc, size); 8372 8373 /* exit if we failed to retrieve a buffer */ 8374 if (!skb) { 8375 rx_ring->rx_stats.alloc_failed++; 8376 rx_buffer->pagecnt_bias++; 8377 break; 8378 } 8379 8380 igb_put_rx_buffer(rx_ring, rx_buffer); 8381 cleaned_count++; 8382 8383 /* fetch next buffer in frame if non-eop */ 8384 if (igb_is_non_eop(rx_ring, rx_desc)) 8385 continue; 8386 8387 /* verify the packet layout is correct */ 8388 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8389 skb = NULL; 8390 continue; 8391 } 8392 8393 /* probably a little skewed due to removing CRC */ 8394 total_bytes += skb->len; 8395 8396 /* populate checksum, timestamp, VLAN, and protocol */ 8397 igb_process_skb_fields(rx_ring, rx_desc, skb); 8398 8399 napi_gro_receive(&q_vector->napi, skb); 8400 8401 /* reset skb pointer */ 8402 skb = NULL; 8403 8404 /* update budget accounting */ 8405 total_packets++; 8406 } 8407 8408 /* place incomplete frames back on ring for completion */ 8409 rx_ring->skb = skb; 8410 8411 u64_stats_update_begin(&rx_ring->rx_syncp); 8412 rx_ring->rx_stats.packets += total_packets; 8413 rx_ring->rx_stats.bytes += total_bytes; 8414 u64_stats_update_end(&rx_ring->rx_syncp); 8415 q_vector->rx.total_packets += total_packets; 8416 q_vector->rx.total_bytes += total_bytes; 8417 8418 if (cleaned_count) 8419 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8420 8421 return total_packets; 8422 } 8423 8424 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8425 { 8426 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8427 } 8428 8429 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8430 struct igb_rx_buffer *bi) 8431 { 8432 struct page *page = bi->page; 8433 dma_addr_t dma; 8434 8435 /* since we are recycling buffers we should seldom need to alloc */ 8436 if (likely(page)) 8437 return true; 8438 8439 /* alloc new page for storage */ 8440 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8441 if (unlikely(!page)) { 8442 rx_ring->rx_stats.alloc_failed++; 8443 return false; 8444 } 8445 8446 /* map page for use */ 8447 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8448 igb_rx_pg_size(rx_ring), 8449 DMA_FROM_DEVICE, 8450 IGB_RX_DMA_ATTR); 8451 8452 /* if mapping failed free memory back to system since 8453 * there isn't much point in holding memory we can't use 8454 */ 8455 if (dma_mapping_error(rx_ring->dev, dma)) { 8456 __free_pages(page, igb_rx_pg_order(rx_ring)); 8457 8458 rx_ring->rx_stats.alloc_failed++; 8459 return false; 8460 } 8461 8462 bi->dma = dma; 8463 bi->page = page; 8464 bi->page_offset = igb_rx_offset(rx_ring); 8465 bi->pagecnt_bias = 1; 8466 8467 return true; 8468 } 8469 8470 /** 8471 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8472 * @adapter: address of board private structure 8473 **/ 8474 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8475 { 8476 union e1000_adv_rx_desc *rx_desc; 8477 struct igb_rx_buffer *bi; 8478 u16 i = rx_ring->next_to_use; 8479 u16 bufsz; 8480 8481 /* nothing to do */ 8482 if (!cleaned_count) 8483 return; 8484 8485 rx_desc = IGB_RX_DESC(rx_ring, i); 8486 bi = &rx_ring->rx_buffer_info[i]; 8487 i -= rx_ring->count; 8488 8489 bufsz = igb_rx_bufsz(rx_ring); 8490 8491 do { 8492 if (!igb_alloc_mapped_page(rx_ring, bi)) 8493 break; 8494 8495 /* sync the buffer for use by the device */ 8496 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8497 bi->page_offset, bufsz, 8498 DMA_FROM_DEVICE); 8499 8500 /* Refresh the desc even if buffer_addrs didn't change 8501 * because each write-back erases this info. 8502 */ 8503 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8504 8505 rx_desc++; 8506 bi++; 8507 i++; 8508 if (unlikely(!i)) { 8509 rx_desc = IGB_RX_DESC(rx_ring, 0); 8510 bi = rx_ring->rx_buffer_info; 8511 i -= rx_ring->count; 8512 } 8513 8514 /* clear the length for the next_to_use descriptor */ 8515 rx_desc->wb.upper.length = 0; 8516 8517 cleaned_count--; 8518 } while (cleaned_count); 8519 8520 i += rx_ring->count; 8521 8522 if (rx_ring->next_to_use != i) { 8523 /* record the next descriptor to use */ 8524 rx_ring->next_to_use = i; 8525 8526 /* update next to alloc since we have filled the ring */ 8527 rx_ring->next_to_alloc = i; 8528 8529 /* Force memory writes to complete before letting h/w 8530 * know there are new descriptors to fetch. (Only 8531 * applicable for weak-ordered memory model archs, 8532 * such as IA-64). 8533 */ 8534 wmb(); 8535 writel(i, rx_ring->tail); 8536 } 8537 } 8538 8539 /** 8540 * igb_mii_ioctl - 8541 * @netdev: 8542 * @ifreq: 8543 * @cmd: 8544 **/ 8545 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8546 { 8547 struct igb_adapter *adapter = netdev_priv(netdev); 8548 struct mii_ioctl_data *data = if_mii(ifr); 8549 8550 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8551 return -EOPNOTSUPP; 8552 8553 switch (cmd) { 8554 case SIOCGMIIPHY: 8555 data->phy_id = adapter->hw.phy.addr; 8556 break; 8557 case SIOCGMIIREG: 8558 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8559 &data->val_out)) 8560 return -EIO; 8561 break; 8562 case SIOCSMIIREG: 8563 default: 8564 return -EOPNOTSUPP; 8565 } 8566 return 0; 8567 } 8568 8569 /** 8570 * igb_ioctl - 8571 * @netdev: 8572 * @ifreq: 8573 * @cmd: 8574 **/ 8575 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8576 { 8577 switch (cmd) { 8578 case SIOCGMIIPHY: 8579 case SIOCGMIIREG: 8580 case SIOCSMIIREG: 8581 return igb_mii_ioctl(netdev, ifr, cmd); 8582 case SIOCGHWTSTAMP: 8583 return igb_ptp_get_ts_config(netdev, ifr); 8584 case SIOCSHWTSTAMP: 8585 return igb_ptp_set_ts_config(netdev, ifr); 8586 default: 8587 return -EOPNOTSUPP; 8588 } 8589 } 8590 8591 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8592 { 8593 struct igb_adapter *adapter = hw->back; 8594 8595 pci_read_config_word(adapter->pdev, reg, value); 8596 } 8597 8598 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8599 { 8600 struct igb_adapter *adapter = hw->back; 8601 8602 pci_write_config_word(adapter->pdev, reg, *value); 8603 } 8604 8605 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8606 { 8607 struct igb_adapter *adapter = hw->back; 8608 8609 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8610 return -E1000_ERR_CONFIG; 8611 8612 return 0; 8613 } 8614 8615 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8616 { 8617 struct igb_adapter *adapter = hw->back; 8618 8619 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8620 return -E1000_ERR_CONFIG; 8621 8622 return 0; 8623 } 8624 8625 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8626 { 8627 struct igb_adapter *adapter = netdev_priv(netdev); 8628 struct e1000_hw *hw = &adapter->hw; 8629 u32 ctrl, rctl; 8630 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8631 8632 if (enable) { 8633 /* enable VLAN tag insert/strip */ 8634 ctrl = rd32(E1000_CTRL); 8635 ctrl |= E1000_CTRL_VME; 8636 wr32(E1000_CTRL, ctrl); 8637 8638 /* Disable CFI check */ 8639 rctl = rd32(E1000_RCTL); 8640 rctl &= ~E1000_RCTL_CFIEN; 8641 wr32(E1000_RCTL, rctl); 8642 } else { 8643 /* disable VLAN tag insert/strip */ 8644 ctrl = rd32(E1000_CTRL); 8645 ctrl &= ~E1000_CTRL_VME; 8646 wr32(E1000_CTRL, ctrl); 8647 } 8648 8649 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8650 } 8651 8652 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8653 __be16 proto, u16 vid) 8654 { 8655 struct igb_adapter *adapter = netdev_priv(netdev); 8656 struct e1000_hw *hw = &adapter->hw; 8657 int pf_id = adapter->vfs_allocated_count; 8658 8659 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8660 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8661 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8662 8663 set_bit(vid, adapter->active_vlans); 8664 8665 return 0; 8666 } 8667 8668 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8669 __be16 proto, u16 vid) 8670 { 8671 struct igb_adapter *adapter = netdev_priv(netdev); 8672 int pf_id = adapter->vfs_allocated_count; 8673 struct e1000_hw *hw = &adapter->hw; 8674 8675 /* remove VID from filter table */ 8676 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8677 igb_vfta_set(hw, vid, pf_id, false, true); 8678 8679 clear_bit(vid, adapter->active_vlans); 8680 8681 return 0; 8682 } 8683 8684 static void igb_restore_vlan(struct igb_adapter *adapter) 8685 { 8686 u16 vid = 1; 8687 8688 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8689 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8690 8691 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8692 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8693 } 8694 8695 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8696 { 8697 struct pci_dev *pdev = adapter->pdev; 8698 struct e1000_mac_info *mac = &adapter->hw.mac; 8699 8700 mac->autoneg = 0; 8701 8702 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8703 * for the switch() below to work 8704 */ 8705 if ((spd & 1) || (dplx & ~1)) 8706 goto err_inval; 8707 8708 /* Fiber NIC's only allow 1000 gbps Full duplex 8709 * and 100Mbps Full duplex for 100baseFx sfp 8710 */ 8711 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8712 switch (spd + dplx) { 8713 case SPEED_10 + DUPLEX_HALF: 8714 case SPEED_10 + DUPLEX_FULL: 8715 case SPEED_100 + DUPLEX_HALF: 8716 goto err_inval; 8717 default: 8718 break; 8719 } 8720 } 8721 8722 switch (spd + dplx) { 8723 case SPEED_10 + DUPLEX_HALF: 8724 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8725 break; 8726 case SPEED_10 + DUPLEX_FULL: 8727 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8728 break; 8729 case SPEED_100 + DUPLEX_HALF: 8730 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8731 break; 8732 case SPEED_100 + DUPLEX_FULL: 8733 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8734 break; 8735 case SPEED_1000 + DUPLEX_FULL: 8736 mac->autoneg = 1; 8737 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8738 break; 8739 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8740 default: 8741 goto err_inval; 8742 } 8743 8744 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8745 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8746 8747 return 0; 8748 8749 err_inval: 8750 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8751 return -EINVAL; 8752 } 8753 8754 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8755 bool runtime) 8756 { 8757 struct net_device *netdev = pci_get_drvdata(pdev); 8758 struct igb_adapter *adapter = netdev_priv(netdev); 8759 struct e1000_hw *hw = &adapter->hw; 8760 u32 ctrl, rctl, status; 8761 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8762 #ifdef CONFIG_PM 8763 int retval = 0; 8764 #endif 8765 8766 rtnl_lock(); 8767 netif_device_detach(netdev); 8768 8769 if (netif_running(netdev)) 8770 __igb_close(netdev, true); 8771 8772 igb_ptp_suspend(adapter); 8773 8774 igb_clear_interrupt_scheme(adapter); 8775 rtnl_unlock(); 8776 8777 #ifdef CONFIG_PM 8778 retval = pci_save_state(pdev); 8779 if (retval) 8780 return retval; 8781 #endif 8782 8783 status = rd32(E1000_STATUS); 8784 if (status & E1000_STATUS_LU) 8785 wufc &= ~E1000_WUFC_LNKC; 8786 8787 if (wufc) { 8788 igb_setup_rctl(adapter); 8789 igb_set_rx_mode(netdev); 8790 8791 /* turn on all-multi mode if wake on multicast is enabled */ 8792 if (wufc & E1000_WUFC_MC) { 8793 rctl = rd32(E1000_RCTL); 8794 rctl |= E1000_RCTL_MPE; 8795 wr32(E1000_RCTL, rctl); 8796 } 8797 8798 ctrl = rd32(E1000_CTRL); 8799 /* advertise wake from D3Cold */ 8800 #define E1000_CTRL_ADVD3WUC 0x00100000 8801 /* phy power management enable */ 8802 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 8803 ctrl |= E1000_CTRL_ADVD3WUC; 8804 wr32(E1000_CTRL, ctrl); 8805 8806 /* Allow time for pending master requests to run */ 8807 igb_disable_pcie_master(hw); 8808 8809 wr32(E1000_WUC, E1000_WUC_PME_EN); 8810 wr32(E1000_WUFC, wufc); 8811 } else { 8812 wr32(E1000_WUC, 0); 8813 wr32(E1000_WUFC, 0); 8814 } 8815 8816 *enable_wake = wufc || adapter->en_mng_pt; 8817 if (!*enable_wake) 8818 igb_power_down_link(adapter); 8819 else 8820 igb_power_up_link(adapter); 8821 8822 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8823 * would have already happened in close and is redundant. 8824 */ 8825 igb_release_hw_control(adapter); 8826 8827 pci_disable_device(pdev); 8828 8829 return 0; 8830 } 8831 8832 static void igb_deliver_wake_packet(struct net_device *netdev) 8833 { 8834 struct igb_adapter *adapter = netdev_priv(netdev); 8835 struct e1000_hw *hw = &adapter->hw; 8836 struct sk_buff *skb; 8837 u32 wupl; 8838 8839 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8840 8841 /* WUPM stores only the first 128 bytes of the wake packet. 8842 * Read the packet only if we have the whole thing. 8843 */ 8844 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8845 return; 8846 8847 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8848 if (!skb) 8849 return; 8850 8851 skb_put(skb, wupl); 8852 8853 /* Ensure reads are 32-bit aligned */ 8854 wupl = roundup(wupl, 4); 8855 8856 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8857 8858 skb->protocol = eth_type_trans(skb, netdev); 8859 netif_rx(skb); 8860 } 8861 8862 static int __maybe_unused igb_suspend(struct device *dev) 8863 { 8864 int retval; 8865 bool wake; 8866 struct pci_dev *pdev = to_pci_dev(dev); 8867 8868 retval = __igb_shutdown(pdev, &wake, 0); 8869 if (retval) 8870 return retval; 8871 8872 if (wake) { 8873 pci_prepare_to_sleep(pdev); 8874 } else { 8875 pci_wake_from_d3(pdev, false); 8876 pci_set_power_state(pdev, PCI_D3hot); 8877 } 8878 8879 return 0; 8880 } 8881 8882 static int __maybe_unused igb_resume(struct device *dev) 8883 { 8884 struct pci_dev *pdev = to_pci_dev(dev); 8885 struct net_device *netdev = pci_get_drvdata(pdev); 8886 struct igb_adapter *adapter = netdev_priv(netdev); 8887 struct e1000_hw *hw = &adapter->hw; 8888 u32 err, val; 8889 8890 pci_set_power_state(pdev, PCI_D0); 8891 pci_restore_state(pdev); 8892 pci_save_state(pdev); 8893 8894 if (!pci_device_is_present(pdev)) 8895 return -ENODEV; 8896 err = pci_enable_device_mem(pdev); 8897 if (err) { 8898 dev_err(&pdev->dev, 8899 "igb: Cannot enable PCI device from suspend\n"); 8900 return err; 8901 } 8902 pci_set_master(pdev); 8903 8904 pci_enable_wake(pdev, PCI_D3hot, 0); 8905 pci_enable_wake(pdev, PCI_D3cold, 0); 8906 8907 if (igb_init_interrupt_scheme(adapter, true)) { 8908 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8909 return -ENOMEM; 8910 } 8911 8912 igb_reset(adapter); 8913 8914 /* let the f/w know that the h/w is now under the control of the 8915 * driver. 8916 */ 8917 igb_get_hw_control(adapter); 8918 8919 val = rd32(E1000_WUS); 8920 if (val & WAKE_PKT_WUS) 8921 igb_deliver_wake_packet(netdev); 8922 8923 wr32(E1000_WUS, ~0); 8924 8925 rtnl_lock(); 8926 if (!err && netif_running(netdev)) 8927 err = __igb_open(netdev, true); 8928 8929 if (!err) 8930 netif_device_attach(netdev); 8931 rtnl_unlock(); 8932 8933 return err; 8934 } 8935 8936 static int __maybe_unused igb_runtime_idle(struct device *dev) 8937 { 8938 struct pci_dev *pdev = to_pci_dev(dev); 8939 struct net_device *netdev = pci_get_drvdata(pdev); 8940 struct igb_adapter *adapter = netdev_priv(netdev); 8941 8942 if (!igb_has_link(adapter)) 8943 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8944 8945 return -EBUSY; 8946 } 8947 8948 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8949 { 8950 struct pci_dev *pdev = to_pci_dev(dev); 8951 int retval; 8952 bool wake; 8953 8954 retval = __igb_shutdown(pdev, &wake, 1); 8955 if (retval) 8956 return retval; 8957 8958 if (wake) { 8959 pci_prepare_to_sleep(pdev); 8960 } else { 8961 pci_wake_from_d3(pdev, false); 8962 pci_set_power_state(pdev, PCI_D3hot); 8963 } 8964 8965 return 0; 8966 } 8967 8968 static int __maybe_unused igb_runtime_resume(struct device *dev) 8969 { 8970 return igb_resume(dev); 8971 } 8972 8973 static void igb_shutdown(struct pci_dev *pdev) 8974 { 8975 bool wake; 8976 8977 __igb_shutdown(pdev, &wake, 0); 8978 8979 if (system_state == SYSTEM_POWER_OFF) { 8980 pci_wake_from_d3(pdev, wake); 8981 pci_set_power_state(pdev, PCI_D3hot); 8982 } 8983 } 8984 8985 #ifdef CONFIG_PCI_IOV 8986 static int igb_sriov_reinit(struct pci_dev *dev) 8987 { 8988 struct net_device *netdev = pci_get_drvdata(dev); 8989 struct igb_adapter *adapter = netdev_priv(netdev); 8990 struct pci_dev *pdev = adapter->pdev; 8991 8992 rtnl_lock(); 8993 8994 if (netif_running(netdev)) 8995 igb_close(netdev); 8996 else 8997 igb_reset(adapter); 8998 8999 igb_clear_interrupt_scheme(adapter); 9000 9001 igb_init_queue_configuration(adapter); 9002 9003 if (igb_init_interrupt_scheme(adapter, true)) { 9004 rtnl_unlock(); 9005 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9006 return -ENOMEM; 9007 } 9008 9009 if (netif_running(netdev)) 9010 igb_open(netdev); 9011 9012 rtnl_unlock(); 9013 9014 return 0; 9015 } 9016 9017 static int igb_pci_disable_sriov(struct pci_dev *dev) 9018 { 9019 int err = igb_disable_sriov(dev); 9020 9021 if (!err) 9022 err = igb_sriov_reinit(dev); 9023 9024 return err; 9025 } 9026 9027 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9028 { 9029 int err = igb_enable_sriov(dev, num_vfs); 9030 9031 if (err) 9032 goto out; 9033 9034 err = igb_sriov_reinit(dev); 9035 if (!err) 9036 return num_vfs; 9037 9038 out: 9039 return err; 9040 } 9041 9042 #endif 9043 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9044 { 9045 #ifdef CONFIG_PCI_IOV 9046 if (num_vfs == 0) 9047 return igb_pci_disable_sriov(dev); 9048 else 9049 return igb_pci_enable_sriov(dev, num_vfs); 9050 #endif 9051 return 0; 9052 } 9053 9054 #ifdef CONFIG_NET_POLL_CONTROLLER 9055 /* Polling 'interrupt' - used by things like netconsole to send skbs 9056 * without having to re-enable interrupts. It's not called while 9057 * the interrupt routine is executing. 9058 */ 9059 static void igb_netpoll(struct net_device *netdev) 9060 { 9061 struct igb_adapter *adapter = netdev_priv(netdev); 9062 struct e1000_hw *hw = &adapter->hw; 9063 struct igb_q_vector *q_vector; 9064 int i; 9065 9066 for (i = 0; i < adapter->num_q_vectors; i++) { 9067 q_vector = adapter->q_vector[i]; 9068 if (adapter->flags & IGB_FLAG_HAS_MSIX) 9069 wr32(E1000_EIMC, q_vector->eims_value); 9070 else 9071 igb_irq_disable(adapter); 9072 napi_schedule(&q_vector->napi); 9073 } 9074 } 9075 #endif /* CONFIG_NET_POLL_CONTROLLER */ 9076 9077 /** 9078 * igb_io_error_detected - called when PCI error is detected 9079 * @pdev: Pointer to PCI device 9080 * @state: The current pci connection state 9081 * 9082 * This function is called after a PCI bus error affecting 9083 * this device has been detected. 9084 **/ 9085 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9086 pci_channel_state_t state) 9087 { 9088 struct net_device *netdev = pci_get_drvdata(pdev); 9089 struct igb_adapter *adapter = netdev_priv(netdev); 9090 9091 netif_device_detach(netdev); 9092 9093 if (state == pci_channel_io_perm_failure) 9094 return PCI_ERS_RESULT_DISCONNECT; 9095 9096 if (netif_running(netdev)) 9097 igb_down(adapter); 9098 pci_disable_device(pdev); 9099 9100 /* Request a slot slot reset. */ 9101 return PCI_ERS_RESULT_NEED_RESET; 9102 } 9103 9104 /** 9105 * igb_io_slot_reset - called after the pci bus has been reset. 9106 * @pdev: Pointer to PCI device 9107 * 9108 * Restart the card from scratch, as if from a cold-boot. Implementation 9109 * resembles the first-half of the igb_resume routine. 9110 **/ 9111 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9112 { 9113 struct net_device *netdev = pci_get_drvdata(pdev); 9114 struct igb_adapter *adapter = netdev_priv(netdev); 9115 struct e1000_hw *hw = &adapter->hw; 9116 pci_ers_result_t result; 9117 int err; 9118 9119 if (pci_enable_device_mem(pdev)) { 9120 dev_err(&pdev->dev, 9121 "Cannot re-enable PCI device after reset.\n"); 9122 result = PCI_ERS_RESULT_DISCONNECT; 9123 } else { 9124 pci_set_master(pdev); 9125 pci_restore_state(pdev); 9126 pci_save_state(pdev); 9127 9128 pci_enable_wake(pdev, PCI_D3hot, 0); 9129 pci_enable_wake(pdev, PCI_D3cold, 0); 9130 9131 /* In case of PCI error, adapter lose its HW address 9132 * so we should re-assign it here. 9133 */ 9134 hw->hw_addr = adapter->io_addr; 9135 9136 igb_reset(adapter); 9137 wr32(E1000_WUS, ~0); 9138 result = PCI_ERS_RESULT_RECOVERED; 9139 } 9140 9141 err = pci_cleanup_aer_uncorrect_error_status(pdev); 9142 if (err) { 9143 dev_err(&pdev->dev, 9144 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 9145 err); 9146 /* non-fatal, continue */ 9147 } 9148 9149 return result; 9150 } 9151 9152 /** 9153 * igb_io_resume - called when traffic can start flowing again. 9154 * @pdev: Pointer to PCI device 9155 * 9156 * This callback is called when the error recovery driver tells us that 9157 * its OK to resume normal operation. Implementation resembles the 9158 * second-half of the igb_resume routine. 9159 */ 9160 static void igb_io_resume(struct pci_dev *pdev) 9161 { 9162 struct net_device *netdev = pci_get_drvdata(pdev); 9163 struct igb_adapter *adapter = netdev_priv(netdev); 9164 9165 if (netif_running(netdev)) { 9166 if (igb_up(adapter)) { 9167 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9168 return; 9169 } 9170 } 9171 9172 netif_device_attach(netdev); 9173 9174 /* let the f/w know that the h/w is now under the control of the 9175 * driver. 9176 */ 9177 igb_get_hw_control(adapter); 9178 } 9179 9180 /** 9181 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9182 * @adapter: Pointer to adapter structure 9183 * @index: Index of the RAR entry which need to be synced with MAC table 9184 **/ 9185 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9186 { 9187 struct e1000_hw *hw = &adapter->hw; 9188 u32 rar_low, rar_high; 9189 u8 *addr = adapter->mac_table[index].addr; 9190 9191 /* HW expects these to be in network order when they are plugged 9192 * into the registers which are little endian. In order to guarantee 9193 * that ordering we need to do an leXX_to_cpup here in order to be 9194 * ready for the byteswap that occurs with writel 9195 */ 9196 rar_low = le32_to_cpup((__le32 *)(addr)); 9197 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9198 9199 /* Indicate to hardware the Address is Valid. */ 9200 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9201 if (is_valid_ether_addr(addr)) 9202 rar_high |= E1000_RAH_AV; 9203 9204 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9205 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9206 9207 switch (hw->mac.type) { 9208 case e1000_82575: 9209 case e1000_i210: 9210 if (adapter->mac_table[index].state & 9211 IGB_MAC_STATE_QUEUE_STEERING) 9212 rar_high |= E1000_RAH_QSEL_ENABLE; 9213 9214 rar_high |= E1000_RAH_POOL_1 * 9215 adapter->mac_table[index].queue; 9216 break; 9217 default: 9218 rar_high |= E1000_RAH_POOL_1 << 9219 adapter->mac_table[index].queue; 9220 break; 9221 } 9222 } 9223 9224 wr32(E1000_RAL(index), rar_low); 9225 wrfl(); 9226 wr32(E1000_RAH(index), rar_high); 9227 wrfl(); 9228 } 9229 9230 static int igb_set_vf_mac(struct igb_adapter *adapter, 9231 int vf, unsigned char *mac_addr) 9232 { 9233 struct e1000_hw *hw = &adapter->hw; 9234 /* VF MAC addresses start at end of receive addresses and moves 9235 * towards the first, as a result a collision should not be possible 9236 */ 9237 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9238 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9239 9240 ether_addr_copy(vf_mac_addr, mac_addr); 9241 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9242 adapter->mac_table[rar_entry].queue = vf; 9243 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9244 igb_rar_set_index(adapter, rar_entry); 9245 9246 return 0; 9247 } 9248 9249 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9250 { 9251 struct igb_adapter *adapter = netdev_priv(netdev); 9252 9253 if (vf >= adapter->vfs_allocated_count) 9254 return -EINVAL; 9255 9256 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9257 * flag and allows to overwrite the MAC via VF netdev. This 9258 * is necessary to allow libvirt a way to restore the original 9259 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9260 * down a VM. 9261 */ 9262 if (is_zero_ether_addr(mac)) { 9263 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9264 dev_info(&adapter->pdev->dev, 9265 "remove administratively set MAC on VF %d\n", 9266 vf); 9267 } else if (is_valid_ether_addr(mac)) { 9268 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9269 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9270 mac, vf); 9271 dev_info(&adapter->pdev->dev, 9272 "Reload the VF driver to make this change effective."); 9273 /* Generate additional warning if PF is down */ 9274 if (test_bit(__IGB_DOWN, &adapter->state)) { 9275 dev_warn(&adapter->pdev->dev, 9276 "The VF MAC address has been set, but the PF device is not up.\n"); 9277 dev_warn(&adapter->pdev->dev, 9278 "Bring the PF device up before attempting to use the VF device.\n"); 9279 } 9280 } else { 9281 return -EINVAL; 9282 } 9283 return igb_set_vf_mac(adapter, vf, mac); 9284 } 9285 9286 static int igb_link_mbps(int internal_link_speed) 9287 { 9288 switch (internal_link_speed) { 9289 case SPEED_100: 9290 return 100; 9291 case SPEED_1000: 9292 return 1000; 9293 default: 9294 return 0; 9295 } 9296 } 9297 9298 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9299 int link_speed) 9300 { 9301 int rf_dec, rf_int; 9302 u32 bcnrc_val; 9303 9304 if (tx_rate != 0) { 9305 /* Calculate the rate factor values to set */ 9306 rf_int = link_speed / tx_rate; 9307 rf_dec = (link_speed - (rf_int * tx_rate)); 9308 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9309 tx_rate; 9310 9311 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9312 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9313 E1000_RTTBCNRC_RF_INT_MASK); 9314 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9315 } else { 9316 bcnrc_val = 0; 9317 } 9318 9319 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9320 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9321 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9322 */ 9323 wr32(E1000_RTTBCNRM, 0x14); 9324 wr32(E1000_RTTBCNRC, bcnrc_val); 9325 } 9326 9327 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9328 { 9329 int actual_link_speed, i; 9330 bool reset_rate = false; 9331 9332 /* VF TX rate limit was not set or not supported */ 9333 if ((adapter->vf_rate_link_speed == 0) || 9334 (adapter->hw.mac.type != e1000_82576)) 9335 return; 9336 9337 actual_link_speed = igb_link_mbps(adapter->link_speed); 9338 if (actual_link_speed != adapter->vf_rate_link_speed) { 9339 reset_rate = true; 9340 adapter->vf_rate_link_speed = 0; 9341 dev_info(&adapter->pdev->dev, 9342 "Link speed has been changed. VF Transmit rate is disabled\n"); 9343 } 9344 9345 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9346 if (reset_rate) 9347 adapter->vf_data[i].tx_rate = 0; 9348 9349 igb_set_vf_rate_limit(&adapter->hw, i, 9350 adapter->vf_data[i].tx_rate, 9351 actual_link_speed); 9352 } 9353 } 9354 9355 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9356 int min_tx_rate, int max_tx_rate) 9357 { 9358 struct igb_adapter *adapter = netdev_priv(netdev); 9359 struct e1000_hw *hw = &adapter->hw; 9360 int actual_link_speed; 9361 9362 if (hw->mac.type != e1000_82576) 9363 return -EOPNOTSUPP; 9364 9365 if (min_tx_rate) 9366 return -EINVAL; 9367 9368 actual_link_speed = igb_link_mbps(adapter->link_speed); 9369 if ((vf >= adapter->vfs_allocated_count) || 9370 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9371 (max_tx_rate < 0) || 9372 (max_tx_rate > actual_link_speed)) 9373 return -EINVAL; 9374 9375 adapter->vf_rate_link_speed = actual_link_speed; 9376 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9377 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9378 9379 return 0; 9380 } 9381 9382 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9383 bool setting) 9384 { 9385 struct igb_adapter *adapter = netdev_priv(netdev); 9386 struct e1000_hw *hw = &adapter->hw; 9387 u32 reg_val, reg_offset; 9388 9389 if (!adapter->vfs_allocated_count) 9390 return -EOPNOTSUPP; 9391 9392 if (vf >= adapter->vfs_allocated_count) 9393 return -EINVAL; 9394 9395 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9396 reg_val = rd32(reg_offset); 9397 if (setting) 9398 reg_val |= (BIT(vf) | 9399 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9400 else 9401 reg_val &= ~(BIT(vf) | 9402 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9403 wr32(reg_offset, reg_val); 9404 9405 adapter->vf_data[vf].spoofchk_enabled = setting; 9406 return 0; 9407 } 9408 9409 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9410 { 9411 struct igb_adapter *adapter = netdev_priv(netdev); 9412 9413 if (vf >= adapter->vfs_allocated_count) 9414 return -EINVAL; 9415 if (adapter->vf_data[vf].trusted == setting) 9416 return 0; 9417 9418 adapter->vf_data[vf].trusted = setting; 9419 9420 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9421 vf, setting ? "" : "not "); 9422 return 0; 9423 } 9424 9425 static int igb_ndo_get_vf_config(struct net_device *netdev, 9426 int vf, struct ifla_vf_info *ivi) 9427 { 9428 struct igb_adapter *adapter = netdev_priv(netdev); 9429 if (vf >= adapter->vfs_allocated_count) 9430 return -EINVAL; 9431 ivi->vf = vf; 9432 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9433 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9434 ivi->min_tx_rate = 0; 9435 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9436 ivi->qos = adapter->vf_data[vf].pf_qos; 9437 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9438 ivi->trusted = adapter->vf_data[vf].trusted; 9439 return 0; 9440 } 9441 9442 static void igb_vmm_control(struct igb_adapter *adapter) 9443 { 9444 struct e1000_hw *hw = &adapter->hw; 9445 u32 reg; 9446 9447 switch (hw->mac.type) { 9448 case e1000_82575: 9449 case e1000_i210: 9450 case e1000_i211: 9451 case e1000_i354: 9452 default: 9453 /* replication is not supported for 82575 */ 9454 return; 9455 case e1000_82576: 9456 /* notify HW that the MAC is adding vlan tags */ 9457 reg = rd32(E1000_DTXCTL); 9458 reg |= E1000_DTXCTL_VLAN_ADDED; 9459 wr32(E1000_DTXCTL, reg); 9460 /* Fall through */ 9461 case e1000_82580: 9462 /* enable replication vlan tag stripping */ 9463 reg = rd32(E1000_RPLOLR); 9464 reg |= E1000_RPLOLR_STRVLAN; 9465 wr32(E1000_RPLOLR, reg); 9466 /* Fall through */ 9467 case e1000_i350: 9468 /* none of the above registers are supported by i350 */ 9469 break; 9470 } 9471 9472 if (adapter->vfs_allocated_count) { 9473 igb_vmdq_set_loopback_pf(hw, true); 9474 igb_vmdq_set_replication_pf(hw, true); 9475 igb_vmdq_set_anti_spoofing_pf(hw, true, 9476 adapter->vfs_allocated_count); 9477 } else { 9478 igb_vmdq_set_loopback_pf(hw, false); 9479 igb_vmdq_set_replication_pf(hw, false); 9480 } 9481 } 9482 9483 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9484 { 9485 struct e1000_hw *hw = &adapter->hw; 9486 u32 dmac_thr; 9487 u16 hwm; 9488 9489 if (hw->mac.type > e1000_82580) { 9490 if (adapter->flags & IGB_FLAG_DMAC) { 9491 u32 reg; 9492 9493 /* force threshold to 0. */ 9494 wr32(E1000_DMCTXTH, 0); 9495 9496 /* DMA Coalescing high water mark needs to be greater 9497 * than the Rx threshold. Set hwm to PBA - max frame 9498 * size in 16B units, capping it at PBA - 6KB. 9499 */ 9500 hwm = 64 * (pba - 6); 9501 reg = rd32(E1000_FCRTC); 9502 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9503 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9504 & E1000_FCRTC_RTH_COAL_MASK); 9505 wr32(E1000_FCRTC, reg); 9506 9507 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9508 * frame size, capping it at PBA - 10KB. 9509 */ 9510 dmac_thr = pba - 10; 9511 reg = rd32(E1000_DMACR); 9512 reg &= ~E1000_DMACR_DMACTHR_MASK; 9513 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9514 & E1000_DMACR_DMACTHR_MASK); 9515 9516 /* transition to L0x or L1 if available..*/ 9517 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9518 9519 /* watchdog timer= +-1000 usec in 32usec intervals */ 9520 reg |= (1000 >> 5); 9521 9522 /* Disable BMC-to-OS Watchdog Enable */ 9523 if (hw->mac.type != e1000_i354) 9524 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9525 9526 wr32(E1000_DMACR, reg); 9527 9528 /* no lower threshold to disable 9529 * coalescing(smart fifb)-UTRESH=0 9530 */ 9531 wr32(E1000_DMCRTRH, 0); 9532 9533 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9534 9535 wr32(E1000_DMCTLX, reg); 9536 9537 /* free space in tx packet buffer to wake from 9538 * DMA coal 9539 */ 9540 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9541 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9542 9543 /* make low power state decision controlled 9544 * by DMA coal 9545 */ 9546 reg = rd32(E1000_PCIEMISC); 9547 reg &= ~E1000_PCIEMISC_LX_DECISION; 9548 wr32(E1000_PCIEMISC, reg); 9549 } /* endif adapter->dmac is not disabled */ 9550 } else if (hw->mac.type == e1000_82580) { 9551 u32 reg = rd32(E1000_PCIEMISC); 9552 9553 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9554 wr32(E1000_DMACR, 0); 9555 } 9556 } 9557 9558 /** 9559 * igb_read_i2c_byte - Reads 8 bit word over I2C 9560 * @hw: pointer to hardware structure 9561 * @byte_offset: byte offset to read 9562 * @dev_addr: device address 9563 * @data: value read 9564 * 9565 * Performs byte read operation over I2C interface at 9566 * a specified device address. 9567 **/ 9568 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9569 u8 dev_addr, u8 *data) 9570 { 9571 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9572 struct i2c_client *this_client = adapter->i2c_client; 9573 s32 status; 9574 u16 swfw_mask = 0; 9575 9576 if (!this_client) 9577 return E1000_ERR_I2C; 9578 9579 swfw_mask = E1000_SWFW_PHY0_SM; 9580 9581 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9582 return E1000_ERR_SWFW_SYNC; 9583 9584 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9585 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9586 9587 if (status < 0) 9588 return E1000_ERR_I2C; 9589 else { 9590 *data = status; 9591 return 0; 9592 } 9593 } 9594 9595 /** 9596 * igb_write_i2c_byte - Writes 8 bit word over I2C 9597 * @hw: pointer to hardware structure 9598 * @byte_offset: byte offset to write 9599 * @dev_addr: device address 9600 * @data: value to write 9601 * 9602 * Performs byte write operation over I2C interface at 9603 * a specified device address. 9604 **/ 9605 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9606 u8 dev_addr, u8 data) 9607 { 9608 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9609 struct i2c_client *this_client = adapter->i2c_client; 9610 s32 status; 9611 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9612 9613 if (!this_client) 9614 return E1000_ERR_I2C; 9615 9616 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9617 return E1000_ERR_SWFW_SYNC; 9618 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9619 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9620 9621 if (status) 9622 return E1000_ERR_I2C; 9623 else 9624 return 0; 9625 9626 } 9627 9628 int igb_reinit_queues(struct igb_adapter *adapter) 9629 { 9630 struct net_device *netdev = adapter->netdev; 9631 struct pci_dev *pdev = adapter->pdev; 9632 int err = 0; 9633 9634 if (netif_running(netdev)) 9635 igb_close(netdev); 9636 9637 igb_reset_interrupt_capability(adapter); 9638 9639 if (igb_init_interrupt_scheme(adapter, true)) { 9640 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9641 return -ENOMEM; 9642 } 9643 9644 if (netif_running(netdev)) 9645 err = igb_open(netdev); 9646 9647 return err; 9648 } 9649 9650 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9651 { 9652 struct igb_nfc_filter *rule; 9653 9654 spin_lock(&adapter->nfc_lock); 9655 9656 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9657 igb_erase_filter(adapter, rule); 9658 9659 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9660 igb_erase_filter(adapter, rule); 9661 9662 spin_unlock(&adapter->nfc_lock); 9663 } 9664 9665 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9666 { 9667 struct igb_nfc_filter *rule; 9668 9669 spin_lock(&adapter->nfc_lock); 9670 9671 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9672 igb_add_filter(adapter, rule); 9673 9674 spin_unlock(&adapter->nfc_lock); 9675 } 9676 /* igb_main.c */ 9677