1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #ifdef CONFIG_IGB_DCA 54 #include <linux/dca.h> 55 #endif 56 #include <linux/i2c.h> 57 #include "igb.h" 58 59 #define MAJ 5 60 #define MIN 3 61 #define BUILD 0 62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 63 __stringify(BUILD) "-k" 64 char igb_driver_name[] = "igb"; 65 char igb_driver_version[] = DRV_VERSION; 66 static const char igb_driver_string[] = 67 "Intel(R) Gigabit Ethernet Network Driver"; 68 static const char igb_copyright[] = 69 "Copyright (c) 2007-2014 Intel Corporation."; 70 71 static const struct e1000_info *igb_info_tbl[] = { 72 [board_82575] = &e1000_82575_info, 73 }; 74 75 static const struct pci_device_id igb_pci_tbl[] = { 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 111 /* required last entry */ 112 {0, } 113 }; 114 115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 116 117 static int igb_setup_all_tx_resources(struct igb_adapter *); 118 static int igb_setup_all_rx_resources(struct igb_adapter *); 119 static void igb_free_all_tx_resources(struct igb_adapter *); 120 static void igb_free_all_rx_resources(struct igb_adapter *); 121 static void igb_setup_mrqc(struct igb_adapter *); 122 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 123 static void igb_remove(struct pci_dev *pdev); 124 static int igb_sw_init(struct igb_adapter *); 125 static int igb_open(struct net_device *); 126 static int igb_close(struct net_device *); 127 static void igb_configure(struct igb_adapter *); 128 static void igb_configure_tx(struct igb_adapter *); 129 static void igb_configure_rx(struct igb_adapter *); 130 static void igb_clean_all_tx_rings(struct igb_adapter *); 131 static void igb_clean_all_rx_rings(struct igb_adapter *); 132 static void igb_clean_tx_ring(struct igb_ring *); 133 static void igb_clean_rx_ring(struct igb_ring *); 134 static void igb_set_rx_mode(struct net_device *); 135 static void igb_update_phy_info(unsigned long); 136 static void igb_watchdog(unsigned long); 137 static void igb_watchdog_task(struct work_struct *); 138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 140 struct rtnl_link_stats64 *stats); 141 static int igb_change_mtu(struct net_device *, int); 142 static int igb_set_mac(struct net_device *, void *); 143 static void igb_set_uta(struct igb_adapter *adapter); 144 static irqreturn_t igb_intr(int irq, void *); 145 static irqreturn_t igb_intr_msi(int irq, void *); 146 static irqreturn_t igb_msix_other(int irq, void *); 147 static irqreturn_t igb_msix_ring(int irq, void *); 148 #ifdef CONFIG_IGB_DCA 149 static void igb_update_dca(struct igb_q_vector *); 150 static void igb_setup_dca(struct igb_adapter *); 151 #endif /* CONFIG_IGB_DCA */ 152 static int igb_poll(struct napi_struct *, int); 153 static bool igb_clean_tx_irq(struct igb_q_vector *); 154 static int igb_clean_rx_irq(struct igb_q_vector *, int); 155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 156 static void igb_tx_timeout(struct net_device *); 157 static void igb_reset_task(struct work_struct *); 158 static void igb_vlan_mode(struct net_device *netdev, 159 netdev_features_t features); 160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 162 static void igb_restore_vlan(struct igb_adapter *); 163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 164 static void igb_ping_all_vfs(struct igb_adapter *); 165 static void igb_msg_task(struct igb_adapter *); 166 static void igb_vmm_control(struct igb_adapter *); 167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 170 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 171 int vf, u16 vlan, u8 qos); 172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 174 bool setting); 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177 static void igb_check_vf_rate_limit(struct igb_adapter *); 178 179 #ifdef CONFIG_PCI_IOV 180 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 182 static int igb_disable_sriov(struct pci_dev *dev); 183 static int igb_pci_disable_sriov(struct pci_dev *dev); 184 #endif 185 186 #ifdef CONFIG_PM 187 #ifdef CONFIG_PM_SLEEP 188 static int igb_suspend(struct device *); 189 #endif 190 static int igb_resume(struct device *); 191 static int igb_runtime_suspend(struct device *dev); 192 static int igb_runtime_resume(struct device *dev); 193 static int igb_runtime_idle(struct device *dev); 194 static const struct dev_pm_ops igb_pm_ops = { 195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 197 igb_runtime_idle) 198 }; 199 #endif 200 static void igb_shutdown(struct pci_dev *); 201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 202 #ifdef CONFIG_IGB_DCA 203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 204 static struct notifier_block dca_notifier = { 205 .notifier_call = igb_notify_dca, 206 .next = NULL, 207 .priority = 0 208 }; 209 #endif 210 #ifdef CONFIG_NET_POLL_CONTROLLER 211 /* for netdump / net console */ 212 static void igb_netpoll(struct net_device *); 213 #endif 214 #ifdef CONFIG_PCI_IOV 215 static unsigned int max_vfs; 216 module_param(max_vfs, uint, 0); 217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 218 #endif /* CONFIG_PCI_IOV */ 219 220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 221 pci_channel_state_t); 222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 223 static void igb_io_resume(struct pci_dev *); 224 225 static const struct pci_error_handlers igb_err_handler = { 226 .error_detected = igb_io_error_detected, 227 .slot_reset = igb_io_slot_reset, 228 .resume = igb_io_resume, 229 }; 230 231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 232 233 static struct pci_driver igb_driver = { 234 .name = igb_driver_name, 235 .id_table = igb_pci_tbl, 236 .probe = igb_probe, 237 .remove = igb_remove, 238 #ifdef CONFIG_PM 239 .driver.pm = &igb_pm_ops, 240 #endif 241 .shutdown = igb_shutdown, 242 .sriov_configure = igb_pci_sriov_configure, 243 .err_handler = &igb_err_handler 244 }; 245 246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 248 MODULE_LICENSE("GPL"); 249 MODULE_VERSION(DRV_VERSION); 250 251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 252 static int debug = -1; 253 module_param(debug, int, 0); 254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 255 256 struct igb_reg_info { 257 u32 ofs; 258 char *name; 259 }; 260 261 static const struct igb_reg_info igb_reg_info_tbl[] = { 262 263 /* General Registers */ 264 {E1000_CTRL, "CTRL"}, 265 {E1000_STATUS, "STATUS"}, 266 {E1000_CTRL_EXT, "CTRL_EXT"}, 267 268 /* Interrupt Registers */ 269 {E1000_ICR, "ICR"}, 270 271 /* RX Registers */ 272 {E1000_RCTL, "RCTL"}, 273 {E1000_RDLEN(0), "RDLEN"}, 274 {E1000_RDH(0), "RDH"}, 275 {E1000_RDT(0), "RDT"}, 276 {E1000_RXDCTL(0), "RXDCTL"}, 277 {E1000_RDBAL(0), "RDBAL"}, 278 {E1000_RDBAH(0), "RDBAH"}, 279 280 /* TX Registers */ 281 {E1000_TCTL, "TCTL"}, 282 {E1000_TDBAL(0), "TDBAL"}, 283 {E1000_TDBAH(0), "TDBAH"}, 284 {E1000_TDLEN(0), "TDLEN"}, 285 {E1000_TDH(0), "TDH"}, 286 {E1000_TDT(0), "TDT"}, 287 {E1000_TXDCTL(0), "TXDCTL"}, 288 {E1000_TDFH, "TDFH"}, 289 {E1000_TDFT, "TDFT"}, 290 {E1000_TDFHS, "TDFHS"}, 291 {E1000_TDFPC, "TDFPC"}, 292 293 /* List Terminator */ 294 {} 295 }; 296 297 /* igb_regdump - register printout routine */ 298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 299 { 300 int n = 0; 301 char rname[16]; 302 u32 regs[8]; 303 304 switch (reginfo->ofs) { 305 case E1000_RDLEN(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RDLEN(n)); 308 break; 309 case E1000_RDH(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDH(n)); 312 break; 313 case E1000_RDT(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDT(n)); 316 break; 317 case E1000_RXDCTL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RXDCTL(n)); 320 break; 321 case E1000_RDBAL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RDBAL(n)); 324 break; 325 case E1000_RDBAH(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAH(n)); 328 break; 329 case E1000_TDBAL(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAL(n)); 332 break; 333 case E1000_TDBAH(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDBAH(n)); 336 break; 337 case E1000_TDLEN(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDLEN(n)); 340 break; 341 case E1000_TDH(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDH(n)); 344 break; 345 case E1000_TDT(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDT(n)); 348 break; 349 case E1000_TXDCTL(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TXDCTL(n)); 352 break; 353 default: 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 355 return; 356 } 357 358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 360 regs[2], regs[3]); 361 } 362 363 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 364 static void igb_dump(struct igb_adapter *adapter) 365 { 366 struct net_device *netdev = adapter->netdev; 367 struct e1000_hw *hw = &adapter->hw; 368 struct igb_reg_info *reginfo; 369 struct igb_ring *tx_ring; 370 union e1000_adv_tx_desc *tx_desc; 371 struct my_u0 { u64 a; u64 b; } *u0; 372 struct igb_ring *rx_ring; 373 union e1000_adv_rx_desc *rx_desc; 374 u32 staterr; 375 u16 i, n; 376 377 if (!netif_msg_hw(adapter)) 378 return; 379 380 /* Print netdevice Info */ 381 if (netdev) { 382 dev_info(&adapter->pdev->dev, "Net device Info\n"); 383 pr_info("Device Name state trans_start last_rx\n"); 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 385 netdev->state, netdev->trans_start, netdev->last_rx); 386 } 387 388 /* Print Registers */ 389 dev_info(&adapter->pdev->dev, "Register Dump\n"); 390 pr_info(" Register Name Value\n"); 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 392 reginfo->name; reginfo++) { 393 igb_regdump(hw, reginfo); 394 } 395 396 /* Print TX Ring Summary */ 397 if (!netdev || !netif_running(netdev)) 398 goto exit; 399 400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 402 for (n = 0; n < adapter->num_tx_queues; n++) { 403 struct igb_tx_buffer *buffer_info; 404 tx_ring = adapter->tx_ring[n]; 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 407 n, tx_ring->next_to_use, tx_ring->next_to_clean, 408 (u64)dma_unmap_addr(buffer_info, dma), 409 dma_unmap_len(buffer_info, len), 410 buffer_info->next_to_watch, 411 (u64)buffer_info->time_stamp); 412 } 413 414 /* Print TX Rings */ 415 if (!netif_msg_tx_done(adapter)) 416 goto rx_ring_summary; 417 418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 419 420 /* Transmit Descriptor Formats 421 * 422 * Advanced Transmit Descriptor 423 * +--------------------------------------------------------------+ 424 * 0 | Buffer Address [63:0] | 425 * +--------------------------------------------------------------+ 426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 427 * +--------------------------------------------------------------+ 428 * 63 46 45 40 39 38 36 35 32 31 24 15 0 429 */ 430 431 for (n = 0; n < adapter->num_tx_queues; n++) { 432 tx_ring = adapter->tx_ring[n]; 433 pr_info("------------------------------------\n"); 434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 435 pr_info("------------------------------------\n"); 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 455 i, le64_to_cpu(u0->a), 456 le64_to_cpu(u0->b), 457 (u64)dma_unmap_addr(buffer_info, dma), 458 dma_unmap_len(buffer_info, len), 459 buffer_info->next_to_watch, 460 (u64)buffer_info->time_stamp, 461 buffer_info->skb, next_desc); 462 463 if (netif_msg_pktdata(adapter) && buffer_info->skb) 464 print_hex_dump(KERN_INFO, "", 465 DUMP_PREFIX_ADDRESS, 466 16, 1, buffer_info->skb->data, 467 dma_unmap_len(buffer_info, len), 468 true); 469 } 470 } 471 472 /* Print RX Rings Summary */ 473 rx_ring_summary: 474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 475 pr_info("Queue [NTU] [NTC]\n"); 476 for (n = 0; n < adapter->num_rx_queues; n++) { 477 rx_ring = adapter->rx_ring[n]; 478 pr_info(" %5d %5X %5X\n", 479 n, rx_ring->next_to_use, rx_ring->next_to_clean); 480 } 481 482 /* Print RX Rings */ 483 if (!netif_msg_rx_status(adapter)) 484 goto exit; 485 486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 487 488 /* Advanced Receive Descriptor (Read) Format 489 * 63 1 0 490 * +-----------------------------------------------------+ 491 * 0 | Packet Buffer Address [63:1] |A0/NSE| 492 * +----------------------------------------------+------+ 493 * 8 | Header Buffer Address [63:1] | DD | 494 * +-----------------------------------------------------+ 495 * 496 * 497 * Advanced Receive Descriptor (Write-Back) Format 498 * 499 * 63 48 47 32 31 30 21 20 17 16 4 3 0 500 * +------------------------------------------------------+ 501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 502 * | Checksum Ident | | | | Type | Type | 503 * +------------------------------------------------------+ 504 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 505 * +------------------------------------------------------+ 506 * 63 48 47 32 31 20 19 0 507 */ 508 509 for (n = 0; n < adapter->num_rx_queues; n++) { 510 rx_ring = adapter->rx_ring[n]; 511 pr_info("------------------------------------\n"); 512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 513 pr_info("------------------------------------\n"); 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 516 517 for (i = 0; i < rx_ring->count; i++) { 518 const char *next_desc; 519 struct igb_rx_buffer *buffer_info; 520 buffer_info = &rx_ring->rx_buffer_info[i]; 521 rx_desc = IGB_RX_DESC(rx_ring, i); 522 u0 = (struct my_u0 *)rx_desc; 523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 524 525 if (i == rx_ring->next_to_use) 526 next_desc = " NTU"; 527 else if (i == rx_ring->next_to_clean) 528 next_desc = " NTC"; 529 else 530 next_desc = ""; 531 532 if (staterr & E1000_RXD_STAT_DD) { 533 /* Descriptor Done */ 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 535 "RWB", i, 536 le64_to_cpu(u0->a), 537 le64_to_cpu(u0->b), 538 next_desc); 539 } else { 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 541 "R ", i, 542 le64_to_cpu(u0->a), 543 le64_to_cpu(u0->b), 544 (u64)buffer_info->dma, 545 next_desc); 546 547 if (netif_msg_pktdata(adapter) && 548 buffer_info->dma && buffer_info->page) { 549 print_hex_dump(KERN_INFO, "", 550 DUMP_PREFIX_ADDRESS, 551 16, 1, 552 page_address(buffer_info->page) + 553 buffer_info->page_offset, 554 IGB_RX_BUFSZ, true); 555 } 556 } 557 } 558 } 559 560 exit: 561 return; 562 } 563 564 /** 565 * igb_get_i2c_data - Reads the I2C SDA data bit 566 * @hw: pointer to hardware structure 567 * @i2cctl: Current value of I2CCTL register 568 * 569 * Returns the I2C data bit value 570 **/ 571 static int igb_get_i2c_data(void *data) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 return !!(i2cctl & E1000_I2C_DATA_IN); 578 } 579 580 /** 581 * igb_set_i2c_data - Sets the I2C data bit 582 * @data: pointer to hardware structure 583 * @state: I2C data value (0 or 1) to set 584 * 585 * Sets the I2C data bit 586 **/ 587 static void igb_set_i2c_data(void *data, int state) 588 { 589 struct igb_adapter *adapter = (struct igb_adapter *)data; 590 struct e1000_hw *hw = &adapter->hw; 591 s32 i2cctl = rd32(E1000_I2CPARAMS); 592 593 if (state) 594 i2cctl |= E1000_I2C_DATA_OUT; 595 else 596 i2cctl &= ~E1000_I2C_DATA_OUT; 597 598 i2cctl &= ~E1000_I2C_DATA_OE_N; 599 i2cctl |= E1000_I2C_CLK_OE_N; 600 wr32(E1000_I2CPARAMS, i2cctl); 601 wrfl(); 602 603 } 604 605 /** 606 * igb_set_i2c_clk - Sets the I2C SCL clock 607 * @data: pointer to hardware structure 608 * @state: state to set clock 609 * 610 * Sets the I2C clock line to state 611 **/ 612 static void igb_set_i2c_clk(void *data, int state) 613 { 614 struct igb_adapter *adapter = (struct igb_adapter *)data; 615 struct e1000_hw *hw = &adapter->hw; 616 s32 i2cctl = rd32(E1000_I2CPARAMS); 617 618 if (state) { 619 i2cctl |= E1000_I2C_CLK_OUT; 620 i2cctl &= ~E1000_I2C_CLK_OE_N; 621 } else { 622 i2cctl &= ~E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } 625 wr32(E1000_I2CPARAMS, i2cctl); 626 wrfl(); 627 } 628 629 /** 630 * igb_get_i2c_clk - Gets the I2C SCL clock state 631 * @data: pointer to hardware structure 632 * 633 * Gets the I2C clock state 634 **/ 635 static int igb_get_i2c_clk(void *data) 636 { 637 struct igb_adapter *adapter = (struct igb_adapter *)data; 638 struct e1000_hw *hw = &adapter->hw; 639 s32 i2cctl = rd32(E1000_I2CPARAMS); 640 641 return !!(i2cctl & E1000_I2C_CLK_IN); 642 } 643 644 static const struct i2c_algo_bit_data igb_i2c_algo = { 645 .setsda = igb_set_i2c_data, 646 .setscl = igb_set_i2c_clk, 647 .getsda = igb_get_i2c_data, 648 .getscl = igb_get_i2c_clk, 649 .udelay = 5, 650 .timeout = 20, 651 }; 652 653 /** 654 * igb_get_hw_dev - return device 655 * @hw: pointer to hardware structure 656 * 657 * used by hardware layer to print debugging information 658 **/ 659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 660 { 661 struct igb_adapter *adapter = hw->back; 662 return adapter->netdev; 663 } 664 665 /** 666 * igb_init_module - Driver Registration Routine 667 * 668 * igb_init_module is the first routine called when the driver is 669 * loaded. All it does is register with the PCI subsystem. 670 **/ 671 static int __init igb_init_module(void) 672 { 673 int ret; 674 675 pr_info("%s - version %s\n", 676 igb_driver_string, igb_driver_version); 677 pr_info("%s\n", igb_copyright); 678 679 #ifdef CONFIG_IGB_DCA 680 dca_register_notify(&dca_notifier); 681 #endif 682 ret = pci_register_driver(&igb_driver); 683 return ret; 684 } 685 686 module_init(igb_init_module); 687 688 /** 689 * igb_exit_module - Driver Exit Cleanup Routine 690 * 691 * igb_exit_module is called just before the driver is removed 692 * from memory. 693 **/ 694 static void __exit igb_exit_module(void) 695 { 696 #ifdef CONFIG_IGB_DCA 697 dca_unregister_notify(&dca_notifier); 698 #endif 699 pci_unregister_driver(&igb_driver); 700 } 701 702 module_exit(igb_exit_module); 703 704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 705 /** 706 * igb_cache_ring_register - Descriptor ring to register mapping 707 * @adapter: board private structure to initialize 708 * 709 * Once we know the feature-set enabled for the device, we'll cache 710 * the register offset the descriptor ring is assigned to. 711 **/ 712 static void igb_cache_ring_register(struct igb_adapter *adapter) 713 { 714 int i = 0, j = 0; 715 u32 rbase_offset = adapter->vfs_allocated_count; 716 717 switch (adapter->hw.mac.type) { 718 case e1000_82576: 719 /* The queues are allocated for virtualization such that VF 0 720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 721 * In order to avoid collision we start at the first free queue 722 * and continue consuming queues in the same sequence 723 */ 724 if (adapter->vfs_allocated_count) { 725 for (; i < adapter->rss_queues; i++) 726 adapter->rx_ring[i]->reg_idx = rbase_offset + 727 Q_IDX_82576(i); 728 } 729 /* Fall through */ 730 case e1000_82575: 731 case e1000_82580: 732 case e1000_i350: 733 case e1000_i354: 734 case e1000_i210: 735 case e1000_i211: 736 /* Fall through */ 737 default: 738 for (; i < adapter->num_rx_queues; i++) 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 740 for (; j < adapter->num_tx_queues; j++) 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 742 break; 743 } 744 } 745 746 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 747 { 748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 750 u32 value = 0; 751 752 if (E1000_REMOVED(hw_addr)) 753 return ~value; 754 755 value = readl(&hw_addr[reg]); 756 757 /* reads should not return all F's */ 758 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 759 struct net_device *netdev = igb->netdev; 760 hw->hw_addr = NULL; 761 netif_device_detach(netdev); 762 netdev_err(netdev, "PCIe link lost, device now detached\n"); 763 } 764 765 return value; 766 } 767 768 /** 769 * igb_write_ivar - configure ivar for given MSI-X vector 770 * @hw: pointer to the HW structure 771 * @msix_vector: vector number we are allocating to a given ring 772 * @index: row index of IVAR register to write within IVAR table 773 * @offset: column offset of in IVAR, should be multiple of 8 774 * 775 * This function is intended to handle the writing of the IVAR register 776 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 777 * each containing an cause allocation for an Rx and Tx ring, and a 778 * variable number of rows depending on the number of queues supported. 779 **/ 780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 781 int index, int offset) 782 { 783 u32 ivar = array_rd32(E1000_IVAR0, index); 784 785 /* clear any bits that are currently set */ 786 ivar &= ~((u32)0xFF << offset); 787 788 /* write vector and valid bit */ 789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 790 791 array_wr32(E1000_IVAR0, index, ivar); 792 } 793 794 #define IGB_N0_QUEUE -1 795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 796 { 797 struct igb_adapter *adapter = q_vector->adapter; 798 struct e1000_hw *hw = &adapter->hw; 799 int rx_queue = IGB_N0_QUEUE; 800 int tx_queue = IGB_N0_QUEUE; 801 u32 msixbm = 0; 802 803 if (q_vector->rx.ring) 804 rx_queue = q_vector->rx.ring->reg_idx; 805 if (q_vector->tx.ring) 806 tx_queue = q_vector->tx.ring->reg_idx; 807 808 switch (hw->mac.type) { 809 case e1000_82575: 810 /* The 82575 assigns vectors using a bitmask, which matches the 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one 812 * or more queues to a vector, we write the appropriate bits 813 * into the MSIXBM register for that vector. 814 */ 815 if (rx_queue > IGB_N0_QUEUE) 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 817 if (tx_queue > IGB_N0_QUEUE) 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 820 msixbm |= E1000_EIMS_OTHER; 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 822 q_vector->eims_value = msixbm; 823 break; 824 case e1000_82576: 825 /* 82576 uses a table that essentially consists of 2 columns 826 * with 8 rows. The ordering is column-major so we use the 827 * lower 3 bits as the row index, and the 4th bit as the 828 * column offset. 829 */ 830 if (rx_queue > IGB_N0_QUEUE) 831 igb_write_ivar(hw, msix_vector, 832 rx_queue & 0x7, 833 (rx_queue & 0x8) << 1); 834 if (tx_queue > IGB_N0_QUEUE) 835 igb_write_ivar(hw, msix_vector, 836 tx_queue & 0x7, 837 ((tx_queue & 0x8) << 1) + 8); 838 q_vector->eims_value = 1 << msix_vector; 839 break; 840 case e1000_82580: 841 case e1000_i350: 842 case e1000_i354: 843 case e1000_i210: 844 case e1000_i211: 845 /* On 82580 and newer adapters the scheme is similar to 82576 846 * however instead of ordering column-major we have things 847 * ordered row-major. So we traverse the table by using 848 * bit 0 as the column offset, and the remaining bits as the 849 * row index. 850 */ 851 if (rx_queue > IGB_N0_QUEUE) 852 igb_write_ivar(hw, msix_vector, 853 rx_queue >> 1, 854 (rx_queue & 0x1) << 4); 855 if (tx_queue > IGB_N0_QUEUE) 856 igb_write_ivar(hw, msix_vector, 857 tx_queue >> 1, 858 ((tx_queue & 0x1) << 4) + 8); 859 q_vector->eims_value = 1 << msix_vector; 860 break; 861 default: 862 BUG(); 863 break; 864 } 865 866 /* add q_vector eims value to global eims_enable_mask */ 867 adapter->eims_enable_mask |= q_vector->eims_value; 868 869 /* configure q_vector to set itr on first interrupt */ 870 q_vector->set_itr = 1; 871 } 872 873 /** 874 * igb_configure_msix - Configure MSI-X hardware 875 * @adapter: board private structure to initialize 876 * 877 * igb_configure_msix sets up the hardware to properly 878 * generate MSI-X interrupts. 879 **/ 880 static void igb_configure_msix(struct igb_adapter *adapter) 881 { 882 u32 tmp; 883 int i, vector = 0; 884 struct e1000_hw *hw = &adapter->hw; 885 886 adapter->eims_enable_mask = 0; 887 888 /* set vector for other causes, i.e. link changes */ 889 switch (hw->mac.type) { 890 case e1000_82575: 891 tmp = rd32(E1000_CTRL_EXT); 892 /* enable MSI-X PBA support*/ 893 tmp |= E1000_CTRL_EXT_PBA_CLR; 894 895 /* Auto-Mask interrupts upon ICR read. */ 896 tmp |= E1000_CTRL_EXT_EIAME; 897 tmp |= E1000_CTRL_EXT_IRCA; 898 899 wr32(E1000_CTRL_EXT, tmp); 900 901 /* enable msix_other interrupt */ 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 903 adapter->eims_other = E1000_EIMS_OTHER; 904 905 break; 906 907 case e1000_82576: 908 case e1000_82580: 909 case e1000_i350: 910 case e1000_i354: 911 case e1000_i210: 912 case e1000_i211: 913 /* Turn on MSI-X capability first, or our settings 914 * won't stick. And it will take days to debug. 915 */ 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 917 E1000_GPIE_PBA | E1000_GPIE_EIAME | 918 E1000_GPIE_NSICR); 919 920 /* enable msix_other interrupt */ 921 adapter->eims_other = 1 << vector; 922 tmp = (vector++ | E1000_IVAR_VALID) << 8; 923 924 wr32(E1000_IVAR_MISC, tmp); 925 break; 926 default: 927 /* do nothing, since nothing else supports MSI-X */ 928 break; 929 } /* switch (hw->mac.type) */ 930 931 adapter->eims_enable_mask |= adapter->eims_other; 932 933 for (i = 0; i < adapter->num_q_vectors; i++) 934 igb_assign_vector(adapter->q_vector[i], vector++); 935 936 wrfl(); 937 } 938 939 /** 940 * igb_request_msix - Initialize MSI-X interrupts 941 * @adapter: board private structure to initialize 942 * 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 944 * kernel. 945 **/ 946 static int igb_request_msix(struct igb_adapter *adapter) 947 { 948 struct net_device *netdev = adapter->netdev; 949 int i, err = 0, vector = 0, free_vector = 0; 950 951 err = request_irq(adapter->msix_entries[vector].vector, 952 igb_msix_other, 0, netdev->name, adapter); 953 if (err) 954 goto err_out; 955 956 for (i = 0; i < adapter->num_q_vectors; i++) { 957 struct igb_q_vector *q_vector = adapter->q_vector[i]; 958 959 vector++; 960 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 962 963 if (q_vector->rx.ring && q_vector->tx.ring) 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 965 q_vector->rx.ring->queue_index); 966 else if (q_vector->tx.ring) 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 968 q_vector->tx.ring->queue_index); 969 else if (q_vector->rx.ring) 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 971 q_vector->rx.ring->queue_index); 972 else 973 sprintf(q_vector->name, "%s-unused", netdev->name); 974 975 err = request_irq(adapter->msix_entries[vector].vector, 976 igb_msix_ring, 0, q_vector->name, 977 q_vector); 978 if (err) 979 goto err_free; 980 } 981 982 igb_configure_msix(adapter); 983 return 0; 984 985 err_free: 986 /* free already assigned IRQs */ 987 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 988 989 vector--; 990 for (i = 0; i < vector; i++) { 991 free_irq(adapter->msix_entries[free_vector++].vector, 992 adapter->q_vector[i]); 993 } 994 err_out: 995 return err; 996 } 997 998 /** 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1000 * @adapter: board private structure to initialize 1001 * @v_idx: Index of vector to be freed 1002 * 1003 * This function frees the memory allocated to the q_vector. 1004 **/ 1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1006 { 1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1008 1009 adapter->q_vector[v_idx] = NULL; 1010 1011 /* igb_get_stats64() might access the rings on this vector, 1012 * we must wait a grace period before freeing it. 1013 */ 1014 if (q_vector) 1015 kfree_rcu(q_vector, rcu); 1016 } 1017 1018 /** 1019 * igb_reset_q_vector - Reset config for interrupt vector 1020 * @adapter: board private structure to initialize 1021 * @v_idx: Index of vector to be reset 1022 * 1023 * If NAPI is enabled it will delete any references to the 1024 * NAPI struct. This is preparation for igb_free_q_vector. 1025 **/ 1026 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1027 { 1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1029 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1031 * allocated. So, q_vector is NULL so we should stop here. 1032 */ 1033 if (!q_vector) 1034 return; 1035 1036 if (q_vector->tx.ring) 1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1038 1039 if (q_vector->rx.ring) 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1041 1042 netif_napi_del(&q_vector->napi); 1043 1044 } 1045 1046 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1047 { 1048 int v_idx = adapter->num_q_vectors; 1049 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1051 pci_disable_msix(adapter->pdev); 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1053 pci_disable_msi(adapter->pdev); 1054 1055 while (v_idx--) 1056 igb_reset_q_vector(adapter, v_idx); 1057 } 1058 1059 /** 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1061 * @adapter: board private structure to initialize 1062 * 1063 * This function frees the memory allocated to the q_vectors. In addition if 1064 * NAPI is enabled it will delete any references to the NAPI struct prior 1065 * to freeing the q_vector. 1066 **/ 1067 static void igb_free_q_vectors(struct igb_adapter *adapter) 1068 { 1069 int v_idx = adapter->num_q_vectors; 1070 1071 adapter->num_tx_queues = 0; 1072 adapter->num_rx_queues = 0; 1073 adapter->num_q_vectors = 0; 1074 1075 while (v_idx--) { 1076 igb_reset_q_vector(adapter, v_idx); 1077 igb_free_q_vector(adapter, v_idx); 1078 } 1079 } 1080 1081 /** 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1083 * @adapter: board private structure to initialize 1084 * 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1086 * MSI-X interrupts allocated. 1087 */ 1088 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1089 { 1090 igb_free_q_vectors(adapter); 1091 igb_reset_interrupt_capability(adapter); 1092 } 1093 1094 /** 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1096 * @adapter: board private structure to initialize 1097 * @msix: boolean value of MSIX capability 1098 * 1099 * Attempt to configure interrupts using the best available 1100 * capabilities of the hardware and kernel. 1101 **/ 1102 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1103 { 1104 int err; 1105 int numvecs, i; 1106 1107 if (!msix) 1108 goto msi_only; 1109 adapter->flags |= IGB_FLAG_HAS_MSIX; 1110 1111 /* Number of supported queues. */ 1112 adapter->num_rx_queues = adapter->rss_queues; 1113 if (adapter->vfs_allocated_count) 1114 adapter->num_tx_queues = 1; 1115 else 1116 adapter->num_tx_queues = adapter->rss_queues; 1117 1118 /* start with one vector for every Rx queue */ 1119 numvecs = adapter->num_rx_queues; 1120 1121 /* if Tx handler is separate add 1 for every Tx queue */ 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1123 numvecs += adapter->num_tx_queues; 1124 1125 /* store the number of vectors reserved for queues */ 1126 adapter->num_q_vectors = numvecs; 1127 1128 /* add 1 vector for link status interrupts */ 1129 numvecs++; 1130 for (i = 0; i < numvecs; i++) 1131 adapter->msix_entries[i].entry = i; 1132 1133 err = pci_enable_msix_range(adapter->pdev, 1134 adapter->msix_entries, 1135 numvecs, 1136 numvecs); 1137 if (err > 0) 1138 return; 1139 1140 igb_reset_interrupt_capability(adapter); 1141 1142 /* If we can't do MSI-X, try MSI */ 1143 msi_only: 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1145 #ifdef CONFIG_PCI_IOV 1146 /* disable SR-IOV for non MSI-X configurations */ 1147 if (adapter->vf_data) { 1148 struct e1000_hw *hw = &adapter->hw; 1149 /* disable iov and allow time for transactions to clear */ 1150 pci_disable_sriov(adapter->pdev); 1151 msleep(500); 1152 1153 kfree(adapter->vf_data); 1154 adapter->vf_data = NULL; 1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1156 wrfl(); 1157 msleep(100); 1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1159 } 1160 #endif 1161 adapter->vfs_allocated_count = 0; 1162 adapter->rss_queues = 1; 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1164 adapter->num_rx_queues = 1; 1165 adapter->num_tx_queues = 1; 1166 adapter->num_q_vectors = 1; 1167 if (!pci_enable_msi(adapter->pdev)) 1168 adapter->flags |= IGB_FLAG_HAS_MSI; 1169 } 1170 1171 static void igb_add_ring(struct igb_ring *ring, 1172 struct igb_ring_container *head) 1173 { 1174 head->ring = ring; 1175 head->count++; 1176 } 1177 1178 /** 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1180 * @adapter: board private structure to initialize 1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1182 * @v_idx: index of vector in adapter struct 1183 * @txr_count: total number of Tx rings to allocate 1184 * @txr_idx: index of first Tx ring to allocate 1185 * @rxr_count: total number of Rx rings to allocate 1186 * @rxr_idx: index of first Rx ring to allocate 1187 * 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1189 **/ 1190 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1191 int v_count, int v_idx, 1192 int txr_count, int txr_idx, 1193 int rxr_count, int rxr_idx) 1194 { 1195 struct igb_q_vector *q_vector; 1196 struct igb_ring *ring; 1197 int ring_count, size; 1198 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1200 if (txr_count > 1 || rxr_count > 1) 1201 return -ENOMEM; 1202 1203 ring_count = txr_count + rxr_count; 1204 size = sizeof(struct igb_q_vector) + 1205 (sizeof(struct igb_ring) * ring_count); 1206 1207 /* allocate q_vector and rings */ 1208 q_vector = adapter->q_vector[v_idx]; 1209 if (!q_vector) { 1210 q_vector = kzalloc(size, GFP_KERNEL); 1211 } else if (size > ksize(q_vector)) { 1212 kfree_rcu(q_vector, rcu); 1213 q_vector = kzalloc(size, GFP_KERNEL); 1214 } else { 1215 memset(q_vector, 0, size); 1216 } 1217 if (!q_vector) 1218 return -ENOMEM; 1219 1220 /* initialize NAPI */ 1221 netif_napi_add(adapter->netdev, &q_vector->napi, 1222 igb_poll, 64); 1223 1224 /* tie q_vector and adapter together */ 1225 adapter->q_vector[v_idx] = q_vector; 1226 q_vector->adapter = adapter; 1227 1228 /* initialize work limits */ 1229 q_vector->tx.work_limit = adapter->tx_work_limit; 1230 1231 /* initialize ITR configuration */ 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1233 q_vector->itr_val = IGB_START_ITR; 1234 1235 /* initialize pointer to rings */ 1236 ring = q_vector->ring; 1237 1238 /* intialize ITR */ 1239 if (rxr_count) { 1240 /* rx or rx/tx vector */ 1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1242 q_vector->itr_val = adapter->rx_itr_setting; 1243 } else { 1244 /* tx only vector */ 1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1246 q_vector->itr_val = adapter->tx_itr_setting; 1247 } 1248 1249 if (txr_count) { 1250 /* assign generic ring traits */ 1251 ring->dev = &adapter->pdev->dev; 1252 ring->netdev = adapter->netdev; 1253 1254 /* configure backlink on ring */ 1255 ring->q_vector = q_vector; 1256 1257 /* update q_vector Tx values */ 1258 igb_add_ring(ring, &q_vector->tx); 1259 1260 /* For 82575, context index must be unique per ring. */ 1261 if (adapter->hw.mac.type == e1000_82575) 1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1263 1264 /* apply Tx specific ring traits */ 1265 ring->count = adapter->tx_ring_count; 1266 ring->queue_index = txr_idx; 1267 1268 u64_stats_init(&ring->tx_syncp); 1269 u64_stats_init(&ring->tx_syncp2); 1270 1271 /* assign ring to adapter */ 1272 adapter->tx_ring[txr_idx] = ring; 1273 1274 /* push pointer to next ring */ 1275 ring++; 1276 } 1277 1278 if (rxr_count) { 1279 /* assign generic ring traits */ 1280 ring->dev = &adapter->pdev->dev; 1281 ring->netdev = adapter->netdev; 1282 1283 /* configure backlink on ring */ 1284 ring->q_vector = q_vector; 1285 1286 /* update q_vector Rx values */ 1287 igb_add_ring(ring, &q_vector->rx); 1288 1289 /* set flag indicating ring supports SCTP checksum offload */ 1290 if (adapter->hw.mac.type >= e1000_82576) 1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1292 1293 /* On i350, i354, i210, and i211, loopback VLAN packets 1294 * have the tag byte-swapped. 1295 */ 1296 if (adapter->hw.mac.type >= e1000_i350) 1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1298 1299 /* apply Rx specific ring traits */ 1300 ring->count = adapter->rx_ring_count; 1301 ring->queue_index = rxr_idx; 1302 1303 u64_stats_init(&ring->rx_syncp); 1304 1305 /* assign ring to adapter */ 1306 adapter->rx_ring[rxr_idx] = ring; 1307 } 1308 1309 return 0; 1310 } 1311 1312 1313 /** 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1315 * @adapter: board private structure to initialize 1316 * 1317 * We allocate one q_vector per queue interrupt. If allocation fails we 1318 * return -ENOMEM. 1319 **/ 1320 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1321 { 1322 int q_vectors = adapter->num_q_vectors; 1323 int rxr_remaining = adapter->num_rx_queues; 1324 int txr_remaining = adapter->num_tx_queues; 1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1326 int err; 1327 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1329 for (; rxr_remaining; v_idx++) { 1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1331 0, 0, 1, rxr_idx); 1332 1333 if (err) 1334 goto err_out; 1335 1336 /* update counts and index */ 1337 rxr_remaining--; 1338 rxr_idx++; 1339 } 1340 } 1341 1342 for (; v_idx < q_vectors; v_idx++) { 1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1345 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1347 tqpv, txr_idx, rqpv, rxr_idx); 1348 1349 if (err) 1350 goto err_out; 1351 1352 /* update counts and index */ 1353 rxr_remaining -= rqpv; 1354 txr_remaining -= tqpv; 1355 rxr_idx++; 1356 txr_idx++; 1357 } 1358 1359 return 0; 1360 1361 err_out: 1362 adapter->num_tx_queues = 0; 1363 adapter->num_rx_queues = 0; 1364 adapter->num_q_vectors = 0; 1365 1366 while (v_idx--) 1367 igb_free_q_vector(adapter, v_idx); 1368 1369 return -ENOMEM; 1370 } 1371 1372 /** 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1374 * @adapter: board private structure to initialize 1375 * @msix: boolean value of MSIX capability 1376 * 1377 * This function initializes the interrupts and allocates all of the queues. 1378 **/ 1379 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1380 { 1381 struct pci_dev *pdev = adapter->pdev; 1382 int err; 1383 1384 igb_set_interrupt_capability(adapter, msix); 1385 1386 err = igb_alloc_q_vectors(adapter); 1387 if (err) { 1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1389 goto err_alloc_q_vectors; 1390 } 1391 1392 igb_cache_ring_register(adapter); 1393 1394 return 0; 1395 1396 err_alloc_q_vectors: 1397 igb_reset_interrupt_capability(adapter); 1398 return err; 1399 } 1400 1401 /** 1402 * igb_request_irq - initialize interrupts 1403 * @adapter: board private structure to initialize 1404 * 1405 * Attempts to configure interrupts using the best available 1406 * capabilities of the hardware and kernel. 1407 **/ 1408 static int igb_request_irq(struct igb_adapter *adapter) 1409 { 1410 struct net_device *netdev = adapter->netdev; 1411 struct pci_dev *pdev = adapter->pdev; 1412 int err = 0; 1413 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1415 err = igb_request_msix(adapter); 1416 if (!err) 1417 goto request_done; 1418 /* fall back to MSI */ 1419 igb_free_all_tx_resources(adapter); 1420 igb_free_all_rx_resources(adapter); 1421 1422 igb_clear_interrupt_scheme(adapter); 1423 err = igb_init_interrupt_scheme(adapter, false); 1424 if (err) 1425 goto request_done; 1426 1427 igb_setup_all_tx_resources(adapter); 1428 igb_setup_all_rx_resources(adapter); 1429 igb_configure(adapter); 1430 } 1431 1432 igb_assign_vector(adapter->q_vector[0], 0); 1433 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1435 err = request_irq(pdev->irq, igb_intr_msi, 0, 1436 netdev->name, adapter); 1437 if (!err) 1438 goto request_done; 1439 1440 /* fall back to legacy interrupts */ 1441 igb_reset_interrupt_capability(adapter); 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1443 } 1444 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1446 netdev->name, adapter); 1447 1448 if (err) 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1450 err); 1451 1452 request_done: 1453 return err; 1454 } 1455 1456 static void igb_free_irq(struct igb_adapter *adapter) 1457 { 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1459 int vector = 0, i; 1460 1461 free_irq(adapter->msix_entries[vector++].vector, adapter); 1462 1463 for (i = 0; i < adapter->num_q_vectors; i++) 1464 free_irq(adapter->msix_entries[vector++].vector, 1465 adapter->q_vector[i]); 1466 } else { 1467 free_irq(adapter->pdev->irq, adapter); 1468 } 1469 } 1470 1471 /** 1472 * igb_irq_disable - Mask off interrupt generation on the NIC 1473 * @adapter: board private structure 1474 **/ 1475 static void igb_irq_disable(struct igb_adapter *adapter) 1476 { 1477 struct e1000_hw *hw = &adapter->hw; 1478 1479 /* we need to be careful when disabling interrupts. The VFs are also 1480 * mapped into these registers and so clearing the bits can cause 1481 * issues on the VF drivers so we only need to clear what we set 1482 */ 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1484 u32 regval = rd32(E1000_EIAM); 1485 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1487 wr32(E1000_EIMC, adapter->eims_enable_mask); 1488 regval = rd32(E1000_EIAC); 1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1490 } 1491 1492 wr32(E1000_IAM, 0); 1493 wr32(E1000_IMC, ~0); 1494 wrfl(); 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1496 int i; 1497 1498 for (i = 0; i < adapter->num_q_vectors; i++) 1499 synchronize_irq(adapter->msix_entries[i].vector); 1500 } else { 1501 synchronize_irq(adapter->pdev->irq); 1502 } 1503 } 1504 1505 /** 1506 * igb_irq_enable - Enable default interrupt generation settings 1507 * @adapter: board private structure 1508 **/ 1509 static void igb_irq_enable(struct igb_adapter *adapter) 1510 { 1511 struct e1000_hw *hw = &adapter->hw; 1512 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1515 u32 regval = rd32(E1000_EIAC); 1516 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1518 regval = rd32(E1000_EIAM); 1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1520 wr32(E1000_EIMS, adapter->eims_enable_mask); 1521 if (adapter->vfs_allocated_count) { 1522 wr32(E1000_MBVFIMR, 0xFF); 1523 ims |= E1000_IMS_VMMB; 1524 } 1525 wr32(E1000_IMS, ims); 1526 } else { 1527 wr32(E1000_IMS, IMS_ENABLE_MASK | 1528 E1000_IMS_DRSTA); 1529 wr32(E1000_IAM, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 } 1532 } 1533 1534 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1535 { 1536 struct e1000_hw *hw = &adapter->hw; 1537 u16 vid = adapter->hw.mng_cookie.vlan_id; 1538 u16 old_vid = adapter->mng_vlan_id; 1539 1540 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1541 /* add VID to filter table */ 1542 igb_vfta_set(hw, vid, true); 1543 adapter->mng_vlan_id = vid; 1544 } else { 1545 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1546 } 1547 1548 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1549 (vid != old_vid) && 1550 !test_bit(old_vid, adapter->active_vlans)) { 1551 /* remove VID from filter table */ 1552 igb_vfta_set(hw, old_vid, false); 1553 } 1554 } 1555 1556 /** 1557 * igb_release_hw_control - release control of the h/w to f/w 1558 * @adapter: address of board private structure 1559 * 1560 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1561 * For ASF and Pass Through versions of f/w this means that the 1562 * driver is no longer loaded. 1563 **/ 1564 static void igb_release_hw_control(struct igb_adapter *adapter) 1565 { 1566 struct e1000_hw *hw = &adapter->hw; 1567 u32 ctrl_ext; 1568 1569 /* Let firmware take over control of h/w */ 1570 ctrl_ext = rd32(E1000_CTRL_EXT); 1571 wr32(E1000_CTRL_EXT, 1572 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1573 } 1574 1575 /** 1576 * igb_get_hw_control - get control of the h/w from f/w 1577 * @adapter: address of board private structure 1578 * 1579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1580 * For ASF and Pass Through versions of f/w this means that 1581 * the driver is loaded. 1582 **/ 1583 static void igb_get_hw_control(struct igb_adapter *adapter) 1584 { 1585 struct e1000_hw *hw = &adapter->hw; 1586 u32 ctrl_ext; 1587 1588 /* Let firmware know the driver has taken over */ 1589 ctrl_ext = rd32(E1000_CTRL_EXT); 1590 wr32(E1000_CTRL_EXT, 1591 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1592 } 1593 1594 /** 1595 * igb_configure - configure the hardware for RX and TX 1596 * @adapter: private board structure 1597 **/ 1598 static void igb_configure(struct igb_adapter *adapter) 1599 { 1600 struct net_device *netdev = adapter->netdev; 1601 int i; 1602 1603 igb_get_hw_control(adapter); 1604 igb_set_rx_mode(netdev); 1605 1606 igb_restore_vlan(adapter); 1607 1608 igb_setup_tctl(adapter); 1609 igb_setup_mrqc(adapter); 1610 igb_setup_rctl(adapter); 1611 1612 igb_configure_tx(adapter); 1613 igb_configure_rx(adapter); 1614 1615 igb_rx_fifo_flush_82575(&adapter->hw); 1616 1617 /* call igb_desc_unused which always leaves 1618 * at least 1 descriptor unused to make sure 1619 * next_to_use != next_to_clean 1620 */ 1621 for (i = 0; i < adapter->num_rx_queues; i++) { 1622 struct igb_ring *ring = adapter->rx_ring[i]; 1623 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1624 } 1625 } 1626 1627 /** 1628 * igb_power_up_link - Power up the phy/serdes link 1629 * @adapter: address of board private structure 1630 **/ 1631 void igb_power_up_link(struct igb_adapter *adapter) 1632 { 1633 igb_reset_phy(&adapter->hw); 1634 1635 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1636 igb_power_up_phy_copper(&adapter->hw); 1637 else 1638 igb_power_up_serdes_link_82575(&adapter->hw); 1639 1640 igb_setup_link(&adapter->hw); 1641 } 1642 1643 /** 1644 * igb_power_down_link - Power down the phy/serdes link 1645 * @adapter: address of board private structure 1646 */ 1647 static void igb_power_down_link(struct igb_adapter *adapter) 1648 { 1649 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1650 igb_power_down_phy_copper_82575(&adapter->hw); 1651 else 1652 igb_shutdown_serdes_link_82575(&adapter->hw); 1653 } 1654 1655 /** 1656 * Detect and switch function for Media Auto Sense 1657 * @adapter: address of the board private structure 1658 **/ 1659 static void igb_check_swap_media(struct igb_adapter *adapter) 1660 { 1661 struct e1000_hw *hw = &adapter->hw; 1662 u32 ctrl_ext, connsw; 1663 bool swap_now = false; 1664 1665 ctrl_ext = rd32(E1000_CTRL_EXT); 1666 connsw = rd32(E1000_CONNSW); 1667 1668 /* need to live swap if current media is copper and we have fiber/serdes 1669 * to go to. 1670 */ 1671 1672 if ((hw->phy.media_type == e1000_media_type_copper) && 1673 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1674 swap_now = true; 1675 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1676 /* copper signal takes time to appear */ 1677 if (adapter->copper_tries < 4) { 1678 adapter->copper_tries++; 1679 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1680 wr32(E1000_CONNSW, connsw); 1681 return; 1682 } else { 1683 adapter->copper_tries = 0; 1684 if ((connsw & E1000_CONNSW_PHYSD) && 1685 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1686 swap_now = true; 1687 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1688 wr32(E1000_CONNSW, connsw); 1689 } 1690 } 1691 } 1692 1693 if (!swap_now) 1694 return; 1695 1696 switch (hw->phy.media_type) { 1697 case e1000_media_type_copper: 1698 netdev_info(adapter->netdev, 1699 "MAS: changing media to fiber/serdes\n"); 1700 ctrl_ext |= 1701 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1702 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1703 adapter->copper_tries = 0; 1704 break; 1705 case e1000_media_type_internal_serdes: 1706 case e1000_media_type_fiber: 1707 netdev_info(adapter->netdev, 1708 "MAS: changing media to copper\n"); 1709 ctrl_ext &= 1710 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1711 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1712 break; 1713 default: 1714 /* shouldn't get here during regular operation */ 1715 netdev_err(adapter->netdev, 1716 "AMS: Invalid media type found, returning\n"); 1717 break; 1718 } 1719 wr32(E1000_CTRL_EXT, ctrl_ext); 1720 } 1721 1722 /** 1723 * igb_up - Open the interface and prepare it to handle traffic 1724 * @adapter: board private structure 1725 **/ 1726 int igb_up(struct igb_adapter *adapter) 1727 { 1728 struct e1000_hw *hw = &adapter->hw; 1729 int i; 1730 1731 /* hardware has been reset, we need to reload some things */ 1732 igb_configure(adapter); 1733 1734 clear_bit(__IGB_DOWN, &adapter->state); 1735 1736 for (i = 0; i < adapter->num_q_vectors; i++) 1737 napi_enable(&(adapter->q_vector[i]->napi)); 1738 1739 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1740 igb_configure_msix(adapter); 1741 else 1742 igb_assign_vector(adapter->q_vector[0], 0); 1743 1744 /* Clear any pending interrupts. */ 1745 rd32(E1000_ICR); 1746 igb_irq_enable(adapter); 1747 1748 /* notify VFs that reset has been completed */ 1749 if (adapter->vfs_allocated_count) { 1750 u32 reg_data = rd32(E1000_CTRL_EXT); 1751 1752 reg_data |= E1000_CTRL_EXT_PFRSTD; 1753 wr32(E1000_CTRL_EXT, reg_data); 1754 } 1755 1756 netif_tx_start_all_queues(adapter->netdev); 1757 1758 /* start the watchdog. */ 1759 hw->mac.get_link_status = 1; 1760 schedule_work(&adapter->watchdog_task); 1761 1762 if ((adapter->flags & IGB_FLAG_EEE) && 1763 (!hw->dev_spec._82575.eee_disable)) 1764 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1765 1766 return 0; 1767 } 1768 1769 void igb_down(struct igb_adapter *adapter) 1770 { 1771 struct net_device *netdev = adapter->netdev; 1772 struct e1000_hw *hw = &adapter->hw; 1773 u32 tctl, rctl; 1774 int i; 1775 1776 /* signal that we're down so the interrupt handler does not 1777 * reschedule our watchdog timer 1778 */ 1779 set_bit(__IGB_DOWN, &adapter->state); 1780 1781 /* disable receives in the hardware */ 1782 rctl = rd32(E1000_RCTL); 1783 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1784 /* flush and sleep below */ 1785 1786 netif_carrier_off(netdev); 1787 netif_tx_stop_all_queues(netdev); 1788 1789 /* disable transmits in the hardware */ 1790 tctl = rd32(E1000_TCTL); 1791 tctl &= ~E1000_TCTL_EN; 1792 wr32(E1000_TCTL, tctl); 1793 /* flush both disables and wait for them to finish */ 1794 wrfl(); 1795 usleep_range(10000, 11000); 1796 1797 igb_irq_disable(adapter); 1798 1799 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1800 1801 for (i = 0; i < adapter->num_q_vectors; i++) { 1802 if (adapter->q_vector[i]) { 1803 napi_synchronize(&adapter->q_vector[i]->napi); 1804 napi_disable(&adapter->q_vector[i]->napi); 1805 } 1806 } 1807 1808 del_timer_sync(&adapter->watchdog_timer); 1809 del_timer_sync(&adapter->phy_info_timer); 1810 1811 /* record the stats before reset*/ 1812 spin_lock(&adapter->stats64_lock); 1813 igb_update_stats(adapter, &adapter->stats64); 1814 spin_unlock(&adapter->stats64_lock); 1815 1816 adapter->link_speed = 0; 1817 adapter->link_duplex = 0; 1818 1819 if (!pci_channel_offline(adapter->pdev)) 1820 igb_reset(adapter); 1821 igb_clean_all_tx_rings(adapter); 1822 igb_clean_all_rx_rings(adapter); 1823 #ifdef CONFIG_IGB_DCA 1824 1825 /* since we reset the hardware DCA settings were cleared */ 1826 igb_setup_dca(adapter); 1827 #endif 1828 } 1829 1830 void igb_reinit_locked(struct igb_adapter *adapter) 1831 { 1832 WARN_ON(in_interrupt()); 1833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1834 usleep_range(1000, 2000); 1835 igb_down(adapter); 1836 igb_up(adapter); 1837 clear_bit(__IGB_RESETTING, &adapter->state); 1838 } 1839 1840 /** igb_enable_mas - Media Autosense re-enable after swap 1841 * 1842 * @adapter: adapter struct 1843 **/ 1844 static void igb_enable_mas(struct igb_adapter *adapter) 1845 { 1846 struct e1000_hw *hw = &adapter->hw; 1847 u32 connsw = rd32(E1000_CONNSW); 1848 1849 /* configure for SerDes media detect */ 1850 if ((hw->phy.media_type == e1000_media_type_copper) && 1851 (!(connsw & E1000_CONNSW_SERDESD))) { 1852 connsw |= E1000_CONNSW_ENRGSRC; 1853 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1854 wr32(E1000_CONNSW, connsw); 1855 wrfl(); 1856 } 1857 } 1858 1859 void igb_reset(struct igb_adapter *adapter) 1860 { 1861 struct pci_dev *pdev = adapter->pdev; 1862 struct e1000_hw *hw = &adapter->hw; 1863 struct e1000_mac_info *mac = &hw->mac; 1864 struct e1000_fc_info *fc = &hw->fc; 1865 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1866 1867 /* Repartition Pba for greater than 9k mtu 1868 * To take effect CTRL.RST is required. 1869 */ 1870 switch (mac->type) { 1871 case e1000_i350: 1872 case e1000_i354: 1873 case e1000_82580: 1874 pba = rd32(E1000_RXPBS); 1875 pba = igb_rxpbs_adjust_82580(pba); 1876 break; 1877 case e1000_82576: 1878 pba = rd32(E1000_RXPBS); 1879 pba &= E1000_RXPBS_SIZE_MASK_82576; 1880 break; 1881 case e1000_82575: 1882 case e1000_i210: 1883 case e1000_i211: 1884 default: 1885 pba = E1000_PBA_34K; 1886 break; 1887 } 1888 1889 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1890 (mac->type < e1000_82576)) { 1891 /* adjust PBA for jumbo frames */ 1892 wr32(E1000_PBA, pba); 1893 1894 /* To maintain wire speed transmits, the Tx FIFO should be 1895 * large enough to accommodate two full transmit packets, 1896 * rounded up to the next 1KB and expressed in KB. Likewise, 1897 * the Rx FIFO should be large enough to accommodate at least 1898 * one full receive packet and is similarly rounded up and 1899 * expressed in KB. 1900 */ 1901 pba = rd32(E1000_PBA); 1902 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1903 tx_space = pba >> 16; 1904 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1905 pba &= 0xffff; 1906 /* the Tx fifo also stores 16 bytes of information about the Tx 1907 * but don't include ethernet FCS because hardware appends it 1908 */ 1909 min_tx_space = (adapter->max_frame_size + 1910 sizeof(union e1000_adv_tx_desc) - 1911 ETH_FCS_LEN) * 2; 1912 min_tx_space = ALIGN(min_tx_space, 1024); 1913 min_tx_space >>= 10; 1914 /* software strips receive CRC, so leave room for it */ 1915 min_rx_space = adapter->max_frame_size; 1916 min_rx_space = ALIGN(min_rx_space, 1024); 1917 min_rx_space >>= 10; 1918 1919 /* If current Tx allocation is less than the min Tx FIFO size, 1920 * and the min Tx FIFO size is less than the current Rx FIFO 1921 * allocation, take space away from current Rx allocation 1922 */ 1923 if (tx_space < min_tx_space && 1924 ((min_tx_space - tx_space) < pba)) { 1925 pba = pba - (min_tx_space - tx_space); 1926 1927 /* if short on Rx space, Rx wins and must trump Tx 1928 * adjustment 1929 */ 1930 if (pba < min_rx_space) 1931 pba = min_rx_space; 1932 } 1933 wr32(E1000_PBA, pba); 1934 } 1935 1936 /* flow control settings */ 1937 /* The high water mark must be low enough to fit one full frame 1938 * (or the size used for early receive) above it in the Rx FIFO. 1939 * Set it to the lower of: 1940 * - 90% of the Rx FIFO size, or 1941 * - the full Rx FIFO size minus one full frame 1942 */ 1943 hwm = min(((pba << 10) * 9 / 10), 1944 ((pba << 10) - 2 * adapter->max_frame_size)); 1945 1946 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1947 fc->low_water = fc->high_water - 16; 1948 fc->pause_time = 0xFFFF; 1949 fc->send_xon = 1; 1950 fc->current_mode = fc->requested_mode; 1951 1952 /* disable receive for all VFs and wait one second */ 1953 if (adapter->vfs_allocated_count) { 1954 int i; 1955 1956 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1957 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1958 1959 /* ping all the active vfs to let them know we are going down */ 1960 igb_ping_all_vfs(adapter); 1961 1962 /* disable transmits and receives */ 1963 wr32(E1000_VFRE, 0); 1964 wr32(E1000_VFTE, 0); 1965 } 1966 1967 /* Allow time for pending master requests to run */ 1968 hw->mac.ops.reset_hw(hw); 1969 wr32(E1000_WUC, 0); 1970 1971 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1972 /* need to resetup here after media swap */ 1973 adapter->ei.get_invariants(hw); 1974 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1975 } 1976 if ((mac->type == e1000_82575) && 1977 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1978 igb_enable_mas(adapter); 1979 } 1980 if (hw->mac.ops.init_hw(hw)) 1981 dev_err(&pdev->dev, "Hardware Error\n"); 1982 1983 /* Flow control settings reset on hardware reset, so guarantee flow 1984 * control is off when forcing speed. 1985 */ 1986 if (!hw->mac.autoneg) 1987 igb_force_mac_fc(hw); 1988 1989 igb_init_dmac(adapter, pba); 1990 #ifdef CONFIG_IGB_HWMON 1991 /* Re-initialize the thermal sensor on i350 devices. */ 1992 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1993 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1994 /* If present, re-initialize the external thermal sensor 1995 * interface. 1996 */ 1997 if (adapter->ets) 1998 mac->ops.init_thermal_sensor_thresh(hw); 1999 } 2000 } 2001 #endif 2002 /* Re-establish EEE setting */ 2003 if (hw->phy.media_type == e1000_media_type_copper) { 2004 switch (mac->type) { 2005 case e1000_i350: 2006 case e1000_i210: 2007 case e1000_i211: 2008 igb_set_eee_i350(hw, true, true); 2009 break; 2010 case e1000_i354: 2011 igb_set_eee_i354(hw, true, true); 2012 break; 2013 default: 2014 break; 2015 } 2016 } 2017 if (!netif_running(adapter->netdev)) 2018 igb_power_down_link(adapter); 2019 2020 igb_update_mng_vlan(adapter); 2021 2022 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2023 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2024 2025 /* Re-enable PTP, where applicable. */ 2026 igb_ptp_reset(adapter); 2027 2028 igb_get_phy_info(hw); 2029 } 2030 2031 static netdev_features_t igb_fix_features(struct net_device *netdev, 2032 netdev_features_t features) 2033 { 2034 /* Since there is no support for separate Rx/Tx vlan accel 2035 * enable/disable make sure Tx flag is always in same state as Rx. 2036 */ 2037 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2038 features |= NETIF_F_HW_VLAN_CTAG_TX; 2039 else 2040 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2041 2042 return features; 2043 } 2044 2045 static int igb_set_features(struct net_device *netdev, 2046 netdev_features_t features) 2047 { 2048 netdev_features_t changed = netdev->features ^ features; 2049 struct igb_adapter *adapter = netdev_priv(netdev); 2050 2051 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2052 igb_vlan_mode(netdev, features); 2053 2054 if (!(changed & NETIF_F_RXALL)) 2055 return 0; 2056 2057 netdev->features = features; 2058 2059 if (netif_running(netdev)) 2060 igb_reinit_locked(adapter); 2061 else 2062 igb_reset(adapter); 2063 2064 return 0; 2065 } 2066 2067 static const struct net_device_ops igb_netdev_ops = { 2068 .ndo_open = igb_open, 2069 .ndo_stop = igb_close, 2070 .ndo_start_xmit = igb_xmit_frame, 2071 .ndo_get_stats64 = igb_get_stats64, 2072 .ndo_set_rx_mode = igb_set_rx_mode, 2073 .ndo_set_mac_address = igb_set_mac, 2074 .ndo_change_mtu = igb_change_mtu, 2075 .ndo_do_ioctl = igb_ioctl, 2076 .ndo_tx_timeout = igb_tx_timeout, 2077 .ndo_validate_addr = eth_validate_addr, 2078 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2079 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2080 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2081 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2082 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2083 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2084 .ndo_get_vf_config = igb_ndo_get_vf_config, 2085 #ifdef CONFIG_NET_POLL_CONTROLLER 2086 .ndo_poll_controller = igb_netpoll, 2087 #endif 2088 .ndo_fix_features = igb_fix_features, 2089 .ndo_set_features = igb_set_features, 2090 .ndo_features_check = passthru_features_check, 2091 }; 2092 2093 /** 2094 * igb_set_fw_version - Configure version string for ethtool 2095 * @adapter: adapter struct 2096 **/ 2097 void igb_set_fw_version(struct igb_adapter *adapter) 2098 { 2099 struct e1000_hw *hw = &adapter->hw; 2100 struct e1000_fw_version fw; 2101 2102 igb_get_fw_version(hw, &fw); 2103 2104 switch (hw->mac.type) { 2105 case e1000_i210: 2106 case e1000_i211: 2107 if (!(igb_get_flash_presence_i210(hw))) { 2108 snprintf(adapter->fw_version, 2109 sizeof(adapter->fw_version), 2110 "%2d.%2d-%d", 2111 fw.invm_major, fw.invm_minor, 2112 fw.invm_img_type); 2113 break; 2114 } 2115 /* fall through */ 2116 default: 2117 /* if option is rom valid, display its version too */ 2118 if (fw.or_valid) { 2119 snprintf(adapter->fw_version, 2120 sizeof(adapter->fw_version), 2121 "%d.%d, 0x%08x, %d.%d.%d", 2122 fw.eep_major, fw.eep_minor, fw.etrack_id, 2123 fw.or_major, fw.or_build, fw.or_patch); 2124 /* no option rom */ 2125 } else if (fw.etrack_id != 0X0000) { 2126 snprintf(adapter->fw_version, 2127 sizeof(adapter->fw_version), 2128 "%d.%d, 0x%08x", 2129 fw.eep_major, fw.eep_minor, fw.etrack_id); 2130 } else { 2131 snprintf(adapter->fw_version, 2132 sizeof(adapter->fw_version), 2133 "%d.%d.%d", 2134 fw.eep_major, fw.eep_minor, fw.eep_build); 2135 } 2136 break; 2137 } 2138 } 2139 2140 /** 2141 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2142 * 2143 * @adapter: adapter struct 2144 **/ 2145 static void igb_init_mas(struct igb_adapter *adapter) 2146 { 2147 struct e1000_hw *hw = &adapter->hw; 2148 u16 eeprom_data; 2149 2150 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2151 switch (hw->bus.func) { 2152 case E1000_FUNC_0: 2153 if (eeprom_data & IGB_MAS_ENABLE_0) { 2154 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2155 netdev_info(adapter->netdev, 2156 "MAS: Enabling Media Autosense for port %d\n", 2157 hw->bus.func); 2158 } 2159 break; 2160 case E1000_FUNC_1: 2161 if (eeprom_data & IGB_MAS_ENABLE_1) { 2162 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2163 netdev_info(adapter->netdev, 2164 "MAS: Enabling Media Autosense for port %d\n", 2165 hw->bus.func); 2166 } 2167 break; 2168 case E1000_FUNC_2: 2169 if (eeprom_data & IGB_MAS_ENABLE_2) { 2170 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2171 netdev_info(adapter->netdev, 2172 "MAS: Enabling Media Autosense for port %d\n", 2173 hw->bus.func); 2174 } 2175 break; 2176 case E1000_FUNC_3: 2177 if (eeprom_data & IGB_MAS_ENABLE_3) { 2178 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2179 netdev_info(adapter->netdev, 2180 "MAS: Enabling Media Autosense for port %d\n", 2181 hw->bus.func); 2182 } 2183 break; 2184 default: 2185 /* Shouldn't get here */ 2186 netdev_err(adapter->netdev, 2187 "MAS: Invalid port configuration, returning\n"); 2188 break; 2189 } 2190 } 2191 2192 /** 2193 * igb_init_i2c - Init I2C interface 2194 * @adapter: pointer to adapter structure 2195 **/ 2196 static s32 igb_init_i2c(struct igb_adapter *adapter) 2197 { 2198 s32 status = 0; 2199 2200 /* I2C interface supported on i350 devices */ 2201 if (adapter->hw.mac.type != e1000_i350) 2202 return 0; 2203 2204 /* Initialize the i2c bus which is controlled by the registers. 2205 * This bus will use the i2c_algo_bit structue that implements 2206 * the protocol through toggling of the 4 bits in the register. 2207 */ 2208 adapter->i2c_adap.owner = THIS_MODULE; 2209 adapter->i2c_algo = igb_i2c_algo; 2210 adapter->i2c_algo.data = adapter; 2211 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2212 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2213 strlcpy(adapter->i2c_adap.name, "igb BB", 2214 sizeof(adapter->i2c_adap.name)); 2215 status = i2c_bit_add_bus(&adapter->i2c_adap); 2216 return status; 2217 } 2218 2219 /** 2220 * igb_probe - Device Initialization Routine 2221 * @pdev: PCI device information struct 2222 * @ent: entry in igb_pci_tbl 2223 * 2224 * Returns 0 on success, negative on failure 2225 * 2226 * igb_probe initializes an adapter identified by a pci_dev structure. 2227 * The OS initialization, configuring of the adapter private structure, 2228 * and a hardware reset occur. 2229 **/ 2230 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2231 { 2232 struct net_device *netdev; 2233 struct igb_adapter *adapter; 2234 struct e1000_hw *hw; 2235 u16 eeprom_data = 0; 2236 s32 ret_val; 2237 static int global_quad_port_a; /* global quad port a indication */ 2238 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2239 int err, pci_using_dac; 2240 u8 part_str[E1000_PBANUM_LENGTH]; 2241 2242 /* Catch broken hardware that put the wrong VF device ID in 2243 * the PCIe SR-IOV capability. 2244 */ 2245 if (pdev->is_virtfn) { 2246 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2247 pci_name(pdev), pdev->vendor, pdev->device); 2248 return -EINVAL; 2249 } 2250 2251 err = pci_enable_device_mem(pdev); 2252 if (err) 2253 return err; 2254 2255 pci_using_dac = 0; 2256 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2257 if (!err) { 2258 pci_using_dac = 1; 2259 } else { 2260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2261 if (err) { 2262 dev_err(&pdev->dev, 2263 "No usable DMA configuration, aborting\n"); 2264 goto err_dma; 2265 } 2266 } 2267 2268 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2269 IORESOURCE_MEM), 2270 igb_driver_name); 2271 if (err) 2272 goto err_pci_reg; 2273 2274 pci_enable_pcie_error_reporting(pdev); 2275 2276 pci_set_master(pdev); 2277 pci_save_state(pdev); 2278 2279 err = -ENOMEM; 2280 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2281 IGB_MAX_TX_QUEUES); 2282 if (!netdev) 2283 goto err_alloc_etherdev; 2284 2285 SET_NETDEV_DEV(netdev, &pdev->dev); 2286 2287 pci_set_drvdata(pdev, netdev); 2288 adapter = netdev_priv(netdev); 2289 adapter->netdev = netdev; 2290 adapter->pdev = pdev; 2291 hw = &adapter->hw; 2292 hw->back = adapter; 2293 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2294 2295 err = -EIO; 2296 adapter->io_addr = pci_iomap(pdev, 0, 0); 2297 if (!adapter->io_addr) 2298 goto err_ioremap; 2299 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2300 hw->hw_addr = adapter->io_addr; 2301 2302 netdev->netdev_ops = &igb_netdev_ops; 2303 igb_set_ethtool_ops(netdev); 2304 netdev->watchdog_timeo = 5 * HZ; 2305 2306 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2307 2308 netdev->mem_start = pci_resource_start(pdev, 0); 2309 netdev->mem_end = pci_resource_end(pdev, 0); 2310 2311 /* PCI config space info */ 2312 hw->vendor_id = pdev->vendor; 2313 hw->device_id = pdev->device; 2314 hw->revision_id = pdev->revision; 2315 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2316 hw->subsystem_device_id = pdev->subsystem_device; 2317 2318 /* Copy the default MAC, PHY and NVM function pointers */ 2319 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2320 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2321 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2322 /* Initialize skew-specific constants */ 2323 err = ei->get_invariants(hw); 2324 if (err) 2325 goto err_sw_init; 2326 2327 /* setup the private structure */ 2328 err = igb_sw_init(adapter); 2329 if (err) 2330 goto err_sw_init; 2331 2332 igb_get_bus_info_pcie(hw); 2333 2334 hw->phy.autoneg_wait_to_complete = false; 2335 2336 /* Copper options */ 2337 if (hw->phy.media_type == e1000_media_type_copper) { 2338 hw->phy.mdix = AUTO_ALL_MODES; 2339 hw->phy.disable_polarity_correction = false; 2340 hw->phy.ms_type = e1000_ms_hw_default; 2341 } 2342 2343 if (igb_check_reset_block(hw)) 2344 dev_info(&pdev->dev, 2345 "PHY reset is blocked due to SOL/IDER session.\n"); 2346 2347 /* features is initialized to 0 in allocation, it might have bits 2348 * set by igb_sw_init so we should use an or instead of an 2349 * assignment. 2350 */ 2351 netdev->features |= NETIF_F_SG | 2352 NETIF_F_IP_CSUM | 2353 NETIF_F_IPV6_CSUM | 2354 NETIF_F_TSO | 2355 NETIF_F_TSO6 | 2356 NETIF_F_RXHASH | 2357 NETIF_F_RXCSUM | 2358 NETIF_F_HW_VLAN_CTAG_RX | 2359 NETIF_F_HW_VLAN_CTAG_TX; 2360 2361 /* copy netdev features into list of user selectable features */ 2362 netdev->hw_features |= netdev->features; 2363 netdev->hw_features |= NETIF_F_RXALL; 2364 2365 /* set this bit last since it cannot be part of hw_features */ 2366 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2367 2368 netdev->vlan_features |= NETIF_F_TSO | 2369 NETIF_F_TSO6 | 2370 NETIF_F_IP_CSUM | 2371 NETIF_F_IPV6_CSUM | 2372 NETIF_F_SG; 2373 2374 netdev->priv_flags |= IFF_SUPP_NOFCS; 2375 2376 if (pci_using_dac) { 2377 netdev->features |= NETIF_F_HIGHDMA; 2378 netdev->vlan_features |= NETIF_F_HIGHDMA; 2379 } 2380 2381 if (hw->mac.type >= e1000_82576) { 2382 netdev->hw_features |= NETIF_F_SCTP_CRC; 2383 netdev->features |= NETIF_F_SCTP_CRC; 2384 } 2385 2386 netdev->priv_flags |= IFF_UNICAST_FLT; 2387 2388 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2389 2390 /* before reading the NVM, reset the controller to put the device in a 2391 * known good starting state 2392 */ 2393 hw->mac.ops.reset_hw(hw); 2394 2395 /* make sure the NVM is good , i211/i210 parts can have special NVM 2396 * that doesn't contain a checksum 2397 */ 2398 switch (hw->mac.type) { 2399 case e1000_i210: 2400 case e1000_i211: 2401 if (igb_get_flash_presence_i210(hw)) { 2402 if (hw->nvm.ops.validate(hw) < 0) { 2403 dev_err(&pdev->dev, 2404 "The NVM Checksum Is Not Valid\n"); 2405 err = -EIO; 2406 goto err_eeprom; 2407 } 2408 } 2409 break; 2410 default: 2411 if (hw->nvm.ops.validate(hw) < 0) { 2412 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2413 err = -EIO; 2414 goto err_eeprom; 2415 } 2416 break; 2417 } 2418 2419 /* copy the MAC address out of the NVM */ 2420 if (hw->mac.ops.read_mac_addr(hw)) 2421 dev_err(&pdev->dev, "NVM Read Error\n"); 2422 2423 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2424 2425 if (!is_valid_ether_addr(netdev->dev_addr)) { 2426 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2427 err = -EIO; 2428 goto err_eeprom; 2429 } 2430 2431 /* get firmware version for ethtool -i */ 2432 igb_set_fw_version(adapter); 2433 2434 /* configure RXPBSIZE and TXPBSIZE */ 2435 if (hw->mac.type == e1000_i210) { 2436 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2437 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2438 } 2439 2440 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2441 (unsigned long) adapter); 2442 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2443 (unsigned long) adapter); 2444 2445 INIT_WORK(&adapter->reset_task, igb_reset_task); 2446 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2447 2448 /* Initialize link properties that are user-changeable */ 2449 adapter->fc_autoneg = true; 2450 hw->mac.autoneg = true; 2451 hw->phy.autoneg_advertised = 0x2f; 2452 2453 hw->fc.requested_mode = e1000_fc_default; 2454 hw->fc.current_mode = e1000_fc_default; 2455 2456 igb_validate_mdi_setting(hw); 2457 2458 /* By default, support wake on port A */ 2459 if (hw->bus.func == 0) 2460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2461 2462 /* Check the NVM for wake support on non-port A ports */ 2463 if (hw->mac.type >= e1000_82580) 2464 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2465 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2466 &eeprom_data); 2467 else if (hw->bus.func == 1) 2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2469 2470 if (eeprom_data & IGB_EEPROM_APME) 2471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2472 2473 /* now that we have the eeprom settings, apply the special cases where 2474 * the eeprom may be wrong or the board simply won't support wake on 2475 * lan on a particular port 2476 */ 2477 switch (pdev->device) { 2478 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2479 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2480 break; 2481 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2482 case E1000_DEV_ID_82576_FIBER: 2483 case E1000_DEV_ID_82576_SERDES: 2484 /* Wake events only supported on port A for dual fiber 2485 * regardless of eeprom setting 2486 */ 2487 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2488 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2489 break; 2490 case E1000_DEV_ID_82576_QUAD_COPPER: 2491 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2492 /* if quad port adapter, disable WoL on all but port A */ 2493 if (global_quad_port_a != 0) 2494 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2495 else 2496 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2497 /* Reset for multiple quad port adapters */ 2498 if (++global_quad_port_a == 4) 2499 global_quad_port_a = 0; 2500 break; 2501 default: 2502 /* If the device can't wake, don't set software support */ 2503 if (!device_can_wakeup(&adapter->pdev->dev)) 2504 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2505 } 2506 2507 /* initialize the wol settings based on the eeprom settings */ 2508 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2509 adapter->wol |= E1000_WUFC_MAG; 2510 2511 /* Some vendors want WoL disabled by default, but still supported */ 2512 if ((hw->mac.type == e1000_i350) && 2513 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2514 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2515 adapter->wol = 0; 2516 } 2517 2518 device_set_wakeup_enable(&adapter->pdev->dev, 2519 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2520 2521 /* reset the hardware with the new settings */ 2522 igb_reset(adapter); 2523 2524 /* Init the I2C interface */ 2525 err = igb_init_i2c(adapter); 2526 if (err) { 2527 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2528 goto err_eeprom; 2529 } 2530 2531 /* let the f/w know that the h/w is now under the control of the 2532 * driver. 2533 */ 2534 igb_get_hw_control(adapter); 2535 2536 strcpy(netdev->name, "eth%d"); 2537 err = register_netdev(netdev); 2538 if (err) 2539 goto err_register; 2540 2541 /* carrier off reporting is important to ethtool even BEFORE open */ 2542 netif_carrier_off(netdev); 2543 2544 #ifdef CONFIG_IGB_DCA 2545 if (dca_add_requester(&pdev->dev) == 0) { 2546 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2547 dev_info(&pdev->dev, "DCA enabled\n"); 2548 igb_setup_dca(adapter); 2549 } 2550 2551 #endif 2552 #ifdef CONFIG_IGB_HWMON 2553 /* Initialize the thermal sensor on i350 devices. */ 2554 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2555 u16 ets_word; 2556 2557 /* Read the NVM to determine if this i350 device supports an 2558 * external thermal sensor. 2559 */ 2560 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2561 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2562 adapter->ets = true; 2563 else 2564 adapter->ets = false; 2565 if (igb_sysfs_init(adapter)) 2566 dev_err(&pdev->dev, 2567 "failed to allocate sysfs resources\n"); 2568 } else { 2569 adapter->ets = false; 2570 } 2571 #endif 2572 /* Check if Media Autosense is enabled */ 2573 adapter->ei = *ei; 2574 if (hw->dev_spec._82575.mas_capable) 2575 igb_init_mas(adapter); 2576 2577 /* do hw tstamp init after resetting */ 2578 igb_ptp_init(adapter); 2579 2580 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2581 /* print bus type/speed/width info, not applicable to i354 */ 2582 if (hw->mac.type != e1000_i354) { 2583 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2584 netdev->name, 2585 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2586 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2587 "unknown"), 2588 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2589 "Width x4" : 2590 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2591 "Width x2" : 2592 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2593 "Width x1" : "unknown"), netdev->dev_addr); 2594 } 2595 2596 if ((hw->mac.type >= e1000_i210 || 2597 igb_get_flash_presence_i210(hw))) { 2598 ret_val = igb_read_part_string(hw, part_str, 2599 E1000_PBANUM_LENGTH); 2600 } else { 2601 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2602 } 2603 2604 if (ret_val) 2605 strcpy(part_str, "Unknown"); 2606 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2607 dev_info(&pdev->dev, 2608 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2609 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2610 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2611 adapter->num_rx_queues, adapter->num_tx_queues); 2612 if (hw->phy.media_type == e1000_media_type_copper) { 2613 switch (hw->mac.type) { 2614 case e1000_i350: 2615 case e1000_i210: 2616 case e1000_i211: 2617 /* Enable EEE for internal copper PHY devices */ 2618 err = igb_set_eee_i350(hw, true, true); 2619 if ((!err) && 2620 (!hw->dev_spec._82575.eee_disable)) { 2621 adapter->eee_advert = 2622 MDIO_EEE_100TX | MDIO_EEE_1000T; 2623 adapter->flags |= IGB_FLAG_EEE; 2624 } 2625 break; 2626 case e1000_i354: 2627 if ((rd32(E1000_CTRL_EXT) & 2628 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2629 err = igb_set_eee_i354(hw, true, true); 2630 if ((!err) && 2631 (!hw->dev_spec._82575.eee_disable)) { 2632 adapter->eee_advert = 2633 MDIO_EEE_100TX | MDIO_EEE_1000T; 2634 adapter->flags |= IGB_FLAG_EEE; 2635 } 2636 } 2637 break; 2638 default: 2639 break; 2640 } 2641 } 2642 pm_runtime_put_noidle(&pdev->dev); 2643 return 0; 2644 2645 err_register: 2646 igb_release_hw_control(adapter); 2647 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2648 err_eeprom: 2649 if (!igb_check_reset_block(hw)) 2650 igb_reset_phy(hw); 2651 2652 if (hw->flash_address) 2653 iounmap(hw->flash_address); 2654 err_sw_init: 2655 kfree(adapter->shadow_vfta); 2656 igb_clear_interrupt_scheme(adapter); 2657 #ifdef CONFIG_PCI_IOV 2658 igb_disable_sriov(pdev); 2659 #endif 2660 pci_iounmap(pdev, adapter->io_addr); 2661 err_ioremap: 2662 free_netdev(netdev); 2663 err_alloc_etherdev: 2664 pci_release_selected_regions(pdev, 2665 pci_select_bars(pdev, IORESOURCE_MEM)); 2666 err_pci_reg: 2667 err_dma: 2668 pci_disable_device(pdev); 2669 return err; 2670 } 2671 2672 #ifdef CONFIG_PCI_IOV 2673 static int igb_disable_sriov(struct pci_dev *pdev) 2674 { 2675 struct net_device *netdev = pci_get_drvdata(pdev); 2676 struct igb_adapter *adapter = netdev_priv(netdev); 2677 struct e1000_hw *hw = &adapter->hw; 2678 2679 /* reclaim resources allocated to VFs */ 2680 if (adapter->vf_data) { 2681 /* disable iov and allow time for transactions to clear */ 2682 if (pci_vfs_assigned(pdev)) { 2683 dev_warn(&pdev->dev, 2684 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2685 return -EPERM; 2686 } else { 2687 pci_disable_sriov(pdev); 2688 msleep(500); 2689 } 2690 2691 kfree(adapter->vf_data); 2692 adapter->vf_data = NULL; 2693 adapter->vfs_allocated_count = 0; 2694 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2695 wrfl(); 2696 msleep(100); 2697 dev_info(&pdev->dev, "IOV Disabled\n"); 2698 2699 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2700 adapter->flags |= IGB_FLAG_DMAC; 2701 } 2702 2703 return 0; 2704 } 2705 2706 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2707 { 2708 struct net_device *netdev = pci_get_drvdata(pdev); 2709 struct igb_adapter *adapter = netdev_priv(netdev); 2710 int old_vfs = pci_num_vf(pdev); 2711 int err = 0; 2712 int i; 2713 2714 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2715 err = -EPERM; 2716 goto out; 2717 } 2718 if (!num_vfs) 2719 goto out; 2720 2721 if (old_vfs) { 2722 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2723 old_vfs, max_vfs); 2724 adapter->vfs_allocated_count = old_vfs; 2725 } else 2726 adapter->vfs_allocated_count = num_vfs; 2727 2728 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2729 sizeof(struct vf_data_storage), GFP_KERNEL); 2730 2731 /* if allocation failed then we do not support SR-IOV */ 2732 if (!adapter->vf_data) { 2733 adapter->vfs_allocated_count = 0; 2734 dev_err(&pdev->dev, 2735 "Unable to allocate memory for VF Data Storage\n"); 2736 err = -ENOMEM; 2737 goto out; 2738 } 2739 2740 /* only call pci_enable_sriov() if no VFs are allocated already */ 2741 if (!old_vfs) { 2742 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2743 if (err) 2744 goto err_out; 2745 } 2746 dev_info(&pdev->dev, "%d VFs allocated\n", 2747 adapter->vfs_allocated_count); 2748 for (i = 0; i < adapter->vfs_allocated_count; i++) 2749 igb_vf_configure(adapter, i); 2750 2751 /* DMA Coalescing is not supported in IOV mode. */ 2752 adapter->flags &= ~IGB_FLAG_DMAC; 2753 goto out; 2754 2755 err_out: 2756 kfree(adapter->vf_data); 2757 adapter->vf_data = NULL; 2758 adapter->vfs_allocated_count = 0; 2759 out: 2760 return err; 2761 } 2762 2763 #endif 2764 /** 2765 * igb_remove_i2c - Cleanup I2C interface 2766 * @adapter: pointer to adapter structure 2767 **/ 2768 static void igb_remove_i2c(struct igb_adapter *adapter) 2769 { 2770 /* free the adapter bus structure */ 2771 i2c_del_adapter(&adapter->i2c_adap); 2772 } 2773 2774 /** 2775 * igb_remove - Device Removal Routine 2776 * @pdev: PCI device information struct 2777 * 2778 * igb_remove is called by the PCI subsystem to alert the driver 2779 * that it should release a PCI device. The could be caused by a 2780 * Hot-Plug event, or because the driver is going to be removed from 2781 * memory. 2782 **/ 2783 static void igb_remove(struct pci_dev *pdev) 2784 { 2785 struct net_device *netdev = pci_get_drvdata(pdev); 2786 struct igb_adapter *adapter = netdev_priv(netdev); 2787 struct e1000_hw *hw = &adapter->hw; 2788 2789 pm_runtime_get_noresume(&pdev->dev); 2790 #ifdef CONFIG_IGB_HWMON 2791 igb_sysfs_exit(adapter); 2792 #endif 2793 igb_remove_i2c(adapter); 2794 igb_ptp_stop(adapter); 2795 /* The watchdog timer may be rescheduled, so explicitly 2796 * disable watchdog from being rescheduled. 2797 */ 2798 set_bit(__IGB_DOWN, &adapter->state); 2799 del_timer_sync(&adapter->watchdog_timer); 2800 del_timer_sync(&adapter->phy_info_timer); 2801 2802 cancel_work_sync(&adapter->reset_task); 2803 cancel_work_sync(&adapter->watchdog_task); 2804 2805 #ifdef CONFIG_IGB_DCA 2806 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2807 dev_info(&pdev->dev, "DCA disabled\n"); 2808 dca_remove_requester(&pdev->dev); 2809 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2811 } 2812 #endif 2813 2814 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2815 * would have already happened in close and is redundant. 2816 */ 2817 igb_release_hw_control(adapter); 2818 2819 #ifdef CONFIG_PCI_IOV 2820 igb_disable_sriov(pdev); 2821 #endif 2822 2823 unregister_netdev(netdev); 2824 2825 igb_clear_interrupt_scheme(adapter); 2826 2827 pci_iounmap(pdev, adapter->io_addr); 2828 if (hw->flash_address) 2829 iounmap(hw->flash_address); 2830 pci_release_selected_regions(pdev, 2831 pci_select_bars(pdev, IORESOURCE_MEM)); 2832 2833 kfree(adapter->shadow_vfta); 2834 free_netdev(netdev); 2835 2836 pci_disable_pcie_error_reporting(pdev); 2837 2838 pci_disable_device(pdev); 2839 } 2840 2841 /** 2842 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2843 * @adapter: board private structure to initialize 2844 * 2845 * This function initializes the vf specific data storage and then attempts to 2846 * allocate the VFs. The reason for ordering it this way is because it is much 2847 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2848 * the memory for the VFs. 2849 **/ 2850 static void igb_probe_vfs(struct igb_adapter *adapter) 2851 { 2852 #ifdef CONFIG_PCI_IOV 2853 struct pci_dev *pdev = adapter->pdev; 2854 struct e1000_hw *hw = &adapter->hw; 2855 2856 /* Virtualization features not supported on i210 family. */ 2857 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2858 return; 2859 2860 /* Of the below we really only want the effect of getting 2861 * IGB_FLAG_HAS_MSIX set (if available), without which 2862 * igb_enable_sriov() has no effect. 2863 */ 2864 igb_set_interrupt_capability(adapter, true); 2865 igb_reset_interrupt_capability(adapter); 2866 2867 pci_sriov_set_totalvfs(pdev, 7); 2868 igb_enable_sriov(pdev, max_vfs); 2869 2870 #endif /* CONFIG_PCI_IOV */ 2871 } 2872 2873 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2874 { 2875 struct e1000_hw *hw = &adapter->hw; 2876 u32 max_rss_queues; 2877 2878 /* Determine the maximum number of RSS queues supported. */ 2879 switch (hw->mac.type) { 2880 case e1000_i211: 2881 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2882 break; 2883 case e1000_82575: 2884 case e1000_i210: 2885 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2886 break; 2887 case e1000_i350: 2888 /* I350 cannot do RSS and SR-IOV at the same time */ 2889 if (!!adapter->vfs_allocated_count) { 2890 max_rss_queues = 1; 2891 break; 2892 } 2893 /* fall through */ 2894 case e1000_82576: 2895 if (!!adapter->vfs_allocated_count) { 2896 max_rss_queues = 2; 2897 break; 2898 } 2899 /* fall through */ 2900 case e1000_82580: 2901 case e1000_i354: 2902 default: 2903 max_rss_queues = IGB_MAX_RX_QUEUES; 2904 break; 2905 } 2906 2907 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2908 2909 igb_set_flag_queue_pairs(adapter, max_rss_queues); 2910 } 2911 2912 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 2913 const u32 max_rss_queues) 2914 { 2915 struct e1000_hw *hw = &adapter->hw; 2916 2917 /* Determine if we need to pair queues. */ 2918 switch (hw->mac.type) { 2919 case e1000_82575: 2920 case e1000_i211: 2921 /* Device supports enough interrupts without queue pairing. */ 2922 break; 2923 case e1000_82576: 2924 /* If VFs are going to be allocated with RSS queues then we 2925 * should pair the queues in order to conserve interrupts due 2926 * to limited supply. 2927 */ 2928 if ((adapter->rss_queues > 1) && 2929 (adapter->vfs_allocated_count > 6)) 2930 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2931 /* fall through */ 2932 case e1000_82580: 2933 case e1000_i350: 2934 case e1000_i354: 2935 case e1000_i210: 2936 default: 2937 /* If rss_queues > half of max_rss_queues, pair the queues in 2938 * order to conserve interrupts due to limited supply. 2939 */ 2940 if (adapter->rss_queues > (max_rss_queues / 2)) 2941 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2942 break; 2943 } 2944 } 2945 2946 /** 2947 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2948 * @adapter: board private structure to initialize 2949 * 2950 * igb_sw_init initializes the Adapter private data structure. 2951 * Fields are initialized based on PCI device information and 2952 * OS network device settings (MTU size). 2953 **/ 2954 static int igb_sw_init(struct igb_adapter *adapter) 2955 { 2956 struct e1000_hw *hw = &adapter->hw; 2957 struct net_device *netdev = adapter->netdev; 2958 struct pci_dev *pdev = adapter->pdev; 2959 2960 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2961 2962 /* set default ring sizes */ 2963 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2964 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2965 2966 /* set default ITR values */ 2967 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2968 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2969 2970 /* set default work limits */ 2971 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2972 2973 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2974 VLAN_HLEN; 2975 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2976 2977 spin_lock_init(&adapter->stats64_lock); 2978 #ifdef CONFIG_PCI_IOV 2979 switch (hw->mac.type) { 2980 case e1000_82576: 2981 case e1000_i350: 2982 if (max_vfs > 7) { 2983 dev_warn(&pdev->dev, 2984 "Maximum of 7 VFs per PF, using max\n"); 2985 max_vfs = adapter->vfs_allocated_count = 7; 2986 } else 2987 adapter->vfs_allocated_count = max_vfs; 2988 if (adapter->vfs_allocated_count) 2989 dev_warn(&pdev->dev, 2990 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2991 break; 2992 default: 2993 break; 2994 } 2995 #endif /* CONFIG_PCI_IOV */ 2996 2997 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 2998 adapter->flags |= IGB_FLAG_HAS_MSIX; 2999 3000 igb_probe_vfs(adapter); 3001 3002 igb_init_queue_configuration(adapter); 3003 3004 /* Setup and initialize a copy of the hw vlan table array */ 3005 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3006 GFP_ATOMIC); 3007 3008 /* This call may decrease the number of queues */ 3009 if (igb_init_interrupt_scheme(adapter, true)) { 3010 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3011 return -ENOMEM; 3012 } 3013 3014 /* Explicitly disable IRQ since the NIC can be in any state. */ 3015 igb_irq_disable(adapter); 3016 3017 if (hw->mac.type >= e1000_i350) 3018 adapter->flags &= ~IGB_FLAG_DMAC; 3019 3020 set_bit(__IGB_DOWN, &adapter->state); 3021 return 0; 3022 } 3023 3024 /** 3025 * igb_open - Called when a network interface is made active 3026 * @netdev: network interface device structure 3027 * 3028 * Returns 0 on success, negative value on failure 3029 * 3030 * The open entry point is called when a network interface is made 3031 * active by the system (IFF_UP). At this point all resources needed 3032 * for transmit and receive operations are allocated, the interrupt 3033 * handler is registered with the OS, the watchdog timer is started, 3034 * and the stack is notified that the interface is ready. 3035 **/ 3036 static int __igb_open(struct net_device *netdev, bool resuming) 3037 { 3038 struct igb_adapter *adapter = netdev_priv(netdev); 3039 struct e1000_hw *hw = &adapter->hw; 3040 struct pci_dev *pdev = adapter->pdev; 3041 int err; 3042 int i; 3043 3044 /* disallow open during test */ 3045 if (test_bit(__IGB_TESTING, &adapter->state)) { 3046 WARN_ON(resuming); 3047 return -EBUSY; 3048 } 3049 3050 if (!resuming) 3051 pm_runtime_get_sync(&pdev->dev); 3052 3053 netif_carrier_off(netdev); 3054 3055 /* allocate transmit descriptors */ 3056 err = igb_setup_all_tx_resources(adapter); 3057 if (err) 3058 goto err_setup_tx; 3059 3060 /* allocate receive descriptors */ 3061 err = igb_setup_all_rx_resources(adapter); 3062 if (err) 3063 goto err_setup_rx; 3064 3065 igb_power_up_link(adapter); 3066 3067 /* before we allocate an interrupt, we must be ready to handle it. 3068 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3069 * as soon as we call pci_request_irq, so we have to setup our 3070 * clean_rx handler before we do so. 3071 */ 3072 igb_configure(adapter); 3073 3074 err = igb_request_irq(adapter); 3075 if (err) 3076 goto err_req_irq; 3077 3078 /* Notify the stack of the actual queue counts. */ 3079 err = netif_set_real_num_tx_queues(adapter->netdev, 3080 adapter->num_tx_queues); 3081 if (err) 3082 goto err_set_queues; 3083 3084 err = netif_set_real_num_rx_queues(adapter->netdev, 3085 adapter->num_rx_queues); 3086 if (err) 3087 goto err_set_queues; 3088 3089 /* From here on the code is the same as igb_up() */ 3090 clear_bit(__IGB_DOWN, &adapter->state); 3091 3092 for (i = 0; i < adapter->num_q_vectors; i++) 3093 napi_enable(&(adapter->q_vector[i]->napi)); 3094 3095 /* Clear any pending interrupts. */ 3096 rd32(E1000_ICR); 3097 3098 igb_irq_enable(adapter); 3099 3100 /* notify VFs that reset has been completed */ 3101 if (adapter->vfs_allocated_count) { 3102 u32 reg_data = rd32(E1000_CTRL_EXT); 3103 3104 reg_data |= E1000_CTRL_EXT_PFRSTD; 3105 wr32(E1000_CTRL_EXT, reg_data); 3106 } 3107 3108 netif_tx_start_all_queues(netdev); 3109 3110 if (!resuming) 3111 pm_runtime_put(&pdev->dev); 3112 3113 /* start the watchdog. */ 3114 hw->mac.get_link_status = 1; 3115 schedule_work(&adapter->watchdog_task); 3116 3117 return 0; 3118 3119 err_set_queues: 3120 igb_free_irq(adapter); 3121 err_req_irq: 3122 igb_release_hw_control(adapter); 3123 igb_power_down_link(adapter); 3124 igb_free_all_rx_resources(adapter); 3125 err_setup_rx: 3126 igb_free_all_tx_resources(adapter); 3127 err_setup_tx: 3128 igb_reset(adapter); 3129 if (!resuming) 3130 pm_runtime_put(&pdev->dev); 3131 3132 return err; 3133 } 3134 3135 static int igb_open(struct net_device *netdev) 3136 { 3137 return __igb_open(netdev, false); 3138 } 3139 3140 /** 3141 * igb_close - Disables a network interface 3142 * @netdev: network interface device structure 3143 * 3144 * Returns 0, this is not allowed to fail 3145 * 3146 * The close entry point is called when an interface is de-activated 3147 * by the OS. The hardware is still under the driver's control, but 3148 * needs to be disabled. A global MAC reset is issued to stop the 3149 * hardware, and all transmit and receive resources are freed. 3150 **/ 3151 static int __igb_close(struct net_device *netdev, bool suspending) 3152 { 3153 struct igb_adapter *adapter = netdev_priv(netdev); 3154 struct pci_dev *pdev = adapter->pdev; 3155 3156 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3157 3158 if (!suspending) 3159 pm_runtime_get_sync(&pdev->dev); 3160 3161 igb_down(adapter); 3162 igb_free_irq(adapter); 3163 3164 igb_free_all_tx_resources(adapter); 3165 igb_free_all_rx_resources(adapter); 3166 3167 if (!suspending) 3168 pm_runtime_put_sync(&pdev->dev); 3169 return 0; 3170 } 3171 3172 static int igb_close(struct net_device *netdev) 3173 { 3174 return __igb_close(netdev, false); 3175 } 3176 3177 /** 3178 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3179 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3180 * 3181 * Return 0 on success, negative on failure 3182 **/ 3183 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3184 { 3185 struct device *dev = tx_ring->dev; 3186 int size; 3187 3188 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3189 3190 tx_ring->tx_buffer_info = vzalloc(size); 3191 if (!tx_ring->tx_buffer_info) 3192 goto err; 3193 3194 /* round up to nearest 4K */ 3195 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3196 tx_ring->size = ALIGN(tx_ring->size, 4096); 3197 3198 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3199 &tx_ring->dma, GFP_KERNEL); 3200 if (!tx_ring->desc) 3201 goto err; 3202 3203 tx_ring->next_to_use = 0; 3204 tx_ring->next_to_clean = 0; 3205 3206 return 0; 3207 3208 err: 3209 vfree(tx_ring->tx_buffer_info); 3210 tx_ring->tx_buffer_info = NULL; 3211 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3212 return -ENOMEM; 3213 } 3214 3215 /** 3216 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3217 * (Descriptors) for all queues 3218 * @adapter: board private structure 3219 * 3220 * Return 0 on success, negative on failure 3221 **/ 3222 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3223 { 3224 struct pci_dev *pdev = adapter->pdev; 3225 int i, err = 0; 3226 3227 for (i = 0; i < adapter->num_tx_queues; i++) { 3228 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3229 if (err) { 3230 dev_err(&pdev->dev, 3231 "Allocation for Tx Queue %u failed\n", i); 3232 for (i--; i >= 0; i--) 3233 igb_free_tx_resources(adapter->tx_ring[i]); 3234 break; 3235 } 3236 } 3237 3238 return err; 3239 } 3240 3241 /** 3242 * igb_setup_tctl - configure the transmit control registers 3243 * @adapter: Board private structure 3244 **/ 3245 void igb_setup_tctl(struct igb_adapter *adapter) 3246 { 3247 struct e1000_hw *hw = &adapter->hw; 3248 u32 tctl; 3249 3250 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3251 wr32(E1000_TXDCTL(0), 0); 3252 3253 /* Program the Transmit Control Register */ 3254 tctl = rd32(E1000_TCTL); 3255 tctl &= ~E1000_TCTL_CT; 3256 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3257 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3258 3259 igb_config_collision_dist(hw); 3260 3261 /* Enable transmits */ 3262 tctl |= E1000_TCTL_EN; 3263 3264 wr32(E1000_TCTL, tctl); 3265 } 3266 3267 /** 3268 * igb_configure_tx_ring - Configure transmit ring after Reset 3269 * @adapter: board private structure 3270 * @ring: tx ring to configure 3271 * 3272 * Configure a transmit ring after a reset. 3273 **/ 3274 void igb_configure_tx_ring(struct igb_adapter *adapter, 3275 struct igb_ring *ring) 3276 { 3277 struct e1000_hw *hw = &adapter->hw; 3278 u32 txdctl = 0; 3279 u64 tdba = ring->dma; 3280 int reg_idx = ring->reg_idx; 3281 3282 /* disable the queue */ 3283 wr32(E1000_TXDCTL(reg_idx), 0); 3284 wrfl(); 3285 mdelay(10); 3286 3287 wr32(E1000_TDLEN(reg_idx), 3288 ring->count * sizeof(union e1000_adv_tx_desc)); 3289 wr32(E1000_TDBAL(reg_idx), 3290 tdba & 0x00000000ffffffffULL); 3291 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3292 3293 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3294 wr32(E1000_TDH(reg_idx), 0); 3295 writel(0, ring->tail); 3296 3297 txdctl |= IGB_TX_PTHRESH; 3298 txdctl |= IGB_TX_HTHRESH << 8; 3299 txdctl |= IGB_TX_WTHRESH << 16; 3300 3301 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3302 wr32(E1000_TXDCTL(reg_idx), txdctl); 3303 } 3304 3305 /** 3306 * igb_configure_tx - Configure transmit Unit after Reset 3307 * @adapter: board private structure 3308 * 3309 * Configure the Tx unit of the MAC after a reset. 3310 **/ 3311 static void igb_configure_tx(struct igb_adapter *adapter) 3312 { 3313 int i; 3314 3315 for (i = 0; i < adapter->num_tx_queues; i++) 3316 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3317 } 3318 3319 /** 3320 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3321 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3322 * 3323 * Returns 0 on success, negative on failure 3324 **/ 3325 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3326 { 3327 struct device *dev = rx_ring->dev; 3328 int size; 3329 3330 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3331 3332 rx_ring->rx_buffer_info = vzalloc(size); 3333 if (!rx_ring->rx_buffer_info) 3334 goto err; 3335 3336 /* Round up to nearest 4K */ 3337 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3338 rx_ring->size = ALIGN(rx_ring->size, 4096); 3339 3340 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3341 &rx_ring->dma, GFP_KERNEL); 3342 if (!rx_ring->desc) 3343 goto err; 3344 3345 rx_ring->next_to_alloc = 0; 3346 rx_ring->next_to_clean = 0; 3347 rx_ring->next_to_use = 0; 3348 3349 return 0; 3350 3351 err: 3352 vfree(rx_ring->rx_buffer_info); 3353 rx_ring->rx_buffer_info = NULL; 3354 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3355 return -ENOMEM; 3356 } 3357 3358 /** 3359 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3360 * (Descriptors) for all queues 3361 * @adapter: board private structure 3362 * 3363 * Return 0 on success, negative on failure 3364 **/ 3365 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3366 { 3367 struct pci_dev *pdev = adapter->pdev; 3368 int i, err = 0; 3369 3370 for (i = 0; i < adapter->num_rx_queues; i++) { 3371 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3372 if (err) { 3373 dev_err(&pdev->dev, 3374 "Allocation for Rx Queue %u failed\n", i); 3375 for (i--; i >= 0; i--) 3376 igb_free_rx_resources(adapter->rx_ring[i]); 3377 break; 3378 } 3379 } 3380 3381 return err; 3382 } 3383 3384 /** 3385 * igb_setup_mrqc - configure the multiple receive queue control registers 3386 * @adapter: Board private structure 3387 **/ 3388 static void igb_setup_mrqc(struct igb_adapter *adapter) 3389 { 3390 struct e1000_hw *hw = &adapter->hw; 3391 u32 mrqc, rxcsum; 3392 u32 j, num_rx_queues; 3393 u32 rss_key[10]; 3394 3395 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3396 for (j = 0; j < 10; j++) 3397 wr32(E1000_RSSRK(j), rss_key[j]); 3398 3399 num_rx_queues = adapter->rss_queues; 3400 3401 switch (hw->mac.type) { 3402 case e1000_82576: 3403 /* 82576 supports 2 RSS queues for SR-IOV */ 3404 if (adapter->vfs_allocated_count) 3405 num_rx_queues = 2; 3406 break; 3407 default: 3408 break; 3409 } 3410 3411 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3412 for (j = 0; j < IGB_RETA_SIZE; j++) 3413 adapter->rss_indir_tbl[j] = 3414 (j * num_rx_queues) / IGB_RETA_SIZE; 3415 adapter->rss_indir_tbl_init = num_rx_queues; 3416 } 3417 igb_write_rss_indir_tbl(adapter); 3418 3419 /* Disable raw packet checksumming so that RSS hash is placed in 3420 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3421 * offloads as they are enabled by default 3422 */ 3423 rxcsum = rd32(E1000_RXCSUM); 3424 rxcsum |= E1000_RXCSUM_PCSD; 3425 3426 if (adapter->hw.mac.type >= e1000_82576) 3427 /* Enable Receive Checksum Offload for SCTP */ 3428 rxcsum |= E1000_RXCSUM_CRCOFL; 3429 3430 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3431 wr32(E1000_RXCSUM, rxcsum); 3432 3433 /* Generate RSS hash based on packet types, TCP/UDP 3434 * port numbers and/or IPv4/v6 src and dst addresses 3435 */ 3436 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3437 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3438 E1000_MRQC_RSS_FIELD_IPV6 | 3439 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3440 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3441 3442 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3443 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3444 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3445 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3446 3447 /* If VMDq is enabled then we set the appropriate mode for that, else 3448 * we default to RSS so that an RSS hash is calculated per packet even 3449 * if we are only using one queue 3450 */ 3451 if (adapter->vfs_allocated_count) { 3452 if (hw->mac.type > e1000_82575) { 3453 /* Set the default pool for the PF's first queue */ 3454 u32 vtctl = rd32(E1000_VT_CTL); 3455 3456 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3457 E1000_VT_CTL_DISABLE_DEF_POOL); 3458 vtctl |= adapter->vfs_allocated_count << 3459 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3460 wr32(E1000_VT_CTL, vtctl); 3461 } 3462 if (adapter->rss_queues > 1) 3463 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3464 else 3465 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3466 } else { 3467 if (hw->mac.type != e1000_i211) 3468 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3469 } 3470 igb_vmm_control(adapter); 3471 3472 wr32(E1000_MRQC, mrqc); 3473 } 3474 3475 /** 3476 * igb_setup_rctl - configure the receive control registers 3477 * @adapter: Board private structure 3478 **/ 3479 void igb_setup_rctl(struct igb_adapter *adapter) 3480 { 3481 struct e1000_hw *hw = &adapter->hw; 3482 u32 rctl; 3483 3484 rctl = rd32(E1000_RCTL); 3485 3486 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3487 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3488 3489 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3490 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3491 3492 /* enable stripping of CRC. It's unlikely this will break BMC 3493 * redirection as it did with e1000. Newer features require 3494 * that the HW strips the CRC. 3495 */ 3496 rctl |= E1000_RCTL_SECRC; 3497 3498 /* disable store bad packets and clear size bits. */ 3499 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3500 3501 /* enable LPE to prevent packets larger than max_frame_size */ 3502 rctl |= E1000_RCTL_LPE; 3503 3504 /* disable queue 0 to prevent tail write w/o re-config */ 3505 wr32(E1000_RXDCTL(0), 0); 3506 3507 /* Attention!!! For SR-IOV PF driver operations you must enable 3508 * queue drop for all VF and PF queues to prevent head of line blocking 3509 * if an un-trusted VF does not provide descriptors to hardware. 3510 */ 3511 if (adapter->vfs_allocated_count) { 3512 /* set all queue drop enable bits */ 3513 wr32(E1000_QDE, ALL_QUEUES); 3514 } 3515 3516 /* This is useful for sniffing bad packets. */ 3517 if (adapter->netdev->features & NETIF_F_RXALL) { 3518 /* UPE and MPE will be handled by normal PROMISC logic 3519 * in e1000e_set_rx_mode 3520 */ 3521 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3522 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3523 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3524 3525 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3526 E1000_RCTL_DPF | /* Allow filtered pause */ 3527 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3528 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3529 * and that breaks VLANs. 3530 */ 3531 } 3532 3533 wr32(E1000_RCTL, rctl); 3534 } 3535 3536 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3537 int vfn) 3538 { 3539 struct e1000_hw *hw = &adapter->hw; 3540 u32 vmolr; 3541 3542 /* if it isn't the PF check to see if VFs are enabled and 3543 * increase the size to support vlan tags 3544 */ 3545 if (vfn < adapter->vfs_allocated_count && 3546 adapter->vf_data[vfn].vlans_enabled) 3547 size += VLAN_TAG_SIZE; 3548 3549 vmolr = rd32(E1000_VMOLR(vfn)); 3550 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3551 vmolr |= size | E1000_VMOLR_LPE; 3552 wr32(E1000_VMOLR(vfn), vmolr); 3553 3554 return 0; 3555 } 3556 3557 /** 3558 * igb_rlpml_set - set maximum receive packet size 3559 * @adapter: board private structure 3560 * 3561 * Configure maximum receivable packet size. 3562 **/ 3563 static void igb_rlpml_set(struct igb_adapter *adapter) 3564 { 3565 u32 max_frame_size = adapter->max_frame_size; 3566 struct e1000_hw *hw = &adapter->hw; 3567 u16 pf_id = adapter->vfs_allocated_count; 3568 3569 if (pf_id) { 3570 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3571 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3572 * to our max jumbo frame size, in case we need to enable 3573 * jumbo frames on one of the rings later. 3574 * This will not pass over-length frames into the default 3575 * queue because it's gated by the VMOLR.RLPML. 3576 */ 3577 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3578 } 3579 3580 wr32(E1000_RLPML, max_frame_size); 3581 } 3582 3583 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3584 int vfn, bool aupe) 3585 { 3586 struct e1000_hw *hw = &adapter->hw; 3587 u32 vmolr; 3588 3589 /* This register exists only on 82576 and newer so if we are older then 3590 * we should exit and do nothing 3591 */ 3592 if (hw->mac.type < e1000_82576) 3593 return; 3594 3595 vmolr = rd32(E1000_VMOLR(vfn)); 3596 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3597 if (hw->mac.type == e1000_i350) { 3598 u32 dvmolr; 3599 3600 dvmolr = rd32(E1000_DVMOLR(vfn)); 3601 dvmolr |= E1000_DVMOLR_STRVLAN; 3602 wr32(E1000_DVMOLR(vfn), dvmolr); 3603 } 3604 if (aupe) 3605 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3606 else 3607 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3608 3609 /* clear all bits that might not be set */ 3610 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3611 3612 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3613 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3614 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3615 * multicast packets 3616 */ 3617 if (vfn <= adapter->vfs_allocated_count) 3618 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3619 3620 wr32(E1000_VMOLR(vfn), vmolr); 3621 } 3622 3623 /** 3624 * igb_configure_rx_ring - Configure a receive ring after Reset 3625 * @adapter: board private structure 3626 * @ring: receive ring to be configured 3627 * 3628 * Configure the Rx unit of the MAC after a reset. 3629 **/ 3630 void igb_configure_rx_ring(struct igb_adapter *adapter, 3631 struct igb_ring *ring) 3632 { 3633 struct e1000_hw *hw = &adapter->hw; 3634 u64 rdba = ring->dma; 3635 int reg_idx = ring->reg_idx; 3636 u32 srrctl = 0, rxdctl = 0; 3637 3638 /* disable the queue */ 3639 wr32(E1000_RXDCTL(reg_idx), 0); 3640 3641 /* Set DMA base address registers */ 3642 wr32(E1000_RDBAL(reg_idx), 3643 rdba & 0x00000000ffffffffULL); 3644 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3645 wr32(E1000_RDLEN(reg_idx), 3646 ring->count * sizeof(union e1000_adv_rx_desc)); 3647 3648 /* initialize head and tail */ 3649 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3650 wr32(E1000_RDH(reg_idx), 0); 3651 writel(0, ring->tail); 3652 3653 /* set descriptor configuration */ 3654 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3655 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3656 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3657 if (hw->mac.type >= e1000_82580) 3658 srrctl |= E1000_SRRCTL_TIMESTAMP; 3659 /* Only set Drop Enable if we are supporting multiple queues */ 3660 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3661 srrctl |= E1000_SRRCTL_DROP_EN; 3662 3663 wr32(E1000_SRRCTL(reg_idx), srrctl); 3664 3665 /* set filtering for VMDQ pools */ 3666 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3667 3668 rxdctl |= IGB_RX_PTHRESH; 3669 rxdctl |= IGB_RX_HTHRESH << 8; 3670 rxdctl |= IGB_RX_WTHRESH << 16; 3671 3672 /* enable receive descriptor fetching */ 3673 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3674 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3675 } 3676 3677 /** 3678 * igb_configure_rx - Configure receive Unit after Reset 3679 * @adapter: board private structure 3680 * 3681 * Configure the Rx unit of the MAC after a reset. 3682 **/ 3683 static void igb_configure_rx(struct igb_adapter *adapter) 3684 { 3685 int i; 3686 3687 /* set UTA to appropriate mode */ 3688 igb_set_uta(adapter); 3689 3690 /* set the correct pool for the PF default MAC address in entry 0 */ 3691 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3692 adapter->vfs_allocated_count); 3693 3694 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3695 * the Base and Length of the Rx Descriptor Ring 3696 */ 3697 for (i = 0; i < adapter->num_rx_queues; i++) 3698 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3699 } 3700 3701 /** 3702 * igb_free_tx_resources - Free Tx Resources per Queue 3703 * @tx_ring: Tx descriptor ring for a specific queue 3704 * 3705 * Free all transmit software resources 3706 **/ 3707 void igb_free_tx_resources(struct igb_ring *tx_ring) 3708 { 3709 igb_clean_tx_ring(tx_ring); 3710 3711 vfree(tx_ring->tx_buffer_info); 3712 tx_ring->tx_buffer_info = NULL; 3713 3714 /* if not set, then don't free */ 3715 if (!tx_ring->desc) 3716 return; 3717 3718 dma_free_coherent(tx_ring->dev, tx_ring->size, 3719 tx_ring->desc, tx_ring->dma); 3720 3721 tx_ring->desc = NULL; 3722 } 3723 3724 /** 3725 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3726 * @adapter: board private structure 3727 * 3728 * Free all transmit software resources 3729 **/ 3730 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3731 { 3732 int i; 3733 3734 for (i = 0; i < adapter->num_tx_queues; i++) 3735 if (adapter->tx_ring[i]) 3736 igb_free_tx_resources(adapter->tx_ring[i]); 3737 } 3738 3739 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3740 struct igb_tx_buffer *tx_buffer) 3741 { 3742 if (tx_buffer->skb) { 3743 dev_kfree_skb_any(tx_buffer->skb); 3744 if (dma_unmap_len(tx_buffer, len)) 3745 dma_unmap_single(ring->dev, 3746 dma_unmap_addr(tx_buffer, dma), 3747 dma_unmap_len(tx_buffer, len), 3748 DMA_TO_DEVICE); 3749 } else if (dma_unmap_len(tx_buffer, len)) { 3750 dma_unmap_page(ring->dev, 3751 dma_unmap_addr(tx_buffer, dma), 3752 dma_unmap_len(tx_buffer, len), 3753 DMA_TO_DEVICE); 3754 } 3755 tx_buffer->next_to_watch = NULL; 3756 tx_buffer->skb = NULL; 3757 dma_unmap_len_set(tx_buffer, len, 0); 3758 /* buffer_info must be completely set up in the transmit path */ 3759 } 3760 3761 /** 3762 * igb_clean_tx_ring - Free Tx Buffers 3763 * @tx_ring: ring to be cleaned 3764 **/ 3765 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3766 { 3767 struct igb_tx_buffer *buffer_info; 3768 unsigned long size; 3769 u16 i; 3770 3771 if (!tx_ring->tx_buffer_info) 3772 return; 3773 /* Free all the Tx ring sk_buffs */ 3774 3775 for (i = 0; i < tx_ring->count; i++) { 3776 buffer_info = &tx_ring->tx_buffer_info[i]; 3777 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3778 } 3779 3780 netdev_tx_reset_queue(txring_txq(tx_ring)); 3781 3782 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3783 memset(tx_ring->tx_buffer_info, 0, size); 3784 3785 /* Zero out the descriptor ring */ 3786 memset(tx_ring->desc, 0, tx_ring->size); 3787 3788 tx_ring->next_to_use = 0; 3789 tx_ring->next_to_clean = 0; 3790 } 3791 3792 /** 3793 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3794 * @adapter: board private structure 3795 **/ 3796 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3797 { 3798 int i; 3799 3800 for (i = 0; i < adapter->num_tx_queues; i++) 3801 if (adapter->tx_ring[i]) 3802 igb_clean_tx_ring(adapter->tx_ring[i]); 3803 } 3804 3805 /** 3806 * igb_free_rx_resources - Free Rx Resources 3807 * @rx_ring: ring to clean the resources from 3808 * 3809 * Free all receive software resources 3810 **/ 3811 void igb_free_rx_resources(struct igb_ring *rx_ring) 3812 { 3813 igb_clean_rx_ring(rx_ring); 3814 3815 vfree(rx_ring->rx_buffer_info); 3816 rx_ring->rx_buffer_info = NULL; 3817 3818 /* if not set, then don't free */ 3819 if (!rx_ring->desc) 3820 return; 3821 3822 dma_free_coherent(rx_ring->dev, rx_ring->size, 3823 rx_ring->desc, rx_ring->dma); 3824 3825 rx_ring->desc = NULL; 3826 } 3827 3828 /** 3829 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3830 * @adapter: board private structure 3831 * 3832 * Free all receive software resources 3833 **/ 3834 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3835 { 3836 int i; 3837 3838 for (i = 0; i < adapter->num_rx_queues; i++) 3839 if (adapter->rx_ring[i]) 3840 igb_free_rx_resources(adapter->rx_ring[i]); 3841 } 3842 3843 /** 3844 * igb_clean_rx_ring - Free Rx Buffers per Queue 3845 * @rx_ring: ring to free buffers from 3846 **/ 3847 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3848 { 3849 unsigned long size; 3850 u16 i; 3851 3852 if (rx_ring->skb) 3853 dev_kfree_skb(rx_ring->skb); 3854 rx_ring->skb = NULL; 3855 3856 if (!rx_ring->rx_buffer_info) 3857 return; 3858 3859 /* Free all the Rx ring sk_buffs */ 3860 for (i = 0; i < rx_ring->count; i++) { 3861 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3862 3863 if (!buffer_info->page) 3864 continue; 3865 3866 dma_unmap_page(rx_ring->dev, 3867 buffer_info->dma, 3868 PAGE_SIZE, 3869 DMA_FROM_DEVICE); 3870 __free_page(buffer_info->page); 3871 3872 buffer_info->page = NULL; 3873 } 3874 3875 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3876 memset(rx_ring->rx_buffer_info, 0, size); 3877 3878 /* Zero out the descriptor ring */ 3879 memset(rx_ring->desc, 0, rx_ring->size); 3880 3881 rx_ring->next_to_alloc = 0; 3882 rx_ring->next_to_clean = 0; 3883 rx_ring->next_to_use = 0; 3884 } 3885 3886 /** 3887 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3888 * @adapter: board private structure 3889 **/ 3890 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3891 { 3892 int i; 3893 3894 for (i = 0; i < adapter->num_rx_queues; i++) 3895 if (adapter->rx_ring[i]) 3896 igb_clean_rx_ring(adapter->rx_ring[i]); 3897 } 3898 3899 /** 3900 * igb_set_mac - Change the Ethernet Address of the NIC 3901 * @netdev: network interface device structure 3902 * @p: pointer to an address structure 3903 * 3904 * Returns 0 on success, negative on failure 3905 **/ 3906 static int igb_set_mac(struct net_device *netdev, void *p) 3907 { 3908 struct igb_adapter *adapter = netdev_priv(netdev); 3909 struct e1000_hw *hw = &adapter->hw; 3910 struct sockaddr *addr = p; 3911 3912 if (!is_valid_ether_addr(addr->sa_data)) 3913 return -EADDRNOTAVAIL; 3914 3915 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3916 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3917 3918 /* set the correct pool for the new PF MAC address in entry 0 */ 3919 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3920 adapter->vfs_allocated_count); 3921 3922 return 0; 3923 } 3924 3925 /** 3926 * igb_write_mc_addr_list - write multicast addresses to MTA 3927 * @netdev: network interface device structure 3928 * 3929 * Writes multicast address list to the MTA hash table. 3930 * Returns: -ENOMEM on failure 3931 * 0 on no addresses written 3932 * X on writing X addresses to MTA 3933 **/ 3934 static int igb_write_mc_addr_list(struct net_device *netdev) 3935 { 3936 struct igb_adapter *adapter = netdev_priv(netdev); 3937 struct e1000_hw *hw = &adapter->hw; 3938 struct netdev_hw_addr *ha; 3939 u8 *mta_list; 3940 int i; 3941 3942 if (netdev_mc_empty(netdev)) { 3943 /* nothing to program, so clear mc list */ 3944 igb_update_mc_addr_list(hw, NULL, 0); 3945 igb_restore_vf_multicasts(adapter); 3946 return 0; 3947 } 3948 3949 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3950 if (!mta_list) 3951 return -ENOMEM; 3952 3953 /* The shared function expects a packed array of only addresses. */ 3954 i = 0; 3955 netdev_for_each_mc_addr(ha, netdev) 3956 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3957 3958 igb_update_mc_addr_list(hw, mta_list, i); 3959 kfree(mta_list); 3960 3961 return netdev_mc_count(netdev); 3962 } 3963 3964 /** 3965 * igb_write_uc_addr_list - write unicast addresses to RAR table 3966 * @netdev: network interface device structure 3967 * 3968 * Writes unicast address list to the RAR table. 3969 * Returns: -ENOMEM on failure/insufficient address space 3970 * 0 on no addresses written 3971 * X on writing X addresses to the RAR table 3972 **/ 3973 static int igb_write_uc_addr_list(struct net_device *netdev) 3974 { 3975 struct igb_adapter *adapter = netdev_priv(netdev); 3976 struct e1000_hw *hw = &adapter->hw; 3977 unsigned int vfn = adapter->vfs_allocated_count; 3978 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3979 int count = 0; 3980 3981 /* return ENOMEM indicating insufficient memory for addresses */ 3982 if (netdev_uc_count(netdev) > rar_entries) 3983 return -ENOMEM; 3984 3985 if (!netdev_uc_empty(netdev) && rar_entries) { 3986 struct netdev_hw_addr *ha; 3987 3988 netdev_for_each_uc_addr(ha, netdev) { 3989 if (!rar_entries) 3990 break; 3991 igb_rar_set_qsel(adapter, ha->addr, 3992 rar_entries--, 3993 vfn); 3994 count++; 3995 } 3996 } 3997 /* write the addresses in reverse order to avoid write combining */ 3998 for (; rar_entries > 0 ; rar_entries--) { 3999 wr32(E1000_RAH(rar_entries), 0); 4000 wr32(E1000_RAL(rar_entries), 0); 4001 } 4002 wrfl(); 4003 4004 return count; 4005 } 4006 4007 /** 4008 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4009 * @netdev: network interface device structure 4010 * 4011 * The set_rx_mode entry point is called whenever the unicast or multicast 4012 * address lists or the network interface flags are updated. This routine is 4013 * responsible for configuring the hardware for proper unicast, multicast, 4014 * promiscuous mode, and all-multi behavior. 4015 **/ 4016 static void igb_set_rx_mode(struct net_device *netdev) 4017 { 4018 struct igb_adapter *adapter = netdev_priv(netdev); 4019 struct e1000_hw *hw = &adapter->hw; 4020 unsigned int vfn = adapter->vfs_allocated_count; 4021 u32 rctl, vmolr = 0; 4022 int count; 4023 4024 /* Check for Promiscuous and All Multicast modes */ 4025 rctl = rd32(E1000_RCTL); 4026 4027 /* clear the effected bits */ 4028 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4029 4030 if (netdev->flags & IFF_PROMISC) { 4031 /* retain VLAN HW filtering if in VT mode */ 4032 if (adapter->vfs_allocated_count) 4033 rctl |= E1000_RCTL_VFE; 4034 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4035 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4036 } else { 4037 if (netdev->flags & IFF_ALLMULTI) { 4038 rctl |= E1000_RCTL_MPE; 4039 vmolr |= E1000_VMOLR_MPME; 4040 } else { 4041 /* Write addresses to the MTA, if the attempt fails 4042 * then we should just turn on promiscuous mode so 4043 * that we can at least receive multicast traffic 4044 */ 4045 count = igb_write_mc_addr_list(netdev); 4046 if (count < 0) { 4047 rctl |= E1000_RCTL_MPE; 4048 vmolr |= E1000_VMOLR_MPME; 4049 } else if (count) { 4050 vmolr |= E1000_VMOLR_ROMPE; 4051 } 4052 } 4053 /* Write addresses to available RAR registers, if there is not 4054 * sufficient space to store all the addresses then enable 4055 * unicast promiscuous mode 4056 */ 4057 count = igb_write_uc_addr_list(netdev); 4058 if (count < 0) { 4059 rctl |= E1000_RCTL_UPE; 4060 vmolr |= E1000_VMOLR_ROPE; 4061 } 4062 rctl |= E1000_RCTL_VFE; 4063 } 4064 wr32(E1000_RCTL, rctl); 4065 4066 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4067 * the VMOLR to enable the appropriate modes. Without this workaround 4068 * we will have issues with VLAN tag stripping not being done for frames 4069 * that are only arriving because we are the default pool 4070 */ 4071 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4072 return; 4073 4074 vmolr |= rd32(E1000_VMOLR(vfn)) & 4075 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4076 wr32(E1000_VMOLR(vfn), vmolr); 4077 igb_restore_vf_multicasts(adapter); 4078 } 4079 4080 static void igb_check_wvbr(struct igb_adapter *adapter) 4081 { 4082 struct e1000_hw *hw = &adapter->hw; 4083 u32 wvbr = 0; 4084 4085 switch (hw->mac.type) { 4086 case e1000_82576: 4087 case e1000_i350: 4088 wvbr = rd32(E1000_WVBR); 4089 if (!wvbr) 4090 return; 4091 break; 4092 default: 4093 break; 4094 } 4095 4096 adapter->wvbr |= wvbr; 4097 } 4098 4099 #define IGB_STAGGERED_QUEUE_OFFSET 8 4100 4101 static void igb_spoof_check(struct igb_adapter *adapter) 4102 { 4103 int j; 4104 4105 if (!adapter->wvbr) 4106 return; 4107 4108 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4109 if (adapter->wvbr & (1 << j) || 4110 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4111 dev_warn(&adapter->pdev->dev, 4112 "Spoof event(s) detected on VF %d\n", j); 4113 adapter->wvbr &= 4114 ~((1 << j) | 4115 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4116 } 4117 } 4118 } 4119 4120 /* Need to wait a few seconds after link up to get diagnostic information from 4121 * the phy 4122 */ 4123 static void igb_update_phy_info(unsigned long data) 4124 { 4125 struct igb_adapter *adapter = (struct igb_adapter *) data; 4126 igb_get_phy_info(&adapter->hw); 4127 } 4128 4129 /** 4130 * igb_has_link - check shared code for link and determine up/down 4131 * @adapter: pointer to driver private info 4132 **/ 4133 bool igb_has_link(struct igb_adapter *adapter) 4134 { 4135 struct e1000_hw *hw = &adapter->hw; 4136 bool link_active = false; 4137 4138 /* get_link_status is set on LSC (link status) interrupt or 4139 * rx sequence error interrupt. get_link_status will stay 4140 * false until the e1000_check_for_link establishes link 4141 * for copper adapters ONLY 4142 */ 4143 switch (hw->phy.media_type) { 4144 case e1000_media_type_copper: 4145 if (!hw->mac.get_link_status) 4146 return true; 4147 case e1000_media_type_internal_serdes: 4148 hw->mac.ops.check_for_link(hw); 4149 link_active = !hw->mac.get_link_status; 4150 break; 4151 default: 4152 case e1000_media_type_unknown: 4153 break; 4154 } 4155 4156 if (((hw->mac.type == e1000_i210) || 4157 (hw->mac.type == e1000_i211)) && 4158 (hw->phy.id == I210_I_PHY_ID)) { 4159 if (!netif_carrier_ok(adapter->netdev)) { 4160 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4161 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4162 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4163 adapter->link_check_timeout = jiffies; 4164 } 4165 } 4166 4167 return link_active; 4168 } 4169 4170 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4171 { 4172 bool ret = false; 4173 u32 ctrl_ext, thstat; 4174 4175 /* check for thermal sensor event on i350 copper only */ 4176 if (hw->mac.type == e1000_i350) { 4177 thstat = rd32(E1000_THSTAT); 4178 ctrl_ext = rd32(E1000_CTRL_EXT); 4179 4180 if ((hw->phy.media_type == e1000_media_type_copper) && 4181 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4182 ret = !!(thstat & event); 4183 } 4184 4185 return ret; 4186 } 4187 4188 /** 4189 * igb_check_lvmmc - check for malformed packets received 4190 * and indicated in LVMMC register 4191 * @adapter: pointer to adapter 4192 **/ 4193 static void igb_check_lvmmc(struct igb_adapter *adapter) 4194 { 4195 struct e1000_hw *hw = &adapter->hw; 4196 u32 lvmmc; 4197 4198 lvmmc = rd32(E1000_LVMMC); 4199 if (lvmmc) { 4200 if (unlikely(net_ratelimit())) { 4201 netdev_warn(adapter->netdev, 4202 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4203 lvmmc); 4204 } 4205 } 4206 } 4207 4208 /** 4209 * igb_watchdog - Timer Call-back 4210 * @data: pointer to adapter cast into an unsigned long 4211 **/ 4212 static void igb_watchdog(unsigned long data) 4213 { 4214 struct igb_adapter *adapter = (struct igb_adapter *)data; 4215 /* Do the rest outside of interrupt context */ 4216 schedule_work(&adapter->watchdog_task); 4217 } 4218 4219 static void igb_watchdog_task(struct work_struct *work) 4220 { 4221 struct igb_adapter *adapter = container_of(work, 4222 struct igb_adapter, 4223 watchdog_task); 4224 struct e1000_hw *hw = &adapter->hw; 4225 struct e1000_phy_info *phy = &hw->phy; 4226 struct net_device *netdev = adapter->netdev; 4227 u32 link; 4228 int i; 4229 u32 connsw; 4230 4231 link = igb_has_link(adapter); 4232 4233 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4234 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4235 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4236 else 4237 link = false; 4238 } 4239 4240 /* Force link down if we have fiber to swap to */ 4241 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4242 if (hw->phy.media_type == e1000_media_type_copper) { 4243 connsw = rd32(E1000_CONNSW); 4244 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4245 link = 0; 4246 } 4247 } 4248 if (link) { 4249 /* Perform a reset if the media type changed. */ 4250 if (hw->dev_spec._82575.media_changed) { 4251 hw->dev_spec._82575.media_changed = false; 4252 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4253 igb_reset(adapter); 4254 } 4255 /* Cancel scheduled suspend requests. */ 4256 pm_runtime_resume(netdev->dev.parent); 4257 4258 if (!netif_carrier_ok(netdev)) { 4259 u32 ctrl; 4260 4261 hw->mac.ops.get_speed_and_duplex(hw, 4262 &adapter->link_speed, 4263 &adapter->link_duplex); 4264 4265 ctrl = rd32(E1000_CTRL); 4266 /* Links status message must follow this format */ 4267 netdev_info(netdev, 4268 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4269 netdev->name, 4270 adapter->link_speed, 4271 adapter->link_duplex == FULL_DUPLEX ? 4272 "Full" : "Half", 4273 (ctrl & E1000_CTRL_TFCE) && 4274 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4275 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4276 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4277 4278 /* disable EEE if enabled */ 4279 if ((adapter->flags & IGB_FLAG_EEE) && 4280 (adapter->link_duplex == HALF_DUPLEX)) { 4281 dev_info(&adapter->pdev->dev, 4282 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4283 adapter->hw.dev_spec._82575.eee_disable = true; 4284 adapter->flags &= ~IGB_FLAG_EEE; 4285 } 4286 4287 /* check if SmartSpeed worked */ 4288 igb_check_downshift(hw); 4289 if (phy->speed_downgraded) 4290 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4291 4292 /* check for thermal sensor event */ 4293 if (igb_thermal_sensor_event(hw, 4294 E1000_THSTAT_LINK_THROTTLE)) 4295 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4296 4297 /* adjust timeout factor according to speed/duplex */ 4298 adapter->tx_timeout_factor = 1; 4299 switch (adapter->link_speed) { 4300 case SPEED_10: 4301 adapter->tx_timeout_factor = 14; 4302 break; 4303 case SPEED_100: 4304 /* maybe add some timeout factor ? */ 4305 break; 4306 } 4307 4308 netif_carrier_on(netdev); 4309 4310 igb_ping_all_vfs(adapter); 4311 igb_check_vf_rate_limit(adapter); 4312 4313 /* link state has changed, schedule phy info update */ 4314 if (!test_bit(__IGB_DOWN, &adapter->state)) 4315 mod_timer(&adapter->phy_info_timer, 4316 round_jiffies(jiffies + 2 * HZ)); 4317 } 4318 } else { 4319 if (netif_carrier_ok(netdev)) { 4320 adapter->link_speed = 0; 4321 adapter->link_duplex = 0; 4322 4323 /* check for thermal sensor event */ 4324 if (igb_thermal_sensor_event(hw, 4325 E1000_THSTAT_PWR_DOWN)) { 4326 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4327 } 4328 4329 /* Links status message must follow this format */ 4330 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4331 netdev->name); 4332 netif_carrier_off(netdev); 4333 4334 igb_ping_all_vfs(adapter); 4335 4336 /* link state has changed, schedule phy info update */ 4337 if (!test_bit(__IGB_DOWN, &adapter->state)) 4338 mod_timer(&adapter->phy_info_timer, 4339 round_jiffies(jiffies + 2 * HZ)); 4340 4341 /* link is down, time to check for alternate media */ 4342 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4343 igb_check_swap_media(adapter); 4344 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4345 schedule_work(&adapter->reset_task); 4346 /* return immediately */ 4347 return; 4348 } 4349 } 4350 pm_schedule_suspend(netdev->dev.parent, 4351 MSEC_PER_SEC * 5); 4352 4353 /* also check for alternate media here */ 4354 } else if (!netif_carrier_ok(netdev) && 4355 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4356 igb_check_swap_media(adapter); 4357 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4358 schedule_work(&adapter->reset_task); 4359 /* return immediately */ 4360 return; 4361 } 4362 } 4363 } 4364 4365 spin_lock(&adapter->stats64_lock); 4366 igb_update_stats(adapter, &adapter->stats64); 4367 spin_unlock(&adapter->stats64_lock); 4368 4369 for (i = 0; i < adapter->num_tx_queues; i++) { 4370 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4371 if (!netif_carrier_ok(netdev)) { 4372 /* We've lost link, so the controller stops DMA, 4373 * but we've got queued Tx work that's never going 4374 * to get done, so reset controller to flush Tx. 4375 * (Do the reset outside of interrupt context). 4376 */ 4377 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4378 adapter->tx_timeout_count++; 4379 schedule_work(&adapter->reset_task); 4380 /* return immediately since reset is imminent */ 4381 return; 4382 } 4383 } 4384 4385 /* Force detection of hung controller every watchdog period */ 4386 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4387 } 4388 4389 /* Cause software interrupt to ensure Rx ring is cleaned */ 4390 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4391 u32 eics = 0; 4392 4393 for (i = 0; i < adapter->num_q_vectors; i++) 4394 eics |= adapter->q_vector[i]->eims_value; 4395 wr32(E1000_EICS, eics); 4396 } else { 4397 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4398 } 4399 4400 igb_spoof_check(adapter); 4401 igb_ptp_rx_hang(adapter); 4402 4403 /* Check LVMMC register on i350/i354 only */ 4404 if ((adapter->hw.mac.type == e1000_i350) || 4405 (adapter->hw.mac.type == e1000_i354)) 4406 igb_check_lvmmc(adapter); 4407 4408 /* Reset the timer */ 4409 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4410 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4411 mod_timer(&adapter->watchdog_timer, 4412 round_jiffies(jiffies + HZ)); 4413 else 4414 mod_timer(&adapter->watchdog_timer, 4415 round_jiffies(jiffies + 2 * HZ)); 4416 } 4417 } 4418 4419 enum latency_range { 4420 lowest_latency = 0, 4421 low_latency = 1, 4422 bulk_latency = 2, 4423 latency_invalid = 255 4424 }; 4425 4426 /** 4427 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4428 * @q_vector: pointer to q_vector 4429 * 4430 * Stores a new ITR value based on strictly on packet size. This 4431 * algorithm is less sophisticated than that used in igb_update_itr, 4432 * due to the difficulty of synchronizing statistics across multiple 4433 * receive rings. The divisors and thresholds used by this function 4434 * were determined based on theoretical maximum wire speed and testing 4435 * data, in order to minimize response time while increasing bulk 4436 * throughput. 4437 * This functionality is controlled by ethtool's coalescing settings. 4438 * NOTE: This function is called only when operating in a multiqueue 4439 * receive environment. 4440 **/ 4441 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4442 { 4443 int new_val = q_vector->itr_val; 4444 int avg_wire_size = 0; 4445 struct igb_adapter *adapter = q_vector->adapter; 4446 unsigned int packets; 4447 4448 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4449 * ints/sec - ITR timer value of 120 ticks. 4450 */ 4451 if (adapter->link_speed != SPEED_1000) { 4452 new_val = IGB_4K_ITR; 4453 goto set_itr_val; 4454 } 4455 4456 packets = q_vector->rx.total_packets; 4457 if (packets) 4458 avg_wire_size = q_vector->rx.total_bytes / packets; 4459 4460 packets = q_vector->tx.total_packets; 4461 if (packets) 4462 avg_wire_size = max_t(u32, avg_wire_size, 4463 q_vector->tx.total_bytes / packets); 4464 4465 /* if avg_wire_size isn't set no work was done */ 4466 if (!avg_wire_size) 4467 goto clear_counts; 4468 4469 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4470 avg_wire_size += 24; 4471 4472 /* Don't starve jumbo frames */ 4473 avg_wire_size = min(avg_wire_size, 3000); 4474 4475 /* Give a little boost to mid-size frames */ 4476 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4477 new_val = avg_wire_size / 3; 4478 else 4479 new_val = avg_wire_size / 2; 4480 4481 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4482 if (new_val < IGB_20K_ITR && 4483 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4484 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4485 new_val = IGB_20K_ITR; 4486 4487 set_itr_val: 4488 if (new_val != q_vector->itr_val) { 4489 q_vector->itr_val = new_val; 4490 q_vector->set_itr = 1; 4491 } 4492 clear_counts: 4493 q_vector->rx.total_bytes = 0; 4494 q_vector->rx.total_packets = 0; 4495 q_vector->tx.total_bytes = 0; 4496 q_vector->tx.total_packets = 0; 4497 } 4498 4499 /** 4500 * igb_update_itr - update the dynamic ITR value based on statistics 4501 * @q_vector: pointer to q_vector 4502 * @ring_container: ring info to update the itr for 4503 * 4504 * Stores a new ITR value based on packets and byte 4505 * counts during the last interrupt. The advantage of per interrupt 4506 * computation is faster updates and more accurate ITR for the current 4507 * traffic pattern. Constants in this function were computed 4508 * based on theoretical maximum wire speed and thresholds were set based 4509 * on testing data as well as attempting to minimize response time 4510 * while increasing bulk throughput. 4511 * This functionality is controlled by ethtool's coalescing settings. 4512 * NOTE: These calculations are only valid when operating in a single- 4513 * queue environment. 4514 **/ 4515 static void igb_update_itr(struct igb_q_vector *q_vector, 4516 struct igb_ring_container *ring_container) 4517 { 4518 unsigned int packets = ring_container->total_packets; 4519 unsigned int bytes = ring_container->total_bytes; 4520 u8 itrval = ring_container->itr; 4521 4522 /* no packets, exit with status unchanged */ 4523 if (packets == 0) 4524 return; 4525 4526 switch (itrval) { 4527 case lowest_latency: 4528 /* handle TSO and jumbo frames */ 4529 if (bytes/packets > 8000) 4530 itrval = bulk_latency; 4531 else if ((packets < 5) && (bytes > 512)) 4532 itrval = low_latency; 4533 break; 4534 case low_latency: /* 50 usec aka 20000 ints/s */ 4535 if (bytes > 10000) { 4536 /* this if handles the TSO accounting */ 4537 if (bytes/packets > 8000) 4538 itrval = bulk_latency; 4539 else if ((packets < 10) || ((bytes/packets) > 1200)) 4540 itrval = bulk_latency; 4541 else if ((packets > 35)) 4542 itrval = lowest_latency; 4543 } else if (bytes/packets > 2000) { 4544 itrval = bulk_latency; 4545 } else if (packets <= 2 && bytes < 512) { 4546 itrval = lowest_latency; 4547 } 4548 break; 4549 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4550 if (bytes > 25000) { 4551 if (packets > 35) 4552 itrval = low_latency; 4553 } else if (bytes < 1500) { 4554 itrval = low_latency; 4555 } 4556 break; 4557 } 4558 4559 /* clear work counters since we have the values we need */ 4560 ring_container->total_bytes = 0; 4561 ring_container->total_packets = 0; 4562 4563 /* write updated itr to ring container */ 4564 ring_container->itr = itrval; 4565 } 4566 4567 static void igb_set_itr(struct igb_q_vector *q_vector) 4568 { 4569 struct igb_adapter *adapter = q_vector->adapter; 4570 u32 new_itr = q_vector->itr_val; 4571 u8 current_itr = 0; 4572 4573 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4574 if (adapter->link_speed != SPEED_1000) { 4575 current_itr = 0; 4576 new_itr = IGB_4K_ITR; 4577 goto set_itr_now; 4578 } 4579 4580 igb_update_itr(q_vector, &q_vector->tx); 4581 igb_update_itr(q_vector, &q_vector->rx); 4582 4583 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4584 4585 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4586 if (current_itr == lowest_latency && 4587 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4588 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4589 current_itr = low_latency; 4590 4591 switch (current_itr) { 4592 /* counts and packets in update_itr are dependent on these numbers */ 4593 case lowest_latency: 4594 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4595 break; 4596 case low_latency: 4597 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4598 break; 4599 case bulk_latency: 4600 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4601 break; 4602 default: 4603 break; 4604 } 4605 4606 set_itr_now: 4607 if (new_itr != q_vector->itr_val) { 4608 /* this attempts to bias the interrupt rate towards Bulk 4609 * by adding intermediate steps when interrupt rate is 4610 * increasing 4611 */ 4612 new_itr = new_itr > q_vector->itr_val ? 4613 max((new_itr * q_vector->itr_val) / 4614 (new_itr + (q_vector->itr_val >> 2)), 4615 new_itr) : new_itr; 4616 /* Don't write the value here; it resets the adapter's 4617 * internal timer, and causes us to delay far longer than 4618 * we should between interrupts. Instead, we write the ITR 4619 * value at the beginning of the next interrupt so the timing 4620 * ends up being correct. 4621 */ 4622 q_vector->itr_val = new_itr; 4623 q_vector->set_itr = 1; 4624 } 4625 } 4626 4627 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4628 u32 type_tucmd, u32 mss_l4len_idx) 4629 { 4630 struct e1000_adv_tx_context_desc *context_desc; 4631 u16 i = tx_ring->next_to_use; 4632 4633 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4634 4635 i++; 4636 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4637 4638 /* set bits to identify this as an advanced context descriptor */ 4639 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4640 4641 /* For 82575, context index must be unique per ring. */ 4642 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4643 mss_l4len_idx |= tx_ring->reg_idx << 4; 4644 4645 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4646 context_desc->seqnum_seed = 0; 4647 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4648 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4649 } 4650 4651 static int igb_tso(struct igb_ring *tx_ring, 4652 struct igb_tx_buffer *first, 4653 u8 *hdr_len) 4654 { 4655 struct sk_buff *skb = first->skb; 4656 u32 vlan_macip_lens, type_tucmd; 4657 u32 mss_l4len_idx, l4len; 4658 int err; 4659 4660 if (skb->ip_summed != CHECKSUM_PARTIAL) 4661 return 0; 4662 4663 if (!skb_is_gso(skb)) 4664 return 0; 4665 4666 err = skb_cow_head(skb, 0); 4667 if (err < 0) 4668 return err; 4669 4670 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4671 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4672 4673 if (first->protocol == htons(ETH_P_IP)) { 4674 struct iphdr *iph = ip_hdr(skb); 4675 iph->tot_len = 0; 4676 iph->check = 0; 4677 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4678 iph->daddr, 0, 4679 IPPROTO_TCP, 4680 0); 4681 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4682 first->tx_flags |= IGB_TX_FLAGS_TSO | 4683 IGB_TX_FLAGS_CSUM | 4684 IGB_TX_FLAGS_IPV4; 4685 } else if (skb_is_gso_v6(skb)) { 4686 ipv6_hdr(skb)->payload_len = 0; 4687 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4688 &ipv6_hdr(skb)->daddr, 4689 0, IPPROTO_TCP, 0); 4690 first->tx_flags |= IGB_TX_FLAGS_TSO | 4691 IGB_TX_FLAGS_CSUM; 4692 } 4693 4694 /* compute header lengths */ 4695 l4len = tcp_hdrlen(skb); 4696 *hdr_len = skb_transport_offset(skb) + l4len; 4697 4698 /* update gso size and bytecount with header size */ 4699 first->gso_segs = skb_shinfo(skb)->gso_segs; 4700 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4701 4702 /* MSS L4LEN IDX */ 4703 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4704 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4705 4706 /* VLAN MACLEN IPLEN */ 4707 vlan_macip_lens = skb_network_header_len(skb); 4708 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4709 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4710 4711 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4712 4713 return 1; 4714 } 4715 4716 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4717 { 4718 struct sk_buff *skb = first->skb; 4719 u32 vlan_macip_lens = 0; 4720 u32 mss_l4len_idx = 0; 4721 u32 type_tucmd = 0; 4722 4723 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4724 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4725 return; 4726 } else { 4727 u8 l4_hdr = 0; 4728 4729 switch (first->protocol) { 4730 case htons(ETH_P_IP): 4731 vlan_macip_lens |= skb_network_header_len(skb); 4732 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4733 l4_hdr = ip_hdr(skb)->protocol; 4734 break; 4735 case htons(ETH_P_IPV6): 4736 vlan_macip_lens |= skb_network_header_len(skb); 4737 l4_hdr = ipv6_hdr(skb)->nexthdr; 4738 break; 4739 default: 4740 if (unlikely(net_ratelimit())) { 4741 dev_warn(tx_ring->dev, 4742 "partial checksum but proto=%x!\n", 4743 first->protocol); 4744 } 4745 break; 4746 } 4747 4748 switch (l4_hdr) { 4749 case IPPROTO_TCP: 4750 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4751 mss_l4len_idx = tcp_hdrlen(skb) << 4752 E1000_ADVTXD_L4LEN_SHIFT; 4753 break; 4754 case IPPROTO_SCTP: 4755 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4756 mss_l4len_idx = sizeof(struct sctphdr) << 4757 E1000_ADVTXD_L4LEN_SHIFT; 4758 break; 4759 case IPPROTO_UDP: 4760 mss_l4len_idx = sizeof(struct udphdr) << 4761 E1000_ADVTXD_L4LEN_SHIFT; 4762 break; 4763 default: 4764 if (unlikely(net_ratelimit())) { 4765 dev_warn(tx_ring->dev, 4766 "partial checksum but l4 proto=%x!\n", 4767 l4_hdr); 4768 } 4769 break; 4770 } 4771 4772 /* update TX checksum flag */ 4773 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4774 } 4775 4776 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4777 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4778 4779 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4780 } 4781 4782 #define IGB_SET_FLAG(_input, _flag, _result) \ 4783 ((_flag <= _result) ? \ 4784 ((u32)(_input & _flag) * (_result / _flag)) : \ 4785 ((u32)(_input & _flag) / (_flag / _result))) 4786 4787 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4788 { 4789 /* set type for advanced descriptor with frame checksum insertion */ 4790 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4791 E1000_ADVTXD_DCMD_DEXT | 4792 E1000_ADVTXD_DCMD_IFCS; 4793 4794 /* set HW vlan bit if vlan is present */ 4795 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4796 (E1000_ADVTXD_DCMD_VLE)); 4797 4798 /* set segmentation bits for TSO */ 4799 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4800 (E1000_ADVTXD_DCMD_TSE)); 4801 4802 /* set timestamp bit if present */ 4803 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4804 (E1000_ADVTXD_MAC_TSTAMP)); 4805 4806 /* insert frame checksum */ 4807 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4808 4809 return cmd_type; 4810 } 4811 4812 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4813 union e1000_adv_tx_desc *tx_desc, 4814 u32 tx_flags, unsigned int paylen) 4815 { 4816 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4817 4818 /* 82575 requires a unique index per ring */ 4819 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4820 olinfo_status |= tx_ring->reg_idx << 4; 4821 4822 /* insert L4 checksum */ 4823 olinfo_status |= IGB_SET_FLAG(tx_flags, 4824 IGB_TX_FLAGS_CSUM, 4825 (E1000_TXD_POPTS_TXSM << 8)); 4826 4827 /* insert IPv4 checksum */ 4828 olinfo_status |= IGB_SET_FLAG(tx_flags, 4829 IGB_TX_FLAGS_IPV4, 4830 (E1000_TXD_POPTS_IXSM << 8)); 4831 4832 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4833 } 4834 4835 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4836 { 4837 struct net_device *netdev = tx_ring->netdev; 4838 4839 netif_stop_subqueue(netdev, tx_ring->queue_index); 4840 4841 /* Herbert's original patch had: 4842 * smp_mb__after_netif_stop_queue(); 4843 * but since that doesn't exist yet, just open code it. 4844 */ 4845 smp_mb(); 4846 4847 /* We need to check again in a case another CPU has just 4848 * made room available. 4849 */ 4850 if (igb_desc_unused(tx_ring) < size) 4851 return -EBUSY; 4852 4853 /* A reprieve! */ 4854 netif_wake_subqueue(netdev, tx_ring->queue_index); 4855 4856 u64_stats_update_begin(&tx_ring->tx_syncp2); 4857 tx_ring->tx_stats.restart_queue2++; 4858 u64_stats_update_end(&tx_ring->tx_syncp2); 4859 4860 return 0; 4861 } 4862 4863 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4864 { 4865 if (igb_desc_unused(tx_ring) >= size) 4866 return 0; 4867 return __igb_maybe_stop_tx(tx_ring, size); 4868 } 4869 4870 static void igb_tx_map(struct igb_ring *tx_ring, 4871 struct igb_tx_buffer *first, 4872 const u8 hdr_len) 4873 { 4874 struct sk_buff *skb = first->skb; 4875 struct igb_tx_buffer *tx_buffer; 4876 union e1000_adv_tx_desc *tx_desc; 4877 struct skb_frag_struct *frag; 4878 dma_addr_t dma; 4879 unsigned int data_len, size; 4880 u32 tx_flags = first->tx_flags; 4881 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4882 u16 i = tx_ring->next_to_use; 4883 4884 tx_desc = IGB_TX_DESC(tx_ring, i); 4885 4886 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4887 4888 size = skb_headlen(skb); 4889 data_len = skb->data_len; 4890 4891 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4892 4893 tx_buffer = first; 4894 4895 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4896 if (dma_mapping_error(tx_ring->dev, dma)) 4897 goto dma_error; 4898 4899 /* record length, and DMA address */ 4900 dma_unmap_len_set(tx_buffer, len, size); 4901 dma_unmap_addr_set(tx_buffer, dma, dma); 4902 4903 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4904 4905 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4906 tx_desc->read.cmd_type_len = 4907 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4908 4909 i++; 4910 tx_desc++; 4911 if (i == tx_ring->count) { 4912 tx_desc = IGB_TX_DESC(tx_ring, 0); 4913 i = 0; 4914 } 4915 tx_desc->read.olinfo_status = 0; 4916 4917 dma += IGB_MAX_DATA_PER_TXD; 4918 size -= IGB_MAX_DATA_PER_TXD; 4919 4920 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4921 } 4922 4923 if (likely(!data_len)) 4924 break; 4925 4926 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4927 4928 i++; 4929 tx_desc++; 4930 if (i == tx_ring->count) { 4931 tx_desc = IGB_TX_DESC(tx_ring, 0); 4932 i = 0; 4933 } 4934 tx_desc->read.olinfo_status = 0; 4935 4936 size = skb_frag_size(frag); 4937 data_len -= size; 4938 4939 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4940 size, DMA_TO_DEVICE); 4941 4942 tx_buffer = &tx_ring->tx_buffer_info[i]; 4943 } 4944 4945 /* write last descriptor with RS and EOP bits */ 4946 cmd_type |= size | IGB_TXD_DCMD; 4947 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4948 4949 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4950 4951 /* set the timestamp */ 4952 first->time_stamp = jiffies; 4953 4954 /* Force memory writes to complete before letting h/w know there 4955 * are new descriptors to fetch. (Only applicable for weak-ordered 4956 * memory model archs, such as IA-64). 4957 * 4958 * We also need this memory barrier to make certain all of the 4959 * status bits have been updated before next_to_watch is written. 4960 */ 4961 wmb(); 4962 4963 /* set next_to_watch value indicating a packet is present */ 4964 first->next_to_watch = tx_desc; 4965 4966 i++; 4967 if (i == tx_ring->count) 4968 i = 0; 4969 4970 tx_ring->next_to_use = i; 4971 4972 /* Make sure there is space in the ring for the next send. */ 4973 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4974 4975 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 4976 writel(i, tx_ring->tail); 4977 4978 /* we need this if more than one processor can write to our tail 4979 * at a time, it synchronizes IO on IA64/Altix systems 4980 */ 4981 mmiowb(); 4982 } 4983 return; 4984 4985 dma_error: 4986 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4987 4988 /* clear dma mappings for failed tx_buffer_info map */ 4989 for (;;) { 4990 tx_buffer = &tx_ring->tx_buffer_info[i]; 4991 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4992 if (tx_buffer == first) 4993 break; 4994 if (i == 0) 4995 i = tx_ring->count; 4996 i--; 4997 } 4998 4999 tx_ring->next_to_use = i; 5000 } 5001 5002 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5003 struct igb_ring *tx_ring) 5004 { 5005 struct igb_tx_buffer *first; 5006 int tso; 5007 u32 tx_flags = 0; 5008 unsigned short f; 5009 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5010 __be16 protocol = vlan_get_protocol(skb); 5011 u8 hdr_len = 0; 5012 5013 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5014 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5015 * + 2 desc gap to keep tail from touching head, 5016 * + 1 desc for context descriptor, 5017 * otherwise try next time 5018 */ 5019 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5020 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5021 5022 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5023 /* this is a hard error */ 5024 return NETDEV_TX_BUSY; 5025 } 5026 5027 /* record the location of the first descriptor for this packet */ 5028 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5029 first->skb = skb; 5030 first->bytecount = skb->len; 5031 first->gso_segs = 1; 5032 5033 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5034 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5035 5036 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5037 &adapter->state)) { 5038 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5039 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5040 5041 adapter->ptp_tx_skb = skb_get(skb); 5042 adapter->ptp_tx_start = jiffies; 5043 if (adapter->hw.mac.type == e1000_82576) 5044 schedule_work(&adapter->ptp_tx_work); 5045 } 5046 } 5047 5048 skb_tx_timestamp(skb); 5049 5050 if (skb_vlan_tag_present(skb)) { 5051 tx_flags |= IGB_TX_FLAGS_VLAN; 5052 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5053 } 5054 5055 /* record initial flags and protocol */ 5056 first->tx_flags = tx_flags; 5057 first->protocol = protocol; 5058 5059 tso = igb_tso(tx_ring, first, &hdr_len); 5060 if (tso < 0) 5061 goto out_drop; 5062 else if (!tso) 5063 igb_tx_csum(tx_ring, first); 5064 5065 igb_tx_map(tx_ring, first, hdr_len); 5066 5067 return NETDEV_TX_OK; 5068 5069 out_drop: 5070 igb_unmap_and_free_tx_resource(tx_ring, first); 5071 5072 return NETDEV_TX_OK; 5073 } 5074 5075 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5076 struct sk_buff *skb) 5077 { 5078 unsigned int r_idx = skb->queue_mapping; 5079 5080 if (r_idx >= adapter->num_tx_queues) 5081 r_idx = r_idx % adapter->num_tx_queues; 5082 5083 return adapter->tx_ring[r_idx]; 5084 } 5085 5086 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5087 struct net_device *netdev) 5088 { 5089 struct igb_adapter *adapter = netdev_priv(netdev); 5090 5091 if (test_bit(__IGB_DOWN, &adapter->state)) { 5092 dev_kfree_skb_any(skb); 5093 return NETDEV_TX_OK; 5094 } 5095 5096 if (skb->len <= 0) { 5097 dev_kfree_skb_any(skb); 5098 return NETDEV_TX_OK; 5099 } 5100 5101 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5102 * in order to meet this minimum size requirement. 5103 */ 5104 if (skb_put_padto(skb, 17)) 5105 return NETDEV_TX_OK; 5106 5107 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5108 } 5109 5110 /** 5111 * igb_tx_timeout - Respond to a Tx Hang 5112 * @netdev: network interface device structure 5113 **/ 5114 static void igb_tx_timeout(struct net_device *netdev) 5115 { 5116 struct igb_adapter *adapter = netdev_priv(netdev); 5117 struct e1000_hw *hw = &adapter->hw; 5118 5119 /* Do the reset outside of interrupt context */ 5120 adapter->tx_timeout_count++; 5121 5122 if (hw->mac.type >= e1000_82580) 5123 hw->dev_spec._82575.global_device_reset = true; 5124 5125 schedule_work(&adapter->reset_task); 5126 wr32(E1000_EICS, 5127 (adapter->eims_enable_mask & ~adapter->eims_other)); 5128 } 5129 5130 static void igb_reset_task(struct work_struct *work) 5131 { 5132 struct igb_adapter *adapter; 5133 adapter = container_of(work, struct igb_adapter, reset_task); 5134 5135 igb_dump(adapter); 5136 netdev_err(adapter->netdev, "Reset adapter\n"); 5137 igb_reinit_locked(adapter); 5138 } 5139 5140 /** 5141 * igb_get_stats64 - Get System Network Statistics 5142 * @netdev: network interface device structure 5143 * @stats: rtnl_link_stats64 pointer 5144 **/ 5145 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5146 struct rtnl_link_stats64 *stats) 5147 { 5148 struct igb_adapter *adapter = netdev_priv(netdev); 5149 5150 spin_lock(&adapter->stats64_lock); 5151 igb_update_stats(adapter, &adapter->stats64); 5152 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5153 spin_unlock(&adapter->stats64_lock); 5154 5155 return stats; 5156 } 5157 5158 /** 5159 * igb_change_mtu - Change the Maximum Transfer Unit 5160 * @netdev: network interface device structure 5161 * @new_mtu: new value for maximum frame size 5162 * 5163 * Returns 0 on success, negative on failure 5164 **/ 5165 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5166 { 5167 struct igb_adapter *adapter = netdev_priv(netdev); 5168 struct pci_dev *pdev = adapter->pdev; 5169 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5170 5171 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5172 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5173 return -EINVAL; 5174 } 5175 5176 #define MAX_STD_JUMBO_FRAME_SIZE 9238 5177 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5178 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5179 return -EINVAL; 5180 } 5181 5182 /* adjust max frame to be at least the size of a standard frame */ 5183 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5184 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5185 5186 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5187 usleep_range(1000, 2000); 5188 5189 /* igb_down has a dependency on max_frame_size */ 5190 adapter->max_frame_size = max_frame; 5191 5192 if (netif_running(netdev)) 5193 igb_down(adapter); 5194 5195 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5196 netdev->mtu, new_mtu); 5197 netdev->mtu = new_mtu; 5198 5199 if (netif_running(netdev)) 5200 igb_up(adapter); 5201 else 5202 igb_reset(adapter); 5203 5204 clear_bit(__IGB_RESETTING, &adapter->state); 5205 5206 return 0; 5207 } 5208 5209 /** 5210 * igb_update_stats - Update the board statistics counters 5211 * @adapter: board private structure 5212 **/ 5213 void igb_update_stats(struct igb_adapter *adapter, 5214 struct rtnl_link_stats64 *net_stats) 5215 { 5216 struct e1000_hw *hw = &adapter->hw; 5217 struct pci_dev *pdev = adapter->pdev; 5218 u32 reg, mpc; 5219 int i; 5220 u64 bytes, packets; 5221 unsigned int start; 5222 u64 _bytes, _packets; 5223 5224 /* Prevent stats update while adapter is being reset, or if the pci 5225 * connection is down. 5226 */ 5227 if (adapter->link_speed == 0) 5228 return; 5229 if (pci_channel_offline(pdev)) 5230 return; 5231 5232 bytes = 0; 5233 packets = 0; 5234 5235 rcu_read_lock(); 5236 for (i = 0; i < adapter->num_rx_queues; i++) { 5237 struct igb_ring *ring = adapter->rx_ring[i]; 5238 u32 rqdpc = rd32(E1000_RQDPC(i)); 5239 if (hw->mac.type >= e1000_i210) 5240 wr32(E1000_RQDPC(i), 0); 5241 5242 if (rqdpc) { 5243 ring->rx_stats.drops += rqdpc; 5244 net_stats->rx_fifo_errors += rqdpc; 5245 } 5246 5247 do { 5248 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5249 _bytes = ring->rx_stats.bytes; 5250 _packets = ring->rx_stats.packets; 5251 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5252 bytes += _bytes; 5253 packets += _packets; 5254 } 5255 5256 net_stats->rx_bytes = bytes; 5257 net_stats->rx_packets = packets; 5258 5259 bytes = 0; 5260 packets = 0; 5261 for (i = 0; i < adapter->num_tx_queues; i++) { 5262 struct igb_ring *ring = adapter->tx_ring[i]; 5263 do { 5264 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5265 _bytes = ring->tx_stats.bytes; 5266 _packets = ring->tx_stats.packets; 5267 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5268 bytes += _bytes; 5269 packets += _packets; 5270 } 5271 net_stats->tx_bytes = bytes; 5272 net_stats->tx_packets = packets; 5273 rcu_read_unlock(); 5274 5275 /* read stats registers */ 5276 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5277 adapter->stats.gprc += rd32(E1000_GPRC); 5278 adapter->stats.gorc += rd32(E1000_GORCL); 5279 rd32(E1000_GORCH); /* clear GORCL */ 5280 adapter->stats.bprc += rd32(E1000_BPRC); 5281 adapter->stats.mprc += rd32(E1000_MPRC); 5282 adapter->stats.roc += rd32(E1000_ROC); 5283 5284 adapter->stats.prc64 += rd32(E1000_PRC64); 5285 adapter->stats.prc127 += rd32(E1000_PRC127); 5286 adapter->stats.prc255 += rd32(E1000_PRC255); 5287 adapter->stats.prc511 += rd32(E1000_PRC511); 5288 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5289 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5290 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5291 adapter->stats.sec += rd32(E1000_SEC); 5292 5293 mpc = rd32(E1000_MPC); 5294 adapter->stats.mpc += mpc; 5295 net_stats->rx_fifo_errors += mpc; 5296 adapter->stats.scc += rd32(E1000_SCC); 5297 adapter->stats.ecol += rd32(E1000_ECOL); 5298 adapter->stats.mcc += rd32(E1000_MCC); 5299 adapter->stats.latecol += rd32(E1000_LATECOL); 5300 adapter->stats.dc += rd32(E1000_DC); 5301 adapter->stats.rlec += rd32(E1000_RLEC); 5302 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5303 adapter->stats.xontxc += rd32(E1000_XONTXC); 5304 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5305 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5306 adapter->stats.fcruc += rd32(E1000_FCRUC); 5307 adapter->stats.gptc += rd32(E1000_GPTC); 5308 adapter->stats.gotc += rd32(E1000_GOTCL); 5309 rd32(E1000_GOTCH); /* clear GOTCL */ 5310 adapter->stats.rnbc += rd32(E1000_RNBC); 5311 adapter->stats.ruc += rd32(E1000_RUC); 5312 adapter->stats.rfc += rd32(E1000_RFC); 5313 adapter->stats.rjc += rd32(E1000_RJC); 5314 adapter->stats.tor += rd32(E1000_TORH); 5315 adapter->stats.tot += rd32(E1000_TOTH); 5316 adapter->stats.tpr += rd32(E1000_TPR); 5317 5318 adapter->stats.ptc64 += rd32(E1000_PTC64); 5319 adapter->stats.ptc127 += rd32(E1000_PTC127); 5320 adapter->stats.ptc255 += rd32(E1000_PTC255); 5321 adapter->stats.ptc511 += rd32(E1000_PTC511); 5322 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5323 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5324 5325 adapter->stats.mptc += rd32(E1000_MPTC); 5326 adapter->stats.bptc += rd32(E1000_BPTC); 5327 5328 adapter->stats.tpt += rd32(E1000_TPT); 5329 adapter->stats.colc += rd32(E1000_COLC); 5330 5331 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5332 /* read internal phy specific stats */ 5333 reg = rd32(E1000_CTRL_EXT); 5334 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5335 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5336 5337 /* this stat has invalid values on i210/i211 */ 5338 if ((hw->mac.type != e1000_i210) && 5339 (hw->mac.type != e1000_i211)) 5340 adapter->stats.tncrs += rd32(E1000_TNCRS); 5341 } 5342 5343 adapter->stats.tsctc += rd32(E1000_TSCTC); 5344 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5345 5346 adapter->stats.iac += rd32(E1000_IAC); 5347 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5348 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5349 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5350 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5351 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5352 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5353 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5354 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5355 5356 /* Fill out the OS statistics structure */ 5357 net_stats->multicast = adapter->stats.mprc; 5358 net_stats->collisions = adapter->stats.colc; 5359 5360 /* Rx Errors */ 5361 5362 /* RLEC on some newer hardware can be incorrect so build 5363 * our own version based on RUC and ROC 5364 */ 5365 net_stats->rx_errors = adapter->stats.rxerrc + 5366 adapter->stats.crcerrs + adapter->stats.algnerrc + 5367 adapter->stats.ruc + adapter->stats.roc + 5368 adapter->stats.cexterr; 5369 net_stats->rx_length_errors = adapter->stats.ruc + 5370 adapter->stats.roc; 5371 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5372 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5373 net_stats->rx_missed_errors = adapter->stats.mpc; 5374 5375 /* Tx Errors */ 5376 net_stats->tx_errors = adapter->stats.ecol + 5377 adapter->stats.latecol; 5378 net_stats->tx_aborted_errors = adapter->stats.ecol; 5379 net_stats->tx_window_errors = adapter->stats.latecol; 5380 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5381 5382 /* Tx Dropped needs to be maintained elsewhere */ 5383 5384 /* Management Stats */ 5385 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5386 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5387 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5388 5389 /* OS2BMC Stats */ 5390 reg = rd32(E1000_MANC); 5391 if (reg & E1000_MANC_EN_BMC2OS) { 5392 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5393 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5394 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5395 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5396 } 5397 } 5398 5399 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5400 { 5401 struct e1000_hw *hw = &adapter->hw; 5402 struct ptp_clock_event event; 5403 struct timespec64 ts; 5404 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5405 5406 if (tsicr & TSINTR_SYS_WRAP) { 5407 event.type = PTP_CLOCK_PPS; 5408 if (adapter->ptp_caps.pps) 5409 ptp_clock_event(adapter->ptp_clock, &event); 5410 else 5411 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5412 ack |= TSINTR_SYS_WRAP; 5413 } 5414 5415 if (tsicr & E1000_TSICR_TXTS) { 5416 /* retrieve hardware timestamp */ 5417 schedule_work(&adapter->ptp_tx_work); 5418 ack |= E1000_TSICR_TXTS; 5419 } 5420 5421 if (tsicr & TSINTR_TT0) { 5422 spin_lock(&adapter->tmreg_lock); 5423 ts = timespec64_add(adapter->perout[0].start, 5424 adapter->perout[0].period); 5425 /* u32 conversion of tv_sec is safe until y2106 */ 5426 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5427 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5428 tsauxc = rd32(E1000_TSAUXC); 5429 tsauxc |= TSAUXC_EN_TT0; 5430 wr32(E1000_TSAUXC, tsauxc); 5431 adapter->perout[0].start = ts; 5432 spin_unlock(&adapter->tmreg_lock); 5433 ack |= TSINTR_TT0; 5434 } 5435 5436 if (tsicr & TSINTR_TT1) { 5437 spin_lock(&adapter->tmreg_lock); 5438 ts = timespec64_add(adapter->perout[1].start, 5439 adapter->perout[1].period); 5440 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5441 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5442 tsauxc = rd32(E1000_TSAUXC); 5443 tsauxc |= TSAUXC_EN_TT1; 5444 wr32(E1000_TSAUXC, tsauxc); 5445 adapter->perout[1].start = ts; 5446 spin_unlock(&adapter->tmreg_lock); 5447 ack |= TSINTR_TT1; 5448 } 5449 5450 if (tsicr & TSINTR_AUTT0) { 5451 nsec = rd32(E1000_AUXSTMPL0); 5452 sec = rd32(E1000_AUXSTMPH0); 5453 event.type = PTP_CLOCK_EXTTS; 5454 event.index = 0; 5455 event.timestamp = sec * 1000000000ULL + nsec; 5456 ptp_clock_event(adapter->ptp_clock, &event); 5457 ack |= TSINTR_AUTT0; 5458 } 5459 5460 if (tsicr & TSINTR_AUTT1) { 5461 nsec = rd32(E1000_AUXSTMPL1); 5462 sec = rd32(E1000_AUXSTMPH1); 5463 event.type = PTP_CLOCK_EXTTS; 5464 event.index = 1; 5465 event.timestamp = sec * 1000000000ULL + nsec; 5466 ptp_clock_event(adapter->ptp_clock, &event); 5467 ack |= TSINTR_AUTT1; 5468 } 5469 5470 /* acknowledge the interrupts */ 5471 wr32(E1000_TSICR, ack); 5472 } 5473 5474 static irqreturn_t igb_msix_other(int irq, void *data) 5475 { 5476 struct igb_adapter *adapter = data; 5477 struct e1000_hw *hw = &adapter->hw; 5478 u32 icr = rd32(E1000_ICR); 5479 /* reading ICR causes bit 31 of EICR to be cleared */ 5480 5481 if (icr & E1000_ICR_DRSTA) 5482 schedule_work(&adapter->reset_task); 5483 5484 if (icr & E1000_ICR_DOUTSYNC) { 5485 /* HW is reporting DMA is out of sync */ 5486 adapter->stats.doosync++; 5487 /* The DMA Out of Sync is also indication of a spoof event 5488 * in IOV mode. Check the Wrong VM Behavior register to 5489 * see if it is really a spoof event. 5490 */ 5491 igb_check_wvbr(adapter); 5492 } 5493 5494 /* Check for a mailbox event */ 5495 if (icr & E1000_ICR_VMMB) 5496 igb_msg_task(adapter); 5497 5498 if (icr & E1000_ICR_LSC) { 5499 hw->mac.get_link_status = 1; 5500 /* guard against interrupt when we're going down */ 5501 if (!test_bit(__IGB_DOWN, &adapter->state)) 5502 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5503 } 5504 5505 if (icr & E1000_ICR_TS) 5506 igb_tsync_interrupt(adapter); 5507 5508 wr32(E1000_EIMS, adapter->eims_other); 5509 5510 return IRQ_HANDLED; 5511 } 5512 5513 static void igb_write_itr(struct igb_q_vector *q_vector) 5514 { 5515 struct igb_adapter *adapter = q_vector->adapter; 5516 u32 itr_val = q_vector->itr_val & 0x7FFC; 5517 5518 if (!q_vector->set_itr) 5519 return; 5520 5521 if (!itr_val) 5522 itr_val = 0x4; 5523 5524 if (adapter->hw.mac.type == e1000_82575) 5525 itr_val |= itr_val << 16; 5526 else 5527 itr_val |= E1000_EITR_CNT_IGNR; 5528 5529 writel(itr_val, q_vector->itr_register); 5530 q_vector->set_itr = 0; 5531 } 5532 5533 static irqreturn_t igb_msix_ring(int irq, void *data) 5534 { 5535 struct igb_q_vector *q_vector = data; 5536 5537 /* Write the ITR value calculated from the previous interrupt. */ 5538 igb_write_itr(q_vector); 5539 5540 napi_schedule(&q_vector->napi); 5541 5542 return IRQ_HANDLED; 5543 } 5544 5545 #ifdef CONFIG_IGB_DCA 5546 static void igb_update_tx_dca(struct igb_adapter *adapter, 5547 struct igb_ring *tx_ring, 5548 int cpu) 5549 { 5550 struct e1000_hw *hw = &adapter->hw; 5551 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5552 5553 if (hw->mac.type != e1000_82575) 5554 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5555 5556 /* We can enable relaxed ordering for reads, but not writes when 5557 * DCA is enabled. This is due to a known issue in some chipsets 5558 * which will cause the DCA tag to be cleared. 5559 */ 5560 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5561 E1000_DCA_TXCTRL_DATA_RRO_EN | 5562 E1000_DCA_TXCTRL_DESC_DCA_EN; 5563 5564 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5565 } 5566 5567 static void igb_update_rx_dca(struct igb_adapter *adapter, 5568 struct igb_ring *rx_ring, 5569 int cpu) 5570 { 5571 struct e1000_hw *hw = &adapter->hw; 5572 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5573 5574 if (hw->mac.type != e1000_82575) 5575 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5576 5577 /* We can enable relaxed ordering for reads, but not writes when 5578 * DCA is enabled. This is due to a known issue in some chipsets 5579 * which will cause the DCA tag to be cleared. 5580 */ 5581 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5582 E1000_DCA_RXCTRL_DESC_DCA_EN; 5583 5584 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5585 } 5586 5587 static void igb_update_dca(struct igb_q_vector *q_vector) 5588 { 5589 struct igb_adapter *adapter = q_vector->adapter; 5590 int cpu = get_cpu(); 5591 5592 if (q_vector->cpu == cpu) 5593 goto out_no_update; 5594 5595 if (q_vector->tx.ring) 5596 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5597 5598 if (q_vector->rx.ring) 5599 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5600 5601 q_vector->cpu = cpu; 5602 out_no_update: 5603 put_cpu(); 5604 } 5605 5606 static void igb_setup_dca(struct igb_adapter *adapter) 5607 { 5608 struct e1000_hw *hw = &adapter->hw; 5609 int i; 5610 5611 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5612 return; 5613 5614 /* Always use CB2 mode, difference is masked in the CB driver. */ 5615 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5616 5617 for (i = 0; i < adapter->num_q_vectors; i++) { 5618 adapter->q_vector[i]->cpu = -1; 5619 igb_update_dca(adapter->q_vector[i]); 5620 } 5621 } 5622 5623 static int __igb_notify_dca(struct device *dev, void *data) 5624 { 5625 struct net_device *netdev = dev_get_drvdata(dev); 5626 struct igb_adapter *adapter = netdev_priv(netdev); 5627 struct pci_dev *pdev = adapter->pdev; 5628 struct e1000_hw *hw = &adapter->hw; 5629 unsigned long event = *(unsigned long *)data; 5630 5631 switch (event) { 5632 case DCA_PROVIDER_ADD: 5633 /* if already enabled, don't do it again */ 5634 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5635 break; 5636 if (dca_add_requester(dev) == 0) { 5637 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5638 dev_info(&pdev->dev, "DCA enabled\n"); 5639 igb_setup_dca(adapter); 5640 break; 5641 } 5642 /* Fall Through since DCA is disabled. */ 5643 case DCA_PROVIDER_REMOVE: 5644 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5645 /* without this a class_device is left 5646 * hanging around in the sysfs model 5647 */ 5648 dca_remove_requester(dev); 5649 dev_info(&pdev->dev, "DCA disabled\n"); 5650 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5651 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5652 } 5653 break; 5654 } 5655 5656 return 0; 5657 } 5658 5659 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5660 void *p) 5661 { 5662 int ret_val; 5663 5664 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5665 __igb_notify_dca); 5666 5667 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5668 } 5669 #endif /* CONFIG_IGB_DCA */ 5670 5671 #ifdef CONFIG_PCI_IOV 5672 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5673 { 5674 unsigned char mac_addr[ETH_ALEN]; 5675 5676 eth_zero_addr(mac_addr); 5677 igb_set_vf_mac(adapter, vf, mac_addr); 5678 5679 /* By default spoof check is enabled for all VFs */ 5680 adapter->vf_data[vf].spoofchk_enabled = true; 5681 5682 return 0; 5683 } 5684 5685 #endif 5686 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5687 { 5688 struct e1000_hw *hw = &adapter->hw; 5689 u32 ping; 5690 int i; 5691 5692 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5693 ping = E1000_PF_CONTROL_MSG; 5694 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5695 ping |= E1000_VT_MSGTYPE_CTS; 5696 igb_write_mbx(hw, &ping, 1, i); 5697 } 5698 } 5699 5700 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5701 { 5702 struct e1000_hw *hw = &adapter->hw; 5703 u32 vmolr = rd32(E1000_VMOLR(vf)); 5704 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5705 5706 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5707 IGB_VF_FLAG_MULTI_PROMISC); 5708 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5709 5710 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5711 vmolr |= E1000_VMOLR_MPME; 5712 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5713 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5714 } else { 5715 /* if we have hashes and we are clearing a multicast promisc 5716 * flag we need to write the hashes to the MTA as this step 5717 * was previously skipped 5718 */ 5719 if (vf_data->num_vf_mc_hashes > 30) { 5720 vmolr |= E1000_VMOLR_MPME; 5721 } else if (vf_data->num_vf_mc_hashes) { 5722 int j; 5723 5724 vmolr |= E1000_VMOLR_ROMPE; 5725 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5726 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5727 } 5728 } 5729 5730 wr32(E1000_VMOLR(vf), vmolr); 5731 5732 /* there are flags left unprocessed, likely not supported */ 5733 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5734 return -EINVAL; 5735 5736 return 0; 5737 } 5738 5739 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5740 u32 *msgbuf, u32 vf) 5741 { 5742 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5743 u16 *hash_list = (u16 *)&msgbuf[1]; 5744 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5745 int i; 5746 5747 /* salt away the number of multicast addresses assigned 5748 * to this VF for later use to restore when the PF multi cast 5749 * list changes 5750 */ 5751 vf_data->num_vf_mc_hashes = n; 5752 5753 /* only up to 30 hash values supported */ 5754 if (n > 30) 5755 n = 30; 5756 5757 /* store the hashes for later use */ 5758 for (i = 0; i < n; i++) 5759 vf_data->vf_mc_hashes[i] = hash_list[i]; 5760 5761 /* Flush and reset the mta with the new values */ 5762 igb_set_rx_mode(adapter->netdev); 5763 5764 return 0; 5765 } 5766 5767 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5768 { 5769 struct e1000_hw *hw = &adapter->hw; 5770 struct vf_data_storage *vf_data; 5771 int i, j; 5772 5773 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5774 u32 vmolr = rd32(E1000_VMOLR(i)); 5775 5776 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5777 5778 vf_data = &adapter->vf_data[i]; 5779 5780 if ((vf_data->num_vf_mc_hashes > 30) || 5781 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5782 vmolr |= E1000_VMOLR_MPME; 5783 } else if (vf_data->num_vf_mc_hashes) { 5784 vmolr |= E1000_VMOLR_ROMPE; 5785 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5786 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5787 } 5788 wr32(E1000_VMOLR(i), vmolr); 5789 } 5790 } 5791 5792 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5793 { 5794 struct e1000_hw *hw = &adapter->hw; 5795 u32 pool_mask, reg, vid; 5796 int i; 5797 5798 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5799 5800 /* Find the vlan filter for this id */ 5801 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5802 reg = rd32(E1000_VLVF(i)); 5803 5804 /* remove the vf from the pool */ 5805 reg &= ~pool_mask; 5806 5807 /* if pool is empty then remove entry from vfta */ 5808 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5809 (reg & E1000_VLVF_VLANID_ENABLE)) { 5810 reg = 0; 5811 vid = reg & E1000_VLVF_VLANID_MASK; 5812 igb_vfta_set(hw, vid, false); 5813 } 5814 5815 wr32(E1000_VLVF(i), reg); 5816 } 5817 5818 adapter->vf_data[vf].vlans_enabled = 0; 5819 } 5820 5821 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5822 { 5823 struct e1000_hw *hw = &adapter->hw; 5824 u32 reg, i; 5825 5826 /* The vlvf table only exists on 82576 hardware and newer */ 5827 if (hw->mac.type < e1000_82576) 5828 return -1; 5829 5830 /* we only need to do this if VMDq is enabled */ 5831 if (!adapter->vfs_allocated_count) 5832 return -1; 5833 5834 /* Find the vlan filter for this id */ 5835 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5836 reg = rd32(E1000_VLVF(i)); 5837 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5838 vid == (reg & E1000_VLVF_VLANID_MASK)) 5839 break; 5840 } 5841 5842 if (add) { 5843 if (i == E1000_VLVF_ARRAY_SIZE) { 5844 /* Did not find a matching VLAN ID entry that was 5845 * enabled. Search for a free filter entry, i.e. 5846 * one without the enable bit set 5847 */ 5848 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5849 reg = rd32(E1000_VLVF(i)); 5850 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5851 break; 5852 } 5853 } 5854 if (i < E1000_VLVF_ARRAY_SIZE) { 5855 /* Found an enabled/available entry */ 5856 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5857 5858 /* if !enabled we need to set this up in vfta */ 5859 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5860 /* add VID to filter table */ 5861 igb_vfta_set(hw, vid, true); 5862 reg |= E1000_VLVF_VLANID_ENABLE; 5863 } 5864 reg &= ~E1000_VLVF_VLANID_MASK; 5865 reg |= vid; 5866 wr32(E1000_VLVF(i), reg); 5867 5868 /* do not modify RLPML for PF devices */ 5869 if (vf >= adapter->vfs_allocated_count) 5870 return 0; 5871 5872 if (!adapter->vf_data[vf].vlans_enabled) { 5873 u32 size; 5874 5875 reg = rd32(E1000_VMOLR(vf)); 5876 size = reg & E1000_VMOLR_RLPML_MASK; 5877 size += 4; 5878 reg &= ~E1000_VMOLR_RLPML_MASK; 5879 reg |= size; 5880 wr32(E1000_VMOLR(vf), reg); 5881 } 5882 5883 adapter->vf_data[vf].vlans_enabled++; 5884 } 5885 } else { 5886 if (i < E1000_VLVF_ARRAY_SIZE) { 5887 /* remove vf from the pool */ 5888 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5889 /* if pool is empty then remove entry from vfta */ 5890 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5891 reg = 0; 5892 igb_vfta_set(hw, vid, false); 5893 } 5894 wr32(E1000_VLVF(i), reg); 5895 5896 /* do not modify RLPML for PF devices */ 5897 if (vf >= adapter->vfs_allocated_count) 5898 return 0; 5899 5900 adapter->vf_data[vf].vlans_enabled--; 5901 if (!adapter->vf_data[vf].vlans_enabled) { 5902 u32 size; 5903 5904 reg = rd32(E1000_VMOLR(vf)); 5905 size = reg & E1000_VMOLR_RLPML_MASK; 5906 size -= 4; 5907 reg &= ~E1000_VMOLR_RLPML_MASK; 5908 reg |= size; 5909 wr32(E1000_VMOLR(vf), reg); 5910 } 5911 } 5912 } 5913 return 0; 5914 } 5915 5916 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5917 { 5918 struct e1000_hw *hw = &adapter->hw; 5919 5920 if (vid) 5921 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5922 else 5923 wr32(E1000_VMVIR(vf), 0); 5924 } 5925 5926 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5927 int vf, u16 vlan, u8 qos) 5928 { 5929 int err = 0; 5930 struct igb_adapter *adapter = netdev_priv(netdev); 5931 5932 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5933 return -EINVAL; 5934 if (vlan || qos) { 5935 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5936 if (err) 5937 goto out; 5938 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5939 igb_set_vmolr(adapter, vf, !vlan); 5940 adapter->vf_data[vf].pf_vlan = vlan; 5941 adapter->vf_data[vf].pf_qos = qos; 5942 dev_info(&adapter->pdev->dev, 5943 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5944 if (test_bit(__IGB_DOWN, &adapter->state)) { 5945 dev_warn(&adapter->pdev->dev, 5946 "The VF VLAN has been set, but the PF device is not up.\n"); 5947 dev_warn(&adapter->pdev->dev, 5948 "Bring the PF device up before attempting to use the VF device.\n"); 5949 } 5950 } else { 5951 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5952 false, vf); 5953 igb_set_vmvir(adapter, vlan, vf); 5954 igb_set_vmolr(adapter, vf, true); 5955 adapter->vf_data[vf].pf_vlan = 0; 5956 adapter->vf_data[vf].pf_qos = 0; 5957 } 5958 out: 5959 return err; 5960 } 5961 5962 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5963 { 5964 struct e1000_hw *hw = &adapter->hw; 5965 int i; 5966 u32 reg; 5967 5968 /* Find the vlan filter for this id */ 5969 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5970 reg = rd32(E1000_VLVF(i)); 5971 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5972 vid == (reg & E1000_VLVF_VLANID_MASK)) 5973 break; 5974 } 5975 5976 if (i >= E1000_VLVF_ARRAY_SIZE) 5977 i = -1; 5978 5979 return i; 5980 } 5981 5982 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5983 { 5984 struct e1000_hw *hw = &adapter->hw; 5985 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5986 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5987 int err = 0; 5988 5989 /* If in promiscuous mode we need to make sure the PF also has 5990 * the VLAN filter set. 5991 */ 5992 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5993 err = igb_vlvf_set(adapter, vid, add, 5994 adapter->vfs_allocated_count); 5995 if (err) 5996 goto out; 5997 5998 err = igb_vlvf_set(adapter, vid, add, vf); 5999 6000 if (err) 6001 goto out; 6002 6003 /* Go through all the checks to see if the VLAN filter should 6004 * be wiped completely. 6005 */ 6006 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 6007 u32 vlvf, bits; 6008 int regndx = igb_find_vlvf_entry(adapter, vid); 6009 6010 if (regndx < 0) 6011 goto out; 6012 /* See if any other pools are set for this VLAN filter 6013 * entry other than the PF. 6014 */ 6015 vlvf = bits = rd32(E1000_VLVF(regndx)); 6016 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 6017 adapter->vfs_allocated_count); 6018 /* If the filter was removed then ensure PF pool bit 6019 * is cleared if the PF only added itself to the pool 6020 * because the PF is in promiscuous mode. 6021 */ 6022 if ((vlvf & VLAN_VID_MASK) == vid && 6023 !test_bit(vid, adapter->active_vlans) && 6024 !bits) 6025 igb_vlvf_set(adapter, vid, add, 6026 adapter->vfs_allocated_count); 6027 } 6028 6029 out: 6030 return err; 6031 } 6032 6033 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6034 { 6035 /* clear flags - except flag that indicates PF has set the MAC */ 6036 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 6037 adapter->vf_data[vf].last_nack = jiffies; 6038 6039 /* reset offloads to defaults */ 6040 igb_set_vmolr(adapter, vf, true); 6041 6042 /* reset vlans for device */ 6043 igb_clear_vf_vfta(adapter, vf); 6044 if (adapter->vf_data[vf].pf_vlan) 6045 igb_ndo_set_vf_vlan(adapter->netdev, vf, 6046 adapter->vf_data[vf].pf_vlan, 6047 adapter->vf_data[vf].pf_qos); 6048 else 6049 igb_clear_vf_vfta(adapter, vf); 6050 6051 /* reset multicast table array for vf */ 6052 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6053 6054 /* Flush and reset the mta with the new values */ 6055 igb_set_rx_mode(adapter->netdev); 6056 } 6057 6058 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6059 { 6060 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6061 6062 /* clear mac address as we were hotplug removed/added */ 6063 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6064 eth_zero_addr(vf_mac); 6065 6066 /* process remaining reset events */ 6067 igb_vf_reset(adapter, vf); 6068 } 6069 6070 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6071 { 6072 struct e1000_hw *hw = &adapter->hw; 6073 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6074 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6075 u32 reg, msgbuf[3]; 6076 u8 *addr = (u8 *)(&msgbuf[1]); 6077 6078 /* process all the same items cleared in a function level reset */ 6079 igb_vf_reset(adapter, vf); 6080 6081 /* set vf mac address */ 6082 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6083 6084 /* enable transmit and receive for vf */ 6085 reg = rd32(E1000_VFTE); 6086 wr32(E1000_VFTE, reg | (1 << vf)); 6087 reg = rd32(E1000_VFRE); 6088 wr32(E1000_VFRE, reg | (1 << vf)); 6089 6090 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6091 6092 /* reply to reset with ack and vf mac address */ 6093 if (!is_zero_ether_addr(vf_mac)) { 6094 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6095 memcpy(addr, vf_mac, ETH_ALEN); 6096 } else { 6097 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6098 } 6099 igb_write_mbx(hw, msgbuf, 3, vf); 6100 } 6101 6102 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6103 { 6104 /* The VF MAC Address is stored in a packed array of bytes 6105 * starting at the second 32 bit word of the msg array 6106 */ 6107 unsigned char *addr = (char *)&msg[1]; 6108 int err = -1; 6109 6110 if (is_valid_ether_addr(addr)) 6111 err = igb_set_vf_mac(adapter, vf, addr); 6112 6113 return err; 6114 } 6115 6116 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6117 { 6118 struct e1000_hw *hw = &adapter->hw; 6119 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6120 u32 msg = E1000_VT_MSGTYPE_NACK; 6121 6122 /* if device isn't clear to send it shouldn't be reading either */ 6123 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6124 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6125 igb_write_mbx(hw, &msg, 1, vf); 6126 vf_data->last_nack = jiffies; 6127 } 6128 } 6129 6130 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6131 { 6132 struct pci_dev *pdev = adapter->pdev; 6133 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6134 struct e1000_hw *hw = &adapter->hw; 6135 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6136 s32 retval; 6137 6138 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6139 6140 if (retval) { 6141 /* if receive failed revoke VF CTS stats and restart init */ 6142 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6143 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6144 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6145 return; 6146 goto out; 6147 } 6148 6149 /* this is a message we already processed, do nothing */ 6150 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6151 return; 6152 6153 /* until the vf completes a reset it should not be 6154 * allowed to start any configuration. 6155 */ 6156 if (msgbuf[0] == E1000_VF_RESET) { 6157 igb_vf_reset_msg(adapter, vf); 6158 return; 6159 } 6160 6161 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6162 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6163 return; 6164 retval = -1; 6165 goto out; 6166 } 6167 6168 switch ((msgbuf[0] & 0xFFFF)) { 6169 case E1000_VF_SET_MAC_ADDR: 6170 retval = -EINVAL; 6171 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6172 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6173 else 6174 dev_warn(&pdev->dev, 6175 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6176 vf); 6177 break; 6178 case E1000_VF_SET_PROMISC: 6179 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6180 break; 6181 case E1000_VF_SET_MULTICAST: 6182 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6183 break; 6184 case E1000_VF_SET_LPE: 6185 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6186 break; 6187 case E1000_VF_SET_VLAN: 6188 retval = -1; 6189 if (vf_data->pf_vlan) 6190 dev_warn(&pdev->dev, 6191 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6192 vf); 6193 else 6194 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6195 break; 6196 default: 6197 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6198 retval = -1; 6199 break; 6200 } 6201 6202 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6203 out: 6204 /* notify the VF of the results of what it sent us */ 6205 if (retval) 6206 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6207 else 6208 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6209 6210 igb_write_mbx(hw, msgbuf, 1, vf); 6211 } 6212 6213 static void igb_msg_task(struct igb_adapter *adapter) 6214 { 6215 struct e1000_hw *hw = &adapter->hw; 6216 u32 vf; 6217 6218 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6219 /* process any reset requests */ 6220 if (!igb_check_for_rst(hw, vf)) 6221 igb_vf_reset_event(adapter, vf); 6222 6223 /* process any messages pending */ 6224 if (!igb_check_for_msg(hw, vf)) 6225 igb_rcv_msg_from_vf(adapter, vf); 6226 6227 /* process any acks */ 6228 if (!igb_check_for_ack(hw, vf)) 6229 igb_rcv_ack_from_vf(adapter, vf); 6230 } 6231 } 6232 6233 /** 6234 * igb_set_uta - Set unicast filter table address 6235 * @adapter: board private structure 6236 * 6237 * The unicast table address is a register array of 32-bit registers. 6238 * The table is meant to be used in a way similar to how the MTA is used 6239 * however due to certain limitations in the hardware it is necessary to 6240 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6241 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6242 **/ 6243 static void igb_set_uta(struct igb_adapter *adapter) 6244 { 6245 struct e1000_hw *hw = &adapter->hw; 6246 int i; 6247 6248 /* The UTA table only exists on 82576 hardware and newer */ 6249 if (hw->mac.type < e1000_82576) 6250 return; 6251 6252 /* we only need to do this if VMDq is enabled */ 6253 if (!adapter->vfs_allocated_count) 6254 return; 6255 6256 for (i = 0; i < hw->mac.uta_reg_count; i++) 6257 array_wr32(E1000_UTA, i, ~0); 6258 } 6259 6260 /** 6261 * igb_intr_msi - Interrupt Handler 6262 * @irq: interrupt number 6263 * @data: pointer to a network interface device structure 6264 **/ 6265 static irqreturn_t igb_intr_msi(int irq, void *data) 6266 { 6267 struct igb_adapter *adapter = data; 6268 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6269 struct e1000_hw *hw = &adapter->hw; 6270 /* read ICR disables interrupts using IAM */ 6271 u32 icr = rd32(E1000_ICR); 6272 6273 igb_write_itr(q_vector); 6274 6275 if (icr & E1000_ICR_DRSTA) 6276 schedule_work(&adapter->reset_task); 6277 6278 if (icr & E1000_ICR_DOUTSYNC) { 6279 /* HW is reporting DMA is out of sync */ 6280 adapter->stats.doosync++; 6281 } 6282 6283 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6284 hw->mac.get_link_status = 1; 6285 if (!test_bit(__IGB_DOWN, &adapter->state)) 6286 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6287 } 6288 6289 if (icr & E1000_ICR_TS) 6290 igb_tsync_interrupt(adapter); 6291 6292 napi_schedule(&q_vector->napi); 6293 6294 return IRQ_HANDLED; 6295 } 6296 6297 /** 6298 * igb_intr - Legacy Interrupt Handler 6299 * @irq: interrupt number 6300 * @data: pointer to a network interface device structure 6301 **/ 6302 static irqreturn_t igb_intr(int irq, void *data) 6303 { 6304 struct igb_adapter *adapter = data; 6305 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6306 struct e1000_hw *hw = &adapter->hw; 6307 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6308 * need for the IMC write 6309 */ 6310 u32 icr = rd32(E1000_ICR); 6311 6312 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6313 * not set, then the adapter didn't send an interrupt 6314 */ 6315 if (!(icr & E1000_ICR_INT_ASSERTED)) 6316 return IRQ_NONE; 6317 6318 igb_write_itr(q_vector); 6319 6320 if (icr & E1000_ICR_DRSTA) 6321 schedule_work(&adapter->reset_task); 6322 6323 if (icr & E1000_ICR_DOUTSYNC) { 6324 /* HW is reporting DMA is out of sync */ 6325 adapter->stats.doosync++; 6326 } 6327 6328 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6329 hw->mac.get_link_status = 1; 6330 /* guard against interrupt when we're going down */ 6331 if (!test_bit(__IGB_DOWN, &adapter->state)) 6332 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6333 } 6334 6335 if (icr & E1000_ICR_TS) 6336 igb_tsync_interrupt(adapter); 6337 6338 napi_schedule(&q_vector->napi); 6339 6340 return IRQ_HANDLED; 6341 } 6342 6343 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6344 { 6345 struct igb_adapter *adapter = q_vector->adapter; 6346 struct e1000_hw *hw = &adapter->hw; 6347 6348 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6349 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6350 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6351 igb_set_itr(q_vector); 6352 else 6353 igb_update_ring_itr(q_vector); 6354 } 6355 6356 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6357 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6358 wr32(E1000_EIMS, q_vector->eims_value); 6359 else 6360 igb_irq_enable(adapter); 6361 } 6362 } 6363 6364 /** 6365 * igb_poll - NAPI Rx polling callback 6366 * @napi: napi polling structure 6367 * @budget: count of how many packets we should handle 6368 **/ 6369 static int igb_poll(struct napi_struct *napi, int budget) 6370 { 6371 struct igb_q_vector *q_vector = container_of(napi, 6372 struct igb_q_vector, 6373 napi); 6374 bool clean_complete = true; 6375 int work_done = 0; 6376 6377 #ifdef CONFIG_IGB_DCA 6378 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6379 igb_update_dca(q_vector); 6380 #endif 6381 if (q_vector->tx.ring) 6382 clean_complete = igb_clean_tx_irq(q_vector); 6383 6384 if (q_vector->rx.ring) { 6385 int cleaned = igb_clean_rx_irq(q_vector, budget); 6386 6387 work_done += cleaned; 6388 clean_complete &= (cleaned < budget); 6389 } 6390 6391 /* If all work not completed, return budget and keep polling */ 6392 if (!clean_complete) 6393 return budget; 6394 6395 /* If not enough Rx work done, exit the polling mode */ 6396 napi_complete_done(napi, work_done); 6397 igb_ring_irq_enable(q_vector); 6398 6399 return 0; 6400 } 6401 6402 /** 6403 * igb_clean_tx_irq - Reclaim resources after transmit completes 6404 * @q_vector: pointer to q_vector containing needed info 6405 * 6406 * returns true if ring is completely cleaned 6407 **/ 6408 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6409 { 6410 struct igb_adapter *adapter = q_vector->adapter; 6411 struct igb_ring *tx_ring = q_vector->tx.ring; 6412 struct igb_tx_buffer *tx_buffer; 6413 union e1000_adv_tx_desc *tx_desc; 6414 unsigned int total_bytes = 0, total_packets = 0; 6415 unsigned int budget = q_vector->tx.work_limit; 6416 unsigned int i = tx_ring->next_to_clean; 6417 6418 if (test_bit(__IGB_DOWN, &adapter->state)) 6419 return true; 6420 6421 tx_buffer = &tx_ring->tx_buffer_info[i]; 6422 tx_desc = IGB_TX_DESC(tx_ring, i); 6423 i -= tx_ring->count; 6424 6425 do { 6426 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6427 6428 /* if next_to_watch is not set then there is no work pending */ 6429 if (!eop_desc) 6430 break; 6431 6432 /* prevent any other reads prior to eop_desc */ 6433 read_barrier_depends(); 6434 6435 /* if DD is not set pending work has not been completed */ 6436 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6437 break; 6438 6439 /* clear next_to_watch to prevent false hangs */ 6440 tx_buffer->next_to_watch = NULL; 6441 6442 /* update the statistics for this packet */ 6443 total_bytes += tx_buffer->bytecount; 6444 total_packets += tx_buffer->gso_segs; 6445 6446 /* free the skb */ 6447 dev_consume_skb_any(tx_buffer->skb); 6448 6449 /* unmap skb header data */ 6450 dma_unmap_single(tx_ring->dev, 6451 dma_unmap_addr(tx_buffer, dma), 6452 dma_unmap_len(tx_buffer, len), 6453 DMA_TO_DEVICE); 6454 6455 /* clear tx_buffer data */ 6456 tx_buffer->skb = NULL; 6457 dma_unmap_len_set(tx_buffer, len, 0); 6458 6459 /* clear last DMA location and unmap remaining buffers */ 6460 while (tx_desc != eop_desc) { 6461 tx_buffer++; 6462 tx_desc++; 6463 i++; 6464 if (unlikely(!i)) { 6465 i -= tx_ring->count; 6466 tx_buffer = tx_ring->tx_buffer_info; 6467 tx_desc = IGB_TX_DESC(tx_ring, 0); 6468 } 6469 6470 /* unmap any remaining paged data */ 6471 if (dma_unmap_len(tx_buffer, len)) { 6472 dma_unmap_page(tx_ring->dev, 6473 dma_unmap_addr(tx_buffer, dma), 6474 dma_unmap_len(tx_buffer, len), 6475 DMA_TO_DEVICE); 6476 dma_unmap_len_set(tx_buffer, len, 0); 6477 } 6478 } 6479 6480 /* move us one more past the eop_desc for start of next pkt */ 6481 tx_buffer++; 6482 tx_desc++; 6483 i++; 6484 if (unlikely(!i)) { 6485 i -= tx_ring->count; 6486 tx_buffer = tx_ring->tx_buffer_info; 6487 tx_desc = IGB_TX_DESC(tx_ring, 0); 6488 } 6489 6490 /* issue prefetch for next Tx descriptor */ 6491 prefetch(tx_desc); 6492 6493 /* update budget accounting */ 6494 budget--; 6495 } while (likely(budget)); 6496 6497 netdev_tx_completed_queue(txring_txq(tx_ring), 6498 total_packets, total_bytes); 6499 i += tx_ring->count; 6500 tx_ring->next_to_clean = i; 6501 u64_stats_update_begin(&tx_ring->tx_syncp); 6502 tx_ring->tx_stats.bytes += total_bytes; 6503 tx_ring->tx_stats.packets += total_packets; 6504 u64_stats_update_end(&tx_ring->tx_syncp); 6505 q_vector->tx.total_bytes += total_bytes; 6506 q_vector->tx.total_packets += total_packets; 6507 6508 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6509 struct e1000_hw *hw = &adapter->hw; 6510 6511 /* Detect a transmit hang in hardware, this serializes the 6512 * check with the clearing of time_stamp and movement of i 6513 */ 6514 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6515 if (tx_buffer->next_to_watch && 6516 time_after(jiffies, tx_buffer->time_stamp + 6517 (adapter->tx_timeout_factor * HZ)) && 6518 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6519 6520 /* detected Tx unit hang */ 6521 dev_err(tx_ring->dev, 6522 "Detected Tx Unit Hang\n" 6523 " Tx Queue <%d>\n" 6524 " TDH <%x>\n" 6525 " TDT <%x>\n" 6526 " next_to_use <%x>\n" 6527 " next_to_clean <%x>\n" 6528 "buffer_info[next_to_clean]\n" 6529 " time_stamp <%lx>\n" 6530 " next_to_watch <%p>\n" 6531 " jiffies <%lx>\n" 6532 " desc.status <%x>\n", 6533 tx_ring->queue_index, 6534 rd32(E1000_TDH(tx_ring->reg_idx)), 6535 readl(tx_ring->tail), 6536 tx_ring->next_to_use, 6537 tx_ring->next_to_clean, 6538 tx_buffer->time_stamp, 6539 tx_buffer->next_to_watch, 6540 jiffies, 6541 tx_buffer->next_to_watch->wb.status); 6542 netif_stop_subqueue(tx_ring->netdev, 6543 tx_ring->queue_index); 6544 6545 /* we are about to reset, no point in enabling stuff */ 6546 return true; 6547 } 6548 } 6549 6550 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6551 if (unlikely(total_packets && 6552 netif_carrier_ok(tx_ring->netdev) && 6553 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6554 /* Make sure that anybody stopping the queue after this 6555 * sees the new next_to_clean. 6556 */ 6557 smp_mb(); 6558 if (__netif_subqueue_stopped(tx_ring->netdev, 6559 tx_ring->queue_index) && 6560 !(test_bit(__IGB_DOWN, &adapter->state))) { 6561 netif_wake_subqueue(tx_ring->netdev, 6562 tx_ring->queue_index); 6563 6564 u64_stats_update_begin(&tx_ring->tx_syncp); 6565 tx_ring->tx_stats.restart_queue++; 6566 u64_stats_update_end(&tx_ring->tx_syncp); 6567 } 6568 } 6569 6570 return !!budget; 6571 } 6572 6573 /** 6574 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6575 * @rx_ring: rx descriptor ring to store buffers on 6576 * @old_buff: donor buffer to have page reused 6577 * 6578 * Synchronizes page for reuse by the adapter 6579 **/ 6580 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6581 struct igb_rx_buffer *old_buff) 6582 { 6583 struct igb_rx_buffer *new_buff; 6584 u16 nta = rx_ring->next_to_alloc; 6585 6586 new_buff = &rx_ring->rx_buffer_info[nta]; 6587 6588 /* update, and store next to alloc */ 6589 nta++; 6590 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6591 6592 /* transfer page from old buffer to new buffer */ 6593 *new_buff = *old_buff; 6594 6595 /* sync the buffer for use by the device */ 6596 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6597 old_buff->page_offset, 6598 IGB_RX_BUFSZ, 6599 DMA_FROM_DEVICE); 6600 } 6601 6602 static inline bool igb_page_is_reserved(struct page *page) 6603 { 6604 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 6605 } 6606 6607 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6608 struct page *page, 6609 unsigned int truesize) 6610 { 6611 /* avoid re-using remote pages */ 6612 if (unlikely(igb_page_is_reserved(page))) 6613 return false; 6614 6615 #if (PAGE_SIZE < 8192) 6616 /* if we are only owner of page we can reuse it */ 6617 if (unlikely(page_count(page) != 1)) 6618 return false; 6619 6620 /* flip page offset to other buffer */ 6621 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6622 #else 6623 /* move offset up to the next cache line */ 6624 rx_buffer->page_offset += truesize; 6625 6626 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6627 return false; 6628 #endif 6629 6630 /* Even if we own the page, we are not allowed to use atomic_set() 6631 * This would break get_page_unless_zero() users. 6632 */ 6633 atomic_inc(&page->_count); 6634 6635 return true; 6636 } 6637 6638 /** 6639 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6640 * @rx_ring: rx descriptor ring to transact packets on 6641 * @rx_buffer: buffer containing page to add 6642 * @rx_desc: descriptor containing length of buffer written by hardware 6643 * @skb: sk_buff to place the data into 6644 * 6645 * This function will add the data contained in rx_buffer->page to the skb. 6646 * This is done either through a direct copy if the data in the buffer is 6647 * less than the skb header size, otherwise it will just attach the page as 6648 * a frag to the skb. 6649 * 6650 * The function will then update the page offset if necessary and return 6651 * true if the buffer can be reused by the adapter. 6652 **/ 6653 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6654 struct igb_rx_buffer *rx_buffer, 6655 union e1000_adv_rx_desc *rx_desc, 6656 struct sk_buff *skb) 6657 { 6658 struct page *page = rx_buffer->page; 6659 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6660 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6661 #if (PAGE_SIZE < 8192) 6662 unsigned int truesize = IGB_RX_BUFSZ; 6663 #else 6664 unsigned int truesize = SKB_DATA_ALIGN(size); 6665 #endif 6666 unsigned int pull_len; 6667 6668 if (unlikely(skb_is_nonlinear(skb))) 6669 goto add_tail_frag; 6670 6671 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 6672 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6673 va += IGB_TS_HDR_LEN; 6674 size -= IGB_TS_HDR_LEN; 6675 } 6676 6677 if (likely(size <= IGB_RX_HDR_LEN)) { 6678 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6679 6680 /* page is not reserved, we can reuse buffer as-is */ 6681 if (likely(!igb_page_is_reserved(page))) 6682 return true; 6683 6684 /* this page cannot be reused so discard it */ 6685 __free_page(page); 6686 return false; 6687 } 6688 6689 /* we need the header to contain the greater of either ETH_HLEN or 6690 * 60 bytes if the skb->len is less than 60 for skb_pad. 6691 */ 6692 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6693 6694 /* align pull length to size of long to optimize memcpy performance */ 6695 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 6696 6697 /* update all of the pointers */ 6698 va += pull_len; 6699 size -= pull_len; 6700 6701 add_tail_frag: 6702 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6703 (unsigned long)va & ~PAGE_MASK, size, truesize); 6704 6705 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6706 } 6707 6708 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6709 union e1000_adv_rx_desc *rx_desc, 6710 struct sk_buff *skb) 6711 { 6712 struct igb_rx_buffer *rx_buffer; 6713 struct page *page; 6714 6715 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6716 page = rx_buffer->page; 6717 prefetchw(page); 6718 6719 if (likely(!skb)) { 6720 void *page_addr = page_address(page) + 6721 rx_buffer->page_offset; 6722 6723 /* prefetch first cache line of first page */ 6724 prefetch(page_addr); 6725 #if L1_CACHE_BYTES < 128 6726 prefetch(page_addr + L1_CACHE_BYTES); 6727 #endif 6728 6729 /* allocate a skb to store the frags */ 6730 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6731 if (unlikely(!skb)) { 6732 rx_ring->rx_stats.alloc_failed++; 6733 return NULL; 6734 } 6735 6736 /* we will be copying header into skb->data in 6737 * pskb_may_pull so it is in our interest to prefetch 6738 * it now to avoid a possible cache miss 6739 */ 6740 prefetchw(skb->data); 6741 } 6742 6743 /* we are reusing so sync this buffer for CPU use */ 6744 dma_sync_single_range_for_cpu(rx_ring->dev, 6745 rx_buffer->dma, 6746 rx_buffer->page_offset, 6747 IGB_RX_BUFSZ, 6748 DMA_FROM_DEVICE); 6749 6750 /* pull page into skb */ 6751 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6752 /* hand second half of page back to the ring */ 6753 igb_reuse_rx_page(rx_ring, rx_buffer); 6754 } else { 6755 /* we are not reusing the buffer so unmap it */ 6756 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6757 PAGE_SIZE, DMA_FROM_DEVICE); 6758 } 6759 6760 /* clear contents of rx_buffer */ 6761 rx_buffer->page = NULL; 6762 6763 return skb; 6764 } 6765 6766 static inline void igb_rx_checksum(struct igb_ring *ring, 6767 union e1000_adv_rx_desc *rx_desc, 6768 struct sk_buff *skb) 6769 { 6770 skb_checksum_none_assert(skb); 6771 6772 /* Ignore Checksum bit is set */ 6773 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6774 return; 6775 6776 /* Rx checksum disabled via ethtool */ 6777 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6778 return; 6779 6780 /* TCP/UDP checksum error bit is set */ 6781 if (igb_test_staterr(rx_desc, 6782 E1000_RXDEXT_STATERR_TCPE | 6783 E1000_RXDEXT_STATERR_IPE)) { 6784 /* work around errata with sctp packets where the TCPE aka 6785 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6786 * packets, (aka let the stack check the crc32c) 6787 */ 6788 if (!((skb->len == 60) && 6789 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6790 u64_stats_update_begin(&ring->rx_syncp); 6791 ring->rx_stats.csum_err++; 6792 u64_stats_update_end(&ring->rx_syncp); 6793 } 6794 /* let the stack verify checksum errors */ 6795 return; 6796 } 6797 /* It must be a TCP or UDP packet with a valid checksum */ 6798 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6799 E1000_RXD_STAT_UDPCS)) 6800 skb->ip_summed = CHECKSUM_UNNECESSARY; 6801 6802 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6803 le32_to_cpu(rx_desc->wb.upper.status_error)); 6804 } 6805 6806 static inline void igb_rx_hash(struct igb_ring *ring, 6807 union e1000_adv_rx_desc *rx_desc, 6808 struct sk_buff *skb) 6809 { 6810 if (ring->netdev->features & NETIF_F_RXHASH) 6811 skb_set_hash(skb, 6812 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6813 PKT_HASH_TYPE_L3); 6814 } 6815 6816 /** 6817 * igb_is_non_eop - process handling of non-EOP buffers 6818 * @rx_ring: Rx ring being processed 6819 * @rx_desc: Rx descriptor for current buffer 6820 * @skb: current socket buffer containing buffer in progress 6821 * 6822 * This function updates next to clean. If the buffer is an EOP buffer 6823 * this function exits returning false, otherwise it will place the 6824 * sk_buff in the next buffer to be chained and return true indicating 6825 * that this is in fact a non-EOP buffer. 6826 **/ 6827 static bool igb_is_non_eop(struct igb_ring *rx_ring, 6828 union e1000_adv_rx_desc *rx_desc) 6829 { 6830 u32 ntc = rx_ring->next_to_clean + 1; 6831 6832 /* fetch, update, and store next to clean */ 6833 ntc = (ntc < rx_ring->count) ? ntc : 0; 6834 rx_ring->next_to_clean = ntc; 6835 6836 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6837 6838 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6839 return false; 6840 6841 return true; 6842 } 6843 6844 /** 6845 * igb_cleanup_headers - Correct corrupted or empty headers 6846 * @rx_ring: rx descriptor ring packet is being transacted on 6847 * @rx_desc: pointer to the EOP Rx descriptor 6848 * @skb: pointer to current skb being fixed 6849 * 6850 * Address the case where we are pulling data in on pages only 6851 * and as such no data is present in the skb header. 6852 * 6853 * In addition if skb is not at least 60 bytes we need to pad it so that 6854 * it is large enough to qualify as a valid Ethernet frame. 6855 * 6856 * Returns true if an error was encountered and skb was freed. 6857 **/ 6858 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6859 union e1000_adv_rx_desc *rx_desc, 6860 struct sk_buff *skb) 6861 { 6862 if (unlikely((igb_test_staterr(rx_desc, 6863 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6864 struct net_device *netdev = rx_ring->netdev; 6865 if (!(netdev->features & NETIF_F_RXALL)) { 6866 dev_kfree_skb_any(skb); 6867 return true; 6868 } 6869 } 6870 6871 /* if eth_skb_pad returns an error the skb was freed */ 6872 if (eth_skb_pad(skb)) 6873 return true; 6874 6875 return false; 6876 } 6877 6878 /** 6879 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6880 * @rx_ring: rx descriptor ring packet is being transacted on 6881 * @rx_desc: pointer to the EOP Rx descriptor 6882 * @skb: pointer to current skb being populated 6883 * 6884 * This function checks the ring, descriptor, and packet information in 6885 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6886 * other fields within the skb. 6887 **/ 6888 static void igb_process_skb_fields(struct igb_ring *rx_ring, 6889 union e1000_adv_rx_desc *rx_desc, 6890 struct sk_buff *skb) 6891 { 6892 struct net_device *dev = rx_ring->netdev; 6893 6894 igb_rx_hash(rx_ring, rx_desc, skb); 6895 6896 igb_rx_checksum(rx_ring, rx_desc, skb); 6897 6898 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6899 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6900 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6901 6902 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6903 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6904 u16 vid; 6905 6906 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6907 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6908 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6909 else 6910 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6911 6912 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6913 } 6914 6915 skb_record_rx_queue(skb, rx_ring->queue_index); 6916 6917 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6918 } 6919 6920 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6921 { 6922 struct igb_ring *rx_ring = q_vector->rx.ring; 6923 struct sk_buff *skb = rx_ring->skb; 6924 unsigned int total_bytes = 0, total_packets = 0; 6925 u16 cleaned_count = igb_desc_unused(rx_ring); 6926 6927 while (likely(total_packets < budget)) { 6928 union e1000_adv_rx_desc *rx_desc; 6929 6930 /* return some buffers to hardware, one at a time is too slow */ 6931 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6932 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6933 cleaned_count = 0; 6934 } 6935 6936 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6937 6938 if (!rx_desc->wb.upper.status_error) 6939 break; 6940 6941 /* This memory barrier is needed to keep us from reading 6942 * any other fields out of the rx_desc until we know the 6943 * descriptor has been written back 6944 */ 6945 dma_rmb(); 6946 6947 /* retrieve a buffer from the ring */ 6948 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6949 6950 /* exit if we failed to retrieve a buffer */ 6951 if (!skb) 6952 break; 6953 6954 cleaned_count++; 6955 6956 /* fetch next buffer in frame if non-eop */ 6957 if (igb_is_non_eop(rx_ring, rx_desc)) 6958 continue; 6959 6960 /* verify the packet layout is correct */ 6961 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6962 skb = NULL; 6963 continue; 6964 } 6965 6966 /* probably a little skewed due to removing CRC */ 6967 total_bytes += skb->len; 6968 6969 /* populate checksum, timestamp, VLAN, and protocol */ 6970 igb_process_skb_fields(rx_ring, rx_desc, skb); 6971 6972 napi_gro_receive(&q_vector->napi, skb); 6973 6974 /* reset skb pointer */ 6975 skb = NULL; 6976 6977 /* update budget accounting */ 6978 total_packets++; 6979 } 6980 6981 /* place incomplete frames back on ring for completion */ 6982 rx_ring->skb = skb; 6983 6984 u64_stats_update_begin(&rx_ring->rx_syncp); 6985 rx_ring->rx_stats.packets += total_packets; 6986 rx_ring->rx_stats.bytes += total_bytes; 6987 u64_stats_update_end(&rx_ring->rx_syncp); 6988 q_vector->rx.total_packets += total_packets; 6989 q_vector->rx.total_bytes += total_bytes; 6990 6991 if (cleaned_count) 6992 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6993 6994 return total_packets; 6995 } 6996 6997 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6998 struct igb_rx_buffer *bi) 6999 { 7000 struct page *page = bi->page; 7001 dma_addr_t dma; 7002 7003 /* since we are recycling buffers we should seldom need to alloc */ 7004 if (likely(page)) 7005 return true; 7006 7007 /* alloc new page for storage */ 7008 page = dev_alloc_page(); 7009 if (unlikely(!page)) { 7010 rx_ring->rx_stats.alloc_failed++; 7011 return false; 7012 } 7013 7014 /* map page for use */ 7015 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7016 7017 /* if mapping failed free memory back to system since 7018 * there isn't much point in holding memory we can't use 7019 */ 7020 if (dma_mapping_error(rx_ring->dev, dma)) { 7021 __free_page(page); 7022 7023 rx_ring->rx_stats.alloc_failed++; 7024 return false; 7025 } 7026 7027 bi->dma = dma; 7028 bi->page = page; 7029 bi->page_offset = 0; 7030 7031 return true; 7032 } 7033 7034 /** 7035 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7036 * @adapter: address of board private structure 7037 **/ 7038 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7039 { 7040 union e1000_adv_rx_desc *rx_desc; 7041 struct igb_rx_buffer *bi; 7042 u16 i = rx_ring->next_to_use; 7043 7044 /* nothing to do */ 7045 if (!cleaned_count) 7046 return; 7047 7048 rx_desc = IGB_RX_DESC(rx_ring, i); 7049 bi = &rx_ring->rx_buffer_info[i]; 7050 i -= rx_ring->count; 7051 7052 do { 7053 if (!igb_alloc_mapped_page(rx_ring, bi)) 7054 break; 7055 7056 /* Refresh the desc even if buffer_addrs didn't change 7057 * because each write-back erases this info. 7058 */ 7059 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7060 7061 rx_desc++; 7062 bi++; 7063 i++; 7064 if (unlikely(!i)) { 7065 rx_desc = IGB_RX_DESC(rx_ring, 0); 7066 bi = rx_ring->rx_buffer_info; 7067 i -= rx_ring->count; 7068 } 7069 7070 /* clear the status bits for the next_to_use descriptor */ 7071 rx_desc->wb.upper.status_error = 0; 7072 7073 cleaned_count--; 7074 } while (cleaned_count); 7075 7076 i += rx_ring->count; 7077 7078 if (rx_ring->next_to_use != i) { 7079 /* record the next descriptor to use */ 7080 rx_ring->next_to_use = i; 7081 7082 /* update next to alloc since we have filled the ring */ 7083 rx_ring->next_to_alloc = i; 7084 7085 /* Force memory writes to complete before letting h/w 7086 * know there are new descriptors to fetch. (Only 7087 * applicable for weak-ordered memory model archs, 7088 * such as IA-64). 7089 */ 7090 wmb(); 7091 writel(i, rx_ring->tail); 7092 } 7093 } 7094 7095 /** 7096 * igb_mii_ioctl - 7097 * @netdev: 7098 * @ifreq: 7099 * @cmd: 7100 **/ 7101 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7102 { 7103 struct igb_adapter *adapter = netdev_priv(netdev); 7104 struct mii_ioctl_data *data = if_mii(ifr); 7105 7106 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7107 return -EOPNOTSUPP; 7108 7109 switch (cmd) { 7110 case SIOCGMIIPHY: 7111 data->phy_id = adapter->hw.phy.addr; 7112 break; 7113 case SIOCGMIIREG: 7114 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7115 &data->val_out)) 7116 return -EIO; 7117 break; 7118 case SIOCSMIIREG: 7119 default: 7120 return -EOPNOTSUPP; 7121 } 7122 return 0; 7123 } 7124 7125 /** 7126 * igb_ioctl - 7127 * @netdev: 7128 * @ifreq: 7129 * @cmd: 7130 **/ 7131 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7132 { 7133 switch (cmd) { 7134 case SIOCGMIIPHY: 7135 case SIOCGMIIREG: 7136 case SIOCSMIIREG: 7137 return igb_mii_ioctl(netdev, ifr, cmd); 7138 case SIOCGHWTSTAMP: 7139 return igb_ptp_get_ts_config(netdev, ifr); 7140 case SIOCSHWTSTAMP: 7141 return igb_ptp_set_ts_config(netdev, ifr); 7142 default: 7143 return -EOPNOTSUPP; 7144 } 7145 } 7146 7147 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7148 { 7149 struct igb_adapter *adapter = hw->back; 7150 7151 pci_read_config_word(adapter->pdev, reg, value); 7152 } 7153 7154 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7155 { 7156 struct igb_adapter *adapter = hw->back; 7157 7158 pci_write_config_word(adapter->pdev, reg, *value); 7159 } 7160 7161 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7162 { 7163 struct igb_adapter *adapter = hw->back; 7164 7165 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7166 return -E1000_ERR_CONFIG; 7167 7168 return 0; 7169 } 7170 7171 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7172 { 7173 struct igb_adapter *adapter = hw->back; 7174 7175 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7176 return -E1000_ERR_CONFIG; 7177 7178 return 0; 7179 } 7180 7181 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7182 { 7183 struct igb_adapter *adapter = netdev_priv(netdev); 7184 struct e1000_hw *hw = &adapter->hw; 7185 u32 ctrl, rctl; 7186 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7187 7188 if (enable) { 7189 /* enable VLAN tag insert/strip */ 7190 ctrl = rd32(E1000_CTRL); 7191 ctrl |= E1000_CTRL_VME; 7192 wr32(E1000_CTRL, ctrl); 7193 7194 /* Disable CFI check */ 7195 rctl = rd32(E1000_RCTL); 7196 rctl &= ~E1000_RCTL_CFIEN; 7197 wr32(E1000_RCTL, rctl); 7198 } else { 7199 /* disable VLAN tag insert/strip */ 7200 ctrl = rd32(E1000_CTRL); 7201 ctrl &= ~E1000_CTRL_VME; 7202 wr32(E1000_CTRL, ctrl); 7203 } 7204 7205 igb_rlpml_set(adapter); 7206 } 7207 7208 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7209 __be16 proto, u16 vid) 7210 { 7211 struct igb_adapter *adapter = netdev_priv(netdev); 7212 struct e1000_hw *hw = &adapter->hw; 7213 int pf_id = adapter->vfs_allocated_count; 7214 7215 /* attempt to add filter to vlvf array */ 7216 igb_vlvf_set(adapter, vid, true, pf_id); 7217 7218 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7219 igb_vfta_set(hw, vid, true); 7220 7221 set_bit(vid, adapter->active_vlans); 7222 7223 return 0; 7224 } 7225 7226 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7227 __be16 proto, u16 vid) 7228 { 7229 struct igb_adapter *adapter = netdev_priv(netdev); 7230 struct e1000_hw *hw = &adapter->hw; 7231 int pf_id = adapter->vfs_allocated_count; 7232 s32 err; 7233 7234 /* remove vlan from VLVF table array */ 7235 err = igb_vlvf_set(adapter, vid, false, pf_id); 7236 7237 /* if vid was not present in VLVF just remove it from table */ 7238 if (err) 7239 igb_vfta_set(hw, vid, false); 7240 7241 clear_bit(vid, adapter->active_vlans); 7242 7243 return 0; 7244 } 7245 7246 static void igb_restore_vlan(struct igb_adapter *adapter) 7247 { 7248 u16 vid; 7249 7250 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7251 7252 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7253 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7254 } 7255 7256 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7257 { 7258 struct pci_dev *pdev = adapter->pdev; 7259 struct e1000_mac_info *mac = &adapter->hw.mac; 7260 7261 mac->autoneg = 0; 7262 7263 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7264 * for the switch() below to work 7265 */ 7266 if ((spd & 1) || (dplx & ~1)) 7267 goto err_inval; 7268 7269 /* Fiber NIC's only allow 1000 gbps Full duplex 7270 * and 100Mbps Full duplex for 100baseFx sfp 7271 */ 7272 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7273 switch (spd + dplx) { 7274 case SPEED_10 + DUPLEX_HALF: 7275 case SPEED_10 + DUPLEX_FULL: 7276 case SPEED_100 + DUPLEX_HALF: 7277 goto err_inval; 7278 default: 7279 break; 7280 } 7281 } 7282 7283 switch (spd + dplx) { 7284 case SPEED_10 + DUPLEX_HALF: 7285 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7286 break; 7287 case SPEED_10 + DUPLEX_FULL: 7288 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7289 break; 7290 case SPEED_100 + DUPLEX_HALF: 7291 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7292 break; 7293 case SPEED_100 + DUPLEX_FULL: 7294 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7295 break; 7296 case SPEED_1000 + DUPLEX_FULL: 7297 mac->autoneg = 1; 7298 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7299 break; 7300 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7301 default: 7302 goto err_inval; 7303 } 7304 7305 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7306 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7307 7308 return 0; 7309 7310 err_inval: 7311 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7312 return -EINVAL; 7313 } 7314 7315 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7316 bool runtime) 7317 { 7318 struct net_device *netdev = pci_get_drvdata(pdev); 7319 struct igb_adapter *adapter = netdev_priv(netdev); 7320 struct e1000_hw *hw = &adapter->hw; 7321 u32 ctrl, rctl, status; 7322 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7323 #ifdef CONFIG_PM 7324 int retval = 0; 7325 #endif 7326 7327 netif_device_detach(netdev); 7328 7329 if (netif_running(netdev)) 7330 __igb_close(netdev, true); 7331 7332 igb_clear_interrupt_scheme(adapter); 7333 7334 #ifdef CONFIG_PM 7335 retval = pci_save_state(pdev); 7336 if (retval) 7337 return retval; 7338 #endif 7339 7340 status = rd32(E1000_STATUS); 7341 if (status & E1000_STATUS_LU) 7342 wufc &= ~E1000_WUFC_LNKC; 7343 7344 if (wufc) { 7345 igb_setup_rctl(adapter); 7346 igb_set_rx_mode(netdev); 7347 7348 /* turn on all-multi mode if wake on multicast is enabled */ 7349 if (wufc & E1000_WUFC_MC) { 7350 rctl = rd32(E1000_RCTL); 7351 rctl |= E1000_RCTL_MPE; 7352 wr32(E1000_RCTL, rctl); 7353 } 7354 7355 ctrl = rd32(E1000_CTRL); 7356 /* advertise wake from D3Cold */ 7357 #define E1000_CTRL_ADVD3WUC 0x00100000 7358 /* phy power management enable */ 7359 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7360 ctrl |= E1000_CTRL_ADVD3WUC; 7361 wr32(E1000_CTRL, ctrl); 7362 7363 /* Allow time for pending master requests to run */ 7364 igb_disable_pcie_master(hw); 7365 7366 wr32(E1000_WUC, E1000_WUC_PME_EN); 7367 wr32(E1000_WUFC, wufc); 7368 } else { 7369 wr32(E1000_WUC, 0); 7370 wr32(E1000_WUFC, 0); 7371 } 7372 7373 *enable_wake = wufc || adapter->en_mng_pt; 7374 if (!*enable_wake) 7375 igb_power_down_link(adapter); 7376 else 7377 igb_power_up_link(adapter); 7378 7379 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7380 * would have already happened in close and is redundant. 7381 */ 7382 igb_release_hw_control(adapter); 7383 7384 pci_disable_device(pdev); 7385 7386 return 0; 7387 } 7388 7389 #ifdef CONFIG_PM 7390 #ifdef CONFIG_PM_SLEEP 7391 static int igb_suspend(struct device *dev) 7392 { 7393 int retval; 7394 bool wake; 7395 struct pci_dev *pdev = to_pci_dev(dev); 7396 7397 retval = __igb_shutdown(pdev, &wake, 0); 7398 if (retval) 7399 return retval; 7400 7401 if (wake) { 7402 pci_prepare_to_sleep(pdev); 7403 } else { 7404 pci_wake_from_d3(pdev, false); 7405 pci_set_power_state(pdev, PCI_D3hot); 7406 } 7407 7408 return 0; 7409 } 7410 #endif /* CONFIG_PM_SLEEP */ 7411 7412 static int igb_resume(struct device *dev) 7413 { 7414 struct pci_dev *pdev = to_pci_dev(dev); 7415 struct net_device *netdev = pci_get_drvdata(pdev); 7416 struct igb_adapter *adapter = netdev_priv(netdev); 7417 struct e1000_hw *hw = &adapter->hw; 7418 u32 err; 7419 7420 pci_set_power_state(pdev, PCI_D0); 7421 pci_restore_state(pdev); 7422 pci_save_state(pdev); 7423 7424 if (!pci_device_is_present(pdev)) 7425 return -ENODEV; 7426 err = pci_enable_device_mem(pdev); 7427 if (err) { 7428 dev_err(&pdev->dev, 7429 "igb: Cannot enable PCI device from suspend\n"); 7430 return err; 7431 } 7432 pci_set_master(pdev); 7433 7434 pci_enable_wake(pdev, PCI_D3hot, 0); 7435 pci_enable_wake(pdev, PCI_D3cold, 0); 7436 7437 if (igb_init_interrupt_scheme(adapter, true)) { 7438 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7439 rtnl_unlock(); 7440 return -ENOMEM; 7441 } 7442 7443 igb_reset(adapter); 7444 7445 /* let the f/w know that the h/w is now under the control of the 7446 * driver. 7447 */ 7448 igb_get_hw_control(adapter); 7449 7450 wr32(E1000_WUS, ~0); 7451 7452 if (netdev->flags & IFF_UP) { 7453 rtnl_lock(); 7454 err = __igb_open(netdev, true); 7455 rtnl_unlock(); 7456 if (err) 7457 return err; 7458 } 7459 7460 netif_device_attach(netdev); 7461 return 0; 7462 } 7463 7464 static int igb_runtime_idle(struct device *dev) 7465 { 7466 struct pci_dev *pdev = to_pci_dev(dev); 7467 struct net_device *netdev = pci_get_drvdata(pdev); 7468 struct igb_adapter *adapter = netdev_priv(netdev); 7469 7470 if (!igb_has_link(adapter)) 7471 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7472 7473 return -EBUSY; 7474 } 7475 7476 static int igb_runtime_suspend(struct device *dev) 7477 { 7478 struct pci_dev *pdev = to_pci_dev(dev); 7479 int retval; 7480 bool wake; 7481 7482 retval = __igb_shutdown(pdev, &wake, 1); 7483 if (retval) 7484 return retval; 7485 7486 if (wake) { 7487 pci_prepare_to_sleep(pdev); 7488 } else { 7489 pci_wake_from_d3(pdev, false); 7490 pci_set_power_state(pdev, PCI_D3hot); 7491 } 7492 7493 return 0; 7494 } 7495 7496 static int igb_runtime_resume(struct device *dev) 7497 { 7498 return igb_resume(dev); 7499 } 7500 #endif /* CONFIG_PM */ 7501 7502 static void igb_shutdown(struct pci_dev *pdev) 7503 { 7504 bool wake; 7505 7506 __igb_shutdown(pdev, &wake, 0); 7507 7508 if (system_state == SYSTEM_POWER_OFF) { 7509 pci_wake_from_d3(pdev, wake); 7510 pci_set_power_state(pdev, PCI_D3hot); 7511 } 7512 } 7513 7514 #ifdef CONFIG_PCI_IOV 7515 static int igb_sriov_reinit(struct pci_dev *dev) 7516 { 7517 struct net_device *netdev = pci_get_drvdata(dev); 7518 struct igb_adapter *adapter = netdev_priv(netdev); 7519 struct pci_dev *pdev = adapter->pdev; 7520 7521 rtnl_lock(); 7522 7523 if (netif_running(netdev)) 7524 igb_close(netdev); 7525 else 7526 igb_reset(adapter); 7527 7528 igb_clear_interrupt_scheme(adapter); 7529 7530 igb_init_queue_configuration(adapter); 7531 7532 if (igb_init_interrupt_scheme(adapter, true)) { 7533 rtnl_unlock(); 7534 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7535 return -ENOMEM; 7536 } 7537 7538 if (netif_running(netdev)) 7539 igb_open(netdev); 7540 7541 rtnl_unlock(); 7542 7543 return 0; 7544 } 7545 7546 static int igb_pci_disable_sriov(struct pci_dev *dev) 7547 { 7548 int err = igb_disable_sriov(dev); 7549 7550 if (!err) 7551 err = igb_sriov_reinit(dev); 7552 7553 return err; 7554 } 7555 7556 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7557 { 7558 int err = igb_enable_sriov(dev, num_vfs); 7559 7560 if (err) 7561 goto out; 7562 7563 err = igb_sriov_reinit(dev); 7564 if (!err) 7565 return num_vfs; 7566 7567 out: 7568 return err; 7569 } 7570 7571 #endif 7572 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7573 { 7574 #ifdef CONFIG_PCI_IOV 7575 if (num_vfs == 0) 7576 return igb_pci_disable_sriov(dev); 7577 else 7578 return igb_pci_enable_sriov(dev, num_vfs); 7579 #endif 7580 return 0; 7581 } 7582 7583 #ifdef CONFIG_NET_POLL_CONTROLLER 7584 /* Polling 'interrupt' - used by things like netconsole to send skbs 7585 * without having to re-enable interrupts. It's not called while 7586 * the interrupt routine is executing. 7587 */ 7588 static void igb_netpoll(struct net_device *netdev) 7589 { 7590 struct igb_adapter *adapter = netdev_priv(netdev); 7591 struct e1000_hw *hw = &adapter->hw; 7592 struct igb_q_vector *q_vector; 7593 int i; 7594 7595 for (i = 0; i < adapter->num_q_vectors; i++) { 7596 q_vector = adapter->q_vector[i]; 7597 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7598 wr32(E1000_EIMC, q_vector->eims_value); 7599 else 7600 igb_irq_disable(adapter); 7601 napi_schedule(&q_vector->napi); 7602 } 7603 } 7604 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7605 7606 /** 7607 * igb_io_error_detected - called when PCI error is detected 7608 * @pdev: Pointer to PCI device 7609 * @state: The current pci connection state 7610 * 7611 * This function is called after a PCI bus error affecting 7612 * this device has been detected. 7613 **/ 7614 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7615 pci_channel_state_t state) 7616 { 7617 struct net_device *netdev = pci_get_drvdata(pdev); 7618 struct igb_adapter *adapter = netdev_priv(netdev); 7619 7620 netif_device_detach(netdev); 7621 7622 if (state == pci_channel_io_perm_failure) 7623 return PCI_ERS_RESULT_DISCONNECT; 7624 7625 if (netif_running(netdev)) 7626 igb_down(adapter); 7627 pci_disable_device(pdev); 7628 7629 /* Request a slot slot reset. */ 7630 return PCI_ERS_RESULT_NEED_RESET; 7631 } 7632 7633 /** 7634 * igb_io_slot_reset - called after the pci bus has been reset. 7635 * @pdev: Pointer to PCI device 7636 * 7637 * Restart the card from scratch, as if from a cold-boot. Implementation 7638 * resembles the first-half of the igb_resume routine. 7639 **/ 7640 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7641 { 7642 struct net_device *netdev = pci_get_drvdata(pdev); 7643 struct igb_adapter *adapter = netdev_priv(netdev); 7644 struct e1000_hw *hw = &adapter->hw; 7645 pci_ers_result_t result; 7646 int err; 7647 7648 if (pci_enable_device_mem(pdev)) { 7649 dev_err(&pdev->dev, 7650 "Cannot re-enable PCI device after reset.\n"); 7651 result = PCI_ERS_RESULT_DISCONNECT; 7652 } else { 7653 pci_set_master(pdev); 7654 pci_restore_state(pdev); 7655 pci_save_state(pdev); 7656 7657 pci_enable_wake(pdev, PCI_D3hot, 0); 7658 pci_enable_wake(pdev, PCI_D3cold, 0); 7659 7660 igb_reset(adapter); 7661 wr32(E1000_WUS, ~0); 7662 result = PCI_ERS_RESULT_RECOVERED; 7663 } 7664 7665 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7666 if (err) { 7667 dev_err(&pdev->dev, 7668 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7669 err); 7670 /* non-fatal, continue */ 7671 } 7672 7673 return result; 7674 } 7675 7676 /** 7677 * igb_io_resume - called when traffic can start flowing again. 7678 * @pdev: Pointer to PCI device 7679 * 7680 * This callback is called when the error recovery driver tells us that 7681 * its OK to resume normal operation. Implementation resembles the 7682 * second-half of the igb_resume routine. 7683 */ 7684 static void igb_io_resume(struct pci_dev *pdev) 7685 { 7686 struct net_device *netdev = pci_get_drvdata(pdev); 7687 struct igb_adapter *adapter = netdev_priv(netdev); 7688 7689 if (netif_running(netdev)) { 7690 if (igb_up(adapter)) { 7691 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7692 return; 7693 } 7694 } 7695 7696 netif_device_attach(netdev); 7697 7698 /* let the f/w know that the h/w is now under the control of the 7699 * driver. 7700 */ 7701 igb_get_hw_control(adapter); 7702 } 7703 7704 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7705 u8 qsel) 7706 { 7707 u32 rar_low, rar_high; 7708 struct e1000_hw *hw = &adapter->hw; 7709 7710 /* HW expects these in little endian so we reverse the byte order 7711 * from network order (big endian) to little endian 7712 */ 7713 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7714 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7715 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7716 7717 /* Indicate to hardware the Address is Valid. */ 7718 rar_high |= E1000_RAH_AV; 7719 7720 if (hw->mac.type == e1000_82575) 7721 rar_high |= E1000_RAH_POOL_1 * qsel; 7722 else 7723 rar_high |= E1000_RAH_POOL_1 << qsel; 7724 7725 wr32(E1000_RAL(index), rar_low); 7726 wrfl(); 7727 wr32(E1000_RAH(index), rar_high); 7728 wrfl(); 7729 } 7730 7731 static int igb_set_vf_mac(struct igb_adapter *adapter, 7732 int vf, unsigned char *mac_addr) 7733 { 7734 struct e1000_hw *hw = &adapter->hw; 7735 /* VF MAC addresses start at end of receive addresses and moves 7736 * towards the first, as a result a collision should not be possible 7737 */ 7738 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7739 7740 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7741 7742 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7743 7744 return 0; 7745 } 7746 7747 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7748 { 7749 struct igb_adapter *adapter = netdev_priv(netdev); 7750 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7751 return -EINVAL; 7752 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7753 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7754 dev_info(&adapter->pdev->dev, 7755 "Reload the VF driver to make this change effective."); 7756 if (test_bit(__IGB_DOWN, &adapter->state)) { 7757 dev_warn(&adapter->pdev->dev, 7758 "The VF MAC address has been set, but the PF device is not up.\n"); 7759 dev_warn(&adapter->pdev->dev, 7760 "Bring the PF device up before attempting to use the VF device.\n"); 7761 } 7762 return igb_set_vf_mac(adapter, vf, mac); 7763 } 7764 7765 static int igb_link_mbps(int internal_link_speed) 7766 { 7767 switch (internal_link_speed) { 7768 case SPEED_100: 7769 return 100; 7770 case SPEED_1000: 7771 return 1000; 7772 default: 7773 return 0; 7774 } 7775 } 7776 7777 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7778 int link_speed) 7779 { 7780 int rf_dec, rf_int; 7781 u32 bcnrc_val; 7782 7783 if (tx_rate != 0) { 7784 /* Calculate the rate factor values to set */ 7785 rf_int = link_speed / tx_rate; 7786 rf_dec = (link_speed - (rf_int * tx_rate)); 7787 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7788 tx_rate; 7789 7790 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7791 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7792 E1000_RTTBCNRC_RF_INT_MASK); 7793 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7794 } else { 7795 bcnrc_val = 0; 7796 } 7797 7798 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7799 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7800 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7801 */ 7802 wr32(E1000_RTTBCNRM, 0x14); 7803 wr32(E1000_RTTBCNRC, bcnrc_val); 7804 } 7805 7806 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7807 { 7808 int actual_link_speed, i; 7809 bool reset_rate = false; 7810 7811 /* VF TX rate limit was not set or not supported */ 7812 if ((adapter->vf_rate_link_speed == 0) || 7813 (adapter->hw.mac.type != e1000_82576)) 7814 return; 7815 7816 actual_link_speed = igb_link_mbps(adapter->link_speed); 7817 if (actual_link_speed != adapter->vf_rate_link_speed) { 7818 reset_rate = true; 7819 adapter->vf_rate_link_speed = 0; 7820 dev_info(&adapter->pdev->dev, 7821 "Link speed has been changed. VF Transmit rate is disabled\n"); 7822 } 7823 7824 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7825 if (reset_rate) 7826 adapter->vf_data[i].tx_rate = 0; 7827 7828 igb_set_vf_rate_limit(&adapter->hw, i, 7829 adapter->vf_data[i].tx_rate, 7830 actual_link_speed); 7831 } 7832 } 7833 7834 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 7835 int min_tx_rate, int max_tx_rate) 7836 { 7837 struct igb_adapter *adapter = netdev_priv(netdev); 7838 struct e1000_hw *hw = &adapter->hw; 7839 int actual_link_speed; 7840 7841 if (hw->mac.type != e1000_82576) 7842 return -EOPNOTSUPP; 7843 7844 if (min_tx_rate) 7845 return -EINVAL; 7846 7847 actual_link_speed = igb_link_mbps(adapter->link_speed); 7848 if ((vf >= adapter->vfs_allocated_count) || 7849 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7850 (max_tx_rate < 0) || 7851 (max_tx_rate > actual_link_speed)) 7852 return -EINVAL; 7853 7854 adapter->vf_rate_link_speed = actual_link_speed; 7855 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 7856 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 7857 7858 return 0; 7859 } 7860 7861 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7862 bool setting) 7863 { 7864 struct igb_adapter *adapter = netdev_priv(netdev); 7865 struct e1000_hw *hw = &adapter->hw; 7866 u32 reg_val, reg_offset; 7867 7868 if (!adapter->vfs_allocated_count) 7869 return -EOPNOTSUPP; 7870 7871 if (vf >= adapter->vfs_allocated_count) 7872 return -EINVAL; 7873 7874 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7875 reg_val = rd32(reg_offset); 7876 if (setting) 7877 reg_val |= ((1 << vf) | 7878 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7879 else 7880 reg_val &= ~((1 << vf) | 7881 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7882 wr32(reg_offset, reg_val); 7883 7884 adapter->vf_data[vf].spoofchk_enabled = setting; 7885 return 0; 7886 } 7887 7888 static int igb_ndo_get_vf_config(struct net_device *netdev, 7889 int vf, struct ifla_vf_info *ivi) 7890 { 7891 struct igb_adapter *adapter = netdev_priv(netdev); 7892 if (vf >= adapter->vfs_allocated_count) 7893 return -EINVAL; 7894 ivi->vf = vf; 7895 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7896 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 7897 ivi->min_tx_rate = 0; 7898 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7899 ivi->qos = adapter->vf_data[vf].pf_qos; 7900 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7901 return 0; 7902 } 7903 7904 static void igb_vmm_control(struct igb_adapter *adapter) 7905 { 7906 struct e1000_hw *hw = &adapter->hw; 7907 u32 reg; 7908 7909 switch (hw->mac.type) { 7910 case e1000_82575: 7911 case e1000_i210: 7912 case e1000_i211: 7913 case e1000_i354: 7914 default: 7915 /* replication is not supported for 82575 */ 7916 return; 7917 case e1000_82576: 7918 /* notify HW that the MAC is adding vlan tags */ 7919 reg = rd32(E1000_DTXCTL); 7920 reg |= E1000_DTXCTL_VLAN_ADDED; 7921 wr32(E1000_DTXCTL, reg); 7922 /* Fall through */ 7923 case e1000_82580: 7924 /* enable replication vlan tag stripping */ 7925 reg = rd32(E1000_RPLOLR); 7926 reg |= E1000_RPLOLR_STRVLAN; 7927 wr32(E1000_RPLOLR, reg); 7928 /* Fall through */ 7929 case e1000_i350: 7930 /* none of the above registers are supported by i350 */ 7931 break; 7932 } 7933 7934 if (adapter->vfs_allocated_count) { 7935 igb_vmdq_set_loopback_pf(hw, true); 7936 igb_vmdq_set_replication_pf(hw, true); 7937 igb_vmdq_set_anti_spoofing_pf(hw, true, 7938 adapter->vfs_allocated_count); 7939 } else { 7940 igb_vmdq_set_loopback_pf(hw, false); 7941 igb_vmdq_set_replication_pf(hw, false); 7942 } 7943 } 7944 7945 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7946 { 7947 struct e1000_hw *hw = &adapter->hw; 7948 u32 dmac_thr; 7949 u16 hwm; 7950 7951 if (hw->mac.type > e1000_82580) { 7952 if (adapter->flags & IGB_FLAG_DMAC) { 7953 u32 reg; 7954 7955 /* force threshold to 0. */ 7956 wr32(E1000_DMCTXTH, 0); 7957 7958 /* DMA Coalescing high water mark needs to be greater 7959 * than the Rx threshold. Set hwm to PBA - max frame 7960 * size in 16B units, capping it at PBA - 6KB. 7961 */ 7962 hwm = 64 * pba - adapter->max_frame_size / 16; 7963 if (hwm < 64 * (pba - 6)) 7964 hwm = 64 * (pba - 6); 7965 reg = rd32(E1000_FCRTC); 7966 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7967 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7968 & E1000_FCRTC_RTH_COAL_MASK); 7969 wr32(E1000_FCRTC, reg); 7970 7971 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7972 * frame size, capping it at PBA - 10KB. 7973 */ 7974 dmac_thr = pba - adapter->max_frame_size / 512; 7975 if (dmac_thr < pba - 10) 7976 dmac_thr = pba - 10; 7977 reg = rd32(E1000_DMACR); 7978 reg &= ~E1000_DMACR_DMACTHR_MASK; 7979 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7980 & E1000_DMACR_DMACTHR_MASK); 7981 7982 /* transition to L0x or L1 if available..*/ 7983 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7984 7985 /* watchdog timer= +-1000 usec in 32usec intervals */ 7986 reg |= (1000 >> 5); 7987 7988 /* Disable BMC-to-OS Watchdog Enable */ 7989 if (hw->mac.type != e1000_i354) 7990 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7991 7992 wr32(E1000_DMACR, reg); 7993 7994 /* no lower threshold to disable 7995 * coalescing(smart fifb)-UTRESH=0 7996 */ 7997 wr32(E1000_DMCRTRH, 0); 7998 7999 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8000 8001 wr32(E1000_DMCTLX, reg); 8002 8003 /* free space in tx packet buffer to wake from 8004 * DMA coal 8005 */ 8006 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8007 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8008 8009 /* make low power state decision controlled 8010 * by DMA coal 8011 */ 8012 reg = rd32(E1000_PCIEMISC); 8013 reg &= ~E1000_PCIEMISC_LX_DECISION; 8014 wr32(E1000_PCIEMISC, reg); 8015 } /* endif adapter->dmac is not disabled */ 8016 } else if (hw->mac.type == e1000_82580) { 8017 u32 reg = rd32(E1000_PCIEMISC); 8018 8019 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8020 wr32(E1000_DMACR, 0); 8021 } 8022 } 8023 8024 /** 8025 * igb_read_i2c_byte - Reads 8 bit word over I2C 8026 * @hw: pointer to hardware structure 8027 * @byte_offset: byte offset to read 8028 * @dev_addr: device address 8029 * @data: value read 8030 * 8031 * Performs byte read operation over I2C interface at 8032 * a specified device address. 8033 **/ 8034 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8035 u8 dev_addr, u8 *data) 8036 { 8037 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8038 struct i2c_client *this_client = adapter->i2c_client; 8039 s32 status; 8040 u16 swfw_mask = 0; 8041 8042 if (!this_client) 8043 return E1000_ERR_I2C; 8044 8045 swfw_mask = E1000_SWFW_PHY0_SM; 8046 8047 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8048 return E1000_ERR_SWFW_SYNC; 8049 8050 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8051 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8052 8053 if (status < 0) 8054 return E1000_ERR_I2C; 8055 else { 8056 *data = status; 8057 return 0; 8058 } 8059 } 8060 8061 /** 8062 * igb_write_i2c_byte - Writes 8 bit word over I2C 8063 * @hw: pointer to hardware structure 8064 * @byte_offset: byte offset to write 8065 * @dev_addr: device address 8066 * @data: value to write 8067 * 8068 * Performs byte write operation over I2C interface at 8069 * a specified device address. 8070 **/ 8071 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8072 u8 dev_addr, u8 data) 8073 { 8074 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8075 struct i2c_client *this_client = adapter->i2c_client; 8076 s32 status; 8077 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8078 8079 if (!this_client) 8080 return E1000_ERR_I2C; 8081 8082 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8083 return E1000_ERR_SWFW_SYNC; 8084 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8085 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8086 8087 if (status) 8088 return E1000_ERR_I2C; 8089 else 8090 return 0; 8091 8092 } 8093 8094 int igb_reinit_queues(struct igb_adapter *adapter) 8095 { 8096 struct net_device *netdev = adapter->netdev; 8097 struct pci_dev *pdev = adapter->pdev; 8098 int err = 0; 8099 8100 if (netif_running(netdev)) 8101 igb_close(netdev); 8102 8103 igb_reset_interrupt_capability(adapter); 8104 8105 if (igb_init_interrupt_scheme(adapter, true)) { 8106 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8107 return -ENOMEM; 8108 } 8109 8110 if (netif_running(netdev)) 8111 err = igb_open(netdev); 8112 8113 return err; 8114 } 8115 /* igb_main.c */ 8116