1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 110 static void igb_remove(struct pci_dev *pdev); 111 static void igb_init_queue_configuration(struct igb_adapter *adapter); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 179 #endif 180 181 static int igb_suspend(struct device *); 182 static int igb_resume(struct device *); 183 static int igb_runtime_suspend(struct device *dev); 184 static int igb_runtime_resume(struct device *dev); 185 static int igb_runtime_idle(struct device *dev); 186 #ifdef CONFIG_PM 187 static const struct dev_pm_ops igb_pm_ops = { 188 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 189 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 190 igb_runtime_idle) 191 }; 192 #endif 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { __le64 a; __le64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) { 581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 582 } else { 583 i2cctl &= ~E1000_I2C_DATA_OE_N; 584 i2cctl &= ~E1000_I2C_DATA_OUT; 585 } 586 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 } 590 591 /** 592 * igb_set_i2c_clk - Sets the I2C SCL clock 593 * @data: pointer to hardware structure 594 * @state: state to set clock 595 * 596 * Sets the I2C clock line to state 597 **/ 598 static void igb_set_i2c_clk(void *data, int state) 599 { 600 struct igb_adapter *adapter = (struct igb_adapter *)data; 601 struct e1000_hw *hw = &adapter->hw; 602 s32 i2cctl = rd32(E1000_I2CPARAMS); 603 604 if (state) { 605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 606 } else { 607 i2cctl &= ~E1000_I2C_CLK_OUT; 608 i2cctl &= ~E1000_I2C_CLK_OE_N; 609 } 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 } 613 614 /** 615 * igb_get_i2c_clk - Gets the I2C SCL clock state 616 * @data: pointer to hardware structure 617 * 618 * Gets the I2C clock state 619 **/ 620 static int igb_get_i2c_clk(void *data) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 return !!(i2cctl & E1000_I2C_CLK_IN); 627 } 628 629 static const struct i2c_algo_bit_data igb_i2c_algo = { 630 .setsda = igb_set_i2c_data, 631 .setscl = igb_set_i2c_clk, 632 .getsda = igb_get_i2c_data, 633 .getscl = igb_get_i2c_clk, 634 .udelay = 5, 635 .timeout = 20, 636 }; 637 638 /** 639 * igb_get_hw_dev - return device 640 * @hw: pointer to hardware structure 641 * 642 * used by hardware layer to print debugging information 643 **/ 644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 645 { 646 struct igb_adapter *adapter = hw->back; 647 return adapter->netdev; 648 } 649 650 /** 651 * igb_init_module - Driver Registration Routine 652 * 653 * igb_init_module is the first routine called when the driver is 654 * loaded. All it does is register with the PCI subsystem. 655 **/ 656 static int __init igb_init_module(void) 657 { 658 int ret; 659 660 pr_info("%s\n", igb_driver_string); 661 pr_info("%s\n", igb_copyright); 662 663 #ifdef CONFIG_IGB_DCA 664 dca_register_notify(&dca_notifier); 665 #endif 666 ret = pci_register_driver(&igb_driver); 667 return ret; 668 } 669 670 module_init(igb_init_module); 671 672 /** 673 * igb_exit_module - Driver Exit Cleanup Routine 674 * 675 * igb_exit_module is called just before the driver is removed 676 * from memory. 677 **/ 678 static void __exit igb_exit_module(void) 679 { 680 #ifdef CONFIG_IGB_DCA 681 dca_unregister_notify(&dca_notifier); 682 #endif 683 pci_unregister_driver(&igb_driver); 684 } 685 686 module_exit(igb_exit_module); 687 688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 689 /** 690 * igb_cache_ring_register - Descriptor ring to register mapping 691 * @adapter: board private structure to initialize 692 * 693 * Once we know the feature-set enabled for the device, we'll cache 694 * the register offset the descriptor ring is assigned to. 695 **/ 696 static void igb_cache_ring_register(struct igb_adapter *adapter) 697 { 698 int i = 0, j = 0; 699 u32 rbase_offset = adapter->vfs_allocated_count; 700 701 switch (adapter->hw.mac.type) { 702 case e1000_82576: 703 /* The queues are allocated for virtualization such that VF 0 704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 705 * In order to avoid collision we start at the first free queue 706 * and continue consuming queues in the same sequence 707 */ 708 if (adapter->vfs_allocated_count) { 709 for (; i < adapter->rss_queues; i++) 710 adapter->rx_ring[i]->reg_idx = rbase_offset + 711 Q_IDX_82576(i); 712 } 713 fallthrough; 714 case e1000_82575: 715 case e1000_82580: 716 case e1000_i350: 717 case e1000_i354: 718 case e1000_i210: 719 case e1000_i211: 720 default: 721 for (; i < adapter->num_rx_queues; i++) 722 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 723 for (; j < adapter->num_tx_queues; j++) 724 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 725 break; 726 } 727 } 728 729 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 730 { 731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 733 u32 value = 0; 734 735 if (E1000_REMOVED(hw_addr)) 736 return ~value; 737 738 value = readl(&hw_addr[reg]); 739 740 /* reads should not return all F's */ 741 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 742 struct net_device *netdev = igb->netdev; 743 hw->hw_addr = NULL; 744 netdev_err(netdev, "PCIe link lost\n"); 745 WARN(pci_device_is_present(igb->pdev), 746 "igb: Failed to read reg 0x%x!\n", reg); 747 } 748 749 return value; 750 } 751 752 /** 753 * igb_write_ivar - configure ivar for given MSI-X vector 754 * @hw: pointer to the HW structure 755 * @msix_vector: vector number we are allocating to a given ring 756 * @index: row index of IVAR register to write within IVAR table 757 * @offset: column offset of in IVAR, should be multiple of 8 758 * 759 * This function is intended to handle the writing of the IVAR register 760 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 761 * each containing an cause allocation for an Rx and Tx ring, and a 762 * variable number of rows depending on the number of queues supported. 763 **/ 764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 765 int index, int offset) 766 { 767 u32 ivar = array_rd32(E1000_IVAR0, index); 768 769 /* clear any bits that are currently set */ 770 ivar &= ~((u32)0xFF << offset); 771 772 /* write vector and valid bit */ 773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 774 775 array_wr32(E1000_IVAR0, index, ivar); 776 } 777 778 #define IGB_N0_QUEUE -1 779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 780 { 781 struct igb_adapter *adapter = q_vector->adapter; 782 struct e1000_hw *hw = &adapter->hw; 783 int rx_queue = IGB_N0_QUEUE; 784 int tx_queue = IGB_N0_QUEUE; 785 u32 msixbm = 0; 786 787 if (q_vector->rx.ring) 788 rx_queue = q_vector->rx.ring->reg_idx; 789 if (q_vector->tx.ring) 790 tx_queue = q_vector->tx.ring->reg_idx; 791 792 switch (hw->mac.type) { 793 case e1000_82575: 794 /* The 82575 assigns vectors using a bitmask, which matches the 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one 796 * or more queues to a vector, we write the appropriate bits 797 * into the MSIXBM register for that vector. 798 */ 799 if (rx_queue > IGB_N0_QUEUE) 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 801 if (tx_queue > IGB_N0_QUEUE) 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 804 msixbm |= E1000_EIMS_OTHER; 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 806 q_vector->eims_value = msixbm; 807 break; 808 case e1000_82576: 809 /* 82576 uses a table that essentially consists of 2 columns 810 * with 8 rows. The ordering is column-major so we use the 811 * lower 3 bits as the row index, and the 4th bit as the 812 * column offset. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue & 0x7, 817 (rx_queue & 0x8) << 1); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue & 0x7, 821 ((tx_queue & 0x8) << 1) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 case e1000_82580: 825 case e1000_i350: 826 case e1000_i354: 827 case e1000_i210: 828 case e1000_i211: 829 /* On 82580 and newer adapters the scheme is similar to 82576 830 * however instead of ordering column-major we have things 831 * ordered row-major. So we traverse the table by using 832 * bit 0 as the column offset, and the remaining bits as the 833 * row index. 834 */ 835 if (rx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 rx_queue >> 1, 838 (rx_queue & 0x1) << 4); 839 if (tx_queue > IGB_N0_QUEUE) 840 igb_write_ivar(hw, msix_vector, 841 tx_queue >> 1, 842 ((tx_queue & 0x1) << 4) + 8); 843 q_vector->eims_value = BIT(msix_vector); 844 break; 845 default: 846 BUG(); 847 break; 848 } 849 850 /* add q_vector eims value to global eims_enable_mask */ 851 adapter->eims_enable_mask |= q_vector->eims_value; 852 853 /* configure q_vector to set itr on first interrupt */ 854 q_vector->set_itr = 1; 855 } 856 857 /** 858 * igb_configure_msix - Configure MSI-X hardware 859 * @adapter: board private structure to initialize 860 * 861 * igb_configure_msix sets up the hardware to properly 862 * generate MSI-X interrupts. 863 **/ 864 static void igb_configure_msix(struct igb_adapter *adapter) 865 { 866 u32 tmp; 867 int i, vector = 0; 868 struct e1000_hw *hw = &adapter->hw; 869 870 adapter->eims_enable_mask = 0; 871 872 /* set vector for other causes, i.e. link changes */ 873 switch (hw->mac.type) { 874 case e1000_82575: 875 tmp = rd32(E1000_CTRL_EXT); 876 /* enable MSI-X PBA support*/ 877 tmp |= E1000_CTRL_EXT_PBA_CLR; 878 879 /* Auto-Mask interrupts upon ICR read. */ 880 tmp |= E1000_CTRL_EXT_EIAME; 881 tmp |= E1000_CTRL_EXT_IRCA; 882 883 wr32(E1000_CTRL_EXT, tmp); 884 885 /* enable msix_other interrupt */ 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 887 adapter->eims_other = E1000_EIMS_OTHER; 888 889 break; 890 891 case e1000_82576: 892 case e1000_82580: 893 case e1000_i350: 894 case e1000_i354: 895 case e1000_i210: 896 case e1000_i211: 897 /* Turn on MSI-X capability first, or our settings 898 * won't stick. And it will take days to debug. 899 */ 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 901 E1000_GPIE_PBA | E1000_GPIE_EIAME | 902 E1000_GPIE_NSICR); 903 904 /* enable msix_other interrupt */ 905 adapter->eims_other = BIT(vector); 906 tmp = (vector++ | E1000_IVAR_VALID) << 8; 907 908 wr32(E1000_IVAR_MISC, tmp); 909 break; 910 default: 911 /* do nothing, since nothing else supports MSI-X */ 912 break; 913 } /* switch (hw->mac.type) */ 914 915 adapter->eims_enable_mask |= adapter->eims_other; 916 917 for (i = 0; i < adapter->num_q_vectors; i++) 918 igb_assign_vector(adapter->q_vector[i], vector++); 919 920 wrfl(); 921 } 922 923 /** 924 * igb_request_msix - Initialize MSI-X interrupts 925 * @adapter: board private structure to initialize 926 * 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 928 * kernel. 929 **/ 930 static int igb_request_msix(struct igb_adapter *adapter) 931 { 932 unsigned int num_q_vectors = adapter->num_q_vectors; 933 struct net_device *netdev = adapter->netdev; 934 int i, err = 0, vector = 0, free_vector = 0; 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_other, 0, netdev->name, adapter); 938 if (err) 939 goto err_out; 940 941 if (num_q_vectors > MAX_Q_VECTORS) { 942 num_q_vectors = MAX_Q_VECTORS; 943 dev_warn(&adapter->pdev->dev, 944 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 945 adapter->num_q_vectors, MAX_Q_VECTORS); 946 } 947 for (i = 0; i < num_q_vectors; i++) { 948 struct igb_q_vector *q_vector = adapter->q_vector[i]; 949 950 vector++; 951 952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 953 954 if (q_vector->rx.ring && q_vector->tx.ring) 955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 956 q_vector->rx.ring->queue_index); 957 else if (q_vector->tx.ring) 958 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 959 q_vector->tx.ring->queue_index); 960 else if (q_vector->rx.ring) 961 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 962 q_vector->rx.ring->queue_index); 963 else 964 sprintf(q_vector->name, "%s-unused", netdev->name); 965 966 err = request_irq(adapter->msix_entries[vector].vector, 967 igb_msix_ring, 0, q_vector->name, 968 q_vector); 969 if (err) 970 goto err_free; 971 } 972 973 igb_configure_msix(adapter); 974 return 0; 975 976 err_free: 977 /* free already assigned IRQs */ 978 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 979 980 vector--; 981 for (i = 0; i < vector; i++) { 982 free_irq(adapter->msix_entries[free_vector++].vector, 983 adapter->q_vector[i]); 984 } 985 err_out: 986 return err; 987 } 988 989 /** 990 * igb_free_q_vector - Free memory allocated for specific interrupt vector 991 * @adapter: board private structure to initialize 992 * @v_idx: Index of vector to be freed 993 * 994 * This function frees the memory allocated to the q_vector. 995 **/ 996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 997 { 998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 999 1000 adapter->q_vector[v_idx] = NULL; 1001 1002 /* igb_get_stats64() might access the rings on this vector, 1003 * we must wait a grace period before freeing it. 1004 */ 1005 if (q_vector) 1006 kfree_rcu(q_vector, rcu); 1007 } 1008 1009 /** 1010 * igb_reset_q_vector - Reset config for interrupt vector 1011 * @adapter: board private structure to initialize 1012 * @v_idx: Index of vector to be reset 1013 * 1014 * If NAPI is enabled it will delete any references to the 1015 * NAPI struct. This is preparation for igb_free_q_vector. 1016 **/ 1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1018 { 1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1020 1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1022 * allocated. So, q_vector is NULL so we should stop here. 1023 */ 1024 if (!q_vector) 1025 return; 1026 1027 if (q_vector->tx.ring) 1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1029 1030 if (q_vector->rx.ring) 1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1032 1033 netif_napi_del(&q_vector->napi); 1034 1035 } 1036 1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1038 { 1039 int v_idx = adapter->num_q_vectors; 1040 1041 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1042 pci_disable_msix(adapter->pdev); 1043 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1044 pci_disable_msi(adapter->pdev); 1045 1046 while (v_idx--) 1047 igb_reset_q_vector(adapter, v_idx); 1048 } 1049 1050 /** 1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1052 * @adapter: board private structure to initialize 1053 * 1054 * This function frees the memory allocated to the q_vectors. In addition if 1055 * NAPI is enabled it will delete any references to the NAPI struct prior 1056 * to freeing the q_vector. 1057 **/ 1058 static void igb_free_q_vectors(struct igb_adapter *adapter) 1059 { 1060 int v_idx = adapter->num_q_vectors; 1061 1062 adapter->num_tx_queues = 0; 1063 adapter->num_rx_queues = 0; 1064 adapter->num_q_vectors = 0; 1065 1066 while (v_idx--) { 1067 igb_reset_q_vector(adapter, v_idx); 1068 igb_free_q_vector(adapter, v_idx); 1069 } 1070 } 1071 1072 /** 1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1074 * @adapter: board private structure to initialize 1075 * 1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1077 * MSI-X interrupts allocated. 1078 */ 1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1080 { 1081 igb_free_q_vectors(adapter); 1082 igb_reset_interrupt_capability(adapter); 1083 } 1084 1085 /** 1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1087 * @adapter: board private structure to initialize 1088 * @msix: boolean value of MSIX capability 1089 * 1090 * Attempt to configure interrupts using the best available 1091 * capabilities of the hardware and kernel. 1092 **/ 1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1094 { 1095 int err; 1096 int numvecs, i; 1097 1098 if (!msix) 1099 goto msi_only; 1100 adapter->flags |= IGB_FLAG_HAS_MSIX; 1101 1102 /* Number of supported queues. */ 1103 adapter->num_rx_queues = adapter->rss_queues; 1104 if (adapter->vfs_allocated_count) 1105 adapter->num_tx_queues = 1; 1106 else 1107 adapter->num_tx_queues = adapter->rss_queues; 1108 1109 /* start with one vector for every Rx queue */ 1110 numvecs = adapter->num_rx_queues; 1111 1112 /* if Tx handler is separate add 1 for every Tx queue */ 1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1114 numvecs += adapter->num_tx_queues; 1115 1116 /* store the number of vectors reserved for queues */ 1117 adapter->num_q_vectors = numvecs; 1118 1119 /* add 1 vector for link status interrupts */ 1120 numvecs++; 1121 for (i = 0; i < numvecs; i++) 1122 adapter->msix_entries[i].entry = i; 1123 1124 err = pci_enable_msix_range(adapter->pdev, 1125 adapter->msix_entries, 1126 numvecs, 1127 numvecs); 1128 if (err > 0) 1129 return; 1130 1131 igb_reset_interrupt_capability(adapter); 1132 1133 /* If we can't do MSI-X, try MSI */ 1134 msi_only: 1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1136 #ifdef CONFIG_PCI_IOV 1137 /* disable SR-IOV for non MSI-X configurations */ 1138 if (adapter->vf_data) { 1139 struct e1000_hw *hw = &adapter->hw; 1140 /* disable iov and allow time for transactions to clear */ 1141 pci_disable_sriov(adapter->pdev); 1142 msleep(500); 1143 1144 kfree(adapter->vf_mac_list); 1145 adapter->vf_mac_list = NULL; 1146 kfree(adapter->vf_data); 1147 adapter->vf_data = NULL; 1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1149 wrfl(); 1150 msleep(100); 1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1152 } 1153 #endif 1154 adapter->vfs_allocated_count = 0; 1155 adapter->rss_queues = 1; 1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1157 adapter->num_rx_queues = 1; 1158 adapter->num_tx_queues = 1; 1159 adapter->num_q_vectors = 1; 1160 if (!pci_enable_msi(adapter->pdev)) 1161 adapter->flags |= IGB_FLAG_HAS_MSI; 1162 } 1163 1164 static void igb_add_ring(struct igb_ring *ring, 1165 struct igb_ring_container *head) 1166 { 1167 head->ring = ring; 1168 head->count++; 1169 } 1170 1171 /** 1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1173 * @adapter: board private structure to initialize 1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1175 * @v_idx: index of vector in adapter struct 1176 * @txr_count: total number of Tx rings to allocate 1177 * @txr_idx: index of first Tx ring to allocate 1178 * @rxr_count: total number of Rx rings to allocate 1179 * @rxr_idx: index of first Rx ring to allocate 1180 * 1181 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1182 **/ 1183 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1184 int v_count, int v_idx, 1185 int txr_count, int txr_idx, 1186 int rxr_count, int rxr_idx) 1187 { 1188 struct igb_q_vector *q_vector; 1189 struct igb_ring *ring; 1190 int ring_count; 1191 size_t size; 1192 1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1194 if (txr_count > 1 || rxr_count > 1) 1195 return -ENOMEM; 1196 1197 ring_count = txr_count + rxr_count; 1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1199 1200 /* allocate q_vector and rings */ 1201 q_vector = adapter->q_vector[v_idx]; 1202 if (!q_vector) { 1203 q_vector = kzalloc(size, GFP_KERNEL); 1204 } else if (size > ksize(q_vector)) { 1205 struct igb_q_vector *new_q_vector; 1206 1207 new_q_vector = kzalloc(size, GFP_KERNEL); 1208 if (new_q_vector) 1209 kfree_rcu(q_vector, rcu); 1210 q_vector = new_q_vector; 1211 } else { 1212 memset(q_vector, 0, size); 1213 } 1214 if (!q_vector) 1215 return -ENOMEM; 1216 1217 /* initialize NAPI */ 1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1219 1220 /* tie q_vector and adapter together */ 1221 adapter->q_vector[v_idx] = q_vector; 1222 q_vector->adapter = adapter; 1223 1224 /* initialize work limits */ 1225 q_vector->tx.work_limit = adapter->tx_work_limit; 1226 1227 /* initialize ITR configuration */ 1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1229 q_vector->itr_val = IGB_START_ITR; 1230 1231 /* initialize pointer to rings */ 1232 ring = q_vector->ring; 1233 1234 /* intialize ITR */ 1235 if (rxr_count) { 1236 /* rx or rx/tx vector */ 1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1238 q_vector->itr_val = adapter->rx_itr_setting; 1239 } else { 1240 /* tx only vector */ 1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1242 q_vector->itr_val = adapter->tx_itr_setting; 1243 } 1244 1245 if (txr_count) { 1246 /* assign generic ring traits */ 1247 ring->dev = &adapter->pdev->dev; 1248 ring->netdev = adapter->netdev; 1249 1250 /* configure backlink on ring */ 1251 ring->q_vector = q_vector; 1252 1253 /* update q_vector Tx values */ 1254 igb_add_ring(ring, &q_vector->tx); 1255 1256 /* For 82575, context index must be unique per ring. */ 1257 if (adapter->hw.mac.type == e1000_82575) 1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1259 1260 /* apply Tx specific ring traits */ 1261 ring->count = adapter->tx_ring_count; 1262 ring->queue_index = txr_idx; 1263 1264 ring->cbs_enable = false; 1265 ring->idleslope = 0; 1266 ring->sendslope = 0; 1267 ring->hicredit = 0; 1268 ring->locredit = 0; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* On i350, i354, i210, and i211, loopback VLAN packets 1296 * have the tag byte-swapped. 1297 */ 1298 if (adapter->hw.mac.type >= e1000_i350) 1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1300 1301 /* apply Rx specific ring traits */ 1302 ring->count = adapter->rx_ring_count; 1303 ring->queue_index = rxr_idx; 1304 1305 u64_stats_init(&ring->rx_syncp); 1306 1307 /* assign ring to adapter */ 1308 adapter->rx_ring[rxr_idx] = ring; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 /** 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1317 * @adapter: board private structure to initialize 1318 * 1319 * We allocate one q_vector per queue interrupt. If allocation fails we 1320 * return -ENOMEM. 1321 **/ 1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1323 { 1324 int q_vectors = adapter->num_q_vectors; 1325 int rxr_remaining = adapter->num_rx_queues; 1326 int txr_remaining = adapter->num_tx_queues; 1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1328 int err; 1329 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1331 for (; rxr_remaining; v_idx++) { 1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1333 0, 0, 1, rxr_idx); 1334 1335 if (err) 1336 goto err_out; 1337 1338 /* update counts and index */ 1339 rxr_remaining--; 1340 rxr_idx++; 1341 } 1342 } 1343 1344 for (; v_idx < q_vectors; v_idx++) { 1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1347 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363 err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372 } 1373 1374 /** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382 { 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398 err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401 } 1402 1403 /** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410 static int igb_request_irq(struct igb_adapter *adapter) 1411 { 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454 request_done: 1455 return err; 1456 } 1457 1458 static void igb_free_irq(struct igb_adapter *adapter) 1459 { 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471 } 1472 1473 /** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477 static void igb_irq_disable(struct igb_adapter *adapter) 1478 { 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1489 wr32(E1000_EIMC, adapter->eims_enable_mask); 1490 regval = rd32(E1000_EIAC); 1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1492 } 1493 1494 wr32(E1000_IAM, 0); 1495 wr32(E1000_IMC, ~0); 1496 wrfl(); 1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1498 int i; 1499 1500 for (i = 0; i < adapter->num_q_vectors; i++) 1501 synchronize_irq(adapter->msix_entries[i].vector); 1502 } else { 1503 synchronize_irq(adapter->pdev->irq); 1504 } 1505 } 1506 1507 /** 1508 * igb_irq_enable - Enable default interrupt generation settings 1509 * @adapter: board private structure 1510 **/ 1511 static void igb_irq_enable(struct igb_adapter *adapter) 1512 { 1513 struct e1000_hw *hw = &adapter->hw; 1514 1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1517 u32 regval = rd32(E1000_EIAC); 1518 1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1520 regval = rd32(E1000_EIAM); 1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1522 wr32(E1000_EIMS, adapter->eims_enable_mask); 1523 if (adapter->vfs_allocated_count) { 1524 wr32(E1000_MBVFIMR, 0xFF); 1525 ims |= E1000_IMS_VMMB; 1526 } 1527 wr32(E1000_IMS, ims); 1528 } else { 1529 wr32(E1000_IMS, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 wr32(E1000_IAM, IMS_ENABLE_MASK | 1532 E1000_IMS_DRSTA); 1533 } 1534 } 1535 1536 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1537 { 1538 struct e1000_hw *hw = &adapter->hw; 1539 u16 pf_id = adapter->vfs_allocated_count; 1540 u16 vid = adapter->hw.mng_cookie.vlan_id; 1541 u16 old_vid = adapter->mng_vlan_id; 1542 1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1544 /* add VID to filter table */ 1545 igb_vfta_set(hw, vid, pf_id, true, true); 1546 adapter->mng_vlan_id = vid; 1547 } else { 1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1549 } 1550 1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1552 (vid != old_vid) && 1553 !test_bit(old_vid, adapter->active_vlans)) { 1554 /* remove VID from filter table */ 1555 igb_vfta_set(hw, vid, pf_id, false, true); 1556 } 1557 } 1558 1559 /** 1560 * igb_release_hw_control - release control of the h/w to f/w 1561 * @adapter: address of board private structure 1562 * 1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1564 * For ASF and Pass Through versions of f/w this means that the 1565 * driver is no longer loaded. 1566 **/ 1567 static void igb_release_hw_control(struct igb_adapter *adapter) 1568 { 1569 struct e1000_hw *hw = &adapter->hw; 1570 u32 ctrl_ext; 1571 1572 /* Let firmware take over control of h/w */ 1573 ctrl_ext = rd32(E1000_CTRL_EXT); 1574 wr32(E1000_CTRL_EXT, 1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1576 } 1577 1578 /** 1579 * igb_get_hw_control - get control of the h/w from f/w 1580 * @adapter: address of board private structure 1581 * 1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1583 * For ASF and Pass Through versions of f/w this means that 1584 * the driver is loaded. 1585 **/ 1586 static void igb_get_hw_control(struct igb_adapter *adapter) 1587 { 1588 struct e1000_hw *hw = &adapter->hw; 1589 u32 ctrl_ext; 1590 1591 /* Let firmware know the driver has taken over */ 1592 ctrl_ext = rd32(E1000_CTRL_EXT); 1593 wr32(E1000_CTRL_EXT, 1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1595 } 1596 1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1598 { 1599 struct net_device *netdev = adapter->netdev; 1600 struct e1000_hw *hw = &adapter->hw; 1601 1602 WARN_ON(hw->mac.type != e1000_i210); 1603 1604 if (enable) 1605 adapter->flags |= IGB_FLAG_FQTSS; 1606 else 1607 adapter->flags &= ~IGB_FLAG_FQTSS; 1608 1609 if (netif_running(netdev)) 1610 schedule_work(&adapter->reset_task); 1611 } 1612 1613 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1614 { 1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1616 } 1617 1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1619 enum tx_queue_prio prio) 1620 { 1621 u32 val; 1622 1623 WARN_ON(hw->mac.type != e1000_i210); 1624 WARN_ON(queue < 0 || queue > 4); 1625 1626 val = rd32(E1000_I210_TXDCTL(queue)); 1627 1628 if (prio == TX_QUEUE_PRIO_HIGH) 1629 val |= E1000_TXDCTL_PRIORITY; 1630 else 1631 val &= ~E1000_TXDCTL_PRIORITY; 1632 1633 wr32(E1000_I210_TXDCTL(queue), val); 1634 } 1635 1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1637 { 1638 u32 val; 1639 1640 WARN_ON(hw->mac.type != e1000_i210); 1641 WARN_ON(queue < 0 || queue > 1); 1642 1643 val = rd32(E1000_I210_TQAVCC(queue)); 1644 1645 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1646 val |= E1000_TQAVCC_QUEUEMODE; 1647 else 1648 val &= ~E1000_TQAVCC_QUEUEMODE; 1649 1650 wr32(E1000_I210_TQAVCC(queue), val); 1651 } 1652 1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1654 { 1655 int i; 1656 1657 for (i = 0; i < adapter->num_tx_queues; i++) { 1658 if (adapter->tx_ring[i]->cbs_enable) 1659 return true; 1660 } 1661 1662 return false; 1663 } 1664 1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1666 { 1667 int i; 1668 1669 for (i = 0; i < adapter->num_tx_queues; i++) { 1670 if (adapter->tx_ring[i]->launchtime_enable) 1671 return true; 1672 } 1673 1674 return false; 1675 } 1676 1677 /** 1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * 1682 * Configure CBS and Launchtime for a given hardware queue. 1683 * Parameters are retrieved from the correct Tx ring, so 1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1685 * for setting those correctly prior to this function being called. 1686 **/ 1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1688 { 1689 struct net_device *netdev = adapter->netdev; 1690 struct e1000_hw *hw = &adapter->hw; 1691 struct igb_ring *ring; 1692 u32 tqavcc, tqavctrl; 1693 u16 value; 1694 1695 WARN_ON(hw->mac.type != e1000_i210); 1696 WARN_ON(queue < 0 || queue > 1); 1697 ring = adapter->tx_ring[queue]; 1698 1699 /* If any of the Qav features is enabled, configure queues as SR and 1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1701 * as SP. 1702 */ 1703 if (ring->cbs_enable || ring->launchtime_enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 } else { 1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1709 } 1710 1711 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1712 if (ring->cbs_enable || queue == 0) { 1713 /* i210 does not allow the queue 0 to be in the Strict 1714 * Priority mode while the Qav mode is enabled, so, 1715 * instead of disabling strict priority mode, we give 1716 * queue 0 the maximum of credits possible. 1717 * 1718 * See section 8.12.19 of the i210 datasheet, "Note: 1719 * Queue0 QueueMode must be set to 1b when 1720 * TransmitMode is set to Qav." 1721 */ 1722 if (queue == 0 && !ring->cbs_enable) { 1723 /* max "linkspeed" idleslope in kbps */ 1724 ring->idleslope = 1000000; 1725 ring->hicredit = ETH_FRAME_LEN; 1726 } 1727 1728 /* Always set data transfer arbitration to credit-based 1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1730 * the queues. 1731 */ 1732 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1735 1736 /* According to i210 datasheet section 7.2.7.7, we should set 1737 * the 'idleSlope' field from TQAVCC register following the 1738 * equation: 1739 * 1740 * For 100 Mbps link speed: 1741 * 1742 * value = BW * 0x7735 * 0.2 (E1) 1743 * 1744 * For 1000Mbps link speed: 1745 * 1746 * value = BW * 0x7735 * 2 (E2) 1747 * 1748 * E1 and E2 can be merged into one equation as shown below. 1749 * Note that 'link-speed' is in Mbps. 1750 * 1751 * value = BW * 0x7735 * 2 * link-speed 1752 * -------------- (E3) 1753 * 1000 1754 * 1755 * 'BW' is the percentage bandwidth out of full link speed 1756 * which can be found with the following equation. Note that 1757 * idleSlope here is the parameter from this function which 1758 * is in kbps. 1759 * 1760 * BW = idleSlope 1761 * ----------------- (E4) 1762 * link-speed * 1000 1763 * 1764 * That said, we can come up with a generic equation to 1765 * calculate the value we should set it TQAVCC register by 1766 * replacing 'BW' in E3 by E4. The resulting equation is: 1767 * 1768 * value = idleSlope * 0x7735 * 2 * link-speed 1769 * ----------------- -------------- (E5) 1770 * link-speed * 1000 1000 1771 * 1772 * 'link-speed' is present in both sides of the fraction so 1773 * it is canceled out. The final equation is the following: 1774 * 1775 * value = idleSlope * 61034 1776 * ----------------- (E6) 1777 * 1000000 1778 * 1779 * NOTE: For i210, given the above, we can see that idleslope 1780 * is represented in 16.38431 kbps units by the value at 1781 * the TQAVCC register (1Gbps / 61034), which reduces 1782 * the granularity for idleslope increments. 1783 * For instance, if you want to configure a 2576kbps 1784 * idleslope, the value to be written on the register 1785 * would have to be 157.23. If rounded down, you end 1786 * up with less bandwidth available than originally 1787 * required (~2572 kbps). If rounded up, you end up 1788 * with a higher bandwidth (~2589 kbps). Below the 1789 * approach we take is to always round up the 1790 * calculated value, so the resulting bandwidth might 1791 * be slightly higher for some configurations. 1792 */ 1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1794 1795 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1797 tqavcc |= value; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 wr32(E1000_I210_TQAVHC(queue), 1801 0x80000000 + ring->hicredit * 0x7735); 1802 } else { 1803 1804 /* Set idleSlope to zero. */ 1805 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1808 1809 /* Set hiCredit to zero. */ 1810 wr32(E1000_I210_TQAVHC(queue), 0); 1811 1812 /* If CBS is not enabled for any queues anymore, then return to 1813 * the default state of Data Transmission Arbitration on 1814 * TQAVCTRL. 1815 */ 1816 if (!is_any_cbs_enabled(adapter)) { 1817 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1820 } 1821 } 1822 1823 /* If LaunchTime is enabled, set DataTranTIM. */ 1824 if (ring->launchtime_enable) { 1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1826 * for any of the SR queues, and configure fetchtime delta. 1827 * XXX NOTE: 1828 * - LaunchTime will be enabled for all SR queues. 1829 * - A fixed offset can be added relative to the launch 1830 * time of all packets if configured at reg LAUNCH_OS0. 1831 * We are keeping it as 0 for now (default value). 1832 */ 1833 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1835 E1000_TQAVCTRL_FETCHTIME_DELTA; 1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1837 } else { 1838 /* If Launchtime is not enabled for any SR queues anymore, 1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1840 * effectively disabling Launchtime. 1841 */ 1842 if (!is_any_txtime_enabled(adapter)) { 1843 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1847 } 1848 } 1849 1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1851 * CBS are not configurable by software so we don't do any 'controller 1852 * configuration' in respect to these parameters. 1853 */ 1854 1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1856 ring->cbs_enable ? "enabled" : "disabled", 1857 ring->launchtime_enable ? "enabled" : "disabled", 1858 queue, 1859 ring->idleslope, ring->sendslope, 1860 ring->hicredit, ring->locredit); 1861 } 1862 1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1864 bool enable) 1865 { 1866 struct igb_ring *ring; 1867 1868 if (queue < 0 || queue > adapter->num_tx_queues) 1869 return -EINVAL; 1870 1871 ring = adapter->tx_ring[queue]; 1872 ring->launchtime_enable = enable; 1873 1874 return 0; 1875 } 1876 1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1878 bool enable, int idleslope, int sendslope, 1879 int hicredit, int locredit) 1880 { 1881 struct igb_ring *ring; 1882 1883 if (queue < 0 || queue > adapter->num_tx_queues) 1884 return -EINVAL; 1885 1886 ring = adapter->tx_ring[queue]; 1887 1888 ring->cbs_enable = enable; 1889 ring->idleslope = idleslope; 1890 ring->sendslope = sendslope; 1891 ring->hicredit = hicredit; 1892 ring->locredit = locredit; 1893 1894 return 0; 1895 } 1896 1897 /** 1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1899 * @adapter: pointer to adapter struct 1900 * 1901 * Configure TQAVCTRL register switching the controller's Tx mode 1902 * if FQTSS mode is enabled or disabled. Additionally, will issue 1903 * a call to igb_config_tx_modes() per queue so any previously saved 1904 * Tx parameters are applied. 1905 **/ 1906 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1907 { 1908 struct net_device *netdev = adapter->netdev; 1909 struct e1000_hw *hw = &adapter->hw; 1910 u32 val; 1911 1912 /* Only i210 controller supports changing the transmission mode. */ 1913 if (hw->mac.type != e1000_i210) 1914 return; 1915 1916 if (is_fqtss_enabled(adapter)) { 1917 int i, max_queue; 1918 1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1921 * so SP queues wait for SR ones. 1922 */ 1923 val = rd32(E1000_I210_TQAVCTRL); 1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1926 wr32(E1000_I210_TQAVCTRL, val); 1927 1928 /* Configure Tx and Rx packet buffers sizes as described in 1929 * i210 datasheet section 7.2.7.7. 1930 */ 1931 val = rd32(E1000_TXPBS); 1932 val &= ~I210_TXPBSIZE_MASK; 1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1935 wr32(E1000_TXPBS, val); 1936 1937 val = rd32(E1000_RXPBS); 1938 val &= ~I210_RXPBSIZE_MASK; 1939 val |= I210_RXPBSIZE_PB_30KB; 1940 wr32(E1000_RXPBS, val); 1941 1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1943 * register should not exceed the buffer size programmed in 1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1945 * so according to the datasheet we should set MAX_TPKT_SIZE to 1946 * 4kB / 64. 1947 * 1948 * However, when we do so, no frame from queue 2 and 3 are 1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1950 * or _equal_ to the buffer size programmed in TXPBS. For this 1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1952 */ 1953 val = (4096 - 1) / 64; 1954 wr32(E1000_I210_DTXMXPKTSZ, val); 1955 1956 /* Since FQTSS mode is enabled, apply any CBS configuration 1957 * previously set. If no previous CBS configuration has been 1958 * done, then the initial configuration is applied, which means 1959 * CBS is disabled. 1960 */ 1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1963 1964 for (i = 0; i < max_queue; i++) { 1965 igb_config_tx_modes(adapter, i); 1966 } 1967 } else { 1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1971 1972 val = rd32(E1000_I210_TQAVCTRL); 1973 /* According to Section 8.12.21, the other flags we've set when 1974 * enabling FQTSS are not relevant when disabling FQTSS so we 1975 * don't set they here. 1976 */ 1977 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1978 wr32(E1000_I210_TQAVCTRL, val); 1979 } 1980 1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1982 "enabled" : "disabled"); 1983 } 1984 1985 /** 1986 * igb_configure - configure the hardware for RX and TX 1987 * @adapter: private board structure 1988 **/ 1989 static void igb_configure(struct igb_adapter *adapter) 1990 { 1991 struct net_device *netdev = adapter->netdev; 1992 int i; 1993 1994 igb_get_hw_control(adapter); 1995 igb_set_rx_mode(netdev); 1996 igb_setup_tx_mode(adapter); 1997 1998 igb_restore_vlan(adapter); 1999 2000 igb_setup_tctl(adapter); 2001 igb_setup_mrqc(adapter); 2002 igb_setup_rctl(adapter); 2003 2004 igb_nfc_filter_restore(adapter); 2005 igb_configure_tx(adapter); 2006 igb_configure_rx(adapter); 2007 2008 igb_rx_fifo_flush_82575(&adapter->hw); 2009 2010 /* call igb_desc_unused which always leaves 2011 * at least 1 descriptor unused to make sure 2012 * next_to_use != next_to_clean 2013 */ 2014 for (i = 0; i < adapter->num_rx_queues; i++) { 2015 struct igb_ring *ring = adapter->rx_ring[i]; 2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2017 } 2018 } 2019 2020 /** 2021 * igb_power_up_link - Power up the phy/serdes link 2022 * @adapter: address of board private structure 2023 **/ 2024 void igb_power_up_link(struct igb_adapter *adapter) 2025 { 2026 igb_reset_phy(&adapter->hw); 2027 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_up_phy_copper(&adapter->hw); 2030 else 2031 igb_power_up_serdes_link_82575(&adapter->hw); 2032 2033 igb_setup_link(&adapter->hw); 2034 } 2035 2036 /** 2037 * igb_power_down_link - Power down the phy/serdes link 2038 * @adapter: address of board private structure 2039 */ 2040 static void igb_power_down_link(struct igb_adapter *adapter) 2041 { 2042 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2043 igb_power_down_phy_copper_82575(&adapter->hw); 2044 else 2045 igb_shutdown_serdes_link_82575(&adapter->hw); 2046 } 2047 2048 /** 2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2050 * @adapter: address of the board private structure 2051 **/ 2052 static void igb_check_swap_media(struct igb_adapter *adapter) 2053 { 2054 struct e1000_hw *hw = &adapter->hw; 2055 u32 ctrl_ext, connsw; 2056 bool swap_now = false; 2057 2058 ctrl_ext = rd32(E1000_CTRL_EXT); 2059 connsw = rd32(E1000_CONNSW); 2060 2061 /* need to live swap if current media is copper and we have fiber/serdes 2062 * to go to. 2063 */ 2064 2065 if ((hw->phy.media_type == e1000_media_type_copper) && 2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2067 swap_now = true; 2068 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2069 !(connsw & E1000_CONNSW_SERDESD)) { 2070 /* copper signal takes time to appear */ 2071 if (adapter->copper_tries < 4) { 2072 adapter->copper_tries++; 2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2074 wr32(E1000_CONNSW, connsw); 2075 return; 2076 } else { 2077 adapter->copper_tries = 0; 2078 if ((connsw & E1000_CONNSW_PHYSD) && 2079 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2080 swap_now = true; 2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2082 wr32(E1000_CONNSW, connsw); 2083 } 2084 } 2085 } 2086 2087 if (!swap_now) 2088 return; 2089 2090 switch (hw->phy.media_type) { 2091 case e1000_media_type_copper: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to fiber/serdes\n"); 2094 ctrl_ext |= 2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 adapter->copper_tries = 0; 2098 break; 2099 case e1000_media_type_internal_serdes: 2100 case e1000_media_type_fiber: 2101 netdev_info(adapter->netdev, 2102 "MAS: changing media to copper\n"); 2103 ctrl_ext &= 2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2105 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2106 break; 2107 default: 2108 /* shouldn't get here during regular operation */ 2109 netdev_err(adapter->netdev, 2110 "AMS: Invalid media type found, returning\n"); 2111 break; 2112 } 2113 wr32(E1000_CTRL_EXT, ctrl_ext); 2114 } 2115 2116 /** 2117 * igb_up - Open the interface and prepare it to handle traffic 2118 * @adapter: board private structure 2119 **/ 2120 int igb_up(struct igb_adapter *adapter) 2121 { 2122 struct e1000_hw *hw = &adapter->hw; 2123 int i; 2124 2125 /* hardware has been reset, we need to reload some things */ 2126 igb_configure(adapter); 2127 2128 clear_bit(__IGB_DOWN, &adapter->state); 2129 2130 for (i = 0; i < adapter->num_q_vectors; i++) 2131 napi_enable(&(adapter->q_vector[i]->napi)); 2132 2133 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2134 igb_configure_msix(adapter); 2135 else 2136 igb_assign_vector(adapter->q_vector[0], 0); 2137 2138 /* Clear any pending interrupts. */ 2139 rd32(E1000_TSICR); 2140 rd32(E1000_ICR); 2141 igb_irq_enable(adapter); 2142 2143 /* notify VFs that reset has been completed */ 2144 if (adapter->vfs_allocated_count) { 2145 u32 reg_data = rd32(E1000_CTRL_EXT); 2146 2147 reg_data |= E1000_CTRL_EXT_PFRSTD; 2148 wr32(E1000_CTRL_EXT, reg_data); 2149 } 2150 2151 netif_tx_start_all_queues(adapter->netdev); 2152 2153 /* start the watchdog. */ 2154 hw->mac.get_link_status = 1; 2155 schedule_work(&adapter->watchdog_task); 2156 2157 if ((adapter->flags & IGB_FLAG_EEE) && 2158 (!hw->dev_spec._82575.eee_disable)) 2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2160 2161 return 0; 2162 } 2163 2164 void igb_down(struct igb_adapter *adapter) 2165 { 2166 struct net_device *netdev = adapter->netdev; 2167 struct e1000_hw *hw = &adapter->hw; 2168 u32 tctl, rctl; 2169 int i; 2170 2171 /* signal that we're down so the interrupt handler does not 2172 * reschedule our watchdog timer 2173 */ 2174 set_bit(__IGB_DOWN, &adapter->state); 2175 2176 /* disable receives in the hardware */ 2177 rctl = rd32(E1000_RCTL); 2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2179 /* flush and sleep below */ 2180 2181 igb_nfc_filter_exit(adapter); 2182 2183 netif_carrier_off(netdev); 2184 netif_tx_stop_all_queues(netdev); 2185 2186 /* disable transmits in the hardware */ 2187 tctl = rd32(E1000_TCTL); 2188 tctl &= ~E1000_TCTL_EN; 2189 wr32(E1000_TCTL, tctl); 2190 /* flush both disables and wait for them to finish */ 2191 wrfl(); 2192 usleep_range(10000, 11000); 2193 2194 igb_irq_disable(adapter); 2195 2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2197 2198 for (i = 0; i < adapter->num_q_vectors; i++) { 2199 if (adapter->q_vector[i]) { 2200 napi_synchronize(&adapter->q_vector[i]->napi); 2201 napi_disable(&adapter->q_vector[i]->napi); 2202 } 2203 } 2204 2205 del_timer_sync(&adapter->watchdog_timer); 2206 del_timer_sync(&adapter->phy_info_timer); 2207 2208 /* record the stats before reset*/ 2209 spin_lock(&adapter->stats64_lock); 2210 igb_update_stats(adapter); 2211 spin_unlock(&adapter->stats64_lock); 2212 2213 adapter->link_speed = 0; 2214 adapter->link_duplex = 0; 2215 2216 if (!pci_channel_offline(adapter->pdev)) 2217 igb_reset(adapter); 2218 2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2221 2222 igb_clean_all_tx_rings(adapter); 2223 igb_clean_all_rx_rings(adapter); 2224 #ifdef CONFIG_IGB_DCA 2225 2226 /* since we reset the hardware DCA settings were cleared */ 2227 igb_setup_dca(adapter); 2228 #endif 2229 } 2230 2231 void igb_reinit_locked(struct igb_adapter *adapter) 2232 { 2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2234 usleep_range(1000, 2000); 2235 igb_down(adapter); 2236 igb_up(adapter); 2237 clear_bit(__IGB_RESETTING, &adapter->state); 2238 } 2239 2240 /** igb_enable_mas - Media Autosense re-enable after swap 2241 * 2242 * @adapter: adapter struct 2243 **/ 2244 static void igb_enable_mas(struct igb_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 connsw = rd32(E1000_CONNSW); 2248 2249 /* configure for SerDes media detect */ 2250 if ((hw->phy.media_type == e1000_media_type_copper) && 2251 (!(connsw & E1000_CONNSW_SERDESD))) { 2252 connsw |= E1000_CONNSW_ENRGSRC; 2253 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2254 wr32(E1000_CONNSW, connsw); 2255 wrfl(); 2256 } 2257 } 2258 2259 #ifdef CONFIG_IGB_HWMON 2260 /** 2261 * igb_set_i2c_bb - Init I2C interface 2262 * @hw: pointer to hardware structure 2263 **/ 2264 static void igb_set_i2c_bb(struct e1000_hw *hw) 2265 { 2266 u32 ctrl_ext; 2267 s32 i2cctl; 2268 2269 ctrl_ext = rd32(E1000_CTRL_EXT); 2270 ctrl_ext |= E1000_CTRL_I2C_ENA; 2271 wr32(E1000_CTRL_EXT, ctrl_ext); 2272 wrfl(); 2273 2274 i2cctl = rd32(E1000_I2CPARAMS); 2275 i2cctl |= E1000_I2CBB_EN 2276 | E1000_I2C_CLK_OE_N 2277 | E1000_I2C_DATA_OE_N; 2278 wr32(E1000_I2CPARAMS, i2cctl); 2279 wrfl(); 2280 } 2281 #endif 2282 2283 void igb_reset(struct igb_adapter *adapter) 2284 { 2285 struct pci_dev *pdev = adapter->pdev; 2286 struct e1000_hw *hw = &adapter->hw; 2287 struct e1000_mac_info *mac = &hw->mac; 2288 struct e1000_fc_info *fc = &hw->fc; 2289 u32 pba, hwm; 2290 2291 /* Repartition Pba for greater than 9k mtu 2292 * To take effect CTRL.RST is required. 2293 */ 2294 switch (mac->type) { 2295 case e1000_i350: 2296 case e1000_i354: 2297 case e1000_82580: 2298 pba = rd32(E1000_RXPBS); 2299 pba = igb_rxpbs_adjust_82580(pba); 2300 break; 2301 case e1000_82576: 2302 pba = rd32(E1000_RXPBS); 2303 pba &= E1000_RXPBS_SIZE_MASK_82576; 2304 break; 2305 case e1000_82575: 2306 case e1000_i210: 2307 case e1000_i211: 2308 default: 2309 pba = E1000_PBA_34K; 2310 break; 2311 } 2312 2313 if (mac->type == e1000_82575) { 2314 u32 min_rx_space, min_tx_space, needed_tx_space; 2315 2316 /* write Rx PBA so that hardware can report correct Tx PBA */ 2317 wr32(E1000_PBA, pba); 2318 2319 /* To maintain wire speed transmits, the Tx FIFO should be 2320 * large enough to accommodate two full transmit packets, 2321 * rounded up to the next 1KB and expressed in KB. Likewise, 2322 * the Rx FIFO should be large enough to accommodate at least 2323 * one full receive packet and is similarly rounded up and 2324 * expressed in KB. 2325 */ 2326 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2327 2328 /* The Tx FIFO also stores 16 bytes of information about the Tx 2329 * but don't include Ethernet FCS because hardware appends it. 2330 * We only need to round down to the nearest 512 byte block 2331 * count since the value we care about is 2 frames, not 1. 2332 */ 2333 min_tx_space = adapter->max_frame_size; 2334 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2335 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2336 2337 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2338 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2339 2340 /* If current Tx allocation is less than the min Tx FIFO size, 2341 * and the min Tx FIFO size is less than the current Rx FIFO 2342 * allocation, take space away from current Rx allocation. 2343 */ 2344 if (needed_tx_space < pba) { 2345 pba -= needed_tx_space; 2346 2347 /* if short on Rx space, Rx wins and must trump Tx 2348 * adjustment 2349 */ 2350 if (pba < min_rx_space) 2351 pba = min_rx_space; 2352 } 2353 2354 /* adjust PBA for jumbo frames */ 2355 wr32(E1000_PBA, pba); 2356 } 2357 2358 /* flow control settings 2359 * The high water mark must be low enough to fit one full frame 2360 * after transmitting the pause frame. As such we must have enough 2361 * space to allow for us to complete our current transmit and then 2362 * receive the frame that is in progress from the link partner. 2363 * Set it to: 2364 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2365 */ 2366 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2367 2368 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2369 fc->low_water = fc->high_water - 16; 2370 fc->pause_time = 0xFFFF; 2371 fc->send_xon = 1; 2372 fc->current_mode = fc->requested_mode; 2373 2374 /* disable receive for all VFs and wait one second */ 2375 if (adapter->vfs_allocated_count) { 2376 int i; 2377 2378 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2379 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2380 2381 /* ping all the active vfs to let them know we are going down */ 2382 igb_ping_all_vfs(adapter); 2383 2384 /* disable transmits and receives */ 2385 wr32(E1000_VFRE, 0); 2386 wr32(E1000_VFTE, 0); 2387 } 2388 2389 /* Allow time for pending master requests to run */ 2390 hw->mac.ops.reset_hw(hw); 2391 wr32(E1000_WUC, 0); 2392 2393 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2394 /* need to resetup here after media swap */ 2395 adapter->ei.get_invariants(hw); 2396 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2397 } 2398 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2399 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2400 igb_enable_mas(adapter); 2401 } 2402 if (hw->mac.ops.init_hw(hw)) 2403 dev_err(&pdev->dev, "Hardware Error\n"); 2404 2405 /* RAR registers were cleared during init_hw, clear mac table */ 2406 igb_flush_mac_table(adapter); 2407 __dev_uc_unsync(adapter->netdev, NULL); 2408 2409 /* Recover default RAR entry */ 2410 igb_set_default_mac_filter(adapter); 2411 2412 /* Flow control settings reset on hardware reset, so guarantee flow 2413 * control is off when forcing speed. 2414 */ 2415 if (!hw->mac.autoneg) 2416 igb_force_mac_fc(hw); 2417 2418 igb_init_dmac(adapter, pba); 2419 #ifdef CONFIG_IGB_HWMON 2420 /* Re-initialize the thermal sensor on i350 devices. */ 2421 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2422 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2423 /* If present, re-initialize the external thermal sensor 2424 * interface. 2425 */ 2426 if (adapter->ets) 2427 igb_set_i2c_bb(hw); 2428 mac->ops.init_thermal_sensor_thresh(hw); 2429 } 2430 } 2431 #endif 2432 /* Re-establish EEE setting */ 2433 if (hw->phy.media_type == e1000_media_type_copper) { 2434 switch (mac->type) { 2435 case e1000_i350: 2436 case e1000_i210: 2437 case e1000_i211: 2438 igb_set_eee_i350(hw, true, true); 2439 break; 2440 case e1000_i354: 2441 igb_set_eee_i354(hw, true, true); 2442 break; 2443 default: 2444 break; 2445 } 2446 } 2447 if (!netif_running(adapter->netdev)) 2448 igb_power_down_link(adapter); 2449 2450 igb_update_mng_vlan(adapter); 2451 2452 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2453 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2454 2455 /* Re-enable PTP, where applicable. */ 2456 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2457 igb_ptp_reset(adapter); 2458 2459 igb_get_phy_info(hw); 2460 } 2461 2462 static netdev_features_t igb_fix_features(struct net_device *netdev, 2463 netdev_features_t features) 2464 { 2465 /* Since there is no support for separate Rx/Tx vlan accel 2466 * enable/disable make sure Tx flag is always in same state as Rx. 2467 */ 2468 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2469 features |= NETIF_F_HW_VLAN_CTAG_TX; 2470 else 2471 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2472 2473 return features; 2474 } 2475 2476 static int igb_set_features(struct net_device *netdev, 2477 netdev_features_t features) 2478 { 2479 netdev_features_t changed = netdev->features ^ features; 2480 struct igb_adapter *adapter = netdev_priv(netdev); 2481 2482 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2483 igb_vlan_mode(netdev, features); 2484 2485 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2486 return 0; 2487 2488 if (!(features & NETIF_F_NTUPLE)) { 2489 struct hlist_node *node2; 2490 struct igb_nfc_filter *rule; 2491 2492 spin_lock(&adapter->nfc_lock); 2493 hlist_for_each_entry_safe(rule, node2, 2494 &adapter->nfc_filter_list, nfc_node) { 2495 igb_erase_filter(adapter, rule); 2496 hlist_del(&rule->nfc_node); 2497 kfree(rule); 2498 } 2499 spin_unlock(&adapter->nfc_lock); 2500 adapter->nfc_filter_count = 0; 2501 } 2502 2503 netdev->features = features; 2504 2505 if (netif_running(netdev)) 2506 igb_reinit_locked(adapter); 2507 else 2508 igb_reset(adapter); 2509 2510 return 1; 2511 } 2512 2513 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2514 struct net_device *dev, 2515 const unsigned char *addr, u16 vid, 2516 u16 flags, 2517 struct netlink_ext_ack *extack) 2518 { 2519 /* guarantee we can provide a unique filter for the unicast address */ 2520 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2521 struct igb_adapter *adapter = netdev_priv(dev); 2522 int vfn = adapter->vfs_allocated_count; 2523 2524 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2525 return -ENOMEM; 2526 } 2527 2528 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2529 } 2530 2531 #define IGB_MAX_MAC_HDR_LEN 127 2532 #define IGB_MAX_NETWORK_HDR_LEN 511 2533 2534 static netdev_features_t 2535 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2536 netdev_features_t features) 2537 { 2538 unsigned int network_hdr_len, mac_hdr_len; 2539 2540 /* Make certain the headers can be described by a context descriptor */ 2541 mac_hdr_len = skb_network_header(skb) - skb->data; 2542 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2543 return features & ~(NETIF_F_HW_CSUM | 2544 NETIF_F_SCTP_CRC | 2545 NETIF_F_GSO_UDP_L4 | 2546 NETIF_F_HW_VLAN_CTAG_TX | 2547 NETIF_F_TSO | 2548 NETIF_F_TSO6); 2549 2550 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2551 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2552 return features & ~(NETIF_F_HW_CSUM | 2553 NETIF_F_SCTP_CRC | 2554 NETIF_F_GSO_UDP_L4 | 2555 NETIF_F_TSO | 2556 NETIF_F_TSO6); 2557 2558 /* We can only support IPV4 TSO in tunnels if we can mangle the 2559 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2560 */ 2561 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2562 features &= ~NETIF_F_TSO; 2563 2564 return features; 2565 } 2566 2567 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2568 { 2569 if (!is_fqtss_enabled(adapter)) { 2570 enable_fqtss(adapter, true); 2571 return; 2572 } 2573 2574 igb_config_tx_modes(adapter, queue); 2575 2576 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2577 enable_fqtss(adapter, false); 2578 } 2579 2580 static int igb_offload_cbs(struct igb_adapter *adapter, 2581 struct tc_cbs_qopt_offload *qopt) 2582 { 2583 struct e1000_hw *hw = &adapter->hw; 2584 int err; 2585 2586 /* CBS offloading is only supported by i210 controller. */ 2587 if (hw->mac.type != e1000_i210) 2588 return -EOPNOTSUPP; 2589 2590 /* CBS offloading is only supported by queue 0 and queue 1. */ 2591 if (qopt->queue < 0 || qopt->queue > 1) 2592 return -EINVAL; 2593 2594 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2595 qopt->idleslope, qopt->sendslope, 2596 qopt->hicredit, qopt->locredit); 2597 if (err) 2598 return err; 2599 2600 igb_offload_apply(adapter, qopt->queue); 2601 2602 return 0; 2603 } 2604 2605 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2606 #define VLAN_PRIO_FULL_MASK (0x07) 2607 2608 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2609 struct flow_cls_offload *f, 2610 int traffic_class, 2611 struct igb_nfc_filter *input) 2612 { 2613 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2614 struct flow_dissector *dissector = rule->match.dissector; 2615 struct netlink_ext_ack *extack = f->common.extack; 2616 2617 if (dissector->used_keys & 2618 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2619 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2620 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2621 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2622 NL_SET_ERR_MSG_MOD(extack, 2623 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2624 return -EOPNOTSUPP; 2625 } 2626 2627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2628 struct flow_match_eth_addrs match; 2629 2630 flow_rule_match_eth_addrs(rule, &match); 2631 if (!is_zero_ether_addr(match.mask->dst)) { 2632 if (!is_broadcast_ether_addr(match.mask->dst)) { 2633 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2634 return -EINVAL; 2635 } 2636 2637 input->filter.match_flags |= 2638 IGB_FILTER_FLAG_DST_MAC_ADDR; 2639 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2640 } 2641 2642 if (!is_zero_ether_addr(match.mask->src)) { 2643 if (!is_broadcast_ether_addr(match.mask->src)) { 2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2645 return -EINVAL; 2646 } 2647 2648 input->filter.match_flags |= 2649 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2650 ether_addr_copy(input->filter.src_addr, match.key->src); 2651 } 2652 } 2653 2654 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2655 struct flow_match_basic match; 2656 2657 flow_rule_match_basic(rule, &match); 2658 if (match.mask->n_proto) { 2659 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2660 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2661 return -EINVAL; 2662 } 2663 2664 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2665 input->filter.etype = match.key->n_proto; 2666 } 2667 } 2668 2669 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2670 struct flow_match_vlan match; 2671 2672 flow_rule_match_vlan(rule, &match); 2673 if (match.mask->vlan_priority) { 2674 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2675 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2676 return -EINVAL; 2677 } 2678 2679 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2680 input->filter.vlan_tci = 2681 (__force __be16)match.key->vlan_priority; 2682 } 2683 } 2684 2685 input->action = traffic_class; 2686 input->cookie = f->cookie; 2687 2688 return 0; 2689 } 2690 2691 static int igb_configure_clsflower(struct igb_adapter *adapter, 2692 struct flow_cls_offload *cls_flower) 2693 { 2694 struct netlink_ext_ack *extack = cls_flower->common.extack; 2695 struct igb_nfc_filter *filter, *f; 2696 int err, tc; 2697 2698 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2699 if (tc < 0) { 2700 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2701 return -EINVAL; 2702 } 2703 2704 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2705 if (!filter) 2706 return -ENOMEM; 2707 2708 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2709 if (err < 0) 2710 goto err_parse; 2711 2712 spin_lock(&adapter->nfc_lock); 2713 2714 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2715 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2716 err = -EEXIST; 2717 NL_SET_ERR_MSG_MOD(extack, 2718 "This filter is already set in ethtool"); 2719 goto err_locked; 2720 } 2721 } 2722 2723 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2724 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2725 err = -EEXIST; 2726 NL_SET_ERR_MSG_MOD(extack, 2727 "This filter is already set in cls_flower"); 2728 goto err_locked; 2729 } 2730 } 2731 2732 err = igb_add_filter(adapter, filter); 2733 if (err < 0) { 2734 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2735 goto err_locked; 2736 } 2737 2738 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2739 2740 spin_unlock(&adapter->nfc_lock); 2741 2742 return 0; 2743 2744 err_locked: 2745 spin_unlock(&adapter->nfc_lock); 2746 2747 err_parse: 2748 kfree(filter); 2749 2750 return err; 2751 } 2752 2753 static int igb_delete_clsflower(struct igb_adapter *adapter, 2754 struct flow_cls_offload *cls_flower) 2755 { 2756 struct igb_nfc_filter *filter; 2757 int err; 2758 2759 spin_lock(&adapter->nfc_lock); 2760 2761 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2762 if (filter->cookie == cls_flower->cookie) 2763 break; 2764 2765 if (!filter) { 2766 err = -ENOENT; 2767 goto out; 2768 } 2769 2770 err = igb_erase_filter(adapter, filter); 2771 if (err < 0) 2772 goto out; 2773 2774 hlist_del(&filter->nfc_node); 2775 kfree(filter); 2776 2777 out: 2778 spin_unlock(&adapter->nfc_lock); 2779 2780 return err; 2781 } 2782 2783 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2784 struct flow_cls_offload *cls_flower) 2785 { 2786 switch (cls_flower->command) { 2787 case FLOW_CLS_REPLACE: 2788 return igb_configure_clsflower(adapter, cls_flower); 2789 case FLOW_CLS_DESTROY: 2790 return igb_delete_clsflower(adapter, cls_flower); 2791 case FLOW_CLS_STATS: 2792 return -EOPNOTSUPP; 2793 default: 2794 return -EOPNOTSUPP; 2795 } 2796 } 2797 2798 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2799 void *cb_priv) 2800 { 2801 struct igb_adapter *adapter = cb_priv; 2802 2803 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2804 return -EOPNOTSUPP; 2805 2806 switch (type) { 2807 case TC_SETUP_CLSFLOWER: 2808 return igb_setup_tc_cls_flower(adapter, type_data); 2809 2810 default: 2811 return -EOPNOTSUPP; 2812 } 2813 } 2814 2815 static int igb_offload_txtime(struct igb_adapter *adapter, 2816 struct tc_etf_qopt_offload *qopt) 2817 { 2818 struct e1000_hw *hw = &adapter->hw; 2819 int err; 2820 2821 /* Launchtime offloading is only supported by i210 controller. */ 2822 if (hw->mac.type != e1000_i210) 2823 return -EOPNOTSUPP; 2824 2825 /* Launchtime offloading is only supported by queues 0 and 1. */ 2826 if (qopt->queue < 0 || qopt->queue > 1) 2827 return -EINVAL; 2828 2829 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2830 if (err) 2831 return err; 2832 2833 igb_offload_apply(adapter, qopt->queue); 2834 2835 return 0; 2836 } 2837 2838 static int igb_tc_query_caps(struct igb_adapter *adapter, 2839 struct tc_query_caps_base *base) 2840 { 2841 switch (base->type) { 2842 case TC_SETUP_QDISC_TAPRIO: { 2843 struct tc_taprio_caps *caps = base->caps; 2844 2845 caps->broken_mqprio = true; 2846 2847 return 0; 2848 } 2849 default: 2850 return -EOPNOTSUPP; 2851 } 2852 } 2853 2854 static LIST_HEAD(igb_block_cb_list); 2855 2856 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2857 void *type_data) 2858 { 2859 struct igb_adapter *adapter = netdev_priv(dev); 2860 2861 switch (type) { 2862 case TC_QUERY_CAPS: 2863 return igb_tc_query_caps(adapter, type_data); 2864 case TC_SETUP_QDISC_CBS: 2865 return igb_offload_cbs(adapter, type_data); 2866 case TC_SETUP_BLOCK: 2867 return flow_block_cb_setup_simple(type_data, 2868 &igb_block_cb_list, 2869 igb_setup_tc_block_cb, 2870 adapter, adapter, true); 2871 2872 case TC_SETUP_QDISC_ETF: 2873 return igb_offload_txtime(adapter, type_data); 2874 2875 default: 2876 return -EOPNOTSUPP; 2877 } 2878 } 2879 2880 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2881 { 2882 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2883 struct igb_adapter *adapter = netdev_priv(dev); 2884 struct bpf_prog *prog = bpf->prog, *old_prog; 2885 bool running = netif_running(dev); 2886 bool need_reset; 2887 2888 /* verify igb ring attributes are sufficient for XDP */ 2889 for (i = 0; i < adapter->num_rx_queues; i++) { 2890 struct igb_ring *ring = adapter->rx_ring[i]; 2891 2892 if (frame_size > igb_rx_bufsz(ring)) { 2893 NL_SET_ERR_MSG_MOD(bpf->extack, 2894 "The RX buffer size is too small for the frame size"); 2895 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2896 igb_rx_bufsz(ring), frame_size); 2897 return -EINVAL; 2898 } 2899 } 2900 2901 old_prog = xchg(&adapter->xdp_prog, prog); 2902 need_reset = (!!prog != !!old_prog); 2903 2904 /* device is up and bpf is added/removed, must setup the RX queues */ 2905 if (need_reset && running) { 2906 igb_close(dev); 2907 } else { 2908 for (i = 0; i < adapter->num_rx_queues; i++) 2909 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2910 adapter->xdp_prog); 2911 } 2912 2913 if (old_prog) 2914 bpf_prog_put(old_prog); 2915 2916 /* bpf is just replaced, RXQ and MTU are already setup */ 2917 if (!need_reset) { 2918 return 0; 2919 } else { 2920 if (prog) 2921 xdp_features_set_redirect_target(dev, true); 2922 else 2923 xdp_features_clear_redirect_target(dev); 2924 } 2925 2926 if (running) 2927 igb_open(dev); 2928 2929 return 0; 2930 } 2931 2932 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2933 { 2934 switch (xdp->command) { 2935 case XDP_SETUP_PROG: 2936 return igb_xdp_setup(dev, xdp); 2937 default: 2938 return -EINVAL; 2939 } 2940 } 2941 2942 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2943 { 2944 /* Force memory writes to complete before letting h/w know there 2945 * are new descriptors to fetch. 2946 */ 2947 wmb(); 2948 writel(ring->next_to_use, ring->tail); 2949 } 2950 2951 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2952 { 2953 unsigned int r_idx = smp_processor_id(); 2954 2955 if (r_idx >= adapter->num_tx_queues) 2956 r_idx = r_idx % adapter->num_tx_queues; 2957 2958 return adapter->tx_ring[r_idx]; 2959 } 2960 2961 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2962 { 2963 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2964 int cpu = smp_processor_id(); 2965 struct igb_ring *tx_ring; 2966 struct netdev_queue *nq; 2967 u32 ret; 2968 2969 if (unlikely(!xdpf)) 2970 return IGB_XDP_CONSUMED; 2971 2972 /* During program transitions its possible adapter->xdp_prog is assigned 2973 * but ring has not been configured yet. In this case simply abort xmit. 2974 */ 2975 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2976 if (unlikely(!tx_ring)) 2977 return IGB_XDP_CONSUMED; 2978 2979 nq = txring_txq(tx_ring); 2980 __netif_tx_lock(nq, cpu); 2981 /* Avoid transmit queue timeout since we share it with the slow path */ 2982 txq_trans_cond_update(nq); 2983 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2984 __netif_tx_unlock(nq); 2985 2986 return ret; 2987 } 2988 2989 static int igb_xdp_xmit(struct net_device *dev, int n, 2990 struct xdp_frame **frames, u32 flags) 2991 { 2992 struct igb_adapter *adapter = netdev_priv(dev); 2993 int cpu = smp_processor_id(); 2994 struct igb_ring *tx_ring; 2995 struct netdev_queue *nq; 2996 int nxmit = 0; 2997 int i; 2998 2999 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 3000 return -ENETDOWN; 3001 3002 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3003 return -EINVAL; 3004 3005 /* During program transitions its possible adapter->xdp_prog is assigned 3006 * but ring has not been configured yet. In this case simply abort xmit. 3007 */ 3008 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 3009 if (unlikely(!tx_ring)) 3010 return -ENXIO; 3011 3012 nq = txring_txq(tx_ring); 3013 __netif_tx_lock(nq, cpu); 3014 3015 /* Avoid transmit queue timeout since we share it with the slow path */ 3016 txq_trans_cond_update(nq); 3017 3018 for (i = 0; i < n; i++) { 3019 struct xdp_frame *xdpf = frames[i]; 3020 int err; 3021 3022 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3023 if (err != IGB_XDP_TX) 3024 break; 3025 nxmit++; 3026 } 3027 3028 __netif_tx_unlock(nq); 3029 3030 if (unlikely(flags & XDP_XMIT_FLUSH)) 3031 igb_xdp_ring_update_tail(tx_ring); 3032 3033 return nxmit; 3034 } 3035 3036 static const struct net_device_ops igb_netdev_ops = { 3037 .ndo_open = igb_open, 3038 .ndo_stop = igb_close, 3039 .ndo_start_xmit = igb_xmit_frame, 3040 .ndo_get_stats64 = igb_get_stats64, 3041 .ndo_set_rx_mode = igb_set_rx_mode, 3042 .ndo_set_mac_address = igb_set_mac, 3043 .ndo_change_mtu = igb_change_mtu, 3044 .ndo_eth_ioctl = igb_ioctl, 3045 .ndo_tx_timeout = igb_tx_timeout, 3046 .ndo_validate_addr = eth_validate_addr, 3047 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3048 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3049 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3050 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3051 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3052 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3053 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3054 .ndo_get_vf_config = igb_ndo_get_vf_config, 3055 .ndo_fix_features = igb_fix_features, 3056 .ndo_set_features = igb_set_features, 3057 .ndo_fdb_add = igb_ndo_fdb_add, 3058 .ndo_features_check = igb_features_check, 3059 .ndo_setup_tc = igb_setup_tc, 3060 .ndo_bpf = igb_xdp, 3061 .ndo_xdp_xmit = igb_xdp_xmit, 3062 }; 3063 3064 /** 3065 * igb_set_fw_version - Configure version string for ethtool 3066 * @adapter: adapter struct 3067 **/ 3068 void igb_set_fw_version(struct igb_adapter *adapter) 3069 { 3070 struct e1000_hw *hw = &adapter->hw; 3071 struct e1000_fw_version fw; 3072 3073 igb_get_fw_version(hw, &fw); 3074 3075 switch (hw->mac.type) { 3076 case e1000_i210: 3077 case e1000_i211: 3078 if (!(igb_get_flash_presence_i210(hw))) { 3079 snprintf(adapter->fw_version, 3080 sizeof(adapter->fw_version), 3081 "%2d.%2d-%d", 3082 fw.invm_major, fw.invm_minor, 3083 fw.invm_img_type); 3084 break; 3085 } 3086 fallthrough; 3087 default: 3088 /* if option is rom valid, display its version too */ 3089 if (fw.or_valid) { 3090 snprintf(adapter->fw_version, 3091 sizeof(adapter->fw_version), 3092 "%d.%d, 0x%08x, %d.%d.%d", 3093 fw.eep_major, fw.eep_minor, fw.etrack_id, 3094 fw.or_major, fw.or_build, fw.or_patch); 3095 /* no option rom */ 3096 } else if (fw.etrack_id != 0X0000) { 3097 snprintf(adapter->fw_version, 3098 sizeof(adapter->fw_version), 3099 "%d.%d, 0x%08x", 3100 fw.eep_major, fw.eep_minor, fw.etrack_id); 3101 } else { 3102 snprintf(adapter->fw_version, 3103 sizeof(adapter->fw_version), 3104 "%d.%d.%d", 3105 fw.eep_major, fw.eep_minor, fw.eep_build); 3106 } 3107 break; 3108 } 3109 } 3110 3111 /** 3112 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3113 * 3114 * @adapter: adapter struct 3115 **/ 3116 static void igb_init_mas(struct igb_adapter *adapter) 3117 { 3118 struct e1000_hw *hw = &adapter->hw; 3119 u16 eeprom_data; 3120 3121 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3122 switch (hw->bus.func) { 3123 case E1000_FUNC_0: 3124 if (eeprom_data & IGB_MAS_ENABLE_0) { 3125 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3126 netdev_info(adapter->netdev, 3127 "MAS: Enabling Media Autosense for port %d\n", 3128 hw->bus.func); 3129 } 3130 break; 3131 case E1000_FUNC_1: 3132 if (eeprom_data & IGB_MAS_ENABLE_1) { 3133 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3134 netdev_info(adapter->netdev, 3135 "MAS: Enabling Media Autosense for port %d\n", 3136 hw->bus.func); 3137 } 3138 break; 3139 case E1000_FUNC_2: 3140 if (eeprom_data & IGB_MAS_ENABLE_2) { 3141 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3142 netdev_info(adapter->netdev, 3143 "MAS: Enabling Media Autosense for port %d\n", 3144 hw->bus.func); 3145 } 3146 break; 3147 case E1000_FUNC_3: 3148 if (eeprom_data & IGB_MAS_ENABLE_3) { 3149 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3150 netdev_info(adapter->netdev, 3151 "MAS: Enabling Media Autosense for port %d\n", 3152 hw->bus.func); 3153 } 3154 break; 3155 default: 3156 /* Shouldn't get here */ 3157 netdev_err(adapter->netdev, 3158 "MAS: Invalid port configuration, returning\n"); 3159 break; 3160 } 3161 } 3162 3163 /** 3164 * igb_init_i2c - Init I2C interface 3165 * @adapter: pointer to adapter structure 3166 **/ 3167 static s32 igb_init_i2c(struct igb_adapter *adapter) 3168 { 3169 s32 status = 0; 3170 3171 /* I2C interface supported on i350 devices */ 3172 if (adapter->hw.mac.type != e1000_i350) 3173 return 0; 3174 3175 /* Initialize the i2c bus which is controlled by the registers. 3176 * This bus will use the i2c_algo_bit structure that implements 3177 * the protocol through toggling of the 4 bits in the register. 3178 */ 3179 adapter->i2c_adap.owner = THIS_MODULE; 3180 adapter->i2c_algo = igb_i2c_algo; 3181 adapter->i2c_algo.data = adapter; 3182 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3183 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3184 strscpy(adapter->i2c_adap.name, "igb BB", 3185 sizeof(adapter->i2c_adap.name)); 3186 status = i2c_bit_add_bus(&adapter->i2c_adap); 3187 return status; 3188 } 3189 3190 /** 3191 * igb_probe - Device Initialization Routine 3192 * @pdev: PCI device information struct 3193 * @ent: entry in igb_pci_tbl 3194 * 3195 * Returns 0 on success, negative on failure 3196 * 3197 * igb_probe initializes an adapter identified by a pci_dev structure. 3198 * The OS initialization, configuring of the adapter private structure, 3199 * and a hardware reset occur. 3200 **/ 3201 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3202 { 3203 struct net_device *netdev; 3204 struct igb_adapter *adapter; 3205 struct e1000_hw *hw; 3206 u16 eeprom_data = 0; 3207 s32 ret_val; 3208 static int global_quad_port_a; /* global quad port a indication */ 3209 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3210 u8 part_str[E1000_PBANUM_LENGTH]; 3211 int err; 3212 3213 /* Catch broken hardware that put the wrong VF device ID in 3214 * the PCIe SR-IOV capability. 3215 */ 3216 if (pdev->is_virtfn) { 3217 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3218 pci_name(pdev), pdev->vendor, pdev->device); 3219 return -EINVAL; 3220 } 3221 3222 err = pci_enable_device_mem(pdev); 3223 if (err) 3224 return err; 3225 3226 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3227 if (err) { 3228 dev_err(&pdev->dev, 3229 "No usable DMA configuration, aborting\n"); 3230 goto err_dma; 3231 } 3232 3233 err = pci_request_mem_regions(pdev, igb_driver_name); 3234 if (err) 3235 goto err_pci_reg; 3236 3237 pci_set_master(pdev); 3238 pci_save_state(pdev); 3239 3240 err = -ENOMEM; 3241 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3242 IGB_MAX_TX_QUEUES); 3243 if (!netdev) 3244 goto err_alloc_etherdev; 3245 3246 SET_NETDEV_DEV(netdev, &pdev->dev); 3247 3248 pci_set_drvdata(pdev, netdev); 3249 adapter = netdev_priv(netdev); 3250 adapter->netdev = netdev; 3251 adapter->pdev = pdev; 3252 hw = &adapter->hw; 3253 hw->back = adapter; 3254 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3255 3256 err = -EIO; 3257 adapter->io_addr = pci_iomap(pdev, 0, 0); 3258 if (!adapter->io_addr) 3259 goto err_ioremap; 3260 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3261 hw->hw_addr = adapter->io_addr; 3262 3263 netdev->netdev_ops = &igb_netdev_ops; 3264 igb_set_ethtool_ops(netdev); 3265 netdev->watchdog_timeo = 5 * HZ; 3266 3267 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3268 3269 netdev->mem_start = pci_resource_start(pdev, 0); 3270 netdev->mem_end = pci_resource_end(pdev, 0); 3271 3272 /* PCI config space info */ 3273 hw->vendor_id = pdev->vendor; 3274 hw->device_id = pdev->device; 3275 hw->revision_id = pdev->revision; 3276 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3277 hw->subsystem_device_id = pdev->subsystem_device; 3278 3279 /* Copy the default MAC, PHY and NVM function pointers */ 3280 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3281 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3282 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3283 /* Initialize skew-specific constants */ 3284 err = ei->get_invariants(hw); 3285 if (err) 3286 goto err_sw_init; 3287 3288 /* setup the private structure */ 3289 err = igb_sw_init(adapter); 3290 if (err) 3291 goto err_sw_init; 3292 3293 igb_get_bus_info_pcie(hw); 3294 3295 hw->phy.autoneg_wait_to_complete = false; 3296 3297 /* Copper options */ 3298 if (hw->phy.media_type == e1000_media_type_copper) { 3299 hw->phy.mdix = AUTO_ALL_MODES; 3300 hw->phy.disable_polarity_correction = false; 3301 hw->phy.ms_type = e1000_ms_hw_default; 3302 } 3303 3304 if (igb_check_reset_block(hw)) 3305 dev_info(&pdev->dev, 3306 "PHY reset is blocked due to SOL/IDER session.\n"); 3307 3308 /* features is initialized to 0 in allocation, it might have bits 3309 * set by igb_sw_init so we should use an or instead of an 3310 * assignment. 3311 */ 3312 netdev->features |= NETIF_F_SG | 3313 NETIF_F_TSO | 3314 NETIF_F_TSO6 | 3315 NETIF_F_RXHASH | 3316 NETIF_F_RXCSUM | 3317 NETIF_F_HW_CSUM; 3318 3319 if (hw->mac.type >= e1000_82576) 3320 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3321 3322 if (hw->mac.type >= e1000_i350) 3323 netdev->features |= NETIF_F_HW_TC; 3324 3325 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3326 NETIF_F_GSO_GRE_CSUM | \ 3327 NETIF_F_GSO_IPXIP4 | \ 3328 NETIF_F_GSO_IPXIP6 | \ 3329 NETIF_F_GSO_UDP_TUNNEL | \ 3330 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3331 3332 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3333 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3334 3335 /* copy netdev features into list of user selectable features */ 3336 netdev->hw_features |= netdev->features | 3337 NETIF_F_HW_VLAN_CTAG_RX | 3338 NETIF_F_HW_VLAN_CTAG_TX | 3339 NETIF_F_RXALL; 3340 3341 if (hw->mac.type >= e1000_i350) 3342 netdev->hw_features |= NETIF_F_NTUPLE; 3343 3344 netdev->features |= NETIF_F_HIGHDMA; 3345 3346 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3347 netdev->mpls_features |= NETIF_F_HW_CSUM; 3348 netdev->hw_enc_features |= netdev->vlan_features; 3349 3350 /* set this bit last since it cannot be part of vlan_features */ 3351 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3352 NETIF_F_HW_VLAN_CTAG_RX | 3353 NETIF_F_HW_VLAN_CTAG_TX; 3354 3355 netdev->priv_flags |= IFF_SUPP_NOFCS; 3356 3357 netdev->priv_flags |= IFF_UNICAST_FLT; 3358 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3359 3360 /* MTU range: 68 - 9216 */ 3361 netdev->min_mtu = ETH_MIN_MTU; 3362 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3363 3364 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3365 3366 /* before reading the NVM, reset the controller to put the device in a 3367 * known good starting state 3368 */ 3369 hw->mac.ops.reset_hw(hw); 3370 3371 /* make sure the NVM is good , i211/i210 parts can have special NVM 3372 * that doesn't contain a checksum 3373 */ 3374 switch (hw->mac.type) { 3375 case e1000_i210: 3376 case e1000_i211: 3377 if (igb_get_flash_presence_i210(hw)) { 3378 if (hw->nvm.ops.validate(hw) < 0) { 3379 dev_err(&pdev->dev, 3380 "The NVM Checksum Is Not Valid\n"); 3381 err = -EIO; 3382 goto err_eeprom; 3383 } 3384 } 3385 break; 3386 default: 3387 if (hw->nvm.ops.validate(hw) < 0) { 3388 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3389 err = -EIO; 3390 goto err_eeprom; 3391 } 3392 break; 3393 } 3394 3395 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3396 /* copy the MAC address out of the NVM */ 3397 if (hw->mac.ops.read_mac_addr(hw)) 3398 dev_err(&pdev->dev, "NVM Read Error\n"); 3399 } 3400 3401 eth_hw_addr_set(netdev, hw->mac.addr); 3402 3403 if (!is_valid_ether_addr(netdev->dev_addr)) { 3404 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3405 err = -EIO; 3406 goto err_eeprom; 3407 } 3408 3409 igb_set_default_mac_filter(adapter); 3410 3411 /* get firmware version for ethtool -i */ 3412 igb_set_fw_version(adapter); 3413 3414 /* configure RXPBSIZE and TXPBSIZE */ 3415 if (hw->mac.type == e1000_i210) { 3416 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3417 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3418 } 3419 3420 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3421 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3422 3423 INIT_WORK(&adapter->reset_task, igb_reset_task); 3424 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3425 3426 /* Initialize link properties that are user-changeable */ 3427 adapter->fc_autoneg = true; 3428 hw->mac.autoneg = true; 3429 hw->phy.autoneg_advertised = 0x2f; 3430 3431 hw->fc.requested_mode = e1000_fc_default; 3432 hw->fc.current_mode = e1000_fc_default; 3433 3434 igb_validate_mdi_setting(hw); 3435 3436 /* By default, support wake on port A */ 3437 if (hw->bus.func == 0) 3438 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3439 3440 /* Check the NVM for wake support on non-port A ports */ 3441 if (hw->mac.type >= e1000_82580) 3442 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3443 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3444 &eeprom_data); 3445 else if (hw->bus.func == 1) 3446 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3447 3448 if (eeprom_data & IGB_EEPROM_APME) 3449 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3450 3451 /* now that we have the eeprom settings, apply the special cases where 3452 * the eeprom may be wrong or the board simply won't support wake on 3453 * lan on a particular port 3454 */ 3455 switch (pdev->device) { 3456 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3457 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3458 break; 3459 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3460 case E1000_DEV_ID_82576_FIBER: 3461 case E1000_DEV_ID_82576_SERDES: 3462 /* Wake events only supported on port A for dual fiber 3463 * regardless of eeprom setting 3464 */ 3465 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3466 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3467 break; 3468 case E1000_DEV_ID_82576_QUAD_COPPER: 3469 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3470 /* if quad port adapter, disable WoL on all but port A */ 3471 if (global_quad_port_a != 0) 3472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3473 else 3474 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3475 /* Reset for multiple quad port adapters */ 3476 if (++global_quad_port_a == 4) 3477 global_quad_port_a = 0; 3478 break; 3479 default: 3480 /* If the device can't wake, don't set software support */ 3481 if (!device_can_wakeup(&adapter->pdev->dev)) 3482 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3483 } 3484 3485 /* initialize the wol settings based on the eeprom settings */ 3486 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3487 adapter->wol |= E1000_WUFC_MAG; 3488 3489 /* Some vendors want WoL disabled by default, but still supported */ 3490 if ((hw->mac.type == e1000_i350) && 3491 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3492 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3493 adapter->wol = 0; 3494 } 3495 3496 /* Some vendors want the ability to Use the EEPROM setting as 3497 * enable/disable only, and not for capability 3498 */ 3499 if (((hw->mac.type == e1000_i350) || 3500 (hw->mac.type == e1000_i354)) && 3501 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3502 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3503 adapter->wol = 0; 3504 } 3505 if (hw->mac.type == e1000_i350) { 3506 if (((pdev->subsystem_device == 0x5001) || 3507 (pdev->subsystem_device == 0x5002)) && 3508 (hw->bus.func == 0)) { 3509 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3510 adapter->wol = 0; 3511 } 3512 if (pdev->subsystem_device == 0x1F52) 3513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3514 } 3515 3516 device_set_wakeup_enable(&adapter->pdev->dev, 3517 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3518 3519 /* reset the hardware with the new settings */ 3520 igb_reset(adapter); 3521 3522 /* Init the I2C interface */ 3523 err = igb_init_i2c(adapter); 3524 if (err) { 3525 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3526 goto err_eeprom; 3527 } 3528 3529 /* let the f/w know that the h/w is now under the control of the 3530 * driver. 3531 */ 3532 igb_get_hw_control(adapter); 3533 3534 strcpy(netdev->name, "eth%d"); 3535 err = register_netdev(netdev); 3536 if (err) 3537 goto err_register; 3538 3539 /* carrier off reporting is important to ethtool even BEFORE open */ 3540 netif_carrier_off(netdev); 3541 3542 #ifdef CONFIG_IGB_DCA 3543 if (dca_add_requester(&pdev->dev) == 0) { 3544 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3545 dev_info(&pdev->dev, "DCA enabled\n"); 3546 igb_setup_dca(adapter); 3547 } 3548 3549 #endif 3550 #ifdef CONFIG_IGB_HWMON 3551 /* Initialize the thermal sensor on i350 devices. */ 3552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3553 u16 ets_word; 3554 3555 /* Read the NVM to determine if this i350 device supports an 3556 * external thermal sensor. 3557 */ 3558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3559 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3560 adapter->ets = true; 3561 else 3562 adapter->ets = false; 3563 /* Only enable I2C bit banging if an external thermal 3564 * sensor is supported. 3565 */ 3566 if (adapter->ets) 3567 igb_set_i2c_bb(hw); 3568 hw->mac.ops.init_thermal_sensor_thresh(hw); 3569 if (igb_sysfs_init(adapter)) 3570 dev_err(&pdev->dev, 3571 "failed to allocate sysfs resources\n"); 3572 } else { 3573 adapter->ets = false; 3574 } 3575 #endif 3576 /* Check if Media Autosense is enabled */ 3577 adapter->ei = *ei; 3578 if (hw->dev_spec._82575.mas_capable) 3579 igb_init_mas(adapter); 3580 3581 /* do hw tstamp init after resetting */ 3582 igb_ptp_init(adapter); 3583 3584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3585 /* print bus type/speed/width info, not applicable to i354 */ 3586 if (hw->mac.type != e1000_i354) { 3587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3588 netdev->name, 3589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3591 "unknown"), 3592 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3593 "Width x4" : 3594 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3595 "Width x2" : 3596 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3597 "Width x1" : "unknown"), netdev->dev_addr); 3598 } 3599 3600 if ((hw->mac.type == e1000_82576 && 3601 rd32(E1000_EECD) & E1000_EECD_PRES) || 3602 (hw->mac.type >= e1000_i210 || 3603 igb_get_flash_presence_i210(hw))) { 3604 ret_val = igb_read_part_string(hw, part_str, 3605 E1000_PBANUM_LENGTH); 3606 } else { 3607 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3608 } 3609 3610 if (ret_val) 3611 strcpy(part_str, "Unknown"); 3612 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3613 dev_info(&pdev->dev, 3614 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3615 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3616 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3617 adapter->num_rx_queues, adapter->num_tx_queues); 3618 if (hw->phy.media_type == e1000_media_type_copper) { 3619 switch (hw->mac.type) { 3620 case e1000_i350: 3621 case e1000_i210: 3622 case e1000_i211: 3623 /* Enable EEE for internal copper PHY devices */ 3624 err = igb_set_eee_i350(hw, true, true); 3625 if ((!err) && 3626 (!hw->dev_spec._82575.eee_disable)) { 3627 adapter->eee_advert = 3628 MDIO_EEE_100TX | MDIO_EEE_1000T; 3629 adapter->flags |= IGB_FLAG_EEE; 3630 } 3631 break; 3632 case e1000_i354: 3633 if ((rd32(E1000_CTRL_EXT) & 3634 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3635 err = igb_set_eee_i354(hw, true, true); 3636 if ((!err) && 3637 (!hw->dev_spec._82575.eee_disable)) { 3638 adapter->eee_advert = 3639 MDIO_EEE_100TX | MDIO_EEE_1000T; 3640 adapter->flags |= IGB_FLAG_EEE; 3641 } 3642 } 3643 break; 3644 default: 3645 break; 3646 } 3647 } 3648 3649 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3650 3651 pm_runtime_put_noidle(&pdev->dev); 3652 return 0; 3653 3654 err_register: 3655 igb_release_hw_control(adapter); 3656 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3657 err_eeprom: 3658 if (!igb_check_reset_block(hw)) 3659 igb_reset_phy(hw); 3660 3661 if (hw->flash_address) 3662 iounmap(hw->flash_address); 3663 err_sw_init: 3664 kfree(adapter->mac_table); 3665 kfree(adapter->shadow_vfta); 3666 igb_clear_interrupt_scheme(adapter); 3667 #ifdef CONFIG_PCI_IOV 3668 igb_disable_sriov(pdev, false); 3669 #endif 3670 pci_iounmap(pdev, adapter->io_addr); 3671 err_ioremap: 3672 free_netdev(netdev); 3673 err_alloc_etherdev: 3674 pci_release_mem_regions(pdev); 3675 err_pci_reg: 3676 err_dma: 3677 pci_disable_device(pdev); 3678 return err; 3679 } 3680 3681 #ifdef CONFIG_PCI_IOV 3682 static int igb_sriov_reinit(struct pci_dev *dev) 3683 { 3684 struct net_device *netdev = pci_get_drvdata(dev); 3685 struct igb_adapter *adapter = netdev_priv(netdev); 3686 struct pci_dev *pdev = adapter->pdev; 3687 3688 rtnl_lock(); 3689 3690 if (netif_running(netdev)) 3691 igb_close(netdev); 3692 else 3693 igb_reset(adapter); 3694 3695 igb_clear_interrupt_scheme(adapter); 3696 3697 igb_init_queue_configuration(adapter); 3698 3699 if (igb_init_interrupt_scheme(adapter, true)) { 3700 rtnl_unlock(); 3701 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3702 return -ENOMEM; 3703 } 3704 3705 if (netif_running(netdev)) 3706 igb_open(netdev); 3707 3708 rtnl_unlock(); 3709 3710 return 0; 3711 } 3712 3713 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3714 { 3715 struct net_device *netdev = pci_get_drvdata(pdev); 3716 struct igb_adapter *adapter = netdev_priv(netdev); 3717 struct e1000_hw *hw = &adapter->hw; 3718 unsigned long flags; 3719 3720 /* reclaim resources allocated to VFs */ 3721 if (adapter->vf_data) { 3722 /* disable iov and allow time for transactions to clear */ 3723 if (pci_vfs_assigned(pdev)) { 3724 dev_warn(&pdev->dev, 3725 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3726 return -EPERM; 3727 } else { 3728 pci_disable_sriov(pdev); 3729 msleep(500); 3730 } 3731 spin_lock_irqsave(&adapter->vfs_lock, flags); 3732 kfree(adapter->vf_mac_list); 3733 adapter->vf_mac_list = NULL; 3734 kfree(adapter->vf_data); 3735 adapter->vf_data = NULL; 3736 adapter->vfs_allocated_count = 0; 3737 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3738 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3739 wrfl(); 3740 msleep(100); 3741 dev_info(&pdev->dev, "IOV Disabled\n"); 3742 3743 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3744 adapter->flags |= IGB_FLAG_DMAC; 3745 } 3746 3747 return reinit ? igb_sriov_reinit(pdev) : 0; 3748 } 3749 3750 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3751 { 3752 struct net_device *netdev = pci_get_drvdata(pdev); 3753 struct igb_adapter *adapter = netdev_priv(netdev); 3754 int old_vfs = pci_num_vf(pdev); 3755 struct vf_mac_filter *mac_list; 3756 int err = 0; 3757 int num_vf_mac_filters, i; 3758 3759 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3760 err = -EPERM; 3761 goto out; 3762 } 3763 if (!num_vfs) 3764 goto out; 3765 3766 if (old_vfs) { 3767 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3768 old_vfs, max_vfs); 3769 adapter->vfs_allocated_count = old_vfs; 3770 } else 3771 adapter->vfs_allocated_count = num_vfs; 3772 3773 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3774 sizeof(struct vf_data_storage), GFP_KERNEL); 3775 3776 /* if allocation failed then we do not support SR-IOV */ 3777 if (!adapter->vf_data) { 3778 adapter->vfs_allocated_count = 0; 3779 err = -ENOMEM; 3780 goto out; 3781 } 3782 3783 /* Due to the limited number of RAR entries calculate potential 3784 * number of MAC filters available for the VFs. Reserve entries 3785 * for PF default MAC, PF MAC filters and at least one RAR entry 3786 * for each VF for VF MAC. 3787 */ 3788 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3789 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3790 adapter->vfs_allocated_count); 3791 3792 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3793 sizeof(struct vf_mac_filter), 3794 GFP_KERNEL); 3795 3796 mac_list = adapter->vf_mac_list; 3797 INIT_LIST_HEAD(&adapter->vf_macs.l); 3798 3799 if (adapter->vf_mac_list) { 3800 /* Initialize list of VF MAC filters */ 3801 for (i = 0; i < num_vf_mac_filters; i++) { 3802 mac_list->vf = -1; 3803 mac_list->free = true; 3804 list_add(&mac_list->l, &adapter->vf_macs.l); 3805 mac_list++; 3806 } 3807 } else { 3808 /* If we could not allocate memory for the VF MAC filters 3809 * we can continue without this feature but warn user. 3810 */ 3811 dev_err(&pdev->dev, 3812 "Unable to allocate memory for VF MAC filter list\n"); 3813 } 3814 3815 dev_info(&pdev->dev, "%d VFs allocated\n", 3816 adapter->vfs_allocated_count); 3817 for (i = 0; i < adapter->vfs_allocated_count; i++) 3818 igb_vf_configure(adapter, i); 3819 3820 /* DMA Coalescing is not supported in IOV mode. */ 3821 adapter->flags &= ~IGB_FLAG_DMAC; 3822 3823 if (reinit) { 3824 err = igb_sriov_reinit(pdev); 3825 if (err) 3826 goto err_out; 3827 } 3828 3829 /* only call pci_enable_sriov() if no VFs are allocated already */ 3830 if (!old_vfs) 3831 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3832 3833 goto out; 3834 3835 err_out: 3836 kfree(adapter->vf_mac_list); 3837 adapter->vf_mac_list = NULL; 3838 kfree(adapter->vf_data); 3839 adapter->vf_data = NULL; 3840 adapter->vfs_allocated_count = 0; 3841 out: 3842 return err; 3843 } 3844 3845 #endif 3846 /** 3847 * igb_remove_i2c - Cleanup I2C interface 3848 * @adapter: pointer to adapter structure 3849 **/ 3850 static void igb_remove_i2c(struct igb_adapter *adapter) 3851 { 3852 /* free the adapter bus structure */ 3853 i2c_del_adapter(&adapter->i2c_adap); 3854 } 3855 3856 /** 3857 * igb_remove - Device Removal Routine 3858 * @pdev: PCI device information struct 3859 * 3860 * igb_remove is called by the PCI subsystem to alert the driver 3861 * that it should release a PCI device. The could be caused by a 3862 * Hot-Plug event, or because the driver is going to be removed from 3863 * memory. 3864 **/ 3865 static void igb_remove(struct pci_dev *pdev) 3866 { 3867 struct net_device *netdev = pci_get_drvdata(pdev); 3868 struct igb_adapter *adapter = netdev_priv(netdev); 3869 struct e1000_hw *hw = &adapter->hw; 3870 3871 pm_runtime_get_noresume(&pdev->dev); 3872 #ifdef CONFIG_IGB_HWMON 3873 igb_sysfs_exit(adapter); 3874 #endif 3875 igb_remove_i2c(adapter); 3876 igb_ptp_stop(adapter); 3877 /* The watchdog timer may be rescheduled, so explicitly 3878 * disable watchdog from being rescheduled. 3879 */ 3880 set_bit(__IGB_DOWN, &adapter->state); 3881 del_timer_sync(&adapter->watchdog_timer); 3882 del_timer_sync(&adapter->phy_info_timer); 3883 3884 cancel_work_sync(&adapter->reset_task); 3885 cancel_work_sync(&adapter->watchdog_task); 3886 3887 #ifdef CONFIG_IGB_DCA 3888 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3889 dev_info(&pdev->dev, "DCA disabled\n"); 3890 dca_remove_requester(&pdev->dev); 3891 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3892 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3893 } 3894 #endif 3895 3896 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3897 * would have already happened in close and is redundant. 3898 */ 3899 igb_release_hw_control(adapter); 3900 3901 #ifdef CONFIG_PCI_IOV 3902 igb_disable_sriov(pdev, false); 3903 #endif 3904 3905 unregister_netdev(netdev); 3906 3907 igb_clear_interrupt_scheme(adapter); 3908 3909 pci_iounmap(pdev, adapter->io_addr); 3910 if (hw->flash_address) 3911 iounmap(hw->flash_address); 3912 pci_release_mem_regions(pdev); 3913 3914 kfree(adapter->mac_table); 3915 kfree(adapter->shadow_vfta); 3916 free_netdev(netdev); 3917 3918 pci_disable_device(pdev); 3919 } 3920 3921 /** 3922 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3923 * @adapter: board private structure to initialize 3924 * 3925 * This function initializes the vf specific data storage and then attempts to 3926 * allocate the VFs. The reason for ordering it this way is because it is much 3927 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3928 * the memory for the VFs. 3929 **/ 3930 static void igb_probe_vfs(struct igb_adapter *adapter) 3931 { 3932 #ifdef CONFIG_PCI_IOV 3933 struct pci_dev *pdev = adapter->pdev; 3934 struct e1000_hw *hw = &adapter->hw; 3935 3936 /* Virtualization features not supported on i210 family. */ 3937 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3938 return; 3939 3940 /* Of the below we really only want the effect of getting 3941 * IGB_FLAG_HAS_MSIX set (if available), without which 3942 * igb_enable_sriov() has no effect. 3943 */ 3944 igb_set_interrupt_capability(adapter, true); 3945 igb_reset_interrupt_capability(adapter); 3946 3947 pci_sriov_set_totalvfs(pdev, 7); 3948 igb_enable_sriov(pdev, max_vfs, false); 3949 3950 #endif /* CONFIG_PCI_IOV */ 3951 } 3952 3953 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3954 { 3955 struct e1000_hw *hw = &adapter->hw; 3956 unsigned int max_rss_queues; 3957 3958 /* Determine the maximum number of RSS queues supported. */ 3959 switch (hw->mac.type) { 3960 case e1000_i211: 3961 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3962 break; 3963 case e1000_82575: 3964 case e1000_i210: 3965 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3966 break; 3967 case e1000_i350: 3968 /* I350 cannot do RSS and SR-IOV at the same time */ 3969 if (!!adapter->vfs_allocated_count) { 3970 max_rss_queues = 1; 3971 break; 3972 } 3973 fallthrough; 3974 case e1000_82576: 3975 if (!!adapter->vfs_allocated_count) { 3976 max_rss_queues = 2; 3977 break; 3978 } 3979 fallthrough; 3980 case e1000_82580: 3981 case e1000_i354: 3982 default: 3983 max_rss_queues = IGB_MAX_RX_QUEUES; 3984 break; 3985 } 3986 3987 return max_rss_queues; 3988 } 3989 3990 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3991 { 3992 u32 max_rss_queues; 3993 3994 max_rss_queues = igb_get_max_rss_queues(adapter); 3995 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3996 3997 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3998 } 3999 4000 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4001 const u32 max_rss_queues) 4002 { 4003 struct e1000_hw *hw = &adapter->hw; 4004 4005 /* Determine if we need to pair queues. */ 4006 switch (hw->mac.type) { 4007 case e1000_82575: 4008 case e1000_i211: 4009 /* Device supports enough interrupts without queue pairing. */ 4010 break; 4011 case e1000_82576: 4012 case e1000_82580: 4013 case e1000_i350: 4014 case e1000_i354: 4015 case e1000_i210: 4016 default: 4017 /* If rss_queues > half of max_rss_queues, pair the queues in 4018 * order to conserve interrupts due to limited supply. 4019 */ 4020 if (adapter->rss_queues > (max_rss_queues / 2)) 4021 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4022 else 4023 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4024 break; 4025 } 4026 } 4027 4028 /** 4029 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4030 * @adapter: board private structure to initialize 4031 * 4032 * igb_sw_init initializes the Adapter private data structure. 4033 * Fields are initialized based on PCI device information and 4034 * OS network device settings (MTU size). 4035 **/ 4036 static int igb_sw_init(struct igb_adapter *adapter) 4037 { 4038 struct e1000_hw *hw = &adapter->hw; 4039 struct net_device *netdev = adapter->netdev; 4040 struct pci_dev *pdev = adapter->pdev; 4041 4042 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4043 4044 /* set default ring sizes */ 4045 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4046 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4047 4048 /* set default ITR values */ 4049 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4050 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4051 4052 /* set default work limits */ 4053 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4054 4055 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4056 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4057 4058 spin_lock_init(&adapter->nfc_lock); 4059 spin_lock_init(&adapter->stats64_lock); 4060 4061 /* init spinlock to avoid concurrency of VF resources */ 4062 spin_lock_init(&adapter->vfs_lock); 4063 #ifdef CONFIG_PCI_IOV 4064 switch (hw->mac.type) { 4065 case e1000_82576: 4066 case e1000_i350: 4067 if (max_vfs > 7) { 4068 dev_warn(&pdev->dev, 4069 "Maximum of 7 VFs per PF, using max\n"); 4070 max_vfs = adapter->vfs_allocated_count = 7; 4071 } else 4072 adapter->vfs_allocated_count = max_vfs; 4073 if (adapter->vfs_allocated_count) 4074 dev_warn(&pdev->dev, 4075 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4076 break; 4077 default: 4078 break; 4079 } 4080 #endif /* CONFIG_PCI_IOV */ 4081 4082 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4083 adapter->flags |= IGB_FLAG_HAS_MSIX; 4084 4085 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4086 sizeof(struct igb_mac_addr), 4087 GFP_KERNEL); 4088 if (!adapter->mac_table) 4089 return -ENOMEM; 4090 4091 igb_probe_vfs(adapter); 4092 4093 igb_init_queue_configuration(adapter); 4094 4095 /* Setup and initialize a copy of the hw vlan table array */ 4096 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4097 GFP_KERNEL); 4098 if (!adapter->shadow_vfta) 4099 return -ENOMEM; 4100 4101 /* This call may decrease the number of queues */ 4102 if (igb_init_interrupt_scheme(adapter, true)) { 4103 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4104 return -ENOMEM; 4105 } 4106 4107 /* Explicitly disable IRQ since the NIC can be in any state. */ 4108 igb_irq_disable(adapter); 4109 4110 if (hw->mac.type >= e1000_i350) 4111 adapter->flags &= ~IGB_FLAG_DMAC; 4112 4113 set_bit(__IGB_DOWN, &adapter->state); 4114 return 0; 4115 } 4116 4117 /** 4118 * __igb_open - Called when a network interface is made active 4119 * @netdev: network interface device structure 4120 * @resuming: indicates whether we are in a resume call 4121 * 4122 * Returns 0 on success, negative value on failure 4123 * 4124 * The open entry point is called when a network interface is made 4125 * active by the system (IFF_UP). At this point all resources needed 4126 * for transmit and receive operations are allocated, the interrupt 4127 * handler is registered with the OS, the watchdog timer is started, 4128 * and the stack is notified that the interface is ready. 4129 **/ 4130 static int __igb_open(struct net_device *netdev, bool resuming) 4131 { 4132 struct igb_adapter *adapter = netdev_priv(netdev); 4133 struct e1000_hw *hw = &adapter->hw; 4134 struct pci_dev *pdev = adapter->pdev; 4135 int err; 4136 int i; 4137 4138 /* disallow open during test */ 4139 if (test_bit(__IGB_TESTING, &adapter->state)) { 4140 WARN_ON(resuming); 4141 return -EBUSY; 4142 } 4143 4144 if (!resuming) 4145 pm_runtime_get_sync(&pdev->dev); 4146 4147 netif_carrier_off(netdev); 4148 4149 /* allocate transmit descriptors */ 4150 err = igb_setup_all_tx_resources(adapter); 4151 if (err) 4152 goto err_setup_tx; 4153 4154 /* allocate receive descriptors */ 4155 err = igb_setup_all_rx_resources(adapter); 4156 if (err) 4157 goto err_setup_rx; 4158 4159 igb_power_up_link(adapter); 4160 4161 /* before we allocate an interrupt, we must be ready to handle it. 4162 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4163 * as soon as we call pci_request_irq, so we have to setup our 4164 * clean_rx handler before we do so. 4165 */ 4166 igb_configure(adapter); 4167 4168 err = igb_request_irq(adapter); 4169 if (err) 4170 goto err_req_irq; 4171 4172 /* Notify the stack of the actual queue counts. */ 4173 err = netif_set_real_num_tx_queues(adapter->netdev, 4174 adapter->num_tx_queues); 4175 if (err) 4176 goto err_set_queues; 4177 4178 err = netif_set_real_num_rx_queues(adapter->netdev, 4179 adapter->num_rx_queues); 4180 if (err) 4181 goto err_set_queues; 4182 4183 /* From here on the code is the same as igb_up() */ 4184 clear_bit(__IGB_DOWN, &adapter->state); 4185 4186 for (i = 0; i < adapter->num_q_vectors; i++) 4187 napi_enable(&(adapter->q_vector[i]->napi)); 4188 4189 /* Clear any pending interrupts. */ 4190 rd32(E1000_TSICR); 4191 rd32(E1000_ICR); 4192 4193 igb_irq_enable(adapter); 4194 4195 /* notify VFs that reset has been completed */ 4196 if (adapter->vfs_allocated_count) { 4197 u32 reg_data = rd32(E1000_CTRL_EXT); 4198 4199 reg_data |= E1000_CTRL_EXT_PFRSTD; 4200 wr32(E1000_CTRL_EXT, reg_data); 4201 } 4202 4203 netif_tx_start_all_queues(netdev); 4204 4205 if (!resuming) 4206 pm_runtime_put(&pdev->dev); 4207 4208 /* start the watchdog. */ 4209 hw->mac.get_link_status = 1; 4210 schedule_work(&adapter->watchdog_task); 4211 4212 return 0; 4213 4214 err_set_queues: 4215 igb_free_irq(adapter); 4216 err_req_irq: 4217 igb_release_hw_control(adapter); 4218 igb_power_down_link(adapter); 4219 igb_free_all_rx_resources(adapter); 4220 err_setup_rx: 4221 igb_free_all_tx_resources(adapter); 4222 err_setup_tx: 4223 igb_reset(adapter); 4224 if (!resuming) 4225 pm_runtime_put(&pdev->dev); 4226 4227 return err; 4228 } 4229 4230 int igb_open(struct net_device *netdev) 4231 { 4232 return __igb_open(netdev, false); 4233 } 4234 4235 /** 4236 * __igb_close - Disables a network interface 4237 * @netdev: network interface device structure 4238 * @suspending: indicates we are in a suspend call 4239 * 4240 * Returns 0, this is not allowed to fail 4241 * 4242 * The close entry point is called when an interface is de-activated 4243 * by the OS. The hardware is still under the driver's control, but 4244 * needs to be disabled. A global MAC reset is issued to stop the 4245 * hardware, and all transmit and receive resources are freed. 4246 **/ 4247 static int __igb_close(struct net_device *netdev, bool suspending) 4248 { 4249 struct igb_adapter *adapter = netdev_priv(netdev); 4250 struct pci_dev *pdev = adapter->pdev; 4251 4252 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4253 4254 if (!suspending) 4255 pm_runtime_get_sync(&pdev->dev); 4256 4257 igb_down(adapter); 4258 igb_free_irq(adapter); 4259 4260 igb_free_all_tx_resources(adapter); 4261 igb_free_all_rx_resources(adapter); 4262 4263 if (!suspending) 4264 pm_runtime_put_sync(&pdev->dev); 4265 return 0; 4266 } 4267 4268 int igb_close(struct net_device *netdev) 4269 { 4270 if (netif_device_present(netdev) || netdev->dismantle) 4271 return __igb_close(netdev, false); 4272 return 0; 4273 } 4274 4275 /** 4276 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4277 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4278 * 4279 * Return 0 on success, negative on failure 4280 **/ 4281 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4282 { 4283 struct device *dev = tx_ring->dev; 4284 int size; 4285 4286 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4287 4288 tx_ring->tx_buffer_info = vmalloc(size); 4289 if (!tx_ring->tx_buffer_info) 4290 goto err; 4291 4292 /* round up to nearest 4K */ 4293 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4294 tx_ring->size = ALIGN(tx_ring->size, 4096); 4295 4296 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4297 &tx_ring->dma, GFP_KERNEL); 4298 if (!tx_ring->desc) 4299 goto err; 4300 4301 tx_ring->next_to_use = 0; 4302 tx_ring->next_to_clean = 0; 4303 4304 return 0; 4305 4306 err: 4307 vfree(tx_ring->tx_buffer_info); 4308 tx_ring->tx_buffer_info = NULL; 4309 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4310 return -ENOMEM; 4311 } 4312 4313 /** 4314 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4315 * (Descriptors) for all queues 4316 * @adapter: board private structure 4317 * 4318 * Return 0 on success, negative on failure 4319 **/ 4320 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4321 { 4322 struct pci_dev *pdev = adapter->pdev; 4323 int i, err = 0; 4324 4325 for (i = 0; i < adapter->num_tx_queues; i++) { 4326 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4327 if (err) { 4328 dev_err(&pdev->dev, 4329 "Allocation for Tx Queue %u failed\n", i); 4330 for (i--; i >= 0; i--) 4331 igb_free_tx_resources(adapter->tx_ring[i]); 4332 break; 4333 } 4334 } 4335 4336 return err; 4337 } 4338 4339 /** 4340 * igb_setup_tctl - configure the transmit control registers 4341 * @adapter: Board private structure 4342 **/ 4343 void igb_setup_tctl(struct igb_adapter *adapter) 4344 { 4345 struct e1000_hw *hw = &adapter->hw; 4346 u32 tctl; 4347 4348 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4349 wr32(E1000_TXDCTL(0), 0); 4350 4351 /* Program the Transmit Control Register */ 4352 tctl = rd32(E1000_TCTL); 4353 tctl &= ~E1000_TCTL_CT; 4354 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4355 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4356 4357 igb_config_collision_dist(hw); 4358 4359 /* Enable transmits */ 4360 tctl |= E1000_TCTL_EN; 4361 4362 wr32(E1000_TCTL, tctl); 4363 } 4364 4365 /** 4366 * igb_configure_tx_ring - Configure transmit ring after Reset 4367 * @adapter: board private structure 4368 * @ring: tx ring to configure 4369 * 4370 * Configure a transmit ring after a reset. 4371 **/ 4372 void igb_configure_tx_ring(struct igb_adapter *adapter, 4373 struct igb_ring *ring) 4374 { 4375 struct e1000_hw *hw = &adapter->hw; 4376 u32 txdctl = 0; 4377 u64 tdba = ring->dma; 4378 int reg_idx = ring->reg_idx; 4379 4380 wr32(E1000_TDLEN(reg_idx), 4381 ring->count * sizeof(union e1000_adv_tx_desc)); 4382 wr32(E1000_TDBAL(reg_idx), 4383 tdba & 0x00000000ffffffffULL); 4384 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4385 4386 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4387 wr32(E1000_TDH(reg_idx), 0); 4388 writel(0, ring->tail); 4389 4390 txdctl |= IGB_TX_PTHRESH; 4391 txdctl |= IGB_TX_HTHRESH << 8; 4392 txdctl |= IGB_TX_WTHRESH << 16; 4393 4394 /* reinitialize tx_buffer_info */ 4395 memset(ring->tx_buffer_info, 0, 4396 sizeof(struct igb_tx_buffer) * ring->count); 4397 4398 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4399 wr32(E1000_TXDCTL(reg_idx), txdctl); 4400 } 4401 4402 /** 4403 * igb_configure_tx - Configure transmit Unit after Reset 4404 * @adapter: board private structure 4405 * 4406 * Configure the Tx unit of the MAC after a reset. 4407 **/ 4408 static void igb_configure_tx(struct igb_adapter *adapter) 4409 { 4410 struct e1000_hw *hw = &adapter->hw; 4411 int i; 4412 4413 /* disable the queues */ 4414 for (i = 0; i < adapter->num_tx_queues; i++) 4415 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4416 4417 wrfl(); 4418 usleep_range(10000, 20000); 4419 4420 for (i = 0; i < adapter->num_tx_queues; i++) 4421 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4422 } 4423 4424 /** 4425 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4426 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4427 * 4428 * Returns 0 on success, negative on failure 4429 **/ 4430 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4431 { 4432 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4433 struct device *dev = rx_ring->dev; 4434 int size, res; 4435 4436 /* XDP RX-queue info */ 4437 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4438 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4439 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4440 rx_ring->queue_index, 0); 4441 if (res < 0) { 4442 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4443 rx_ring->queue_index); 4444 return res; 4445 } 4446 4447 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4448 4449 rx_ring->rx_buffer_info = vmalloc(size); 4450 if (!rx_ring->rx_buffer_info) 4451 goto err; 4452 4453 /* Round up to nearest 4K */ 4454 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4455 rx_ring->size = ALIGN(rx_ring->size, 4096); 4456 4457 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4458 &rx_ring->dma, GFP_KERNEL); 4459 if (!rx_ring->desc) 4460 goto err; 4461 4462 rx_ring->next_to_alloc = 0; 4463 rx_ring->next_to_clean = 0; 4464 rx_ring->next_to_use = 0; 4465 4466 rx_ring->xdp_prog = adapter->xdp_prog; 4467 4468 return 0; 4469 4470 err: 4471 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4472 vfree(rx_ring->rx_buffer_info); 4473 rx_ring->rx_buffer_info = NULL; 4474 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4475 return -ENOMEM; 4476 } 4477 4478 /** 4479 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4480 * (Descriptors) for all queues 4481 * @adapter: board private structure 4482 * 4483 * Return 0 on success, negative on failure 4484 **/ 4485 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4486 { 4487 struct pci_dev *pdev = adapter->pdev; 4488 int i, err = 0; 4489 4490 for (i = 0; i < adapter->num_rx_queues; i++) { 4491 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4492 if (err) { 4493 dev_err(&pdev->dev, 4494 "Allocation for Rx Queue %u failed\n", i); 4495 for (i--; i >= 0; i--) 4496 igb_free_rx_resources(adapter->rx_ring[i]); 4497 break; 4498 } 4499 } 4500 4501 return err; 4502 } 4503 4504 /** 4505 * igb_setup_mrqc - configure the multiple receive queue control registers 4506 * @adapter: Board private structure 4507 **/ 4508 static void igb_setup_mrqc(struct igb_adapter *adapter) 4509 { 4510 struct e1000_hw *hw = &adapter->hw; 4511 u32 mrqc, rxcsum; 4512 u32 j, num_rx_queues; 4513 u32 rss_key[10]; 4514 4515 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4516 for (j = 0; j < 10; j++) 4517 wr32(E1000_RSSRK(j), rss_key[j]); 4518 4519 num_rx_queues = adapter->rss_queues; 4520 4521 switch (hw->mac.type) { 4522 case e1000_82576: 4523 /* 82576 supports 2 RSS queues for SR-IOV */ 4524 if (adapter->vfs_allocated_count) 4525 num_rx_queues = 2; 4526 break; 4527 default: 4528 break; 4529 } 4530 4531 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4532 for (j = 0; j < IGB_RETA_SIZE; j++) 4533 adapter->rss_indir_tbl[j] = 4534 (j * num_rx_queues) / IGB_RETA_SIZE; 4535 adapter->rss_indir_tbl_init = num_rx_queues; 4536 } 4537 igb_write_rss_indir_tbl(adapter); 4538 4539 /* Disable raw packet checksumming so that RSS hash is placed in 4540 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4541 * offloads as they are enabled by default 4542 */ 4543 rxcsum = rd32(E1000_RXCSUM); 4544 rxcsum |= E1000_RXCSUM_PCSD; 4545 4546 if (adapter->hw.mac.type >= e1000_82576) 4547 /* Enable Receive Checksum Offload for SCTP */ 4548 rxcsum |= E1000_RXCSUM_CRCOFL; 4549 4550 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4551 wr32(E1000_RXCSUM, rxcsum); 4552 4553 /* Generate RSS hash based on packet types, TCP/UDP 4554 * port numbers and/or IPv4/v6 src and dst addresses 4555 */ 4556 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4557 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4558 E1000_MRQC_RSS_FIELD_IPV6 | 4559 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4560 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4561 4562 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4563 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4564 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4565 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4566 4567 /* If VMDq is enabled then we set the appropriate mode for that, else 4568 * we default to RSS so that an RSS hash is calculated per packet even 4569 * if we are only using one queue 4570 */ 4571 if (adapter->vfs_allocated_count) { 4572 if (hw->mac.type > e1000_82575) { 4573 /* Set the default pool for the PF's first queue */ 4574 u32 vtctl = rd32(E1000_VT_CTL); 4575 4576 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4577 E1000_VT_CTL_DISABLE_DEF_POOL); 4578 vtctl |= adapter->vfs_allocated_count << 4579 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4580 wr32(E1000_VT_CTL, vtctl); 4581 } 4582 if (adapter->rss_queues > 1) 4583 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4584 else 4585 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4586 } else { 4587 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4588 } 4589 igb_vmm_control(adapter); 4590 4591 wr32(E1000_MRQC, mrqc); 4592 } 4593 4594 /** 4595 * igb_setup_rctl - configure the receive control registers 4596 * @adapter: Board private structure 4597 **/ 4598 void igb_setup_rctl(struct igb_adapter *adapter) 4599 { 4600 struct e1000_hw *hw = &adapter->hw; 4601 u32 rctl; 4602 4603 rctl = rd32(E1000_RCTL); 4604 4605 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4606 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4607 4608 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4609 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4610 4611 /* enable stripping of CRC. It's unlikely this will break BMC 4612 * redirection as it did with e1000. Newer features require 4613 * that the HW strips the CRC. 4614 */ 4615 rctl |= E1000_RCTL_SECRC; 4616 4617 /* disable store bad packets and clear size bits. */ 4618 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4619 4620 /* enable LPE to allow for reception of jumbo frames */ 4621 rctl |= E1000_RCTL_LPE; 4622 4623 /* disable queue 0 to prevent tail write w/o re-config */ 4624 wr32(E1000_RXDCTL(0), 0); 4625 4626 /* Attention!!! For SR-IOV PF driver operations you must enable 4627 * queue drop for all VF and PF queues to prevent head of line blocking 4628 * if an un-trusted VF does not provide descriptors to hardware. 4629 */ 4630 if (adapter->vfs_allocated_count) { 4631 /* set all queue drop enable bits */ 4632 wr32(E1000_QDE, ALL_QUEUES); 4633 } 4634 4635 /* This is useful for sniffing bad packets. */ 4636 if (adapter->netdev->features & NETIF_F_RXALL) { 4637 /* UPE and MPE will be handled by normal PROMISC logic 4638 * in e1000e_set_rx_mode 4639 */ 4640 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4641 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4642 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4643 4644 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4645 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4646 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4647 * and that breaks VLANs. 4648 */ 4649 } 4650 4651 wr32(E1000_RCTL, rctl); 4652 } 4653 4654 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4655 int vfn) 4656 { 4657 struct e1000_hw *hw = &adapter->hw; 4658 u32 vmolr; 4659 4660 if (size > MAX_JUMBO_FRAME_SIZE) 4661 size = MAX_JUMBO_FRAME_SIZE; 4662 4663 vmolr = rd32(E1000_VMOLR(vfn)); 4664 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4665 vmolr |= size | E1000_VMOLR_LPE; 4666 wr32(E1000_VMOLR(vfn), vmolr); 4667 4668 return 0; 4669 } 4670 4671 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4672 int vfn, bool enable) 4673 { 4674 struct e1000_hw *hw = &adapter->hw; 4675 u32 val, reg; 4676 4677 if (hw->mac.type < e1000_82576) 4678 return; 4679 4680 if (hw->mac.type == e1000_i350) 4681 reg = E1000_DVMOLR(vfn); 4682 else 4683 reg = E1000_VMOLR(vfn); 4684 4685 val = rd32(reg); 4686 if (enable) 4687 val |= E1000_VMOLR_STRVLAN; 4688 else 4689 val &= ~(E1000_VMOLR_STRVLAN); 4690 wr32(reg, val); 4691 } 4692 4693 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4694 int vfn, bool aupe) 4695 { 4696 struct e1000_hw *hw = &adapter->hw; 4697 u32 vmolr; 4698 4699 /* This register exists only on 82576 and newer so if we are older then 4700 * we should exit and do nothing 4701 */ 4702 if (hw->mac.type < e1000_82576) 4703 return; 4704 4705 vmolr = rd32(E1000_VMOLR(vfn)); 4706 if (aupe) 4707 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4708 else 4709 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4710 4711 /* clear all bits that might not be set */ 4712 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4713 4714 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4715 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4716 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4717 * multicast packets 4718 */ 4719 if (vfn <= adapter->vfs_allocated_count) 4720 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4721 4722 wr32(E1000_VMOLR(vfn), vmolr); 4723 } 4724 4725 /** 4726 * igb_setup_srrctl - configure the split and replication receive control 4727 * registers 4728 * @adapter: Board private structure 4729 * @ring: receive ring to be configured 4730 **/ 4731 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4732 { 4733 struct e1000_hw *hw = &adapter->hw; 4734 int reg_idx = ring->reg_idx; 4735 u32 srrctl = 0; 4736 4737 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4738 if (ring_uses_large_buffer(ring)) 4739 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4740 else 4741 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4742 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4743 if (hw->mac.type >= e1000_82580) 4744 srrctl |= E1000_SRRCTL_TIMESTAMP; 4745 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4746 * queues and rx flow control is disabled 4747 */ 4748 if (adapter->vfs_allocated_count || 4749 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4750 adapter->num_rx_queues > 1)) 4751 srrctl |= E1000_SRRCTL_DROP_EN; 4752 4753 wr32(E1000_SRRCTL(reg_idx), srrctl); 4754 } 4755 4756 /** 4757 * igb_configure_rx_ring - Configure a receive ring after Reset 4758 * @adapter: board private structure 4759 * @ring: receive ring to be configured 4760 * 4761 * Configure the Rx unit of the MAC after a reset. 4762 **/ 4763 void igb_configure_rx_ring(struct igb_adapter *adapter, 4764 struct igb_ring *ring) 4765 { 4766 struct e1000_hw *hw = &adapter->hw; 4767 union e1000_adv_rx_desc *rx_desc; 4768 u64 rdba = ring->dma; 4769 int reg_idx = ring->reg_idx; 4770 u32 rxdctl = 0; 4771 4772 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4773 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4774 MEM_TYPE_PAGE_SHARED, NULL)); 4775 4776 /* disable the queue */ 4777 wr32(E1000_RXDCTL(reg_idx), 0); 4778 4779 /* Set DMA base address registers */ 4780 wr32(E1000_RDBAL(reg_idx), 4781 rdba & 0x00000000ffffffffULL); 4782 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4783 wr32(E1000_RDLEN(reg_idx), 4784 ring->count * sizeof(union e1000_adv_rx_desc)); 4785 4786 /* initialize head and tail */ 4787 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4788 wr32(E1000_RDH(reg_idx), 0); 4789 writel(0, ring->tail); 4790 4791 /* set descriptor configuration */ 4792 igb_setup_srrctl(adapter, ring); 4793 4794 /* set filtering for VMDQ pools */ 4795 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4796 4797 rxdctl |= IGB_RX_PTHRESH; 4798 rxdctl |= IGB_RX_HTHRESH << 8; 4799 rxdctl |= IGB_RX_WTHRESH << 16; 4800 4801 /* initialize rx_buffer_info */ 4802 memset(ring->rx_buffer_info, 0, 4803 sizeof(struct igb_rx_buffer) * ring->count); 4804 4805 /* initialize Rx descriptor 0 */ 4806 rx_desc = IGB_RX_DESC(ring, 0); 4807 rx_desc->wb.upper.length = 0; 4808 4809 /* enable receive descriptor fetching */ 4810 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4811 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4812 } 4813 4814 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4815 struct igb_ring *rx_ring) 4816 { 4817 /* set build_skb and buffer size flags */ 4818 clear_ring_build_skb_enabled(rx_ring); 4819 clear_ring_uses_large_buffer(rx_ring); 4820 4821 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4822 return; 4823 4824 set_ring_build_skb_enabled(rx_ring); 4825 4826 #if (PAGE_SIZE < 8192) 4827 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4828 return; 4829 4830 set_ring_uses_large_buffer(rx_ring); 4831 #endif 4832 } 4833 4834 /** 4835 * igb_configure_rx - Configure receive Unit after Reset 4836 * @adapter: board private structure 4837 * 4838 * Configure the Rx unit of the MAC after a reset. 4839 **/ 4840 static void igb_configure_rx(struct igb_adapter *adapter) 4841 { 4842 int i; 4843 4844 /* set the correct pool for the PF default MAC address in entry 0 */ 4845 igb_set_default_mac_filter(adapter); 4846 4847 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4848 * the Base and Length of the Rx Descriptor Ring 4849 */ 4850 for (i = 0; i < adapter->num_rx_queues; i++) { 4851 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4852 4853 igb_set_rx_buffer_len(adapter, rx_ring); 4854 igb_configure_rx_ring(adapter, rx_ring); 4855 } 4856 } 4857 4858 /** 4859 * igb_free_tx_resources - Free Tx Resources per Queue 4860 * @tx_ring: Tx descriptor ring for a specific queue 4861 * 4862 * Free all transmit software resources 4863 **/ 4864 void igb_free_tx_resources(struct igb_ring *tx_ring) 4865 { 4866 igb_clean_tx_ring(tx_ring); 4867 4868 vfree(tx_ring->tx_buffer_info); 4869 tx_ring->tx_buffer_info = NULL; 4870 4871 /* if not set, then don't free */ 4872 if (!tx_ring->desc) 4873 return; 4874 4875 dma_free_coherent(tx_ring->dev, tx_ring->size, 4876 tx_ring->desc, tx_ring->dma); 4877 4878 tx_ring->desc = NULL; 4879 } 4880 4881 /** 4882 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4883 * @adapter: board private structure 4884 * 4885 * Free all transmit software resources 4886 **/ 4887 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4888 { 4889 int i; 4890 4891 for (i = 0; i < adapter->num_tx_queues; i++) 4892 if (adapter->tx_ring[i]) 4893 igb_free_tx_resources(adapter->tx_ring[i]); 4894 } 4895 4896 /** 4897 * igb_clean_tx_ring - Free Tx Buffers 4898 * @tx_ring: ring to be cleaned 4899 **/ 4900 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4901 { 4902 u16 i = tx_ring->next_to_clean; 4903 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4904 4905 while (i != tx_ring->next_to_use) { 4906 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4907 4908 /* Free all the Tx ring sk_buffs or xdp frames */ 4909 if (tx_buffer->type == IGB_TYPE_SKB) 4910 dev_kfree_skb_any(tx_buffer->skb); 4911 else 4912 xdp_return_frame(tx_buffer->xdpf); 4913 4914 /* unmap skb header data */ 4915 dma_unmap_single(tx_ring->dev, 4916 dma_unmap_addr(tx_buffer, dma), 4917 dma_unmap_len(tx_buffer, len), 4918 DMA_TO_DEVICE); 4919 4920 /* check for eop_desc to determine the end of the packet */ 4921 eop_desc = tx_buffer->next_to_watch; 4922 tx_desc = IGB_TX_DESC(tx_ring, i); 4923 4924 /* unmap remaining buffers */ 4925 while (tx_desc != eop_desc) { 4926 tx_buffer++; 4927 tx_desc++; 4928 i++; 4929 if (unlikely(i == tx_ring->count)) { 4930 i = 0; 4931 tx_buffer = tx_ring->tx_buffer_info; 4932 tx_desc = IGB_TX_DESC(tx_ring, 0); 4933 } 4934 4935 /* unmap any remaining paged data */ 4936 if (dma_unmap_len(tx_buffer, len)) 4937 dma_unmap_page(tx_ring->dev, 4938 dma_unmap_addr(tx_buffer, dma), 4939 dma_unmap_len(tx_buffer, len), 4940 DMA_TO_DEVICE); 4941 } 4942 4943 tx_buffer->next_to_watch = NULL; 4944 4945 /* move us one more past the eop_desc for start of next pkt */ 4946 tx_buffer++; 4947 i++; 4948 if (unlikely(i == tx_ring->count)) { 4949 i = 0; 4950 tx_buffer = tx_ring->tx_buffer_info; 4951 } 4952 } 4953 4954 /* reset BQL for queue */ 4955 netdev_tx_reset_queue(txring_txq(tx_ring)); 4956 4957 /* reset next_to_use and next_to_clean */ 4958 tx_ring->next_to_use = 0; 4959 tx_ring->next_to_clean = 0; 4960 } 4961 4962 /** 4963 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4964 * @adapter: board private structure 4965 **/ 4966 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4967 { 4968 int i; 4969 4970 for (i = 0; i < adapter->num_tx_queues; i++) 4971 if (adapter->tx_ring[i]) 4972 igb_clean_tx_ring(adapter->tx_ring[i]); 4973 } 4974 4975 /** 4976 * igb_free_rx_resources - Free Rx Resources 4977 * @rx_ring: ring to clean the resources from 4978 * 4979 * Free all receive software resources 4980 **/ 4981 void igb_free_rx_resources(struct igb_ring *rx_ring) 4982 { 4983 igb_clean_rx_ring(rx_ring); 4984 4985 rx_ring->xdp_prog = NULL; 4986 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4987 vfree(rx_ring->rx_buffer_info); 4988 rx_ring->rx_buffer_info = NULL; 4989 4990 /* if not set, then don't free */ 4991 if (!rx_ring->desc) 4992 return; 4993 4994 dma_free_coherent(rx_ring->dev, rx_ring->size, 4995 rx_ring->desc, rx_ring->dma); 4996 4997 rx_ring->desc = NULL; 4998 } 4999 5000 /** 5001 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5002 * @adapter: board private structure 5003 * 5004 * Free all receive software resources 5005 **/ 5006 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5007 { 5008 int i; 5009 5010 for (i = 0; i < adapter->num_rx_queues; i++) 5011 if (adapter->rx_ring[i]) 5012 igb_free_rx_resources(adapter->rx_ring[i]); 5013 } 5014 5015 /** 5016 * igb_clean_rx_ring - Free Rx Buffers per Queue 5017 * @rx_ring: ring to free buffers from 5018 **/ 5019 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5020 { 5021 u16 i = rx_ring->next_to_clean; 5022 5023 dev_kfree_skb(rx_ring->skb); 5024 rx_ring->skb = NULL; 5025 5026 /* Free all the Rx ring sk_buffs */ 5027 while (i != rx_ring->next_to_alloc) { 5028 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5029 5030 /* Invalidate cache lines that may have been written to by 5031 * device so that we avoid corrupting memory. 5032 */ 5033 dma_sync_single_range_for_cpu(rx_ring->dev, 5034 buffer_info->dma, 5035 buffer_info->page_offset, 5036 igb_rx_bufsz(rx_ring), 5037 DMA_FROM_DEVICE); 5038 5039 /* free resources associated with mapping */ 5040 dma_unmap_page_attrs(rx_ring->dev, 5041 buffer_info->dma, 5042 igb_rx_pg_size(rx_ring), 5043 DMA_FROM_DEVICE, 5044 IGB_RX_DMA_ATTR); 5045 __page_frag_cache_drain(buffer_info->page, 5046 buffer_info->pagecnt_bias); 5047 5048 i++; 5049 if (i == rx_ring->count) 5050 i = 0; 5051 } 5052 5053 rx_ring->next_to_alloc = 0; 5054 rx_ring->next_to_clean = 0; 5055 rx_ring->next_to_use = 0; 5056 } 5057 5058 /** 5059 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5060 * @adapter: board private structure 5061 **/ 5062 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5063 { 5064 int i; 5065 5066 for (i = 0; i < adapter->num_rx_queues; i++) 5067 if (adapter->rx_ring[i]) 5068 igb_clean_rx_ring(adapter->rx_ring[i]); 5069 } 5070 5071 /** 5072 * igb_set_mac - Change the Ethernet Address of the NIC 5073 * @netdev: network interface device structure 5074 * @p: pointer to an address structure 5075 * 5076 * Returns 0 on success, negative on failure 5077 **/ 5078 static int igb_set_mac(struct net_device *netdev, void *p) 5079 { 5080 struct igb_adapter *adapter = netdev_priv(netdev); 5081 struct e1000_hw *hw = &adapter->hw; 5082 struct sockaddr *addr = p; 5083 5084 if (!is_valid_ether_addr(addr->sa_data)) 5085 return -EADDRNOTAVAIL; 5086 5087 eth_hw_addr_set(netdev, addr->sa_data); 5088 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5089 5090 /* set the correct pool for the new PF MAC address in entry 0 */ 5091 igb_set_default_mac_filter(adapter); 5092 5093 return 0; 5094 } 5095 5096 /** 5097 * igb_write_mc_addr_list - write multicast addresses to MTA 5098 * @netdev: network interface device structure 5099 * 5100 * Writes multicast address list to the MTA hash table. 5101 * Returns: -ENOMEM on failure 5102 * 0 on no addresses written 5103 * X on writing X addresses to MTA 5104 **/ 5105 static int igb_write_mc_addr_list(struct net_device *netdev) 5106 { 5107 struct igb_adapter *adapter = netdev_priv(netdev); 5108 struct e1000_hw *hw = &adapter->hw; 5109 struct netdev_hw_addr *ha; 5110 u8 *mta_list; 5111 int i; 5112 5113 if (netdev_mc_empty(netdev)) { 5114 /* nothing to program, so clear mc list */ 5115 igb_update_mc_addr_list(hw, NULL, 0); 5116 igb_restore_vf_multicasts(adapter); 5117 return 0; 5118 } 5119 5120 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5121 if (!mta_list) 5122 return -ENOMEM; 5123 5124 /* The shared function expects a packed array of only addresses. */ 5125 i = 0; 5126 netdev_for_each_mc_addr(ha, netdev) 5127 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5128 5129 igb_update_mc_addr_list(hw, mta_list, i); 5130 kfree(mta_list); 5131 5132 return netdev_mc_count(netdev); 5133 } 5134 5135 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5136 { 5137 struct e1000_hw *hw = &adapter->hw; 5138 u32 i, pf_id; 5139 5140 switch (hw->mac.type) { 5141 case e1000_i210: 5142 case e1000_i211: 5143 case e1000_i350: 5144 /* VLAN filtering needed for VLAN prio filter */ 5145 if (adapter->netdev->features & NETIF_F_NTUPLE) 5146 break; 5147 fallthrough; 5148 case e1000_82576: 5149 case e1000_82580: 5150 case e1000_i354: 5151 /* VLAN filtering needed for pool filtering */ 5152 if (adapter->vfs_allocated_count) 5153 break; 5154 fallthrough; 5155 default: 5156 return 1; 5157 } 5158 5159 /* We are already in VLAN promisc, nothing to do */ 5160 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5161 return 0; 5162 5163 if (!adapter->vfs_allocated_count) 5164 goto set_vfta; 5165 5166 /* Add PF to all active pools */ 5167 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5168 5169 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5170 u32 vlvf = rd32(E1000_VLVF(i)); 5171 5172 vlvf |= BIT(pf_id); 5173 wr32(E1000_VLVF(i), vlvf); 5174 } 5175 5176 set_vfta: 5177 /* Set all bits in the VLAN filter table array */ 5178 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5179 hw->mac.ops.write_vfta(hw, i, ~0U); 5180 5181 /* Set flag so we don't redo unnecessary work */ 5182 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5183 5184 return 0; 5185 } 5186 5187 #define VFTA_BLOCK_SIZE 8 5188 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5189 { 5190 struct e1000_hw *hw = &adapter->hw; 5191 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5192 u32 vid_start = vfta_offset * 32; 5193 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5194 u32 i, vid, word, bits, pf_id; 5195 5196 /* guarantee that we don't scrub out management VLAN */ 5197 vid = adapter->mng_vlan_id; 5198 if (vid >= vid_start && vid < vid_end) 5199 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5200 5201 if (!adapter->vfs_allocated_count) 5202 goto set_vfta; 5203 5204 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5205 5206 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5207 u32 vlvf = rd32(E1000_VLVF(i)); 5208 5209 /* pull VLAN ID from VLVF */ 5210 vid = vlvf & VLAN_VID_MASK; 5211 5212 /* only concern ourselves with a certain range */ 5213 if (vid < vid_start || vid >= vid_end) 5214 continue; 5215 5216 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5217 /* record VLAN ID in VFTA */ 5218 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5219 5220 /* if PF is part of this then continue */ 5221 if (test_bit(vid, adapter->active_vlans)) 5222 continue; 5223 } 5224 5225 /* remove PF from the pool */ 5226 bits = ~BIT(pf_id); 5227 bits &= rd32(E1000_VLVF(i)); 5228 wr32(E1000_VLVF(i), bits); 5229 } 5230 5231 set_vfta: 5232 /* extract values from active_vlans and write back to VFTA */ 5233 for (i = VFTA_BLOCK_SIZE; i--;) { 5234 vid = (vfta_offset + i) * 32; 5235 word = vid / BITS_PER_LONG; 5236 bits = vid % BITS_PER_LONG; 5237 5238 vfta[i] |= adapter->active_vlans[word] >> bits; 5239 5240 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5241 } 5242 } 5243 5244 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5245 { 5246 u32 i; 5247 5248 /* We are not in VLAN promisc, nothing to do */ 5249 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5250 return; 5251 5252 /* Set flag so we don't redo unnecessary work */ 5253 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5254 5255 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5256 igb_scrub_vfta(adapter, i); 5257 } 5258 5259 /** 5260 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5261 * @netdev: network interface device structure 5262 * 5263 * The set_rx_mode entry point is called whenever the unicast or multicast 5264 * address lists or the network interface flags are updated. This routine is 5265 * responsible for configuring the hardware for proper unicast, multicast, 5266 * promiscuous mode, and all-multi behavior. 5267 **/ 5268 static void igb_set_rx_mode(struct net_device *netdev) 5269 { 5270 struct igb_adapter *adapter = netdev_priv(netdev); 5271 struct e1000_hw *hw = &adapter->hw; 5272 unsigned int vfn = adapter->vfs_allocated_count; 5273 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5274 int count; 5275 5276 /* Check for Promiscuous and All Multicast modes */ 5277 if (netdev->flags & IFF_PROMISC) { 5278 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5279 vmolr |= E1000_VMOLR_MPME; 5280 5281 /* enable use of UTA filter to force packets to default pool */ 5282 if (hw->mac.type == e1000_82576) 5283 vmolr |= E1000_VMOLR_ROPE; 5284 } else { 5285 if (netdev->flags & IFF_ALLMULTI) { 5286 rctl |= E1000_RCTL_MPE; 5287 vmolr |= E1000_VMOLR_MPME; 5288 } else { 5289 /* Write addresses to the MTA, if the attempt fails 5290 * then we should just turn on promiscuous mode so 5291 * that we can at least receive multicast traffic 5292 */ 5293 count = igb_write_mc_addr_list(netdev); 5294 if (count < 0) { 5295 rctl |= E1000_RCTL_MPE; 5296 vmolr |= E1000_VMOLR_MPME; 5297 } else if (count) { 5298 vmolr |= E1000_VMOLR_ROMPE; 5299 } 5300 } 5301 } 5302 5303 /* Write addresses to available RAR registers, if there is not 5304 * sufficient space to store all the addresses then enable 5305 * unicast promiscuous mode 5306 */ 5307 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5308 rctl |= E1000_RCTL_UPE; 5309 vmolr |= E1000_VMOLR_ROPE; 5310 } 5311 5312 /* enable VLAN filtering by default */ 5313 rctl |= E1000_RCTL_VFE; 5314 5315 /* disable VLAN filtering for modes that require it */ 5316 if ((netdev->flags & IFF_PROMISC) || 5317 (netdev->features & NETIF_F_RXALL)) { 5318 /* if we fail to set all rules then just clear VFE */ 5319 if (igb_vlan_promisc_enable(adapter)) 5320 rctl &= ~E1000_RCTL_VFE; 5321 } else { 5322 igb_vlan_promisc_disable(adapter); 5323 } 5324 5325 /* update state of unicast, multicast, and VLAN filtering modes */ 5326 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5327 E1000_RCTL_VFE); 5328 wr32(E1000_RCTL, rctl); 5329 5330 #if (PAGE_SIZE < 8192) 5331 if (!adapter->vfs_allocated_count) { 5332 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5333 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5334 } 5335 #endif 5336 wr32(E1000_RLPML, rlpml); 5337 5338 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5339 * the VMOLR to enable the appropriate modes. Without this workaround 5340 * we will have issues with VLAN tag stripping not being done for frames 5341 * that are only arriving because we are the default pool 5342 */ 5343 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5344 return; 5345 5346 /* set UTA to appropriate mode */ 5347 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5348 5349 vmolr |= rd32(E1000_VMOLR(vfn)) & 5350 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5351 5352 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5353 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5354 #if (PAGE_SIZE < 8192) 5355 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5356 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5357 else 5358 #endif 5359 vmolr |= MAX_JUMBO_FRAME_SIZE; 5360 vmolr |= E1000_VMOLR_LPE; 5361 5362 wr32(E1000_VMOLR(vfn), vmolr); 5363 5364 igb_restore_vf_multicasts(adapter); 5365 } 5366 5367 static void igb_check_wvbr(struct igb_adapter *adapter) 5368 { 5369 struct e1000_hw *hw = &adapter->hw; 5370 u32 wvbr = 0; 5371 5372 switch (hw->mac.type) { 5373 case e1000_82576: 5374 case e1000_i350: 5375 wvbr = rd32(E1000_WVBR); 5376 if (!wvbr) 5377 return; 5378 break; 5379 default: 5380 break; 5381 } 5382 5383 adapter->wvbr |= wvbr; 5384 } 5385 5386 #define IGB_STAGGERED_QUEUE_OFFSET 8 5387 5388 static void igb_spoof_check(struct igb_adapter *adapter) 5389 { 5390 int j; 5391 5392 if (!adapter->wvbr) 5393 return; 5394 5395 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5396 if (adapter->wvbr & BIT(j) || 5397 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5398 dev_warn(&adapter->pdev->dev, 5399 "Spoof event(s) detected on VF %d\n", j); 5400 adapter->wvbr &= 5401 ~(BIT(j) | 5402 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5403 } 5404 } 5405 } 5406 5407 /* Need to wait a few seconds after link up to get diagnostic information from 5408 * the phy 5409 */ 5410 static void igb_update_phy_info(struct timer_list *t) 5411 { 5412 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5413 igb_get_phy_info(&adapter->hw); 5414 } 5415 5416 /** 5417 * igb_has_link - check shared code for link and determine up/down 5418 * @adapter: pointer to driver private info 5419 **/ 5420 bool igb_has_link(struct igb_adapter *adapter) 5421 { 5422 struct e1000_hw *hw = &adapter->hw; 5423 bool link_active = false; 5424 5425 /* get_link_status is set on LSC (link status) interrupt or 5426 * rx sequence error interrupt. get_link_status will stay 5427 * false until the e1000_check_for_link establishes link 5428 * for copper adapters ONLY 5429 */ 5430 switch (hw->phy.media_type) { 5431 case e1000_media_type_copper: 5432 if (!hw->mac.get_link_status) 5433 return true; 5434 fallthrough; 5435 case e1000_media_type_internal_serdes: 5436 hw->mac.ops.check_for_link(hw); 5437 link_active = !hw->mac.get_link_status; 5438 break; 5439 default: 5440 case e1000_media_type_unknown: 5441 break; 5442 } 5443 5444 if (((hw->mac.type == e1000_i210) || 5445 (hw->mac.type == e1000_i211)) && 5446 (hw->phy.id == I210_I_PHY_ID)) { 5447 if (!netif_carrier_ok(adapter->netdev)) { 5448 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5449 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5450 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5451 adapter->link_check_timeout = jiffies; 5452 } 5453 } 5454 5455 return link_active; 5456 } 5457 5458 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5459 { 5460 bool ret = false; 5461 u32 ctrl_ext, thstat; 5462 5463 /* check for thermal sensor event on i350 copper only */ 5464 if (hw->mac.type == e1000_i350) { 5465 thstat = rd32(E1000_THSTAT); 5466 ctrl_ext = rd32(E1000_CTRL_EXT); 5467 5468 if ((hw->phy.media_type == e1000_media_type_copper) && 5469 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5470 ret = !!(thstat & event); 5471 } 5472 5473 return ret; 5474 } 5475 5476 /** 5477 * igb_check_lvmmc - check for malformed packets received 5478 * and indicated in LVMMC register 5479 * @adapter: pointer to adapter 5480 **/ 5481 static void igb_check_lvmmc(struct igb_adapter *adapter) 5482 { 5483 struct e1000_hw *hw = &adapter->hw; 5484 u32 lvmmc; 5485 5486 lvmmc = rd32(E1000_LVMMC); 5487 if (lvmmc) { 5488 if (unlikely(net_ratelimit())) { 5489 netdev_warn(adapter->netdev, 5490 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5491 lvmmc); 5492 } 5493 } 5494 } 5495 5496 /** 5497 * igb_watchdog - Timer Call-back 5498 * @t: pointer to timer_list containing our private info pointer 5499 **/ 5500 static void igb_watchdog(struct timer_list *t) 5501 { 5502 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5503 /* Do the rest outside of interrupt context */ 5504 schedule_work(&adapter->watchdog_task); 5505 } 5506 5507 static void igb_watchdog_task(struct work_struct *work) 5508 { 5509 struct igb_adapter *adapter = container_of(work, 5510 struct igb_adapter, 5511 watchdog_task); 5512 struct e1000_hw *hw = &adapter->hw; 5513 struct e1000_phy_info *phy = &hw->phy; 5514 struct net_device *netdev = adapter->netdev; 5515 u32 link; 5516 int i; 5517 u32 connsw; 5518 u16 phy_data, retry_count = 20; 5519 5520 link = igb_has_link(adapter); 5521 5522 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5523 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5524 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5525 else 5526 link = false; 5527 } 5528 5529 /* Force link down if we have fiber to swap to */ 5530 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5531 if (hw->phy.media_type == e1000_media_type_copper) { 5532 connsw = rd32(E1000_CONNSW); 5533 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5534 link = 0; 5535 } 5536 } 5537 if (link) { 5538 /* Perform a reset if the media type changed. */ 5539 if (hw->dev_spec._82575.media_changed) { 5540 hw->dev_spec._82575.media_changed = false; 5541 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5542 igb_reset(adapter); 5543 } 5544 /* Cancel scheduled suspend requests. */ 5545 pm_runtime_resume(netdev->dev.parent); 5546 5547 if (!netif_carrier_ok(netdev)) { 5548 u32 ctrl; 5549 5550 hw->mac.ops.get_speed_and_duplex(hw, 5551 &adapter->link_speed, 5552 &adapter->link_duplex); 5553 5554 ctrl = rd32(E1000_CTRL); 5555 /* Links status message must follow this format */ 5556 netdev_info(netdev, 5557 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5558 netdev->name, 5559 adapter->link_speed, 5560 adapter->link_duplex == FULL_DUPLEX ? 5561 "Full" : "Half", 5562 (ctrl & E1000_CTRL_TFCE) && 5563 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5564 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5565 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5566 5567 /* disable EEE if enabled */ 5568 if ((adapter->flags & IGB_FLAG_EEE) && 5569 (adapter->link_duplex == HALF_DUPLEX)) { 5570 dev_info(&adapter->pdev->dev, 5571 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5572 adapter->hw.dev_spec._82575.eee_disable = true; 5573 adapter->flags &= ~IGB_FLAG_EEE; 5574 } 5575 5576 /* check if SmartSpeed worked */ 5577 igb_check_downshift(hw); 5578 if (phy->speed_downgraded) 5579 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5580 5581 /* check for thermal sensor event */ 5582 if (igb_thermal_sensor_event(hw, 5583 E1000_THSTAT_LINK_THROTTLE)) 5584 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5585 5586 /* adjust timeout factor according to speed/duplex */ 5587 adapter->tx_timeout_factor = 1; 5588 switch (adapter->link_speed) { 5589 case SPEED_10: 5590 adapter->tx_timeout_factor = 14; 5591 break; 5592 case SPEED_100: 5593 /* maybe add some timeout factor ? */ 5594 break; 5595 } 5596 5597 if (adapter->link_speed != SPEED_1000 || 5598 !hw->phy.ops.read_reg) 5599 goto no_wait; 5600 5601 /* wait for Remote receiver status OK */ 5602 retry_read_status: 5603 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5604 &phy_data)) { 5605 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5606 retry_count) { 5607 msleep(100); 5608 retry_count--; 5609 goto retry_read_status; 5610 } else if (!retry_count) { 5611 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5612 } 5613 } else { 5614 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5615 } 5616 no_wait: 5617 netif_carrier_on(netdev); 5618 5619 igb_ping_all_vfs(adapter); 5620 igb_check_vf_rate_limit(adapter); 5621 5622 /* link state has changed, schedule phy info update */ 5623 if (!test_bit(__IGB_DOWN, &adapter->state)) 5624 mod_timer(&adapter->phy_info_timer, 5625 round_jiffies(jiffies + 2 * HZ)); 5626 } 5627 } else { 5628 if (netif_carrier_ok(netdev)) { 5629 adapter->link_speed = 0; 5630 adapter->link_duplex = 0; 5631 5632 /* check for thermal sensor event */ 5633 if (igb_thermal_sensor_event(hw, 5634 E1000_THSTAT_PWR_DOWN)) { 5635 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5636 } 5637 5638 /* Links status message must follow this format */ 5639 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5640 netdev->name); 5641 netif_carrier_off(netdev); 5642 5643 igb_ping_all_vfs(adapter); 5644 5645 /* link state has changed, schedule phy info update */ 5646 if (!test_bit(__IGB_DOWN, &adapter->state)) 5647 mod_timer(&adapter->phy_info_timer, 5648 round_jiffies(jiffies + 2 * HZ)); 5649 5650 /* link is down, time to check for alternate media */ 5651 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5652 igb_check_swap_media(adapter); 5653 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5654 schedule_work(&adapter->reset_task); 5655 /* return immediately */ 5656 return; 5657 } 5658 } 5659 pm_schedule_suspend(netdev->dev.parent, 5660 MSEC_PER_SEC * 5); 5661 5662 /* also check for alternate media here */ 5663 } else if (!netif_carrier_ok(netdev) && 5664 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5665 igb_check_swap_media(adapter); 5666 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5667 schedule_work(&adapter->reset_task); 5668 /* return immediately */ 5669 return; 5670 } 5671 } 5672 } 5673 5674 spin_lock(&adapter->stats64_lock); 5675 igb_update_stats(adapter); 5676 spin_unlock(&adapter->stats64_lock); 5677 5678 for (i = 0; i < adapter->num_tx_queues; i++) { 5679 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5680 if (!netif_carrier_ok(netdev)) { 5681 /* We've lost link, so the controller stops DMA, 5682 * but we've got queued Tx work that's never going 5683 * to get done, so reset controller to flush Tx. 5684 * (Do the reset outside of interrupt context). 5685 */ 5686 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5687 adapter->tx_timeout_count++; 5688 schedule_work(&adapter->reset_task); 5689 /* return immediately since reset is imminent */ 5690 return; 5691 } 5692 } 5693 5694 /* Force detection of hung controller every watchdog period */ 5695 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5696 } 5697 5698 /* Cause software interrupt to ensure Rx ring is cleaned */ 5699 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5700 u32 eics = 0; 5701 5702 for (i = 0; i < adapter->num_q_vectors; i++) 5703 eics |= adapter->q_vector[i]->eims_value; 5704 wr32(E1000_EICS, eics); 5705 } else { 5706 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5707 } 5708 5709 igb_spoof_check(adapter); 5710 igb_ptp_rx_hang(adapter); 5711 igb_ptp_tx_hang(adapter); 5712 5713 /* Check LVMMC register on i350/i354 only */ 5714 if ((adapter->hw.mac.type == e1000_i350) || 5715 (adapter->hw.mac.type == e1000_i354)) 5716 igb_check_lvmmc(adapter); 5717 5718 /* Reset the timer */ 5719 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5720 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5721 mod_timer(&adapter->watchdog_timer, 5722 round_jiffies(jiffies + HZ)); 5723 else 5724 mod_timer(&adapter->watchdog_timer, 5725 round_jiffies(jiffies + 2 * HZ)); 5726 } 5727 } 5728 5729 enum latency_range { 5730 lowest_latency = 0, 5731 low_latency = 1, 5732 bulk_latency = 2, 5733 latency_invalid = 255 5734 }; 5735 5736 /** 5737 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5738 * @q_vector: pointer to q_vector 5739 * 5740 * Stores a new ITR value based on strictly on packet size. This 5741 * algorithm is less sophisticated than that used in igb_update_itr, 5742 * due to the difficulty of synchronizing statistics across multiple 5743 * receive rings. The divisors and thresholds used by this function 5744 * were determined based on theoretical maximum wire speed and testing 5745 * data, in order to minimize response time while increasing bulk 5746 * throughput. 5747 * This functionality is controlled by ethtool's coalescing settings. 5748 * NOTE: This function is called only when operating in a multiqueue 5749 * receive environment. 5750 **/ 5751 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5752 { 5753 int new_val = q_vector->itr_val; 5754 int avg_wire_size = 0; 5755 struct igb_adapter *adapter = q_vector->adapter; 5756 unsigned int packets; 5757 5758 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5759 * ints/sec - ITR timer value of 120 ticks. 5760 */ 5761 if (adapter->link_speed != SPEED_1000) { 5762 new_val = IGB_4K_ITR; 5763 goto set_itr_val; 5764 } 5765 5766 packets = q_vector->rx.total_packets; 5767 if (packets) 5768 avg_wire_size = q_vector->rx.total_bytes / packets; 5769 5770 packets = q_vector->tx.total_packets; 5771 if (packets) 5772 avg_wire_size = max_t(u32, avg_wire_size, 5773 q_vector->tx.total_bytes / packets); 5774 5775 /* if avg_wire_size isn't set no work was done */ 5776 if (!avg_wire_size) 5777 goto clear_counts; 5778 5779 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5780 avg_wire_size += 24; 5781 5782 /* Don't starve jumbo frames */ 5783 avg_wire_size = min(avg_wire_size, 3000); 5784 5785 /* Give a little boost to mid-size frames */ 5786 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5787 new_val = avg_wire_size / 3; 5788 else 5789 new_val = avg_wire_size / 2; 5790 5791 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5792 if (new_val < IGB_20K_ITR && 5793 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5794 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5795 new_val = IGB_20K_ITR; 5796 5797 set_itr_val: 5798 if (new_val != q_vector->itr_val) { 5799 q_vector->itr_val = new_val; 5800 q_vector->set_itr = 1; 5801 } 5802 clear_counts: 5803 q_vector->rx.total_bytes = 0; 5804 q_vector->rx.total_packets = 0; 5805 q_vector->tx.total_bytes = 0; 5806 q_vector->tx.total_packets = 0; 5807 } 5808 5809 /** 5810 * igb_update_itr - update the dynamic ITR value based on statistics 5811 * @q_vector: pointer to q_vector 5812 * @ring_container: ring info to update the itr for 5813 * 5814 * Stores a new ITR value based on packets and byte 5815 * counts during the last interrupt. The advantage of per interrupt 5816 * computation is faster updates and more accurate ITR for the current 5817 * traffic pattern. Constants in this function were computed 5818 * based on theoretical maximum wire speed and thresholds were set based 5819 * on testing data as well as attempting to minimize response time 5820 * while increasing bulk throughput. 5821 * This functionality is controlled by ethtool's coalescing settings. 5822 * NOTE: These calculations are only valid when operating in a single- 5823 * queue environment. 5824 **/ 5825 static void igb_update_itr(struct igb_q_vector *q_vector, 5826 struct igb_ring_container *ring_container) 5827 { 5828 unsigned int packets = ring_container->total_packets; 5829 unsigned int bytes = ring_container->total_bytes; 5830 u8 itrval = ring_container->itr; 5831 5832 /* no packets, exit with status unchanged */ 5833 if (packets == 0) 5834 return; 5835 5836 switch (itrval) { 5837 case lowest_latency: 5838 /* handle TSO and jumbo frames */ 5839 if (bytes/packets > 8000) 5840 itrval = bulk_latency; 5841 else if ((packets < 5) && (bytes > 512)) 5842 itrval = low_latency; 5843 break; 5844 case low_latency: /* 50 usec aka 20000 ints/s */ 5845 if (bytes > 10000) { 5846 /* this if handles the TSO accounting */ 5847 if (bytes/packets > 8000) 5848 itrval = bulk_latency; 5849 else if ((packets < 10) || ((bytes/packets) > 1200)) 5850 itrval = bulk_latency; 5851 else if ((packets > 35)) 5852 itrval = lowest_latency; 5853 } else if (bytes/packets > 2000) { 5854 itrval = bulk_latency; 5855 } else if (packets <= 2 && bytes < 512) { 5856 itrval = lowest_latency; 5857 } 5858 break; 5859 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5860 if (bytes > 25000) { 5861 if (packets > 35) 5862 itrval = low_latency; 5863 } else if (bytes < 1500) { 5864 itrval = low_latency; 5865 } 5866 break; 5867 } 5868 5869 /* clear work counters since we have the values we need */ 5870 ring_container->total_bytes = 0; 5871 ring_container->total_packets = 0; 5872 5873 /* write updated itr to ring container */ 5874 ring_container->itr = itrval; 5875 } 5876 5877 static void igb_set_itr(struct igb_q_vector *q_vector) 5878 { 5879 struct igb_adapter *adapter = q_vector->adapter; 5880 u32 new_itr = q_vector->itr_val; 5881 u8 current_itr = 0; 5882 5883 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5884 if (adapter->link_speed != SPEED_1000) { 5885 current_itr = 0; 5886 new_itr = IGB_4K_ITR; 5887 goto set_itr_now; 5888 } 5889 5890 igb_update_itr(q_vector, &q_vector->tx); 5891 igb_update_itr(q_vector, &q_vector->rx); 5892 5893 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5894 5895 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5896 if (current_itr == lowest_latency && 5897 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5898 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5899 current_itr = low_latency; 5900 5901 switch (current_itr) { 5902 /* counts and packets in update_itr are dependent on these numbers */ 5903 case lowest_latency: 5904 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5905 break; 5906 case low_latency: 5907 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5908 break; 5909 case bulk_latency: 5910 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5911 break; 5912 default: 5913 break; 5914 } 5915 5916 set_itr_now: 5917 if (new_itr != q_vector->itr_val) { 5918 /* this attempts to bias the interrupt rate towards Bulk 5919 * by adding intermediate steps when interrupt rate is 5920 * increasing 5921 */ 5922 new_itr = new_itr > q_vector->itr_val ? 5923 max((new_itr * q_vector->itr_val) / 5924 (new_itr + (q_vector->itr_val >> 2)), 5925 new_itr) : new_itr; 5926 /* Don't write the value here; it resets the adapter's 5927 * internal timer, and causes us to delay far longer than 5928 * we should between interrupts. Instead, we write the ITR 5929 * value at the beginning of the next interrupt so the timing 5930 * ends up being correct. 5931 */ 5932 q_vector->itr_val = new_itr; 5933 q_vector->set_itr = 1; 5934 } 5935 } 5936 5937 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5938 struct igb_tx_buffer *first, 5939 u32 vlan_macip_lens, u32 type_tucmd, 5940 u32 mss_l4len_idx) 5941 { 5942 struct e1000_adv_tx_context_desc *context_desc; 5943 u16 i = tx_ring->next_to_use; 5944 struct timespec64 ts; 5945 5946 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5947 5948 i++; 5949 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5950 5951 /* set bits to identify this as an advanced context descriptor */ 5952 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5953 5954 /* For 82575, context index must be unique per ring. */ 5955 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5956 mss_l4len_idx |= tx_ring->reg_idx << 4; 5957 5958 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5959 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5960 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5961 5962 /* We assume there is always a valid tx time available. Invalid times 5963 * should have been handled by the upper layers. 5964 */ 5965 if (tx_ring->launchtime_enable) { 5966 ts = ktime_to_timespec64(first->skb->tstamp); 5967 skb_txtime_consumed(first->skb); 5968 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5969 } else { 5970 context_desc->seqnum_seed = 0; 5971 } 5972 } 5973 5974 static int igb_tso(struct igb_ring *tx_ring, 5975 struct igb_tx_buffer *first, 5976 u8 *hdr_len) 5977 { 5978 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5979 struct sk_buff *skb = first->skb; 5980 union { 5981 struct iphdr *v4; 5982 struct ipv6hdr *v6; 5983 unsigned char *hdr; 5984 } ip; 5985 union { 5986 struct tcphdr *tcp; 5987 struct udphdr *udp; 5988 unsigned char *hdr; 5989 } l4; 5990 u32 paylen, l4_offset; 5991 int err; 5992 5993 if (skb->ip_summed != CHECKSUM_PARTIAL) 5994 return 0; 5995 5996 if (!skb_is_gso(skb)) 5997 return 0; 5998 5999 err = skb_cow_head(skb, 0); 6000 if (err < 0) 6001 return err; 6002 6003 ip.hdr = skb_network_header(skb); 6004 l4.hdr = skb_checksum_start(skb); 6005 6006 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6007 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6008 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6009 6010 /* initialize outer IP header fields */ 6011 if (ip.v4->version == 4) { 6012 unsigned char *csum_start = skb_checksum_start(skb); 6013 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6014 6015 /* IP header will have to cancel out any data that 6016 * is not a part of the outer IP header 6017 */ 6018 ip.v4->check = csum_fold(csum_partial(trans_start, 6019 csum_start - trans_start, 6020 0)); 6021 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6022 6023 ip.v4->tot_len = 0; 6024 first->tx_flags |= IGB_TX_FLAGS_TSO | 6025 IGB_TX_FLAGS_CSUM | 6026 IGB_TX_FLAGS_IPV4; 6027 } else { 6028 ip.v6->payload_len = 0; 6029 first->tx_flags |= IGB_TX_FLAGS_TSO | 6030 IGB_TX_FLAGS_CSUM; 6031 } 6032 6033 /* determine offset of inner transport header */ 6034 l4_offset = l4.hdr - skb->data; 6035 6036 /* remove payload length from inner checksum */ 6037 paylen = skb->len - l4_offset; 6038 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6039 /* compute length of segmentation header */ 6040 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6041 csum_replace_by_diff(&l4.tcp->check, 6042 (__force __wsum)htonl(paylen)); 6043 } else { 6044 /* compute length of segmentation header */ 6045 *hdr_len = sizeof(*l4.udp) + l4_offset; 6046 csum_replace_by_diff(&l4.udp->check, 6047 (__force __wsum)htonl(paylen)); 6048 } 6049 6050 /* update gso size and bytecount with header size */ 6051 first->gso_segs = skb_shinfo(skb)->gso_segs; 6052 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6053 6054 /* MSS L4LEN IDX */ 6055 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6056 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6057 6058 /* VLAN MACLEN IPLEN */ 6059 vlan_macip_lens = l4.hdr - ip.hdr; 6060 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6061 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6062 6063 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6064 type_tucmd, mss_l4len_idx); 6065 6066 return 1; 6067 } 6068 6069 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6070 { 6071 struct sk_buff *skb = first->skb; 6072 u32 vlan_macip_lens = 0; 6073 u32 type_tucmd = 0; 6074 6075 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6076 csum_failed: 6077 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6078 !tx_ring->launchtime_enable) 6079 return; 6080 goto no_csum; 6081 } 6082 6083 switch (skb->csum_offset) { 6084 case offsetof(struct tcphdr, check): 6085 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6086 fallthrough; 6087 case offsetof(struct udphdr, check): 6088 break; 6089 case offsetof(struct sctphdr, checksum): 6090 /* validate that this is actually an SCTP request */ 6091 if (skb_csum_is_sctp(skb)) { 6092 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6093 break; 6094 } 6095 fallthrough; 6096 default: 6097 skb_checksum_help(skb); 6098 goto csum_failed; 6099 } 6100 6101 /* update TX checksum flag */ 6102 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6103 vlan_macip_lens = skb_checksum_start_offset(skb) - 6104 skb_network_offset(skb); 6105 no_csum: 6106 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6107 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6108 6109 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6110 } 6111 6112 #define IGB_SET_FLAG(_input, _flag, _result) \ 6113 ((_flag <= _result) ? \ 6114 ((u32)(_input & _flag) * (_result / _flag)) : \ 6115 ((u32)(_input & _flag) / (_flag / _result))) 6116 6117 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6118 { 6119 /* set type for advanced descriptor with frame checksum insertion */ 6120 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6121 E1000_ADVTXD_DCMD_DEXT | 6122 E1000_ADVTXD_DCMD_IFCS; 6123 6124 /* set HW vlan bit if vlan is present */ 6125 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6126 (E1000_ADVTXD_DCMD_VLE)); 6127 6128 /* set segmentation bits for TSO */ 6129 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6130 (E1000_ADVTXD_DCMD_TSE)); 6131 6132 /* set timestamp bit if present */ 6133 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6134 (E1000_ADVTXD_MAC_TSTAMP)); 6135 6136 /* insert frame checksum */ 6137 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6138 6139 return cmd_type; 6140 } 6141 6142 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6143 union e1000_adv_tx_desc *tx_desc, 6144 u32 tx_flags, unsigned int paylen) 6145 { 6146 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6147 6148 /* 82575 requires a unique index per ring */ 6149 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6150 olinfo_status |= tx_ring->reg_idx << 4; 6151 6152 /* insert L4 checksum */ 6153 olinfo_status |= IGB_SET_FLAG(tx_flags, 6154 IGB_TX_FLAGS_CSUM, 6155 (E1000_TXD_POPTS_TXSM << 8)); 6156 6157 /* insert IPv4 checksum */ 6158 olinfo_status |= IGB_SET_FLAG(tx_flags, 6159 IGB_TX_FLAGS_IPV4, 6160 (E1000_TXD_POPTS_IXSM << 8)); 6161 6162 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6163 } 6164 6165 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6166 { 6167 struct net_device *netdev = tx_ring->netdev; 6168 6169 netif_stop_subqueue(netdev, tx_ring->queue_index); 6170 6171 /* Herbert's original patch had: 6172 * smp_mb__after_netif_stop_queue(); 6173 * but since that doesn't exist yet, just open code it. 6174 */ 6175 smp_mb(); 6176 6177 /* We need to check again in a case another CPU has just 6178 * made room available. 6179 */ 6180 if (igb_desc_unused(tx_ring) < size) 6181 return -EBUSY; 6182 6183 /* A reprieve! */ 6184 netif_wake_subqueue(netdev, tx_ring->queue_index); 6185 6186 u64_stats_update_begin(&tx_ring->tx_syncp2); 6187 tx_ring->tx_stats.restart_queue2++; 6188 u64_stats_update_end(&tx_ring->tx_syncp2); 6189 6190 return 0; 6191 } 6192 6193 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6194 { 6195 if (igb_desc_unused(tx_ring) >= size) 6196 return 0; 6197 return __igb_maybe_stop_tx(tx_ring, size); 6198 } 6199 6200 static int igb_tx_map(struct igb_ring *tx_ring, 6201 struct igb_tx_buffer *first, 6202 const u8 hdr_len) 6203 { 6204 struct sk_buff *skb = first->skb; 6205 struct igb_tx_buffer *tx_buffer; 6206 union e1000_adv_tx_desc *tx_desc; 6207 skb_frag_t *frag; 6208 dma_addr_t dma; 6209 unsigned int data_len, size; 6210 u32 tx_flags = first->tx_flags; 6211 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6212 u16 i = tx_ring->next_to_use; 6213 6214 tx_desc = IGB_TX_DESC(tx_ring, i); 6215 6216 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6217 6218 size = skb_headlen(skb); 6219 data_len = skb->data_len; 6220 6221 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6222 6223 tx_buffer = first; 6224 6225 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6226 if (dma_mapping_error(tx_ring->dev, dma)) 6227 goto dma_error; 6228 6229 /* record length, and DMA address */ 6230 dma_unmap_len_set(tx_buffer, len, size); 6231 dma_unmap_addr_set(tx_buffer, dma, dma); 6232 6233 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6234 6235 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6236 tx_desc->read.cmd_type_len = 6237 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6238 6239 i++; 6240 tx_desc++; 6241 if (i == tx_ring->count) { 6242 tx_desc = IGB_TX_DESC(tx_ring, 0); 6243 i = 0; 6244 } 6245 tx_desc->read.olinfo_status = 0; 6246 6247 dma += IGB_MAX_DATA_PER_TXD; 6248 size -= IGB_MAX_DATA_PER_TXD; 6249 6250 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6251 } 6252 6253 if (likely(!data_len)) 6254 break; 6255 6256 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6257 6258 i++; 6259 tx_desc++; 6260 if (i == tx_ring->count) { 6261 tx_desc = IGB_TX_DESC(tx_ring, 0); 6262 i = 0; 6263 } 6264 tx_desc->read.olinfo_status = 0; 6265 6266 size = skb_frag_size(frag); 6267 data_len -= size; 6268 6269 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6270 size, DMA_TO_DEVICE); 6271 6272 tx_buffer = &tx_ring->tx_buffer_info[i]; 6273 } 6274 6275 /* write last descriptor with RS and EOP bits */ 6276 cmd_type |= size | IGB_TXD_DCMD; 6277 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6278 6279 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6280 6281 /* set the timestamp */ 6282 first->time_stamp = jiffies; 6283 6284 skb_tx_timestamp(skb); 6285 6286 /* Force memory writes to complete before letting h/w know there 6287 * are new descriptors to fetch. (Only applicable for weak-ordered 6288 * memory model archs, such as IA-64). 6289 * 6290 * We also need this memory barrier to make certain all of the 6291 * status bits have been updated before next_to_watch is written. 6292 */ 6293 dma_wmb(); 6294 6295 /* set next_to_watch value indicating a packet is present */ 6296 first->next_to_watch = tx_desc; 6297 6298 i++; 6299 if (i == tx_ring->count) 6300 i = 0; 6301 6302 tx_ring->next_to_use = i; 6303 6304 /* Make sure there is space in the ring for the next send. */ 6305 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6306 6307 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6308 writel(i, tx_ring->tail); 6309 } 6310 return 0; 6311 6312 dma_error: 6313 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6314 tx_buffer = &tx_ring->tx_buffer_info[i]; 6315 6316 /* clear dma mappings for failed tx_buffer_info map */ 6317 while (tx_buffer != first) { 6318 if (dma_unmap_len(tx_buffer, len)) 6319 dma_unmap_page(tx_ring->dev, 6320 dma_unmap_addr(tx_buffer, dma), 6321 dma_unmap_len(tx_buffer, len), 6322 DMA_TO_DEVICE); 6323 dma_unmap_len_set(tx_buffer, len, 0); 6324 6325 if (i-- == 0) 6326 i += tx_ring->count; 6327 tx_buffer = &tx_ring->tx_buffer_info[i]; 6328 } 6329 6330 if (dma_unmap_len(tx_buffer, len)) 6331 dma_unmap_single(tx_ring->dev, 6332 dma_unmap_addr(tx_buffer, dma), 6333 dma_unmap_len(tx_buffer, len), 6334 DMA_TO_DEVICE); 6335 dma_unmap_len_set(tx_buffer, len, 0); 6336 6337 dev_kfree_skb_any(tx_buffer->skb); 6338 tx_buffer->skb = NULL; 6339 6340 tx_ring->next_to_use = i; 6341 6342 return -1; 6343 } 6344 6345 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6346 struct igb_ring *tx_ring, 6347 struct xdp_frame *xdpf) 6348 { 6349 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6350 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6351 u16 count, i, index = tx_ring->next_to_use; 6352 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6353 struct igb_tx_buffer *tx_buffer = tx_head; 6354 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6355 u32 len = xdpf->len, cmd_type, olinfo_status; 6356 void *data = xdpf->data; 6357 6358 count = TXD_USE_COUNT(len); 6359 for (i = 0; i < nr_frags; i++) 6360 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6361 6362 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6363 return IGB_XDP_CONSUMED; 6364 6365 i = 0; 6366 /* record the location of the first descriptor for this packet */ 6367 tx_head->bytecount = xdp_get_frame_len(xdpf); 6368 tx_head->type = IGB_TYPE_XDP; 6369 tx_head->gso_segs = 1; 6370 tx_head->xdpf = xdpf; 6371 6372 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6373 /* 82575 requires a unique index per ring */ 6374 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6375 olinfo_status |= tx_ring->reg_idx << 4; 6376 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6377 6378 for (;;) { 6379 dma_addr_t dma; 6380 6381 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6382 if (dma_mapping_error(tx_ring->dev, dma)) 6383 goto unmap; 6384 6385 /* record length, and DMA address */ 6386 dma_unmap_len_set(tx_buffer, len, len); 6387 dma_unmap_addr_set(tx_buffer, dma, dma); 6388 6389 /* put descriptor type bits */ 6390 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6391 E1000_ADVTXD_DCMD_IFCS | len; 6392 6393 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6394 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6395 6396 tx_buffer->protocol = 0; 6397 6398 if (++index == tx_ring->count) 6399 index = 0; 6400 6401 if (i == nr_frags) 6402 break; 6403 6404 tx_buffer = &tx_ring->tx_buffer_info[index]; 6405 tx_desc = IGB_TX_DESC(tx_ring, index); 6406 tx_desc->read.olinfo_status = 0; 6407 6408 data = skb_frag_address(&sinfo->frags[i]); 6409 len = skb_frag_size(&sinfo->frags[i]); 6410 i++; 6411 } 6412 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6413 6414 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6415 /* set the timestamp */ 6416 tx_head->time_stamp = jiffies; 6417 6418 /* Avoid any potential race with xdp_xmit and cleanup */ 6419 smp_wmb(); 6420 6421 /* set next_to_watch value indicating a packet is present */ 6422 tx_head->next_to_watch = tx_desc; 6423 tx_ring->next_to_use = index; 6424 6425 /* Make sure there is space in the ring for the next send. */ 6426 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6427 6428 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6429 writel(index, tx_ring->tail); 6430 6431 return IGB_XDP_TX; 6432 6433 unmap: 6434 for (;;) { 6435 tx_buffer = &tx_ring->tx_buffer_info[index]; 6436 if (dma_unmap_len(tx_buffer, len)) 6437 dma_unmap_page(tx_ring->dev, 6438 dma_unmap_addr(tx_buffer, dma), 6439 dma_unmap_len(tx_buffer, len), 6440 DMA_TO_DEVICE); 6441 dma_unmap_len_set(tx_buffer, len, 0); 6442 if (tx_buffer == tx_head) 6443 break; 6444 6445 if (!index) 6446 index += tx_ring->count; 6447 index--; 6448 } 6449 6450 return IGB_XDP_CONSUMED; 6451 } 6452 6453 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6454 struct igb_ring *tx_ring) 6455 { 6456 struct igb_tx_buffer *first; 6457 int tso; 6458 u32 tx_flags = 0; 6459 unsigned short f; 6460 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6461 __be16 protocol = vlan_get_protocol(skb); 6462 u8 hdr_len = 0; 6463 6464 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6465 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6466 * + 2 desc gap to keep tail from touching head, 6467 * + 1 desc for context descriptor, 6468 * otherwise try next time 6469 */ 6470 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6471 count += TXD_USE_COUNT(skb_frag_size( 6472 &skb_shinfo(skb)->frags[f])); 6473 6474 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6475 /* this is a hard error */ 6476 return NETDEV_TX_BUSY; 6477 } 6478 6479 /* record the location of the first descriptor for this packet */ 6480 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6481 first->type = IGB_TYPE_SKB; 6482 first->skb = skb; 6483 first->bytecount = skb->len; 6484 first->gso_segs = 1; 6485 6486 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6487 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6488 6489 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6490 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6491 &adapter->state)) { 6492 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6493 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6494 6495 adapter->ptp_tx_skb = skb_get(skb); 6496 adapter->ptp_tx_start = jiffies; 6497 if (adapter->hw.mac.type == e1000_82576) 6498 schedule_work(&adapter->ptp_tx_work); 6499 } else { 6500 adapter->tx_hwtstamp_skipped++; 6501 } 6502 } 6503 6504 if (skb_vlan_tag_present(skb)) { 6505 tx_flags |= IGB_TX_FLAGS_VLAN; 6506 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6507 } 6508 6509 /* record initial flags and protocol */ 6510 first->tx_flags = tx_flags; 6511 first->protocol = protocol; 6512 6513 tso = igb_tso(tx_ring, first, &hdr_len); 6514 if (tso < 0) 6515 goto out_drop; 6516 else if (!tso) 6517 igb_tx_csum(tx_ring, first); 6518 6519 if (igb_tx_map(tx_ring, first, hdr_len)) 6520 goto cleanup_tx_tstamp; 6521 6522 return NETDEV_TX_OK; 6523 6524 out_drop: 6525 dev_kfree_skb_any(first->skb); 6526 first->skb = NULL; 6527 cleanup_tx_tstamp: 6528 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6529 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6530 6531 dev_kfree_skb_any(adapter->ptp_tx_skb); 6532 adapter->ptp_tx_skb = NULL; 6533 if (adapter->hw.mac.type == e1000_82576) 6534 cancel_work_sync(&adapter->ptp_tx_work); 6535 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6536 } 6537 6538 return NETDEV_TX_OK; 6539 } 6540 6541 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6542 struct sk_buff *skb) 6543 { 6544 unsigned int r_idx = skb->queue_mapping; 6545 6546 if (r_idx >= adapter->num_tx_queues) 6547 r_idx = r_idx % adapter->num_tx_queues; 6548 6549 return adapter->tx_ring[r_idx]; 6550 } 6551 6552 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6553 struct net_device *netdev) 6554 { 6555 struct igb_adapter *adapter = netdev_priv(netdev); 6556 6557 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6558 * in order to meet this minimum size requirement. 6559 */ 6560 if (skb_put_padto(skb, 17)) 6561 return NETDEV_TX_OK; 6562 6563 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6564 } 6565 6566 /** 6567 * igb_tx_timeout - Respond to a Tx Hang 6568 * @netdev: network interface device structure 6569 * @txqueue: number of the Tx queue that hung (unused) 6570 **/ 6571 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6572 { 6573 struct igb_adapter *adapter = netdev_priv(netdev); 6574 struct e1000_hw *hw = &adapter->hw; 6575 6576 /* Do the reset outside of interrupt context */ 6577 adapter->tx_timeout_count++; 6578 6579 if (hw->mac.type >= e1000_82580) 6580 hw->dev_spec._82575.global_device_reset = true; 6581 6582 schedule_work(&adapter->reset_task); 6583 wr32(E1000_EICS, 6584 (adapter->eims_enable_mask & ~adapter->eims_other)); 6585 } 6586 6587 static void igb_reset_task(struct work_struct *work) 6588 { 6589 struct igb_adapter *adapter; 6590 adapter = container_of(work, struct igb_adapter, reset_task); 6591 6592 rtnl_lock(); 6593 /* If we're already down or resetting, just bail */ 6594 if (test_bit(__IGB_DOWN, &adapter->state) || 6595 test_bit(__IGB_RESETTING, &adapter->state)) { 6596 rtnl_unlock(); 6597 return; 6598 } 6599 6600 igb_dump(adapter); 6601 netdev_err(adapter->netdev, "Reset adapter\n"); 6602 igb_reinit_locked(adapter); 6603 rtnl_unlock(); 6604 } 6605 6606 /** 6607 * igb_get_stats64 - Get System Network Statistics 6608 * @netdev: network interface device structure 6609 * @stats: rtnl_link_stats64 pointer 6610 **/ 6611 static void igb_get_stats64(struct net_device *netdev, 6612 struct rtnl_link_stats64 *stats) 6613 { 6614 struct igb_adapter *adapter = netdev_priv(netdev); 6615 6616 spin_lock(&adapter->stats64_lock); 6617 igb_update_stats(adapter); 6618 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6619 spin_unlock(&adapter->stats64_lock); 6620 } 6621 6622 /** 6623 * igb_change_mtu - Change the Maximum Transfer Unit 6624 * @netdev: network interface device structure 6625 * @new_mtu: new value for maximum frame size 6626 * 6627 * Returns 0 on success, negative on failure 6628 **/ 6629 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6630 { 6631 struct igb_adapter *adapter = netdev_priv(netdev); 6632 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6633 6634 if (adapter->xdp_prog) { 6635 int i; 6636 6637 for (i = 0; i < adapter->num_rx_queues; i++) { 6638 struct igb_ring *ring = adapter->rx_ring[i]; 6639 6640 if (max_frame > igb_rx_bufsz(ring)) { 6641 netdev_warn(adapter->netdev, 6642 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6643 max_frame); 6644 return -EINVAL; 6645 } 6646 } 6647 } 6648 6649 /* adjust max frame to be at least the size of a standard frame */ 6650 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6651 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6652 6653 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6654 usleep_range(1000, 2000); 6655 6656 /* igb_down has a dependency on max_frame_size */ 6657 adapter->max_frame_size = max_frame; 6658 6659 if (netif_running(netdev)) 6660 igb_down(adapter); 6661 6662 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6663 netdev->mtu, new_mtu); 6664 netdev->mtu = new_mtu; 6665 6666 if (netif_running(netdev)) 6667 igb_up(adapter); 6668 else 6669 igb_reset(adapter); 6670 6671 clear_bit(__IGB_RESETTING, &adapter->state); 6672 6673 return 0; 6674 } 6675 6676 /** 6677 * igb_update_stats - Update the board statistics counters 6678 * @adapter: board private structure 6679 **/ 6680 void igb_update_stats(struct igb_adapter *adapter) 6681 { 6682 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6683 struct e1000_hw *hw = &adapter->hw; 6684 struct pci_dev *pdev = adapter->pdev; 6685 u32 reg, mpc; 6686 int i; 6687 u64 bytes, packets; 6688 unsigned int start; 6689 u64 _bytes, _packets; 6690 6691 /* Prevent stats update while adapter is being reset, or if the pci 6692 * connection is down. 6693 */ 6694 if (adapter->link_speed == 0) 6695 return; 6696 if (pci_channel_offline(pdev)) 6697 return; 6698 6699 bytes = 0; 6700 packets = 0; 6701 6702 rcu_read_lock(); 6703 for (i = 0; i < adapter->num_rx_queues; i++) { 6704 struct igb_ring *ring = adapter->rx_ring[i]; 6705 u32 rqdpc = rd32(E1000_RQDPC(i)); 6706 if (hw->mac.type >= e1000_i210) 6707 wr32(E1000_RQDPC(i), 0); 6708 6709 if (rqdpc) { 6710 ring->rx_stats.drops += rqdpc; 6711 net_stats->rx_fifo_errors += rqdpc; 6712 } 6713 6714 do { 6715 start = u64_stats_fetch_begin(&ring->rx_syncp); 6716 _bytes = ring->rx_stats.bytes; 6717 _packets = ring->rx_stats.packets; 6718 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6719 bytes += _bytes; 6720 packets += _packets; 6721 } 6722 6723 net_stats->rx_bytes = bytes; 6724 net_stats->rx_packets = packets; 6725 6726 bytes = 0; 6727 packets = 0; 6728 for (i = 0; i < adapter->num_tx_queues; i++) { 6729 struct igb_ring *ring = adapter->tx_ring[i]; 6730 do { 6731 start = u64_stats_fetch_begin(&ring->tx_syncp); 6732 _bytes = ring->tx_stats.bytes; 6733 _packets = ring->tx_stats.packets; 6734 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6735 bytes += _bytes; 6736 packets += _packets; 6737 } 6738 net_stats->tx_bytes = bytes; 6739 net_stats->tx_packets = packets; 6740 rcu_read_unlock(); 6741 6742 /* read stats registers */ 6743 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6744 adapter->stats.gprc += rd32(E1000_GPRC); 6745 adapter->stats.gorc += rd32(E1000_GORCL); 6746 rd32(E1000_GORCH); /* clear GORCL */ 6747 adapter->stats.bprc += rd32(E1000_BPRC); 6748 adapter->stats.mprc += rd32(E1000_MPRC); 6749 adapter->stats.roc += rd32(E1000_ROC); 6750 6751 adapter->stats.prc64 += rd32(E1000_PRC64); 6752 adapter->stats.prc127 += rd32(E1000_PRC127); 6753 adapter->stats.prc255 += rd32(E1000_PRC255); 6754 adapter->stats.prc511 += rd32(E1000_PRC511); 6755 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6756 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6757 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6758 adapter->stats.sec += rd32(E1000_SEC); 6759 6760 mpc = rd32(E1000_MPC); 6761 adapter->stats.mpc += mpc; 6762 net_stats->rx_fifo_errors += mpc; 6763 adapter->stats.scc += rd32(E1000_SCC); 6764 adapter->stats.ecol += rd32(E1000_ECOL); 6765 adapter->stats.mcc += rd32(E1000_MCC); 6766 adapter->stats.latecol += rd32(E1000_LATECOL); 6767 adapter->stats.dc += rd32(E1000_DC); 6768 adapter->stats.rlec += rd32(E1000_RLEC); 6769 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6770 adapter->stats.xontxc += rd32(E1000_XONTXC); 6771 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6772 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6773 adapter->stats.fcruc += rd32(E1000_FCRUC); 6774 adapter->stats.gptc += rd32(E1000_GPTC); 6775 adapter->stats.gotc += rd32(E1000_GOTCL); 6776 rd32(E1000_GOTCH); /* clear GOTCL */ 6777 adapter->stats.rnbc += rd32(E1000_RNBC); 6778 adapter->stats.ruc += rd32(E1000_RUC); 6779 adapter->stats.rfc += rd32(E1000_RFC); 6780 adapter->stats.rjc += rd32(E1000_RJC); 6781 adapter->stats.tor += rd32(E1000_TORH); 6782 adapter->stats.tot += rd32(E1000_TOTH); 6783 adapter->stats.tpr += rd32(E1000_TPR); 6784 6785 adapter->stats.ptc64 += rd32(E1000_PTC64); 6786 adapter->stats.ptc127 += rd32(E1000_PTC127); 6787 adapter->stats.ptc255 += rd32(E1000_PTC255); 6788 adapter->stats.ptc511 += rd32(E1000_PTC511); 6789 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6790 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6791 6792 adapter->stats.mptc += rd32(E1000_MPTC); 6793 adapter->stats.bptc += rd32(E1000_BPTC); 6794 6795 adapter->stats.tpt += rd32(E1000_TPT); 6796 adapter->stats.colc += rd32(E1000_COLC); 6797 6798 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6799 /* read internal phy specific stats */ 6800 reg = rd32(E1000_CTRL_EXT); 6801 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6802 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6803 6804 /* this stat has invalid values on i210/i211 */ 6805 if ((hw->mac.type != e1000_i210) && 6806 (hw->mac.type != e1000_i211)) 6807 adapter->stats.tncrs += rd32(E1000_TNCRS); 6808 } 6809 6810 adapter->stats.tsctc += rd32(E1000_TSCTC); 6811 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6812 6813 adapter->stats.iac += rd32(E1000_IAC); 6814 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6815 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6816 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6817 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6818 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6819 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6820 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6821 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6822 6823 /* Fill out the OS statistics structure */ 6824 net_stats->multicast = adapter->stats.mprc; 6825 net_stats->collisions = adapter->stats.colc; 6826 6827 /* Rx Errors */ 6828 6829 /* RLEC on some newer hardware can be incorrect so build 6830 * our own version based on RUC and ROC 6831 */ 6832 net_stats->rx_errors = adapter->stats.rxerrc + 6833 adapter->stats.crcerrs + adapter->stats.algnerrc + 6834 adapter->stats.ruc + adapter->stats.roc + 6835 adapter->stats.cexterr; 6836 net_stats->rx_length_errors = adapter->stats.ruc + 6837 adapter->stats.roc; 6838 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6839 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6840 net_stats->rx_missed_errors = adapter->stats.mpc; 6841 6842 /* Tx Errors */ 6843 net_stats->tx_errors = adapter->stats.ecol + 6844 adapter->stats.latecol; 6845 net_stats->tx_aborted_errors = adapter->stats.ecol; 6846 net_stats->tx_window_errors = adapter->stats.latecol; 6847 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6848 6849 /* Tx Dropped needs to be maintained elsewhere */ 6850 6851 /* Management Stats */ 6852 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6853 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6854 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6855 6856 /* OS2BMC Stats */ 6857 reg = rd32(E1000_MANC); 6858 if (reg & E1000_MANC_EN_BMC2OS) { 6859 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6860 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6861 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6862 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6863 } 6864 } 6865 6866 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6867 { 6868 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6869 struct e1000_hw *hw = &adapter->hw; 6870 struct timespec64 ts; 6871 u32 tsauxc; 6872 6873 if (pin < 0 || pin >= IGB_N_SDP) 6874 return; 6875 6876 spin_lock(&adapter->tmreg_lock); 6877 6878 if (hw->mac.type == e1000_82580 || 6879 hw->mac.type == e1000_i354 || 6880 hw->mac.type == e1000_i350) { 6881 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6882 u32 systiml, systimh, level_mask, level, rem; 6883 u64 systim, now; 6884 6885 /* read systim registers in sequence */ 6886 rd32(E1000_SYSTIMR); 6887 systiml = rd32(E1000_SYSTIML); 6888 systimh = rd32(E1000_SYSTIMH); 6889 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6890 now = timecounter_cyc2time(&adapter->tc, systim); 6891 6892 if (pin < 2) { 6893 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6894 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6895 } else { 6896 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6897 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6898 } 6899 6900 div_u64_rem(now, ns, &rem); 6901 systim = systim + (ns - rem); 6902 6903 /* synchronize pin level with rising/falling edges */ 6904 div_u64_rem(now, ns << 1, &rem); 6905 if (rem < ns) { 6906 /* first half of period */ 6907 if (level == 0) { 6908 /* output is already low, skip this period */ 6909 systim += ns; 6910 pr_notice("igb: periodic output on %s missed falling edge\n", 6911 adapter->sdp_config[pin].name); 6912 } 6913 } else { 6914 /* second half of period */ 6915 if (level == 1) { 6916 /* output is already high, skip this period */ 6917 systim += ns; 6918 pr_notice("igb: periodic output on %s missed rising edge\n", 6919 adapter->sdp_config[pin].name); 6920 } 6921 } 6922 6923 /* for this chip family tv_sec is the upper part of the binary value, 6924 * so not seconds 6925 */ 6926 ts.tv_nsec = (u32)systim; 6927 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6928 } else { 6929 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6930 adapter->perout[tsintr_tt].period); 6931 } 6932 6933 /* u32 conversion of tv_sec is safe until y2106 */ 6934 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6935 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6936 tsauxc = rd32(E1000_TSAUXC); 6937 tsauxc |= TSAUXC_EN_TT0; 6938 wr32(E1000_TSAUXC, tsauxc); 6939 adapter->perout[tsintr_tt].start = ts; 6940 6941 spin_unlock(&adapter->tmreg_lock); 6942 } 6943 6944 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6945 { 6946 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6947 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6948 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6949 struct e1000_hw *hw = &adapter->hw; 6950 struct ptp_clock_event event; 6951 struct timespec64 ts; 6952 6953 if (pin < 0 || pin >= IGB_N_SDP) 6954 return; 6955 6956 if (hw->mac.type == e1000_82580 || 6957 hw->mac.type == e1000_i354 || 6958 hw->mac.type == e1000_i350) { 6959 s64 ns = rd32(auxstmpl); 6960 6961 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6962 ts = ns_to_timespec64(ns); 6963 } else { 6964 ts.tv_nsec = rd32(auxstmpl); 6965 ts.tv_sec = rd32(auxstmph); 6966 } 6967 6968 event.type = PTP_CLOCK_EXTTS; 6969 event.index = tsintr_tt; 6970 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6971 ptp_clock_event(adapter->ptp_clock, &event); 6972 } 6973 6974 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6975 { 6976 struct e1000_hw *hw = &adapter->hw; 6977 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6978 struct ptp_clock_event event; 6979 6980 if (tsicr & TSINTR_SYS_WRAP) { 6981 event.type = PTP_CLOCK_PPS; 6982 if (adapter->ptp_caps.pps) 6983 ptp_clock_event(adapter->ptp_clock, &event); 6984 ack |= TSINTR_SYS_WRAP; 6985 } 6986 6987 if (tsicr & E1000_TSICR_TXTS) { 6988 /* retrieve hardware timestamp */ 6989 schedule_work(&adapter->ptp_tx_work); 6990 ack |= E1000_TSICR_TXTS; 6991 } 6992 6993 if (tsicr & TSINTR_TT0) { 6994 igb_perout(adapter, 0); 6995 ack |= TSINTR_TT0; 6996 } 6997 6998 if (tsicr & TSINTR_TT1) { 6999 igb_perout(adapter, 1); 7000 ack |= TSINTR_TT1; 7001 } 7002 7003 if (tsicr & TSINTR_AUTT0) { 7004 igb_extts(adapter, 0); 7005 ack |= TSINTR_AUTT0; 7006 } 7007 7008 if (tsicr & TSINTR_AUTT1) { 7009 igb_extts(adapter, 1); 7010 ack |= TSINTR_AUTT1; 7011 } 7012 7013 /* acknowledge the interrupts */ 7014 wr32(E1000_TSICR, ack); 7015 } 7016 7017 static irqreturn_t igb_msix_other(int irq, void *data) 7018 { 7019 struct igb_adapter *adapter = data; 7020 struct e1000_hw *hw = &adapter->hw; 7021 u32 icr = rd32(E1000_ICR); 7022 /* reading ICR causes bit 31 of EICR to be cleared */ 7023 7024 if (icr & E1000_ICR_DRSTA) 7025 schedule_work(&adapter->reset_task); 7026 7027 if (icr & E1000_ICR_DOUTSYNC) { 7028 /* HW is reporting DMA is out of sync */ 7029 adapter->stats.doosync++; 7030 /* The DMA Out of Sync is also indication of a spoof event 7031 * in IOV mode. Check the Wrong VM Behavior register to 7032 * see if it is really a spoof event. 7033 */ 7034 igb_check_wvbr(adapter); 7035 } 7036 7037 /* Check for a mailbox event */ 7038 if (icr & E1000_ICR_VMMB) 7039 igb_msg_task(adapter); 7040 7041 if (icr & E1000_ICR_LSC) { 7042 hw->mac.get_link_status = 1; 7043 /* guard against interrupt when we're going down */ 7044 if (!test_bit(__IGB_DOWN, &adapter->state)) 7045 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7046 } 7047 7048 if (icr & E1000_ICR_TS) 7049 igb_tsync_interrupt(adapter); 7050 7051 wr32(E1000_EIMS, adapter->eims_other); 7052 7053 return IRQ_HANDLED; 7054 } 7055 7056 static void igb_write_itr(struct igb_q_vector *q_vector) 7057 { 7058 struct igb_adapter *adapter = q_vector->adapter; 7059 u32 itr_val = q_vector->itr_val & 0x7FFC; 7060 7061 if (!q_vector->set_itr) 7062 return; 7063 7064 if (!itr_val) 7065 itr_val = 0x4; 7066 7067 if (adapter->hw.mac.type == e1000_82575) 7068 itr_val |= itr_val << 16; 7069 else 7070 itr_val |= E1000_EITR_CNT_IGNR; 7071 7072 writel(itr_val, q_vector->itr_register); 7073 q_vector->set_itr = 0; 7074 } 7075 7076 static irqreturn_t igb_msix_ring(int irq, void *data) 7077 { 7078 struct igb_q_vector *q_vector = data; 7079 7080 /* Write the ITR value calculated from the previous interrupt. */ 7081 igb_write_itr(q_vector); 7082 7083 napi_schedule(&q_vector->napi); 7084 7085 return IRQ_HANDLED; 7086 } 7087 7088 #ifdef CONFIG_IGB_DCA 7089 static void igb_update_tx_dca(struct igb_adapter *adapter, 7090 struct igb_ring *tx_ring, 7091 int cpu) 7092 { 7093 struct e1000_hw *hw = &adapter->hw; 7094 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7095 7096 if (hw->mac.type != e1000_82575) 7097 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7098 7099 /* We can enable relaxed ordering for reads, but not writes when 7100 * DCA is enabled. This is due to a known issue in some chipsets 7101 * which will cause the DCA tag to be cleared. 7102 */ 7103 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7104 E1000_DCA_TXCTRL_DATA_RRO_EN | 7105 E1000_DCA_TXCTRL_DESC_DCA_EN; 7106 7107 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7108 } 7109 7110 static void igb_update_rx_dca(struct igb_adapter *adapter, 7111 struct igb_ring *rx_ring, 7112 int cpu) 7113 { 7114 struct e1000_hw *hw = &adapter->hw; 7115 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7116 7117 if (hw->mac.type != e1000_82575) 7118 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7119 7120 /* We can enable relaxed ordering for reads, but not writes when 7121 * DCA is enabled. This is due to a known issue in some chipsets 7122 * which will cause the DCA tag to be cleared. 7123 */ 7124 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7125 E1000_DCA_RXCTRL_DESC_DCA_EN; 7126 7127 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7128 } 7129 7130 static void igb_update_dca(struct igb_q_vector *q_vector) 7131 { 7132 struct igb_adapter *adapter = q_vector->adapter; 7133 int cpu = get_cpu(); 7134 7135 if (q_vector->cpu == cpu) 7136 goto out_no_update; 7137 7138 if (q_vector->tx.ring) 7139 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7140 7141 if (q_vector->rx.ring) 7142 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7143 7144 q_vector->cpu = cpu; 7145 out_no_update: 7146 put_cpu(); 7147 } 7148 7149 static void igb_setup_dca(struct igb_adapter *adapter) 7150 { 7151 struct e1000_hw *hw = &adapter->hw; 7152 int i; 7153 7154 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7155 return; 7156 7157 /* Always use CB2 mode, difference is masked in the CB driver. */ 7158 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7159 7160 for (i = 0; i < adapter->num_q_vectors; i++) { 7161 adapter->q_vector[i]->cpu = -1; 7162 igb_update_dca(adapter->q_vector[i]); 7163 } 7164 } 7165 7166 static int __igb_notify_dca(struct device *dev, void *data) 7167 { 7168 struct net_device *netdev = dev_get_drvdata(dev); 7169 struct igb_adapter *adapter = netdev_priv(netdev); 7170 struct pci_dev *pdev = adapter->pdev; 7171 struct e1000_hw *hw = &adapter->hw; 7172 unsigned long event = *(unsigned long *)data; 7173 7174 switch (event) { 7175 case DCA_PROVIDER_ADD: 7176 /* if already enabled, don't do it again */ 7177 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7178 break; 7179 if (dca_add_requester(dev) == 0) { 7180 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7181 dev_info(&pdev->dev, "DCA enabled\n"); 7182 igb_setup_dca(adapter); 7183 break; 7184 } 7185 fallthrough; /* since DCA is disabled. */ 7186 case DCA_PROVIDER_REMOVE: 7187 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7188 /* without this a class_device is left 7189 * hanging around in the sysfs model 7190 */ 7191 dca_remove_requester(dev); 7192 dev_info(&pdev->dev, "DCA disabled\n"); 7193 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7194 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7195 } 7196 break; 7197 } 7198 7199 return 0; 7200 } 7201 7202 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7203 void *p) 7204 { 7205 int ret_val; 7206 7207 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7208 __igb_notify_dca); 7209 7210 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7211 } 7212 #endif /* CONFIG_IGB_DCA */ 7213 7214 #ifdef CONFIG_PCI_IOV 7215 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7216 { 7217 unsigned char mac_addr[ETH_ALEN]; 7218 7219 eth_zero_addr(mac_addr); 7220 igb_set_vf_mac(adapter, vf, mac_addr); 7221 7222 /* By default spoof check is enabled for all VFs */ 7223 adapter->vf_data[vf].spoofchk_enabled = true; 7224 7225 /* By default VFs are not trusted */ 7226 adapter->vf_data[vf].trusted = false; 7227 7228 return 0; 7229 } 7230 7231 #endif 7232 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7233 { 7234 struct e1000_hw *hw = &adapter->hw; 7235 u32 ping; 7236 int i; 7237 7238 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7239 ping = E1000_PF_CONTROL_MSG; 7240 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7241 ping |= E1000_VT_MSGTYPE_CTS; 7242 igb_write_mbx(hw, &ping, 1, i); 7243 } 7244 } 7245 7246 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7247 { 7248 struct e1000_hw *hw = &adapter->hw; 7249 u32 vmolr = rd32(E1000_VMOLR(vf)); 7250 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7251 7252 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7253 IGB_VF_FLAG_MULTI_PROMISC); 7254 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7255 7256 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7257 vmolr |= E1000_VMOLR_MPME; 7258 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7259 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7260 } else { 7261 /* if we have hashes and we are clearing a multicast promisc 7262 * flag we need to write the hashes to the MTA as this step 7263 * was previously skipped 7264 */ 7265 if (vf_data->num_vf_mc_hashes > 30) { 7266 vmolr |= E1000_VMOLR_MPME; 7267 } else if (vf_data->num_vf_mc_hashes) { 7268 int j; 7269 7270 vmolr |= E1000_VMOLR_ROMPE; 7271 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7272 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7273 } 7274 } 7275 7276 wr32(E1000_VMOLR(vf), vmolr); 7277 7278 /* there are flags left unprocessed, likely not supported */ 7279 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7280 return -EINVAL; 7281 7282 return 0; 7283 } 7284 7285 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7286 u32 *msgbuf, u32 vf) 7287 { 7288 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7289 u16 *hash_list = (u16 *)&msgbuf[1]; 7290 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7291 int i; 7292 7293 /* salt away the number of multicast addresses assigned 7294 * to this VF for later use to restore when the PF multi cast 7295 * list changes 7296 */ 7297 vf_data->num_vf_mc_hashes = n; 7298 7299 /* only up to 30 hash values supported */ 7300 if (n > 30) 7301 n = 30; 7302 7303 /* store the hashes for later use */ 7304 for (i = 0; i < n; i++) 7305 vf_data->vf_mc_hashes[i] = hash_list[i]; 7306 7307 /* Flush and reset the mta with the new values */ 7308 igb_set_rx_mode(adapter->netdev); 7309 7310 return 0; 7311 } 7312 7313 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7314 { 7315 struct e1000_hw *hw = &adapter->hw; 7316 struct vf_data_storage *vf_data; 7317 int i, j; 7318 7319 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7320 u32 vmolr = rd32(E1000_VMOLR(i)); 7321 7322 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7323 7324 vf_data = &adapter->vf_data[i]; 7325 7326 if ((vf_data->num_vf_mc_hashes > 30) || 7327 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7328 vmolr |= E1000_VMOLR_MPME; 7329 } else if (vf_data->num_vf_mc_hashes) { 7330 vmolr |= E1000_VMOLR_ROMPE; 7331 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7332 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7333 } 7334 wr32(E1000_VMOLR(i), vmolr); 7335 } 7336 } 7337 7338 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7339 { 7340 struct e1000_hw *hw = &adapter->hw; 7341 u32 pool_mask, vlvf_mask, i; 7342 7343 /* create mask for VF and other pools */ 7344 pool_mask = E1000_VLVF_POOLSEL_MASK; 7345 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7346 7347 /* drop PF from pool bits */ 7348 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7349 adapter->vfs_allocated_count); 7350 7351 /* Find the vlan filter for this id */ 7352 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7353 u32 vlvf = rd32(E1000_VLVF(i)); 7354 u32 vfta_mask, vid, vfta; 7355 7356 /* remove the vf from the pool */ 7357 if (!(vlvf & vlvf_mask)) 7358 continue; 7359 7360 /* clear out bit from VLVF */ 7361 vlvf ^= vlvf_mask; 7362 7363 /* if other pools are present, just remove ourselves */ 7364 if (vlvf & pool_mask) 7365 goto update_vlvfb; 7366 7367 /* if PF is present, leave VFTA */ 7368 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7369 goto update_vlvf; 7370 7371 vid = vlvf & E1000_VLVF_VLANID_MASK; 7372 vfta_mask = BIT(vid % 32); 7373 7374 /* clear bit from VFTA */ 7375 vfta = adapter->shadow_vfta[vid / 32]; 7376 if (vfta & vfta_mask) 7377 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7378 update_vlvf: 7379 /* clear pool selection enable */ 7380 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7381 vlvf &= E1000_VLVF_POOLSEL_MASK; 7382 else 7383 vlvf = 0; 7384 update_vlvfb: 7385 /* clear pool bits */ 7386 wr32(E1000_VLVF(i), vlvf); 7387 } 7388 } 7389 7390 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7391 { 7392 u32 vlvf; 7393 int idx; 7394 7395 /* short cut the special case */ 7396 if (vlan == 0) 7397 return 0; 7398 7399 /* Search for the VLAN id in the VLVF entries */ 7400 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7401 vlvf = rd32(E1000_VLVF(idx)); 7402 if ((vlvf & VLAN_VID_MASK) == vlan) 7403 break; 7404 } 7405 7406 return idx; 7407 } 7408 7409 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7410 { 7411 struct e1000_hw *hw = &adapter->hw; 7412 u32 bits, pf_id; 7413 int idx; 7414 7415 idx = igb_find_vlvf_entry(hw, vid); 7416 if (!idx) 7417 return; 7418 7419 /* See if any other pools are set for this VLAN filter 7420 * entry other than the PF. 7421 */ 7422 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7423 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7424 bits &= rd32(E1000_VLVF(idx)); 7425 7426 /* Disable the filter so this falls into the default pool. */ 7427 if (!bits) { 7428 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7429 wr32(E1000_VLVF(idx), BIT(pf_id)); 7430 else 7431 wr32(E1000_VLVF(idx), 0); 7432 } 7433 } 7434 7435 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7436 bool add, u32 vf) 7437 { 7438 int pf_id = adapter->vfs_allocated_count; 7439 struct e1000_hw *hw = &adapter->hw; 7440 int err; 7441 7442 /* If VLAN overlaps with one the PF is currently monitoring make 7443 * sure that we are able to allocate a VLVF entry. This may be 7444 * redundant but it guarantees PF will maintain visibility to 7445 * the VLAN. 7446 */ 7447 if (add && test_bit(vid, adapter->active_vlans)) { 7448 err = igb_vfta_set(hw, vid, pf_id, true, false); 7449 if (err) 7450 return err; 7451 } 7452 7453 err = igb_vfta_set(hw, vid, vf, add, false); 7454 7455 if (add && !err) 7456 return err; 7457 7458 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7459 * we may need to drop the PF pool bit in order to allow us to free 7460 * up the VLVF resources. 7461 */ 7462 if (test_bit(vid, adapter->active_vlans) || 7463 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7464 igb_update_pf_vlvf(adapter, vid); 7465 7466 return err; 7467 } 7468 7469 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7470 { 7471 struct e1000_hw *hw = &adapter->hw; 7472 7473 if (vid) 7474 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7475 else 7476 wr32(E1000_VMVIR(vf), 0); 7477 } 7478 7479 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7480 u16 vlan, u8 qos) 7481 { 7482 int err; 7483 7484 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7485 if (err) 7486 return err; 7487 7488 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7489 igb_set_vmolr(adapter, vf, !vlan); 7490 7491 /* revoke access to previous VLAN */ 7492 if (vlan != adapter->vf_data[vf].pf_vlan) 7493 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7494 false, vf); 7495 7496 adapter->vf_data[vf].pf_vlan = vlan; 7497 adapter->vf_data[vf].pf_qos = qos; 7498 igb_set_vf_vlan_strip(adapter, vf, true); 7499 dev_info(&adapter->pdev->dev, 7500 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7501 if (test_bit(__IGB_DOWN, &adapter->state)) { 7502 dev_warn(&adapter->pdev->dev, 7503 "The VF VLAN has been set, but the PF device is not up.\n"); 7504 dev_warn(&adapter->pdev->dev, 7505 "Bring the PF device up before attempting to use the VF device.\n"); 7506 } 7507 7508 return err; 7509 } 7510 7511 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7512 { 7513 /* Restore tagless access via VLAN 0 */ 7514 igb_set_vf_vlan(adapter, 0, true, vf); 7515 7516 igb_set_vmvir(adapter, 0, vf); 7517 igb_set_vmolr(adapter, vf, true); 7518 7519 /* Remove any PF assigned VLAN */ 7520 if (adapter->vf_data[vf].pf_vlan) 7521 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7522 false, vf); 7523 7524 adapter->vf_data[vf].pf_vlan = 0; 7525 adapter->vf_data[vf].pf_qos = 0; 7526 igb_set_vf_vlan_strip(adapter, vf, false); 7527 7528 return 0; 7529 } 7530 7531 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7532 u16 vlan, u8 qos, __be16 vlan_proto) 7533 { 7534 struct igb_adapter *adapter = netdev_priv(netdev); 7535 7536 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7537 return -EINVAL; 7538 7539 if (vlan_proto != htons(ETH_P_8021Q)) 7540 return -EPROTONOSUPPORT; 7541 7542 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7543 igb_disable_port_vlan(adapter, vf); 7544 } 7545 7546 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7547 { 7548 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7549 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7550 int ret; 7551 7552 if (adapter->vf_data[vf].pf_vlan) 7553 return -1; 7554 7555 /* VLAN 0 is a special case, don't allow it to be removed */ 7556 if (!vid && !add) 7557 return 0; 7558 7559 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7560 if (!ret) 7561 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7562 return ret; 7563 } 7564 7565 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7566 { 7567 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7568 7569 /* clear flags - except flag that indicates PF has set the MAC */ 7570 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7571 vf_data->last_nack = jiffies; 7572 7573 /* reset vlans for device */ 7574 igb_clear_vf_vfta(adapter, vf); 7575 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7576 igb_set_vmvir(adapter, vf_data->pf_vlan | 7577 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7578 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7579 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7580 7581 /* reset multicast table array for vf */ 7582 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7583 7584 /* Flush and reset the mta with the new values */ 7585 igb_set_rx_mode(adapter->netdev); 7586 } 7587 7588 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7589 { 7590 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7591 7592 /* clear mac address as we were hotplug removed/added */ 7593 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7594 eth_zero_addr(vf_mac); 7595 7596 /* process remaining reset events */ 7597 igb_vf_reset(adapter, vf); 7598 } 7599 7600 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7601 { 7602 struct e1000_hw *hw = &adapter->hw; 7603 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7604 u32 reg, msgbuf[3] = {}; 7605 u8 *addr = (u8 *)(&msgbuf[1]); 7606 7607 /* process all the same items cleared in a function level reset */ 7608 igb_vf_reset(adapter, vf); 7609 7610 /* set vf mac address */ 7611 igb_set_vf_mac(adapter, vf, vf_mac); 7612 7613 /* enable transmit and receive for vf */ 7614 reg = rd32(E1000_VFTE); 7615 wr32(E1000_VFTE, reg | BIT(vf)); 7616 reg = rd32(E1000_VFRE); 7617 wr32(E1000_VFRE, reg | BIT(vf)); 7618 7619 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7620 7621 /* reply to reset with ack and vf mac address */ 7622 if (!is_zero_ether_addr(vf_mac)) { 7623 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7624 memcpy(addr, vf_mac, ETH_ALEN); 7625 } else { 7626 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7627 } 7628 igb_write_mbx(hw, msgbuf, 3, vf); 7629 } 7630 7631 static void igb_flush_mac_table(struct igb_adapter *adapter) 7632 { 7633 struct e1000_hw *hw = &adapter->hw; 7634 int i; 7635 7636 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7637 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7638 eth_zero_addr(adapter->mac_table[i].addr); 7639 adapter->mac_table[i].queue = 0; 7640 igb_rar_set_index(adapter, i); 7641 } 7642 } 7643 7644 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7645 { 7646 struct e1000_hw *hw = &adapter->hw; 7647 /* do not count rar entries reserved for VFs MAC addresses */ 7648 int rar_entries = hw->mac.rar_entry_count - 7649 adapter->vfs_allocated_count; 7650 int i, count = 0; 7651 7652 for (i = 0; i < rar_entries; i++) { 7653 /* do not count default entries */ 7654 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7655 continue; 7656 7657 /* do not count "in use" entries for different queues */ 7658 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7659 (adapter->mac_table[i].queue != queue)) 7660 continue; 7661 7662 count++; 7663 } 7664 7665 return count; 7666 } 7667 7668 /* Set default MAC address for the PF in the first RAR entry */ 7669 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7670 { 7671 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7672 7673 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7674 mac_table->queue = adapter->vfs_allocated_count; 7675 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7676 7677 igb_rar_set_index(adapter, 0); 7678 } 7679 7680 /* If the filter to be added and an already existing filter express 7681 * the same address and address type, it should be possible to only 7682 * override the other configurations, for example the queue to steer 7683 * traffic. 7684 */ 7685 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7686 const u8 *addr, const u8 flags) 7687 { 7688 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7689 return true; 7690 7691 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7692 (flags & IGB_MAC_STATE_SRC_ADDR)) 7693 return false; 7694 7695 if (!ether_addr_equal(addr, entry->addr)) 7696 return false; 7697 7698 return true; 7699 } 7700 7701 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7702 * 'flags' is used to indicate what kind of match is made, match is by 7703 * default for the destination address, if matching by source address 7704 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7705 */ 7706 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7707 const u8 *addr, const u8 queue, 7708 const u8 flags) 7709 { 7710 struct e1000_hw *hw = &adapter->hw; 7711 int rar_entries = hw->mac.rar_entry_count - 7712 adapter->vfs_allocated_count; 7713 int i; 7714 7715 if (is_zero_ether_addr(addr)) 7716 return -EINVAL; 7717 7718 /* Search for the first empty entry in the MAC table. 7719 * Do not touch entries at the end of the table reserved for the VF MAC 7720 * addresses. 7721 */ 7722 for (i = 0; i < rar_entries; i++) { 7723 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7724 addr, flags)) 7725 continue; 7726 7727 ether_addr_copy(adapter->mac_table[i].addr, addr); 7728 adapter->mac_table[i].queue = queue; 7729 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7730 7731 igb_rar_set_index(adapter, i); 7732 return i; 7733 } 7734 7735 return -ENOSPC; 7736 } 7737 7738 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7739 const u8 queue) 7740 { 7741 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7742 } 7743 7744 /* Remove a MAC filter for 'addr' directing matching traffic to 7745 * 'queue', 'flags' is used to indicate what kind of match need to be 7746 * removed, match is by default for the destination address, if 7747 * matching by source address is to be removed the flag 7748 * IGB_MAC_STATE_SRC_ADDR can be used. 7749 */ 7750 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7751 const u8 *addr, const u8 queue, 7752 const u8 flags) 7753 { 7754 struct e1000_hw *hw = &adapter->hw; 7755 int rar_entries = hw->mac.rar_entry_count - 7756 adapter->vfs_allocated_count; 7757 int i; 7758 7759 if (is_zero_ether_addr(addr)) 7760 return -EINVAL; 7761 7762 /* Search for matching entry in the MAC table based on given address 7763 * and queue. Do not touch entries at the end of the table reserved 7764 * for the VF MAC addresses. 7765 */ 7766 for (i = 0; i < rar_entries; i++) { 7767 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7768 continue; 7769 if ((adapter->mac_table[i].state & flags) != flags) 7770 continue; 7771 if (adapter->mac_table[i].queue != queue) 7772 continue; 7773 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7774 continue; 7775 7776 /* When a filter for the default address is "deleted", 7777 * we return it to its initial configuration 7778 */ 7779 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7780 adapter->mac_table[i].state = 7781 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7782 adapter->mac_table[i].queue = 7783 adapter->vfs_allocated_count; 7784 } else { 7785 adapter->mac_table[i].state = 0; 7786 adapter->mac_table[i].queue = 0; 7787 eth_zero_addr(adapter->mac_table[i].addr); 7788 } 7789 7790 igb_rar_set_index(adapter, i); 7791 return 0; 7792 } 7793 7794 return -ENOENT; 7795 } 7796 7797 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7798 const u8 queue) 7799 { 7800 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7801 } 7802 7803 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7804 const u8 *addr, u8 queue, u8 flags) 7805 { 7806 struct e1000_hw *hw = &adapter->hw; 7807 7808 /* In theory, this should be supported on 82575 as well, but 7809 * that part wasn't easily accessible during development. 7810 */ 7811 if (hw->mac.type != e1000_i210) 7812 return -EOPNOTSUPP; 7813 7814 return igb_add_mac_filter_flags(adapter, addr, queue, 7815 IGB_MAC_STATE_QUEUE_STEERING | flags); 7816 } 7817 7818 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7819 const u8 *addr, u8 queue, u8 flags) 7820 { 7821 return igb_del_mac_filter_flags(adapter, addr, queue, 7822 IGB_MAC_STATE_QUEUE_STEERING | flags); 7823 } 7824 7825 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7826 { 7827 struct igb_adapter *adapter = netdev_priv(netdev); 7828 int ret; 7829 7830 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7831 7832 return min_t(int, ret, 0); 7833 } 7834 7835 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7836 { 7837 struct igb_adapter *adapter = netdev_priv(netdev); 7838 7839 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7840 7841 return 0; 7842 } 7843 7844 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7845 const u32 info, const u8 *addr) 7846 { 7847 struct pci_dev *pdev = adapter->pdev; 7848 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7849 struct list_head *pos; 7850 struct vf_mac_filter *entry = NULL; 7851 int ret = 0; 7852 7853 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7854 !vf_data->trusted) { 7855 dev_warn(&pdev->dev, 7856 "VF %d requested MAC filter but is administratively denied\n", 7857 vf); 7858 return -EINVAL; 7859 } 7860 if (!is_valid_ether_addr(addr)) { 7861 dev_warn(&pdev->dev, 7862 "VF %d attempted to set invalid MAC filter\n", 7863 vf); 7864 return -EINVAL; 7865 } 7866 7867 switch (info) { 7868 case E1000_VF_MAC_FILTER_CLR: 7869 /* remove all unicast MAC filters related to the current VF */ 7870 list_for_each(pos, &adapter->vf_macs.l) { 7871 entry = list_entry(pos, struct vf_mac_filter, l); 7872 if (entry->vf == vf) { 7873 entry->vf = -1; 7874 entry->free = true; 7875 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7876 } 7877 } 7878 break; 7879 case E1000_VF_MAC_FILTER_ADD: 7880 /* try to find empty slot in the list */ 7881 list_for_each(pos, &adapter->vf_macs.l) { 7882 entry = list_entry(pos, struct vf_mac_filter, l); 7883 if (entry->free) 7884 break; 7885 } 7886 7887 if (entry && entry->free) { 7888 entry->free = false; 7889 entry->vf = vf; 7890 ether_addr_copy(entry->vf_mac, addr); 7891 7892 ret = igb_add_mac_filter(adapter, addr, vf); 7893 ret = min_t(int, ret, 0); 7894 } else { 7895 ret = -ENOSPC; 7896 } 7897 7898 if (ret == -ENOSPC) 7899 dev_warn(&pdev->dev, 7900 "VF %d has requested MAC filter but there is no space for it\n", 7901 vf); 7902 break; 7903 default: 7904 ret = -EINVAL; 7905 break; 7906 } 7907 7908 return ret; 7909 } 7910 7911 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7912 { 7913 struct pci_dev *pdev = adapter->pdev; 7914 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7915 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7916 7917 /* The VF MAC Address is stored in a packed array of bytes 7918 * starting at the second 32 bit word of the msg array 7919 */ 7920 unsigned char *addr = (unsigned char *)&msg[1]; 7921 int ret = 0; 7922 7923 if (!info) { 7924 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7925 !vf_data->trusted) { 7926 dev_warn(&pdev->dev, 7927 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7928 vf); 7929 return -EINVAL; 7930 } 7931 7932 if (!is_valid_ether_addr(addr)) { 7933 dev_warn(&pdev->dev, 7934 "VF %d attempted to set invalid MAC\n", 7935 vf); 7936 return -EINVAL; 7937 } 7938 7939 ret = igb_set_vf_mac(adapter, vf, addr); 7940 } else { 7941 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7942 } 7943 7944 return ret; 7945 } 7946 7947 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7948 { 7949 struct e1000_hw *hw = &adapter->hw; 7950 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7951 u32 msg = E1000_VT_MSGTYPE_NACK; 7952 7953 /* if device isn't clear to send it shouldn't be reading either */ 7954 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7955 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7956 igb_write_mbx(hw, &msg, 1, vf); 7957 vf_data->last_nack = jiffies; 7958 } 7959 } 7960 7961 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7962 { 7963 struct pci_dev *pdev = adapter->pdev; 7964 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7965 struct e1000_hw *hw = &adapter->hw; 7966 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7967 s32 retval; 7968 7969 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7970 7971 if (retval) { 7972 /* if receive failed revoke VF CTS stats and restart init */ 7973 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7974 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7975 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7976 goto unlock; 7977 goto out; 7978 } 7979 7980 /* this is a message we already processed, do nothing */ 7981 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7982 goto unlock; 7983 7984 /* until the vf completes a reset it should not be 7985 * allowed to start any configuration. 7986 */ 7987 if (msgbuf[0] == E1000_VF_RESET) { 7988 /* unlocks mailbox */ 7989 igb_vf_reset_msg(adapter, vf); 7990 return; 7991 } 7992 7993 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7994 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7995 goto unlock; 7996 retval = -1; 7997 goto out; 7998 } 7999 8000 switch ((msgbuf[0] & 0xFFFF)) { 8001 case E1000_VF_SET_MAC_ADDR: 8002 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8003 break; 8004 case E1000_VF_SET_PROMISC: 8005 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8006 break; 8007 case E1000_VF_SET_MULTICAST: 8008 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8009 break; 8010 case E1000_VF_SET_LPE: 8011 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8012 break; 8013 case E1000_VF_SET_VLAN: 8014 retval = -1; 8015 if (vf_data->pf_vlan) 8016 dev_warn(&pdev->dev, 8017 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8018 vf); 8019 else 8020 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8021 break; 8022 default: 8023 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8024 retval = -1; 8025 break; 8026 } 8027 8028 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8029 out: 8030 /* notify the VF of the results of what it sent us */ 8031 if (retval) 8032 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8033 else 8034 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8035 8036 /* unlocks mailbox */ 8037 igb_write_mbx(hw, msgbuf, 1, vf); 8038 return; 8039 8040 unlock: 8041 igb_unlock_mbx(hw, vf); 8042 } 8043 8044 static void igb_msg_task(struct igb_adapter *adapter) 8045 { 8046 struct e1000_hw *hw = &adapter->hw; 8047 unsigned long flags; 8048 u32 vf; 8049 8050 spin_lock_irqsave(&adapter->vfs_lock, flags); 8051 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8052 /* process any reset requests */ 8053 if (!igb_check_for_rst(hw, vf)) 8054 igb_vf_reset_event(adapter, vf); 8055 8056 /* process any messages pending */ 8057 if (!igb_check_for_msg(hw, vf)) 8058 igb_rcv_msg_from_vf(adapter, vf); 8059 8060 /* process any acks */ 8061 if (!igb_check_for_ack(hw, vf)) 8062 igb_rcv_ack_from_vf(adapter, vf); 8063 } 8064 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8065 } 8066 8067 /** 8068 * igb_set_uta - Set unicast filter table address 8069 * @adapter: board private structure 8070 * @set: boolean indicating if we are setting or clearing bits 8071 * 8072 * The unicast table address is a register array of 32-bit registers. 8073 * The table is meant to be used in a way similar to how the MTA is used 8074 * however due to certain limitations in the hardware it is necessary to 8075 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8076 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8077 **/ 8078 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8079 { 8080 struct e1000_hw *hw = &adapter->hw; 8081 u32 uta = set ? ~0 : 0; 8082 int i; 8083 8084 /* we only need to do this if VMDq is enabled */ 8085 if (!adapter->vfs_allocated_count) 8086 return; 8087 8088 for (i = hw->mac.uta_reg_count; i--;) 8089 array_wr32(E1000_UTA, i, uta); 8090 } 8091 8092 /** 8093 * igb_intr_msi - Interrupt Handler 8094 * @irq: interrupt number 8095 * @data: pointer to a network interface device structure 8096 **/ 8097 static irqreturn_t igb_intr_msi(int irq, void *data) 8098 { 8099 struct igb_adapter *adapter = data; 8100 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8101 struct e1000_hw *hw = &adapter->hw; 8102 /* read ICR disables interrupts using IAM */ 8103 u32 icr = rd32(E1000_ICR); 8104 8105 igb_write_itr(q_vector); 8106 8107 if (icr & E1000_ICR_DRSTA) 8108 schedule_work(&adapter->reset_task); 8109 8110 if (icr & E1000_ICR_DOUTSYNC) { 8111 /* HW is reporting DMA is out of sync */ 8112 adapter->stats.doosync++; 8113 } 8114 8115 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8116 hw->mac.get_link_status = 1; 8117 if (!test_bit(__IGB_DOWN, &adapter->state)) 8118 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8119 } 8120 8121 if (icr & E1000_ICR_TS) 8122 igb_tsync_interrupt(adapter); 8123 8124 napi_schedule(&q_vector->napi); 8125 8126 return IRQ_HANDLED; 8127 } 8128 8129 /** 8130 * igb_intr - Legacy Interrupt Handler 8131 * @irq: interrupt number 8132 * @data: pointer to a network interface device structure 8133 **/ 8134 static irqreturn_t igb_intr(int irq, void *data) 8135 { 8136 struct igb_adapter *adapter = data; 8137 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8138 struct e1000_hw *hw = &adapter->hw; 8139 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8140 * need for the IMC write 8141 */ 8142 u32 icr = rd32(E1000_ICR); 8143 8144 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8145 * not set, then the adapter didn't send an interrupt 8146 */ 8147 if (!(icr & E1000_ICR_INT_ASSERTED)) 8148 return IRQ_NONE; 8149 8150 igb_write_itr(q_vector); 8151 8152 if (icr & E1000_ICR_DRSTA) 8153 schedule_work(&adapter->reset_task); 8154 8155 if (icr & E1000_ICR_DOUTSYNC) { 8156 /* HW is reporting DMA is out of sync */ 8157 adapter->stats.doosync++; 8158 } 8159 8160 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8161 hw->mac.get_link_status = 1; 8162 /* guard against interrupt when we're going down */ 8163 if (!test_bit(__IGB_DOWN, &adapter->state)) 8164 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8165 } 8166 8167 if (icr & E1000_ICR_TS) 8168 igb_tsync_interrupt(adapter); 8169 8170 napi_schedule(&q_vector->napi); 8171 8172 return IRQ_HANDLED; 8173 } 8174 8175 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8176 { 8177 struct igb_adapter *adapter = q_vector->adapter; 8178 struct e1000_hw *hw = &adapter->hw; 8179 8180 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8181 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8182 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8183 igb_set_itr(q_vector); 8184 else 8185 igb_update_ring_itr(q_vector); 8186 } 8187 8188 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8189 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8190 wr32(E1000_EIMS, q_vector->eims_value); 8191 else 8192 igb_irq_enable(adapter); 8193 } 8194 } 8195 8196 /** 8197 * igb_poll - NAPI Rx polling callback 8198 * @napi: napi polling structure 8199 * @budget: count of how many packets we should handle 8200 **/ 8201 static int igb_poll(struct napi_struct *napi, int budget) 8202 { 8203 struct igb_q_vector *q_vector = container_of(napi, 8204 struct igb_q_vector, 8205 napi); 8206 bool clean_complete = true; 8207 int work_done = 0; 8208 8209 #ifdef CONFIG_IGB_DCA 8210 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8211 igb_update_dca(q_vector); 8212 #endif 8213 if (q_vector->tx.ring) 8214 clean_complete = igb_clean_tx_irq(q_vector, budget); 8215 8216 if (q_vector->rx.ring) { 8217 int cleaned = igb_clean_rx_irq(q_vector, budget); 8218 8219 work_done += cleaned; 8220 if (cleaned >= budget) 8221 clean_complete = false; 8222 } 8223 8224 /* If all work not completed, return budget and keep polling */ 8225 if (!clean_complete) 8226 return budget; 8227 8228 /* Exit the polling mode, but don't re-enable interrupts if stack might 8229 * poll us due to busy-polling 8230 */ 8231 if (likely(napi_complete_done(napi, work_done))) 8232 igb_ring_irq_enable(q_vector); 8233 8234 return work_done; 8235 } 8236 8237 /** 8238 * igb_clean_tx_irq - Reclaim resources after transmit completes 8239 * @q_vector: pointer to q_vector containing needed info 8240 * @napi_budget: Used to determine if we are in netpoll 8241 * 8242 * returns true if ring is completely cleaned 8243 **/ 8244 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8245 { 8246 struct igb_adapter *adapter = q_vector->adapter; 8247 struct igb_ring *tx_ring = q_vector->tx.ring; 8248 struct igb_tx_buffer *tx_buffer; 8249 union e1000_adv_tx_desc *tx_desc; 8250 unsigned int total_bytes = 0, total_packets = 0; 8251 unsigned int budget = q_vector->tx.work_limit; 8252 unsigned int i = tx_ring->next_to_clean; 8253 8254 if (test_bit(__IGB_DOWN, &adapter->state)) 8255 return true; 8256 8257 tx_buffer = &tx_ring->tx_buffer_info[i]; 8258 tx_desc = IGB_TX_DESC(tx_ring, i); 8259 i -= tx_ring->count; 8260 8261 do { 8262 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8263 8264 /* if next_to_watch is not set then there is no work pending */ 8265 if (!eop_desc) 8266 break; 8267 8268 /* prevent any other reads prior to eop_desc */ 8269 smp_rmb(); 8270 8271 /* if DD is not set pending work has not been completed */ 8272 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8273 break; 8274 8275 /* clear next_to_watch to prevent false hangs */ 8276 tx_buffer->next_to_watch = NULL; 8277 8278 /* update the statistics for this packet */ 8279 total_bytes += tx_buffer->bytecount; 8280 total_packets += tx_buffer->gso_segs; 8281 8282 /* free the skb */ 8283 if (tx_buffer->type == IGB_TYPE_SKB) 8284 napi_consume_skb(tx_buffer->skb, napi_budget); 8285 else 8286 xdp_return_frame(tx_buffer->xdpf); 8287 8288 /* unmap skb header data */ 8289 dma_unmap_single(tx_ring->dev, 8290 dma_unmap_addr(tx_buffer, dma), 8291 dma_unmap_len(tx_buffer, len), 8292 DMA_TO_DEVICE); 8293 8294 /* clear tx_buffer data */ 8295 dma_unmap_len_set(tx_buffer, len, 0); 8296 8297 /* clear last DMA location and unmap remaining buffers */ 8298 while (tx_desc != eop_desc) { 8299 tx_buffer++; 8300 tx_desc++; 8301 i++; 8302 if (unlikely(!i)) { 8303 i -= tx_ring->count; 8304 tx_buffer = tx_ring->tx_buffer_info; 8305 tx_desc = IGB_TX_DESC(tx_ring, 0); 8306 } 8307 8308 /* unmap any remaining paged data */ 8309 if (dma_unmap_len(tx_buffer, len)) { 8310 dma_unmap_page(tx_ring->dev, 8311 dma_unmap_addr(tx_buffer, dma), 8312 dma_unmap_len(tx_buffer, len), 8313 DMA_TO_DEVICE); 8314 dma_unmap_len_set(tx_buffer, len, 0); 8315 } 8316 } 8317 8318 /* move us one more past the eop_desc for start of next pkt */ 8319 tx_buffer++; 8320 tx_desc++; 8321 i++; 8322 if (unlikely(!i)) { 8323 i -= tx_ring->count; 8324 tx_buffer = tx_ring->tx_buffer_info; 8325 tx_desc = IGB_TX_DESC(tx_ring, 0); 8326 } 8327 8328 /* issue prefetch for next Tx descriptor */ 8329 prefetch(tx_desc); 8330 8331 /* update budget accounting */ 8332 budget--; 8333 } while (likely(budget)); 8334 8335 netdev_tx_completed_queue(txring_txq(tx_ring), 8336 total_packets, total_bytes); 8337 i += tx_ring->count; 8338 tx_ring->next_to_clean = i; 8339 u64_stats_update_begin(&tx_ring->tx_syncp); 8340 tx_ring->tx_stats.bytes += total_bytes; 8341 tx_ring->tx_stats.packets += total_packets; 8342 u64_stats_update_end(&tx_ring->tx_syncp); 8343 q_vector->tx.total_bytes += total_bytes; 8344 q_vector->tx.total_packets += total_packets; 8345 8346 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8347 struct e1000_hw *hw = &adapter->hw; 8348 8349 /* Detect a transmit hang in hardware, this serializes the 8350 * check with the clearing of time_stamp and movement of i 8351 */ 8352 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8353 if (tx_buffer->next_to_watch && 8354 time_after(jiffies, tx_buffer->time_stamp + 8355 (adapter->tx_timeout_factor * HZ)) && 8356 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8357 8358 /* detected Tx unit hang */ 8359 dev_err(tx_ring->dev, 8360 "Detected Tx Unit Hang\n" 8361 " Tx Queue <%d>\n" 8362 " TDH <%x>\n" 8363 " TDT <%x>\n" 8364 " next_to_use <%x>\n" 8365 " next_to_clean <%x>\n" 8366 "buffer_info[next_to_clean]\n" 8367 " time_stamp <%lx>\n" 8368 " next_to_watch <%p>\n" 8369 " jiffies <%lx>\n" 8370 " desc.status <%x>\n", 8371 tx_ring->queue_index, 8372 rd32(E1000_TDH(tx_ring->reg_idx)), 8373 readl(tx_ring->tail), 8374 tx_ring->next_to_use, 8375 tx_ring->next_to_clean, 8376 tx_buffer->time_stamp, 8377 tx_buffer->next_to_watch, 8378 jiffies, 8379 tx_buffer->next_to_watch->wb.status); 8380 netif_stop_subqueue(tx_ring->netdev, 8381 tx_ring->queue_index); 8382 8383 /* we are about to reset, no point in enabling stuff */ 8384 return true; 8385 } 8386 } 8387 8388 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8389 if (unlikely(total_packets && 8390 netif_carrier_ok(tx_ring->netdev) && 8391 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8392 /* Make sure that anybody stopping the queue after this 8393 * sees the new next_to_clean. 8394 */ 8395 smp_mb(); 8396 if (__netif_subqueue_stopped(tx_ring->netdev, 8397 tx_ring->queue_index) && 8398 !(test_bit(__IGB_DOWN, &adapter->state))) { 8399 netif_wake_subqueue(tx_ring->netdev, 8400 tx_ring->queue_index); 8401 8402 u64_stats_update_begin(&tx_ring->tx_syncp); 8403 tx_ring->tx_stats.restart_queue++; 8404 u64_stats_update_end(&tx_ring->tx_syncp); 8405 } 8406 } 8407 8408 return !!budget; 8409 } 8410 8411 /** 8412 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8413 * @rx_ring: rx descriptor ring to store buffers on 8414 * @old_buff: donor buffer to have page reused 8415 * 8416 * Synchronizes page for reuse by the adapter 8417 **/ 8418 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8419 struct igb_rx_buffer *old_buff) 8420 { 8421 struct igb_rx_buffer *new_buff; 8422 u16 nta = rx_ring->next_to_alloc; 8423 8424 new_buff = &rx_ring->rx_buffer_info[nta]; 8425 8426 /* update, and store next to alloc */ 8427 nta++; 8428 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8429 8430 /* Transfer page from old buffer to new buffer. 8431 * Move each member individually to avoid possible store 8432 * forwarding stalls. 8433 */ 8434 new_buff->dma = old_buff->dma; 8435 new_buff->page = old_buff->page; 8436 new_buff->page_offset = old_buff->page_offset; 8437 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8438 } 8439 8440 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8441 int rx_buf_pgcnt) 8442 { 8443 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8444 struct page *page = rx_buffer->page; 8445 8446 /* avoid re-using remote and pfmemalloc pages */ 8447 if (!dev_page_is_reusable(page)) 8448 return false; 8449 8450 #if (PAGE_SIZE < 8192) 8451 /* if we are only owner of page we can reuse it */ 8452 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8453 return false; 8454 #else 8455 #define IGB_LAST_OFFSET \ 8456 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8457 8458 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8459 return false; 8460 #endif 8461 8462 /* If we have drained the page fragment pool we need to update 8463 * the pagecnt_bias and page count so that we fully restock the 8464 * number of references the driver holds. 8465 */ 8466 if (unlikely(pagecnt_bias == 1)) { 8467 page_ref_add(page, USHRT_MAX - 1); 8468 rx_buffer->pagecnt_bias = USHRT_MAX; 8469 } 8470 8471 return true; 8472 } 8473 8474 /** 8475 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8476 * @rx_ring: rx descriptor ring to transact packets on 8477 * @rx_buffer: buffer containing page to add 8478 * @skb: sk_buff to place the data into 8479 * @size: size of buffer to be added 8480 * 8481 * This function will add the data contained in rx_buffer->page to the skb. 8482 **/ 8483 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8484 struct igb_rx_buffer *rx_buffer, 8485 struct sk_buff *skb, 8486 unsigned int size) 8487 { 8488 #if (PAGE_SIZE < 8192) 8489 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8490 #else 8491 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8492 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8493 SKB_DATA_ALIGN(size); 8494 #endif 8495 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8496 rx_buffer->page_offset, size, truesize); 8497 #if (PAGE_SIZE < 8192) 8498 rx_buffer->page_offset ^= truesize; 8499 #else 8500 rx_buffer->page_offset += truesize; 8501 #endif 8502 } 8503 8504 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8505 struct igb_rx_buffer *rx_buffer, 8506 struct xdp_buff *xdp, 8507 ktime_t timestamp) 8508 { 8509 #if (PAGE_SIZE < 8192) 8510 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8511 #else 8512 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8513 xdp->data_hard_start); 8514 #endif 8515 unsigned int size = xdp->data_end - xdp->data; 8516 unsigned int headlen; 8517 struct sk_buff *skb; 8518 8519 /* prefetch first cache line of first page */ 8520 net_prefetch(xdp->data); 8521 8522 /* allocate a skb to store the frags */ 8523 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8524 if (unlikely(!skb)) 8525 return NULL; 8526 8527 if (timestamp) 8528 skb_hwtstamps(skb)->hwtstamp = timestamp; 8529 8530 /* Determine available headroom for copy */ 8531 headlen = size; 8532 if (headlen > IGB_RX_HDR_LEN) 8533 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8534 8535 /* align pull length to size of long to optimize memcpy performance */ 8536 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8537 8538 /* update all of the pointers */ 8539 size -= headlen; 8540 if (size) { 8541 skb_add_rx_frag(skb, 0, rx_buffer->page, 8542 (xdp->data + headlen) - page_address(rx_buffer->page), 8543 size, truesize); 8544 #if (PAGE_SIZE < 8192) 8545 rx_buffer->page_offset ^= truesize; 8546 #else 8547 rx_buffer->page_offset += truesize; 8548 #endif 8549 } else { 8550 rx_buffer->pagecnt_bias++; 8551 } 8552 8553 return skb; 8554 } 8555 8556 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8557 struct igb_rx_buffer *rx_buffer, 8558 struct xdp_buff *xdp, 8559 ktime_t timestamp) 8560 { 8561 #if (PAGE_SIZE < 8192) 8562 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8563 #else 8564 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8565 SKB_DATA_ALIGN(xdp->data_end - 8566 xdp->data_hard_start); 8567 #endif 8568 unsigned int metasize = xdp->data - xdp->data_meta; 8569 struct sk_buff *skb; 8570 8571 /* prefetch first cache line of first page */ 8572 net_prefetch(xdp->data_meta); 8573 8574 /* build an skb around the page buffer */ 8575 skb = napi_build_skb(xdp->data_hard_start, truesize); 8576 if (unlikely(!skb)) 8577 return NULL; 8578 8579 /* update pointers within the skb to store the data */ 8580 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8581 __skb_put(skb, xdp->data_end - xdp->data); 8582 8583 if (metasize) 8584 skb_metadata_set(skb, metasize); 8585 8586 if (timestamp) 8587 skb_hwtstamps(skb)->hwtstamp = timestamp; 8588 8589 /* update buffer offset */ 8590 #if (PAGE_SIZE < 8192) 8591 rx_buffer->page_offset ^= truesize; 8592 #else 8593 rx_buffer->page_offset += truesize; 8594 #endif 8595 8596 return skb; 8597 } 8598 8599 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8600 struct igb_ring *rx_ring, 8601 struct xdp_buff *xdp) 8602 { 8603 int err, result = IGB_XDP_PASS; 8604 struct bpf_prog *xdp_prog; 8605 u32 act; 8606 8607 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8608 8609 if (!xdp_prog) 8610 goto xdp_out; 8611 8612 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8613 8614 act = bpf_prog_run_xdp(xdp_prog, xdp); 8615 switch (act) { 8616 case XDP_PASS: 8617 break; 8618 case XDP_TX: 8619 result = igb_xdp_xmit_back(adapter, xdp); 8620 if (result == IGB_XDP_CONSUMED) 8621 goto out_failure; 8622 break; 8623 case XDP_REDIRECT: 8624 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8625 if (err) 8626 goto out_failure; 8627 result = IGB_XDP_REDIR; 8628 break; 8629 default: 8630 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8631 fallthrough; 8632 case XDP_ABORTED: 8633 out_failure: 8634 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8635 fallthrough; 8636 case XDP_DROP: 8637 result = IGB_XDP_CONSUMED; 8638 break; 8639 } 8640 xdp_out: 8641 return ERR_PTR(-result); 8642 } 8643 8644 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8645 unsigned int size) 8646 { 8647 unsigned int truesize; 8648 8649 #if (PAGE_SIZE < 8192) 8650 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8651 #else 8652 truesize = ring_uses_build_skb(rx_ring) ? 8653 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8654 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8655 SKB_DATA_ALIGN(size); 8656 #endif 8657 return truesize; 8658 } 8659 8660 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8661 struct igb_rx_buffer *rx_buffer, 8662 unsigned int size) 8663 { 8664 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8665 #if (PAGE_SIZE < 8192) 8666 rx_buffer->page_offset ^= truesize; 8667 #else 8668 rx_buffer->page_offset += truesize; 8669 #endif 8670 } 8671 8672 static inline void igb_rx_checksum(struct igb_ring *ring, 8673 union e1000_adv_rx_desc *rx_desc, 8674 struct sk_buff *skb) 8675 { 8676 skb_checksum_none_assert(skb); 8677 8678 /* Ignore Checksum bit is set */ 8679 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8680 return; 8681 8682 /* Rx checksum disabled via ethtool */ 8683 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8684 return; 8685 8686 /* TCP/UDP checksum error bit is set */ 8687 if (igb_test_staterr(rx_desc, 8688 E1000_RXDEXT_STATERR_TCPE | 8689 E1000_RXDEXT_STATERR_IPE)) { 8690 /* work around errata with sctp packets where the TCPE aka 8691 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8692 * packets, (aka let the stack check the crc32c) 8693 */ 8694 if (!((skb->len == 60) && 8695 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8696 u64_stats_update_begin(&ring->rx_syncp); 8697 ring->rx_stats.csum_err++; 8698 u64_stats_update_end(&ring->rx_syncp); 8699 } 8700 /* let the stack verify checksum errors */ 8701 return; 8702 } 8703 /* It must be a TCP or UDP packet with a valid checksum */ 8704 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8705 E1000_RXD_STAT_UDPCS)) 8706 skb->ip_summed = CHECKSUM_UNNECESSARY; 8707 8708 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8709 le32_to_cpu(rx_desc->wb.upper.status_error)); 8710 } 8711 8712 static inline void igb_rx_hash(struct igb_ring *ring, 8713 union e1000_adv_rx_desc *rx_desc, 8714 struct sk_buff *skb) 8715 { 8716 if (ring->netdev->features & NETIF_F_RXHASH) 8717 skb_set_hash(skb, 8718 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8719 PKT_HASH_TYPE_L3); 8720 } 8721 8722 /** 8723 * igb_is_non_eop - process handling of non-EOP buffers 8724 * @rx_ring: Rx ring being processed 8725 * @rx_desc: Rx descriptor for current buffer 8726 * 8727 * This function updates next to clean. If the buffer is an EOP buffer 8728 * this function exits returning false, otherwise it will place the 8729 * sk_buff in the next buffer to be chained and return true indicating 8730 * that this is in fact a non-EOP buffer. 8731 **/ 8732 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8733 union e1000_adv_rx_desc *rx_desc) 8734 { 8735 u32 ntc = rx_ring->next_to_clean + 1; 8736 8737 /* fetch, update, and store next to clean */ 8738 ntc = (ntc < rx_ring->count) ? ntc : 0; 8739 rx_ring->next_to_clean = ntc; 8740 8741 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8742 8743 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8744 return false; 8745 8746 return true; 8747 } 8748 8749 /** 8750 * igb_cleanup_headers - Correct corrupted or empty headers 8751 * @rx_ring: rx descriptor ring packet is being transacted on 8752 * @rx_desc: pointer to the EOP Rx descriptor 8753 * @skb: pointer to current skb being fixed 8754 * 8755 * Address the case where we are pulling data in on pages only 8756 * and as such no data is present in the skb header. 8757 * 8758 * In addition if skb is not at least 60 bytes we need to pad it so that 8759 * it is large enough to qualify as a valid Ethernet frame. 8760 * 8761 * Returns true if an error was encountered and skb was freed. 8762 **/ 8763 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8764 union e1000_adv_rx_desc *rx_desc, 8765 struct sk_buff *skb) 8766 { 8767 /* XDP packets use error pointer so abort at this point */ 8768 if (IS_ERR(skb)) 8769 return true; 8770 8771 if (unlikely((igb_test_staterr(rx_desc, 8772 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8773 struct net_device *netdev = rx_ring->netdev; 8774 if (!(netdev->features & NETIF_F_RXALL)) { 8775 dev_kfree_skb_any(skb); 8776 return true; 8777 } 8778 } 8779 8780 /* if eth_skb_pad returns an error the skb was freed */ 8781 if (eth_skb_pad(skb)) 8782 return true; 8783 8784 return false; 8785 } 8786 8787 /** 8788 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8789 * @rx_ring: rx descriptor ring packet is being transacted on 8790 * @rx_desc: pointer to the EOP Rx descriptor 8791 * @skb: pointer to current skb being populated 8792 * 8793 * This function checks the ring, descriptor, and packet information in 8794 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8795 * other fields within the skb. 8796 **/ 8797 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8798 union e1000_adv_rx_desc *rx_desc, 8799 struct sk_buff *skb) 8800 { 8801 struct net_device *dev = rx_ring->netdev; 8802 8803 igb_rx_hash(rx_ring, rx_desc, skb); 8804 8805 igb_rx_checksum(rx_ring, rx_desc, skb); 8806 8807 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8808 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8809 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8810 8811 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8812 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8813 u16 vid; 8814 8815 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8816 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8817 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8818 else 8819 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8820 8821 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8822 } 8823 8824 skb_record_rx_queue(skb, rx_ring->queue_index); 8825 8826 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8827 } 8828 8829 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8830 { 8831 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8832 } 8833 8834 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8835 const unsigned int size, int *rx_buf_pgcnt) 8836 { 8837 struct igb_rx_buffer *rx_buffer; 8838 8839 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8840 *rx_buf_pgcnt = 8841 #if (PAGE_SIZE < 8192) 8842 page_count(rx_buffer->page); 8843 #else 8844 0; 8845 #endif 8846 prefetchw(rx_buffer->page); 8847 8848 /* we are reusing so sync this buffer for CPU use */ 8849 dma_sync_single_range_for_cpu(rx_ring->dev, 8850 rx_buffer->dma, 8851 rx_buffer->page_offset, 8852 size, 8853 DMA_FROM_DEVICE); 8854 8855 rx_buffer->pagecnt_bias--; 8856 8857 return rx_buffer; 8858 } 8859 8860 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8861 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8862 { 8863 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8864 /* hand second half of page back to the ring */ 8865 igb_reuse_rx_page(rx_ring, rx_buffer); 8866 } else { 8867 /* We are not reusing the buffer so unmap it and free 8868 * any references we are holding to it 8869 */ 8870 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8871 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8872 IGB_RX_DMA_ATTR); 8873 __page_frag_cache_drain(rx_buffer->page, 8874 rx_buffer->pagecnt_bias); 8875 } 8876 8877 /* clear contents of rx_buffer */ 8878 rx_buffer->page = NULL; 8879 } 8880 8881 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8882 { 8883 struct igb_adapter *adapter = q_vector->adapter; 8884 struct igb_ring *rx_ring = q_vector->rx.ring; 8885 struct sk_buff *skb = rx_ring->skb; 8886 unsigned int total_bytes = 0, total_packets = 0; 8887 u16 cleaned_count = igb_desc_unused(rx_ring); 8888 unsigned int xdp_xmit = 0; 8889 struct xdp_buff xdp; 8890 u32 frame_sz = 0; 8891 int rx_buf_pgcnt; 8892 8893 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8894 #if (PAGE_SIZE < 8192) 8895 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8896 #endif 8897 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8898 8899 while (likely(total_packets < budget)) { 8900 union e1000_adv_rx_desc *rx_desc; 8901 struct igb_rx_buffer *rx_buffer; 8902 ktime_t timestamp = 0; 8903 int pkt_offset = 0; 8904 unsigned int size; 8905 void *pktbuf; 8906 8907 /* return some buffers to hardware, one at a time is too slow */ 8908 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8909 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8910 cleaned_count = 0; 8911 } 8912 8913 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8914 size = le16_to_cpu(rx_desc->wb.upper.length); 8915 if (!size) 8916 break; 8917 8918 /* This memory barrier is needed to keep us from reading 8919 * any other fields out of the rx_desc until we know the 8920 * descriptor has been written back 8921 */ 8922 dma_rmb(); 8923 8924 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8925 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8926 8927 /* pull rx packet timestamp if available and valid */ 8928 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8929 int ts_hdr_len; 8930 8931 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8932 pktbuf, ×tamp); 8933 8934 pkt_offset += ts_hdr_len; 8935 size -= ts_hdr_len; 8936 } 8937 8938 /* retrieve a buffer from the ring */ 8939 if (!skb) { 8940 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8941 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8942 8943 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8944 xdp_buff_clear_frags_flag(&xdp); 8945 #if (PAGE_SIZE > 4096) 8946 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8947 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8948 #endif 8949 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8950 } 8951 8952 if (IS_ERR(skb)) { 8953 unsigned int xdp_res = -PTR_ERR(skb); 8954 8955 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8956 xdp_xmit |= xdp_res; 8957 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8958 } else { 8959 rx_buffer->pagecnt_bias++; 8960 } 8961 total_packets++; 8962 total_bytes += size; 8963 } else if (skb) 8964 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8965 else if (ring_uses_build_skb(rx_ring)) 8966 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8967 timestamp); 8968 else 8969 skb = igb_construct_skb(rx_ring, rx_buffer, 8970 &xdp, timestamp); 8971 8972 /* exit if we failed to retrieve a buffer */ 8973 if (!skb) { 8974 rx_ring->rx_stats.alloc_failed++; 8975 rx_buffer->pagecnt_bias++; 8976 break; 8977 } 8978 8979 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8980 cleaned_count++; 8981 8982 /* fetch next buffer in frame if non-eop */ 8983 if (igb_is_non_eop(rx_ring, rx_desc)) 8984 continue; 8985 8986 /* verify the packet layout is correct */ 8987 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8988 skb = NULL; 8989 continue; 8990 } 8991 8992 /* probably a little skewed due to removing CRC */ 8993 total_bytes += skb->len; 8994 8995 /* populate checksum, timestamp, VLAN, and protocol */ 8996 igb_process_skb_fields(rx_ring, rx_desc, skb); 8997 8998 napi_gro_receive(&q_vector->napi, skb); 8999 9000 /* reset skb pointer */ 9001 skb = NULL; 9002 9003 /* update budget accounting */ 9004 total_packets++; 9005 } 9006 9007 /* place incomplete frames back on ring for completion */ 9008 rx_ring->skb = skb; 9009 9010 if (xdp_xmit & IGB_XDP_REDIR) 9011 xdp_do_flush(); 9012 9013 if (xdp_xmit & IGB_XDP_TX) { 9014 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 9015 9016 igb_xdp_ring_update_tail(tx_ring); 9017 } 9018 9019 u64_stats_update_begin(&rx_ring->rx_syncp); 9020 rx_ring->rx_stats.packets += total_packets; 9021 rx_ring->rx_stats.bytes += total_bytes; 9022 u64_stats_update_end(&rx_ring->rx_syncp); 9023 q_vector->rx.total_packets += total_packets; 9024 q_vector->rx.total_bytes += total_bytes; 9025 9026 if (cleaned_count) 9027 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9028 9029 return total_packets; 9030 } 9031 9032 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9033 struct igb_rx_buffer *bi) 9034 { 9035 struct page *page = bi->page; 9036 dma_addr_t dma; 9037 9038 /* since we are recycling buffers we should seldom need to alloc */ 9039 if (likely(page)) 9040 return true; 9041 9042 /* alloc new page for storage */ 9043 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9044 if (unlikely(!page)) { 9045 rx_ring->rx_stats.alloc_failed++; 9046 return false; 9047 } 9048 9049 /* map page for use */ 9050 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9051 igb_rx_pg_size(rx_ring), 9052 DMA_FROM_DEVICE, 9053 IGB_RX_DMA_ATTR); 9054 9055 /* if mapping failed free memory back to system since 9056 * there isn't much point in holding memory we can't use 9057 */ 9058 if (dma_mapping_error(rx_ring->dev, dma)) { 9059 __free_pages(page, igb_rx_pg_order(rx_ring)); 9060 9061 rx_ring->rx_stats.alloc_failed++; 9062 return false; 9063 } 9064 9065 bi->dma = dma; 9066 bi->page = page; 9067 bi->page_offset = igb_rx_offset(rx_ring); 9068 page_ref_add(page, USHRT_MAX - 1); 9069 bi->pagecnt_bias = USHRT_MAX; 9070 9071 return true; 9072 } 9073 9074 /** 9075 * igb_alloc_rx_buffers - Replace used receive buffers 9076 * @rx_ring: rx descriptor ring to allocate new receive buffers 9077 * @cleaned_count: count of buffers to allocate 9078 **/ 9079 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9080 { 9081 union e1000_adv_rx_desc *rx_desc; 9082 struct igb_rx_buffer *bi; 9083 u16 i = rx_ring->next_to_use; 9084 u16 bufsz; 9085 9086 /* nothing to do */ 9087 if (!cleaned_count) 9088 return; 9089 9090 rx_desc = IGB_RX_DESC(rx_ring, i); 9091 bi = &rx_ring->rx_buffer_info[i]; 9092 i -= rx_ring->count; 9093 9094 bufsz = igb_rx_bufsz(rx_ring); 9095 9096 do { 9097 if (!igb_alloc_mapped_page(rx_ring, bi)) 9098 break; 9099 9100 /* sync the buffer for use by the device */ 9101 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9102 bi->page_offset, bufsz, 9103 DMA_FROM_DEVICE); 9104 9105 /* Refresh the desc even if buffer_addrs didn't change 9106 * because each write-back erases this info. 9107 */ 9108 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9109 9110 rx_desc++; 9111 bi++; 9112 i++; 9113 if (unlikely(!i)) { 9114 rx_desc = IGB_RX_DESC(rx_ring, 0); 9115 bi = rx_ring->rx_buffer_info; 9116 i -= rx_ring->count; 9117 } 9118 9119 /* clear the length for the next_to_use descriptor */ 9120 rx_desc->wb.upper.length = 0; 9121 9122 cleaned_count--; 9123 } while (cleaned_count); 9124 9125 i += rx_ring->count; 9126 9127 if (rx_ring->next_to_use != i) { 9128 /* record the next descriptor to use */ 9129 rx_ring->next_to_use = i; 9130 9131 /* update next to alloc since we have filled the ring */ 9132 rx_ring->next_to_alloc = i; 9133 9134 /* Force memory writes to complete before letting h/w 9135 * know there are new descriptors to fetch. (Only 9136 * applicable for weak-ordered memory model archs, 9137 * such as IA-64). 9138 */ 9139 dma_wmb(); 9140 writel(i, rx_ring->tail); 9141 } 9142 } 9143 9144 /** 9145 * igb_mii_ioctl - 9146 * @netdev: pointer to netdev struct 9147 * @ifr: interface structure 9148 * @cmd: ioctl command to execute 9149 **/ 9150 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9151 { 9152 struct igb_adapter *adapter = netdev_priv(netdev); 9153 struct mii_ioctl_data *data = if_mii(ifr); 9154 9155 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9156 return -EOPNOTSUPP; 9157 9158 switch (cmd) { 9159 case SIOCGMIIPHY: 9160 data->phy_id = adapter->hw.phy.addr; 9161 break; 9162 case SIOCGMIIREG: 9163 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9164 &data->val_out)) 9165 return -EIO; 9166 break; 9167 case SIOCSMIIREG: 9168 default: 9169 return -EOPNOTSUPP; 9170 } 9171 return 0; 9172 } 9173 9174 /** 9175 * igb_ioctl - 9176 * @netdev: pointer to netdev struct 9177 * @ifr: interface structure 9178 * @cmd: ioctl command to execute 9179 **/ 9180 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9181 { 9182 switch (cmd) { 9183 case SIOCGMIIPHY: 9184 case SIOCGMIIREG: 9185 case SIOCSMIIREG: 9186 return igb_mii_ioctl(netdev, ifr, cmd); 9187 case SIOCGHWTSTAMP: 9188 return igb_ptp_get_ts_config(netdev, ifr); 9189 case SIOCSHWTSTAMP: 9190 return igb_ptp_set_ts_config(netdev, ifr); 9191 default: 9192 return -EOPNOTSUPP; 9193 } 9194 } 9195 9196 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9197 { 9198 struct igb_adapter *adapter = hw->back; 9199 9200 pci_read_config_word(adapter->pdev, reg, value); 9201 } 9202 9203 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9204 { 9205 struct igb_adapter *adapter = hw->back; 9206 9207 pci_write_config_word(adapter->pdev, reg, *value); 9208 } 9209 9210 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9211 { 9212 struct igb_adapter *adapter = hw->back; 9213 9214 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9215 return -E1000_ERR_CONFIG; 9216 9217 return 0; 9218 } 9219 9220 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9221 { 9222 struct igb_adapter *adapter = hw->back; 9223 9224 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9225 return -E1000_ERR_CONFIG; 9226 9227 return 0; 9228 } 9229 9230 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9231 { 9232 struct igb_adapter *adapter = netdev_priv(netdev); 9233 struct e1000_hw *hw = &adapter->hw; 9234 u32 ctrl, rctl; 9235 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9236 9237 if (enable) { 9238 /* enable VLAN tag insert/strip */ 9239 ctrl = rd32(E1000_CTRL); 9240 ctrl |= E1000_CTRL_VME; 9241 wr32(E1000_CTRL, ctrl); 9242 9243 /* Disable CFI check */ 9244 rctl = rd32(E1000_RCTL); 9245 rctl &= ~E1000_RCTL_CFIEN; 9246 wr32(E1000_RCTL, rctl); 9247 } else { 9248 /* disable VLAN tag insert/strip */ 9249 ctrl = rd32(E1000_CTRL); 9250 ctrl &= ~E1000_CTRL_VME; 9251 wr32(E1000_CTRL, ctrl); 9252 } 9253 9254 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9255 } 9256 9257 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9258 __be16 proto, u16 vid) 9259 { 9260 struct igb_adapter *adapter = netdev_priv(netdev); 9261 struct e1000_hw *hw = &adapter->hw; 9262 int pf_id = adapter->vfs_allocated_count; 9263 9264 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9265 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9266 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9267 9268 set_bit(vid, adapter->active_vlans); 9269 9270 return 0; 9271 } 9272 9273 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9274 __be16 proto, u16 vid) 9275 { 9276 struct igb_adapter *adapter = netdev_priv(netdev); 9277 int pf_id = adapter->vfs_allocated_count; 9278 struct e1000_hw *hw = &adapter->hw; 9279 9280 /* remove VID from filter table */ 9281 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9282 igb_vfta_set(hw, vid, pf_id, false, true); 9283 9284 clear_bit(vid, adapter->active_vlans); 9285 9286 return 0; 9287 } 9288 9289 static void igb_restore_vlan(struct igb_adapter *adapter) 9290 { 9291 u16 vid = 1; 9292 9293 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9294 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9295 9296 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9297 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9298 } 9299 9300 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9301 { 9302 struct pci_dev *pdev = adapter->pdev; 9303 struct e1000_mac_info *mac = &adapter->hw.mac; 9304 9305 mac->autoneg = 0; 9306 9307 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9308 * for the switch() below to work 9309 */ 9310 if ((spd & 1) || (dplx & ~1)) 9311 goto err_inval; 9312 9313 /* Fiber NIC's only allow 1000 gbps Full duplex 9314 * and 100Mbps Full duplex for 100baseFx sfp 9315 */ 9316 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9317 switch (spd + dplx) { 9318 case SPEED_10 + DUPLEX_HALF: 9319 case SPEED_10 + DUPLEX_FULL: 9320 case SPEED_100 + DUPLEX_HALF: 9321 goto err_inval; 9322 default: 9323 break; 9324 } 9325 } 9326 9327 switch (spd + dplx) { 9328 case SPEED_10 + DUPLEX_HALF: 9329 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9330 break; 9331 case SPEED_10 + DUPLEX_FULL: 9332 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9333 break; 9334 case SPEED_100 + DUPLEX_HALF: 9335 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9336 break; 9337 case SPEED_100 + DUPLEX_FULL: 9338 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9339 break; 9340 case SPEED_1000 + DUPLEX_FULL: 9341 mac->autoneg = 1; 9342 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9343 break; 9344 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9345 default: 9346 goto err_inval; 9347 } 9348 9349 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9350 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9351 9352 return 0; 9353 9354 err_inval: 9355 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9356 return -EINVAL; 9357 } 9358 9359 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9360 bool runtime) 9361 { 9362 struct net_device *netdev = pci_get_drvdata(pdev); 9363 struct igb_adapter *adapter = netdev_priv(netdev); 9364 struct e1000_hw *hw = &adapter->hw; 9365 u32 ctrl, rctl, status; 9366 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9367 bool wake; 9368 9369 rtnl_lock(); 9370 netif_device_detach(netdev); 9371 9372 if (netif_running(netdev)) 9373 __igb_close(netdev, true); 9374 9375 igb_ptp_suspend(adapter); 9376 9377 igb_clear_interrupt_scheme(adapter); 9378 rtnl_unlock(); 9379 9380 status = rd32(E1000_STATUS); 9381 if (status & E1000_STATUS_LU) 9382 wufc &= ~E1000_WUFC_LNKC; 9383 9384 if (wufc) { 9385 igb_setup_rctl(adapter); 9386 igb_set_rx_mode(netdev); 9387 9388 /* turn on all-multi mode if wake on multicast is enabled */ 9389 if (wufc & E1000_WUFC_MC) { 9390 rctl = rd32(E1000_RCTL); 9391 rctl |= E1000_RCTL_MPE; 9392 wr32(E1000_RCTL, rctl); 9393 } 9394 9395 ctrl = rd32(E1000_CTRL); 9396 ctrl |= E1000_CTRL_ADVD3WUC; 9397 wr32(E1000_CTRL, ctrl); 9398 9399 /* Allow time for pending master requests to run */ 9400 igb_disable_pcie_master(hw); 9401 9402 wr32(E1000_WUC, E1000_WUC_PME_EN); 9403 wr32(E1000_WUFC, wufc); 9404 } else { 9405 wr32(E1000_WUC, 0); 9406 wr32(E1000_WUFC, 0); 9407 } 9408 9409 wake = wufc || adapter->en_mng_pt; 9410 if (!wake) 9411 igb_power_down_link(adapter); 9412 else 9413 igb_power_up_link(adapter); 9414 9415 if (enable_wake) 9416 *enable_wake = wake; 9417 9418 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9419 * would have already happened in close and is redundant. 9420 */ 9421 igb_release_hw_control(adapter); 9422 9423 pci_disable_device(pdev); 9424 9425 return 0; 9426 } 9427 9428 static void igb_deliver_wake_packet(struct net_device *netdev) 9429 { 9430 struct igb_adapter *adapter = netdev_priv(netdev); 9431 struct e1000_hw *hw = &adapter->hw; 9432 struct sk_buff *skb; 9433 u32 wupl; 9434 9435 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9436 9437 /* WUPM stores only the first 128 bytes of the wake packet. 9438 * Read the packet only if we have the whole thing. 9439 */ 9440 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9441 return; 9442 9443 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9444 if (!skb) 9445 return; 9446 9447 skb_put(skb, wupl); 9448 9449 /* Ensure reads are 32-bit aligned */ 9450 wupl = roundup(wupl, 4); 9451 9452 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9453 9454 skb->protocol = eth_type_trans(skb, netdev); 9455 netif_rx(skb); 9456 } 9457 9458 static int __maybe_unused igb_suspend(struct device *dev) 9459 { 9460 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9461 } 9462 9463 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9464 { 9465 struct pci_dev *pdev = to_pci_dev(dev); 9466 struct net_device *netdev = pci_get_drvdata(pdev); 9467 struct igb_adapter *adapter = netdev_priv(netdev); 9468 struct e1000_hw *hw = &adapter->hw; 9469 u32 err, val; 9470 9471 pci_set_power_state(pdev, PCI_D0); 9472 pci_restore_state(pdev); 9473 pci_save_state(pdev); 9474 9475 if (!pci_device_is_present(pdev)) 9476 return -ENODEV; 9477 err = pci_enable_device_mem(pdev); 9478 if (err) { 9479 dev_err(&pdev->dev, 9480 "igb: Cannot enable PCI device from suspend\n"); 9481 return err; 9482 } 9483 pci_set_master(pdev); 9484 9485 pci_enable_wake(pdev, PCI_D3hot, 0); 9486 pci_enable_wake(pdev, PCI_D3cold, 0); 9487 9488 if (igb_init_interrupt_scheme(adapter, true)) { 9489 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9490 return -ENOMEM; 9491 } 9492 9493 igb_reset(adapter); 9494 9495 /* let the f/w know that the h/w is now under the control of the 9496 * driver. 9497 */ 9498 igb_get_hw_control(adapter); 9499 9500 val = rd32(E1000_WUS); 9501 if (val & WAKE_PKT_WUS) 9502 igb_deliver_wake_packet(netdev); 9503 9504 wr32(E1000_WUS, ~0); 9505 9506 if (!rpm) 9507 rtnl_lock(); 9508 if (!err && netif_running(netdev)) 9509 err = __igb_open(netdev, true); 9510 9511 if (!err) 9512 netif_device_attach(netdev); 9513 if (!rpm) 9514 rtnl_unlock(); 9515 9516 return err; 9517 } 9518 9519 static int __maybe_unused igb_resume(struct device *dev) 9520 { 9521 return __igb_resume(dev, false); 9522 } 9523 9524 static int __maybe_unused igb_runtime_idle(struct device *dev) 9525 { 9526 struct net_device *netdev = dev_get_drvdata(dev); 9527 struct igb_adapter *adapter = netdev_priv(netdev); 9528 9529 if (!igb_has_link(adapter)) 9530 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9531 9532 return -EBUSY; 9533 } 9534 9535 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9536 { 9537 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9538 } 9539 9540 static int __maybe_unused igb_runtime_resume(struct device *dev) 9541 { 9542 return __igb_resume(dev, true); 9543 } 9544 9545 static void igb_shutdown(struct pci_dev *pdev) 9546 { 9547 bool wake; 9548 9549 __igb_shutdown(pdev, &wake, 0); 9550 9551 if (system_state == SYSTEM_POWER_OFF) { 9552 pci_wake_from_d3(pdev, wake); 9553 pci_set_power_state(pdev, PCI_D3hot); 9554 } 9555 } 9556 9557 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9558 { 9559 #ifdef CONFIG_PCI_IOV 9560 int err; 9561 9562 if (num_vfs == 0) { 9563 return igb_disable_sriov(dev, true); 9564 } else { 9565 err = igb_enable_sriov(dev, num_vfs, true); 9566 return err ? err : num_vfs; 9567 } 9568 #endif 9569 return 0; 9570 } 9571 9572 /** 9573 * igb_io_error_detected - called when PCI error is detected 9574 * @pdev: Pointer to PCI device 9575 * @state: The current pci connection state 9576 * 9577 * This function is called after a PCI bus error affecting 9578 * this device has been detected. 9579 **/ 9580 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9581 pci_channel_state_t state) 9582 { 9583 struct net_device *netdev = pci_get_drvdata(pdev); 9584 struct igb_adapter *adapter = netdev_priv(netdev); 9585 9586 netif_device_detach(netdev); 9587 9588 if (state == pci_channel_io_perm_failure) 9589 return PCI_ERS_RESULT_DISCONNECT; 9590 9591 if (netif_running(netdev)) 9592 igb_down(adapter); 9593 pci_disable_device(pdev); 9594 9595 /* Request a slot reset. */ 9596 return PCI_ERS_RESULT_NEED_RESET; 9597 } 9598 9599 /** 9600 * igb_io_slot_reset - called after the pci bus has been reset. 9601 * @pdev: Pointer to PCI device 9602 * 9603 * Restart the card from scratch, as if from a cold-boot. Implementation 9604 * resembles the first-half of the __igb_resume routine. 9605 **/ 9606 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9607 { 9608 struct net_device *netdev = pci_get_drvdata(pdev); 9609 struct igb_adapter *adapter = netdev_priv(netdev); 9610 struct e1000_hw *hw = &adapter->hw; 9611 pci_ers_result_t result; 9612 9613 if (pci_enable_device_mem(pdev)) { 9614 dev_err(&pdev->dev, 9615 "Cannot re-enable PCI device after reset.\n"); 9616 result = PCI_ERS_RESULT_DISCONNECT; 9617 } else { 9618 pci_set_master(pdev); 9619 pci_restore_state(pdev); 9620 pci_save_state(pdev); 9621 9622 pci_enable_wake(pdev, PCI_D3hot, 0); 9623 pci_enable_wake(pdev, PCI_D3cold, 0); 9624 9625 /* In case of PCI error, adapter lose its HW address 9626 * so we should re-assign it here. 9627 */ 9628 hw->hw_addr = adapter->io_addr; 9629 9630 igb_reset(adapter); 9631 wr32(E1000_WUS, ~0); 9632 result = PCI_ERS_RESULT_RECOVERED; 9633 } 9634 9635 return result; 9636 } 9637 9638 /** 9639 * igb_io_resume - called when traffic can start flowing again. 9640 * @pdev: Pointer to PCI device 9641 * 9642 * This callback is called when the error recovery driver tells us that 9643 * its OK to resume normal operation. Implementation resembles the 9644 * second-half of the __igb_resume routine. 9645 */ 9646 static void igb_io_resume(struct pci_dev *pdev) 9647 { 9648 struct net_device *netdev = pci_get_drvdata(pdev); 9649 struct igb_adapter *adapter = netdev_priv(netdev); 9650 9651 if (netif_running(netdev)) { 9652 if (igb_up(adapter)) { 9653 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9654 return; 9655 } 9656 } 9657 9658 netif_device_attach(netdev); 9659 9660 /* let the f/w know that the h/w is now under the control of the 9661 * driver. 9662 */ 9663 igb_get_hw_control(adapter); 9664 } 9665 9666 /** 9667 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9668 * @adapter: Pointer to adapter structure 9669 * @index: Index of the RAR entry which need to be synced with MAC table 9670 **/ 9671 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9672 { 9673 struct e1000_hw *hw = &adapter->hw; 9674 u32 rar_low, rar_high; 9675 u8 *addr = adapter->mac_table[index].addr; 9676 9677 /* HW expects these to be in network order when they are plugged 9678 * into the registers which are little endian. In order to guarantee 9679 * that ordering we need to do an leXX_to_cpup here in order to be 9680 * ready for the byteswap that occurs with writel 9681 */ 9682 rar_low = le32_to_cpup((__le32 *)(addr)); 9683 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9684 9685 /* Indicate to hardware the Address is Valid. */ 9686 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9687 if (is_valid_ether_addr(addr)) 9688 rar_high |= E1000_RAH_AV; 9689 9690 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9691 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9692 9693 switch (hw->mac.type) { 9694 case e1000_82575: 9695 case e1000_i210: 9696 if (adapter->mac_table[index].state & 9697 IGB_MAC_STATE_QUEUE_STEERING) 9698 rar_high |= E1000_RAH_QSEL_ENABLE; 9699 9700 rar_high |= E1000_RAH_POOL_1 * 9701 adapter->mac_table[index].queue; 9702 break; 9703 default: 9704 rar_high |= E1000_RAH_POOL_1 << 9705 adapter->mac_table[index].queue; 9706 break; 9707 } 9708 } 9709 9710 wr32(E1000_RAL(index), rar_low); 9711 wrfl(); 9712 wr32(E1000_RAH(index), rar_high); 9713 wrfl(); 9714 } 9715 9716 static int igb_set_vf_mac(struct igb_adapter *adapter, 9717 int vf, unsigned char *mac_addr) 9718 { 9719 struct e1000_hw *hw = &adapter->hw; 9720 /* VF MAC addresses start at end of receive addresses and moves 9721 * towards the first, as a result a collision should not be possible 9722 */ 9723 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9724 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9725 9726 ether_addr_copy(vf_mac_addr, mac_addr); 9727 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9728 adapter->mac_table[rar_entry].queue = vf; 9729 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9730 igb_rar_set_index(adapter, rar_entry); 9731 9732 return 0; 9733 } 9734 9735 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9736 { 9737 struct igb_adapter *adapter = netdev_priv(netdev); 9738 9739 if (vf >= adapter->vfs_allocated_count) 9740 return -EINVAL; 9741 9742 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9743 * flag and allows to overwrite the MAC via VF netdev. This 9744 * is necessary to allow libvirt a way to restore the original 9745 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9746 * down a VM. 9747 */ 9748 if (is_zero_ether_addr(mac)) { 9749 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9750 dev_info(&adapter->pdev->dev, 9751 "remove administratively set MAC on VF %d\n", 9752 vf); 9753 } else if (is_valid_ether_addr(mac)) { 9754 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9755 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9756 mac, vf); 9757 dev_info(&adapter->pdev->dev, 9758 "Reload the VF driver to make this change effective."); 9759 /* Generate additional warning if PF is down */ 9760 if (test_bit(__IGB_DOWN, &adapter->state)) { 9761 dev_warn(&adapter->pdev->dev, 9762 "The VF MAC address has been set, but the PF device is not up.\n"); 9763 dev_warn(&adapter->pdev->dev, 9764 "Bring the PF device up before attempting to use the VF device.\n"); 9765 } 9766 } else { 9767 return -EINVAL; 9768 } 9769 return igb_set_vf_mac(adapter, vf, mac); 9770 } 9771 9772 static int igb_link_mbps(int internal_link_speed) 9773 { 9774 switch (internal_link_speed) { 9775 case SPEED_100: 9776 return 100; 9777 case SPEED_1000: 9778 return 1000; 9779 default: 9780 return 0; 9781 } 9782 } 9783 9784 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9785 int link_speed) 9786 { 9787 int rf_dec, rf_int; 9788 u32 bcnrc_val; 9789 9790 if (tx_rate != 0) { 9791 /* Calculate the rate factor values to set */ 9792 rf_int = link_speed / tx_rate; 9793 rf_dec = (link_speed - (rf_int * tx_rate)); 9794 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9795 tx_rate; 9796 9797 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9798 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9799 E1000_RTTBCNRC_RF_INT_MASK); 9800 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9801 } else { 9802 bcnrc_val = 0; 9803 } 9804 9805 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9806 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9807 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9808 */ 9809 wr32(E1000_RTTBCNRM, 0x14); 9810 wr32(E1000_RTTBCNRC, bcnrc_val); 9811 } 9812 9813 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9814 { 9815 int actual_link_speed, i; 9816 bool reset_rate = false; 9817 9818 /* VF TX rate limit was not set or not supported */ 9819 if ((adapter->vf_rate_link_speed == 0) || 9820 (adapter->hw.mac.type != e1000_82576)) 9821 return; 9822 9823 actual_link_speed = igb_link_mbps(adapter->link_speed); 9824 if (actual_link_speed != adapter->vf_rate_link_speed) { 9825 reset_rate = true; 9826 adapter->vf_rate_link_speed = 0; 9827 dev_info(&adapter->pdev->dev, 9828 "Link speed has been changed. VF Transmit rate is disabled\n"); 9829 } 9830 9831 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9832 if (reset_rate) 9833 adapter->vf_data[i].tx_rate = 0; 9834 9835 igb_set_vf_rate_limit(&adapter->hw, i, 9836 adapter->vf_data[i].tx_rate, 9837 actual_link_speed); 9838 } 9839 } 9840 9841 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9842 int min_tx_rate, int max_tx_rate) 9843 { 9844 struct igb_adapter *adapter = netdev_priv(netdev); 9845 struct e1000_hw *hw = &adapter->hw; 9846 int actual_link_speed; 9847 9848 if (hw->mac.type != e1000_82576) 9849 return -EOPNOTSUPP; 9850 9851 if (min_tx_rate) 9852 return -EINVAL; 9853 9854 actual_link_speed = igb_link_mbps(adapter->link_speed); 9855 if ((vf >= adapter->vfs_allocated_count) || 9856 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9857 (max_tx_rate < 0) || 9858 (max_tx_rate > actual_link_speed)) 9859 return -EINVAL; 9860 9861 adapter->vf_rate_link_speed = actual_link_speed; 9862 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9863 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9864 9865 return 0; 9866 } 9867 9868 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9869 bool setting) 9870 { 9871 struct igb_adapter *adapter = netdev_priv(netdev); 9872 struct e1000_hw *hw = &adapter->hw; 9873 u32 reg_val, reg_offset; 9874 9875 if (!adapter->vfs_allocated_count) 9876 return -EOPNOTSUPP; 9877 9878 if (vf >= adapter->vfs_allocated_count) 9879 return -EINVAL; 9880 9881 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9882 reg_val = rd32(reg_offset); 9883 if (setting) 9884 reg_val |= (BIT(vf) | 9885 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9886 else 9887 reg_val &= ~(BIT(vf) | 9888 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9889 wr32(reg_offset, reg_val); 9890 9891 adapter->vf_data[vf].spoofchk_enabled = setting; 9892 return 0; 9893 } 9894 9895 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9896 { 9897 struct igb_adapter *adapter = netdev_priv(netdev); 9898 9899 if (vf >= adapter->vfs_allocated_count) 9900 return -EINVAL; 9901 if (adapter->vf_data[vf].trusted == setting) 9902 return 0; 9903 9904 adapter->vf_data[vf].trusted = setting; 9905 9906 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9907 vf, setting ? "" : "not "); 9908 return 0; 9909 } 9910 9911 static int igb_ndo_get_vf_config(struct net_device *netdev, 9912 int vf, struct ifla_vf_info *ivi) 9913 { 9914 struct igb_adapter *adapter = netdev_priv(netdev); 9915 if (vf >= adapter->vfs_allocated_count) 9916 return -EINVAL; 9917 ivi->vf = vf; 9918 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9919 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9920 ivi->min_tx_rate = 0; 9921 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9922 ivi->qos = adapter->vf_data[vf].pf_qos; 9923 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9924 ivi->trusted = adapter->vf_data[vf].trusted; 9925 return 0; 9926 } 9927 9928 static void igb_vmm_control(struct igb_adapter *adapter) 9929 { 9930 struct e1000_hw *hw = &adapter->hw; 9931 u32 reg; 9932 9933 switch (hw->mac.type) { 9934 case e1000_82575: 9935 case e1000_i210: 9936 case e1000_i211: 9937 case e1000_i354: 9938 default: 9939 /* replication is not supported for 82575 */ 9940 return; 9941 case e1000_82576: 9942 /* notify HW that the MAC is adding vlan tags */ 9943 reg = rd32(E1000_DTXCTL); 9944 reg |= E1000_DTXCTL_VLAN_ADDED; 9945 wr32(E1000_DTXCTL, reg); 9946 fallthrough; 9947 case e1000_82580: 9948 /* enable replication vlan tag stripping */ 9949 reg = rd32(E1000_RPLOLR); 9950 reg |= E1000_RPLOLR_STRVLAN; 9951 wr32(E1000_RPLOLR, reg); 9952 fallthrough; 9953 case e1000_i350: 9954 /* none of the above registers are supported by i350 */ 9955 break; 9956 } 9957 9958 if (adapter->vfs_allocated_count) { 9959 igb_vmdq_set_loopback_pf(hw, true); 9960 igb_vmdq_set_replication_pf(hw, true); 9961 igb_vmdq_set_anti_spoofing_pf(hw, true, 9962 adapter->vfs_allocated_count); 9963 } else { 9964 igb_vmdq_set_loopback_pf(hw, false); 9965 igb_vmdq_set_replication_pf(hw, false); 9966 } 9967 } 9968 9969 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9970 { 9971 struct e1000_hw *hw = &adapter->hw; 9972 u32 dmac_thr; 9973 u16 hwm; 9974 u32 reg; 9975 9976 if (hw->mac.type > e1000_82580) { 9977 if (adapter->flags & IGB_FLAG_DMAC) { 9978 /* force threshold to 0. */ 9979 wr32(E1000_DMCTXTH, 0); 9980 9981 /* DMA Coalescing high water mark needs to be greater 9982 * than the Rx threshold. Set hwm to PBA - max frame 9983 * size in 16B units, capping it at PBA - 6KB. 9984 */ 9985 hwm = 64 * (pba - 6); 9986 reg = rd32(E1000_FCRTC); 9987 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9988 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9989 & E1000_FCRTC_RTH_COAL_MASK); 9990 wr32(E1000_FCRTC, reg); 9991 9992 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9993 * frame size, capping it at PBA - 10KB. 9994 */ 9995 dmac_thr = pba - 10; 9996 reg = rd32(E1000_DMACR); 9997 reg &= ~E1000_DMACR_DMACTHR_MASK; 9998 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9999 & E1000_DMACR_DMACTHR_MASK); 10000 10001 /* transition to L0x or L1 if available..*/ 10002 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10003 10004 /* watchdog timer= +-1000 usec in 32usec intervals */ 10005 reg |= (1000 >> 5); 10006 10007 /* Disable BMC-to-OS Watchdog Enable */ 10008 if (hw->mac.type != e1000_i354) 10009 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10010 wr32(E1000_DMACR, reg); 10011 10012 /* no lower threshold to disable 10013 * coalescing(smart fifb)-UTRESH=0 10014 */ 10015 wr32(E1000_DMCRTRH, 0); 10016 10017 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10018 10019 wr32(E1000_DMCTLX, reg); 10020 10021 /* free space in tx packet buffer to wake from 10022 * DMA coal 10023 */ 10024 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10025 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10026 } 10027 10028 if (hw->mac.type >= e1000_i210 || 10029 (adapter->flags & IGB_FLAG_DMAC)) { 10030 reg = rd32(E1000_PCIEMISC); 10031 reg |= E1000_PCIEMISC_LX_DECISION; 10032 wr32(E1000_PCIEMISC, reg); 10033 } /* endif adapter->dmac is not disabled */ 10034 } else if (hw->mac.type == e1000_82580) { 10035 u32 reg = rd32(E1000_PCIEMISC); 10036 10037 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10038 wr32(E1000_DMACR, 0); 10039 } 10040 } 10041 10042 /** 10043 * igb_read_i2c_byte - Reads 8 bit word over I2C 10044 * @hw: pointer to hardware structure 10045 * @byte_offset: byte offset to read 10046 * @dev_addr: device address 10047 * @data: value read 10048 * 10049 * Performs byte read operation over I2C interface at 10050 * a specified device address. 10051 **/ 10052 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10053 u8 dev_addr, u8 *data) 10054 { 10055 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10056 struct i2c_client *this_client = adapter->i2c_client; 10057 s32 status; 10058 u16 swfw_mask = 0; 10059 10060 if (!this_client) 10061 return E1000_ERR_I2C; 10062 10063 swfw_mask = E1000_SWFW_PHY0_SM; 10064 10065 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10066 return E1000_ERR_SWFW_SYNC; 10067 10068 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10069 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10070 10071 if (status < 0) 10072 return E1000_ERR_I2C; 10073 else { 10074 *data = status; 10075 return 0; 10076 } 10077 } 10078 10079 /** 10080 * igb_write_i2c_byte - Writes 8 bit word over I2C 10081 * @hw: pointer to hardware structure 10082 * @byte_offset: byte offset to write 10083 * @dev_addr: device address 10084 * @data: value to write 10085 * 10086 * Performs byte write operation over I2C interface at 10087 * a specified device address. 10088 **/ 10089 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10090 u8 dev_addr, u8 data) 10091 { 10092 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10093 struct i2c_client *this_client = adapter->i2c_client; 10094 s32 status; 10095 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10096 10097 if (!this_client) 10098 return E1000_ERR_I2C; 10099 10100 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10101 return E1000_ERR_SWFW_SYNC; 10102 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10103 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10104 10105 if (status) 10106 return E1000_ERR_I2C; 10107 else 10108 return 0; 10109 10110 } 10111 10112 int igb_reinit_queues(struct igb_adapter *adapter) 10113 { 10114 struct net_device *netdev = adapter->netdev; 10115 struct pci_dev *pdev = adapter->pdev; 10116 int err = 0; 10117 10118 if (netif_running(netdev)) 10119 igb_close(netdev); 10120 10121 igb_reset_interrupt_capability(adapter); 10122 10123 if (igb_init_interrupt_scheme(adapter, true)) { 10124 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10125 return -ENOMEM; 10126 } 10127 10128 if (netif_running(netdev)) 10129 err = igb_open(netdev); 10130 10131 return err; 10132 } 10133 10134 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10135 { 10136 struct igb_nfc_filter *rule; 10137 10138 spin_lock(&adapter->nfc_lock); 10139 10140 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10141 igb_erase_filter(adapter, rule); 10142 10143 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10144 igb_erase_filter(adapter, rule); 10145 10146 spin_unlock(&adapter->nfc_lock); 10147 } 10148 10149 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10150 { 10151 struct igb_nfc_filter *rule; 10152 10153 spin_lock(&adapter->nfc_lock); 10154 10155 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10156 igb_add_filter(adapter, rule); 10157 10158 spin_unlock(&adapter->nfc_lock); 10159 } 10160 /* igb_main.c */ 10161