1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_TDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { u64 a; u64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) 581 i2cctl |= E1000_I2C_DATA_OUT; 582 else 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 585 i2cctl &= ~E1000_I2C_DATA_OE_N; 586 i2cctl |= E1000_I2C_CLK_OE_N; 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 590 } 591 592 /** 593 * igb_set_i2c_clk - Sets the I2C SCL clock 594 * @data: pointer to hardware structure 595 * @state: state to set clock 596 * 597 * Sets the I2C clock line to state 598 **/ 599 static void igb_set_i2c_clk(void *data, int state) 600 { 601 struct igb_adapter *adapter = (struct igb_adapter *)data; 602 struct e1000_hw *hw = &adapter->hw; 603 s32 i2cctl = rd32(E1000_I2CPARAMS); 604 605 if (state) { 606 i2cctl |= E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } else { 609 i2cctl &= ~E1000_I2C_CLK_OUT; 610 i2cctl &= ~E1000_I2C_CLK_OE_N; 611 } 612 wr32(E1000_I2CPARAMS, i2cctl); 613 wrfl(); 614 } 615 616 /** 617 * igb_get_i2c_clk - Gets the I2C SCL clock state 618 * @data: pointer to hardware structure 619 * 620 * Gets the I2C clock state 621 **/ 622 static int igb_get_i2c_clk(void *data) 623 { 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 return !!(i2cctl & E1000_I2C_CLK_IN); 629 } 630 631 static const struct i2c_algo_bit_data igb_i2c_algo = { 632 .setsda = igb_set_i2c_data, 633 .setscl = igb_set_i2c_clk, 634 .getsda = igb_get_i2c_data, 635 .getscl = igb_get_i2c_clk, 636 .udelay = 5, 637 .timeout = 20, 638 }; 639 640 /** 641 * igb_get_hw_dev - return device 642 * @hw: pointer to hardware structure 643 * 644 * used by hardware layer to print debugging information 645 **/ 646 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 647 { 648 struct igb_adapter *adapter = hw->back; 649 return adapter->netdev; 650 } 651 652 /** 653 * igb_init_module - Driver Registration Routine 654 * 655 * igb_init_module is the first routine called when the driver is 656 * loaded. All it does is register with the PCI subsystem. 657 **/ 658 static int __init igb_init_module(void) 659 { 660 int ret; 661 662 pr_info("%s\n", igb_driver_string); 663 pr_info("%s\n", igb_copyright); 664 665 #ifdef CONFIG_IGB_DCA 666 dca_register_notify(&dca_notifier); 667 #endif 668 ret = pci_register_driver(&igb_driver); 669 return ret; 670 } 671 672 module_init(igb_init_module); 673 674 /** 675 * igb_exit_module - Driver Exit Cleanup Routine 676 * 677 * igb_exit_module is called just before the driver is removed 678 * from memory. 679 **/ 680 static void __exit igb_exit_module(void) 681 { 682 #ifdef CONFIG_IGB_DCA 683 dca_unregister_notify(&dca_notifier); 684 #endif 685 pci_unregister_driver(&igb_driver); 686 } 687 688 module_exit(igb_exit_module); 689 690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 691 /** 692 * igb_cache_ring_register - Descriptor ring to register mapping 693 * @adapter: board private structure to initialize 694 * 695 * Once we know the feature-set enabled for the device, we'll cache 696 * the register offset the descriptor ring is assigned to. 697 **/ 698 static void igb_cache_ring_register(struct igb_adapter *adapter) 699 { 700 int i = 0, j = 0; 701 u32 rbase_offset = adapter->vfs_allocated_count; 702 703 switch (adapter->hw.mac.type) { 704 case e1000_82576: 705 /* The queues are allocated for virtualization such that VF 0 706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 707 * In order to avoid collision we start at the first free queue 708 * and continue consuming queues in the same sequence 709 */ 710 if (adapter->vfs_allocated_count) { 711 for (; i < adapter->rss_queues; i++) 712 adapter->rx_ring[i]->reg_idx = rbase_offset + 713 Q_IDX_82576(i); 714 } 715 fallthrough; 716 case e1000_82575: 717 case e1000_82580: 718 case e1000_i350: 719 case e1000_i354: 720 case e1000_i210: 721 case e1000_i211: 722 default: 723 for (; i < adapter->num_rx_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 725 for (; j < adapter->num_tx_queues; j++) 726 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 727 break; 728 } 729 } 730 731 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 732 { 733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 735 u32 value = 0; 736 737 if (E1000_REMOVED(hw_addr)) 738 return ~value; 739 740 value = readl(&hw_addr[reg]); 741 742 /* reads should not return all F's */ 743 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 744 struct net_device *netdev = igb->netdev; 745 hw->hw_addr = NULL; 746 netdev_err(netdev, "PCIe link lost\n"); 747 WARN(pci_device_is_present(igb->pdev), 748 "igb: Failed to read reg 0x%x!\n", reg); 749 } 750 751 return value; 752 } 753 754 /** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768 { 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778 } 779 780 #define IGB_N0_QUEUE -1 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782 { 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = BIT(msix_vector); 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = BIT(msix_vector); 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857 } 858 859 /** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866 static void igb_configure_msix(struct igb_adapter *adapter) 867 { 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = BIT(vector); 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923 } 924 925 /** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932 static int igb_request_msix(struct igb_adapter *adapter) 933 { 934 struct net_device *netdev = adapter->netdev; 935 int i, err = 0, vector = 0, free_vector = 0; 936 937 err = request_irq(adapter->msix_entries[vector].vector, 938 igb_msix_other, 0, netdev->name, adapter); 939 if (err) 940 goto err_out; 941 942 for (i = 0; i < adapter->num_q_vectors; i++) { 943 struct igb_q_vector *q_vector = adapter->q_vector[i]; 944 945 vector++; 946 947 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 948 949 if (q_vector->rx.ring && q_vector->tx.ring) 950 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 951 q_vector->rx.ring->queue_index); 952 else if (q_vector->tx.ring) 953 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 954 q_vector->tx.ring->queue_index); 955 else if (q_vector->rx.ring) 956 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 957 q_vector->rx.ring->queue_index); 958 else 959 sprintf(q_vector->name, "%s-unused", netdev->name); 960 961 err = request_irq(adapter->msix_entries[vector].vector, 962 igb_msix_ring, 0, q_vector->name, 963 q_vector); 964 if (err) 965 goto err_free; 966 } 967 968 igb_configure_msix(adapter); 969 return 0; 970 971 err_free: 972 /* free already assigned IRQs */ 973 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 974 975 vector--; 976 for (i = 0; i < vector; i++) { 977 free_irq(adapter->msix_entries[free_vector++].vector, 978 adapter->q_vector[i]); 979 } 980 err_out: 981 return err; 982 } 983 984 /** 985 * igb_free_q_vector - Free memory allocated for specific interrupt vector 986 * @adapter: board private structure to initialize 987 * @v_idx: Index of vector to be freed 988 * 989 * This function frees the memory allocated to the q_vector. 990 **/ 991 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 992 { 993 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 994 995 adapter->q_vector[v_idx] = NULL; 996 997 /* igb_get_stats64() might access the rings on this vector, 998 * we must wait a grace period before freeing it. 999 */ 1000 if (q_vector) 1001 kfree_rcu(q_vector, rcu); 1002 } 1003 1004 /** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013 { 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1017 * allocated. So, q_vector is NULL so we should stop here. 1018 */ 1019 if (!q_vector) 1020 return; 1021 1022 if (q_vector->tx.ring) 1023 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1024 1025 if (q_vector->rx.ring) 1026 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1027 1028 netif_napi_del(&q_vector->napi); 1029 1030 } 1031 1032 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1033 { 1034 int v_idx = adapter->num_q_vectors; 1035 1036 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1037 pci_disable_msix(adapter->pdev); 1038 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1039 pci_disable_msi(adapter->pdev); 1040 1041 while (v_idx--) 1042 igb_reset_q_vector(adapter, v_idx); 1043 } 1044 1045 /** 1046 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function frees the memory allocated to the q_vectors. In addition if 1050 * NAPI is enabled it will delete any references to the NAPI struct prior 1051 * to freeing the q_vector. 1052 **/ 1053 static void igb_free_q_vectors(struct igb_adapter *adapter) 1054 { 1055 int v_idx = adapter->num_q_vectors; 1056 1057 adapter->num_tx_queues = 0; 1058 adapter->num_rx_queues = 0; 1059 adapter->num_q_vectors = 0; 1060 1061 while (v_idx--) { 1062 igb_reset_q_vector(adapter, v_idx); 1063 igb_free_q_vector(adapter, v_idx); 1064 } 1065 } 1066 1067 /** 1068 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1072 * MSI-X interrupts allocated. 1073 */ 1074 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1075 { 1076 igb_free_q_vectors(adapter); 1077 igb_reset_interrupt_capability(adapter); 1078 } 1079 1080 /** 1081 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1082 * @adapter: board private structure to initialize 1083 * @msix: boolean value of MSIX capability 1084 * 1085 * Attempt to configure interrupts using the best available 1086 * capabilities of the hardware and kernel. 1087 **/ 1088 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1089 { 1090 int err; 1091 int numvecs, i; 1092 1093 if (!msix) 1094 goto msi_only; 1095 adapter->flags |= IGB_FLAG_HAS_MSIX; 1096 1097 /* Number of supported queues. */ 1098 adapter->num_rx_queues = adapter->rss_queues; 1099 if (adapter->vfs_allocated_count) 1100 adapter->num_tx_queues = 1; 1101 else 1102 adapter->num_tx_queues = adapter->rss_queues; 1103 1104 /* start with one vector for every Rx queue */ 1105 numvecs = adapter->num_rx_queues; 1106 1107 /* if Tx handler is separate add 1 for every Tx queue */ 1108 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1109 numvecs += adapter->num_tx_queues; 1110 1111 /* store the number of vectors reserved for queues */ 1112 adapter->num_q_vectors = numvecs; 1113 1114 /* add 1 vector for link status interrupts */ 1115 numvecs++; 1116 for (i = 0; i < numvecs; i++) 1117 adapter->msix_entries[i].entry = i; 1118 1119 err = pci_enable_msix_range(adapter->pdev, 1120 adapter->msix_entries, 1121 numvecs, 1122 numvecs); 1123 if (err > 0) 1124 return; 1125 1126 igb_reset_interrupt_capability(adapter); 1127 1128 /* If we can't do MSI-X, try MSI */ 1129 msi_only: 1130 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1131 #ifdef CONFIG_PCI_IOV 1132 /* disable SR-IOV for non MSI-X configurations */ 1133 if (adapter->vf_data) { 1134 struct e1000_hw *hw = &adapter->hw; 1135 /* disable iov and allow time for transactions to clear */ 1136 pci_disable_sriov(adapter->pdev); 1137 msleep(500); 1138 1139 kfree(adapter->vf_mac_list); 1140 adapter->vf_mac_list = NULL; 1141 kfree(adapter->vf_data); 1142 adapter->vf_data = NULL; 1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1144 wrfl(); 1145 msleep(100); 1146 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1147 } 1148 #endif 1149 adapter->vfs_allocated_count = 0; 1150 adapter->rss_queues = 1; 1151 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1152 adapter->num_rx_queues = 1; 1153 adapter->num_tx_queues = 1; 1154 adapter->num_q_vectors = 1; 1155 if (!pci_enable_msi(adapter->pdev)) 1156 adapter->flags |= IGB_FLAG_HAS_MSI; 1157 } 1158 1159 static void igb_add_ring(struct igb_ring *ring, 1160 struct igb_ring_container *head) 1161 { 1162 head->ring = ring; 1163 head->count++; 1164 } 1165 1166 /** 1167 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1168 * @adapter: board private structure to initialize 1169 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1170 * @v_idx: index of vector in adapter struct 1171 * @txr_count: total number of Tx rings to allocate 1172 * @txr_idx: index of first Tx ring to allocate 1173 * @rxr_count: total number of Rx rings to allocate 1174 * @rxr_idx: index of first Rx ring to allocate 1175 * 1176 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1177 **/ 1178 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1179 int v_count, int v_idx, 1180 int txr_count, int txr_idx, 1181 int rxr_count, int rxr_idx) 1182 { 1183 struct igb_q_vector *q_vector; 1184 struct igb_ring *ring; 1185 int ring_count; 1186 size_t size; 1187 1188 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1189 if (txr_count > 1 || rxr_count > 1) 1190 return -ENOMEM; 1191 1192 ring_count = txr_count + rxr_count; 1193 size = struct_size(q_vector, ring, ring_count); 1194 1195 /* allocate q_vector and rings */ 1196 q_vector = adapter->q_vector[v_idx]; 1197 if (!q_vector) { 1198 q_vector = kzalloc(size, GFP_KERNEL); 1199 } else if (size > ksize(q_vector)) { 1200 kfree_rcu(q_vector, rcu); 1201 q_vector = kzalloc(size, GFP_KERNEL); 1202 } else { 1203 memset(q_vector, 0, size); 1204 } 1205 if (!q_vector) 1206 return -ENOMEM; 1207 1208 /* initialize NAPI */ 1209 netif_napi_add(adapter->netdev, &q_vector->napi, 1210 igb_poll, 64); 1211 1212 /* tie q_vector and adapter together */ 1213 adapter->q_vector[v_idx] = q_vector; 1214 q_vector->adapter = adapter; 1215 1216 /* initialize work limits */ 1217 q_vector->tx.work_limit = adapter->tx_work_limit; 1218 1219 /* initialize ITR configuration */ 1220 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1221 q_vector->itr_val = IGB_START_ITR; 1222 1223 /* initialize pointer to rings */ 1224 ring = q_vector->ring; 1225 1226 /* intialize ITR */ 1227 if (rxr_count) { 1228 /* rx or rx/tx vector */ 1229 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1230 q_vector->itr_val = adapter->rx_itr_setting; 1231 } else { 1232 /* tx only vector */ 1233 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1234 q_vector->itr_val = adapter->tx_itr_setting; 1235 } 1236 1237 if (txr_count) { 1238 /* assign generic ring traits */ 1239 ring->dev = &adapter->pdev->dev; 1240 ring->netdev = adapter->netdev; 1241 1242 /* configure backlink on ring */ 1243 ring->q_vector = q_vector; 1244 1245 /* update q_vector Tx values */ 1246 igb_add_ring(ring, &q_vector->tx); 1247 1248 /* For 82575, context index must be unique per ring. */ 1249 if (adapter->hw.mac.type == e1000_82575) 1250 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1251 1252 /* apply Tx specific ring traits */ 1253 ring->count = adapter->tx_ring_count; 1254 ring->queue_index = txr_idx; 1255 1256 ring->cbs_enable = false; 1257 ring->idleslope = 0; 1258 ring->sendslope = 0; 1259 ring->hicredit = 0; 1260 ring->locredit = 0; 1261 1262 u64_stats_init(&ring->tx_syncp); 1263 u64_stats_init(&ring->tx_syncp2); 1264 1265 /* assign ring to adapter */ 1266 adapter->tx_ring[txr_idx] = ring; 1267 1268 /* push pointer to next ring */ 1269 ring++; 1270 } 1271 1272 if (rxr_count) { 1273 /* assign generic ring traits */ 1274 ring->dev = &adapter->pdev->dev; 1275 ring->netdev = adapter->netdev; 1276 1277 /* configure backlink on ring */ 1278 ring->q_vector = q_vector; 1279 1280 /* update q_vector Rx values */ 1281 igb_add_ring(ring, &q_vector->rx); 1282 1283 /* set flag indicating ring supports SCTP checksum offload */ 1284 if (adapter->hw.mac.type >= e1000_82576) 1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1286 1287 /* On i350, i354, i210, and i211, loopback VLAN packets 1288 * have the tag byte-swapped. 1289 */ 1290 if (adapter->hw.mac.type >= e1000_i350) 1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1292 1293 /* apply Rx specific ring traits */ 1294 ring->count = adapter->rx_ring_count; 1295 ring->queue_index = rxr_idx; 1296 1297 u64_stats_init(&ring->rx_syncp); 1298 1299 /* assign ring to adapter */ 1300 adapter->rx_ring[rxr_idx] = ring; 1301 } 1302 1303 return 0; 1304 } 1305 1306 1307 /** 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1309 * @adapter: board private structure to initialize 1310 * 1311 * We allocate one q_vector per queue interrupt. If allocation fails we 1312 * return -ENOMEM. 1313 **/ 1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1315 { 1316 int q_vectors = adapter->num_q_vectors; 1317 int rxr_remaining = adapter->num_rx_queues; 1318 int txr_remaining = adapter->num_tx_queues; 1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1320 int err; 1321 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1323 for (; rxr_remaining; v_idx++) { 1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1325 0, 0, 1, rxr_idx); 1326 1327 if (err) 1328 goto err_out; 1329 1330 /* update counts and index */ 1331 rxr_remaining--; 1332 rxr_idx++; 1333 } 1334 } 1335 1336 for (; v_idx < q_vectors; v_idx++) { 1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1339 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1341 tqpv, txr_idx, rqpv, rxr_idx); 1342 1343 if (err) 1344 goto err_out; 1345 1346 /* update counts and index */ 1347 rxr_remaining -= rqpv; 1348 txr_remaining -= tqpv; 1349 rxr_idx++; 1350 txr_idx++; 1351 } 1352 1353 return 0; 1354 1355 err_out: 1356 adapter->num_tx_queues = 0; 1357 adapter->num_rx_queues = 0; 1358 adapter->num_q_vectors = 0; 1359 1360 while (v_idx--) 1361 igb_free_q_vector(adapter, v_idx); 1362 1363 return -ENOMEM; 1364 } 1365 1366 /** 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1368 * @adapter: board private structure to initialize 1369 * @msix: boolean value of MSIX capability 1370 * 1371 * This function initializes the interrupts and allocates all of the queues. 1372 **/ 1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1374 { 1375 struct pci_dev *pdev = adapter->pdev; 1376 int err; 1377 1378 igb_set_interrupt_capability(adapter, msix); 1379 1380 err = igb_alloc_q_vectors(adapter); 1381 if (err) { 1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1383 goto err_alloc_q_vectors; 1384 } 1385 1386 igb_cache_ring_register(adapter); 1387 1388 return 0; 1389 1390 err_alloc_q_vectors: 1391 igb_reset_interrupt_capability(adapter); 1392 return err; 1393 } 1394 1395 /** 1396 * igb_request_irq - initialize interrupts 1397 * @adapter: board private structure to initialize 1398 * 1399 * Attempts to configure interrupts using the best available 1400 * capabilities of the hardware and kernel. 1401 **/ 1402 static int igb_request_irq(struct igb_adapter *adapter) 1403 { 1404 struct net_device *netdev = adapter->netdev; 1405 struct pci_dev *pdev = adapter->pdev; 1406 int err = 0; 1407 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1409 err = igb_request_msix(adapter); 1410 if (!err) 1411 goto request_done; 1412 /* fall back to MSI */ 1413 igb_free_all_tx_resources(adapter); 1414 igb_free_all_rx_resources(adapter); 1415 1416 igb_clear_interrupt_scheme(adapter); 1417 err = igb_init_interrupt_scheme(adapter, false); 1418 if (err) 1419 goto request_done; 1420 1421 igb_setup_all_tx_resources(adapter); 1422 igb_setup_all_rx_resources(adapter); 1423 igb_configure(adapter); 1424 } 1425 1426 igb_assign_vector(adapter->q_vector[0], 0); 1427 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1429 err = request_irq(pdev->irq, igb_intr_msi, 0, 1430 netdev->name, adapter); 1431 if (!err) 1432 goto request_done; 1433 1434 /* fall back to legacy interrupts */ 1435 igb_reset_interrupt_capability(adapter); 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1437 } 1438 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1440 netdev->name, adapter); 1441 1442 if (err) 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1444 err); 1445 1446 request_done: 1447 return err; 1448 } 1449 1450 static void igb_free_irq(struct igb_adapter *adapter) 1451 { 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1453 int vector = 0, i; 1454 1455 free_irq(adapter->msix_entries[vector++].vector, adapter); 1456 1457 for (i = 0; i < adapter->num_q_vectors; i++) 1458 free_irq(adapter->msix_entries[vector++].vector, 1459 adapter->q_vector[i]); 1460 } else { 1461 free_irq(adapter->pdev->irq, adapter); 1462 } 1463 } 1464 1465 /** 1466 * igb_irq_disable - Mask off interrupt generation on the NIC 1467 * @adapter: board private structure 1468 **/ 1469 static void igb_irq_disable(struct igb_adapter *adapter) 1470 { 1471 struct e1000_hw *hw = &adapter->hw; 1472 1473 /* we need to be careful when disabling interrupts. The VFs are also 1474 * mapped into these registers and so clearing the bits can cause 1475 * issues on the VF drivers so we only need to clear what we set 1476 */ 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1478 u32 regval = rd32(E1000_EIAM); 1479 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 1492 for (i = 0; i < adapter->num_q_vectors; i++) 1493 synchronize_irq(adapter->msix_entries[i].vector); 1494 } else { 1495 synchronize_irq(adapter->pdev->irq); 1496 } 1497 } 1498 1499 /** 1500 * igb_irq_enable - Enable default interrupt generation settings 1501 * @adapter: board private structure 1502 **/ 1503 static void igb_irq_enable(struct igb_adapter *adapter) 1504 { 1505 struct e1000_hw *hw = &adapter->hw; 1506 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1509 u32 regval = rd32(E1000_EIAC); 1510 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1512 regval = rd32(E1000_EIAM); 1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1514 wr32(E1000_EIMS, adapter->eims_enable_mask); 1515 if (adapter->vfs_allocated_count) { 1516 wr32(E1000_MBVFIMR, 0xFF); 1517 ims |= E1000_IMS_VMMB; 1518 } 1519 wr32(E1000_IMS, ims); 1520 } else { 1521 wr32(E1000_IMS, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 wr32(E1000_IAM, IMS_ENABLE_MASK | 1524 E1000_IMS_DRSTA); 1525 } 1526 } 1527 1528 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1529 { 1530 struct e1000_hw *hw = &adapter->hw; 1531 u16 pf_id = adapter->vfs_allocated_count; 1532 u16 vid = adapter->hw.mng_cookie.vlan_id; 1533 u16 old_vid = adapter->mng_vlan_id; 1534 1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1536 /* add VID to filter table */ 1537 igb_vfta_set(hw, vid, pf_id, true, true); 1538 adapter->mng_vlan_id = vid; 1539 } else { 1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1541 } 1542 1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1544 (vid != old_vid) && 1545 !test_bit(old_vid, adapter->active_vlans)) { 1546 /* remove VID from filter table */ 1547 igb_vfta_set(hw, vid, pf_id, false, true); 1548 } 1549 } 1550 1551 /** 1552 * igb_release_hw_control - release control of the h/w to f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that the 1557 * driver is no longer loaded. 1558 **/ 1559 static void igb_release_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware take over control of h/w */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 /** 1571 * igb_get_hw_control - get control of the h/w from f/w 1572 * @adapter: address of board private structure 1573 * 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1575 * For ASF and Pass Through versions of f/w this means that 1576 * the driver is loaded. 1577 **/ 1578 static void igb_get_hw_control(struct igb_adapter *adapter) 1579 { 1580 struct e1000_hw *hw = &adapter->hw; 1581 u32 ctrl_ext; 1582 1583 /* Let firmware know the driver has taken over */ 1584 ctrl_ext = rd32(E1000_CTRL_EXT); 1585 wr32(E1000_CTRL_EXT, 1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1587 } 1588 1589 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1590 { 1591 struct net_device *netdev = adapter->netdev; 1592 struct e1000_hw *hw = &adapter->hw; 1593 1594 WARN_ON(hw->mac.type != e1000_i210); 1595 1596 if (enable) 1597 adapter->flags |= IGB_FLAG_FQTSS; 1598 else 1599 adapter->flags &= ~IGB_FLAG_FQTSS; 1600 1601 if (netif_running(netdev)) 1602 schedule_work(&adapter->reset_task); 1603 } 1604 1605 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1606 { 1607 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1608 } 1609 1610 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1611 enum tx_queue_prio prio) 1612 { 1613 u32 val; 1614 1615 WARN_ON(hw->mac.type != e1000_i210); 1616 WARN_ON(queue < 0 || queue > 4); 1617 1618 val = rd32(E1000_I210_TXDCTL(queue)); 1619 1620 if (prio == TX_QUEUE_PRIO_HIGH) 1621 val |= E1000_TXDCTL_PRIORITY; 1622 else 1623 val &= ~E1000_TXDCTL_PRIORITY; 1624 1625 wr32(E1000_I210_TXDCTL(queue), val); 1626 } 1627 1628 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1629 { 1630 u32 val; 1631 1632 WARN_ON(hw->mac.type != e1000_i210); 1633 WARN_ON(queue < 0 || queue > 1); 1634 1635 val = rd32(E1000_I210_TQAVCC(queue)); 1636 1637 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1638 val |= E1000_TQAVCC_QUEUEMODE; 1639 else 1640 val &= ~E1000_TQAVCC_QUEUEMODE; 1641 1642 wr32(E1000_I210_TQAVCC(queue), val); 1643 } 1644 1645 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1646 { 1647 int i; 1648 1649 for (i = 0; i < adapter->num_tx_queues; i++) { 1650 if (adapter->tx_ring[i]->cbs_enable) 1651 return true; 1652 } 1653 1654 return false; 1655 } 1656 1657 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1658 { 1659 int i; 1660 1661 for (i = 0; i < adapter->num_tx_queues; i++) { 1662 if (adapter->tx_ring[i]->launchtime_enable) 1663 return true; 1664 } 1665 1666 return false; 1667 } 1668 1669 /** 1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1671 * @adapter: pointer to adapter struct 1672 * @queue: queue number 1673 * 1674 * Configure CBS and Launchtime for a given hardware queue. 1675 * Parameters are retrieved from the correct Tx ring, so 1676 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1677 * for setting those correctly prior to this function being called. 1678 **/ 1679 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1680 { 1681 struct igb_ring *ring = adapter->tx_ring[queue]; 1682 struct net_device *netdev = adapter->netdev; 1683 struct e1000_hw *hw = &adapter->hw; 1684 u32 tqavcc, tqavctrl; 1685 u16 value; 1686 1687 WARN_ON(hw->mac.type != e1000_i210); 1688 WARN_ON(queue < 0 || queue > 1); 1689 1690 /* If any of the Qav features is enabled, configure queues as SR and 1691 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1692 * as SP. 1693 */ 1694 if (ring->cbs_enable || ring->launchtime_enable) { 1695 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1696 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1697 } else { 1698 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1699 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1700 } 1701 1702 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1703 if (ring->cbs_enable || queue == 0) { 1704 /* i210 does not allow the queue 0 to be in the Strict 1705 * Priority mode while the Qav mode is enabled, so, 1706 * instead of disabling strict priority mode, we give 1707 * queue 0 the maximum of credits possible. 1708 * 1709 * See section 8.12.19 of the i210 datasheet, "Note: 1710 * Queue0 QueueMode must be set to 1b when 1711 * TransmitMode is set to Qav." 1712 */ 1713 if (queue == 0 && !ring->cbs_enable) { 1714 /* max "linkspeed" idleslope in kbps */ 1715 ring->idleslope = 1000000; 1716 ring->hicredit = ETH_FRAME_LEN; 1717 } 1718 1719 /* Always set data transfer arbitration to credit-based 1720 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1721 * the queues. 1722 */ 1723 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1724 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1725 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1726 1727 /* According to i210 datasheet section 7.2.7.7, we should set 1728 * the 'idleSlope' field from TQAVCC register following the 1729 * equation: 1730 * 1731 * For 100 Mbps link speed: 1732 * 1733 * value = BW * 0x7735 * 0.2 (E1) 1734 * 1735 * For 1000Mbps link speed: 1736 * 1737 * value = BW * 0x7735 * 2 (E2) 1738 * 1739 * E1 and E2 can be merged into one equation as shown below. 1740 * Note that 'link-speed' is in Mbps. 1741 * 1742 * value = BW * 0x7735 * 2 * link-speed 1743 * -------------- (E3) 1744 * 1000 1745 * 1746 * 'BW' is the percentage bandwidth out of full link speed 1747 * which can be found with the following equation. Note that 1748 * idleSlope here is the parameter from this function which 1749 * is in kbps. 1750 * 1751 * BW = idleSlope 1752 * ----------------- (E4) 1753 * link-speed * 1000 1754 * 1755 * That said, we can come up with a generic equation to 1756 * calculate the value we should set it TQAVCC register by 1757 * replacing 'BW' in E3 by E4. The resulting equation is: 1758 * 1759 * value = idleSlope * 0x7735 * 2 * link-speed 1760 * ----------------- -------------- (E5) 1761 * link-speed * 1000 1000 1762 * 1763 * 'link-speed' is present in both sides of the fraction so 1764 * it is canceled out. The final equation is the following: 1765 * 1766 * value = idleSlope * 61034 1767 * ----------------- (E6) 1768 * 1000000 1769 * 1770 * NOTE: For i210, given the above, we can see that idleslope 1771 * is represented in 16.38431 kbps units by the value at 1772 * the TQAVCC register (1Gbps / 61034), which reduces 1773 * the granularity for idleslope increments. 1774 * For instance, if you want to configure a 2576kbps 1775 * idleslope, the value to be written on the register 1776 * would have to be 157.23. If rounded down, you end 1777 * up with less bandwidth available than originally 1778 * required (~2572 kbps). If rounded up, you end up 1779 * with a higher bandwidth (~2589 kbps). Below the 1780 * approach we take is to always round up the 1781 * calculated value, so the resulting bandwidth might 1782 * be slightly higher for some configurations. 1783 */ 1784 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1785 1786 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1787 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1788 tqavcc |= value; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 wr32(E1000_I210_TQAVHC(queue), 1792 0x80000000 + ring->hicredit * 0x7735); 1793 } else { 1794 1795 /* Set idleSlope to zero. */ 1796 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1797 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 /* Set hiCredit to zero. */ 1801 wr32(E1000_I210_TQAVHC(queue), 0); 1802 1803 /* If CBS is not enabled for any queues anymore, then return to 1804 * the default state of Data Transmission Arbitration on 1805 * TQAVCTRL. 1806 */ 1807 if (!is_any_cbs_enabled(adapter)) { 1808 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1809 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1810 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1811 } 1812 } 1813 1814 /* If LaunchTime is enabled, set DataTranTIM. */ 1815 if (ring->launchtime_enable) { 1816 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1817 * for any of the SR queues, and configure fetchtime delta. 1818 * XXX NOTE: 1819 * - LaunchTime will be enabled for all SR queues. 1820 * - A fixed offset can be added relative to the launch 1821 * time of all packets if configured at reg LAUNCH_OS0. 1822 * We are keeping it as 0 for now (default value). 1823 */ 1824 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1825 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1826 E1000_TQAVCTRL_FETCHTIME_DELTA; 1827 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1828 } else { 1829 /* If Launchtime is not enabled for any SR queues anymore, 1830 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1831 * effectively disabling Launchtime. 1832 */ 1833 if (!is_any_txtime_enabled(adapter)) { 1834 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1835 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1836 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1837 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1838 } 1839 } 1840 1841 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1842 * CBS are not configurable by software so we don't do any 'controller 1843 * configuration' in respect to these parameters. 1844 */ 1845 1846 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1847 ring->cbs_enable ? "enabled" : "disabled", 1848 ring->launchtime_enable ? "enabled" : "disabled", 1849 queue, 1850 ring->idleslope, ring->sendslope, 1851 ring->hicredit, ring->locredit); 1852 } 1853 1854 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1855 bool enable) 1856 { 1857 struct igb_ring *ring; 1858 1859 if (queue < 0 || queue > adapter->num_tx_queues) 1860 return -EINVAL; 1861 1862 ring = adapter->tx_ring[queue]; 1863 ring->launchtime_enable = enable; 1864 1865 return 0; 1866 } 1867 1868 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1869 bool enable, int idleslope, int sendslope, 1870 int hicredit, int locredit) 1871 { 1872 struct igb_ring *ring; 1873 1874 if (queue < 0 || queue > adapter->num_tx_queues) 1875 return -EINVAL; 1876 1877 ring = adapter->tx_ring[queue]; 1878 1879 ring->cbs_enable = enable; 1880 ring->idleslope = idleslope; 1881 ring->sendslope = sendslope; 1882 ring->hicredit = hicredit; 1883 ring->locredit = locredit; 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1890 * @adapter: pointer to adapter struct 1891 * 1892 * Configure TQAVCTRL register switching the controller's Tx mode 1893 * if FQTSS mode is enabled or disabled. Additionally, will issue 1894 * a call to igb_config_tx_modes() per queue so any previously saved 1895 * Tx parameters are applied. 1896 **/ 1897 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1898 { 1899 struct net_device *netdev = adapter->netdev; 1900 struct e1000_hw *hw = &adapter->hw; 1901 u32 val; 1902 1903 /* Only i210 controller supports changing the transmission mode. */ 1904 if (hw->mac.type != e1000_i210) 1905 return; 1906 1907 if (is_fqtss_enabled(adapter)) { 1908 int i, max_queue; 1909 1910 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1911 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1912 * so SP queues wait for SR ones. 1913 */ 1914 val = rd32(E1000_I210_TQAVCTRL); 1915 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1916 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1917 wr32(E1000_I210_TQAVCTRL, val); 1918 1919 /* Configure Tx and Rx packet buffers sizes as described in 1920 * i210 datasheet section 7.2.7.7. 1921 */ 1922 val = rd32(E1000_TXPBS); 1923 val &= ~I210_TXPBSIZE_MASK; 1924 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1925 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1926 wr32(E1000_TXPBS, val); 1927 1928 val = rd32(E1000_RXPBS); 1929 val &= ~I210_RXPBSIZE_MASK; 1930 val |= I210_RXPBSIZE_PB_30KB; 1931 wr32(E1000_RXPBS, val); 1932 1933 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1934 * register should not exceed the buffer size programmed in 1935 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1936 * so according to the datasheet we should set MAX_TPKT_SIZE to 1937 * 4kB / 64. 1938 * 1939 * However, when we do so, no frame from queue 2 and 3 are 1940 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1941 * or _equal_ to the buffer size programmed in TXPBS. For this 1942 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1943 */ 1944 val = (4096 - 1) / 64; 1945 wr32(E1000_I210_DTXMXPKTSZ, val); 1946 1947 /* Since FQTSS mode is enabled, apply any CBS configuration 1948 * previously set. If no previous CBS configuration has been 1949 * done, then the initial configuration is applied, which means 1950 * CBS is disabled. 1951 */ 1952 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1953 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1954 1955 for (i = 0; i < max_queue; i++) { 1956 igb_config_tx_modes(adapter, i); 1957 } 1958 } else { 1959 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1960 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1961 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1962 1963 val = rd32(E1000_I210_TQAVCTRL); 1964 /* According to Section 8.12.21, the other flags we've set when 1965 * enabling FQTSS are not relevant when disabling FQTSS so we 1966 * don't set they here. 1967 */ 1968 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1969 wr32(E1000_I210_TQAVCTRL, val); 1970 } 1971 1972 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1973 "enabled" : "disabled"); 1974 } 1975 1976 /** 1977 * igb_configure - configure the hardware for RX and TX 1978 * @adapter: private board structure 1979 **/ 1980 static void igb_configure(struct igb_adapter *adapter) 1981 { 1982 struct net_device *netdev = adapter->netdev; 1983 int i; 1984 1985 igb_get_hw_control(adapter); 1986 igb_set_rx_mode(netdev); 1987 igb_setup_tx_mode(adapter); 1988 1989 igb_restore_vlan(adapter); 1990 1991 igb_setup_tctl(adapter); 1992 igb_setup_mrqc(adapter); 1993 igb_setup_rctl(adapter); 1994 1995 igb_nfc_filter_restore(adapter); 1996 igb_configure_tx(adapter); 1997 igb_configure_rx(adapter); 1998 1999 igb_rx_fifo_flush_82575(&adapter->hw); 2000 2001 /* call igb_desc_unused which always leaves 2002 * at least 1 descriptor unused to make sure 2003 * next_to_use != next_to_clean 2004 */ 2005 for (i = 0; i < adapter->num_rx_queues; i++) { 2006 struct igb_ring *ring = adapter->rx_ring[i]; 2007 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2008 } 2009 } 2010 2011 /** 2012 * igb_power_up_link - Power up the phy/serdes link 2013 * @adapter: address of board private structure 2014 **/ 2015 void igb_power_up_link(struct igb_adapter *adapter) 2016 { 2017 igb_reset_phy(&adapter->hw); 2018 2019 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2020 igb_power_up_phy_copper(&adapter->hw); 2021 else 2022 igb_power_up_serdes_link_82575(&adapter->hw); 2023 2024 igb_setup_link(&adapter->hw); 2025 } 2026 2027 /** 2028 * igb_power_down_link - Power down the phy/serdes link 2029 * @adapter: address of board private structure 2030 */ 2031 static void igb_power_down_link(struct igb_adapter *adapter) 2032 { 2033 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2034 igb_power_down_phy_copper_82575(&adapter->hw); 2035 else 2036 igb_shutdown_serdes_link_82575(&adapter->hw); 2037 } 2038 2039 /** 2040 * Detect and switch function for Media Auto Sense 2041 * @adapter: address of the board private structure 2042 **/ 2043 static void igb_check_swap_media(struct igb_adapter *adapter) 2044 { 2045 struct e1000_hw *hw = &adapter->hw; 2046 u32 ctrl_ext, connsw; 2047 bool swap_now = false; 2048 2049 ctrl_ext = rd32(E1000_CTRL_EXT); 2050 connsw = rd32(E1000_CONNSW); 2051 2052 /* need to live swap if current media is copper and we have fiber/serdes 2053 * to go to. 2054 */ 2055 2056 if ((hw->phy.media_type == e1000_media_type_copper) && 2057 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2058 swap_now = true; 2059 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2060 !(connsw & E1000_CONNSW_SERDESD)) { 2061 /* copper signal takes time to appear */ 2062 if (adapter->copper_tries < 4) { 2063 adapter->copper_tries++; 2064 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2065 wr32(E1000_CONNSW, connsw); 2066 return; 2067 } else { 2068 adapter->copper_tries = 0; 2069 if ((connsw & E1000_CONNSW_PHYSD) && 2070 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2071 swap_now = true; 2072 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 } 2075 } 2076 } 2077 2078 if (!swap_now) 2079 return; 2080 2081 switch (hw->phy.media_type) { 2082 case e1000_media_type_copper: 2083 netdev_info(adapter->netdev, 2084 "MAS: changing media to fiber/serdes\n"); 2085 ctrl_ext |= 2086 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2087 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2088 adapter->copper_tries = 0; 2089 break; 2090 case e1000_media_type_internal_serdes: 2091 case e1000_media_type_fiber: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to copper\n"); 2094 ctrl_ext &= 2095 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 break; 2098 default: 2099 /* shouldn't get here during regular operation */ 2100 netdev_err(adapter->netdev, 2101 "AMS: Invalid media type found, returning\n"); 2102 break; 2103 } 2104 wr32(E1000_CTRL_EXT, ctrl_ext); 2105 } 2106 2107 /** 2108 * igb_up - Open the interface and prepare it to handle traffic 2109 * @adapter: board private structure 2110 **/ 2111 int igb_up(struct igb_adapter *adapter) 2112 { 2113 struct e1000_hw *hw = &adapter->hw; 2114 int i; 2115 2116 /* hardware has been reset, we need to reload some things */ 2117 igb_configure(adapter); 2118 2119 clear_bit(__IGB_DOWN, &adapter->state); 2120 2121 for (i = 0; i < adapter->num_q_vectors; i++) 2122 napi_enable(&(adapter->q_vector[i]->napi)); 2123 2124 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2125 igb_configure_msix(adapter); 2126 else 2127 igb_assign_vector(adapter->q_vector[0], 0); 2128 2129 /* Clear any pending interrupts. */ 2130 rd32(E1000_TSICR); 2131 rd32(E1000_ICR); 2132 igb_irq_enable(adapter); 2133 2134 /* notify VFs that reset has been completed */ 2135 if (adapter->vfs_allocated_count) { 2136 u32 reg_data = rd32(E1000_CTRL_EXT); 2137 2138 reg_data |= E1000_CTRL_EXT_PFRSTD; 2139 wr32(E1000_CTRL_EXT, reg_data); 2140 } 2141 2142 netif_tx_start_all_queues(adapter->netdev); 2143 2144 /* start the watchdog. */ 2145 hw->mac.get_link_status = 1; 2146 schedule_work(&adapter->watchdog_task); 2147 2148 if ((adapter->flags & IGB_FLAG_EEE) && 2149 (!hw->dev_spec._82575.eee_disable)) 2150 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2151 2152 return 0; 2153 } 2154 2155 void igb_down(struct igb_adapter *adapter) 2156 { 2157 struct net_device *netdev = adapter->netdev; 2158 struct e1000_hw *hw = &adapter->hw; 2159 u32 tctl, rctl; 2160 int i; 2161 2162 /* signal that we're down so the interrupt handler does not 2163 * reschedule our watchdog timer 2164 */ 2165 set_bit(__IGB_DOWN, &adapter->state); 2166 2167 /* disable receives in the hardware */ 2168 rctl = rd32(E1000_RCTL); 2169 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2170 /* flush and sleep below */ 2171 2172 igb_nfc_filter_exit(adapter); 2173 2174 netif_carrier_off(netdev); 2175 netif_tx_stop_all_queues(netdev); 2176 2177 /* disable transmits in the hardware */ 2178 tctl = rd32(E1000_TCTL); 2179 tctl &= ~E1000_TCTL_EN; 2180 wr32(E1000_TCTL, tctl); 2181 /* flush both disables and wait for them to finish */ 2182 wrfl(); 2183 usleep_range(10000, 11000); 2184 2185 igb_irq_disable(adapter); 2186 2187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2188 2189 for (i = 0; i < adapter->num_q_vectors; i++) { 2190 if (adapter->q_vector[i]) { 2191 napi_synchronize(&adapter->q_vector[i]->napi); 2192 napi_disable(&adapter->q_vector[i]->napi); 2193 } 2194 } 2195 2196 del_timer_sync(&adapter->watchdog_timer); 2197 del_timer_sync(&adapter->phy_info_timer); 2198 2199 /* record the stats before reset*/ 2200 spin_lock(&adapter->stats64_lock); 2201 igb_update_stats(adapter); 2202 spin_unlock(&adapter->stats64_lock); 2203 2204 adapter->link_speed = 0; 2205 adapter->link_duplex = 0; 2206 2207 if (!pci_channel_offline(adapter->pdev)) 2208 igb_reset(adapter); 2209 2210 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2211 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2212 2213 igb_clean_all_tx_rings(adapter); 2214 igb_clean_all_rx_rings(adapter); 2215 #ifdef CONFIG_IGB_DCA 2216 2217 /* since we reset the hardware DCA settings were cleared */ 2218 igb_setup_dca(adapter); 2219 #endif 2220 } 2221 2222 void igb_reinit_locked(struct igb_adapter *adapter) 2223 { 2224 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2225 usleep_range(1000, 2000); 2226 igb_down(adapter); 2227 igb_up(adapter); 2228 clear_bit(__IGB_RESETTING, &adapter->state); 2229 } 2230 2231 /** igb_enable_mas - Media Autosense re-enable after swap 2232 * 2233 * @adapter: adapter struct 2234 **/ 2235 static void igb_enable_mas(struct igb_adapter *adapter) 2236 { 2237 struct e1000_hw *hw = &adapter->hw; 2238 u32 connsw = rd32(E1000_CONNSW); 2239 2240 /* configure for SerDes media detect */ 2241 if ((hw->phy.media_type == e1000_media_type_copper) && 2242 (!(connsw & E1000_CONNSW_SERDESD))) { 2243 connsw |= E1000_CONNSW_ENRGSRC; 2244 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2245 wr32(E1000_CONNSW, connsw); 2246 wrfl(); 2247 } 2248 } 2249 2250 void igb_reset(struct igb_adapter *adapter) 2251 { 2252 struct pci_dev *pdev = adapter->pdev; 2253 struct e1000_hw *hw = &adapter->hw; 2254 struct e1000_mac_info *mac = &hw->mac; 2255 struct e1000_fc_info *fc = &hw->fc; 2256 u32 pba, hwm; 2257 2258 /* Repartition Pba for greater than 9k mtu 2259 * To take effect CTRL.RST is required. 2260 */ 2261 switch (mac->type) { 2262 case e1000_i350: 2263 case e1000_i354: 2264 case e1000_82580: 2265 pba = rd32(E1000_RXPBS); 2266 pba = igb_rxpbs_adjust_82580(pba); 2267 break; 2268 case e1000_82576: 2269 pba = rd32(E1000_RXPBS); 2270 pba &= E1000_RXPBS_SIZE_MASK_82576; 2271 break; 2272 case e1000_82575: 2273 case e1000_i210: 2274 case e1000_i211: 2275 default: 2276 pba = E1000_PBA_34K; 2277 break; 2278 } 2279 2280 if (mac->type == e1000_82575) { 2281 u32 min_rx_space, min_tx_space, needed_tx_space; 2282 2283 /* write Rx PBA so that hardware can report correct Tx PBA */ 2284 wr32(E1000_PBA, pba); 2285 2286 /* To maintain wire speed transmits, the Tx FIFO should be 2287 * large enough to accommodate two full transmit packets, 2288 * rounded up to the next 1KB and expressed in KB. Likewise, 2289 * the Rx FIFO should be large enough to accommodate at least 2290 * one full receive packet and is similarly rounded up and 2291 * expressed in KB. 2292 */ 2293 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2294 2295 /* The Tx FIFO also stores 16 bytes of information about the Tx 2296 * but don't include Ethernet FCS because hardware appends it. 2297 * We only need to round down to the nearest 512 byte block 2298 * count since the value we care about is 2 frames, not 1. 2299 */ 2300 min_tx_space = adapter->max_frame_size; 2301 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2302 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2303 2304 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2305 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2306 2307 /* If current Tx allocation is less than the min Tx FIFO size, 2308 * and the min Tx FIFO size is less than the current Rx FIFO 2309 * allocation, take space away from current Rx allocation. 2310 */ 2311 if (needed_tx_space < pba) { 2312 pba -= needed_tx_space; 2313 2314 /* if short on Rx space, Rx wins and must trump Tx 2315 * adjustment 2316 */ 2317 if (pba < min_rx_space) 2318 pba = min_rx_space; 2319 } 2320 2321 /* adjust PBA for jumbo frames */ 2322 wr32(E1000_PBA, pba); 2323 } 2324 2325 /* flow control settings 2326 * The high water mark must be low enough to fit one full frame 2327 * after transmitting the pause frame. As such we must have enough 2328 * space to allow for us to complete our current transmit and then 2329 * receive the frame that is in progress from the link partner. 2330 * Set it to: 2331 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2332 */ 2333 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2334 2335 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2336 fc->low_water = fc->high_water - 16; 2337 fc->pause_time = 0xFFFF; 2338 fc->send_xon = 1; 2339 fc->current_mode = fc->requested_mode; 2340 2341 /* disable receive for all VFs and wait one second */ 2342 if (adapter->vfs_allocated_count) { 2343 int i; 2344 2345 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2346 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2347 2348 /* ping all the active vfs to let them know we are going down */ 2349 igb_ping_all_vfs(adapter); 2350 2351 /* disable transmits and receives */ 2352 wr32(E1000_VFRE, 0); 2353 wr32(E1000_VFTE, 0); 2354 } 2355 2356 /* Allow time for pending master requests to run */ 2357 hw->mac.ops.reset_hw(hw); 2358 wr32(E1000_WUC, 0); 2359 2360 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2361 /* need to resetup here after media swap */ 2362 adapter->ei.get_invariants(hw); 2363 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2364 } 2365 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2366 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2367 igb_enable_mas(adapter); 2368 } 2369 if (hw->mac.ops.init_hw(hw)) 2370 dev_err(&pdev->dev, "Hardware Error\n"); 2371 2372 /* RAR registers were cleared during init_hw, clear mac table */ 2373 igb_flush_mac_table(adapter); 2374 __dev_uc_unsync(adapter->netdev, NULL); 2375 2376 /* Recover default RAR entry */ 2377 igb_set_default_mac_filter(adapter); 2378 2379 /* Flow control settings reset on hardware reset, so guarantee flow 2380 * control is off when forcing speed. 2381 */ 2382 if (!hw->mac.autoneg) 2383 igb_force_mac_fc(hw); 2384 2385 igb_init_dmac(adapter, pba); 2386 #ifdef CONFIG_IGB_HWMON 2387 /* Re-initialize the thermal sensor on i350 devices. */ 2388 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2389 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2390 /* If present, re-initialize the external thermal sensor 2391 * interface. 2392 */ 2393 if (adapter->ets) 2394 mac->ops.init_thermal_sensor_thresh(hw); 2395 } 2396 } 2397 #endif 2398 /* Re-establish EEE setting */ 2399 if (hw->phy.media_type == e1000_media_type_copper) { 2400 switch (mac->type) { 2401 case e1000_i350: 2402 case e1000_i210: 2403 case e1000_i211: 2404 igb_set_eee_i350(hw, true, true); 2405 break; 2406 case e1000_i354: 2407 igb_set_eee_i354(hw, true, true); 2408 break; 2409 default: 2410 break; 2411 } 2412 } 2413 if (!netif_running(adapter->netdev)) 2414 igb_power_down_link(adapter); 2415 2416 igb_update_mng_vlan(adapter); 2417 2418 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2419 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2420 2421 /* Re-enable PTP, where applicable. */ 2422 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2423 igb_ptp_reset(adapter); 2424 2425 igb_get_phy_info(hw); 2426 } 2427 2428 static netdev_features_t igb_fix_features(struct net_device *netdev, 2429 netdev_features_t features) 2430 { 2431 /* Since there is no support for separate Rx/Tx vlan accel 2432 * enable/disable make sure Tx flag is always in same state as Rx. 2433 */ 2434 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2435 features |= NETIF_F_HW_VLAN_CTAG_TX; 2436 else 2437 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2438 2439 return features; 2440 } 2441 2442 static int igb_set_features(struct net_device *netdev, 2443 netdev_features_t features) 2444 { 2445 netdev_features_t changed = netdev->features ^ features; 2446 struct igb_adapter *adapter = netdev_priv(netdev); 2447 2448 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2449 igb_vlan_mode(netdev, features); 2450 2451 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2452 return 0; 2453 2454 if (!(features & NETIF_F_NTUPLE)) { 2455 struct hlist_node *node2; 2456 struct igb_nfc_filter *rule; 2457 2458 spin_lock(&adapter->nfc_lock); 2459 hlist_for_each_entry_safe(rule, node2, 2460 &adapter->nfc_filter_list, nfc_node) { 2461 igb_erase_filter(adapter, rule); 2462 hlist_del(&rule->nfc_node); 2463 kfree(rule); 2464 } 2465 spin_unlock(&adapter->nfc_lock); 2466 adapter->nfc_filter_count = 0; 2467 } 2468 2469 netdev->features = features; 2470 2471 if (netif_running(netdev)) 2472 igb_reinit_locked(adapter); 2473 else 2474 igb_reset(adapter); 2475 2476 return 1; 2477 } 2478 2479 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2480 struct net_device *dev, 2481 const unsigned char *addr, u16 vid, 2482 u16 flags, 2483 struct netlink_ext_ack *extack) 2484 { 2485 /* guarantee we can provide a unique filter for the unicast address */ 2486 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2487 struct igb_adapter *adapter = netdev_priv(dev); 2488 int vfn = adapter->vfs_allocated_count; 2489 2490 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2491 return -ENOMEM; 2492 } 2493 2494 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2495 } 2496 2497 #define IGB_MAX_MAC_HDR_LEN 127 2498 #define IGB_MAX_NETWORK_HDR_LEN 511 2499 2500 static netdev_features_t 2501 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2502 netdev_features_t features) 2503 { 2504 unsigned int network_hdr_len, mac_hdr_len; 2505 2506 /* Make certain the headers can be described by a context descriptor */ 2507 mac_hdr_len = skb_network_header(skb) - skb->data; 2508 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2509 return features & ~(NETIF_F_HW_CSUM | 2510 NETIF_F_SCTP_CRC | 2511 NETIF_F_GSO_UDP_L4 | 2512 NETIF_F_HW_VLAN_CTAG_TX | 2513 NETIF_F_TSO | 2514 NETIF_F_TSO6); 2515 2516 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2517 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_TSO | 2522 NETIF_F_TSO6); 2523 2524 /* We can only support IPV4 TSO in tunnels if we can mangle the 2525 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2526 */ 2527 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2528 features &= ~NETIF_F_TSO; 2529 2530 return features; 2531 } 2532 2533 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2534 { 2535 if (!is_fqtss_enabled(adapter)) { 2536 enable_fqtss(adapter, true); 2537 return; 2538 } 2539 2540 igb_config_tx_modes(adapter, queue); 2541 2542 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2543 enable_fqtss(adapter, false); 2544 } 2545 2546 static int igb_offload_cbs(struct igb_adapter *adapter, 2547 struct tc_cbs_qopt_offload *qopt) 2548 { 2549 struct e1000_hw *hw = &adapter->hw; 2550 int err; 2551 2552 /* CBS offloading is only supported by i210 controller. */ 2553 if (hw->mac.type != e1000_i210) 2554 return -EOPNOTSUPP; 2555 2556 /* CBS offloading is only supported by queue 0 and queue 1. */ 2557 if (qopt->queue < 0 || qopt->queue > 1) 2558 return -EINVAL; 2559 2560 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2561 qopt->idleslope, qopt->sendslope, 2562 qopt->hicredit, qopt->locredit); 2563 if (err) 2564 return err; 2565 2566 igb_offload_apply(adapter, qopt->queue); 2567 2568 return 0; 2569 } 2570 2571 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2572 #define VLAN_PRIO_FULL_MASK (0x07) 2573 2574 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2575 struct flow_cls_offload *f, 2576 int traffic_class, 2577 struct igb_nfc_filter *input) 2578 { 2579 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2580 struct flow_dissector *dissector = rule->match.dissector; 2581 struct netlink_ext_ack *extack = f->common.extack; 2582 2583 if (dissector->used_keys & 2584 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2585 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2586 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2587 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2588 NL_SET_ERR_MSG_MOD(extack, 2589 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2590 return -EOPNOTSUPP; 2591 } 2592 2593 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2594 struct flow_match_eth_addrs match; 2595 2596 flow_rule_match_eth_addrs(rule, &match); 2597 if (!is_zero_ether_addr(match.mask->dst)) { 2598 if (!is_broadcast_ether_addr(match.mask->dst)) { 2599 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2600 return -EINVAL; 2601 } 2602 2603 input->filter.match_flags |= 2604 IGB_FILTER_FLAG_DST_MAC_ADDR; 2605 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2606 } 2607 2608 if (!is_zero_ether_addr(match.mask->src)) { 2609 if (!is_broadcast_ether_addr(match.mask->src)) { 2610 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2611 return -EINVAL; 2612 } 2613 2614 input->filter.match_flags |= 2615 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2616 ether_addr_copy(input->filter.src_addr, match.key->src); 2617 } 2618 } 2619 2620 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2621 struct flow_match_basic match; 2622 2623 flow_rule_match_basic(rule, &match); 2624 if (match.mask->n_proto) { 2625 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2626 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2627 return -EINVAL; 2628 } 2629 2630 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2631 input->filter.etype = match.key->n_proto; 2632 } 2633 } 2634 2635 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2636 struct flow_match_vlan match; 2637 2638 flow_rule_match_vlan(rule, &match); 2639 if (match.mask->vlan_priority) { 2640 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2641 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2642 return -EINVAL; 2643 } 2644 2645 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2646 input->filter.vlan_tci = match.key->vlan_priority; 2647 } 2648 } 2649 2650 input->action = traffic_class; 2651 input->cookie = f->cookie; 2652 2653 return 0; 2654 } 2655 2656 static int igb_configure_clsflower(struct igb_adapter *adapter, 2657 struct flow_cls_offload *cls_flower) 2658 { 2659 struct netlink_ext_ack *extack = cls_flower->common.extack; 2660 struct igb_nfc_filter *filter, *f; 2661 int err, tc; 2662 2663 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2664 if (tc < 0) { 2665 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2666 return -EINVAL; 2667 } 2668 2669 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2670 if (!filter) 2671 return -ENOMEM; 2672 2673 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2674 if (err < 0) 2675 goto err_parse; 2676 2677 spin_lock(&adapter->nfc_lock); 2678 2679 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2680 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2681 err = -EEXIST; 2682 NL_SET_ERR_MSG_MOD(extack, 2683 "This filter is already set in ethtool"); 2684 goto err_locked; 2685 } 2686 } 2687 2688 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2690 err = -EEXIST; 2691 NL_SET_ERR_MSG_MOD(extack, 2692 "This filter is already set in cls_flower"); 2693 goto err_locked; 2694 } 2695 } 2696 2697 err = igb_add_filter(adapter, filter); 2698 if (err < 0) { 2699 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2700 goto err_locked; 2701 } 2702 2703 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2704 2705 spin_unlock(&adapter->nfc_lock); 2706 2707 return 0; 2708 2709 err_locked: 2710 spin_unlock(&adapter->nfc_lock); 2711 2712 err_parse: 2713 kfree(filter); 2714 2715 return err; 2716 } 2717 2718 static int igb_delete_clsflower(struct igb_adapter *adapter, 2719 struct flow_cls_offload *cls_flower) 2720 { 2721 struct igb_nfc_filter *filter; 2722 int err; 2723 2724 spin_lock(&adapter->nfc_lock); 2725 2726 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2727 if (filter->cookie == cls_flower->cookie) 2728 break; 2729 2730 if (!filter) { 2731 err = -ENOENT; 2732 goto out; 2733 } 2734 2735 err = igb_erase_filter(adapter, filter); 2736 if (err < 0) 2737 goto out; 2738 2739 hlist_del(&filter->nfc_node); 2740 kfree(filter); 2741 2742 out: 2743 spin_unlock(&adapter->nfc_lock); 2744 2745 return err; 2746 } 2747 2748 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2749 struct flow_cls_offload *cls_flower) 2750 { 2751 switch (cls_flower->command) { 2752 case FLOW_CLS_REPLACE: 2753 return igb_configure_clsflower(adapter, cls_flower); 2754 case FLOW_CLS_DESTROY: 2755 return igb_delete_clsflower(adapter, cls_flower); 2756 case FLOW_CLS_STATS: 2757 return -EOPNOTSUPP; 2758 default: 2759 return -EOPNOTSUPP; 2760 } 2761 } 2762 2763 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2764 void *cb_priv) 2765 { 2766 struct igb_adapter *adapter = cb_priv; 2767 2768 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2769 return -EOPNOTSUPP; 2770 2771 switch (type) { 2772 case TC_SETUP_CLSFLOWER: 2773 return igb_setup_tc_cls_flower(adapter, type_data); 2774 2775 default: 2776 return -EOPNOTSUPP; 2777 } 2778 } 2779 2780 static int igb_offload_txtime(struct igb_adapter *adapter, 2781 struct tc_etf_qopt_offload *qopt) 2782 { 2783 struct e1000_hw *hw = &adapter->hw; 2784 int err; 2785 2786 /* Launchtime offloading is only supported by i210 controller. */ 2787 if (hw->mac.type != e1000_i210) 2788 return -EOPNOTSUPP; 2789 2790 /* Launchtime offloading is only supported by queues 0 and 1. */ 2791 if (qopt->queue < 0 || qopt->queue > 1) 2792 return -EINVAL; 2793 2794 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2795 if (err) 2796 return err; 2797 2798 igb_offload_apply(adapter, qopt->queue); 2799 2800 return 0; 2801 } 2802 2803 static LIST_HEAD(igb_block_cb_list); 2804 2805 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2806 void *type_data) 2807 { 2808 struct igb_adapter *adapter = netdev_priv(dev); 2809 2810 switch (type) { 2811 case TC_SETUP_QDISC_CBS: 2812 return igb_offload_cbs(adapter, type_data); 2813 case TC_SETUP_BLOCK: 2814 return flow_block_cb_setup_simple(type_data, 2815 &igb_block_cb_list, 2816 igb_setup_tc_block_cb, 2817 adapter, adapter, true); 2818 2819 case TC_SETUP_QDISC_ETF: 2820 return igb_offload_txtime(adapter, type_data); 2821 2822 default: 2823 return -EOPNOTSUPP; 2824 } 2825 } 2826 2827 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2828 { 2829 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2830 struct igb_adapter *adapter = netdev_priv(dev); 2831 struct bpf_prog *prog = bpf->prog, *old_prog; 2832 bool running = netif_running(dev); 2833 bool need_reset; 2834 2835 /* verify igb ring attributes are sufficient for XDP */ 2836 for (i = 0; i < adapter->num_rx_queues; i++) { 2837 struct igb_ring *ring = adapter->rx_ring[i]; 2838 2839 if (frame_size > igb_rx_bufsz(ring)) { 2840 NL_SET_ERR_MSG_MOD(bpf->extack, 2841 "The RX buffer size is too small for the frame size"); 2842 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2843 igb_rx_bufsz(ring), frame_size); 2844 return -EINVAL; 2845 } 2846 } 2847 2848 old_prog = xchg(&adapter->xdp_prog, prog); 2849 need_reset = (!!prog != !!old_prog); 2850 2851 /* device is up and bpf is added/removed, must setup the RX queues */ 2852 if (need_reset && running) { 2853 igb_close(dev); 2854 } else { 2855 for (i = 0; i < adapter->num_rx_queues; i++) 2856 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2857 adapter->xdp_prog); 2858 } 2859 2860 if (old_prog) 2861 bpf_prog_put(old_prog); 2862 2863 /* bpf is just replaced, RXQ and MTU are already setup */ 2864 if (!need_reset) 2865 return 0; 2866 2867 if (running) 2868 igb_open(dev); 2869 2870 return 0; 2871 } 2872 2873 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2874 { 2875 switch (xdp->command) { 2876 case XDP_SETUP_PROG: 2877 return igb_xdp_setup(dev, xdp); 2878 default: 2879 return -EINVAL; 2880 } 2881 } 2882 2883 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2884 { 2885 /* Force memory writes to complete before letting h/w know there 2886 * are new descriptors to fetch. 2887 */ 2888 wmb(); 2889 writel(ring->next_to_use, ring->tail); 2890 } 2891 2892 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2893 { 2894 unsigned int r_idx = smp_processor_id(); 2895 2896 if (r_idx >= adapter->num_tx_queues) 2897 r_idx = r_idx % adapter->num_tx_queues; 2898 2899 return adapter->tx_ring[r_idx]; 2900 } 2901 2902 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2903 { 2904 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2905 int cpu = smp_processor_id(); 2906 struct igb_ring *tx_ring; 2907 struct netdev_queue *nq; 2908 u32 ret; 2909 2910 if (unlikely(!xdpf)) 2911 return IGB_XDP_CONSUMED; 2912 2913 /* During program transitions its possible adapter->xdp_prog is assigned 2914 * but ring has not been configured yet. In this case simply abort xmit. 2915 */ 2916 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2917 if (unlikely(!tx_ring)) 2918 return IGB_XDP_CONSUMED; 2919 2920 nq = txring_txq(tx_ring); 2921 __netif_tx_lock(nq, cpu); 2922 /* Avoid transmit queue timeout since we share it with the slow path */ 2923 nq->trans_start = jiffies; 2924 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2925 __netif_tx_unlock(nq); 2926 2927 return ret; 2928 } 2929 2930 static int igb_xdp_xmit(struct net_device *dev, int n, 2931 struct xdp_frame **frames, u32 flags) 2932 { 2933 struct igb_adapter *adapter = netdev_priv(dev); 2934 int cpu = smp_processor_id(); 2935 struct igb_ring *tx_ring; 2936 struct netdev_queue *nq; 2937 int drops = 0; 2938 int i; 2939 2940 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2941 return -ENETDOWN; 2942 2943 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2944 return -EINVAL; 2945 2946 /* During program transitions its possible adapter->xdp_prog is assigned 2947 * but ring has not been configured yet. In this case simply abort xmit. 2948 */ 2949 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2950 if (unlikely(!tx_ring)) 2951 return -ENXIO; 2952 2953 nq = txring_txq(tx_ring); 2954 __netif_tx_lock(nq, cpu); 2955 2956 /* Avoid transmit queue timeout since we share it with the slow path */ 2957 nq->trans_start = jiffies; 2958 2959 for (i = 0; i < n; i++) { 2960 struct xdp_frame *xdpf = frames[i]; 2961 int err; 2962 2963 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2964 if (err != IGB_XDP_TX) { 2965 xdp_return_frame_rx_napi(xdpf); 2966 drops++; 2967 } 2968 } 2969 2970 __netif_tx_unlock(nq); 2971 2972 if (unlikely(flags & XDP_XMIT_FLUSH)) 2973 igb_xdp_ring_update_tail(tx_ring); 2974 2975 return n - drops; 2976 } 2977 2978 static const struct net_device_ops igb_netdev_ops = { 2979 .ndo_open = igb_open, 2980 .ndo_stop = igb_close, 2981 .ndo_start_xmit = igb_xmit_frame, 2982 .ndo_get_stats64 = igb_get_stats64, 2983 .ndo_set_rx_mode = igb_set_rx_mode, 2984 .ndo_set_mac_address = igb_set_mac, 2985 .ndo_change_mtu = igb_change_mtu, 2986 .ndo_do_ioctl = igb_ioctl, 2987 .ndo_tx_timeout = igb_tx_timeout, 2988 .ndo_validate_addr = eth_validate_addr, 2989 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2990 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2991 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2992 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2993 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2994 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2995 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2996 .ndo_get_vf_config = igb_ndo_get_vf_config, 2997 .ndo_fix_features = igb_fix_features, 2998 .ndo_set_features = igb_set_features, 2999 .ndo_fdb_add = igb_ndo_fdb_add, 3000 .ndo_features_check = igb_features_check, 3001 .ndo_setup_tc = igb_setup_tc, 3002 .ndo_bpf = igb_xdp, 3003 .ndo_xdp_xmit = igb_xdp_xmit, 3004 }; 3005 3006 /** 3007 * igb_set_fw_version - Configure version string for ethtool 3008 * @adapter: adapter struct 3009 **/ 3010 void igb_set_fw_version(struct igb_adapter *adapter) 3011 { 3012 struct e1000_hw *hw = &adapter->hw; 3013 struct e1000_fw_version fw; 3014 3015 igb_get_fw_version(hw, &fw); 3016 3017 switch (hw->mac.type) { 3018 case e1000_i210: 3019 case e1000_i211: 3020 if (!(igb_get_flash_presence_i210(hw))) { 3021 snprintf(adapter->fw_version, 3022 sizeof(adapter->fw_version), 3023 "%2d.%2d-%d", 3024 fw.invm_major, fw.invm_minor, 3025 fw.invm_img_type); 3026 break; 3027 } 3028 fallthrough; 3029 default: 3030 /* if option is rom valid, display its version too */ 3031 if (fw.or_valid) { 3032 snprintf(adapter->fw_version, 3033 sizeof(adapter->fw_version), 3034 "%d.%d, 0x%08x, %d.%d.%d", 3035 fw.eep_major, fw.eep_minor, fw.etrack_id, 3036 fw.or_major, fw.or_build, fw.or_patch); 3037 /* no option rom */ 3038 } else if (fw.etrack_id != 0X0000) { 3039 snprintf(adapter->fw_version, 3040 sizeof(adapter->fw_version), 3041 "%d.%d, 0x%08x", 3042 fw.eep_major, fw.eep_minor, fw.etrack_id); 3043 } else { 3044 snprintf(adapter->fw_version, 3045 sizeof(adapter->fw_version), 3046 "%d.%d.%d", 3047 fw.eep_major, fw.eep_minor, fw.eep_build); 3048 } 3049 break; 3050 } 3051 } 3052 3053 /** 3054 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3055 * 3056 * @adapter: adapter struct 3057 **/ 3058 static void igb_init_mas(struct igb_adapter *adapter) 3059 { 3060 struct e1000_hw *hw = &adapter->hw; 3061 u16 eeprom_data; 3062 3063 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3064 switch (hw->bus.func) { 3065 case E1000_FUNC_0: 3066 if (eeprom_data & IGB_MAS_ENABLE_0) { 3067 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3068 netdev_info(adapter->netdev, 3069 "MAS: Enabling Media Autosense for port %d\n", 3070 hw->bus.func); 3071 } 3072 break; 3073 case E1000_FUNC_1: 3074 if (eeprom_data & IGB_MAS_ENABLE_1) { 3075 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3076 netdev_info(adapter->netdev, 3077 "MAS: Enabling Media Autosense for port %d\n", 3078 hw->bus.func); 3079 } 3080 break; 3081 case E1000_FUNC_2: 3082 if (eeprom_data & IGB_MAS_ENABLE_2) { 3083 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3084 netdev_info(adapter->netdev, 3085 "MAS: Enabling Media Autosense for port %d\n", 3086 hw->bus.func); 3087 } 3088 break; 3089 case E1000_FUNC_3: 3090 if (eeprom_data & IGB_MAS_ENABLE_3) { 3091 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3092 netdev_info(adapter->netdev, 3093 "MAS: Enabling Media Autosense for port %d\n", 3094 hw->bus.func); 3095 } 3096 break; 3097 default: 3098 /* Shouldn't get here */ 3099 netdev_err(adapter->netdev, 3100 "MAS: Invalid port configuration, returning\n"); 3101 break; 3102 } 3103 } 3104 3105 /** 3106 * igb_init_i2c - Init I2C interface 3107 * @adapter: pointer to adapter structure 3108 **/ 3109 static s32 igb_init_i2c(struct igb_adapter *adapter) 3110 { 3111 s32 status = 0; 3112 3113 /* I2C interface supported on i350 devices */ 3114 if (adapter->hw.mac.type != e1000_i350) 3115 return 0; 3116 3117 /* Initialize the i2c bus which is controlled by the registers. 3118 * This bus will use the i2c_algo_bit structue that implements 3119 * the protocol through toggling of the 4 bits in the register. 3120 */ 3121 adapter->i2c_adap.owner = THIS_MODULE; 3122 adapter->i2c_algo = igb_i2c_algo; 3123 adapter->i2c_algo.data = adapter; 3124 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3125 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3126 strlcpy(adapter->i2c_adap.name, "igb BB", 3127 sizeof(adapter->i2c_adap.name)); 3128 status = i2c_bit_add_bus(&adapter->i2c_adap); 3129 return status; 3130 } 3131 3132 /** 3133 * igb_probe - Device Initialization Routine 3134 * @pdev: PCI device information struct 3135 * @ent: entry in igb_pci_tbl 3136 * 3137 * Returns 0 on success, negative on failure 3138 * 3139 * igb_probe initializes an adapter identified by a pci_dev structure. 3140 * The OS initialization, configuring of the adapter private structure, 3141 * and a hardware reset occur. 3142 **/ 3143 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3144 { 3145 struct net_device *netdev; 3146 struct igb_adapter *adapter; 3147 struct e1000_hw *hw; 3148 u16 eeprom_data = 0; 3149 s32 ret_val; 3150 static int global_quad_port_a; /* global quad port a indication */ 3151 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3152 int err, pci_using_dac; 3153 u8 part_str[E1000_PBANUM_LENGTH]; 3154 3155 /* Catch broken hardware that put the wrong VF device ID in 3156 * the PCIe SR-IOV capability. 3157 */ 3158 if (pdev->is_virtfn) { 3159 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3160 pci_name(pdev), pdev->vendor, pdev->device); 3161 return -EINVAL; 3162 } 3163 3164 err = pci_enable_device_mem(pdev); 3165 if (err) 3166 return err; 3167 3168 pci_using_dac = 0; 3169 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3170 if (!err) { 3171 pci_using_dac = 1; 3172 } else { 3173 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3174 if (err) { 3175 dev_err(&pdev->dev, 3176 "No usable DMA configuration, aborting\n"); 3177 goto err_dma; 3178 } 3179 } 3180 3181 err = pci_request_mem_regions(pdev, igb_driver_name); 3182 if (err) 3183 goto err_pci_reg; 3184 3185 pci_enable_pcie_error_reporting(pdev); 3186 3187 pci_set_master(pdev); 3188 pci_save_state(pdev); 3189 3190 err = -ENOMEM; 3191 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3192 IGB_MAX_TX_QUEUES); 3193 if (!netdev) 3194 goto err_alloc_etherdev; 3195 3196 SET_NETDEV_DEV(netdev, &pdev->dev); 3197 3198 pci_set_drvdata(pdev, netdev); 3199 adapter = netdev_priv(netdev); 3200 adapter->netdev = netdev; 3201 adapter->pdev = pdev; 3202 hw = &adapter->hw; 3203 hw->back = adapter; 3204 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3205 3206 err = -EIO; 3207 adapter->io_addr = pci_iomap(pdev, 0, 0); 3208 if (!adapter->io_addr) 3209 goto err_ioremap; 3210 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3211 hw->hw_addr = adapter->io_addr; 3212 3213 netdev->netdev_ops = &igb_netdev_ops; 3214 igb_set_ethtool_ops(netdev); 3215 netdev->watchdog_timeo = 5 * HZ; 3216 3217 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3218 3219 netdev->mem_start = pci_resource_start(pdev, 0); 3220 netdev->mem_end = pci_resource_end(pdev, 0); 3221 3222 /* PCI config space info */ 3223 hw->vendor_id = pdev->vendor; 3224 hw->device_id = pdev->device; 3225 hw->revision_id = pdev->revision; 3226 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3227 hw->subsystem_device_id = pdev->subsystem_device; 3228 3229 /* Copy the default MAC, PHY and NVM function pointers */ 3230 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3231 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3232 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3233 /* Initialize skew-specific constants */ 3234 err = ei->get_invariants(hw); 3235 if (err) 3236 goto err_sw_init; 3237 3238 /* setup the private structure */ 3239 err = igb_sw_init(adapter); 3240 if (err) 3241 goto err_sw_init; 3242 3243 igb_get_bus_info_pcie(hw); 3244 3245 hw->phy.autoneg_wait_to_complete = false; 3246 3247 /* Copper options */ 3248 if (hw->phy.media_type == e1000_media_type_copper) { 3249 hw->phy.mdix = AUTO_ALL_MODES; 3250 hw->phy.disable_polarity_correction = false; 3251 hw->phy.ms_type = e1000_ms_hw_default; 3252 } 3253 3254 if (igb_check_reset_block(hw)) 3255 dev_info(&pdev->dev, 3256 "PHY reset is blocked due to SOL/IDER session.\n"); 3257 3258 /* features is initialized to 0 in allocation, it might have bits 3259 * set by igb_sw_init so we should use an or instead of an 3260 * assignment. 3261 */ 3262 netdev->features |= NETIF_F_SG | 3263 NETIF_F_TSO | 3264 NETIF_F_TSO6 | 3265 NETIF_F_RXHASH | 3266 NETIF_F_RXCSUM | 3267 NETIF_F_HW_CSUM; 3268 3269 if (hw->mac.type >= e1000_82576) 3270 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3271 3272 if (hw->mac.type >= e1000_i350) 3273 netdev->features |= NETIF_F_HW_TC; 3274 3275 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3276 NETIF_F_GSO_GRE_CSUM | \ 3277 NETIF_F_GSO_IPXIP4 | \ 3278 NETIF_F_GSO_IPXIP6 | \ 3279 NETIF_F_GSO_UDP_TUNNEL | \ 3280 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3281 3282 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3283 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3284 3285 /* copy netdev features into list of user selectable features */ 3286 netdev->hw_features |= netdev->features | 3287 NETIF_F_HW_VLAN_CTAG_RX | 3288 NETIF_F_HW_VLAN_CTAG_TX | 3289 NETIF_F_RXALL; 3290 3291 if (hw->mac.type >= e1000_i350) 3292 netdev->hw_features |= NETIF_F_NTUPLE; 3293 3294 if (pci_using_dac) 3295 netdev->features |= NETIF_F_HIGHDMA; 3296 3297 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3298 netdev->mpls_features |= NETIF_F_HW_CSUM; 3299 netdev->hw_enc_features |= netdev->vlan_features; 3300 3301 /* set this bit last since it cannot be part of vlan_features */ 3302 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3303 NETIF_F_HW_VLAN_CTAG_RX | 3304 NETIF_F_HW_VLAN_CTAG_TX; 3305 3306 netdev->priv_flags |= IFF_SUPP_NOFCS; 3307 3308 netdev->priv_flags |= IFF_UNICAST_FLT; 3309 3310 /* MTU range: 68 - 9216 */ 3311 netdev->min_mtu = ETH_MIN_MTU; 3312 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3313 3314 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3315 3316 /* before reading the NVM, reset the controller to put the device in a 3317 * known good starting state 3318 */ 3319 hw->mac.ops.reset_hw(hw); 3320 3321 /* make sure the NVM is good , i211/i210 parts can have special NVM 3322 * that doesn't contain a checksum 3323 */ 3324 switch (hw->mac.type) { 3325 case e1000_i210: 3326 case e1000_i211: 3327 if (igb_get_flash_presence_i210(hw)) { 3328 if (hw->nvm.ops.validate(hw) < 0) { 3329 dev_err(&pdev->dev, 3330 "The NVM Checksum Is Not Valid\n"); 3331 err = -EIO; 3332 goto err_eeprom; 3333 } 3334 } 3335 break; 3336 default: 3337 if (hw->nvm.ops.validate(hw) < 0) { 3338 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3339 err = -EIO; 3340 goto err_eeprom; 3341 } 3342 break; 3343 } 3344 3345 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3346 /* copy the MAC address out of the NVM */ 3347 if (hw->mac.ops.read_mac_addr(hw)) 3348 dev_err(&pdev->dev, "NVM Read Error\n"); 3349 } 3350 3351 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3352 3353 if (!is_valid_ether_addr(netdev->dev_addr)) { 3354 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3355 err = -EIO; 3356 goto err_eeprom; 3357 } 3358 3359 igb_set_default_mac_filter(adapter); 3360 3361 /* get firmware version for ethtool -i */ 3362 igb_set_fw_version(adapter); 3363 3364 /* configure RXPBSIZE and TXPBSIZE */ 3365 if (hw->mac.type == e1000_i210) { 3366 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3367 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3368 } 3369 3370 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3371 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3372 3373 INIT_WORK(&adapter->reset_task, igb_reset_task); 3374 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3375 3376 /* Initialize link properties that are user-changeable */ 3377 adapter->fc_autoneg = true; 3378 hw->mac.autoneg = true; 3379 hw->phy.autoneg_advertised = 0x2f; 3380 3381 hw->fc.requested_mode = e1000_fc_default; 3382 hw->fc.current_mode = e1000_fc_default; 3383 3384 igb_validate_mdi_setting(hw); 3385 3386 /* By default, support wake on port A */ 3387 if (hw->bus.func == 0) 3388 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3389 3390 /* Check the NVM for wake support on non-port A ports */ 3391 if (hw->mac.type >= e1000_82580) 3392 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3393 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3394 &eeprom_data); 3395 else if (hw->bus.func == 1) 3396 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3397 3398 if (eeprom_data & IGB_EEPROM_APME) 3399 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3400 3401 /* now that we have the eeprom settings, apply the special cases where 3402 * the eeprom may be wrong or the board simply won't support wake on 3403 * lan on a particular port 3404 */ 3405 switch (pdev->device) { 3406 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3407 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3408 break; 3409 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3410 case E1000_DEV_ID_82576_FIBER: 3411 case E1000_DEV_ID_82576_SERDES: 3412 /* Wake events only supported on port A for dual fiber 3413 * regardless of eeprom setting 3414 */ 3415 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3416 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3417 break; 3418 case E1000_DEV_ID_82576_QUAD_COPPER: 3419 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3420 /* if quad port adapter, disable WoL on all but port A */ 3421 if (global_quad_port_a != 0) 3422 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3423 else 3424 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3425 /* Reset for multiple quad port adapters */ 3426 if (++global_quad_port_a == 4) 3427 global_quad_port_a = 0; 3428 break; 3429 default: 3430 /* If the device can't wake, don't set software support */ 3431 if (!device_can_wakeup(&adapter->pdev->dev)) 3432 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3433 } 3434 3435 /* initialize the wol settings based on the eeprom settings */ 3436 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3437 adapter->wol |= E1000_WUFC_MAG; 3438 3439 /* Some vendors want WoL disabled by default, but still supported */ 3440 if ((hw->mac.type == e1000_i350) && 3441 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3443 adapter->wol = 0; 3444 } 3445 3446 /* Some vendors want the ability to Use the EEPROM setting as 3447 * enable/disable only, and not for capability 3448 */ 3449 if (((hw->mac.type == e1000_i350) || 3450 (hw->mac.type == e1000_i354)) && 3451 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3452 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3453 adapter->wol = 0; 3454 } 3455 if (hw->mac.type == e1000_i350) { 3456 if (((pdev->subsystem_device == 0x5001) || 3457 (pdev->subsystem_device == 0x5002)) && 3458 (hw->bus.func == 0)) { 3459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3460 adapter->wol = 0; 3461 } 3462 if (pdev->subsystem_device == 0x1F52) 3463 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3464 } 3465 3466 device_set_wakeup_enable(&adapter->pdev->dev, 3467 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3468 3469 /* reset the hardware with the new settings */ 3470 igb_reset(adapter); 3471 3472 /* Init the I2C interface */ 3473 err = igb_init_i2c(adapter); 3474 if (err) { 3475 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3476 goto err_eeprom; 3477 } 3478 3479 /* let the f/w know that the h/w is now under the control of the 3480 * driver. 3481 */ 3482 igb_get_hw_control(adapter); 3483 3484 strcpy(netdev->name, "eth%d"); 3485 err = register_netdev(netdev); 3486 if (err) 3487 goto err_register; 3488 3489 /* carrier off reporting is important to ethtool even BEFORE open */ 3490 netif_carrier_off(netdev); 3491 3492 #ifdef CONFIG_IGB_DCA 3493 if (dca_add_requester(&pdev->dev) == 0) { 3494 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3495 dev_info(&pdev->dev, "DCA enabled\n"); 3496 igb_setup_dca(adapter); 3497 } 3498 3499 #endif 3500 #ifdef CONFIG_IGB_HWMON 3501 /* Initialize the thermal sensor on i350 devices. */ 3502 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3503 u16 ets_word; 3504 3505 /* Read the NVM to determine if this i350 device supports an 3506 * external thermal sensor. 3507 */ 3508 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3509 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3510 adapter->ets = true; 3511 else 3512 adapter->ets = false; 3513 if (igb_sysfs_init(adapter)) 3514 dev_err(&pdev->dev, 3515 "failed to allocate sysfs resources\n"); 3516 } else { 3517 adapter->ets = false; 3518 } 3519 #endif 3520 /* Check if Media Autosense is enabled */ 3521 adapter->ei = *ei; 3522 if (hw->dev_spec._82575.mas_capable) 3523 igb_init_mas(adapter); 3524 3525 /* do hw tstamp init after resetting */ 3526 igb_ptp_init(adapter); 3527 3528 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3529 /* print bus type/speed/width info, not applicable to i354 */ 3530 if (hw->mac.type != e1000_i354) { 3531 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3532 netdev->name, 3533 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3534 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3535 "unknown"), 3536 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3537 "Width x4" : 3538 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3539 "Width x2" : 3540 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3541 "Width x1" : "unknown"), netdev->dev_addr); 3542 } 3543 3544 if ((hw->mac.type == e1000_82576 && 3545 rd32(E1000_EECD) & E1000_EECD_PRES) || 3546 (hw->mac.type >= e1000_i210 || 3547 igb_get_flash_presence_i210(hw))) { 3548 ret_val = igb_read_part_string(hw, part_str, 3549 E1000_PBANUM_LENGTH); 3550 } else { 3551 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3552 } 3553 3554 if (ret_val) 3555 strcpy(part_str, "Unknown"); 3556 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3557 dev_info(&pdev->dev, 3558 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3559 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3560 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3561 adapter->num_rx_queues, adapter->num_tx_queues); 3562 if (hw->phy.media_type == e1000_media_type_copper) { 3563 switch (hw->mac.type) { 3564 case e1000_i350: 3565 case e1000_i210: 3566 case e1000_i211: 3567 /* Enable EEE for internal copper PHY devices */ 3568 err = igb_set_eee_i350(hw, true, true); 3569 if ((!err) && 3570 (!hw->dev_spec._82575.eee_disable)) { 3571 adapter->eee_advert = 3572 MDIO_EEE_100TX | MDIO_EEE_1000T; 3573 adapter->flags |= IGB_FLAG_EEE; 3574 } 3575 break; 3576 case e1000_i354: 3577 if ((rd32(E1000_CTRL_EXT) & 3578 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3579 err = igb_set_eee_i354(hw, true, true); 3580 if ((!err) && 3581 (!hw->dev_spec._82575.eee_disable)) { 3582 adapter->eee_advert = 3583 MDIO_EEE_100TX | MDIO_EEE_1000T; 3584 adapter->flags |= IGB_FLAG_EEE; 3585 } 3586 } 3587 break; 3588 default: 3589 break; 3590 } 3591 } 3592 3593 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3594 3595 pm_runtime_put_noidle(&pdev->dev); 3596 return 0; 3597 3598 err_register: 3599 igb_release_hw_control(adapter); 3600 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3601 err_eeprom: 3602 if (!igb_check_reset_block(hw)) 3603 igb_reset_phy(hw); 3604 3605 if (hw->flash_address) 3606 iounmap(hw->flash_address); 3607 err_sw_init: 3608 kfree(adapter->mac_table); 3609 kfree(adapter->shadow_vfta); 3610 igb_clear_interrupt_scheme(adapter); 3611 #ifdef CONFIG_PCI_IOV 3612 igb_disable_sriov(pdev); 3613 #endif 3614 pci_iounmap(pdev, adapter->io_addr); 3615 err_ioremap: 3616 free_netdev(netdev); 3617 err_alloc_etherdev: 3618 pci_release_mem_regions(pdev); 3619 err_pci_reg: 3620 err_dma: 3621 pci_disable_device(pdev); 3622 return err; 3623 } 3624 3625 #ifdef CONFIG_PCI_IOV 3626 static int igb_disable_sriov(struct pci_dev *pdev) 3627 { 3628 struct net_device *netdev = pci_get_drvdata(pdev); 3629 struct igb_adapter *adapter = netdev_priv(netdev); 3630 struct e1000_hw *hw = &adapter->hw; 3631 3632 /* reclaim resources allocated to VFs */ 3633 if (adapter->vf_data) { 3634 /* disable iov and allow time for transactions to clear */ 3635 if (pci_vfs_assigned(pdev)) { 3636 dev_warn(&pdev->dev, 3637 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3638 return -EPERM; 3639 } else { 3640 pci_disable_sriov(pdev); 3641 msleep(500); 3642 } 3643 3644 kfree(adapter->vf_mac_list); 3645 adapter->vf_mac_list = NULL; 3646 kfree(adapter->vf_data); 3647 adapter->vf_data = NULL; 3648 adapter->vfs_allocated_count = 0; 3649 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3650 wrfl(); 3651 msleep(100); 3652 dev_info(&pdev->dev, "IOV Disabled\n"); 3653 3654 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3655 adapter->flags |= IGB_FLAG_DMAC; 3656 } 3657 3658 return 0; 3659 } 3660 3661 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3662 { 3663 struct net_device *netdev = pci_get_drvdata(pdev); 3664 struct igb_adapter *adapter = netdev_priv(netdev); 3665 int old_vfs = pci_num_vf(pdev); 3666 struct vf_mac_filter *mac_list; 3667 int err = 0; 3668 int num_vf_mac_filters, i; 3669 3670 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3671 err = -EPERM; 3672 goto out; 3673 } 3674 if (!num_vfs) 3675 goto out; 3676 3677 if (old_vfs) { 3678 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3679 old_vfs, max_vfs); 3680 adapter->vfs_allocated_count = old_vfs; 3681 } else 3682 adapter->vfs_allocated_count = num_vfs; 3683 3684 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3685 sizeof(struct vf_data_storage), GFP_KERNEL); 3686 3687 /* if allocation failed then we do not support SR-IOV */ 3688 if (!adapter->vf_data) { 3689 adapter->vfs_allocated_count = 0; 3690 err = -ENOMEM; 3691 goto out; 3692 } 3693 3694 /* Due to the limited number of RAR entries calculate potential 3695 * number of MAC filters available for the VFs. Reserve entries 3696 * for PF default MAC, PF MAC filters and at least one RAR entry 3697 * for each VF for VF MAC. 3698 */ 3699 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3700 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3701 adapter->vfs_allocated_count); 3702 3703 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3704 sizeof(struct vf_mac_filter), 3705 GFP_KERNEL); 3706 3707 mac_list = adapter->vf_mac_list; 3708 INIT_LIST_HEAD(&adapter->vf_macs.l); 3709 3710 if (adapter->vf_mac_list) { 3711 /* Initialize list of VF MAC filters */ 3712 for (i = 0; i < num_vf_mac_filters; i++) { 3713 mac_list->vf = -1; 3714 mac_list->free = true; 3715 list_add(&mac_list->l, &adapter->vf_macs.l); 3716 mac_list++; 3717 } 3718 } else { 3719 /* If we could not allocate memory for the VF MAC filters 3720 * we can continue without this feature but warn user. 3721 */ 3722 dev_err(&pdev->dev, 3723 "Unable to allocate memory for VF MAC filter list\n"); 3724 } 3725 3726 /* only call pci_enable_sriov() if no VFs are allocated already */ 3727 if (!old_vfs) { 3728 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3729 if (err) 3730 goto err_out; 3731 } 3732 dev_info(&pdev->dev, "%d VFs allocated\n", 3733 adapter->vfs_allocated_count); 3734 for (i = 0; i < adapter->vfs_allocated_count; i++) 3735 igb_vf_configure(adapter, i); 3736 3737 /* DMA Coalescing is not supported in IOV mode. */ 3738 adapter->flags &= ~IGB_FLAG_DMAC; 3739 goto out; 3740 3741 err_out: 3742 kfree(adapter->vf_mac_list); 3743 adapter->vf_mac_list = NULL; 3744 kfree(adapter->vf_data); 3745 adapter->vf_data = NULL; 3746 adapter->vfs_allocated_count = 0; 3747 out: 3748 return err; 3749 } 3750 3751 #endif 3752 /** 3753 * igb_remove_i2c - Cleanup I2C interface 3754 * @adapter: pointer to adapter structure 3755 **/ 3756 static void igb_remove_i2c(struct igb_adapter *adapter) 3757 { 3758 /* free the adapter bus structure */ 3759 i2c_del_adapter(&adapter->i2c_adap); 3760 } 3761 3762 /** 3763 * igb_remove - Device Removal Routine 3764 * @pdev: PCI device information struct 3765 * 3766 * igb_remove is called by the PCI subsystem to alert the driver 3767 * that it should release a PCI device. The could be caused by a 3768 * Hot-Plug event, or because the driver is going to be removed from 3769 * memory. 3770 **/ 3771 static void igb_remove(struct pci_dev *pdev) 3772 { 3773 struct net_device *netdev = pci_get_drvdata(pdev); 3774 struct igb_adapter *adapter = netdev_priv(netdev); 3775 struct e1000_hw *hw = &adapter->hw; 3776 3777 pm_runtime_get_noresume(&pdev->dev); 3778 #ifdef CONFIG_IGB_HWMON 3779 igb_sysfs_exit(adapter); 3780 #endif 3781 igb_remove_i2c(adapter); 3782 igb_ptp_stop(adapter); 3783 /* The watchdog timer may be rescheduled, so explicitly 3784 * disable watchdog from being rescheduled. 3785 */ 3786 set_bit(__IGB_DOWN, &adapter->state); 3787 del_timer_sync(&adapter->watchdog_timer); 3788 del_timer_sync(&adapter->phy_info_timer); 3789 3790 cancel_work_sync(&adapter->reset_task); 3791 cancel_work_sync(&adapter->watchdog_task); 3792 3793 #ifdef CONFIG_IGB_DCA 3794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3795 dev_info(&pdev->dev, "DCA disabled\n"); 3796 dca_remove_requester(&pdev->dev); 3797 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3798 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3799 } 3800 #endif 3801 3802 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3803 * would have already happened in close and is redundant. 3804 */ 3805 igb_release_hw_control(adapter); 3806 3807 #ifdef CONFIG_PCI_IOV 3808 igb_disable_sriov(pdev); 3809 #endif 3810 3811 unregister_netdev(netdev); 3812 3813 igb_clear_interrupt_scheme(adapter); 3814 3815 pci_iounmap(pdev, adapter->io_addr); 3816 if (hw->flash_address) 3817 iounmap(hw->flash_address); 3818 pci_release_mem_regions(pdev); 3819 3820 kfree(adapter->mac_table); 3821 kfree(adapter->shadow_vfta); 3822 free_netdev(netdev); 3823 3824 pci_disable_pcie_error_reporting(pdev); 3825 3826 pci_disable_device(pdev); 3827 } 3828 3829 /** 3830 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3831 * @adapter: board private structure to initialize 3832 * 3833 * This function initializes the vf specific data storage and then attempts to 3834 * allocate the VFs. The reason for ordering it this way is because it is much 3835 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3836 * the memory for the VFs. 3837 **/ 3838 static void igb_probe_vfs(struct igb_adapter *adapter) 3839 { 3840 #ifdef CONFIG_PCI_IOV 3841 struct pci_dev *pdev = adapter->pdev; 3842 struct e1000_hw *hw = &adapter->hw; 3843 3844 /* Virtualization features not supported on i210 family. */ 3845 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3846 return; 3847 3848 /* Of the below we really only want the effect of getting 3849 * IGB_FLAG_HAS_MSIX set (if available), without which 3850 * igb_enable_sriov() has no effect. 3851 */ 3852 igb_set_interrupt_capability(adapter, true); 3853 igb_reset_interrupt_capability(adapter); 3854 3855 pci_sriov_set_totalvfs(pdev, 7); 3856 igb_enable_sriov(pdev, max_vfs); 3857 3858 #endif /* CONFIG_PCI_IOV */ 3859 } 3860 3861 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3862 { 3863 struct e1000_hw *hw = &adapter->hw; 3864 unsigned int max_rss_queues; 3865 3866 /* Determine the maximum number of RSS queues supported. */ 3867 switch (hw->mac.type) { 3868 case e1000_i211: 3869 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3870 break; 3871 case e1000_82575: 3872 case e1000_i210: 3873 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3874 break; 3875 case e1000_i350: 3876 /* I350 cannot do RSS and SR-IOV at the same time */ 3877 if (!!adapter->vfs_allocated_count) { 3878 max_rss_queues = 1; 3879 break; 3880 } 3881 fallthrough; 3882 case e1000_82576: 3883 if (!!adapter->vfs_allocated_count) { 3884 max_rss_queues = 2; 3885 break; 3886 } 3887 fallthrough; 3888 case e1000_82580: 3889 case e1000_i354: 3890 default: 3891 max_rss_queues = IGB_MAX_RX_QUEUES; 3892 break; 3893 } 3894 3895 return max_rss_queues; 3896 } 3897 3898 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3899 { 3900 u32 max_rss_queues; 3901 3902 max_rss_queues = igb_get_max_rss_queues(adapter); 3903 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3904 3905 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3906 } 3907 3908 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3909 const u32 max_rss_queues) 3910 { 3911 struct e1000_hw *hw = &adapter->hw; 3912 3913 /* Determine if we need to pair queues. */ 3914 switch (hw->mac.type) { 3915 case e1000_82575: 3916 case e1000_i211: 3917 /* Device supports enough interrupts without queue pairing. */ 3918 break; 3919 case e1000_82576: 3920 case e1000_82580: 3921 case e1000_i350: 3922 case e1000_i354: 3923 case e1000_i210: 3924 default: 3925 /* If rss_queues > half of max_rss_queues, pair the queues in 3926 * order to conserve interrupts due to limited supply. 3927 */ 3928 if (adapter->rss_queues > (max_rss_queues / 2)) 3929 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3930 else 3931 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3932 break; 3933 } 3934 } 3935 3936 /** 3937 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3938 * @adapter: board private structure to initialize 3939 * 3940 * igb_sw_init initializes the Adapter private data structure. 3941 * Fields are initialized based on PCI device information and 3942 * OS network device settings (MTU size). 3943 **/ 3944 static int igb_sw_init(struct igb_adapter *adapter) 3945 { 3946 struct e1000_hw *hw = &adapter->hw; 3947 struct net_device *netdev = adapter->netdev; 3948 struct pci_dev *pdev = adapter->pdev; 3949 3950 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3951 3952 /* set default ring sizes */ 3953 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3954 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3955 3956 /* set default ITR values */ 3957 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3958 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3959 3960 /* set default work limits */ 3961 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3962 3963 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3964 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3965 3966 spin_lock_init(&adapter->nfc_lock); 3967 spin_lock_init(&adapter->stats64_lock); 3968 #ifdef CONFIG_PCI_IOV 3969 switch (hw->mac.type) { 3970 case e1000_82576: 3971 case e1000_i350: 3972 if (max_vfs > 7) { 3973 dev_warn(&pdev->dev, 3974 "Maximum of 7 VFs per PF, using max\n"); 3975 max_vfs = adapter->vfs_allocated_count = 7; 3976 } else 3977 adapter->vfs_allocated_count = max_vfs; 3978 if (adapter->vfs_allocated_count) 3979 dev_warn(&pdev->dev, 3980 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3981 break; 3982 default: 3983 break; 3984 } 3985 #endif /* CONFIG_PCI_IOV */ 3986 3987 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3988 adapter->flags |= IGB_FLAG_HAS_MSIX; 3989 3990 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3991 sizeof(struct igb_mac_addr), 3992 GFP_KERNEL); 3993 if (!adapter->mac_table) 3994 return -ENOMEM; 3995 3996 igb_probe_vfs(adapter); 3997 3998 igb_init_queue_configuration(adapter); 3999 4000 /* Setup and initialize a copy of the hw vlan table array */ 4001 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4002 GFP_KERNEL); 4003 if (!adapter->shadow_vfta) 4004 return -ENOMEM; 4005 4006 /* This call may decrease the number of queues */ 4007 if (igb_init_interrupt_scheme(adapter, true)) { 4008 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4009 return -ENOMEM; 4010 } 4011 4012 /* Explicitly disable IRQ since the NIC can be in any state. */ 4013 igb_irq_disable(adapter); 4014 4015 if (hw->mac.type >= e1000_i350) 4016 adapter->flags &= ~IGB_FLAG_DMAC; 4017 4018 set_bit(__IGB_DOWN, &adapter->state); 4019 return 0; 4020 } 4021 4022 /** 4023 * igb_open - Called when a network interface is made active 4024 * @netdev: network interface device structure 4025 * @resuming: indicates whether we are in a resume call 4026 * 4027 * Returns 0 on success, negative value on failure 4028 * 4029 * The open entry point is called when a network interface is made 4030 * active by the system (IFF_UP). At this point all resources needed 4031 * for transmit and receive operations are allocated, the interrupt 4032 * handler is registered with the OS, the watchdog timer is started, 4033 * and the stack is notified that the interface is ready. 4034 **/ 4035 static int __igb_open(struct net_device *netdev, bool resuming) 4036 { 4037 struct igb_adapter *adapter = netdev_priv(netdev); 4038 struct e1000_hw *hw = &adapter->hw; 4039 struct pci_dev *pdev = adapter->pdev; 4040 int err; 4041 int i; 4042 4043 /* disallow open during test */ 4044 if (test_bit(__IGB_TESTING, &adapter->state)) { 4045 WARN_ON(resuming); 4046 return -EBUSY; 4047 } 4048 4049 if (!resuming) 4050 pm_runtime_get_sync(&pdev->dev); 4051 4052 netif_carrier_off(netdev); 4053 4054 /* allocate transmit descriptors */ 4055 err = igb_setup_all_tx_resources(adapter); 4056 if (err) 4057 goto err_setup_tx; 4058 4059 /* allocate receive descriptors */ 4060 err = igb_setup_all_rx_resources(adapter); 4061 if (err) 4062 goto err_setup_rx; 4063 4064 igb_power_up_link(adapter); 4065 4066 /* before we allocate an interrupt, we must be ready to handle it. 4067 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4068 * as soon as we call pci_request_irq, so we have to setup our 4069 * clean_rx handler before we do so. 4070 */ 4071 igb_configure(adapter); 4072 4073 err = igb_request_irq(adapter); 4074 if (err) 4075 goto err_req_irq; 4076 4077 /* Notify the stack of the actual queue counts. */ 4078 err = netif_set_real_num_tx_queues(adapter->netdev, 4079 adapter->num_tx_queues); 4080 if (err) 4081 goto err_set_queues; 4082 4083 err = netif_set_real_num_rx_queues(adapter->netdev, 4084 adapter->num_rx_queues); 4085 if (err) 4086 goto err_set_queues; 4087 4088 /* From here on the code is the same as igb_up() */ 4089 clear_bit(__IGB_DOWN, &adapter->state); 4090 4091 for (i = 0; i < adapter->num_q_vectors; i++) 4092 napi_enable(&(adapter->q_vector[i]->napi)); 4093 4094 /* Clear any pending interrupts. */ 4095 rd32(E1000_TSICR); 4096 rd32(E1000_ICR); 4097 4098 igb_irq_enable(adapter); 4099 4100 /* notify VFs that reset has been completed */ 4101 if (adapter->vfs_allocated_count) { 4102 u32 reg_data = rd32(E1000_CTRL_EXT); 4103 4104 reg_data |= E1000_CTRL_EXT_PFRSTD; 4105 wr32(E1000_CTRL_EXT, reg_data); 4106 } 4107 4108 netif_tx_start_all_queues(netdev); 4109 4110 if (!resuming) 4111 pm_runtime_put(&pdev->dev); 4112 4113 /* start the watchdog. */ 4114 hw->mac.get_link_status = 1; 4115 schedule_work(&adapter->watchdog_task); 4116 4117 return 0; 4118 4119 err_set_queues: 4120 igb_free_irq(adapter); 4121 err_req_irq: 4122 igb_release_hw_control(adapter); 4123 igb_power_down_link(adapter); 4124 igb_free_all_rx_resources(adapter); 4125 err_setup_rx: 4126 igb_free_all_tx_resources(adapter); 4127 err_setup_tx: 4128 igb_reset(adapter); 4129 if (!resuming) 4130 pm_runtime_put(&pdev->dev); 4131 4132 return err; 4133 } 4134 4135 int igb_open(struct net_device *netdev) 4136 { 4137 return __igb_open(netdev, false); 4138 } 4139 4140 /** 4141 * igb_close - Disables a network interface 4142 * @netdev: network interface device structure 4143 * @suspending: indicates we are in a suspend call 4144 * 4145 * Returns 0, this is not allowed to fail 4146 * 4147 * The close entry point is called when an interface is de-activated 4148 * by the OS. The hardware is still under the driver's control, but 4149 * needs to be disabled. A global MAC reset is issued to stop the 4150 * hardware, and all transmit and receive resources are freed. 4151 **/ 4152 static int __igb_close(struct net_device *netdev, bool suspending) 4153 { 4154 struct igb_adapter *adapter = netdev_priv(netdev); 4155 struct pci_dev *pdev = adapter->pdev; 4156 4157 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4158 4159 if (!suspending) 4160 pm_runtime_get_sync(&pdev->dev); 4161 4162 igb_down(adapter); 4163 igb_free_irq(adapter); 4164 4165 igb_free_all_tx_resources(adapter); 4166 igb_free_all_rx_resources(adapter); 4167 4168 if (!suspending) 4169 pm_runtime_put_sync(&pdev->dev); 4170 return 0; 4171 } 4172 4173 int igb_close(struct net_device *netdev) 4174 { 4175 if (netif_device_present(netdev) || netdev->dismantle) 4176 return __igb_close(netdev, false); 4177 return 0; 4178 } 4179 4180 /** 4181 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4182 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4183 * 4184 * Return 0 on success, negative on failure 4185 **/ 4186 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4187 { 4188 struct device *dev = tx_ring->dev; 4189 int size; 4190 4191 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4192 4193 tx_ring->tx_buffer_info = vmalloc(size); 4194 if (!tx_ring->tx_buffer_info) 4195 goto err; 4196 4197 /* round up to nearest 4K */ 4198 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4199 tx_ring->size = ALIGN(tx_ring->size, 4096); 4200 4201 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4202 &tx_ring->dma, GFP_KERNEL); 4203 if (!tx_ring->desc) 4204 goto err; 4205 4206 tx_ring->next_to_use = 0; 4207 tx_ring->next_to_clean = 0; 4208 4209 return 0; 4210 4211 err: 4212 vfree(tx_ring->tx_buffer_info); 4213 tx_ring->tx_buffer_info = NULL; 4214 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4215 return -ENOMEM; 4216 } 4217 4218 /** 4219 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4220 * (Descriptors) for all queues 4221 * @adapter: board private structure 4222 * 4223 * Return 0 on success, negative on failure 4224 **/ 4225 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4226 { 4227 struct pci_dev *pdev = adapter->pdev; 4228 int i, err = 0; 4229 4230 for (i = 0; i < adapter->num_tx_queues; i++) { 4231 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4232 if (err) { 4233 dev_err(&pdev->dev, 4234 "Allocation for Tx Queue %u failed\n", i); 4235 for (i--; i >= 0; i--) 4236 igb_free_tx_resources(adapter->tx_ring[i]); 4237 break; 4238 } 4239 } 4240 4241 return err; 4242 } 4243 4244 /** 4245 * igb_setup_tctl - configure the transmit control registers 4246 * @adapter: Board private structure 4247 **/ 4248 void igb_setup_tctl(struct igb_adapter *adapter) 4249 { 4250 struct e1000_hw *hw = &adapter->hw; 4251 u32 tctl; 4252 4253 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4254 wr32(E1000_TXDCTL(0), 0); 4255 4256 /* Program the Transmit Control Register */ 4257 tctl = rd32(E1000_TCTL); 4258 tctl &= ~E1000_TCTL_CT; 4259 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4260 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4261 4262 igb_config_collision_dist(hw); 4263 4264 /* Enable transmits */ 4265 tctl |= E1000_TCTL_EN; 4266 4267 wr32(E1000_TCTL, tctl); 4268 } 4269 4270 /** 4271 * igb_configure_tx_ring - Configure transmit ring after Reset 4272 * @adapter: board private structure 4273 * @ring: tx ring to configure 4274 * 4275 * Configure a transmit ring after a reset. 4276 **/ 4277 void igb_configure_tx_ring(struct igb_adapter *adapter, 4278 struct igb_ring *ring) 4279 { 4280 struct e1000_hw *hw = &adapter->hw; 4281 u32 txdctl = 0; 4282 u64 tdba = ring->dma; 4283 int reg_idx = ring->reg_idx; 4284 4285 wr32(E1000_TDLEN(reg_idx), 4286 ring->count * sizeof(union e1000_adv_tx_desc)); 4287 wr32(E1000_TDBAL(reg_idx), 4288 tdba & 0x00000000ffffffffULL); 4289 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4290 4291 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4292 wr32(E1000_TDH(reg_idx), 0); 4293 writel(0, ring->tail); 4294 4295 txdctl |= IGB_TX_PTHRESH; 4296 txdctl |= IGB_TX_HTHRESH << 8; 4297 txdctl |= IGB_TX_WTHRESH << 16; 4298 4299 /* reinitialize tx_buffer_info */ 4300 memset(ring->tx_buffer_info, 0, 4301 sizeof(struct igb_tx_buffer) * ring->count); 4302 4303 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4304 wr32(E1000_TXDCTL(reg_idx), txdctl); 4305 } 4306 4307 /** 4308 * igb_configure_tx - Configure transmit Unit after Reset 4309 * @adapter: board private structure 4310 * 4311 * Configure the Tx unit of the MAC after a reset. 4312 **/ 4313 static void igb_configure_tx(struct igb_adapter *adapter) 4314 { 4315 struct e1000_hw *hw = &adapter->hw; 4316 int i; 4317 4318 /* disable the queues */ 4319 for (i = 0; i < adapter->num_tx_queues; i++) 4320 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4321 4322 wrfl(); 4323 usleep_range(10000, 20000); 4324 4325 for (i = 0; i < adapter->num_tx_queues; i++) 4326 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4327 } 4328 4329 /** 4330 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4331 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4332 * 4333 * Returns 0 on success, negative on failure 4334 **/ 4335 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4336 { 4337 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4338 struct device *dev = rx_ring->dev; 4339 int size; 4340 4341 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4342 4343 rx_ring->rx_buffer_info = vmalloc(size); 4344 if (!rx_ring->rx_buffer_info) 4345 goto err; 4346 4347 /* Round up to nearest 4K */ 4348 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4349 rx_ring->size = ALIGN(rx_ring->size, 4096); 4350 4351 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4352 &rx_ring->dma, GFP_KERNEL); 4353 if (!rx_ring->desc) 4354 goto err; 4355 4356 rx_ring->next_to_alloc = 0; 4357 rx_ring->next_to_clean = 0; 4358 rx_ring->next_to_use = 0; 4359 4360 rx_ring->xdp_prog = adapter->xdp_prog; 4361 4362 /* XDP RX-queue info */ 4363 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4364 rx_ring->queue_index, 0) < 0) 4365 goto err; 4366 4367 return 0; 4368 4369 err: 4370 vfree(rx_ring->rx_buffer_info); 4371 rx_ring->rx_buffer_info = NULL; 4372 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4373 return -ENOMEM; 4374 } 4375 4376 /** 4377 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4378 * (Descriptors) for all queues 4379 * @adapter: board private structure 4380 * 4381 * Return 0 on success, negative on failure 4382 **/ 4383 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4384 { 4385 struct pci_dev *pdev = adapter->pdev; 4386 int i, err = 0; 4387 4388 for (i = 0; i < adapter->num_rx_queues; i++) { 4389 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4390 if (err) { 4391 dev_err(&pdev->dev, 4392 "Allocation for Rx Queue %u failed\n", i); 4393 for (i--; i >= 0; i--) 4394 igb_free_rx_resources(adapter->rx_ring[i]); 4395 break; 4396 } 4397 } 4398 4399 return err; 4400 } 4401 4402 /** 4403 * igb_setup_mrqc - configure the multiple receive queue control registers 4404 * @adapter: Board private structure 4405 **/ 4406 static void igb_setup_mrqc(struct igb_adapter *adapter) 4407 { 4408 struct e1000_hw *hw = &adapter->hw; 4409 u32 mrqc, rxcsum; 4410 u32 j, num_rx_queues; 4411 u32 rss_key[10]; 4412 4413 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4414 for (j = 0; j < 10; j++) 4415 wr32(E1000_RSSRK(j), rss_key[j]); 4416 4417 num_rx_queues = adapter->rss_queues; 4418 4419 switch (hw->mac.type) { 4420 case e1000_82576: 4421 /* 82576 supports 2 RSS queues for SR-IOV */ 4422 if (adapter->vfs_allocated_count) 4423 num_rx_queues = 2; 4424 break; 4425 default: 4426 break; 4427 } 4428 4429 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4430 for (j = 0; j < IGB_RETA_SIZE; j++) 4431 adapter->rss_indir_tbl[j] = 4432 (j * num_rx_queues) / IGB_RETA_SIZE; 4433 adapter->rss_indir_tbl_init = num_rx_queues; 4434 } 4435 igb_write_rss_indir_tbl(adapter); 4436 4437 /* Disable raw packet checksumming so that RSS hash is placed in 4438 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4439 * offloads as they are enabled by default 4440 */ 4441 rxcsum = rd32(E1000_RXCSUM); 4442 rxcsum |= E1000_RXCSUM_PCSD; 4443 4444 if (adapter->hw.mac.type >= e1000_82576) 4445 /* Enable Receive Checksum Offload for SCTP */ 4446 rxcsum |= E1000_RXCSUM_CRCOFL; 4447 4448 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4449 wr32(E1000_RXCSUM, rxcsum); 4450 4451 /* Generate RSS hash based on packet types, TCP/UDP 4452 * port numbers and/or IPv4/v6 src and dst addresses 4453 */ 4454 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4455 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4456 E1000_MRQC_RSS_FIELD_IPV6 | 4457 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4458 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4459 4460 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4461 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4462 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4463 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4464 4465 /* If VMDq is enabled then we set the appropriate mode for that, else 4466 * we default to RSS so that an RSS hash is calculated per packet even 4467 * if we are only using one queue 4468 */ 4469 if (adapter->vfs_allocated_count) { 4470 if (hw->mac.type > e1000_82575) { 4471 /* Set the default pool for the PF's first queue */ 4472 u32 vtctl = rd32(E1000_VT_CTL); 4473 4474 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4475 E1000_VT_CTL_DISABLE_DEF_POOL); 4476 vtctl |= adapter->vfs_allocated_count << 4477 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4478 wr32(E1000_VT_CTL, vtctl); 4479 } 4480 if (adapter->rss_queues > 1) 4481 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4482 else 4483 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4484 } else { 4485 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4486 } 4487 igb_vmm_control(adapter); 4488 4489 wr32(E1000_MRQC, mrqc); 4490 } 4491 4492 /** 4493 * igb_setup_rctl - configure the receive control registers 4494 * @adapter: Board private structure 4495 **/ 4496 void igb_setup_rctl(struct igb_adapter *adapter) 4497 { 4498 struct e1000_hw *hw = &adapter->hw; 4499 u32 rctl; 4500 4501 rctl = rd32(E1000_RCTL); 4502 4503 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4504 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4505 4506 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4507 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4508 4509 /* enable stripping of CRC. It's unlikely this will break BMC 4510 * redirection as it did with e1000. Newer features require 4511 * that the HW strips the CRC. 4512 */ 4513 rctl |= E1000_RCTL_SECRC; 4514 4515 /* disable store bad packets and clear size bits. */ 4516 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4517 4518 /* enable LPE to allow for reception of jumbo frames */ 4519 rctl |= E1000_RCTL_LPE; 4520 4521 /* disable queue 0 to prevent tail write w/o re-config */ 4522 wr32(E1000_RXDCTL(0), 0); 4523 4524 /* Attention!!! For SR-IOV PF driver operations you must enable 4525 * queue drop for all VF and PF queues to prevent head of line blocking 4526 * if an un-trusted VF does not provide descriptors to hardware. 4527 */ 4528 if (adapter->vfs_allocated_count) { 4529 /* set all queue drop enable bits */ 4530 wr32(E1000_QDE, ALL_QUEUES); 4531 } 4532 4533 /* This is useful for sniffing bad packets. */ 4534 if (adapter->netdev->features & NETIF_F_RXALL) { 4535 /* UPE and MPE will be handled by normal PROMISC logic 4536 * in e1000e_set_rx_mode 4537 */ 4538 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4539 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4540 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4541 4542 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4543 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4544 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4545 * and that breaks VLANs. 4546 */ 4547 } 4548 4549 wr32(E1000_RCTL, rctl); 4550 } 4551 4552 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4553 int vfn) 4554 { 4555 struct e1000_hw *hw = &adapter->hw; 4556 u32 vmolr; 4557 4558 if (size > MAX_JUMBO_FRAME_SIZE) 4559 size = MAX_JUMBO_FRAME_SIZE; 4560 4561 vmolr = rd32(E1000_VMOLR(vfn)); 4562 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4563 vmolr |= size | E1000_VMOLR_LPE; 4564 wr32(E1000_VMOLR(vfn), vmolr); 4565 4566 return 0; 4567 } 4568 4569 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4570 int vfn, bool enable) 4571 { 4572 struct e1000_hw *hw = &adapter->hw; 4573 u32 val, reg; 4574 4575 if (hw->mac.type < e1000_82576) 4576 return; 4577 4578 if (hw->mac.type == e1000_i350) 4579 reg = E1000_DVMOLR(vfn); 4580 else 4581 reg = E1000_VMOLR(vfn); 4582 4583 val = rd32(reg); 4584 if (enable) 4585 val |= E1000_VMOLR_STRVLAN; 4586 else 4587 val &= ~(E1000_VMOLR_STRVLAN); 4588 wr32(reg, val); 4589 } 4590 4591 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4592 int vfn, bool aupe) 4593 { 4594 struct e1000_hw *hw = &adapter->hw; 4595 u32 vmolr; 4596 4597 /* This register exists only on 82576 and newer so if we are older then 4598 * we should exit and do nothing 4599 */ 4600 if (hw->mac.type < e1000_82576) 4601 return; 4602 4603 vmolr = rd32(E1000_VMOLR(vfn)); 4604 if (aupe) 4605 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4606 else 4607 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4608 4609 /* clear all bits that might not be set */ 4610 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4611 4612 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4613 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4614 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4615 * multicast packets 4616 */ 4617 if (vfn <= adapter->vfs_allocated_count) 4618 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4619 4620 wr32(E1000_VMOLR(vfn), vmolr); 4621 } 4622 4623 /** 4624 * igb_setup_srrctl - configure the split and replication receive control 4625 * registers 4626 * @adapter: Board private structure 4627 * @ring: receive ring to be configured 4628 **/ 4629 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4630 { 4631 struct e1000_hw *hw = &adapter->hw; 4632 int reg_idx = ring->reg_idx; 4633 u32 srrctl = 0; 4634 4635 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4636 if (ring_uses_large_buffer(ring)) 4637 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4638 else 4639 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4640 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4641 if (hw->mac.type >= e1000_82580) 4642 srrctl |= E1000_SRRCTL_TIMESTAMP; 4643 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4644 * queues and rx flow control is disabled 4645 */ 4646 if (adapter->vfs_allocated_count || 4647 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4648 adapter->num_rx_queues > 1)) 4649 srrctl |= E1000_SRRCTL_DROP_EN; 4650 4651 wr32(E1000_SRRCTL(reg_idx), srrctl); 4652 } 4653 4654 /** 4655 * igb_configure_rx_ring - Configure a receive ring after Reset 4656 * @adapter: board private structure 4657 * @ring: receive ring to be configured 4658 * 4659 * Configure the Rx unit of the MAC after a reset. 4660 **/ 4661 void igb_configure_rx_ring(struct igb_adapter *adapter, 4662 struct igb_ring *ring) 4663 { 4664 struct e1000_hw *hw = &adapter->hw; 4665 union e1000_adv_rx_desc *rx_desc; 4666 u64 rdba = ring->dma; 4667 int reg_idx = ring->reg_idx; 4668 u32 rxdctl = 0; 4669 4670 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4671 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4672 MEM_TYPE_PAGE_SHARED, NULL)); 4673 4674 /* disable the queue */ 4675 wr32(E1000_RXDCTL(reg_idx), 0); 4676 4677 /* Set DMA base address registers */ 4678 wr32(E1000_RDBAL(reg_idx), 4679 rdba & 0x00000000ffffffffULL); 4680 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4681 wr32(E1000_RDLEN(reg_idx), 4682 ring->count * sizeof(union e1000_adv_rx_desc)); 4683 4684 /* initialize head and tail */ 4685 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4686 wr32(E1000_RDH(reg_idx), 0); 4687 writel(0, ring->tail); 4688 4689 /* set descriptor configuration */ 4690 igb_setup_srrctl(adapter, ring); 4691 4692 /* set filtering for VMDQ pools */ 4693 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4694 4695 rxdctl |= IGB_RX_PTHRESH; 4696 rxdctl |= IGB_RX_HTHRESH << 8; 4697 rxdctl |= IGB_RX_WTHRESH << 16; 4698 4699 /* initialize rx_buffer_info */ 4700 memset(ring->rx_buffer_info, 0, 4701 sizeof(struct igb_rx_buffer) * ring->count); 4702 4703 /* initialize Rx descriptor 0 */ 4704 rx_desc = IGB_RX_DESC(ring, 0); 4705 rx_desc->wb.upper.length = 0; 4706 4707 /* enable receive descriptor fetching */ 4708 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4709 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4710 } 4711 4712 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4713 struct igb_ring *rx_ring) 4714 { 4715 /* set build_skb and buffer size flags */ 4716 clear_ring_build_skb_enabled(rx_ring); 4717 clear_ring_uses_large_buffer(rx_ring); 4718 4719 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4720 return; 4721 4722 set_ring_build_skb_enabled(rx_ring); 4723 4724 #if (PAGE_SIZE < 8192) 4725 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4726 return; 4727 4728 set_ring_uses_large_buffer(rx_ring); 4729 #endif 4730 } 4731 4732 /** 4733 * igb_configure_rx - Configure receive Unit after Reset 4734 * @adapter: board private structure 4735 * 4736 * Configure the Rx unit of the MAC after a reset. 4737 **/ 4738 static void igb_configure_rx(struct igb_adapter *adapter) 4739 { 4740 int i; 4741 4742 /* set the correct pool for the PF default MAC address in entry 0 */ 4743 igb_set_default_mac_filter(adapter); 4744 4745 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4746 * the Base and Length of the Rx Descriptor Ring 4747 */ 4748 for (i = 0; i < adapter->num_rx_queues; i++) { 4749 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4750 4751 igb_set_rx_buffer_len(adapter, rx_ring); 4752 igb_configure_rx_ring(adapter, rx_ring); 4753 } 4754 } 4755 4756 /** 4757 * igb_free_tx_resources - Free Tx Resources per Queue 4758 * @tx_ring: Tx descriptor ring for a specific queue 4759 * 4760 * Free all transmit software resources 4761 **/ 4762 void igb_free_tx_resources(struct igb_ring *tx_ring) 4763 { 4764 igb_clean_tx_ring(tx_ring); 4765 4766 vfree(tx_ring->tx_buffer_info); 4767 tx_ring->tx_buffer_info = NULL; 4768 4769 /* if not set, then don't free */ 4770 if (!tx_ring->desc) 4771 return; 4772 4773 dma_free_coherent(tx_ring->dev, tx_ring->size, 4774 tx_ring->desc, tx_ring->dma); 4775 4776 tx_ring->desc = NULL; 4777 } 4778 4779 /** 4780 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4781 * @adapter: board private structure 4782 * 4783 * Free all transmit software resources 4784 **/ 4785 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4786 { 4787 int i; 4788 4789 for (i = 0; i < adapter->num_tx_queues; i++) 4790 if (adapter->tx_ring[i]) 4791 igb_free_tx_resources(adapter->tx_ring[i]); 4792 } 4793 4794 /** 4795 * igb_clean_tx_ring - Free Tx Buffers 4796 * @tx_ring: ring to be cleaned 4797 **/ 4798 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4799 { 4800 u16 i = tx_ring->next_to_clean; 4801 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4802 4803 while (i != tx_ring->next_to_use) { 4804 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4805 4806 /* Free all the Tx ring sk_buffs */ 4807 dev_kfree_skb_any(tx_buffer->skb); 4808 4809 /* unmap skb header data */ 4810 dma_unmap_single(tx_ring->dev, 4811 dma_unmap_addr(tx_buffer, dma), 4812 dma_unmap_len(tx_buffer, len), 4813 DMA_TO_DEVICE); 4814 4815 /* check for eop_desc to determine the end of the packet */ 4816 eop_desc = tx_buffer->next_to_watch; 4817 tx_desc = IGB_TX_DESC(tx_ring, i); 4818 4819 /* unmap remaining buffers */ 4820 while (tx_desc != eop_desc) { 4821 tx_buffer++; 4822 tx_desc++; 4823 i++; 4824 if (unlikely(i == tx_ring->count)) { 4825 i = 0; 4826 tx_buffer = tx_ring->tx_buffer_info; 4827 tx_desc = IGB_TX_DESC(tx_ring, 0); 4828 } 4829 4830 /* unmap any remaining paged data */ 4831 if (dma_unmap_len(tx_buffer, len)) 4832 dma_unmap_page(tx_ring->dev, 4833 dma_unmap_addr(tx_buffer, dma), 4834 dma_unmap_len(tx_buffer, len), 4835 DMA_TO_DEVICE); 4836 } 4837 4838 /* move us one more past the eop_desc for start of next pkt */ 4839 tx_buffer++; 4840 i++; 4841 if (unlikely(i == tx_ring->count)) { 4842 i = 0; 4843 tx_buffer = tx_ring->tx_buffer_info; 4844 } 4845 } 4846 4847 /* reset BQL for queue */ 4848 netdev_tx_reset_queue(txring_txq(tx_ring)); 4849 4850 /* reset next_to_use and next_to_clean */ 4851 tx_ring->next_to_use = 0; 4852 tx_ring->next_to_clean = 0; 4853 } 4854 4855 /** 4856 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4857 * @adapter: board private structure 4858 **/ 4859 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4860 { 4861 int i; 4862 4863 for (i = 0; i < adapter->num_tx_queues; i++) 4864 if (adapter->tx_ring[i]) 4865 igb_clean_tx_ring(adapter->tx_ring[i]); 4866 } 4867 4868 /** 4869 * igb_free_rx_resources - Free Rx Resources 4870 * @rx_ring: ring to clean the resources from 4871 * 4872 * Free all receive software resources 4873 **/ 4874 void igb_free_rx_resources(struct igb_ring *rx_ring) 4875 { 4876 igb_clean_rx_ring(rx_ring); 4877 4878 rx_ring->xdp_prog = NULL; 4879 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4880 vfree(rx_ring->rx_buffer_info); 4881 rx_ring->rx_buffer_info = NULL; 4882 4883 /* if not set, then don't free */ 4884 if (!rx_ring->desc) 4885 return; 4886 4887 dma_free_coherent(rx_ring->dev, rx_ring->size, 4888 rx_ring->desc, rx_ring->dma); 4889 4890 rx_ring->desc = NULL; 4891 } 4892 4893 /** 4894 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4895 * @adapter: board private structure 4896 * 4897 * Free all receive software resources 4898 **/ 4899 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4900 { 4901 int i; 4902 4903 for (i = 0; i < adapter->num_rx_queues; i++) 4904 if (adapter->rx_ring[i]) 4905 igb_free_rx_resources(adapter->rx_ring[i]); 4906 } 4907 4908 /** 4909 * igb_clean_rx_ring - Free Rx Buffers per Queue 4910 * @rx_ring: ring to free buffers from 4911 **/ 4912 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4913 { 4914 u16 i = rx_ring->next_to_clean; 4915 4916 dev_kfree_skb(rx_ring->skb); 4917 rx_ring->skb = NULL; 4918 4919 /* Free all the Rx ring sk_buffs */ 4920 while (i != rx_ring->next_to_alloc) { 4921 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4922 4923 /* Invalidate cache lines that may have been written to by 4924 * device so that we avoid corrupting memory. 4925 */ 4926 dma_sync_single_range_for_cpu(rx_ring->dev, 4927 buffer_info->dma, 4928 buffer_info->page_offset, 4929 igb_rx_bufsz(rx_ring), 4930 DMA_FROM_DEVICE); 4931 4932 /* free resources associated with mapping */ 4933 dma_unmap_page_attrs(rx_ring->dev, 4934 buffer_info->dma, 4935 igb_rx_pg_size(rx_ring), 4936 DMA_FROM_DEVICE, 4937 IGB_RX_DMA_ATTR); 4938 __page_frag_cache_drain(buffer_info->page, 4939 buffer_info->pagecnt_bias); 4940 4941 i++; 4942 if (i == rx_ring->count) 4943 i = 0; 4944 } 4945 4946 rx_ring->next_to_alloc = 0; 4947 rx_ring->next_to_clean = 0; 4948 rx_ring->next_to_use = 0; 4949 } 4950 4951 /** 4952 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4953 * @adapter: board private structure 4954 **/ 4955 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4956 { 4957 int i; 4958 4959 for (i = 0; i < adapter->num_rx_queues; i++) 4960 if (adapter->rx_ring[i]) 4961 igb_clean_rx_ring(adapter->rx_ring[i]); 4962 } 4963 4964 /** 4965 * igb_set_mac - Change the Ethernet Address of the NIC 4966 * @netdev: network interface device structure 4967 * @p: pointer to an address structure 4968 * 4969 * Returns 0 on success, negative on failure 4970 **/ 4971 static int igb_set_mac(struct net_device *netdev, void *p) 4972 { 4973 struct igb_adapter *adapter = netdev_priv(netdev); 4974 struct e1000_hw *hw = &adapter->hw; 4975 struct sockaddr *addr = p; 4976 4977 if (!is_valid_ether_addr(addr->sa_data)) 4978 return -EADDRNOTAVAIL; 4979 4980 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4981 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4982 4983 /* set the correct pool for the new PF MAC address in entry 0 */ 4984 igb_set_default_mac_filter(adapter); 4985 4986 return 0; 4987 } 4988 4989 /** 4990 * igb_write_mc_addr_list - write multicast addresses to MTA 4991 * @netdev: network interface device structure 4992 * 4993 * Writes multicast address list to the MTA hash table. 4994 * Returns: -ENOMEM on failure 4995 * 0 on no addresses written 4996 * X on writing X addresses to MTA 4997 **/ 4998 static int igb_write_mc_addr_list(struct net_device *netdev) 4999 { 5000 struct igb_adapter *adapter = netdev_priv(netdev); 5001 struct e1000_hw *hw = &adapter->hw; 5002 struct netdev_hw_addr *ha; 5003 u8 *mta_list; 5004 int i; 5005 5006 if (netdev_mc_empty(netdev)) { 5007 /* nothing to program, so clear mc list */ 5008 igb_update_mc_addr_list(hw, NULL, 0); 5009 igb_restore_vf_multicasts(adapter); 5010 return 0; 5011 } 5012 5013 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5014 if (!mta_list) 5015 return -ENOMEM; 5016 5017 /* The shared function expects a packed array of only addresses. */ 5018 i = 0; 5019 netdev_for_each_mc_addr(ha, netdev) 5020 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5021 5022 igb_update_mc_addr_list(hw, mta_list, i); 5023 kfree(mta_list); 5024 5025 return netdev_mc_count(netdev); 5026 } 5027 5028 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5029 { 5030 struct e1000_hw *hw = &adapter->hw; 5031 u32 i, pf_id; 5032 5033 switch (hw->mac.type) { 5034 case e1000_i210: 5035 case e1000_i211: 5036 case e1000_i350: 5037 /* VLAN filtering needed for VLAN prio filter */ 5038 if (adapter->netdev->features & NETIF_F_NTUPLE) 5039 break; 5040 fallthrough; 5041 case e1000_82576: 5042 case e1000_82580: 5043 case e1000_i354: 5044 /* VLAN filtering needed for pool filtering */ 5045 if (adapter->vfs_allocated_count) 5046 break; 5047 fallthrough; 5048 default: 5049 return 1; 5050 } 5051 5052 /* We are already in VLAN promisc, nothing to do */ 5053 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5054 return 0; 5055 5056 if (!adapter->vfs_allocated_count) 5057 goto set_vfta; 5058 5059 /* Add PF to all active pools */ 5060 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5061 5062 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5063 u32 vlvf = rd32(E1000_VLVF(i)); 5064 5065 vlvf |= BIT(pf_id); 5066 wr32(E1000_VLVF(i), vlvf); 5067 } 5068 5069 set_vfta: 5070 /* Set all bits in the VLAN filter table array */ 5071 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5072 hw->mac.ops.write_vfta(hw, i, ~0U); 5073 5074 /* Set flag so we don't redo unnecessary work */ 5075 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5076 5077 return 0; 5078 } 5079 5080 #define VFTA_BLOCK_SIZE 8 5081 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5082 { 5083 struct e1000_hw *hw = &adapter->hw; 5084 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5085 u32 vid_start = vfta_offset * 32; 5086 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5087 u32 i, vid, word, bits, pf_id; 5088 5089 /* guarantee that we don't scrub out management VLAN */ 5090 vid = adapter->mng_vlan_id; 5091 if (vid >= vid_start && vid < vid_end) 5092 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5093 5094 if (!adapter->vfs_allocated_count) 5095 goto set_vfta; 5096 5097 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5098 5099 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5100 u32 vlvf = rd32(E1000_VLVF(i)); 5101 5102 /* pull VLAN ID from VLVF */ 5103 vid = vlvf & VLAN_VID_MASK; 5104 5105 /* only concern ourselves with a certain range */ 5106 if (vid < vid_start || vid >= vid_end) 5107 continue; 5108 5109 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5110 /* record VLAN ID in VFTA */ 5111 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5112 5113 /* if PF is part of this then continue */ 5114 if (test_bit(vid, adapter->active_vlans)) 5115 continue; 5116 } 5117 5118 /* remove PF from the pool */ 5119 bits = ~BIT(pf_id); 5120 bits &= rd32(E1000_VLVF(i)); 5121 wr32(E1000_VLVF(i), bits); 5122 } 5123 5124 set_vfta: 5125 /* extract values from active_vlans and write back to VFTA */ 5126 for (i = VFTA_BLOCK_SIZE; i--;) { 5127 vid = (vfta_offset + i) * 32; 5128 word = vid / BITS_PER_LONG; 5129 bits = vid % BITS_PER_LONG; 5130 5131 vfta[i] |= adapter->active_vlans[word] >> bits; 5132 5133 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5134 } 5135 } 5136 5137 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5138 { 5139 u32 i; 5140 5141 /* We are not in VLAN promisc, nothing to do */ 5142 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5143 return; 5144 5145 /* Set flag so we don't redo unnecessary work */ 5146 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5147 5148 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5149 igb_scrub_vfta(adapter, i); 5150 } 5151 5152 /** 5153 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5154 * @netdev: network interface device structure 5155 * 5156 * The set_rx_mode entry point is called whenever the unicast or multicast 5157 * address lists or the network interface flags are updated. This routine is 5158 * responsible for configuring the hardware for proper unicast, multicast, 5159 * promiscuous mode, and all-multi behavior. 5160 **/ 5161 static void igb_set_rx_mode(struct net_device *netdev) 5162 { 5163 struct igb_adapter *adapter = netdev_priv(netdev); 5164 struct e1000_hw *hw = &adapter->hw; 5165 unsigned int vfn = adapter->vfs_allocated_count; 5166 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5167 int count; 5168 5169 /* Check for Promiscuous and All Multicast modes */ 5170 if (netdev->flags & IFF_PROMISC) { 5171 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5172 vmolr |= E1000_VMOLR_MPME; 5173 5174 /* enable use of UTA filter to force packets to default pool */ 5175 if (hw->mac.type == e1000_82576) 5176 vmolr |= E1000_VMOLR_ROPE; 5177 } else { 5178 if (netdev->flags & IFF_ALLMULTI) { 5179 rctl |= E1000_RCTL_MPE; 5180 vmolr |= E1000_VMOLR_MPME; 5181 } else { 5182 /* Write addresses to the MTA, if the attempt fails 5183 * then we should just turn on promiscuous mode so 5184 * that we can at least receive multicast traffic 5185 */ 5186 count = igb_write_mc_addr_list(netdev); 5187 if (count < 0) { 5188 rctl |= E1000_RCTL_MPE; 5189 vmolr |= E1000_VMOLR_MPME; 5190 } else if (count) { 5191 vmolr |= E1000_VMOLR_ROMPE; 5192 } 5193 } 5194 } 5195 5196 /* Write addresses to available RAR registers, if there is not 5197 * sufficient space to store all the addresses then enable 5198 * unicast promiscuous mode 5199 */ 5200 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5201 rctl |= E1000_RCTL_UPE; 5202 vmolr |= E1000_VMOLR_ROPE; 5203 } 5204 5205 /* enable VLAN filtering by default */ 5206 rctl |= E1000_RCTL_VFE; 5207 5208 /* disable VLAN filtering for modes that require it */ 5209 if ((netdev->flags & IFF_PROMISC) || 5210 (netdev->features & NETIF_F_RXALL)) { 5211 /* if we fail to set all rules then just clear VFE */ 5212 if (igb_vlan_promisc_enable(adapter)) 5213 rctl &= ~E1000_RCTL_VFE; 5214 } else { 5215 igb_vlan_promisc_disable(adapter); 5216 } 5217 5218 /* update state of unicast, multicast, and VLAN filtering modes */ 5219 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5220 E1000_RCTL_VFE); 5221 wr32(E1000_RCTL, rctl); 5222 5223 #if (PAGE_SIZE < 8192) 5224 if (!adapter->vfs_allocated_count) { 5225 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5226 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5227 } 5228 #endif 5229 wr32(E1000_RLPML, rlpml); 5230 5231 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5232 * the VMOLR to enable the appropriate modes. Without this workaround 5233 * we will have issues with VLAN tag stripping not being done for frames 5234 * that are only arriving because we are the default pool 5235 */ 5236 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5237 return; 5238 5239 /* set UTA to appropriate mode */ 5240 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5241 5242 vmolr |= rd32(E1000_VMOLR(vfn)) & 5243 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5244 5245 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5246 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5247 #if (PAGE_SIZE < 8192) 5248 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5249 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5250 else 5251 #endif 5252 vmolr |= MAX_JUMBO_FRAME_SIZE; 5253 vmolr |= E1000_VMOLR_LPE; 5254 5255 wr32(E1000_VMOLR(vfn), vmolr); 5256 5257 igb_restore_vf_multicasts(adapter); 5258 } 5259 5260 static void igb_check_wvbr(struct igb_adapter *adapter) 5261 { 5262 struct e1000_hw *hw = &adapter->hw; 5263 u32 wvbr = 0; 5264 5265 switch (hw->mac.type) { 5266 case e1000_82576: 5267 case e1000_i350: 5268 wvbr = rd32(E1000_WVBR); 5269 if (!wvbr) 5270 return; 5271 break; 5272 default: 5273 break; 5274 } 5275 5276 adapter->wvbr |= wvbr; 5277 } 5278 5279 #define IGB_STAGGERED_QUEUE_OFFSET 8 5280 5281 static void igb_spoof_check(struct igb_adapter *adapter) 5282 { 5283 int j; 5284 5285 if (!adapter->wvbr) 5286 return; 5287 5288 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5289 if (adapter->wvbr & BIT(j) || 5290 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5291 dev_warn(&adapter->pdev->dev, 5292 "Spoof event(s) detected on VF %d\n", j); 5293 adapter->wvbr &= 5294 ~(BIT(j) | 5295 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5296 } 5297 } 5298 } 5299 5300 /* Need to wait a few seconds after link up to get diagnostic information from 5301 * the phy 5302 */ 5303 static void igb_update_phy_info(struct timer_list *t) 5304 { 5305 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5306 igb_get_phy_info(&adapter->hw); 5307 } 5308 5309 /** 5310 * igb_has_link - check shared code for link and determine up/down 5311 * @adapter: pointer to driver private info 5312 **/ 5313 bool igb_has_link(struct igb_adapter *adapter) 5314 { 5315 struct e1000_hw *hw = &adapter->hw; 5316 bool link_active = false; 5317 5318 /* get_link_status is set on LSC (link status) interrupt or 5319 * rx sequence error interrupt. get_link_status will stay 5320 * false until the e1000_check_for_link establishes link 5321 * for copper adapters ONLY 5322 */ 5323 switch (hw->phy.media_type) { 5324 case e1000_media_type_copper: 5325 if (!hw->mac.get_link_status) 5326 return true; 5327 fallthrough; 5328 case e1000_media_type_internal_serdes: 5329 hw->mac.ops.check_for_link(hw); 5330 link_active = !hw->mac.get_link_status; 5331 break; 5332 default: 5333 case e1000_media_type_unknown: 5334 break; 5335 } 5336 5337 if (((hw->mac.type == e1000_i210) || 5338 (hw->mac.type == e1000_i211)) && 5339 (hw->phy.id == I210_I_PHY_ID)) { 5340 if (!netif_carrier_ok(adapter->netdev)) { 5341 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5342 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5343 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5344 adapter->link_check_timeout = jiffies; 5345 } 5346 } 5347 5348 return link_active; 5349 } 5350 5351 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5352 { 5353 bool ret = false; 5354 u32 ctrl_ext, thstat; 5355 5356 /* check for thermal sensor event on i350 copper only */ 5357 if (hw->mac.type == e1000_i350) { 5358 thstat = rd32(E1000_THSTAT); 5359 ctrl_ext = rd32(E1000_CTRL_EXT); 5360 5361 if ((hw->phy.media_type == e1000_media_type_copper) && 5362 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5363 ret = !!(thstat & event); 5364 } 5365 5366 return ret; 5367 } 5368 5369 /** 5370 * igb_check_lvmmc - check for malformed packets received 5371 * and indicated in LVMMC register 5372 * @adapter: pointer to adapter 5373 **/ 5374 static void igb_check_lvmmc(struct igb_adapter *adapter) 5375 { 5376 struct e1000_hw *hw = &adapter->hw; 5377 u32 lvmmc; 5378 5379 lvmmc = rd32(E1000_LVMMC); 5380 if (lvmmc) { 5381 if (unlikely(net_ratelimit())) { 5382 netdev_warn(adapter->netdev, 5383 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5384 lvmmc); 5385 } 5386 } 5387 } 5388 5389 /** 5390 * igb_watchdog - Timer Call-back 5391 * @t: pointer to timer_list containing our private info pointer 5392 **/ 5393 static void igb_watchdog(struct timer_list *t) 5394 { 5395 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5396 /* Do the rest outside of interrupt context */ 5397 schedule_work(&adapter->watchdog_task); 5398 } 5399 5400 static void igb_watchdog_task(struct work_struct *work) 5401 { 5402 struct igb_adapter *adapter = container_of(work, 5403 struct igb_adapter, 5404 watchdog_task); 5405 struct e1000_hw *hw = &adapter->hw; 5406 struct e1000_phy_info *phy = &hw->phy; 5407 struct net_device *netdev = adapter->netdev; 5408 u32 link; 5409 int i; 5410 u32 connsw; 5411 u16 phy_data, retry_count = 20; 5412 5413 link = igb_has_link(adapter); 5414 5415 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5416 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5417 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5418 else 5419 link = false; 5420 } 5421 5422 /* Force link down if we have fiber to swap to */ 5423 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5424 if (hw->phy.media_type == e1000_media_type_copper) { 5425 connsw = rd32(E1000_CONNSW); 5426 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5427 link = 0; 5428 } 5429 } 5430 if (link) { 5431 /* Perform a reset if the media type changed. */ 5432 if (hw->dev_spec._82575.media_changed) { 5433 hw->dev_spec._82575.media_changed = false; 5434 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5435 igb_reset(adapter); 5436 } 5437 /* Cancel scheduled suspend requests. */ 5438 pm_runtime_resume(netdev->dev.parent); 5439 5440 if (!netif_carrier_ok(netdev)) { 5441 u32 ctrl; 5442 5443 hw->mac.ops.get_speed_and_duplex(hw, 5444 &adapter->link_speed, 5445 &adapter->link_duplex); 5446 5447 ctrl = rd32(E1000_CTRL); 5448 /* Links status message must follow this format */ 5449 netdev_info(netdev, 5450 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5451 netdev->name, 5452 adapter->link_speed, 5453 adapter->link_duplex == FULL_DUPLEX ? 5454 "Full" : "Half", 5455 (ctrl & E1000_CTRL_TFCE) && 5456 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5457 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5458 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5459 5460 /* disable EEE if enabled */ 5461 if ((adapter->flags & IGB_FLAG_EEE) && 5462 (adapter->link_duplex == HALF_DUPLEX)) { 5463 dev_info(&adapter->pdev->dev, 5464 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5465 adapter->hw.dev_spec._82575.eee_disable = true; 5466 adapter->flags &= ~IGB_FLAG_EEE; 5467 } 5468 5469 /* check if SmartSpeed worked */ 5470 igb_check_downshift(hw); 5471 if (phy->speed_downgraded) 5472 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5473 5474 /* check for thermal sensor event */ 5475 if (igb_thermal_sensor_event(hw, 5476 E1000_THSTAT_LINK_THROTTLE)) 5477 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5478 5479 /* adjust timeout factor according to speed/duplex */ 5480 adapter->tx_timeout_factor = 1; 5481 switch (adapter->link_speed) { 5482 case SPEED_10: 5483 adapter->tx_timeout_factor = 14; 5484 break; 5485 case SPEED_100: 5486 /* maybe add some timeout factor ? */ 5487 break; 5488 } 5489 5490 if (adapter->link_speed != SPEED_1000) 5491 goto no_wait; 5492 5493 /* wait for Remote receiver status OK */ 5494 retry_read_status: 5495 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5496 &phy_data)) { 5497 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5498 retry_count) { 5499 msleep(100); 5500 retry_count--; 5501 goto retry_read_status; 5502 } else if (!retry_count) { 5503 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5504 } 5505 } else { 5506 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5507 } 5508 no_wait: 5509 netif_carrier_on(netdev); 5510 5511 igb_ping_all_vfs(adapter); 5512 igb_check_vf_rate_limit(adapter); 5513 5514 /* link state has changed, schedule phy info update */ 5515 if (!test_bit(__IGB_DOWN, &adapter->state)) 5516 mod_timer(&adapter->phy_info_timer, 5517 round_jiffies(jiffies + 2 * HZ)); 5518 } 5519 } else { 5520 if (netif_carrier_ok(netdev)) { 5521 adapter->link_speed = 0; 5522 adapter->link_duplex = 0; 5523 5524 /* check for thermal sensor event */ 5525 if (igb_thermal_sensor_event(hw, 5526 E1000_THSTAT_PWR_DOWN)) { 5527 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5528 } 5529 5530 /* Links status message must follow this format */ 5531 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5532 netdev->name); 5533 netif_carrier_off(netdev); 5534 5535 igb_ping_all_vfs(adapter); 5536 5537 /* link state has changed, schedule phy info update */ 5538 if (!test_bit(__IGB_DOWN, &adapter->state)) 5539 mod_timer(&adapter->phy_info_timer, 5540 round_jiffies(jiffies + 2 * HZ)); 5541 5542 /* link is down, time to check for alternate media */ 5543 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5544 igb_check_swap_media(adapter); 5545 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5546 schedule_work(&adapter->reset_task); 5547 /* return immediately */ 5548 return; 5549 } 5550 } 5551 pm_schedule_suspend(netdev->dev.parent, 5552 MSEC_PER_SEC * 5); 5553 5554 /* also check for alternate media here */ 5555 } else if (!netif_carrier_ok(netdev) && 5556 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5557 igb_check_swap_media(adapter); 5558 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5559 schedule_work(&adapter->reset_task); 5560 /* return immediately */ 5561 return; 5562 } 5563 } 5564 } 5565 5566 spin_lock(&adapter->stats64_lock); 5567 igb_update_stats(adapter); 5568 spin_unlock(&adapter->stats64_lock); 5569 5570 for (i = 0; i < adapter->num_tx_queues; i++) { 5571 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5572 if (!netif_carrier_ok(netdev)) { 5573 /* We've lost link, so the controller stops DMA, 5574 * but we've got queued Tx work that's never going 5575 * to get done, so reset controller to flush Tx. 5576 * (Do the reset outside of interrupt context). 5577 */ 5578 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5579 adapter->tx_timeout_count++; 5580 schedule_work(&adapter->reset_task); 5581 /* return immediately since reset is imminent */ 5582 return; 5583 } 5584 } 5585 5586 /* Force detection of hung controller every watchdog period */ 5587 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5588 } 5589 5590 /* Cause software interrupt to ensure Rx ring is cleaned */ 5591 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5592 u32 eics = 0; 5593 5594 for (i = 0; i < adapter->num_q_vectors; i++) 5595 eics |= adapter->q_vector[i]->eims_value; 5596 wr32(E1000_EICS, eics); 5597 } else { 5598 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5599 } 5600 5601 igb_spoof_check(adapter); 5602 igb_ptp_rx_hang(adapter); 5603 igb_ptp_tx_hang(adapter); 5604 5605 /* Check LVMMC register on i350/i354 only */ 5606 if ((adapter->hw.mac.type == e1000_i350) || 5607 (adapter->hw.mac.type == e1000_i354)) 5608 igb_check_lvmmc(adapter); 5609 5610 /* Reset the timer */ 5611 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5612 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5613 mod_timer(&adapter->watchdog_timer, 5614 round_jiffies(jiffies + HZ)); 5615 else 5616 mod_timer(&adapter->watchdog_timer, 5617 round_jiffies(jiffies + 2 * HZ)); 5618 } 5619 } 5620 5621 enum latency_range { 5622 lowest_latency = 0, 5623 low_latency = 1, 5624 bulk_latency = 2, 5625 latency_invalid = 255 5626 }; 5627 5628 /** 5629 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5630 * @q_vector: pointer to q_vector 5631 * 5632 * Stores a new ITR value based on strictly on packet size. This 5633 * algorithm is less sophisticated than that used in igb_update_itr, 5634 * due to the difficulty of synchronizing statistics across multiple 5635 * receive rings. The divisors and thresholds used by this function 5636 * were determined based on theoretical maximum wire speed and testing 5637 * data, in order to minimize response time while increasing bulk 5638 * throughput. 5639 * This functionality is controlled by ethtool's coalescing settings. 5640 * NOTE: This function is called only when operating in a multiqueue 5641 * receive environment. 5642 **/ 5643 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5644 { 5645 int new_val = q_vector->itr_val; 5646 int avg_wire_size = 0; 5647 struct igb_adapter *adapter = q_vector->adapter; 5648 unsigned int packets; 5649 5650 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5651 * ints/sec - ITR timer value of 120 ticks. 5652 */ 5653 if (adapter->link_speed != SPEED_1000) { 5654 new_val = IGB_4K_ITR; 5655 goto set_itr_val; 5656 } 5657 5658 packets = q_vector->rx.total_packets; 5659 if (packets) 5660 avg_wire_size = q_vector->rx.total_bytes / packets; 5661 5662 packets = q_vector->tx.total_packets; 5663 if (packets) 5664 avg_wire_size = max_t(u32, avg_wire_size, 5665 q_vector->tx.total_bytes / packets); 5666 5667 /* if avg_wire_size isn't set no work was done */ 5668 if (!avg_wire_size) 5669 goto clear_counts; 5670 5671 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5672 avg_wire_size += 24; 5673 5674 /* Don't starve jumbo frames */ 5675 avg_wire_size = min(avg_wire_size, 3000); 5676 5677 /* Give a little boost to mid-size frames */ 5678 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5679 new_val = avg_wire_size / 3; 5680 else 5681 new_val = avg_wire_size / 2; 5682 5683 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5684 if (new_val < IGB_20K_ITR && 5685 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5686 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5687 new_val = IGB_20K_ITR; 5688 5689 set_itr_val: 5690 if (new_val != q_vector->itr_val) { 5691 q_vector->itr_val = new_val; 5692 q_vector->set_itr = 1; 5693 } 5694 clear_counts: 5695 q_vector->rx.total_bytes = 0; 5696 q_vector->rx.total_packets = 0; 5697 q_vector->tx.total_bytes = 0; 5698 q_vector->tx.total_packets = 0; 5699 } 5700 5701 /** 5702 * igb_update_itr - update the dynamic ITR value based on statistics 5703 * @q_vector: pointer to q_vector 5704 * @ring_container: ring info to update the itr for 5705 * 5706 * Stores a new ITR value based on packets and byte 5707 * counts during the last interrupt. The advantage of per interrupt 5708 * computation is faster updates and more accurate ITR for the current 5709 * traffic pattern. Constants in this function were computed 5710 * based on theoretical maximum wire speed and thresholds were set based 5711 * on testing data as well as attempting to minimize response time 5712 * while increasing bulk throughput. 5713 * This functionality is controlled by ethtool's coalescing settings. 5714 * NOTE: These calculations are only valid when operating in a single- 5715 * queue environment. 5716 **/ 5717 static void igb_update_itr(struct igb_q_vector *q_vector, 5718 struct igb_ring_container *ring_container) 5719 { 5720 unsigned int packets = ring_container->total_packets; 5721 unsigned int bytes = ring_container->total_bytes; 5722 u8 itrval = ring_container->itr; 5723 5724 /* no packets, exit with status unchanged */ 5725 if (packets == 0) 5726 return; 5727 5728 switch (itrval) { 5729 case lowest_latency: 5730 /* handle TSO and jumbo frames */ 5731 if (bytes/packets > 8000) 5732 itrval = bulk_latency; 5733 else if ((packets < 5) && (bytes > 512)) 5734 itrval = low_latency; 5735 break; 5736 case low_latency: /* 50 usec aka 20000 ints/s */ 5737 if (bytes > 10000) { 5738 /* this if handles the TSO accounting */ 5739 if (bytes/packets > 8000) 5740 itrval = bulk_latency; 5741 else if ((packets < 10) || ((bytes/packets) > 1200)) 5742 itrval = bulk_latency; 5743 else if ((packets > 35)) 5744 itrval = lowest_latency; 5745 } else if (bytes/packets > 2000) { 5746 itrval = bulk_latency; 5747 } else if (packets <= 2 && bytes < 512) { 5748 itrval = lowest_latency; 5749 } 5750 break; 5751 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5752 if (bytes > 25000) { 5753 if (packets > 35) 5754 itrval = low_latency; 5755 } else if (bytes < 1500) { 5756 itrval = low_latency; 5757 } 5758 break; 5759 } 5760 5761 /* clear work counters since we have the values we need */ 5762 ring_container->total_bytes = 0; 5763 ring_container->total_packets = 0; 5764 5765 /* write updated itr to ring container */ 5766 ring_container->itr = itrval; 5767 } 5768 5769 static void igb_set_itr(struct igb_q_vector *q_vector) 5770 { 5771 struct igb_adapter *adapter = q_vector->adapter; 5772 u32 new_itr = q_vector->itr_val; 5773 u8 current_itr = 0; 5774 5775 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5776 if (adapter->link_speed != SPEED_1000) { 5777 current_itr = 0; 5778 new_itr = IGB_4K_ITR; 5779 goto set_itr_now; 5780 } 5781 5782 igb_update_itr(q_vector, &q_vector->tx); 5783 igb_update_itr(q_vector, &q_vector->rx); 5784 5785 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5786 5787 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5788 if (current_itr == lowest_latency && 5789 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5790 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5791 current_itr = low_latency; 5792 5793 switch (current_itr) { 5794 /* counts and packets in update_itr are dependent on these numbers */ 5795 case lowest_latency: 5796 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5797 break; 5798 case low_latency: 5799 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5800 break; 5801 case bulk_latency: 5802 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5803 break; 5804 default: 5805 break; 5806 } 5807 5808 set_itr_now: 5809 if (new_itr != q_vector->itr_val) { 5810 /* this attempts to bias the interrupt rate towards Bulk 5811 * by adding intermediate steps when interrupt rate is 5812 * increasing 5813 */ 5814 new_itr = new_itr > q_vector->itr_val ? 5815 max((new_itr * q_vector->itr_val) / 5816 (new_itr + (q_vector->itr_val >> 2)), 5817 new_itr) : new_itr; 5818 /* Don't write the value here; it resets the adapter's 5819 * internal timer, and causes us to delay far longer than 5820 * we should between interrupts. Instead, we write the ITR 5821 * value at the beginning of the next interrupt so the timing 5822 * ends up being correct. 5823 */ 5824 q_vector->itr_val = new_itr; 5825 q_vector->set_itr = 1; 5826 } 5827 } 5828 5829 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5830 struct igb_tx_buffer *first, 5831 u32 vlan_macip_lens, u32 type_tucmd, 5832 u32 mss_l4len_idx) 5833 { 5834 struct e1000_adv_tx_context_desc *context_desc; 5835 u16 i = tx_ring->next_to_use; 5836 struct timespec64 ts; 5837 5838 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5839 5840 i++; 5841 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5842 5843 /* set bits to identify this as an advanced context descriptor */ 5844 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5845 5846 /* For 82575, context index must be unique per ring. */ 5847 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5848 mss_l4len_idx |= tx_ring->reg_idx << 4; 5849 5850 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5851 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5852 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5853 5854 /* We assume there is always a valid tx time available. Invalid times 5855 * should have been handled by the upper layers. 5856 */ 5857 if (tx_ring->launchtime_enable) { 5858 ts = ktime_to_timespec64(first->skb->tstamp); 5859 first->skb->tstamp = ktime_set(0, 0); 5860 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5861 } else { 5862 context_desc->seqnum_seed = 0; 5863 } 5864 } 5865 5866 static int igb_tso(struct igb_ring *tx_ring, 5867 struct igb_tx_buffer *first, 5868 u8 *hdr_len) 5869 { 5870 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5871 struct sk_buff *skb = first->skb; 5872 union { 5873 struct iphdr *v4; 5874 struct ipv6hdr *v6; 5875 unsigned char *hdr; 5876 } ip; 5877 union { 5878 struct tcphdr *tcp; 5879 struct udphdr *udp; 5880 unsigned char *hdr; 5881 } l4; 5882 u32 paylen, l4_offset; 5883 int err; 5884 5885 if (skb->ip_summed != CHECKSUM_PARTIAL) 5886 return 0; 5887 5888 if (!skb_is_gso(skb)) 5889 return 0; 5890 5891 err = skb_cow_head(skb, 0); 5892 if (err < 0) 5893 return err; 5894 5895 ip.hdr = skb_network_header(skb); 5896 l4.hdr = skb_checksum_start(skb); 5897 5898 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5899 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5900 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5901 5902 /* initialize outer IP header fields */ 5903 if (ip.v4->version == 4) { 5904 unsigned char *csum_start = skb_checksum_start(skb); 5905 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5906 5907 /* IP header will have to cancel out any data that 5908 * is not a part of the outer IP header 5909 */ 5910 ip.v4->check = csum_fold(csum_partial(trans_start, 5911 csum_start - trans_start, 5912 0)); 5913 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5914 5915 ip.v4->tot_len = 0; 5916 first->tx_flags |= IGB_TX_FLAGS_TSO | 5917 IGB_TX_FLAGS_CSUM | 5918 IGB_TX_FLAGS_IPV4; 5919 } else { 5920 ip.v6->payload_len = 0; 5921 first->tx_flags |= IGB_TX_FLAGS_TSO | 5922 IGB_TX_FLAGS_CSUM; 5923 } 5924 5925 /* determine offset of inner transport header */ 5926 l4_offset = l4.hdr - skb->data; 5927 5928 /* remove payload length from inner checksum */ 5929 paylen = skb->len - l4_offset; 5930 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5931 /* compute length of segmentation header */ 5932 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5933 csum_replace_by_diff(&l4.tcp->check, 5934 (__force __wsum)htonl(paylen)); 5935 } else { 5936 /* compute length of segmentation header */ 5937 *hdr_len = sizeof(*l4.udp) + l4_offset; 5938 csum_replace_by_diff(&l4.udp->check, 5939 (__force __wsum)htonl(paylen)); 5940 } 5941 5942 /* update gso size and bytecount with header size */ 5943 first->gso_segs = skb_shinfo(skb)->gso_segs; 5944 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5945 5946 /* MSS L4LEN IDX */ 5947 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5948 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5949 5950 /* VLAN MACLEN IPLEN */ 5951 vlan_macip_lens = l4.hdr - ip.hdr; 5952 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5953 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5954 5955 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5956 type_tucmd, mss_l4len_idx); 5957 5958 return 1; 5959 } 5960 5961 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5962 { 5963 struct sk_buff *skb = first->skb; 5964 u32 vlan_macip_lens = 0; 5965 u32 type_tucmd = 0; 5966 5967 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5968 csum_failed: 5969 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5970 !tx_ring->launchtime_enable) 5971 return; 5972 goto no_csum; 5973 } 5974 5975 switch (skb->csum_offset) { 5976 case offsetof(struct tcphdr, check): 5977 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5978 fallthrough; 5979 case offsetof(struct udphdr, check): 5980 break; 5981 case offsetof(struct sctphdr, checksum): 5982 /* validate that this is actually an SCTP request */ 5983 if (skb_csum_is_sctp(skb)) { 5984 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5985 break; 5986 } 5987 fallthrough; 5988 default: 5989 skb_checksum_help(skb); 5990 goto csum_failed; 5991 } 5992 5993 /* update TX checksum flag */ 5994 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5995 vlan_macip_lens = skb_checksum_start_offset(skb) - 5996 skb_network_offset(skb); 5997 no_csum: 5998 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5999 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6000 6001 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6002 } 6003 6004 #define IGB_SET_FLAG(_input, _flag, _result) \ 6005 ((_flag <= _result) ? \ 6006 ((u32)(_input & _flag) * (_result / _flag)) : \ 6007 ((u32)(_input & _flag) / (_flag / _result))) 6008 6009 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6010 { 6011 /* set type for advanced descriptor with frame checksum insertion */ 6012 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6013 E1000_ADVTXD_DCMD_DEXT | 6014 E1000_ADVTXD_DCMD_IFCS; 6015 6016 /* set HW vlan bit if vlan is present */ 6017 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6018 (E1000_ADVTXD_DCMD_VLE)); 6019 6020 /* set segmentation bits for TSO */ 6021 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6022 (E1000_ADVTXD_DCMD_TSE)); 6023 6024 /* set timestamp bit if present */ 6025 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6026 (E1000_ADVTXD_MAC_TSTAMP)); 6027 6028 /* insert frame checksum */ 6029 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6030 6031 return cmd_type; 6032 } 6033 6034 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6035 union e1000_adv_tx_desc *tx_desc, 6036 u32 tx_flags, unsigned int paylen) 6037 { 6038 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6039 6040 /* 82575 requires a unique index per ring */ 6041 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6042 olinfo_status |= tx_ring->reg_idx << 4; 6043 6044 /* insert L4 checksum */ 6045 olinfo_status |= IGB_SET_FLAG(tx_flags, 6046 IGB_TX_FLAGS_CSUM, 6047 (E1000_TXD_POPTS_TXSM << 8)); 6048 6049 /* insert IPv4 checksum */ 6050 olinfo_status |= IGB_SET_FLAG(tx_flags, 6051 IGB_TX_FLAGS_IPV4, 6052 (E1000_TXD_POPTS_IXSM << 8)); 6053 6054 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6055 } 6056 6057 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6058 { 6059 struct net_device *netdev = tx_ring->netdev; 6060 6061 netif_stop_subqueue(netdev, tx_ring->queue_index); 6062 6063 /* Herbert's original patch had: 6064 * smp_mb__after_netif_stop_queue(); 6065 * but since that doesn't exist yet, just open code it. 6066 */ 6067 smp_mb(); 6068 6069 /* We need to check again in a case another CPU has just 6070 * made room available. 6071 */ 6072 if (igb_desc_unused(tx_ring) < size) 6073 return -EBUSY; 6074 6075 /* A reprieve! */ 6076 netif_wake_subqueue(netdev, tx_ring->queue_index); 6077 6078 u64_stats_update_begin(&tx_ring->tx_syncp2); 6079 tx_ring->tx_stats.restart_queue2++; 6080 u64_stats_update_end(&tx_ring->tx_syncp2); 6081 6082 return 0; 6083 } 6084 6085 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6086 { 6087 if (igb_desc_unused(tx_ring) >= size) 6088 return 0; 6089 return __igb_maybe_stop_tx(tx_ring, size); 6090 } 6091 6092 static int igb_tx_map(struct igb_ring *tx_ring, 6093 struct igb_tx_buffer *first, 6094 const u8 hdr_len) 6095 { 6096 struct sk_buff *skb = first->skb; 6097 struct igb_tx_buffer *tx_buffer; 6098 union e1000_adv_tx_desc *tx_desc; 6099 skb_frag_t *frag; 6100 dma_addr_t dma; 6101 unsigned int data_len, size; 6102 u32 tx_flags = first->tx_flags; 6103 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6104 u16 i = tx_ring->next_to_use; 6105 6106 tx_desc = IGB_TX_DESC(tx_ring, i); 6107 6108 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6109 6110 size = skb_headlen(skb); 6111 data_len = skb->data_len; 6112 6113 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6114 6115 tx_buffer = first; 6116 6117 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6118 if (dma_mapping_error(tx_ring->dev, dma)) 6119 goto dma_error; 6120 6121 /* record length, and DMA address */ 6122 dma_unmap_len_set(tx_buffer, len, size); 6123 dma_unmap_addr_set(tx_buffer, dma, dma); 6124 6125 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6126 6127 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6128 tx_desc->read.cmd_type_len = 6129 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6130 6131 i++; 6132 tx_desc++; 6133 if (i == tx_ring->count) { 6134 tx_desc = IGB_TX_DESC(tx_ring, 0); 6135 i = 0; 6136 } 6137 tx_desc->read.olinfo_status = 0; 6138 6139 dma += IGB_MAX_DATA_PER_TXD; 6140 size -= IGB_MAX_DATA_PER_TXD; 6141 6142 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6143 } 6144 6145 if (likely(!data_len)) 6146 break; 6147 6148 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6149 6150 i++; 6151 tx_desc++; 6152 if (i == tx_ring->count) { 6153 tx_desc = IGB_TX_DESC(tx_ring, 0); 6154 i = 0; 6155 } 6156 tx_desc->read.olinfo_status = 0; 6157 6158 size = skb_frag_size(frag); 6159 data_len -= size; 6160 6161 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6162 size, DMA_TO_DEVICE); 6163 6164 tx_buffer = &tx_ring->tx_buffer_info[i]; 6165 } 6166 6167 /* write last descriptor with RS and EOP bits */ 6168 cmd_type |= size | IGB_TXD_DCMD; 6169 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6170 6171 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6172 6173 /* set the timestamp */ 6174 first->time_stamp = jiffies; 6175 6176 skb_tx_timestamp(skb); 6177 6178 /* Force memory writes to complete before letting h/w know there 6179 * are new descriptors to fetch. (Only applicable for weak-ordered 6180 * memory model archs, such as IA-64). 6181 * 6182 * We also need this memory barrier to make certain all of the 6183 * status bits have been updated before next_to_watch is written. 6184 */ 6185 dma_wmb(); 6186 6187 /* set next_to_watch value indicating a packet is present */ 6188 first->next_to_watch = tx_desc; 6189 6190 i++; 6191 if (i == tx_ring->count) 6192 i = 0; 6193 6194 tx_ring->next_to_use = i; 6195 6196 /* Make sure there is space in the ring for the next send. */ 6197 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6198 6199 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6200 writel(i, tx_ring->tail); 6201 } 6202 return 0; 6203 6204 dma_error: 6205 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6206 tx_buffer = &tx_ring->tx_buffer_info[i]; 6207 6208 /* clear dma mappings for failed tx_buffer_info map */ 6209 while (tx_buffer != first) { 6210 if (dma_unmap_len(tx_buffer, len)) 6211 dma_unmap_page(tx_ring->dev, 6212 dma_unmap_addr(tx_buffer, dma), 6213 dma_unmap_len(tx_buffer, len), 6214 DMA_TO_DEVICE); 6215 dma_unmap_len_set(tx_buffer, len, 0); 6216 6217 if (i-- == 0) 6218 i += tx_ring->count; 6219 tx_buffer = &tx_ring->tx_buffer_info[i]; 6220 } 6221 6222 if (dma_unmap_len(tx_buffer, len)) 6223 dma_unmap_single(tx_ring->dev, 6224 dma_unmap_addr(tx_buffer, dma), 6225 dma_unmap_len(tx_buffer, len), 6226 DMA_TO_DEVICE); 6227 dma_unmap_len_set(tx_buffer, len, 0); 6228 6229 dev_kfree_skb_any(tx_buffer->skb); 6230 tx_buffer->skb = NULL; 6231 6232 tx_ring->next_to_use = i; 6233 6234 return -1; 6235 } 6236 6237 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6238 struct igb_ring *tx_ring, 6239 struct xdp_frame *xdpf) 6240 { 6241 union e1000_adv_tx_desc *tx_desc; 6242 u32 len, cmd_type, olinfo_status; 6243 struct igb_tx_buffer *tx_buffer; 6244 dma_addr_t dma; 6245 u16 i; 6246 6247 len = xdpf->len; 6248 6249 if (unlikely(!igb_desc_unused(tx_ring))) 6250 return IGB_XDP_CONSUMED; 6251 6252 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE); 6253 if (dma_mapping_error(tx_ring->dev, dma)) 6254 return IGB_XDP_CONSUMED; 6255 6256 /* record the location of the first descriptor for this packet */ 6257 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6258 tx_buffer->bytecount = len; 6259 tx_buffer->gso_segs = 1; 6260 tx_buffer->protocol = 0; 6261 6262 i = tx_ring->next_to_use; 6263 tx_desc = IGB_TX_DESC(tx_ring, i); 6264 6265 dma_unmap_len_set(tx_buffer, len, len); 6266 dma_unmap_addr_set(tx_buffer, dma, dma); 6267 tx_buffer->type = IGB_TYPE_XDP; 6268 tx_buffer->xdpf = xdpf; 6269 6270 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6271 6272 /* put descriptor type bits */ 6273 cmd_type = E1000_ADVTXD_DTYP_DATA | 6274 E1000_ADVTXD_DCMD_DEXT | 6275 E1000_ADVTXD_DCMD_IFCS; 6276 cmd_type |= len | IGB_TXD_DCMD; 6277 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6278 6279 olinfo_status = cpu_to_le32(len << E1000_ADVTXD_PAYLEN_SHIFT); 6280 /* 82575 requires a unique index per ring */ 6281 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6282 olinfo_status |= tx_ring->reg_idx << 4; 6283 6284 tx_desc->read.olinfo_status = olinfo_status; 6285 6286 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount); 6287 6288 /* set the timestamp */ 6289 tx_buffer->time_stamp = jiffies; 6290 6291 /* Avoid any potential race with xdp_xmit and cleanup */ 6292 smp_wmb(); 6293 6294 /* set next_to_watch value indicating a packet is present */ 6295 i++; 6296 if (i == tx_ring->count) 6297 i = 0; 6298 6299 tx_buffer->next_to_watch = tx_desc; 6300 tx_ring->next_to_use = i; 6301 6302 /* Make sure there is space in the ring for the next send. */ 6303 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6304 6305 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6306 writel(i, tx_ring->tail); 6307 6308 return IGB_XDP_TX; 6309 } 6310 6311 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6312 struct igb_ring *tx_ring) 6313 { 6314 struct igb_tx_buffer *first; 6315 int tso; 6316 u32 tx_flags = 0; 6317 unsigned short f; 6318 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6319 __be16 protocol = vlan_get_protocol(skb); 6320 u8 hdr_len = 0; 6321 6322 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6323 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6324 * + 2 desc gap to keep tail from touching head, 6325 * + 1 desc for context descriptor, 6326 * otherwise try next time 6327 */ 6328 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6329 count += TXD_USE_COUNT(skb_frag_size( 6330 &skb_shinfo(skb)->frags[f])); 6331 6332 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6333 /* this is a hard error */ 6334 return NETDEV_TX_BUSY; 6335 } 6336 6337 /* record the location of the first descriptor for this packet */ 6338 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6339 first->type = IGB_TYPE_SKB; 6340 first->skb = skb; 6341 first->bytecount = skb->len; 6342 first->gso_segs = 1; 6343 6344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6345 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6346 6347 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6348 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6349 &adapter->state)) { 6350 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6351 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6352 6353 adapter->ptp_tx_skb = skb_get(skb); 6354 adapter->ptp_tx_start = jiffies; 6355 if (adapter->hw.mac.type == e1000_82576) 6356 schedule_work(&adapter->ptp_tx_work); 6357 } else { 6358 adapter->tx_hwtstamp_skipped++; 6359 } 6360 } 6361 6362 if (skb_vlan_tag_present(skb)) { 6363 tx_flags |= IGB_TX_FLAGS_VLAN; 6364 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6365 } 6366 6367 /* record initial flags and protocol */ 6368 first->tx_flags = tx_flags; 6369 first->protocol = protocol; 6370 6371 tso = igb_tso(tx_ring, first, &hdr_len); 6372 if (tso < 0) 6373 goto out_drop; 6374 else if (!tso) 6375 igb_tx_csum(tx_ring, first); 6376 6377 if (igb_tx_map(tx_ring, first, hdr_len)) 6378 goto cleanup_tx_tstamp; 6379 6380 return NETDEV_TX_OK; 6381 6382 out_drop: 6383 dev_kfree_skb_any(first->skb); 6384 first->skb = NULL; 6385 cleanup_tx_tstamp: 6386 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6387 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6388 6389 dev_kfree_skb_any(adapter->ptp_tx_skb); 6390 adapter->ptp_tx_skb = NULL; 6391 if (adapter->hw.mac.type == e1000_82576) 6392 cancel_work_sync(&adapter->ptp_tx_work); 6393 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6394 } 6395 6396 return NETDEV_TX_OK; 6397 } 6398 6399 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6400 struct sk_buff *skb) 6401 { 6402 unsigned int r_idx = skb->queue_mapping; 6403 6404 if (r_idx >= adapter->num_tx_queues) 6405 r_idx = r_idx % adapter->num_tx_queues; 6406 6407 return adapter->tx_ring[r_idx]; 6408 } 6409 6410 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6411 struct net_device *netdev) 6412 { 6413 struct igb_adapter *adapter = netdev_priv(netdev); 6414 6415 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6416 * in order to meet this minimum size requirement. 6417 */ 6418 if (skb_put_padto(skb, 17)) 6419 return NETDEV_TX_OK; 6420 6421 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6422 } 6423 6424 /** 6425 * igb_tx_timeout - Respond to a Tx Hang 6426 * @netdev: network interface device structure 6427 * @txqueue: number of the Tx queue that hung (unused) 6428 **/ 6429 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6430 { 6431 struct igb_adapter *adapter = netdev_priv(netdev); 6432 struct e1000_hw *hw = &adapter->hw; 6433 6434 /* Do the reset outside of interrupt context */ 6435 adapter->tx_timeout_count++; 6436 6437 if (hw->mac.type >= e1000_82580) 6438 hw->dev_spec._82575.global_device_reset = true; 6439 6440 schedule_work(&adapter->reset_task); 6441 wr32(E1000_EICS, 6442 (adapter->eims_enable_mask & ~adapter->eims_other)); 6443 } 6444 6445 static void igb_reset_task(struct work_struct *work) 6446 { 6447 struct igb_adapter *adapter; 6448 adapter = container_of(work, struct igb_adapter, reset_task); 6449 6450 rtnl_lock(); 6451 /* If we're already down or resetting, just bail */ 6452 if (test_bit(__IGB_DOWN, &adapter->state) || 6453 test_bit(__IGB_RESETTING, &adapter->state)) { 6454 rtnl_unlock(); 6455 return; 6456 } 6457 6458 igb_dump(adapter); 6459 netdev_err(adapter->netdev, "Reset adapter\n"); 6460 igb_reinit_locked(adapter); 6461 rtnl_unlock(); 6462 } 6463 6464 /** 6465 * igb_get_stats64 - Get System Network Statistics 6466 * @netdev: network interface device structure 6467 * @stats: rtnl_link_stats64 pointer 6468 **/ 6469 static void igb_get_stats64(struct net_device *netdev, 6470 struct rtnl_link_stats64 *stats) 6471 { 6472 struct igb_adapter *adapter = netdev_priv(netdev); 6473 6474 spin_lock(&adapter->stats64_lock); 6475 igb_update_stats(adapter); 6476 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6477 spin_unlock(&adapter->stats64_lock); 6478 } 6479 6480 /** 6481 * igb_change_mtu - Change the Maximum Transfer Unit 6482 * @netdev: network interface device structure 6483 * @new_mtu: new value for maximum frame size 6484 * 6485 * Returns 0 on success, negative on failure 6486 **/ 6487 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6488 { 6489 struct igb_adapter *adapter = netdev_priv(netdev); 6490 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6491 6492 if (adapter->xdp_prog) { 6493 int i; 6494 6495 for (i = 0; i < adapter->num_rx_queues; i++) { 6496 struct igb_ring *ring = adapter->rx_ring[i]; 6497 6498 if (max_frame > igb_rx_bufsz(ring)) { 6499 netdev_warn(adapter->netdev, 6500 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6501 max_frame); 6502 return -EINVAL; 6503 } 6504 } 6505 } 6506 6507 /* adjust max frame to be at least the size of a standard frame */ 6508 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6509 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6510 6511 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6512 usleep_range(1000, 2000); 6513 6514 /* igb_down has a dependency on max_frame_size */ 6515 adapter->max_frame_size = max_frame; 6516 6517 if (netif_running(netdev)) 6518 igb_down(adapter); 6519 6520 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6521 netdev->mtu, new_mtu); 6522 netdev->mtu = new_mtu; 6523 6524 if (netif_running(netdev)) 6525 igb_up(adapter); 6526 else 6527 igb_reset(adapter); 6528 6529 clear_bit(__IGB_RESETTING, &adapter->state); 6530 6531 return 0; 6532 } 6533 6534 /** 6535 * igb_update_stats - Update the board statistics counters 6536 * @adapter: board private structure 6537 **/ 6538 void igb_update_stats(struct igb_adapter *adapter) 6539 { 6540 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6541 struct e1000_hw *hw = &adapter->hw; 6542 struct pci_dev *pdev = adapter->pdev; 6543 u32 reg, mpc; 6544 int i; 6545 u64 bytes, packets; 6546 unsigned int start; 6547 u64 _bytes, _packets; 6548 6549 /* Prevent stats update while adapter is being reset, or if the pci 6550 * connection is down. 6551 */ 6552 if (adapter->link_speed == 0) 6553 return; 6554 if (pci_channel_offline(pdev)) 6555 return; 6556 6557 bytes = 0; 6558 packets = 0; 6559 6560 rcu_read_lock(); 6561 for (i = 0; i < adapter->num_rx_queues; i++) { 6562 struct igb_ring *ring = adapter->rx_ring[i]; 6563 u32 rqdpc = rd32(E1000_RQDPC(i)); 6564 if (hw->mac.type >= e1000_i210) 6565 wr32(E1000_RQDPC(i), 0); 6566 6567 if (rqdpc) { 6568 ring->rx_stats.drops += rqdpc; 6569 net_stats->rx_fifo_errors += rqdpc; 6570 } 6571 6572 do { 6573 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6574 _bytes = ring->rx_stats.bytes; 6575 _packets = ring->rx_stats.packets; 6576 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6577 bytes += _bytes; 6578 packets += _packets; 6579 } 6580 6581 net_stats->rx_bytes = bytes; 6582 net_stats->rx_packets = packets; 6583 6584 bytes = 0; 6585 packets = 0; 6586 for (i = 0; i < adapter->num_tx_queues; i++) { 6587 struct igb_ring *ring = adapter->tx_ring[i]; 6588 do { 6589 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6590 _bytes = ring->tx_stats.bytes; 6591 _packets = ring->tx_stats.packets; 6592 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6593 bytes += _bytes; 6594 packets += _packets; 6595 } 6596 net_stats->tx_bytes = bytes; 6597 net_stats->tx_packets = packets; 6598 rcu_read_unlock(); 6599 6600 /* read stats registers */ 6601 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6602 adapter->stats.gprc += rd32(E1000_GPRC); 6603 adapter->stats.gorc += rd32(E1000_GORCL); 6604 rd32(E1000_GORCH); /* clear GORCL */ 6605 adapter->stats.bprc += rd32(E1000_BPRC); 6606 adapter->stats.mprc += rd32(E1000_MPRC); 6607 adapter->stats.roc += rd32(E1000_ROC); 6608 6609 adapter->stats.prc64 += rd32(E1000_PRC64); 6610 adapter->stats.prc127 += rd32(E1000_PRC127); 6611 adapter->stats.prc255 += rd32(E1000_PRC255); 6612 adapter->stats.prc511 += rd32(E1000_PRC511); 6613 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6614 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6615 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6616 adapter->stats.sec += rd32(E1000_SEC); 6617 6618 mpc = rd32(E1000_MPC); 6619 adapter->stats.mpc += mpc; 6620 net_stats->rx_fifo_errors += mpc; 6621 adapter->stats.scc += rd32(E1000_SCC); 6622 adapter->stats.ecol += rd32(E1000_ECOL); 6623 adapter->stats.mcc += rd32(E1000_MCC); 6624 adapter->stats.latecol += rd32(E1000_LATECOL); 6625 adapter->stats.dc += rd32(E1000_DC); 6626 adapter->stats.rlec += rd32(E1000_RLEC); 6627 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6628 adapter->stats.xontxc += rd32(E1000_XONTXC); 6629 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6630 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6631 adapter->stats.fcruc += rd32(E1000_FCRUC); 6632 adapter->stats.gptc += rd32(E1000_GPTC); 6633 adapter->stats.gotc += rd32(E1000_GOTCL); 6634 rd32(E1000_GOTCH); /* clear GOTCL */ 6635 adapter->stats.rnbc += rd32(E1000_RNBC); 6636 adapter->stats.ruc += rd32(E1000_RUC); 6637 adapter->stats.rfc += rd32(E1000_RFC); 6638 adapter->stats.rjc += rd32(E1000_RJC); 6639 adapter->stats.tor += rd32(E1000_TORH); 6640 adapter->stats.tot += rd32(E1000_TOTH); 6641 adapter->stats.tpr += rd32(E1000_TPR); 6642 6643 adapter->stats.ptc64 += rd32(E1000_PTC64); 6644 adapter->stats.ptc127 += rd32(E1000_PTC127); 6645 adapter->stats.ptc255 += rd32(E1000_PTC255); 6646 adapter->stats.ptc511 += rd32(E1000_PTC511); 6647 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6648 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6649 6650 adapter->stats.mptc += rd32(E1000_MPTC); 6651 adapter->stats.bptc += rd32(E1000_BPTC); 6652 6653 adapter->stats.tpt += rd32(E1000_TPT); 6654 adapter->stats.colc += rd32(E1000_COLC); 6655 6656 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6657 /* read internal phy specific stats */ 6658 reg = rd32(E1000_CTRL_EXT); 6659 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6660 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6661 6662 /* this stat has invalid values on i210/i211 */ 6663 if ((hw->mac.type != e1000_i210) && 6664 (hw->mac.type != e1000_i211)) 6665 adapter->stats.tncrs += rd32(E1000_TNCRS); 6666 } 6667 6668 adapter->stats.tsctc += rd32(E1000_TSCTC); 6669 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6670 6671 adapter->stats.iac += rd32(E1000_IAC); 6672 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6673 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6674 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6675 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6676 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6677 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6678 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6679 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6680 6681 /* Fill out the OS statistics structure */ 6682 net_stats->multicast = adapter->stats.mprc; 6683 net_stats->collisions = adapter->stats.colc; 6684 6685 /* Rx Errors */ 6686 6687 /* RLEC on some newer hardware can be incorrect so build 6688 * our own version based on RUC and ROC 6689 */ 6690 net_stats->rx_errors = adapter->stats.rxerrc + 6691 adapter->stats.crcerrs + adapter->stats.algnerrc + 6692 adapter->stats.ruc + adapter->stats.roc + 6693 adapter->stats.cexterr; 6694 net_stats->rx_length_errors = adapter->stats.ruc + 6695 adapter->stats.roc; 6696 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6697 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6698 net_stats->rx_missed_errors = adapter->stats.mpc; 6699 6700 /* Tx Errors */ 6701 net_stats->tx_errors = adapter->stats.ecol + 6702 adapter->stats.latecol; 6703 net_stats->tx_aborted_errors = adapter->stats.ecol; 6704 net_stats->tx_window_errors = adapter->stats.latecol; 6705 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6706 6707 /* Tx Dropped needs to be maintained elsewhere */ 6708 6709 /* Management Stats */ 6710 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6711 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6712 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6713 6714 /* OS2BMC Stats */ 6715 reg = rd32(E1000_MANC); 6716 if (reg & E1000_MANC_EN_BMC2OS) { 6717 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6718 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6719 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6720 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6721 } 6722 } 6723 6724 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6725 { 6726 struct e1000_hw *hw = &adapter->hw; 6727 struct ptp_clock_event event; 6728 struct timespec64 ts; 6729 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6730 6731 if (tsicr & TSINTR_SYS_WRAP) { 6732 event.type = PTP_CLOCK_PPS; 6733 if (adapter->ptp_caps.pps) 6734 ptp_clock_event(adapter->ptp_clock, &event); 6735 ack |= TSINTR_SYS_WRAP; 6736 } 6737 6738 if (tsicr & E1000_TSICR_TXTS) { 6739 /* retrieve hardware timestamp */ 6740 schedule_work(&adapter->ptp_tx_work); 6741 ack |= E1000_TSICR_TXTS; 6742 } 6743 6744 if (tsicr & TSINTR_TT0) { 6745 spin_lock(&adapter->tmreg_lock); 6746 ts = timespec64_add(adapter->perout[0].start, 6747 adapter->perout[0].period); 6748 /* u32 conversion of tv_sec is safe until y2106 */ 6749 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6750 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6751 tsauxc = rd32(E1000_TSAUXC); 6752 tsauxc |= TSAUXC_EN_TT0; 6753 wr32(E1000_TSAUXC, tsauxc); 6754 adapter->perout[0].start = ts; 6755 spin_unlock(&adapter->tmreg_lock); 6756 ack |= TSINTR_TT0; 6757 } 6758 6759 if (tsicr & TSINTR_TT1) { 6760 spin_lock(&adapter->tmreg_lock); 6761 ts = timespec64_add(adapter->perout[1].start, 6762 adapter->perout[1].period); 6763 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6764 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6765 tsauxc = rd32(E1000_TSAUXC); 6766 tsauxc |= TSAUXC_EN_TT1; 6767 wr32(E1000_TSAUXC, tsauxc); 6768 adapter->perout[1].start = ts; 6769 spin_unlock(&adapter->tmreg_lock); 6770 ack |= TSINTR_TT1; 6771 } 6772 6773 if (tsicr & TSINTR_AUTT0) { 6774 nsec = rd32(E1000_AUXSTMPL0); 6775 sec = rd32(E1000_AUXSTMPH0); 6776 event.type = PTP_CLOCK_EXTTS; 6777 event.index = 0; 6778 event.timestamp = sec * 1000000000ULL + nsec; 6779 ptp_clock_event(adapter->ptp_clock, &event); 6780 ack |= TSINTR_AUTT0; 6781 } 6782 6783 if (tsicr & TSINTR_AUTT1) { 6784 nsec = rd32(E1000_AUXSTMPL1); 6785 sec = rd32(E1000_AUXSTMPH1); 6786 event.type = PTP_CLOCK_EXTTS; 6787 event.index = 1; 6788 event.timestamp = sec * 1000000000ULL + nsec; 6789 ptp_clock_event(adapter->ptp_clock, &event); 6790 ack |= TSINTR_AUTT1; 6791 } 6792 6793 /* acknowledge the interrupts */ 6794 wr32(E1000_TSICR, ack); 6795 } 6796 6797 static irqreturn_t igb_msix_other(int irq, void *data) 6798 { 6799 struct igb_adapter *adapter = data; 6800 struct e1000_hw *hw = &adapter->hw; 6801 u32 icr = rd32(E1000_ICR); 6802 /* reading ICR causes bit 31 of EICR to be cleared */ 6803 6804 if (icr & E1000_ICR_DRSTA) 6805 schedule_work(&adapter->reset_task); 6806 6807 if (icr & E1000_ICR_DOUTSYNC) { 6808 /* HW is reporting DMA is out of sync */ 6809 adapter->stats.doosync++; 6810 /* The DMA Out of Sync is also indication of a spoof event 6811 * in IOV mode. Check the Wrong VM Behavior register to 6812 * see if it is really a spoof event. 6813 */ 6814 igb_check_wvbr(adapter); 6815 } 6816 6817 /* Check for a mailbox event */ 6818 if (icr & E1000_ICR_VMMB) 6819 igb_msg_task(adapter); 6820 6821 if (icr & E1000_ICR_LSC) { 6822 hw->mac.get_link_status = 1; 6823 /* guard against interrupt when we're going down */ 6824 if (!test_bit(__IGB_DOWN, &adapter->state)) 6825 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6826 } 6827 6828 if (icr & E1000_ICR_TS) 6829 igb_tsync_interrupt(adapter); 6830 6831 wr32(E1000_EIMS, adapter->eims_other); 6832 6833 return IRQ_HANDLED; 6834 } 6835 6836 static void igb_write_itr(struct igb_q_vector *q_vector) 6837 { 6838 struct igb_adapter *adapter = q_vector->adapter; 6839 u32 itr_val = q_vector->itr_val & 0x7FFC; 6840 6841 if (!q_vector->set_itr) 6842 return; 6843 6844 if (!itr_val) 6845 itr_val = 0x4; 6846 6847 if (adapter->hw.mac.type == e1000_82575) 6848 itr_val |= itr_val << 16; 6849 else 6850 itr_val |= E1000_EITR_CNT_IGNR; 6851 6852 writel(itr_val, q_vector->itr_register); 6853 q_vector->set_itr = 0; 6854 } 6855 6856 static irqreturn_t igb_msix_ring(int irq, void *data) 6857 { 6858 struct igb_q_vector *q_vector = data; 6859 6860 /* Write the ITR value calculated from the previous interrupt. */ 6861 igb_write_itr(q_vector); 6862 6863 napi_schedule(&q_vector->napi); 6864 6865 return IRQ_HANDLED; 6866 } 6867 6868 #ifdef CONFIG_IGB_DCA 6869 static void igb_update_tx_dca(struct igb_adapter *adapter, 6870 struct igb_ring *tx_ring, 6871 int cpu) 6872 { 6873 struct e1000_hw *hw = &adapter->hw; 6874 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6875 6876 if (hw->mac.type != e1000_82575) 6877 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6878 6879 /* We can enable relaxed ordering for reads, but not writes when 6880 * DCA is enabled. This is due to a known issue in some chipsets 6881 * which will cause the DCA tag to be cleared. 6882 */ 6883 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6884 E1000_DCA_TXCTRL_DATA_RRO_EN | 6885 E1000_DCA_TXCTRL_DESC_DCA_EN; 6886 6887 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6888 } 6889 6890 static void igb_update_rx_dca(struct igb_adapter *adapter, 6891 struct igb_ring *rx_ring, 6892 int cpu) 6893 { 6894 struct e1000_hw *hw = &adapter->hw; 6895 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6896 6897 if (hw->mac.type != e1000_82575) 6898 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6899 6900 /* We can enable relaxed ordering for reads, but not writes when 6901 * DCA is enabled. This is due to a known issue in some chipsets 6902 * which will cause the DCA tag to be cleared. 6903 */ 6904 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6905 E1000_DCA_RXCTRL_DESC_DCA_EN; 6906 6907 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6908 } 6909 6910 static void igb_update_dca(struct igb_q_vector *q_vector) 6911 { 6912 struct igb_adapter *adapter = q_vector->adapter; 6913 int cpu = get_cpu(); 6914 6915 if (q_vector->cpu == cpu) 6916 goto out_no_update; 6917 6918 if (q_vector->tx.ring) 6919 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6920 6921 if (q_vector->rx.ring) 6922 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6923 6924 q_vector->cpu = cpu; 6925 out_no_update: 6926 put_cpu(); 6927 } 6928 6929 static void igb_setup_dca(struct igb_adapter *adapter) 6930 { 6931 struct e1000_hw *hw = &adapter->hw; 6932 int i; 6933 6934 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6935 return; 6936 6937 /* Always use CB2 mode, difference is masked in the CB driver. */ 6938 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6939 6940 for (i = 0; i < adapter->num_q_vectors; i++) { 6941 adapter->q_vector[i]->cpu = -1; 6942 igb_update_dca(adapter->q_vector[i]); 6943 } 6944 } 6945 6946 static int __igb_notify_dca(struct device *dev, void *data) 6947 { 6948 struct net_device *netdev = dev_get_drvdata(dev); 6949 struct igb_adapter *adapter = netdev_priv(netdev); 6950 struct pci_dev *pdev = adapter->pdev; 6951 struct e1000_hw *hw = &adapter->hw; 6952 unsigned long event = *(unsigned long *)data; 6953 6954 switch (event) { 6955 case DCA_PROVIDER_ADD: 6956 /* if already enabled, don't do it again */ 6957 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6958 break; 6959 if (dca_add_requester(dev) == 0) { 6960 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6961 dev_info(&pdev->dev, "DCA enabled\n"); 6962 igb_setup_dca(adapter); 6963 break; 6964 } 6965 fallthrough; /* since DCA is disabled. */ 6966 case DCA_PROVIDER_REMOVE: 6967 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6968 /* without this a class_device is left 6969 * hanging around in the sysfs model 6970 */ 6971 dca_remove_requester(dev); 6972 dev_info(&pdev->dev, "DCA disabled\n"); 6973 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6974 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6975 } 6976 break; 6977 } 6978 6979 return 0; 6980 } 6981 6982 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6983 void *p) 6984 { 6985 int ret_val; 6986 6987 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6988 __igb_notify_dca); 6989 6990 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6991 } 6992 #endif /* CONFIG_IGB_DCA */ 6993 6994 #ifdef CONFIG_PCI_IOV 6995 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6996 { 6997 unsigned char mac_addr[ETH_ALEN]; 6998 6999 eth_zero_addr(mac_addr); 7000 igb_set_vf_mac(adapter, vf, mac_addr); 7001 7002 /* By default spoof check is enabled for all VFs */ 7003 adapter->vf_data[vf].spoofchk_enabled = true; 7004 7005 /* By default VFs are not trusted */ 7006 adapter->vf_data[vf].trusted = false; 7007 7008 return 0; 7009 } 7010 7011 #endif 7012 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7013 { 7014 struct e1000_hw *hw = &adapter->hw; 7015 u32 ping; 7016 int i; 7017 7018 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7019 ping = E1000_PF_CONTROL_MSG; 7020 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7021 ping |= E1000_VT_MSGTYPE_CTS; 7022 igb_write_mbx(hw, &ping, 1, i); 7023 } 7024 } 7025 7026 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7027 { 7028 struct e1000_hw *hw = &adapter->hw; 7029 u32 vmolr = rd32(E1000_VMOLR(vf)); 7030 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7031 7032 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7033 IGB_VF_FLAG_MULTI_PROMISC); 7034 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7035 7036 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7037 vmolr |= E1000_VMOLR_MPME; 7038 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7039 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7040 } else { 7041 /* if we have hashes and we are clearing a multicast promisc 7042 * flag we need to write the hashes to the MTA as this step 7043 * was previously skipped 7044 */ 7045 if (vf_data->num_vf_mc_hashes > 30) { 7046 vmolr |= E1000_VMOLR_MPME; 7047 } else if (vf_data->num_vf_mc_hashes) { 7048 int j; 7049 7050 vmolr |= E1000_VMOLR_ROMPE; 7051 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7052 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7053 } 7054 } 7055 7056 wr32(E1000_VMOLR(vf), vmolr); 7057 7058 /* there are flags left unprocessed, likely not supported */ 7059 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7060 return -EINVAL; 7061 7062 return 0; 7063 } 7064 7065 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7066 u32 *msgbuf, u32 vf) 7067 { 7068 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7069 u16 *hash_list = (u16 *)&msgbuf[1]; 7070 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7071 int i; 7072 7073 /* salt away the number of multicast addresses assigned 7074 * to this VF for later use to restore when the PF multi cast 7075 * list changes 7076 */ 7077 vf_data->num_vf_mc_hashes = n; 7078 7079 /* only up to 30 hash values supported */ 7080 if (n > 30) 7081 n = 30; 7082 7083 /* store the hashes for later use */ 7084 for (i = 0; i < n; i++) 7085 vf_data->vf_mc_hashes[i] = hash_list[i]; 7086 7087 /* Flush and reset the mta with the new values */ 7088 igb_set_rx_mode(adapter->netdev); 7089 7090 return 0; 7091 } 7092 7093 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7094 { 7095 struct e1000_hw *hw = &adapter->hw; 7096 struct vf_data_storage *vf_data; 7097 int i, j; 7098 7099 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7100 u32 vmolr = rd32(E1000_VMOLR(i)); 7101 7102 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7103 7104 vf_data = &adapter->vf_data[i]; 7105 7106 if ((vf_data->num_vf_mc_hashes > 30) || 7107 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7108 vmolr |= E1000_VMOLR_MPME; 7109 } else if (vf_data->num_vf_mc_hashes) { 7110 vmolr |= E1000_VMOLR_ROMPE; 7111 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7112 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7113 } 7114 wr32(E1000_VMOLR(i), vmolr); 7115 } 7116 } 7117 7118 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7119 { 7120 struct e1000_hw *hw = &adapter->hw; 7121 u32 pool_mask, vlvf_mask, i; 7122 7123 /* create mask for VF and other pools */ 7124 pool_mask = E1000_VLVF_POOLSEL_MASK; 7125 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7126 7127 /* drop PF from pool bits */ 7128 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7129 adapter->vfs_allocated_count); 7130 7131 /* Find the vlan filter for this id */ 7132 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7133 u32 vlvf = rd32(E1000_VLVF(i)); 7134 u32 vfta_mask, vid, vfta; 7135 7136 /* remove the vf from the pool */ 7137 if (!(vlvf & vlvf_mask)) 7138 continue; 7139 7140 /* clear out bit from VLVF */ 7141 vlvf ^= vlvf_mask; 7142 7143 /* if other pools are present, just remove ourselves */ 7144 if (vlvf & pool_mask) 7145 goto update_vlvfb; 7146 7147 /* if PF is present, leave VFTA */ 7148 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7149 goto update_vlvf; 7150 7151 vid = vlvf & E1000_VLVF_VLANID_MASK; 7152 vfta_mask = BIT(vid % 32); 7153 7154 /* clear bit from VFTA */ 7155 vfta = adapter->shadow_vfta[vid / 32]; 7156 if (vfta & vfta_mask) 7157 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7158 update_vlvf: 7159 /* clear pool selection enable */ 7160 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7161 vlvf &= E1000_VLVF_POOLSEL_MASK; 7162 else 7163 vlvf = 0; 7164 update_vlvfb: 7165 /* clear pool bits */ 7166 wr32(E1000_VLVF(i), vlvf); 7167 } 7168 } 7169 7170 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7171 { 7172 u32 vlvf; 7173 int idx; 7174 7175 /* short cut the special case */ 7176 if (vlan == 0) 7177 return 0; 7178 7179 /* Search for the VLAN id in the VLVF entries */ 7180 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7181 vlvf = rd32(E1000_VLVF(idx)); 7182 if ((vlvf & VLAN_VID_MASK) == vlan) 7183 break; 7184 } 7185 7186 return idx; 7187 } 7188 7189 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7190 { 7191 struct e1000_hw *hw = &adapter->hw; 7192 u32 bits, pf_id; 7193 int idx; 7194 7195 idx = igb_find_vlvf_entry(hw, vid); 7196 if (!idx) 7197 return; 7198 7199 /* See if any other pools are set for this VLAN filter 7200 * entry other than the PF. 7201 */ 7202 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7203 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7204 bits &= rd32(E1000_VLVF(idx)); 7205 7206 /* Disable the filter so this falls into the default pool. */ 7207 if (!bits) { 7208 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7209 wr32(E1000_VLVF(idx), BIT(pf_id)); 7210 else 7211 wr32(E1000_VLVF(idx), 0); 7212 } 7213 } 7214 7215 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7216 bool add, u32 vf) 7217 { 7218 int pf_id = adapter->vfs_allocated_count; 7219 struct e1000_hw *hw = &adapter->hw; 7220 int err; 7221 7222 /* If VLAN overlaps with one the PF is currently monitoring make 7223 * sure that we are able to allocate a VLVF entry. This may be 7224 * redundant but it guarantees PF will maintain visibility to 7225 * the VLAN. 7226 */ 7227 if (add && test_bit(vid, adapter->active_vlans)) { 7228 err = igb_vfta_set(hw, vid, pf_id, true, false); 7229 if (err) 7230 return err; 7231 } 7232 7233 err = igb_vfta_set(hw, vid, vf, add, false); 7234 7235 if (add && !err) 7236 return err; 7237 7238 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7239 * we may need to drop the PF pool bit in order to allow us to free 7240 * up the VLVF resources. 7241 */ 7242 if (test_bit(vid, adapter->active_vlans) || 7243 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7244 igb_update_pf_vlvf(adapter, vid); 7245 7246 return err; 7247 } 7248 7249 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7250 { 7251 struct e1000_hw *hw = &adapter->hw; 7252 7253 if (vid) 7254 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7255 else 7256 wr32(E1000_VMVIR(vf), 0); 7257 } 7258 7259 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7260 u16 vlan, u8 qos) 7261 { 7262 int err; 7263 7264 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7265 if (err) 7266 return err; 7267 7268 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7269 igb_set_vmolr(adapter, vf, !vlan); 7270 7271 /* revoke access to previous VLAN */ 7272 if (vlan != adapter->vf_data[vf].pf_vlan) 7273 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7274 false, vf); 7275 7276 adapter->vf_data[vf].pf_vlan = vlan; 7277 adapter->vf_data[vf].pf_qos = qos; 7278 igb_set_vf_vlan_strip(adapter, vf, true); 7279 dev_info(&adapter->pdev->dev, 7280 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7281 if (test_bit(__IGB_DOWN, &adapter->state)) { 7282 dev_warn(&adapter->pdev->dev, 7283 "The VF VLAN has been set, but the PF device is not up.\n"); 7284 dev_warn(&adapter->pdev->dev, 7285 "Bring the PF device up before attempting to use the VF device.\n"); 7286 } 7287 7288 return err; 7289 } 7290 7291 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7292 { 7293 /* Restore tagless access via VLAN 0 */ 7294 igb_set_vf_vlan(adapter, 0, true, vf); 7295 7296 igb_set_vmvir(adapter, 0, vf); 7297 igb_set_vmolr(adapter, vf, true); 7298 7299 /* Remove any PF assigned VLAN */ 7300 if (adapter->vf_data[vf].pf_vlan) 7301 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7302 false, vf); 7303 7304 adapter->vf_data[vf].pf_vlan = 0; 7305 adapter->vf_data[vf].pf_qos = 0; 7306 igb_set_vf_vlan_strip(adapter, vf, false); 7307 7308 return 0; 7309 } 7310 7311 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7312 u16 vlan, u8 qos, __be16 vlan_proto) 7313 { 7314 struct igb_adapter *adapter = netdev_priv(netdev); 7315 7316 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7317 return -EINVAL; 7318 7319 if (vlan_proto != htons(ETH_P_8021Q)) 7320 return -EPROTONOSUPPORT; 7321 7322 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7323 igb_disable_port_vlan(adapter, vf); 7324 } 7325 7326 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7327 { 7328 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7329 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7330 int ret; 7331 7332 if (adapter->vf_data[vf].pf_vlan) 7333 return -1; 7334 7335 /* VLAN 0 is a special case, don't allow it to be removed */ 7336 if (!vid && !add) 7337 return 0; 7338 7339 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7340 if (!ret) 7341 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7342 return ret; 7343 } 7344 7345 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7346 { 7347 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7348 7349 /* clear flags - except flag that indicates PF has set the MAC */ 7350 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7351 vf_data->last_nack = jiffies; 7352 7353 /* reset vlans for device */ 7354 igb_clear_vf_vfta(adapter, vf); 7355 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7356 igb_set_vmvir(adapter, vf_data->pf_vlan | 7357 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7358 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7359 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7360 7361 /* reset multicast table array for vf */ 7362 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7363 7364 /* Flush and reset the mta with the new values */ 7365 igb_set_rx_mode(adapter->netdev); 7366 } 7367 7368 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7369 { 7370 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7371 7372 /* clear mac address as we were hotplug removed/added */ 7373 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7374 eth_zero_addr(vf_mac); 7375 7376 /* process remaining reset events */ 7377 igb_vf_reset(adapter, vf); 7378 } 7379 7380 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7381 { 7382 struct e1000_hw *hw = &adapter->hw; 7383 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7384 u32 reg, msgbuf[3]; 7385 u8 *addr = (u8 *)(&msgbuf[1]); 7386 7387 /* process all the same items cleared in a function level reset */ 7388 igb_vf_reset(adapter, vf); 7389 7390 /* set vf mac address */ 7391 igb_set_vf_mac(adapter, vf, vf_mac); 7392 7393 /* enable transmit and receive for vf */ 7394 reg = rd32(E1000_VFTE); 7395 wr32(E1000_VFTE, reg | BIT(vf)); 7396 reg = rd32(E1000_VFRE); 7397 wr32(E1000_VFRE, reg | BIT(vf)); 7398 7399 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7400 7401 /* reply to reset with ack and vf mac address */ 7402 if (!is_zero_ether_addr(vf_mac)) { 7403 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7404 memcpy(addr, vf_mac, ETH_ALEN); 7405 } else { 7406 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7407 } 7408 igb_write_mbx(hw, msgbuf, 3, vf); 7409 } 7410 7411 static void igb_flush_mac_table(struct igb_adapter *adapter) 7412 { 7413 struct e1000_hw *hw = &adapter->hw; 7414 int i; 7415 7416 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7417 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7418 eth_zero_addr(adapter->mac_table[i].addr); 7419 adapter->mac_table[i].queue = 0; 7420 igb_rar_set_index(adapter, i); 7421 } 7422 } 7423 7424 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7425 { 7426 struct e1000_hw *hw = &adapter->hw; 7427 /* do not count rar entries reserved for VFs MAC addresses */ 7428 int rar_entries = hw->mac.rar_entry_count - 7429 adapter->vfs_allocated_count; 7430 int i, count = 0; 7431 7432 for (i = 0; i < rar_entries; i++) { 7433 /* do not count default entries */ 7434 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7435 continue; 7436 7437 /* do not count "in use" entries for different queues */ 7438 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7439 (adapter->mac_table[i].queue != queue)) 7440 continue; 7441 7442 count++; 7443 } 7444 7445 return count; 7446 } 7447 7448 /* Set default MAC address for the PF in the first RAR entry */ 7449 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7450 { 7451 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7452 7453 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7454 mac_table->queue = adapter->vfs_allocated_count; 7455 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7456 7457 igb_rar_set_index(adapter, 0); 7458 } 7459 7460 /* If the filter to be added and an already existing filter express 7461 * the same address and address type, it should be possible to only 7462 * override the other configurations, for example the queue to steer 7463 * traffic. 7464 */ 7465 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7466 const u8 *addr, const u8 flags) 7467 { 7468 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7469 return true; 7470 7471 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7472 (flags & IGB_MAC_STATE_SRC_ADDR)) 7473 return false; 7474 7475 if (!ether_addr_equal(addr, entry->addr)) 7476 return false; 7477 7478 return true; 7479 } 7480 7481 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7482 * 'flags' is used to indicate what kind of match is made, match is by 7483 * default for the destination address, if matching by source address 7484 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7485 */ 7486 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7487 const u8 *addr, const u8 queue, 7488 const u8 flags) 7489 { 7490 struct e1000_hw *hw = &adapter->hw; 7491 int rar_entries = hw->mac.rar_entry_count - 7492 adapter->vfs_allocated_count; 7493 int i; 7494 7495 if (is_zero_ether_addr(addr)) 7496 return -EINVAL; 7497 7498 /* Search for the first empty entry in the MAC table. 7499 * Do not touch entries at the end of the table reserved for the VF MAC 7500 * addresses. 7501 */ 7502 for (i = 0; i < rar_entries; i++) { 7503 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7504 addr, flags)) 7505 continue; 7506 7507 ether_addr_copy(adapter->mac_table[i].addr, addr); 7508 adapter->mac_table[i].queue = queue; 7509 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7510 7511 igb_rar_set_index(adapter, i); 7512 return i; 7513 } 7514 7515 return -ENOSPC; 7516 } 7517 7518 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7519 const u8 queue) 7520 { 7521 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7522 } 7523 7524 /* Remove a MAC filter for 'addr' directing matching traffic to 7525 * 'queue', 'flags' is used to indicate what kind of match need to be 7526 * removed, match is by default for the destination address, if 7527 * matching by source address is to be removed the flag 7528 * IGB_MAC_STATE_SRC_ADDR can be used. 7529 */ 7530 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7531 const u8 *addr, const u8 queue, 7532 const u8 flags) 7533 { 7534 struct e1000_hw *hw = &adapter->hw; 7535 int rar_entries = hw->mac.rar_entry_count - 7536 adapter->vfs_allocated_count; 7537 int i; 7538 7539 if (is_zero_ether_addr(addr)) 7540 return -EINVAL; 7541 7542 /* Search for matching entry in the MAC table based on given address 7543 * and queue. Do not touch entries at the end of the table reserved 7544 * for the VF MAC addresses. 7545 */ 7546 for (i = 0; i < rar_entries; i++) { 7547 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7548 continue; 7549 if ((adapter->mac_table[i].state & flags) != flags) 7550 continue; 7551 if (adapter->mac_table[i].queue != queue) 7552 continue; 7553 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7554 continue; 7555 7556 /* When a filter for the default address is "deleted", 7557 * we return it to its initial configuration 7558 */ 7559 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7560 adapter->mac_table[i].state = 7561 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7562 adapter->mac_table[i].queue = 7563 adapter->vfs_allocated_count; 7564 } else { 7565 adapter->mac_table[i].state = 0; 7566 adapter->mac_table[i].queue = 0; 7567 eth_zero_addr(adapter->mac_table[i].addr); 7568 } 7569 7570 igb_rar_set_index(adapter, i); 7571 return 0; 7572 } 7573 7574 return -ENOENT; 7575 } 7576 7577 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7578 const u8 queue) 7579 { 7580 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7581 } 7582 7583 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7584 const u8 *addr, u8 queue, u8 flags) 7585 { 7586 struct e1000_hw *hw = &adapter->hw; 7587 7588 /* In theory, this should be supported on 82575 as well, but 7589 * that part wasn't easily accessible during development. 7590 */ 7591 if (hw->mac.type != e1000_i210) 7592 return -EOPNOTSUPP; 7593 7594 return igb_add_mac_filter_flags(adapter, addr, queue, 7595 IGB_MAC_STATE_QUEUE_STEERING | flags); 7596 } 7597 7598 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7599 const u8 *addr, u8 queue, u8 flags) 7600 { 7601 return igb_del_mac_filter_flags(adapter, addr, queue, 7602 IGB_MAC_STATE_QUEUE_STEERING | flags); 7603 } 7604 7605 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7606 { 7607 struct igb_adapter *adapter = netdev_priv(netdev); 7608 int ret; 7609 7610 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7611 7612 return min_t(int, ret, 0); 7613 } 7614 7615 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7616 { 7617 struct igb_adapter *adapter = netdev_priv(netdev); 7618 7619 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7620 7621 return 0; 7622 } 7623 7624 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7625 const u32 info, const u8 *addr) 7626 { 7627 struct pci_dev *pdev = adapter->pdev; 7628 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7629 struct list_head *pos; 7630 struct vf_mac_filter *entry = NULL; 7631 int ret = 0; 7632 7633 switch (info) { 7634 case E1000_VF_MAC_FILTER_CLR: 7635 /* remove all unicast MAC filters related to the current VF */ 7636 list_for_each(pos, &adapter->vf_macs.l) { 7637 entry = list_entry(pos, struct vf_mac_filter, l); 7638 if (entry->vf == vf) { 7639 entry->vf = -1; 7640 entry->free = true; 7641 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7642 } 7643 } 7644 break; 7645 case E1000_VF_MAC_FILTER_ADD: 7646 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7647 !vf_data->trusted) { 7648 dev_warn(&pdev->dev, 7649 "VF %d requested MAC filter but is administratively denied\n", 7650 vf); 7651 return -EINVAL; 7652 } 7653 if (!is_valid_ether_addr(addr)) { 7654 dev_warn(&pdev->dev, 7655 "VF %d attempted to set invalid MAC filter\n", 7656 vf); 7657 return -EINVAL; 7658 } 7659 7660 /* try to find empty slot in the list */ 7661 list_for_each(pos, &adapter->vf_macs.l) { 7662 entry = list_entry(pos, struct vf_mac_filter, l); 7663 if (entry->free) 7664 break; 7665 } 7666 7667 if (entry && entry->free) { 7668 entry->free = false; 7669 entry->vf = vf; 7670 ether_addr_copy(entry->vf_mac, addr); 7671 7672 ret = igb_add_mac_filter(adapter, addr, vf); 7673 ret = min_t(int, ret, 0); 7674 } else { 7675 ret = -ENOSPC; 7676 } 7677 7678 if (ret == -ENOSPC) 7679 dev_warn(&pdev->dev, 7680 "VF %d has requested MAC filter but there is no space for it\n", 7681 vf); 7682 break; 7683 default: 7684 ret = -EINVAL; 7685 break; 7686 } 7687 7688 return ret; 7689 } 7690 7691 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7692 { 7693 struct pci_dev *pdev = adapter->pdev; 7694 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7695 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7696 7697 /* The VF MAC Address is stored in a packed array of bytes 7698 * starting at the second 32 bit word of the msg array 7699 */ 7700 unsigned char *addr = (unsigned char *)&msg[1]; 7701 int ret = 0; 7702 7703 if (!info) { 7704 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7705 !vf_data->trusted) { 7706 dev_warn(&pdev->dev, 7707 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7708 vf); 7709 return -EINVAL; 7710 } 7711 7712 if (!is_valid_ether_addr(addr)) { 7713 dev_warn(&pdev->dev, 7714 "VF %d attempted to set invalid MAC\n", 7715 vf); 7716 return -EINVAL; 7717 } 7718 7719 ret = igb_set_vf_mac(adapter, vf, addr); 7720 } else { 7721 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7722 } 7723 7724 return ret; 7725 } 7726 7727 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7728 { 7729 struct e1000_hw *hw = &adapter->hw; 7730 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7731 u32 msg = E1000_VT_MSGTYPE_NACK; 7732 7733 /* if device isn't clear to send it shouldn't be reading either */ 7734 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7735 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7736 igb_write_mbx(hw, &msg, 1, vf); 7737 vf_data->last_nack = jiffies; 7738 } 7739 } 7740 7741 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7742 { 7743 struct pci_dev *pdev = adapter->pdev; 7744 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7745 struct e1000_hw *hw = &adapter->hw; 7746 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7747 s32 retval; 7748 7749 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7750 7751 if (retval) { 7752 /* if receive failed revoke VF CTS stats and restart init */ 7753 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7754 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7755 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7756 goto unlock; 7757 goto out; 7758 } 7759 7760 /* this is a message we already processed, do nothing */ 7761 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7762 goto unlock; 7763 7764 /* until the vf completes a reset it should not be 7765 * allowed to start any configuration. 7766 */ 7767 if (msgbuf[0] == E1000_VF_RESET) { 7768 /* unlocks mailbox */ 7769 igb_vf_reset_msg(adapter, vf); 7770 return; 7771 } 7772 7773 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7774 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7775 goto unlock; 7776 retval = -1; 7777 goto out; 7778 } 7779 7780 switch ((msgbuf[0] & 0xFFFF)) { 7781 case E1000_VF_SET_MAC_ADDR: 7782 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7783 break; 7784 case E1000_VF_SET_PROMISC: 7785 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7786 break; 7787 case E1000_VF_SET_MULTICAST: 7788 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7789 break; 7790 case E1000_VF_SET_LPE: 7791 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7792 break; 7793 case E1000_VF_SET_VLAN: 7794 retval = -1; 7795 if (vf_data->pf_vlan) 7796 dev_warn(&pdev->dev, 7797 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7798 vf); 7799 else 7800 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7801 break; 7802 default: 7803 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7804 retval = -1; 7805 break; 7806 } 7807 7808 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7809 out: 7810 /* notify the VF of the results of what it sent us */ 7811 if (retval) 7812 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7813 else 7814 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7815 7816 /* unlocks mailbox */ 7817 igb_write_mbx(hw, msgbuf, 1, vf); 7818 return; 7819 7820 unlock: 7821 igb_unlock_mbx(hw, vf); 7822 } 7823 7824 static void igb_msg_task(struct igb_adapter *adapter) 7825 { 7826 struct e1000_hw *hw = &adapter->hw; 7827 u32 vf; 7828 7829 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7830 /* process any reset requests */ 7831 if (!igb_check_for_rst(hw, vf)) 7832 igb_vf_reset_event(adapter, vf); 7833 7834 /* process any messages pending */ 7835 if (!igb_check_for_msg(hw, vf)) 7836 igb_rcv_msg_from_vf(adapter, vf); 7837 7838 /* process any acks */ 7839 if (!igb_check_for_ack(hw, vf)) 7840 igb_rcv_ack_from_vf(adapter, vf); 7841 } 7842 } 7843 7844 /** 7845 * igb_set_uta - Set unicast filter table address 7846 * @adapter: board private structure 7847 * @set: boolean indicating if we are setting or clearing bits 7848 * 7849 * The unicast table address is a register array of 32-bit registers. 7850 * The table is meant to be used in a way similar to how the MTA is used 7851 * however due to certain limitations in the hardware it is necessary to 7852 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7853 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7854 **/ 7855 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7856 { 7857 struct e1000_hw *hw = &adapter->hw; 7858 u32 uta = set ? ~0 : 0; 7859 int i; 7860 7861 /* we only need to do this if VMDq is enabled */ 7862 if (!adapter->vfs_allocated_count) 7863 return; 7864 7865 for (i = hw->mac.uta_reg_count; i--;) 7866 array_wr32(E1000_UTA, i, uta); 7867 } 7868 7869 /** 7870 * igb_intr_msi - Interrupt Handler 7871 * @irq: interrupt number 7872 * @data: pointer to a network interface device structure 7873 **/ 7874 static irqreturn_t igb_intr_msi(int irq, void *data) 7875 { 7876 struct igb_adapter *adapter = data; 7877 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7878 struct e1000_hw *hw = &adapter->hw; 7879 /* read ICR disables interrupts using IAM */ 7880 u32 icr = rd32(E1000_ICR); 7881 7882 igb_write_itr(q_vector); 7883 7884 if (icr & E1000_ICR_DRSTA) 7885 schedule_work(&adapter->reset_task); 7886 7887 if (icr & E1000_ICR_DOUTSYNC) { 7888 /* HW is reporting DMA is out of sync */ 7889 adapter->stats.doosync++; 7890 } 7891 7892 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7893 hw->mac.get_link_status = 1; 7894 if (!test_bit(__IGB_DOWN, &adapter->state)) 7895 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7896 } 7897 7898 if (icr & E1000_ICR_TS) 7899 igb_tsync_interrupt(adapter); 7900 7901 napi_schedule(&q_vector->napi); 7902 7903 return IRQ_HANDLED; 7904 } 7905 7906 /** 7907 * igb_intr - Legacy Interrupt Handler 7908 * @irq: interrupt number 7909 * @data: pointer to a network interface device structure 7910 **/ 7911 static irqreturn_t igb_intr(int irq, void *data) 7912 { 7913 struct igb_adapter *adapter = data; 7914 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7915 struct e1000_hw *hw = &adapter->hw; 7916 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7917 * need for the IMC write 7918 */ 7919 u32 icr = rd32(E1000_ICR); 7920 7921 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7922 * not set, then the adapter didn't send an interrupt 7923 */ 7924 if (!(icr & E1000_ICR_INT_ASSERTED)) 7925 return IRQ_NONE; 7926 7927 igb_write_itr(q_vector); 7928 7929 if (icr & E1000_ICR_DRSTA) 7930 schedule_work(&adapter->reset_task); 7931 7932 if (icr & E1000_ICR_DOUTSYNC) { 7933 /* HW is reporting DMA is out of sync */ 7934 adapter->stats.doosync++; 7935 } 7936 7937 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7938 hw->mac.get_link_status = 1; 7939 /* guard against interrupt when we're going down */ 7940 if (!test_bit(__IGB_DOWN, &adapter->state)) 7941 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7942 } 7943 7944 if (icr & E1000_ICR_TS) 7945 igb_tsync_interrupt(adapter); 7946 7947 napi_schedule(&q_vector->napi); 7948 7949 return IRQ_HANDLED; 7950 } 7951 7952 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7953 { 7954 struct igb_adapter *adapter = q_vector->adapter; 7955 struct e1000_hw *hw = &adapter->hw; 7956 7957 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7958 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7959 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7960 igb_set_itr(q_vector); 7961 else 7962 igb_update_ring_itr(q_vector); 7963 } 7964 7965 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7966 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7967 wr32(E1000_EIMS, q_vector->eims_value); 7968 else 7969 igb_irq_enable(adapter); 7970 } 7971 } 7972 7973 /** 7974 * igb_poll - NAPI Rx polling callback 7975 * @napi: napi polling structure 7976 * @budget: count of how many packets we should handle 7977 **/ 7978 static int igb_poll(struct napi_struct *napi, int budget) 7979 { 7980 struct igb_q_vector *q_vector = container_of(napi, 7981 struct igb_q_vector, 7982 napi); 7983 bool clean_complete = true; 7984 int work_done = 0; 7985 7986 #ifdef CONFIG_IGB_DCA 7987 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7988 igb_update_dca(q_vector); 7989 #endif 7990 if (q_vector->tx.ring) 7991 clean_complete = igb_clean_tx_irq(q_vector, budget); 7992 7993 if (q_vector->rx.ring) { 7994 int cleaned = igb_clean_rx_irq(q_vector, budget); 7995 7996 work_done += cleaned; 7997 if (cleaned >= budget) 7998 clean_complete = false; 7999 } 8000 8001 /* If all work not completed, return budget and keep polling */ 8002 if (!clean_complete) 8003 return budget; 8004 8005 /* Exit the polling mode, but don't re-enable interrupts if stack might 8006 * poll us due to busy-polling 8007 */ 8008 if (likely(napi_complete_done(napi, work_done))) 8009 igb_ring_irq_enable(q_vector); 8010 8011 return min(work_done, budget - 1); 8012 } 8013 8014 /** 8015 * igb_clean_tx_irq - Reclaim resources after transmit completes 8016 * @q_vector: pointer to q_vector containing needed info 8017 * @napi_budget: Used to determine if we are in netpoll 8018 * 8019 * returns true if ring is completely cleaned 8020 **/ 8021 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8022 { 8023 struct igb_adapter *adapter = q_vector->adapter; 8024 struct igb_ring *tx_ring = q_vector->tx.ring; 8025 struct igb_tx_buffer *tx_buffer; 8026 union e1000_adv_tx_desc *tx_desc; 8027 unsigned int total_bytes = 0, total_packets = 0; 8028 unsigned int budget = q_vector->tx.work_limit; 8029 unsigned int i = tx_ring->next_to_clean; 8030 8031 if (test_bit(__IGB_DOWN, &adapter->state)) 8032 return true; 8033 8034 tx_buffer = &tx_ring->tx_buffer_info[i]; 8035 tx_desc = IGB_TX_DESC(tx_ring, i); 8036 i -= tx_ring->count; 8037 8038 do { 8039 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8040 8041 /* if next_to_watch is not set then there is no work pending */ 8042 if (!eop_desc) 8043 break; 8044 8045 /* prevent any other reads prior to eop_desc */ 8046 smp_rmb(); 8047 8048 /* if DD is not set pending work has not been completed */ 8049 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8050 break; 8051 8052 /* clear next_to_watch to prevent false hangs */ 8053 tx_buffer->next_to_watch = NULL; 8054 8055 /* update the statistics for this packet */ 8056 total_bytes += tx_buffer->bytecount; 8057 total_packets += tx_buffer->gso_segs; 8058 8059 /* free the skb */ 8060 if (tx_buffer->type == IGB_TYPE_SKB) 8061 napi_consume_skb(tx_buffer->skb, napi_budget); 8062 else 8063 xdp_return_frame(tx_buffer->xdpf); 8064 8065 /* unmap skb header data */ 8066 dma_unmap_single(tx_ring->dev, 8067 dma_unmap_addr(tx_buffer, dma), 8068 dma_unmap_len(tx_buffer, len), 8069 DMA_TO_DEVICE); 8070 8071 /* clear tx_buffer data */ 8072 dma_unmap_len_set(tx_buffer, len, 0); 8073 8074 /* clear last DMA location and unmap remaining buffers */ 8075 while (tx_desc != eop_desc) { 8076 tx_buffer++; 8077 tx_desc++; 8078 i++; 8079 if (unlikely(!i)) { 8080 i -= tx_ring->count; 8081 tx_buffer = tx_ring->tx_buffer_info; 8082 tx_desc = IGB_TX_DESC(tx_ring, 0); 8083 } 8084 8085 /* unmap any remaining paged data */ 8086 if (dma_unmap_len(tx_buffer, len)) { 8087 dma_unmap_page(tx_ring->dev, 8088 dma_unmap_addr(tx_buffer, dma), 8089 dma_unmap_len(tx_buffer, len), 8090 DMA_TO_DEVICE); 8091 dma_unmap_len_set(tx_buffer, len, 0); 8092 } 8093 } 8094 8095 /* move us one more past the eop_desc for start of next pkt */ 8096 tx_buffer++; 8097 tx_desc++; 8098 i++; 8099 if (unlikely(!i)) { 8100 i -= tx_ring->count; 8101 tx_buffer = tx_ring->tx_buffer_info; 8102 tx_desc = IGB_TX_DESC(tx_ring, 0); 8103 } 8104 8105 /* issue prefetch for next Tx descriptor */ 8106 prefetch(tx_desc); 8107 8108 /* update budget accounting */ 8109 budget--; 8110 } while (likely(budget)); 8111 8112 netdev_tx_completed_queue(txring_txq(tx_ring), 8113 total_packets, total_bytes); 8114 i += tx_ring->count; 8115 tx_ring->next_to_clean = i; 8116 u64_stats_update_begin(&tx_ring->tx_syncp); 8117 tx_ring->tx_stats.bytes += total_bytes; 8118 tx_ring->tx_stats.packets += total_packets; 8119 u64_stats_update_end(&tx_ring->tx_syncp); 8120 q_vector->tx.total_bytes += total_bytes; 8121 q_vector->tx.total_packets += total_packets; 8122 8123 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8124 struct e1000_hw *hw = &adapter->hw; 8125 8126 /* Detect a transmit hang in hardware, this serializes the 8127 * check with the clearing of time_stamp and movement of i 8128 */ 8129 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8130 if (tx_buffer->next_to_watch && 8131 time_after(jiffies, tx_buffer->time_stamp + 8132 (adapter->tx_timeout_factor * HZ)) && 8133 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8134 8135 /* detected Tx unit hang */ 8136 dev_err(tx_ring->dev, 8137 "Detected Tx Unit Hang\n" 8138 " Tx Queue <%d>\n" 8139 " TDH <%x>\n" 8140 " TDT <%x>\n" 8141 " next_to_use <%x>\n" 8142 " next_to_clean <%x>\n" 8143 "buffer_info[next_to_clean]\n" 8144 " time_stamp <%lx>\n" 8145 " next_to_watch <%p>\n" 8146 " jiffies <%lx>\n" 8147 " desc.status <%x>\n", 8148 tx_ring->queue_index, 8149 rd32(E1000_TDH(tx_ring->reg_idx)), 8150 readl(tx_ring->tail), 8151 tx_ring->next_to_use, 8152 tx_ring->next_to_clean, 8153 tx_buffer->time_stamp, 8154 tx_buffer->next_to_watch, 8155 jiffies, 8156 tx_buffer->next_to_watch->wb.status); 8157 netif_stop_subqueue(tx_ring->netdev, 8158 tx_ring->queue_index); 8159 8160 /* we are about to reset, no point in enabling stuff */ 8161 return true; 8162 } 8163 } 8164 8165 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8166 if (unlikely(total_packets && 8167 netif_carrier_ok(tx_ring->netdev) && 8168 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8169 /* Make sure that anybody stopping the queue after this 8170 * sees the new next_to_clean. 8171 */ 8172 smp_mb(); 8173 if (__netif_subqueue_stopped(tx_ring->netdev, 8174 tx_ring->queue_index) && 8175 !(test_bit(__IGB_DOWN, &adapter->state))) { 8176 netif_wake_subqueue(tx_ring->netdev, 8177 tx_ring->queue_index); 8178 8179 u64_stats_update_begin(&tx_ring->tx_syncp); 8180 tx_ring->tx_stats.restart_queue++; 8181 u64_stats_update_end(&tx_ring->tx_syncp); 8182 } 8183 } 8184 8185 return !!budget; 8186 } 8187 8188 /** 8189 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8190 * @rx_ring: rx descriptor ring to store buffers on 8191 * @old_buff: donor buffer to have page reused 8192 * 8193 * Synchronizes page for reuse by the adapter 8194 **/ 8195 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8196 struct igb_rx_buffer *old_buff) 8197 { 8198 struct igb_rx_buffer *new_buff; 8199 u16 nta = rx_ring->next_to_alloc; 8200 8201 new_buff = &rx_ring->rx_buffer_info[nta]; 8202 8203 /* update, and store next to alloc */ 8204 nta++; 8205 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8206 8207 /* Transfer page from old buffer to new buffer. 8208 * Move each member individually to avoid possible store 8209 * forwarding stalls. 8210 */ 8211 new_buff->dma = old_buff->dma; 8212 new_buff->page = old_buff->page; 8213 new_buff->page_offset = old_buff->page_offset; 8214 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8215 } 8216 8217 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8218 int rx_buf_pgcnt) 8219 { 8220 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8221 struct page *page = rx_buffer->page; 8222 8223 /* avoid re-using remote and pfmemalloc pages */ 8224 if (!dev_page_is_reusable(page)) 8225 return false; 8226 8227 #if (PAGE_SIZE < 8192) 8228 /* if we are only owner of page we can reuse it */ 8229 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8230 return false; 8231 #else 8232 #define IGB_LAST_OFFSET \ 8233 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8234 8235 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8236 return false; 8237 #endif 8238 8239 /* If we have drained the page fragment pool we need to update 8240 * the pagecnt_bias and page count so that we fully restock the 8241 * number of references the driver holds. 8242 */ 8243 if (unlikely(pagecnt_bias == 1)) { 8244 page_ref_add(page, USHRT_MAX - 1); 8245 rx_buffer->pagecnt_bias = USHRT_MAX; 8246 } 8247 8248 return true; 8249 } 8250 8251 /** 8252 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8253 * @rx_ring: rx descriptor ring to transact packets on 8254 * @rx_buffer: buffer containing page to add 8255 * @skb: sk_buff to place the data into 8256 * @size: size of buffer to be added 8257 * 8258 * This function will add the data contained in rx_buffer->page to the skb. 8259 **/ 8260 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8261 struct igb_rx_buffer *rx_buffer, 8262 struct sk_buff *skb, 8263 unsigned int size) 8264 { 8265 #if (PAGE_SIZE < 8192) 8266 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8267 #else 8268 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8269 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8270 SKB_DATA_ALIGN(size); 8271 #endif 8272 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8273 rx_buffer->page_offset, size, truesize); 8274 #if (PAGE_SIZE < 8192) 8275 rx_buffer->page_offset ^= truesize; 8276 #else 8277 rx_buffer->page_offset += truesize; 8278 #endif 8279 } 8280 8281 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8282 struct igb_rx_buffer *rx_buffer, 8283 struct xdp_buff *xdp, 8284 union e1000_adv_rx_desc *rx_desc) 8285 { 8286 #if (PAGE_SIZE < 8192) 8287 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8288 #else 8289 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8290 xdp->data_hard_start); 8291 #endif 8292 unsigned int size = xdp->data_end - xdp->data; 8293 unsigned int headlen; 8294 struct sk_buff *skb; 8295 8296 /* prefetch first cache line of first page */ 8297 net_prefetch(xdp->data); 8298 8299 /* allocate a skb to store the frags */ 8300 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8301 if (unlikely(!skb)) 8302 return NULL; 8303 8304 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8305 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, xdp->data, skb)) { 8306 xdp->data += IGB_TS_HDR_LEN; 8307 size -= IGB_TS_HDR_LEN; 8308 } 8309 } 8310 8311 /* Determine available headroom for copy */ 8312 headlen = size; 8313 if (headlen > IGB_RX_HDR_LEN) 8314 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8315 8316 /* align pull length to size of long to optimize memcpy performance */ 8317 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8318 8319 /* update all of the pointers */ 8320 size -= headlen; 8321 if (size) { 8322 skb_add_rx_frag(skb, 0, rx_buffer->page, 8323 (xdp->data + headlen) - page_address(rx_buffer->page), 8324 size, truesize); 8325 #if (PAGE_SIZE < 8192) 8326 rx_buffer->page_offset ^= truesize; 8327 #else 8328 rx_buffer->page_offset += truesize; 8329 #endif 8330 } else { 8331 rx_buffer->pagecnt_bias++; 8332 } 8333 8334 return skb; 8335 } 8336 8337 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8338 struct igb_rx_buffer *rx_buffer, 8339 struct xdp_buff *xdp, 8340 union e1000_adv_rx_desc *rx_desc) 8341 { 8342 #if (PAGE_SIZE < 8192) 8343 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8344 #else 8345 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8346 SKB_DATA_ALIGN(xdp->data_end - 8347 xdp->data_hard_start); 8348 #endif 8349 unsigned int metasize = xdp->data - xdp->data_meta; 8350 struct sk_buff *skb; 8351 8352 /* prefetch first cache line of first page */ 8353 net_prefetch(xdp->data_meta); 8354 8355 /* build an skb around the page buffer */ 8356 skb = build_skb(xdp->data_hard_start, truesize); 8357 if (unlikely(!skb)) 8358 return NULL; 8359 8360 /* update pointers within the skb to store the data */ 8361 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8362 __skb_put(skb, xdp->data_end - xdp->data); 8363 8364 if (metasize) 8365 skb_metadata_set(skb, metasize); 8366 8367 /* pull timestamp out of packet data */ 8368 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8369 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb)) 8370 __skb_pull(skb, IGB_TS_HDR_LEN); 8371 } 8372 8373 /* update buffer offset */ 8374 #if (PAGE_SIZE < 8192) 8375 rx_buffer->page_offset ^= truesize; 8376 #else 8377 rx_buffer->page_offset += truesize; 8378 #endif 8379 8380 return skb; 8381 } 8382 8383 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8384 struct igb_ring *rx_ring, 8385 struct xdp_buff *xdp) 8386 { 8387 int err, result = IGB_XDP_PASS; 8388 struct bpf_prog *xdp_prog; 8389 u32 act; 8390 8391 rcu_read_lock(); 8392 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8393 8394 if (!xdp_prog) 8395 goto xdp_out; 8396 8397 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8398 8399 act = bpf_prog_run_xdp(xdp_prog, xdp); 8400 switch (act) { 8401 case XDP_PASS: 8402 break; 8403 case XDP_TX: 8404 result = igb_xdp_xmit_back(adapter, xdp); 8405 break; 8406 case XDP_REDIRECT: 8407 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8408 if (!err) 8409 result = IGB_XDP_REDIR; 8410 else 8411 result = IGB_XDP_CONSUMED; 8412 break; 8413 default: 8414 bpf_warn_invalid_xdp_action(act); 8415 fallthrough; 8416 case XDP_ABORTED: 8417 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8418 fallthrough; 8419 case XDP_DROP: 8420 result = IGB_XDP_CONSUMED; 8421 break; 8422 } 8423 xdp_out: 8424 rcu_read_unlock(); 8425 return ERR_PTR(-result); 8426 } 8427 8428 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8429 unsigned int size) 8430 { 8431 unsigned int truesize; 8432 8433 #if (PAGE_SIZE < 8192) 8434 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8435 #else 8436 truesize = ring_uses_build_skb(rx_ring) ? 8437 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8438 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8439 SKB_DATA_ALIGN(size); 8440 #endif 8441 return truesize; 8442 } 8443 8444 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8445 struct igb_rx_buffer *rx_buffer, 8446 unsigned int size) 8447 { 8448 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8449 #if (PAGE_SIZE < 8192) 8450 rx_buffer->page_offset ^= truesize; 8451 #else 8452 rx_buffer->page_offset += truesize; 8453 #endif 8454 } 8455 8456 static inline void igb_rx_checksum(struct igb_ring *ring, 8457 union e1000_adv_rx_desc *rx_desc, 8458 struct sk_buff *skb) 8459 { 8460 skb_checksum_none_assert(skb); 8461 8462 /* Ignore Checksum bit is set */ 8463 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8464 return; 8465 8466 /* Rx checksum disabled via ethtool */ 8467 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8468 return; 8469 8470 /* TCP/UDP checksum error bit is set */ 8471 if (igb_test_staterr(rx_desc, 8472 E1000_RXDEXT_STATERR_TCPE | 8473 E1000_RXDEXT_STATERR_IPE)) { 8474 /* work around errata with sctp packets where the TCPE aka 8475 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8476 * packets, (aka let the stack check the crc32c) 8477 */ 8478 if (!((skb->len == 60) && 8479 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8480 u64_stats_update_begin(&ring->rx_syncp); 8481 ring->rx_stats.csum_err++; 8482 u64_stats_update_end(&ring->rx_syncp); 8483 } 8484 /* let the stack verify checksum errors */ 8485 return; 8486 } 8487 /* It must be a TCP or UDP packet with a valid checksum */ 8488 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8489 E1000_RXD_STAT_UDPCS)) 8490 skb->ip_summed = CHECKSUM_UNNECESSARY; 8491 8492 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8493 le32_to_cpu(rx_desc->wb.upper.status_error)); 8494 } 8495 8496 static inline void igb_rx_hash(struct igb_ring *ring, 8497 union e1000_adv_rx_desc *rx_desc, 8498 struct sk_buff *skb) 8499 { 8500 if (ring->netdev->features & NETIF_F_RXHASH) 8501 skb_set_hash(skb, 8502 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8503 PKT_HASH_TYPE_L3); 8504 } 8505 8506 /** 8507 * igb_is_non_eop - process handling of non-EOP buffers 8508 * @rx_ring: Rx ring being processed 8509 * @rx_desc: Rx descriptor for current buffer 8510 * 8511 * This function updates next to clean. If the buffer is an EOP buffer 8512 * this function exits returning false, otherwise it will place the 8513 * sk_buff in the next buffer to be chained and return true indicating 8514 * that this is in fact a non-EOP buffer. 8515 **/ 8516 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8517 union e1000_adv_rx_desc *rx_desc) 8518 { 8519 u32 ntc = rx_ring->next_to_clean + 1; 8520 8521 /* fetch, update, and store next to clean */ 8522 ntc = (ntc < rx_ring->count) ? ntc : 0; 8523 rx_ring->next_to_clean = ntc; 8524 8525 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8526 8527 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8528 return false; 8529 8530 return true; 8531 } 8532 8533 /** 8534 * igb_cleanup_headers - Correct corrupted or empty headers 8535 * @rx_ring: rx descriptor ring packet is being transacted on 8536 * @rx_desc: pointer to the EOP Rx descriptor 8537 * @skb: pointer to current skb being fixed 8538 * 8539 * Address the case where we are pulling data in on pages only 8540 * and as such no data is present in the skb header. 8541 * 8542 * In addition if skb is not at least 60 bytes we need to pad it so that 8543 * it is large enough to qualify as a valid Ethernet frame. 8544 * 8545 * Returns true if an error was encountered and skb was freed. 8546 **/ 8547 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8548 union e1000_adv_rx_desc *rx_desc, 8549 struct sk_buff *skb) 8550 { 8551 /* XDP packets use error pointer so abort at this point */ 8552 if (IS_ERR(skb)) 8553 return true; 8554 8555 if (unlikely((igb_test_staterr(rx_desc, 8556 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8557 struct net_device *netdev = rx_ring->netdev; 8558 if (!(netdev->features & NETIF_F_RXALL)) { 8559 dev_kfree_skb_any(skb); 8560 return true; 8561 } 8562 } 8563 8564 /* if eth_skb_pad returns an error the skb was freed */ 8565 if (eth_skb_pad(skb)) 8566 return true; 8567 8568 return false; 8569 } 8570 8571 /** 8572 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8573 * @rx_ring: rx descriptor ring packet is being transacted on 8574 * @rx_desc: pointer to the EOP Rx descriptor 8575 * @skb: pointer to current skb being populated 8576 * 8577 * This function checks the ring, descriptor, and packet information in 8578 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8579 * other fields within the skb. 8580 **/ 8581 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8582 union e1000_adv_rx_desc *rx_desc, 8583 struct sk_buff *skb) 8584 { 8585 struct net_device *dev = rx_ring->netdev; 8586 8587 igb_rx_hash(rx_ring, rx_desc, skb); 8588 8589 igb_rx_checksum(rx_ring, rx_desc, skb); 8590 8591 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8592 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8593 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8594 8595 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8596 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8597 u16 vid; 8598 8599 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8600 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8601 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8602 else 8603 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8604 8605 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8606 } 8607 8608 skb_record_rx_queue(skb, rx_ring->queue_index); 8609 8610 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8611 } 8612 8613 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8614 { 8615 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8616 } 8617 8618 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8619 const unsigned int size, int *rx_buf_pgcnt) 8620 { 8621 struct igb_rx_buffer *rx_buffer; 8622 8623 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8624 *rx_buf_pgcnt = 8625 #if (PAGE_SIZE < 8192) 8626 page_count(rx_buffer->page); 8627 #else 8628 0; 8629 #endif 8630 prefetchw(rx_buffer->page); 8631 8632 /* we are reusing so sync this buffer for CPU use */ 8633 dma_sync_single_range_for_cpu(rx_ring->dev, 8634 rx_buffer->dma, 8635 rx_buffer->page_offset, 8636 size, 8637 DMA_FROM_DEVICE); 8638 8639 rx_buffer->pagecnt_bias--; 8640 8641 return rx_buffer; 8642 } 8643 8644 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8645 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8646 { 8647 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8648 /* hand second half of page back to the ring */ 8649 igb_reuse_rx_page(rx_ring, rx_buffer); 8650 } else { 8651 /* We are not reusing the buffer so unmap it and free 8652 * any references we are holding to it 8653 */ 8654 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8655 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8656 IGB_RX_DMA_ATTR); 8657 __page_frag_cache_drain(rx_buffer->page, 8658 rx_buffer->pagecnt_bias); 8659 } 8660 8661 /* clear contents of rx_buffer */ 8662 rx_buffer->page = NULL; 8663 } 8664 8665 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8666 { 8667 struct igb_adapter *adapter = q_vector->adapter; 8668 struct igb_ring *rx_ring = q_vector->rx.ring; 8669 struct sk_buff *skb = rx_ring->skb; 8670 unsigned int total_bytes = 0, total_packets = 0; 8671 u16 cleaned_count = igb_desc_unused(rx_ring); 8672 unsigned int xdp_xmit = 0; 8673 struct xdp_buff xdp; 8674 u32 frame_sz = 0; 8675 int rx_buf_pgcnt; 8676 8677 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8678 #if (PAGE_SIZE < 8192) 8679 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8680 #endif 8681 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8682 8683 while (likely(total_packets < budget)) { 8684 union e1000_adv_rx_desc *rx_desc; 8685 struct igb_rx_buffer *rx_buffer; 8686 unsigned int size; 8687 8688 /* return some buffers to hardware, one at a time is too slow */ 8689 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8690 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8691 cleaned_count = 0; 8692 } 8693 8694 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8695 size = le16_to_cpu(rx_desc->wb.upper.length); 8696 if (!size) 8697 break; 8698 8699 /* This memory barrier is needed to keep us from reading 8700 * any other fields out of the rx_desc until we know the 8701 * descriptor has been written back 8702 */ 8703 dma_rmb(); 8704 8705 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8706 8707 /* retrieve a buffer from the ring */ 8708 if (!skb) { 8709 unsigned int offset = igb_rx_offset(rx_ring); 8710 unsigned char *hard_start; 8711 8712 hard_start = page_address(rx_buffer->page) + 8713 rx_buffer->page_offset - offset; 8714 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8715 #if (PAGE_SIZE > 4096) 8716 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8717 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8718 #endif 8719 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8720 } 8721 8722 if (IS_ERR(skb)) { 8723 unsigned int xdp_res = -PTR_ERR(skb); 8724 8725 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8726 xdp_xmit |= xdp_res; 8727 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8728 } else { 8729 rx_buffer->pagecnt_bias++; 8730 } 8731 total_packets++; 8732 total_bytes += size; 8733 } else if (skb) 8734 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8735 else if (ring_uses_build_skb(rx_ring)) 8736 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, rx_desc); 8737 else 8738 skb = igb_construct_skb(rx_ring, rx_buffer, 8739 &xdp, rx_desc); 8740 8741 /* exit if we failed to retrieve a buffer */ 8742 if (!skb) { 8743 rx_ring->rx_stats.alloc_failed++; 8744 rx_buffer->pagecnt_bias++; 8745 break; 8746 } 8747 8748 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8749 cleaned_count++; 8750 8751 /* fetch next buffer in frame if non-eop */ 8752 if (igb_is_non_eop(rx_ring, rx_desc)) 8753 continue; 8754 8755 /* verify the packet layout is correct */ 8756 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8757 skb = NULL; 8758 continue; 8759 } 8760 8761 /* probably a little skewed due to removing CRC */ 8762 total_bytes += skb->len; 8763 8764 /* populate checksum, timestamp, VLAN, and protocol */ 8765 igb_process_skb_fields(rx_ring, rx_desc, skb); 8766 8767 napi_gro_receive(&q_vector->napi, skb); 8768 8769 /* reset skb pointer */ 8770 skb = NULL; 8771 8772 /* update budget accounting */ 8773 total_packets++; 8774 } 8775 8776 /* place incomplete frames back on ring for completion */ 8777 rx_ring->skb = skb; 8778 8779 if (xdp_xmit & IGB_XDP_REDIR) 8780 xdp_do_flush(); 8781 8782 if (xdp_xmit & IGB_XDP_TX) { 8783 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8784 8785 igb_xdp_ring_update_tail(tx_ring); 8786 } 8787 8788 u64_stats_update_begin(&rx_ring->rx_syncp); 8789 rx_ring->rx_stats.packets += total_packets; 8790 rx_ring->rx_stats.bytes += total_bytes; 8791 u64_stats_update_end(&rx_ring->rx_syncp); 8792 q_vector->rx.total_packets += total_packets; 8793 q_vector->rx.total_bytes += total_bytes; 8794 8795 if (cleaned_count) 8796 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8797 8798 return total_packets; 8799 } 8800 8801 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8802 struct igb_rx_buffer *bi) 8803 { 8804 struct page *page = bi->page; 8805 dma_addr_t dma; 8806 8807 /* since we are recycling buffers we should seldom need to alloc */ 8808 if (likely(page)) 8809 return true; 8810 8811 /* alloc new page for storage */ 8812 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8813 if (unlikely(!page)) { 8814 rx_ring->rx_stats.alloc_failed++; 8815 return false; 8816 } 8817 8818 /* map page for use */ 8819 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8820 igb_rx_pg_size(rx_ring), 8821 DMA_FROM_DEVICE, 8822 IGB_RX_DMA_ATTR); 8823 8824 /* if mapping failed free memory back to system since 8825 * there isn't much point in holding memory we can't use 8826 */ 8827 if (dma_mapping_error(rx_ring->dev, dma)) { 8828 __free_pages(page, igb_rx_pg_order(rx_ring)); 8829 8830 rx_ring->rx_stats.alloc_failed++; 8831 return false; 8832 } 8833 8834 bi->dma = dma; 8835 bi->page = page; 8836 bi->page_offset = igb_rx_offset(rx_ring); 8837 page_ref_add(page, USHRT_MAX - 1); 8838 bi->pagecnt_bias = USHRT_MAX; 8839 8840 return true; 8841 } 8842 8843 /** 8844 * igb_alloc_rx_buffers - Replace used receive buffers 8845 * @rx_ring: rx descriptor ring to allocate new receive buffers 8846 * @cleaned_count: count of buffers to allocate 8847 **/ 8848 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8849 { 8850 union e1000_adv_rx_desc *rx_desc; 8851 struct igb_rx_buffer *bi; 8852 u16 i = rx_ring->next_to_use; 8853 u16 bufsz; 8854 8855 /* nothing to do */ 8856 if (!cleaned_count) 8857 return; 8858 8859 rx_desc = IGB_RX_DESC(rx_ring, i); 8860 bi = &rx_ring->rx_buffer_info[i]; 8861 i -= rx_ring->count; 8862 8863 bufsz = igb_rx_bufsz(rx_ring); 8864 8865 do { 8866 if (!igb_alloc_mapped_page(rx_ring, bi)) 8867 break; 8868 8869 /* sync the buffer for use by the device */ 8870 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8871 bi->page_offset, bufsz, 8872 DMA_FROM_DEVICE); 8873 8874 /* Refresh the desc even if buffer_addrs didn't change 8875 * because each write-back erases this info. 8876 */ 8877 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8878 8879 rx_desc++; 8880 bi++; 8881 i++; 8882 if (unlikely(!i)) { 8883 rx_desc = IGB_RX_DESC(rx_ring, 0); 8884 bi = rx_ring->rx_buffer_info; 8885 i -= rx_ring->count; 8886 } 8887 8888 /* clear the length for the next_to_use descriptor */ 8889 rx_desc->wb.upper.length = 0; 8890 8891 cleaned_count--; 8892 } while (cleaned_count); 8893 8894 i += rx_ring->count; 8895 8896 if (rx_ring->next_to_use != i) { 8897 /* record the next descriptor to use */ 8898 rx_ring->next_to_use = i; 8899 8900 /* update next to alloc since we have filled the ring */ 8901 rx_ring->next_to_alloc = i; 8902 8903 /* Force memory writes to complete before letting h/w 8904 * know there are new descriptors to fetch. (Only 8905 * applicable for weak-ordered memory model archs, 8906 * such as IA-64). 8907 */ 8908 dma_wmb(); 8909 writel(i, rx_ring->tail); 8910 } 8911 } 8912 8913 /** 8914 * igb_mii_ioctl - 8915 * @netdev: pointer to netdev struct 8916 * @ifr: interface structure 8917 * @cmd: ioctl command to execute 8918 **/ 8919 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8920 { 8921 struct igb_adapter *adapter = netdev_priv(netdev); 8922 struct mii_ioctl_data *data = if_mii(ifr); 8923 8924 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8925 return -EOPNOTSUPP; 8926 8927 switch (cmd) { 8928 case SIOCGMIIPHY: 8929 data->phy_id = adapter->hw.phy.addr; 8930 break; 8931 case SIOCGMIIREG: 8932 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8933 &data->val_out)) 8934 return -EIO; 8935 break; 8936 case SIOCSMIIREG: 8937 default: 8938 return -EOPNOTSUPP; 8939 } 8940 return 0; 8941 } 8942 8943 /** 8944 * igb_ioctl - 8945 * @netdev: pointer to netdev struct 8946 * @ifr: interface structure 8947 * @cmd: ioctl command to execute 8948 **/ 8949 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8950 { 8951 switch (cmd) { 8952 case SIOCGMIIPHY: 8953 case SIOCGMIIREG: 8954 case SIOCSMIIREG: 8955 return igb_mii_ioctl(netdev, ifr, cmd); 8956 case SIOCGHWTSTAMP: 8957 return igb_ptp_get_ts_config(netdev, ifr); 8958 case SIOCSHWTSTAMP: 8959 return igb_ptp_set_ts_config(netdev, ifr); 8960 default: 8961 return -EOPNOTSUPP; 8962 } 8963 } 8964 8965 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8966 { 8967 struct igb_adapter *adapter = hw->back; 8968 8969 pci_read_config_word(adapter->pdev, reg, value); 8970 } 8971 8972 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8973 { 8974 struct igb_adapter *adapter = hw->back; 8975 8976 pci_write_config_word(adapter->pdev, reg, *value); 8977 } 8978 8979 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8980 { 8981 struct igb_adapter *adapter = hw->back; 8982 8983 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8984 return -E1000_ERR_CONFIG; 8985 8986 return 0; 8987 } 8988 8989 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8990 { 8991 struct igb_adapter *adapter = hw->back; 8992 8993 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8994 return -E1000_ERR_CONFIG; 8995 8996 return 0; 8997 } 8998 8999 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9000 { 9001 struct igb_adapter *adapter = netdev_priv(netdev); 9002 struct e1000_hw *hw = &adapter->hw; 9003 u32 ctrl, rctl; 9004 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9005 9006 if (enable) { 9007 /* enable VLAN tag insert/strip */ 9008 ctrl = rd32(E1000_CTRL); 9009 ctrl |= E1000_CTRL_VME; 9010 wr32(E1000_CTRL, ctrl); 9011 9012 /* Disable CFI check */ 9013 rctl = rd32(E1000_RCTL); 9014 rctl &= ~E1000_RCTL_CFIEN; 9015 wr32(E1000_RCTL, rctl); 9016 } else { 9017 /* disable VLAN tag insert/strip */ 9018 ctrl = rd32(E1000_CTRL); 9019 ctrl &= ~E1000_CTRL_VME; 9020 wr32(E1000_CTRL, ctrl); 9021 } 9022 9023 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9024 } 9025 9026 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9027 __be16 proto, u16 vid) 9028 { 9029 struct igb_adapter *adapter = netdev_priv(netdev); 9030 struct e1000_hw *hw = &adapter->hw; 9031 int pf_id = adapter->vfs_allocated_count; 9032 9033 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9034 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9035 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9036 9037 set_bit(vid, adapter->active_vlans); 9038 9039 return 0; 9040 } 9041 9042 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9043 __be16 proto, u16 vid) 9044 { 9045 struct igb_adapter *adapter = netdev_priv(netdev); 9046 int pf_id = adapter->vfs_allocated_count; 9047 struct e1000_hw *hw = &adapter->hw; 9048 9049 /* remove VID from filter table */ 9050 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9051 igb_vfta_set(hw, vid, pf_id, false, true); 9052 9053 clear_bit(vid, adapter->active_vlans); 9054 9055 return 0; 9056 } 9057 9058 static void igb_restore_vlan(struct igb_adapter *adapter) 9059 { 9060 u16 vid = 1; 9061 9062 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9063 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9064 9065 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9066 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9067 } 9068 9069 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9070 { 9071 struct pci_dev *pdev = adapter->pdev; 9072 struct e1000_mac_info *mac = &adapter->hw.mac; 9073 9074 mac->autoneg = 0; 9075 9076 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9077 * for the switch() below to work 9078 */ 9079 if ((spd & 1) || (dplx & ~1)) 9080 goto err_inval; 9081 9082 /* Fiber NIC's only allow 1000 gbps Full duplex 9083 * and 100Mbps Full duplex for 100baseFx sfp 9084 */ 9085 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9086 switch (spd + dplx) { 9087 case SPEED_10 + DUPLEX_HALF: 9088 case SPEED_10 + DUPLEX_FULL: 9089 case SPEED_100 + DUPLEX_HALF: 9090 goto err_inval; 9091 default: 9092 break; 9093 } 9094 } 9095 9096 switch (spd + dplx) { 9097 case SPEED_10 + DUPLEX_HALF: 9098 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9099 break; 9100 case SPEED_10 + DUPLEX_FULL: 9101 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9102 break; 9103 case SPEED_100 + DUPLEX_HALF: 9104 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9105 break; 9106 case SPEED_100 + DUPLEX_FULL: 9107 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9108 break; 9109 case SPEED_1000 + DUPLEX_FULL: 9110 mac->autoneg = 1; 9111 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9112 break; 9113 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9114 default: 9115 goto err_inval; 9116 } 9117 9118 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9119 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9120 9121 return 0; 9122 9123 err_inval: 9124 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9125 return -EINVAL; 9126 } 9127 9128 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9129 bool runtime) 9130 { 9131 struct net_device *netdev = pci_get_drvdata(pdev); 9132 struct igb_adapter *adapter = netdev_priv(netdev); 9133 struct e1000_hw *hw = &adapter->hw; 9134 u32 ctrl, rctl, status; 9135 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9136 bool wake; 9137 9138 rtnl_lock(); 9139 netif_device_detach(netdev); 9140 9141 if (netif_running(netdev)) 9142 __igb_close(netdev, true); 9143 9144 igb_ptp_suspend(adapter); 9145 9146 igb_clear_interrupt_scheme(adapter); 9147 rtnl_unlock(); 9148 9149 status = rd32(E1000_STATUS); 9150 if (status & E1000_STATUS_LU) 9151 wufc &= ~E1000_WUFC_LNKC; 9152 9153 if (wufc) { 9154 igb_setup_rctl(adapter); 9155 igb_set_rx_mode(netdev); 9156 9157 /* turn on all-multi mode if wake on multicast is enabled */ 9158 if (wufc & E1000_WUFC_MC) { 9159 rctl = rd32(E1000_RCTL); 9160 rctl |= E1000_RCTL_MPE; 9161 wr32(E1000_RCTL, rctl); 9162 } 9163 9164 ctrl = rd32(E1000_CTRL); 9165 ctrl |= E1000_CTRL_ADVD3WUC; 9166 wr32(E1000_CTRL, ctrl); 9167 9168 /* Allow time for pending master requests to run */ 9169 igb_disable_pcie_master(hw); 9170 9171 wr32(E1000_WUC, E1000_WUC_PME_EN); 9172 wr32(E1000_WUFC, wufc); 9173 } else { 9174 wr32(E1000_WUC, 0); 9175 wr32(E1000_WUFC, 0); 9176 } 9177 9178 wake = wufc || adapter->en_mng_pt; 9179 if (!wake) 9180 igb_power_down_link(adapter); 9181 else 9182 igb_power_up_link(adapter); 9183 9184 if (enable_wake) 9185 *enable_wake = wake; 9186 9187 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9188 * would have already happened in close and is redundant. 9189 */ 9190 igb_release_hw_control(adapter); 9191 9192 pci_disable_device(pdev); 9193 9194 return 0; 9195 } 9196 9197 static void igb_deliver_wake_packet(struct net_device *netdev) 9198 { 9199 struct igb_adapter *adapter = netdev_priv(netdev); 9200 struct e1000_hw *hw = &adapter->hw; 9201 struct sk_buff *skb; 9202 u32 wupl; 9203 9204 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9205 9206 /* WUPM stores only the first 128 bytes of the wake packet. 9207 * Read the packet only if we have the whole thing. 9208 */ 9209 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9210 return; 9211 9212 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9213 if (!skb) 9214 return; 9215 9216 skb_put(skb, wupl); 9217 9218 /* Ensure reads are 32-bit aligned */ 9219 wupl = roundup(wupl, 4); 9220 9221 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9222 9223 skb->protocol = eth_type_trans(skb, netdev); 9224 netif_rx(skb); 9225 } 9226 9227 static int __maybe_unused igb_suspend(struct device *dev) 9228 { 9229 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9230 } 9231 9232 static int __maybe_unused igb_resume(struct device *dev) 9233 { 9234 struct pci_dev *pdev = to_pci_dev(dev); 9235 struct net_device *netdev = pci_get_drvdata(pdev); 9236 struct igb_adapter *adapter = netdev_priv(netdev); 9237 struct e1000_hw *hw = &adapter->hw; 9238 u32 err, val; 9239 9240 pci_set_power_state(pdev, PCI_D0); 9241 pci_restore_state(pdev); 9242 pci_save_state(pdev); 9243 9244 if (!pci_device_is_present(pdev)) 9245 return -ENODEV; 9246 err = pci_enable_device_mem(pdev); 9247 if (err) { 9248 dev_err(&pdev->dev, 9249 "igb: Cannot enable PCI device from suspend\n"); 9250 return err; 9251 } 9252 pci_set_master(pdev); 9253 9254 pci_enable_wake(pdev, PCI_D3hot, 0); 9255 pci_enable_wake(pdev, PCI_D3cold, 0); 9256 9257 if (igb_init_interrupt_scheme(adapter, true)) { 9258 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9259 return -ENOMEM; 9260 } 9261 9262 igb_reset(adapter); 9263 9264 /* let the f/w know that the h/w is now under the control of the 9265 * driver. 9266 */ 9267 igb_get_hw_control(adapter); 9268 9269 val = rd32(E1000_WUS); 9270 if (val & WAKE_PKT_WUS) 9271 igb_deliver_wake_packet(netdev); 9272 9273 wr32(E1000_WUS, ~0); 9274 9275 rtnl_lock(); 9276 if (!err && netif_running(netdev)) 9277 err = __igb_open(netdev, true); 9278 9279 if (!err) 9280 netif_device_attach(netdev); 9281 rtnl_unlock(); 9282 9283 return err; 9284 } 9285 9286 static int __maybe_unused igb_runtime_idle(struct device *dev) 9287 { 9288 struct net_device *netdev = dev_get_drvdata(dev); 9289 struct igb_adapter *adapter = netdev_priv(netdev); 9290 9291 if (!igb_has_link(adapter)) 9292 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9293 9294 return -EBUSY; 9295 } 9296 9297 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9298 { 9299 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9300 } 9301 9302 static int __maybe_unused igb_runtime_resume(struct device *dev) 9303 { 9304 return igb_resume(dev); 9305 } 9306 9307 static void igb_shutdown(struct pci_dev *pdev) 9308 { 9309 bool wake; 9310 9311 __igb_shutdown(pdev, &wake, 0); 9312 9313 if (system_state == SYSTEM_POWER_OFF) { 9314 pci_wake_from_d3(pdev, wake); 9315 pci_set_power_state(pdev, PCI_D3hot); 9316 } 9317 } 9318 9319 #ifdef CONFIG_PCI_IOV 9320 static int igb_sriov_reinit(struct pci_dev *dev) 9321 { 9322 struct net_device *netdev = pci_get_drvdata(dev); 9323 struct igb_adapter *adapter = netdev_priv(netdev); 9324 struct pci_dev *pdev = adapter->pdev; 9325 9326 rtnl_lock(); 9327 9328 if (netif_running(netdev)) 9329 igb_close(netdev); 9330 else 9331 igb_reset(adapter); 9332 9333 igb_clear_interrupt_scheme(adapter); 9334 9335 igb_init_queue_configuration(adapter); 9336 9337 if (igb_init_interrupt_scheme(adapter, true)) { 9338 rtnl_unlock(); 9339 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9340 return -ENOMEM; 9341 } 9342 9343 if (netif_running(netdev)) 9344 igb_open(netdev); 9345 9346 rtnl_unlock(); 9347 9348 return 0; 9349 } 9350 9351 static int igb_pci_disable_sriov(struct pci_dev *dev) 9352 { 9353 int err = igb_disable_sriov(dev); 9354 9355 if (!err) 9356 err = igb_sriov_reinit(dev); 9357 9358 return err; 9359 } 9360 9361 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9362 { 9363 int err = igb_enable_sriov(dev, num_vfs); 9364 9365 if (err) 9366 goto out; 9367 9368 err = igb_sriov_reinit(dev); 9369 if (!err) 9370 return num_vfs; 9371 9372 out: 9373 return err; 9374 } 9375 9376 #endif 9377 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9378 { 9379 #ifdef CONFIG_PCI_IOV 9380 if (num_vfs == 0) 9381 return igb_pci_disable_sriov(dev); 9382 else 9383 return igb_pci_enable_sriov(dev, num_vfs); 9384 #endif 9385 return 0; 9386 } 9387 9388 /** 9389 * igb_io_error_detected - called when PCI error is detected 9390 * @pdev: Pointer to PCI device 9391 * @state: The current pci connection state 9392 * 9393 * This function is called after a PCI bus error affecting 9394 * this device has been detected. 9395 **/ 9396 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9397 pci_channel_state_t state) 9398 { 9399 struct net_device *netdev = pci_get_drvdata(pdev); 9400 struct igb_adapter *adapter = netdev_priv(netdev); 9401 9402 netif_device_detach(netdev); 9403 9404 if (state == pci_channel_io_perm_failure) 9405 return PCI_ERS_RESULT_DISCONNECT; 9406 9407 if (netif_running(netdev)) 9408 igb_down(adapter); 9409 pci_disable_device(pdev); 9410 9411 /* Request a slot slot reset. */ 9412 return PCI_ERS_RESULT_NEED_RESET; 9413 } 9414 9415 /** 9416 * igb_io_slot_reset - called after the pci bus has been reset. 9417 * @pdev: Pointer to PCI device 9418 * 9419 * Restart the card from scratch, as if from a cold-boot. Implementation 9420 * resembles the first-half of the igb_resume routine. 9421 **/ 9422 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9423 { 9424 struct net_device *netdev = pci_get_drvdata(pdev); 9425 struct igb_adapter *adapter = netdev_priv(netdev); 9426 struct e1000_hw *hw = &adapter->hw; 9427 pci_ers_result_t result; 9428 9429 if (pci_enable_device_mem(pdev)) { 9430 dev_err(&pdev->dev, 9431 "Cannot re-enable PCI device after reset.\n"); 9432 result = PCI_ERS_RESULT_DISCONNECT; 9433 } else { 9434 pci_set_master(pdev); 9435 pci_restore_state(pdev); 9436 pci_save_state(pdev); 9437 9438 pci_enable_wake(pdev, PCI_D3hot, 0); 9439 pci_enable_wake(pdev, PCI_D3cold, 0); 9440 9441 /* In case of PCI error, adapter lose its HW address 9442 * so we should re-assign it here. 9443 */ 9444 hw->hw_addr = adapter->io_addr; 9445 9446 igb_reset(adapter); 9447 wr32(E1000_WUS, ~0); 9448 result = PCI_ERS_RESULT_RECOVERED; 9449 } 9450 9451 return result; 9452 } 9453 9454 /** 9455 * igb_io_resume - called when traffic can start flowing again. 9456 * @pdev: Pointer to PCI device 9457 * 9458 * This callback is called when the error recovery driver tells us that 9459 * its OK to resume normal operation. Implementation resembles the 9460 * second-half of the igb_resume routine. 9461 */ 9462 static void igb_io_resume(struct pci_dev *pdev) 9463 { 9464 struct net_device *netdev = pci_get_drvdata(pdev); 9465 struct igb_adapter *adapter = netdev_priv(netdev); 9466 9467 if (netif_running(netdev)) { 9468 if (igb_up(adapter)) { 9469 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9470 return; 9471 } 9472 } 9473 9474 netif_device_attach(netdev); 9475 9476 /* let the f/w know that the h/w is now under the control of the 9477 * driver. 9478 */ 9479 igb_get_hw_control(adapter); 9480 } 9481 9482 /** 9483 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9484 * @adapter: Pointer to adapter structure 9485 * @index: Index of the RAR entry which need to be synced with MAC table 9486 **/ 9487 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9488 { 9489 struct e1000_hw *hw = &adapter->hw; 9490 u32 rar_low, rar_high; 9491 u8 *addr = adapter->mac_table[index].addr; 9492 9493 /* HW expects these to be in network order when they are plugged 9494 * into the registers which are little endian. In order to guarantee 9495 * that ordering we need to do an leXX_to_cpup here in order to be 9496 * ready for the byteswap that occurs with writel 9497 */ 9498 rar_low = le32_to_cpup((__le32 *)(addr)); 9499 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9500 9501 /* Indicate to hardware the Address is Valid. */ 9502 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9503 if (is_valid_ether_addr(addr)) 9504 rar_high |= E1000_RAH_AV; 9505 9506 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9507 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9508 9509 switch (hw->mac.type) { 9510 case e1000_82575: 9511 case e1000_i210: 9512 if (adapter->mac_table[index].state & 9513 IGB_MAC_STATE_QUEUE_STEERING) 9514 rar_high |= E1000_RAH_QSEL_ENABLE; 9515 9516 rar_high |= E1000_RAH_POOL_1 * 9517 adapter->mac_table[index].queue; 9518 break; 9519 default: 9520 rar_high |= E1000_RAH_POOL_1 << 9521 adapter->mac_table[index].queue; 9522 break; 9523 } 9524 } 9525 9526 wr32(E1000_RAL(index), rar_low); 9527 wrfl(); 9528 wr32(E1000_RAH(index), rar_high); 9529 wrfl(); 9530 } 9531 9532 static int igb_set_vf_mac(struct igb_adapter *adapter, 9533 int vf, unsigned char *mac_addr) 9534 { 9535 struct e1000_hw *hw = &adapter->hw; 9536 /* VF MAC addresses start at end of receive addresses and moves 9537 * towards the first, as a result a collision should not be possible 9538 */ 9539 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9540 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9541 9542 ether_addr_copy(vf_mac_addr, mac_addr); 9543 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9544 adapter->mac_table[rar_entry].queue = vf; 9545 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9546 igb_rar_set_index(adapter, rar_entry); 9547 9548 return 0; 9549 } 9550 9551 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9552 { 9553 struct igb_adapter *adapter = netdev_priv(netdev); 9554 9555 if (vf >= adapter->vfs_allocated_count) 9556 return -EINVAL; 9557 9558 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9559 * flag and allows to overwrite the MAC via VF netdev. This 9560 * is necessary to allow libvirt a way to restore the original 9561 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9562 * down a VM. 9563 */ 9564 if (is_zero_ether_addr(mac)) { 9565 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9566 dev_info(&adapter->pdev->dev, 9567 "remove administratively set MAC on VF %d\n", 9568 vf); 9569 } else if (is_valid_ether_addr(mac)) { 9570 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9571 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9572 mac, vf); 9573 dev_info(&adapter->pdev->dev, 9574 "Reload the VF driver to make this change effective."); 9575 /* Generate additional warning if PF is down */ 9576 if (test_bit(__IGB_DOWN, &adapter->state)) { 9577 dev_warn(&adapter->pdev->dev, 9578 "The VF MAC address has been set, but the PF device is not up.\n"); 9579 dev_warn(&adapter->pdev->dev, 9580 "Bring the PF device up before attempting to use the VF device.\n"); 9581 } 9582 } else { 9583 return -EINVAL; 9584 } 9585 return igb_set_vf_mac(adapter, vf, mac); 9586 } 9587 9588 static int igb_link_mbps(int internal_link_speed) 9589 { 9590 switch (internal_link_speed) { 9591 case SPEED_100: 9592 return 100; 9593 case SPEED_1000: 9594 return 1000; 9595 default: 9596 return 0; 9597 } 9598 } 9599 9600 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9601 int link_speed) 9602 { 9603 int rf_dec, rf_int; 9604 u32 bcnrc_val; 9605 9606 if (tx_rate != 0) { 9607 /* Calculate the rate factor values to set */ 9608 rf_int = link_speed / tx_rate; 9609 rf_dec = (link_speed - (rf_int * tx_rate)); 9610 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9611 tx_rate; 9612 9613 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9614 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9615 E1000_RTTBCNRC_RF_INT_MASK); 9616 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9617 } else { 9618 bcnrc_val = 0; 9619 } 9620 9621 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9622 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9623 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9624 */ 9625 wr32(E1000_RTTBCNRM, 0x14); 9626 wr32(E1000_RTTBCNRC, bcnrc_val); 9627 } 9628 9629 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9630 { 9631 int actual_link_speed, i; 9632 bool reset_rate = false; 9633 9634 /* VF TX rate limit was not set or not supported */ 9635 if ((adapter->vf_rate_link_speed == 0) || 9636 (adapter->hw.mac.type != e1000_82576)) 9637 return; 9638 9639 actual_link_speed = igb_link_mbps(adapter->link_speed); 9640 if (actual_link_speed != adapter->vf_rate_link_speed) { 9641 reset_rate = true; 9642 adapter->vf_rate_link_speed = 0; 9643 dev_info(&adapter->pdev->dev, 9644 "Link speed has been changed. VF Transmit rate is disabled\n"); 9645 } 9646 9647 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9648 if (reset_rate) 9649 adapter->vf_data[i].tx_rate = 0; 9650 9651 igb_set_vf_rate_limit(&adapter->hw, i, 9652 adapter->vf_data[i].tx_rate, 9653 actual_link_speed); 9654 } 9655 } 9656 9657 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9658 int min_tx_rate, int max_tx_rate) 9659 { 9660 struct igb_adapter *adapter = netdev_priv(netdev); 9661 struct e1000_hw *hw = &adapter->hw; 9662 int actual_link_speed; 9663 9664 if (hw->mac.type != e1000_82576) 9665 return -EOPNOTSUPP; 9666 9667 if (min_tx_rate) 9668 return -EINVAL; 9669 9670 actual_link_speed = igb_link_mbps(adapter->link_speed); 9671 if ((vf >= adapter->vfs_allocated_count) || 9672 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9673 (max_tx_rate < 0) || 9674 (max_tx_rate > actual_link_speed)) 9675 return -EINVAL; 9676 9677 adapter->vf_rate_link_speed = actual_link_speed; 9678 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9679 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9680 9681 return 0; 9682 } 9683 9684 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9685 bool setting) 9686 { 9687 struct igb_adapter *adapter = netdev_priv(netdev); 9688 struct e1000_hw *hw = &adapter->hw; 9689 u32 reg_val, reg_offset; 9690 9691 if (!adapter->vfs_allocated_count) 9692 return -EOPNOTSUPP; 9693 9694 if (vf >= adapter->vfs_allocated_count) 9695 return -EINVAL; 9696 9697 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9698 reg_val = rd32(reg_offset); 9699 if (setting) 9700 reg_val |= (BIT(vf) | 9701 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9702 else 9703 reg_val &= ~(BIT(vf) | 9704 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9705 wr32(reg_offset, reg_val); 9706 9707 adapter->vf_data[vf].spoofchk_enabled = setting; 9708 return 0; 9709 } 9710 9711 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9712 { 9713 struct igb_adapter *adapter = netdev_priv(netdev); 9714 9715 if (vf >= adapter->vfs_allocated_count) 9716 return -EINVAL; 9717 if (adapter->vf_data[vf].trusted == setting) 9718 return 0; 9719 9720 adapter->vf_data[vf].trusted = setting; 9721 9722 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9723 vf, setting ? "" : "not "); 9724 return 0; 9725 } 9726 9727 static int igb_ndo_get_vf_config(struct net_device *netdev, 9728 int vf, struct ifla_vf_info *ivi) 9729 { 9730 struct igb_adapter *adapter = netdev_priv(netdev); 9731 if (vf >= adapter->vfs_allocated_count) 9732 return -EINVAL; 9733 ivi->vf = vf; 9734 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9735 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9736 ivi->min_tx_rate = 0; 9737 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9738 ivi->qos = adapter->vf_data[vf].pf_qos; 9739 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9740 ivi->trusted = adapter->vf_data[vf].trusted; 9741 return 0; 9742 } 9743 9744 static void igb_vmm_control(struct igb_adapter *adapter) 9745 { 9746 struct e1000_hw *hw = &adapter->hw; 9747 u32 reg; 9748 9749 switch (hw->mac.type) { 9750 case e1000_82575: 9751 case e1000_i210: 9752 case e1000_i211: 9753 case e1000_i354: 9754 default: 9755 /* replication is not supported for 82575 */ 9756 return; 9757 case e1000_82576: 9758 /* notify HW that the MAC is adding vlan tags */ 9759 reg = rd32(E1000_DTXCTL); 9760 reg |= E1000_DTXCTL_VLAN_ADDED; 9761 wr32(E1000_DTXCTL, reg); 9762 fallthrough; 9763 case e1000_82580: 9764 /* enable replication vlan tag stripping */ 9765 reg = rd32(E1000_RPLOLR); 9766 reg |= E1000_RPLOLR_STRVLAN; 9767 wr32(E1000_RPLOLR, reg); 9768 fallthrough; 9769 case e1000_i350: 9770 /* none of the above registers are supported by i350 */ 9771 break; 9772 } 9773 9774 if (adapter->vfs_allocated_count) { 9775 igb_vmdq_set_loopback_pf(hw, true); 9776 igb_vmdq_set_replication_pf(hw, true); 9777 igb_vmdq_set_anti_spoofing_pf(hw, true, 9778 adapter->vfs_allocated_count); 9779 } else { 9780 igb_vmdq_set_loopback_pf(hw, false); 9781 igb_vmdq_set_replication_pf(hw, false); 9782 } 9783 } 9784 9785 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9786 { 9787 struct e1000_hw *hw = &adapter->hw; 9788 u32 dmac_thr; 9789 u16 hwm; 9790 9791 if (hw->mac.type > e1000_82580) { 9792 if (adapter->flags & IGB_FLAG_DMAC) { 9793 u32 reg; 9794 9795 /* force threshold to 0. */ 9796 wr32(E1000_DMCTXTH, 0); 9797 9798 /* DMA Coalescing high water mark needs to be greater 9799 * than the Rx threshold. Set hwm to PBA - max frame 9800 * size in 16B units, capping it at PBA - 6KB. 9801 */ 9802 hwm = 64 * (pba - 6); 9803 reg = rd32(E1000_FCRTC); 9804 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9805 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9806 & E1000_FCRTC_RTH_COAL_MASK); 9807 wr32(E1000_FCRTC, reg); 9808 9809 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9810 * frame size, capping it at PBA - 10KB. 9811 */ 9812 dmac_thr = pba - 10; 9813 reg = rd32(E1000_DMACR); 9814 reg &= ~E1000_DMACR_DMACTHR_MASK; 9815 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9816 & E1000_DMACR_DMACTHR_MASK); 9817 9818 /* transition to L0x or L1 if available..*/ 9819 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9820 9821 /* watchdog timer= +-1000 usec in 32usec intervals */ 9822 reg |= (1000 >> 5); 9823 9824 /* Disable BMC-to-OS Watchdog Enable */ 9825 if (hw->mac.type != e1000_i354) 9826 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9827 9828 wr32(E1000_DMACR, reg); 9829 9830 /* no lower threshold to disable 9831 * coalescing(smart fifb)-UTRESH=0 9832 */ 9833 wr32(E1000_DMCRTRH, 0); 9834 9835 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9836 9837 wr32(E1000_DMCTLX, reg); 9838 9839 /* free space in tx packet buffer to wake from 9840 * DMA coal 9841 */ 9842 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9843 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9844 9845 /* make low power state decision controlled 9846 * by DMA coal 9847 */ 9848 reg = rd32(E1000_PCIEMISC); 9849 reg &= ~E1000_PCIEMISC_LX_DECISION; 9850 wr32(E1000_PCIEMISC, reg); 9851 } /* endif adapter->dmac is not disabled */ 9852 } else if (hw->mac.type == e1000_82580) { 9853 u32 reg = rd32(E1000_PCIEMISC); 9854 9855 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9856 wr32(E1000_DMACR, 0); 9857 } 9858 } 9859 9860 /** 9861 * igb_read_i2c_byte - Reads 8 bit word over I2C 9862 * @hw: pointer to hardware structure 9863 * @byte_offset: byte offset to read 9864 * @dev_addr: device address 9865 * @data: value read 9866 * 9867 * Performs byte read operation over I2C interface at 9868 * a specified device address. 9869 **/ 9870 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9871 u8 dev_addr, u8 *data) 9872 { 9873 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9874 struct i2c_client *this_client = adapter->i2c_client; 9875 s32 status; 9876 u16 swfw_mask = 0; 9877 9878 if (!this_client) 9879 return E1000_ERR_I2C; 9880 9881 swfw_mask = E1000_SWFW_PHY0_SM; 9882 9883 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9884 return E1000_ERR_SWFW_SYNC; 9885 9886 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9887 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9888 9889 if (status < 0) 9890 return E1000_ERR_I2C; 9891 else { 9892 *data = status; 9893 return 0; 9894 } 9895 } 9896 9897 /** 9898 * igb_write_i2c_byte - Writes 8 bit word over I2C 9899 * @hw: pointer to hardware structure 9900 * @byte_offset: byte offset to write 9901 * @dev_addr: device address 9902 * @data: value to write 9903 * 9904 * Performs byte write operation over I2C interface at 9905 * a specified device address. 9906 **/ 9907 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9908 u8 dev_addr, u8 data) 9909 { 9910 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9911 struct i2c_client *this_client = adapter->i2c_client; 9912 s32 status; 9913 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9914 9915 if (!this_client) 9916 return E1000_ERR_I2C; 9917 9918 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9919 return E1000_ERR_SWFW_SYNC; 9920 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9921 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9922 9923 if (status) 9924 return E1000_ERR_I2C; 9925 else 9926 return 0; 9927 9928 } 9929 9930 int igb_reinit_queues(struct igb_adapter *adapter) 9931 { 9932 struct net_device *netdev = adapter->netdev; 9933 struct pci_dev *pdev = adapter->pdev; 9934 int err = 0; 9935 9936 if (netif_running(netdev)) 9937 igb_close(netdev); 9938 9939 igb_reset_interrupt_capability(adapter); 9940 9941 if (igb_init_interrupt_scheme(adapter, true)) { 9942 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9943 return -ENOMEM; 9944 } 9945 9946 if (netif_running(netdev)) 9947 err = igb_open(netdev); 9948 9949 return err; 9950 } 9951 9952 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9953 { 9954 struct igb_nfc_filter *rule; 9955 9956 spin_lock(&adapter->nfc_lock); 9957 9958 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9959 igb_erase_filter(adapter, rule); 9960 9961 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9962 igb_erase_filter(adapter, rule); 9963 9964 spin_unlock(&adapter->nfc_lock); 9965 } 9966 9967 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9968 { 9969 struct igb_nfc_filter *rule; 9970 9971 spin_lock(&adapter->nfc_lock); 9972 9973 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9974 igb_add_filter(adapter, rule); 9975 9976 spin_unlock(&adapter->nfc_lock); 9977 } 9978 /* igb_main.c */ 9979