1 // SPDX-License-Identifier: GPL-2.0 2 /* Intel(R) Gigabit Ethernet Linux driver 3 * Copyright(c) 2007-2014 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, see <http://www.gnu.org/licenses/>. 16 * 17 * The full GNU General Public License is included in this distribution in 18 * the file called "COPYING". 19 * 20 * Contact Information: 21 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/module.h> 28 #include <linux/types.h> 29 #include <linux/init.h> 30 #include <linux/bitops.h> 31 #include <linux/vmalloc.h> 32 #include <linux/pagemap.h> 33 #include <linux/netdevice.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <net/pkt_sched.h> 39 #include <linux/net_tstamp.h> 40 #include <linux/mii.h> 41 #include <linux/ethtool.h> 42 #include <linux/if.h> 43 #include <linux/if_vlan.h> 44 #include <linux/pci.h> 45 #include <linux/pci-aspm.h> 46 #include <linux/delay.h> 47 #include <linux/interrupt.h> 48 #include <linux/ip.h> 49 #include <linux/tcp.h> 50 #include <linux/sctp.h> 51 #include <linux/if_ether.h> 52 #include <linux/aer.h> 53 #include <linux/prefetch.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/etherdevice.h> 56 #ifdef CONFIG_IGB_DCA 57 #include <linux/dca.h> 58 #endif 59 #include <linux/i2c.h> 60 #include "igb.h" 61 62 #define MAJ 5 63 #define MIN 4 64 #define BUILD 0 65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66 __stringify(BUILD) "-k" 67 68 enum queue_mode { 69 QUEUE_MODE_STRICT_PRIORITY, 70 QUEUE_MODE_STREAM_RESERVATION, 71 }; 72 73 enum tx_queue_prio { 74 TX_QUEUE_PRIO_HIGH, 75 TX_QUEUE_PRIO_LOW, 76 }; 77 78 char igb_driver_name[] = "igb"; 79 char igb_driver_version[] = DRV_VERSION; 80 static const char igb_driver_string[] = 81 "Intel(R) Gigabit Ethernet Network Driver"; 82 static const char igb_copyright[] = 83 "Copyright (c) 2007-2014 Intel Corporation."; 84 85 static const struct e1000_info *igb_info_tbl[] = { 86 [board_82575] = &e1000_82575_info, 87 }; 88 89 static const struct pci_device_id igb_pci_tbl[] = { 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 115 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 116 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 117 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 118 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 119 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 120 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 121 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 122 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 123 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 124 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 125 /* required last entry */ 126 {0, } 127 }; 128 129 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 130 131 static int igb_setup_all_tx_resources(struct igb_adapter *); 132 static int igb_setup_all_rx_resources(struct igb_adapter *); 133 static void igb_free_all_tx_resources(struct igb_adapter *); 134 static void igb_free_all_rx_resources(struct igb_adapter *); 135 static void igb_setup_mrqc(struct igb_adapter *); 136 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 137 static void igb_remove(struct pci_dev *pdev); 138 static int igb_sw_init(struct igb_adapter *); 139 int igb_open(struct net_device *); 140 int igb_close(struct net_device *); 141 static void igb_configure(struct igb_adapter *); 142 static void igb_configure_tx(struct igb_adapter *); 143 static void igb_configure_rx(struct igb_adapter *); 144 static void igb_clean_all_tx_rings(struct igb_adapter *); 145 static void igb_clean_all_rx_rings(struct igb_adapter *); 146 static void igb_clean_tx_ring(struct igb_ring *); 147 static void igb_clean_rx_ring(struct igb_ring *); 148 static void igb_set_rx_mode(struct net_device *); 149 static void igb_update_phy_info(struct timer_list *); 150 static void igb_watchdog(struct timer_list *); 151 static void igb_watchdog_task(struct work_struct *); 152 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 153 static void igb_get_stats64(struct net_device *dev, 154 struct rtnl_link_stats64 *stats); 155 static int igb_change_mtu(struct net_device *, int); 156 static int igb_set_mac(struct net_device *, void *); 157 static void igb_set_uta(struct igb_adapter *adapter, bool set); 158 static irqreturn_t igb_intr(int irq, void *); 159 static irqreturn_t igb_intr_msi(int irq, void *); 160 static irqreturn_t igb_msix_other(int irq, void *); 161 static irqreturn_t igb_msix_ring(int irq, void *); 162 #ifdef CONFIG_IGB_DCA 163 static void igb_update_dca(struct igb_q_vector *); 164 static void igb_setup_dca(struct igb_adapter *); 165 #endif /* CONFIG_IGB_DCA */ 166 static int igb_poll(struct napi_struct *, int); 167 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 168 static int igb_clean_rx_irq(struct igb_q_vector *, int); 169 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 170 static void igb_tx_timeout(struct net_device *); 171 static void igb_reset_task(struct work_struct *); 172 static void igb_vlan_mode(struct net_device *netdev, 173 netdev_features_t features); 174 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 175 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 176 static void igb_restore_vlan(struct igb_adapter *); 177 static void igb_rar_set_index(struct igb_adapter *, u32); 178 static void igb_ping_all_vfs(struct igb_adapter *); 179 static void igb_msg_task(struct igb_adapter *); 180 static void igb_vmm_control(struct igb_adapter *); 181 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 182 static void igb_flush_mac_table(struct igb_adapter *); 183 static int igb_available_rars(struct igb_adapter *, u8); 184 static void igb_set_default_mac_filter(struct igb_adapter *); 185 static int igb_uc_sync(struct net_device *, const unsigned char *); 186 static int igb_uc_unsync(struct net_device *, const unsigned char *); 187 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 188 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 189 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 190 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 191 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 192 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 193 bool setting); 194 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 195 bool setting); 196 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 197 struct ifla_vf_info *ivi); 198 static void igb_check_vf_rate_limit(struct igb_adapter *); 199 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 200 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 201 202 #ifdef CONFIG_PCI_IOV 203 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 204 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 205 static int igb_disable_sriov(struct pci_dev *dev); 206 static int igb_pci_disable_sriov(struct pci_dev *dev); 207 #endif 208 209 static int igb_suspend(struct device *); 210 static int igb_resume(struct device *); 211 static int igb_runtime_suspend(struct device *dev); 212 static int igb_runtime_resume(struct device *dev); 213 static int igb_runtime_idle(struct device *dev); 214 static const struct dev_pm_ops igb_pm_ops = { 215 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 216 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 217 igb_runtime_idle) 218 }; 219 static void igb_shutdown(struct pci_dev *); 220 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 221 #ifdef CONFIG_IGB_DCA 222 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 223 static struct notifier_block dca_notifier = { 224 .notifier_call = igb_notify_dca, 225 .next = NULL, 226 .priority = 0 227 }; 228 #endif 229 #ifdef CONFIG_NET_POLL_CONTROLLER 230 /* for netdump / net console */ 231 static void igb_netpoll(struct net_device *); 232 #endif 233 #ifdef CONFIG_PCI_IOV 234 static unsigned int max_vfs; 235 module_param(max_vfs, uint, 0); 236 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 237 #endif /* CONFIG_PCI_IOV */ 238 239 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 240 pci_channel_state_t); 241 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 242 static void igb_io_resume(struct pci_dev *); 243 244 static const struct pci_error_handlers igb_err_handler = { 245 .error_detected = igb_io_error_detected, 246 .slot_reset = igb_io_slot_reset, 247 .resume = igb_io_resume, 248 }; 249 250 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 251 252 static struct pci_driver igb_driver = { 253 .name = igb_driver_name, 254 .id_table = igb_pci_tbl, 255 .probe = igb_probe, 256 .remove = igb_remove, 257 #ifdef CONFIG_PM 258 .driver.pm = &igb_pm_ops, 259 #endif 260 .shutdown = igb_shutdown, 261 .sriov_configure = igb_pci_sriov_configure, 262 .err_handler = &igb_err_handler 263 }; 264 265 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 266 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 267 MODULE_LICENSE("GPL"); 268 MODULE_VERSION(DRV_VERSION); 269 270 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 271 static int debug = -1; 272 module_param(debug, int, 0); 273 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 274 275 struct igb_reg_info { 276 u32 ofs; 277 char *name; 278 }; 279 280 static const struct igb_reg_info igb_reg_info_tbl[] = { 281 282 /* General Registers */ 283 {E1000_CTRL, "CTRL"}, 284 {E1000_STATUS, "STATUS"}, 285 {E1000_CTRL_EXT, "CTRL_EXT"}, 286 287 /* Interrupt Registers */ 288 {E1000_ICR, "ICR"}, 289 290 /* RX Registers */ 291 {E1000_RCTL, "RCTL"}, 292 {E1000_RDLEN(0), "RDLEN"}, 293 {E1000_RDH(0), "RDH"}, 294 {E1000_RDT(0), "RDT"}, 295 {E1000_RXDCTL(0), "RXDCTL"}, 296 {E1000_RDBAL(0), "RDBAL"}, 297 {E1000_RDBAH(0), "RDBAH"}, 298 299 /* TX Registers */ 300 {E1000_TCTL, "TCTL"}, 301 {E1000_TDBAL(0), "TDBAL"}, 302 {E1000_TDBAH(0), "TDBAH"}, 303 {E1000_TDLEN(0), "TDLEN"}, 304 {E1000_TDH(0), "TDH"}, 305 {E1000_TDT(0), "TDT"}, 306 {E1000_TXDCTL(0), "TXDCTL"}, 307 {E1000_TDFH, "TDFH"}, 308 {E1000_TDFT, "TDFT"}, 309 {E1000_TDFHS, "TDFHS"}, 310 {E1000_TDFPC, "TDFPC"}, 311 312 /* List Terminator */ 313 {} 314 }; 315 316 /* igb_regdump - register printout routine */ 317 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 318 { 319 int n = 0; 320 char rname[16]; 321 u32 regs[8]; 322 323 switch (reginfo->ofs) { 324 case E1000_RDLEN(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDLEN(n)); 327 break; 328 case E1000_RDH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDH(n)); 331 break; 332 case E1000_RDT(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_RDT(n)); 335 break; 336 case E1000_RXDCTL(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_RXDCTL(n)); 339 break; 340 case E1000_RDBAL(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_RDBAL(n)); 343 break; 344 case E1000_RDBAH(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_RDBAH(n)); 347 break; 348 case E1000_TDBAL(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_RDBAL(n)); 351 break; 352 case E1000_TDBAH(0): 353 for (n = 0; n < 4; n++) 354 regs[n] = rd32(E1000_TDBAH(n)); 355 break; 356 case E1000_TDLEN(0): 357 for (n = 0; n < 4; n++) 358 regs[n] = rd32(E1000_TDLEN(n)); 359 break; 360 case E1000_TDH(0): 361 for (n = 0; n < 4; n++) 362 regs[n] = rd32(E1000_TDH(n)); 363 break; 364 case E1000_TDT(0): 365 for (n = 0; n < 4; n++) 366 regs[n] = rd32(E1000_TDT(n)); 367 break; 368 case E1000_TXDCTL(0): 369 for (n = 0; n < 4; n++) 370 regs[n] = rd32(E1000_TXDCTL(n)); 371 break; 372 default: 373 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 374 return; 375 } 376 377 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 378 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 379 regs[2], regs[3]); 380 } 381 382 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 383 static void igb_dump(struct igb_adapter *adapter) 384 { 385 struct net_device *netdev = adapter->netdev; 386 struct e1000_hw *hw = &adapter->hw; 387 struct igb_reg_info *reginfo; 388 struct igb_ring *tx_ring; 389 union e1000_adv_tx_desc *tx_desc; 390 struct my_u0 { u64 a; u64 b; } *u0; 391 struct igb_ring *rx_ring; 392 union e1000_adv_rx_desc *rx_desc; 393 u32 staterr; 394 u16 i, n; 395 396 if (!netif_msg_hw(adapter)) 397 return; 398 399 /* Print netdevice Info */ 400 if (netdev) { 401 dev_info(&adapter->pdev->dev, "Net device Info\n"); 402 pr_info("Device Name state trans_start\n"); 403 pr_info("%-15s %016lX %016lX\n", netdev->name, 404 netdev->state, dev_trans_start(netdev)); 405 } 406 407 /* Print Registers */ 408 dev_info(&adapter->pdev->dev, "Register Dump\n"); 409 pr_info(" Register Name Value\n"); 410 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 411 reginfo->name; reginfo++) { 412 igb_regdump(hw, reginfo); 413 } 414 415 /* Print TX Ring Summary */ 416 if (!netdev || !netif_running(netdev)) 417 goto exit; 418 419 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 420 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 421 for (n = 0; n < adapter->num_tx_queues; n++) { 422 struct igb_tx_buffer *buffer_info; 423 tx_ring = adapter->tx_ring[n]; 424 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 425 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 426 n, tx_ring->next_to_use, tx_ring->next_to_clean, 427 (u64)dma_unmap_addr(buffer_info, dma), 428 dma_unmap_len(buffer_info, len), 429 buffer_info->next_to_watch, 430 (u64)buffer_info->time_stamp); 431 } 432 433 /* Print TX Rings */ 434 if (!netif_msg_tx_done(adapter)) 435 goto rx_ring_summary; 436 437 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 438 439 /* Transmit Descriptor Formats 440 * 441 * Advanced Transmit Descriptor 442 * +--------------------------------------------------------------+ 443 * 0 | Buffer Address [63:0] | 444 * +--------------------------------------------------------------+ 445 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 446 * +--------------------------------------------------------------+ 447 * 63 46 45 40 39 38 36 35 32 31 24 15 0 448 */ 449 450 for (n = 0; n < adapter->num_tx_queues; n++) { 451 tx_ring = adapter->tx_ring[n]; 452 pr_info("------------------------------------\n"); 453 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 454 pr_info("------------------------------------\n"); 455 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 456 457 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 458 const char *next_desc; 459 struct igb_tx_buffer *buffer_info; 460 tx_desc = IGB_TX_DESC(tx_ring, i); 461 buffer_info = &tx_ring->tx_buffer_info[i]; 462 u0 = (struct my_u0 *)tx_desc; 463 if (i == tx_ring->next_to_use && 464 i == tx_ring->next_to_clean) 465 next_desc = " NTC/U"; 466 else if (i == tx_ring->next_to_use) 467 next_desc = " NTU"; 468 else if (i == tx_ring->next_to_clean) 469 next_desc = " NTC"; 470 else 471 next_desc = ""; 472 473 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 474 i, le64_to_cpu(u0->a), 475 le64_to_cpu(u0->b), 476 (u64)dma_unmap_addr(buffer_info, dma), 477 dma_unmap_len(buffer_info, len), 478 buffer_info->next_to_watch, 479 (u64)buffer_info->time_stamp, 480 buffer_info->skb, next_desc); 481 482 if (netif_msg_pktdata(adapter) && buffer_info->skb) 483 print_hex_dump(KERN_INFO, "", 484 DUMP_PREFIX_ADDRESS, 485 16, 1, buffer_info->skb->data, 486 dma_unmap_len(buffer_info, len), 487 true); 488 } 489 } 490 491 /* Print RX Rings Summary */ 492 rx_ring_summary: 493 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 494 pr_info("Queue [NTU] [NTC]\n"); 495 for (n = 0; n < adapter->num_rx_queues; n++) { 496 rx_ring = adapter->rx_ring[n]; 497 pr_info(" %5d %5X %5X\n", 498 n, rx_ring->next_to_use, rx_ring->next_to_clean); 499 } 500 501 /* Print RX Rings */ 502 if (!netif_msg_rx_status(adapter)) 503 goto exit; 504 505 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 506 507 /* Advanced Receive Descriptor (Read) Format 508 * 63 1 0 509 * +-----------------------------------------------------+ 510 * 0 | Packet Buffer Address [63:1] |A0/NSE| 511 * +----------------------------------------------+------+ 512 * 8 | Header Buffer Address [63:1] | DD | 513 * +-----------------------------------------------------+ 514 * 515 * 516 * Advanced Receive Descriptor (Write-Back) Format 517 * 518 * 63 48 47 32 31 30 21 20 17 16 4 3 0 519 * +------------------------------------------------------+ 520 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 521 * | Checksum Ident | | | | Type | Type | 522 * +------------------------------------------------------+ 523 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 524 * +------------------------------------------------------+ 525 * 63 48 47 32 31 20 19 0 526 */ 527 528 for (n = 0; n < adapter->num_rx_queues; n++) { 529 rx_ring = adapter->rx_ring[n]; 530 pr_info("------------------------------------\n"); 531 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 532 pr_info("------------------------------------\n"); 533 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 534 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 535 536 for (i = 0; i < rx_ring->count; i++) { 537 const char *next_desc; 538 struct igb_rx_buffer *buffer_info; 539 buffer_info = &rx_ring->rx_buffer_info[i]; 540 rx_desc = IGB_RX_DESC(rx_ring, i); 541 u0 = (struct my_u0 *)rx_desc; 542 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 543 544 if (i == rx_ring->next_to_use) 545 next_desc = " NTU"; 546 else if (i == rx_ring->next_to_clean) 547 next_desc = " NTC"; 548 else 549 next_desc = ""; 550 551 if (staterr & E1000_RXD_STAT_DD) { 552 /* Descriptor Done */ 553 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 554 "RWB", i, 555 le64_to_cpu(u0->a), 556 le64_to_cpu(u0->b), 557 next_desc); 558 } else { 559 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 560 "R ", i, 561 le64_to_cpu(u0->a), 562 le64_to_cpu(u0->b), 563 (u64)buffer_info->dma, 564 next_desc); 565 566 if (netif_msg_pktdata(adapter) && 567 buffer_info->dma && buffer_info->page) { 568 print_hex_dump(KERN_INFO, "", 569 DUMP_PREFIX_ADDRESS, 570 16, 1, 571 page_address(buffer_info->page) + 572 buffer_info->page_offset, 573 igb_rx_bufsz(rx_ring), true); 574 } 575 } 576 } 577 } 578 579 exit: 580 return; 581 } 582 583 /** 584 * igb_get_i2c_data - Reads the I2C SDA data bit 585 * @hw: pointer to hardware structure 586 * @i2cctl: Current value of I2CCTL register 587 * 588 * Returns the I2C data bit value 589 **/ 590 static int igb_get_i2c_data(void *data) 591 { 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 return !!(i2cctl & E1000_I2C_DATA_IN); 597 } 598 599 /** 600 * igb_set_i2c_data - Sets the I2C data bit 601 * @data: pointer to hardware structure 602 * @state: I2C data value (0 or 1) to set 603 * 604 * Sets the I2C data bit 605 **/ 606 static void igb_set_i2c_data(void *data, int state) 607 { 608 struct igb_adapter *adapter = (struct igb_adapter *)data; 609 struct e1000_hw *hw = &adapter->hw; 610 s32 i2cctl = rd32(E1000_I2CPARAMS); 611 612 if (state) 613 i2cctl |= E1000_I2C_DATA_OUT; 614 else 615 i2cctl &= ~E1000_I2C_DATA_OUT; 616 617 i2cctl &= ~E1000_I2C_DATA_OE_N; 618 i2cctl |= E1000_I2C_CLK_OE_N; 619 wr32(E1000_I2CPARAMS, i2cctl); 620 wrfl(); 621 622 } 623 624 /** 625 * igb_set_i2c_clk - Sets the I2C SCL clock 626 * @data: pointer to hardware structure 627 * @state: state to set clock 628 * 629 * Sets the I2C clock line to state 630 **/ 631 static void igb_set_i2c_clk(void *data, int state) 632 { 633 struct igb_adapter *adapter = (struct igb_adapter *)data; 634 struct e1000_hw *hw = &adapter->hw; 635 s32 i2cctl = rd32(E1000_I2CPARAMS); 636 637 if (state) { 638 i2cctl |= E1000_I2C_CLK_OUT; 639 i2cctl &= ~E1000_I2C_CLK_OE_N; 640 } else { 641 i2cctl &= ~E1000_I2C_CLK_OUT; 642 i2cctl &= ~E1000_I2C_CLK_OE_N; 643 } 644 wr32(E1000_I2CPARAMS, i2cctl); 645 wrfl(); 646 } 647 648 /** 649 * igb_get_i2c_clk - Gets the I2C SCL clock state 650 * @data: pointer to hardware structure 651 * 652 * Gets the I2C clock state 653 **/ 654 static int igb_get_i2c_clk(void *data) 655 { 656 struct igb_adapter *adapter = (struct igb_adapter *)data; 657 struct e1000_hw *hw = &adapter->hw; 658 s32 i2cctl = rd32(E1000_I2CPARAMS); 659 660 return !!(i2cctl & E1000_I2C_CLK_IN); 661 } 662 663 static const struct i2c_algo_bit_data igb_i2c_algo = { 664 .setsda = igb_set_i2c_data, 665 .setscl = igb_set_i2c_clk, 666 .getsda = igb_get_i2c_data, 667 .getscl = igb_get_i2c_clk, 668 .udelay = 5, 669 .timeout = 20, 670 }; 671 672 /** 673 * igb_get_hw_dev - return device 674 * @hw: pointer to hardware structure 675 * 676 * used by hardware layer to print debugging information 677 **/ 678 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 679 { 680 struct igb_adapter *adapter = hw->back; 681 return adapter->netdev; 682 } 683 684 /** 685 * igb_init_module - Driver Registration Routine 686 * 687 * igb_init_module is the first routine called when the driver is 688 * loaded. All it does is register with the PCI subsystem. 689 **/ 690 static int __init igb_init_module(void) 691 { 692 int ret; 693 694 pr_info("%s - version %s\n", 695 igb_driver_string, igb_driver_version); 696 pr_info("%s\n", igb_copyright); 697 698 #ifdef CONFIG_IGB_DCA 699 dca_register_notify(&dca_notifier); 700 #endif 701 ret = pci_register_driver(&igb_driver); 702 return ret; 703 } 704 705 module_init(igb_init_module); 706 707 /** 708 * igb_exit_module - Driver Exit Cleanup Routine 709 * 710 * igb_exit_module is called just before the driver is removed 711 * from memory. 712 **/ 713 static void __exit igb_exit_module(void) 714 { 715 #ifdef CONFIG_IGB_DCA 716 dca_unregister_notify(&dca_notifier); 717 #endif 718 pci_unregister_driver(&igb_driver); 719 } 720 721 module_exit(igb_exit_module); 722 723 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 724 /** 725 * igb_cache_ring_register - Descriptor ring to register mapping 726 * @adapter: board private structure to initialize 727 * 728 * Once we know the feature-set enabled for the device, we'll cache 729 * the register offset the descriptor ring is assigned to. 730 **/ 731 static void igb_cache_ring_register(struct igb_adapter *adapter) 732 { 733 int i = 0, j = 0; 734 u32 rbase_offset = adapter->vfs_allocated_count; 735 736 switch (adapter->hw.mac.type) { 737 case e1000_82576: 738 /* The queues are allocated for virtualization such that VF 0 739 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 740 * In order to avoid collision we start at the first free queue 741 * and continue consuming queues in the same sequence 742 */ 743 if (adapter->vfs_allocated_count) { 744 for (; i < adapter->rss_queues; i++) 745 adapter->rx_ring[i]->reg_idx = rbase_offset + 746 Q_IDX_82576(i); 747 } 748 /* Fall through */ 749 case e1000_82575: 750 case e1000_82580: 751 case e1000_i350: 752 case e1000_i354: 753 case e1000_i210: 754 case e1000_i211: 755 /* Fall through */ 756 default: 757 for (; i < adapter->num_rx_queues; i++) 758 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 759 for (; j < adapter->num_tx_queues; j++) 760 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 761 break; 762 } 763 } 764 765 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 766 { 767 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 768 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 769 u32 value = 0; 770 771 if (E1000_REMOVED(hw_addr)) 772 return ~value; 773 774 value = readl(&hw_addr[reg]); 775 776 /* reads should not return all F's */ 777 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 778 struct net_device *netdev = igb->netdev; 779 hw->hw_addr = NULL; 780 netdev_err(netdev, "PCIe link lost\n"); 781 } 782 783 return value; 784 } 785 786 /** 787 * igb_write_ivar - configure ivar for given MSI-X vector 788 * @hw: pointer to the HW structure 789 * @msix_vector: vector number we are allocating to a given ring 790 * @index: row index of IVAR register to write within IVAR table 791 * @offset: column offset of in IVAR, should be multiple of 8 792 * 793 * This function is intended to handle the writing of the IVAR register 794 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 795 * each containing an cause allocation for an Rx and Tx ring, and a 796 * variable number of rows depending on the number of queues supported. 797 **/ 798 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 799 int index, int offset) 800 { 801 u32 ivar = array_rd32(E1000_IVAR0, index); 802 803 /* clear any bits that are currently set */ 804 ivar &= ~((u32)0xFF << offset); 805 806 /* write vector and valid bit */ 807 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 808 809 array_wr32(E1000_IVAR0, index, ivar); 810 } 811 812 #define IGB_N0_QUEUE -1 813 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 814 { 815 struct igb_adapter *adapter = q_vector->adapter; 816 struct e1000_hw *hw = &adapter->hw; 817 int rx_queue = IGB_N0_QUEUE; 818 int tx_queue = IGB_N0_QUEUE; 819 u32 msixbm = 0; 820 821 if (q_vector->rx.ring) 822 rx_queue = q_vector->rx.ring->reg_idx; 823 if (q_vector->tx.ring) 824 tx_queue = q_vector->tx.ring->reg_idx; 825 826 switch (hw->mac.type) { 827 case e1000_82575: 828 /* The 82575 assigns vectors using a bitmask, which matches the 829 * bitmask for the EICR/EIMS/EIMC registers. To assign one 830 * or more queues to a vector, we write the appropriate bits 831 * into the MSIXBM register for that vector. 832 */ 833 if (rx_queue > IGB_N0_QUEUE) 834 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 835 if (tx_queue > IGB_N0_QUEUE) 836 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 837 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 838 msixbm |= E1000_EIMS_OTHER; 839 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 840 q_vector->eims_value = msixbm; 841 break; 842 case e1000_82576: 843 /* 82576 uses a table that essentially consists of 2 columns 844 * with 8 rows. The ordering is column-major so we use the 845 * lower 3 bits as the row index, and the 4th bit as the 846 * column offset. 847 */ 848 if (rx_queue > IGB_N0_QUEUE) 849 igb_write_ivar(hw, msix_vector, 850 rx_queue & 0x7, 851 (rx_queue & 0x8) << 1); 852 if (tx_queue > IGB_N0_QUEUE) 853 igb_write_ivar(hw, msix_vector, 854 tx_queue & 0x7, 855 ((tx_queue & 0x8) << 1) + 8); 856 q_vector->eims_value = BIT(msix_vector); 857 break; 858 case e1000_82580: 859 case e1000_i350: 860 case e1000_i354: 861 case e1000_i210: 862 case e1000_i211: 863 /* On 82580 and newer adapters the scheme is similar to 82576 864 * however instead of ordering column-major we have things 865 * ordered row-major. So we traverse the table by using 866 * bit 0 as the column offset, and the remaining bits as the 867 * row index. 868 */ 869 if (rx_queue > IGB_N0_QUEUE) 870 igb_write_ivar(hw, msix_vector, 871 rx_queue >> 1, 872 (rx_queue & 0x1) << 4); 873 if (tx_queue > IGB_N0_QUEUE) 874 igb_write_ivar(hw, msix_vector, 875 tx_queue >> 1, 876 ((tx_queue & 0x1) << 4) + 8); 877 q_vector->eims_value = BIT(msix_vector); 878 break; 879 default: 880 BUG(); 881 break; 882 } 883 884 /* add q_vector eims value to global eims_enable_mask */ 885 adapter->eims_enable_mask |= q_vector->eims_value; 886 887 /* configure q_vector to set itr on first interrupt */ 888 q_vector->set_itr = 1; 889 } 890 891 /** 892 * igb_configure_msix - Configure MSI-X hardware 893 * @adapter: board private structure to initialize 894 * 895 * igb_configure_msix sets up the hardware to properly 896 * generate MSI-X interrupts. 897 **/ 898 static void igb_configure_msix(struct igb_adapter *adapter) 899 { 900 u32 tmp; 901 int i, vector = 0; 902 struct e1000_hw *hw = &adapter->hw; 903 904 adapter->eims_enable_mask = 0; 905 906 /* set vector for other causes, i.e. link changes */ 907 switch (hw->mac.type) { 908 case e1000_82575: 909 tmp = rd32(E1000_CTRL_EXT); 910 /* enable MSI-X PBA support*/ 911 tmp |= E1000_CTRL_EXT_PBA_CLR; 912 913 /* Auto-Mask interrupts upon ICR read. */ 914 tmp |= E1000_CTRL_EXT_EIAME; 915 tmp |= E1000_CTRL_EXT_IRCA; 916 917 wr32(E1000_CTRL_EXT, tmp); 918 919 /* enable msix_other interrupt */ 920 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 921 adapter->eims_other = E1000_EIMS_OTHER; 922 923 break; 924 925 case e1000_82576: 926 case e1000_82580: 927 case e1000_i350: 928 case e1000_i354: 929 case e1000_i210: 930 case e1000_i211: 931 /* Turn on MSI-X capability first, or our settings 932 * won't stick. And it will take days to debug. 933 */ 934 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 935 E1000_GPIE_PBA | E1000_GPIE_EIAME | 936 E1000_GPIE_NSICR); 937 938 /* enable msix_other interrupt */ 939 adapter->eims_other = BIT(vector); 940 tmp = (vector++ | E1000_IVAR_VALID) << 8; 941 942 wr32(E1000_IVAR_MISC, tmp); 943 break; 944 default: 945 /* do nothing, since nothing else supports MSI-X */ 946 break; 947 } /* switch (hw->mac.type) */ 948 949 adapter->eims_enable_mask |= adapter->eims_other; 950 951 for (i = 0; i < adapter->num_q_vectors; i++) 952 igb_assign_vector(adapter->q_vector[i], vector++); 953 954 wrfl(); 955 } 956 957 /** 958 * igb_request_msix - Initialize MSI-X interrupts 959 * @adapter: board private structure to initialize 960 * 961 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 962 * kernel. 963 **/ 964 static int igb_request_msix(struct igb_adapter *adapter) 965 { 966 struct net_device *netdev = adapter->netdev; 967 int i, err = 0, vector = 0, free_vector = 0; 968 969 err = request_irq(adapter->msix_entries[vector].vector, 970 igb_msix_other, 0, netdev->name, adapter); 971 if (err) 972 goto err_out; 973 974 for (i = 0; i < adapter->num_q_vectors; i++) { 975 struct igb_q_vector *q_vector = adapter->q_vector[i]; 976 977 vector++; 978 979 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 980 981 if (q_vector->rx.ring && q_vector->tx.ring) 982 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 983 q_vector->rx.ring->queue_index); 984 else if (q_vector->tx.ring) 985 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 986 q_vector->tx.ring->queue_index); 987 else if (q_vector->rx.ring) 988 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 989 q_vector->rx.ring->queue_index); 990 else 991 sprintf(q_vector->name, "%s-unused", netdev->name); 992 993 err = request_irq(adapter->msix_entries[vector].vector, 994 igb_msix_ring, 0, q_vector->name, 995 q_vector); 996 if (err) 997 goto err_free; 998 } 999 1000 igb_configure_msix(adapter); 1001 return 0; 1002 1003 err_free: 1004 /* free already assigned IRQs */ 1005 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 1006 1007 vector--; 1008 for (i = 0; i < vector; i++) { 1009 free_irq(adapter->msix_entries[free_vector++].vector, 1010 adapter->q_vector[i]); 1011 } 1012 err_out: 1013 return err; 1014 } 1015 1016 /** 1017 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1018 * @adapter: board private structure to initialize 1019 * @v_idx: Index of vector to be freed 1020 * 1021 * This function frees the memory allocated to the q_vector. 1022 **/ 1023 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1024 { 1025 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1026 1027 adapter->q_vector[v_idx] = NULL; 1028 1029 /* igb_get_stats64() might access the rings on this vector, 1030 * we must wait a grace period before freeing it. 1031 */ 1032 if (q_vector) 1033 kfree_rcu(q_vector, rcu); 1034 } 1035 1036 /** 1037 * igb_reset_q_vector - Reset config for interrupt vector 1038 * @adapter: board private structure to initialize 1039 * @v_idx: Index of vector to be reset 1040 * 1041 * If NAPI is enabled it will delete any references to the 1042 * NAPI struct. This is preparation for igb_free_q_vector. 1043 **/ 1044 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1045 { 1046 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1047 1048 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1049 * allocated. So, q_vector is NULL so we should stop here. 1050 */ 1051 if (!q_vector) 1052 return; 1053 1054 if (q_vector->tx.ring) 1055 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1056 1057 if (q_vector->rx.ring) 1058 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1059 1060 netif_napi_del(&q_vector->napi); 1061 1062 } 1063 1064 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1065 { 1066 int v_idx = adapter->num_q_vectors; 1067 1068 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1069 pci_disable_msix(adapter->pdev); 1070 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1071 pci_disable_msi(adapter->pdev); 1072 1073 while (v_idx--) 1074 igb_reset_q_vector(adapter, v_idx); 1075 } 1076 1077 /** 1078 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1079 * @adapter: board private structure to initialize 1080 * 1081 * This function frees the memory allocated to the q_vectors. In addition if 1082 * NAPI is enabled it will delete any references to the NAPI struct prior 1083 * to freeing the q_vector. 1084 **/ 1085 static void igb_free_q_vectors(struct igb_adapter *adapter) 1086 { 1087 int v_idx = adapter->num_q_vectors; 1088 1089 adapter->num_tx_queues = 0; 1090 adapter->num_rx_queues = 0; 1091 adapter->num_q_vectors = 0; 1092 1093 while (v_idx--) { 1094 igb_reset_q_vector(adapter, v_idx); 1095 igb_free_q_vector(adapter, v_idx); 1096 } 1097 } 1098 1099 /** 1100 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1101 * @adapter: board private structure to initialize 1102 * 1103 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1104 * MSI-X interrupts allocated. 1105 */ 1106 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1107 { 1108 igb_free_q_vectors(adapter); 1109 igb_reset_interrupt_capability(adapter); 1110 } 1111 1112 /** 1113 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1114 * @adapter: board private structure to initialize 1115 * @msix: boolean value of MSIX capability 1116 * 1117 * Attempt to configure interrupts using the best available 1118 * capabilities of the hardware and kernel. 1119 **/ 1120 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1121 { 1122 int err; 1123 int numvecs, i; 1124 1125 if (!msix) 1126 goto msi_only; 1127 adapter->flags |= IGB_FLAG_HAS_MSIX; 1128 1129 /* Number of supported queues. */ 1130 adapter->num_rx_queues = adapter->rss_queues; 1131 if (adapter->vfs_allocated_count) 1132 adapter->num_tx_queues = 1; 1133 else 1134 adapter->num_tx_queues = adapter->rss_queues; 1135 1136 /* start with one vector for every Rx queue */ 1137 numvecs = adapter->num_rx_queues; 1138 1139 /* if Tx handler is separate add 1 for every Tx queue */ 1140 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1141 numvecs += adapter->num_tx_queues; 1142 1143 /* store the number of vectors reserved for queues */ 1144 adapter->num_q_vectors = numvecs; 1145 1146 /* add 1 vector for link status interrupts */ 1147 numvecs++; 1148 for (i = 0; i < numvecs; i++) 1149 adapter->msix_entries[i].entry = i; 1150 1151 err = pci_enable_msix_range(adapter->pdev, 1152 adapter->msix_entries, 1153 numvecs, 1154 numvecs); 1155 if (err > 0) 1156 return; 1157 1158 igb_reset_interrupt_capability(adapter); 1159 1160 /* If we can't do MSI-X, try MSI */ 1161 msi_only: 1162 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1163 #ifdef CONFIG_PCI_IOV 1164 /* disable SR-IOV for non MSI-X configurations */ 1165 if (adapter->vf_data) { 1166 struct e1000_hw *hw = &adapter->hw; 1167 /* disable iov and allow time for transactions to clear */ 1168 pci_disable_sriov(adapter->pdev); 1169 msleep(500); 1170 1171 kfree(adapter->vf_mac_list); 1172 adapter->vf_mac_list = NULL; 1173 kfree(adapter->vf_data); 1174 adapter->vf_data = NULL; 1175 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1176 wrfl(); 1177 msleep(100); 1178 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1179 } 1180 #endif 1181 adapter->vfs_allocated_count = 0; 1182 adapter->rss_queues = 1; 1183 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1184 adapter->num_rx_queues = 1; 1185 adapter->num_tx_queues = 1; 1186 adapter->num_q_vectors = 1; 1187 if (!pci_enable_msi(adapter->pdev)) 1188 adapter->flags |= IGB_FLAG_HAS_MSI; 1189 } 1190 1191 static void igb_add_ring(struct igb_ring *ring, 1192 struct igb_ring_container *head) 1193 { 1194 head->ring = ring; 1195 head->count++; 1196 } 1197 1198 /** 1199 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1200 * @adapter: board private structure to initialize 1201 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1202 * @v_idx: index of vector in adapter struct 1203 * @txr_count: total number of Tx rings to allocate 1204 * @txr_idx: index of first Tx ring to allocate 1205 * @rxr_count: total number of Rx rings to allocate 1206 * @rxr_idx: index of first Rx ring to allocate 1207 * 1208 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1209 **/ 1210 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1211 int v_count, int v_idx, 1212 int txr_count, int txr_idx, 1213 int rxr_count, int rxr_idx) 1214 { 1215 struct igb_q_vector *q_vector; 1216 struct igb_ring *ring; 1217 int ring_count, size; 1218 1219 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1220 if (txr_count > 1 || rxr_count > 1) 1221 return -ENOMEM; 1222 1223 ring_count = txr_count + rxr_count; 1224 size = sizeof(struct igb_q_vector) + 1225 (sizeof(struct igb_ring) * ring_count); 1226 1227 /* allocate q_vector and rings */ 1228 q_vector = adapter->q_vector[v_idx]; 1229 if (!q_vector) { 1230 q_vector = kzalloc(size, GFP_KERNEL); 1231 } else if (size > ksize(q_vector)) { 1232 kfree_rcu(q_vector, rcu); 1233 q_vector = kzalloc(size, GFP_KERNEL); 1234 } else { 1235 memset(q_vector, 0, size); 1236 } 1237 if (!q_vector) 1238 return -ENOMEM; 1239 1240 /* initialize NAPI */ 1241 netif_napi_add(adapter->netdev, &q_vector->napi, 1242 igb_poll, 64); 1243 1244 /* tie q_vector and adapter together */ 1245 adapter->q_vector[v_idx] = q_vector; 1246 q_vector->adapter = adapter; 1247 1248 /* initialize work limits */ 1249 q_vector->tx.work_limit = adapter->tx_work_limit; 1250 1251 /* initialize ITR configuration */ 1252 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1253 q_vector->itr_val = IGB_START_ITR; 1254 1255 /* initialize pointer to rings */ 1256 ring = q_vector->ring; 1257 1258 /* intialize ITR */ 1259 if (rxr_count) { 1260 /* rx or rx/tx vector */ 1261 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1262 q_vector->itr_val = adapter->rx_itr_setting; 1263 } else { 1264 /* tx only vector */ 1265 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1266 q_vector->itr_val = adapter->tx_itr_setting; 1267 } 1268 1269 if (txr_count) { 1270 /* assign generic ring traits */ 1271 ring->dev = &adapter->pdev->dev; 1272 ring->netdev = adapter->netdev; 1273 1274 /* configure backlink on ring */ 1275 ring->q_vector = q_vector; 1276 1277 /* update q_vector Tx values */ 1278 igb_add_ring(ring, &q_vector->tx); 1279 1280 /* For 82575, context index must be unique per ring. */ 1281 if (adapter->hw.mac.type == e1000_82575) 1282 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1283 1284 /* apply Tx specific ring traits */ 1285 ring->count = adapter->tx_ring_count; 1286 ring->queue_index = txr_idx; 1287 1288 ring->cbs_enable = false; 1289 ring->idleslope = 0; 1290 ring->sendslope = 0; 1291 ring->hicredit = 0; 1292 ring->locredit = 0; 1293 1294 u64_stats_init(&ring->tx_syncp); 1295 u64_stats_init(&ring->tx_syncp2); 1296 1297 /* assign ring to adapter */ 1298 adapter->tx_ring[txr_idx] = ring; 1299 1300 /* push pointer to next ring */ 1301 ring++; 1302 } 1303 1304 if (rxr_count) { 1305 /* assign generic ring traits */ 1306 ring->dev = &adapter->pdev->dev; 1307 ring->netdev = adapter->netdev; 1308 1309 /* configure backlink on ring */ 1310 ring->q_vector = q_vector; 1311 1312 /* update q_vector Rx values */ 1313 igb_add_ring(ring, &q_vector->rx); 1314 1315 /* set flag indicating ring supports SCTP checksum offload */ 1316 if (adapter->hw.mac.type >= e1000_82576) 1317 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1318 1319 /* On i350, i354, i210, and i211, loopback VLAN packets 1320 * have the tag byte-swapped. 1321 */ 1322 if (adapter->hw.mac.type >= e1000_i350) 1323 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1324 1325 /* apply Rx specific ring traits */ 1326 ring->count = adapter->rx_ring_count; 1327 ring->queue_index = rxr_idx; 1328 1329 u64_stats_init(&ring->rx_syncp); 1330 1331 /* assign ring to adapter */ 1332 adapter->rx_ring[rxr_idx] = ring; 1333 } 1334 1335 return 0; 1336 } 1337 1338 1339 /** 1340 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1341 * @adapter: board private structure to initialize 1342 * 1343 * We allocate one q_vector per queue interrupt. If allocation fails we 1344 * return -ENOMEM. 1345 **/ 1346 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1347 { 1348 int q_vectors = adapter->num_q_vectors; 1349 int rxr_remaining = adapter->num_rx_queues; 1350 int txr_remaining = adapter->num_tx_queues; 1351 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1352 int err; 1353 1354 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1355 for (; rxr_remaining; v_idx++) { 1356 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1357 0, 0, 1, rxr_idx); 1358 1359 if (err) 1360 goto err_out; 1361 1362 /* update counts and index */ 1363 rxr_remaining--; 1364 rxr_idx++; 1365 } 1366 } 1367 1368 for (; v_idx < q_vectors; v_idx++) { 1369 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1370 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1371 1372 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1373 tqpv, txr_idx, rqpv, rxr_idx); 1374 1375 if (err) 1376 goto err_out; 1377 1378 /* update counts and index */ 1379 rxr_remaining -= rqpv; 1380 txr_remaining -= tqpv; 1381 rxr_idx++; 1382 txr_idx++; 1383 } 1384 1385 return 0; 1386 1387 err_out: 1388 adapter->num_tx_queues = 0; 1389 adapter->num_rx_queues = 0; 1390 adapter->num_q_vectors = 0; 1391 1392 while (v_idx--) 1393 igb_free_q_vector(adapter, v_idx); 1394 1395 return -ENOMEM; 1396 } 1397 1398 /** 1399 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1400 * @adapter: board private structure to initialize 1401 * @msix: boolean value of MSIX capability 1402 * 1403 * This function initializes the interrupts and allocates all of the queues. 1404 **/ 1405 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1406 { 1407 struct pci_dev *pdev = adapter->pdev; 1408 int err; 1409 1410 igb_set_interrupt_capability(adapter, msix); 1411 1412 err = igb_alloc_q_vectors(adapter); 1413 if (err) { 1414 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1415 goto err_alloc_q_vectors; 1416 } 1417 1418 igb_cache_ring_register(adapter); 1419 1420 return 0; 1421 1422 err_alloc_q_vectors: 1423 igb_reset_interrupt_capability(adapter); 1424 return err; 1425 } 1426 1427 /** 1428 * igb_request_irq - initialize interrupts 1429 * @adapter: board private structure to initialize 1430 * 1431 * Attempts to configure interrupts using the best available 1432 * capabilities of the hardware and kernel. 1433 **/ 1434 static int igb_request_irq(struct igb_adapter *adapter) 1435 { 1436 struct net_device *netdev = adapter->netdev; 1437 struct pci_dev *pdev = adapter->pdev; 1438 int err = 0; 1439 1440 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1441 err = igb_request_msix(adapter); 1442 if (!err) 1443 goto request_done; 1444 /* fall back to MSI */ 1445 igb_free_all_tx_resources(adapter); 1446 igb_free_all_rx_resources(adapter); 1447 1448 igb_clear_interrupt_scheme(adapter); 1449 err = igb_init_interrupt_scheme(adapter, false); 1450 if (err) 1451 goto request_done; 1452 1453 igb_setup_all_tx_resources(adapter); 1454 igb_setup_all_rx_resources(adapter); 1455 igb_configure(adapter); 1456 } 1457 1458 igb_assign_vector(adapter->q_vector[0], 0); 1459 1460 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1461 err = request_irq(pdev->irq, igb_intr_msi, 0, 1462 netdev->name, adapter); 1463 if (!err) 1464 goto request_done; 1465 1466 /* fall back to legacy interrupts */ 1467 igb_reset_interrupt_capability(adapter); 1468 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1469 } 1470 1471 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1472 netdev->name, adapter); 1473 1474 if (err) 1475 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1476 err); 1477 1478 request_done: 1479 return err; 1480 } 1481 1482 static void igb_free_irq(struct igb_adapter *adapter) 1483 { 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 int vector = 0, i; 1486 1487 free_irq(adapter->msix_entries[vector++].vector, adapter); 1488 1489 for (i = 0; i < adapter->num_q_vectors; i++) 1490 free_irq(adapter->msix_entries[vector++].vector, 1491 adapter->q_vector[i]); 1492 } else { 1493 free_irq(adapter->pdev->irq, adapter); 1494 } 1495 } 1496 1497 /** 1498 * igb_irq_disable - Mask off interrupt generation on the NIC 1499 * @adapter: board private structure 1500 **/ 1501 static void igb_irq_disable(struct igb_adapter *adapter) 1502 { 1503 struct e1000_hw *hw = &adapter->hw; 1504 1505 /* we need to be careful when disabling interrupts. The VFs are also 1506 * mapped into these registers and so clearing the bits can cause 1507 * issues on the VF drivers so we only need to clear what we set 1508 */ 1509 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1510 u32 regval = rd32(E1000_EIAM); 1511 1512 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1513 wr32(E1000_EIMC, adapter->eims_enable_mask); 1514 regval = rd32(E1000_EIAC); 1515 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1516 } 1517 1518 wr32(E1000_IAM, 0); 1519 wr32(E1000_IMC, ~0); 1520 wrfl(); 1521 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1522 int i; 1523 1524 for (i = 0; i < adapter->num_q_vectors; i++) 1525 synchronize_irq(adapter->msix_entries[i].vector); 1526 } else { 1527 synchronize_irq(adapter->pdev->irq); 1528 } 1529 } 1530 1531 /** 1532 * igb_irq_enable - Enable default interrupt generation settings 1533 * @adapter: board private structure 1534 **/ 1535 static void igb_irq_enable(struct igb_adapter *adapter) 1536 { 1537 struct e1000_hw *hw = &adapter->hw; 1538 1539 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1540 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1541 u32 regval = rd32(E1000_EIAC); 1542 1543 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1544 regval = rd32(E1000_EIAM); 1545 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1546 wr32(E1000_EIMS, adapter->eims_enable_mask); 1547 if (adapter->vfs_allocated_count) { 1548 wr32(E1000_MBVFIMR, 0xFF); 1549 ims |= E1000_IMS_VMMB; 1550 } 1551 wr32(E1000_IMS, ims); 1552 } else { 1553 wr32(E1000_IMS, IMS_ENABLE_MASK | 1554 E1000_IMS_DRSTA); 1555 wr32(E1000_IAM, IMS_ENABLE_MASK | 1556 E1000_IMS_DRSTA); 1557 } 1558 } 1559 1560 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1561 { 1562 struct e1000_hw *hw = &adapter->hw; 1563 u16 pf_id = adapter->vfs_allocated_count; 1564 u16 vid = adapter->hw.mng_cookie.vlan_id; 1565 u16 old_vid = adapter->mng_vlan_id; 1566 1567 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1568 /* add VID to filter table */ 1569 igb_vfta_set(hw, vid, pf_id, true, true); 1570 adapter->mng_vlan_id = vid; 1571 } else { 1572 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1573 } 1574 1575 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1576 (vid != old_vid) && 1577 !test_bit(old_vid, adapter->active_vlans)) { 1578 /* remove VID from filter table */ 1579 igb_vfta_set(hw, vid, pf_id, false, true); 1580 } 1581 } 1582 1583 /** 1584 * igb_release_hw_control - release control of the h/w to f/w 1585 * @adapter: address of board private structure 1586 * 1587 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1588 * For ASF and Pass Through versions of f/w this means that the 1589 * driver is no longer loaded. 1590 **/ 1591 static void igb_release_hw_control(struct igb_adapter *adapter) 1592 { 1593 struct e1000_hw *hw = &adapter->hw; 1594 u32 ctrl_ext; 1595 1596 /* Let firmware take over control of h/w */ 1597 ctrl_ext = rd32(E1000_CTRL_EXT); 1598 wr32(E1000_CTRL_EXT, 1599 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1600 } 1601 1602 /** 1603 * igb_get_hw_control - get control of the h/w from f/w 1604 * @adapter: address of board private structure 1605 * 1606 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1607 * For ASF and Pass Through versions of f/w this means that 1608 * the driver is loaded. 1609 **/ 1610 static void igb_get_hw_control(struct igb_adapter *adapter) 1611 { 1612 struct e1000_hw *hw = &adapter->hw; 1613 u32 ctrl_ext; 1614 1615 /* Let firmware know the driver has taken over */ 1616 ctrl_ext = rd32(E1000_CTRL_EXT); 1617 wr32(E1000_CTRL_EXT, 1618 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1619 } 1620 1621 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1622 { 1623 struct net_device *netdev = adapter->netdev; 1624 struct e1000_hw *hw = &adapter->hw; 1625 1626 WARN_ON(hw->mac.type != e1000_i210); 1627 1628 if (enable) 1629 adapter->flags |= IGB_FLAG_FQTSS; 1630 else 1631 adapter->flags &= ~IGB_FLAG_FQTSS; 1632 1633 if (netif_running(netdev)) 1634 schedule_work(&adapter->reset_task); 1635 } 1636 1637 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1638 { 1639 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1640 } 1641 1642 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1643 enum tx_queue_prio prio) 1644 { 1645 u32 val; 1646 1647 WARN_ON(hw->mac.type != e1000_i210); 1648 WARN_ON(queue < 0 || queue > 4); 1649 1650 val = rd32(E1000_I210_TXDCTL(queue)); 1651 1652 if (prio == TX_QUEUE_PRIO_HIGH) 1653 val |= E1000_TXDCTL_PRIORITY; 1654 else 1655 val &= ~E1000_TXDCTL_PRIORITY; 1656 1657 wr32(E1000_I210_TXDCTL(queue), val); 1658 } 1659 1660 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1661 { 1662 u32 val; 1663 1664 WARN_ON(hw->mac.type != e1000_i210); 1665 WARN_ON(queue < 0 || queue > 1); 1666 1667 val = rd32(E1000_I210_TQAVCC(queue)); 1668 1669 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1670 val |= E1000_TQAVCC_QUEUEMODE; 1671 else 1672 val &= ~E1000_TQAVCC_QUEUEMODE; 1673 1674 wr32(E1000_I210_TQAVCC(queue), val); 1675 } 1676 1677 /** 1678 * igb_configure_cbs - Configure Credit-Based Shaper (CBS) 1679 * @adapter: pointer to adapter struct 1680 * @queue: queue number 1681 * @enable: true = enable CBS, false = disable CBS 1682 * @idleslope: idleSlope in kbps 1683 * @sendslope: sendSlope in kbps 1684 * @hicredit: hiCredit in bytes 1685 * @locredit: loCredit in bytes 1686 * 1687 * Configure CBS for a given hardware queue. When disabling, idleslope, 1688 * sendslope, hicredit, locredit arguments are ignored. Returns 0 if 1689 * success. Negative otherwise. 1690 **/ 1691 static void igb_configure_cbs(struct igb_adapter *adapter, int queue, 1692 bool enable, int idleslope, int sendslope, 1693 int hicredit, int locredit) 1694 { 1695 struct net_device *netdev = adapter->netdev; 1696 struct e1000_hw *hw = &adapter->hw; 1697 u32 tqavcc; 1698 u16 value; 1699 1700 WARN_ON(hw->mac.type != e1000_i210); 1701 WARN_ON(queue < 0 || queue > 1); 1702 1703 if (enable) { 1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1706 1707 /* According to i210 datasheet section 7.2.7.7, we should set 1708 * the 'idleSlope' field from TQAVCC register following the 1709 * equation: 1710 * 1711 * For 100 Mbps link speed: 1712 * 1713 * value = BW * 0x7735 * 0.2 (E1) 1714 * 1715 * For 1000Mbps link speed: 1716 * 1717 * value = BW * 0x7735 * 2 (E2) 1718 * 1719 * E1 and E2 can be merged into one equation as shown below. 1720 * Note that 'link-speed' is in Mbps. 1721 * 1722 * value = BW * 0x7735 * 2 * link-speed 1723 * -------------- (E3) 1724 * 1000 1725 * 1726 * 'BW' is the percentage bandwidth out of full link speed 1727 * which can be found with the following equation. Note that 1728 * idleSlope here is the parameter from this function which 1729 * is in kbps. 1730 * 1731 * BW = idleSlope 1732 * ----------------- (E4) 1733 * link-speed * 1000 1734 * 1735 * That said, we can come up with a generic equation to 1736 * calculate the value we should set it TQAVCC register by 1737 * replacing 'BW' in E3 by E4. The resulting equation is: 1738 * 1739 * value = idleSlope * 0x7735 * 2 * link-speed 1740 * ----------------- -------------- (E5) 1741 * link-speed * 1000 1000 1742 * 1743 * 'link-speed' is present in both sides of the fraction so 1744 * it is canceled out. The final equation is the following: 1745 * 1746 * value = idleSlope * 61034 1747 * ----------------- (E6) 1748 * 1000000 1749 * 1750 * NOTE: For i210, given the above, we can see that idleslope 1751 * is represented in 16.38431 kbps units by the value at 1752 * the TQAVCC register (1Gbps / 61034), which reduces 1753 * the granularity for idleslope increments. 1754 * For instance, if you want to configure a 2576kbps 1755 * idleslope, the value to be written on the register 1756 * would have to be 157.23. If rounded down, you end 1757 * up with less bandwidth available than originally 1758 * required (~2572 kbps). If rounded up, you end up 1759 * with a higher bandwidth (~2589 kbps). Below the 1760 * approach we take is to always round up the 1761 * calculated value, so the resulting bandwidth might 1762 * be slightly higher for some configurations. 1763 */ 1764 value = DIV_ROUND_UP_ULL(idleslope * 61034ULL, 1000000); 1765 1766 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1767 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1768 tqavcc |= value; 1769 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1770 1771 wr32(E1000_I210_TQAVHC(queue), 0x80000000 + hicredit * 0x7735); 1772 } else { 1773 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1774 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1775 1776 /* Set idleSlope to zero. */ 1777 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1778 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1779 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1780 1781 /* Set hiCredit to zero. */ 1782 wr32(E1000_I210_TQAVHC(queue), 0); 1783 } 1784 1785 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1786 * CBS are not configurable by software so we don't do any 'controller 1787 * configuration' in respect to these parameters. 1788 */ 1789 1790 netdev_dbg(netdev, "CBS %s: queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1791 (enable) ? "enabled" : "disabled", queue, 1792 idleslope, sendslope, hicredit, locredit); 1793 } 1794 1795 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1796 bool enable, int idleslope, int sendslope, 1797 int hicredit, int locredit) 1798 { 1799 struct igb_ring *ring; 1800 1801 if (queue < 0 || queue > adapter->num_tx_queues) 1802 return -EINVAL; 1803 1804 ring = adapter->tx_ring[queue]; 1805 1806 ring->cbs_enable = enable; 1807 ring->idleslope = idleslope; 1808 ring->sendslope = sendslope; 1809 ring->hicredit = hicredit; 1810 ring->locredit = locredit; 1811 1812 return 0; 1813 } 1814 1815 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1816 { 1817 struct igb_ring *ring; 1818 int i; 1819 1820 for (i = 0; i < adapter->num_tx_queues; i++) { 1821 ring = adapter->tx_ring[i]; 1822 1823 if (ring->cbs_enable) 1824 return true; 1825 } 1826 1827 return false; 1828 } 1829 1830 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1831 { 1832 struct net_device *netdev = adapter->netdev; 1833 struct e1000_hw *hw = &adapter->hw; 1834 u32 val; 1835 1836 /* Only i210 controller supports changing the transmission mode. */ 1837 if (hw->mac.type != e1000_i210) 1838 return; 1839 1840 if (is_fqtss_enabled(adapter)) { 1841 int i, max_queue; 1842 1843 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1844 * set data fetch arbitration to 'round robin' and set data 1845 * transfer arbitration to 'credit shaper algorithm. 1846 */ 1847 val = rd32(E1000_I210_TQAVCTRL); 1848 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_DATATRANARB; 1849 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1850 wr32(E1000_I210_TQAVCTRL, val); 1851 1852 /* Configure Tx and Rx packet buffers sizes as described in 1853 * i210 datasheet section 7.2.7.7. 1854 */ 1855 val = rd32(E1000_TXPBS); 1856 val &= ~I210_TXPBSIZE_MASK; 1857 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1858 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1859 wr32(E1000_TXPBS, val); 1860 1861 val = rd32(E1000_RXPBS); 1862 val &= ~I210_RXPBSIZE_MASK; 1863 val |= I210_RXPBSIZE_PB_32KB; 1864 wr32(E1000_RXPBS, val); 1865 1866 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1867 * register should not exceed the buffer size programmed in 1868 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1869 * so according to the datasheet we should set MAX_TPKT_SIZE to 1870 * 4kB / 64. 1871 * 1872 * However, when we do so, no frame from queue 2 and 3 are 1873 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1874 * or _equal_ to the buffer size programmed in TXPBS. For this 1875 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1876 */ 1877 val = (4096 - 1) / 64; 1878 wr32(E1000_I210_DTXMXPKTSZ, val); 1879 1880 /* Since FQTSS mode is enabled, apply any CBS configuration 1881 * previously set. If no previous CBS configuration has been 1882 * done, then the initial configuration is applied, which means 1883 * CBS is disabled. 1884 */ 1885 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1886 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1887 1888 for (i = 0; i < max_queue; i++) { 1889 struct igb_ring *ring = adapter->tx_ring[i]; 1890 1891 igb_configure_cbs(adapter, i, ring->cbs_enable, 1892 ring->idleslope, ring->sendslope, 1893 ring->hicredit, ring->locredit); 1894 } 1895 } else { 1896 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1897 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1898 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1899 1900 val = rd32(E1000_I210_TQAVCTRL); 1901 /* According to Section 8.12.21, the other flags we've set when 1902 * enabling FQTSS are not relevant when disabling FQTSS so we 1903 * don't set they here. 1904 */ 1905 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1906 wr32(E1000_I210_TQAVCTRL, val); 1907 } 1908 1909 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1910 "enabled" : "disabled"); 1911 } 1912 1913 /** 1914 * igb_configure - configure the hardware for RX and TX 1915 * @adapter: private board structure 1916 **/ 1917 static void igb_configure(struct igb_adapter *adapter) 1918 { 1919 struct net_device *netdev = adapter->netdev; 1920 int i; 1921 1922 igb_get_hw_control(adapter); 1923 igb_set_rx_mode(netdev); 1924 igb_setup_tx_mode(adapter); 1925 1926 igb_restore_vlan(adapter); 1927 1928 igb_setup_tctl(adapter); 1929 igb_setup_mrqc(adapter); 1930 igb_setup_rctl(adapter); 1931 1932 igb_nfc_filter_restore(adapter); 1933 igb_configure_tx(adapter); 1934 igb_configure_rx(adapter); 1935 1936 igb_rx_fifo_flush_82575(&adapter->hw); 1937 1938 /* call igb_desc_unused which always leaves 1939 * at least 1 descriptor unused to make sure 1940 * next_to_use != next_to_clean 1941 */ 1942 for (i = 0; i < adapter->num_rx_queues; i++) { 1943 struct igb_ring *ring = adapter->rx_ring[i]; 1944 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1945 } 1946 } 1947 1948 /** 1949 * igb_power_up_link - Power up the phy/serdes link 1950 * @adapter: address of board private structure 1951 **/ 1952 void igb_power_up_link(struct igb_adapter *adapter) 1953 { 1954 igb_reset_phy(&adapter->hw); 1955 1956 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1957 igb_power_up_phy_copper(&adapter->hw); 1958 else 1959 igb_power_up_serdes_link_82575(&adapter->hw); 1960 1961 igb_setup_link(&adapter->hw); 1962 } 1963 1964 /** 1965 * igb_power_down_link - Power down the phy/serdes link 1966 * @adapter: address of board private structure 1967 */ 1968 static void igb_power_down_link(struct igb_adapter *adapter) 1969 { 1970 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1971 igb_power_down_phy_copper_82575(&adapter->hw); 1972 else 1973 igb_shutdown_serdes_link_82575(&adapter->hw); 1974 } 1975 1976 /** 1977 * Detect and switch function for Media Auto Sense 1978 * @adapter: address of the board private structure 1979 **/ 1980 static void igb_check_swap_media(struct igb_adapter *adapter) 1981 { 1982 struct e1000_hw *hw = &adapter->hw; 1983 u32 ctrl_ext, connsw; 1984 bool swap_now = false; 1985 1986 ctrl_ext = rd32(E1000_CTRL_EXT); 1987 connsw = rd32(E1000_CONNSW); 1988 1989 /* need to live swap if current media is copper and we have fiber/serdes 1990 * to go to. 1991 */ 1992 1993 if ((hw->phy.media_type == e1000_media_type_copper) && 1994 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1995 swap_now = true; 1996 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1997 /* copper signal takes time to appear */ 1998 if (adapter->copper_tries < 4) { 1999 adapter->copper_tries++; 2000 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2001 wr32(E1000_CONNSW, connsw); 2002 return; 2003 } else { 2004 adapter->copper_tries = 0; 2005 if ((connsw & E1000_CONNSW_PHYSD) && 2006 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2007 swap_now = true; 2008 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2009 wr32(E1000_CONNSW, connsw); 2010 } 2011 } 2012 } 2013 2014 if (!swap_now) 2015 return; 2016 2017 switch (hw->phy.media_type) { 2018 case e1000_media_type_copper: 2019 netdev_info(adapter->netdev, 2020 "MAS: changing media to fiber/serdes\n"); 2021 ctrl_ext |= 2022 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2023 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2024 adapter->copper_tries = 0; 2025 break; 2026 case e1000_media_type_internal_serdes: 2027 case e1000_media_type_fiber: 2028 netdev_info(adapter->netdev, 2029 "MAS: changing media to copper\n"); 2030 ctrl_ext &= 2031 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2032 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2033 break; 2034 default: 2035 /* shouldn't get here during regular operation */ 2036 netdev_err(adapter->netdev, 2037 "AMS: Invalid media type found, returning\n"); 2038 break; 2039 } 2040 wr32(E1000_CTRL_EXT, ctrl_ext); 2041 } 2042 2043 /** 2044 * igb_up - Open the interface and prepare it to handle traffic 2045 * @adapter: board private structure 2046 **/ 2047 int igb_up(struct igb_adapter *adapter) 2048 { 2049 struct e1000_hw *hw = &adapter->hw; 2050 int i; 2051 2052 /* hardware has been reset, we need to reload some things */ 2053 igb_configure(adapter); 2054 2055 clear_bit(__IGB_DOWN, &adapter->state); 2056 2057 for (i = 0; i < adapter->num_q_vectors; i++) 2058 napi_enable(&(adapter->q_vector[i]->napi)); 2059 2060 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2061 igb_configure_msix(adapter); 2062 else 2063 igb_assign_vector(adapter->q_vector[0], 0); 2064 2065 /* Clear any pending interrupts. */ 2066 rd32(E1000_ICR); 2067 igb_irq_enable(adapter); 2068 2069 /* notify VFs that reset has been completed */ 2070 if (adapter->vfs_allocated_count) { 2071 u32 reg_data = rd32(E1000_CTRL_EXT); 2072 2073 reg_data |= E1000_CTRL_EXT_PFRSTD; 2074 wr32(E1000_CTRL_EXT, reg_data); 2075 } 2076 2077 netif_tx_start_all_queues(adapter->netdev); 2078 2079 /* start the watchdog. */ 2080 hw->mac.get_link_status = 1; 2081 schedule_work(&adapter->watchdog_task); 2082 2083 if ((adapter->flags & IGB_FLAG_EEE) && 2084 (!hw->dev_spec._82575.eee_disable)) 2085 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2086 2087 return 0; 2088 } 2089 2090 void igb_down(struct igb_adapter *adapter) 2091 { 2092 struct net_device *netdev = adapter->netdev; 2093 struct e1000_hw *hw = &adapter->hw; 2094 u32 tctl, rctl; 2095 int i; 2096 2097 /* signal that we're down so the interrupt handler does not 2098 * reschedule our watchdog timer 2099 */ 2100 set_bit(__IGB_DOWN, &adapter->state); 2101 2102 /* disable receives in the hardware */ 2103 rctl = rd32(E1000_RCTL); 2104 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2105 /* flush and sleep below */ 2106 2107 igb_nfc_filter_exit(adapter); 2108 2109 netif_carrier_off(netdev); 2110 netif_tx_stop_all_queues(netdev); 2111 2112 /* disable transmits in the hardware */ 2113 tctl = rd32(E1000_TCTL); 2114 tctl &= ~E1000_TCTL_EN; 2115 wr32(E1000_TCTL, tctl); 2116 /* flush both disables and wait for them to finish */ 2117 wrfl(); 2118 usleep_range(10000, 11000); 2119 2120 igb_irq_disable(adapter); 2121 2122 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2123 2124 for (i = 0; i < adapter->num_q_vectors; i++) { 2125 if (adapter->q_vector[i]) { 2126 napi_synchronize(&adapter->q_vector[i]->napi); 2127 napi_disable(&adapter->q_vector[i]->napi); 2128 } 2129 } 2130 2131 del_timer_sync(&adapter->watchdog_timer); 2132 del_timer_sync(&adapter->phy_info_timer); 2133 2134 /* record the stats before reset*/ 2135 spin_lock(&adapter->stats64_lock); 2136 igb_update_stats(adapter); 2137 spin_unlock(&adapter->stats64_lock); 2138 2139 adapter->link_speed = 0; 2140 adapter->link_duplex = 0; 2141 2142 if (!pci_channel_offline(adapter->pdev)) 2143 igb_reset(adapter); 2144 2145 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2146 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2147 2148 igb_clean_all_tx_rings(adapter); 2149 igb_clean_all_rx_rings(adapter); 2150 #ifdef CONFIG_IGB_DCA 2151 2152 /* since we reset the hardware DCA settings were cleared */ 2153 igb_setup_dca(adapter); 2154 #endif 2155 } 2156 2157 void igb_reinit_locked(struct igb_adapter *adapter) 2158 { 2159 WARN_ON(in_interrupt()); 2160 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2161 usleep_range(1000, 2000); 2162 igb_down(adapter); 2163 igb_up(adapter); 2164 clear_bit(__IGB_RESETTING, &adapter->state); 2165 } 2166 2167 /** igb_enable_mas - Media Autosense re-enable after swap 2168 * 2169 * @adapter: adapter struct 2170 **/ 2171 static void igb_enable_mas(struct igb_adapter *adapter) 2172 { 2173 struct e1000_hw *hw = &adapter->hw; 2174 u32 connsw = rd32(E1000_CONNSW); 2175 2176 /* configure for SerDes media detect */ 2177 if ((hw->phy.media_type == e1000_media_type_copper) && 2178 (!(connsw & E1000_CONNSW_SERDESD))) { 2179 connsw |= E1000_CONNSW_ENRGSRC; 2180 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2181 wr32(E1000_CONNSW, connsw); 2182 wrfl(); 2183 } 2184 } 2185 2186 void igb_reset(struct igb_adapter *adapter) 2187 { 2188 struct pci_dev *pdev = adapter->pdev; 2189 struct e1000_hw *hw = &adapter->hw; 2190 struct e1000_mac_info *mac = &hw->mac; 2191 struct e1000_fc_info *fc = &hw->fc; 2192 u32 pba, hwm; 2193 2194 /* Repartition Pba for greater than 9k mtu 2195 * To take effect CTRL.RST is required. 2196 */ 2197 switch (mac->type) { 2198 case e1000_i350: 2199 case e1000_i354: 2200 case e1000_82580: 2201 pba = rd32(E1000_RXPBS); 2202 pba = igb_rxpbs_adjust_82580(pba); 2203 break; 2204 case e1000_82576: 2205 pba = rd32(E1000_RXPBS); 2206 pba &= E1000_RXPBS_SIZE_MASK_82576; 2207 break; 2208 case e1000_82575: 2209 case e1000_i210: 2210 case e1000_i211: 2211 default: 2212 pba = E1000_PBA_34K; 2213 break; 2214 } 2215 2216 if (mac->type == e1000_82575) { 2217 u32 min_rx_space, min_tx_space, needed_tx_space; 2218 2219 /* write Rx PBA so that hardware can report correct Tx PBA */ 2220 wr32(E1000_PBA, pba); 2221 2222 /* To maintain wire speed transmits, the Tx FIFO should be 2223 * large enough to accommodate two full transmit packets, 2224 * rounded up to the next 1KB and expressed in KB. Likewise, 2225 * the Rx FIFO should be large enough to accommodate at least 2226 * one full receive packet and is similarly rounded up and 2227 * expressed in KB. 2228 */ 2229 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2230 2231 /* The Tx FIFO also stores 16 bytes of information about the Tx 2232 * but don't include Ethernet FCS because hardware appends it. 2233 * We only need to round down to the nearest 512 byte block 2234 * count since the value we care about is 2 frames, not 1. 2235 */ 2236 min_tx_space = adapter->max_frame_size; 2237 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2238 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2239 2240 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2241 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2242 2243 /* If current Tx allocation is less than the min Tx FIFO size, 2244 * and the min Tx FIFO size is less than the current Rx FIFO 2245 * allocation, take space away from current Rx allocation. 2246 */ 2247 if (needed_tx_space < pba) { 2248 pba -= needed_tx_space; 2249 2250 /* if short on Rx space, Rx wins and must trump Tx 2251 * adjustment 2252 */ 2253 if (pba < min_rx_space) 2254 pba = min_rx_space; 2255 } 2256 2257 /* adjust PBA for jumbo frames */ 2258 wr32(E1000_PBA, pba); 2259 } 2260 2261 /* flow control settings 2262 * The high water mark must be low enough to fit one full frame 2263 * after transmitting the pause frame. As such we must have enough 2264 * space to allow for us to complete our current transmit and then 2265 * receive the frame that is in progress from the link partner. 2266 * Set it to: 2267 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2268 */ 2269 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2270 2271 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2272 fc->low_water = fc->high_water - 16; 2273 fc->pause_time = 0xFFFF; 2274 fc->send_xon = 1; 2275 fc->current_mode = fc->requested_mode; 2276 2277 /* disable receive for all VFs and wait one second */ 2278 if (adapter->vfs_allocated_count) { 2279 int i; 2280 2281 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2282 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2283 2284 /* ping all the active vfs to let them know we are going down */ 2285 igb_ping_all_vfs(adapter); 2286 2287 /* disable transmits and receives */ 2288 wr32(E1000_VFRE, 0); 2289 wr32(E1000_VFTE, 0); 2290 } 2291 2292 /* Allow time for pending master requests to run */ 2293 hw->mac.ops.reset_hw(hw); 2294 wr32(E1000_WUC, 0); 2295 2296 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2297 /* need to resetup here after media swap */ 2298 adapter->ei.get_invariants(hw); 2299 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2300 } 2301 if ((mac->type == e1000_82575) && 2302 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2303 igb_enable_mas(adapter); 2304 } 2305 if (hw->mac.ops.init_hw(hw)) 2306 dev_err(&pdev->dev, "Hardware Error\n"); 2307 2308 /* RAR registers were cleared during init_hw, clear mac table */ 2309 igb_flush_mac_table(adapter); 2310 __dev_uc_unsync(adapter->netdev, NULL); 2311 2312 /* Recover default RAR entry */ 2313 igb_set_default_mac_filter(adapter); 2314 2315 /* Flow control settings reset on hardware reset, so guarantee flow 2316 * control is off when forcing speed. 2317 */ 2318 if (!hw->mac.autoneg) 2319 igb_force_mac_fc(hw); 2320 2321 igb_init_dmac(adapter, pba); 2322 #ifdef CONFIG_IGB_HWMON 2323 /* Re-initialize the thermal sensor on i350 devices. */ 2324 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2325 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2326 /* If present, re-initialize the external thermal sensor 2327 * interface. 2328 */ 2329 if (adapter->ets) 2330 mac->ops.init_thermal_sensor_thresh(hw); 2331 } 2332 } 2333 #endif 2334 /* Re-establish EEE setting */ 2335 if (hw->phy.media_type == e1000_media_type_copper) { 2336 switch (mac->type) { 2337 case e1000_i350: 2338 case e1000_i210: 2339 case e1000_i211: 2340 igb_set_eee_i350(hw, true, true); 2341 break; 2342 case e1000_i354: 2343 igb_set_eee_i354(hw, true, true); 2344 break; 2345 default: 2346 break; 2347 } 2348 } 2349 if (!netif_running(adapter->netdev)) 2350 igb_power_down_link(adapter); 2351 2352 igb_update_mng_vlan(adapter); 2353 2354 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2355 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2356 2357 /* Re-enable PTP, where applicable. */ 2358 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2359 igb_ptp_reset(adapter); 2360 2361 igb_get_phy_info(hw); 2362 } 2363 2364 static netdev_features_t igb_fix_features(struct net_device *netdev, 2365 netdev_features_t features) 2366 { 2367 /* Since there is no support for separate Rx/Tx vlan accel 2368 * enable/disable make sure Tx flag is always in same state as Rx. 2369 */ 2370 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2371 features |= NETIF_F_HW_VLAN_CTAG_TX; 2372 else 2373 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2374 2375 return features; 2376 } 2377 2378 static int igb_set_features(struct net_device *netdev, 2379 netdev_features_t features) 2380 { 2381 netdev_features_t changed = netdev->features ^ features; 2382 struct igb_adapter *adapter = netdev_priv(netdev); 2383 2384 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2385 igb_vlan_mode(netdev, features); 2386 2387 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2388 return 0; 2389 2390 if (!(features & NETIF_F_NTUPLE)) { 2391 struct hlist_node *node2; 2392 struct igb_nfc_filter *rule; 2393 2394 spin_lock(&adapter->nfc_lock); 2395 hlist_for_each_entry_safe(rule, node2, 2396 &adapter->nfc_filter_list, nfc_node) { 2397 igb_erase_filter(adapter, rule); 2398 hlist_del(&rule->nfc_node); 2399 kfree(rule); 2400 } 2401 spin_unlock(&adapter->nfc_lock); 2402 adapter->nfc_filter_count = 0; 2403 } 2404 2405 netdev->features = features; 2406 2407 if (netif_running(netdev)) 2408 igb_reinit_locked(adapter); 2409 else 2410 igb_reset(adapter); 2411 2412 return 0; 2413 } 2414 2415 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2416 struct net_device *dev, 2417 const unsigned char *addr, u16 vid, 2418 u16 flags) 2419 { 2420 /* guarantee we can provide a unique filter for the unicast address */ 2421 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2422 struct igb_adapter *adapter = netdev_priv(dev); 2423 int vfn = adapter->vfs_allocated_count; 2424 2425 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2426 return -ENOMEM; 2427 } 2428 2429 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2430 } 2431 2432 #define IGB_MAX_MAC_HDR_LEN 127 2433 #define IGB_MAX_NETWORK_HDR_LEN 511 2434 2435 static netdev_features_t 2436 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2437 netdev_features_t features) 2438 { 2439 unsigned int network_hdr_len, mac_hdr_len; 2440 2441 /* Make certain the headers can be described by a context descriptor */ 2442 mac_hdr_len = skb_network_header(skb) - skb->data; 2443 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2444 return features & ~(NETIF_F_HW_CSUM | 2445 NETIF_F_SCTP_CRC | 2446 NETIF_F_HW_VLAN_CTAG_TX | 2447 NETIF_F_TSO | 2448 NETIF_F_TSO6); 2449 2450 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2451 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2452 return features & ~(NETIF_F_HW_CSUM | 2453 NETIF_F_SCTP_CRC | 2454 NETIF_F_TSO | 2455 NETIF_F_TSO6); 2456 2457 /* We can only support IPV4 TSO in tunnels if we can mangle the 2458 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2459 */ 2460 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2461 features &= ~NETIF_F_TSO; 2462 2463 return features; 2464 } 2465 2466 static int igb_offload_cbs(struct igb_adapter *adapter, 2467 struct tc_cbs_qopt_offload *qopt) 2468 { 2469 struct e1000_hw *hw = &adapter->hw; 2470 int err; 2471 2472 /* CBS offloading is only supported by i210 controller. */ 2473 if (hw->mac.type != e1000_i210) 2474 return -EOPNOTSUPP; 2475 2476 /* CBS offloading is only supported by queue 0 and queue 1. */ 2477 if (qopt->queue < 0 || qopt->queue > 1) 2478 return -EINVAL; 2479 2480 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2481 qopt->idleslope, qopt->sendslope, 2482 qopt->hicredit, qopt->locredit); 2483 if (err) 2484 return err; 2485 2486 if (is_fqtss_enabled(adapter)) { 2487 igb_configure_cbs(adapter, qopt->queue, qopt->enable, 2488 qopt->idleslope, qopt->sendslope, 2489 qopt->hicredit, qopt->locredit); 2490 2491 if (!is_any_cbs_enabled(adapter)) 2492 enable_fqtss(adapter, false); 2493 2494 } else { 2495 enable_fqtss(adapter, true); 2496 } 2497 2498 return 0; 2499 } 2500 2501 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2502 void *type_data) 2503 { 2504 struct igb_adapter *adapter = netdev_priv(dev); 2505 2506 switch (type) { 2507 case TC_SETUP_QDISC_CBS: 2508 return igb_offload_cbs(adapter, type_data); 2509 2510 default: 2511 return -EOPNOTSUPP; 2512 } 2513 } 2514 2515 static const struct net_device_ops igb_netdev_ops = { 2516 .ndo_open = igb_open, 2517 .ndo_stop = igb_close, 2518 .ndo_start_xmit = igb_xmit_frame, 2519 .ndo_get_stats64 = igb_get_stats64, 2520 .ndo_set_rx_mode = igb_set_rx_mode, 2521 .ndo_set_mac_address = igb_set_mac, 2522 .ndo_change_mtu = igb_change_mtu, 2523 .ndo_do_ioctl = igb_ioctl, 2524 .ndo_tx_timeout = igb_tx_timeout, 2525 .ndo_validate_addr = eth_validate_addr, 2526 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2527 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2528 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2529 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2530 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2531 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2532 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2533 .ndo_get_vf_config = igb_ndo_get_vf_config, 2534 #ifdef CONFIG_NET_POLL_CONTROLLER 2535 .ndo_poll_controller = igb_netpoll, 2536 #endif 2537 .ndo_fix_features = igb_fix_features, 2538 .ndo_set_features = igb_set_features, 2539 .ndo_fdb_add = igb_ndo_fdb_add, 2540 .ndo_features_check = igb_features_check, 2541 .ndo_setup_tc = igb_setup_tc, 2542 }; 2543 2544 /** 2545 * igb_set_fw_version - Configure version string for ethtool 2546 * @adapter: adapter struct 2547 **/ 2548 void igb_set_fw_version(struct igb_adapter *adapter) 2549 { 2550 struct e1000_hw *hw = &adapter->hw; 2551 struct e1000_fw_version fw; 2552 2553 igb_get_fw_version(hw, &fw); 2554 2555 switch (hw->mac.type) { 2556 case e1000_i210: 2557 case e1000_i211: 2558 if (!(igb_get_flash_presence_i210(hw))) { 2559 snprintf(adapter->fw_version, 2560 sizeof(adapter->fw_version), 2561 "%2d.%2d-%d", 2562 fw.invm_major, fw.invm_minor, 2563 fw.invm_img_type); 2564 break; 2565 } 2566 /* fall through */ 2567 default: 2568 /* if option is rom valid, display its version too */ 2569 if (fw.or_valid) { 2570 snprintf(adapter->fw_version, 2571 sizeof(adapter->fw_version), 2572 "%d.%d, 0x%08x, %d.%d.%d", 2573 fw.eep_major, fw.eep_minor, fw.etrack_id, 2574 fw.or_major, fw.or_build, fw.or_patch); 2575 /* no option rom */ 2576 } else if (fw.etrack_id != 0X0000) { 2577 snprintf(adapter->fw_version, 2578 sizeof(adapter->fw_version), 2579 "%d.%d, 0x%08x", 2580 fw.eep_major, fw.eep_minor, fw.etrack_id); 2581 } else { 2582 snprintf(adapter->fw_version, 2583 sizeof(adapter->fw_version), 2584 "%d.%d.%d", 2585 fw.eep_major, fw.eep_minor, fw.eep_build); 2586 } 2587 break; 2588 } 2589 } 2590 2591 /** 2592 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2593 * 2594 * @adapter: adapter struct 2595 **/ 2596 static void igb_init_mas(struct igb_adapter *adapter) 2597 { 2598 struct e1000_hw *hw = &adapter->hw; 2599 u16 eeprom_data; 2600 2601 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2602 switch (hw->bus.func) { 2603 case E1000_FUNC_0: 2604 if (eeprom_data & IGB_MAS_ENABLE_0) { 2605 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2606 netdev_info(adapter->netdev, 2607 "MAS: Enabling Media Autosense for port %d\n", 2608 hw->bus.func); 2609 } 2610 break; 2611 case E1000_FUNC_1: 2612 if (eeprom_data & IGB_MAS_ENABLE_1) { 2613 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2614 netdev_info(adapter->netdev, 2615 "MAS: Enabling Media Autosense for port %d\n", 2616 hw->bus.func); 2617 } 2618 break; 2619 case E1000_FUNC_2: 2620 if (eeprom_data & IGB_MAS_ENABLE_2) { 2621 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2622 netdev_info(adapter->netdev, 2623 "MAS: Enabling Media Autosense for port %d\n", 2624 hw->bus.func); 2625 } 2626 break; 2627 case E1000_FUNC_3: 2628 if (eeprom_data & IGB_MAS_ENABLE_3) { 2629 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2630 netdev_info(adapter->netdev, 2631 "MAS: Enabling Media Autosense for port %d\n", 2632 hw->bus.func); 2633 } 2634 break; 2635 default: 2636 /* Shouldn't get here */ 2637 netdev_err(adapter->netdev, 2638 "MAS: Invalid port configuration, returning\n"); 2639 break; 2640 } 2641 } 2642 2643 /** 2644 * igb_init_i2c - Init I2C interface 2645 * @adapter: pointer to adapter structure 2646 **/ 2647 static s32 igb_init_i2c(struct igb_adapter *adapter) 2648 { 2649 s32 status = 0; 2650 2651 /* I2C interface supported on i350 devices */ 2652 if (adapter->hw.mac.type != e1000_i350) 2653 return 0; 2654 2655 /* Initialize the i2c bus which is controlled by the registers. 2656 * This bus will use the i2c_algo_bit structue that implements 2657 * the protocol through toggling of the 4 bits in the register. 2658 */ 2659 adapter->i2c_adap.owner = THIS_MODULE; 2660 adapter->i2c_algo = igb_i2c_algo; 2661 adapter->i2c_algo.data = adapter; 2662 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2663 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2664 strlcpy(adapter->i2c_adap.name, "igb BB", 2665 sizeof(adapter->i2c_adap.name)); 2666 status = i2c_bit_add_bus(&adapter->i2c_adap); 2667 return status; 2668 } 2669 2670 /** 2671 * igb_probe - Device Initialization Routine 2672 * @pdev: PCI device information struct 2673 * @ent: entry in igb_pci_tbl 2674 * 2675 * Returns 0 on success, negative on failure 2676 * 2677 * igb_probe initializes an adapter identified by a pci_dev structure. 2678 * The OS initialization, configuring of the adapter private structure, 2679 * and a hardware reset occur. 2680 **/ 2681 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2682 { 2683 struct net_device *netdev; 2684 struct igb_adapter *adapter; 2685 struct e1000_hw *hw; 2686 u16 eeprom_data = 0; 2687 s32 ret_val; 2688 static int global_quad_port_a; /* global quad port a indication */ 2689 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2690 int err, pci_using_dac; 2691 u8 part_str[E1000_PBANUM_LENGTH]; 2692 2693 /* Catch broken hardware that put the wrong VF device ID in 2694 * the PCIe SR-IOV capability. 2695 */ 2696 if (pdev->is_virtfn) { 2697 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2698 pci_name(pdev), pdev->vendor, pdev->device); 2699 return -EINVAL; 2700 } 2701 2702 err = pci_enable_device_mem(pdev); 2703 if (err) 2704 return err; 2705 2706 pci_using_dac = 0; 2707 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2708 if (!err) { 2709 pci_using_dac = 1; 2710 } else { 2711 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2712 if (err) { 2713 dev_err(&pdev->dev, 2714 "No usable DMA configuration, aborting\n"); 2715 goto err_dma; 2716 } 2717 } 2718 2719 err = pci_request_mem_regions(pdev, igb_driver_name); 2720 if (err) 2721 goto err_pci_reg; 2722 2723 pci_enable_pcie_error_reporting(pdev); 2724 2725 pci_set_master(pdev); 2726 pci_save_state(pdev); 2727 2728 err = -ENOMEM; 2729 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2730 IGB_MAX_TX_QUEUES); 2731 if (!netdev) 2732 goto err_alloc_etherdev; 2733 2734 SET_NETDEV_DEV(netdev, &pdev->dev); 2735 2736 pci_set_drvdata(pdev, netdev); 2737 adapter = netdev_priv(netdev); 2738 adapter->netdev = netdev; 2739 adapter->pdev = pdev; 2740 hw = &adapter->hw; 2741 hw->back = adapter; 2742 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2743 2744 err = -EIO; 2745 adapter->io_addr = pci_iomap(pdev, 0, 0); 2746 if (!adapter->io_addr) 2747 goto err_ioremap; 2748 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2749 hw->hw_addr = adapter->io_addr; 2750 2751 netdev->netdev_ops = &igb_netdev_ops; 2752 igb_set_ethtool_ops(netdev); 2753 netdev->watchdog_timeo = 5 * HZ; 2754 2755 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2756 2757 netdev->mem_start = pci_resource_start(pdev, 0); 2758 netdev->mem_end = pci_resource_end(pdev, 0); 2759 2760 /* PCI config space info */ 2761 hw->vendor_id = pdev->vendor; 2762 hw->device_id = pdev->device; 2763 hw->revision_id = pdev->revision; 2764 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2765 hw->subsystem_device_id = pdev->subsystem_device; 2766 2767 /* Copy the default MAC, PHY and NVM function pointers */ 2768 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2769 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2770 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2771 /* Initialize skew-specific constants */ 2772 err = ei->get_invariants(hw); 2773 if (err) 2774 goto err_sw_init; 2775 2776 /* setup the private structure */ 2777 err = igb_sw_init(adapter); 2778 if (err) 2779 goto err_sw_init; 2780 2781 igb_get_bus_info_pcie(hw); 2782 2783 hw->phy.autoneg_wait_to_complete = false; 2784 2785 /* Copper options */ 2786 if (hw->phy.media_type == e1000_media_type_copper) { 2787 hw->phy.mdix = AUTO_ALL_MODES; 2788 hw->phy.disable_polarity_correction = false; 2789 hw->phy.ms_type = e1000_ms_hw_default; 2790 } 2791 2792 if (igb_check_reset_block(hw)) 2793 dev_info(&pdev->dev, 2794 "PHY reset is blocked due to SOL/IDER session.\n"); 2795 2796 /* features is initialized to 0 in allocation, it might have bits 2797 * set by igb_sw_init so we should use an or instead of an 2798 * assignment. 2799 */ 2800 netdev->features |= NETIF_F_SG | 2801 NETIF_F_TSO | 2802 NETIF_F_TSO6 | 2803 NETIF_F_RXHASH | 2804 NETIF_F_RXCSUM | 2805 NETIF_F_HW_CSUM; 2806 2807 if (hw->mac.type >= e1000_82576) 2808 netdev->features |= NETIF_F_SCTP_CRC; 2809 2810 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2811 NETIF_F_GSO_GRE_CSUM | \ 2812 NETIF_F_GSO_IPXIP4 | \ 2813 NETIF_F_GSO_IPXIP6 | \ 2814 NETIF_F_GSO_UDP_TUNNEL | \ 2815 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2816 2817 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2818 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2819 2820 /* copy netdev features into list of user selectable features */ 2821 netdev->hw_features |= netdev->features | 2822 NETIF_F_HW_VLAN_CTAG_RX | 2823 NETIF_F_HW_VLAN_CTAG_TX | 2824 NETIF_F_RXALL; 2825 2826 if (hw->mac.type >= e1000_i350) 2827 netdev->hw_features |= NETIF_F_NTUPLE; 2828 2829 if (pci_using_dac) 2830 netdev->features |= NETIF_F_HIGHDMA; 2831 2832 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2833 netdev->mpls_features |= NETIF_F_HW_CSUM; 2834 netdev->hw_enc_features |= netdev->vlan_features; 2835 2836 /* set this bit last since it cannot be part of vlan_features */ 2837 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2838 NETIF_F_HW_VLAN_CTAG_RX | 2839 NETIF_F_HW_VLAN_CTAG_TX; 2840 2841 netdev->priv_flags |= IFF_SUPP_NOFCS; 2842 2843 netdev->priv_flags |= IFF_UNICAST_FLT; 2844 2845 /* MTU range: 68 - 9216 */ 2846 netdev->min_mtu = ETH_MIN_MTU; 2847 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2848 2849 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2850 2851 /* before reading the NVM, reset the controller to put the device in a 2852 * known good starting state 2853 */ 2854 hw->mac.ops.reset_hw(hw); 2855 2856 /* make sure the NVM is good , i211/i210 parts can have special NVM 2857 * that doesn't contain a checksum 2858 */ 2859 switch (hw->mac.type) { 2860 case e1000_i210: 2861 case e1000_i211: 2862 if (igb_get_flash_presence_i210(hw)) { 2863 if (hw->nvm.ops.validate(hw) < 0) { 2864 dev_err(&pdev->dev, 2865 "The NVM Checksum Is Not Valid\n"); 2866 err = -EIO; 2867 goto err_eeprom; 2868 } 2869 } 2870 break; 2871 default: 2872 if (hw->nvm.ops.validate(hw) < 0) { 2873 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2874 err = -EIO; 2875 goto err_eeprom; 2876 } 2877 break; 2878 } 2879 2880 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2881 /* copy the MAC address out of the NVM */ 2882 if (hw->mac.ops.read_mac_addr(hw)) 2883 dev_err(&pdev->dev, "NVM Read Error\n"); 2884 } 2885 2886 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2887 2888 if (!is_valid_ether_addr(netdev->dev_addr)) { 2889 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2890 err = -EIO; 2891 goto err_eeprom; 2892 } 2893 2894 igb_set_default_mac_filter(adapter); 2895 2896 /* get firmware version for ethtool -i */ 2897 igb_set_fw_version(adapter); 2898 2899 /* configure RXPBSIZE and TXPBSIZE */ 2900 if (hw->mac.type == e1000_i210) { 2901 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2902 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2903 } 2904 2905 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 2906 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 2907 2908 INIT_WORK(&adapter->reset_task, igb_reset_task); 2909 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2910 2911 /* Initialize link properties that are user-changeable */ 2912 adapter->fc_autoneg = true; 2913 hw->mac.autoneg = true; 2914 hw->phy.autoneg_advertised = 0x2f; 2915 2916 hw->fc.requested_mode = e1000_fc_default; 2917 hw->fc.current_mode = e1000_fc_default; 2918 2919 igb_validate_mdi_setting(hw); 2920 2921 /* By default, support wake on port A */ 2922 if (hw->bus.func == 0) 2923 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2924 2925 /* Check the NVM for wake support on non-port A ports */ 2926 if (hw->mac.type >= e1000_82580) 2927 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2928 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2929 &eeprom_data); 2930 else if (hw->bus.func == 1) 2931 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2932 2933 if (eeprom_data & IGB_EEPROM_APME) 2934 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2935 2936 /* now that we have the eeprom settings, apply the special cases where 2937 * the eeprom may be wrong or the board simply won't support wake on 2938 * lan on a particular port 2939 */ 2940 switch (pdev->device) { 2941 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2942 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2943 break; 2944 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2945 case E1000_DEV_ID_82576_FIBER: 2946 case E1000_DEV_ID_82576_SERDES: 2947 /* Wake events only supported on port A for dual fiber 2948 * regardless of eeprom setting 2949 */ 2950 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2951 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2952 break; 2953 case E1000_DEV_ID_82576_QUAD_COPPER: 2954 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2955 /* if quad port adapter, disable WoL on all but port A */ 2956 if (global_quad_port_a != 0) 2957 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2958 else 2959 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2960 /* Reset for multiple quad port adapters */ 2961 if (++global_quad_port_a == 4) 2962 global_quad_port_a = 0; 2963 break; 2964 default: 2965 /* If the device can't wake, don't set software support */ 2966 if (!device_can_wakeup(&adapter->pdev->dev)) 2967 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2968 } 2969 2970 /* initialize the wol settings based on the eeprom settings */ 2971 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2972 adapter->wol |= E1000_WUFC_MAG; 2973 2974 /* Some vendors want WoL disabled by default, but still supported */ 2975 if ((hw->mac.type == e1000_i350) && 2976 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2977 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2978 adapter->wol = 0; 2979 } 2980 2981 /* Some vendors want the ability to Use the EEPROM setting as 2982 * enable/disable only, and not for capability 2983 */ 2984 if (((hw->mac.type == e1000_i350) || 2985 (hw->mac.type == e1000_i354)) && 2986 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2987 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2988 adapter->wol = 0; 2989 } 2990 if (hw->mac.type == e1000_i350) { 2991 if (((pdev->subsystem_device == 0x5001) || 2992 (pdev->subsystem_device == 0x5002)) && 2993 (hw->bus.func == 0)) { 2994 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2995 adapter->wol = 0; 2996 } 2997 if (pdev->subsystem_device == 0x1F52) 2998 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2999 } 3000 3001 device_set_wakeup_enable(&adapter->pdev->dev, 3002 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3003 3004 /* reset the hardware with the new settings */ 3005 igb_reset(adapter); 3006 3007 /* Init the I2C interface */ 3008 err = igb_init_i2c(adapter); 3009 if (err) { 3010 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3011 goto err_eeprom; 3012 } 3013 3014 /* let the f/w know that the h/w is now under the control of the 3015 * driver. 3016 */ 3017 igb_get_hw_control(adapter); 3018 3019 strcpy(netdev->name, "eth%d"); 3020 err = register_netdev(netdev); 3021 if (err) 3022 goto err_register; 3023 3024 /* carrier off reporting is important to ethtool even BEFORE open */ 3025 netif_carrier_off(netdev); 3026 3027 #ifdef CONFIG_IGB_DCA 3028 if (dca_add_requester(&pdev->dev) == 0) { 3029 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3030 dev_info(&pdev->dev, "DCA enabled\n"); 3031 igb_setup_dca(adapter); 3032 } 3033 3034 #endif 3035 #ifdef CONFIG_IGB_HWMON 3036 /* Initialize the thermal sensor on i350 devices. */ 3037 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3038 u16 ets_word; 3039 3040 /* Read the NVM to determine if this i350 device supports an 3041 * external thermal sensor. 3042 */ 3043 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3044 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3045 adapter->ets = true; 3046 else 3047 adapter->ets = false; 3048 if (igb_sysfs_init(adapter)) 3049 dev_err(&pdev->dev, 3050 "failed to allocate sysfs resources\n"); 3051 } else { 3052 adapter->ets = false; 3053 } 3054 #endif 3055 /* Check if Media Autosense is enabled */ 3056 adapter->ei = *ei; 3057 if (hw->dev_spec._82575.mas_capable) 3058 igb_init_mas(adapter); 3059 3060 /* do hw tstamp init after resetting */ 3061 igb_ptp_init(adapter); 3062 3063 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3064 /* print bus type/speed/width info, not applicable to i354 */ 3065 if (hw->mac.type != e1000_i354) { 3066 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3067 netdev->name, 3068 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3069 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3070 "unknown"), 3071 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3072 "Width x4" : 3073 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3074 "Width x2" : 3075 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3076 "Width x1" : "unknown"), netdev->dev_addr); 3077 } 3078 3079 if ((hw->mac.type >= e1000_i210 || 3080 igb_get_flash_presence_i210(hw))) { 3081 ret_val = igb_read_part_string(hw, part_str, 3082 E1000_PBANUM_LENGTH); 3083 } else { 3084 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3085 } 3086 3087 if (ret_val) 3088 strcpy(part_str, "Unknown"); 3089 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3090 dev_info(&pdev->dev, 3091 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3092 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3093 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3094 adapter->num_rx_queues, adapter->num_tx_queues); 3095 if (hw->phy.media_type == e1000_media_type_copper) { 3096 switch (hw->mac.type) { 3097 case e1000_i350: 3098 case e1000_i210: 3099 case e1000_i211: 3100 /* Enable EEE for internal copper PHY devices */ 3101 err = igb_set_eee_i350(hw, true, true); 3102 if ((!err) && 3103 (!hw->dev_spec._82575.eee_disable)) { 3104 adapter->eee_advert = 3105 MDIO_EEE_100TX | MDIO_EEE_1000T; 3106 adapter->flags |= IGB_FLAG_EEE; 3107 } 3108 break; 3109 case e1000_i354: 3110 if ((rd32(E1000_CTRL_EXT) & 3111 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3112 err = igb_set_eee_i354(hw, true, true); 3113 if ((!err) && 3114 (!hw->dev_spec._82575.eee_disable)) { 3115 adapter->eee_advert = 3116 MDIO_EEE_100TX | MDIO_EEE_1000T; 3117 adapter->flags |= IGB_FLAG_EEE; 3118 } 3119 } 3120 break; 3121 default: 3122 break; 3123 } 3124 } 3125 pm_runtime_put_noidle(&pdev->dev); 3126 return 0; 3127 3128 err_register: 3129 igb_release_hw_control(adapter); 3130 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3131 err_eeprom: 3132 if (!igb_check_reset_block(hw)) 3133 igb_reset_phy(hw); 3134 3135 if (hw->flash_address) 3136 iounmap(hw->flash_address); 3137 err_sw_init: 3138 kfree(adapter->mac_table); 3139 kfree(adapter->shadow_vfta); 3140 igb_clear_interrupt_scheme(adapter); 3141 #ifdef CONFIG_PCI_IOV 3142 igb_disable_sriov(pdev); 3143 #endif 3144 pci_iounmap(pdev, adapter->io_addr); 3145 err_ioremap: 3146 free_netdev(netdev); 3147 err_alloc_etherdev: 3148 pci_release_mem_regions(pdev); 3149 err_pci_reg: 3150 err_dma: 3151 pci_disable_device(pdev); 3152 return err; 3153 } 3154 3155 #ifdef CONFIG_PCI_IOV 3156 static int igb_disable_sriov(struct pci_dev *pdev) 3157 { 3158 struct net_device *netdev = pci_get_drvdata(pdev); 3159 struct igb_adapter *adapter = netdev_priv(netdev); 3160 struct e1000_hw *hw = &adapter->hw; 3161 3162 /* reclaim resources allocated to VFs */ 3163 if (adapter->vf_data) { 3164 /* disable iov and allow time for transactions to clear */ 3165 if (pci_vfs_assigned(pdev)) { 3166 dev_warn(&pdev->dev, 3167 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3168 return -EPERM; 3169 } else { 3170 pci_disable_sriov(pdev); 3171 msleep(500); 3172 } 3173 3174 kfree(adapter->vf_mac_list); 3175 adapter->vf_mac_list = NULL; 3176 kfree(adapter->vf_data); 3177 adapter->vf_data = NULL; 3178 adapter->vfs_allocated_count = 0; 3179 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3180 wrfl(); 3181 msleep(100); 3182 dev_info(&pdev->dev, "IOV Disabled\n"); 3183 3184 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3185 adapter->flags |= IGB_FLAG_DMAC; 3186 } 3187 3188 return 0; 3189 } 3190 3191 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3192 { 3193 struct net_device *netdev = pci_get_drvdata(pdev); 3194 struct igb_adapter *adapter = netdev_priv(netdev); 3195 int old_vfs = pci_num_vf(pdev); 3196 struct vf_mac_filter *mac_list; 3197 int err = 0; 3198 int num_vf_mac_filters, i; 3199 3200 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3201 err = -EPERM; 3202 goto out; 3203 } 3204 if (!num_vfs) 3205 goto out; 3206 3207 if (old_vfs) { 3208 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3209 old_vfs, max_vfs); 3210 adapter->vfs_allocated_count = old_vfs; 3211 } else 3212 adapter->vfs_allocated_count = num_vfs; 3213 3214 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3215 sizeof(struct vf_data_storage), GFP_KERNEL); 3216 3217 /* if allocation failed then we do not support SR-IOV */ 3218 if (!adapter->vf_data) { 3219 adapter->vfs_allocated_count = 0; 3220 err = -ENOMEM; 3221 goto out; 3222 } 3223 3224 /* Due to the limited number of RAR entries calculate potential 3225 * number of MAC filters available for the VFs. Reserve entries 3226 * for PF default MAC, PF MAC filters and at least one RAR entry 3227 * for each VF for VF MAC. 3228 */ 3229 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3230 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3231 adapter->vfs_allocated_count); 3232 3233 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3234 sizeof(struct vf_mac_filter), 3235 GFP_KERNEL); 3236 3237 mac_list = adapter->vf_mac_list; 3238 INIT_LIST_HEAD(&adapter->vf_macs.l); 3239 3240 if (adapter->vf_mac_list) { 3241 /* Initialize list of VF MAC filters */ 3242 for (i = 0; i < num_vf_mac_filters; i++) { 3243 mac_list->vf = -1; 3244 mac_list->free = true; 3245 list_add(&mac_list->l, &adapter->vf_macs.l); 3246 mac_list++; 3247 } 3248 } else { 3249 /* If we could not allocate memory for the VF MAC filters 3250 * we can continue without this feature but warn user. 3251 */ 3252 dev_err(&pdev->dev, 3253 "Unable to allocate memory for VF MAC filter list\n"); 3254 } 3255 3256 /* only call pci_enable_sriov() if no VFs are allocated already */ 3257 if (!old_vfs) { 3258 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3259 if (err) 3260 goto err_out; 3261 } 3262 dev_info(&pdev->dev, "%d VFs allocated\n", 3263 adapter->vfs_allocated_count); 3264 for (i = 0; i < adapter->vfs_allocated_count; i++) 3265 igb_vf_configure(adapter, i); 3266 3267 /* DMA Coalescing is not supported in IOV mode. */ 3268 adapter->flags &= ~IGB_FLAG_DMAC; 3269 goto out; 3270 3271 err_out: 3272 kfree(adapter->vf_mac_list); 3273 adapter->vf_mac_list = NULL; 3274 kfree(adapter->vf_data); 3275 adapter->vf_data = NULL; 3276 adapter->vfs_allocated_count = 0; 3277 out: 3278 return err; 3279 } 3280 3281 #endif 3282 /** 3283 * igb_remove_i2c - Cleanup I2C interface 3284 * @adapter: pointer to adapter structure 3285 **/ 3286 static void igb_remove_i2c(struct igb_adapter *adapter) 3287 { 3288 /* free the adapter bus structure */ 3289 i2c_del_adapter(&adapter->i2c_adap); 3290 } 3291 3292 /** 3293 * igb_remove - Device Removal Routine 3294 * @pdev: PCI device information struct 3295 * 3296 * igb_remove is called by the PCI subsystem to alert the driver 3297 * that it should release a PCI device. The could be caused by a 3298 * Hot-Plug event, or because the driver is going to be removed from 3299 * memory. 3300 **/ 3301 static void igb_remove(struct pci_dev *pdev) 3302 { 3303 struct net_device *netdev = pci_get_drvdata(pdev); 3304 struct igb_adapter *adapter = netdev_priv(netdev); 3305 struct e1000_hw *hw = &adapter->hw; 3306 3307 pm_runtime_get_noresume(&pdev->dev); 3308 #ifdef CONFIG_IGB_HWMON 3309 igb_sysfs_exit(adapter); 3310 #endif 3311 igb_remove_i2c(adapter); 3312 igb_ptp_stop(adapter); 3313 /* The watchdog timer may be rescheduled, so explicitly 3314 * disable watchdog from being rescheduled. 3315 */ 3316 set_bit(__IGB_DOWN, &adapter->state); 3317 del_timer_sync(&adapter->watchdog_timer); 3318 del_timer_sync(&adapter->phy_info_timer); 3319 3320 cancel_work_sync(&adapter->reset_task); 3321 cancel_work_sync(&adapter->watchdog_task); 3322 3323 #ifdef CONFIG_IGB_DCA 3324 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3325 dev_info(&pdev->dev, "DCA disabled\n"); 3326 dca_remove_requester(&pdev->dev); 3327 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3328 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3329 } 3330 #endif 3331 3332 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3333 * would have already happened in close and is redundant. 3334 */ 3335 igb_release_hw_control(adapter); 3336 3337 #ifdef CONFIG_PCI_IOV 3338 igb_disable_sriov(pdev); 3339 #endif 3340 3341 unregister_netdev(netdev); 3342 3343 igb_clear_interrupt_scheme(adapter); 3344 3345 pci_iounmap(pdev, adapter->io_addr); 3346 if (hw->flash_address) 3347 iounmap(hw->flash_address); 3348 pci_release_mem_regions(pdev); 3349 3350 kfree(adapter->mac_table); 3351 kfree(adapter->shadow_vfta); 3352 free_netdev(netdev); 3353 3354 pci_disable_pcie_error_reporting(pdev); 3355 3356 pci_disable_device(pdev); 3357 } 3358 3359 /** 3360 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3361 * @adapter: board private structure to initialize 3362 * 3363 * This function initializes the vf specific data storage and then attempts to 3364 * allocate the VFs. The reason for ordering it this way is because it is much 3365 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3366 * the memory for the VFs. 3367 **/ 3368 static void igb_probe_vfs(struct igb_adapter *adapter) 3369 { 3370 #ifdef CONFIG_PCI_IOV 3371 struct pci_dev *pdev = adapter->pdev; 3372 struct e1000_hw *hw = &adapter->hw; 3373 3374 /* Virtualization features not supported on i210 family. */ 3375 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3376 return; 3377 3378 /* Of the below we really only want the effect of getting 3379 * IGB_FLAG_HAS_MSIX set (if available), without which 3380 * igb_enable_sriov() has no effect. 3381 */ 3382 igb_set_interrupt_capability(adapter, true); 3383 igb_reset_interrupt_capability(adapter); 3384 3385 pci_sriov_set_totalvfs(pdev, 7); 3386 igb_enable_sriov(pdev, max_vfs); 3387 3388 #endif /* CONFIG_PCI_IOV */ 3389 } 3390 3391 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3392 { 3393 struct e1000_hw *hw = &adapter->hw; 3394 unsigned int max_rss_queues; 3395 3396 /* Determine the maximum number of RSS queues supported. */ 3397 switch (hw->mac.type) { 3398 case e1000_i211: 3399 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3400 break; 3401 case e1000_82575: 3402 case e1000_i210: 3403 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3404 break; 3405 case e1000_i350: 3406 /* I350 cannot do RSS and SR-IOV at the same time */ 3407 if (!!adapter->vfs_allocated_count) { 3408 max_rss_queues = 1; 3409 break; 3410 } 3411 /* fall through */ 3412 case e1000_82576: 3413 if (!!adapter->vfs_allocated_count) { 3414 max_rss_queues = 2; 3415 break; 3416 } 3417 /* fall through */ 3418 case e1000_82580: 3419 case e1000_i354: 3420 default: 3421 max_rss_queues = IGB_MAX_RX_QUEUES; 3422 break; 3423 } 3424 3425 return max_rss_queues; 3426 } 3427 3428 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3429 { 3430 u32 max_rss_queues; 3431 3432 max_rss_queues = igb_get_max_rss_queues(adapter); 3433 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3434 3435 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3436 } 3437 3438 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3439 const u32 max_rss_queues) 3440 { 3441 struct e1000_hw *hw = &adapter->hw; 3442 3443 /* Determine if we need to pair queues. */ 3444 switch (hw->mac.type) { 3445 case e1000_82575: 3446 case e1000_i211: 3447 /* Device supports enough interrupts without queue pairing. */ 3448 break; 3449 case e1000_82576: 3450 case e1000_82580: 3451 case e1000_i350: 3452 case e1000_i354: 3453 case e1000_i210: 3454 default: 3455 /* If rss_queues > half of max_rss_queues, pair the queues in 3456 * order to conserve interrupts due to limited supply. 3457 */ 3458 if (adapter->rss_queues > (max_rss_queues / 2)) 3459 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3460 else 3461 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3462 break; 3463 } 3464 } 3465 3466 /** 3467 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3468 * @adapter: board private structure to initialize 3469 * 3470 * igb_sw_init initializes the Adapter private data structure. 3471 * Fields are initialized based on PCI device information and 3472 * OS network device settings (MTU size). 3473 **/ 3474 static int igb_sw_init(struct igb_adapter *adapter) 3475 { 3476 struct e1000_hw *hw = &adapter->hw; 3477 struct net_device *netdev = adapter->netdev; 3478 struct pci_dev *pdev = adapter->pdev; 3479 3480 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3481 3482 /* set default ring sizes */ 3483 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3484 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3485 3486 /* set default ITR values */ 3487 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3488 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3489 3490 /* set default work limits */ 3491 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3492 3493 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3494 VLAN_HLEN; 3495 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3496 3497 spin_lock_init(&adapter->nfc_lock); 3498 spin_lock_init(&adapter->stats64_lock); 3499 #ifdef CONFIG_PCI_IOV 3500 switch (hw->mac.type) { 3501 case e1000_82576: 3502 case e1000_i350: 3503 if (max_vfs > 7) { 3504 dev_warn(&pdev->dev, 3505 "Maximum of 7 VFs per PF, using max\n"); 3506 max_vfs = adapter->vfs_allocated_count = 7; 3507 } else 3508 adapter->vfs_allocated_count = max_vfs; 3509 if (adapter->vfs_allocated_count) 3510 dev_warn(&pdev->dev, 3511 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3512 break; 3513 default: 3514 break; 3515 } 3516 #endif /* CONFIG_PCI_IOV */ 3517 3518 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3519 adapter->flags |= IGB_FLAG_HAS_MSIX; 3520 3521 adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) * 3522 hw->mac.rar_entry_count, GFP_ATOMIC); 3523 if (!adapter->mac_table) 3524 return -ENOMEM; 3525 3526 igb_probe_vfs(adapter); 3527 3528 igb_init_queue_configuration(adapter); 3529 3530 /* Setup and initialize a copy of the hw vlan table array */ 3531 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3532 GFP_ATOMIC); 3533 if (!adapter->shadow_vfta) 3534 return -ENOMEM; 3535 3536 /* This call may decrease the number of queues */ 3537 if (igb_init_interrupt_scheme(adapter, true)) { 3538 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3539 return -ENOMEM; 3540 } 3541 3542 /* Explicitly disable IRQ since the NIC can be in any state. */ 3543 igb_irq_disable(adapter); 3544 3545 if (hw->mac.type >= e1000_i350) 3546 adapter->flags &= ~IGB_FLAG_DMAC; 3547 3548 set_bit(__IGB_DOWN, &adapter->state); 3549 return 0; 3550 } 3551 3552 /** 3553 * igb_open - Called when a network interface is made active 3554 * @netdev: network interface device structure 3555 * 3556 * Returns 0 on success, negative value on failure 3557 * 3558 * The open entry point is called when a network interface is made 3559 * active by the system (IFF_UP). At this point all resources needed 3560 * for transmit and receive operations are allocated, the interrupt 3561 * handler is registered with the OS, the watchdog timer is started, 3562 * and the stack is notified that the interface is ready. 3563 **/ 3564 static int __igb_open(struct net_device *netdev, bool resuming) 3565 { 3566 struct igb_adapter *adapter = netdev_priv(netdev); 3567 struct e1000_hw *hw = &adapter->hw; 3568 struct pci_dev *pdev = adapter->pdev; 3569 int err; 3570 int i; 3571 3572 /* disallow open during test */ 3573 if (test_bit(__IGB_TESTING, &adapter->state)) { 3574 WARN_ON(resuming); 3575 return -EBUSY; 3576 } 3577 3578 if (!resuming) 3579 pm_runtime_get_sync(&pdev->dev); 3580 3581 netif_carrier_off(netdev); 3582 3583 /* allocate transmit descriptors */ 3584 err = igb_setup_all_tx_resources(adapter); 3585 if (err) 3586 goto err_setup_tx; 3587 3588 /* allocate receive descriptors */ 3589 err = igb_setup_all_rx_resources(adapter); 3590 if (err) 3591 goto err_setup_rx; 3592 3593 igb_power_up_link(adapter); 3594 3595 /* before we allocate an interrupt, we must be ready to handle it. 3596 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3597 * as soon as we call pci_request_irq, so we have to setup our 3598 * clean_rx handler before we do so. 3599 */ 3600 igb_configure(adapter); 3601 3602 err = igb_request_irq(adapter); 3603 if (err) 3604 goto err_req_irq; 3605 3606 /* Notify the stack of the actual queue counts. */ 3607 err = netif_set_real_num_tx_queues(adapter->netdev, 3608 adapter->num_tx_queues); 3609 if (err) 3610 goto err_set_queues; 3611 3612 err = netif_set_real_num_rx_queues(adapter->netdev, 3613 adapter->num_rx_queues); 3614 if (err) 3615 goto err_set_queues; 3616 3617 /* From here on the code is the same as igb_up() */ 3618 clear_bit(__IGB_DOWN, &adapter->state); 3619 3620 for (i = 0; i < adapter->num_q_vectors; i++) 3621 napi_enable(&(adapter->q_vector[i]->napi)); 3622 3623 /* Clear any pending interrupts. */ 3624 rd32(E1000_ICR); 3625 3626 igb_irq_enable(adapter); 3627 3628 /* notify VFs that reset has been completed */ 3629 if (adapter->vfs_allocated_count) { 3630 u32 reg_data = rd32(E1000_CTRL_EXT); 3631 3632 reg_data |= E1000_CTRL_EXT_PFRSTD; 3633 wr32(E1000_CTRL_EXT, reg_data); 3634 } 3635 3636 netif_tx_start_all_queues(netdev); 3637 3638 if (!resuming) 3639 pm_runtime_put(&pdev->dev); 3640 3641 /* start the watchdog. */ 3642 hw->mac.get_link_status = 1; 3643 schedule_work(&adapter->watchdog_task); 3644 3645 return 0; 3646 3647 err_set_queues: 3648 igb_free_irq(adapter); 3649 err_req_irq: 3650 igb_release_hw_control(adapter); 3651 igb_power_down_link(adapter); 3652 igb_free_all_rx_resources(adapter); 3653 err_setup_rx: 3654 igb_free_all_tx_resources(adapter); 3655 err_setup_tx: 3656 igb_reset(adapter); 3657 if (!resuming) 3658 pm_runtime_put(&pdev->dev); 3659 3660 return err; 3661 } 3662 3663 int igb_open(struct net_device *netdev) 3664 { 3665 return __igb_open(netdev, false); 3666 } 3667 3668 /** 3669 * igb_close - Disables a network interface 3670 * @netdev: network interface device structure 3671 * 3672 * Returns 0, this is not allowed to fail 3673 * 3674 * The close entry point is called when an interface is de-activated 3675 * by the OS. The hardware is still under the driver's control, but 3676 * needs to be disabled. A global MAC reset is issued to stop the 3677 * hardware, and all transmit and receive resources are freed. 3678 **/ 3679 static int __igb_close(struct net_device *netdev, bool suspending) 3680 { 3681 struct igb_adapter *adapter = netdev_priv(netdev); 3682 struct pci_dev *pdev = adapter->pdev; 3683 3684 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3685 3686 if (!suspending) 3687 pm_runtime_get_sync(&pdev->dev); 3688 3689 igb_down(adapter); 3690 igb_free_irq(adapter); 3691 3692 igb_free_all_tx_resources(adapter); 3693 igb_free_all_rx_resources(adapter); 3694 3695 if (!suspending) 3696 pm_runtime_put_sync(&pdev->dev); 3697 return 0; 3698 } 3699 3700 int igb_close(struct net_device *netdev) 3701 { 3702 if (netif_device_present(netdev) || netdev->dismantle) 3703 return __igb_close(netdev, false); 3704 return 0; 3705 } 3706 3707 /** 3708 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3709 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3710 * 3711 * Return 0 on success, negative on failure 3712 **/ 3713 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3714 { 3715 struct device *dev = tx_ring->dev; 3716 int size; 3717 3718 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3719 3720 tx_ring->tx_buffer_info = vmalloc(size); 3721 if (!tx_ring->tx_buffer_info) 3722 goto err; 3723 3724 /* round up to nearest 4K */ 3725 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3726 tx_ring->size = ALIGN(tx_ring->size, 4096); 3727 3728 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3729 &tx_ring->dma, GFP_KERNEL); 3730 if (!tx_ring->desc) 3731 goto err; 3732 3733 tx_ring->next_to_use = 0; 3734 tx_ring->next_to_clean = 0; 3735 3736 return 0; 3737 3738 err: 3739 vfree(tx_ring->tx_buffer_info); 3740 tx_ring->tx_buffer_info = NULL; 3741 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3742 return -ENOMEM; 3743 } 3744 3745 /** 3746 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3747 * (Descriptors) for all queues 3748 * @adapter: board private structure 3749 * 3750 * Return 0 on success, negative on failure 3751 **/ 3752 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3753 { 3754 struct pci_dev *pdev = adapter->pdev; 3755 int i, err = 0; 3756 3757 for (i = 0; i < adapter->num_tx_queues; i++) { 3758 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3759 if (err) { 3760 dev_err(&pdev->dev, 3761 "Allocation for Tx Queue %u failed\n", i); 3762 for (i--; i >= 0; i--) 3763 igb_free_tx_resources(adapter->tx_ring[i]); 3764 break; 3765 } 3766 } 3767 3768 return err; 3769 } 3770 3771 /** 3772 * igb_setup_tctl - configure the transmit control registers 3773 * @adapter: Board private structure 3774 **/ 3775 void igb_setup_tctl(struct igb_adapter *adapter) 3776 { 3777 struct e1000_hw *hw = &adapter->hw; 3778 u32 tctl; 3779 3780 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3781 wr32(E1000_TXDCTL(0), 0); 3782 3783 /* Program the Transmit Control Register */ 3784 tctl = rd32(E1000_TCTL); 3785 tctl &= ~E1000_TCTL_CT; 3786 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3787 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3788 3789 igb_config_collision_dist(hw); 3790 3791 /* Enable transmits */ 3792 tctl |= E1000_TCTL_EN; 3793 3794 wr32(E1000_TCTL, tctl); 3795 } 3796 3797 /** 3798 * igb_configure_tx_ring - Configure transmit ring after Reset 3799 * @adapter: board private structure 3800 * @ring: tx ring to configure 3801 * 3802 * Configure a transmit ring after a reset. 3803 **/ 3804 void igb_configure_tx_ring(struct igb_adapter *adapter, 3805 struct igb_ring *ring) 3806 { 3807 struct e1000_hw *hw = &adapter->hw; 3808 u32 txdctl = 0; 3809 u64 tdba = ring->dma; 3810 int reg_idx = ring->reg_idx; 3811 3812 /* disable the queue */ 3813 wr32(E1000_TXDCTL(reg_idx), 0); 3814 wrfl(); 3815 mdelay(10); 3816 3817 wr32(E1000_TDLEN(reg_idx), 3818 ring->count * sizeof(union e1000_adv_tx_desc)); 3819 wr32(E1000_TDBAL(reg_idx), 3820 tdba & 0x00000000ffffffffULL); 3821 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3822 3823 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 3824 wr32(E1000_TDH(reg_idx), 0); 3825 writel(0, ring->tail); 3826 3827 txdctl |= IGB_TX_PTHRESH; 3828 txdctl |= IGB_TX_HTHRESH << 8; 3829 txdctl |= IGB_TX_WTHRESH << 16; 3830 3831 /* reinitialize tx_buffer_info */ 3832 memset(ring->tx_buffer_info, 0, 3833 sizeof(struct igb_tx_buffer) * ring->count); 3834 3835 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3836 wr32(E1000_TXDCTL(reg_idx), txdctl); 3837 } 3838 3839 /** 3840 * igb_configure_tx - Configure transmit Unit after Reset 3841 * @adapter: board private structure 3842 * 3843 * Configure the Tx unit of the MAC after a reset. 3844 **/ 3845 static void igb_configure_tx(struct igb_adapter *adapter) 3846 { 3847 int i; 3848 3849 for (i = 0; i < adapter->num_tx_queues; i++) 3850 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3851 } 3852 3853 /** 3854 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3855 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3856 * 3857 * Returns 0 on success, negative on failure 3858 **/ 3859 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3860 { 3861 struct device *dev = rx_ring->dev; 3862 int size; 3863 3864 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3865 3866 rx_ring->rx_buffer_info = vmalloc(size); 3867 if (!rx_ring->rx_buffer_info) 3868 goto err; 3869 3870 /* Round up to nearest 4K */ 3871 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3872 rx_ring->size = ALIGN(rx_ring->size, 4096); 3873 3874 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3875 &rx_ring->dma, GFP_KERNEL); 3876 if (!rx_ring->desc) 3877 goto err; 3878 3879 rx_ring->next_to_alloc = 0; 3880 rx_ring->next_to_clean = 0; 3881 rx_ring->next_to_use = 0; 3882 3883 return 0; 3884 3885 err: 3886 vfree(rx_ring->rx_buffer_info); 3887 rx_ring->rx_buffer_info = NULL; 3888 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3889 return -ENOMEM; 3890 } 3891 3892 /** 3893 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3894 * (Descriptors) for all queues 3895 * @adapter: board private structure 3896 * 3897 * Return 0 on success, negative on failure 3898 **/ 3899 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3900 { 3901 struct pci_dev *pdev = adapter->pdev; 3902 int i, err = 0; 3903 3904 for (i = 0; i < adapter->num_rx_queues; i++) { 3905 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3906 if (err) { 3907 dev_err(&pdev->dev, 3908 "Allocation for Rx Queue %u failed\n", i); 3909 for (i--; i >= 0; i--) 3910 igb_free_rx_resources(adapter->rx_ring[i]); 3911 break; 3912 } 3913 } 3914 3915 return err; 3916 } 3917 3918 /** 3919 * igb_setup_mrqc - configure the multiple receive queue control registers 3920 * @adapter: Board private structure 3921 **/ 3922 static void igb_setup_mrqc(struct igb_adapter *adapter) 3923 { 3924 struct e1000_hw *hw = &adapter->hw; 3925 u32 mrqc, rxcsum; 3926 u32 j, num_rx_queues; 3927 u32 rss_key[10]; 3928 3929 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3930 for (j = 0; j < 10; j++) 3931 wr32(E1000_RSSRK(j), rss_key[j]); 3932 3933 num_rx_queues = adapter->rss_queues; 3934 3935 switch (hw->mac.type) { 3936 case e1000_82576: 3937 /* 82576 supports 2 RSS queues for SR-IOV */ 3938 if (adapter->vfs_allocated_count) 3939 num_rx_queues = 2; 3940 break; 3941 default: 3942 break; 3943 } 3944 3945 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3946 for (j = 0; j < IGB_RETA_SIZE; j++) 3947 adapter->rss_indir_tbl[j] = 3948 (j * num_rx_queues) / IGB_RETA_SIZE; 3949 adapter->rss_indir_tbl_init = num_rx_queues; 3950 } 3951 igb_write_rss_indir_tbl(adapter); 3952 3953 /* Disable raw packet checksumming so that RSS hash is placed in 3954 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3955 * offloads as they are enabled by default 3956 */ 3957 rxcsum = rd32(E1000_RXCSUM); 3958 rxcsum |= E1000_RXCSUM_PCSD; 3959 3960 if (adapter->hw.mac.type >= e1000_82576) 3961 /* Enable Receive Checksum Offload for SCTP */ 3962 rxcsum |= E1000_RXCSUM_CRCOFL; 3963 3964 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3965 wr32(E1000_RXCSUM, rxcsum); 3966 3967 /* Generate RSS hash based on packet types, TCP/UDP 3968 * port numbers and/or IPv4/v6 src and dst addresses 3969 */ 3970 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3971 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3972 E1000_MRQC_RSS_FIELD_IPV6 | 3973 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3974 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3975 3976 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3977 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3978 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3979 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3980 3981 /* If VMDq is enabled then we set the appropriate mode for that, else 3982 * we default to RSS so that an RSS hash is calculated per packet even 3983 * if we are only using one queue 3984 */ 3985 if (adapter->vfs_allocated_count) { 3986 if (hw->mac.type > e1000_82575) { 3987 /* Set the default pool for the PF's first queue */ 3988 u32 vtctl = rd32(E1000_VT_CTL); 3989 3990 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3991 E1000_VT_CTL_DISABLE_DEF_POOL); 3992 vtctl |= adapter->vfs_allocated_count << 3993 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3994 wr32(E1000_VT_CTL, vtctl); 3995 } 3996 if (adapter->rss_queues > 1) 3997 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3998 else 3999 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4000 } else { 4001 if (hw->mac.type != e1000_i211) 4002 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4003 } 4004 igb_vmm_control(adapter); 4005 4006 wr32(E1000_MRQC, mrqc); 4007 } 4008 4009 /** 4010 * igb_setup_rctl - configure the receive control registers 4011 * @adapter: Board private structure 4012 **/ 4013 void igb_setup_rctl(struct igb_adapter *adapter) 4014 { 4015 struct e1000_hw *hw = &adapter->hw; 4016 u32 rctl; 4017 4018 rctl = rd32(E1000_RCTL); 4019 4020 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4021 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4022 4023 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4024 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4025 4026 /* enable stripping of CRC. It's unlikely this will break BMC 4027 * redirection as it did with e1000. Newer features require 4028 * that the HW strips the CRC. 4029 */ 4030 rctl |= E1000_RCTL_SECRC; 4031 4032 /* disable store bad packets and clear size bits. */ 4033 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4034 4035 /* enable LPE to allow for reception of jumbo frames */ 4036 rctl |= E1000_RCTL_LPE; 4037 4038 /* disable queue 0 to prevent tail write w/o re-config */ 4039 wr32(E1000_RXDCTL(0), 0); 4040 4041 /* Attention!!! For SR-IOV PF driver operations you must enable 4042 * queue drop for all VF and PF queues to prevent head of line blocking 4043 * if an un-trusted VF does not provide descriptors to hardware. 4044 */ 4045 if (adapter->vfs_allocated_count) { 4046 /* set all queue drop enable bits */ 4047 wr32(E1000_QDE, ALL_QUEUES); 4048 } 4049 4050 /* This is useful for sniffing bad packets. */ 4051 if (adapter->netdev->features & NETIF_F_RXALL) { 4052 /* UPE and MPE will be handled by normal PROMISC logic 4053 * in e1000e_set_rx_mode 4054 */ 4055 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4056 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4057 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4058 4059 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4060 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4061 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4062 * and that breaks VLANs. 4063 */ 4064 } 4065 4066 wr32(E1000_RCTL, rctl); 4067 } 4068 4069 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4070 int vfn) 4071 { 4072 struct e1000_hw *hw = &adapter->hw; 4073 u32 vmolr; 4074 4075 if (size > MAX_JUMBO_FRAME_SIZE) 4076 size = MAX_JUMBO_FRAME_SIZE; 4077 4078 vmolr = rd32(E1000_VMOLR(vfn)); 4079 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4080 vmolr |= size | E1000_VMOLR_LPE; 4081 wr32(E1000_VMOLR(vfn), vmolr); 4082 4083 return 0; 4084 } 4085 4086 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4087 int vfn, bool enable) 4088 { 4089 struct e1000_hw *hw = &adapter->hw; 4090 u32 val, reg; 4091 4092 if (hw->mac.type < e1000_82576) 4093 return; 4094 4095 if (hw->mac.type == e1000_i350) 4096 reg = E1000_DVMOLR(vfn); 4097 else 4098 reg = E1000_VMOLR(vfn); 4099 4100 val = rd32(reg); 4101 if (enable) 4102 val |= E1000_VMOLR_STRVLAN; 4103 else 4104 val &= ~(E1000_VMOLR_STRVLAN); 4105 wr32(reg, val); 4106 } 4107 4108 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4109 int vfn, bool aupe) 4110 { 4111 struct e1000_hw *hw = &adapter->hw; 4112 u32 vmolr; 4113 4114 /* This register exists only on 82576 and newer so if we are older then 4115 * we should exit and do nothing 4116 */ 4117 if (hw->mac.type < e1000_82576) 4118 return; 4119 4120 vmolr = rd32(E1000_VMOLR(vfn)); 4121 if (aupe) 4122 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4123 else 4124 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4125 4126 /* clear all bits that might not be set */ 4127 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4128 4129 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4130 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4131 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4132 * multicast packets 4133 */ 4134 if (vfn <= adapter->vfs_allocated_count) 4135 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4136 4137 wr32(E1000_VMOLR(vfn), vmolr); 4138 } 4139 4140 /** 4141 * igb_configure_rx_ring - Configure a receive ring after Reset 4142 * @adapter: board private structure 4143 * @ring: receive ring to be configured 4144 * 4145 * Configure the Rx unit of the MAC after a reset. 4146 **/ 4147 void igb_configure_rx_ring(struct igb_adapter *adapter, 4148 struct igb_ring *ring) 4149 { 4150 struct e1000_hw *hw = &adapter->hw; 4151 union e1000_adv_rx_desc *rx_desc; 4152 u64 rdba = ring->dma; 4153 int reg_idx = ring->reg_idx; 4154 u32 srrctl = 0, rxdctl = 0; 4155 4156 /* disable the queue */ 4157 wr32(E1000_RXDCTL(reg_idx), 0); 4158 4159 /* Set DMA base address registers */ 4160 wr32(E1000_RDBAL(reg_idx), 4161 rdba & 0x00000000ffffffffULL); 4162 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4163 wr32(E1000_RDLEN(reg_idx), 4164 ring->count * sizeof(union e1000_adv_rx_desc)); 4165 4166 /* initialize head and tail */ 4167 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4168 wr32(E1000_RDH(reg_idx), 0); 4169 writel(0, ring->tail); 4170 4171 /* set descriptor configuration */ 4172 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4173 if (ring_uses_large_buffer(ring)) 4174 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4175 else 4176 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4177 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4178 if (hw->mac.type >= e1000_82580) 4179 srrctl |= E1000_SRRCTL_TIMESTAMP; 4180 /* Only set Drop Enable if we are supporting multiple queues */ 4181 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 4182 srrctl |= E1000_SRRCTL_DROP_EN; 4183 4184 wr32(E1000_SRRCTL(reg_idx), srrctl); 4185 4186 /* set filtering for VMDQ pools */ 4187 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4188 4189 rxdctl |= IGB_RX_PTHRESH; 4190 rxdctl |= IGB_RX_HTHRESH << 8; 4191 rxdctl |= IGB_RX_WTHRESH << 16; 4192 4193 /* initialize rx_buffer_info */ 4194 memset(ring->rx_buffer_info, 0, 4195 sizeof(struct igb_rx_buffer) * ring->count); 4196 4197 /* initialize Rx descriptor 0 */ 4198 rx_desc = IGB_RX_DESC(ring, 0); 4199 rx_desc->wb.upper.length = 0; 4200 4201 /* enable receive descriptor fetching */ 4202 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4203 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4204 } 4205 4206 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4207 struct igb_ring *rx_ring) 4208 { 4209 /* set build_skb and buffer size flags */ 4210 clear_ring_build_skb_enabled(rx_ring); 4211 clear_ring_uses_large_buffer(rx_ring); 4212 4213 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4214 return; 4215 4216 set_ring_build_skb_enabled(rx_ring); 4217 4218 #if (PAGE_SIZE < 8192) 4219 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4220 return; 4221 4222 set_ring_uses_large_buffer(rx_ring); 4223 #endif 4224 } 4225 4226 /** 4227 * igb_configure_rx - Configure receive Unit after Reset 4228 * @adapter: board private structure 4229 * 4230 * Configure the Rx unit of the MAC after a reset. 4231 **/ 4232 static void igb_configure_rx(struct igb_adapter *adapter) 4233 { 4234 int i; 4235 4236 /* set the correct pool for the PF default MAC address in entry 0 */ 4237 igb_set_default_mac_filter(adapter); 4238 4239 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4240 * the Base and Length of the Rx Descriptor Ring 4241 */ 4242 for (i = 0; i < adapter->num_rx_queues; i++) { 4243 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4244 4245 igb_set_rx_buffer_len(adapter, rx_ring); 4246 igb_configure_rx_ring(adapter, rx_ring); 4247 } 4248 } 4249 4250 /** 4251 * igb_free_tx_resources - Free Tx Resources per Queue 4252 * @tx_ring: Tx descriptor ring for a specific queue 4253 * 4254 * Free all transmit software resources 4255 **/ 4256 void igb_free_tx_resources(struct igb_ring *tx_ring) 4257 { 4258 igb_clean_tx_ring(tx_ring); 4259 4260 vfree(tx_ring->tx_buffer_info); 4261 tx_ring->tx_buffer_info = NULL; 4262 4263 /* if not set, then don't free */ 4264 if (!tx_ring->desc) 4265 return; 4266 4267 dma_free_coherent(tx_ring->dev, tx_ring->size, 4268 tx_ring->desc, tx_ring->dma); 4269 4270 tx_ring->desc = NULL; 4271 } 4272 4273 /** 4274 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4275 * @adapter: board private structure 4276 * 4277 * Free all transmit software resources 4278 **/ 4279 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4280 { 4281 int i; 4282 4283 for (i = 0; i < adapter->num_tx_queues; i++) 4284 if (adapter->tx_ring[i]) 4285 igb_free_tx_resources(adapter->tx_ring[i]); 4286 } 4287 4288 /** 4289 * igb_clean_tx_ring - Free Tx Buffers 4290 * @tx_ring: ring to be cleaned 4291 **/ 4292 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4293 { 4294 u16 i = tx_ring->next_to_clean; 4295 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4296 4297 while (i != tx_ring->next_to_use) { 4298 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4299 4300 /* Free all the Tx ring sk_buffs */ 4301 dev_kfree_skb_any(tx_buffer->skb); 4302 4303 /* unmap skb header data */ 4304 dma_unmap_single(tx_ring->dev, 4305 dma_unmap_addr(tx_buffer, dma), 4306 dma_unmap_len(tx_buffer, len), 4307 DMA_TO_DEVICE); 4308 4309 /* check for eop_desc to determine the end of the packet */ 4310 eop_desc = tx_buffer->next_to_watch; 4311 tx_desc = IGB_TX_DESC(tx_ring, i); 4312 4313 /* unmap remaining buffers */ 4314 while (tx_desc != eop_desc) { 4315 tx_buffer++; 4316 tx_desc++; 4317 i++; 4318 if (unlikely(i == tx_ring->count)) { 4319 i = 0; 4320 tx_buffer = tx_ring->tx_buffer_info; 4321 tx_desc = IGB_TX_DESC(tx_ring, 0); 4322 } 4323 4324 /* unmap any remaining paged data */ 4325 if (dma_unmap_len(tx_buffer, len)) 4326 dma_unmap_page(tx_ring->dev, 4327 dma_unmap_addr(tx_buffer, dma), 4328 dma_unmap_len(tx_buffer, len), 4329 DMA_TO_DEVICE); 4330 } 4331 4332 /* move us one more past the eop_desc for start of next pkt */ 4333 tx_buffer++; 4334 i++; 4335 if (unlikely(i == tx_ring->count)) { 4336 i = 0; 4337 tx_buffer = tx_ring->tx_buffer_info; 4338 } 4339 } 4340 4341 /* reset BQL for queue */ 4342 netdev_tx_reset_queue(txring_txq(tx_ring)); 4343 4344 /* reset next_to_use and next_to_clean */ 4345 tx_ring->next_to_use = 0; 4346 tx_ring->next_to_clean = 0; 4347 } 4348 4349 /** 4350 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4351 * @adapter: board private structure 4352 **/ 4353 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4354 { 4355 int i; 4356 4357 for (i = 0; i < adapter->num_tx_queues; i++) 4358 if (adapter->tx_ring[i]) 4359 igb_clean_tx_ring(adapter->tx_ring[i]); 4360 } 4361 4362 /** 4363 * igb_free_rx_resources - Free Rx Resources 4364 * @rx_ring: ring to clean the resources from 4365 * 4366 * Free all receive software resources 4367 **/ 4368 void igb_free_rx_resources(struct igb_ring *rx_ring) 4369 { 4370 igb_clean_rx_ring(rx_ring); 4371 4372 vfree(rx_ring->rx_buffer_info); 4373 rx_ring->rx_buffer_info = NULL; 4374 4375 /* if not set, then don't free */ 4376 if (!rx_ring->desc) 4377 return; 4378 4379 dma_free_coherent(rx_ring->dev, rx_ring->size, 4380 rx_ring->desc, rx_ring->dma); 4381 4382 rx_ring->desc = NULL; 4383 } 4384 4385 /** 4386 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4387 * @adapter: board private structure 4388 * 4389 * Free all receive software resources 4390 **/ 4391 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4392 { 4393 int i; 4394 4395 for (i = 0; i < adapter->num_rx_queues; i++) 4396 if (adapter->rx_ring[i]) 4397 igb_free_rx_resources(adapter->rx_ring[i]); 4398 } 4399 4400 /** 4401 * igb_clean_rx_ring - Free Rx Buffers per Queue 4402 * @rx_ring: ring to free buffers from 4403 **/ 4404 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4405 { 4406 u16 i = rx_ring->next_to_clean; 4407 4408 if (rx_ring->skb) 4409 dev_kfree_skb(rx_ring->skb); 4410 rx_ring->skb = NULL; 4411 4412 /* Free all the Rx ring sk_buffs */ 4413 while (i != rx_ring->next_to_alloc) { 4414 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4415 4416 /* Invalidate cache lines that may have been written to by 4417 * device so that we avoid corrupting memory. 4418 */ 4419 dma_sync_single_range_for_cpu(rx_ring->dev, 4420 buffer_info->dma, 4421 buffer_info->page_offset, 4422 igb_rx_bufsz(rx_ring), 4423 DMA_FROM_DEVICE); 4424 4425 /* free resources associated with mapping */ 4426 dma_unmap_page_attrs(rx_ring->dev, 4427 buffer_info->dma, 4428 igb_rx_pg_size(rx_ring), 4429 DMA_FROM_DEVICE, 4430 IGB_RX_DMA_ATTR); 4431 __page_frag_cache_drain(buffer_info->page, 4432 buffer_info->pagecnt_bias); 4433 4434 i++; 4435 if (i == rx_ring->count) 4436 i = 0; 4437 } 4438 4439 rx_ring->next_to_alloc = 0; 4440 rx_ring->next_to_clean = 0; 4441 rx_ring->next_to_use = 0; 4442 } 4443 4444 /** 4445 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4446 * @adapter: board private structure 4447 **/ 4448 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4449 { 4450 int i; 4451 4452 for (i = 0; i < adapter->num_rx_queues; i++) 4453 if (adapter->rx_ring[i]) 4454 igb_clean_rx_ring(adapter->rx_ring[i]); 4455 } 4456 4457 /** 4458 * igb_set_mac - Change the Ethernet Address of the NIC 4459 * @netdev: network interface device structure 4460 * @p: pointer to an address structure 4461 * 4462 * Returns 0 on success, negative on failure 4463 **/ 4464 static int igb_set_mac(struct net_device *netdev, void *p) 4465 { 4466 struct igb_adapter *adapter = netdev_priv(netdev); 4467 struct e1000_hw *hw = &adapter->hw; 4468 struct sockaddr *addr = p; 4469 4470 if (!is_valid_ether_addr(addr->sa_data)) 4471 return -EADDRNOTAVAIL; 4472 4473 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4474 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4475 4476 /* set the correct pool for the new PF MAC address in entry 0 */ 4477 igb_set_default_mac_filter(adapter); 4478 4479 return 0; 4480 } 4481 4482 /** 4483 * igb_write_mc_addr_list - write multicast addresses to MTA 4484 * @netdev: network interface device structure 4485 * 4486 * Writes multicast address list to the MTA hash table. 4487 * Returns: -ENOMEM on failure 4488 * 0 on no addresses written 4489 * X on writing X addresses to MTA 4490 **/ 4491 static int igb_write_mc_addr_list(struct net_device *netdev) 4492 { 4493 struct igb_adapter *adapter = netdev_priv(netdev); 4494 struct e1000_hw *hw = &adapter->hw; 4495 struct netdev_hw_addr *ha; 4496 u8 *mta_list; 4497 int i; 4498 4499 if (netdev_mc_empty(netdev)) { 4500 /* nothing to program, so clear mc list */ 4501 igb_update_mc_addr_list(hw, NULL, 0); 4502 igb_restore_vf_multicasts(adapter); 4503 return 0; 4504 } 4505 4506 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4507 if (!mta_list) 4508 return -ENOMEM; 4509 4510 /* The shared function expects a packed array of only addresses. */ 4511 i = 0; 4512 netdev_for_each_mc_addr(ha, netdev) 4513 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4514 4515 igb_update_mc_addr_list(hw, mta_list, i); 4516 kfree(mta_list); 4517 4518 return netdev_mc_count(netdev); 4519 } 4520 4521 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4522 { 4523 struct e1000_hw *hw = &adapter->hw; 4524 u32 i, pf_id; 4525 4526 switch (hw->mac.type) { 4527 case e1000_i210: 4528 case e1000_i211: 4529 case e1000_i350: 4530 /* VLAN filtering needed for VLAN prio filter */ 4531 if (adapter->netdev->features & NETIF_F_NTUPLE) 4532 break; 4533 /* fall through */ 4534 case e1000_82576: 4535 case e1000_82580: 4536 case e1000_i354: 4537 /* VLAN filtering needed for pool filtering */ 4538 if (adapter->vfs_allocated_count) 4539 break; 4540 /* fall through */ 4541 default: 4542 return 1; 4543 } 4544 4545 /* We are already in VLAN promisc, nothing to do */ 4546 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4547 return 0; 4548 4549 if (!adapter->vfs_allocated_count) 4550 goto set_vfta; 4551 4552 /* Add PF to all active pools */ 4553 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4554 4555 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4556 u32 vlvf = rd32(E1000_VLVF(i)); 4557 4558 vlvf |= BIT(pf_id); 4559 wr32(E1000_VLVF(i), vlvf); 4560 } 4561 4562 set_vfta: 4563 /* Set all bits in the VLAN filter table array */ 4564 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4565 hw->mac.ops.write_vfta(hw, i, ~0U); 4566 4567 /* Set flag so we don't redo unnecessary work */ 4568 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4569 4570 return 0; 4571 } 4572 4573 #define VFTA_BLOCK_SIZE 8 4574 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4575 { 4576 struct e1000_hw *hw = &adapter->hw; 4577 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4578 u32 vid_start = vfta_offset * 32; 4579 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4580 u32 i, vid, word, bits, pf_id; 4581 4582 /* guarantee that we don't scrub out management VLAN */ 4583 vid = adapter->mng_vlan_id; 4584 if (vid >= vid_start && vid < vid_end) 4585 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4586 4587 if (!adapter->vfs_allocated_count) 4588 goto set_vfta; 4589 4590 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4591 4592 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4593 u32 vlvf = rd32(E1000_VLVF(i)); 4594 4595 /* pull VLAN ID from VLVF */ 4596 vid = vlvf & VLAN_VID_MASK; 4597 4598 /* only concern ourselves with a certain range */ 4599 if (vid < vid_start || vid >= vid_end) 4600 continue; 4601 4602 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4603 /* record VLAN ID in VFTA */ 4604 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4605 4606 /* if PF is part of this then continue */ 4607 if (test_bit(vid, adapter->active_vlans)) 4608 continue; 4609 } 4610 4611 /* remove PF from the pool */ 4612 bits = ~BIT(pf_id); 4613 bits &= rd32(E1000_VLVF(i)); 4614 wr32(E1000_VLVF(i), bits); 4615 } 4616 4617 set_vfta: 4618 /* extract values from active_vlans and write back to VFTA */ 4619 for (i = VFTA_BLOCK_SIZE; i--;) { 4620 vid = (vfta_offset + i) * 32; 4621 word = vid / BITS_PER_LONG; 4622 bits = vid % BITS_PER_LONG; 4623 4624 vfta[i] |= adapter->active_vlans[word] >> bits; 4625 4626 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4627 } 4628 } 4629 4630 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4631 { 4632 u32 i; 4633 4634 /* We are not in VLAN promisc, nothing to do */ 4635 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4636 return; 4637 4638 /* Set flag so we don't redo unnecessary work */ 4639 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4640 4641 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4642 igb_scrub_vfta(adapter, i); 4643 } 4644 4645 /** 4646 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4647 * @netdev: network interface device structure 4648 * 4649 * The set_rx_mode entry point is called whenever the unicast or multicast 4650 * address lists or the network interface flags are updated. This routine is 4651 * responsible for configuring the hardware for proper unicast, multicast, 4652 * promiscuous mode, and all-multi behavior. 4653 **/ 4654 static void igb_set_rx_mode(struct net_device *netdev) 4655 { 4656 struct igb_adapter *adapter = netdev_priv(netdev); 4657 struct e1000_hw *hw = &adapter->hw; 4658 unsigned int vfn = adapter->vfs_allocated_count; 4659 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4660 int count; 4661 4662 /* Check for Promiscuous and All Multicast modes */ 4663 if (netdev->flags & IFF_PROMISC) { 4664 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4665 vmolr |= E1000_VMOLR_MPME; 4666 4667 /* enable use of UTA filter to force packets to default pool */ 4668 if (hw->mac.type == e1000_82576) 4669 vmolr |= E1000_VMOLR_ROPE; 4670 } else { 4671 if (netdev->flags & IFF_ALLMULTI) { 4672 rctl |= E1000_RCTL_MPE; 4673 vmolr |= E1000_VMOLR_MPME; 4674 } else { 4675 /* Write addresses to the MTA, if the attempt fails 4676 * then we should just turn on promiscuous mode so 4677 * that we can at least receive multicast traffic 4678 */ 4679 count = igb_write_mc_addr_list(netdev); 4680 if (count < 0) { 4681 rctl |= E1000_RCTL_MPE; 4682 vmolr |= E1000_VMOLR_MPME; 4683 } else if (count) { 4684 vmolr |= E1000_VMOLR_ROMPE; 4685 } 4686 } 4687 } 4688 4689 /* Write addresses to available RAR registers, if there is not 4690 * sufficient space to store all the addresses then enable 4691 * unicast promiscuous mode 4692 */ 4693 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 4694 rctl |= E1000_RCTL_UPE; 4695 vmolr |= E1000_VMOLR_ROPE; 4696 } 4697 4698 /* enable VLAN filtering by default */ 4699 rctl |= E1000_RCTL_VFE; 4700 4701 /* disable VLAN filtering for modes that require it */ 4702 if ((netdev->flags & IFF_PROMISC) || 4703 (netdev->features & NETIF_F_RXALL)) { 4704 /* if we fail to set all rules then just clear VFE */ 4705 if (igb_vlan_promisc_enable(adapter)) 4706 rctl &= ~E1000_RCTL_VFE; 4707 } else { 4708 igb_vlan_promisc_disable(adapter); 4709 } 4710 4711 /* update state of unicast, multicast, and VLAN filtering modes */ 4712 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4713 E1000_RCTL_VFE); 4714 wr32(E1000_RCTL, rctl); 4715 4716 #if (PAGE_SIZE < 8192) 4717 if (!adapter->vfs_allocated_count) { 4718 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4719 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4720 } 4721 #endif 4722 wr32(E1000_RLPML, rlpml); 4723 4724 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4725 * the VMOLR to enable the appropriate modes. Without this workaround 4726 * we will have issues with VLAN tag stripping not being done for frames 4727 * that are only arriving because we are the default pool 4728 */ 4729 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4730 return; 4731 4732 /* set UTA to appropriate mode */ 4733 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4734 4735 vmolr |= rd32(E1000_VMOLR(vfn)) & 4736 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4737 4738 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4739 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4740 #if (PAGE_SIZE < 8192) 4741 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4742 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4743 else 4744 #endif 4745 vmolr |= MAX_JUMBO_FRAME_SIZE; 4746 vmolr |= E1000_VMOLR_LPE; 4747 4748 wr32(E1000_VMOLR(vfn), vmolr); 4749 4750 igb_restore_vf_multicasts(adapter); 4751 } 4752 4753 static void igb_check_wvbr(struct igb_adapter *adapter) 4754 { 4755 struct e1000_hw *hw = &adapter->hw; 4756 u32 wvbr = 0; 4757 4758 switch (hw->mac.type) { 4759 case e1000_82576: 4760 case e1000_i350: 4761 wvbr = rd32(E1000_WVBR); 4762 if (!wvbr) 4763 return; 4764 break; 4765 default: 4766 break; 4767 } 4768 4769 adapter->wvbr |= wvbr; 4770 } 4771 4772 #define IGB_STAGGERED_QUEUE_OFFSET 8 4773 4774 static void igb_spoof_check(struct igb_adapter *adapter) 4775 { 4776 int j; 4777 4778 if (!adapter->wvbr) 4779 return; 4780 4781 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4782 if (adapter->wvbr & BIT(j) || 4783 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4784 dev_warn(&adapter->pdev->dev, 4785 "Spoof event(s) detected on VF %d\n", j); 4786 adapter->wvbr &= 4787 ~(BIT(j) | 4788 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4789 } 4790 } 4791 } 4792 4793 /* Need to wait a few seconds after link up to get diagnostic information from 4794 * the phy 4795 */ 4796 static void igb_update_phy_info(struct timer_list *t) 4797 { 4798 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4799 igb_get_phy_info(&adapter->hw); 4800 } 4801 4802 /** 4803 * igb_has_link - check shared code for link and determine up/down 4804 * @adapter: pointer to driver private info 4805 **/ 4806 bool igb_has_link(struct igb_adapter *adapter) 4807 { 4808 struct e1000_hw *hw = &adapter->hw; 4809 bool link_active = false; 4810 4811 /* get_link_status is set on LSC (link status) interrupt or 4812 * rx sequence error interrupt. get_link_status will stay 4813 * false until the e1000_check_for_link establishes link 4814 * for copper adapters ONLY 4815 */ 4816 switch (hw->phy.media_type) { 4817 case e1000_media_type_copper: 4818 if (!hw->mac.get_link_status) 4819 return true; 4820 case e1000_media_type_internal_serdes: 4821 hw->mac.ops.check_for_link(hw); 4822 link_active = !hw->mac.get_link_status; 4823 break; 4824 default: 4825 case e1000_media_type_unknown: 4826 break; 4827 } 4828 4829 if (((hw->mac.type == e1000_i210) || 4830 (hw->mac.type == e1000_i211)) && 4831 (hw->phy.id == I210_I_PHY_ID)) { 4832 if (!netif_carrier_ok(adapter->netdev)) { 4833 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4834 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4835 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4836 adapter->link_check_timeout = jiffies; 4837 } 4838 } 4839 4840 return link_active; 4841 } 4842 4843 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4844 { 4845 bool ret = false; 4846 u32 ctrl_ext, thstat; 4847 4848 /* check for thermal sensor event on i350 copper only */ 4849 if (hw->mac.type == e1000_i350) { 4850 thstat = rd32(E1000_THSTAT); 4851 ctrl_ext = rd32(E1000_CTRL_EXT); 4852 4853 if ((hw->phy.media_type == e1000_media_type_copper) && 4854 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4855 ret = !!(thstat & event); 4856 } 4857 4858 return ret; 4859 } 4860 4861 /** 4862 * igb_check_lvmmc - check for malformed packets received 4863 * and indicated in LVMMC register 4864 * @adapter: pointer to adapter 4865 **/ 4866 static void igb_check_lvmmc(struct igb_adapter *adapter) 4867 { 4868 struct e1000_hw *hw = &adapter->hw; 4869 u32 lvmmc; 4870 4871 lvmmc = rd32(E1000_LVMMC); 4872 if (lvmmc) { 4873 if (unlikely(net_ratelimit())) { 4874 netdev_warn(adapter->netdev, 4875 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4876 lvmmc); 4877 } 4878 } 4879 } 4880 4881 /** 4882 * igb_watchdog - Timer Call-back 4883 * @data: pointer to adapter cast into an unsigned long 4884 **/ 4885 static void igb_watchdog(struct timer_list *t) 4886 { 4887 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 4888 /* Do the rest outside of interrupt context */ 4889 schedule_work(&adapter->watchdog_task); 4890 } 4891 4892 static void igb_watchdog_task(struct work_struct *work) 4893 { 4894 struct igb_adapter *adapter = container_of(work, 4895 struct igb_adapter, 4896 watchdog_task); 4897 struct e1000_hw *hw = &adapter->hw; 4898 struct e1000_phy_info *phy = &hw->phy; 4899 struct net_device *netdev = adapter->netdev; 4900 u32 link; 4901 int i; 4902 u32 connsw; 4903 u16 phy_data, retry_count = 20; 4904 4905 link = igb_has_link(adapter); 4906 4907 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4908 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4909 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4910 else 4911 link = false; 4912 } 4913 4914 /* Force link down if we have fiber to swap to */ 4915 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4916 if (hw->phy.media_type == e1000_media_type_copper) { 4917 connsw = rd32(E1000_CONNSW); 4918 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4919 link = 0; 4920 } 4921 } 4922 if (link) { 4923 /* Perform a reset if the media type changed. */ 4924 if (hw->dev_spec._82575.media_changed) { 4925 hw->dev_spec._82575.media_changed = false; 4926 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4927 igb_reset(adapter); 4928 } 4929 /* Cancel scheduled suspend requests. */ 4930 pm_runtime_resume(netdev->dev.parent); 4931 4932 if (!netif_carrier_ok(netdev)) { 4933 u32 ctrl; 4934 4935 hw->mac.ops.get_speed_and_duplex(hw, 4936 &adapter->link_speed, 4937 &adapter->link_duplex); 4938 4939 ctrl = rd32(E1000_CTRL); 4940 /* Links status message must follow this format */ 4941 netdev_info(netdev, 4942 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4943 netdev->name, 4944 adapter->link_speed, 4945 adapter->link_duplex == FULL_DUPLEX ? 4946 "Full" : "Half", 4947 (ctrl & E1000_CTRL_TFCE) && 4948 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4949 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4950 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4951 4952 /* disable EEE if enabled */ 4953 if ((adapter->flags & IGB_FLAG_EEE) && 4954 (adapter->link_duplex == HALF_DUPLEX)) { 4955 dev_info(&adapter->pdev->dev, 4956 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4957 adapter->hw.dev_spec._82575.eee_disable = true; 4958 adapter->flags &= ~IGB_FLAG_EEE; 4959 } 4960 4961 /* check if SmartSpeed worked */ 4962 igb_check_downshift(hw); 4963 if (phy->speed_downgraded) 4964 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4965 4966 /* check for thermal sensor event */ 4967 if (igb_thermal_sensor_event(hw, 4968 E1000_THSTAT_LINK_THROTTLE)) 4969 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4970 4971 /* adjust timeout factor according to speed/duplex */ 4972 adapter->tx_timeout_factor = 1; 4973 switch (adapter->link_speed) { 4974 case SPEED_10: 4975 adapter->tx_timeout_factor = 14; 4976 break; 4977 case SPEED_100: 4978 /* maybe add some timeout factor ? */ 4979 break; 4980 } 4981 4982 if (adapter->link_speed != SPEED_1000) 4983 goto no_wait; 4984 4985 /* wait for Remote receiver status OK */ 4986 retry_read_status: 4987 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4988 &phy_data)) { 4989 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4990 retry_count) { 4991 msleep(100); 4992 retry_count--; 4993 goto retry_read_status; 4994 } else if (!retry_count) { 4995 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4996 } 4997 } else { 4998 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4999 } 5000 no_wait: 5001 netif_carrier_on(netdev); 5002 5003 igb_ping_all_vfs(adapter); 5004 igb_check_vf_rate_limit(adapter); 5005 5006 /* link state has changed, schedule phy info update */ 5007 if (!test_bit(__IGB_DOWN, &adapter->state)) 5008 mod_timer(&adapter->phy_info_timer, 5009 round_jiffies(jiffies + 2 * HZ)); 5010 } 5011 } else { 5012 if (netif_carrier_ok(netdev)) { 5013 adapter->link_speed = 0; 5014 adapter->link_duplex = 0; 5015 5016 /* check for thermal sensor event */ 5017 if (igb_thermal_sensor_event(hw, 5018 E1000_THSTAT_PWR_DOWN)) { 5019 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5020 } 5021 5022 /* Links status message must follow this format */ 5023 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5024 netdev->name); 5025 netif_carrier_off(netdev); 5026 5027 igb_ping_all_vfs(adapter); 5028 5029 /* link state has changed, schedule phy info update */ 5030 if (!test_bit(__IGB_DOWN, &adapter->state)) 5031 mod_timer(&adapter->phy_info_timer, 5032 round_jiffies(jiffies + 2 * HZ)); 5033 5034 /* link is down, time to check for alternate media */ 5035 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5036 igb_check_swap_media(adapter); 5037 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5038 schedule_work(&adapter->reset_task); 5039 /* return immediately */ 5040 return; 5041 } 5042 } 5043 pm_schedule_suspend(netdev->dev.parent, 5044 MSEC_PER_SEC * 5); 5045 5046 /* also check for alternate media here */ 5047 } else if (!netif_carrier_ok(netdev) && 5048 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5049 igb_check_swap_media(adapter); 5050 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5051 schedule_work(&adapter->reset_task); 5052 /* return immediately */ 5053 return; 5054 } 5055 } 5056 } 5057 5058 spin_lock(&adapter->stats64_lock); 5059 igb_update_stats(adapter); 5060 spin_unlock(&adapter->stats64_lock); 5061 5062 for (i = 0; i < adapter->num_tx_queues; i++) { 5063 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5064 if (!netif_carrier_ok(netdev)) { 5065 /* We've lost link, so the controller stops DMA, 5066 * but we've got queued Tx work that's never going 5067 * to get done, so reset controller to flush Tx. 5068 * (Do the reset outside of interrupt context). 5069 */ 5070 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5071 adapter->tx_timeout_count++; 5072 schedule_work(&adapter->reset_task); 5073 /* return immediately since reset is imminent */ 5074 return; 5075 } 5076 } 5077 5078 /* Force detection of hung controller every watchdog period */ 5079 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5080 } 5081 5082 /* Cause software interrupt to ensure Rx ring is cleaned */ 5083 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5084 u32 eics = 0; 5085 5086 for (i = 0; i < adapter->num_q_vectors; i++) 5087 eics |= adapter->q_vector[i]->eims_value; 5088 wr32(E1000_EICS, eics); 5089 } else { 5090 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5091 } 5092 5093 igb_spoof_check(adapter); 5094 igb_ptp_rx_hang(adapter); 5095 igb_ptp_tx_hang(adapter); 5096 5097 /* Check LVMMC register on i350/i354 only */ 5098 if ((adapter->hw.mac.type == e1000_i350) || 5099 (adapter->hw.mac.type == e1000_i354)) 5100 igb_check_lvmmc(adapter); 5101 5102 /* Reset the timer */ 5103 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5104 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5105 mod_timer(&adapter->watchdog_timer, 5106 round_jiffies(jiffies + HZ)); 5107 else 5108 mod_timer(&adapter->watchdog_timer, 5109 round_jiffies(jiffies + 2 * HZ)); 5110 } 5111 } 5112 5113 enum latency_range { 5114 lowest_latency = 0, 5115 low_latency = 1, 5116 bulk_latency = 2, 5117 latency_invalid = 255 5118 }; 5119 5120 /** 5121 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5122 * @q_vector: pointer to q_vector 5123 * 5124 * Stores a new ITR value based on strictly on packet size. This 5125 * algorithm is less sophisticated than that used in igb_update_itr, 5126 * due to the difficulty of synchronizing statistics across multiple 5127 * receive rings. The divisors and thresholds used by this function 5128 * were determined based on theoretical maximum wire speed and testing 5129 * data, in order to minimize response time while increasing bulk 5130 * throughput. 5131 * This functionality is controlled by ethtool's coalescing settings. 5132 * NOTE: This function is called only when operating in a multiqueue 5133 * receive environment. 5134 **/ 5135 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5136 { 5137 int new_val = q_vector->itr_val; 5138 int avg_wire_size = 0; 5139 struct igb_adapter *adapter = q_vector->adapter; 5140 unsigned int packets; 5141 5142 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5143 * ints/sec - ITR timer value of 120 ticks. 5144 */ 5145 if (adapter->link_speed != SPEED_1000) { 5146 new_val = IGB_4K_ITR; 5147 goto set_itr_val; 5148 } 5149 5150 packets = q_vector->rx.total_packets; 5151 if (packets) 5152 avg_wire_size = q_vector->rx.total_bytes / packets; 5153 5154 packets = q_vector->tx.total_packets; 5155 if (packets) 5156 avg_wire_size = max_t(u32, avg_wire_size, 5157 q_vector->tx.total_bytes / packets); 5158 5159 /* if avg_wire_size isn't set no work was done */ 5160 if (!avg_wire_size) 5161 goto clear_counts; 5162 5163 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5164 avg_wire_size += 24; 5165 5166 /* Don't starve jumbo frames */ 5167 avg_wire_size = min(avg_wire_size, 3000); 5168 5169 /* Give a little boost to mid-size frames */ 5170 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5171 new_val = avg_wire_size / 3; 5172 else 5173 new_val = avg_wire_size / 2; 5174 5175 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5176 if (new_val < IGB_20K_ITR && 5177 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5178 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5179 new_val = IGB_20K_ITR; 5180 5181 set_itr_val: 5182 if (new_val != q_vector->itr_val) { 5183 q_vector->itr_val = new_val; 5184 q_vector->set_itr = 1; 5185 } 5186 clear_counts: 5187 q_vector->rx.total_bytes = 0; 5188 q_vector->rx.total_packets = 0; 5189 q_vector->tx.total_bytes = 0; 5190 q_vector->tx.total_packets = 0; 5191 } 5192 5193 /** 5194 * igb_update_itr - update the dynamic ITR value based on statistics 5195 * @q_vector: pointer to q_vector 5196 * @ring_container: ring info to update the itr for 5197 * 5198 * Stores a new ITR value based on packets and byte 5199 * counts during the last interrupt. The advantage of per interrupt 5200 * computation is faster updates and more accurate ITR for the current 5201 * traffic pattern. Constants in this function were computed 5202 * based on theoretical maximum wire speed and thresholds were set based 5203 * on testing data as well as attempting to minimize response time 5204 * while increasing bulk throughput. 5205 * This functionality is controlled by ethtool's coalescing settings. 5206 * NOTE: These calculations are only valid when operating in a single- 5207 * queue environment. 5208 **/ 5209 static void igb_update_itr(struct igb_q_vector *q_vector, 5210 struct igb_ring_container *ring_container) 5211 { 5212 unsigned int packets = ring_container->total_packets; 5213 unsigned int bytes = ring_container->total_bytes; 5214 u8 itrval = ring_container->itr; 5215 5216 /* no packets, exit with status unchanged */ 5217 if (packets == 0) 5218 return; 5219 5220 switch (itrval) { 5221 case lowest_latency: 5222 /* handle TSO and jumbo frames */ 5223 if (bytes/packets > 8000) 5224 itrval = bulk_latency; 5225 else if ((packets < 5) && (bytes > 512)) 5226 itrval = low_latency; 5227 break; 5228 case low_latency: /* 50 usec aka 20000 ints/s */ 5229 if (bytes > 10000) { 5230 /* this if handles the TSO accounting */ 5231 if (bytes/packets > 8000) 5232 itrval = bulk_latency; 5233 else if ((packets < 10) || ((bytes/packets) > 1200)) 5234 itrval = bulk_latency; 5235 else if ((packets > 35)) 5236 itrval = lowest_latency; 5237 } else if (bytes/packets > 2000) { 5238 itrval = bulk_latency; 5239 } else if (packets <= 2 && bytes < 512) { 5240 itrval = lowest_latency; 5241 } 5242 break; 5243 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5244 if (bytes > 25000) { 5245 if (packets > 35) 5246 itrval = low_latency; 5247 } else if (bytes < 1500) { 5248 itrval = low_latency; 5249 } 5250 break; 5251 } 5252 5253 /* clear work counters since we have the values we need */ 5254 ring_container->total_bytes = 0; 5255 ring_container->total_packets = 0; 5256 5257 /* write updated itr to ring container */ 5258 ring_container->itr = itrval; 5259 } 5260 5261 static void igb_set_itr(struct igb_q_vector *q_vector) 5262 { 5263 struct igb_adapter *adapter = q_vector->adapter; 5264 u32 new_itr = q_vector->itr_val; 5265 u8 current_itr = 0; 5266 5267 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5268 if (adapter->link_speed != SPEED_1000) { 5269 current_itr = 0; 5270 new_itr = IGB_4K_ITR; 5271 goto set_itr_now; 5272 } 5273 5274 igb_update_itr(q_vector, &q_vector->tx); 5275 igb_update_itr(q_vector, &q_vector->rx); 5276 5277 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5278 5279 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5280 if (current_itr == lowest_latency && 5281 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5282 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5283 current_itr = low_latency; 5284 5285 switch (current_itr) { 5286 /* counts and packets in update_itr are dependent on these numbers */ 5287 case lowest_latency: 5288 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5289 break; 5290 case low_latency: 5291 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5292 break; 5293 case bulk_latency: 5294 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5295 break; 5296 default: 5297 break; 5298 } 5299 5300 set_itr_now: 5301 if (new_itr != q_vector->itr_val) { 5302 /* this attempts to bias the interrupt rate towards Bulk 5303 * by adding intermediate steps when interrupt rate is 5304 * increasing 5305 */ 5306 new_itr = new_itr > q_vector->itr_val ? 5307 max((new_itr * q_vector->itr_val) / 5308 (new_itr + (q_vector->itr_val >> 2)), 5309 new_itr) : new_itr; 5310 /* Don't write the value here; it resets the adapter's 5311 * internal timer, and causes us to delay far longer than 5312 * we should between interrupts. Instead, we write the ITR 5313 * value at the beginning of the next interrupt so the timing 5314 * ends up being correct. 5315 */ 5316 q_vector->itr_val = new_itr; 5317 q_vector->set_itr = 1; 5318 } 5319 } 5320 5321 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 5322 u32 type_tucmd, u32 mss_l4len_idx) 5323 { 5324 struct e1000_adv_tx_context_desc *context_desc; 5325 u16 i = tx_ring->next_to_use; 5326 5327 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5328 5329 i++; 5330 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5331 5332 /* set bits to identify this as an advanced context descriptor */ 5333 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5334 5335 /* For 82575, context index must be unique per ring. */ 5336 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5337 mss_l4len_idx |= tx_ring->reg_idx << 4; 5338 5339 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5340 context_desc->seqnum_seed = 0; 5341 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5342 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5343 } 5344 5345 static int igb_tso(struct igb_ring *tx_ring, 5346 struct igb_tx_buffer *first, 5347 u8 *hdr_len) 5348 { 5349 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5350 struct sk_buff *skb = first->skb; 5351 union { 5352 struct iphdr *v4; 5353 struct ipv6hdr *v6; 5354 unsigned char *hdr; 5355 } ip; 5356 union { 5357 struct tcphdr *tcp; 5358 unsigned char *hdr; 5359 } l4; 5360 u32 paylen, l4_offset; 5361 int err; 5362 5363 if (skb->ip_summed != CHECKSUM_PARTIAL) 5364 return 0; 5365 5366 if (!skb_is_gso(skb)) 5367 return 0; 5368 5369 err = skb_cow_head(skb, 0); 5370 if (err < 0) 5371 return err; 5372 5373 ip.hdr = skb_network_header(skb); 5374 l4.hdr = skb_checksum_start(skb); 5375 5376 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5377 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5378 5379 /* initialize outer IP header fields */ 5380 if (ip.v4->version == 4) { 5381 unsigned char *csum_start = skb_checksum_start(skb); 5382 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5383 5384 /* IP header will have to cancel out any data that 5385 * is not a part of the outer IP header 5386 */ 5387 ip.v4->check = csum_fold(csum_partial(trans_start, 5388 csum_start - trans_start, 5389 0)); 5390 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5391 5392 ip.v4->tot_len = 0; 5393 first->tx_flags |= IGB_TX_FLAGS_TSO | 5394 IGB_TX_FLAGS_CSUM | 5395 IGB_TX_FLAGS_IPV4; 5396 } else { 5397 ip.v6->payload_len = 0; 5398 first->tx_flags |= IGB_TX_FLAGS_TSO | 5399 IGB_TX_FLAGS_CSUM; 5400 } 5401 5402 /* determine offset of inner transport header */ 5403 l4_offset = l4.hdr - skb->data; 5404 5405 /* compute length of segmentation header */ 5406 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5407 5408 /* remove payload length from inner checksum */ 5409 paylen = skb->len - l4_offset; 5410 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5411 5412 /* update gso size and bytecount with header size */ 5413 first->gso_segs = skb_shinfo(skb)->gso_segs; 5414 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5415 5416 /* MSS L4LEN IDX */ 5417 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5418 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5419 5420 /* VLAN MACLEN IPLEN */ 5421 vlan_macip_lens = l4.hdr - ip.hdr; 5422 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5423 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5424 5425 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5426 5427 return 1; 5428 } 5429 5430 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5431 { 5432 unsigned int offset = 0; 5433 5434 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5435 5436 return offset == skb_checksum_start_offset(skb); 5437 } 5438 5439 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5440 { 5441 struct sk_buff *skb = first->skb; 5442 u32 vlan_macip_lens = 0; 5443 u32 type_tucmd = 0; 5444 5445 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5446 csum_failed: 5447 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5448 return; 5449 goto no_csum; 5450 } 5451 5452 switch (skb->csum_offset) { 5453 case offsetof(struct tcphdr, check): 5454 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5455 /* fall through */ 5456 case offsetof(struct udphdr, check): 5457 break; 5458 case offsetof(struct sctphdr, checksum): 5459 /* validate that this is actually an SCTP request */ 5460 if (((first->protocol == htons(ETH_P_IP)) && 5461 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5462 ((first->protocol == htons(ETH_P_IPV6)) && 5463 igb_ipv6_csum_is_sctp(skb))) { 5464 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5465 break; 5466 } 5467 default: 5468 skb_checksum_help(skb); 5469 goto csum_failed; 5470 } 5471 5472 /* update TX checksum flag */ 5473 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5474 vlan_macip_lens = skb_checksum_start_offset(skb) - 5475 skb_network_offset(skb); 5476 no_csum: 5477 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5478 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5479 5480 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5481 } 5482 5483 #define IGB_SET_FLAG(_input, _flag, _result) \ 5484 ((_flag <= _result) ? \ 5485 ((u32)(_input & _flag) * (_result / _flag)) : \ 5486 ((u32)(_input & _flag) / (_flag / _result))) 5487 5488 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5489 { 5490 /* set type for advanced descriptor with frame checksum insertion */ 5491 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5492 E1000_ADVTXD_DCMD_DEXT | 5493 E1000_ADVTXD_DCMD_IFCS; 5494 5495 /* set HW vlan bit if vlan is present */ 5496 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5497 (E1000_ADVTXD_DCMD_VLE)); 5498 5499 /* set segmentation bits for TSO */ 5500 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5501 (E1000_ADVTXD_DCMD_TSE)); 5502 5503 /* set timestamp bit if present */ 5504 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5505 (E1000_ADVTXD_MAC_TSTAMP)); 5506 5507 /* insert frame checksum */ 5508 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5509 5510 return cmd_type; 5511 } 5512 5513 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5514 union e1000_adv_tx_desc *tx_desc, 5515 u32 tx_flags, unsigned int paylen) 5516 { 5517 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5518 5519 /* 82575 requires a unique index per ring */ 5520 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5521 olinfo_status |= tx_ring->reg_idx << 4; 5522 5523 /* insert L4 checksum */ 5524 olinfo_status |= IGB_SET_FLAG(tx_flags, 5525 IGB_TX_FLAGS_CSUM, 5526 (E1000_TXD_POPTS_TXSM << 8)); 5527 5528 /* insert IPv4 checksum */ 5529 olinfo_status |= IGB_SET_FLAG(tx_flags, 5530 IGB_TX_FLAGS_IPV4, 5531 (E1000_TXD_POPTS_IXSM << 8)); 5532 5533 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5534 } 5535 5536 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5537 { 5538 struct net_device *netdev = tx_ring->netdev; 5539 5540 netif_stop_subqueue(netdev, tx_ring->queue_index); 5541 5542 /* Herbert's original patch had: 5543 * smp_mb__after_netif_stop_queue(); 5544 * but since that doesn't exist yet, just open code it. 5545 */ 5546 smp_mb(); 5547 5548 /* We need to check again in a case another CPU has just 5549 * made room available. 5550 */ 5551 if (igb_desc_unused(tx_ring) < size) 5552 return -EBUSY; 5553 5554 /* A reprieve! */ 5555 netif_wake_subqueue(netdev, tx_ring->queue_index); 5556 5557 u64_stats_update_begin(&tx_ring->tx_syncp2); 5558 tx_ring->tx_stats.restart_queue2++; 5559 u64_stats_update_end(&tx_ring->tx_syncp2); 5560 5561 return 0; 5562 } 5563 5564 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5565 { 5566 if (igb_desc_unused(tx_ring) >= size) 5567 return 0; 5568 return __igb_maybe_stop_tx(tx_ring, size); 5569 } 5570 5571 static int igb_tx_map(struct igb_ring *tx_ring, 5572 struct igb_tx_buffer *first, 5573 const u8 hdr_len) 5574 { 5575 struct sk_buff *skb = first->skb; 5576 struct igb_tx_buffer *tx_buffer; 5577 union e1000_adv_tx_desc *tx_desc; 5578 struct skb_frag_struct *frag; 5579 dma_addr_t dma; 5580 unsigned int data_len, size; 5581 u32 tx_flags = first->tx_flags; 5582 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5583 u16 i = tx_ring->next_to_use; 5584 5585 tx_desc = IGB_TX_DESC(tx_ring, i); 5586 5587 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5588 5589 size = skb_headlen(skb); 5590 data_len = skb->data_len; 5591 5592 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5593 5594 tx_buffer = first; 5595 5596 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5597 if (dma_mapping_error(tx_ring->dev, dma)) 5598 goto dma_error; 5599 5600 /* record length, and DMA address */ 5601 dma_unmap_len_set(tx_buffer, len, size); 5602 dma_unmap_addr_set(tx_buffer, dma, dma); 5603 5604 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5605 5606 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5607 tx_desc->read.cmd_type_len = 5608 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5609 5610 i++; 5611 tx_desc++; 5612 if (i == tx_ring->count) { 5613 tx_desc = IGB_TX_DESC(tx_ring, 0); 5614 i = 0; 5615 } 5616 tx_desc->read.olinfo_status = 0; 5617 5618 dma += IGB_MAX_DATA_PER_TXD; 5619 size -= IGB_MAX_DATA_PER_TXD; 5620 5621 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5622 } 5623 5624 if (likely(!data_len)) 5625 break; 5626 5627 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5628 5629 i++; 5630 tx_desc++; 5631 if (i == tx_ring->count) { 5632 tx_desc = IGB_TX_DESC(tx_ring, 0); 5633 i = 0; 5634 } 5635 tx_desc->read.olinfo_status = 0; 5636 5637 size = skb_frag_size(frag); 5638 data_len -= size; 5639 5640 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5641 size, DMA_TO_DEVICE); 5642 5643 tx_buffer = &tx_ring->tx_buffer_info[i]; 5644 } 5645 5646 /* write last descriptor with RS and EOP bits */ 5647 cmd_type |= size | IGB_TXD_DCMD; 5648 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5649 5650 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5651 5652 /* set the timestamp */ 5653 first->time_stamp = jiffies; 5654 5655 /* Force memory writes to complete before letting h/w know there 5656 * are new descriptors to fetch. (Only applicable for weak-ordered 5657 * memory model archs, such as IA-64). 5658 * 5659 * We also need this memory barrier to make certain all of the 5660 * status bits have been updated before next_to_watch is written. 5661 */ 5662 wmb(); 5663 5664 /* set next_to_watch value indicating a packet is present */ 5665 first->next_to_watch = tx_desc; 5666 5667 i++; 5668 if (i == tx_ring->count) 5669 i = 0; 5670 5671 tx_ring->next_to_use = i; 5672 5673 /* Make sure there is space in the ring for the next send. */ 5674 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5675 5676 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5677 writel(i, tx_ring->tail); 5678 5679 /* we need this if more than one processor can write to our tail 5680 * at a time, it synchronizes IO on IA64/Altix systems 5681 */ 5682 mmiowb(); 5683 } 5684 return 0; 5685 5686 dma_error: 5687 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5688 tx_buffer = &tx_ring->tx_buffer_info[i]; 5689 5690 /* clear dma mappings for failed tx_buffer_info map */ 5691 while (tx_buffer != first) { 5692 if (dma_unmap_len(tx_buffer, len)) 5693 dma_unmap_page(tx_ring->dev, 5694 dma_unmap_addr(tx_buffer, dma), 5695 dma_unmap_len(tx_buffer, len), 5696 DMA_TO_DEVICE); 5697 dma_unmap_len_set(tx_buffer, len, 0); 5698 5699 if (i-- == 0) 5700 i += tx_ring->count; 5701 tx_buffer = &tx_ring->tx_buffer_info[i]; 5702 } 5703 5704 if (dma_unmap_len(tx_buffer, len)) 5705 dma_unmap_single(tx_ring->dev, 5706 dma_unmap_addr(tx_buffer, dma), 5707 dma_unmap_len(tx_buffer, len), 5708 DMA_TO_DEVICE); 5709 dma_unmap_len_set(tx_buffer, len, 0); 5710 5711 dev_kfree_skb_any(tx_buffer->skb); 5712 tx_buffer->skb = NULL; 5713 5714 tx_ring->next_to_use = i; 5715 5716 return -1; 5717 } 5718 5719 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5720 struct igb_ring *tx_ring) 5721 { 5722 struct igb_tx_buffer *first; 5723 int tso; 5724 u32 tx_flags = 0; 5725 unsigned short f; 5726 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5727 __be16 protocol = vlan_get_protocol(skb); 5728 u8 hdr_len = 0; 5729 5730 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5731 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5732 * + 2 desc gap to keep tail from touching head, 5733 * + 1 desc for context descriptor, 5734 * otherwise try next time 5735 */ 5736 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5737 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5738 5739 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5740 /* this is a hard error */ 5741 return NETDEV_TX_BUSY; 5742 } 5743 5744 /* record the location of the first descriptor for this packet */ 5745 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5746 first->skb = skb; 5747 first->bytecount = skb->len; 5748 first->gso_segs = 1; 5749 5750 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5751 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5752 5753 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 5754 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5755 &adapter->state)) { 5756 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5757 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5758 5759 adapter->ptp_tx_skb = skb_get(skb); 5760 adapter->ptp_tx_start = jiffies; 5761 if (adapter->hw.mac.type == e1000_82576) 5762 schedule_work(&adapter->ptp_tx_work); 5763 } else { 5764 adapter->tx_hwtstamp_skipped++; 5765 } 5766 } 5767 5768 skb_tx_timestamp(skb); 5769 5770 if (skb_vlan_tag_present(skb)) { 5771 tx_flags |= IGB_TX_FLAGS_VLAN; 5772 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5773 } 5774 5775 /* record initial flags and protocol */ 5776 first->tx_flags = tx_flags; 5777 first->protocol = protocol; 5778 5779 tso = igb_tso(tx_ring, first, &hdr_len); 5780 if (tso < 0) 5781 goto out_drop; 5782 else if (!tso) 5783 igb_tx_csum(tx_ring, first); 5784 5785 if (igb_tx_map(tx_ring, first, hdr_len)) 5786 goto cleanup_tx_tstamp; 5787 5788 return NETDEV_TX_OK; 5789 5790 out_drop: 5791 dev_kfree_skb_any(first->skb); 5792 first->skb = NULL; 5793 cleanup_tx_tstamp: 5794 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 5795 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5796 5797 dev_kfree_skb_any(adapter->ptp_tx_skb); 5798 adapter->ptp_tx_skb = NULL; 5799 if (adapter->hw.mac.type == e1000_82576) 5800 cancel_work_sync(&adapter->ptp_tx_work); 5801 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 5802 } 5803 5804 return NETDEV_TX_OK; 5805 } 5806 5807 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5808 struct sk_buff *skb) 5809 { 5810 unsigned int r_idx = skb->queue_mapping; 5811 5812 if (r_idx >= adapter->num_tx_queues) 5813 r_idx = r_idx % adapter->num_tx_queues; 5814 5815 return adapter->tx_ring[r_idx]; 5816 } 5817 5818 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5819 struct net_device *netdev) 5820 { 5821 struct igb_adapter *adapter = netdev_priv(netdev); 5822 5823 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5824 * in order to meet this minimum size requirement. 5825 */ 5826 if (skb_put_padto(skb, 17)) 5827 return NETDEV_TX_OK; 5828 5829 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5830 } 5831 5832 /** 5833 * igb_tx_timeout - Respond to a Tx Hang 5834 * @netdev: network interface device structure 5835 **/ 5836 static void igb_tx_timeout(struct net_device *netdev) 5837 { 5838 struct igb_adapter *adapter = netdev_priv(netdev); 5839 struct e1000_hw *hw = &adapter->hw; 5840 5841 /* Do the reset outside of interrupt context */ 5842 adapter->tx_timeout_count++; 5843 5844 if (hw->mac.type >= e1000_82580) 5845 hw->dev_spec._82575.global_device_reset = true; 5846 5847 schedule_work(&adapter->reset_task); 5848 wr32(E1000_EICS, 5849 (adapter->eims_enable_mask & ~adapter->eims_other)); 5850 } 5851 5852 static void igb_reset_task(struct work_struct *work) 5853 { 5854 struct igb_adapter *adapter; 5855 adapter = container_of(work, struct igb_adapter, reset_task); 5856 5857 igb_dump(adapter); 5858 netdev_err(adapter->netdev, "Reset adapter\n"); 5859 igb_reinit_locked(adapter); 5860 } 5861 5862 /** 5863 * igb_get_stats64 - Get System Network Statistics 5864 * @netdev: network interface device structure 5865 * @stats: rtnl_link_stats64 pointer 5866 **/ 5867 static void igb_get_stats64(struct net_device *netdev, 5868 struct rtnl_link_stats64 *stats) 5869 { 5870 struct igb_adapter *adapter = netdev_priv(netdev); 5871 5872 spin_lock(&adapter->stats64_lock); 5873 igb_update_stats(adapter); 5874 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5875 spin_unlock(&adapter->stats64_lock); 5876 } 5877 5878 /** 5879 * igb_change_mtu - Change the Maximum Transfer Unit 5880 * @netdev: network interface device structure 5881 * @new_mtu: new value for maximum frame size 5882 * 5883 * Returns 0 on success, negative on failure 5884 **/ 5885 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5886 { 5887 struct igb_adapter *adapter = netdev_priv(netdev); 5888 struct pci_dev *pdev = adapter->pdev; 5889 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5890 5891 /* adjust max frame to be at least the size of a standard frame */ 5892 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5893 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5894 5895 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5896 usleep_range(1000, 2000); 5897 5898 /* igb_down has a dependency on max_frame_size */ 5899 adapter->max_frame_size = max_frame; 5900 5901 if (netif_running(netdev)) 5902 igb_down(adapter); 5903 5904 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5905 netdev->mtu, new_mtu); 5906 netdev->mtu = new_mtu; 5907 5908 if (netif_running(netdev)) 5909 igb_up(adapter); 5910 else 5911 igb_reset(adapter); 5912 5913 clear_bit(__IGB_RESETTING, &adapter->state); 5914 5915 return 0; 5916 } 5917 5918 /** 5919 * igb_update_stats - Update the board statistics counters 5920 * @adapter: board private structure 5921 **/ 5922 void igb_update_stats(struct igb_adapter *adapter) 5923 { 5924 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 5925 struct e1000_hw *hw = &adapter->hw; 5926 struct pci_dev *pdev = adapter->pdev; 5927 u32 reg, mpc; 5928 int i; 5929 u64 bytes, packets; 5930 unsigned int start; 5931 u64 _bytes, _packets; 5932 5933 /* Prevent stats update while adapter is being reset, or if the pci 5934 * connection is down. 5935 */ 5936 if (adapter->link_speed == 0) 5937 return; 5938 if (pci_channel_offline(pdev)) 5939 return; 5940 5941 bytes = 0; 5942 packets = 0; 5943 5944 rcu_read_lock(); 5945 for (i = 0; i < adapter->num_rx_queues; i++) { 5946 struct igb_ring *ring = adapter->rx_ring[i]; 5947 u32 rqdpc = rd32(E1000_RQDPC(i)); 5948 if (hw->mac.type >= e1000_i210) 5949 wr32(E1000_RQDPC(i), 0); 5950 5951 if (rqdpc) { 5952 ring->rx_stats.drops += rqdpc; 5953 net_stats->rx_fifo_errors += rqdpc; 5954 } 5955 5956 do { 5957 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5958 _bytes = ring->rx_stats.bytes; 5959 _packets = ring->rx_stats.packets; 5960 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5961 bytes += _bytes; 5962 packets += _packets; 5963 } 5964 5965 net_stats->rx_bytes = bytes; 5966 net_stats->rx_packets = packets; 5967 5968 bytes = 0; 5969 packets = 0; 5970 for (i = 0; i < adapter->num_tx_queues; i++) { 5971 struct igb_ring *ring = adapter->tx_ring[i]; 5972 do { 5973 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5974 _bytes = ring->tx_stats.bytes; 5975 _packets = ring->tx_stats.packets; 5976 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5977 bytes += _bytes; 5978 packets += _packets; 5979 } 5980 net_stats->tx_bytes = bytes; 5981 net_stats->tx_packets = packets; 5982 rcu_read_unlock(); 5983 5984 /* read stats registers */ 5985 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5986 adapter->stats.gprc += rd32(E1000_GPRC); 5987 adapter->stats.gorc += rd32(E1000_GORCL); 5988 rd32(E1000_GORCH); /* clear GORCL */ 5989 adapter->stats.bprc += rd32(E1000_BPRC); 5990 adapter->stats.mprc += rd32(E1000_MPRC); 5991 adapter->stats.roc += rd32(E1000_ROC); 5992 5993 adapter->stats.prc64 += rd32(E1000_PRC64); 5994 adapter->stats.prc127 += rd32(E1000_PRC127); 5995 adapter->stats.prc255 += rd32(E1000_PRC255); 5996 adapter->stats.prc511 += rd32(E1000_PRC511); 5997 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5998 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5999 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6000 adapter->stats.sec += rd32(E1000_SEC); 6001 6002 mpc = rd32(E1000_MPC); 6003 adapter->stats.mpc += mpc; 6004 net_stats->rx_fifo_errors += mpc; 6005 adapter->stats.scc += rd32(E1000_SCC); 6006 adapter->stats.ecol += rd32(E1000_ECOL); 6007 adapter->stats.mcc += rd32(E1000_MCC); 6008 adapter->stats.latecol += rd32(E1000_LATECOL); 6009 adapter->stats.dc += rd32(E1000_DC); 6010 adapter->stats.rlec += rd32(E1000_RLEC); 6011 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6012 adapter->stats.xontxc += rd32(E1000_XONTXC); 6013 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6014 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6015 adapter->stats.fcruc += rd32(E1000_FCRUC); 6016 adapter->stats.gptc += rd32(E1000_GPTC); 6017 adapter->stats.gotc += rd32(E1000_GOTCL); 6018 rd32(E1000_GOTCH); /* clear GOTCL */ 6019 adapter->stats.rnbc += rd32(E1000_RNBC); 6020 adapter->stats.ruc += rd32(E1000_RUC); 6021 adapter->stats.rfc += rd32(E1000_RFC); 6022 adapter->stats.rjc += rd32(E1000_RJC); 6023 adapter->stats.tor += rd32(E1000_TORH); 6024 adapter->stats.tot += rd32(E1000_TOTH); 6025 adapter->stats.tpr += rd32(E1000_TPR); 6026 6027 adapter->stats.ptc64 += rd32(E1000_PTC64); 6028 adapter->stats.ptc127 += rd32(E1000_PTC127); 6029 adapter->stats.ptc255 += rd32(E1000_PTC255); 6030 adapter->stats.ptc511 += rd32(E1000_PTC511); 6031 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6032 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6033 6034 adapter->stats.mptc += rd32(E1000_MPTC); 6035 adapter->stats.bptc += rd32(E1000_BPTC); 6036 6037 adapter->stats.tpt += rd32(E1000_TPT); 6038 adapter->stats.colc += rd32(E1000_COLC); 6039 6040 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6041 /* read internal phy specific stats */ 6042 reg = rd32(E1000_CTRL_EXT); 6043 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6044 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6045 6046 /* this stat has invalid values on i210/i211 */ 6047 if ((hw->mac.type != e1000_i210) && 6048 (hw->mac.type != e1000_i211)) 6049 adapter->stats.tncrs += rd32(E1000_TNCRS); 6050 } 6051 6052 adapter->stats.tsctc += rd32(E1000_TSCTC); 6053 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6054 6055 adapter->stats.iac += rd32(E1000_IAC); 6056 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6057 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6058 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6059 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6060 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6061 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6062 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6063 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6064 6065 /* Fill out the OS statistics structure */ 6066 net_stats->multicast = adapter->stats.mprc; 6067 net_stats->collisions = adapter->stats.colc; 6068 6069 /* Rx Errors */ 6070 6071 /* RLEC on some newer hardware can be incorrect so build 6072 * our own version based on RUC and ROC 6073 */ 6074 net_stats->rx_errors = adapter->stats.rxerrc + 6075 adapter->stats.crcerrs + adapter->stats.algnerrc + 6076 adapter->stats.ruc + adapter->stats.roc + 6077 adapter->stats.cexterr; 6078 net_stats->rx_length_errors = adapter->stats.ruc + 6079 adapter->stats.roc; 6080 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6081 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6082 net_stats->rx_missed_errors = adapter->stats.mpc; 6083 6084 /* Tx Errors */ 6085 net_stats->tx_errors = adapter->stats.ecol + 6086 adapter->stats.latecol; 6087 net_stats->tx_aborted_errors = adapter->stats.ecol; 6088 net_stats->tx_window_errors = adapter->stats.latecol; 6089 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6090 6091 /* Tx Dropped needs to be maintained elsewhere */ 6092 6093 /* Management Stats */ 6094 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6095 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6096 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6097 6098 /* OS2BMC Stats */ 6099 reg = rd32(E1000_MANC); 6100 if (reg & E1000_MANC_EN_BMC2OS) { 6101 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6102 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6103 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6104 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6105 } 6106 } 6107 6108 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6109 { 6110 struct e1000_hw *hw = &adapter->hw; 6111 struct ptp_clock_event event; 6112 struct timespec64 ts; 6113 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6114 6115 if (tsicr & TSINTR_SYS_WRAP) { 6116 event.type = PTP_CLOCK_PPS; 6117 if (adapter->ptp_caps.pps) 6118 ptp_clock_event(adapter->ptp_clock, &event); 6119 ack |= TSINTR_SYS_WRAP; 6120 } 6121 6122 if (tsicr & E1000_TSICR_TXTS) { 6123 /* retrieve hardware timestamp */ 6124 schedule_work(&adapter->ptp_tx_work); 6125 ack |= E1000_TSICR_TXTS; 6126 } 6127 6128 if (tsicr & TSINTR_TT0) { 6129 spin_lock(&adapter->tmreg_lock); 6130 ts = timespec64_add(adapter->perout[0].start, 6131 adapter->perout[0].period); 6132 /* u32 conversion of tv_sec is safe until y2106 */ 6133 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6134 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6135 tsauxc = rd32(E1000_TSAUXC); 6136 tsauxc |= TSAUXC_EN_TT0; 6137 wr32(E1000_TSAUXC, tsauxc); 6138 adapter->perout[0].start = ts; 6139 spin_unlock(&adapter->tmreg_lock); 6140 ack |= TSINTR_TT0; 6141 } 6142 6143 if (tsicr & TSINTR_TT1) { 6144 spin_lock(&adapter->tmreg_lock); 6145 ts = timespec64_add(adapter->perout[1].start, 6146 adapter->perout[1].period); 6147 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6148 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6149 tsauxc = rd32(E1000_TSAUXC); 6150 tsauxc |= TSAUXC_EN_TT1; 6151 wr32(E1000_TSAUXC, tsauxc); 6152 adapter->perout[1].start = ts; 6153 spin_unlock(&adapter->tmreg_lock); 6154 ack |= TSINTR_TT1; 6155 } 6156 6157 if (tsicr & TSINTR_AUTT0) { 6158 nsec = rd32(E1000_AUXSTMPL0); 6159 sec = rd32(E1000_AUXSTMPH0); 6160 event.type = PTP_CLOCK_EXTTS; 6161 event.index = 0; 6162 event.timestamp = sec * 1000000000ULL + nsec; 6163 ptp_clock_event(adapter->ptp_clock, &event); 6164 ack |= TSINTR_AUTT0; 6165 } 6166 6167 if (tsicr & TSINTR_AUTT1) { 6168 nsec = rd32(E1000_AUXSTMPL1); 6169 sec = rd32(E1000_AUXSTMPH1); 6170 event.type = PTP_CLOCK_EXTTS; 6171 event.index = 1; 6172 event.timestamp = sec * 1000000000ULL + nsec; 6173 ptp_clock_event(adapter->ptp_clock, &event); 6174 ack |= TSINTR_AUTT1; 6175 } 6176 6177 /* acknowledge the interrupts */ 6178 wr32(E1000_TSICR, ack); 6179 } 6180 6181 static irqreturn_t igb_msix_other(int irq, void *data) 6182 { 6183 struct igb_adapter *adapter = data; 6184 struct e1000_hw *hw = &adapter->hw; 6185 u32 icr = rd32(E1000_ICR); 6186 /* reading ICR causes bit 31 of EICR to be cleared */ 6187 6188 if (icr & E1000_ICR_DRSTA) 6189 schedule_work(&adapter->reset_task); 6190 6191 if (icr & E1000_ICR_DOUTSYNC) { 6192 /* HW is reporting DMA is out of sync */ 6193 adapter->stats.doosync++; 6194 /* The DMA Out of Sync is also indication of a spoof event 6195 * in IOV mode. Check the Wrong VM Behavior register to 6196 * see if it is really a spoof event. 6197 */ 6198 igb_check_wvbr(adapter); 6199 } 6200 6201 /* Check for a mailbox event */ 6202 if (icr & E1000_ICR_VMMB) 6203 igb_msg_task(adapter); 6204 6205 if (icr & E1000_ICR_LSC) { 6206 hw->mac.get_link_status = 1; 6207 /* guard against interrupt when we're going down */ 6208 if (!test_bit(__IGB_DOWN, &adapter->state)) 6209 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6210 } 6211 6212 if (icr & E1000_ICR_TS) 6213 igb_tsync_interrupt(adapter); 6214 6215 wr32(E1000_EIMS, adapter->eims_other); 6216 6217 return IRQ_HANDLED; 6218 } 6219 6220 static void igb_write_itr(struct igb_q_vector *q_vector) 6221 { 6222 struct igb_adapter *adapter = q_vector->adapter; 6223 u32 itr_val = q_vector->itr_val & 0x7FFC; 6224 6225 if (!q_vector->set_itr) 6226 return; 6227 6228 if (!itr_val) 6229 itr_val = 0x4; 6230 6231 if (adapter->hw.mac.type == e1000_82575) 6232 itr_val |= itr_val << 16; 6233 else 6234 itr_val |= E1000_EITR_CNT_IGNR; 6235 6236 writel(itr_val, q_vector->itr_register); 6237 q_vector->set_itr = 0; 6238 } 6239 6240 static irqreturn_t igb_msix_ring(int irq, void *data) 6241 { 6242 struct igb_q_vector *q_vector = data; 6243 6244 /* Write the ITR value calculated from the previous interrupt. */ 6245 igb_write_itr(q_vector); 6246 6247 napi_schedule(&q_vector->napi); 6248 6249 return IRQ_HANDLED; 6250 } 6251 6252 #ifdef CONFIG_IGB_DCA 6253 static void igb_update_tx_dca(struct igb_adapter *adapter, 6254 struct igb_ring *tx_ring, 6255 int cpu) 6256 { 6257 struct e1000_hw *hw = &adapter->hw; 6258 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6259 6260 if (hw->mac.type != e1000_82575) 6261 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6262 6263 /* We can enable relaxed ordering for reads, but not writes when 6264 * DCA is enabled. This is due to a known issue in some chipsets 6265 * which will cause the DCA tag to be cleared. 6266 */ 6267 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6268 E1000_DCA_TXCTRL_DATA_RRO_EN | 6269 E1000_DCA_TXCTRL_DESC_DCA_EN; 6270 6271 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6272 } 6273 6274 static void igb_update_rx_dca(struct igb_adapter *adapter, 6275 struct igb_ring *rx_ring, 6276 int cpu) 6277 { 6278 struct e1000_hw *hw = &adapter->hw; 6279 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6280 6281 if (hw->mac.type != e1000_82575) 6282 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6283 6284 /* We can enable relaxed ordering for reads, but not writes when 6285 * DCA is enabled. This is due to a known issue in some chipsets 6286 * which will cause the DCA tag to be cleared. 6287 */ 6288 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6289 E1000_DCA_RXCTRL_DESC_DCA_EN; 6290 6291 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6292 } 6293 6294 static void igb_update_dca(struct igb_q_vector *q_vector) 6295 { 6296 struct igb_adapter *adapter = q_vector->adapter; 6297 int cpu = get_cpu(); 6298 6299 if (q_vector->cpu == cpu) 6300 goto out_no_update; 6301 6302 if (q_vector->tx.ring) 6303 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6304 6305 if (q_vector->rx.ring) 6306 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6307 6308 q_vector->cpu = cpu; 6309 out_no_update: 6310 put_cpu(); 6311 } 6312 6313 static void igb_setup_dca(struct igb_adapter *adapter) 6314 { 6315 struct e1000_hw *hw = &adapter->hw; 6316 int i; 6317 6318 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6319 return; 6320 6321 /* Always use CB2 mode, difference is masked in the CB driver. */ 6322 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6323 6324 for (i = 0; i < adapter->num_q_vectors; i++) { 6325 adapter->q_vector[i]->cpu = -1; 6326 igb_update_dca(adapter->q_vector[i]); 6327 } 6328 } 6329 6330 static int __igb_notify_dca(struct device *dev, void *data) 6331 { 6332 struct net_device *netdev = dev_get_drvdata(dev); 6333 struct igb_adapter *adapter = netdev_priv(netdev); 6334 struct pci_dev *pdev = adapter->pdev; 6335 struct e1000_hw *hw = &adapter->hw; 6336 unsigned long event = *(unsigned long *)data; 6337 6338 switch (event) { 6339 case DCA_PROVIDER_ADD: 6340 /* if already enabled, don't do it again */ 6341 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6342 break; 6343 if (dca_add_requester(dev) == 0) { 6344 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6345 dev_info(&pdev->dev, "DCA enabled\n"); 6346 igb_setup_dca(adapter); 6347 break; 6348 } 6349 /* Fall Through since DCA is disabled. */ 6350 case DCA_PROVIDER_REMOVE: 6351 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6352 /* without this a class_device is left 6353 * hanging around in the sysfs model 6354 */ 6355 dca_remove_requester(dev); 6356 dev_info(&pdev->dev, "DCA disabled\n"); 6357 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6358 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6359 } 6360 break; 6361 } 6362 6363 return 0; 6364 } 6365 6366 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6367 void *p) 6368 { 6369 int ret_val; 6370 6371 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6372 __igb_notify_dca); 6373 6374 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6375 } 6376 #endif /* CONFIG_IGB_DCA */ 6377 6378 #ifdef CONFIG_PCI_IOV 6379 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6380 { 6381 unsigned char mac_addr[ETH_ALEN]; 6382 6383 eth_zero_addr(mac_addr); 6384 igb_set_vf_mac(adapter, vf, mac_addr); 6385 6386 /* By default spoof check is enabled for all VFs */ 6387 adapter->vf_data[vf].spoofchk_enabled = true; 6388 6389 /* By default VFs are not trusted */ 6390 adapter->vf_data[vf].trusted = false; 6391 6392 return 0; 6393 } 6394 6395 #endif 6396 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6397 { 6398 struct e1000_hw *hw = &adapter->hw; 6399 u32 ping; 6400 int i; 6401 6402 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6403 ping = E1000_PF_CONTROL_MSG; 6404 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6405 ping |= E1000_VT_MSGTYPE_CTS; 6406 igb_write_mbx(hw, &ping, 1, i); 6407 } 6408 } 6409 6410 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6411 { 6412 struct e1000_hw *hw = &adapter->hw; 6413 u32 vmolr = rd32(E1000_VMOLR(vf)); 6414 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6415 6416 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6417 IGB_VF_FLAG_MULTI_PROMISC); 6418 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6419 6420 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6421 vmolr |= E1000_VMOLR_MPME; 6422 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6423 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6424 } else { 6425 /* if we have hashes and we are clearing a multicast promisc 6426 * flag we need to write the hashes to the MTA as this step 6427 * was previously skipped 6428 */ 6429 if (vf_data->num_vf_mc_hashes > 30) { 6430 vmolr |= E1000_VMOLR_MPME; 6431 } else if (vf_data->num_vf_mc_hashes) { 6432 int j; 6433 6434 vmolr |= E1000_VMOLR_ROMPE; 6435 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6436 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6437 } 6438 } 6439 6440 wr32(E1000_VMOLR(vf), vmolr); 6441 6442 /* there are flags left unprocessed, likely not supported */ 6443 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6444 return -EINVAL; 6445 6446 return 0; 6447 } 6448 6449 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6450 u32 *msgbuf, u32 vf) 6451 { 6452 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6453 u16 *hash_list = (u16 *)&msgbuf[1]; 6454 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6455 int i; 6456 6457 /* salt away the number of multicast addresses assigned 6458 * to this VF for later use to restore when the PF multi cast 6459 * list changes 6460 */ 6461 vf_data->num_vf_mc_hashes = n; 6462 6463 /* only up to 30 hash values supported */ 6464 if (n > 30) 6465 n = 30; 6466 6467 /* store the hashes for later use */ 6468 for (i = 0; i < n; i++) 6469 vf_data->vf_mc_hashes[i] = hash_list[i]; 6470 6471 /* Flush and reset the mta with the new values */ 6472 igb_set_rx_mode(adapter->netdev); 6473 6474 return 0; 6475 } 6476 6477 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6478 { 6479 struct e1000_hw *hw = &adapter->hw; 6480 struct vf_data_storage *vf_data; 6481 int i, j; 6482 6483 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6484 u32 vmolr = rd32(E1000_VMOLR(i)); 6485 6486 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6487 6488 vf_data = &adapter->vf_data[i]; 6489 6490 if ((vf_data->num_vf_mc_hashes > 30) || 6491 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6492 vmolr |= E1000_VMOLR_MPME; 6493 } else if (vf_data->num_vf_mc_hashes) { 6494 vmolr |= E1000_VMOLR_ROMPE; 6495 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6496 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6497 } 6498 wr32(E1000_VMOLR(i), vmolr); 6499 } 6500 } 6501 6502 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6503 { 6504 struct e1000_hw *hw = &adapter->hw; 6505 u32 pool_mask, vlvf_mask, i; 6506 6507 /* create mask for VF and other pools */ 6508 pool_mask = E1000_VLVF_POOLSEL_MASK; 6509 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6510 6511 /* drop PF from pool bits */ 6512 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6513 adapter->vfs_allocated_count); 6514 6515 /* Find the vlan filter for this id */ 6516 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6517 u32 vlvf = rd32(E1000_VLVF(i)); 6518 u32 vfta_mask, vid, vfta; 6519 6520 /* remove the vf from the pool */ 6521 if (!(vlvf & vlvf_mask)) 6522 continue; 6523 6524 /* clear out bit from VLVF */ 6525 vlvf ^= vlvf_mask; 6526 6527 /* if other pools are present, just remove ourselves */ 6528 if (vlvf & pool_mask) 6529 goto update_vlvfb; 6530 6531 /* if PF is present, leave VFTA */ 6532 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6533 goto update_vlvf; 6534 6535 vid = vlvf & E1000_VLVF_VLANID_MASK; 6536 vfta_mask = BIT(vid % 32); 6537 6538 /* clear bit from VFTA */ 6539 vfta = adapter->shadow_vfta[vid / 32]; 6540 if (vfta & vfta_mask) 6541 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6542 update_vlvf: 6543 /* clear pool selection enable */ 6544 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6545 vlvf &= E1000_VLVF_POOLSEL_MASK; 6546 else 6547 vlvf = 0; 6548 update_vlvfb: 6549 /* clear pool bits */ 6550 wr32(E1000_VLVF(i), vlvf); 6551 } 6552 } 6553 6554 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6555 { 6556 u32 vlvf; 6557 int idx; 6558 6559 /* short cut the special case */ 6560 if (vlan == 0) 6561 return 0; 6562 6563 /* Search for the VLAN id in the VLVF entries */ 6564 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6565 vlvf = rd32(E1000_VLVF(idx)); 6566 if ((vlvf & VLAN_VID_MASK) == vlan) 6567 break; 6568 } 6569 6570 return idx; 6571 } 6572 6573 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6574 { 6575 struct e1000_hw *hw = &adapter->hw; 6576 u32 bits, pf_id; 6577 int idx; 6578 6579 idx = igb_find_vlvf_entry(hw, vid); 6580 if (!idx) 6581 return; 6582 6583 /* See if any other pools are set for this VLAN filter 6584 * entry other than the PF. 6585 */ 6586 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6587 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6588 bits &= rd32(E1000_VLVF(idx)); 6589 6590 /* Disable the filter so this falls into the default pool. */ 6591 if (!bits) { 6592 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6593 wr32(E1000_VLVF(idx), BIT(pf_id)); 6594 else 6595 wr32(E1000_VLVF(idx), 0); 6596 } 6597 } 6598 6599 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6600 bool add, u32 vf) 6601 { 6602 int pf_id = adapter->vfs_allocated_count; 6603 struct e1000_hw *hw = &adapter->hw; 6604 int err; 6605 6606 /* If VLAN overlaps with one the PF is currently monitoring make 6607 * sure that we are able to allocate a VLVF entry. This may be 6608 * redundant but it guarantees PF will maintain visibility to 6609 * the VLAN. 6610 */ 6611 if (add && test_bit(vid, adapter->active_vlans)) { 6612 err = igb_vfta_set(hw, vid, pf_id, true, false); 6613 if (err) 6614 return err; 6615 } 6616 6617 err = igb_vfta_set(hw, vid, vf, add, false); 6618 6619 if (add && !err) 6620 return err; 6621 6622 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6623 * we may need to drop the PF pool bit in order to allow us to free 6624 * up the VLVF resources. 6625 */ 6626 if (test_bit(vid, adapter->active_vlans) || 6627 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6628 igb_update_pf_vlvf(adapter, vid); 6629 6630 return err; 6631 } 6632 6633 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6634 { 6635 struct e1000_hw *hw = &adapter->hw; 6636 6637 if (vid) 6638 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6639 else 6640 wr32(E1000_VMVIR(vf), 0); 6641 } 6642 6643 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6644 u16 vlan, u8 qos) 6645 { 6646 int err; 6647 6648 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6649 if (err) 6650 return err; 6651 6652 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6653 igb_set_vmolr(adapter, vf, !vlan); 6654 6655 /* revoke access to previous VLAN */ 6656 if (vlan != adapter->vf_data[vf].pf_vlan) 6657 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6658 false, vf); 6659 6660 adapter->vf_data[vf].pf_vlan = vlan; 6661 adapter->vf_data[vf].pf_qos = qos; 6662 igb_set_vf_vlan_strip(adapter, vf, true); 6663 dev_info(&adapter->pdev->dev, 6664 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6665 if (test_bit(__IGB_DOWN, &adapter->state)) { 6666 dev_warn(&adapter->pdev->dev, 6667 "The VF VLAN has been set, but the PF device is not up.\n"); 6668 dev_warn(&adapter->pdev->dev, 6669 "Bring the PF device up before attempting to use the VF device.\n"); 6670 } 6671 6672 return err; 6673 } 6674 6675 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6676 { 6677 /* Restore tagless access via VLAN 0 */ 6678 igb_set_vf_vlan(adapter, 0, true, vf); 6679 6680 igb_set_vmvir(adapter, 0, vf); 6681 igb_set_vmolr(adapter, vf, true); 6682 6683 /* Remove any PF assigned VLAN */ 6684 if (adapter->vf_data[vf].pf_vlan) 6685 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6686 false, vf); 6687 6688 adapter->vf_data[vf].pf_vlan = 0; 6689 adapter->vf_data[vf].pf_qos = 0; 6690 igb_set_vf_vlan_strip(adapter, vf, false); 6691 6692 return 0; 6693 } 6694 6695 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6696 u16 vlan, u8 qos, __be16 vlan_proto) 6697 { 6698 struct igb_adapter *adapter = netdev_priv(netdev); 6699 6700 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6701 return -EINVAL; 6702 6703 if (vlan_proto != htons(ETH_P_8021Q)) 6704 return -EPROTONOSUPPORT; 6705 6706 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6707 igb_disable_port_vlan(adapter, vf); 6708 } 6709 6710 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6711 { 6712 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6713 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6714 int ret; 6715 6716 if (adapter->vf_data[vf].pf_vlan) 6717 return -1; 6718 6719 /* VLAN 0 is a special case, don't allow it to be removed */ 6720 if (!vid && !add) 6721 return 0; 6722 6723 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6724 if (!ret) 6725 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6726 return ret; 6727 } 6728 6729 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6730 { 6731 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6732 6733 /* clear flags - except flag that indicates PF has set the MAC */ 6734 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6735 vf_data->last_nack = jiffies; 6736 6737 /* reset vlans for device */ 6738 igb_clear_vf_vfta(adapter, vf); 6739 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6740 igb_set_vmvir(adapter, vf_data->pf_vlan | 6741 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6742 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6743 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6744 6745 /* reset multicast table array for vf */ 6746 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6747 6748 /* Flush and reset the mta with the new values */ 6749 igb_set_rx_mode(adapter->netdev); 6750 } 6751 6752 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6753 { 6754 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6755 6756 /* clear mac address as we were hotplug removed/added */ 6757 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6758 eth_zero_addr(vf_mac); 6759 6760 /* process remaining reset events */ 6761 igb_vf_reset(adapter, vf); 6762 } 6763 6764 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6765 { 6766 struct e1000_hw *hw = &adapter->hw; 6767 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6768 u32 reg, msgbuf[3]; 6769 u8 *addr = (u8 *)(&msgbuf[1]); 6770 6771 /* process all the same items cleared in a function level reset */ 6772 igb_vf_reset(adapter, vf); 6773 6774 /* set vf mac address */ 6775 igb_set_vf_mac(adapter, vf, vf_mac); 6776 6777 /* enable transmit and receive for vf */ 6778 reg = rd32(E1000_VFTE); 6779 wr32(E1000_VFTE, reg | BIT(vf)); 6780 reg = rd32(E1000_VFRE); 6781 wr32(E1000_VFRE, reg | BIT(vf)); 6782 6783 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6784 6785 /* reply to reset with ack and vf mac address */ 6786 if (!is_zero_ether_addr(vf_mac)) { 6787 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6788 memcpy(addr, vf_mac, ETH_ALEN); 6789 } else { 6790 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6791 } 6792 igb_write_mbx(hw, msgbuf, 3, vf); 6793 } 6794 6795 static void igb_flush_mac_table(struct igb_adapter *adapter) 6796 { 6797 struct e1000_hw *hw = &adapter->hw; 6798 int i; 6799 6800 for (i = 0; i < hw->mac.rar_entry_count; i++) { 6801 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6802 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6803 adapter->mac_table[i].queue = 0; 6804 igb_rar_set_index(adapter, i); 6805 } 6806 } 6807 6808 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 6809 { 6810 struct e1000_hw *hw = &adapter->hw; 6811 /* do not count rar entries reserved for VFs MAC addresses */ 6812 int rar_entries = hw->mac.rar_entry_count - 6813 adapter->vfs_allocated_count; 6814 int i, count = 0; 6815 6816 for (i = 0; i < rar_entries; i++) { 6817 /* do not count default entries */ 6818 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 6819 continue; 6820 6821 /* do not count "in use" entries for different queues */ 6822 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 6823 (adapter->mac_table[i].queue != queue)) 6824 continue; 6825 6826 count++; 6827 } 6828 6829 return count; 6830 } 6831 6832 /* Set default MAC address for the PF in the first RAR entry */ 6833 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 6834 { 6835 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 6836 6837 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 6838 mac_table->queue = adapter->vfs_allocated_count; 6839 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 6840 6841 igb_rar_set_index(adapter, 0); 6842 } 6843 6844 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6845 const u8 queue) 6846 { 6847 struct e1000_hw *hw = &adapter->hw; 6848 int rar_entries = hw->mac.rar_entry_count - 6849 adapter->vfs_allocated_count; 6850 int i; 6851 6852 if (is_zero_ether_addr(addr)) 6853 return -EINVAL; 6854 6855 /* Search for the first empty entry in the MAC table. 6856 * Do not touch entries at the end of the table reserved for the VF MAC 6857 * addresses. 6858 */ 6859 for (i = 0; i < rar_entries; i++) { 6860 if (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) 6861 continue; 6862 6863 ether_addr_copy(adapter->mac_table[i].addr, addr); 6864 adapter->mac_table[i].queue = queue; 6865 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE; 6866 6867 igb_rar_set_index(adapter, i); 6868 return i; 6869 } 6870 6871 return -ENOSPC; 6872 } 6873 6874 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6875 const u8 queue) 6876 { 6877 struct e1000_hw *hw = &adapter->hw; 6878 int rar_entries = hw->mac.rar_entry_count - 6879 adapter->vfs_allocated_count; 6880 int i; 6881 6882 if (is_zero_ether_addr(addr)) 6883 return -EINVAL; 6884 6885 /* Search for matching entry in the MAC table based on given address 6886 * and queue. Do not touch entries at the end of the table reserved 6887 * for the VF MAC addresses. 6888 */ 6889 for (i = 0; i < rar_entries; i++) { 6890 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 6891 continue; 6892 if (adapter->mac_table[i].queue != queue) 6893 continue; 6894 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 6895 continue; 6896 6897 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6898 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6899 adapter->mac_table[i].queue = 0; 6900 6901 igb_rar_set_index(adapter, i); 6902 return 0; 6903 } 6904 6905 return -ENOENT; 6906 } 6907 6908 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 6909 { 6910 struct igb_adapter *adapter = netdev_priv(netdev); 6911 int ret; 6912 6913 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6914 6915 return min_t(int, ret, 0); 6916 } 6917 6918 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 6919 { 6920 struct igb_adapter *adapter = netdev_priv(netdev); 6921 6922 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6923 6924 return 0; 6925 } 6926 6927 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 6928 const u32 info, const u8 *addr) 6929 { 6930 struct pci_dev *pdev = adapter->pdev; 6931 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6932 struct list_head *pos; 6933 struct vf_mac_filter *entry = NULL; 6934 int ret = 0; 6935 6936 switch (info) { 6937 case E1000_VF_MAC_FILTER_CLR: 6938 /* remove all unicast MAC filters related to the current VF */ 6939 list_for_each(pos, &adapter->vf_macs.l) { 6940 entry = list_entry(pos, struct vf_mac_filter, l); 6941 if (entry->vf == vf) { 6942 entry->vf = -1; 6943 entry->free = true; 6944 igb_del_mac_filter(adapter, entry->vf_mac, vf); 6945 } 6946 } 6947 break; 6948 case E1000_VF_MAC_FILTER_ADD: 6949 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 6950 !vf_data->trusted) { 6951 dev_warn(&pdev->dev, 6952 "VF %d requested MAC filter but is administratively denied\n", 6953 vf); 6954 return -EINVAL; 6955 } 6956 if (!is_valid_ether_addr(addr)) { 6957 dev_warn(&pdev->dev, 6958 "VF %d attempted to set invalid MAC filter\n", 6959 vf); 6960 return -EINVAL; 6961 } 6962 6963 /* try to find empty slot in the list */ 6964 list_for_each(pos, &adapter->vf_macs.l) { 6965 entry = list_entry(pos, struct vf_mac_filter, l); 6966 if (entry->free) 6967 break; 6968 } 6969 6970 if (entry && entry->free) { 6971 entry->free = false; 6972 entry->vf = vf; 6973 ether_addr_copy(entry->vf_mac, addr); 6974 6975 ret = igb_add_mac_filter(adapter, addr, vf); 6976 ret = min_t(int, ret, 0); 6977 } else { 6978 ret = -ENOSPC; 6979 } 6980 6981 if (ret == -ENOSPC) 6982 dev_warn(&pdev->dev, 6983 "VF %d has requested MAC filter but there is no space for it\n", 6984 vf); 6985 break; 6986 default: 6987 ret = -EINVAL; 6988 break; 6989 } 6990 6991 return ret; 6992 } 6993 6994 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6995 { 6996 struct pci_dev *pdev = adapter->pdev; 6997 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6998 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 6999 7000 /* The VF MAC Address is stored in a packed array of bytes 7001 * starting at the second 32 bit word of the msg array 7002 */ 7003 unsigned char *addr = (unsigned char *)&msg[1]; 7004 int ret = 0; 7005 7006 if (!info) { 7007 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7008 !vf_data->trusted) { 7009 dev_warn(&pdev->dev, 7010 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7011 vf); 7012 return -EINVAL; 7013 } 7014 7015 if (!is_valid_ether_addr(addr)) { 7016 dev_warn(&pdev->dev, 7017 "VF %d attempted to set invalid MAC\n", 7018 vf); 7019 return -EINVAL; 7020 } 7021 7022 ret = igb_set_vf_mac(adapter, vf, addr); 7023 } else { 7024 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7025 } 7026 7027 return ret; 7028 } 7029 7030 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7031 { 7032 struct e1000_hw *hw = &adapter->hw; 7033 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7034 u32 msg = E1000_VT_MSGTYPE_NACK; 7035 7036 /* if device isn't clear to send it shouldn't be reading either */ 7037 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7038 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7039 igb_write_mbx(hw, &msg, 1, vf); 7040 vf_data->last_nack = jiffies; 7041 } 7042 } 7043 7044 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7045 { 7046 struct pci_dev *pdev = adapter->pdev; 7047 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7048 struct e1000_hw *hw = &adapter->hw; 7049 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7050 s32 retval; 7051 7052 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7053 7054 if (retval) { 7055 /* if receive failed revoke VF CTS stats and restart init */ 7056 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7057 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7058 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7059 goto unlock; 7060 goto out; 7061 } 7062 7063 /* this is a message we already processed, do nothing */ 7064 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7065 goto unlock; 7066 7067 /* until the vf completes a reset it should not be 7068 * allowed to start any configuration. 7069 */ 7070 if (msgbuf[0] == E1000_VF_RESET) { 7071 /* unlocks mailbox */ 7072 igb_vf_reset_msg(adapter, vf); 7073 return; 7074 } 7075 7076 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7077 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7078 goto unlock; 7079 retval = -1; 7080 goto out; 7081 } 7082 7083 switch ((msgbuf[0] & 0xFFFF)) { 7084 case E1000_VF_SET_MAC_ADDR: 7085 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7086 break; 7087 case E1000_VF_SET_PROMISC: 7088 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7089 break; 7090 case E1000_VF_SET_MULTICAST: 7091 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7092 break; 7093 case E1000_VF_SET_LPE: 7094 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7095 break; 7096 case E1000_VF_SET_VLAN: 7097 retval = -1; 7098 if (vf_data->pf_vlan) 7099 dev_warn(&pdev->dev, 7100 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7101 vf); 7102 else 7103 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7104 break; 7105 default: 7106 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7107 retval = -1; 7108 break; 7109 } 7110 7111 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7112 out: 7113 /* notify the VF of the results of what it sent us */ 7114 if (retval) 7115 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7116 else 7117 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7118 7119 /* unlocks mailbox */ 7120 igb_write_mbx(hw, msgbuf, 1, vf); 7121 return; 7122 7123 unlock: 7124 igb_unlock_mbx(hw, vf); 7125 } 7126 7127 static void igb_msg_task(struct igb_adapter *adapter) 7128 { 7129 struct e1000_hw *hw = &adapter->hw; 7130 u32 vf; 7131 7132 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7133 /* process any reset requests */ 7134 if (!igb_check_for_rst(hw, vf)) 7135 igb_vf_reset_event(adapter, vf); 7136 7137 /* process any messages pending */ 7138 if (!igb_check_for_msg(hw, vf)) 7139 igb_rcv_msg_from_vf(adapter, vf); 7140 7141 /* process any acks */ 7142 if (!igb_check_for_ack(hw, vf)) 7143 igb_rcv_ack_from_vf(adapter, vf); 7144 } 7145 } 7146 7147 /** 7148 * igb_set_uta - Set unicast filter table address 7149 * @adapter: board private structure 7150 * @set: boolean indicating if we are setting or clearing bits 7151 * 7152 * The unicast table address is a register array of 32-bit registers. 7153 * The table is meant to be used in a way similar to how the MTA is used 7154 * however due to certain limitations in the hardware it is necessary to 7155 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7156 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7157 **/ 7158 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7159 { 7160 struct e1000_hw *hw = &adapter->hw; 7161 u32 uta = set ? ~0 : 0; 7162 int i; 7163 7164 /* we only need to do this if VMDq is enabled */ 7165 if (!adapter->vfs_allocated_count) 7166 return; 7167 7168 for (i = hw->mac.uta_reg_count; i--;) 7169 array_wr32(E1000_UTA, i, uta); 7170 } 7171 7172 /** 7173 * igb_intr_msi - Interrupt Handler 7174 * @irq: interrupt number 7175 * @data: pointer to a network interface device structure 7176 **/ 7177 static irqreturn_t igb_intr_msi(int irq, void *data) 7178 { 7179 struct igb_adapter *adapter = data; 7180 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7181 struct e1000_hw *hw = &adapter->hw; 7182 /* read ICR disables interrupts using IAM */ 7183 u32 icr = rd32(E1000_ICR); 7184 7185 igb_write_itr(q_vector); 7186 7187 if (icr & E1000_ICR_DRSTA) 7188 schedule_work(&adapter->reset_task); 7189 7190 if (icr & E1000_ICR_DOUTSYNC) { 7191 /* HW is reporting DMA is out of sync */ 7192 adapter->stats.doosync++; 7193 } 7194 7195 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7196 hw->mac.get_link_status = 1; 7197 if (!test_bit(__IGB_DOWN, &adapter->state)) 7198 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7199 } 7200 7201 if (icr & E1000_ICR_TS) 7202 igb_tsync_interrupt(adapter); 7203 7204 napi_schedule(&q_vector->napi); 7205 7206 return IRQ_HANDLED; 7207 } 7208 7209 /** 7210 * igb_intr - Legacy Interrupt Handler 7211 * @irq: interrupt number 7212 * @data: pointer to a network interface device structure 7213 **/ 7214 static irqreturn_t igb_intr(int irq, void *data) 7215 { 7216 struct igb_adapter *adapter = data; 7217 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7218 struct e1000_hw *hw = &adapter->hw; 7219 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7220 * need for the IMC write 7221 */ 7222 u32 icr = rd32(E1000_ICR); 7223 7224 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7225 * not set, then the adapter didn't send an interrupt 7226 */ 7227 if (!(icr & E1000_ICR_INT_ASSERTED)) 7228 return IRQ_NONE; 7229 7230 igb_write_itr(q_vector); 7231 7232 if (icr & E1000_ICR_DRSTA) 7233 schedule_work(&adapter->reset_task); 7234 7235 if (icr & E1000_ICR_DOUTSYNC) { 7236 /* HW is reporting DMA is out of sync */ 7237 adapter->stats.doosync++; 7238 } 7239 7240 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7241 hw->mac.get_link_status = 1; 7242 /* guard against interrupt when we're going down */ 7243 if (!test_bit(__IGB_DOWN, &adapter->state)) 7244 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7245 } 7246 7247 if (icr & E1000_ICR_TS) 7248 igb_tsync_interrupt(adapter); 7249 7250 napi_schedule(&q_vector->napi); 7251 7252 return IRQ_HANDLED; 7253 } 7254 7255 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7256 { 7257 struct igb_adapter *adapter = q_vector->adapter; 7258 struct e1000_hw *hw = &adapter->hw; 7259 7260 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7261 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7262 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7263 igb_set_itr(q_vector); 7264 else 7265 igb_update_ring_itr(q_vector); 7266 } 7267 7268 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7269 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7270 wr32(E1000_EIMS, q_vector->eims_value); 7271 else 7272 igb_irq_enable(adapter); 7273 } 7274 } 7275 7276 /** 7277 * igb_poll - NAPI Rx polling callback 7278 * @napi: napi polling structure 7279 * @budget: count of how many packets we should handle 7280 **/ 7281 static int igb_poll(struct napi_struct *napi, int budget) 7282 { 7283 struct igb_q_vector *q_vector = container_of(napi, 7284 struct igb_q_vector, 7285 napi); 7286 bool clean_complete = true; 7287 int work_done = 0; 7288 7289 #ifdef CONFIG_IGB_DCA 7290 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 7291 igb_update_dca(q_vector); 7292 #endif 7293 if (q_vector->tx.ring) 7294 clean_complete = igb_clean_tx_irq(q_vector, budget); 7295 7296 if (q_vector->rx.ring) { 7297 int cleaned = igb_clean_rx_irq(q_vector, budget); 7298 7299 work_done += cleaned; 7300 if (cleaned >= budget) 7301 clean_complete = false; 7302 } 7303 7304 /* If all work not completed, return budget and keep polling */ 7305 if (!clean_complete) 7306 return budget; 7307 7308 /* If not enough Rx work done, exit the polling mode */ 7309 napi_complete_done(napi, work_done); 7310 igb_ring_irq_enable(q_vector); 7311 7312 return 0; 7313 } 7314 7315 /** 7316 * igb_clean_tx_irq - Reclaim resources after transmit completes 7317 * @q_vector: pointer to q_vector containing needed info 7318 * @napi_budget: Used to determine if we are in netpoll 7319 * 7320 * returns true if ring is completely cleaned 7321 **/ 7322 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 7323 { 7324 struct igb_adapter *adapter = q_vector->adapter; 7325 struct igb_ring *tx_ring = q_vector->tx.ring; 7326 struct igb_tx_buffer *tx_buffer; 7327 union e1000_adv_tx_desc *tx_desc; 7328 unsigned int total_bytes = 0, total_packets = 0; 7329 unsigned int budget = q_vector->tx.work_limit; 7330 unsigned int i = tx_ring->next_to_clean; 7331 7332 if (test_bit(__IGB_DOWN, &adapter->state)) 7333 return true; 7334 7335 tx_buffer = &tx_ring->tx_buffer_info[i]; 7336 tx_desc = IGB_TX_DESC(tx_ring, i); 7337 i -= tx_ring->count; 7338 7339 do { 7340 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 7341 7342 /* if next_to_watch is not set then there is no work pending */ 7343 if (!eop_desc) 7344 break; 7345 7346 /* prevent any other reads prior to eop_desc */ 7347 smp_rmb(); 7348 7349 /* if DD is not set pending work has not been completed */ 7350 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 7351 break; 7352 7353 /* clear next_to_watch to prevent false hangs */ 7354 tx_buffer->next_to_watch = NULL; 7355 7356 /* update the statistics for this packet */ 7357 total_bytes += tx_buffer->bytecount; 7358 total_packets += tx_buffer->gso_segs; 7359 7360 /* free the skb */ 7361 napi_consume_skb(tx_buffer->skb, napi_budget); 7362 7363 /* unmap skb header data */ 7364 dma_unmap_single(tx_ring->dev, 7365 dma_unmap_addr(tx_buffer, dma), 7366 dma_unmap_len(tx_buffer, len), 7367 DMA_TO_DEVICE); 7368 7369 /* clear tx_buffer data */ 7370 dma_unmap_len_set(tx_buffer, len, 0); 7371 7372 /* clear last DMA location and unmap remaining buffers */ 7373 while (tx_desc != eop_desc) { 7374 tx_buffer++; 7375 tx_desc++; 7376 i++; 7377 if (unlikely(!i)) { 7378 i -= tx_ring->count; 7379 tx_buffer = tx_ring->tx_buffer_info; 7380 tx_desc = IGB_TX_DESC(tx_ring, 0); 7381 } 7382 7383 /* unmap any remaining paged data */ 7384 if (dma_unmap_len(tx_buffer, len)) { 7385 dma_unmap_page(tx_ring->dev, 7386 dma_unmap_addr(tx_buffer, dma), 7387 dma_unmap_len(tx_buffer, len), 7388 DMA_TO_DEVICE); 7389 dma_unmap_len_set(tx_buffer, len, 0); 7390 } 7391 } 7392 7393 /* move us one more past the eop_desc for start of next pkt */ 7394 tx_buffer++; 7395 tx_desc++; 7396 i++; 7397 if (unlikely(!i)) { 7398 i -= tx_ring->count; 7399 tx_buffer = tx_ring->tx_buffer_info; 7400 tx_desc = IGB_TX_DESC(tx_ring, 0); 7401 } 7402 7403 /* issue prefetch for next Tx descriptor */ 7404 prefetch(tx_desc); 7405 7406 /* update budget accounting */ 7407 budget--; 7408 } while (likely(budget)); 7409 7410 netdev_tx_completed_queue(txring_txq(tx_ring), 7411 total_packets, total_bytes); 7412 i += tx_ring->count; 7413 tx_ring->next_to_clean = i; 7414 u64_stats_update_begin(&tx_ring->tx_syncp); 7415 tx_ring->tx_stats.bytes += total_bytes; 7416 tx_ring->tx_stats.packets += total_packets; 7417 u64_stats_update_end(&tx_ring->tx_syncp); 7418 q_vector->tx.total_bytes += total_bytes; 7419 q_vector->tx.total_packets += total_packets; 7420 7421 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7422 struct e1000_hw *hw = &adapter->hw; 7423 7424 /* Detect a transmit hang in hardware, this serializes the 7425 * check with the clearing of time_stamp and movement of i 7426 */ 7427 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7428 if (tx_buffer->next_to_watch && 7429 time_after(jiffies, tx_buffer->time_stamp + 7430 (adapter->tx_timeout_factor * HZ)) && 7431 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7432 7433 /* detected Tx unit hang */ 7434 dev_err(tx_ring->dev, 7435 "Detected Tx Unit Hang\n" 7436 " Tx Queue <%d>\n" 7437 " TDH <%x>\n" 7438 " TDT <%x>\n" 7439 " next_to_use <%x>\n" 7440 " next_to_clean <%x>\n" 7441 "buffer_info[next_to_clean]\n" 7442 " time_stamp <%lx>\n" 7443 " next_to_watch <%p>\n" 7444 " jiffies <%lx>\n" 7445 " desc.status <%x>\n", 7446 tx_ring->queue_index, 7447 rd32(E1000_TDH(tx_ring->reg_idx)), 7448 readl(tx_ring->tail), 7449 tx_ring->next_to_use, 7450 tx_ring->next_to_clean, 7451 tx_buffer->time_stamp, 7452 tx_buffer->next_to_watch, 7453 jiffies, 7454 tx_buffer->next_to_watch->wb.status); 7455 netif_stop_subqueue(tx_ring->netdev, 7456 tx_ring->queue_index); 7457 7458 /* we are about to reset, no point in enabling stuff */ 7459 return true; 7460 } 7461 } 7462 7463 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7464 if (unlikely(total_packets && 7465 netif_carrier_ok(tx_ring->netdev) && 7466 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7467 /* Make sure that anybody stopping the queue after this 7468 * sees the new next_to_clean. 7469 */ 7470 smp_mb(); 7471 if (__netif_subqueue_stopped(tx_ring->netdev, 7472 tx_ring->queue_index) && 7473 !(test_bit(__IGB_DOWN, &adapter->state))) { 7474 netif_wake_subqueue(tx_ring->netdev, 7475 tx_ring->queue_index); 7476 7477 u64_stats_update_begin(&tx_ring->tx_syncp); 7478 tx_ring->tx_stats.restart_queue++; 7479 u64_stats_update_end(&tx_ring->tx_syncp); 7480 } 7481 } 7482 7483 return !!budget; 7484 } 7485 7486 /** 7487 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7488 * @rx_ring: rx descriptor ring to store buffers on 7489 * @old_buff: donor buffer to have page reused 7490 * 7491 * Synchronizes page for reuse by the adapter 7492 **/ 7493 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7494 struct igb_rx_buffer *old_buff) 7495 { 7496 struct igb_rx_buffer *new_buff; 7497 u16 nta = rx_ring->next_to_alloc; 7498 7499 new_buff = &rx_ring->rx_buffer_info[nta]; 7500 7501 /* update, and store next to alloc */ 7502 nta++; 7503 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7504 7505 /* Transfer page from old buffer to new buffer. 7506 * Move each member individually to avoid possible store 7507 * forwarding stalls. 7508 */ 7509 new_buff->dma = old_buff->dma; 7510 new_buff->page = old_buff->page; 7511 new_buff->page_offset = old_buff->page_offset; 7512 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7513 } 7514 7515 static inline bool igb_page_is_reserved(struct page *page) 7516 { 7517 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7518 } 7519 7520 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7521 { 7522 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7523 struct page *page = rx_buffer->page; 7524 7525 /* avoid re-using remote pages */ 7526 if (unlikely(igb_page_is_reserved(page))) 7527 return false; 7528 7529 #if (PAGE_SIZE < 8192) 7530 /* if we are only owner of page we can reuse it */ 7531 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7532 return false; 7533 #else 7534 #define IGB_LAST_OFFSET \ 7535 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7536 7537 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7538 return false; 7539 #endif 7540 7541 /* If we have drained the page fragment pool we need to update 7542 * the pagecnt_bias and page count so that we fully restock the 7543 * number of references the driver holds. 7544 */ 7545 if (unlikely(!pagecnt_bias)) { 7546 page_ref_add(page, USHRT_MAX); 7547 rx_buffer->pagecnt_bias = USHRT_MAX; 7548 } 7549 7550 return true; 7551 } 7552 7553 /** 7554 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7555 * @rx_ring: rx descriptor ring to transact packets on 7556 * @rx_buffer: buffer containing page to add 7557 * @skb: sk_buff to place the data into 7558 * @size: size of buffer to be added 7559 * 7560 * This function will add the data contained in rx_buffer->page to the skb. 7561 **/ 7562 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7563 struct igb_rx_buffer *rx_buffer, 7564 struct sk_buff *skb, 7565 unsigned int size) 7566 { 7567 #if (PAGE_SIZE < 8192) 7568 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7569 #else 7570 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7571 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7572 SKB_DATA_ALIGN(size); 7573 #endif 7574 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7575 rx_buffer->page_offset, size, truesize); 7576 #if (PAGE_SIZE < 8192) 7577 rx_buffer->page_offset ^= truesize; 7578 #else 7579 rx_buffer->page_offset += truesize; 7580 #endif 7581 } 7582 7583 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 7584 struct igb_rx_buffer *rx_buffer, 7585 union e1000_adv_rx_desc *rx_desc, 7586 unsigned int size) 7587 { 7588 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7589 #if (PAGE_SIZE < 8192) 7590 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7591 #else 7592 unsigned int truesize = SKB_DATA_ALIGN(size); 7593 #endif 7594 unsigned int headlen; 7595 struct sk_buff *skb; 7596 7597 /* prefetch first cache line of first page */ 7598 prefetch(va); 7599 #if L1_CACHE_BYTES < 128 7600 prefetch(va + L1_CACHE_BYTES); 7601 #endif 7602 7603 /* allocate a skb to store the frags */ 7604 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 7605 if (unlikely(!skb)) 7606 return NULL; 7607 7608 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 7609 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 7610 va += IGB_TS_HDR_LEN; 7611 size -= IGB_TS_HDR_LEN; 7612 } 7613 7614 /* Determine available headroom for copy */ 7615 headlen = size; 7616 if (headlen > IGB_RX_HDR_LEN) 7617 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7618 7619 /* align pull length to size of long to optimize memcpy performance */ 7620 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7621 7622 /* update all of the pointers */ 7623 size -= headlen; 7624 if (size) { 7625 skb_add_rx_frag(skb, 0, rx_buffer->page, 7626 (va + headlen) - page_address(rx_buffer->page), 7627 size, truesize); 7628 #if (PAGE_SIZE < 8192) 7629 rx_buffer->page_offset ^= truesize; 7630 #else 7631 rx_buffer->page_offset += truesize; 7632 #endif 7633 } else { 7634 rx_buffer->pagecnt_bias++; 7635 } 7636 7637 return skb; 7638 } 7639 7640 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7641 struct igb_rx_buffer *rx_buffer, 7642 union e1000_adv_rx_desc *rx_desc, 7643 unsigned int size) 7644 { 7645 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7646 #if (PAGE_SIZE < 8192) 7647 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7648 #else 7649 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7650 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7651 #endif 7652 struct sk_buff *skb; 7653 7654 /* prefetch first cache line of first page */ 7655 prefetch(va); 7656 #if L1_CACHE_BYTES < 128 7657 prefetch(va + L1_CACHE_BYTES); 7658 #endif 7659 7660 /* build an skb around the page buffer */ 7661 skb = build_skb(va - IGB_SKB_PAD, truesize); 7662 if (unlikely(!skb)) 7663 return NULL; 7664 7665 /* update pointers within the skb to store the data */ 7666 skb_reserve(skb, IGB_SKB_PAD); 7667 __skb_put(skb, size); 7668 7669 /* pull timestamp out of packet data */ 7670 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7671 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7672 __skb_pull(skb, IGB_TS_HDR_LEN); 7673 } 7674 7675 /* update buffer offset */ 7676 #if (PAGE_SIZE < 8192) 7677 rx_buffer->page_offset ^= truesize; 7678 #else 7679 rx_buffer->page_offset += truesize; 7680 #endif 7681 7682 return skb; 7683 } 7684 7685 static inline void igb_rx_checksum(struct igb_ring *ring, 7686 union e1000_adv_rx_desc *rx_desc, 7687 struct sk_buff *skb) 7688 { 7689 skb_checksum_none_assert(skb); 7690 7691 /* Ignore Checksum bit is set */ 7692 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 7693 return; 7694 7695 /* Rx checksum disabled via ethtool */ 7696 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 7697 return; 7698 7699 /* TCP/UDP checksum error bit is set */ 7700 if (igb_test_staterr(rx_desc, 7701 E1000_RXDEXT_STATERR_TCPE | 7702 E1000_RXDEXT_STATERR_IPE)) { 7703 /* work around errata with sctp packets where the TCPE aka 7704 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7705 * packets, (aka let the stack check the crc32c) 7706 */ 7707 if (!((skb->len == 60) && 7708 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7709 u64_stats_update_begin(&ring->rx_syncp); 7710 ring->rx_stats.csum_err++; 7711 u64_stats_update_end(&ring->rx_syncp); 7712 } 7713 /* let the stack verify checksum errors */ 7714 return; 7715 } 7716 /* It must be a TCP or UDP packet with a valid checksum */ 7717 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7718 E1000_RXD_STAT_UDPCS)) 7719 skb->ip_summed = CHECKSUM_UNNECESSARY; 7720 7721 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7722 le32_to_cpu(rx_desc->wb.upper.status_error)); 7723 } 7724 7725 static inline void igb_rx_hash(struct igb_ring *ring, 7726 union e1000_adv_rx_desc *rx_desc, 7727 struct sk_buff *skb) 7728 { 7729 if (ring->netdev->features & NETIF_F_RXHASH) 7730 skb_set_hash(skb, 7731 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7732 PKT_HASH_TYPE_L3); 7733 } 7734 7735 /** 7736 * igb_is_non_eop - process handling of non-EOP buffers 7737 * @rx_ring: Rx ring being processed 7738 * @rx_desc: Rx descriptor for current buffer 7739 * @skb: current socket buffer containing buffer in progress 7740 * 7741 * This function updates next to clean. If the buffer is an EOP buffer 7742 * this function exits returning false, otherwise it will place the 7743 * sk_buff in the next buffer to be chained and return true indicating 7744 * that this is in fact a non-EOP buffer. 7745 **/ 7746 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7747 union e1000_adv_rx_desc *rx_desc) 7748 { 7749 u32 ntc = rx_ring->next_to_clean + 1; 7750 7751 /* fetch, update, and store next to clean */ 7752 ntc = (ntc < rx_ring->count) ? ntc : 0; 7753 rx_ring->next_to_clean = ntc; 7754 7755 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7756 7757 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7758 return false; 7759 7760 return true; 7761 } 7762 7763 /** 7764 * igb_cleanup_headers - Correct corrupted or empty headers 7765 * @rx_ring: rx descriptor ring packet is being transacted on 7766 * @rx_desc: pointer to the EOP Rx descriptor 7767 * @skb: pointer to current skb being fixed 7768 * 7769 * Address the case where we are pulling data in on pages only 7770 * and as such no data is present in the skb header. 7771 * 7772 * In addition if skb is not at least 60 bytes we need to pad it so that 7773 * it is large enough to qualify as a valid Ethernet frame. 7774 * 7775 * Returns true if an error was encountered and skb was freed. 7776 **/ 7777 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7778 union e1000_adv_rx_desc *rx_desc, 7779 struct sk_buff *skb) 7780 { 7781 if (unlikely((igb_test_staterr(rx_desc, 7782 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7783 struct net_device *netdev = rx_ring->netdev; 7784 if (!(netdev->features & NETIF_F_RXALL)) { 7785 dev_kfree_skb_any(skb); 7786 return true; 7787 } 7788 } 7789 7790 /* if eth_skb_pad returns an error the skb was freed */ 7791 if (eth_skb_pad(skb)) 7792 return true; 7793 7794 return false; 7795 } 7796 7797 /** 7798 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7799 * @rx_ring: rx descriptor ring packet is being transacted on 7800 * @rx_desc: pointer to the EOP Rx descriptor 7801 * @skb: pointer to current skb being populated 7802 * 7803 * This function checks the ring, descriptor, and packet information in 7804 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7805 * other fields within the skb. 7806 **/ 7807 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7808 union e1000_adv_rx_desc *rx_desc, 7809 struct sk_buff *skb) 7810 { 7811 struct net_device *dev = rx_ring->netdev; 7812 7813 igb_rx_hash(rx_ring, rx_desc, skb); 7814 7815 igb_rx_checksum(rx_ring, rx_desc, skb); 7816 7817 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7818 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7819 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7820 7821 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7822 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7823 u16 vid; 7824 7825 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7826 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7827 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7828 else 7829 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7830 7831 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7832 } 7833 7834 skb_record_rx_queue(skb, rx_ring->queue_index); 7835 7836 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7837 } 7838 7839 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 7840 const unsigned int size) 7841 { 7842 struct igb_rx_buffer *rx_buffer; 7843 7844 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 7845 prefetchw(rx_buffer->page); 7846 7847 /* we are reusing so sync this buffer for CPU use */ 7848 dma_sync_single_range_for_cpu(rx_ring->dev, 7849 rx_buffer->dma, 7850 rx_buffer->page_offset, 7851 size, 7852 DMA_FROM_DEVICE); 7853 7854 rx_buffer->pagecnt_bias--; 7855 7856 return rx_buffer; 7857 } 7858 7859 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 7860 struct igb_rx_buffer *rx_buffer) 7861 { 7862 if (igb_can_reuse_rx_page(rx_buffer)) { 7863 /* hand second half of page back to the ring */ 7864 igb_reuse_rx_page(rx_ring, rx_buffer); 7865 } else { 7866 /* We are not reusing the buffer so unmap it and free 7867 * any references we are holding to it 7868 */ 7869 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 7870 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 7871 IGB_RX_DMA_ATTR); 7872 __page_frag_cache_drain(rx_buffer->page, 7873 rx_buffer->pagecnt_bias); 7874 } 7875 7876 /* clear contents of rx_buffer */ 7877 rx_buffer->page = NULL; 7878 } 7879 7880 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7881 { 7882 struct igb_ring *rx_ring = q_vector->rx.ring; 7883 struct sk_buff *skb = rx_ring->skb; 7884 unsigned int total_bytes = 0, total_packets = 0; 7885 u16 cleaned_count = igb_desc_unused(rx_ring); 7886 7887 while (likely(total_packets < budget)) { 7888 union e1000_adv_rx_desc *rx_desc; 7889 struct igb_rx_buffer *rx_buffer; 7890 unsigned int size; 7891 7892 /* return some buffers to hardware, one at a time is too slow */ 7893 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7894 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7895 cleaned_count = 0; 7896 } 7897 7898 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7899 size = le16_to_cpu(rx_desc->wb.upper.length); 7900 if (!size) 7901 break; 7902 7903 /* This memory barrier is needed to keep us from reading 7904 * any other fields out of the rx_desc until we know the 7905 * descriptor has been written back 7906 */ 7907 dma_rmb(); 7908 7909 rx_buffer = igb_get_rx_buffer(rx_ring, size); 7910 7911 /* retrieve a buffer from the ring */ 7912 if (skb) 7913 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 7914 else if (ring_uses_build_skb(rx_ring)) 7915 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 7916 else 7917 skb = igb_construct_skb(rx_ring, rx_buffer, 7918 rx_desc, size); 7919 7920 /* exit if we failed to retrieve a buffer */ 7921 if (!skb) { 7922 rx_ring->rx_stats.alloc_failed++; 7923 rx_buffer->pagecnt_bias++; 7924 break; 7925 } 7926 7927 igb_put_rx_buffer(rx_ring, rx_buffer); 7928 cleaned_count++; 7929 7930 /* fetch next buffer in frame if non-eop */ 7931 if (igb_is_non_eop(rx_ring, rx_desc)) 7932 continue; 7933 7934 /* verify the packet layout is correct */ 7935 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7936 skb = NULL; 7937 continue; 7938 } 7939 7940 /* probably a little skewed due to removing CRC */ 7941 total_bytes += skb->len; 7942 7943 /* populate checksum, timestamp, VLAN, and protocol */ 7944 igb_process_skb_fields(rx_ring, rx_desc, skb); 7945 7946 napi_gro_receive(&q_vector->napi, skb); 7947 7948 /* reset skb pointer */ 7949 skb = NULL; 7950 7951 /* update budget accounting */ 7952 total_packets++; 7953 } 7954 7955 /* place incomplete frames back on ring for completion */ 7956 rx_ring->skb = skb; 7957 7958 u64_stats_update_begin(&rx_ring->rx_syncp); 7959 rx_ring->rx_stats.packets += total_packets; 7960 rx_ring->rx_stats.bytes += total_bytes; 7961 u64_stats_update_end(&rx_ring->rx_syncp); 7962 q_vector->rx.total_packets += total_packets; 7963 q_vector->rx.total_bytes += total_bytes; 7964 7965 if (cleaned_count) 7966 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7967 7968 return total_packets; 7969 } 7970 7971 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 7972 { 7973 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 7974 } 7975 7976 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7977 struct igb_rx_buffer *bi) 7978 { 7979 struct page *page = bi->page; 7980 dma_addr_t dma; 7981 7982 /* since we are recycling buffers we should seldom need to alloc */ 7983 if (likely(page)) 7984 return true; 7985 7986 /* alloc new page for storage */ 7987 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 7988 if (unlikely(!page)) { 7989 rx_ring->rx_stats.alloc_failed++; 7990 return false; 7991 } 7992 7993 /* map page for use */ 7994 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 7995 igb_rx_pg_size(rx_ring), 7996 DMA_FROM_DEVICE, 7997 IGB_RX_DMA_ATTR); 7998 7999 /* if mapping failed free memory back to system since 8000 * there isn't much point in holding memory we can't use 8001 */ 8002 if (dma_mapping_error(rx_ring->dev, dma)) { 8003 __free_pages(page, igb_rx_pg_order(rx_ring)); 8004 8005 rx_ring->rx_stats.alloc_failed++; 8006 return false; 8007 } 8008 8009 bi->dma = dma; 8010 bi->page = page; 8011 bi->page_offset = igb_rx_offset(rx_ring); 8012 bi->pagecnt_bias = 1; 8013 8014 return true; 8015 } 8016 8017 /** 8018 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 8019 * @adapter: address of board private structure 8020 **/ 8021 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8022 { 8023 union e1000_adv_rx_desc *rx_desc; 8024 struct igb_rx_buffer *bi; 8025 u16 i = rx_ring->next_to_use; 8026 u16 bufsz; 8027 8028 /* nothing to do */ 8029 if (!cleaned_count) 8030 return; 8031 8032 rx_desc = IGB_RX_DESC(rx_ring, i); 8033 bi = &rx_ring->rx_buffer_info[i]; 8034 i -= rx_ring->count; 8035 8036 bufsz = igb_rx_bufsz(rx_ring); 8037 8038 do { 8039 if (!igb_alloc_mapped_page(rx_ring, bi)) 8040 break; 8041 8042 /* sync the buffer for use by the device */ 8043 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8044 bi->page_offset, bufsz, 8045 DMA_FROM_DEVICE); 8046 8047 /* Refresh the desc even if buffer_addrs didn't change 8048 * because each write-back erases this info. 8049 */ 8050 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8051 8052 rx_desc++; 8053 bi++; 8054 i++; 8055 if (unlikely(!i)) { 8056 rx_desc = IGB_RX_DESC(rx_ring, 0); 8057 bi = rx_ring->rx_buffer_info; 8058 i -= rx_ring->count; 8059 } 8060 8061 /* clear the length for the next_to_use descriptor */ 8062 rx_desc->wb.upper.length = 0; 8063 8064 cleaned_count--; 8065 } while (cleaned_count); 8066 8067 i += rx_ring->count; 8068 8069 if (rx_ring->next_to_use != i) { 8070 /* record the next descriptor to use */ 8071 rx_ring->next_to_use = i; 8072 8073 /* update next to alloc since we have filled the ring */ 8074 rx_ring->next_to_alloc = i; 8075 8076 /* Force memory writes to complete before letting h/w 8077 * know there are new descriptors to fetch. (Only 8078 * applicable for weak-ordered memory model archs, 8079 * such as IA-64). 8080 */ 8081 wmb(); 8082 writel(i, rx_ring->tail); 8083 } 8084 } 8085 8086 /** 8087 * igb_mii_ioctl - 8088 * @netdev: 8089 * @ifreq: 8090 * @cmd: 8091 **/ 8092 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8093 { 8094 struct igb_adapter *adapter = netdev_priv(netdev); 8095 struct mii_ioctl_data *data = if_mii(ifr); 8096 8097 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8098 return -EOPNOTSUPP; 8099 8100 switch (cmd) { 8101 case SIOCGMIIPHY: 8102 data->phy_id = adapter->hw.phy.addr; 8103 break; 8104 case SIOCGMIIREG: 8105 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8106 &data->val_out)) 8107 return -EIO; 8108 break; 8109 case SIOCSMIIREG: 8110 default: 8111 return -EOPNOTSUPP; 8112 } 8113 return 0; 8114 } 8115 8116 /** 8117 * igb_ioctl - 8118 * @netdev: 8119 * @ifreq: 8120 * @cmd: 8121 **/ 8122 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8123 { 8124 switch (cmd) { 8125 case SIOCGMIIPHY: 8126 case SIOCGMIIREG: 8127 case SIOCSMIIREG: 8128 return igb_mii_ioctl(netdev, ifr, cmd); 8129 case SIOCGHWTSTAMP: 8130 return igb_ptp_get_ts_config(netdev, ifr); 8131 case SIOCSHWTSTAMP: 8132 return igb_ptp_set_ts_config(netdev, ifr); 8133 default: 8134 return -EOPNOTSUPP; 8135 } 8136 } 8137 8138 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8139 { 8140 struct igb_adapter *adapter = hw->back; 8141 8142 pci_read_config_word(adapter->pdev, reg, value); 8143 } 8144 8145 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8146 { 8147 struct igb_adapter *adapter = hw->back; 8148 8149 pci_write_config_word(adapter->pdev, reg, *value); 8150 } 8151 8152 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8153 { 8154 struct igb_adapter *adapter = hw->back; 8155 8156 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8157 return -E1000_ERR_CONFIG; 8158 8159 return 0; 8160 } 8161 8162 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8163 { 8164 struct igb_adapter *adapter = hw->back; 8165 8166 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 8167 return -E1000_ERR_CONFIG; 8168 8169 return 0; 8170 } 8171 8172 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 8173 { 8174 struct igb_adapter *adapter = netdev_priv(netdev); 8175 struct e1000_hw *hw = &adapter->hw; 8176 u32 ctrl, rctl; 8177 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 8178 8179 if (enable) { 8180 /* enable VLAN tag insert/strip */ 8181 ctrl = rd32(E1000_CTRL); 8182 ctrl |= E1000_CTRL_VME; 8183 wr32(E1000_CTRL, ctrl); 8184 8185 /* Disable CFI check */ 8186 rctl = rd32(E1000_RCTL); 8187 rctl &= ~E1000_RCTL_CFIEN; 8188 wr32(E1000_RCTL, rctl); 8189 } else { 8190 /* disable VLAN tag insert/strip */ 8191 ctrl = rd32(E1000_CTRL); 8192 ctrl &= ~E1000_CTRL_VME; 8193 wr32(E1000_CTRL, ctrl); 8194 } 8195 8196 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 8197 } 8198 8199 static int igb_vlan_rx_add_vid(struct net_device *netdev, 8200 __be16 proto, u16 vid) 8201 { 8202 struct igb_adapter *adapter = netdev_priv(netdev); 8203 struct e1000_hw *hw = &adapter->hw; 8204 int pf_id = adapter->vfs_allocated_count; 8205 8206 /* add the filter since PF can receive vlans w/o entry in vlvf */ 8207 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8208 igb_vfta_set(hw, vid, pf_id, true, !!vid); 8209 8210 set_bit(vid, adapter->active_vlans); 8211 8212 return 0; 8213 } 8214 8215 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 8216 __be16 proto, u16 vid) 8217 { 8218 struct igb_adapter *adapter = netdev_priv(netdev); 8219 int pf_id = adapter->vfs_allocated_count; 8220 struct e1000_hw *hw = &adapter->hw; 8221 8222 /* remove VID from filter table */ 8223 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 8224 igb_vfta_set(hw, vid, pf_id, false, true); 8225 8226 clear_bit(vid, adapter->active_vlans); 8227 8228 return 0; 8229 } 8230 8231 static void igb_restore_vlan(struct igb_adapter *adapter) 8232 { 8233 u16 vid = 1; 8234 8235 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 8236 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 8237 8238 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 8239 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 8240 } 8241 8242 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 8243 { 8244 struct pci_dev *pdev = adapter->pdev; 8245 struct e1000_mac_info *mac = &adapter->hw.mac; 8246 8247 mac->autoneg = 0; 8248 8249 /* Make sure dplx is at most 1 bit and lsb of speed is not set 8250 * for the switch() below to work 8251 */ 8252 if ((spd & 1) || (dplx & ~1)) 8253 goto err_inval; 8254 8255 /* Fiber NIC's only allow 1000 gbps Full duplex 8256 * and 100Mbps Full duplex for 100baseFx sfp 8257 */ 8258 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 8259 switch (spd + dplx) { 8260 case SPEED_10 + DUPLEX_HALF: 8261 case SPEED_10 + DUPLEX_FULL: 8262 case SPEED_100 + DUPLEX_HALF: 8263 goto err_inval; 8264 default: 8265 break; 8266 } 8267 } 8268 8269 switch (spd + dplx) { 8270 case SPEED_10 + DUPLEX_HALF: 8271 mac->forced_speed_duplex = ADVERTISE_10_HALF; 8272 break; 8273 case SPEED_10 + DUPLEX_FULL: 8274 mac->forced_speed_duplex = ADVERTISE_10_FULL; 8275 break; 8276 case SPEED_100 + DUPLEX_HALF: 8277 mac->forced_speed_duplex = ADVERTISE_100_HALF; 8278 break; 8279 case SPEED_100 + DUPLEX_FULL: 8280 mac->forced_speed_duplex = ADVERTISE_100_FULL; 8281 break; 8282 case SPEED_1000 + DUPLEX_FULL: 8283 mac->autoneg = 1; 8284 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 8285 break; 8286 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 8287 default: 8288 goto err_inval; 8289 } 8290 8291 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 8292 adapter->hw.phy.mdix = AUTO_ALL_MODES; 8293 8294 return 0; 8295 8296 err_inval: 8297 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 8298 return -EINVAL; 8299 } 8300 8301 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 8302 bool runtime) 8303 { 8304 struct net_device *netdev = pci_get_drvdata(pdev); 8305 struct igb_adapter *adapter = netdev_priv(netdev); 8306 struct e1000_hw *hw = &adapter->hw; 8307 u32 ctrl, rctl, status; 8308 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 8309 #ifdef CONFIG_PM 8310 int retval = 0; 8311 #endif 8312 8313 rtnl_lock(); 8314 netif_device_detach(netdev); 8315 8316 if (netif_running(netdev)) 8317 __igb_close(netdev, true); 8318 8319 igb_ptp_suspend(adapter); 8320 8321 igb_clear_interrupt_scheme(adapter); 8322 rtnl_unlock(); 8323 8324 #ifdef CONFIG_PM 8325 retval = pci_save_state(pdev); 8326 if (retval) 8327 return retval; 8328 #endif 8329 8330 status = rd32(E1000_STATUS); 8331 if (status & E1000_STATUS_LU) 8332 wufc &= ~E1000_WUFC_LNKC; 8333 8334 if (wufc) { 8335 igb_setup_rctl(adapter); 8336 igb_set_rx_mode(netdev); 8337 8338 /* turn on all-multi mode if wake on multicast is enabled */ 8339 if (wufc & E1000_WUFC_MC) { 8340 rctl = rd32(E1000_RCTL); 8341 rctl |= E1000_RCTL_MPE; 8342 wr32(E1000_RCTL, rctl); 8343 } 8344 8345 ctrl = rd32(E1000_CTRL); 8346 /* advertise wake from D3Cold */ 8347 #define E1000_CTRL_ADVD3WUC 0x00100000 8348 /* phy power management enable */ 8349 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 8350 ctrl |= E1000_CTRL_ADVD3WUC; 8351 wr32(E1000_CTRL, ctrl); 8352 8353 /* Allow time for pending master requests to run */ 8354 igb_disable_pcie_master(hw); 8355 8356 wr32(E1000_WUC, E1000_WUC_PME_EN); 8357 wr32(E1000_WUFC, wufc); 8358 } else { 8359 wr32(E1000_WUC, 0); 8360 wr32(E1000_WUFC, 0); 8361 } 8362 8363 *enable_wake = wufc || adapter->en_mng_pt; 8364 if (!*enable_wake) 8365 igb_power_down_link(adapter); 8366 else 8367 igb_power_up_link(adapter); 8368 8369 /* Release control of h/w to f/w. If f/w is AMT enabled, this 8370 * would have already happened in close and is redundant. 8371 */ 8372 igb_release_hw_control(adapter); 8373 8374 pci_disable_device(pdev); 8375 8376 return 0; 8377 } 8378 8379 static void igb_deliver_wake_packet(struct net_device *netdev) 8380 { 8381 struct igb_adapter *adapter = netdev_priv(netdev); 8382 struct e1000_hw *hw = &adapter->hw; 8383 struct sk_buff *skb; 8384 u32 wupl; 8385 8386 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8387 8388 /* WUPM stores only the first 128 bytes of the wake packet. 8389 * Read the packet only if we have the whole thing. 8390 */ 8391 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8392 return; 8393 8394 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8395 if (!skb) 8396 return; 8397 8398 skb_put(skb, wupl); 8399 8400 /* Ensure reads are 32-bit aligned */ 8401 wupl = roundup(wupl, 4); 8402 8403 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8404 8405 skb->protocol = eth_type_trans(skb, netdev); 8406 netif_rx(skb); 8407 } 8408 8409 static int __maybe_unused igb_suspend(struct device *dev) 8410 { 8411 int retval; 8412 bool wake; 8413 struct pci_dev *pdev = to_pci_dev(dev); 8414 8415 retval = __igb_shutdown(pdev, &wake, 0); 8416 if (retval) 8417 return retval; 8418 8419 if (wake) { 8420 pci_prepare_to_sleep(pdev); 8421 } else { 8422 pci_wake_from_d3(pdev, false); 8423 pci_set_power_state(pdev, PCI_D3hot); 8424 } 8425 8426 return 0; 8427 } 8428 8429 static int __maybe_unused igb_resume(struct device *dev) 8430 { 8431 struct pci_dev *pdev = to_pci_dev(dev); 8432 struct net_device *netdev = pci_get_drvdata(pdev); 8433 struct igb_adapter *adapter = netdev_priv(netdev); 8434 struct e1000_hw *hw = &adapter->hw; 8435 u32 err, val; 8436 8437 pci_set_power_state(pdev, PCI_D0); 8438 pci_restore_state(pdev); 8439 pci_save_state(pdev); 8440 8441 if (!pci_device_is_present(pdev)) 8442 return -ENODEV; 8443 err = pci_enable_device_mem(pdev); 8444 if (err) { 8445 dev_err(&pdev->dev, 8446 "igb: Cannot enable PCI device from suspend\n"); 8447 return err; 8448 } 8449 pci_set_master(pdev); 8450 8451 pci_enable_wake(pdev, PCI_D3hot, 0); 8452 pci_enable_wake(pdev, PCI_D3cold, 0); 8453 8454 if (igb_init_interrupt_scheme(adapter, true)) { 8455 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8456 return -ENOMEM; 8457 } 8458 8459 igb_reset(adapter); 8460 8461 /* let the f/w know that the h/w is now under the control of the 8462 * driver. 8463 */ 8464 igb_get_hw_control(adapter); 8465 8466 val = rd32(E1000_WUS); 8467 if (val & WAKE_PKT_WUS) 8468 igb_deliver_wake_packet(netdev); 8469 8470 wr32(E1000_WUS, ~0); 8471 8472 rtnl_lock(); 8473 if (!err && netif_running(netdev)) 8474 err = __igb_open(netdev, true); 8475 8476 if (!err) 8477 netif_device_attach(netdev); 8478 rtnl_unlock(); 8479 8480 return err; 8481 } 8482 8483 static int __maybe_unused igb_runtime_idle(struct device *dev) 8484 { 8485 struct pci_dev *pdev = to_pci_dev(dev); 8486 struct net_device *netdev = pci_get_drvdata(pdev); 8487 struct igb_adapter *adapter = netdev_priv(netdev); 8488 8489 if (!igb_has_link(adapter)) 8490 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8491 8492 return -EBUSY; 8493 } 8494 8495 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8496 { 8497 struct pci_dev *pdev = to_pci_dev(dev); 8498 int retval; 8499 bool wake; 8500 8501 retval = __igb_shutdown(pdev, &wake, 1); 8502 if (retval) 8503 return retval; 8504 8505 if (wake) { 8506 pci_prepare_to_sleep(pdev); 8507 } else { 8508 pci_wake_from_d3(pdev, false); 8509 pci_set_power_state(pdev, PCI_D3hot); 8510 } 8511 8512 return 0; 8513 } 8514 8515 static int __maybe_unused igb_runtime_resume(struct device *dev) 8516 { 8517 return igb_resume(dev); 8518 } 8519 8520 static void igb_shutdown(struct pci_dev *pdev) 8521 { 8522 bool wake; 8523 8524 __igb_shutdown(pdev, &wake, 0); 8525 8526 if (system_state == SYSTEM_POWER_OFF) { 8527 pci_wake_from_d3(pdev, wake); 8528 pci_set_power_state(pdev, PCI_D3hot); 8529 } 8530 } 8531 8532 #ifdef CONFIG_PCI_IOV 8533 static int igb_sriov_reinit(struct pci_dev *dev) 8534 { 8535 struct net_device *netdev = pci_get_drvdata(dev); 8536 struct igb_adapter *adapter = netdev_priv(netdev); 8537 struct pci_dev *pdev = adapter->pdev; 8538 8539 rtnl_lock(); 8540 8541 if (netif_running(netdev)) 8542 igb_close(netdev); 8543 else 8544 igb_reset(adapter); 8545 8546 igb_clear_interrupt_scheme(adapter); 8547 8548 igb_init_queue_configuration(adapter); 8549 8550 if (igb_init_interrupt_scheme(adapter, true)) { 8551 rtnl_unlock(); 8552 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8553 return -ENOMEM; 8554 } 8555 8556 if (netif_running(netdev)) 8557 igb_open(netdev); 8558 8559 rtnl_unlock(); 8560 8561 return 0; 8562 } 8563 8564 static int igb_pci_disable_sriov(struct pci_dev *dev) 8565 { 8566 int err = igb_disable_sriov(dev); 8567 8568 if (!err) 8569 err = igb_sriov_reinit(dev); 8570 8571 return err; 8572 } 8573 8574 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8575 { 8576 int err = igb_enable_sriov(dev, num_vfs); 8577 8578 if (err) 8579 goto out; 8580 8581 err = igb_sriov_reinit(dev); 8582 if (!err) 8583 return num_vfs; 8584 8585 out: 8586 return err; 8587 } 8588 8589 #endif 8590 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8591 { 8592 #ifdef CONFIG_PCI_IOV 8593 if (num_vfs == 0) 8594 return igb_pci_disable_sriov(dev); 8595 else 8596 return igb_pci_enable_sriov(dev, num_vfs); 8597 #endif 8598 return 0; 8599 } 8600 8601 #ifdef CONFIG_NET_POLL_CONTROLLER 8602 /* Polling 'interrupt' - used by things like netconsole to send skbs 8603 * without having to re-enable interrupts. It's not called while 8604 * the interrupt routine is executing. 8605 */ 8606 static void igb_netpoll(struct net_device *netdev) 8607 { 8608 struct igb_adapter *adapter = netdev_priv(netdev); 8609 struct e1000_hw *hw = &adapter->hw; 8610 struct igb_q_vector *q_vector; 8611 int i; 8612 8613 for (i = 0; i < adapter->num_q_vectors; i++) { 8614 q_vector = adapter->q_vector[i]; 8615 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8616 wr32(E1000_EIMC, q_vector->eims_value); 8617 else 8618 igb_irq_disable(adapter); 8619 napi_schedule(&q_vector->napi); 8620 } 8621 } 8622 #endif /* CONFIG_NET_POLL_CONTROLLER */ 8623 8624 /** 8625 * igb_io_error_detected - called when PCI error is detected 8626 * @pdev: Pointer to PCI device 8627 * @state: The current pci connection state 8628 * 8629 * This function is called after a PCI bus error affecting 8630 * this device has been detected. 8631 **/ 8632 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8633 pci_channel_state_t state) 8634 { 8635 struct net_device *netdev = pci_get_drvdata(pdev); 8636 struct igb_adapter *adapter = netdev_priv(netdev); 8637 8638 netif_device_detach(netdev); 8639 8640 if (state == pci_channel_io_perm_failure) 8641 return PCI_ERS_RESULT_DISCONNECT; 8642 8643 if (netif_running(netdev)) 8644 igb_down(adapter); 8645 pci_disable_device(pdev); 8646 8647 /* Request a slot slot reset. */ 8648 return PCI_ERS_RESULT_NEED_RESET; 8649 } 8650 8651 /** 8652 * igb_io_slot_reset - called after the pci bus has been reset. 8653 * @pdev: Pointer to PCI device 8654 * 8655 * Restart the card from scratch, as if from a cold-boot. Implementation 8656 * resembles the first-half of the igb_resume routine. 8657 **/ 8658 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8659 { 8660 struct net_device *netdev = pci_get_drvdata(pdev); 8661 struct igb_adapter *adapter = netdev_priv(netdev); 8662 struct e1000_hw *hw = &adapter->hw; 8663 pci_ers_result_t result; 8664 int err; 8665 8666 if (pci_enable_device_mem(pdev)) { 8667 dev_err(&pdev->dev, 8668 "Cannot re-enable PCI device after reset.\n"); 8669 result = PCI_ERS_RESULT_DISCONNECT; 8670 } else { 8671 pci_set_master(pdev); 8672 pci_restore_state(pdev); 8673 pci_save_state(pdev); 8674 8675 pci_enable_wake(pdev, PCI_D3hot, 0); 8676 pci_enable_wake(pdev, PCI_D3cold, 0); 8677 8678 /* In case of PCI error, adapter lose its HW address 8679 * so we should re-assign it here. 8680 */ 8681 hw->hw_addr = adapter->io_addr; 8682 8683 igb_reset(adapter); 8684 wr32(E1000_WUS, ~0); 8685 result = PCI_ERS_RESULT_RECOVERED; 8686 } 8687 8688 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8689 if (err) { 8690 dev_err(&pdev->dev, 8691 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8692 err); 8693 /* non-fatal, continue */ 8694 } 8695 8696 return result; 8697 } 8698 8699 /** 8700 * igb_io_resume - called when traffic can start flowing again. 8701 * @pdev: Pointer to PCI device 8702 * 8703 * This callback is called when the error recovery driver tells us that 8704 * its OK to resume normal operation. Implementation resembles the 8705 * second-half of the igb_resume routine. 8706 */ 8707 static void igb_io_resume(struct pci_dev *pdev) 8708 { 8709 struct net_device *netdev = pci_get_drvdata(pdev); 8710 struct igb_adapter *adapter = netdev_priv(netdev); 8711 8712 if (netif_running(netdev)) { 8713 if (igb_up(adapter)) { 8714 dev_err(&pdev->dev, "igb_up failed after reset\n"); 8715 return; 8716 } 8717 } 8718 8719 netif_device_attach(netdev); 8720 8721 /* let the f/w know that the h/w is now under the control of the 8722 * driver. 8723 */ 8724 igb_get_hw_control(adapter); 8725 } 8726 8727 /** 8728 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 8729 * @adapter: Pointer to adapter structure 8730 * @index: Index of the RAR entry which need to be synced with MAC table 8731 **/ 8732 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 8733 { 8734 struct e1000_hw *hw = &adapter->hw; 8735 u32 rar_low, rar_high; 8736 u8 *addr = adapter->mac_table[index].addr; 8737 8738 /* HW expects these to be in network order when they are plugged 8739 * into the registers which are little endian. In order to guarantee 8740 * that ordering we need to do an leXX_to_cpup here in order to be 8741 * ready for the byteswap that occurs with writel 8742 */ 8743 rar_low = le32_to_cpup((__le32 *)(addr)); 8744 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 8745 8746 /* Indicate to hardware the Address is Valid. */ 8747 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 8748 if (is_valid_ether_addr(addr)) 8749 rar_high |= E1000_RAH_AV; 8750 8751 if (hw->mac.type == e1000_82575) 8752 rar_high |= E1000_RAH_POOL_1 * 8753 adapter->mac_table[index].queue; 8754 else 8755 rar_high |= E1000_RAH_POOL_1 << 8756 adapter->mac_table[index].queue; 8757 } 8758 8759 wr32(E1000_RAL(index), rar_low); 8760 wrfl(); 8761 wr32(E1000_RAH(index), rar_high); 8762 wrfl(); 8763 } 8764 8765 static int igb_set_vf_mac(struct igb_adapter *adapter, 8766 int vf, unsigned char *mac_addr) 8767 { 8768 struct e1000_hw *hw = &adapter->hw; 8769 /* VF MAC addresses start at end of receive addresses and moves 8770 * towards the first, as a result a collision should not be possible 8771 */ 8772 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 8773 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 8774 8775 ether_addr_copy(vf_mac_addr, mac_addr); 8776 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 8777 adapter->mac_table[rar_entry].queue = vf; 8778 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 8779 igb_rar_set_index(adapter, rar_entry); 8780 8781 return 0; 8782 } 8783 8784 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 8785 { 8786 struct igb_adapter *adapter = netdev_priv(netdev); 8787 8788 if (vf >= adapter->vfs_allocated_count) 8789 return -EINVAL; 8790 8791 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 8792 * flag and allows to overwrite the MAC via VF netdev. This 8793 * is necessary to allow libvirt a way to restore the original 8794 * MAC after unbinding vfio-pci and reloading igbvf after shutting 8795 * down a VM. 8796 */ 8797 if (is_zero_ether_addr(mac)) { 8798 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 8799 dev_info(&adapter->pdev->dev, 8800 "remove administratively set MAC on VF %d\n", 8801 vf); 8802 } else if (is_valid_ether_addr(mac)) { 8803 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 8804 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 8805 mac, vf); 8806 dev_info(&adapter->pdev->dev, 8807 "Reload the VF driver to make this change effective."); 8808 /* Generate additional warning if PF is down */ 8809 if (test_bit(__IGB_DOWN, &adapter->state)) { 8810 dev_warn(&adapter->pdev->dev, 8811 "The VF MAC address has been set, but the PF device is not up.\n"); 8812 dev_warn(&adapter->pdev->dev, 8813 "Bring the PF device up before attempting to use the VF device.\n"); 8814 } 8815 } else { 8816 return -EINVAL; 8817 } 8818 return igb_set_vf_mac(adapter, vf, mac); 8819 } 8820 8821 static int igb_link_mbps(int internal_link_speed) 8822 { 8823 switch (internal_link_speed) { 8824 case SPEED_100: 8825 return 100; 8826 case SPEED_1000: 8827 return 1000; 8828 default: 8829 return 0; 8830 } 8831 } 8832 8833 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 8834 int link_speed) 8835 { 8836 int rf_dec, rf_int; 8837 u32 bcnrc_val; 8838 8839 if (tx_rate != 0) { 8840 /* Calculate the rate factor values to set */ 8841 rf_int = link_speed / tx_rate; 8842 rf_dec = (link_speed - (rf_int * tx_rate)); 8843 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8844 tx_rate; 8845 8846 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8847 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8848 E1000_RTTBCNRC_RF_INT_MASK); 8849 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8850 } else { 8851 bcnrc_val = 0; 8852 } 8853 8854 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8855 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8856 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8857 */ 8858 wr32(E1000_RTTBCNRM, 0x14); 8859 wr32(E1000_RTTBCNRC, bcnrc_val); 8860 } 8861 8862 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8863 { 8864 int actual_link_speed, i; 8865 bool reset_rate = false; 8866 8867 /* VF TX rate limit was not set or not supported */ 8868 if ((adapter->vf_rate_link_speed == 0) || 8869 (adapter->hw.mac.type != e1000_82576)) 8870 return; 8871 8872 actual_link_speed = igb_link_mbps(adapter->link_speed); 8873 if (actual_link_speed != adapter->vf_rate_link_speed) { 8874 reset_rate = true; 8875 adapter->vf_rate_link_speed = 0; 8876 dev_info(&adapter->pdev->dev, 8877 "Link speed has been changed. VF Transmit rate is disabled\n"); 8878 } 8879 8880 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8881 if (reset_rate) 8882 adapter->vf_data[i].tx_rate = 0; 8883 8884 igb_set_vf_rate_limit(&adapter->hw, i, 8885 adapter->vf_data[i].tx_rate, 8886 actual_link_speed); 8887 } 8888 } 8889 8890 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8891 int min_tx_rate, int max_tx_rate) 8892 { 8893 struct igb_adapter *adapter = netdev_priv(netdev); 8894 struct e1000_hw *hw = &adapter->hw; 8895 int actual_link_speed; 8896 8897 if (hw->mac.type != e1000_82576) 8898 return -EOPNOTSUPP; 8899 8900 if (min_tx_rate) 8901 return -EINVAL; 8902 8903 actual_link_speed = igb_link_mbps(adapter->link_speed); 8904 if ((vf >= adapter->vfs_allocated_count) || 8905 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8906 (max_tx_rate < 0) || 8907 (max_tx_rate > actual_link_speed)) 8908 return -EINVAL; 8909 8910 adapter->vf_rate_link_speed = actual_link_speed; 8911 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8912 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8913 8914 return 0; 8915 } 8916 8917 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8918 bool setting) 8919 { 8920 struct igb_adapter *adapter = netdev_priv(netdev); 8921 struct e1000_hw *hw = &adapter->hw; 8922 u32 reg_val, reg_offset; 8923 8924 if (!adapter->vfs_allocated_count) 8925 return -EOPNOTSUPP; 8926 8927 if (vf >= adapter->vfs_allocated_count) 8928 return -EINVAL; 8929 8930 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8931 reg_val = rd32(reg_offset); 8932 if (setting) 8933 reg_val |= (BIT(vf) | 8934 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8935 else 8936 reg_val &= ~(BIT(vf) | 8937 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8938 wr32(reg_offset, reg_val); 8939 8940 adapter->vf_data[vf].spoofchk_enabled = setting; 8941 return 0; 8942 } 8943 8944 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 8945 { 8946 struct igb_adapter *adapter = netdev_priv(netdev); 8947 8948 if (vf >= adapter->vfs_allocated_count) 8949 return -EINVAL; 8950 if (adapter->vf_data[vf].trusted == setting) 8951 return 0; 8952 8953 adapter->vf_data[vf].trusted = setting; 8954 8955 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 8956 vf, setting ? "" : "not "); 8957 return 0; 8958 } 8959 8960 static int igb_ndo_get_vf_config(struct net_device *netdev, 8961 int vf, struct ifla_vf_info *ivi) 8962 { 8963 struct igb_adapter *adapter = netdev_priv(netdev); 8964 if (vf >= adapter->vfs_allocated_count) 8965 return -EINVAL; 8966 ivi->vf = vf; 8967 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8968 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8969 ivi->min_tx_rate = 0; 8970 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8971 ivi->qos = adapter->vf_data[vf].pf_qos; 8972 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8973 ivi->trusted = adapter->vf_data[vf].trusted; 8974 return 0; 8975 } 8976 8977 static void igb_vmm_control(struct igb_adapter *adapter) 8978 { 8979 struct e1000_hw *hw = &adapter->hw; 8980 u32 reg; 8981 8982 switch (hw->mac.type) { 8983 case e1000_82575: 8984 case e1000_i210: 8985 case e1000_i211: 8986 case e1000_i354: 8987 default: 8988 /* replication is not supported for 82575 */ 8989 return; 8990 case e1000_82576: 8991 /* notify HW that the MAC is adding vlan tags */ 8992 reg = rd32(E1000_DTXCTL); 8993 reg |= E1000_DTXCTL_VLAN_ADDED; 8994 wr32(E1000_DTXCTL, reg); 8995 /* Fall through */ 8996 case e1000_82580: 8997 /* enable replication vlan tag stripping */ 8998 reg = rd32(E1000_RPLOLR); 8999 reg |= E1000_RPLOLR_STRVLAN; 9000 wr32(E1000_RPLOLR, reg); 9001 /* Fall through */ 9002 case e1000_i350: 9003 /* none of the above registers are supported by i350 */ 9004 break; 9005 } 9006 9007 if (adapter->vfs_allocated_count) { 9008 igb_vmdq_set_loopback_pf(hw, true); 9009 igb_vmdq_set_replication_pf(hw, true); 9010 igb_vmdq_set_anti_spoofing_pf(hw, true, 9011 adapter->vfs_allocated_count); 9012 } else { 9013 igb_vmdq_set_loopback_pf(hw, false); 9014 igb_vmdq_set_replication_pf(hw, false); 9015 } 9016 } 9017 9018 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9019 { 9020 struct e1000_hw *hw = &adapter->hw; 9021 u32 dmac_thr; 9022 u16 hwm; 9023 9024 if (hw->mac.type > e1000_82580) { 9025 if (adapter->flags & IGB_FLAG_DMAC) { 9026 u32 reg; 9027 9028 /* force threshold to 0. */ 9029 wr32(E1000_DMCTXTH, 0); 9030 9031 /* DMA Coalescing high water mark needs to be greater 9032 * than the Rx threshold. Set hwm to PBA - max frame 9033 * size in 16B units, capping it at PBA - 6KB. 9034 */ 9035 hwm = 64 * (pba - 6); 9036 reg = rd32(E1000_FCRTC); 9037 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9038 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9039 & E1000_FCRTC_RTH_COAL_MASK); 9040 wr32(E1000_FCRTC, reg); 9041 9042 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9043 * frame size, capping it at PBA - 10KB. 9044 */ 9045 dmac_thr = pba - 10; 9046 reg = rd32(E1000_DMACR); 9047 reg &= ~E1000_DMACR_DMACTHR_MASK; 9048 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9049 & E1000_DMACR_DMACTHR_MASK); 9050 9051 /* transition to L0x or L1 if available..*/ 9052 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9053 9054 /* watchdog timer= +-1000 usec in 32usec intervals */ 9055 reg |= (1000 >> 5); 9056 9057 /* Disable BMC-to-OS Watchdog Enable */ 9058 if (hw->mac.type != e1000_i354) 9059 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9060 9061 wr32(E1000_DMACR, reg); 9062 9063 /* no lower threshold to disable 9064 * coalescing(smart fifb)-UTRESH=0 9065 */ 9066 wr32(E1000_DMCRTRH, 0); 9067 9068 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9069 9070 wr32(E1000_DMCTLX, reg); 9071 9072 /* free space in tx packet buffer to wake from 9073 * DMA coal 9074 */ 9075 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9076 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9077 9078 /* make low power state decision controlled 9079 * by DMA coal 9080 */ 9081 reg = rd32(E1000_PCIEMISC); 9082 reg &= ~E1000_PCIEMISC_LX_DECISION; 9083 wr32(E1000_PCIEMISC, reg); 9084 } /* endif adapter->dmac is not disabled */ 9085 } else if (hw->mac.type == e1000_82580) { 9086 u32 reg = rd32(E1000_PCIEMISC); 9087 9088 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9089 wr32(E1000_DMACR, 0); 9090 } 9091 } 9092 9093 /** 9094 * igb_read_i2c_byte - Reads 8 bit word over I2C 9095 * @hw: pointer to hardware structure 9096 * @byte_offset: byte offset to read 9097 * @dev_addr: device address 9098 * @data: value read 9099 * 9100 * Performs byte read operation over I2C interface at 9101 * a specified device address. 9102 **/ 9103 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9104 u8 dev_addr, u8 *data) 9105 { 9106 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9107 struct i2c_client *this_client = adapter->i2c_client; 9108 s32 status; 9109 u16 swfw_mask = 0; 9110 9111 if (!this_client) 9112 return E1000_ERR_I2C; 9113 9114 swfw_mask = E1000_SWFW_PHY0_SM; 9115 9116 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9117 return E1000_ERR_SWFW_SYNC; 9118 9119 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9120 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9121 9122 if (status < 0) 9123 return E1000_ERR_I2C; 9124 else { 9125 *data = status; 9126 return 0; 9127 } 9128 } 9129 9130 /** 9131 * igb_write_i2c_byte - Writes 8 bit word over I2C 9132 * @hw: pointer to hardware structure 9133 * @byte_offset: byte offset to write 9134 * @dev_addr: device address 9135 * @data: value to write 9136 * 9137 * Performs byte write operation over I2C interface at 9138 * a specified device address. 9139 **/ 9140 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9141 u8 dev_addr, u8 data) 9142 { 9143 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9144 struct i2c_client *this_client = adapter->i2c_client; 9145 s32 status; 9146 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9147 9148 if (!this_client) 9149 return E1000_ERR_I2C; 9150 9151 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9152 return E1000_ERR_SWFW_SYNC; 9153 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9154 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9155 9156 if (status) 9157 return E1000_ERR_I2C; 9158 else 9159 return 0; 9160 9161 } 9162 9163 int igb_reinit_queues(struct igb_adapter *adapter) 9164 { 9165 struct net_device *netdev = adapter->netdev; 9166 struct pci_dev *pdev = adapter->pdev; 9167 int err = 0; 9168 9169 if (netif_running(netdev)) 9170 igb_close(netdev); 9171 9172 igb_reset_interrupt_capability(adapter); 9173 9174 if (igb_init_interrupt_scheme(adapter, true)) { 9175 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9176 return -ENOMEM; 9177 } 9178 9179 if (netif_running(netdev)) 9180 err = igb_open(netdev); 9181 9182 return err; 9183 } 9184 9185 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9186 { 9187 struct igb_nfc_filter *rule; 9188 9189 spin_lock(&adapter->nfc_lock); 9190 9191 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9192 igb_erase_filter(adapter, rule); 9193 9194 spin_unlock(&adapter->nfc_lock); 9195 } 9196 9197 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9198 { 9199 struct igb_nfc_filter *rule; 9200 9201 spin_lock(&adapter->nfc_lock); 9202 9203 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9204 igb_add_filter(adapter, rule); 9205 9206 spin_unlock(&adapter->nfc_lock); 9207 } 9208 /* igb_main.c */ 9209