1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 110 static void igb_remove(struct pci_dev *pdev); 111 static void igb_init_queue_configuration(struct igb_adapter *adapter); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 179 #endif 180 181 static int igb_suspend(struct device *); 182 static int igb_resume(struct device *); 183 static int igb_runtime_suspend(struct device *dev); 184 static int igb_runtime_resume(struct device *dev); 185 static int igb_runtime_idle(struct device *dev); 186 static const struct dev_pm_ops igb_pm_ops = { 187 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 188 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 189 igb_runtime_idle) 190 }; 191 static void igb_shutdown(struct pci_dev *); 192 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 193 #ifdef CONFIG_IGB_DCA 194 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 195 static struct notifier_block dca_notifier = { 196 .notifier_call = igb_notify_dca, 197 .next = NULL, 198 .priority = 0 199 }; 200 #endif 201 #ifdef CONFIG_PCI_IOV 202 static unsigned int max_vfs; 203 module_param(max_vfs, uint, 0); 204 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 205 #endif /* CONFIG_PCI_IOV */ 206 207 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 208 pci_channel_state_t); 209 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 210 static void igb_io_resume(struct pci_dev *); 211 212 static const struct pci_error_handlers igb_err_handler = { 213 .error_detected = igb_io_error_detected, 214 .slot_reset = igb_io_slot_reset, 215 .resume = igb_io_resume, 216 }; 217 218 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 219 220 static struct pci_driver igb_driver = { 221 .name = igb_driver_name, 222 .id_table = igb_pci_tbl, 223 .probe = igb_probe, 224 .remove = igb_remove, 225 #ifdef CONFIG_PM 226 .driver.pm = &igb_pm_ops, 227 #endif 228 .shutdown = igb_shutdown, 229 .sriov_configure = igb_pci_sriov_configure, 230 .err_handler = &igb_err_handler 231 }; 232 233 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 234 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 235 MODULE_LICENSE("GPL v2"); 236 237 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 238 static int debug = -1; 239 module_param(debug, int, 0); 240 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 241 242 struct igb_reg_info { 243 u32 ofs; 244 char *name; 245 }; 246 247 static const struct igb_reg_info igb_reg_info_tbl[] = { 248 249 /* General Registers */ 250 {E1000_CTRL, "CTRL"}, 251 {E1000_STATUS, "STATUS"}, 252 {E1000_CTRL_EXT, "CTRL_EXT"}, 253 254 /* Interrupt Registers */ 255 {E1000_ICR, "ICR"}, 256 257 /* RX Registers */ 258 {E1000_RCTL, "RCTL"}, 259 {E1000_RDLEN(0), "RDLEN"}, 260 {E1000_RDH(0), "RDH"}, 261 {E1000_RDT(0), "RDT"}, 262 {E1000_RXDCTL(0), "RXDCTL"}, 263 {E1000_RDBAL(0), "RDBAL"}, 264 {E1000_RDBAH(0), "RDBAH"}, 265 266 /* TX Registers */ 267 {E1000_TCTL, "TCTL"}, 268 {E1000_TDBAL(0), "TDBAL"}, 269 {E1000_TDBAH(0), "TDBAH"}, 270 {E1000_TDLEN(0), "TDLEN"}, 271 {E1000_TDH(0), "TDH"}, 272 {E1000_TDT(0), "TDT"}, 273 {E1000_TXDCTL(0), "TXDCTL"}, 274 {E1000_TDFH, "TDFH"}, 275 {E1000_TDFT, "TDFT"}, 276 {E1000_TDFHS, "TDFHS"}, 277 {E1000_TDFPC, "TDFPC"}, 278 279 /* List Terminator */ 280 {} 281 }; 282 283 /* igb_regdump - register printout routine */ 284 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 285 { 286 int n = 0; 287 char rname[16]; 288 u32 regs[8]; 289 290 switch (reginfo->ofs) { 291 case E1000_RDLEN(0): 292 for (n = 0; n < 4; n++) 293 regs[n] = rd32(E1000_RDLEN(n)); 294 break; 295 case E1000_RDH(0): 296 for (n = 0; n < 4; n++) 297 regs[n] = rd32(E1000_RDH(n)); 298 break; 299 case E1000_RDT(0): 300 for (n = 0; n < 4; n++) 301 regs[n] = rd32(E1000_RDT(n)); 302 break; 303 case E1000_RXDCTL(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RXDCTL(n)); 306 break; 307 case E1000_RDBAL(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDBAL(n)); 310 break; 311 case E1000_RDBAH(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RDBAH(n)); 314 break; 315 case E1000_TDBAL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_TDBAL(n)); 318 break; 319 case E1000_TDBAH(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_TDBAH(n)); 322 break; 323 case E1000_TDLEN(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_TDLEN(n)); 326 break; 327 case E1000_TDH(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_TDH(n)); 330 break; 331 case E1000_TDT(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDT(n)); 334 break; 335 case E1000_TXDCTL(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TXDCTL(n)); 338 break; 339 default: 340 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 341 return; 342 } 343 344 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 345 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 346 regs[2], regs[3]); 347 } 348 349 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 350 static void igb_dump(struct igb_adapter *adapter) 351 { 352 struct net_device *netdev = adapter->netdev; 353 struct e1000_hw *hw = &adapter->hw; 354 struct igb_reg_info *reginfo; 355 struct igb_ring *tx_ring; 356 union e1000_adv_tx_desc *tx_desc; 357 struct my_u0 { __le64 a; __le64 b; } *u0; 358 struct igb_ring *rx_ring; 359 union e1000_adv_rx_desc *rx_desc; 360 u32 staterr; 361 u16 i, n; 362 363 if (!netif_msg_hw(adapter)) 364 return; 365 366 /* Print netdevice Info */ 367 if (netdev) { 368 dev_info(&adapter->pdev->dev, "Net device Info\n"); 369 pr_info("Device Name state trans_start\n"); 370 pr_info("%-15s %016lX %016lX\n", netdev->name, 371 netdev->state, dev_trans_start(netdev)); 372 } 373 374 /* Print Registers */ 375 dev_info(&adapter->pdev->dev, "Register Dump\n"); 376 pr_info(" Register Name Value\n"); 377 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 378 reginfo->name; reginfo++) { 379 igb_regdump(hw, reginfo); 380 } 381 382 /* Print TX Ring Summary */ 383 if (!netdev || !netif_running(netdev)) 384 goto exit; 385 386 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 387 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 388 for (n = 0; n < adapter->num_tx_queues; n++) { 389 struct igb_tx_buffer *buffer_info; 390 tx_ring = adapter->tx_ring[n]; 391 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 392 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 393 n, tx_ring->next_to_use, tx_ring->next_to_clean, 394 (u64)dma_unmap_addr(buffer_info, dma), 395 dma_unmap_len(buffer_info, len), 396 buffer_info->next_to_watch, 397 (u64)buffer_info->time_stamp); 398 } 399 400 /* Print TX Rings */ 401 if (!netif_msg_tx_done(adapter)) 402 goto rx_ring_summary; 403 404 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 405 406 /* Transmit Descriptor Formats 407 * 408 * Advanced Transmit Descriptor 409 * +--------------------------------------------------------------+ 410 * 0 | Buffer Address [63:0] | 411 * +--------------------------------------------------------------+ 412 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 413 * +--------------------------------------------------------------+ 414 * 63 46 45 40 39 38 36 35 32 31 24 15 0 415 */ 416 417 for (n = 0; n < adapter->num_tx_queues; n++) { 418 tx_ring = adapter->tx_ring[n]; 419 pr_info("------------------------------------\n"); 420 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 421 pr_info("------------------------------------\n"); 422 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 423 424 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 425 const char *next_desc; 426 struct igb_tx_buffer *buffer_info; 427 tx_desc = IGB_TX_DESC(tx_ring, i); 428 buffer_info = &tx_ring->tx_buffer_info[i]; 429 u0 = (struct my_u0 *)tx_desc; 430 if (i == tx_ring->next_to_use && 431 i == tx_ring->next_to_clean) 432 next_desc = " NTC/U"; 433 else if (i == tx_ring->next_to_use) 434 next_desc = " NTU"; 435 else if (i == tx_ring->next_to_clean) 436 next_desc = " NTC"; 437 else 438 next_desc = ""; 439 440 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 441 i, le64_to_cpu(u0->a), 442 le64_to_cpu(u0->b), 443 (u64)dma_unmap_addr(buffer_info, dma), 444 dma_unmap_len(buffer_info, len), 445 buffer_info->next_to_watch, 446 (u64)buffer_info->time_stamp, 447 buffer_info->skb, next_desc); 448 449 if (netif_msg_pktdata(adapter) && buffer_info->skb) 450 print_hex_dump(KERN_INFO, "", 451 DUMP_PREFIX_ADDRESS, 452 16, 1, buffer_info->skb->data, 453 dma_unmap_len(buffer_info, len), 454 true); 455 } 456 } 457 458 /* Print RX Rings Summary */ 459 rx_ring_summary: 460 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 461 pr_info("Queue [NTU] [NTC]\n"); 462 for (n = 0; n < adapter->num_rx_queues; n++) { 463 rx_ring = adapter->rx_ring[n]; 464 pr_info(" %5d %5X %5X\n", 465 n, rx_ring->next_to_use, rx_ring->next_to_clean); 466 } 467 468 /* Print RX Rings */ 469 if (!netif_msg_rx_status(adapter)) 470 goto exit; 471 472 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 473 474 /* Advanced Receive Descriptor (Read) Format 475 * 63 1 0 476 * +-----------------------------------------------------+ 477 * 0 | Packet Buffer Address [63:1] |A0/NSE| 478 * +----------------------------------------------+------+ 479 * 8 | Header Buffer Address [63:1] | DD | 480 * +-----------------------------------------------------+ 481 * 482 * 483 * Advanced Receive Descriptor (Write-Back) Format 484 * 485 * 63 48 47 32 31 30 21 20 17 16 4 3 0 486 * +------------------------------------------------------+ 487 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 488 * | Checksum Ident | | | | Type | Type | 489 * +------------------------------------------------------+ 490 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 491 * +------------------------------------------------------+ 492 * 63 48 47 32 31 20 19 0 493 */ 494 495 for (n = 0; n < adapter->num_rx_queues; n++) { 496 rx_ring = adapter->rx_ring[n]; 497 pr_info("------------------------------------\n"); 498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 499 pr_info("------------------------------------\n"); 500 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 501 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 502 503 for (i = 0; i < rx_ring->count; i++) { 504 const char *next_desc; 505 struct igb_rx_buffer *buffer_info; 506 buffer_info = &rx_ring->rx_buffer_info[i]; 507 rx_desc = IGB_RX_DESC(rx_ring, i); 508 u0 = (struct my_u0 *)rx_desc; 509 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 510 511 if (i == rx_ring->next_to_use) 512 next_desc = " NTU"; 513 else if (i == rx_ring->next_to_clean) 514 next_desc = " NTC"; 515 else 516 next_desc = ""; 517 518 if (staterr & E1000_RXD_STAT_DD) { 519 /* Descriptor Done */ 520 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 521 "RWB", i, 522 le64_to_cpu(u0->a), 523 le64_to_cpu(u0->b), 524 next_desc); 525 } else { 526 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 527 "R ", i, 528 le64_to_cpu(u0->a), 529 le64_to_cpu(u0->b), 530 (u64)buffer_info->dma, 531 next_desc); 532 533 if (netif_msg_pktdata(adapter) && 534 buffer_info->dma && buffer_info->page) { 535 print_hex_dump(KERN_INFO, "", 536 DUMP_PREFIX_ADDRESS, 537 16, 1, 538 page_address(buffer_info->page) + 539 buffer_info->page_offset, 540 igb_rx_bufsz(rx_ring), true); 541 } 542 } 543 } 544 } 545 546 exit: 547 return; 548 } 549 550 /** 551 * igb_get_i2c_data - Reads the I2C SDA data bit 552 * @data: opaque pointer to adapter struct 553 * 554 * Returns the I2C data bit value 555 **/ 556 static int igb_get_i2c_data(void *data) 557 { 558 struct igb_adapter *adapter = (struct igb_adapter *)data; 559 struct e1000_hw *hw = &adapter->hw; 560 s32 i2cctl = rd32(E1000_I2CPARAMS); 561 562 return !!(i2cctl & E1000_I2C_DATA_IN); 563 } 564 565 /** 566 * igb_set_i2c_data - Sets the I2C data bit 567 * @data: pointer to hardware structure 568 * @state: I2C data value (0 or 1) to set 569 * 570 * Sets the I2C data bit 571 **/ 572 static void igb_set_i2c_data(void *data, int state) 573 { 574 struct igb_adapter *adapter = (struct igb_adapter *)data; 575 struct e1000_hw *hw = &adapter->hw; 576 s32 i2cctl = rd32(E1000_I2CPARAMS); 577 578 if (state) { 579 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 580 } else { 581 i2cctl &= ~E1000_I2C_DATA_OE_N; 582 i2cctl &= ~E1000_I2C_DATA_OUT; 583 } 584 585 wr32(E1000_I2CPARAMS, i2cctl); 586 wrfl(); 587 } 588 589 /** 590 * igb_set_i2c_clk - Sets the I2C SCL clock 591 * @data: pointer to hardware structure 592 * @state: state to set clock 593 * 594 * Sets the I2C clock line to state 595 **/ 596 static void igb_set_i2c_clk(void *data, int state) 597 { 598 struct igb_adapter *adapter = (struct igb_adapter *)data; 599 struct e1000_hw *hw = &adapter->hw; 600 s32 i2cctl = rd32(E1000_I2CPARAMS); 601 602 if (state) { 603 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 604 } else { 605 i2cctl &= ~E1000_I2C_CLK_OUT; 606 i2cctl &= ~E1000_I2C_CLK_OE_N; 607 } 608 wr32(E1000_I2CPARAMS, i2cctl); 609 wrfl(); 610 } 611 612 /** 613 * igb_get_i2c_clk - Gets the I2C SCL clock state 614 * @data: pointer to hardware structure 615 * 616 * Gets the I2C clock state 617 **/ 618 static int igb_get_i2c_clk(void *data) 619 { 620 struct igb_adapter *adapter = (struct igb_adapter *)data; 621 struct e1000_hw *hw = &adapter->hw; 622 s32 i2cctl = rd32(E1000_I2CPARAMS); 623 624 return !!(i2cctl & E1000_I2C_CLK_IN); 625 } 626 627 static const struct i2c_algo_bit_data igb_i2c_algo = { 628 .setsda = igb_set_i2c_data, 629 .setscl = igb_set_i2c_clk, 630 .getsda = igb_get_i2c_data, 631 .getscl = igb_get_i2c_clk, 632 .udelay = 5, 633 .timeout = 20, 634 }; 635 636 /** 637 * igb_get_hw_dev - return device 638 * @hw: pointer to hardware structure 639 * 640 * used by hardware layer to print debugging information 641 **/ 642 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 643 { 644 struct igb_adapter *adapter = hw->back; 645 return adapter->netdev; 646 } 647 648 /** 649 * igb_init_module - Driver Registration Routine 650 * 651 * igb_init_module is the first routine called when the driver is 652 * loaded. All it does is register with the PCI subsystem. 653 **/ 654 static int __init igb_init_module(void) 655 { 656 int ret; 657 658 pr_info("%s\n", igb_driver_string); 659 pr_info("%s\n", igb_copyright); 660 661 #ifdef CONFIG_IGB_DCA 662 dca_register_notify(&dca_notifier); 663 #endif 664 ret = pci_register_driver(&igb_driver); 665 return ret; 666 } 667 668 module_init(igb_init_module); 669 670 /** 671 * igb_exit_module - Driver Exit Cleanup Routine 672 * 673 * igb_exit_module is called just before the driver is removed 674 * from memory. 675 **/ 676 static void __exit igb_exit_module(void) 677 { 678 #ifdef CONFIG_IGB_DCA 679 dca_unregister_notify(&dca_notifier); 680 #endif 681 pci_unregister_driver(&igb_driver); 682 } 683 684 module_exit(igb_exit_module); 685 686 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 687 /** 688 * igb_cache_ring_register - Descriptor ring to register mapping 689 * @adapter: board private structure to initialize 690 * 691 * Once we know the feature-set enabled for the device, we'll cache 692 * the register offset the descriptor ring is assigned to. 693 **/ 694 static void igb_cache_ring_register(struct igb_adapter *adapter) 695 { 696 int i = 0, j = 0; 697 u32 rbase_offset = adapter->vfs_allocated_count; 698 699 switch (adapter->hw.mac.type) { 700 case e1000_82576: 701 /* The queues are allocated for virtualization such that VF 0 702 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 703 * In order to avoid collision we start at the first free queue 704 * and continue consuming queues in the same sequence 705 */ 706 if (adapter->vfs_allocated_count) { 707 for (; i < adapter->rss_queues; i++) 708 adapter->rx_ring[i]->reg_idx = rbase_offset + 709 Q_IDX_82576(i); 710 } 711 fallthrough; 712 case e1000_82575: 713 case e1000_82580: 714 case e1000_i350: 715 case e1000_i354: 716 case e1000_i210: 717 case e1000_i211: 718 default: 719 for (; i < adapter->num_rx_queues; i++) 720 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 721 for (; j < adapter->num_tx_queues; j++) 722 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 723 break; 724 } 725 } 726 727 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 728 { 729 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 730 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 731 u32 value = 0; 732 733 if (E1000_REMOVED(hw_addr)) 734 return ~value; 735 736 value = readl(&hw_addr[reg]); 737 738 /* reads should not return all F's */ 739 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 740 struct net_device *netdev = igb->netdev; 741 hw->hw_addr = NULL; 742 netdev_err(netdev, "PCIe link lost\n"); 743 WARN(pci_device_is_present(igb->pdev), 744 "igb: Failed to read reg 0x%x!\n", reg); 745 } 746 747 return value; 748 } 749 750 /** 751 * igb_write_ivar - configure ivar for given MSI-X vector 752 * @hw: pointer to the HW structure 753 * @msix_vector: vector number we are allocating to a given ring 754 * @index: row index of IVAR register to write within IVAR table 755 * @offset: column offset of in IVAR, should be multiple of 8 756 * 757 * This function is intended to handle the writing of the IVAR register 758 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 759 * each containing an cause allocation for an Rx and Tx ring, and a 760 * variable number of rows depending on the number of queues supported. 761 **/ 762 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 763 int index, int offset) 764 { 765 u32 ivar = array_rd32(E1000_IVAR0, index); 766 767 /* clear any bits that are currently set */ 768 ivar &= ~((u32)0xFF << offset); 769 770 /* write vector and valid bit */ 771 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 772 773 array_wr32(E1000_IVAR0, index, ivar); 774 } 775 776 #define IGB_N0_QUEUE -1 777 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 778 { 779 struct igb_adapter *adapter = q_vector->adapter; 780 struct e1000_hw *hw = &adapter->hw; 781 int rx_queue = IGB_N0_QUEUE; 782 int tx_queue = IGB_N0_QUEUE; 783 u32 msixbm = 0; 784 785 if (q_vector->rx.ring) 786 rx_queue = q_vector->rx.ring->reg_idx; 787 if (q_vector->tx.ring) 788 tx_queue = q_vector->tx.ring->reg_idx; 789 790 switch (hw->mac.type) { 791 case e1000_82575: 792 /* The 82575 assigns vectors using a bitmask, which matches the 793 * bitmask for the EICR/EIMS/EIMC registers. To assign one 794 * or more queues to a vector, we write the appropriate bits 795 * into the MSIXBM register for that vector. 796 */ 797 if (rx_queue > IGB_N0_QUEUE) 798 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 799 if (tx_queue > IGB_N0_QUEUE) 800 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 801 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 802 msixbm |= E1000_EIMS_OTHER; 803 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 804 q_vector->eims_value = msixbm; 805 break; 806 case e1000_82576: 807 /* 82576 uses a table that essentially consists of 2 columns 808 * with 8 rows. The ordering is column-major so we use the 809 * lower 3 bits as the row index, and the 4th bit as the 810 * column offset. 811 */ 812 if (rx_queue > IGB_N0_QUEUE) 813 igb_write_ivar(hw, msix_vector, 814 rx_queue & 0x7, 815 (rx_queue & 0x8) << 1); 816 if (tx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 tx_queue & 0x7, 819 ((tx_queue & 0x8) << 1) + 8); 820 q_vector->eims_value = BIT(msix_vector); 821 break; 822 case e1000_82580: 823 case e1000_i350: 824 case e1000_i354: 825 case e1000_i210: 826 case e1000_i211: 827 /* On 82580 and newer adapters the scheme is similar to 82576 828 * however instead of ordering column-major we have things 829 * ordered row-major. So we traverse the table by using 830 * bit 0 as the column offset, and the remaining bits as the 831 * row index. 832 */ 833 if (rx_queue > IGB_N0_QUEUE) 834 igb_write_ivar(hw, msix_vector, 835 rx_queue >> 1, 836 (rx_queue & 0x1) << 4); 837 if (tx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 tx_queue >> 1, 840 ((tx_queue & 0x1) << 4) + 8); 841 q_vector->eims_value = BIT(msix_vector); 842 break; 843 default: 844 BUG(); 845 break; 846 } 847 848 /* add q_vector eims value to global eims_enable_mask */ 849 adapter->eims_enable_mask |= q_vector->eims_value; 850 851 /* configure q_vector to set itr on first interrupt */ 852 q_vector->set_itr = 1; 853 } 854 855 /** 856 * igb_configure_msix - Configure MSI-X hardware 857 * @adapter: board private structure to initialize 858 * 859 * igb_configure_msix sets up the hardware to properly 860 * generate MSI-X interrupts. 861 **/ 862 static void igb_configure_msix(struct igb_adapter *adapter) 863 { 864 u32 tmp; 865 int i, vector = 0; 866 struct e1000_hw *hw = &adapter->hw; 867 868 adapter->eims_enable_mask = 0; 869 870 /* set vector for other causes, i.e. link changes */ 871 switch (hw->mac.type) { 872 case e1000_82575: 873 tmp = rd32(E1000_CTRL_EXT); 874 /* enable MSI-X PBA support*/ 875 tmp |= E1000_CTRL_EXT_PBA_CLR; 876 877 /* Auto-Mask interrupts upon ICR read. */ 878 tmp |= E1000_CTRL_EXT_EIAME; 879 tmp |= E1000_CTRL_EXT_IRCA; 880 881 wr32(E1000_CTRL_EXT, tmp); 882 883 /* enable msix_other interrupt */ 884 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 885 adapter->eims_other = E1000_EIMS_OTHER; 886 887 break; 888 889 case e1000_82576: 890 case e1000_82580: 891 case e1000_i350: 892 case e1000_i354: 893 case e1000_i210: 894 case e1000_i211: 895 /* Turn on MSI-X capability first, or our settings 896 * won't stick. And it will take days to debug. 897 */ 898 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 899 E1000_GPIE_PBA | E1000_GPIE_EIAME | 900 E1000_GPIE_NSICR); 901 902 /* enable msix_other interrupt */ 903 adapter->eims_other = BIT(vector); 904 tmp = (vector++ | E1000_IVAR_VALID) << 8; 905 906 wr32(E1000_IVAR_MISC, tmp); 907 break; 908 default: 909 /* do nothing, since nothing else supports MSI-X */ 910 break; 911 } /* switch (hw->mac.type) */ 912 913 adapter->eims_enable_mask |= adapter->eims_other; 914 915 for (i = 0; i < adapter->num_q_vectors; i++) 916 igb_assign_vector(adapter->q_vector[i], vector++); 917 918 wrfl(); 919 } 920 921 /** 922 * igb_request_msix - Initialize MSI-X interrupts 923 * @adapter: board private structure to initialize 924 * 925 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 926 * kernel. 927 **/ 928 static int igb_request_msix(struct igb_adapter *adapter) 929 { 930 unsigned int num_q_vectors = adapter->num_q_vectors; 931 struct net_device *netdev = adapter->netdev; 932 int i, err = 0, vector = 0, free_vector = 0; 933 934 err = request_irq(adapter->msix_entries[vector].vector, 935 igb_msix_other, 0, netdev->name, adapter); 936 if (err) 937 goto err_out; 938 939 if (num_q_vectors > MAX_Q_VECTORS) { 940 num_q_vectors = MAX_Q_VECTORS; 941 dev_warn(&adapter->pdev->dev, 942 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 943 adapter->num_q_vectors, MAX_Q_VECTORS); 944 } 945 for (i = 0; i < num_q_vectors; i++) { 946 struct igb_q_vector *q_vector = adapter->q_vector[i]; 947 948 vector++; 949 950 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 951 952 if (q_vector->rx.ring && q_vector->tx.ring) 953 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 954 q_vector->rx.ring->queue_index); 955 else if (q_vector->tx.ring) 956 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 957 q_vector->tx.ring->queue_index); 958 else if (q_vector->rx.ring) 959 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 960 q_vector->rx.ring->queue_index); 961 else 962 sprintf(q_vector->name, "%s-unused", netdev->name); 963 964 err = request_irq(adapter->msix_entries[vector].vector, 965 igb_msix_ring, 0, q_vector->name, 966 q_vector); 967 if (err) 968 goto err_free; 969 } 970 971 igb_configure_msix(adapter); 972 return 0; 973 974 err_free: 975 /* free already assigned IRQs */ 976 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 977 978 vector--; 979 for (i = 0; i < vector; i++) { 980 free_irq(adapter->msix_entries[free_vector++].vector, 981 adapter->q_vector[i]); 982 } 983 err_out: 984 return err; 985 } 986 987 /** 988 * igb_free_q_vector - Free memory allocated for specific interrupt vector 989 * @adapter: board private structure to initialize 990 * @v_idx: Index of vector to be freed 991 * 992 * This function frees the memory allocated to the q_vector. 993 **/ 994 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 995 { 996 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 997 998 adapter->q_vector[v_idx] = NULL; 999 1000 /* igb_get_stats64() might access the rings on this vector, 1001 * we must wait a grace period before freeing it. 1002 */ 1003 if (q_vector) 1004 kfree_rcu(q_vector, rcu); 1005 } 1006 1007 /** 1008 * igb_reset_q_vector - Reset config for interrupt vector 1009 * @adapter: board private structure to initialize 1010 * @v_idx: Index of vector to be reset 1011 * 1012 * If NAPI is enabled it will delete any references to the 1013 * NAPI struct. This is preparation for igb_free_q_vector. 1014 **/ 1015 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1016 { 1017 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1018 1019 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1020 * allocated. So, q_vector is NULL so we should stop here. 1021 */ 1022 if (!q_vector) 1023 return; 1024 1025 if (q_vector->tx.ring) 1026 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1027 1028 if (q_vector->rx.ring) 1029 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1030 1031 netif_napi_del(&q_vector->napi); 1032 1033 } 1034 1035 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1036 { 1037 int v_idx = adapter->num_q_vectors; 1038 1039 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1040 pci_disable_msix(adapter->pdev); 1041 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1042 pci_disable_msi(adapter->pdev); 1043 1044 while (v_idx--) 1045 igb_reset_q_vector(adapter, v_idx); 1046 } 1047 1048 /** 1049 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1050 * @adapter: board private structure to initialize 1051 * 1052 * This function frees the memory allocated to the q_vectors. In addition if 1053 * NAPI is enabled it will delete any references to the NAPI struct prior 1054 * to freeing the q_vector. 1055 **/ 1056 static void igb_free_q_vectors(struct igb_adapter *adapter) 1057 { 1058 int v_idx = adapter->num_q_vectors; 1059 1060 adapter->num_tx_queues = 0; 1061 adapter->num_rx_queues = 0; 1062 adapter->num_q_vectors = 0; 1063 1064 while (v_idx--) { 1065 igb_reset_q_vector(adapter, v_idx); 1066 igb_free_q_vector(adapter, v_idx); 1067 } 1068 } 1069 1070 /** 1071 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1072 * @adapter: board private structure to initialize 1073 * 1074 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1075 * MSI-X interrupts allocated. 1076 */ 1077 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1078 { 1079 igb_free_q_vectors(adapter); 1080 igb_reset_interrupt_capability(adapter); 1081 } 1082 1083 /** 1084 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1085 * @adapter: board private structure to initialize 1086 * @msix: boolean value of MSIX capability 1087 * 1088 * Attempt to configure interrupts using the best available 1089 * capabilities of the hardware and kernel. 1090 **/ 1091 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1092 { 1093 int err; 1094 int numvecs, i; 1095 1096 if (!msix) 1097 goto msi_only; 1098 adapter->flags |= IGB_FLAG_HAS_MSIX; 1099 1100 /* Number of supported queues. */ 1101 adapter->num_rx_queues = adapter->rss_queues; 1102 if (adapter->vfs_allocated_count) 1103 adapter->num_tx_queues = 1; 1104 else 1105 adapter->num_tx_queues = adapter->rss_queues; 1106 1107 /* start with one vector for every Rx queue */ 1108 numvecs = adapter->num_rx_queues; 1109 1110 /* if Tx handler is separate add 1 for every Tx queue */ 1111 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1112 numvecs += adapter->num_tx_queues; 1113 1114 /* store the number of vectors reserved for queues */ 1115 adapter->num_q_vectors = numvecs; 1116 1117 /* add 1 vector for link status interrupts */ 1118 numvecs++; 1119 for (i = 0; i < numvecs; i++) 1120 adapter->msix_entries[i].entry = i; 1121 1122 err = pci_enable_msix_range(adapter->pdev, 1123 adapter->msix_entries, 1124 numvecs, 1125 numvecs); 1126 if (err > 0) 1127 return; 1128 1129 igb_reset_interrupt_capability(adapter); 1130 1131 /* If we can't do MSI-X, try MSI */ 1132 msi_only: 1133 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1134 #ifdef CONFIG_PCI_IOV 1135 /* disable SR-IOV for non MSI-X configurations */ 1136 if (adapter->vf_data) { 1137 struct e1000_hw *hw = &adapter->hw; 1138 /* disable iov and allow time for transactions to clear */ 1139 pci_disable_sriov(adapter->pdev); 1140 msleep(500); 1141 1142 kfree(adapter->vf_mac_list); 1143 adapter->vf_mac_list = NULL; 1144 kfree(adapter->vf_data); 1145 adapter->vf_data = NULL; 1146 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1147 wrfl(); 1148 msleep(100); 1149 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1150 } 1151 #endif 1152 adapter->vfs_allocated_count = 0; 1153 adapter->rss_queues = 1; 1154 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1155 adapter->num_rx_queues = 1; 1156 adapter->num_tx_queues = 1; 1157 adapter->num_q_vectors = 1; 1158 if (!pci_enable_msi(adapter->pdev)) 1159 adapter->flags |= IGB_FLAG_HAS_MSI; 1160 } 1161 1162 static void igb_add_ring(struct igb_ring *ring, 1163 struct igb_ring_container *head) 1164 { 1165 head->ring = ring; 1166 head->count++; 1167 } 1168 1169 /** 1170 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1171 * @adapter: board private structure to initialize 1172 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1173 * @v_idx: index of vector in adapter struct 1174 * @txr_count: total number of Tx rings to allocate 1175 * @txr_idx: index of first Tx ring to allocate 1176 * @rxr_count: total number of Rx rings to allocate 1177 * @rxr_idx: index of first Rx ring to allocate 1178 * 1179 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1180 **/ 1181 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1182 int v_count, int v_idx, 1183 int txr_count, int txr_idx, 1184 int rxr_count, int rxr_idx) 1185 { 1186 struct igb_q_vector *q_vector; 1187 struct igb_ring *ring; 1188 int ring_count; 1189 size_t size; 1190 1191 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1192 if (txr_count > 1 || rxr_count > 1) 1193 return -ENOMEM; 1194 1195 ring_count = txr_count + rxr_count; 1196 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1197 1198 /* allocate q_vector and rings */ 1199 q_vector = adapter->q_vector[v_idx]; 1200 if (!q_vector) { 1201 q_vector = kzalloc(size, GFP_KERNEL); 1202 } else if (size > ksize(q_vector)) { 1203 struct igb_q_vector *new_q_vector; 1204 1205 new_q_vector = kzalloc(size, GFP_KERNEL); 1206 if (new_q_vector) 1207 kfree_rcu(q_vector, rcu); 1208 q_vector = new_q_vector; 1209 } else { 1210 memset(q_vector, 0, size); 1211 } 1212 if (!q_vector) 1213 return -ENOMEM; 1214 1215 /* initialize NAPI */ 1216 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1217 1218 /* tie q_vector and adapter together */ 1219 adapter->q_vector[v_idx] = q_vector; 1220 q_vector->adapter = adapter; 1221 1222 /* initialize work limits */ 1223 q_vector->tx.work_limit = adapter->tx_work_limit; 1224 1225 /* initialize ITR configuration */ 1226 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1227 q_vector->itr_val = IGB_START_ITR; 1228 1229 /* initialize pointer to rings */ 1230 ring = q_vector->ring; 1231 1232 /* intialize ITR */ 1233 if (rxr_count) { 1234 /* rx or rx/tx vector */ 1235 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1236 q_vector->itr_val = adapter->rx_itr_setting; 1237 } else { 1238 /* tx only vector */ 1239 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1240 q_vector->itr_val = adapter->tx_itr_setting; 1241 } 1242 1243 if (txr_count) { 1244 /* assign generic ring traits */ 1245 ring->dev = &adapter->pdev->dev; 1246 ring->netdev = adapter->netdev; 1247 1248 /* configure backlink on ring */ 1249 ring->q_vector = q_vector; 1250 1251 /* update q_vector Tx values */ 1252 igb_add_ring(ring, &q_vector->tx); 1253 1254 /* For 82575, context index must be unique per ring. */ 1255 if (adapter->hw.mac.type == e1000_82575) 1256 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1257 1258 /* apply Tx specific ring traits */ 1259 ring->count = adapter->tx_ring_count; 1260 ring->queue_index = txr_idx; 1261 1262 ring->cbs_enable = false; 1263 ring->idleslope = 0; 1264 ring->sendslope = 0; 1265 ring->hicredit = 0; 1266 ring->locredit = 0; 1267 1268 u64_stats_init(&ring->tx_syncp); 1269 u64_stats_init(&ring->tx_syncp2); 1270 1271 /* assign ring to adapter */ 1272 adapter->tx_ring[txr_idx] = ring; 1273 1274 /* push pointer to next ring */ 1275 ring++; 1276 } 1277 1278 if (rxr_count) { 1279 /* assign generic ring traits */ 1280 ring->dev = &adapter->pdev->dev; 1281 ring->netdev = adapter->netdev; 1282 1283 /* configure backlink on ring */ 1284 ring->q_vector = q_vector; 1285 1286 /* update q_vector Rx values */ 1287 igb_add_ring(ring, &q_vector->rx); 1288 1289 /* set flag indicating ring supports SCTP checksum offload */ 1290 if (adapter->hw.mac.type >= e1000_82576) 1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1292 1293 /* On i350, i354, i210, and i211, loopback VLAN packets 1294 * have the tag byte-swapped. 1295 */ 1296 if (adapter->hw.mac.type >= e1000_i350) 1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1298 1299 /* apply Rx specific ring traits */ 1300 ring->count = adapter->rx_ring_count; 1301 ring->queue_index = rxr_idx; 1302 1303 u64_stats_init(&ring->rx_syncp); 1304 1305 /* assign ring to adapter */ 1306 adapter->rx_ring[rxr_idx] = ring; 1307 } 1308 1309 return 0; 1310 } 1311 1312 1313 /** 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1315 * @adapter: board private structure to initialize 1316 * 1317 * We allocate one q_vector per queue interrupt. If allocation fails we 1318 * return -ENOMEM. 1319 **/ 1320 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1321 { 1322 int q_vectors = adapter->num_q_vectors; 1323 int rxr_remaining = adapter->num_rx_queues; 1324 int txr_remaining = adapter->num_tx_queues; 1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1326 int err; 1327 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1329 for (; rxr_remaining; v_idx++) { 1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1331 0, 0, 1, rxr_idx); 1332 1333 if (err) 1334 goto err_out; 1335 1336 /* update counts and index */ 1337 rxr_remaining--; 1338 rxr_idx++; 1339 } 1340 } 1341 1342 for (; v_idx < q_vectors; v_idx++) { 1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1345 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1347 tqpv, txr_idx, rqpv, rxr_idx); 1348 1349 if (err) 1350 goto err_out; 1351 1352 /* update counts and index */ 1353 rxr_remaining -= rqpv; 1354 txr_remaining -= tqpv; 1355 rxr_idx++; 1356 txr_idx++; 1357 } 1358 1359 return 0; 1360 1361 err_out: 1362 adapter->num_tx_queues = 0; 1363 adapter->num_rx_queues = 0; 1364 adapter->num_q_vectors = 0; 1365 1366 while (v_idx--) 1367 igb_free_q_vector(adapter, v_idx); 1368 1369 return -ENOMEM; 1370 } 1371 1372 /** 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1374 * @adapter: board private structure to initialize 1375 * @msix: boolean value of MSIX capability 1376 * 1377 * This function initializes the interrupts and allocates all of the queues. 1378 **/ 1379 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1380 { 1381 struct pci_dev *pdev = adapter->pdev; 1382 int err; 1383 1384 igb_set_interrupt_capability(adapter, msix); 1385 1386 err = igb_alloc_q_vectors(adapter); 1387 if (err) { 1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1389 goto err_alloc_q_vectors; 1390 } 1391 1392 igb_cache_ring_register(adapter); 1393 1394 return 0; 1395 1396 err_alloc_q_vectors: 1397 igb_reset_interrupt_capability(adapter); 1398 return err; 1399 } 1400 1401 /** 1402 * igb_request_irq - initialize interrupts 1403 * @adapter: board private structure to initialize 1404 * 1405 * Attempts to configure interrupts using the best available 1406 * capabilities of the hardware and kernel. 1407 **/ 1408 static int igb_request_irq(struct igb_adapter *adapter) 1409 { 1410 struct net_device *netdev = adapter->netdev; 1411 struct pci_dev *pdev = adapter->pdev; 1412 int err = 0; 1413 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1415 err = igb_request_msix(adapter); 1416 if (!err) 1417 goto request_done; 1418 /* fall back to MSI */ 1419 igb_free_all_tx_resources(adapter); 1420 igb_free_all_rx_resources(adapter); 1421 1422 igb_clear_interrupt_scheme(adapter); 1423 err = igb_init_interrupt_scheme(adapter, false); 1424 if (err) 1425 goto request_done; 1426 1427 igb_setup_all_tx_resources(adapter); 1428 igb_setup_all_rx_resources(adapter); 1429 igb_configure(adapter); 1430 } 1431 1432 igb_assign_vector(adapter->q_vector[0], 0); 1433 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1435 err = request_irq(pdev->irq, igb_intr_msi, 0, 1436 netdev->name, adapter); 1437 if (!err) 1438 goto request_done; 1439 1440 /* fall back to legacy interrupts */ 1441 igb_reset_interrupt_capability(adapter); 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1443 } 1444 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1446 netdev->name, adapter); 1447 1448 if (err) 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1450 err); 1451 1452 request_done: 1453 return err; 1454 } 1455 1456 static void igb_free_irq(struct igb_adapter *adapter) 1457 { 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1459 int vector = 0, i; 1460 1461 free_irq(adapter->msix_entries[vector++].vector, adapter); 1462 1463 for (i = 0; i < adapter->num_q_vectors; i++) 1464 free_irq(adapter->msix_entries[vector++].vector, 1465 adapter->q_vector[i]); 1466 } else { 1467 free_irq(adapter->pdev->irq, adapter); 1468 } 1469 } 1470 1471 /** 1472 * igb_irq_disable - Mask off interrupt generation on the NIC 1473 * @adapter: board private structure 1474 **/ 1475 static void igb_irq_disable(struct igb_adapter *adapter) 1476 { 1477 struct e1000_hw *hw = &adapter->hw; 1478 1479 /* we need to be careful when disabling interrupts. The VFs are also 1480 * mapped into these registers and so clearing the bits can cause 1481 * issues on the VF drivers so we only need to clear what we set 1482 */ 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1484 u32 regval = rd32(E1000_EIAM); 1485 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1487 wr32(E1000_EIMC, adapter->eims_enable_mask); 1488 regval = rd32(E1000_EIAC); 1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1490 } 1491 1492 wr32(E1000_IAM, 0); 1493 wr32(E1000_IMC, ~0); 1494 wrfl(); 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1496 int i; 1497 1498 for (i = 0; i < adapter->num_q_vectors; i++) 1499 synchronize_irq(adapter->msix_entries[i].vector); 1500 } else { 1501 synchronize_irq(adapter->pdev->irq); 1502 } 1503 } 1504 1505 /** 1506 * igb_irq_enable - Enable default interrupt generation settings 1507 * @adapter: board private structure 1508 **/ 1509 static void igb_irq_enable(struct igb_adapter *adapter) 1510 { 1511 struct e1000_hw *hw = &adapter->hw; 1512 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1515 u32 regval = rd32(E1000_EIAC); 1516 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1518 regval = rd32(E1000_EIAM); 1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1520 wr32(E1000_EIMS, adapter->eims_enable_mask); 1521 if (adapter->vfs_allocated_count) { 1522 wr32(E1000_MBVFIMR, 0xFF); 1523 ims |= E1000_IMS_VMMB; 1524 } 1525 wr32(E1000_IMS, ims); 1526 } else { 1527 wr32(E1000_IMS, IMS_ENABLE_MASK | 1528 E1000_IMS_DRSTA); 1529 wr32(E1000_IAM, IMS_ENABLE_MASK | 1530 E1000_IMS_DRSTA); 1531 } 1532 } 1533 1534 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1535 { 1536 struct e1000_hw *hw = &adapter->hw; 1537 u16 pf_id = adapter->vfs_allocated_count; 1538 u16 vid = adapter->hw.mng_cookie.vlan_id; 1539 u16 old_vid = adapter->mng_vlan_id; 1540 1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1542 /* add VID to filter table */ 1543 igb_vfta_set(hw, vid, pf_id, true, true); 1544 adapter->mng_vlan_id = vid; 1545 } else { 1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1547 } 1548 1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1550 (vid != old_vid) && 1551 !test_bit(old_vid, adapter->active_vlans)) { 1552 /* remove VID from filter table */ 1553 igb_vfta_set(hw, vid, pf_id, false, true); 1554 } 1555 } 1556 1557 /** 1558 * igb_release_hw_control - release control of the h/w to f/w 1559 * @adapter: address of board private structure 1560 * 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1562 * For ASF and Pass Through versions of f/w this means that the 1563 * driver is no longer loaded. 1564 **/ 1565 static void igb_release_hw_control(struct igb_adapter *adapter) 1566 { 1567 struct e1000_hw *hw = &adapter->hw; 1568 u32 ctrl_ext; 1569 1570 /* Let firmware take over control of h/w */ 1571 ctrl_ext = rd32(E1000_CTRL_EXT); 1572 wr32(E1000_CTRL_EXT, 1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1574 } 1575 1576 /** 1577 * igb_get_hw_control - get control of the h/w from f/w 1578 * @adapter: address of board private structure 1579 * 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1581 * For ASF and Pass Through versions of f/w this means that 1582 * the driver is loaded. 1583 **/ 1584 static void igb_get_hw_control(struct igb_adapter *adapter) 1585 { 1586 struct e1000_hw *hw = &adapter->hw; 1587 u32 ctrl_ext; 1588 1589 /* Let firmware know the driver has taken over */ 1590 ctrl_ext = rd32(E1000_CTRL_EXT); 1591 wr32(E1000_CTRL_EXT, 1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1593 } 1594 1595 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1596 { 1597 struct net_device *netdev = adapter->netdev; 1598 struct e1000_hw *hw = &adapter->hw; 1599 1600 WARN_ON(hw->mac.type != e1000_i210); 1601 1602 if (enable) 1603 adapter->flags |= IGB_FLAG_FQTSS; 1604 else 1605 adapter->flags &= ~IGB_FLAG_FQTSS; 1606 1607 if (netif_running(netdev)) 1608 schedule_work(&adapter->reset_task); 1609 } 1610 1611 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1612 { 1613 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1614 } 1615 1616 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1617 enum tx_queue_prio prio) 1618 { 1619 u32 val; 1620 1621 WARN_ON(hw->mac.type != e1000_i210); 1622 WARN_ON(queue < 0 || queue > 4); 1623 1624 val = rd32(E1000_I210_TXDCTL(queue)); 1625 1626 if (prio == TX_QUEUE_PRIO_HIGH) 1627 val |= E1000_TXDCTL_PRIORITY; 1628 else 1629 val &= ~E1000_TXDCTL_PRIORITY; 1630 1631 wr32(E1000_I210_TXDCTL(queue), val); 1632 } 1633 1634 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1635 { 1636 u32 val; 1637 1638 WARN_ON(hw->mac.type != e1000_i210); 1639 WARN_ON(queue < 0 || queue > 1); 1640 1641 val = rd32(E1000_I210_TQAVCC(queue)); 1642 1643 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1644 val |= E1000_TQAVCC_QUEUEMODE; 1645 else 1646 val &= ~E1000_TQAVCC_QUEUEMODE; 1647 1648 wr32(E1000_I210_TQAVCC(queue), val); 1649 } 1650 1651 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1652 { 1653 int i; 1654 1655 for (i = 0; i < adapter->num_tx_queues; i++) { 1656 if (adapter->tx_ring[i]->cbs_enable) 1657 return true; 1658 } 1659 1660 return false; 1661 } 1662 1663 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1664 { 1665 int i; 1666 1667 for (i = 0; i < adapter->num_tx_queues; i++) { 1668 if (adapter->tx_ring[i]->launchtime_enable) 1669 return true; 1670 } 1671 1672 return false; 1673 } 1674 1675 /** 1676 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1677 * @adapter: pointer to adapter struct 1678 * @queue: queue number 1679 * 1680 * Configure CBS and Launchtime for a given hardware queue. 1681 * Parameters are retrieved from the correct Tx ring, so 1682 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1683 * for setting those correctly prior to this function being called. 1684 **/ 1685 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1686 { 1687 struct net_device *netdev = adapter->netdev; 1688 struct e1000_hw *hw = &adapter->hw; 1689 struct igb_ring *ring; 1690 u32 tqavcc, tqavctrl; 1691 u16 value; 1692 1693 WARN_ON(hw->mac.type != e1000_i210); 1694 WARN_ON(queue < 0 || queue > 1); 1695 ring = adapter->tx_ring[queue]; 1696 1697 /* If any of the Qav features is enabled, configure queues as SR and 1698 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1699 * as SP. 1700 */ 1701 if (ring->cbs_enable || ring->launchtime_enable) { 1702 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1703 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1704 } else { 1705 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1706 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1707 } 1708 1709 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1710 if (ring->cbs_enable || queue == 0) { 1711 /* i210 does not allow the queue 0 to be in the Strict 1712 * Priority mode while the Qav mode is enabled, so, 1713 * instead of disabling strict priority mode, we give 1714 * queue 0 the maximum of credits possible. 1715 * 1716 * See section 8.12.19 of the i210 datasheet, "Note: 1717 * Queue0 QueueMode must be set to 1b when 1718 * TransmitMode is set to Qav." 1719 */ 1720 if (queue == 0 && !ring->cbs_enable) { 1721 /* max "linkspeed" idleslope in kbps */ 1722 ring->idleslope = 1000000; 1723 ring->hicredit = ETH_FRAME_LEN; 1724 } 1725 1726 /* Always set data transfer arbitration to credit-based 1727 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1728 * the queues. 1729 */ 1730 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1731 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1732 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1733 1734 /* According to i210 datasheet section 7.2.7.7, we should set 1735 * the 'idleSlope' field from TQAVCC register following the 1736 * equation: 1737 * 1738 * For 100 Mbps link speed: 1739 * 1740 * value = BW * 0x7735 * 0.2 (E1) 1741 * 1742 * For 1000Mbps link speed: 1743 * 1744 * value = BW * 0x7735 * 2 (E2) 1745 * 1746 * E1 and E2 can be merged into one equation as shown below. 1747 * Note that 'link-speed' is in Mbps. 1748 * 1749 * value = BW * 0x7735 * 2 * link-speed 1750 * -------------- (E3) 1751 * 1000 1752 * 1753 * 'BW' is the percentage bandwidth out of full link speed 1754 * which can be found with the following equation. Note that 1755 * idleSlope here is the parameter from this function which 1756 * is in kbps. 1757 * 1758 * BW = idleSlope 1759 * ----------------- (E4) 1760 * link-speed * 1000 1761 * 1762 * That said, we can come up with a generic equation to 1763 * calculate the value we should set it TQAVCC register by 1764 * replacing 'BW' in E3 by E4. The resulting equation is: 1765 * 1766 * value = idleSlope * 0x7735 * 2 * link-speed 1767 * ----------------- -------------- (E5) 1768 * link-speed * 1000 1000 1769 * 1770 * 'link-speed' is present in both sides of the fraction so 1771 * it is canceled out. The final equation is the following: 1772 * 1773 * value = idleSlope * 61034 1774 * ----------------- (E6) 1775 * 1000000 1776 * 1777 * NOTE: For i210, given the above, we can see that idleslope 1778 * is represented in 16.38431 kbps units by the value at 1779 * the TQAVCC register (1Gbps / 61034), which reduces 1780 * the granularity for idleslope increments. 1781 * For instance, if you want to configure a 2576kbps 1782 * idleslope, the value to be written on the register 1783 * would have to be 157.23. If rounded down, you end 1784 * up with less bandwidth available than originally 1785 * required (~2572 kbps). If rounded up, you end up 1786 * with a higher bandwidth (~2589 kbps). Below the 1787 * approach we take is to always round up the 1788 * calculated value, so the resulting bandwidth might 1789 * be slightly higher for some configurations. 1790 */ 1791 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1792 1793 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1794 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1795 tqavcc |= value; 1796 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1797 1798 wr32(E1000_I210_TQAVHC(queue), 1799 0x80000000 + ring->hicredit * 0x7735); 1800 } else { 1801 1802 /* Set idleSlope to zero. */ 1803 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1804 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1805 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1806 1807 /* Set hiCredit to zero. */ 1808 wr32(E1000_I210_TQAVHC(queue), 0); 1809 1810 /* If CBS is not enabled for any queues anymore, then return to 1811 * the default state of Data Transmission Arbitration on 1812 * TQAVCTRL. 1813 */ 1814 if (!is_any_cbs_enabled(adapter)) { 1815 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1816 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1817 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1818 } 1819 } 1820 1821 /* If LaunchTime is enabled, set DataTranTIM. */ 1822 if (ring->launchtime_enable) { 1823 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1824 * for any of the SR queues, and configure fetchtime delta. 1825 * XXX NOTE: 1826 * - LaunchTime will be enabled for all SR queues. 1827 * - A fixed offset can be added relative to the launch 1828 * time of all packets if configured at reg LAUNCH_OS0. 1829 * We are keeping it as 0 for now (default value). 1830 */ 1831 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1832 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1833 E1000_TQAVCTRL_FETCHTIME_DELTA; 1834 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1835 } else { 1836 /* If Launchtime is not enabled for any SR queues anymore, 1837 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1838 * effectively disabling Launchtime. 1839 */ 1840 if (!is_any_txtime_enabled(adapter)) { 1841 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1842 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1843 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1844 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1845 } 1846 } 1847 1848 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1849 * CBS are not configurable by software so we don't do any 'controller 1850 * configuration' in respect to these parameters. 1851 */ 1852 1853 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1854 ring->cbs_enable ? "enabled" : "disabled", 1855 ring->launchtime_enable ? "enabled" : "disabled", 1856 queue, 1857 ring->idleslope, ring->sendslope, 1858 ring->hicredit, ring->locredit); 1859 } 1860 1861 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1862 bool enable) 1863 { 1864 struct igb_ring *ring; 1865 1866 if (queue < 0 || queue > adapter->num_tx_queues) 1867 return -EINVAL; 1868 1869 ring = adapter->tx_ring[queue]; 1870 ring->launchtime_enable = enable; 1871 1872 return 0; 1873 } 1874 1875 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1876 bool enable, int idleslope, int sendslope, 1877 int hicredit, int locredit) 1878 { 1879 struct igb_ring *ring; 1880 1881 if (queue < 0 || queue > adapter->num_tx_queues) 1882 return -EINVAL; 1883 1884 ring = adapter->tx_ring[queue]; 1885 1886 ring->cbs_enable = enable; 1887 ring->idleslope = idleslope; 1888 ring->sendslope = sendslope; 1889 ring->hicredit = hicredit; 1890 ring->locredit = locredit; 1891 1892 return 0; 1893 } 1894 1895 /** 1896 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1897 * @adapter: pointer to adapter struct 1898 * 1899 * Configure TQAVCTRL register switching the controller's Tx mode 1900 * if FQTSS mode is enabled or disabled. Additionally, will issue 1901 * a call to igb_config_tx_modes() per queue so any previously saved 1902 * Tx parameters are applied. 1903 **/ 1904 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1905 { 1906 struct net_device *netdev = adapter->netdev; 1907 struct e1000_hw *hw = &adapter->hw; 1908 u32 val; 1909 1910 /* Only i210 controller supports changing the transmission mode. */ 1911 if (hw->mac.type != e1000_i210) 1912 return; 1913 1914 if (is_fqtss_enabled(adapter)) { 1915 int i, max_queue; 1916 1917 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1918 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1919 * so SP queues wait for SR ones. 1920 */ 1921 val = rd32(E1000_I210_TQAVCTRL); 1922 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1923 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1924 wr32(E1000_I210_TQAVCTRL, val); 1925 1926 /* Configure Tx and Rx packet buffers sizes as described in 1927 * i210 datasheet section 7.2.7.7. 1928 */ 1929 val = rd32(E1000_TXPBS); 1930 val &= ~I210_TXPBSIZE_MASK; 1931 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1932 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1933 wr32(E1000_TXPBS, val); 1934 1935 val = rd32(E1000_RXPBS); 1936 val &= ~I210_RXPBSIZE_MASK; 1937 val |= I210_RXPBSIZE_PB_30KB; 1938 wr32(E1000_RXPBS, val); 1939 1940 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1941 * register should not exceed the buffer size programmed in 1942 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1943 * so according to the datasheet we should set MAX_TPKT_SIZE to 1944 * 4kB / 64. 1945 * 1946 * However, when we do so, no frame from queue 2 and 3 are 1947 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1948 * or _equal_ to the buffer size programmed in TXPBS. For this 1949 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1950 */ 1951 val = (4096 - 1) / 64; 1952 wr32(E1000_I210_DTXMXPKTSZ, val); 1953 1954 /* Since FQTSS mode is enabled, apply any CBS configuration 1955 * previously set. If no previous CBS configuration has been 1956 * done, then the initial configuration is applied, which means 1957 * CBS is disabled. 1958 */ 1959 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1960 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1961 1962 for (i = 0; i < max_queue; i++) { 1963 igb_config_tx_modes(adapter, i); 1964 } 1965 } else { 1966 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1967 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1968 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1969 1970 val = rd32(E1000_I210_TQAVCTRL); 1971 /* According to Section 8.12.21, the other flags we've set when 1972 * enabling FQTSS are not relevant when disabling FQTSS so we 1973 * don't set they here. 1974 */ 1975 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1976 wr32(E1000_I210_TQAVCTRL, val); 1977 } 1978 1979 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1980 "enabled" : "disabled"); 1981 } 1982 1983 /** 1984 * igb_configure - configure the hardware for RX and TX 1985 * @adapter: private board structure 1986 **/ 1987 static void igb_configure(struct igb_adapter *adapter) 1988 { 1989 struct net_device *netdev = adapter->netdev; 1990 int i; 1991 1992 igb_get_hw_control(adapter); 1993 igb_set_rx_mode(netdev); 1994 igb_setup_tx_mode(adapter); 1995 1996 igb_restore_vlan(adapter); 1997 1998 igb_setup_tctl(adapter); 1999 igb_setup_mrqc(adapter); 2000 igb_setup_rctl(adapter); 2001 2002 igb_nfc_filter_restore(adapter); 2003 igb_configure_tx(adapter); 2004 igb_configure_rx(adapter); 2005 2006 igb_rx_fifo_flush_82575(&adapter->hw); 2007 2008 /* call igb_desc_unused which always leaves 2009 * at least 1 descriptor unused to make sure 2010 * next_to_use != next_to_clean 2011 */ 2012 for (i = 0; i < adapter->num_rx_queues; i++) { 2013 struct igb_ring *ring = adapter->rx_ring[i]; 2014 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2015 } 2016 } 2017 2018 /** 2019 * igb_power_up_link - Power up the phy/serdes link 2020 * @adapter: address of board private structure 2021 **/ 2022 void igb_power_up_link(struct igb_adapter *adapter) 2023 { 2024 igb_reset_phy(&adapter->hw); 2025 2026 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2027 igb_power_up_phy_copper(&adapter->hw); 2028 else 2029 igb_power_up_serdes_link_82575(&adapter->hw); 2030 2031 igb_setup_link(&adapter->hw); 2032 } 2033 2034 /** 2035 * igb_power_down_link - Power down the phy/serdes link 2036 * @adapter: address of board private structure 2037 */ 2038 static void igb_power_down_link(struct igb_adapter *adapter) 2039 { 2040 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2041 igb_power_down_phy_copper_82575(&adapter->hw); 2042 else 2043 igb_shutdown_serdes_link_82575(&adapter->hw); 2044 } 2045 2046 /** 2047 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2048 * @adapter: address of the board private structure 2049 **/ 2050 static void igb_check_swap_media(struct igb_adapter *adapter) 2051 { 2052 struct e1000_hw *hw = &adapter->hw; 2053 u32 ctrl_ext, connsw; 2054 bool swap_now = false; 2055 2056 ctrl_ext = rd32(E1000_CTRL_EXT); 2057 connsw = rd32(E1000_CONNSW); 2058 2059 /* need to live swap if current media is copper and we have fiber/serdes 2060 * to go to. 2061 */ 2062 2063 if ((hw->phy.media_type == e1000_media_type_copper) && 2064 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2065 swap_now = true; 2066 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2067 !(connsw & E1000_CONNSW_SERDESD)) { 2068 /* copper signal takes time to appear */ 2069 if (adapter->copper_tries < 4) { 2070 adapter->copper_tries++; 2071 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2072 wr32(E1000_CONNSW, connsw); 2073 return; 2074 } else { 2075 adapter->copper_tries = 0; 2076 if ((connsw & E1000_CONNSW_PHYSD) && 2077 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2078 swap_now = true; 2079 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2080 wr32(E1000_CONNSW, connsw); 2081 } 2082 } 2083 } 2084 2085 if (!swap_now) 2086 return; 2087 2088 switch (hw->phy.media_type) { 2089 case e1000_media_type_copper: 2090 netdev_info(adapter->netdev, 2091 "MAS: changing media to fiber/serdes\n"); 2092 ctrl_ext |= 2093 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2094 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2095 adapter->copper_tries = 0; 2096 break; 2097 case e1000_media_type_internal_serdes: 2098 case e1000_media_type_fiber: 2099 netdev_info(adapter->netdev, 2100 "MAS: changing media to copper\n"); 2101 ctrl_ext &= 2102 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2103 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2104 break; 2105 default: 2106 /* shouldn't get here during regular operation */ 2107 netdev_err(adapter->netdev, 2108 "AMS: Invalid media type found, returning\n"); 2109 break; 2110 } 2111 wr32(E1000_CTRL_EXT, ctrl_ext); 2112 } 2113 2114 /** 2115 * igb_up - Open the interface and prepare it to handle traffic 2116 * @adapter: board private structure 2117 **/ 2118 int igb_up(struct igb_adapter *adapter) 2119 { 2120 struct e1000_hw *hw = &adapter->hw; 2121 int i; 2122 2123 /* hardware has been reset, we need to reload some things */ 2124 igb_configure(adapter); 2125 2126 clear_bit(__IGB_DOWN, &adapter->state); 2127 2128 for (i = 0; i < adapter->num_q_vectors; i++) 2129 napi_enable(&(adapter->q_vector[i]->napi)); 2130 2131 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2132 igb_configure_msix(adapter); 2133 else 2134 igb_assign_vector(adapter->q_vector[0], 0); 2135 2136 /* Clear any pending interrupts. */ 2137 rd32(E1000_TSICR); 2138 rd32(E1000_ICR); 2139 igb_irq_enable(adapter); 2140 2141 /* notify VFs that reset has been completed */ 2142 if (adapter->vfs_allocated_count) { 2143 u32 reg_data = rd32(E1000_CTRL_EXT); 2144 2145 reg_data |= E1000_CTRL_EXT_PFRSTD; 2146 wr32(E1000_CTRL_EXT, reg_data); 2147 } 2148 2149 netif_tx_start_all_queues(adapter->netdev); 2150 2151 /* start the watchdog. */ 2152 hw->mac.get_link_status = 1; 2153 schedule_work(&adapter->watchdog_task); 2154 2155 if ((adapter->flags & IGB_FLAG_EEE) && 2156 (!hw->dev_spec._82575.eee_disable)) 2157 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2158 2159 return 0; 2160 } 2161 2162 void igb_down(struct igb_adapter *adapter) 2163 { 2164 struct net_device *netdev = adapter->netdev; 2165 struct e1000_hw *hw = &adapter->hw; 2166 u32 tctl, rctl; 2167 int i; 2168 2169 /* signal that we're down so the interrupt handler does not 2170 * reschedule our watchdog timer 2171 */ 2172 set_bit(__IGB_DOWN, &adapter->state); 2173 2174 /* disable receives in the hardware */ 2175 rctl = rd32(E1000_RCTL); 2176 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2177 /* flush and sleep below */ 2178 2179 igb_nfc_filter_exit(adapter); 2180 2181 netif_carrier_off(netdev); 2182 netif_tx_stop_all_queues(netdev); 2183 2184 /* disable transmits in the hardware */ 2185 tctl = rd32(E1000_TCTL); 2186 tctl &= ~E1000_TCTL_EN; 2187 wr32(E1000_TCTL, tctl); 2188 /* flush both disables and wait for them to finish */ 2189 wrfl(); 2190 usleep_range(10000, 11000); 2191 2192 igb_irq_disable(adapter); 2193 2194 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2195 2196 for (i = 0; i < adapter->num_q_vectors; i++) { 2197 if (adapter->q_vector[i]) { 2198 napi_synchronize(&adapter->q_vector[i]->napi); 2199 napi_disable(&adapter->q_vector[i]->napi); 2200 } 2201 } 2202 2203 del_timer_sync(&adapter->watchdog_timer); 2204 del_timer_sync(&adapter->phy_info_timer); 2205 2206 /* record the stats before reset*/ 2207 spin_lock(&adapter->stats64_lock); 2208 igb_update_stats(adapter); 2209 spin_unlock(&adapter->stats64_lock); 2210 2211 adapter->link_speed = 0; 2212 adapter->link_duplex = 0; 2213 2214 if (!pci_channel_offline(adapter->pdev)) 2215 igb_reset(adapter); 2216 2217 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2218 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2219 2220 igb_clean_all_tx_rings(adapter); 2221 igb_clean_all_rx_rings(adapter); 2222 #ifdef CONFIG_IGB_DCA 2223 2224 /* since we reset the hardware DCA settings were cleared */ 2225 igb_setup_dca(adapter); 2226 #endif 2227 } 2228 2229 void igb_reinit_locked(struct igb_adapter *adapter) 2230 { 2231 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2232 usleep_range(1000, 2000); 2233 igb_down(adapter); 2234 igb_up(adapter); 2235 clear_bit(__IGB_RESETTING, &adapter->state); 2236 } 2237 2238 /** igb_enable_mas - Media Autosense re-enable after swap 2239 * 2240 * @adapter: adapter struct 2241 **/ 2242 static void igb_enable_mas(struct igb_adapter *adapter) 2243 { 2244 struct e1000_hw *hw = &adapter->hw; 2245 u32 connsw = rd32(E1000_CONNSW); 2246 2247 /* configure for SerDes media detect */ 2248 if ((hw->phy.media_type == e1000_media_type_copper) && 2249 (!(connsw & E1000_CONNSW_SERDESD))) { 2250 connsw |= E1000_CONNSW_ENRGSRC; 2251 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2252 wr32(E1000_CONNSW, connsw); 2253 wrfl(); 2254 } 2255 } 2256 2257 #ifdef CONFIG_IGB_HWMON 2258 /** 2259 * igb_set_i2c_bb - Init I2C interface 2260 * @hw: pointer to hardware structure 2261 **/ 2262 static void igb_set_i2c_bb(struct e1000_hw *hw) 2263 { 2264 u32 ctrl_ext; 2265 s32 i2cctl; 2266 2267 ctrl_ext = rd32(E1000_CTRL_EXT); 2268 ctrl_ext |= E1000_CTRL_I2C_ENA; 2269 wr32(E1000_CTRL_EXT, ctrl_ext); 2270 wrfl(); 2271 2272 i2cctl = rd32(E1000_I2CPARAMS); 2273 i2cctl |= E1000_I2CBB_EN 2274 | E1000_I2C_CLK_OE_N 2275 | E1000_I2C_DATA_OE_N; 2276 wr32(E1000_I2CPARAMS, i2cctl); 2277 wrfl(); 2278 } 2279 #endif 2280 2281 void igb_reset(struct igb_adapter *adapter) 2282 { 2283 struct pci_dev *pdev = adapter->pdev; 2284 struct e1000_hw *hw = &adapter->hw; 2285 struct e1000_mac_info *mac = &hw->mac; 2286 struct e1000_fc_info *fc = &hw->fc; 2287 u32 pba, hwm; 2288 2289 /* Repartition Pba for greater than 9k mtu 2290 * To take effect CTRL.RST is required. 2291 */ 2292 switch (mac->type) { 2293 case e1000_i350: 2294 case e1000_i354: 2295 case e1000_82580: 2296 pba = rd32(E1000_RXPBS); 2297 pba = igb_rxpbs_adjust_82580(pba); 2298 break; 2299 case e1000_82576: 2300 pba = rd32(E1000_RXPBS); 2301 pba &= E1000_RXPBS_SIZE_MASK_82576; 2302 break; 2303 case e1000_82575: 2304 case e1000_i210: 2305 case e1000_i211: 2306 default: 2307 pba = E1000_PBA_34K; 2308 break; 2309 } 2310 2311 if (mac->type == e1000_82575) { 2312 u32 min_rx_space, min_tx_space, needed_tx_space; 2313 2314 /* write Rx PBA so that hardware can report correct Tx PBA */ 2315 wr32(E1000_PBA, pba); 2316 2317 /* To maintain wire speed transmits, the Tx FIFO should be 2318 * large enough to accommodate two full transmit packets, 2319 * rounded up to the next 1KB and expressed in KB. Likewise, 2320 * the Rx FIFO should be large enough to accommodate at least 2321 * one full receive packet and is similarly rounded up and 2322 * expressed in KB. 2323 */ 2324 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2325 2326 /* The Tx FIFO also stores 16 bytes of information about the Tx 2327 * but don't include Ethernet FCS because hardware appends it. 2328 * We only need to round down to the nearest 512 byte block 2329 * count since the value we care about is 2 frames, not 1. 2330 */ 2331 min_tx_space = adapter->max_frame_size; 2332 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2333 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2334 2335 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2336 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2337 2338 /* If current Tx allocation is less than the min Tx FIFO size, 2339 * and the min Tx FIFO size is less than the current Rx FIFO 2340 * allocation, take space away from current Rx allocation. 2341 */ 2342 if (needed_tx_space < pba) { 2343 pba -= needed_tx_space; 2344 2345 /* if short on Rx space, Rx wins and must trump Tx 2346 * adjustment 2347 */ 2348 if (pba < min_rx_space) 2349 pba = min_rx_space; 2350 } 2351 2352 /* adjust PBA for jumbo frames */ 2353 wr32(E1000_PBA, pba); 2354 } 2355 2356 /* flow control settings 2357 * The high water mark must be low enough to fit one full frame 2358 * after transmitting the pause frame. As such we must have enough 2359 * space to allow for us to complete our current transmit and then 2360 * receive the frame that is in progress from the link partner. 2361 * Set it to: 2362 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2363 */ 2364 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2365 2366 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2367 fc->low_water = fc->high_water - 16; 2368 fc->pause_time = 0xFFFF; 2369 fc->send_xon = 1; 2370 fc->current_mode = fc->requested_mode; 2371 2372 /* disable receive for all VFs and wait one second */ 2373 if (adapter->vfs_allocated_count) { 2374 int i; 2375 2376 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2377 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2378 2379 /* ping all the active vfs to let them know we are going down */ 2380 igb_ping_all_vfs(adapter); 2381 2382 /* disable transmits and receives */ 2383 wr32(E1000_VFRE, 0); 2384 wr32(E1000_VFTE, 0); 2385 } 2386 2387 /* Allow time for pending master requests to run */ 2388 hw->mac.ops.reset_hw(hw); 2389 wr32(E1000_WUC, 0); 2390 2391 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2392 /* need to resetup here after media swap */ 2393 adapter->ei.get_invariants(hw); 2394 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2395 } 2396 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2397 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2398 igb_enable_mas(adapter); 2399 } 2400 if (hw->mac.ops.init_hw(hw)) 2401 dev_err(&pdev->dev, "Hardware Error\n"); 2402 2403 /* RAR registers were cleared during init_hw, clear mac table */ 2404 igb_flush_mac_table(adapter); 2405 __dev_uc_unsync(adapter->netdev, NULL); 2406 2407 /* Recover default RAR entry */ 2408 igb_set_default_mac_filter(adapter); 2409 2410 /* Flow control settings reset on hardware reset, so guarantee flow 2411 * control is off when forcing speed. 2412 */ 2413 if (!hw->mac.autoneg) 2414 igb_force_mac_fc(hw); 2415 2416 igb_init_dmac(adapter, pba); 2417 #ifdef CONFIG_IGB_HWMON 2418 /* Re-initialize the thermal sensor on i350 devices. */ 2419 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2420 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2421 /* If present, re-initialize the external thermal sensor 2422 * interface. 2423 */ 2424 if (adapter->ets) 2425 igb_set_i2c_bb(hw); 2426 mac->ops.init_thermal_sensor_thresh(hw); 2427 } 2428 } 2429 #endif 2430 /* Re-establish EEE setting */ 2431 if (hw->phy.media_type == e1000_media_type_copper) { 2432 switch (mac->type) { 2433 case e1000_i350: 2434 case e1000_i210: 2435 case e1000_i211: 2436 igb_set_eee_i350(hw, true, true); 2437 break; 2438 case e1000_i354: 2439 igb_set_eee_i354(hw, true, true); 2440 break; 2441 default: 2442 break; 2443 } 2444 } 2445 if (!netif_running(adapter->netdev)) 2446 igb_power_down_link(adapter); 2447 2448 igb_update_mng_vlan(adapter); 2449 2450 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2451 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2452 2453 /* Re-enable PTP, where applicable. */ 2454 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2455 igb_ptp_reset(adapter); 2456 2457 igb_get_phy_info(hw); 2458 } 2459 2460 static netdev_features_t igb_fix_features(struct net_device *netdev, 2461 netdev_features_t features) 2462 { 2463 /* Since there is no support for separate Rx/Tx vlan accel 2464 * enable/disable make sure Tx flag is always in same state as Rx. 2465 */ 2466 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2467 features |= NETIF_F_HW_VLAN_CTAG_TX; 2468 else 2469 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2470 2471 return features; 2472 } 2473 2474 static int igb_set_features(struct net_device *netdev, 2475 netdev_features_t features) 2476 { 2477 netdev_features_t changed = netdev->features ^ features; 2478 struct igb_adapter *adapter = netdev_priv(netdev); 2479 2480 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2481 igb_vlan_mode(netdev, features); 2482 2483 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2484 return 0; 2485 2486 if (!(features & NETIF_F_NTUPLE)) { 2487 struct hlist_node *node2; 2488 struct igb_nfc_filter *rule; 2489 2490 spin_lock(&adapter->nfc_lock); 2491 hlist_for_each_entry_safe(rule, node2, 2492 &adapter->nfc_filter_list, nfc_node) { 2493 igb_erase_filter(adapter, rule); 2494 hlist_del(&rule->nfc_node); 2495 kfree(rule); 2496 } 2497 spin_unlock(&adapter->nfc_lock); 2498 adapter->nfc_filter_count = 0; 2499 } 2500 2501 netdev->features = features; 2502 2503 if (netif_running(netdev)) 2504 igb_reinit_locked(adapter); 2505 else 2506 igb_reset(adapter); 2507 2508 return 1; 2509 } 2510 2511 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2512 struct net_device *dev, 2513 const unsigned char *addr, u16 vid, 2514 u16 flags, 2515 struct netlink_ext_ack *extack) 2516 { 2517 /* guarantee we can provide a unique filter for the unicast address */ 2518 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2519 struct igb_adapter *adapter = netdev_priv(dev); 2520 int vfn = adapter->vfs_allocated_count; 2521 2522 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2523 return -ENOMEM; 2524 } 2525 2526 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2527 } 2528 2529 #define IGB_MAX_MAC_HDR_LEN 127 2530 #define IGB_MAX_NETWORK_HDR_LEN 511 2531 2532 static netdev_features_t 2533 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2534 netdev_features_t features) 2535 { 2536 unsigned int network_hdr_len, mac_hdr_len; 2537 2538 /* Make certain the headers can be described by a context descriptor */ 2539 mac_hdr_len = skb_network_header(skb) - skb->data; 2540 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2541 return features & ~(NETIF_F_HW_CSUM | 2542 NETIF_F_SCTP_CRC | 2543 NETIF_F_GSO_UDP_L4 | 2544 NETIF_F_HW_VLAN_CTAG_TX | 2545 NETIF_F_TSO | 2546 NETIF_F_TSO6); 2547 2548 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2549 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2550 return features & ~(NETIF_F_HW_CSUM | 2551 NETIF_F_SCTP_CRC | 2552 NETIF_F_GSO_UDP_L4 | 2553 NETIF_F_TSO | 2554 NETIF_F_TSO6); 2555 2556 /* We can only support IPV4 TSO in tunnels if we can mangle the 2557 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2558 */ 2559 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2560 features &= ~NETIF_F_TSO; 2561 2562 return features; 2563 } 2564 2565 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2566 { 2567 if (!is_fqtss_enabled(adapter)) { 2568 enable_fqtss(adapter, true); 2569 return; 2570 } 2571 2572 igb_config_tx_modes(adapter, queue); 2573 2574 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2575 enable_fqtss(adapter, false); 2576 } 2577 2578 static int igb_offload_cbs(struct igb_adapter *adapter, 2579 struct tc_cbs_qopt_offload *qopt) 2580 { 2581 struct e1000_hw *hw = &adapter->hw; 2582 int err; 2583 2584 /* CBS offloading is only supported by i210 controller. */ 2585 if (hw->mac.type != e1000_i210) 2586 return -EOPNOTSUPP; 2587 2588 /* CBS offloading is only supported by queue 0 and queue 1. */ 2589 if (qopt->queue < 0 || qopt->queue > 1) 2590 return -EINVAL; 2591 2592 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2593 qopt->idleslope, qopt->sendslope, 2594 qopt->hicredit, qopt->locredit); 2595 if (err) 2596 return err; 2597 2598 igb_offload_apply(adapter, qopt->queue); 2599 2600 return 0; 2601 } 2602 2603 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2604 #define VLAN_PRIO_FULL_MASK (0x07) 2605 2606 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2607 struct flow_cls_offload *f, 2608 int traffic_class, 2609 struct igb_nfc_filter *input) 2610 { 2611 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2612 struct flow_dissector *dissector = rule->match.dissector; 2613 struct netlink_ext_ack *extack = f->common.extack; 2614 2615 if (dissector->used_keys & 2616 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2617 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2618 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2619 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2620 NL_SET_ERR_MSG_MOD(extack, 2621 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2622 return -EOPNOTSUPP; 2623 } 2624 2625 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2626 struct flow_match_eth_addrs match; 2627 2628 flow_rule_match_eth_addrs(rule, &match); 2629 if (!is_zero_ether_addr(match.mask->dst)) { 2630 if (!is_broadcast_ether_addr(match.mask->dst)) { 2631 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2632 return -EINVAL; 2633 } 2634 2635 input->filter.match_flags |= 2636 IGB_FILTER_FLAG_DST_MAC_ADDR; 2637 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2638 } 2639 2640 if (!is_zero_ether_addr(match.mask->src)) { 2641 if (!is_broadcast_ether_addr(match.mask->src)) { 2642 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2643 return -EINVAL; 2644 } 2645 2646 input->filter.match_flags |= 2647 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2648 ether_addr_copy(input->filter.src_addr, match.key->src); 2649 } 2650 } 2651 2652 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2653 struct flow_match_basic match; 2654 2655 flow_rule_match_basic(rule, &match); 2656 if (match.mask->n_proto) { 2657 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2658 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2659 return -EINVAL; 2660 } 2661 2662 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2663 input->filter.etype = match.key->n_proto; 2664 } 2665 } 2666 2667 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2668 struct flow_match_vlan match; 2669 2670 flow_rule_match_vlan(rule, &match); 2671 if (match.mask->vlan_priority) { 2672 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2673 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2674 return -EINVAL; 2675 } 2676 2677 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2678 input->filter.vlan_tci = 2679 (__force __be16)match.key->vlan_priority; 2680 } 2681 } 2682 2683 input->action = traffic_class; 2684 input->cookie = f->cookie; 2685 2686 return 0; 2687 } 2688 2689 static int igb_configure_clsflower(struct igb_adapter *adapter, 2690 struct flow_cls_offload *cls_flower) 2691 { 2692 struct netlink_ext_ack *extack = cls_flower->common.extack; 2693 struct igb_nfc_filter *filter, *f; 2694 int err, tc; 2695 2696 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2697 if (tc < 0) { 2698 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2699 return -EINVAL; 2700 } 2701 2702 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2703 if (!filter) 2704 return -ENOMEM; 2705 2706 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2707 if (err < 0) 2708 goto err_parse; 2709 2710 spin_lock(&adapter->nfc_lock); 2711 2712 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2713 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2714 err = -EEXIST; 2715 NL_SET_ERR_MSG_MOD(extack, 2716 "This filter is already set in ethtool"); 2717 goto err_locked; 2718 } 2719 } 2720 2721 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2722 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2723 err = -EEXIST; 2724 NL_SET_ERR_MSG_MOD(extack, 2725 "This filter is already set in cls_flower"); 2726 goto err_locked; 2727 } 2728 } 2729 2730 err = igb_add_filter(adapter, filter); 2731 if (err < 0) { 2732 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2733 goto err_locked; 2734 } 2735 2736 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2737 2738 spin_unlock(&adapter->nfc_lock); 2739 2740 return 0; 2741 2742 err_locked: 2743 spin_unlock(&adapter->nfc_lock); 2744 2745 err_parse: 2746 kfree(filter); 2747 2748 return err; 2749 } 2750 2751 static int igb_delete_clsflower(struct igb_adapter *adapter, 2752 struct flow_cls_offload *cls_flower) 2753 { 2754 struct igb_nfc_filter *filter; 2755 int err; 2756 2757 spin_lock(&adapter->nfc_lock); 2758 2759 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2760 if (filter->cookie == cls_flower->cookie) 2761 break; 2762 2763 if (!filter) { 2764 err = -ENOENT; 2765 goto out; 2766 } 2767 2768 err = igb_erase_filter(adapter, filter); 2769 if (err < 0) 2770 goto out; 2771 2772 hlist_del(&filter->nfc_node); 2773 kfree(filter); 2774 2775 out: 2776 spin_unlock(&adapter->nfc_lock); 2777 2778 return err; 2779 } 2780 2781 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2782 struct flow_cls_offload *cls_flower) 2783 { 2784 switch (cls_flower->command) { 2785 case FLOW_CLS_REPLACE: 2786 return igb_configure_clsflower(adapter, cls_flower); 2787 case FLOW_CLS_DESTROY: 2788 return igb_delete_clsflower(adapter, cls_flower); 2789 case FLOW_CLS_STATS: 2790 return -EOPNOTSUPP; 2791 default: 2792 return -EOPNOTSUPP; 2793 } 2794 } 2795 2796 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2797 void *cb_priv) 2798 { 2799 struct igb_adapter *adapter = cb_priv; 2800 2801 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2802 return -EOPNOTSUPP; 2803 2804 switch (type) { 2805 case TC_SETUP_CLSFLOWER: 2806 return igb_setup_tc_cls_flower(adapter, type_data); 2807 2808 default: 2809 return -EOPNOTSUPP; 2810 } 2811 } 2812 2813 static int igb_offload_txtime(struct igb_adapter *adapter, 2814 struct tc_etf_qopt_offload *qopt) 2815 { 2816 struct e1000_hw *hw = &adapter->hw; 2817 int err; 2818 2819 /* Launchtime offloading is only supported by i210 controller. */ 2820 if (hw->mac.type != e1000_i210) 2821 return -EOPNOTSUPP; 2822 2823 /* Launchtime offloading is only supported by queues 0 and 1. */ 2824 if (qopt->queue < 0 || qopt->queue > 1) 2825 return -EINVAL; 2826 2827 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2828 if (err) 2829 return err; 2830 2831 igb_offload_apply(adapter, qopt->queue); 2832 2833 return 0; 2834 } 2835 2836 static int igb_tc_query_caps(struct igb_adapter *adapter, 2837 struct tc_query_caps_base *base) 2838 { 2839 switch (base->type) { 2840 case TC_SETUP_QDISC_TAPRIO: { 2841 struct tc_taprio_caps *caps = base->caps; 2842 2843 caps->broken_mqprio = true; 2844 2845 return 0; 2846 } 2847 default: 2848 return -EOPNOTSUPP; 2849 } 2850 } 2851 2852 static LIST_HEAD(igb_block_cb_list); 2853 2854 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2855 void *type_data) 2856 { 2857 struct igb_adapter *adapter = netdev_priv(dev); 2858 2859 switch (type) { 2860 case TC_QUERY_CAPS: 2861 return igb_tc_query_caps(adapter, type_data); 2862 case TC_SETUP_QDISC_CBS: 2863 return igb_offload_cbs(adapter, type_data); 2864 case TC_SETUP_BLOCK: 2865 return flow_block_cb_setup_simple(type_data, 2866 &igb_block_cb_list, 2867 igb_setup_tc_block_cb, 2868 adapter, adapter, true); 2869 2870 case TC_SETUP_QDISC_ETF: 2871 return igb_offload_txtime(adapter, type_data); 2872 2873 default: 2874 return -EOPNOTSUPP; 2875 } 2876 } 2877 2878 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2879 { 2880 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2881 struct igb_adapter *adapter = netdev_priv(dev); 2882 struct bpf_prog *prog = bpf->prog, *old_prog; 2883 bool running = netif_running(dev); 2884 bool need_reset; 2885 2886 /* verify igb ring attributes are sufficient for XDP */ 2887 for (i = 0; i < adapter->num_rx_queues; i++) { 2888 struct igb_ring *ring = adapter->rx_ring[i]; 2889 2890 if (frame_size > igb_rx_bufsz(ring)) { 2891 NL_SET_ERR_MSG_MOD(bpf->extack, 2892 "The RX buffer size is too small for the frame size"); 2893 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2894 igb_rx_bufsz(ring), frame_size); 2895 return -EINVAL; 2896 } 2897 } 2898 2899 old_prog = xchg(&adapter->xdp_prog, prog); 2900 need_reset = (!!prog != !!old_prog); 2901 2902 /* device is up and bpf is added/removed, must setup the RX queues */ 2903 if (need_reset && running) { 2904 igb_close(dev); 2905 } else { 2906 for (i = 0; i < adapter->num_rx_queues; i++) 2907 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2908 adapter->xdp_prog); 2909 } 2910 2911 if (old_prog) 2912 bpf_prog_put(old_prog); 2913 2914 /* bpf is just replaced, RXQ and MTU are already setup */ 2915 if (!need_reset) { 2916 return 0; 2917 } else { 2918 if (prog) 2919 xdp_features_set_redirect_target(dev, true); 2920 else 2921 xdp_features_clear_redirect_target(dev); 2922 } 2923 2924 if (running) 2925 igb_open(dev); 2926 2927 return 0; 2928 } 2929 2930 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2931 { 2932 switch (xdp->command) { 2933 case XDP_SETUP_PROG: 2934 return igb_xdp_setup(dev, xdp); 2935 default: 2936 return -EINVAL; 2937 } 2938 } 2939 2940 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2941 { 2942 /* Force memory writes to complete before letting h/w know there 2943 * are new descriptors to fetch. 2944 */ 2945 wmb(); 2946 writel(ring->next_to_use, ring->tail); 2947 } 2948 2949 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2950 { 2951 unsigned int r_idx = smp_processor_id(); 2952 2953 if (r_idx >= adapter->num_tx_queues) 2954 r_idx = r_idx % adapter->num_tx_queues; 2955 2956 return adapter->tx_ring[r_idx]; 2957 } 2958 2959 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2960 { 2961 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2962 int cpu = smp_processor_id(); 2963 struct igb_ring *tx_ring; 2964 struct netdev_queue *nq; 2965 u32 ret; 2966 2967 if (unlikely(!xdpf)) 2968 return IGB_XDP_CONSUMED; 2969 2970 /* During program transitions its possible adapter->xdp_prog is assigned 2971 * but ring has not been configured yet. In this case simply abort xmit. 2972 */ 2973 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2974 if (unlikely(!tx_ring)) 2975 return IGB_XDP_CONSUMED; 2976 2977 nq = txring_txq(tx_ring); 2978 __netif_tx_lock(nq, cpu); 2979 /* Avoid transmit queue timeout since we share it with the slow path */ 2980 txq_trans_cond_update(nq); 2981 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2982 __netif_tx_unlock(nq); 2983 2984 return ret; 2985 } 2986 2987 static int igb_xdp_xmit(struct net_device *dev, int n, 2988 struct xdp_frame **frames, u32 flags) 2989 { 2990 struct igb_adapter *adapter = netdev_priv(dev); 2991 int cpu = smp_processor_id(); 2992 struct igb_ring *tx_ring; 2993 struct netdev_queue *nq; 2994 int nxmit = 0; 2995 int i; 2996 2997 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2998 return -ENETDOWN; 2999 3000 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3001 return -EINVAL; 3002 3003 /* During program transitions its possible adapter->xdp_prog is assigned 3004 * but ring has not been configured yet. In this case simply abort xmit. 3005 */ 3006 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 3007 if (unlikely(!tx_ring)) 3008 return -ENXIO; 3009 3010 nq = txring_txq(tx_ring); 3011 __netif_tx_lock(nq, cpu); 3012 3013 /* Avoid transmit queue timeout since we share it with the slow path */ 3014 txq_trans_cond_update(nq); 3015 3016 for (i = 0; i < n; i++) { 3017 struct xdp_frame *xdpf = frames[i]; 3018 int err; 3019 3020 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3021 if (err != IGB_XDP_TX) 3022 break; 3023 nxmit++; 3024 } 3025 3026 __netif_tx_unlock(nq); 3027 3028 if (unlikely(flags & XDP_XMIT_FLUSH)) 3029 igb_xdp_ring_update_tail(tx_ring); 3030 3031 return nxmit; 3032 } 3033 3034 static const struct net_device_ops igb_netdev_ops = { 3035 .ndo_open = igb_open, 3036 .ndo_stop = igb_close, 3037 .ndo_start_xmit = igb_xmit_frame, 3038 .ndo_get_stats64 = igb_get_stats64, 3039 .ndo_set_rx_mode = igb_set_rx_mode, 3040 .ndo_set_mac_address = igb_set_mac, 3041 .ndo_change_mtu = igb_change_mtu, 3042 .ndo_eth_ioctl = igb_ioctl, 3043 .ndo_tx_timeout = igb_tx_timeout, 3044 .ndo_validate_addr = eth_validate_addr, 3045 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3046 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3047 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3048 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3049 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3050 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3051 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3052 .ndo_get_vf_config = igb_ndo_get_vf_config, 3053 .ndo_fix_features = igb_fix_features, 3054 .ndo_set_features = igb_set_features, 3055 .ndo_fdb_add = igb_ndo_fdb_add, 3056 .ndo_features_check = igb_features_check, 3057 .ndo_setup_tc = igb_setup_tc, 3058 .ndo_bpf = igb_xdp, 3059 .ndo_xdp_xmit = igb_xdp_xmit, 3060 }; 3061 3062 /** 3063 * igb_set_fw_version - Configure version string for ethtool 3064 * @adapter: adapter struct 3065 **/ 3066 void igb_set_fw_version(struct igb_adapter *adapter) 3067 { 3068 struct e1000_hw *hw = &adapter->hw; 3069 struct e1000_fw_version fw; 3070 3071 igb_get_fw_version(hw, &fw); 3072 3073 switch (hw->mac.type) { 3074 case e1000_i210: 3075 case e1000_i211: 3076 if (!(igb_get_flash_presence_i210(hw))) { 3077 snprintf(adapter->fw_version, 3078 sizeof(adapter->fw_version), 3079 "%2d.%2d-%d", 3080 fw.invm_major, fw.invm_minor, 3081 fw.invm_img_type); 3082 break; 3083 } 3084 fallthrough; 3085 default: 3086 /* if option is rom valid, display its version too */ 3087 if (fw.or_valid) { 3088 snprintf(adapter->fw_version, 3089 sizeof(adapter->fw_version), 3090 "%d.%d, 0x%08x, %d.%d.%d", 3091 fw.eep_major, fw.eep_minor, fw.etrack_id, 3092 fw.or_major, fw.or_build, fw.or_patch); 3093 /* no option rom */ 3094 } else if (fw.etrack_id != 0X0000) { 3095 snprintf(adapter->fw_version, 3096 sizeof(adapter->fw_version), 3097 "%d.%d, 0x%08x", 3098 fw.eep_major, fw.eep_minor, fw.etrack_id); 3099 } else { 3100 snprintf(adapter->fw_version, 3101 sizeof(adapter->fw_version), 3102 "%d.%d.%d", 3103 fw.eep_major, fw.eep_minor, fw.eep_build); 3104 } 3105 break; 3106 } 3107 } 3108 3109 /** 3110 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3111 * 3112 * @adapter: adapter struct 3113 **/ 3114 static void igb_init_mas(struct igb_adapter *adapter) 3115 { 3116 struct e1000_hw *hw = &adapter->hw; 3117 u16 eeprom_data; 3118 3119 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3120 switch (hw->bus.func) { 3121 case E1000_FUNC_0: 3122 if (eeprom_data & IGB_MAS_ENABLE_0) { 3123 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3124 netdev_info(adapter->netdev, 3125 "MAS: Enabling Media Autosense for port %d\n", 3126 hw->bus.func); 3127 } 3128 break; 3129 case E1000_FUNC_1: 3130 if (eeprom_data & IGB_MAS_ENABLE_1) { 3131 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3132 netdev_info(adapter->netdev, 3133 "MAS: Enabling Media Autosense for port %d\n", 3134 hw->bus.func); 3135 } 3136 break; 3137 case E1000_FUNC_2: 3138 if (eeprom_data & IGB_MAS_ENABLE_2) { 3139 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3140 netdev_info(adapter->netdev, 3141 "MAS: Enabling Media Autosense for port %d\n", 3142 hw->bus.func); 3143 } 3144 break; 3145 case E1000_FUNC_3: 3146 if (eeprom_data & IGB_MAS_ENABLE_3) { 3147 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3148 netdev_info(adapter->netdev, 3149 "MAS: Enabling Media Autosense for port %d\n", 3150 hw->bus.func); 3151 } 3152 break; 3153 default: 3154 /* Shouldn't get here */ 3155 netdev_err(adapter->netdev, 3156 "MAS: Invalid port configuration, returning\n"); 3157 break; 3158 } 3159 } 3160 3161 /** 3162 * igb_init_i2c - Init I2C interface 3163 * @adapter: pointer to adapter structure 3164 **/ 3165 static s32 igb_init_i2c(struct igb_adapter *adapter) 3166 { 3167 s32 status = 0; 3168 3169 /* I2C interface supported on i350 devices */ 3170 if (adapter->hw.mac.type != e1000_i350) 3171 return 0; 3172 3173 /* Initialize the i2c bus which is controlled by the registers. 3174 * This bus will use the i2c_algo_bit structure that implements 3175 * the protocol through toggling of the 4 bits in the register. 3176 */ 3177 adapter->i2c_adap.owner = THIS_MODULE; 3178 adapter->i2c_algo = igb_i2c_algo; 3179 adapter->i2c_algo.data = adapter; 3180 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3181 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3182 strscpy(adapter->i2c_adap.name, "igb BB", 3183 sizeof(adapter->i2c_adap.name)); 3184 status = i2c_bit_add_bus(&adapter->i2c_adap); 3185 return status; 3186 } 3187 3188 /** 3189 * igb_probe - Device Initialization Routine 3190 * @pdev: PCI device information struct 3191 * @ent: entry in igb_pci_tbl 3192 * 3193 * Returns 0 on success, negative on failure 3194 * 3195 * igb_probe initializes an adapter identified by a pci_dev structure. 3196 * The OS initialization, configuring of the adapter private structure, 3197 * and a hardware reset occur. 3198 **/ 3199 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3200 { 3201 struct net_device *netdev; 3202 struct igb_adapter *adapter; 3203 struct e1000_hw *hw; 3204 u16 eeprom_data = 0; 3205 s32 ret_val; 3206 static int global_quad_port_a; /* global quad port a indication */ 3207 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3208 u8 part_str[E1000_PBANUM_LENGTH]; 3209 int err; 3210 3211 /* Catch broken hardware that put the wrong VF device ID in 3212 * the PCIe SR-IOV capability. 3213 */ 3214 if (pdev->is_virtfn) { 3215 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3216 pci_name(pdev), pdev->vendor, pdev->device); 3217 return -EINVAL; 3218 } 3219 3220 err = pci_enable_device_mem(pdev); 3221 if (err) 3222 return err; 3223 3224 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3225 if (err) { 3226 dev_err(&pdev->dev, 3227 "No usable DMA configuration, aborting\n"); 3228 goto err_dma; 3229 } 3230 3231 err = pci_request_mem_regions(pdev, igb_driver_name); 3232 if (err) 3233 goto err_pci_reg; 3234 3235 pci_set_master(pdev); 3236 pci_save_state(pdev); 3237 3238 err = -ENOMEM; 3239 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3240 IGB_MAX_TX_QUEUES); 3241 if (!netdev) 3242 goto err_alloc_etherdev; 3243 3244 SET_NETDEV_DEV(netdev, &pdev->dev); 3245 3246 pci_set_drvdata(pdev, netdev); 3247 adapter = netdev_priv(netdev); 3248 adapter->netdev = netdev; 3249 adapter->pdev = pdev; 3250 hw = &adapter->hw; 3251 hw->back = adapter; 3252 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3253 3254 err = -EIO; 3255 adapter->io_addr = pci_iomap(pdev, 0, 0); 3256 if (!adapter->io_addr) 3257 goto err_ioremap; 3258 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3259 hw->hw_addr = adapter->io_addr; 3260 3261 netdev->netdev_ops = &igb_netdev_ops; 3262 igb_set_ethtool_ops(netdev); 3263 netdev->watchdog_timeo = 5 * HZ; 3264 3265 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3266 3267 netdev->mem_start = pci_resource_start(pdev, 0); 3268 netdev->mem_end = pci_resource_end(pdev, 0); 3269 3270 /* PCI config space info */ 3271 hw->vendor_id = pdev->vendor; 3272 hw->device_id = pdev->device; 3273 hw->revision_id = pdev->revision; 3274 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3275 hw->subsystem_device_id = pdev->subsystem_device; 3276 3277 /* Copy the default MAC, PHY and NVM function pointers */ 3278 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3279 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3280 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3281 /* Initialize skew-specific constants */ 3282 err = ei->get_invariants(hw); 3283 if (err) 3284 goto err_sw_init; 3285 3286 /* setup the private structure */ 3287 err = igb_sw_init(adapter); 3288 if (err) 3289 goto err_sw_init; 3290 3291 igb_get_bus_info_pcie(hw); 3292 3293 hw->phy.autoneg_wait_to_complete = false; 3294 3295 /* Copper options */ 3296 if (hw->phy.media_type == e1000_media_type_copper) { 3297 hw->phy.mdix = AUTO_ALL_MODES; 3298 hw->phy.disable_polarity_correction = false; 3299 hw->phy.ms_type = e1000_ms_hw_default; 3300 } 3301 3302 if (igb_check_reset_block(hw)) 3303 dev_info(&pdev->dev, 3304 "PHY reset is blocked due to SOL/IDER session.\n"); 3305 3306 /* features is initialized to 0 in allocation, it might have bits 3307 * set by igb_sw_init so we should use an or instead of an 3308 * assignment. 3309 */ 3310 netdev->features |= NETIF_F_SG | 3311 NETIF_F_TSO | 3312 NETIF_F_TSO6 | 3313 NETIF_F_RXHASH | 3314 NETIF_F_RXCSUM | 3315 NETIF_F_HW_CSUM; 3316 3317 if (hw->mac.type >= e1000_82576) 3318 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3319 3320 if (hw->mac.type >= e1000_i350) 3321 netdev->features |= NETIF_F_HW_TC; 3322 3323 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3324 NETIF_F_GSO_GRE_CSUM | \ 3325 NETIF_F_GSO_IPXIP4 | \ 3326 NETIF_F_GSO_IPXIP6 | \ 3327 NETIF_F_GSO_UDP_TUNNEL | \ 3328 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3329 3330 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3331 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3332 3333 /* copy netdev features into list of user selectable features */ 3334 netdev->hw_features |= netdev->features | 3335 NETIF_F_HW_VLAN_CTAG_RX | 3336 NETIF_F_HW_VLAN_CTAG_TX | 3337 NETIF_F_RXALL; 3338 3339 if (hw->mac.type >= e1000_i350) 3340 netdev->hw_features |= NETIF_F_NTUPLE; 3341 3342 netdev->features |= NETIF_F_HIGHDMA; 3343 3344 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3345 netdev->mpls_features |= NETIF_F_HW_CSUM; 3346 netdev->hw_enc_features |= netdev->vlan_features; 3347 3348 /* set this bit last since it cannot be part of vlan_features */ 3349 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3350 NETIF_F_HW_VLAN_CTAG_RX | 3351 NETIF_F_HW_VLAN_CTAG_TX; 3352 3353 netdev->priv_flags |= IFF_SUPP_NOFCS; 3354 3355 netdev->priv_flags |= IFF_UNICAST_FLT; 3356 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3357 3358 /* MTU range: 68 - 9216 */ 3359 netdev->min_mtu = ETH_MIN_MTU; 3360 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3361 3362 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3363 3364 /* before reading the NVM, reset the controller to put the device in a 3365 * known good starting state 3366 */ 3367 hw->mac.ops.reset_hw(hw); 3368 3369 /* make sure the NVM is good , i211/i210 parts can have special NVM 3370 * that doesn't contain a checksum 3371 */ 3372 switch (hw->mac.type) { 3373 case e1000_i210: 3374 case e1000_i211: 3375 if (igb_get_flash_presence_i210(hw)) { 3376 if (hw->nvm.ops.validate(hw) < 0) { 3377 dev_err(&pdev->dev, 3378 "The NVM Checksum Is Not Valid\n"); 3379 err = -EIO; 3380 goto err_eeprom; 3381 } 3382 } 3383 break; 3384 default: 3385 if (hw->nvm.ops.validate(hw) < 0) { 3386 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3387 err = -EIO; 3388 goto err_eeprom; 3389 } 3390 break; 3391 } 3392 3393 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3394 /* copy the MAC address out of the NVM */ 3395 if (hw->mac.ops.read_mac_addr(hw)) 3396 dev_err(&pdev->dev, "NVM Read Error\n"); 3397 } 3398 3399 eth_hw_addr_set(netdev, hw->mac.addr); 3400 3401 if (!is_valid_ether_addr(netdev->dev_addr)) { 3402 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3403 err = -EIO; 3404 goto err_eeprom; 3405 } 3406 3407 igb_set_default_mac_filter(adapter); 3408 3409 /* get firmware version for ethtool -i */ 3410 igb_set_fw_version(adapter); 3411 3412 /* configure RXPBSIZE and TXPBSIZE */ 3413 if (hw->mac.type == e1000_i210) { 3414 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3415 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3416 } 3417 3418 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3419 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3420 3421 INIT_WORK(&adapter->reset_task, igb_reset_task); 3422 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3423 3424 /* Initialize link properties that are user-changeable */ 3425 adapter->fc_autoneg = true; 3426 hw->mac.autoneg = true; 3427 hw->phy.autoneg_advertised = 0x2f; 3428 3429 hw->fc.requested_mode = e1000_fc_default; 3430 hw->fc.current_mode = e1000_fc_default; 3431 3432 igb_validate_mdi_setting(hw); 3433 3434 /* By default, support wake on port A */ 3435 if (hw->bus.func == 0) 3436 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3437 3438 /* Check the NVM for wake support on non-port A ports */ 3439 if (hw->mac.type >= e1000_82580) 3440 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3441 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3442 &eeprom_data); 3443 else if (hw->bus.func == 1) 3444 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3445 3446 if (eeprom_data & IGB_EEPROM_APME) 3447 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3448 3449 /* now that we have the eeprom settings, apply the special cases where 3450 * the eeprom may be wrong or the board simply won't support wake on 3451 * lan on a particular port 3452 */ 3453 switch (pdev->device) { 3454 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3455 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3456 break; 3457 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3458 case E1000_DEV_ID_82576_FIBER: 3459 case E1000_DEV_ID_82576_SERDES: 3460 /* Wake events only supported on port A for dual fiber 3461 * regardless of eeprom setting 3462 */ 3463 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3464 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3465 break; 3466 case E1000_DEV_ID_82576_QUAD_COPPER: 3467 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3468 /* if quad port adapter, disable WoL on all but port A */ 3469 if (global_quad_port_a != 0) 3470 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3471 else 3472 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3473 /* Reset for multiple quad port adapters */ 3474 if (++global_quad_port_a == 4) 3475 global_quad_port_a = 0; 3476 break; 3477 default: 3478 /* If the device can't wake, don't set software support */ 3479 if (!device_can_wakeup(&adapter->pdev->dev)) 3480 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3481 } 3482 3483 /* initialize the wol settings based on the eeprom settings */ 3484 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3485 adapter->wol |= E1000_WUFC_MAG; 3486 3487 /* Some vendors want WoL disabled by default, but still supported */ 3488 if ((hw->mac.type == e1000_i350) && 3489 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3490 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3491 adapter->wol = 0; 3492 } 3493 3494 /* Some vendors want the ability to Use the EEPROM setting as 3495 * enable/disable only, and not for capability 3496 */ 3497 if (((hw->mac.type == e1000_i350) || 3498 (hw->mac.type == e1000_i354)) && 3499 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3500 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3501 adapter->wol = 0; 3502 } 3503 if (hw->mac.type == e1000_i350) { 3504 if (((pdev->subsystem_device == 0x5001) || 3505 (pdev->subsystem_device == 0x5002)) && 3506 (hw->bus.func == 0)) { 3507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3508 adapter->wol = 0; 3509 } 3510 if (pdev->subsystem_device == 0x1F52) 3511 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3512 } 3513 3514 device_set_wakeup_enable(&adapter->pdev->dev, 3515 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3516 3517 /* reset the hardware with the new settings */ 3518 igb_reset(adapter); 3519 3520 /* Init the I2C interface */ 3521 err = igb_init_i2c(adapter); 3522 if (err) { 3523 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3524 goto err_eeprom; 3525 } 3526 3527 /* let the f/w know that the h/w is now under the control of the 3528 * driver. 3529 */ 3530 igb_get_hw_control(adapter); 3531 3532 strcpy(netdev->name, "eth%d"); 3533 err = register_netdev(netdev); 3534 if (err) 3535 goto err_register; 3536 3537 /* carrier off reporting is important to ethtool even BEFORE open */ 3538 netif_carrier_off(netdev); 3539 3540 #ifdef CONFIG_IGB_DCA 3541 if (dca_add_requester(&pdev->dev) == 0) { 3542 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3543 dev_info(&pdev->dev, "DCA enabled\n"); 3544 igb_setup_dca(adapter); 3545 } 3546 3547 #endif 3548 #ifdef CONFIG_IGB_HWMON 3549 /* Initialize the thermal sensor on i350 devices. */ 3550 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3551 u16 ets_word; 3552 3553 /* Read the NVM to determine if this i350 device supports an 3554 * external thermal sensor. 3555 */ 3556 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3557 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3558 adapter->ets = true; 3559 else 3560 adapter->ets = false; 3561 /* Only enable I2C bit banging if an external thermal 3562 * sensor is supported. 3563 */ 3564 if (adapter->ets) 3565 igb_set_i2c_bb(hw); 3566 hw->mac.ops.init_thermal_sensor_thresh(hw); 3567 if (igb_sysfs_init(adapter)) 3568 dev_err(&pdev->dev, 3569 "failed to allocate sysfs resources\n"); 3570 } else { 3571 adapter->ets = false; 3572 } 3573 #endif 3574 /* Check if Media Autosense is enabled */ 3575 adapter->ei = *ei; 3576 if (hw->dev_spec._82575.mas_capable) 3577 igb_init_mas(adapter); 3578 3579 /* do hw tstamp init after resetting */ 3580 igb_ptp_init(adapter); 3581 3582 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3583 /* print bus type/speed/width info, not applicable to i354 */ 3584 if (hw->mac.type != e1000_i354) { 3585 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3586 netdev->name, 3587 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3588 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3589 "unknown"), 3590 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3591 "Width x4" : 3592 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3593 "Width x2" : 3594 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3595 "Width x1" : "unknown"), netdev->dev_addr); 3596 } 3597 3598 if ((hw->mac.type == e1000_82576 && 3599 rd32(E1000_EECD) & E1000_EECD_PRES) || 3600 (hw->mac.type >= e1000_i210 || 3601 igb_get_flash_presence_i210(hw))) { 3602 ret_val = igb_read_part_string(hw, part_str, 3603 E1000_PBANUM_LENGTH); 3604 } else { 3605 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3606 } 3607 3608 if (ret_val) 3609 strcpy(part_str, "Unknown"); 3610 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3611 dev_info(&pdev->dev, 3612 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3613 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3614 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3615 adapter->num_rx_queues, adapter->num_tx_queues); 3616 if (hw->phy.media_type == e1000_media_type_copper) { 3617 switch (hw->mac.type) { 3618 case e1000_i350: 3619 case e1000_i210: 3620 case e1000_i211: 3621 /* Enable EEE for internal copper PHY devices */ 3622 err = igb_set_eee_i350(hw, true, true); 3623 if ((!err) && 3624 (!hw->dev_spec._82575.eee_disable)) { 3625 adapter->eee_advert = 3626 MDIO_EEE_100TX | MDIO_EEE_1000T; 3627 adapter->flags |= IGB_FLAG_EEE; 3628 } 3629 break; 3630 case e1000_i354: 3631 if ((rd32(E1000_CTRL_EXT) & 3632 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3633 err = igb_set_eee_i354(hw, true, true); 3634 if ((!err) && 3635 (!hw->dev_spec._82575.eee_disable)) { 3636 adapter->eee_advert = 3637 MDIO_EEE_100TX | MDIO_EEE_1000T; 3638 adapter->flags |= IGB_FLAG_EEE; 3639 } 3640 } 3641 break; 3642 default: 3643 break; 3644 } 3645 } 3646 3647 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3648 3649 pm_runtime_put_noidle(&pdev->dev); 3650 return 0; 3651 3652 err_register: 3653 igb_release_hw_control(adapter); 3654 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3655 err_eeprom: 3656 if (!igb_check_reset_block(hw)) 3657 igb_reset_phy(hw); 3658 3659 if (hw->flash_address) 3660 iounmap(hw->flash_address); 3661 err_sw_init: 3662 kfree(adapter->mac_table); 3663 kfree(adapter->shadow_vfta); 3664 igb_clear_interrupt_scheme(adapter); 3665 #ifdef CONFIG_PCI_IOV 3666 igb_disable_sriov(pdev, false); 3667 #endif 3668 pci_iounmap(pdev, adapter->io_addr); 3669 err_ioremap: 3670 free_netdev(netdev); 3671 err_alloc_etherdev: 3672 pci_release_mem_regions(pdev); 3673 err_pci_reg: 3674 err_dma: 3675 pci_disable_device(pdev); 3676 return err; 3677 } 3678 3679 #ifdef CONFIG_PCI_IOV 3680 static int igb_sriov_reinit(struct pci_dev *dev) 3681 { 3682 struct net_device *netdev = pci_get_drvdata(dev); 3683 struct igb_adapter *adapter = netdev_priv(netdev); 3684 struct pci_dev *pdev = adapter->pdev; 3685 3686 rtnl_lock(); 3687 3688 if (netif_running(netdev)) 3689 igb_close(netdev); 3690 else 3691 igb_reset(adapter); 3692 3693 igb_clear_interrupt_scheme(adapter); 3694 3695 igb_init_queue_configuration(adapter); 3696 3697 if (igb_init_interrupt_scheme(adapter, true)) { 3698 rtnl_unlock(); 3699 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3700 return -ENOMEM; 3701 } 3702 3703 if (netif_running(netdev)) 3704 igb_open(netdev); 3705 3706 rtnl_unlock(); 3707 3708 return 0; 3709 } 3710 3711 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3712 { 3713 struct net_device *netdev = pci_get_drvdata(pdev); 3714 struct igb_adapter *adapter = netdev_priv(netdev); 3715 struct e1000_hw *hw = &adapter->hw; 3716 unsigned long flags; 3717 3718 /* reclaim resources allocated to VFs */ 3719 if (adapter->vf_data) { 3720 /* disable iov and allow time for transactions to clear */ 3721 if (pci_vfs_assigned(pdev)) { 3722 dev_warn(&pdev->dev, 3723 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3724 return -EPERM; 3725 } else { 3726 pci_disable_sriov(pdev); 3727 msleep(500); 3728 } 3729 spin_lock_irqsave(&adapter->vfs_lock, flags); 3730 kfree(adapter->vf_mac_list); 3731 adapter->vf_mac_list = NULL; 3732 kfree(adapter->vf_data); 3733 adapter->vf_data = NULL; 3734 adapter->vfs_allocated_count = 0; 3735 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3736 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3737 wrfl(); 3738 msleep(100); 3739 dev_info(&pdev->dev, "IOV Disabled\n"); 3740 3741 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3742 adapter->flags |= IGB_FLAG_DMAC; 3743 } 3744 3745 return reinit ? igb_sriov_reinit(pdev) : 0; 3746 } 3747 3748 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3749 { 3750 struct net_device *netdev = pci_get_drvdata(pdev); 3751 struct igb_adapter *adapter = netdev_priv(netdev); 3752 int old_vfs = pci_num_vf(pdev); 3753 struct vf_mac_filter *mac_list; 3754 int err = 0; 3755 int num_vf_mac_filters, i; 3756 3757 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3758 err = -EPERM; 3759 goto out; 3760 } 3761 if (!num_vfs) 3762 goto out; 3763 3764 if (old_vfs) { 3765 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3766 old_vfs, max_vfs); 3767 adapter->vfs_allocated_count = old_vfs; 3768 } else 3769 adapter->vfs_allocated_count = num_vfs; 3770 3771 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3772 sizeof(struct vf_data_storage), GFP_KERNEL); 3773 3774 /* if allocation failed then we do not support SR-IOV */ 3775 if (!adapter->vf_data) { 3776 adapter->vfs_allocated_count = 0; 3777 err = -ENOMEM; 3778 goto out; 3779 } 3780 3781 /* Due to the limited number of RAR entries calculate potential 3782 * number of MAC filters available for the VFs. Reserve entries 3783 * for PF default MAC, PF MAC filters and at least one RAR entry 3784 * for each VF for VF MAC. 3785 */ 3786 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3787 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3788 adapter->vfs_allocated_count); 3789 3790 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3791 sizeof(struct vf_mac_filter), 3792 GFP_KERNEL); 3793 3794 mac_list = adapter->vf_mac_list; 3795 INIT_LIST_HEAD(&adapter->vf_macs.l); 3796 3797 if (adapter->vf_mac_list) { 3798 /* Initialize list of VF MAC filters */ 3799 for (i = 0; i < num_vf_mac_filters; i++) { 3800 mac_list->vf = -1; 3801 mac_list->free = true; 3802 list_add(&mac_list->l, &adapter->vf_macs.l); 3803 mac_list++; 3804 } 3805 } else { 3806 /* If we could not allocate memory for the VF MAC filters 3807 * we can continue without this feature but warn user. 3808 */ 3809 dev_err(&pdev->dev, 3810 "Unable to allocate memory for VF MAC filter list\n"); 3811 } 3812 3813 dev_info(&pdev->dev, "%d VFs allocated\n", 3814 adapter->vfs_allocated_count); 3815 for (i = 0; i < adapter->vfs_allocated_count; i++) 3816 igb_vf_configure(adapter, i); 3817 3818 /* DMA Coalescing is not supported in IOV mode. */ 3819 adapter->flags &= ~IGB_FLAG_DMAC; 3820 3821 if (reinit) { 3822 err = igb_sriov_reinit(pdev); 3823 if (err) 3824 goto err_out; 3825 } 3826 3827 /* only call pci_enable_sriov() if no VFs are allocated already */ 3828 if (!old_vfs) 3829 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3830 3831 goto out; 3832 3833 err_out: 3834 kfree(adapter->vf_mac_list); 3835 adapter->vf_mac_list = NULL; 3836 kfree(adapter->vf_data); 3837 adapter->vf_data = NULL; 3838 adapter->vfs_allocated_count = 0; 3839 out: 3840 return err; 3841 } 3842 3843 #endif 3844 /** 3845 * igb_remove_i2c - Cleanup I2C interface 3846 * @adapter: pointer to adapter structure 3847 **/ 3848 static void igb_remove_i2c(struct igb_adapter *adapter) 3849 { 3850 /* free the adapter bus structure */ 3851 i2c_del_adapter(&adapter->i2c_adap); 3852 } 3853 3854 /** 3855 * igb_remove - Device Removal Routine 3856 * @pdev: PCI device information struct 3857 * 3858 * igb_remove is called by the PCI subsystem to alert the driver 3859 * that it should release a PCI device. The could be caused by a 3860 * Hot-Plug event, or because the driver is going to be removed from 3861 * memory. 3862 **/ 3863 static void igb_remove(struct pci_dev *pdev) 3864 { 3865 struct net_device *netdev = pci_get_drvdata(pdev); 3866 struct igb_adapter *adapter = netdev_priv(netdev); 3867 struct e1000_hw *hw = &adapter->hw; 3868 3869 pm_runtime_get_noresume(&pdev->dev); 3870 #ifdef CONFIG_IGB_HWMON 3871 igb_sysfs_exit(adapter); 3872 #endif 3873 igb_remove_i2c(adapter); 3874 igb_ptp_stop(adapter); 3875 /* The watchdog timer may be rescheduled, so explicitly 3876 * disable watchdog from being rescheduled. 3877 */ 3878 set_bit(__IGB_DOWN, &adapter->state); 3879 del_timer_sync(&adapter->watchdog_timer); 3880 del_timer_sync(&adapter->phy_info_timer); 3881 3882 cancel_work_sync(&adapter->reset_task); 3883 cancel_work_sync(&adapter->watchdog_task); 3884 3885 #ifdef CONFIG_IGB_DCA 3886 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3887 dev_info(&pdev->dev, "DCA disabled\n"); 3888 dca_remove_requester(&pdev->dev); 3889 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3890 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3891 } 3892 #endif 3893 3894 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3895 * would have already happened in close and is redundant. 3896 */ 3897 igb_release_hw_control(adapter); 3898 3899 #ifdef CONFIG_PCI_IOV 3900 igb_disable_sriov(pdev, false); 3901 #endif 3902 3903 unregister_netdev(netdev); 3904 3905 igb_clear_interrupt_scheme(adapter); 3906 3907 pci_iounmap(pdev, adapter->io_addr); 3908 if (hw->flash_address) 3909 iounmap(hw->flash_address); 3910 pci_release_mem_regions(pdev); 3911 3912 kfree(adapter->mac_table); 3913 kfree(adapter->shadow_vfta); 3914 free_netdev(netdev); 3915 3916 pci_disable_device(pdev); 3917 } 3918 3919 /** 3920 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3921 * @adapter: board private structure to initialize 3922 * 3923 * This function initializes the vf specific data storage and then attempts to 3924 * allocate the VFs. The reason for ordering it this way is because it is much 3925 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3926 * the memory for the VFs. 3927 **/ 3928 static void igb_probe_vfs(struct igb_adapter *adapter) 3929 { 3930 #ifdef CONFIG_PCI_IOV 3931 struct pci_dev *pdev = adapter->pdev; 3932 struct e1000_hw *hw = &adapter->hw; 3933 3934 /* Virtualization features not supported on i210 family. */ 3935 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3936 return; 3937 3938 /* Of the below we really only want the effect of getting 3939 * IGB_FLAG_HAS_MSIX set (if available), without which 3940 * igb_enable_sriov() has no effect. 3941 */ 3942 igb_set_interrupt_capability(adapter, true); 3943 igb_reset_interrupt_capability(adapter); 3944 3945 pci_sriov_set_totalvfs(pdev, 7); 3946 igb_enable_sriov(pdev, max_vfs, false); 3947 3948 #endif /* CONFIG_PCI_IOV */ 3949 } 3950 3951 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3952 { 3953 struct e1000_hw *hw = &adapter->hw; 3954 unsigned int max_rss_queues; 3955 3956 /* Determine the maximum number of RSS queues supported. */ 3957 switch (hw->mac.type) { 3958 case e1000_i211: 3959 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3960 break; 3961 case e1000_82575: 3962 case e1000_i210: 3963 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3964 break; 3965 case e1000_i350: 3966 /* I350 cannot do RSS and SR-IOV at the same time */ 3967 if (!!adapter->vfs_allocated_count) { 3968 max_rss_queues = 1; 3969 break; 3970 } 3971 fallthrough; 3972 case e1000_82576: 3973 if (!!adapter->vfs_allocated_count) { 3974 max_rss_queues = 2; 3975 break; 3976 } 3977 fallthrough; 3978 case e1000_82580: 3979 case e1000_i354: 3980 default: 3981 max_rss_queues = IGB_MAX_RX_QUEUES; 3982 break; 3983 } 3984 3985 return max_rss_queues; 3986 } 3987 3988 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3989 { 3990 u32 max_rss_queues; 3991 3992 max_rss_queues = igb_get_max_rss_queues(adapter); 3993 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3994 3995 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3996 } 3997 3998 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3999 const u32 max_rss_queues) 4000 { 4001 struct e1000_hw *hw = &adapter->hw; 4002 4003 /* Determine if we need to pair queues. */ 4004 switch (hw->mac.type) { 4005 case e1000_82575: 4006 case e1000_i211: 4007 /* Device supports enough interrupts without queue pairing. */ 4008 break; 4009 case e1000_82576: 4010 case e1000_82580: 4011 case e1000_i350: 4012 case e1000_i354: 4013 case e1000_i210: 4014 default: 4015 /* If rss_queues > half of max_rss_queues, pair the queues in 4016 * order to conserve interrupts due to limited supply. 4017 */ 4018 if (adapter->rss_queues > (max_rss_queues / 2)) 4019 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4020 else 4021 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4022 break; 4023 } 4024 } 4025 4026 /** 4027 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4028 * @adapter: board private structure to initialize 4029 * 4030 * igb_sw_init initializes the Adapter private data structure. 4031 * Fields are initialized based on PCI device information and 4032 * OS network device settings (MTU size). 4033 **/ 4034 static int igb_sw_init(struct igb_adapter *adapter) 4035 { 4036 struct e1000_hw *hw = &adapter->hw; 4037 struct net_device *netdev = adapter->netdev; 4038 struct pci_dev *pdev = adapter->pdev; 4039 4040 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4041 4042 /* set default ring sizes */ 4043 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4044 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4045 4046 /* set default ITR values */ 4047 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4048 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4049 4050 /* set default work limits */ 4051 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4052 4053 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4054 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4055 4056 spin_lock_init(&adapter->nfc_lock); 4057 spin_lock_init(&adapter->stats64_lock); 4058 4059 /* init spinlock to avoid concurrency of VF resources */ 4060 spin_lock_init(&adapter->vfs_lock); 4061 #ifdef CONFIG_PCI_IOV 4062 switch (hw->mac.type) { 4063 case e1000_82576: 4064 case e1000_i350: 4065 if (max_vfs > 7) { 4066 dev_warn(&pdev->dev, 4067 "Maximum of 7 VFs per PF, using max\n"); 4068 max_vfs = adapter->vfs_allocated_count = 7; 4069 } else 4070 adapter->vfs_allocated_count = max_vfs; 4071 if (adapter->vfs_allocated_count) 4072 dev_warn(&pdev->dev, 4073 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4074 break; 4075 default: 4076 break; 4077 } 4078 #endif /* CONFIG_PCI_IOV */ 4079 4080 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4081 adapter->flags |= IGB_FLAG_HAS_MSIX; 4082 4083 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4084 sizeof(struct igb_mac_addr), 4085 GFP_KERNEL); 4086 if (!adapter->mac_table) 4087 return -ENOMEM; 4088 4089 igb_probe_vfs(adapter); 4090 4091 igb_init_queue_configuration(adapter); 4092 4093 /* Setup and initialize a copy of the hw vlan table array */ 4094 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4095 GFP_KERNEL); 4096 if (!adapter->shadow_vfta) 4097 return -ENOMEM; 4098 4099 /* This call may decrease the number of queues */ 4100 if (igb_init_interrupt_scheme(adapter, true)) { 4101 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4102 return -ENOMEM; 4103 } 4104 4105 /* Explicitly disable IRQ since the NIC can be in any state. */ 4106 igb_irq_disable(adapter); 4107 4108 if (hw->mac.type >= e1000_i350) 4109 adapter->flags &= ~IGB_FLAG_DMAC; 4110 4111 set_bit(__IGB_DOWN, &adapter->state); 4112 return 0; 4113 } 4114 4115 /** 4116 * __igb_open - Called when a network interface is made active 4117 * @netdev: network interface device structure 4118 * @resuming: indicates whether we are in a resume call 4119 * 4120 * Returns 0 on success, negative value on failure 4121 * 4122 * The open entry point is called when a network interface is made 4123 * active by the system (IFF_UP). At this point all resources needed 4124 * for transmit and receive operations are allocated, the interrupt 4125 * handler is registered with the OS, the watchdog timer is started, 4126 * and the stack is notified that the interface is ready. 4127 **/ 4128 static int __igb_open(struct net_device *netdev, bool resuming) 4129 { 4130 struct igb_adapter *adapter = netdev_priv(netdev); 4131 struct e1000_hw *hw = &adapter->hw; 4132 struct pci_dev *pdev = adapter->pdev; 4133 int err; 4134 int i; 4135 4136 /* disallow open during test */ 4137 if (test_bit(__IGB_TESTING, &adapter->state)) { 4138 WARN_ON(resuming); 4139 return -EBUSY; 4140 } 4141 4142 if (!resuming) 4143 pm_runtime_get_sync(&pdev->dev); 4144 4145 netif_carrier_off(netdev); 4146 4147 /* allocate transmit descriptors */ 4148 err = igb_setup_all_tx_resources(adapter); 4149 if (err) 4150 goto err_setup_tx; 4151 4152 /* allocate receive descriptors */ 4153 err = igb_setup_all_rx_resources(adapter); 4154 if (err) 4155 goto err_setup_rx; 4156 4157 igb_power_up_link(adapter); 4158 4159 /* before we allocate an interrupt, we must be ready to handle it. 4160 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4161 * as soon as we call pci_request_irq, so we have to setup our 4162 * clean_rx handler before we do so. 4163 */ 4164 igb_configure(adapter); 4165 4166 err = igb_request_irq(adapter); 4167 if (err) 4168 goto err_req_irq; 4169 4170 /* Notify the stack of the actual queue counts. */ 4171 err = netif_set_real_num_tx_queues(adapter->netdev, 4172 adapter->num_tx_queues); 4173 if (err) 4174 goto err_set_queues; 4175 4176 err = netif_set_real_num_rx_queues(adapter->netdev, 4177 adapter->num_rx_queues); 4178 if (err) 4179 goto err_set_queues; 4180 4181 /* From here on the code is the same as igb_up() */ 4182 clear_bit(__IGB_DOWN, &adapter->state); 4183 4184 for (i = 0; i < adapter->num_q_vectors; i++) 4185 napi_enable(&(adapter->q_vector[i]->napi)); 4186 4187 /* Clear any pending interrupts. */ 4188 rd32(E1000_TSICR); 4189 rd32(E1000_ICR); 4190 4191 igb_irq_enable(adapter); 4192 4193 /* notify VFs that reset has been completed */ 4194 if (adapter->vfs_allocated_count) { 4195 u32 reg_data = rd32(E1000_CTRL_EXT); 4196 4197 reg_data |= E1000_CTRL_EXT_PFRSTD; 4198 wr32(E1000_CTRL_EXT, reg_data); 4199 } 4200 4201 netif_tx_start_all_queues(netdev); 4202 4203 if (!resuming) 4204 pm_runtime_put(&pdev->dev); 4205 4206 /* start the watchdog. */ 4207 hw->mac.get_link_status = 1; 4208 schedule_work(&adapter->watchdog_task); 4209 4210 return 0; 4211 4212 err_set_queues: 4213 igb_free_irq(adapter); 4214 err_req_irq: 4215 igb_release_hw_control(adapter); 4216 igb_power_down_link(adapter); 4217 igb_free_all_rx_resources(adapter); 4218 err_setup_rx: 4219 igb_free_all_tx_resources(adapter); 4220 err_setup_tx: 4221 igb_reset(adapter); 4222 if (!resuming) 4223 pm_runtime_put(&pdev->dev); 4224 4225 return err; 4226 } 4227 4228 int igb_open(struct net_device *netdev) 4229 { 4230 return __igb_open(netdev, false); 4231 } 4232 4233 /** 4234 * __igb_close - Disables a network interface 4235 * @netdev: network interface device structure 4236 * @suspending: indicates we are in a suspend call 4237 * 4238 * Returns 0, this is not allowed to fail 4239 * 4240 * The close entry point is called when an interface is de-activated 4241 * by the OS. The hardware is still under the driver's control, but 4242 * needs to be disabled. A global MAC reset is issued to stop the 4243 * hardware, and all transmit and receive resources are freed. 4244 **/ 4245 static int __igb_close(struct net_device *netdev, bool suspending) 4246 { 4247 struct igb_adapter *adapter = netdev_priv(netdev); 4248 struct pci_dev *pdev = adapter->pdev; 4249 4250 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4251 4252 if (!suspending) 4253 pm_runtime_get_sync(&pdev->dev); 4254 4255 igb_down(adapter); 4256 igb_free_irq(adapter); 4257 4258 igb_free_all_tx_resources(adapter); 4259 igb_free_all_rx_resources(adapter); 4260 4261 if (!suspending) 4262 pm_runtime_put_sync(&pdev->dev); 4263 return 0; 4264 } 4265 4266 int igb_close(struct net_device *netdev) 4267 { 4268 if (netif_device_present(netdev) || netdev->dismantle) 4269 return __igb_close(netdev, false); 4270 return 0; 4271 } 4272 4273 /** 4274 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4275 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4276 * 4277 * Return 0 on success, negative on failure 4278 **/ 4279 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4280 { 4281 struct device *dev = tx_ring->dev; 4282 int size; 4283 4284 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4285 4286 tx_ring->tx_buffer_info = vmalloc(size); 4287 if (!tx_ring->tx_buffer_info) 4288 goto err; 4289 4290 /* round up to nearest 4K */ 4291 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4292 tx_ring->size = ALIGN(tx_ring->size, 4096); 4293 4294 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4295 &tx_ring->dma, GFP_KERNEL); 4296 if (!tx_ring->desc) 4297 goto err; 4298 4299 tx_ring->next_to_use = 0; 4300 tx_ring->next_to_clean = 0; 4301 4302 return 0; 4303 4304 err: 4305 vfree(tx_ring->tx_buffer_info); 4306 tx_ring->tx_buffer_info = NULL; 4307 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4308 return -ENOMEM; 4309 } 4310 4311 /** 4312 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4313 * (Descriptors) for all queues 4314 * @adapter: board private structure 4315 * 4316 * Return 0 on success, negative on failure 4317 **/ 4318 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4319 { 4320 struct pci_dev *pdev = adapter->pdev; 4321 int i, err = 0; 4322 4323 for (i = 0; i < adapter->num_tx_queues; i++) { 4324 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4325 if (err) { 4326 dev_err(&pdev->dev, 4327 "Allocation for Tx Queue %u failed\n", i); 4328 for (i--; i >= 0; i--) 4329 igb_free_tx_resources(adapter->tx_ring[i]); 4330 break; 4331 } 4332 } 4333 4334 return err; 4335 } 4336 4337 /** 4338 * igb_setup_tctl - configure the transmit control registers 4339 * @adapter: Board private structure 4340 **/ 4341 void igb_setup_tctl(struct igb_adapter *adapter) 4342 { 4343 struct e1000_hw *hw = &adapter->hw; 4344 u32 tctl; 4345 4346 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4347 wr32(E1000_TXDCTL(0), 0); 4348 4349 /* Program the Transmit Control Register */ 4350 tctl = rd32(E1000_TCTL); 4351 tctl &= ~E1000_TCTL_CT; 4352 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4353 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4354 4355 igb_config_collision_dist(hw); 4356 4357 /* Enable transmits */ 4358 tctl |= E1000_TCTL_EN; 4359 4360 wr32(E1000_TCTL, tctl); 4361 } 4362 4363 /** 4364 * igb_configure_tx_ring - Configure transmit ring after Reset 4365 * @adapter: board private structure 4366 * @ring: tx ring to configure 4367 * 4368 * Configure a transmit ring after a reset. 4369 **/ 4370 void igb_configure_tx_ring(struct igb_adapter *adapter, 4371 struct igb_ring *ring) 4372 { 4373 struct e1000_hw *hw = &adapter->hw; 4374 u32 txdctl = 0; 4375 u64 tdba = ring->dma; 4376 int reg_idx = ring->reg_idx; 4377 4378 wr32(E1000_TDLEN(reg_idx), 4379 ring->count * sizeof(union e1000_adv_tx_desc)); 4380 wr32(E1000_TDBAL(reg_idx), 4381 tdba & 0x00000000ffffffffULL); 4382 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4383 4384 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4385 wr32(E1000_TDH(reg_idx), 0); 4386 writel(0, ring->tail); 4387 4388 txdctl |= IGB_TX_PTHRESH; 4389 txdctl |= IGB_TX_HTHRESH << 8; 4390 txdctl |= IGB_TX_WTHRESH << 16; 4391 4392 /* reinitialize tx_buffer_info */ 4393 memset(ring->tx_buffer_info, 0, 4394 sizeof(struct igb_tx_buffer) * ring->count); 4395 4396 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4397 wr32(E1000_TXDCTL(reg_idx), txdctl); 4398 } 4399 4400 /** 4401 * igb_configure_tx - Configure transmit Unit after Reset 4402 * @adapter: board private structure 4403 * 4404 * Configure the Tx unit of the MAC after a reset. 4405 **/ 4406 static void igb_configure_tx(struct igb_adapter *adapter) 4407 { 4408 struct e1000_hw *hw = &adapter->hw; 4409 int i; 4410 4411 /* disable the queues */ 4412 for (i = 0; i < adapter->num_tx_queues; i++) 4413 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4414 4415 wrfl(); 4416 usleep_range(10000, 20000); 4417 4418 for (i = 0; i < adapter->num_tx_queues; i++) 4419 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4420 } 4421 4422 /** 4423 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4424 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4425 * 4426 * Returns 0 on success, negative on failure 4427 **/ 4428 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4429 { 4430 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4431 struct device *dev = rx_ring->dev; 4432 int size, res; 4433 4434 /* XDP RX-queue info */ 4435 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4436 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4437 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4438 rx_ring->queue_index, 0); 4439 if (res < 0) { 4440 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4441 rx_ring->queue_index); 4442 return res; 4443 } 4444 4445 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4446 4447 rx_ring->rx_buffer_info = vmalloc(size); 4448 if (!rx_ring->rx_buffer_info) 4449 goto err; 4450 4451 /* Round up to nearest 4K */ 4452 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4453 rx_ring->size = ALIGN(rx_ring->size, 4096); 4454 4455 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4456 &rx_ring->dma, GFP_KERNEL); 4457 if (!rx_ring->desc) 4458 goto err; 4459 4460 rx_ring->next_to_alloc = 0; 4461 rx_ring->next_to_clean = 0; 4462 rx_ring->next_to_use = 0; 4463 4464 rx_ring->xdp_prog = adapter->xdp_prog; 4465 4466 return 0; 4467 4468 err: 4469 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4470 vfree(rx_ring->rx_buffer_info); 4471 rx_ring->rx_buffer_info = NULL; 4472 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4473 return -ENOMEM; 4474 } 4475 4476 /** 4477 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4478 * (Descriptors) for all queues 4479 * @adapter: board private structure 4480 * 4481 * Return 0 on success, negative on failure 4482 **/ 4483 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4484 { 4485 struct pci_dev *pdev = adapter->pdev; 4486 int i, err = 0; 4487 4488 for (i = 0; i < adapter->num_rx_queues; i++) { 4489 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4490 if (err) { 4491 dev_err(&pdev->dev, 4492 "Allocation for Rx Queue %u failed\n", i); 4493 for (i--; i >= 0; i--) 4494 igb_free_rx_resources(adapter->rx_ring[i]); 4495 break; 4496 } 4497 } 4498 4499 return err; 4500 } 4501 4502 /** 4503 * igb_setup_mrqc - configure the multiple receive queue control registers 4504 * @adapter: Board private structure 4505 **/ 4506 static void igb_setup_mrqc(struct igb_adapter *adapter) 4507 { 4508 struct e1000_hw *hw = &adapter->hw; 4509 u32 mrqc, rxcsum; 4510 u32 j, num_rx_queues; 4511 u32 rss_key[10]; 4512 4513 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4514 for (j = 0; j < 10; j++) 4515 wr32(E1000_RSSRK(j), rss_key[j]); 4516 4517 num_rx_queues = adapter->rss_queues; 4518 4519 switch (hw->mac.type) { 4520 case e1000_82576: 4521 /* 82576 supports 2 RSS queues for SR-IOV */ 4522 if (adapter->vfs_allocated_count) 4523 num_rx_queues = 2; 4524 break; 4525 default: 4526 break; 4527 } 4528 4529 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4530 for (j = 0; j < IGB_RETA_SIZE; j++) 4531 adapter->rss_indir_tbl[j] = 4532 (j * num_rx_queues) / IGB_RETA_SIZE; 4533 adapter->rss_indir_tbl_init = num_rx_queues; 4534 } 4535 igb_write_rss_indir_tbl(adapter); 4536 4537 /* Disable raw packet checksumming so that RSS hash is placed in 4538 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4539 * offloads as they are enabled by default 4540 */ 4541 rxcsum = rd32(E1000_RXCSUM); 4542 rxcsum |= E1000_RXCSUM_PCSD; 4543 4544 if (adapter->hw.mac.type >= e1000_82576) 4545 /* Enable Receive Checksum Offload for SCTP */ 4546 rxcsum |= E1000_RXCSUM_CRCOFL; 4547 4548 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4549 wr32(E1000_RXCSUM, rxcsum); 4550 4551 /* Generate RSS hash based on packet types, TCP/UDP 4552 * port numbers and/or IPv4/v6 src and dst addresses 4553 */ 4554 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4555 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4556 E1000_MRQC_RSS_FIELD_IPV6 | 4557 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4558 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4559 4560 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4561 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4562 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4563 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4564 4565 /* If VMDq is enabled then we set the appropriate mode for that, else 4566 * we default to RSS so that an RSS hash is calculated per packet even 4567 * if we are only using one queue 4568 */ 4569 if (adapter->vfs_allocated_count) { 4570 if (hw->mac.type > e1000_82575) { 4571 /* Set the default pool for the PF's first queue */ 4572 u32 vtctl = rd32(E1000_VT_CTL); 4573 4574 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4575 E1000_VT_CTL_DISABLE_DEF_POOL); 4576 vtctl |= adapter->vfs_allocated_count << 4577 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4578 wr32(E1000_VT_CTL, vtctl); 4579 } 4580 if (adapter->rss_queues > 1) 4581 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4582 else 4583 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4584 } else { 4585 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4586 } 4587 igb_vmm_control(adapter); 4588 4589 wr32(E1000_MRQC, mrqc); 4590 } 4591 4592 /** 4593 * igb_setup_rctl - configure the receive control registers 4594 * @adapter: Board private structure 4595 **/ 4596 void igb_setup_rctl(struct igb_adapter *adapter) 4597 { 4598 struct e1000_hw *hw = &adapter->hw; 4599 u32 rctl; 4600 4601 rctl = rd32(E1000_RCTL); 4602 4603 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4604 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4605 4606 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4607 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4608 4609 /* enable stripping of CRC. It's unlikely this will break BMC 4610 * redirection as it did with e1000. Newer features require 4611 * that the HW strips the CRC. 4612 */ 4613 rctl |= E1000_RCTL_SECRC; 4614 4615 /* disable store bad packets and clear size bits. */ 4616 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4617 4618 /* enable LPE to allow for reception of jumbo frames */ 4619 rctl |= E1000_RCTL_LPE; 4620 4621 /* disable queue 0 to prevent tail write w/o re-config */ 4622 wr32(E1000_RXDCTL(0), 0); 4623 4624 /* Attention!!! For SR-IOV PF driver operations you must enable 4625 * queue drop for all VF and PF queues to prevent head of line blocking 4626 * if an un-trusted VF does not provide descriptors to hardware. 4627 */ 4628 if (adapter->vfs_allocated_count) { 4629 /* set all queue drop enable bits */ 4630 wr32(E1000_QDE, ALL_QUEUES); 4631 } 4632 4633 /* This is useful for sniffing bad packets. */ 4634 if (adapter->netdev->features & NETIF_F_RXALL) { 4635 /* UPE and MPE will be handled by normal PROMISC logic 4636 * in e1000e_set_rx_mode 4637 */ 4638 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4639 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4640 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4641 4642 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4643 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4644 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4645 * and that breaks VLANs. 4646 */ 4647 } 4648 4649 wr32(E1000_RCTL, rctl); 4650 } 4651 4652 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4653 int vfn) 4654 { 4655 struct e1000_hw *hw = &adapter->hw; 4656 u32 vmolr; 4657 4658 if (size > MAX_JUMBO_FRAME_SIZE) 4659 size = MAX_JUMBO_FRAME_SIZE; 4660 4661 vmolr = rd32(E1000_VMOLR(vfn)); 4662 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4663 vmolr |= size | E1000_VMOLR_LPE; 4664 wr32(E1000_VMOLR(vfn), vmolr); 4665 4666 return 0; 4667 } 4668 4669 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4670 int vfn, bool enable) 4671 { 4672 struct e1000_hw *hw = &adapter->hw; 4673 u32 val, reg; 4674 4675 if (hw->mac.type < e1000_82576) 4676 return; 4677 4678 if (hw->mac.type == e1000_i350) 4679 reg = E1000_DVMOLR(vfn); 4680 else 4681 reg = E1000_VMOLR(vfn); 4682 4683 val = rd32(reg); 4684 if (enable) 4685 val |= E1000_VMOLR_STRVLAN; 4686 else 4687 val &= ~(E1000_VMOLR_STRVLAN); 4688 wr32(reg, val); 4689 } 4690 4691 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4692 int vfn, bool aupe) 4693 { 4694 struct e1000_hw *hw = &adapter->hw; 4695 u32 vmolr; 4696 4697 /* This register exists only on 82576 and newer so if we are older then 4698 * we should exit and do nothing 4699 */ 4700 if (hw->mac.type < e1000_82576) 4701 return; 4702 4703 vmolr = rd32(E1000_VMOLR(vfn)); 4704 if (aupe) 4705 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4706 else 4707 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4708 4709 /* clear all bits that might not be set */ 4710 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4711 4712 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4713 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4714 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4715 * multicast packets 4716 */ 4717 if (vfn <= adapter->vfs_allocated_count) 4718 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4719 4720 wr32(E1000_VMOLR(vfn), vmolr); 4721 } 4722 4723 /** 4724 * igb_setup_srrctl - configure the split and replication receive control 4725 * registers 4726 * @adapter: Board private structure 4727 * @ring: receive ring to be configured 4728 **/ 4729 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4730 { 4731 struct e1000_hw *hw = &adapter->hw; 4732 int reg_idx = ring->reg_idx; 4733 u32 srrctl = 0; 4734 4735 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4736 if (ring_uses_large_buffer(ring)) 4737 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4738 else 4739 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4740 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4741 if (hw->mac.type >= e1000_82580) 4742 srrctl |= E1000_SRRCTL_TIMESTAMP; 4743 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4744 * queues and rx flow control is disabled 4745 */ 4746 if (adapter->vfs_allocated_count || 4747 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4748 adapter->num_rx_queues > 1)) 4749 srrctl |= E1000_SRRCTL_DROP_EN; 4750 4751 wr32(E1000_SRRCTL(reg_idx), srrctl); 4752 } 4753 4754 /** 4755 * igb_configure_rx_ring - Configure a receive ring after Reset 4756 * @adapter: board private structure 4757 * @ring: receive ring to be configured 4758 * 4759 * Configure the Rx unit of the MAC after a reset. 4760 **/ 4761 void igb_configure_rx_ring(struct igb_adapter *adapter, 4762 struct igb_ring *ring) 4763 { 4764 struct e1000_hw *hw = &adapter->hw; 4765 union e1000_adv_rx_desc *rx_desc; 4766 u64 rdba = ring->dma; 4767 int reg_idx = ring->reg_idx; 4768 u32 rxdctl = 0; 4769 4770 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4771 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4772 MEM_TYPE_PAGE_SHARED, NULL)); 4773 4774 /* disable the queue */ 4775 wr32(E1000_RXDCTL(reg_idx), 0); 4776 4777 /* Set DMA base address registers */ 4778 wr32(E1000_RDBAL(reg_idx), 4779 rdba & 0x00000000ffffffffULL); 4780 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4781 wr32(E1000_RDLEN(reg_idx), 4782 ring->count * sizeof(union e1000_adv_rx_desc)); 4783 4784 /* initialize head and tail */ 4785 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4786 wr32(E1000_RDH(reg_idx), 0); 4787 writel(0, ring->tail); 4788 4789 /* set descriptor configuration */ 4790 igb_setup_srrctl(adapter, ring); 4791 4792 /* set filtering for VMDQ pools */ 4793 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4794 4795 rxdctl |= IGB_RX_PTHRESH; 4796 rxdctl |= IGB_RX_HTHRESH << 8; 4797 rxdctl |= IGB_RX_WTHRESH << 16; 4798 4799 /* initialize rx_buffer_info */ 4800 memset(ring->rx_buffer_info, 0, 4801 sizeof(struct igb_rx_buffer) * ring->count); 4802 4803 /* initialize Rx descriptor 0 */ 4804 rx_desc = IGB_RX_DESC(ring, 0); 4805 rx_desc->wb.upper.length = 0; 4806 4807 /* enable receive descriptor fetching */ 4808 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4809 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4810 } 4811 4812 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4813 struct igb_ring *rx_ring) 4814 { 4815 /* set build_skb and buffer size flags */ 4816 clear_ring_build_skb_enabled(rx_ring); 4817 clear_ring_uses_large_buffer(rx_ring); 4818 4819 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4820 return; 4821 4822 set_ring_build_skb_enabled(rx_ring); 4823 4824 #if (PAGE_SIZE < 8192) 4825 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4826 return; 4827 4828 set_ring_uses_large_buffer(rx_ring); 4829 #endif 4830 } 4831 4832 /** 4833 * igb_configure_rx - Configure receive Unit after Reset 4834 * @adapter: board private structure 4835 * 4836 * Configure the Rx unit of the MAC after a reset. 4837 **/ 4838 static void igb_configure_rx(struct igb_adapter *adapter) 4839 { 4840 int i; 4841 4842 /* set the correct pool for the PF default MAC address in entry 0 */ 4843 igb_set_default_mac_filter(adapter); 4844 4845 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4846 * the Base and Length of the Rx Descriptor Ring 4847 */ 4848 for (i = 0; i < adapter->num_rx_queues; i++) { 4849 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4850 4851 igb_set_rx_buffer_len(adapter, rx_ring); 4852 igb_configure_rx_ring(adapter, rx_ring); 4853 } 4854 } 4855 4856 /** 4857 * igb_free_tx_resources - Free Tx Resources per Queue 4858 * @tx_ring: Tx descriptor ring for a specific queue 4859 * 4860 * Free all transmit software resources 4861 **/ 4862 void igb_free_tx_resources(struct igb_ring *tx_ring) 4863 { 4864 igb_clean_tx_ring(tx_ring); 4865 4866 vfree(tx_ring->tx_buffer_info); 4867 tx_ring->tx_buffer_info = NULL; 4868 4869 /* if not set, then don't free */ 4870 if (!tx_ring->desc) 4871 return; 4872 4873 dma_free_coherent(tx_ring->dev, tx_ring->size, 4874 tx_ring->desc, tx_ring->dma); 4875 4876 tx_ring->desc = NULL; 4877 } 4878 4879 /** 4880 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4881 * @adapter: board private structure 4882 * 4883 * Free all transmit software resources 4884 **/ 4885 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4886 { 4887 int i; 4888 4889 for (i = 0; i < adapter->num_tx_queues; i++) 4890 if (adapter->tx_ring[i]) 4891 igb_free_tx_resources(adapter->tx_ring[i]); 4892 } 4893 4894 /** 4895 * igb_clean_tx_ring - Free Tx Buffers 4896 * @tx_ring: ring to be cleaned 4897 **/ 4898 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4899 { 4900 u16 i = tx_ring->next_to_clean; 4901 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4902 4903 while (i != tx_ring->next_to_use) { 4904 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4905 4906 /* Free all the Tx ring sk_buffs or xdp frames */ 4907 if (tx_buffer->type == IGB_TYPE_SKB) 4908 dev_kfree_skb_any(tx_buffer->skb); 4909 else 4910 xdp_return_frame(tx_buffer->xdpf); 4911 4912 /* unmap skb header data */ 4913 dma_unmap_single(tx_ring->dev, 4914 dma_unmap_addr(tx_buffer, dma), 4915 dma_unmap_len(tx_buffer, len), 4916 DMA_TO_DEVICE); 4917 4918 /* check for eop_desc to determine the end of the packet */ 4919 eop_desc = tx_buffer->next_to_watch; 4920 tx_desc = IGB_TX_DESC(tx_ring, i); 4921 4922 /* unmap remaining buffers */ 4923 while (tx_desc != eop_desc) { 4924 tx_buffer++; 4925 tx_desc++; 4926 i++; 4927 if (unlikely(i == tx_ring->count)) { 4928 i = 0; 4929 tx_buffer = tx_ring->tx_buffer_info; 4930 tx_desc = IGB_TX_DESC(tx_ring, 0); 4931 } 4932 4933 /* unmap any remaining paged data */ 4934 if (dma_unmap_len(tx_buffer, len)) 4935 dma_unmap_page(tx_ring->dev, 4936 dma_unmap_addr(tx_buffer, dma), 4937 dma_unmap_len(tx_buffer, len), 4938 DMA_TO_DEVICE); 4939 } 4940 4941 tx_buffer->next_to_watch = NULL; 4942 4943 /* move us one more past the eop_desc for start of next pkt */ 4944 tx_buffer++; 4945 i++; 4946 if (unlikely(i == tx_ring->count)) { 4947 i = 0; 4948 tx_buffer = tx_ring->tx_buffer_info; 4949 } 4950 } 4951 4952 /* reset BQL for queue */ 4953 netdev_tx_reset_queue(txring_txq(tx_ring)); 4954 4955 /* reset next_to_use and next_to_clean */ 4956 tx_ring->next_to_use = 0; 4957 tx_ring->next_to_clean = 0; 4958 } 4959 4960 /** 4961 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4962 * @adapter: board private structure 4963 **/ 4964 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4965 { 4966 int i; 4967 4968 for (i = 0; i < adapter->num_tx_queues; i++) 4969 if (adapter->tx_ring[i]) 4970 igb_clean_tx_ring(adapter->tx_ring[i]); 4971 } 4972 4973 /** 4974 * igb_free_rx_resources - Free Rx Resources 4975 * @rx_ring: ring to clean the resources from 4976 * 4977 * Free all receive software resources 4978 **/ 4979 void igb_free_rx_resources(struct igb_ring *rx_ring) 4980 { 4981 igb_clean_rx_ring(rx_ring); 4982 4983 rx_ring->xdp_prog = NULL; 4984 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4985 vfree(rx_ring->rx_buffer_info); 4986 rx_ring->rx_buffer_info = NULL; 4987 4988 /* if not set, then don't free */ 4989 if (!rx_ring->desc) 4990 return; 4991 4992 dma_free_coherent(rx_ring->dev, rx_ring->size, 4993 rx_ring->desc, rx_ring->dma); 4994 4995 rx_ring->desc = NULL; 4996 } 4997 4998 /** 4999 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5000 * @adapter: board private structure 5001 * 5002 * Free all receive software resources 5003 **/ 5004 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5005 { 5006 int i; 5007 5008 for (i = 0; i < adapter->num_rx_queues; i++) 5009 if (adapter->rx_ring[i]) 5010 igb_free_rx_resources(adapter->rx_ring[i]); 5011 } 5012 5013 /** 5014 * igb_clean_rx_ring - Free Rx Buffers per Queue 5015 * @rx_ring: ring to free buffers from 5016 **/ 5017 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5018 { 5019 u16 i = rx_ring->next_to_clean; 5020 5021 dev_kfree_skb(rx_ring->skb); 5022 rx_ring->skb = NULL; 5023 5024 /* Free all the Rx ring sk_buffs */ 5025 while (i != rx_ring->next_to_alloc) { 5026 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5027 5028 /* Invalidate cache lines that may have been written to by 5029 * device so that we avoid corrupting memory. 5030 */ 5031 dma_sync_single_range_for_cpu(rx_ring->dev, 5032 buffer_info->dma, 5033 buffer_info->page_offset, 5034 igb_rx_bufsz(rx_ring), 5035 DMA_FROM_DEVICE); 5036 5037 /* free resources associated with mapping */ 5038 dma_unmap_page_attrs(rx_ring->dev, 5039 buffer_info->dma, 5040 igb_rx_pg_size(rx_ring), 5041 DMA_FROM_DEVICE, 5042 IGB_RX_DMA_ATTR); 5043 __page_frag_cache_drain(buffer_info->page, 5044 buffer_info->pagecnt_bias); 5045 5046 i++; 5047 if (i == rx_ring->count) 5048 i = 0; 5049 } 5050 5051 rx_ring->next_to_alloc = 0; 5052 rx_ring->next_to_clean = 0; 5053 rx_ring->next_to_use = 0; 5054 } 5055 5056 /** 5057 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5058 * @adapter: board private structure 5059 **/ 5060 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5061 { 5062 int i; 5063 5064 for (i = 0; i < adapter->num_rx_queues; i++) 5065 if (adapter->rx_ring[i]) 5066 igb_clean_rx_ring(adapter->rx_ring[i]); 5067 } 5068 5069 /** 5070 * igb_set_mac - Change the Ethernet Address of the NIC 5071 * @netdev: network interface device structure 5072 * @p: pointer to an address structure 5073 * 5074 * Returns 0 on success, negative on failure 5075 **/ 5076 static int igb_set_mac(struct net_device *netdev, void *p) 5077 { 5078 struct igb_adapter *adapter = netdev_priv(netdev); 5079 struct e1000_hw *hw = &adapter->hw; 5080 struct sockaddr *addr = p; 5081 5082 if (!is_valid_ether_addr(addr->sa_data)) 5083 return -EADDRNOTAVAIL; 5084 5085 eth_hw_addr_set(netdev, addr->sa_data); 5086 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5087 5088 /* set the correct pool for the new PF MAC address in entry 0 */ 5089 igb_set_default_mac_filter(adapter); 5090 5091 return 0; 5092 } 5093 5094 /** 5095 * igb_write_mc_addr_list - write multicast addresses to MTA 5096 * @netdev: network interface device structure 5097 * 5098 * Writes multicast address list to the MTA hash table. 5099 * Returns: -ENOMEM on failure 5100 * 0 on no addresses written 5101 * X on writing X addresses to MTA 5102 **/ 5103 static int igb_write_mc_addr_list(struct net_device *netdev) 5104 { 5105 struct igb_adapter *adapter = netdev_priv(netdev); 5106 struct e1000_hw *hw = &adapter->hw; 5107 struct netdev_hw_addr *ha; 5108 u8 *mta_list; 5109 int i; 5110 5111 if (netdev_mc_empty(netdev)) { 5112 /* nothing to program, so clear mc list */ 5113 igb_update_mc_addr_list(hw, NULL, 0); 5114 igb_restore_vf_multicasts(adapter); 5115 return 0; 5116 } 5117 5118 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5119 if (!mta_list) 5120 return -ENOMEM; 5121 5122 /* The shared function expects a packed array of only addresses. */ 5123 i = 0; 5124 netdev_for_each_mc_addr(ha, netdev) 5125 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5126 5127 igb_update_mc_addr_list(hw, mta_list, i); 5128 kfree(mta_list); 5129 5130 return netdev_mc_count(netdev); 5131 } 5132 5133 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5134 { 5135 struct e1000_hw *hw = &adapter->hw; 5136 u32 i, pf_id; 5137 5138 switch (hw->mac.type) { 5139 case e1000_i210: 5140 case e1000_i211: 5141 case e1000_i350: 5142 /* VLAN filtering needed for VLAN prio filter */ 5143 if (adapter->netdev->features & NETIF_F_NTUPLE) 5144 break; 5145 fallthrough; 5146 case e1000_82576: 5147 case e1000_82580: 5148 case e1000_i354: 5149 /* VLAN filtering needed for pool filtering */ 5150 if (adapter->vfs_allocated_count) 5151 break; 5152 fallthrough; 5153 default: 5154 return 1; 5155 } 5156 5157 /* We are already in VLAN promisc, nothing to do */ 5158 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5159 return 0; 5160 5161 if (!adapter->vfs_allocated_count) 5162 goto set_vfta; 5163 5164 /* Add PF to all active pools */ 5165 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5166 5167 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5168 u32 vlvf = rd32(E1000_VLVF(i)); 5169 5170 vlvf |= BIT(pf_id); 5171 wr32(E1000_VLVF(i), vlvf); 5172 } 5173 5174 set_vfta: 5175 /* Set all bits in the VLAN filter table array */ 5176 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5177 hw->mac.ops.write_vfta(hw, i, ~0U); 5178 5179 /* Set flag so we don't redo unnecessary work */ 5180 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5181 5182 return 0; 5183 } 5184 5185 #define VFTA_BLOCK_SIZE 8 5186 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5187 { 5188 struct e1000_hw *hw = &adapter->hw; 5189 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5190 u32 vid_start = vfta_offset * 32; 5191 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5192 u32 i, vid, word, bits, pf_id; 5193 5194 /* guarantee that we don't scrub out management VLAN */ 5195 vid = adapter->mng_vlan_id; 5196 if (vid >= vid_start && vid < vid_end) 5197 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5198 5199 if (!adapter->vfs_allocated_count) 5200 goto set_vfta; 5201 5202 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5203 5204 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5205 u32 vlvf = rd32(E1000_VLVF(i)); 5206 5207 /* pull VLAN ID from VLVF */ 5208 vid = vlvf & VLAN_VID_MASK; 5209 5210 /* only concern ourselves with a certain range */ 5211 if (vid < vid_start || vid >= vid_end) 5212 continue; 5213 5214 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5215 /* record VLAN ID in VFTA */ 5216 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5217 5218 /* if PF is part of this then continue */ 5219 if (test_bit(vid, adapter->active_vlans)) 5220 continue; 5221 } 5222 5223 /* remove PF from the pool */ 5224 bits = ~BIT(pf_id); 5225 bits &= rd32(E1000_VLVF(i)); 5226 wr32(E1000_VLVF(i), bits); 5227 } 5228 5229 set_vfta: 5230 /* extract values from active_vlans and write back to VFTA */ 5231 for (i = VFTA_BLOCK_SIZE; i--;) { 5232 vid = (vfta_offset + i) * 32; 5233 word = vid / BITS_PER_LONG; 5234 bits = vid % BITS_PER_LONG; 5235 5236 vfta[i] |= adapter->active_vlans[word] >> bits; 5237 5238 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5239 } 5240 } 5241 5242 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5243 { 5244 u32 i; 5245 5246 /* We are not in VLAN promisc, nothing to do */ 5247 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5248 return; 5249 5250 /* Set flag so we don't redo unnecessary work */ 5251 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5252 5253 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5254 igb_scrub_vfta(adapter, i); 5255 } 5256 5257 /** 5258 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5259 * @netdev: network interface device structure 5260 * 5261 * The set_rx_mode entry point is called whenever the unicast or multicast 5262 * address lists or the network interface flags are updated. This routine is 5263 * responsible for configuring the hardware for proper unicast, multicast, 5264 * promiscuous mode, and all-multi behavior. 5265 **/ 5266 static void igb_set_rx_mode(struct net_device *netdev) 5267 { 5268 struct igb_adapter *adapter = netdev_priv(netdev); 5269 struct e1000_hw *hw = &adapter->hw; 5270 unsigned int vfn = adapter->vfs_allocated_count; 5271 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5272 int count; 5273 5274 /* Check for Promiscuous and All Multicast modes */ 5275 if (netdev->flags & IFF_PROMISC) { 5276 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5277 vmolr |= E1000_VMOLR_MPME; 5278 5279 /* enable use of UTA filter to force packets to default pool */ 5280 if (hw->mac.type == e1000_82576) 5281 vmolr |= E1000_VMOLR_ROPE; 5282 } else { 5283 if (netdev->flags & IFF_ALLMULTI) { 5284 rctl |= E1000_RCTL_MPE; 5285 vmolr |= E1000_VMOLR_MPME; 5286 } else { 5287 /* Write addresses to the MTA, if the attempt fails 5288 * then we should just turn on promiscuous mode so 5289 * that we can at least receive multicast traffic 5290 */ 5291 count = igb_write_mc_addr_list(netdev); 5292 if (count < 0) { 5293 rctl |= E1000_RCTL_MPE; 5294 vmolr |= E1000_VMOLR_MPME; 5295 } else if (count) { 5296 vmolr |= E1000_VMOLR_ROMPE; 5297 } 5298 } 5299 } 5300 5301 /* Write addresses to available RAR registers, if there is not 5302 * sufficient space to store all the addresses then enable 5303 * unicast promiscuous mode 5304 */ 5305 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5306 rctl |= E1000_RCTL_UPE; 5307 vmolr |= E1000_VMOLR_ROPE; 5308 } 5309 5310 /* enable VLAN filtering by default */ 5311 rctl |= E1000_RCTL_VFE; 5312 5313 /* disable VLAN filtering for modes that require it */ 5314 if ((netdev->flags & IFF_PROMISC) || 5315 (netdev->features & NETIF_F_RXALL)) { 5316 /* if we fail to set all rules then just clear VFE */ 5317 if (igb_vlan_promisc_enable(adapter)) 5318 rctl &= ~E1000_RCTL_VFE; 5319 } else { 5320 igb_vlan_promisc_disable(adapter); 5321 } 5322 5323 /* update state of unicast, multicast, and VLAN filtering modes */ 5324 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5325 E1000_RCTL_VFE); 5326 wr32(E1000_RCTL, rctl); 5327 5328 #if (PAGE_SIZE < 8192) 5329 if (!adapter->vfs_allocated_count) { 5330 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5331 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5332 } 5333 #endif 5334 wr32(E1000_RLPML, rlpml); 5335 5336 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5337 * the VMOLR to enable the appropriate modes. Without this workaround 5338 * we will have issues with VLAN tag stripping not being done for frames 5339 * that are only arriving because we are the default pool 5340 */ 5341 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5342 return; 5343 5344 /* set UTA to appropriate mode */ 5345 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5346 5347 vmolr |= rd32(E1000_VMOLR(vfn)) & 5348 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5349 5350 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5351 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5352 #if (PAGE_SIZE < 8192) 5353 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5354 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5355 else 5356 #endif 5357 vmolr |= MAX_JUMBO_FRAME_SIZE; 5358 vmolr |= E1000_VMOLR_LPE; 5359 5360 wr32(E1000_VMOLR(vfn), vmolr); 5361 5362 igb_restore_vf_multicasts(adapter); 5363 } 5364 5365 static void igb_check_wvbr(struct igb_adapter *adapter) 5366 { 5367 struct e1000_hw *hw = &adapter->hw; 5368 u32 wvbr = 0; 5369 5370 switch (hw->mac.type) { 5371 case e1000_82576: 5372 case e1000_i350: 5373 wvbr = rd32(E1000_WVBR); 5374 if (!wvbr) 5375 return; 5376 break; 5377 default: 5378 break; 5379 } 5380 5381 adapter->wvbr |= wvbr; 5382 } 5383 5384 #define IGB_STAGGERED_QUEUE_OFFSET 8 5385 5386 static void igb_spoof_check(struct igb_adapter *adapter) 5387 { 5388 int j; 5389 5390 if (!adapter->wvbr) 5391 return; 5392 5393 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5394 if (adapter->wvbr & BIT(j) || 5395 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5396 dev_warn(&adapter->pdev->dev, 5397 "Spoof event(s) detected on VF %d\n", j); 5398 adapter->wvbr &= 5399 ~(BIT(j) | 5400 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5401 } 5402 } 5403 } 5404 5405 /* Need to wait a few seconds after link up to get diagnostic information from 5406 * the phy 5407 */ 5408 static void igb_update_phy_info(struct timer_list *t) 5409 { 5410 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5411 igb_get_phy_info(&adapter->hw); 5412 } 5413 5414 /** 5415 * igb_has_link - check shared code for link and determine up/down 5416 * @adapter: pointer to driver private info 5417 **/ 5418 bool igb_has_link(struct igb_adapter *adapter) 5419 { 5420 struct e1000_hw *hw = &adapter->hw; 5421 bool link_active = false; 5422 5423 /* get_link_status is set on LSC (link status) interrupt or 5424 * rx sequence error interrupt. get_link_status will stay 5425 * false until the e1000_check_for_link establishes link 5426 * for copper adapters ONLY 5427 */ 5428 switch (hw->phy.media_type) { 5429 case e1000_media_type_copper: 5430 if (!hw->mac.get_link_status) 5431 return true; 5432 fallthrough; 5433 case e1000_media_type_internal_serdes: 5434 hw->mac.ops.check_for_link(hw); 5435 link_active = !hw->mac.get_link_status; 5436 break; 5437 default: 5438 case e1000_media_type_unknown: 5439 break; 5440 } 5441 5442 if (((hw->mac.type == e1000_i210) || 5443 (hw->mac.type == e1000_i211)) && 5444 (hw->phy.id == I210_I_PHY_ID)) { 5445 if (!netif_carrier_ok(adapter->netdev)) { 5446 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5447 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5448 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5449 adapter->link_check_timeout = jiffies; 5450 } 5451 } 5452 5453 return link_active; 5454 } 5455 5456 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5457 { 5458 bool ret = false; 5459 u32 ctrl_ext, thstat; 5460 5461 /* check for thermal sensor event on i350 copper only */ 5462 if (hw->mac.type == e1000_i350) { 5463 thstat = rd32(E1000_THSTAT); 5464 ctrl_ext = rd32(E1000_CTRL_EXT); 5465 5466 if ((hw->phy.media_type == e1000_media_type_copper) && 5467 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5468 ret = !!(thstat & event); 5469 } 5470 5471 return ret; 5472 } 5473 5474 /** 5475 * igb_check_lvmmc - check for malformed packets received 5476 * and indicated in LVMMC register 5477 * @adapter: pointer to adapter 5478 **/ 5479 static void igb_check_lvmmc(struct igb_adapter *adapter) 5480 { 5481 struct e1000_hw *hw = &adapter->hw; 5482 u32 lvmmc; 5483 5484 lvmmc = rd32(E1000_LVMMC); 5485 if (lvmmc) { 5486 if (unlikely(net_ratelimit())) { 5487 netdev_warn(adapter->netdev, 5488 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5489 lvmmc); 5490 } 5491 } 5492 } 5493 5494 /** 5495 * igb_watchdog - Timer Call-back 5496 * @t: pointer to timer_list containing our private info pointer 5497 **/ 5498 static void igb_watchdog(struct timer_list *t) 5499 { 5500 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5501 /* Do the rest outside of interrupt context */ 5502 schedule_work(&adapter->watchdog_task); 5503 } 5504 5505 static void igb_watchdog_task(struct work_struct *work) 5506 { 5507 struct igb_adapter *adapter = container_of(work, 5508 struct igb_adapter, 5509 watchdog_task); 5510 struct e1000_hw *hw = &adapter->hw; 5511 struct e1000_phy_info *phy = &hw->phy; 5512 struct net_device *netdev = adapter->netdev; 5513 u32 link; 5514 int i; 5515 u32 connsw; 5516 u16 phy_data, retry_count = 20; 5517 5518 link = igb_has_link(adapter); 5519 5520 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5521 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5522 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5523 else 5524 link = false; 5525 } 5526 5527 /* Force link down if we have fiber to swap to */ 5528 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5529 if (hw->phy.media_type == e1000_media_type_copper) { 5530 connsw = rd32(E1000_CONNSW); 5531 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5532 link = 0; 5533 } 5534 } 5535 if (link) { 5536 /* Perform a reset if the media type changed. */ 5537 if (hw->dev_spec._82575.media_changed) { 5538 hw->dev_spec._82575.media_changed = false; 5539 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5540 igb_reset(adapter); 5541 } 5542 /* Cancel scheduled suspend requests. */ 5543 pm_runtime_resume(netdev->dev.parent); 5544 5545 if (!netif_carrier_ok(netdev)) { 5546 u32 ctrl; 5547 5548 hw->mac.ops.get_speed_and_duplex(hw, 5549 &adapter->link_speed, 5550 &adapter->link_duplex); 5551 5552 ctrl = rd32(E1000_CTRL); 5553 /* Links status message must follow this format */ 5554 netdev_info(netdev, 5555 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5556 netdev->name, 5557 adapter->link_speed, 5558 adapter->link_duplex == FULL_DUPLEX ? 5559 "Full" : "Half", 5560 (ctrl & E1000_CTRL_TFCE) && 5561 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5562 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5563 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5564 5565 /* disable EEE if enabled */ 5566 if ((adapter->flags & IGB_FLAG_EEE) && 5567 (adapter->link_duplex == HALF_DUPLEX)) { 5568 dev_info(&adapter->pdev->dev, 5569 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5570 adapter->hw.dev_spec._82575.eee_disable = true; 5571 adapter->flags &= ~IGB_FLAG_EEE; 5572 } 5573 5574 /* check if SmartSpeed worked */ 5575 igb_check_downshift(hw); 5576 if (phy->speed_downgraded) 5577 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5578 5579 /* check for thermal sensor event */ 5580 if (igb_thermal_sensor_event(hw, 5581 E1000_THSTAT_LINK_THROTTLE)) 5582 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5583 5584 /* adjust timeout factor according to speed/duplex */ 5585 adapter->tx_timeout_factor = 1; 5586 switch (adapter->link_speed) { 5587 case SPEED_10: 5588 adapter->tx_timeout_factor = 14; 5589 break; 5590 case SPEED_100: 5591 /* maybe add some timeout factor ? */ 5592 break; 5593 } 5594 5595 if (adapter->link_speed != SPEED_1000 || 5596 !hw->phy.ops.read_reg) 5597 goto no_wait; 5598 5599 /* wait for Remote receiver status OK */ 5600 retry_read_status: 5601 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5602 &phy_data)) { 5603 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5604 retry_count) { 5605 msleep(100); 5606 retry_count--; 5607 goto retry_read_status; 5608 } else if (!retry_count) { 5609 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5610 } 5611 } else { 5612 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5613 } 5614 no_wait: 5615 netif_carrier_on(netdev); 5616 5617 igb_ping_all_vfs(adapter); 5618 igb_check_vf_rate_limit(adapter); 5619 5620 /* link state has changed, schedule phy info update */ 5621 if (!test_bit(__IGB_DOWN, &adapter->state)) 5622 mod_timer(&adapter->phy_info_timer, 5623 round_jiffies(jiffies + 2 * HZ)); 5624 } 5625 } else { 5626 if (netif_carrier_ok(netdev)) { 5627 adapter->link_speed = 0; 5628 adapter->link_duplex = 0; 5629 5630 /* check for thermal sensor event */ 5631 if (igb_thermal_sensor_event(hw, 5632 E1000_THSTAT_PWR_DOWN)) { 5633 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5634 } 5635 5636 /* Links status message must follow this format */ 5637 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5638 netdev->name); 5639 netif_carrier_off(netdev); 5640 5641 igb_ping_all_vfs(adapter); 5642 5643 /* link state has changed, schedule phy info update */ 5644 if (!test_bit(__IGB_DOWN, &adapter->state)) 5645 mod_timer(&adapter->phy_info_timer, 5646 round_jiffies(jiffies + 2 * HZ)); 5647 5648 /* link is down, time to check for alternate media */ 5649 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5650 igb_check_swap_media(adapter); 5651 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5652 schedule_work(&adapter->reset_task); 5653 /* return immediately */ 5654 return; 5655 } 5656 } 5657 pm_schedule_suspend(netdev->dev.parent, 5658 MSEC_PER_SEC * 5); 5659 5660 /* also check for alternate media here */ 5661 } else if (!netif_carrier_ok(netdev) && 5662 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5663 igb_check_swap_media(adapter); 5664 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5665 schedule_work(&adapter->reset_task); 5666 /* return immediately */ 5667 return; 5668 } 5669 } 5670 } 5671 5672 spin_lock(&adapter->stats64_lock); 5673 igb_update_stats(adapter); 5674 spin_unlock(&adapter->stats64_lock); 5675 5676 for (i = 0; i < adapter->num_tx_queues; i++) { 5677 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5678 if (!netif_carrier_ok(netdev)) { 5679 /* We've lost link, so the controller stops DMA, 5680 * but we've got queued Tx work that's never going 5681 * to get done, so reset controller to flush Tx. 5682 * (Do the reset outside of interrupt context). 5683 */ 5684 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5685 adapter->tx_timeout_count++; 5686 schedule_work(&adapter->reset_task); 5687 /* return immediately since reset is imminent */ 5688 return; 5689 } 5690 } 5691 5692 /* Force detection of hung controller every watchdog period */ 5693 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5694 } 5695 5696 /* Cause software interrupt to ensure Rx ring is cleaned */ 5697 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5698 u32 eics = 0; 5699 5700 for (i = 0; i < adapter->num_q_vectors; i++) 5701 eics |= adapter->q_vector[i]->eims_value; 5702 wr32(E1000_EICS, eics); 5703 } else { 5704 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5705 } 5706 5707 igb_spoof_check(adapter); 5708 igb_ptp_rx_hang(adapter); 5709 igb_ptp_tx_hang(adapter); 5710 5711 /* Check LVMMC register on i350/i354 only */ 5712 if ((adapter->hw.mac.type == e1000_i350) || 5713 (adapter->hw.mac.type == e1000_i354)) 5714 igb_check_lvmmc(adapter); 5715 5716 /* Reset the timer */ 5717 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5718 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5719 mod_timer(&adapter->watchdog_timer, 5720 round_jiffies(jiffies + HZ)); 5721 else 5722 mod_timer(&adapter->watchdog_timer, 5723 round_jiffies(jiffies + 2 * HZ)); 5724 } 5725 } 5726 5727 enum latency_range { 5728 lowest_latency = 0, 5729 low_latency = 1, 5730 bulk_latency = 2, 5731 latency_invalid = 255 5732 }; 5733 5734 /** 5735 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5736 * @q_vector: pointer to q_vector 5737 * 5738 * Stores a new ITR value based on strictly on packet size. This 5739 * algorithm is less sophisticated than that used in igb_update_itr, 5740 * due to the difficulty of synchronizing statistics across multiple 5741 * receive rings. The divisors and thresholds used by this function 5742 * were determined based on theoretical maximum wire speed and testing 5743 * data, in order to minimize response time while increasing bulk 5744 * throughput. 5745 * This functionality is controlled by ethtool's coalescing settings. 5746 * NOTE: This function is called only when operating in a multiqueue 5747 * receive environment. 5748 **/ 5749 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5750 { 5751 int new_val = q_vector->itr_val; 5752 int avg_wire_size = 0; 5753 struct igb_adapter *adapter = q_vector->adapter; 5754 unsigned int packets; 5755 5756 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5757 * ints/sec - ITR timer value of 120 ticks. 5758 */ 5759 if (adapter->link_speed != SPEED_1000) { 5760 new_val = IGB_4K_ITR; 5761 goto set_itr_val; 5762 } 5763 5764 packets = q_vector->rx.total_packets; 5765 if (packets) 5766 avg_wire_size = q_vector->rx.total_bytes / packets; 5767 5768 packets = q_vector->tx.total_packets; 5769 if (packets) 5770 avg_wire_size = max_t(u32, avg_wire_size, 5771 q_vector->tx.total_bytes / packets); 5772 5773 /* if avg_wire_size isn't set no work was done */ 5774 if (!avg_wire_size) 5775 goto clear_counts; 5776 5777 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5778 avg_wire_size += 24; 5779 5780 /* Don't starve jumbo frames */ 5781 avg_wire_size = min(avg_wire_size, 3000); 5782 5783 /* Give a little boost to mid-size frames */ 5784 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5785 new_val = avg_wire_size / 3; 5786 else 5787 new_val = avg_wire_size / 2; 5788 5789 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5790 if (new_val < IGB_20K_ITR && 5791 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5792 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5793 new_val = IGB_20K_ITR; 5794 5795 set_itr_val: 5796 if (new_val != q_vector->itr_val) { 5797 q_vector->itr_val = new_val; 5798 q_vector->set_itr = 1; 5799 } 5800 clear_counts: 5801 q_vector->rx.total_bytes = 0; 5802 q_vector->rx.total_packets = 0; 5803 q_vector->tx.total_bytes = 0; 5804 q_vector->tx.total_packets = 0; 5805 } 5806 5807 /** 5808 * igb_update_itr - update the dynamic ITR value based on statistics 5809 * @q_vector: pointer to q_vector 5810 * @ring_container: ring info to update the itr for 5811 * 5812 * Stores a new ITR value based on packets and byte 5813 * counts during the last interrupt. The advantage of per interrupt 5814 * computation is faster updates and more accurate ITR for the current 5815 * traffic pattern. Constants in this function were computed 5816 * based on theoretical maximum wire speed and thresholds were set based 5817 * on testing data as well as attempting to minimize response time 5818 * while increasing bulk throughput. 5819 * This functionality is controlled by ethtool's coalescing settings. 5820 * NOTE: These calculations are only valid when operating in a single- 5821 * queue environment. 5822 **/ 5823 static void igb_update_itr(struct igb_q_vector *q_vector, 5824 struct igb_ring_container *ring_container) 5825 { 5826 unsigned int packets = ring_container->total_packets; 5827 unsigned int bytes = ring_container->total_bytes; 5828 u8 itrval = ring_container->itr; 5829 5830 /* no packets, exit with status unchanged */ 5831 if (packets == 0) 5832 return; 5833 5834 switch (itrval) { 5835 case lowest_latency: 5836 /* handle TSO and jumbo frames */ 5837 if (bytes/packets > 8000) 5838 itrval = bulk_latency; 5839 else if ((packets < 5) && (bytes > 512)) 5840 itrval = low_latency; 5841 break; 5842 case low_latency: /* 50 usec aka 20000 ints/s */ 5843 if (bytes > 10000) { 5844 /* this if handles the TSO accounting */ 5845 if (bytes/packets > 8000) 5846 itrval = bulk_latency; 5847 else if ((packets < 10) || ((bytes/packets) > 1200)) 5848 itrval = bulk_latency; 5849 else if ((packets > 35)) 5850 itrval = lowest_latency; 5851 } else if (bytes/packets > 2000) { 5852 itrval = bulk_latency; 5853 } else if (packets <= 2 && bytes < 512) { 5854 itrval = lowest_latency; 5855 } 5856 break; 5857 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5858 if (bytes > 25000) { 5859 if (packets > 35) 5860 itrval = low_latency; 5861 } else if (bytes < 1500) { 5862 itrval = low_latency; 5863 } 5864 break; 5865 } 5866 5867 /* clear work counters since we have the values we need */ 5868 ring_container->total_bytes = 0; 5869 ring_container->total_packets = 0; 5870 5871 /* write updated itr to ring container */ 5872 ring_container->itr = itrval; 5873 } 5874 5875 static void igb_set_itr(struct igb_q_vector *q_vector) 5876 { 5877 struct igb_adapter *adapter = q_vector->adapter; 5878 u32 new_itr = q_vector->itr_val; 5879 u8 current_itr = 0; 5880 5881 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5882 if (adapter->link_speed != SPEED_1000) { 5883 current_itr = 0; 5884 new_itr = IGB_4K_ITR; 5885 goto set_itr_now; 5886 } 5887 5888 igb_update_itr(q_vector, &q_vector->tx); 5889 igb_update_itr(q_vector, &q_vector->rx); 5890 5891 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5892 5893 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5894 if (current_itr == lowest_latency && 5895 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5896 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5897 current_itr = low_latency; 5898 5899 switch (current_itr) { 5900 /* counts and packets in update_itr are dependent on these numbers */ 5901 case lowest_latency: 5902 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5903 break; 5904 case low_latency: 5905 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5906 break; 5907 case bulk_latency: 5908 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5909 break; 5910 default: 5911 break; 5912 } 5913 5914 set_itr_now: 5915 if (new_itr != q_vector->itr_val) { 5916 /* this attempts to bias the interrupt rate towards Bulk 5917 * by adding intermediate steps when interrupt rate is 5918 * increasing 5919 */ 5920 new_itr = new_itr > q_vector->itr_val ? 5921 max((new_itr * q_vector->itr_val) / 5922 (new_itr + (q_vector->itr_val >> 2)), 5923 new_itr) : new_itr; 5924 /* Don't write the value here; it resets the adapter's 5925 * internal timer, and causes us to delay far longer than 5926 * we should between interrupts. Instead, we write the ITR 5927 * value at the beginning of the next interrupt so the timing 5928 * ends up being correct. 5929 */ 5930 q_vector->itr_val = new_itr; 5931 q_vector->set_itr = 1; 5932 } 5933 } 5934 5935 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5936 struct igb_tx_buffer *first, 5937 u32 vlan_macip_lens, u32 type_tucmd, 5938 u32 mss_l4len_idx) 5939 { 5940 struct e1000_adv_tx_context_desc *context_desc; 5941 u16 i = tx_ring->next_to_use; 5942 struct timespec64 ts; 5943 5944 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5945 5946 i++; 5947 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5948 5949 /* set bits to identify this as an advanced context descriptor */ 5950 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5951 5952 /* For 82575, context index must be unique per ring. */ 5953 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5954 mss_l4len_idx |= tx_ring->reg_idx << 4; 5955 5956 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5957 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5958 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5959 5960 /* We assume there is always a valid tx time available. Invalid times 5961 * should have been handled by the upper layers. 5962 */ 5963 if (tx_ring->launchtime_enable) { 5964 ts = ktime_to_timespec64(first->skb->tstamp); 5965 skb_txtime_consumed(first->skb); 5966 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5967 } else { 5968 context_desc->seqnum_seed = 0; 5969 } 5970 } 5971 5972 static int igb_tso(struct igb_ring *tx_ring, 5973 struct igb_tx_buffer *first, 5974 u8 *hdr_len) 5975 { 5976 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5977 struct sk_buff *skb = first->skb; 5978 union { 5979 struct iphdr *v4; 5980 struct ipv6hdr *v6; 5981 unsigned char *hdr; 5982 } ip; 5983 union { 5984 struct tcphdr *tcp; 5985 struct udphdr *udp; 5986 unsigned char *hdr; 5987 } l4; 5988 u32 paylen, l4_offset; 5989 int err; 5990 5991 if (skb->ip_summed != CHECKSUM_PARTIAL) 5992 return 0; 5993 5994 if (!skb_is_gso(skb)) 5995 return 0; 5996 5997 err = skb_cow_head(skb, 0); 5998 if (err < 0) 5999 return err; 6000 6001 ip.hdr = skb_network_header(skb); 6002 l4.hdr = skb_checksum_start(skb); 6003 6004 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6005 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6006 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6007 6008 /* initialize outer IP header fields */ 6009 if (ip.v4->version == 4) { 6010 unsigned char *csum_start = skb_checksum_start(skb); 6011 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6012 6013 /* IP header will have to cancel out any data that 6014 * is not a part of the outer IP header 6015 */ 6016 ip.v4->check = csum_fold(csum_partial(trans_start, 6017 csum_start - trans_start, 6018 0)); 6019 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6020 6021 ip.v4->tot_len = 0; 6022 first->tx_flags |= IGB_TX_FLAGS_TSO | 6023 IGB_TX_FLAGS_CSUM | 6024 IGB_TX_FLAGS_IPV4; 6025 } else { 6026 ip.v6->payload_len = 0; 6027 first->tx_flags |= IGB_TX_FLAGS_TSO | 6028 IGB_TX_FLAGS_CSUM; 6029 } 6030 6031 /* determine offset of inner transport header */ 6032 l4_offset = l4.hdr - skb->data; 6033 6034 /* remove payload length from inner checksum */ 6035 paylen = skb->len - l4_offset; 6036 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6037 /* compute length of segmentation header */ 6038 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6039 csum_replace_by_diff(&l4.tcp->check, 6040 (__force __wsum)htonl(paylen)); 6041 } else { 6042 /* compute length of segmentation header */ 6043 *hdr_len = sizeof(*l4.udp) + l4_offset; 6044 csum_replace_by_diff(&l4.udp->check, 6045 (__force __wsum)htonl(paylen)); 6046 } 6047 6048 /* update gso size and bytecount with header size */ 6049 first->gso_segs = skb_shinfo(skb)->gso_segs; 6050 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6051 6052 /* MSS L4LEN IDX */ 6053 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6054 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6055 6056 /* VLAN MACLEN IPLEN */ 6057 vlan_macip_lens = l4.hdr - ip.hdr; 6058 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6059 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6060 6061 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6062 type_tucmd, mss_l4len_idx); 6063 6064 return 1; 6065 } 6066 6067 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6068 { 6069 struct sk_buff *skb = first->skb; 6070 u32 vlan_macip_lens = 0; 6071 u32 type_tucmd = 0; 6072 6073 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6074 csum_failed: 6075 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6076 !tx_ring->launchtime_enable) 6077 return; 6078 goto no_csum; 6079 } 6080 6081 switch (skb->csum_offset) { 6082 case offsetof(struct tcphdr, check): 6083 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6084 fallthrough; 6085 case offsetof(struct udphdr, check): 6086 break; 6087 case offsetof(struct sctphdr, checksum): 6088 /* validate that this is actually an SCTP request */ 6089 if (skb_csum_is_sctp(skb)) { 6090 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6091 break; 6092 } 6093 fallthrough; 6094 default: 6095 skb_checksum_help(skb); 6096 goto csum_failed; 6097 } 6098 6099 /* update TX checksum flag */ 6100 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6101 vlan_macip_lens = skb_checksum_start_offset(skb) - 6102 skb_network_offset(skb); 6103 no_csum: 6104 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6105 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6106 6107 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6108 } 6109 6110 #define IGB_SET_FLAG(_input, _flag, _result) \ 6111 ((_flag <= _result) ? \ 6112 ((u32)(_input & _flag) * (_result / _flag)) : \ 6113 ((u32)(_input & _flag) / (_flag / _result))) 6114 6115 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6116 { 6117 /* set type for advanced descriptor with frame checksum insertion */ 6118 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6119 E1000_ADVTXD_DCMD_DEXT | 6120 E1000_ADVTXD_DCMD_IFCS; 6121 6122 /* set HW vlan bit if vlan is present */ 6123 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6124 (E1000_ADVTXD_DCMD_VLE)); 6125 6126 /* set segmentation bits for TSO */ 6127 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6128 (E1000_ADVTXD_DCMD_TSE)); 6129 6130 /* set timestamp bit if present */ 6131 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6132 (E1000_ADVTXD_MAC_TSTAMP)); 6133 6134 /* insert frame checksum */ 6135 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6136 6137 return cmd_type; 6138 } 6139 6140 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6141 union e1000_adv_tx_desc *tx_desc, 6142 u32 tx_flags, unsigned int paylen) 6143 { 6144 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6145 6146 /* 82575 requires a unique index per ring */ 6147 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6148 olinfo_status |= tx_ring->reg_idx << 4; 6149 6150 /* insert L4 checksum */ 6151 olinfo_status |= IGB_SET_FLAG(tx_flags, 6152 IGB_TX_FLAGS_CSUM, 6153 (E1000_TXD_POPTS_TXSM << 8)); 6154 6155 /* insert IPv4 checksum */ 6156 olinfo_status |= IGB_SET_FLAG(tx_flags, 6157 IGB_TX_FLAGS_IPV4, 6158 (E1000_TXD_POPTS_IXSM << 8)); 6159 6160 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6161 } 6162 6163 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6164 { 6165 struct net_device *netdev = tx_ring->netdev; 6166 6167 netif_stop_subqueue(netdev, tx_ring->queue_index); 6168 6169 /* Herbert's original patch had: 6170 * smp_mb__after_netif_stop_queue(); 6171 * but since that doesn't exist yet, just open code it. 6172 */ 6173 smp_mb(); 6174 6175 /* We need to check again in a case another CPU has just 6176 * made room available. 6177 */ 6178 if (igb_desc_unused(tx_ring) < size) 6179 return -EBUSY; 6180 6181 /* A reprieve! */ 6182 netif_wake_subqueue(netdev, tx_ring->queue_index); 6183 6184 u64_stats_update_begin(&tx_ring->tx_syncp2); 6185 tx_ring->tx_stats.restart_queue2++; 6186 u64_stats_update_end(&tx_ring->tx_syncp2); 6187 6188 return 0; 6189 } 6190 6191 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6192 { 6193 if (igb_desc_unused(tx_ring) >= size) 6194 return 0; 6195 return __igb_maybe_stop_tx(tx_ring, size); 6196 } 6197 6198 static int igb_tx_map(struct igb_ring *tx_ring, 6199 struct igb_tx_buffer *first, 6200 const u8 hdr_len) 6201 { 6202 struct sk_buff *skb = first->skb; 6203 struct igb_tx_buffer *tx_buffer; 6204 union e1000_adv_tx_desc *tx_desc; 6205 skb_frag_t *frag; 6206 dma_addr_t dma; 6207 unsigned int data_len, size; 6208 u32 tx_flags = first->tx_flags; 6209 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6210 u16 i = tx_ring->next_to_use; 6211 6212 tx_desc = IGB_TX_DESC(tx_ring, i); 6213 6214 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6215 6216 size = skb_headlen(skb); 6217 data_len = skb->data_len; 6218 6219 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6220 6221 tx_buffer = first; 6222 6223 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6224 if (dma_mapping_error(tx_ring->dev, dma)) 6225 goto dma_error; 6226 6227 /* record length, and DMA address */ 6228 dma_unmap_len_set(tx_buffer, len, size); 6229 dma_unmap_addr_set(tx_buffer, dma, dma); 6230 6231 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6232 6233 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6234 tx_desc->read.cmd_type_len = 6235 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6236 6237 i++; 6238 tx_desc++; 6239 if (i == tx_ring->count) { 6240 tx_desc = IGB_TX_DESC(tx_ring, 0); 6241 i = 0; 6242 } 6243 tx_desc->read.olinfo_status = 0; 6244 6245 dma += IGB_MAX_DATA_PER_TXD; 6246 size -= IGB_MAX_DATA_PER_TXD; 6247 6248 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6249 } 6250 6251 if (likely(!data_len)) 6252 break; 6253 6254 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6255 6256 i++; 6257 tx_desc++; 6258 if (i == tx_ring->count) { 6259 tx_desc = IGB_TX_DESC(tx_ring, 0); 6260 i = 0; 6261 } 6262 tx_desc->read.olinfo_status = 0; 6263 6264 size = skb_frag_size(frag); 6265 data_len -= size; 6266 6267 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6268 size, DMA_TO_DEVICE); 6269 6270 tx_buffer = &tx_ring->tx_buffer_info[i]; 6271 } 6272 6273 /* write last descriptor with RS and EOP bits */ 6274 cmd_type |= size | IGB_TXD_DCMD; 6275 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6276 6277 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6278 6279 /* set the timestamp */ 6280 first->time_stamp = jiffies; 6281 6282 skb_tx_timestamp(skb); 6283 6284 /* Force memory writes to complete before letting h/w know there 6285 * are new descriptors to fetch. (Only applicable for weak-ordered 6286 * memory model archs, such as IA-64). 6287 * 6288 * We also need this memory barrier to make certain all of the 6289 * status bits have been updated before next_to_watch is written. 6290 */ 6291 dma_wmb(); 6292 6293 /* set next_to_watch value indicating a packet is present */ 6294 first->next_to_watch = tx_desc; 6295 6296 i++; 6297 if (i == tx_ring->count) 6298 i = 0; 6299 6300 tx_ring->next_to_use = i; 6301 6302 /* Make sure there is space in the ring for the next send. */ 6303 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6304 6305 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6306 writel(i, tx_ring->tail); 6307 } 6308 return 0; 6309 6310 dma_error: 6311 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6312 tx_buffer = &tx_ring->tx_buffer_info[i]; 6313 6314 /* clear dma mappings for failed tx_buffer_info map */ 6315 while (tx_buffer != first) { 6316 if (dma_unmap_len(tx_buffer, len)) 6317 dma_unmap_page(tx_ring->dev, 6318 dma_unmap_addr(tx_buffer, dma), 6319 dma_unmap_len(tx_buffer, len), 6320 DMA_TO_DEVICE); 6321 dma_unmap_len_set(tx_buffer, len, 0); 6322 6323 if (i-- == 0) 6324 i += tx_ring->count; 6325 tx_buffer = &tx_ring->tx_buffer_info[i]; 6326 } 6327 6328 if (dma_unmap_len(tx_buffer, len)) 6329 dma_unmap_single(tx_ring->dev, 6330 dma_unmap_addr(tx_buffer, dma), 6331 dma_unmap_len(tx_buffer, len), 6332 DMA_TO_DEVICE); 6333 dma_unmap_len_set(tx_buffer, len, 0); 6334 6335 dev_kfree_skb_any(tx_buffer->skb); 6336 tx_buffer->skb = NULL; 6337 6338 tx_ring->next_to_use = i; 6339 6340 return -1; 6341 } 6342 6343 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6344 struct igb_ring *tx_ring, 6345 struct xdp_frame *xdpf) 6346 { 6347 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6348 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6349 u16 count, i, index = tx_ring->next_to_use; 6350 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6351 struct igb_tx_buffer *tx_buffer = tx_head; 6352 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6353 u32 len = xdpf->len, cmd_type, olinfo_status; 6354 void *data = xdpf->data; 6355 6356 count = TXD_USE_COUNT(len); 6357 for (i = 0; i < nr_frags; i++) 6358 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6359 6360 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6361 return IGB_XDP_CONSUMED; 6362 6363 i = 0; 6364 /* record the location of the first descriptor for this packet */ 6365 tx_head->bytecount = xdp_get_frame_len(xdpf); 6366 tx_head->type = IGB_TYPE_XDP; 6367 tx_head->gso_segs = 1; 6368 tx_head->xdpf = xdpf; 6369 6370 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6371 /* 82575 requires a unique index per ring */ 6372 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6373 olinfo_status |= tx_ring->reg_idx << 4; 6374 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6375 6376 for (;;) { 6377 dma_addr_t dma; 6378 6379 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6380 if (dma_mapping_error(tx_ring->dev, dma)) 6381 goto unmap; 6382 6383 /* record length, and DMA address */ 6384 dma_unmap_len_set(tx_buffer, len, len); 6385 dma_unmap_addr_set(tx_buffer, dma, dma); 6386 6387 /* put descriptor type bits */ 6388 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6389 E1000_ADVTXD_DCMD_IFCS | len; 6390 6391 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6392 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6393 6394 tx_buffer->protocol = 0; 6395 6396 if (++index == tx_ring->count) 6397 index = 0; 6398 6399 if (i == nr_frags) 6400 break; 6401 6402 tx_buffer = &tx_ring->tx_buffer_info[index]; 6403 tx_desc = IGB_TX_DESC(tx_ring, index); 6404 tx_desc->read.olinfo_status = 0; 6405 6406 data = skb_frag_address(&sinfo->frags[i]); 6407 len = skb_frag_size(&sinfo->frags[i]); 6408 i++; 6409 } 6410 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6411 6412 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6413 /* set the timestamp */ 6414 tx_head->time_stamp = jiffies; 6415 6416 /* Avoid any potential race with xdp_xmit and cleanup */ 6417 smp_wmb(); 6418 6419 /* set next_to_watch value indicating a packet is present */ 6420 tx_head->next_to_watch = tx_desc; 6421 tx_ring->next_to_use = index; 6422 6423 /* Make sure there is space in the ring for the next send. */ 6424 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6425 6426 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6427 writel(index, tx_ring->tail); 6428 6429 return IGB_XDP_TX; 6430 6431 unmap: 6432 for (;;) { 6433 tx_buffer = &tx_ring->tx_buffer_info[index]; 6434 if (dma_unmap_len(tx_buffer, len)) 6435 dma_unmap_page(tx_ring->dev, 6436 dma_unmap_addr(tx_buffer, dma), 6437 dma_unmap_len(tx_buffer, len), 6438 DMA_TO_DEVICE); 6439 dma_unmap_len_set(tx_buffer, len, 0); 6440 if (tx_buffer == tx_head) 6441 break; 6442 6443 if (!index) 6444 index += tx_ring->count; 6445 index--; 6446 } 6447 6448 return IGB_XDP_CONSUMED; 6449 } 6450 6451 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6452 struct igb_ring *tx_ring) 6453 { 6454 struct igb_tx_buffer *first; 6455 int tso; 6456 u32 tx_flags = 0; 6457 unsigned short f; 6458 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6459 __be16 protocol = vlan_get_protocol(skb); 6460 u8 hdr_len = 0; 6461 6462 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6463 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6464 * + 2 desc gap to keep tail from touching head, 6465 * + 1 desc for context descriptor, 6466 * otherwise try next time 6467 */ 6468 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6469 count += TXD_USE_COUNT(skb_frag_size( 6470 &skb_shinfo(skb)->frags[f])); 6471 6472 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6473 /* this is a hard error */ 6474 return NETDEV_TX_BUSY; 6475 } 6476 6477 /* record the location of the first descriptor for this packet */ 6478 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6479 first->type = IGB_TYPE_SKB; 6480 first->skb = skb; 6481 first->bytecount = skb->len; 6482 first->gso_segs = 1; 6483 6484 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6485 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6486 6487 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6488 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6489 &adapter->state)) { 6490 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6491 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6492 6493 adapter->ptp_tx_skb = skb_get(skb); 6494 adapter->ptp_tx_start = jiffies; 6495 if (adapter->hw.mac.type == e1000_82576) 6496 schedule_work(&adapter->ptp_tx_work); 6497 } else { 6498 adapter->tx_hwtstamp_skipped++; 6499 } 6500 } 6501 6502 if (skb_vlan_tag_present(skb)) { 6503 tx_flags |= IGB_TX_FLAGS_VLAN; 6504 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6505 } 6506 6507 /* record initial flags and protocol */ 6508 first->tx_flags = tx_flags; 6509 first->protocol = protocol; 6510 6511 tso = igb_tso(tx_ring, first, &hdr_len); 6512 if (tso < 0) 6513 goto out_drop; 6514 else if (!tso) 6515 igb_tx_csum(tx_ring, first); 6516 6517 if (igb_tx_map(tx_ring, first, hdr_len)) 6518 goto cleanup_tx_tstamp; 6519 6520 return NETDEV_TX_OK; 6521 6522 out_drop: 6523 dev_kfree_skb_any(first->skb); 6524 first->skb = NULL; 6525 cleanup_tx_tstamp: 6526 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6527 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6528 6529 dev_kfree_skb_any(adapter->ptp_tx_skb); 6530 adapter->ptp_tx_skb = NULL; 6531 if (adapter->hw.mac.type == e1000_82576) 6532 cancel_work_sync(&adapter->ptp_tx_work); 6533 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6534 } 6535 6536 return NETDEV_TX_OK; 6537 } 6538 6539 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6540 struct sk_buff *skb) 6541 { 6542 unsigned int r_idx = skb->queue_mapping; 6543 6544 if (r_idx >= adapter->num_tx_queues) 6545 r_idx = r_idx % adapter->num_tx_queues; 6546 6547 return adapter->tx_ring[r_idx]; 6548 } 6549 6550 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6551 struct net_device *netdev) 6552 { 6553 struct igb_adapter *adapter = netdev_priv(netdev); 6554 6555 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6556 * in order to meet this minimum size requirement. 6557 */ 6558 if (skb_put_padto(skb, 17)) 6559 return NETDEV_TX_OK; 6560 6561 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6562 } 6563 6564 /** 6565 * igb_tx_timeout - Respond to a Tx Hang 6566 * @netdev: network interface device structure 6567 * @txqueue: number of the Tx queue that hung (unused) 6568 **/ 6569 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6570 { 6571 struct igb_adapter *adapter = netdev_priv(netdev); 6572 struct e1000_hw *hw = &adapter->hw; 6573 6574 /* Do the reset outside of interrupt context */ 6575 adapter->tx_timeout_count++; 6576 6577 if (hw->mac.type >= e1000_82580) 6578 hw->dev_spec._82575.global_device_reset = true; 6579 6580 schedule_work(&adapter->reset_task); 6581 wr32(E1000_EICS, 6582 (adapter->eims_enable_mask & ~adapter->eims_other)); 6583 } 6584 6585 static void igb_reset_task(struct work_struct *work) 6586 { 6587 struct igb_adapter *adapter; 6588 adapter = container_of(work, struct igb_adapter, reset_task); 6589 6590 rtnl_lock(); 6591 /* If we're already down or resetting, just bail */ 6592 if (test_bit(__IGB_DOWN, &adapter->state) || 6593 test_bit(__IGB_RESETTING, &adapter->state)) { 6594 rtnl_unlock(); 6595 return; 6596 } 6597 6598 igb_dump(adapter); 6599 netdev_err(adapter->netdev, "Reset adapter\n"); 6600 igb_reinit_locked(adapter); 6601 rtnl_unlock(); 6602 } 6603 6604 /** 6605 * igb_get_stats64 - Get System Network Statistics 6606 * @netdev: network interface device structure 6607 * @stats: rtnl_link_stats64 pointer 6608 **/ 6609 static void igb_get_stats64(struct net_device *netdev, 6610 struct rtnl_link_stats64 *stats) 6611 { 6612 struct igb_adapter *adapter = netdev_priv(netdev); 6613 6614 spin_lock(&adapter->stats64_lock); 6615 igb_update_stats(adapter); 6616 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6617 spin_unlock(&adapter->stats64_lock); 6618 } 6619 6620 /** 6621 * igb_change_mtu - Change the Maximum Transfer Unit 6622 * @netdev: network interface device structure 6623 * @new_mtu: new value for maximum frame size 6624 * 6625 * Returns 0 on success, negative on failure 6626 **/ 6627 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6628 { 6629 struct igb_adapter *adapter = netdev_priv(netdev); 6630 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6631 6632 if (adapter->xdp_prog) { 6633 int i; 6634 6635 for (i = 0; i < adapter->num_rx_queues; i++) { 6636 struct igb_ring *ring = adapter->rx_ring[i]; 6637 6638 if (max_frame > igb_rx_bufsz(ring)) { 6639 netdev_warn(adapter->netdev, 6640 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6641 max_frame); 6642 return -EINVAL; 6643 } 6644 } 6645 } 6646 6647 /* adjust max frame to be at least the size of a standard frame */ 6648 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6649 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6650 6651 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6652 usleep_range(1000, 2000); 6653 6654 /* igb_down has a dependency on max_frame_size */ 6655 adapter->max_frame_size = max_frame; 6656 6657 if (netif_running(netdev)) 6658 igb_down(adapter); 6659 6660 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6661 netdev->mtu, new_mtu); 6662 netdev->mtu = new_mtu; 6663 6664 if (netif_running(netdev)) 6665 igb_up(adapter); 6666 else 6667 igb_reset(adapter); 6668 6669 clear_bit(__IGB_RESETTING, &adapter->state); 6670 6671 return 0; 6672 } 6673 6674 /** 6675 * igb_update_stats - Update the board statistics counters 6676 * @adapter: board private structure 6677 **/ 6678 void igb_update_stats(struct igb_adapter *adapter) 6679 { 6680 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6681 struct e1000_hw *hw = &adapter->hw; 6682 struct pci_dev *pdev = adapter->pdev; 6683 u32 reg, mpc; 6684 int i; 6685 u64 bytes, packets; 6686 unsigned int start; 6687 u64 _bytes, _packets; 6688 6689 /* Prevent stats update while adapter is being reset, or if the pci 6690 * connection is down. 6691 */ 6692 if (adapter->link_speed == 0) 6693 return; 6694 if (pci_channel_offline(pdev)) 6695 return; 6696 6697 bytes = 0; 6698 packets = 0; 6699 6700 rcu_read_lock(); 6701 for (i = 0; i < adapter->num_rx_queues; i++) { 6702 struct igb_ring *ring = adapter->rx_ring[i]; 6703 u32 rqdpc = rd32(E1000_RQDPC(i)); 6704 if (hw->mac.type >= e1000_i210) 6705 wr32(E1000_RQDPC(i), 0); 6706 6707 if (rqdpc) { 6708 ring->rx_stats.drops += rqdpc; 6709 net_stats->rx_fifo_errors += rqdpc; 6710 } 6711 6712 do { 6713 start = u64_stats_fetch_begin(&ring->rx_syncp); 6714 _bytes = ring->rx_stats.bytes; 6715 _packets = ring->rx_stats.packets; 6716 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6717 bytes += _bytes; 6718 packets += _packets; 6719 } 6720 6721 net_stats->rx_bytes = bytes; 6722 net_stats->rx_packets = packets; 6723 6724 bytes = 0; 6725 packets = 0; 6726 for (i = 0; i < adapter->num_tx_queues; i++) { 6727 struct igb_ring *ring = adapter->tx_ring[i]; 6728 do { 6729 start = u64_stats_fetch_begin(&ring->tx_syncp); 6730 _bytes = ring->tx_stats.bytes; 6731 _packets = ring->tx_stats.packets; 6732 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6733 bytes += _bytes; 6734 packets += _packets; 6735 } 6736 net_stats->tx_bytes = bytes; 6737 net_stats->tx_packets = packets; 6738 rcu_read_unlock(); 6739 6740 /* read stats registers */ 6741 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6742 adapter->stats.gprc += rd32(E1000_GPRC); 6743 adapter->stats.gorc += rd32(E1000_GORCL); 6744 rd32(E1000_GORCH); /* clear GORCL */ 6745 adapter->stats.bprc += rd32(E1000_BPRC); 6746 adapter->stats.mprc += rd32(E1000_MPRC); 6747 adapter->stats.roc += rd32(E1000_ROC); 6748 6749 adapter->stats.prc64 += rd32(E1000_PRC64); 6750 adapter->stats.prc127 += rd32(E1000_PRC127); 6751 adapter->stats.prc255 += rd32(E1000_PRC255); 6752 adapter->stats.prc511 += rd32(E1000_PRC511); 6753 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6754 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6755 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6756 adapter->stats.sec += rd32(E1000_SEC); 6757 6758 mpc = rd32(E1000_MPC); 6759 adapter->stats.mpc += mpc; 6760 net_stats->rx_fifo_errors += mpc; 6761 adapter->stats.scc += rd32(E1000_SCC); 6762 adapter->stats.ecol += rd32(E1000_ECOL); 6763 adapter->stats.mcc += rd32(E1000_MCC); 6764 adapter->stats.latecol += rd32(E1000_LATECOL); 6765 adapter->stats.dc += rd32(E1000_DC); 6766 adapter->stats.rlec += rd32(E1000_RLEC); 6767 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6768 adapter->stats.xontxc += rd32(E1000_XONTXC); 6769 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6770 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6771 adapter->stats.fcruc += rd32(E1000_FCRUC); 6772 adapter->stats.gptc += rd32(E1000_GPTC); 6773 adapter->stats.gotc += rd32(E1000_GOTCL); 6774 rd32(E1000_GOTCH); /* clear GOTCL */ 6775 adapter->stats.rnbc += rd32(E1000_RNBC); 6776 adapter->stats.ruc += rd32(E1000_RUC); 6777 adapter->stats.rfc += rd32(E1000_RFC); 6778 adapter->stats.rjc += rd32(E1000_RJC); 6779 adapter->stats.tor += rd32(E1000_TORH); 6780 adapter->stats.tot += rd32(E1000_TOTH); 6781 adapter->stats.tpr += rd32(E1000_TPR); 6782 6783 adapter->stats.ptc64 += rd32(E1000_PTC64); 6784 adapter->stats.ptc127 += rd32(E1000_PTC127); 6785 adapter->stats.ptc255 += rd32(E1000_PTC255); 6786 adapter->stats.ptc511 += rd32(E1000_PTC511); 6787 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6788 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6789 6790 adapter->stats.mptc += rd32(E1000_MPTC); 6791 adapter->stats.bptc += rd32(E1000_BPTC); 6792 6793 adapter->stats.tpt += rd32(E1000_TPT); 6794 adapter->stats.colc += rd32(E1000_COLC); 6795 6796 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6797 /* read internal phy specific stats */ 6798 reg = rd32(E1000_CTRL_EXT); 6799 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6800 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6801 6802 /* this stat has invalid values on i210/i211 */ 6803 if ((hw->mac.type != e1000_i210) && 6804 (hw->mac.type != e1000_i211)) 6805 adapter->stats.tncrs += rd32(E1000_TNCRS); 6806 } 6807 6808 adapter->stats.tsctc += rd32(E1000_TSCTC); 6809 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6810 6811 adapter->stats.iac += rd32(E1000_IAC); 6812 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6813 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6814 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6815 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6816 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6817 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6818 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6819 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6820 6821 /* Fill out the OS statistics structure */ 6822 net_stats->multicast = adapter->stats.mprc; 6823 net_stats->collisions = adapter->stats.colc; 6824 6825 /* Rx Errors */ 6826 6827 /* RLEC on some newer hardware can be incorrect so build 6828 * our own version based on RUC and ROC 6829 */ 6830 net_stats->rx_errors = adapter->stats.rxerrc + 6831 adapter->stats.crcerrs + adapter->stats.algnerrc + 6832 adapter->stats.ruc + adapter->stats.roc + 6833 adapter->stats.cexterr; 6834 net_stats->rx_length_errors = adapter->stats.ruc + 6835 adapter->stats.roc; 6836 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6837 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6838 net_stats->rx_missed_errors = adapter->stats.mpc; 6839 6840 /* Tx Errors */ 6841 net_stats->tx_errors = adapter->stats.ecol + 6842 adapter->stats.latecol; 6843 net_stats->tx_aborted_errors = adapter->stats.ecol; 6844 net_stats->tx_window_errors = adapter->stats.latecol; 6845 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6846 6847 /* Tx Dropped needs to be maintained elsewhere */ 6848 6849 /* Management Stats */ 6850 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6851 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6852 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6853 6854 /* OS2BMC Stats */ 6855 reg = rd32(E1000_MANC); 6856 if (reg & E1000_MANC_EN_BMC2OS) { 6857 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6858 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6859 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6860 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6861 } 6862 } 6863 6864 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6865 { 6866 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6867 struct e1000_hw *hw = &adapter->hw; 6868 struct timespec64 ts; 6869 u32 tsauxc; 6870 6871 if (pin < 0 || pin >= IGB_N_SDP) 6872 return; 6873 6874 spin_lock(&adapter->tmreg_lock); 6875 6876 if (hw->mac.type == e1000_82580 || 6877 hw->mac.type == e1000_i354 || 6878 hw->mac.type == e1000_i350) { 6879 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6880 u32 systiml, systimh, level_mask, level, rem; 6881 u64 systim, now; 6882 6883 /* read systim registers in sequence */ 6884 rd32(E1000_SYSTIMR); 6885 systiml = rd32(E1000_SYSTIML); 6886 systimh = rd32(E1000_SYSTIMH); 6887 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6888 now = timecounter_cyc2time(&adapter->tc, systim); 6889 6890 if (pin < 2) { 6891 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6892 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6893 } else { 6894 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6895 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6896 } 6897 6898 div_u64_rem(now, ns, &rem); 6899 systim = systim + (ns - rem); 6900 6901 /* synchronize pin level with rising/falling edges */ 6902 div_u64_rem(now, ns << 1, &rem); 6903 if (rem < ns) { 6904 /* first half of period */ 6905 if (level == 0) { 6906 /* output is already low, skip this period */ 6907 systim += ns; 6908 pr_notice("igb: periodic output on %s missed falling edge\n", 6909 adapter->sdp_config[pin].name); 6910 } 6911 } else { 6912 /* second half of period */ 6913 if (level == 1) { 6914 /* output is already high, skip this period */ 6915 systim += ns; 6916 pr_notice("igb: periodic output on %s missed rising edge\n", 6917 adapter->sdp_config[pin].name); 6918 } 6919 } 6920 6921 /* for this chip family tv_sec is the upper part of the binary value, 6922 * so not seconds 6923 */ 6924 ts.tv_nsec = (u32)systim; 6925 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6926 } else { 6927 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6928 adapter->perout[tsintr_tt].period); 6929 } 6930 6931 /* u32 conversion of tv_sec is safe until y2106 */ 6932 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6933 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6934 tsauxc = rd32(E1000_TSAUXC); 6935 tsauxc |= TSAUXC_EN_TT0; 6936 wr32(E1000_TSAUXC, tsauxc); 6937 adapter->perout[tsintr_tt].start = ts; 6938 6939 spin_unlock(&adapter->tmreg_lock); 6940 } 6941 6942 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6943 { 6944 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6945 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6946 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6947 struct e1000_hw *hw = &adapter->hw; 6948 struct ptp_clock_event event; 6949 struct timespec64 ts; 6950 unsigned long flags; 6951 6952 if (pin < 0 || pin >= IGB_N_SDP) 6953 return; 6954 6955 if (hw->mac.type == e1000_82580 || 6956 hw->mac.type == e1000_i354 || 6957 hw->mac.type == e1000_i350) { 6958 u64 ns = rd32(auxstmpl); 6959 6960 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 6961 spin_lock_irqsave(&adapter->tmreg_lock, flags); 6962 ns = timecounter_cyc2time(&adapter->tc, ns); 6963 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 6964 ts = ns_to_timespec64(ns); 6965 } else { 6966 ts.tv_nsec = rd32(auxstmpl); 6967 ts.tv_sec = rd32(auxstmph); 6968 } 6969 6970 event.type = PTP_CLOCK_EXTTS; 6971 event.index = tsintr_tt; 6972 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6973 ptp_clock_event(adapter->ptp_clock, &event); 6974 } 6975 6976 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6977 { 6978 struct e1000_hw *hw = &adapter->hw; 6979 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6980 struct ptp_clock_event event; 6981 6982 if (tsicr & TSINTR_SYS_WRAP) { 6983 event.type = PTP_CLOCK_PPS; 6984 if (adapter->ptp_caps.pps) 6985 ptp_clock_event(adapter->ptp_clock, &event); 6986 ack |= TSINTR_SYS_WRAP; 6987 } 6988 6989 if (tsicr & E1000_TSICR_TXTS) { 6990 /* retrieve hardware timestamp */ 6991 schedule_work(&adapter->ptp_tx_work); 6992 ack |= E1000_TSICR_TXTS; 6993 } 6994 6995 if (tsicr & TSINTR_TT0) { 6996 igb_perout(adapter, 0); 6997 ack |= TSINTR_TT0; 6998 } 6999 7000 if (tsicr & TSINTR_TT1) { 7001 igb_perout(adapter, 1); 7002 ack |= TSINTR_TT1; 7003 } 7004 7005 if (tsicr & TSINTR_AUTT0) { 7006 igb_extts(adapter, 0); 7007 ack |= TSINTR_AUTT0; 7008 } 7009 7010 if (tsicr & TSINTR_AUTT1) { 7011 igb_extts(adapter, 1); 7012 ack |= TSINTR_AUTT1; 7013 } 7014 7015 /* acknowledge the interrupts */ 7016 wr32(E1000_TSICR, ack); 7017 } 7018 7019 static irqreturn_t igb_msix_other(int irq, void *data) 7020 { 7021 struct igb_adapter *adapter = data; 7022 struct e1000_hw *hw = &adapter->hw; 7023 u32 icr = rd32(E1000_ICR); 7024 /* reading ICR causes bit 31 of EICR to be cleared */ 7025 7026 if (icr & E1000_ICR_DRSTA) 7027 schedule_work(&adapter->reset_task); 7028 7029 if (icr & E1000_ICR_DOUTSYNC) { 7030 /* HW is reporting DMA is out of sync */ 7031 adapter->stats.doosync++; 7032 /* The DMA Out of Sync is also indication of a spoof event 7033 * in IOV mode. Check the Wrong VM Behavior register to 7034 * see if it is really a spoof event. 7035 */ 7036 igb_check_wvbr(adapter); 7037 } 7038 7039 /* Check for a mailbox event */ 7040 if (icr & E1000_ICR_VMMB) 7041 igb_msg_task(adapter); 7042 7043 if (icr & E1000_ICR_LSC) { 7044 hw->mac.get_link_status = 1; 7045 /* guard against interrupt when we're going down */ 7046 if (!test_bit(__IGB_DOWN, &adapter->state)) 7047 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7048 } 7049 7050 if (icr & E1000_ICR_TS) 7051 igb_tsync_interrupt(adapter); 7052 7053 wr32(E1000_EIMS, adapter->eims_other); 7054 7055 return IRQ_HANDLED; 7056 } 7057 7058 static void igb_write_itr(struct igb_q_vector *q_vector) 7059 { 7060 struct igb_adapter *adapter = q_vector->adapter; 7061 u32 itr_val = q_vector->itr_val & 0x7FFC; 7062 7063 if (!q_vector->set_itr) 7064 return; 7065 7066 if (!itr_val) 7067 itr_val = 0x4; 7068 7069 if (adapter->hw.mac.type == e1000_82575) 7070 itr_val |= itr_val << 16; 7071 else 7072 itr_val |= E1000_EITR_CNT_IGNR; 7073 7074 writel(itr_val, q_vector->itr_register); 7075 q_vector->set_itr = 0; 7076 } 7077 7078 static irqreturn_t igb_msix_ring(int irq, void *data) 7079 { 7080 struct igb_q_vector *q_vector = data; 7081 7082 /* Write the ITR value calculated from the previous interrupt. */ 7083 igb_write_itr(q_vector); 7084 7085 napi_schedule(&q_vector->napi); 7086 7087 return IRQ_HANDLED; 7088 } 7089 7090 #ifdef CONFIG_IGB_DCA 7091 static void igb_update_tx_dca(struct igb_adapter *adapter, 7092 struct igb_ring *tx_ring, 7093 int cpu) 7094 { 7095 struct e1000_hw *hw = &adapter->hw; 7096 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7097 7098 if (hw->mac.type != e1000_82575) 7099 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7100 7101 /* We can enable relaxed ordering for reads, but not writes when 7102 * DCA is enabled. This is due to a known issue in some chipsets 7103 * which will cause the DCA tag to be cleared. 7104 */ 7105 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7106 E1000_DCA_TXCTRL_DATA_RRO_EN | 7107 E1000_DCA_TXCTRL_DESC_DCA_EN; 7108 7109 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7110 } 7111 7112 static void igb_update_rx_dca(struct igb_adapter *adapter, 7113 struct igb_ring *rx_ring, 7114 int cpu) 7115 { 7116 struct e1000_hw *hw = &adapter->hw; 7117 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7118 7119 if (hw->mac.type != e1000_82575) 7120 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7121 7122 /* We can enable relaxed ordering for reads, but not writes when 7123 * DCA is enabled. This is due to a known issue in some chipsets 7124 * which will cause the DCA tag to be cleared. 7125 */ 7126 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7127 E1000_DCA_RXCTRL_DESC_DCA_EN; 7128 7129 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7130 } 7131 7132 static void igb_update_dca(struct igb_q_vector *q_vector) 7133 { 7134 struct igb_adapter *adapter = q_vector->adapter; 7135 int cpu = get_cpu(); 7136 7137 if (q_vector->cpu == cpu) 7138 goto out_no_update; 7139 7140 if (q_vector->tx.ring) 7141 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7142 7143 if (q_vector->rx.ring) 7144 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7145 7146 q_vector->cpu = cpu; 7147 out_no_update: 7148 put_cpu(); 7149 } 7150 7151 static void igb_setup_dca(struct igb_adapter *adapter) 7152 { 7153 struct e1000_hw *hw = &adapter->hw; 7154 int i; 7155 7156 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7157 return; 7158 7159 /* Always use CB2 mode, difference is masked in the CB driver. */ 7160 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7161 7162 for (i = 0; i < adapter->num_q_vectors; i++) { 7163 adapter->q_vector[i]->cpu = -1; 7164 igb_update_dca(adapter->q_vector[i]); 7165 } 7166 } 7167 7168 static int __igb_notify_dca(struct device *dev, void *data) 7169 { 7170 struct net_device *netdev = dev_get_drvdata(dev); 7171 struct igb_adapter *adapter = netdev_priv(netdev); 7172 struct pci_dev *pdev = adapter->pdev; 7173 struct e1000_hw *hw = &adapter->hw; 7174 unsigned long event = *(unsigned long *)data; 7175 7176 switch (event) { 7177 case DCA_PROVIDER_ADD: 7178 /* if already enabled, don't do it again */ 7179 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7180 break; 7181 if (dca_add_requester(dev) == 0) { 7182 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7183 dev_info(&pdev->dev, "DCA enabled\n"); 7184 igb_setup_dca(adapter); 7185 break; 7186 } 7187 fallthrough; /* since DCA is disabled. */ 7188 case DCA_PROVIDER_REMOVE: 7189 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7190 /* without this a class_device is left 7191 * hanging around in the sysfs model 7192 */ 7193 dca_remove_requester(dev); 7194 dev_info(&pdev->dev, "DCA disabled\n"); 7195 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7196 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7197 } 7198 break; 7199 } 7200 7201 return 0; 7202 } 7203 7204 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7205 void *p) 7206 { 7207 int ret_val; 7208 7209 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7210 __igb_notify_dca); 7211 7212 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7213 } 7214 #endif /* CONFIG_IGB_DCA */ 7215 7216 #ifdef CONFIG_PCI_IOV 7217 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7218 { 7219 unsigned char mac_addr[ETH_ALEN]; 7220 7221 eth_zero_addr(mac_addr); 7222 igb_set_vf_mac(adapter, vf, mac_addr); 7223 7224 /* By default spoof check is enabled for all VFs */ 7225 adapter->vf_data[vf].spoofchk_enabled = true; 7226 7227 /* By default VFs are not trusted */ 7228 adapter->vf_data[vf].trusted = false; 7229 7230 return 0; 7231 } 7232 7233 #endif 7234 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7235 { 7236 struct e1000_hw *hw = &adapter->hw; 7237 u32 ping; 7238 int i; 7239 7240 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7241 ping = E1000_PF_CONTROL_MSG; 7242 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7243 ping |= E1000_VT_MSGTYPE_CTS; 7244 igb_write_mbx(hw, &ping, 1, i); 7245 } 7246 } 7247 7248 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7249 { 7250 struct e1000_hw *hw = &adapter->hw; 7251 u32 vmolr = rd32(E1000_VMOLR(vf)); 7252 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7253 7254 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7255 IGB_VF_FLAG_MULTI_PROMISC); 7256 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7257 7258 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7259 vmolr |= E1000_VMOLR_MPME; 7260 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7261 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7262 } else { 7263 /* if we have hashes and we are clearing a multicast promisc 7264 * flag we need to write the hashes to the MTA as this step 7265 * was previously skipped 7266 */ 7267 if (vf_data->num_vf_mc_hashes > 30) { 7268 vmolr |= E1000_VMOLR_MPME; 7269 } else if (vf_data->num_vf_mc_hashes) { 7270 int j; 7271 7272 vmolr |= E1000_VMOLR_ROMPE; 7273 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7274 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7275 } 7276 } 7277 7278 wr32(E1000_VMOLR(vf), vmolr); 7279 7280 /* there are flags left unprocessed, likely not supported */ 7281 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7282 return -EINVAL; 7283 7284 return 0; 7285 } 7286 7287 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7288 u32 *msgbuf, u32 vf) 7289 { 7290 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7291 u16 *hash_list = (u16 *)&msgbuf[1]; 7292 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7293 int i; 7294 7295 /* salt away the number of multicast addresses assigned 7296 * to this VF for later use to restore when the PF multi cast 7297 * list changes 7298 */ 7299 vf_data->num_vf_mc_hashes = n; 7300 7301 /* only up to 30 hash values supported */ 7302 if (n > 30) 7303 n = 30; 7304 7305 /* store the hashes for later use */ 7306 for (i = 0; i < n; i++) 7307 vf_data->vf_mc_hashes[i] = hash_list[i]; 7308 7309 /* Flush and reset the mta with the new values */ 7310 igb_set_rx_mode(adapter->netdev); 7311 7312 return 0; 7313 } 7314 7315 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7316 { 7317 struct e1000_hw *hw = &adapter->hw; 7318 struct vf_data_storage *vf_data; 7319 int i, j; 7320 7321 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7322 u32 vmolr = rd32(E1000_VMOLR(i)); 7323 7324 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7325 7326 vf_data = &adapter->vf_data[i]; 7327 7328 if ((vf_data->num_vf_mc_hashes > 30) || 7329 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7330 vmolr |= E1000_VMOLR_MPME; 7331 } else if (vf_data->num_vf_mc_hashes) { 7332 vmolr |= E1000_VMOLR_ROMPE; 7333 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7334 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7335 } 7336 wr32(E1000_VMOLR(i), vmolr); 7337 } 7338 } 7339 7340 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7341 { 7342 struct e1000_hw *hw = &adapter->hw; 7343 u32 pool_mask, vlvf_mask, i; 7344 7345 /* create mask for VF and other pools */ 7346 pool_mask = E1000_VLVF_POOLSEL_MASK; 7347 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7348 7349 /* drop PF from pool bits */ 7350 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7351 adapter->vfs_allocated_count); 7352 7353 /* Find the vlan filter for this id */ 7354 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7355 u32 vlvf = rd32(E1000_VLVF(i)); 7356 u32 vfta_mask, vid, vfta; 7357 7358 /* remove the vf from the pool */ 7359 if (!(vlvf & vlvf_mask)) 7360 continue; 7361 7362 /* clear out bit from VLVF */ 7363 vlvf ^= vlvf_mask; 7364 7365 /* if other pools are present, just remove ourselves */ 7366 if (vlvf & pool_mask) 7367 goto update_vlvfb; 7368 7369 /* if PF is present, leave VFTA */ 7370 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7371 goto update_vlvf; 7372 7373 vid = vlvf & E1000_VLVF_VLANID_MASK; 7374 vfta_mask = BIT(vid % 32); 7375 7376 /* clear bit from VFTA */ 7377 vfta = adapter->shadow_vfta[vid / 32]; 7378 if (vfta & vfta_mask) 7379 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7380 update_vlvf: 7381 /* clear pool selection enable */ 7382 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7383 vlvf &= E1000_VLVF_POOLSEL_MASK; 7384 else 7385 vlvf = 0; 7386 update_vlvfb: 7387 /* clear pool bits */ 7388 wr32(E1000_VLVF(i), vlvf); 7389 } 7390 } 7391 7392 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7393 { 7394 u32 vlvf; 7395 int idx; 7396 7397 /* short cut the special case */ 7398 if (vlan == 0) 7399 return 0; 7400 7401 /* Search for the VLAN id in the VLVF entries */ 7402 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7403 vlvf = rd32(E1000_VLVF(idx)); 7404 if ((vlvf & VLAN_VID_MASK) == vlan) 7405 break; 7406 } 7407 7408 return idx; 7409 } 7410 7411 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7412 { 7413 struct e1000_hw *hw = &adapter->hw; 7414 u32 bits, pf_id; 7415 int idx; 7416 7417 idx = igb_find_vlvf_entry(hw, vid); 7418 if (!idx) 7419 return; 7420 7421 /* See if any other pools are set for this VLAN filter 7422 * entry other than the PF. 7423 */ 7424 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7425 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7426 bits &= rd32(E1000_VLVF(idx)); 7427 7428 /* Disable the filter so this falls into the default pool. */ 7429 if (!bits) { 7430 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7431 wr32(E1000_VLVF(idx), BIT(pf_id)); 7432 else 7433 wr32(E1000_VLVF(idx), 0); 7434 } 7435 } 7436 7437 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7438 bool add, u32 vf) 7439 { 7440 int pf_id = adapter->vfs_allocated_count; 7441 struct e1000_hw *hw = &adapter->hw; 7442 int err; 7443 7444 /* If VLAN overlaps with one the PF is currently monitoring make 7445 * sure that we are able to allocate a VLVF entry. This may be 7446 * redundant but it guarantees PF will maintain visibility to 7447 * the VLAN. 7448 */ 7449 if (add && test_bit(vid, adapter->active_vlans)) { 7450 err = igb_vfta_set(hw, vid, pf_id, true, false); 7451 if (err) 7452 return err; 7453 } 7454 7455 err = igb_vfta_set(hw, vid, vf, add, false); 7456 7457 if (add && !err) 7458 return err; 7459 7460 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7461 * we may need to drop the PF pool bit in order to allow us to free 7462 * up the VLVF resources. 7463 */ 7464 if (test_bit(vid, adapter->active_vlans) || 7465 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7466 igb_update_pf_vlvf(adapter, vid); 7467 7468 return err; 7469 } 7470 7471 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7472 { 7473 struct e1000_hw *hw = &adapter->hw; 7474 7475 if (vid) 7476 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7477 else 7478 wr32(E1000_VMVIR(vf), 0); 7479 } 7480 7481 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7482 u16 vlan, u8 qos) 7483 { 7484 int err; 7485 7486 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7487 if (err) 7488 return err; 7489 7490 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7491 igb_set_vmolr(adapter, vf, !vlan); 7492 7493 /* revoke access to previous VLAN */ 7494 if (vlan != adapter->vf_data[vf].pf_vlan) 7495 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7496 false, vf); 7497 7498 adapter->vf_data[vf].pf_vlan = vlan; 7499 adapter->vf_data[vf].pf_qos = qos; 7500 igb_set_vf_vlan_strip(adapter, vf, true); 7501 dev_info(&adapter->pdev->dev, 7502 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7503 if (test_bit(__IGB_DOWN, &adapter->state)) { 7504 dev_warn(&adapter->pdev->dev, 7505 "The VF VLAN has been set, but the PF device is not up.\n"); 7506 dev_warn(&adapter->pdev->dev, 7507 "Bring the PF device up before attempting to use the VF device.\n"); 7508 } 7509 7510 return err; 7511 } 7512 7513 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7514 { 7515 /* Restore tagless access via VLAN 0 */ 7516 igb_set_vf_vlan(adapter, 0, true, vf); 7517 7518 igb_set_vmvir(adapter, 0, vf); 7519 igb_set_vmolr(adapter, vf, true); 7520 7521 /* Remove any PF assigned VLAN */ 7522 if (adapter->vf_data[vf].pf_vlan) 7523 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7524 false, vf); 7525 7526 adapter->vf_data[vf].pf_vlan = 0; 7527 adapter->vf_data[vf].pf_qos = 0; 7528 igb_set_vf_vlan_strip(adapter, vf, false); 7529 7530 return 0; 7531 } 7532 7533 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7534 u16 vlan, u8 qos, __be16 vlan_proto) 7535 { 7536 struct igb_adapter *adapter = netdev_priv(netdev); 7537 7538 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7539 return -EINVAL; 7540 7541 if (vlan_proto != htons(ETH_P_8021Q)) 7542 return -EPROTONOSUPPORT; 7543 7544 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7545 igb_disable_port_vlan(adapter, vf); 7546 } 7547 7548 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7549 { 7550 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7551 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7552 int ret; 7553 7554 if (adapter->vf_data[vf].pf_vlan) 7555 return -1; 7556 7557 /* VLAN 0 is a special case, don't allow it to be removed */ 7558 if (!vid && !add) 7559 return 0; 7560 7561 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7562 if (!ret) 7563 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7564 return ret; 7565 } 7566 7567 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7568 { 7569 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7570 7571 /* clear flags - except flag that indicates PF has set the MAC */ 7572 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7573 vf_data->last_nack = jiffies; 7574 7575 /* reset vlans for device */ 7576 igb_clear_vf_vfta(adapter, vf); 7577 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7578 igb_set_vmvir(adapter, vf_data->pf_vlan | 7579 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7580 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7581 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7582 7583 /* reset multicast table array for vf */ 7584 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7585 7586 /* Flush and reset the mta with the new values */ 7587 igb_set_rx_mode(adapter->netdev); 7588 } 7589 7590 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7591 { 7592 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7593 7594 /* clear mac address as we were hotplug removed/added */ 7595 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7596 eth_zero_addr(vf_mac); 7597 7598 /* process remaining reset events */ 7599 igb_vf_reset(adapter, vf); 7600 } 7601 7602 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7603 { 7604 struct e1000_hw *hw = &adapter->hw; 7605 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7606 u32 reg, msgbuf[3] = {}; 7607 u8 *addr = (u8 *)(&msgbuf[1]); 7608 7609 /* process all the same items cleared in a function level reset */ 7610 igb_vf_reset(adapter, vf); 7611 7612 /* set vf mac address */ 7613 igb_set_vf_mac(adapter, vf, vf_mac); 7614 7615 /* enable transmit and receive for vf */ 7616 reg = rd32(E1000_VFTE); 7617 wr32(E1000_VFTE, reg | BIT(vf)); 7618 reg = rd32(E1000_VFRE); 7619 wr32(E1000_VFRE, reg | BIT(vf)); 7620 7621 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7622 7623 /* reply to reset with ack and vf mac address */ 7624 if (!is_zero_ether_addr(vf_mac)) { 7625 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7626 memcpy(addr, vf_mac, ETH_ALEN); 7627 } else { 7628 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7629 } 7630 igb_write_mbx(hw, msgbuf, 3, vf); 7631 } 7632 7633 static void igb_flush_mac_table(struct igb_adapter *adapter) 7634 { 7635 struct e1000_hw *hw = &adapter->hw; 7636 int i; 7637 7638 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7639 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7640 eth_zero_addr(adapter->mac_table[i].addr); 7641 adapter->mac_table[i].queue = 0; 7642 igb_rar_set_index(adapter, i); 7643 } 7644 } 7645 7646 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7647 { 7648 struct e1000_hw *hw = &adapter->hw; 7649 /* do not count rar entries reserved for VFs MAC addresses */ 7650 int rar_entries = hw->mac.rar_entry_count - 7651 adapter->vfs_allocated_count; 7652 int i, count = 0; 7653 7654 for (i = 0; i < rar_entries; i++) { 7655 /* do not count default entries */ 7656 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7657 continue; 7658 7659 /* do not count "in use" entries for different queues */ 7660 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7661 (adapter->mac_table[i].queue != queue)) 7662 continue; 7663 7664 count++; 7665 } 7666 7667 return count; 7668 } 7669 7670 /* Set default MAC address for the PF in the first RAR entry */ 7671 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7672 { 7673 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7674 7675 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7676 mac_table->queue = adapter->vfs_allocated_count; 7677 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7678 7679 igb_rar_set_index(adapter, 0); 7680 } 7681 7682 /* If the filter to be added and an already existing filter express 7683 * the same address and address type, it should be possible to only 7684 * override the other configurations, for example the queue to steer 7685 * traffic. 7686 */ 7687 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7688 const u8 *addr, const u8 flags) 7689 { 7690 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7691 return true; 7692 7693 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7694 (flags & IGB_MAC_STATE_SRC_ADDR)) 7695 return false; 7696 7697 if (!ether_addr_equal(addr, entry->addr)) 7698 return false; 7699 7700 return true; 7701 } 7702 7703 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7704 * 'flags' is used to indicate what kind of match is made, match is by 7705 * default for the destination address, if matching by source address 7706 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7707 */ 7708 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7709 const u8 *addr, const u8 queue, 7710 const u8 flags) 7711 { 7712 struct e1000_hw *hw = &adapter->hw; 7713 int rar_entries = hw->mac.rar_entry_count - 7714 adapter->vfs_allocated_count; 7715 int i; 7716 7717 if (is_zero_ether_addr(addr)) 7718 return -EINVAL; 7719 7720 /* Search for the first empty entry in the MAC table. 7721 * Do not touch entries at the end of the table reserved for the VF MAC 7722 * addresses. 7723 */ 7724 for (i = 0; i < rar_entries; i++) { 7725 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7726 addr, flags)) 7727 continue; 7728 7729 ether_addr_copy(adapter->mac_table[i].addr, addr); 7730 adapter->mac_table[i].queue = queue; 7731 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7732 7733 igb_rar_set_index(adapter, i); 7734 return i; 7735 } 7736 7737 return -ENOSPC; 7738 } 7739 7740 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7741 const u8 queue) 7742 { 7743 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7744 } 7745 7746 /* Remove a MAC filter for 'addr' directing matching traffic to 7747 * 'queue', 'flags' is used to indicate what kind of match need to be 7748 * removed, match is by default for the destination address, if 7749 * matching by source address is to be removed the flag 7750 * IGB_MAC_STATE_SRC_ADDR can be used. 7751 */ 7752 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7753 const u8 *addr, const u8 queue, 7754 const u8 flags) 7755 { 7756 struct e1000_hw *hw = &adapter->hw; 7757 int rar_entries = hw->mac.rar_entry_count - 7758 adapter->vfs_allocated_count; 7759 int i; 7760 7761 if (is_zero_ether_addr(addr)) 7762 return -EINVAL; 7763 7764 /* Search for matching entry in the MAC table based on given address 7765 * and queue. Do not touch entries at the end of the table reserved 7766 * for the VF MAC addresses. 7767 */ 7768 for (i = 0; i < rar_entries; i++) { 7769 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7770 continue; 7771 if ((adapter->mac_table[i].state & flags) != flags) 7772 continue; 7773 if (adapter->mac_table[i].queue != queue) 7774 continue; 7775 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7776 continue; 7777 7778 /* When a filter for the default address is "deleted", 7779 * we return it to its initial configuration 7780 */ 7781 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7782 adapter->mac_table[i].state = 7783 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7784 adapter->mac_table[i].queue = 7785 adapter->vfs_allocated_count; 7786 } else { 7787 adapter->mac_table[i].state = 0; 7788 adapter->mac_table[i].queue = 0; 7789 eth_zero_addr(adapter->mac_table[i].addr); 7790 } 7791 7792 igb_rar_set_index(adapter, i); 7793 return 0; 7794 } 7795 7796 return -ENOENT; 7797 } 7798 7799 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7800 const u8 queue) 7801 { 7802 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7803 } 7804 7805 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7806 const u8 *addr, u8 queue, u8 flags) 7807 { 7808 struct e1000_hw *hw = &adapter->hw; 7809 7810 /* In theory, this should be supported on 82575 as well, but 7811 * that part wasn't easily accessible during development. 7812 */ 7813 if (hw->mac.type != e1000_i210) 7814 return -EOPNOTSUPP; 7815 7816 return igb_add_mac_filter_flags(adapter, addr, queue, 7817 IGB_MAC_STATE_QUEUE_STEERING | flags); 7818 } 7819 7820 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7821 const u8 *addr, u8 queue, u8 flags) 7822 { 7823 return igb_del_mac_filter_flags(adapter, addr, queue, 7824 IGB_MAC_STATE_QUEUE_STEERING | flags); 7825 } 7826 7827 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7828 { 7829 struct igb_adapter *adapter = netdev_priv(netdev); 7830 int ret; 7831 7832 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7833 7834 return min_t(int, ret, 0); 7835 } 7836 7837 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7838 { 7839 struct igb_adapter *adapter = netdev_priv(netdev); 7840 7841 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7842 7843 return 0; 7844 } 7845 7846 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7847 const u32 info, const u8 *addr) 7848 { 7849 struct pci_dev *pdev = adapter->pdev; 7850 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7851 struct list_head *pos; 7852 struct vf_mac_filter *entry = NULL; 7853 int ret = 0; 7854 7855 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7856 !vf_data->trusted) { 7857 dev_warn(&pdev->dev, 7858 "VF %d requested MAC filter but is administratively denied\n", 7859 vf); 7860 return -EINVAL; 7861 } 7862 if (!is_valid_ether_addr(addr)) { 7863 dev_warn(&pdev->dev, 7864 "VF %d attempted to set invalid MAC filter\n", 7865 vf); 7866 return -EINVAL; 7867 } 7868 7869 switch (info) { 7870 case E1000_VF_MAC_FILTER_CLR: 7871 /* remove all unicast MAC filters related to the current VF */ 7872 list_for_each(pos, &adapter->vf_macs.l) { 7873 entry = list_entry(pos, struct vf_mac_filter, l); 7874 if (entry->vf == vf) { 7875 entry->vf = -1; 7876 entry->free = true; 7877 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7878 } 7879 } 7880 break; 7881 case E1000_VF_MAC_FILTER_ADD: 7882 /* try to find empty slot in the list */ 7883 list_for_each(pos, &adapter->vf_macs.l) { 7884 entry = list_entry(pos, struct vf_mac_filter, l); 7885 if (entry->free) 7886 break; 7887 } 7888 7889 if (entry && entry->free) { 7890 entry->free = false; 7891 entry->vf = vf; 7892 ether_addr_copy(entry->vf_mac, addr); 7893 7894 ret = igb_add_mac_filter(adapter, addr, vf); 7895 ret = min_t(int, ret, 0); 7896 } else { 7897 ret = -ENOSPC; 7898 } 7899 7900 if (ret == -ENOSPC) 7901 dev_warn(&pdev->dev, 7902 "VF %d has requested MAC filter but there is no space for it\n", 7903 vf); 7904 break; 7905 default: 7906 ret = -EINVAL; 7907 break; 7908 } 7909 7910 return ret; 7911 } 7912 7913 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7914 { 7915 struct pci_dev *pdev = adapter->pdev; 7916 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7917 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7918 7919 /* The VF MAC Address is stored in a packed array of bytes 7920 * starting at the second 32 bit word of the msg array 7921 */ 7922 unsigned char *addr = (unsigned char *)&msg[1]; 7923 int ret = 0; 7924 7925 if (!info) { 7926 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7927 !vf_data->trusted) { 7928 dev_warn(&pdev->dev, 7929 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7930 vf); 7931 return -EINVAL; 7932 } 7933 7934 if (!is_valid_ether_addr(addr)) { 7935 dev_warn(&pdev->dev, 7936 "VF %d attempted to set invalid MAC\n", 7937 vf); 7938 return -EINVAL; 7939 } 7940 7941 ret = igb_set_vf_mac(adapter, vf, addr); 7942 } else { 7943 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7944 } 7945 7946 return ret; 7947 } 7948 7949 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7950 { 7951 struct e1000_hw *hw = &adapter->hw; 7952 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7953 u32 msg = E1000_VT_MSGTYPE_NACK; 7954 7955 /* if device isn't clear to send it shouldn't be reading either */ 7956 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7957 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7958 igb_write_mbx(hw, &msg, 1, vf); 7959 vf_data->last_nack = jiffies; 7960 } 7961 } 7962 7963 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7964 { 7965 struct pci_dev *pdev = adapter->pdev; 7966 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7967 struct e1000_hw *hw = &adapter->hw; 7968 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7969 s32 retval; 7970 7971 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7972 7973 if (retval) { 7974 /* if receive failed revoke VF CTS stats and restart init */ 7975 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7976 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7977 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7978 goto unlock; 7979 goto out; 7980 } 7981 7982 /* this is a message we already processed, do nothing */ 7983 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7984 goto unlock; 7985 7986 /* until the vf completes a reset it should not be 7987 * allowed to start any configuration. 7988 */ 7989 if (msgbuf[0] == E1000_VF_RESET) { 7990 /* unlocks mailbox */ 7991 igb_vf_reset_msg(adapter, vf); 7992 return; 7993 } 7994 7995 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7996 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7997 goto unlock; 7998 retval = -1; 7999 goto out; 8000 } 8001 8002 switch ((msgbuf[0] & 0xFFFF)) { 8003 case E1000_VF_SET_MAC_ADDR: 8004 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8005 break; 8006 case E1000_VF_SET_PROMISC: 8007 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8008 break; 8009 case E1000_VF_SET_MULTICAST: 8010 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8011 break; 8012 case E1000_VF_SET_LPE: 8013 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8014 break; 8015 case E1000_VF_SET_VLAN: 8016 retval = -1; 8017 if (vf_data->pf_vlan) 8018 dev_warn(&pdev->dev, 8019 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8020 vf); 8021 else 8022 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8023 break; 8024 default: 8025 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8026 retval = -1; 8027 break; 8028 } 8029 8030 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8031 out: 8032 /* notify the VF of the results of what it sent us */ 8033 if (retval) 8034 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8035 else 8036 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8037 8038 /* unlocks mailbox */ 8039 igb_write_mbx(hw, msgbuf, 1, vf); 8040 return; 8041 8042 unlock: 8043 igb_unlock_mbx(hw, vf); 8044 } 8045 8046 static void igb_msg_task(struct igb_adapter *adapter) 8047 { 8048 struct e1000_hw *hw = &adapter->hw; 8049 unsigned long flags; 8050 u32 vf; 8051 8052 spin_lock_irqsave(&adapter->vfs_lock, flags); 8053 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8054 /* process any reset requests */ 8055 if (!igb_check_for_rst(hw, vf)) 8056 igb_vf_reset_event(adapter, vf); 8057 8058 /* process any messages pending */ 8059 if (!igb_check_for_msg(hw, vf)) 8060 igb_rcv_msg_from_vf(adapter, vf); 8061 8062 /* process any acks */ 8063 if (!igb_check_for_ack(hw, vf)) 8064 igb_rcv_ack_from_vf(adapter, vf); 8065 } 8066 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8067 } 8068 8069 /** 8070 * igb_set_uta - Set unicast filter table address 8071 * @adapter: board private structure 8072 * @set: boolean indicating if we are setting or clearing bits 8073 * 8074 * The unicast table address is a register array of 32-bit registers. 8075 * The table is meant to be used in a way similar to how the MTA is used 8076 * however due to certain limitations in the hardware it is necessary to 8077 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8078 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8079 **/ 8080 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8081 { 8082 struct e1000_hw *hw = &adapter->hw; 8083 u32 uta = set ? ~0 : 0; 8084 int i; 8085 8086 /* we only need to do this if VMDq is enabled */ 8087 if (!adapter->vfs_allocated_count) 8088 return; 8089 8090 for (i = hw->mac.uta_reg_count; i--;) 8091 array_wr32(E1000_UTA, i, uta); 8092 } 8093 8094 /** 8095 * igb_intr_msi - Interrupt Handler 8096 * @irq: interrupt number 8097 * @data: pointer to a network interface device structure 8098 **/ 8099 static irqreturn_t igb_intr_msi(int irq, void *data) 8100 { 8101 struct igb_adapter *adapter = data; 8102 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8103 struct e1000_hw *hw = &adapter->hw; 8104 /* read ICR disables interrupts using IAM */ 8105 u32 icr = rd32(E1000_ICR); 8106 8107 igb_write_itr(q_vector); 8108 8109 if (icr & E1000_ICR_DRSTA) 8110 schedule_work(&adapter->reset_task); 8111 8112 if (icr & E1000_ICR_DOUTSYNC) { 8113 /* HW is reporting DMA is out of sync */ 8114 adapter->stats.doosync++; 8115 } 8116 8117 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8118 hw->mac.get_link_status = 1; 8119 if (!test_bit(__IGB_DOWN, &adapter->state)) 8120 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8121 } 8122 8123 if (icr & E1000_ICR_TS) 8124 igb_tsync_interrupt(adapter); 8125 8126 napi_schedule(&q_vector->napi); 8127 8128 return IRQ_HANDLED; 8129 } 8130 8131 /** 8132 * igb_intr - Legacy Interrupt Handler 8133 * @irq: interrupt number 8134 * @data: pointer to a network interface device structure 8135 **/ 8136 static irqreturn_t igb_intr(int irq, void *data) 8137 { 8138 struct igb_adapter *adapter = data; 8139 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8140 struct e1000_hw *hw = &adapter->hw; 8141 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8142 * need for the IMC write 8143 */ 8144 u32 icr = rd32(E1000_ICR); 8145 8146 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8147 * not set, then the adapter didn't send an interrupt 8148 */ 8149 if (!(icr & E1000_ICR_INT_ASSERTED)) 8150 return IRQ_NONE; 8151 8152 igb_write_itr(q_vector); 8153 8154 if (icr & E1000_ICR_DRSTA) 8155 schedule_work(&adapter->reset_task); 8156 8157 if (icr & E1000_ICR_DOUTSYNC) { 8158 /* HW is reporting DMA is out of sync */ 8159 adapter->stats.doosync++; 8160 } 8161 8162 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8163 hw->mac.get_link_status = 1; 8164 /* guard against interrupt when we're going down */ 8165 if (!test_bit(__IGB_DOWN, &adapter->state)) 8166 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8167 } 8168 8169 if (icr & E1000_ICR_TS) 8170 igb_tsync_interrupt(adapter); 8171 8172 napi_schedule(&q_vector->napi); 8173 8174 return IRQ_HANDLED; 8175 } 8176 8177 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8178 { 8179 struct igb_adapter *adapter = q_vector->adapter; 8180 struct e1000_hw *hw = &adapter->hw; 8181 8182 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8183 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8184 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8185 igb_set_itr(q_vector); 8186 else 8187 igb_update_ring_itr(q_vector); 8188 } 8189 8190 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8191 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8192 wr32(E1000_EIMS, q_vector->eims_value); 8193 else 8194 igb_irq_enable(adapter); 8195 } 8196 } 8197 8198 /** 8199 * igb_poll - NAPI Rx polling callback 8200 * @napi: napi polling structure 8201 * @budget: count of how many packets we should handle 8202 **/ 8203 static int igb_poll(struct napi_struct *napi, int budget) 8204 { 8205 struct igb_q_vector *q_vector = container_of(napi, 8206 struct igb_q_vector, 8207 napi); 8208 bool clean_complete = true; 8209 int work_done = 0; 8210 8211 #ifdef CONFIG_IGB_DCA 8212 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8213 igb_update_dca(q_vector); 8214 #endif 8215 if (q_vector->tx.ring) 8216 clean_complete = igb_clean_tx_irq(q_vector, budget); 8217 8218 if (q_vector->rx.ring) { 8219 int cleaned = igb_clean_rx_irq(q_vector, budget); 8220 8221 work_done += cleaned; 8222 if (cleaned >= budget) 8223 clean_complete = false; 8224 } 8225 8226 /* If all work not completed, return budget and keep polling */ 8227 if (!clean_complete) 8228 return budget; 8229 8230 /* Exit the polling mode, but don't re-enable interrupts if stack might 8231 * poll us due to busy-polling 8232 */ 8233 if (likely(napi_complete_done(napi, work_done))) 8234 igb_ring_irq_enable(q_vector); 8235 8236 return work_done; 8237 } 8238 8239 /** 8240 * igb_clean_tx_irq - Reclaim resources after transmit completes 8241 * @q_vector: pointer to q_vector containing needed info 8242 * @napi_budget: Used to determine if we are in netpoll 8243 * 8244 * returns true if ring is completely cleaned 8245 **/ 8246 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8247 { 8248 struct igb_adapter *adapter = q_vector->adapter; 8249 struct igb_ring *tx_ring = q_vector->tx.ring; 8250 struct igb_tx_buffer *tx_buffer; 8251 union e1000_adv_tx_desc *tx_desc; 8252 unsigned int total_bytes = 0, total_packets = 0; 8253 unsigned int budget = q_vector->tx.work_limit; 8254 unsigned int i = tx_ring->next_to_clean; 8255 8256 if (test_bit(__IGB_DOWN, &adapter->state)) 8257 return true; 8258 8259 tx_buffer = &tx_ring->tx_buffer_info[i]; 8260 tx_desc = IGB_TX_DESC(tx_ring, i); 8261 i -= tx_ring->count; 8262 8263 do { 8264 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8265 8266 /* if next_to_watch is not set then there is no work pending */ 8267 if (!eop_desc) 8268 break; 8269 8270 /* prevent any other reads prior to eop_desc */ 8271 smp_rmb(); 8272 8273 /* if DD is not set pending work has not been completed */ 8274 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8275 break; 8276 8277 /* clear next_to_watch to prevent false hangs */ 8278 tx_buffer->next_to_watch = NULL; 8279 8280 /* update the statistics for this packet */ 8281 total_bytes += tx_buffer->bytecount; 8282 total_packets += tx_buffer->gso_segs; 8283 8284 /* free the skb */ 8285 if (tx_buffer->type == IGB_TYPE_SKB) 8286 napi_consume_skb(tx_buffer->skb, napi_budget); 8287 else 8288 xdp_return_frame(tx_buffer->xdpf); 8289 8290 /* unmap skb header data */ 8291 dma_unmap_single(tx_ring->dev, 8292 dma_unmap_addr(tx_buffer, dma), 8293 dma_unmap_len(tx_buffer, len), 8294 DMA_TO_DEVICE); 8295 8296 /* clear tx_buffer data */ 8297 dma_unmap_len_set(tx_buffer, len, 0); 8298 8299 /* clear last DMA location and unmap remaining buffers */ 8300 while (tx_desc != eop_desc) { 8301 tx_buffer++; 8302 tx_desc++; 8303 i++; 8304 if (unlikely(!i)) { 8305 i -= tx_ring->count; 8306 tx_buffer = tx_ring->tx_buffer_info; 8307 tx_desc = IGB_TX_DESC(tx_ring, 0); 8308 } 8309 8310 /* unmap any remaining paged data */ 8311 if (dma_unmap_len(tx_buffer, len)) { 8312 dma_unmap_page(tx_ring->dev, 8313 dma_unmap_addr(tx_buffer, dma), 8314 dma_unmap_len(tx_buffer, len), 8315 DMA_TO_DEVICE); 8316 dma_unmap_len_set(tx_buffer, len, 0); 8317 } 8318 } 8319 8320 /* move us one more past the eop_desc for start of next pkt */ 8321 tx_buffer++; 8322 tx_desc++; 8323 i++; 8324 if (unlikely(!i)) { 8325 i -= tx_ring->count; 8326 tx_buffer = tx_ring->tx_buffer_info; 8327 tx_desc = IGB_TX_DESC(tx_ring, 0); 8328 } 8329 8330 /* issue prefetch for next Tx descriptor */ 8331 prefetch(tx_desc); 8332 8333 /* update budget accounting */ 8334 budget--; 8335 } while (likely(budget)); 8336 8337 netdev_tx_completed_queue(txring_txq(tx_ring), 8338 total_packets, total_bytes); 8339 i += tx_ring->count; 8340 tx_ring->next_to_clean = i; 8341 u64_stats_update_begin(&tx_ring->tx_syncp); 8342 tx_ring->tx_stats.bytes += total_bytes; 8343 tx_ring->tx_stats.packets += total_packets; 8344 u64_stats_update_end(&tx_ring->tx_syncp); 8345 q_vector->tx.total_bytes += total_bytes; 8346 q_vector->tx.total_packets += total_packets; 8347 8348 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8349 struct e1000_hw *hw = &adapter->hw; 8350 8351 /* Detect a transmit hang in hardware, this serializes the 8352 * check with the clearing of time_stamp and movement of i 8353 */ 8354 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8355 if (tx_buffer->next_to_watch && 8356 time_after(jiffies, tx_buffer->time_stamp + 8357 (adapter->tx_timeout_factor * HZ)) && 8358 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8359 8360 /* detected Tx unit hang */ 8361 dev_err(tx_ring->dev, 8362 "Detected Tx Unit Hang\n" 8363 " Tx Queue <%d>\n" 8364 " TDH <%x>\n" 8365 " TDT <%x>\n" 8366 " next_to_use <%x>\n" 8367 " next_to_clean <%x>\n" 8368 "buffer_info[next_to_clean]\n" 8369 " time_stamp <%lx>\n" 8370 " next_to_watch <%p>\n" 8371 " jiffies <%lx>\n" 8372 " desc.status <%x>\n", 8373 tx_ring->queue_index, 8374 rd32(E1000_TDH(tx_ring->reg_idx)), 8375 readl(tx_ring->tail), 8376 tx_ring->next_to_use, 8377 tx_ring->next_to_clean, 8378 tx_buffer->time_stamp, 8379 tx_buffer->next_to_watch, 8380 jiffies, 8381 tx_buffer->next_to_watch->wb.status); 8382 netif_stop_subqueue(tx_ring->netdev, 8383 tx_ring->queue_index); 8384 8385 /* we are about to reset, no point in enabling stuff */ 8386 return true; 8387 } 8388 } 8389 8390 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8391 if (unlikely(total_packets && 8392 netif_carrier_ok(tx_ring->netdev) && 8393 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8394 /* Make sure that anybody stopping the queue after this 8395 * sees the new next_to_clean. 8396 */ 8397 smp_mb(); 8398 if (__netif_subqueue_stopped(tx_ring->netdev, 8399 tx_ring->queue_index) && 8400 !(test_bit(__IGB_DOWN, &adapter->state))) { 8401 netif_wake_subqueue(tx_ring->netdev, 8402 tx_ring->queue_index); 8403 8404 u64_stats_update_begin(&tx_ring->tx_syncp); 8405 tx_ring->tx_stats.restart_queue++; 8406 u64_stats_update_end(&tx_ring->tx_syncp); 8407 } 8408 } 8409 8410 return !!budget; 8411 } 8412 8413 /** 8414 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8415 * @rx_ring: rx descriptor ring to store buffers on 8416 * @old_buff: donor buffer to have page reused 8417 * 8418 * Synchronizes page for reuse by the adapter 8419 **/ 8420 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8421 struct igb_rx_buffer *old_buff) 8422 { 8423 struct igb_rx_buffer *new_buff; 8424 u16 nta = rx_ring->next_to_alloc; 8425 8426 new_buff = &rx_ring->rx_buffer_info[nta]; 8427 8428 /* update, and store next to alloc */ 8429 nta++; 8430 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8431 8432 /* Transfer page from old buffer to new buffer. 8433 * Move each member individually to avoid possible store 8434 * forwarding stalls. 8435 */ 8436 new_buff->dma = old_buff->dma; 8437 new_buff->page = old_buff->page; 8438 new_buff->page_offset = old_buff->page_offset; 8439 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8440 } 8441 8442 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8443 int rx_buf_pgcnt) 8444 { 8445 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8446 struct page *page = rx_buffer->page; 8447 8448 /* avoid re-using remote and pfmemalloc pages */ 8449 if (!dev_page_is_reusable(page)) 8450 return false; 8451 8452 #if (PAGE_SIZE < 8192) 8453 /* if we are only owner of page we can reuse it */ 8454 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8455 return false; 8456 #else 8457 #define IGB_LAST_OFFSET \ 8458 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8459 8460 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8461 return false; 8462 #endif 8463 8464 /* If we have drained the page fragment pool we need to update 8465 * the pagecnt_bias and page count so that we fully restock the 8466 * number of references the driver holds. 8467 */ 8468 if (unlikely(pagecnt_bias == 1)) { 8469 page_ref_add(page, USHRT_MAX - 1); 8470 rx_buffer->pagecnt_bias = USHRT_MAX; 8471 } 8472 8473 return true; 8474 } 8475 8476 /** 8477 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8478 * @rx_ring: rx descriptor ring to transact packets on 8479 * @rx_buffer: buffer containing page to add 8480 * @skb: sk_buff to place the data into 8481 * @size: size of buffer to be added 8482 * 8483 * This function will add the data contained in rx_buffer->page to the skb. 8484 **/ 8485 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8486 struct igb_rx_buffer *rx_buffer, 8487 struct sk_buff *skb, 8488 unsigned int size) 8489 { 8490 #if (PAGE_SIZE < 8192) 8491 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8492 #else 8493 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8494 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8495 SKB_DATA_ALIGN(size); 8496 #endif 8497 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8498 rx_buffer->page_offset, size, truesize); 8499 #if (PAGE_SIZE < 8192) 8500 rx_buffer->page_offset ^= truesize; 8501 #else 8502 rx_buffer->page_offset += truesize; 8503 #endif 8504 } 8505 8506 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8507 struct igb_rx_buffer *rx_buffer, 8508 struct xdp_buff *xdp, 8509 ktime_t timestamp) 8510 { 8511 #if (PAGE_SIZE < 8192) 8512 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8513 #else 8514 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8515 xdp->data_hard_start); 8516 #endif 8517 unsigned int size = xdp->data_end - xdp->data; 8518 unsigned int headlen; 8519 struct sk_buff *skb; 8520 8521 /* prefetch first cache line of first page */ 8522 net_prefetch(xdp->data); 8523 8524 /* allocate a skb to store the frags */ 8525 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8526 if (unlikely(!skb)) 8527 return NULL; 8528 8529 if (timestamp) 8530 skb_hwtstamps(skb)->hwtstamp = timestamp; 8531 8532 /* Determine available headroom for copy */ 8533 headlen = size; 8534 if (headlen > IGB_RX_HDR_LEN) 8535 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8536 8537 /* align pull length to size of long to optimize memcpy performance */ 8538 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8539 8540 /* update all of the pointers */ 8541 size -= headlen; 8542 if (size) { 8543 skb_add_rx_frag(skb, 0, rx_buffer->page, 8544 (xdp->data + headlen) - page_address(rx_buffer->page), 8545 size, truesize); 8546 #if (PAGE_SIZE < 8192) 8547 rx_buffer->page_offset ^= truesize; 8548 #else 8549 rx_buffer->page_offset += truesize; 8550 #endif 8551 } else { 8552 rx_buffer->pagecnt_bias++; 8553 } 8554 8555 return skb; 8556 } 8557 8558 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8559 struct igb_rx_buffer *rx_buffer, 8560 struct xdp_buff *xdp, 8561 ktime_t timestamp) 8562 { 8563 #if (PAGE_SIZE < 8192) 8564 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8565 #else 8566 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8567 SKB_DATA_ALIGN(xdp->data_end - 8568 xdp->data_hard_start); 8569 #endif 8570 unsigned int metasize = xdp->data - xdp->data_meta; 8571 struct sk_buff *skb; 8572 8573 /* prefetch first cache line of first page */ 8574 net_prefetch(xdp->data_meta); 8575 8576 /* build an skb around the page buffer */ 8577 skb = napi_build_skb(xdp->data_hard_start, truesize); 8578 if (unlikely(!skb)) 8579 return NULL; 8580 8581 /* update pointers within the skb to store the data */ 8582 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8583 __skb_put(skb, xdp->data_end - xdp->data); 8584 8585 if (metasize) 8586 skb_metadata_set(skb, metasize); 8587 8588 if (timestamp) 8589 skb_hwtstamps(skb)->hwtstamp = timestamp; 8590 8591 /* update buffer offset */ 8592 #if (PAGE_SIZE < 8192) 8593 rx_buffer->page_offset ^= truesize; 8594 #else 8595 rx_buffer->page_offset += truesize; 8596 #endif 8597 8598 return skb; 8599 } 8600 8601 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8602 struct igb_ring *rx_ring, 8603 struct xdp_buff *xdp) 8604 { 8605 int err, result = IGB_XDP_PASS; 8606 struct bpf_prog *xdp_prog; 8607 u32 act; 8608 8609 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8610 8611 if (!xdp_prog) 8612 goto xdp_out; 8613 8614 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8615 8616 act = bpf_prog_run_xdp(xdp_prog, xdp); 8617 switch (act) { 8618 case XDP_PASS: 8619 break; 8620 case XDP_TX: 8621 result = igb_xdp_xmit_back(adapter, xdp); 8622 if (result == IGB_XDP_CONSUMED) 8623 goto out_failure; 8624 break; 8625 case XDP_REDIRECT: 8626 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8627 if (err) 8628 goto out_failure; 8629 result = IGB_XDP_REDIR; 8630 break; 8631 default: 8632 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8633 fallthrough; 8634 case XDP_ABORTED: 8635 out_failure: 8636 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8637 fallthrough; 8638 case XDP_DROP: 8639 result = IGB_XDP_CONSUMED; 8640 break; 8641 } 8642 xdp_out: 8643 return ERR_PTR(-result); 8644 } 8645 8646 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8647 unsigned int size) 8648 { 8649 unsigned int truesize; 8650 8651 #if (PAGE_SIZE < 8192) 8652 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8653 #else 8654 truesize = ring_uses_build_skb(rx_ring) ? 8655 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8656 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8657 SKB_DATA_ALIGN(size); 8658 #endif 8659 return truesize; 8660 } 8661 8662 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8663 struct igb_rx_buffer *rx_buffer, 8664 unsigned int size) 8665 { 8666 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8667 #if (PAGE_SIZE < 8192) 8668 rx_buffer->page_offset ^= truesize; 8669 #else 8670 rx_buffer->page_offset += truesize; 8671 #endif 8672 } 8673 8674 static inline void igb_rx_checksum(struct igb_ring *ring, 8675 union e1000_adv_rx_desc *rx_desc, 8676 struct sk_buff *skb) 8677 { 8678 skb_checksum_none_assert(skb); 8679 8680 /* Ignore Checksum bit is set */ 8681 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8682 return; 8683 8684 /* Rx checksum disabled via ethtool */ 8685 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8686 return; 8687 8688 /* TCP/UDP checksum error bit is set */ 8689 if (igb_test_staterr(rx_desc, 8690 E1000_RXDEXT_STATERR_TCPE | 8691 E1000_RXDEXT_STATERR_IPE)) { 8692 /* work around errata with sctp packets where the TCPE aka 8693 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8694 * packets, (aka let the stack check the crc32c) 8695 */ 8696 if (!((skb->len == 60) && 8697 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8698 u64_stats_update_begin(&ring->rx_syncp); 8699 ring->rx_stats.csum_err++; 8700 u64_stats_update_end(&ring->rx_syncp); 8701 } 8702 /* let the stack verify checksum errors */ 8703 return; 8704 } 8705 /* It must be a TCP or UDP packet with a valid checksum */ 8706 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8707 E1000_RXD_STAT_UDPCS)) 8708 skb->ip_summed = CHECKSUM_UNNECESSARY; 8709 8710 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8711 le32_to_cpu(rx_desc->wb.upper.status_error)); 8712 } 8713 8714 static inline void igb_rx_hash(struct igb_ring *ring, 8715 union e1000_adv_rx_desc *rx_desc, 8716 struct sk_buff *skb) 8717 { 8718 if (ring->netdev->features & NETIF_F_RXHASH) 8719 skb_set_hash(skb, 8720 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8721 PKT_HASH_TYPE_L3); 8722 } 8723 8724 /** 8725 * igb_is_non_eop - process handling of non-EOP buffers 8726 * @rx_ring: Rx ring being processed 8727 * @rx_desc: Rx descriptor for current buffer 8728 * 8729 * This function updates next to clean. If the buffer is an EOP buffer 8730 * this function exits returning false, otherwise it will place the 8731 * sk_buff in the next buffer to be chained and return true indicating 8732 * that this is in fact a non-EOP buffer. 8733 **/ 8734 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8735 union e1000_adv_rx_desc *rx_desc) 8736 { 8737 u32 ntc = rx_ring->next_to_clean + 1; 8738 8739 /* fetch, update, and store next to clean */ 8740 ntc = (ntc < rx_ring->count) ? ntc : 0; 8741 rx_ring->next_to_clean = ntc; 8742 8743 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8744 8745 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8746 return false; 8747 8748 return true; 8749 } 8750 8751 /** 8752 * igb_cleanup_headers - Correct corrupted or empty headers 8753 * @rx_ring: rx descriptor ring packet is being transacted on 8754 * @rx_desc: pointer to the EOP Rx descriptor 8755 * @skb: pointer to current skb being fixed 8756 * 8757 * Address the case where we are pulling data in on pages only 8758 * and as such no data is present in the skb header. 8759 * 8760 * In addition if skb is not at least 60 bytes we need to pad it so that 8761 * it is large enough to qualify as a valid Ethernet frame. 8762 * 8763 * Returns true if an error was encountered and skb was freed. 8764 **/ 8765 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8766 union e1000_adv_rx_desc *rx_desc, 8767 struct sk_buff *skb) 8768 { 8769 /* XDP packets use error pointer so abort at this point */ 8770 if (IS_ERR(skb)) 8771 return true; 8772 8773 if (unlikely((igb_test_staterr(rx_desc, 8774 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8775 struct net_device *netdev = rx_ring->netdev; 8776 if (!(netdev->features & NETIF_F_RXALL)) { 8777 dev_kfree_skb_any(skb); 8778 return true; 8779 } 8780 } 8781 8782 /* if eth_skb_pad returns an error the skb was freed */ 8783 if (eth_skb_pad(skb)) 8784 return true; 8785 8786 return false; 8787 } 8788 8789 /** 8790 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8791 * @rx_ring: rx descriptor ring packet is being transacted on 8792 * @rx_desc: pointer to the EOP Rx descriptor 8793 * @skb: pointer to current skb being populated 8794 * 8795 * This function checks the ring, descriptor, and packet information in 8796 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8797 * other fields within the skb. 8798 **/ 8799 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8800 union e1000_adv_rx_desc *rx_desc, 8801 struct sk_buff *skb) 8802 { 8803 struct net_device *dev = rx_ring->netdev; 8804 8805 igb_rx_hash(rx_ring, rx_desc, skb); 8806 8807 igb_rx_checksum(rx_ring, rx_desc, skb); 8808 8809 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8810 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8811 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8812 8813 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8814 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8815 u16 vid; 8816 8817 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8818 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8819 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8820 else 8821 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8822 8823 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8824 } 8825 8826 skb_record_rx_queue(skb, rx_ring->queue_index); 8827 8828 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8829 } 8830 8831 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8832 { 8833 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8834 } 8835 8836 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8837 const unsigned int size, int *rx_buf_pgcnt) 8838 { 8839 struct igb_rx_buffer *rx_buffer; 8840 8841 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8842 *rx_buf_pgcnt = 8843 #if (PAGE_SIZE < 8192) 8844 page_count(rx_buffer->page); 8845 #else 8846 0; 8847 #endif 8848 prefetchw(rx_buffer->page); 8849 8850 /* we are reusing so sync this buffer for CPU use */ 8851 dma_sync_single_range_for_cpu(rx_ring->dev, 8852 rx_buffer->dma, 8853 rx_buffer->page_offset, 8854 size, 8855 DMA_FROM_DEVICE); 8856 8857 rx_buffer->pagecnt_bias--; 8858 8859 return rx_buffer; 8860 } 8861 8862 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8863 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8864 { 8865 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8866 /* hand second half of page back to the ring */ 8867 igb_reuse_rx_page(rx_ring, rx_buffer); 8868 } else { 8869 /* We are not reusing the buffer so unmap it and free 8870 * any references we are holding to it 8871 */ 8872 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8873 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8874 IGB_RX_DMA_ATTR); 8875 __page_frag_cache_drain(rx_buffer->page, 8876 rx_buffer->pagecnt_bias); 8877 } 8878 8879 /* clear contents of rx_buffer */ 8880 rx_buffer->page = NULL; 8881 } 8882 8883 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8884 { 8885 struct igb_adapter *adapter = q_vector->adapter; 8886 struct igb_ring *rx_ring = q_vector->rx.ring; 8887 struct sk_buff *skb = rx_ring->skb; 8888 unsigned int total_bytes = 0, total_packets = 0; 8889 u16 cleaned_count = igb_desc_unused(rx_ring); 8890 unsigned int xdp_xmit = 0; 8891 struct xdp_buff xdp; 8892 u32 frame_sz = 0; 8893 int rx_buf_pgcnt; 8894 8895 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8896 #if (PAGE_SIZE < 8192) 8897 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8898 #endif 8899 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8900 8901 while (likely(total_packets < budget)) { 8902 union e1000_adv_rx_desc *rx_desc; 8903 struct igb_rx_buffer *rx_buffer; 8904 ktime_t timestamp = 0; 8905 int pkt_offset = 0; 8906 unsigned int size; 8907 void *pktbuf; 8908 8909 /* return some buffers to hardware, one at a time is too slow */ 8910 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8911 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8912 cleaned_count = 0; 8913 } 8914 8915 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8916 size = le16_to_cpu(rx_desc->wb.upper.length); 8917 if (!size) 8918 break; 8919 8920 /* This memory barrier is needed to keep us from reading 8921 * any other fields out of the rx_desc until we know the 8922 * descriptor has been written back 8923 */ 8924 dma_rmb(); 8925 8926 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8927 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8928 8929 /* pull rx packet timestamp if available and valid */ 8930 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8931 int ts_hdr_len; 8932 8933 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8934 pktbuf, ×tamp); 8935 8936 pkt_offset += ts_hdr_len; 8937 size -= ts_hdr_len; 8938 } 8939 8940 /* retrieve a buffer from the ring */ 8941 if (!skb) { 8942 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8943 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8944 8945 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8946 xdp_buff_clear_frags_flag(&xdp); 8947 #if (PAGE_SIZE > 4096) 8948 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8949 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8950 #endif 8951 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8952 } 8953 8954 if (IS_ERR(skb)) { 8955 unsigned int xdp_res = -PTR_ERR(skb); 8956 8957 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8958 xdp_xmit |= xdp_res; 8959 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8960 } else { 8961 rx_buffer->pagecnt_bias++; 8962 } 8963 total_packets++; 8964 total_bytes += size; 8965 } else if (skb) 8966 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8967 else if (ring_uses_build_skb(rx_ring)) 8968 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8969 timestamp); 8970 else 8971 skb = igb_construct_skb(rx_ring, rx_buffer, 8972 &xdp, timestamp); 8973 8974 /* exit if we failed to retrieve a buffer */ 8975 if (!skb) { 8976 rx_ring->rx_stats.alloc_failed++; 8977 rx_buffer->pagecnt_bias++; 8978 break; 8979 } 8980 8981 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8982 cleaned_count++; 8983 8984 /* fetch next buffer in frame if non-eop */ 8985 if (igb_is_non_eop(rx_ring, rx_desc)) 8986 continue; 8987 8988 /* verify the packet layout is correct */ 8989 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8990 skb = NULL; 8991 continue; 8992 } 8993 8994 /* probably a little skewed due to removing CRC */ 8995 total_bytes += skb->len; 8996 8997 /* populate checksum, timestamp, VLAN, and protocol */ 8998 igb_process_skb_fields(rx_ring, rx_desc, skb); 8999 9000 napi_gro_receive(&q_vector->napi, skb); 9001 9002 /* reset skb pointer */ 9003 skb = NULL; 9004 9005 /* update budget accounting */ 9006 total_packets++; 9007 } 9008 9009 /* place incomplete frames back on ring for completion */ 9010 rx_ring->skb = skb; 9011 9012 if (xdp_xmit & IGB_XDP_REDIR) 9013 xdp_do_flush(); 9014 9015 if (xdp_xmit & IGB_XDP_TX) { 9016 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 9017 9018 igb_xdp_ring_update_tail(tx_ring); 9019 } 9020 9021 u64_stats_update_begin(&rx_ring->rx_syncp); 9022 rx_ring->rx_stats.packets += total_packets; 9023 rx_ring->rx_stats.bytes += total_bytes; 9024 u64_stats_update_end(&rx_ring->rx_syncp); 9025 q_vector->rx.total_packets += total_packets; 9026 q_vector->rx.total_bytes += total_bytes; 9027 9028 if (cleaned_count) 9029 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9030 9031 return total_packets; 9032 } 9033 9034 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9035 struct igb_rx_buffer *bi) 9036 { 9037 struct page *page = bi->page; 9038 dma_addr_t dma; 9039 9040 /* since we are recycling buffers we should seldom need to alloc */ 9041 if (likely(page)) 9042 return true; 9043 9044 /* alloc new page for storage */ 9045 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9046 if (unlikely(!page)) { 9047 rx_ring->rx_stats.alloc_failed++; 9048 return false; 9049 } 9050 9051 /* map page for use */ 9052 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9053 igb_rx_pg_size(rx_ring), 9054 DMA_FROM_DEVICE, 9055 IGB_RX_DMA_ATTR); 9056 9057 /* if mapping failed free memory back to system since 9058 * there isn't much point in holding memory we can't use 9059 */ 9060 if (dma_mapping_error(rx_ring->dev, dma)) { 9061 __free_pages(page, igb_rx_pg_order(rx_ring)); 9062 9063 rx_ring->rx_stats.alloc_failed++; 9064 return false; 9065 } 9066 9067 bi->dma = dma; 9068 bi->page = page; 9069 bi->page_offset = igb_rx_offset(rx_ring); 9070 page_ref_add(page, USHRT_MAX - 1); 9071 bi->pagecnt_bias = USHRT_MAX; 9072 9073 return true; 9074 } 9075 9076 /** 9077 * igb_alloc_rx_buffers - Replace used receive buffers 9078 * @rx_ring: rx descriptor ring to allocate new receive buffers 9079 * @cleaned_count: count of buffers to allocate 9080 **/ 9081 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9082 { 9083 union e1000_adv_rx_desc *rx_desc; 9084 struct igb_rx_buffer *bi; 9085 u16 i = rx_ring->next_to_use; 9086 u16 bufsz; 9087 9088 /* nothing to do */ 9089 if (!cleaned_count) 9090 return; 9091 9092 rx_desc = IGB_RX_DESC(rx_ring, i); 9093 bi = &rx_ring->rx_buffer_info[i]; 9094 i -= rx_ring->count; 9095 9096 bufsz = igb_rx_bufsz(rx_ring); 9097 9098 do { 9099 if (!igb_alloc_mapped_page(rx_ring, bi)) 9100 break; 9101 9102 /* sync the buffer for use by the device */ 9103 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9104 bi->page_offset, bufsz, 9105 DMA_FROM_DEVICE); 9106 9107 /* Refresh the desc even if buffer_addrs didn't change 9108 * because each write-back erases this info. 9109 */ 9110 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9111 9112 rx_desc++; 9113 bi++; 9114 i++; 9115 if (unlikely(!i)) { 9116 rx_desc = IGB_RX_DESC(rx_ring, 0); 9117 bi = rx_ring->rx_buffer_info; 9118 i -= rx_ring->count; 9119 } 9120 9121 /* clear the length for the next_to_use descriptor */ 9122 rx_desc->wb.upper.length = 0; 9123 9124 cleaned_count--; 9125 } while (cleaned_count); 9126 9127 i += rx_ring->count; 9128 9129 if (rx_ring->next_to_use != i) { 9130 /* record the next descriptor to use */ 9131 rx_ring->next_to_use = i; 9132 9133 /* update next to alloc since we have filled the ring */ 9134 rx_ring->next_to_alloc = i; 9135 9136 /* Force memory writes to complete before letting h/w 9137 * know there are new descriptors to fetch. (Only 9138 * applicable for weak-ordered memory model archs, 9139 * such as IA-64). 9140 */ 9141 dma_wmb(); 9142 writel(i, rx_ring->tail); 9143 } 9144 } 9145 9146 /** 9147 * igb_mii_ioctl - 9148 * @netdev: pointer to netdev struct 9149 * @ifr: interface structure 9150 * @cmd: ioctl command to execute 9151 **/ 9152 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9153 { 9154 struct igb_adapter *adapter = netdev_priv(netdev); 9155 struct mii_ioctl_data *data = if_mii(ifr); 9156 9157 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9158 return -EOPNOTSUPP; 9159 9160 switch (cmd) { 9161 case SIOCGMIIPHY: 9162 data->phy_id = adapter->hw.phy.addr; 9163 break; 9164 case SIOCGMIIREG: 9165 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9166 &data->val_out)) 9167 return -EIO; 9168 break; 9169 case SIOCSMIIREG: 9170 default: 9171 return -EOPNOTSUPP; 9172 } 9173 return 0; 9174 } 9175 9176 /** 9177 * igb_ioctl - 9178 * @netdev: pointer to netdev struct 9179 * @ifr: interface structure 9180 * @cmd: ioctl command to execute 9181 **/ 9182 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9183 { 9184 switch (cmd) { 9185 case SIOCGMIIPHY: 9186 case SIOCGMIIREG: 9187 case SIOCSMIIREG: 9188 return igb_mii_ioctl(netdev, ifr, cmd); 9189 case SIOCGHWTSTAMP: 9190 return igb_ptp_get_ts_config(netdev, ifr); 9191 case SIOCSHWTSTAMP: 9192 return igb_ptp_set_ts_config(netdev, ifr); 9193 default: 9194 return -EOPNOTSUPP; 9195 } 9196 } 9197 9198 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9199 { 9200 struct igb_adapter *adapter = hw->back; 9201 9202 pci_read_config_word(adapter->pdev, reg, value); 9203 } 9204 9205 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9206 { 9207 struct igb_adapter *adapter = hw->back; 9208 9209 pci_write_config_word(adapter->pdev, reg, *value); 9210 } 9211 9212 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9213 { 9214 struct igb_adapter *adapter = hw->back; 9215 9216 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9217 return -E1000_ERR_CONFIG; 9218 9219 return 0; 9220 } 9221 9222 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9223 { 9224 struct igb_adapter *adapter = hw->back; 9225 9226 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9227 return -E1000_ERR_CONFIG; 9228 9229 return 0; 9230 } 9231 9232 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9233 { 9234 struct igb_adapter *adapter = netdev_priv(netdev); 9235 struct e1000_hw *hw = &adapter->hw; 9236 u32 ctrl, rctl; 9237 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9238 9239 if (enable) { 9240 /* enable VLAN tag insert/strip */ 9241 ctrl = rd32(E1000_CTRL); 9242 ctrl |= E1000_CTRL_VME; 9243 wr32(E1000_CTRL, ctrl); 9244 9245 /* Disable CFI check */ 9246 rctl = rd32(E1000_RCTL); 9247 rctl &= ~E1000_RCTL_CFIEN; 9248 wr32(E1000_RCTL, rctl); 9249 } else { 9250 /* disable VLAN tag insert/strip */ 9251 ctrl = rd32(E1000_CTRL); 9252 ctrl &= ~E1000_CTRL_VME; 9253 wr32(E1000_CTRL, ctrl); 9254 } 9255 9256 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9257 } 9258 9259 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9260 __be16 proto, u16 vid) 9261 { 9262 struct igb_adapter *adapter = netdev_priv(netdev); 9263 struct e1000_hw *hw = &adapter->hw; 9264 int pf_id = adapter->vfs_allocated_count; 9265 9266 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9267 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9268 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9269 9270 set_bit(vid, adapter->active_vlans); 9271 9272 return 0; 9273 } 9274 9275 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9276 __be16 proto, u16 vid) 9277 { 9278 struct igb_adapter *adapter = netdev_priv(netdev); 9279 int pf_id = adapter->vfs_allocated_count; 9280 struct e1000_hw *hw = &adapter->hw; 9281 9282 /* remove VID from filter table */ 9283 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9284 igb_vfta_set(hw, vid, pf_id, false, true); 9285 9286 clear_bit(vid, adapter->active_vlans); 9287 9288 return 0; 9289 } 9290 9291 static void igb_restore_vlan(struct igb_adapter *adapter) 9292 { 9293 u16 vid = 1; 9294 9295 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9296 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9297 9298 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9299 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9300 } 9301 9302 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9303 { 9304 struct pci_dev *pdev = adapter->pdev; 9305 struct e1000_mac_info *mac = &adapter->hw.mac; 9306 9307 mac->autoneg = 0; 9308 9309 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9310 * for the switch() below to work 9311 */ 9312 if ((spd & 1) || (dplx & ~1)) 9313 goto err_inval; 9314 9315 /* Fiber NIC's only allow 1000 gbps Full duplex 9316 * and 100Mbps Full duplex for 100baseFx sfp 9317 */ 9318 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9319 switch (spd + dplx) { 9320 case SPEED_10 + DUPLEX_HALF: 9321 case SPEED_10 + DUPLEX_FULL: 9322 case SPEED_100 + DUPLEX_HALF: 9323 goto err_inval; 9324 default: 9325 break; 9326 } 9327 } 9328 9329 switch (spd + dplx) { 9330 case SPEED_10 + DUPLEX_HALF: 9331 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9332 break; 9333 case SPEED_10 + DUPLEX_FULL: 9334 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9335 break; 9336 case SPEED_100 + DUPLEX_HALF: 9337 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9338 break; 9339 case SPEED_100 + DUPLEX_FULL: 9340 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9341 break; 9342 case SPEED_1000 + DUPLEX_FULL: 9343 mac->autoneg = 1; 9344 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9345 break; 9346 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9347 default: 9348 goto err_inval; 9349 } 9350 9351 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9352 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9353 9354 return 0; 9355 9356 err_inval: 9357 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9358 return -EINVAL; 9359 } 9360 9361 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9362 bool runtime) 9363 { 9364 struct net_device *netdev = pci_get_drvdata(pdev); 9365 struct igb_adapter *adapter = netdev_priv(netdev); 9366 struct e1000_hw *hw = &adapter->hw; 9367 u32 ctrl, rctl, status; 9368 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9369 bool wake; 9370 9371 rtnl_lock(); 9372 netif_device_detach(netdev); 9373 9374 if (netif_running(netdev)) 9375 __igb_close(netdev, true); 9376 9377 igb_ptp_suspend(adapter); 9378 9379 igb_clear_interrupt_scheme(adapter); 9380 rtnl_unlock(); 9381 9382 status = rd32(E1000_STATUS); 9383 if (status & E1000_STATUS_LU) 9384 wufc &= ~E1000_WUFC_LNKC; 9385 9386 if (wufc) { 9387 igb_setup_rctl(adapter); 9388 igb_set_rx_mode(netdev); 9389 9390 /* turn on all-multi mode if wake on multicast is enabled */ 9391 if (wufc & E1000_WUFC_MC) { 9392 rctl = rd32(E1000_RCTL); 9393 rctl |= E1000_RCTL_MPE; 9394 wr32(E1000_RCTL, rctl); 9395 } 9396 9397 ctrl = rd32(E1000_CTRL); 9398 ctrl |= E1000_CTRL_ADVD3WUC; 9399 wr32(E1000_CTRL, ctrl); 9400 9401 /* Allow time for pending master requests to run */ 9402 igb_disable_pcie_master(hw); 9403 9404 wr32(E1000_WUC, E1000_WUC_PME_EN); 9405 wr32(E1000_WUFC, wufc); 9406 } else { 9407 wr32(E1000_WUC, 0); 9408 wr32(E1000_WUFC, 0); 9409 } 9410 9411 wake = wufc || adapter->en_mng_pt; 9412 if (!wake) 9413 igb_power_down_link(adapter); 9414 else 9415 igb_power_up_link(adapter); 9416 9417 if (enable_wake) 9418 *enable_wake = wake; 9419 9420 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9421 * would have already happened in close and is redundant. 9422 */ 9423 igb_release_hw_control(adapter); 9424 9425 pci_disable_device(pdev); 9426 9427 return 0; 9428 } 9429 9430 static void igb_deliver_wake_packet(struct net_device *netdev) 9431 { 9432 struct igb_adapter *adapter = netdev_priv(netdev); 9433 struct e1000_hw *hw = &adapter->hw; 9434 struct sk_buff *skb; 9435 u32 wupl; 9436 9437 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9438 9439 /* WUPM stores only the first 128 bytes of the wake packet. 9440 * Read the packet only if we have the whole thing. 9441 */ 9442 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9443 return; 9444 9445 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9446 if (!skb) 9447 return; 9448 9449 skb_put(skb, wupl); 9450 9451 /* Ensure reads are 32-bit aligned */ 9452 wupl = roundup(wupl, 4); 9453 9454 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9455 9456 skb->protocol = eth_type_trans(skb, netdev); 9457 netif_rx(skb); 9458 } 9459 9460 static int __maybe_unused igb_suspend(struct device *dev) 9461 { 9462 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9463 } 9464 9465 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9466 { 9467 struct pci_dev *pdev = to_pci_dev(dev); 9468 struct net_device *netdev = pci_get_drvdata(pdev); 9469 struct igb_adapter *adapter = netdev_priv(netdev); 9470 struct e1000_hw *hw = &adapter->hw; 9471 u32 err, val; 9472 9473 pci_set_power_state(pdev, PCI_D0); 9474 pci_restore_state(pdev); 9475 pci_save_state(pdev); 9476 9477 if (!pci_device_is_present(pdev)) 9478 return -ENODEV; 9479 err = pci_enable_device_mem(pdev); 9480 if (err) { 9481 dev_err(&pdev->dev, 9482 "igb: Cannot enable PCI device from suspend\n"); 9483 return err; 9484 } 9485 pci_set_master(pdev); 9486 9487 pci_enable_wake(pdev, PCI_D3hot, 0); 9488 pci_enable_wake(pdev, PCI_D3cold, 0); 9489 9490 if (igb_init_interrupt_scheme(adapter, true)) { 9491 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9492 return -ENOMEM; 9493 } 9494 9495 igb_reset(adapter); 9496 9497 /* let the f/w know that the h/w is now under the control of the 9498 * driver. 9499 */ 9500 igb_get_hw_control(adapter); 9501 9502 val = rd32(E1000_WUS); 9503 if (val & WAKE_PKT_WUS) 9504 igb_deliver_wake_packet(netdev); 9505 9506 wr32(E1000_WUS, ~0); 9507 9508 if (!rpm) 9509 rtnl_lock(); 9510 if (!err && netif_running(netdev)) 9511 err = __igb_open(netdev, true); 9512 9513 if (!err) 9514 netif_device_attach(netdev); 9515 if (!rpm) 9516 rtnl_unlock(); 9517 9518 return err; 9519 } 9520 9521 static int __maybe_unused igb_resume(struct device *dev) 9522 { 9523 return __igb_resume(dev, false); 9524 } 9525 9526 static int __maybe_unused igb_runtime_idle(struct device *dev) 9527 { 9528 struct net_device *netdev = dev_get_drvdata(dev); 9529 struct igb_adapter *adapter = netdev_priv(netdev); 9530 9531 if (!igb_has_link(adapter)) 9532 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9533 9534 return -EBUSY; 9535 } 9536 9537 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9538 { 9539 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9540 } 9541 9542 static int __maybe_unused igb_runtime_resume(struct device *dev) 9543 { 9544 return __igb_resume(dev, true); 9545 } 9546 9547 static void igb_shutdown(struct pci_dev *pdev) 9548 { 9549 bool wake; 9550 9551 __igb_shutdown(pdev, &wake, 0); 9552 9553 if (system_state == SYSTEM_POWER_OFF) { 9554 pci_wake_from_d3(pdev, wake); 9555 pci_set_power_state(pdev, PCI_D3hot); 9556 } 9557 } 9558 9559 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9560 { 9561 #ifdef CONFIG_PCI_IOV 9562 int err; 9563 9564 if (num_vfs == 0) { 9565 return igb_disable_sriov(dev, true); 9566 } else { 9567 err = igb_enable_sriov(dev, num_vfs, true); 9568 return err ? err : num_vfs; 9569 } 9570 #endif 9571 return 0; 9572 } 9573 9574 /** 9575 * igb_io_error_detected - called when PCI error is detected 9576 * @pdev: Pointer to PCI device 9577 * @state: The current pci connection state 9578 * 9579 * This function is called after a PCI bus error affecting 9580 * this device has been detected. 9581 **/ 9582 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9583 pci_channel_state_t state) 9584 { 9585 struct net_device *netdev = pci_get_drvdata(pdev); 9586 struct igb_adapter *adapter = netdev_priv(netdev); 9587 9588 netif_device_detach(netdev); 9589 9590 if (state == pci_channel_io_perm_failure) 9591 return PCI_ERS_RESULT_DISCONNECT; 9592 9593 if (netif_running(netdev)) 9594 igb_down(adapter); 9595 pci_disable_device(pdev); 9596 9597 /* Request a slot reset. */ 9598 return PCI_ERS_RESULT_NEED_RESET; 9599 } 9600 9601 /** 9602 * igb_io_slot_reset - called after the pci bus has been reset. 9603 * @pdev: Pointer to PCI device 9604 * 9605 * Restart the card from scratch, as if from a cold-boot. Implementation 9606 * resembles the first-half of the __igb_resume routine. 9607 **/ 9608 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9609 { 9610 struct net_device *netdev = pci_get_drvdata(pdev); 9611 struct igb_adapter *adapter = netdev_priv(netdev); 9612 struct e1000_hw *hw = &adapter->hw; 9613 pci_ers_result_t result; 9614 9615 if (pci_enable_device_mem(pdev)) { 9616 dev_err(&pdev->dev, 9617 "Cannot re-enable PCI device after reset.\n"); 9618 result = PCI_ERS_RESULT_DISCONNECT; 9619 } else { 9620 pci_set_master(pdev); 9621 pci_restore_state(pdev); 9622 pci_save_state(pdev); 9623 9624 pci_enable_wake(pdev, PCI_D3hot, 0); 9625 pci_enable_wake(pdev, PCI_D3cold, 0); 9626 9627 /* In case of PCI error, adapter lose its HW address 9628 * so we should re-assign it here. 9629 */ 9630 hw->hw_addr = adapter->io_addr; 9631 9632 igb_reset(adapter); 9633 wr32(E1000_WUS, ~0); 9634 result = PCI_ERS_RESULT_RECOVERED; 9635 } 9636 9637 return result; 9638 } 9639 9640 /** 9641 * igb_io_resume - called when traffic can start flowing again. 9642 * @pdev: Pointer to PCI device 9643 * 9644 * This callback is called when the error recovery driver tells us that 9645 * its OK to resume normal operation. Implementation resembles the 9646 * second-half of the __igb_resume routine. 9647 */ 9648 static void igb_io_resume(struct pci_dev *pdev) 9649 { 9650 struct net_device *netdev = pci_get_drvdata(pdev); 9651 struct igb_adapter *adapter = netdev_priv(netdev); 9652 9653 if (netif_running(netdev)) { 9654 if (igb_up(adapter)) { 9655 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9656 return; 9657 } 9658 } 9659 9660 netif_device_attach(netdev); 9661 9662 /* let the f/w know that the h/w is now under the control of the 9663 * driver. 9664 */ 9665 igb_get_hw_control(adapter); 9666 } 9667 9668 /** 9669 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9670 * @adapter: Pointer to adapter structure 9671 * @index: Index of the RAR entry which need to be synced with MAC table 9672 **/ 9673 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9674 { 9675 struct e1000_hw *hw = &adapter->hw; 9676 u32 rar_low, rar_high; 9677 u8 *addr = adapter->mac_table[index].addr; 9678 9679 /* HW expects these to be in network order when they are plugged 9680 * into the registers which are little endian. In order to guarantee 9681 * that ordering we need to do an leXX_to_cpup here in order to be 9682 * ready for the byteswap that occurs with writel 9683 */ 9684 rar_low = le32_to_cpup((__le32 *)(addr)); 9685 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9686 9687 /* Indicate to hardware the Address is Valid. */ 9688 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9689 if (is_valid_ether_addr(addr)) 9690 rar_high |= E1000_RAH_AV; 9691 9692 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9693 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9694 9695 switch (hw->mac.type) { 9696 case e1000_82575: 9697 case e1000_i210: 9698 if (adapter->mac_table[index].state & 9699 IGB_MAC_STATE_QUEUE_STEERING) 9700 rar_high |= E1000_RAH_QSEL_ENABLE; 9701 9702 rar_high |= E1000_RAH_POOL_1 * 9703 adapter->mac_table[index].queue; 9704 break; 9705 default: 9706 rar_high |= E1000_RAH_POOL_1 << 9707 adapter->mac_table[index].queue; 9708 break; 9709 } 9710 } 9711 9712 wr32(E1000_RAL(index), rar_low); 9713 wrfl(); 9714 wr32(E1000_RAH(index), rar_high); 9715 wrfl(); 9716 } 9717 9718 static int igb_set_vf_mac(struct igb_adapter *adapter, 9719 int vf, unsigned char *mac_addr) 9720 { 9721 struct e1000_hw *hw = &adapter->hw; 9722 /* VF MAC addresses start at end of receive addresses and moves 9723 * towards the first, as a result a collision should not be possible 9724 */ 9725 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9726 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9727 9728 ether_addr_copy(vf_mac_addr, mac_addr); 9729 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9730 adapter->mac_table[rar_entry].queue = vf; 9731 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9732 igb_rar_set_index(adapter, rar_entry); 9733 9734 return 0; 9735 } 9736 9737 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9738 { 9739 struct igb_adapter *adapter = netdev_priv(netdev); 9740 9741 if (vf >= adapter->vfs_allocated_count) 9742 return -EINVAL; 9743 9744 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9745 * flag and allows to overwrite the MAC via VF netdev. This 9746 * is necessary to allow libvirt a way to restore the original 9747 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9748 * down a VM. 9749 */ 9750 if (is_zero_ether_addr(mac)) { 9751 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9752 dev_info(&adapter->pdev->dev, 9753 "remove administratively set MAC on VF %d\n", 9754 vf); 9755 } else if (is_valid_ether_addr(mac)) { 9756 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9757 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9758 mac, vf); 9759 dev_info(&adapter->pdev->dev, 9760 "Reload the VF driver to make this change effective."); 9761 /* Generate additional warning if PF is down */ 9762 if (test_bit(__IGB_DOWN, &adapter->state)) { 9763 dev_warn(&adapter->pdev->dev, 9764 "The VF MAC address has been set, but the PF device is not up.\n"); 9765 dev_warn(&adapter->pdev->dev, 9766 "Bring the PF device up before attempting to use the VF device.\n"); 9767 } 9768 } else { 9769 return -EINVAL; 9770 } 9771 return igb_set_vf_mac(adapter, vf, mac); 9772 } 9773 9774 static int igb_link_mbps(int internal_link_speed) 9775 { 9776 switch (internal_link_speed) { 9777 case SPEED_100: 9778 return 100; 9779 case SPEED_1000: 9780 return 1000; 9781 default: 9782 return 0; 9783 } 9784 } 9785 9786 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9787 int link_speed) 9788 { 9789 int rf_dec, rf_int; 9790 u32 bcnrc_val; 9791 9792 if (tx_rate != 0) { 9793 /* Calculate the rate factor values to set */ 9794 rf_int = link_speed / tx_rate; 9795 rf_dec = (link_speed - (rf_int * tx_rate)); 9796 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9797 tx_rate; 9798 9799 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9800 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9801 E1000_RTTBCNRC_RF_INT_MASK); 9802 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9803 } else { 9804 bcnrc_val = 0; 9805 } 9806 9807 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9808 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9809 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9810 */ 9811 wr32(E1000_RTTBCNRM, 0x14); 9812 wr32(E1000_RTTBCNRC, bcnrc_val); 9813 } 9814 9815 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9816 { 9817 int actual_link_speed, i; 9818 bool reset_rate = false; 9819 9820 /* VF TX rate limit was not set or not supported */ 9821 if ((adapter->vf_rate_link_speed == 0) || 9822 (adapter->hw.mac.type != e1000_82576)) 9823 return; 9824 9825 actual_link_speed = igb_link_mbps(adapter->link_speed); 9826 if (actual_link_speed != adapter->vf_rate_link_speed) { 9827 reset_rate = true; 9828 adapter->vf_rate_link_speed = 0; 9829 dev_info(&adapter->pdev->dev, 9830 "Link speed has been changed. VF Transmit rate is disabled\n"); 9831 } 9832 9833 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9834 if (reset_rate) 9835 adapter->vf_data[i].tx_rate = 0; 9836 9837 igb_set_vf_rate_limit(&adapter->hw, i, 9838 adapter->vf_data[i].tx_rate, 9839 actual_link_speed); 9840 } 9841 } 9842 9843 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9844 int min_tx_rate, int max_tx_rate) 9845 { 9846 struct igb_adapter *adapter = netdev_priv(netdev); 9847 struct e1000_hw *hw = &adapter->hw; 9848 int actual_link_speed; 9849 9850 if (hw->mac.type != e1000_82576) 9851 return -EOPNOTSUPP; 9852 9853 if (min_tx_rate) 9854 return -EINVAL; 9855 9856 actual_link_speed = igb_link_mbps(adapter->link_speed); 9857 if ((vf >= adapter->vfs_allocated_count) || 9858 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9859 (max_tx_rate < 0) || 9860 (max_tx_rate > actual_link_speed)) 9861 return -EINVAL; 9862 9863 adapter->vf_rate_link_speed = actual_link_speed; 9864 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9865 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9866 9867 return 0; 9868 } 9869 9870 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9871 bool setting) 9872 { 9873 struct igb_adapter *adapter = netdev_priv(netdev); 9874 struct e1000_hw *hw = &adapter->hw; 9875 u32 reg_val, reg_offset; 9876 9877 if (!adapter->vfs_allocated_count) 9878 return -EOPNOTSUPP; 9879 9880 if (vf >= adapter->vfs_allocated_count) 9881 return -EINVAL; 9882 9883 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9884 reg_val = rd32(reg_offset); 9885 if (setting) 9886 reg_val |= (BIT(vf) | 9887 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9888 else 9889 reg_val &= ~(BIT(vf) | 9890 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9891 wr32(reg_offset, reg_val); 9892 9893 adapter->vf_data[vf].spoofchk_enabled = setting; 9894 return 0; 9895 } 9896 9897 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9898 { 9899 struct igb_adapter *adapter = netdev_priv(netdev); 9900 9901 if (vf >= adapter->vfs_allocated_count) 9902 return -EINVAL; 9903 if (adapter->vf_data[vf].trusted == setting) 9904 return 0; 9905 9906 adapter->vf_data[vf].trusted = setting; 9907 9908 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9909 vf, setting ? "" : "not "); 9910 return 0; 9911 } 9912 9913 static int igb_ndo_get_vf_config(struct net_device *netdev, 9914 int vf, struct ifla_vf_info *ivi) 9915 { 9916 struct igb_adapter *adapter = netdev_priv(netdev); 9917 if (vf >= adapter->vfs_allocated_count) 9918 return -EINVAL; 9919 ivi->vf = vf; 9920 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9921 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9922 ivi->min_tx_rate = 0; 9923 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9924 ivi->qos = adapter->vf_data[vf].pf_qos; 9925 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9926 ivi->trusted = adapter->vf_data[vf].trusted; 9927 return 0; 9928 } 9929 9930 static void igb_vmm_control(struct igb_adapter *adapter) 9931 { 9932 struct e1000_hw *hw = &adapter->hw; 9933 u32 reg; 9934 9935 switch (hw->mac.type) { 9936 case e1000_82575: 9937 case e1000_i210: 9938 case e1000_i211: 9939 case e1000_i354: 9940 default: 9941 /* replication is not supported for 82575 */ 9942 return; 9943 case e1000_82576: 9944 /* notify HW that the MAC is adding vlan tags */ 9945 reg = rd32(E1000_DTXCTL); 9946 reg |= E1000_DTXCTL_VLAN_ADDED; 9947 wr32(E1000_DTXCTL, reg); 9948 fallthrough; 9949 case e1000_82580: 9950 /* enable replication vlan tag stripping */ 9951 reg = rd32(E1000_RPLOLR); 9952 reg |= E1000_RPLOLR_STRVLAN; 9953 wr32(E1000_RPLOLR, reg); 9954 fallthrough; 9955 case e1000_i350: 9956 /* none of the above registers are supported by i350 */ 9957 break; 9958 } 9959 9960 if (adapter->vfs_allocated_count) { 9961 igb_vmdq_set_loopback_pf(hw, true); 9962 igb_vmdq_set_replication_pf(hw, true); 9963 igb_vmdq_set_anti_spoofing_pf(hw, true, 9964 adapter->vfs_allocated_count); 9965 } else { 9966 igb_vmdq_set_loopback_pf(hw, false); 9967 igb_vmdq_set_replication_pf(hw, false); 9968 } 9969 } 9970 9971 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9972 { 9973 struct e1000_hw *hw = &adapter->hw; 9974 u32 dmac_thr; 9975 u16 hwm; 9976 u32 reg; 9977 9978 if (hw->mac.type > e1000_82580) { 9979 if (adapter->flags & IGB_FLAG_DMAC) { 9980 /* force threshold to 0. */ 9981 wr32(E1000_DMCTXTH, 0); 9982 9983 /* DMA Coalescing high water mark needs to be greater 9984 * than the Rx threshold. Set hwm to PBA - max frame 9985 * size in 16B units, capping it at PBA - 6KB. 9986 */ 9987 hwm = 64 * (pba - 6); 9988 reg = rd32(E1000_FCRTC); 9989 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9990 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9991 & E1000_FCRTC_RTH_COAL_MASK); 9992 wr32(E1000_FCRTC, reg); 9993 9994 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9995 * frame size, capping it at PBA - 10KB. 9996 */ 9997 dmac_thr = pba - 10; 9998 reg = rd32(E1000_DMACR); 9999 reg &= ~E1000_DMACR_DMACTHR_MASK; 10000 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 10001 & E1000_DMACR_DMACTHR_MASK); 10002 10003 /* transition to L0x or L1 if available..*/ 10004 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10005 10006 /* watchdog timer= +-1000 usec in 32usec intervals */ 10007 reg |= (1000 >> 5); 10008 10009 /* Disable BMC-to-OS Watchdog Enable */ 10010 if (hw->mac.type != e1000_i354) 10011 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10012 wr32(E1000_DMACR, reg); 10013 10014 /* no lower threshold to disable 10015 * coalescing(smart fifb)-UTRESH=0 10016 */ 10017 wr32(E1000_DMCRTRH, 0); 10018 10019 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10020 10021 wr32(E1000_DMCTLX, reg); 10022 10023 /* free space in tx packet buffer to wake from 10024 * DMA coal 10025 */ 10026 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10027 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10028 } 10029 10030 if (hw->mac.type >= e1000_i210 || 10031 (adapter->flags & IGB_FLAG_DMAC)) { 10032 reg = rd32(E1000_PCIEMISC); 10033 reg |= E1000_PCIEMISC_LX_DECISION; 10034 wr32(E1000_PCIEMISC, reg); 10035 } /* endif adapter->dmac is not disabled */ 10036 } else if (hw->mac.type == e1000_82580) { 10037 u32 reg = rd32(E1000_PCIEMISC); 10038 10039 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10040 wr32(E1000_DMACR, 0); 10041 } 10042 } 10043 10044 /** 10045 * igb_read_i2c_byte - Reads 8 bit word over I2C 10046 * @hw: pointer to hardware structure 10047 * @byte_offset: byte offset to read 10048 * @dev_addr: device address 10049 * @data: value read 10050 * 10051 * Performs byte read operation over I2C interface at 10052 * a specified device address. 10053 **/ 10054 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10055 u8 dev_addr, u8 *data) 10056 { 10057 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10058 struct i2c_client *this_client = adapter->i2c_client; 10059 s32 status; 10060 u16 swfw_mask = 0; 10061 10062 if (!this_client) 10063 return E1000_ERR_I2C; 10064 10065 swfw_mask = E1000_SWFW_PHY0_SM; 10066 10067 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10068 return E1000_ERR_SWFW_SYNC; 10069 10070 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10071 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10072 10073 if (status < 0) 10074 return E1000_ERR_I2C; 10075 else { 10076 *data = status; 10077 return 0; 10078 } 10079 } 10080 10081 /** 10082 * igb_write_i2c_byte - Writes 8 bit word over I2C 10083 * @hw: pointer to hardware structure 10084 * @byte_offset: byte offset to write 10085 * @dev_addr: device address 10086 * @data: value to write 10087 * 10088 * Performs byte write operation over I2C interface at 10089 * a specified device address. 10090 **/ 10091 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10092 u8 dev_addr, u8 data) 10093 { 10094 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10095 struct i2c_client *this_client = adapter->i2c_client; 10096 s32 status; 10097 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10098 10099 if (!this_client) 10100 return E1000_ERR_I2C; 10101 10102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10103 return E1000_ERR_SWFW_SYNC; 10104 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10105 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10106 10107 if (status) 10108 return E1000_ERR_I2C; 10109 else 10110 return 0; 10111 10112 } 10113 10114 int igb_reinit_queues(struct igb_adapter *adapter) 10115 { 10116 struct net_device *netdev = adapter->netdev; 10117 struct pci_dev *pdev = adapter->pdev; 10118 int err = 0; 10119 10120 if (netif_running(netdev)) 10121 igb_close(netdev); 10122 10123 igb_reset_interrupt_capability(adapter); 10124 10125 if (igb_init_interrupt_scheme(adapter, true)) { 10126 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10127 return -ENOMEM; 10128 } 10129 10130 if (netif_running(netdev)) 10131 err = igb_open(netdev); 10132 10133 return err; 10134 } 10135 10136 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10137 { 10138 struct igb_nfc_filter *rule; 10139 10140 spin_lock(&adapter->nfc_lock); 10141 10142 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10143 igb_erase_filter(adapter, rule); 10144 10145 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10146 igb_erase_filter(adapter, rule); 10147 10148 spin_unlock(&adapter->nfc_lock); 10149 } 10150 10151 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10152 { 10153 struct igb_nfc_filter *rule; 10154 10155 spin_lock(&adapter->nfc_lock); 10156 10157 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10158 igb_add_filter(adapter, rule); 10159 10160 spin_unlock(&adapter->nfc_lock); 10161 } 10162 /* igb_main.c */ 10163