1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 3 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 170 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 171 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 172 int vf, u16 vlan, u8 qos); 173 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 174 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 180 #ifdef CONFIG_PCI_IOV 181 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 182 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 183 static int igb_disable_sriov(struct pci_dev *dev); 184 static int igb_pci_disable_sriov(struct pci_dev *dev); 185 #endif 186 187 #ifdef CONFIG_PM 188 #ifdef CONFIG_PM_SLEEP 189 static int igb_suspend(struct device *); 190 #endif 191 static int igb_resume(struct device *); 192 static int igb_runtime_suspend(struct device *dev); 193 static int igb_runtime_resume(struct device *dev); 194 static int igb_runtime_idle(struct device *dev); 195 static const struct dev_pm_ops igb_pm_ops = { 196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 198 igb_runtime_idle) 199 }; 200 #endif 201 static void igb_shutdown(struct pci_dev *); 202 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 203 #ifdef CONFIG_IGB_DCA 204 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 205 static struct notifier_block dca_notifier = { 206 .notifier_call = igb_notify_dca, 207 .next = NULL, 208 .priority = 0 209 }; 210 #endif 211 #ifdef CONFIG_NET_POLL_CONTROLLER 212 /* for netdump / net console */ 213 static void igb_netpoll(struct net_device *); 214 #endif 215 #ifdef CONFIG_PCI_IOV 216 static unsigned int max_vfs; 217 module_param(max_vfs, uint, 0); 218 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 219 #endif /* CONFIG_PCI_IOV */ 220 221 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 222 pci_channel_state_t); 223 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 224 static void igb_io_resume(struct pci_dev *); 225 226 static const struct pci_error_handlers igb_err_handler = { 227 .error_detected = igb_io_error_detected, 228 .slot_reset = igb_io_slot_reset, 229 .resume = igb_io_resume, 230 }; 231 232 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 233 234 static struct pci_driver igb_driver = { 235 .name = igb_driver_name, 236 .id_table = igb_pci_tbl, 237 .probe = igb_probe, 238 .remove = igb_remove, 239 #ifdef CONFIG_PM 240 .driver.pm = &igb_pm_ops, 241 #endif 242 .shutdown = igb_shutdown, 243 .sriov_configure = igb_pci_sriov_configure, 244 .err_handler = &igb_err_handler 245 }; 246 247 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 248 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 249 MODULE_LICENSE("GPL"); 250 MODULE_VERSION(DRV_VERSION); 251 252 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 253 static int debug = -1; 254 module_param(debug, int, 0); 255 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 256 257 struct igb_reg_info { 258 u32 ofs; 259 char *name; 260 }; 261 262 static const struct igb_reg_info igb_reg_info_tbl[] = { 263 264 /* General Registers */ 265 {E1000_CTRL, "CTRL"}, 266 {E1000_STATUS, "STATUS"}, 267 {E1000_CTRL_EXT, "CTRL_EXT"}, 268 269 /* Interrupt Registers */ 270 {E1000_ICR, "ICR"}, 271 272 /* RX Registers */ 273 {E1000_RCTL, "RCTL"}, 274 {E1000_RDLEN(0), "RDLEN"}, 275 {E1000_RDH(0), "RDH"}, 276 {E1000_RDT(0), "RDT"}, 277 {E1000_RXDCTL(0), "RXDCTL"}, 278 {E1000_RDBAL(0), "RDBAL"}, 279 {E1000_RDBAH(0), "RDBAH"}, 280 281 /* TX Registers */ 282 {E1000_TCTL, "TCTL"}, 283 {E1000_TDBAL(0), "TDBAL"}, 284 {E1000_TDBAH(0), "TDBAH"}, 285 {E1000_TDLEN(0), "TDLEN"}, 286 {E1000_TDH(0), "TDH"}, 287 {E1000_TDT(0), "TDT"}, 288 {E1000_TXDCTL(0), "TXDCTL"}, 289 {E1000_TDFH, "TDFH"}, 290 {E1000_TDFT, "TDFT"}, 291 {E1000_TDFHS, "TDFHS"}, 292 {E1000_TDFPC, "TDFPC"}, 293 294 /* List Terminator */ 295 {} 296 }; 297 298 /* igb_regdump - register printout routine */ 299 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 300 { 301 int n = 0; 302 char rname[16]; 303 u32 regs[8]; 304 305 switch (reginfo->ofs) { 306 case E1000_RDLEN(0): 307 for (n = 0; n < 4; n++) 308 regs[n] = rd32(E1000_RDLEN(n)); 309 break; 310 case E1000_RDH(0): 311 for (n = 0; n < 4; n++) 312 regs[n] = rd32(E1000_RDH(n)); 313 break; 314 case E1000_RDT(0): 315 for (n = 0; n < 4; n++) 316 regs[n] = rd32(E1000_RDT(n)); 317 break; 318 case E1000_RXDCTL(0): 319 for (n = 0; n < 4; n++) 320 regs[n] = rd32(E1000_RXDCTL(n)); 321 break; 322 case E1000_RDBAL(0): 323 for (n = 0; n < 4; n++) 324 regs[n] = rd32(E1000_RDBAL(n)); 325 break; 326 case E1000_RDBAH(0): 327 for (n = 0; n < 4; n++) 328 regs[n] = rd32(E1000_RDBAH(n)); 329 break; 330 case E1000_TDBAL(0): 331 for (n = 0; n < 4; n++) 332 regs[n] = rd32(E1000_RDBAL(n)); 333 break; 334 case E1000_TDBAH(0): 335 for (n = 0; n < 4; n++) 336 regs[n] = rd32(E1000_TDBAH(n)); 337 break; 338 case E1000_TDLEN(0): 339 for (n = 0; n < 4; n++) 340 regs[n] = rd32(E1000_TDLEN(n)); 341 break; 342 case E1000_TDH(0): 343 for (n = 0; n < 4; n++) 344 regs[n] = rd32(E1000_TDH(n)); 345 break; 346 case E1000_TDT(0): 347 for (n = 0; n < 4; n++) 348 regs[n] = rd32(E1000_TDT(n)); 349 break; 350 case E1000_TXDCTL(0): 351 for (n = 0; n < 4; n++) 352 regs[n] = rd32(E1000_TXDCTL(n)); 353 break; 354 default: 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 356 return; 357 } 358 359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 361 regs[2], regs[3]); 362 } 363 364 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 365 static void igb_dump(struct igb_adapter *adapter) 366 { 367 struct net_device *netdev = adapter->netdev; 368 struct e1000_hw *hw = &adapter->hw; 369 struct igb_reg_info *reginfo; 370 struct igb_ring *tx_ring; 371 union e1000_adv_tx_desc *tx_desc; 372 struct my_u0 { u64 a; u64 b; } *u0; 373 struct igb_ring *rx_ring; 374 union e1000_adv_rx_desc *rx_desc; 375 u32 staterr; 376 u16 i, n; 377 378 if (!netif_msg_hw(adapter)) 379 return; 380 381 /* Print netdevice Info */ 382 if (netdev) { 383 dev_info(&adapter->pdev->dev, "Net device Info\n"); 384 pr_info("Device Name state trans_start last_rx\n"); 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 386 netdev->state, dev_trans_start(netdev), netdev->last_rx); 387 } 388 389 /* Print Registers */ 390 dev_info(&adapter->pdev->dev, "Register Dump\n"); 391 pr_info(" Register Name Value\n"); 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 393 reginfo->name; reginfo++) { 394 igb_regdump(hw, reginfo); 395 } 396 397 /* Print TX Ring Summary */ 398 if (!netdev || !netif_running(netdev)) 399 goto exit; 400 401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 403 for (n = 0; n < adapter->num_tx_queues; n++) { 404 struct igb_tx_buffer *buffer_info; 405 tx_ring = adapter->tx_ring[n]; 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 408 n, tx_ring->next_to_use, tx_ring->next_to_clean, 409 (u64)dma_unmap_addr(buffer_info, dma), 410 dma_unmap_len(buffer_info, len), 411 buffer_info->next_to_watch, 412 (u64)buffer_info->time_stamp); 413 } 414 415 /* Print TX Rings */ 416 if (!netif_msg_tx_done(adapter)) 417 goto rx_ring_summary; 418 419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 420 421 /* Transmit Descriptor Formats 422 * 423 * Advanced Transmit Descriptor 424 * +--------------------------------------------------------------+ 425 * 0 | Buffer Address [63:0] | 426 * +--------------------------------------------------------------+ 427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 428 * +--------------------------------------------------------------+ 429 * 63 46 45 40 39 38 36 35 32 31 24 15 0 430 */ 431 432 for (n = 0; n < adapter->num_tx_queues; n++) { 433 tx_ring = adapter->tx_ring[n]; 434 pr_info("------------------------------------\n"); 435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 436 pr_info("------------------------------------\n"); 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 438 439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 440 const char *next_desc; 441 struct igb_tx_buffer *buffer_info; 442 tx_desc = IGB_TX_DESC(tx_ring, i); 443 buffer_info = &tx_ring->tx_buffer_info[i]; 444 u0 = (struct my_u0 *)tx_desc; 445 if (i == tx_ring->next_to_use && 446 i == tx_ring->next_to_clean) 447 next_desc = " NTC/U"; 448 else if (i == tx_ring->next_to_use) 449 next_desc = " NTU"; 450 else if (i == tx_ring->next_to_clean) 451 next_desc = " NTC"; 452 else 453 next_desc = ""; 454 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 456 i, le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)dma_unmap_addr(buffer_info, dma), 459 dma_unmap_len(buffer_info, len), 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 dma_unmap_len(buffer_info, len), 469 true); 470 } 471 } 472 473 /* Print RX Rings Summary */ 474 rx_ring_summary: 475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 476 pr_info("Queue [NTU] [NTC]\n"); 477 for (n = 0; n < adapter->num_rx_queues; n++) { 478 rx_ring = adapter->rx_ring[n]; 479 pr_info(" %5d %5X %5X\n", 480 n, rx_ring->next_to_use, rx_ring->next_to_clean); 481 } 482 483 /* Print RX Rings */ 484 if (!netif_msg_rx_status(adapter)) 485 goto exit; 486 487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 488 489 /* Advanced Receive Descriptor (Read) Format 490 * 63 1 0 491 * +-----------------------------------------------------+ 492 * 0 | Packet Buffer Address [63:1] |A0/NSE| 493 * +----------------------------------------------+------+ 494 * 8 | Header Buffer Address [63:1] | DD | 495 * +-----------------------------------------------------+ 496 * 497 * 498 * Advanced Receive Descriptor (Write-Back) Format 499 * 500 * 63 48 47 32 31 30 21 20 17 16 4 3 0 501 * +------------------------------------------------------+ 502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 503 * | Checksum Ident | | | | Type | Type | 504 * +------------------------------------------------------+ 505 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 506 * +------------------------------------------------------+ 507 * 63 48 47 32 31 20 19 0 508 */ 509 510 for (n = 0; n < adapter->num_rx_queues; n++) { 511 rx_ring = adapter->rx_ring[n]; 512 pr_info("------------------------------------\n"); 513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 514 pr_info("------------------------------------\n"); 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 517 518 for (i = 0; i < rx_ring->count; i++) { 519 const char *next_desc; 520 struct igb_rx_buffer *buffer_info; 521 buffer_info = &rx_ring->rx_buffer_info[i]; 522 rx_desc = IGB_RX_DESC(rx_ring, i); 523 u0 = (struct my_u0 *)rx_desc; 524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 525 526 if (i == rx_ring->next_to_use) 527 next_desc = " NTU"; 528 else if (i == rx_ring->next_to_clean) 529 next_desc = " NTC"; 530 else 531 next_desc = ""; 532 533 if (staterr & E1000_RXD_STAT_DD) { 534 /* Descriptor Done */ 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 536 "RWB", i, 537 le64_to_cpu(u0->a), 538 le64_to_cpu(u0->b), 539 next_desc); 540 } else { 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 542 "R ", i, 543 le64_to_cpu(u0->a), 544 le64_to_cpu(u0->b), 545 (u64)buffer_info->dma, 546 next_desc); 547 548 if (netif_msg_pktdata(adapter) && 549 buffer_info->dma && buffer_info->page) { 550 print_hex_dump(KERN_INFO, "", 551 DUMP_PREFIX_ADDRESS, 552 16, 1, 553 page_address(buffer_info->page) + 554 buffer_info->page_offset, 555 IGB_RX_BUFSZ, true); 556 } 557 } 558 } 559 } 560 561 exit: 562 return; 563 } 564 565 /** 566 * igb_get_i2c_data - Reads the I2C SDA data bit 567 * @hw: pointer to hardware structure 568 * @i2cctl: Current value of I2CCTL register 569 * 570 * Returns the I2C data bit value 571 **/ 572 static int igb_get_i2c_data(void *data) 573 { 574 struct igb_adapter *adapter = (struct igb_adapter *)data; 575 struct e1000_hw *hw = &adapter->hw; 576 s32 i2cctl = rd32(E1000_I2CPARAMS); 577 578 return !!(i2cctl & E1000_I2C_DATA_IN); 579 } 580 581 /** 582 * igb_set_i2c_data - Sets the I2C data bit 583 * @data: pointer to hardware structure 584 * @state: I2C data value (0 or 1) to set 585 * 586 * Sets the I2C data bit 587 **/ 588 static void igb_set_i2c_data(void *data, int state) 589 { 590 struct igb_adapter *adapter = (struct igb_adapter *)data; 591 struct e1000_hw *hw = &adapter->hw; 592 s32 i2cctl = rd32(E1000_I2CPARAMS); 593 594 if (state) 595 i2cctl |= E1000_I2C_DATA_OUT; 596 else 597 i2cctl &= ~E1000_I2C_DATA_OUT; 598 599 i2cctl &= ~E1000_I2C_DATA_OE_N; 600 i2cctl |= E1000_I2C_CLK_OE_N; 601 wr32(E1000_I2CPARAMS, i2cctl); 602 wrfl(); 603 604 } 605 606 /** 607 * igb_set_i2c_clk - Sets the I2C SCL clock 608 * @data: pointer to hardware structure 609 * @state: state to set clock 610 * 611 * Sets the I2C clock line to state 612 **/ 613 static void igb_set_i2c_clk(void *data, int state) 614 { 615 struct igb_adapter *adapter = (struct igb_adapter *)data; 616 struct e1000_hw *hw = &adapter->hw; 617 s32 i2cctl = rd32(E1000_I2CPARAMS); 618 619 if (state) { 620 i2cctl |= E1000_I2C_CLK_OUT; 621 i2cctl &= ~E1000_I2C_CLK_OE_N; 622 } else { 623 i2cctl &= ~E1000_I2C_CLK_OUT; 624 i2cctl &= ~E1000_I2C_CLK_OE_N; 625 } 626 wr32(E1000_I2CPARAMS, i2cctl); 627 wrfl(); 628 } 629 630 /** 631 * igb_get_i2c_clk - Gets the I2C SCL clock state 632 * @data: pointer to hardware structure 633 * 634 * Gets the I2C clock state 635 **/ 636 static int igb_get_i2c_clk(void *data) 637 { 638 struct igb_adapter *adapter = (struct igb_adapter *)data; 639 struct e1000_hw *hw = &adapter->hw; 640 s32 i2cctl = rd32(E1000_I2CPARAMS); 641 642 return !!(i2cctl & E1000_I2C_CLK_IN); 643 } 644 645 static const struct i2c_algo_bit_data igb_i2c_algo = { 646 .setsda = igb_set_i2c_data, 647 .setscl = igb_set_i2c_clk, 648 .getsda = igb_get_i2c_data, 649 .getscl = igb_get_i2c_clk, 650 .udelay = 5, 651 .timeout = 20, 652 }; 653 654 /** 655 * igb_get_hw_dev - return device 656 * @hw: pointer to hardware structure 657 * 658 * used by hardware layer to print debugging information 659 **/ 660 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 661 { 662 struct igb_adapter *adapter = hw->back; 663 return adapter->netdev; 664 } 665 666 /** 667 * igb_init_module - Driver Registration Routine 668 * 669 * igb_init_module is the first routine called when the driver is 670 * loaded. All it does is register with the PCI subsystem. 671 **/ 672 static int __init igb_init_module(void) 673 { 674 int ret; 675 676 pr_info("%s - version %s\n", 677 igb_driver_string, igb_driver_version); 678 pr_info("%s\n", igb_copyright); 679 680 #ifdef CONFIG_IGB_DCA 681 dca_register_notify(&dca_notifier); 682 #endif 683 ret = pci_register_driver(&igb_driver); 684 return ret; 685 } 686 687 module_init(igb_init_module); 688 689 /** 690 * igb_exit_module - Driver Exit Cleanup Routine 691 * 692 * igb_exit_module is called just before the driver is removed 693 * from memory. 694 **/ 695 static void __exit igb_exit_module(void) 696 { 697 #ifdef CONFIG_IGB_DCA 698 dca_unregister_notify(&dca_notifier); 699 #endif 700 pci_unregister_driver(&igb_driver); 701 } 702 703 module_exit(igb_exit_module); 704 705 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 706 /** 707 * igb_cache_ring_register - Descriptor ring to register mapping 708 * @adapter: board private structure to initialize 709 * 710 * Once we know the feature-set enabled for the device, we'll cache 711 * the register offset the descriptor ring is assigned to. 712 **/ 713 static void igb_cache_ring_register(struct igb_adapter *adapter) 714 { 715 int i = 0, j = 0; 716 u32 rbase_offset = adapter->vfs_allocated_count; 717 718 switch (adapter->hw.mac.type) { 719 case e1000_82576: 720 /* The queues are allocated for virtualization such that VF 0 721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 722 * In order to avoid collision we start at the first free queue 723 * and continue consuming queues in the same sequence 724 */ 725 if (adapter->vfs_allocated_count) { 726 for (; i < adapter->rss_queues; i++) 727 adapter->rx_ring[i]->reg_idx = rbase_offset + 728 Q_IDX_82576(i); 729 } 730 /* Fall through */ 731 case e1000_82575: 732 case e1000_82580: 733 case e1000_i350: 734 case e1000_i354: 735 case e1000_i210: 736 case e1000_i211: 737 /* Fall through */ 738 default: 739 for (; i < adapter->num_rx_queues; i++) 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 741 for (; j < adapter->num_tx_queues; j++) 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 743 break; 744 } 745 } 746 747 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 748 { 749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 751 u32 value = 0; 752 753 if (E1000_REMOVED(hw_addr)) 754 return ~value; 755 756 value = readl(&hw_addr[reg]); 757 758 /* reads should not return all F's */ 759 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 760 struct net_device *netdev = igb->netdev; 761 hw->hw_addr = NULL; 762 netif_device_detach(netdev); 763 netdev_err(netdev, "PCIe link lost, device now detached\n"); 764 } 765 766 return value; 767 } 768 769 /** 770 * igb_write_ivar - configure ivar for given MSI-X vector 771 * @hw: pointer to the HW structure 772 * @msix_vector: vector number we are allocating to a given ring 773 * @index: row index of IVAR register to write within IVAR table 774 * @offset: column offset of in IVAR, should be multiple of 8 775 * 776 * This function is intended to handle the writing of the IVAR register 777 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 778 * each containing an cause allocation for an Rx and Tx ring, and a 779 * variable number of rows depending on the number of queues supported. 780 **/ 781 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 782 int index, int offset) 783 { 784 u32 ivar = array_rd32(E1000_IVAR0, index); 785 786 /* clear any bits that are currently set */ 787 ivar &= ~((u32)0xFF << offset); 788 789 /* write vector and valid bit */ 790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 791 792 array_wr32(E1000_IVAR0, index, ivar); 793 } 794 795 #define IGB_N0_QUEUE -1 796 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 797 { 798 struct igb_adapter *adapter = q_vector->adapter; 799 struct e1000_hw *hw = &adapter->hw; 800 int rx_queue = IGB_N0_QUEUE; 801 int tx_queue = IGB_N0_QUEUE; 802 u32 msixbm = 0; 803 804 if (q_vector->rx.ring) 805 rx_queue = q_vector->rx.ring->reg_idx; 806 if (q_vector->tx.ring) 807 tx_queue = q_vector->tx.ring->reg_idx; 808 809 switch (hw->mac.type) { 810 case e1000_82575: 811 /* The 82575 assigns vectors using a bitmask, which matches the 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one 813 * or more queues to a vector, we write the appropriate bits 814 * into the MSIXBM register for that vector. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 818 if (tx_queue > IGB_N0_QUEUE) 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 821 msixbm |= E1000_EIMS_OTHER; 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 823 q_vector->eims_value = msixbm; 824 break; 825 case e1000_82576: 826 /* 82576 uses a table that essentially consists of 2 columns 827 * with 8 rows. The ordering is column-major so we use the 828 * lower 3 bits as the row index, and the 4th bit as the 829 * column offset. 830 */ 831 if (rx_queue > IGB_N0_QUEUE) 832 igb_write_ivar(hw, msix_vector, 833 rx_queue & 0x7, 834 (rx_queue & 0x8) << 1); 835 if (tx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 tx_queue & 0x7, 838 ((tx_queue & 0x8) << 1) + 8); 839 q_vector->eims_value = BIT(msix_vector); 840 break; 841 case e1000_82580: 842 case e1000_i350: 843 case e1000_i354: 844 case e1000_i210: 845 case e1000_i211: 846 /* On 82580 and newer adapters the scheme is similar to 82576 847 * however instead of ordering column-major we have things 848 * ordered row-major. So we traverse the table by using 849 * bit 0 as the column offset, and the remaining bits as the 850 * row index. 851 */ 852 if (rx_queue > IGB_N0_QUEUE) 853 igb_write_ivar(hw, msix_vector, 854 rx_queue >> 1, 855 (rx_queue & 0x1) << 4); 856 if (tx_queue > IGB_N0_QUEUE) 857 igb_write_ivar(hw, msix_vector, 858 tx_queue >> 1, 859 ((tx_queue & 0x1) << 4) + 8); 860 q_vector->eims_value = BIT(msix_vector); 861 break; 862 default: 863 BUG(); 864 break; 865 } 866 867 /* add q_vector eims value to global eims_enable_mask */ 868 adapter->eims_enable_mask |= q_vector->eims_value; 869 870 /* configure q_vector to set itr on first interrupt */ 871 q_vector->set_itr = 1; 872 } 873 874 /** 875 * igb_configure_msix - Configure MSI-X hardware 876 * @adapter: board private structure to initialize 877 * 878 * igb_configure_msix sets up the hardware to properly 879 * generate MSI-X interrupts. 880 **/ 881 static void igb_configure_msix(struct igb_adapter *adapter) 882 { 883 u32 tmp; 884 int i, vector = 0; 885 struct e1000_hw *hw = &adapter->hw; 886 887 adapter->eims_enable_mask = 0; 888 889 /* set vector for other causes, i.e. link changes */ 890 switch (hw->mac.type) { 891 case e1000_82575: 892 tmp = rd32(E1000_CTRL_EXT); 893 /* enable MSI-X PBA support*/ 894 tmp |= E1000_CTRL_EXT_PBA_CLR; 895 896 /* Auto-Mask interrupts upon ICR read. */ 897 tmp |= E1000_CTRL_EXT_EIAME; 898 tmp |= E1000_CTRL_EXT_IRCA; 899 900 wr32(E1000_CTRL_EXT, tmp); 901 902 /* enable msix_other interrupt */ 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 904 adapter->eims_other = E1000_EIMS_OTHER; 905 906 break; 907 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 case e1000_i210: 913 case e1000_i211: 914 /* Turn on MSI-X capability first, or our settings 915 * won't stick. And it will take days to debug. 916 */ 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 918 E1000_GPIE_PBA | E1000_GPIE_EIAME | 919 E1000_GPIE_NSICR); 920 921 /* enable msix_other interrupt */ 922 adapter->eims_other = BIT(vector); 923 tmp = (vector++ | E1000_IVAR_VALID) << 8; 924 925 wr32(E1000_IVAR_MISC, tmp); 926 break; 927 default: 928 /* do nothing, since nothing else supports MSI-X */ 929 break; 930 } /* switch (hw->mac.type) */ 931 932 adapter->eims_enable_mask |= adapter->eims_other; 933 934 for (i = 0; i < adapter->num_q_vectors; i++) 935 igb_assign_vector(adapter->q_vector[i], vector++); 936 937 wrfl(); 938 } 939 940 /** 941 * igb_request_msix - Initialize MSI-X interrupts 942 * @adapter: board private structure to initialize 943 * 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 945 * kernel. 946 **/ 947 static int igb_request_msix(struct igb_adapter *adapter) 948 { 949 struct net_device *netdev = adapter->netdev; 950 int i, err = 0, vector = 0, free_vector = 0; 951 952 err = request_irq(adapter->msix_entries[vector].vector, 953 igb_msix_other, 0, netdev->name, adapter); 954 if (err) 955 goto err_out; 956 957 for (i = 0; i < adapter->num_q_vectors; i++) { 958 struct igb_q_vector *q_vector = adapter->q_vector[i]; 959 960 vector++; 961 962 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 963 964 if (q_vector->rx.ring && q_vector->tx.ring) 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 966 q_vector->rx.ring->queue_index); 967 else if (q_vector->tx.ring) 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 969 q_vector->tx.ring->queue_index); 970 else if (q_vector->rx.ring) 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 972 q_vector->rx.ring->queue_index); 973 else 974 sprintf(q_vector->name, "%s-unused", netdev->name); 975 976 err = request_irq(adapter->msix_entries[vector].vector, 977 igb_msix_ring, 0, q_vector->name, 978 q_vector); 979 if (err) 980 goto err_free; 981 } 982 983 igb_configure_msix(adapter); 984 return 0; 985 986 err_free: 987 /* free already assigned IRQs */ 988 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 989 990 vector--; 991 for (i = 0; i < vector; i++) { 992 free_irq(adapter->msix_entries[free_vector++].vector, 993 adapter->q_vector[i]); 994 } 995 err_out: 996 return err; 997 } 998 999 /** 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1001 * @adapter: board private structure to initialize 1002 * @v_idx: Index of vector to be freed 1003 * 1004 * This function frees the memory allocated to the q_vector. 1005 **/ 1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1007 { 1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1009 1010 adapter->q_vector[v_idx] = NULL; 1011 1012 /* igb_get_stats64() might access the rings on this vector, 1013 * we must wait a grace period before freeing it. 1014 */ 1015 if (q_vector) 1016 kfree_rcu(q_vector, rcu); 1017 } 1018 1019 /** 1020 * igb_reset_q_vector - Reset config for interrupt vector 1021 * @adapter: board private structure to initialize 1022 * @v_idx: Index of vector to be reset 1023 * 1024 * If NAPI is enabled it will delete any references to the 1025 * NAPI struct. This is preparation for igb_free_q_vector. 1026 **/ 1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1028 { 1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1030 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1032 * allocated. So, q_vector is NULL so we should stop here. 1033 */ 1034 if (!q_vector) 1035 return; 1036 1037 if (q_vector->tx.ring) 1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1039 1040 if (q_vector->rx.ring) 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1042 1043 netif_napi_del(&q_vector->napi); 1044 1045 } 1046 1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1048 { 1049 int v_idx = adapter->num_q_vectors; 1050 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1052 pci_disable_msix(adapter->pdev); 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1054 pci_disable_msi(adapter->pdev); 1055 1056 while (v_idx--) 1057 igb_reset_q_vector(adapter, v_idx); 1058 } 1059 1060 /** 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1062 * @adapter: board private structure to initialize 1063 * 1064 * This function frees the memory allocated to the q_vectors. In addition if 1065 * NAPI is enabled it will delete any references to the NAPI struct prior 1066 * to freeing the q_vector. 1067 **/ 1068 static void igb_free_q_vectors(struct igb_adapter *adapter) 1069 { 1070 int v_idx = adapter->num_q_vectors; 1071 1072 adapter->num_tx_queues = 0; 1073 adapter->num_rx_queues = 0; 1074 adapter->num_q_vectors = 0; 1075 1076 while (v_idx--) { 1077 igb_reset_q_vector(adapter, v_idx); 1078 igb_free_q_vector(adapter, v_idx); 1079 } 1080 } 1081 1082 /** 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1084 * @adapter: board private structure to initialize 1085 * 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1087 * MSI-X interrupts allocated. 1088 */ 1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1090 { 1091 igb_free_q_vectors(adapter); 1092 igb_reset_interrupt_capability(adapter); 1093 } 1094 1095 /** 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1097 * @adapter: board private structure to initialize 1098 * @msix: boolean value of MSIX capability 1099 * 1100 * Attempt to configure interrupts using the best available 1101 * capabilities of the hardware and kernel. 1102 **/ 1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1104 { 1105 int err; 1106 int numvecs, i; 1107 1108 if (!msix) 1109 goto msi_only; 1110 adapter->flags |= IGB_FLAG_HAS_MSIX; 1111 1112 /* Number of supported queues. */ 1113 adapter->num_rx_queues = adapter->rss_queues; 1114 if (adapter->vfs_allocated_count) 1115 adapter->num_tx_queues = 1; 1116 else 1117 adapter->num_tx_queues = adapter->rss_queues; 1118 1119 /* start with one vector for every Rx queue */ 1120 numvecs = adapter->num_rx_queues; 1121 1122 /* if Tx handler is separate add 1 for every Tx queue */ 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1124 numvecs += adapter->num_tx_queues; 1125 1126 /* store the number of vectors reserved for queues */ 1127 adapter->num_q_vectors = numvecs; 1128 1129 /* add 1 vector for link status interrupts */ 1130 numvecs++; 1131 for (i = 0; i < numvecs; i++) 1132 adapter->msix_entries[i].entry = i; 1133 1134 err = pci_enable_msix_range(adapter->pdev, 1135 adapter->msix_entries, 1136 numvecs, 1137 numvecs); 1138 if (err > 0) 1139 return; 1140 1141 igb_reset_interrupt_capability(adapter); 1142 1143 /* If we can't do MSI-X, try MSI */ 1144 msi_only: 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1146 #ifdef CONFIG_PCI_IOV 1147 /* disable SR-IOV for non MSI-X configurations */ 1148 if (adapter->vf_data) { 1149 struct e1000_hw *hw = &adapter->hw; 1150 /* disable iov and allow time for transactions to clear */ 1151 pci_disable_sriov(adapter->pdev); 1152 msleep(500); 1153 1154 kfree(adapter->vf_data); 1155 adapter->vf_data = NULL; 1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1157 wrfl(); 1158 msleep(100); 1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1160 } 1161 #endif 1162 adapter->vfs_allocated_count = 0; 1163 adapter->rss_queues = 1; 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1165 adapter->num_rx_queues = 1; 1166 adapter->num_tx_queues = 1; 1167 adapter->num_q_vectors = 1; 1168 if (!pci_enable_msi(adapter->pdev)) 1169 adapter->flags |= IGB_FLAG_HAS_MSI; 1170 } 1171 1172 static void igb_add_ring(struct igb_ring *ring, 1173 struct igb_ring_container *head) 1174 { 1175 head->ring = ring; 1176 head->count++; 1177 } 1178 1179 /** 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1181 * @adapter: board private structure to initialize 1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1183 * @v_idx: index of vector in adapter struct 1184 * @txr_count: total number of Tx rings to allocate 1185 * @txr_idx: index of first Tx ring to allocate 1186 * @rxr_count: total number of Rx rings to allocate 1187 * @rxr_idx: index of first Rx ring to allocate 1188 * 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1190 **/ 1191 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1192 int v_count, int v_idx, 1193 int txr_count, int txr_idx, 1194 int rxr_count, int rxr_idx) 1195 { 1196 struct igb_q_vector *q_vector; 1197 struct igb_ring *ring; 1198 int ring_count, size; 1199 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1201 if (txr_count > 1 || rxr_count > 1) 1202 return -ENOMEM; 1203 1204 ring_count = txr_count + rxr_count; 1205 size = sizeof(struct igb_q_vector) + 1206 (sizeof(struct igb_ring) * ring_count); 1207 1208 /* allocate q_vector and rings */ 1209 q_vector = adapter->q_vector[v_idx]; 1210 if (!q_vector) { 1211 q_vector = kzalloc(size, GFP_KERNEL); 1212 } else if (size > ksize(q_vector)) { 1213 kfree_rcu(q_vector, rcu); 1214 q_vector = kzalloc(size, GFP_KERNEL); 1215 } else { 1216 memset(q_vector, 0, size); 1217 } 1218 if (!q_vector) 1219 return -ENOMEM; 1220 1221 /* initialize NAPI */ 1222 netif_napi_add(adapter->netdev, &q_vector->napi, 1223 igb_poll, 64); 1224 1225 /* tie q_vector and adapter together */ 1226 adapter->q_vector[v_idx] = q_vector; 1227 q_vector->adapter = adapter; 1228 1229 /* initialize work limits */ 1230 q_vector->tx.work_limit = adapter->tx_work_limit; 1231 1232 /* initialize ITR configuration */ 1233 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1234 q_vector->itr_val = IGB_START_ITR; 1235 1236 /* initialize pointer to rings */ 1237 ring = q_vector->ring; 1238 1239 /* intialize ITR */ 1240 if (rxr_count) { 1241 /* rx or rx/tx vector */ 1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1243 q_vector->itr_val = adapter->rx_itr_setting; 1244 } else { 1245 /* tx only vector */ 1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1247 q_vector->itr_val = adapter->tx_itr_setting; 1248 } 1249 1250 if (txr_count) { 1251 /* assign generic ring traits */ 1252 ring->dev = &adapter->pdev->dev; 1253 ring->netdev = adapter->netdev; 1254 1255 /* configure backlink on ring */ 1256 ring->q_vector = q_vector; 1257 1258 /* update q_vector Tx values */ 1259 igb_add_ring(ring, &q_vector->tx); 1260 1261 /* For 82575, context index must be unique per ring. */ 1262 if (adapter->hw.mac.type == e1000_82575) 1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1264 1265 /* apply Tx specific ring traits */ 1266 ring->count = adapter->tx_ring_count; 1267 ring->queue_index = txr_idx; 1268 1269 u64_stats_init(&ring->tx_syncp); 1270 u64_stats_init(&ring->tx_syncp2); 1271 1272 /* assign ring to adapter */ 1273 adapter->tx_ring[txr_idx] = ring; 1274 1275 /* push pointer to next ring */ 1276 ring++; 1277 } 1278 1279 if (rxr_count) { 1280 /* assign generic ring traits */ 1281 ring->dev = &adapter->pdev->dev; 1282 ring->netdev = adapter->netdev; 1283 1284 /* configure backlink on ring */ 1285 ring->q_vector = q_vector; 1286 1287 /* update q_vector Rx values */ 1288 igb_add_ring(ring, &q_vector->rx); 1289 1290 /* set flag indicating ring supports SCTP checksum offload */ 1291 if (adapter->hw.mac.type >= e1000_82576) 1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1293 1294 /* On i350, i354, i210, and i211, loopback VLAN packets 1295 * have the tag byte-swapped. 1296 */ 1297 if (adapter->hw.mac.type >= e1000_i350) 1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1299 1300 /* apply Rx specific ring traits */ 1301 ring->count = adapter->rx_ring_count; 1302 ring->queue_index = rxr_idx; 1303 1304 u64_stats_init(&ring->rx_syncp); 1305 1306 /* assign ring to adapter */ 1307 adapter->rx_ring[rxr_idx] = ring; 1308 } 1309 1310 return 0; 1311 } 1312 1313 1314 /** 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1316 * @adapter: board private structure to initialize 1317 * 1318 * We allocate one q_vector per queue interrupt. If allocation fails we 1319 * return -ENOMEM. 1320 **/ 1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1322 { 1323 int q_vectors = adapter->num_q_vectors; 1324 int rxr_remaining = adapter->num_rx_queues; 1325 int txr_remaining = adapter->num_tx_queues; 1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1327 int err; 1328 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1330 for (; rxr_remaining; v_idx++) { 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 0, 0, 1, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining--; 1339 rxr_idx++; 1340 } 1341 } 1342 1343 for (; v_idx < q_vectors; v_idx++) { 1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1346 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1348 tqpv, txr_idx, rqpv, rxr_idx); 1349 1350 if (err) 1351 goto err_out; 1352 1353 /* update counts and index */ 1354 rxr_remaining -= rqpv; 1355 txr_remaining -= tqpv; 1356 rxr_idx++; 1357 txr_idx++; 1358 } 1359 1360 return 0; 1361 1362 err_out: 1363 adapter->num_tx_queues = 0; 1364 adapter->num_rx_queues = 0; 1365 adapter->num_q_vectors = 0; 1366 1367 while (v_idx--) 1368 igb_free_q_vector(adapter, v_idx); 1369 1370 return -ENOMEM; 1371 } 1372 1373 /** 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1375 * @adapter: board private structure to initialize 1376 * @msix: boolean value of MSIX capability 1377 * 1378 * This function initializes the interrupts and allocates all of the queues. 1379 **/ 1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1381 { 1382 struct pci_dev *pdev = adapter->pdev; 1383 int err; 1384 1385 igb_set_interrupt_capability(adapter, msix); 1386 1387 err = igb_alloc_q_vectors(adapter); 1388 if (err) { 1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1390 goto err_alloc_q_vectors; 1391 } 1392 1393 igb_cache_ring_register(adapter); 1394 1395 return 0; 1396 1397 err_alloc_q_vectors: 1398 igb_reset_interrupt_capability(adapter); 1399 return err; 1400 } 1401 1402 /** 1403 * igb_request_irq - initialize interrupts 1404 * @adapter: board private structure to initialize 1405 * 1406 * Attempts to configure interrupts using the best available 1407 * capabilities of the hardware and kernel. 1408 **/ 1409 static int igb_request_irq(struct igb_adapter *adapter) 1410 { 1411 struct net_device *netdev = adapter->netdev; 1412 struct pci_dev *pdev = adapter->pdev; 1413 int err = 0; 1414 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1416 err = igb_request_msix(adapter); 1417 if (!err) 1418 goto request_done; 1419 /* fall back to MSI */ 1420 igb_free_all_tx_resources(adapter); 1421 igb_free_all_rx_resources(adapter); 1422 1423 igb_clear_interrupt_scheme(adapter); 1424 err = igb_init_interrupt_scheme(adapter, false); 1425 if (err) 1426 goto request_done; 1427 1428 igb_setup_all_tx_resources(adapter); 1429 igb_setup_all_rx_resources(adapter); 1430 igb_configure(adapter); 1431 } 1432 1433 igb_assign_vector(adapter->q_vector[0], 0); 1434 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1436 err = request_irq(pdev->irq, igb_intr_msi, 0, 1437 netdev->name, adapter); 1438 if (!err) 1439 goto request_done; 1440 1441 /* fall back to legacy interrupts */ 1442 igb_reset_interrupt_capability(adapter); 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1444 } 1445 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1447 netdev->name, adapter); 1448 1449 if (err) 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1451 err); 1452 1453 request_done: 1454 return err; 1455 } 1456 1457 static void igb_free_irq(struct igb_adapter *adapter) 1458 { 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1460 int vector = 0, i; 1461 1462 free_irq(adapter->msix_entries[vector++].vector, adapter); 1463 1464 for (i = 0; i < adapter->num_q_vectors; i++) 1465 free_irq(adapter->msix_entries[vector++].vector, 1466 adapter->q_vector[i]); 1467 } else { 1468 free_irq(adapter->pdev->irq, adapter); 1469 } 1470 } 1471 1472 /** 1473 * igb_irq_disable - Mask off interrupt generation on the NIC 1474 * @adapter: board private structure 1475 **/ 1476 static void igb_irq_disable(struct igb_adapter *adapter) 1477 { 1478 struct e1000_hw *hw = &adapter->hw; 1479 1480 /* we need to be careful when disabling interrupts. The VFs are also 1481 * mapped into these registers and so clearing the bits can cause 1482 * issues on the VF drivers so we only need to clear what we set 1483 */ 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 regval = rd32(E1000_EIAM); 1486 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1488 wr32(E1000_EIMC, adapter->eims_enable_mask); 1489 regval = rd32(E1000_EIAC); 1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1491 } 1492 1493 wr32(E1000_IAM, 0); 1494 wr32(E1000_IMC, ~0); 1495 wrfl(); 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1497 int i; 1498 1499 for (i = 0; i < adapter->num_q_vectors; i++) 1500 synchronize_irq(adapter->msix_entries[i].vector); 1501 } else { 1502 synchronize_irq(adapter->pdev->irq); 1503 } 1504 } 1505 1506 /** 1507 * igb_irq_enable - Enable default interrupt generation settings 1508 * @adapter: board private structure 1509 **/ 1510 static void igb_irq_enable(struct igb_adapter *adapter) 1511 { 1512 struct e1000_hw *hw = &adapter->hw; 1513 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1516 u32 regval = rd32(E1000_EIAC); 1517 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1519 regval = rd32(E1000_EIAM); 1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1521 wr32(E1000_EIMS, adapter->eims_enable_mask); 1522 if (adapter->vfs_allocated_count) { 1523 wr32(E1000_MBVFIMR, 0xFF); 1524 ims |= E1000_IMS_VMMB; 1525 } 1526 wr32(E1000_IMS, ims); 1527 } else { 1528 wr32(E1000_IMS, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 wr32(E1000_IAM, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 } 1533 } 1534 1535 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1536 { 1537 struct e1000_hw *hw = &adapter->hw; 1538 u16 pf_id = adapter->vfs_allocated_count; 1539 u16 vid = adapter->hw.mng_cookie.vlan_id; 1540 u16 old_vid = adapter->mng_vlan_id; 1541 1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1543 /* add VID to filter table */ 1544 igb_vfta_set(hw, vid, pf_id, true, true); 1545 adapter->mng_vlan_id = vid; 1546 } else { 1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1548 } 1549 1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1551 (vid != old_vid) && 1552 !test_bit(old_vid, adapter->active_vlans)) { 1553 /* remove VID from filter table */ 1554 igb_vfta_set(hw, vid, pf_id, false, true); 1555 } 1556 } 1557 1558 /** 1559 * igb_release_hw_control - release control of the h/w to f/w 1560 * @adapter: address of board private structure 1561 * 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1563 * For ASF and Pass Through versions of f/w this means that the 1564 * driver is no longer loaded. 1565 **/ 1566 static void igb_release_hw_control(struct igb_adapter *adapter) 1567 { 1568 struct e1000_hw *hw = &adapter->hw; 1569 u32 ctrl_ext; 1570 1571 /* Let firmware take over control of h/w */ 1572 ctrl_ext = rd32(E1000_CTRL_EXT); 1573 wr32(E1000_CTRL_EXT, 1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1575 } 1576 1577 /** 1578 * igb_get_hw_control - get control of the h/w from f/w 1579 * @adapter: address of board private structure 1580 * 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1582 * For ASF and Pass Through versions of f/w this means that 1583 * the driver is loaded. 1584 **/ 1585 static void igb_get_hw_control(struct igb_adapter *adapter) 1586 { 1587 struct e1000_hw *hw = &adapter->hw; 1588 u32 ctrl_ext; 1589 1590 /* Let firmware know the driver has taken over */ 1591 ctrl_ext = rd32(E1000_CTRL_EXT); 1592 wr32(E1000_CTRL_EXT, 1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1594 } 1595 1596 /** 1597 * igb_configure - configure the hardware for RX and TX 1598 * @adapter: private board structure 1599 **/ 1600 static void igb_configure(struct igb_adapter *adapter) 1601 { 1602 struct net_device *netdev = adapter->netdev; 1603 int i; 1604 1605 igb_get_hw_control(adapter); 1606 igb_set_rx_mode(netdev); 1607 1608 igb_restore_vlan(adapter); 1609 1610 igb_setup_tctl(adapter); 1611 igb_setup_mrqc(adapter); 1612 igb_setup_rctl(adapter); 1613 1614 igb_configure_tx(adapter); 1615 igb_configure_rx(adapter); 1616 1617 igb_rx_fifo_flush_82575(&adapter->hw); 1618 1619 /* call igb_desc_unused which always leaves 1620 * at least 1 descriptor unused to make sure 1621 * next_to_use != next_to_clean 1622 */ 1623 for (i = 0; i < adapter->num_rx_queues; i++) { 1624 struct igb_ring *ring = adapter->rx_ring[i]; 1625 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1626 } 1627 } 1628 1629 /** 1630 * igb_power_up_link - Power up the phy/serdes link 1631 * @adapter: address of board private structure 1632 **/ 1633 void igb_power_up_link(struct igb_adapter *adapter) 1634 { 1635 igb_reset_phy(&adapter->hw); 1636 1637 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1638 igb_power_up_phy_copper(&adapter->hw); 1639 else 1640 igb_power_up_serdes_link_82575(&adapter->hw); 1641 1642 igb_setup_link(&adapter->hw); 1643 } 1644 1645 /** 1646 * igb_power_down_link - Power down the phy/serdes link 1647 * @adapter: address of board private structure 1648 */ 1649 static void igb_power_down_link(struct igb_adapter *adapter) 1650 { 1651 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1652 igb_power_down_phy_copper_82575(&adapter->hw); 1653 else 1654 igb_shutdown_serdes_link_82575(&adapter->hw); 1655 } 1656 1657 /** 1658 * Detect and switch function for Media Auto Sense 1659 * @adapter: address of the board private structure 1660 **/ 1661 static void igb_check_swap_media(struct igb_adapter *adapter) 1662 { 1663 struct e1000_hw *hw = &adapter->hw; 1664 u32 ctrl_ext, connsw; 1665 bool swap_now = false; 1666 1667 ctrl_ext = rd32(E1000_CTRL_EXT); 1668 connsw = rd32(E1000_CONNSW); 1669 1670 /* need to live swap if current media is copper and we have fiber/serdes 1671 * to go to. 1672 */ 1673 1674 if ((hw->phy.media_type == e1000_media_type_copper) && 1675 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1676 swap_now = true; 1677 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1678 /* copper signal takes time to appear */ 1679 if (adapter->copper_tries < 4) { 1680 adapter->copper_tries++; 1681 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1682 wr32(E1000_CONNSW, connsw); 1683 return; 1684 } else { 1685 adapter->copper_tries = 0; 1686 if ((connsw & E1000_CONNSW_PHYSD) && 1687 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1688 swap_now = true; 1689 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1690 wr32(E1000_CONNSW, connsw); 1691 } 1692 } 1693 } 1694 1695 if (!swap_now) 1696 return; 1697 1698 switch (hw->phy.media_type) { 1699 case e1000_media_type_copper: 1700 netdev_info(adapter->netdev, 1701 "MAS: changing media to fiber/serdes\n"); 1702 ctrl_ext |= 1703 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1704 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1705 adapter->copper_tries = 0; 1706 break; 1707 case e1000_media_type_internal_serdes: 1708 case e1000_media_type_fiber: 1709 netdev_info(adapter->netdev, 1710 "MAS: changing media to copper\n"); 1711 ctrl_ext &= 1712 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1713 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1714 break; 1715 default: 1716 /* shouldn't get here during regular operation */ 1717 netdev_err(adapter->netdev, 1718 "AMS: Invalid media type found, returning\n"); 1719 break; 1720 } 1721 wr32(E1000_CTRL_EXT, ctrl_ext); 1722 } 1723 1724 /** 1725 * igb_up - Open the interface and prepare it to handle traffic 1726 * @adapter: board private structure 1727 **/ 1728 int igb_up(struct igb_adapter *adapter) 1729 { 1730 struct e1000_hw *hw = &adapter->hw; 1731 int i; 1732 1733 /* hardware has been reset, we need to reload some things */ 1734 igb_configure(adapter); 1735 1736 clear_bit(__IGB_DOWN, &adapter->state); 1737 1738 for (i = 0; i < adapter->num_q_vectors; i++) 1739 napi_enable(&(adapter->q_vector[i]->napi)); 1740 1741 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1742 igb_configure_msix(adapter); 1743 else 1744 igb_assign_vector(adapter->q_vector[0], 0); 1745 1746 /* Clear any pending interrupts. */ 1747 rd32(E1000_ICR); 1748 igb_irq_enable(adapter); 1749 1750 /* notify VFs that reset has been completed */ 1751 if (adapter->vfs_allocated_count) { 1752 u32 reg_data = rd32(E1000_CTRL_EXT); 1753 1754 reg_data |= E1000_CTRL_EXT_PFRSTD; 1755 wr32(E1000_CTRL_EXT, reg_data); 1756 } 1757 1758 netif_tx_start_all_queues(adapter->netdev); 1759 1760 /* start the watchdog. */ 1761 hw->mac.get_link_status = 1; 1762 schedule_work(&adapter->watchdog_task); 1763 1764 if ((adapter->flags & IGB_FLAG_EEE) && 1765 (!hw->dev_spec._82575.eee_disable)) 1766 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1767 1768 return 0; 1769 } 1770 1771 void igb_down(struct igb_adapter *adapter) 1772 { 1773 struct net_device *netdev = adapter->netdev; 1774 struct e1000_hw *hw = &adapter->hw; 1775 u32 tctl, rctl; 1776 int i; 1777 1778 /* signal that we're down so the interrupt handler does not 1779 * reschedule our watchdog timer 1780 */ 1781 set_bit(__IGB_DOWN, &adapter->state); 1782 1783 /* disable receives in the hardware */ 1784 rctl = rd32(E1000_RCTL); 1785 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1786 /* flush and sleep below */ 1787 1788 netif_carrier_off(netdev); 1789 netif_tx_stop_all_queues(netdev); 1790 1791 /* disable transmits in the hardware */ 1792 tctl = rd32(E1000_TCTL); 1793 tctl &= ~E1000_TCTL_EN; 1794 wr32(E1000_TCTL, tctl); 1795 /* flush both disables and wait for them to finish */ 1796 wrfl(); 1797 usleep_range(10000, 11000); 1798 1799 igb_irq_disable(adapter); 1800 1801 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1802 1803 for (i = 0; i < adapter->num_q_vectors; i++) { 1804 if (adapter->q_vector[i]) { 1805 napi_synchronize(&adapter->q_vector[i]->napi); 1806 napi_disable(&adapter->q_vector[i]->napi); 1807 } 1808 } 1809 1810 del_timer_sync(&adapter->watchdog_timer); 1811 del_timer_sync(&adapter->phy_info_timer); 1812 1813 /* record the stats before reset*/ 1814 spin_lock(&adapter->stats64_lock); 1815 igb_update_stats(adapter, &adapter->stats64); 1816 spin_unlock(&adapter->stats64_lock); 1817 1818 adapter->link_speed = 0; 1819 adapter->link_duplex = 0; 1820 1821 if (!pci_channel_offline(adapter->pdev)) 1822 igb_reset(adapter); 1823 1824 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1825 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1826 1827 igb_clean_all_tx_rings(adapter); 1828 igb_clean_all_rx_rings(adapter); 1829 #ifdef CONFIG_IGB_DCA 1830 1831 /* since we reset the hardware DCA settings were cleared */ 1832 igb_setup_dca(adapter); 1833 #endif 1834 } 1835 1836 void igb_reinit_locked(struct igb_adapter *adapter) 1837 { 1838 WARN_ON(in_interrupt()); 1839 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1840 usleep_range(1000, 2000); 1841 igb_down(adapter); 1842 igb_up(adapter); 1843 clear_bit(__IGB_RESETTING, &adapter->state); 1844 } 1845 1846 /** igb_enable_mas - Media Autosense re-enable after swap 1847 * 1848 * @adapter: adapter struct 1849 **/ 1850 static void igb_enable_mas(struct igb_adapter *adapter) 1851 { 1852 struct e1000_hw *hw = &adapter->hw; 1853 u32 connsw = rd32(E1000_CONNSW); 1854 1855 /* configure for SerDes media detect */ 1856 if ((hw->phy.media_type == e1000_media_type_copper) && 1857 (!(connsw & E1000_CONNSW_SERDESD))) { 1858 connsw |= E1000_CONNSW_ENRGSRC; 1859 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1860 wr32(E1000_CONNSW, connsw); 1861 wrfl(); 1862 } 1863 } 1864 1865 void igb_reset(struct igb_adapter *adapter) 1866 { 1867 struct pci_dev *pdev = adapter->pdev; 1868 struct e1000_hw *hw = &adapter->hw; 1869 struct e1000_mac_info *mac = &hw->mac; 1870 struct e1000_fc_info *fc = &hw->fc; 1871 u32 pba, hwm; 1872 1873 /* Repartition Pba for greater than 9k mtu 1874 * To take effect CTRL.RST is required. 1875 */ 1876 switch (mac->type) { 1877 case e1000_i350: 1878 case e1000_i354: 1879 case e1000_82580: 1880 pba = rd32(E1000_RXPBS); 1881 pba = igb_rxpbs_adjust_82580(pba); 1882 break; 1883 case e1000_82576: 1884 pba = rd32(E1000_RXPBS); 1885 pba &= E1000_RXPBS_SIZE_MASK_82576; 1886 break; 1887 case e1000_82575: 1888 case e1000_i210: 1889 case e1000_i211: 1890 default: 1891 pba = E1000_PBA_34K; 1892 break; 1893 } 1894 1895 if (mac->type == e1000_82575) { 1896 u32 min_rx_space, min_tx_space, needed_tx_space; 1897 1898 /* write Rx PBA so that hardware can report correct Tx PBA */ 1899 wr32(E1000_PBA, pba); 1900 1901 /* To maintain wire speed transmits, the Tx FIFO should be 1902 * large enough to accommodate two full transmit packets, 1903 * rounded up to the next 1KB and expressed in KB. Likewise, 1904 * the Rx FIFO should be large enough to accommodate at least 1905 * one full receive packet and is similarly rounded up and 1906 * expressed in KB. 1907 */ 1908 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1909 1910 /* The Tx FIFO also stores 16 bytes of information about the Tx 1911 * but don't include Ethernet FCS because hardware appends it. 1912 * We only need to round down to the nearest 512 byte block 1913 * count since the value we care about is 2 frames, not 1. 1914 */ 1915 min_tx_space = adapter->max_frame_size; 1916 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1917 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1918 1919 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1920 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1921 1922 /* If current Tx allocation is less than the min Tx FIFO size, 1923 * and the min Tx FIFO size is less than the current Rx FIFO 1924 * allocation, take space away from current Rx allocation. 1925 */ 1926 if (needed_tx_space < pba) { 1927 pba -= needed_tx_space; 1928 1929 /* if short on Rx space, Rx wins and must trump Tx 1930 * adjustment 1931 */ 1932 if (pba < min_rx_space) 1933 pba = min_rx_space; 1934 } 1935 1936 /* adjust PBA for jumbo frames */ 1937 wr32(E1000_PBA, pba); 1938 } 1939 1940 /* flow control settings 1941 * The high water mark must be low enough to fit one full frame 1942 * after transmitting the pause frame. As such we must have enough 1943 * space to allow for us to complete our current transmit and then 1944 * receive the frame that is in progress from the link partner. 1945 * Set it to: 1946 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1947 */ 1948 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1949 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1951 fc->low_water = fc->high_water - 16; 1952 fc->pause_time = 0xFFFF; 1953 fc->send_xon = 1; 1954 fc->current_mode = fc->requested_mode; 1955 1956 /* disable receive for all VFs and wait one second */ 1957 if (adapter->vfs_allocated_count) { 1958 int i; 1959 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1962 1963 /* ping all the active vfs to let them know we are going down */ 1964 igb_ping_all_vfs(adapter); 1965 1966 /* disable transmits and receives */ 1967 wr32(E1000_VFRE, 0); 1968 wr32(E1000_VFTE, 0); 1969 } 1970 1971 /* Allow time for pending master requests to run */ 1972 hw->mac.ops.reset_hw(hw); 1973 wr32(E1000_WUC, 0); 1974 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1976 /* need to resetup here after media swap */ 1977 adapter->ei.get_invariants(hw); 1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1979 } 1980 if ((mac->type == e1000_82575) && 1981 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1982 igb_enable_mas(adapter); 1983 } 1984 if (hw->mac.ops.init_hw(hw)) 1985 dev_err(&pdev->dev, "Hardware Error\n"); 1986 1987 /* Flow control settings reset on hardware reset, so guarantee flow 1988 * control is off when forcing speed. 1989 */ 1990 if (!hw->mac.autoneg) 1991 igb_force_mac_fc(hw); 1992 1993 igb_init_dmac(adapter, pba); 1994 #ifdef CONFIG_IGB_HWMON 1995 /* Re-initialize the thermal sensor on i350 devices. */ 1996 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1997 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1998 /* If present, re-initialize the external thermal sensor 1999 * interface. 2000 */ 2001 if (adapter->ets) 2002 mac->ops.init_thermal_sensor_thresh(hw); 2003 } 2004 } 2005 #endif 2006 /* Re-establish EEE setting */ 2007 if (hw->phy.media_type == e1000_media_type_copper) { 2008 switch (mac->type) { 2009 case e1000_i350: 2010 case e1000_i210: 2011 case e1000_i211: 2012 igb_set_eee_i350(hw, true, true); 2013 break; 2014 case e1000_i354: 2015 igb_set_eee_i354(hw, true, true); 2016 break; 2017 default: 2018 break; 2019 } 2020 } 2021 if (!netif_running(adapter->netdev)) 2022 igb_power_down_link(adapter); 2023 2024 igb_update_mng_vlan(adapter); 2025 2026 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2027 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2028 2029 /* Re-enable PTP, where applicable. */ 2030 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2031 igb_ptp_reset(adapter); 2032 2033 igb_get_phy_info(hw); 2034 } 2035 2036 static netdev_features_t igb_fix_features(struct net_device *netdev, 2037 netdev_features_t features) 2038 { 2039 /* Since there is no support for separate Rx/Tx vlan accel 2040 * enable/disable make sure Tx flag is always in same state as Rx. 2041 */ 2042 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2043 features |= NETIF_F_HW_VLAN_CTAG_TX; 2044 else 2045 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2046 2047 return features; 2048 } 2049 2050 static int igb_set_features(struct net_device *netdev, 2051 netdev_features_t features) 2052 { 2053 netdev_features_t changed = netdev->features ^ features; 2054 struct igb_adapter *adapter = netdev_priv(netdev); 2055 2056 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2057 igb_vlan_mode(netdev, features); 2058 2059 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2060 return 0; 2061 2062 netdev->features = features; 2063 2064 if (netif_running(netdev)) 2065 igb_reinit_locked(adapter); 2066 else 2067 igb_reset(adapter); 2068 2069 return 0; 2070 } 2071 2072 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2073 struct net_device *dev, 2074 const unsigned char *addr, u16 vid, 2075 u16 flags) 2076 { 2077 /* guarantee we can provide a unique filter for the unicast address */ 2078 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2079 struct igb_adapter *adapter = netdev_priv(dev); 2080 struct e1000_hw *hw = &adapter->hw; 2081 int vfn = adapter->vfs_allocated_count; 2082 int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 2083 2084 if (netdev_uc_count(dev) >= rar_entries) 2085 return -ENOMEM; 2086 } 2087 2088 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2089 } 2090 2091 #define IGB_MAX_MAC_HDR_LEN 127 2092 #define IGB_MAX_NETWORK_HDR_LEN 511 2093 2094 static netdev_features_t 2095 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2096 netdev_features_t features) 2097 { 2098 unsigned int network_hdr_len, mac_hdr_len; 2099 2100 /* Make certain the headers can be described by a context descriptor */ 2101 mac_hdr_len = skb_network_header(skb) - skb->data; 2102 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2103 return features & ~(NETIF_F_HW_CSUM | 2104 NETIF_F_SCTP_CRC | 2105 NETIF_F_HW_VLAN_CTAG_TX | 2106 NETIF_F_TSO | 2107 NETIF_F_TSO6); 2108 2109 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2110 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2111 return features & ~(NETIF_F_HW_CSUM | 2112 NETIF_F_SCTP_CRC | 2113 NETIF_F_TSO | 2114 NETIF_F_TSO6); 2115 2116 /* We can only support IPV4 TSO in tunnels if we can mangle the 2117 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2118 */ 2119 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2120 features &= ~NETIF_F_TSO; 2121 2122 return features; 2123 } 2124 2125 static const struct net_device_ops igb_netdev_ops = { 2126 .ndo_open = igb_open, 2127 .ndo_stop = igb_close, 2128 .ndo_start_xmit = igb_xmit_frame, 2129 .ndo_get_stats64 = igb_get_stats64, 2130 .ndo_set_rx_mode = igb_set_rx_mode, 2131 .ndo_set_mac_address = igb_set_mac, 2132 .ndo_change_mtu = igb_change_mtu, 2133 .ndo_do_ioctl = igb_ioctl, 2134 .ndo_tx_timeout = igb_tx_timeout, 2135 .ndo_validate_addr = eth_validate_addr, 2136 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2137 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2138 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2139 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2140 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2141 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2142 .ndo_get_vf_config = igb_ndo_get_vf_config, 2143 #ifdef CONFIG_NET_POLL_CONTROLLER 2144 .ndo_poll_controller = igb_netpoll, 2145 #endif 2146 .ndo_fix_features = igb_fix_features, 2147 .ndo_set_features = igb_set_features, 2148 .ndo_fdb_add = igb_ndo_fdb_add, 2149 .ndo_features_check = igb_features_check, 2150 }; 2151 2152 /** 2153 * igb_set_fw_version - Configure version string for ethtool 2154 * @adapter: adapter struct 2155 **/ 2156 void igb_set_fw_version(struct igb_adapter *adapter) 2157 { 2158 struct e1000_hw *hw = &adapter->hw; 2159 struct e1000_fw_version fw; 2160 2161 igb_get_fw_version(hw, &fw); 2162 2163 switch (hw->mac.type) { 2164 case e1000_i210: 2165 case e1000_i211: 2166 if (!(igb_get_flash_presence_i210(hw))) { 2167 snprintf(adapter->fw_version, 2168 sizeof(adapter->fw_version), 2169 "%2d.%2d-%d", 2170 fw.invm_major, fw.invm_minor, 2171 fw.invm_img_type); 2172 break; 2173 } 2174 /* fall through */ 2175 default: 2176 /* if option is rom valid, display its version too */ 2177 if (fw.or_valid) { 2178 snprintf(adapter->fw_version, 2179 sizeof(adapter->fw_version), 2180 "%d.%d, 0x%08x, %d.%d.%d", 2181 fw.eep_major, fw.eep_minor, fw.etrack_id, 2182 fw.or_major, fw.or_build, fw.or_patch); 2183 /* no option rom */ 2184 } else if (fw.etrack_id != 0X0000) { 2185 snprintf(adapter->fw_version, 2186 sizeof(adapter->fw_version), 2187 "%d.%d, 0x%08x", 2188 fw.eep_major, fw.eep_minor, fw.etrack_id); 2189 } else { 2190 snprintf(adapter->fw_version, 2191 sizeof(adapter->fw_version), 2192 "%d.%d.%d", 2193 fw.eep_major, fw.eep_minor, fw.eep_build); 2194 } 2195 break; 2196 } 2197 } 2198 2199 /** 2200 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2201 * 2202 * @adapter: adapter struct 2203 **/ 2204 static void igb_init_mas(struct igb_adapter *adapter) 2205 { 2206 struct e1000_hw *hw = &adapter->hw; 2207 u16 eeprom_data; 2208 2209 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2210 switch (hw->bus.func) { 2211 case E1000_FUNC_0: 2212 if (eeprom_data & IGB_MAS_ENABLE_0) { 2213 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2214 netdev_info(adapter->netdev, 2215 "MAS: Enabling Media Autosense for port %d\n", 2216 hw->bus.func); 2217 } 2218 break; 2219 case E1000_FUNC_1: 2220 if (eeprom_data & IGB_MAS_ENABLE_1) { 2221 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2222 netdev_info(adapter->netdev, 2223 "MAS: Enabling Media Autosense for port %d\n", 2224 hw->bus.func); 2225 } 2226 break; 2227 case E1000_FUNC_2: 2228 if (eeprom_data & IGB_MAS_ENABLE_2) { 2229 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2230 netdev_info(adapter->netdev, 2231 "MAS: Enabling Media Autosense for port %d\n", 2232 hw->bus.func); 2233 } 2234 break; 2235 case E1000_FUNC_3: 2236 if (eeprom_data & IGB_MAS_ENABLE_3) { 2237 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2238 netdev_info(adapter->netdev, 2239 "MAS: Enabling Media Autosense for port %d\n", 2240 hw->bus.func); 2241 } 2242 break; 2243 default: 2244 /* Shouldn't get here */ 2245 netdev_err(adapter->netdev, 2246 "MAS: Invalid port configuration, returning\n"); 2247 break; 2248 } 2249 } 2250 2251 /** 2252 * igb_init_i2c - Init I2C interface 2253 * @adapter: pointer to adapter structure 2254 **/ 2255 static s32 igb_init_i2c(struct igb_adapter *adapter) 2256 { 2257 s32 status = 0; 2258 2259 /* I2C interface supported on i350 devices */ 2260 if (adapter->hw.mac.type != e1000_i350) 2261 return 0; 2262 2263 /* Initialize the i2c bus which is controlled by the registers. 2264 * This bus will use the i2c_algo_bit structue that implements 2265 * the protocol through toggling of the 4 bits in the register. 2266 */ 2267 adapter->i2c_adap.owner = THIS_MODULE; 2268 adapter->i2c_algo = igb_i2c_algo; 2269 adapter->i2c_algo.data = adapter; 2270 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2271 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2272 strlcpy(adapter->i2c_adap.name, "igb BB", 2273 sizeof(adapter->i2c_adap.name)); 2274 status = i2c_bit_add_bus(&adapter->i2c_adap); 2275 return status; 2276 } 2277 2278 /** 2279 * igb_probe - Device Initialization Routine 2280 * @pdev: PCI device information struct 2281 * @ent: entry in igb_pci_tbl 2282 * 2283 * Returns 0 on success, negative on failure 2284 * 2285 * igb_probe initializes an adapter identified by a pci_dev structure. 2286 * The OS initialization, configuring of the adapter private structure, 2287 * and a hardware reset occur. 2288 **/ 2289 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2290 { 2291 struct net_device *netdev; 2292 struct igb_adapter *adapter; 2293 struct e1000_hw *hw; 2294 u16 eeprom_data = 0; 2295 s32 ret_val; 2296 static int global_quad_port_a; /* global quad port a indication */ 2297 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2298 int err, pci_using_dac; 2299 u8 part_str[E1000_PBANUM_LENGTH]; 2300 2301 /* Catch broken hardware that put the wrong VF device ID in 2302 * the PCIe SR-IOV capability. 2303 */ 2304 if (pdev->is_virtfn) { 2305 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2306 pci_name(pdev), pdev->vendor, pdev->device); 2307 return -EINVAL; 2308 } 2309 2310 err = pci_enable_device_mem(pdev); 2311 if (err) 2312 return err; 2313 2314 pci_using_dac = 0; 2315 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2316 if (!err) { 2317 pci_using_dac = 1; 2318 } else { 2319 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2320 if (err) { 2321 dev_err(&pdev->dev, 2322 "No usable DMA configuration, aborting\n"); 2323 goto err_dma; 2324 } 2325 } 2326 2327 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2328 IORESOURCE_MEM), 2329 igb_driver_name); 2330 if (err) 2331 goto err_pci_reg; 2332 2333 pci_enable_pcie_error_reporting(pdev); 2334 2335 pci_set_master(pdev); 2336 pci_save_state(pdev); 2337 2338 err = -ENOMEM; 2339 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2340 IGB_MAX_TX_QUEUES); 2341 if (!netdev) 2342 goto err_alloc_etherdev; 2343 2344 SET_NETDEV_DEV(netdev, &pdev->dev); 2345 2346 pci_set_drvdata(pdev, netdev); 2347 adapter = netdev_priv(netdev); 2348 adapter->netdev = netdev; 2349 adapter->pdev = pdev; 2350 hw = &adapter->hw; 2351 hw->back = adapter; 2352 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2353 2354 err = -EIO; 2355 adapter->io_addr = pci_iomap(pdev, 0, 0); 2356 if (!adapter->io_addr) 2357 goto err_ioremap; 2358 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2359 hw->hw_addr = adapter->io_addr; 2360 2361 netdev->netdev_ops = &igb_netdev_ops; 2362 igb_set_ethtool_ops(netdev); 2363 netdev->watchdog_timeo = 5 * HZ; 2364 2365 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2366 2367 netdev->mem_start = pci_resource_start(pdev, 0); 2368 netdev->mem_end = pci_resource_end(pdev, 0); 2369 2370 /* PCI config space info */ 2371 hw->vendor_id = pdev->vendor; 2372 hw->device_id = pdev->device; 2373 hw->revision_id = pdev->revision; 2374 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2375 hw->subsystem_device_id = pdev->subsystem_device; 2376 2377 /* Copy the default MAC, PHY and NVM function pointers */ 2378 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2379 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2380 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2381 /* Initialize skew-specific constants */ 2382 err = ei->get_invariants(hw); 2383 if (err) 2384 goto err_sw_init; 2385 2386 /* setup the private structure */ 2387 err = igb_sw_init(adapter); 2388 if (err) 2389 goto err_sw_init; 2390 2391 igb_get_bus_info_pcie(hw); 2392 2393 hw->phy.autoneg_wait_to_complete = false; 2394 2395 /* Copper options */ 2396 if (hw->phy.media_type == e1000_media_type_copper) { 2397 hw->phy.mdix = AUTO_ALL_MODES; 2398 hw->phy.disable_polarity_correction = false; 2399 hw->phy.ms_type = e1000_ms_hw_default; 2400 } 2401 2402 if (igb_check_reset_block(hw)) 2403 dev_info(&pdev->dev, 2404 "PHY reset is blocked due to SOL/IDER session.\n"); 2405 2406 /* features is initialized to 0 in allocation, it might have bits 2407 * set by igb_sw_init so we should use an or instead of an 2408 * assignment. 2409 */ 2410 netdev->features |= NETIF_F_SG | 2411 NETIF_F_TSO | 2412 NETIF_F_TSO6 | 2413 NETIF_F_RXHASH | 2414 NETIF_F_RXCSUM | 2415 NETIF_F_HW_CSUM; 2416 2417 if (hw->mac.type >= e1000_82576) 2418 netdev->features |= NETIF_F_SCTP_CRC; 2419 2420 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2421 NETIF_F_GSO_GRE_CSUM | \ 2422 NETIF_F_GSO_IPXIP4 | \ 2423 NETIF_F_GSO_IPXIP6 | \ 2424 NETIF_F_GSO_UDP_TUNNEL | \ 2425 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2426 2427 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2428 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2429 2430 /* copy netdev features into list of user selectable features */ 2431 netdev->hw_features |= netdev->features | 2432 NETIF_F_HW_VLAN_CTAG_RX | 2433 NETIF_F_HW_VLAN_CTAG_TX | 2434 NETIF_F_RXALL; 2435 2436 if (hw->mac.type >= e1000_i350) 2437 netdev->hw_features |= NETIF_F_NTUPLE; 2438 2439 if (pci_using_dac) 2440 netdev->features |= NETIF_F_HIGHDMA; 2441 2442 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2443 netdev->mpls_features |= NETIF_F_HW_CSUM; 2444 netdev->hw_enc_features |= netdev->vlan_features; 2445 2446 /* set this bit last since it cannot be part of vlan_features */ 2447 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2448 NETIF_F_HW_VLAN_CTAG_RX | 2449 NETIF_F_HW_VLAN_CTAG_TX; 2450 2451 netdev->priv_flags |= IFF_SUPP_NOFCS; 2452 2453 netdev->priv_flags |= IFF_UNICAST_FLT; 2454 2455 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2456 2457 /* before reading the NVM, reset the controller to put the device in a 2458 * known good starting state 2459 */ 2460 hw->mac.ops.reset_hw(hw); 2461 2462 /* make sure the NVM is good , i211/i210 parts can have special NVM 2463 * that doesn't contain a checksum 2464 */ 2465 switch (hw->mac.type) { 2466 case e1000_i210: 2467 case e1000_i211: 2468 if (igb_get_flash_presence_i210(hw)) { 2469 if (hw->nvm.ops.validate(hw) < 0) { 2470 dev_err(&pdev->dev, 2471 "The NVM Checksum Is Not Valid\n"); 2472 err = -EIO; 2473 goto err_eeprom; 2474 } 2475 } 2476 break; 2477 default: 2478 if (hw->nvm.ops.validate(hw) < 0) { 2479 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2480 err = -EIO; 2481 goto err_eeprom; 2482 } 2483 break; 2484 } 2485 2486 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2487 /* copy the MAC address out of the NVM */ 2488 if (hw->mac.ops.read_mac_addr(hw)) 2489 dev_err(&pdev->dev, "NVM Read Error\n"); 2490 } 2491 2492 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2493 2494 if (!is_valid_ether_addr(netdev->dev_addr)) { 2495 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2496 err = -EIO; 2497 goto err_eeprom; 2498 } 2499 2500 /* get firmware version for ethtool -i */ 2501 igb_set_fw_version(adapter); 2502 2503 /* configure RXPBSIZE and TXPBSIZE */ 2504 if (hw->mac.type == e1000_i210) { 2505 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2506 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2507 } 2508 2509 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2510 (unsigned long) adapter); 2511 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2512 (unsigned long) adapter); 2513 2514 INIT_WORK(&adapter->reset_task, igb_reset_task); 2515 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2516 2517 /* Initialize link properties that are user-changeable */ 2518 adapter->fc_autoneg = true; 2519 hw->mac.autoneg = true; 2520 hw->phy.autoneg_advertised = 0x2f; 2521 2522 hw->fc.requested_mode = e1000_fc_default; 2523 hw->fc.current_mode = e1000_fc_default; 2524 2525 igb_validate_mdi_setting(hw); 2526 2527 /* By default, support wake on port A */ 2528 if (hw->bus.func == 0) 2529 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2530 2531 /* Check the NVM for wake support on non-port A ports */ 2532 if (hw->mac.type >= e1000_82580) 2533 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2534 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2535 &eeprom_data); 2536 else if (hw->bus.func == 1) 2537 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2538 2539 if (eeprom_data & IGB_EEPROM_APME) 2540 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2541 2542 /* now that we have the eeprom settings, apply the special cases where 2543 * the eeprom may be wrong or the board simply won't support wake on 2544 * lan on a particular port 2545 */ 2546 switch (pdev->device) { 2547 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2548 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2549 break; 2550 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2551 case E1000_DEV_ID_82576_FIBER: 2552 case E1000_DEV_ID_82576_SERDES: 2553 /* Wake events only supported on port A for dual fiber 2554 * regardless of eeprom setting 2555 */ 2556 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2557 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2558 break; 2559 case E1000_DEV_ID_82576_QUAD_COPPER: 2560 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2561 /* if quad port adapter, disable WoL on all but port A */ 2562 if (global_quad_port_a != 0) 2563 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2564 else 2565 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2566 /* Reset for multiple quad port adapters */ 2567 if (++global_quad_port_a == 4) 2568 global_quad_port_a = 0; 2569 break; 2570 default: 2571 /* If the device can't wake, don't set software support */ 2572 if (!device_can_wakeup(&adapter->pdev->dev)) 2573 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2574 } 2575 2576 /* initialize the wol settings based on the eeprom settings */ 2577 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2578 adapter->wol |= E1000_WUFC_MAG; 2579 2580 /* Some vendors want WoL disabled by default, but still supported */ 2581 if ((hw->mac.type == e1000_i350) && 2582 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2583 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2584 adapter->wol = 0; 2585 } 2586 2587 /* Some vendors want the ability to Use the EEPROM setting as 2588 * enable/disable only, and not for capability 2589 */ 2590 if (((hw->mac.type == e1000_i350) || 2591 (hw->mac.type == e1000_i354)) && 2592 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2593 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2594 adapter->wol = 0; 2595 } 2596 if (hw->mac.type == e1000_i350) { 2597 if (((pdev->subsystem_device == 0x5001) || 2598 (pdev->subsystem_device == 0x5002)) && 2599 (hw->bus.func == 0)) { 2600 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2601 adapter->wol = 0; 2602 } 2603 if (pdev->subsystem_device == 0x1F52) 2604 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2605 } 2606 2607 device_set_wakeup_enable(&adapter->pdev->dev, 2608 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2609 2610 /* reset the hardware with the new settings */ 2611 igb_reset(adapter); 2612 2613 /* Init the I2C interface */ 2614 err = igb_init_i2c(adapter); 2615 if (err) { 2616 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2617 goto err_eeprom; 2618 } 2619 2620 /* let the f/w know that the h/w is now under the control of the 2621 * driver. 2622 */ 2623 igb_get_hw_control(adapter); 2624 2625 strcpy(netdev->name, "eth%d"); 2626 err = register_netdev(netdev); 2627 if (err) 2628 goto err_register; 2629 2630 /* carrier off reporting is important to ethtool even BEFORE open */ 2631 netif_carrier_off(netdev); 2632 2633 #ifdef CONFIG_IGB_DCA 2634 if (dca_add_requester(&pdev->dev) == 0) { 2635 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2636 dev_info(&pdev->dev, "DCA enabled\n"); 2637 igb_setup_dca(adapter); 2638 } 2639 2640 #endif 2641 #ifdef CONFIG_IGB_HWMON 2642 /* Initialize the thermal sensor on i350 devices. */ 2643 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2644 u16 ets_word; 2645 2646 /* Read the NVM to determine if this i350 device supports an 2647 * external thermal sensor. 2648 */ 2649 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2650 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2651 adapter->ets = true; 2652 else 2653 adapter->ets = false; 2654 if (igb_sysfs_init(adapter)) 2655 dev_err(&pdev->dev, 2656 "failed to allocate sysfs resources\n"); 2657 } else { 2658 adapter->ets = false; 2659 } 2660 #endif 2661 /* Check if Media Autosense is enabled */ 2662 adapter->ei = *ei; 2663 if (hw->dev_spec._82575.mas_capable) 2664 igb_init_mas(adapter); 2665 2666 /* do hw tstamp init after resetting */ 2667 igb_ptp_init(adapter); 2668 2669 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2670 /* print bus type/speed/width info, not applicable to i354 */ 2671 if (hw->mac.type != e1000_i354) { 2672 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2673 netdev->name, 2674 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2675 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2676 "unknown"), 2677 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2678 "Width x4" : 2679 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2680 "Width x2" : 2681 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2682 "Width x1" : "unknown"), netdev->dev_addr); 2683 } 2684 2685 if ((hw->mac.type >= e1000_i210 || 2686 igb_get_flash_presence_i210(hw))) { 2687 ret_val = igb_read_part_string(hw, part_str, 2688 E1000_PBANUM_LENGTH); 2689 } else { 2690 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2691 } 2692 2693 if (ret_val) 2694 strcpy(part_str, "Unknown"); 2695 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2696 dev_info(&pdev->dev, 2697 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2698 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2699 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2700 adapter->num_rx_queues, adapter->num_tx_queues); 2701 if (hw->phy.media_type == e1000_media_type_copper) { 2702 switch (hw->mac.type) { 2703 case e1000_i350: 2704 case e1000_i210: 2705 case e1000_i211: 2706 /* Enable EEE for internal copper PHY devices */ 2707 err = igb_set_eee_i350(hw, true, true); 2708 if ((!err) && 2709 (!hw->dev_spec._82575.eee_disable)) { 2710 adapter->eee_advert = 2711 MDIO_EEE_100TX | MDIO_EEE_1000T; 2712 adapter->flags |= IGB_FLAG_EEE; 2713 } 2714 break; 2715 case e1000_i354: 2716 if ((rd32(E1000_CTRL_EXT) & 2717 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2718 err = igb_set_eee_i354(hw, true, true); 2719 if ((!err) && 2720 (!hw->dev_spec._82575.eee_disable)) { 2721 adapter->eee_advert = 2722 MDIO_EEE_100TX | MDIO_EEE_1000T; 2723 adapter->flags |= IGB_FLAG_EEE; 2724 } 2725 } 2726 break; 2727 default: 2728 break; 2729 } 2730 } 2731 pm_runtime_put_noidle(&pdev->dev); 2732 return 0; 2733 2734 err_register: 2735 igb_release_hw_control(adapter); 2736 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2737 err_eeprom: 2738 if (!igb_check_reset_block(hw)) 2739 igb_reset_phy(hw); 2740 2741 if (hw->flash_address) 2742 iounmap(hw->flash_address); 2743 err_sw_init: 2744 kfree(adapter->shadow_vfta); 2745 igb_clear_interrupt_scheme(adapter); 2746 #ifdef CONFIG_PCI_IOV 2747 igb_disable_sriov(pdev); 2748 #endif 2749 pci_iounmap(pdev, adapter->io_addr); 2750 err_ioremap: 2751 free_netdev(netdev); 2752 err_alloc_etherdev: 2753 pci_release_selected_regions(pdev, 2754 pci_select_bars(pdev, IORESOURCE_MEM)); 2755 err_pci_reg: 2756 err_dma: 2757 pci_disable_device(pdev); 2758 return err; 2759 } 2760 2761 #ifdef CONFIG_PCI_IOV 2762 static int igb_disable_sriov(struct pci_dev *pdev) 2763 { 2764 struct net_device *netdev = pci_get_drvdata(pdev); 2765 struct igb_adapter *adapter = netdev_priv(netdev); 2766 struct e1000_hw *hw = &adapter->hw; 2767 2768 /* reclaim resources allocated to VFs */ 2769 if (adapter->vf_data) { 2770 /* disable iov and allow time for transactions to clear */ 2771 if (pci_vfs_assigned(pdev)) { 2772 dev_warn(&pdev->dev, 2773 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2774 return -EPERM; 2775 } else { 2776 pci_disable_sriov(pdev); 2777 msleep(500); 2778 } 2779 2780 kfree(adapter->vf_data); 2781 adapter->vf_data = NULL; 2782 adapter->vfs_allocated_count = 0; 2783 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2784 wrfl(); 2785 msleep(100); 2786 dev_info(&pdev->dev, "IOV Disabled\n"); 2787 2788 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2789 adapter->flags |= IGB_FLAG_DMAC; 2790 } 2791 2792 return 0; 2793 } 2794 2795 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2796 { 2797 struct net_device *netdev = pci_get_drvdata(pdev); 2798 struct igb_adapter *adapter = netdev_priv(netdev); 2799 int old_vfs = pci_num_vf(pdev); 2800 int err = 0; 2801 int i; 2802 2803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2804 err = -EPERM; 2805 goto out; 2806 } 2807 if (!num_vfs) 2808 goto out; 2809 2810 if (old_vfs) { 2811 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2812 old_vfs, max_vfs); 2813 adapter->vfs_allocated_count = old_vfs; 2814 } else 2815 adapter->vfs_allocated_count = num_vfs; 2816 2817 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2818 sizeof(struct vf_data_storage), GFP_KERNEL); 2819 2820 /* if allocation failed then we do not support SR-IOV */ 2821 if (!adapter->vf_data) { 2822 adapter->vfs_allocated_count = 0; 2823 dev_err(&pdev->dev, 2824 "Unable to allocate memory for VF Data Storage\n"); 2825 err = -ENOMEM; 2826 goto out; 2827 } 2828 2829 /* only call pci_enable_sriov() if no VFs are allocated already */ 2830 if (!old_vfs) { 2831 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2832 if (err) 2833 goto err_out; 2834 } 2835 dev_info(&pdev->dev, "%d VFs allocated\n", 2836 adapter->vfs_allocated_count); 2837 for (i = 0; i < adapter->vfs_allocated_count; i++) 2838 igb_vf_configure(adapter, i); 2839 2840 /* DMA Coalescing is not supported in IOV mode. */ 2841 adapter->flags &= ~IGB_FLAG_DMAC; 2842 goto out; 2843 2844 err_out: 2845 kfree(adapter->vf_data); 2846 adapter->vf_data = NULL; 2847 adapter->vfs_allocated_count = 0; 2848 out: 2849 return err; 2850 } 2851 2852 #endif 2853 /** 2854 * igb_remove_i2c - Cleanup I2C interface 2855 * @adapter: pointer to adapter structure 2856 **/ 2857 static void igb_remove_i2c(struct igb_adapter *adapter) 2858 { 2859 /* free the adapter bus structure */ 2860 i2c_del_adapter(&adapter->i2c_adap); 2861 } 2862 2863 /** 2864 * igb_remove - Device Removal Routine 2865 * @pdev: PCI device information struct 2866 * 2867 * igb_remove is called by the PCI subsystem to alert the driver 2868 * that it should release a PCI device. The could be caused by a 2869 * Hot-Plug event, or because the driver is going to be removed from 2870 * memory. 2871 **/ 2872 static void igb_remove(struct pci_dev *pdev) 2873 { 2874 struct net_device *netdev = pci_get_drvdata(pdev); 2875 struct igb_adapter *adapter = netdev_priv(netdev); 2876 struct e1000_hw *hw = &adapter->hw; 2877 2878 pm_runtime_get_noresume(&pdev->dev); 2879 #ifdef CONFIG_IGB_HWMON 2880 igb_sysfs_exit(adapter); 2881 #endif 2882 igb_remove_i2c(adapter); 2883 igb_ptp_stop(adapter); 2884 /* The watchdog timer may be rescheduled, so explicitly 2885 * disable watchdog from being rescheduled. 2886 */ 2887 set_bit(__IGB_DOWN, &adapter->state); 2888 del_timer_sync(&adapter->watchdog_timer); 2889 del_timer_sync(&adapter->phy_info_timer); 2890 2891 cancel_work_sync(&adapter->reset_task); 2892 cancel_work_sync(&adapter->watchdog_task); 2893 2894 #ifdef CONFIG_IGB_DCA 2895 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2896 dev_info(&pdev->dev, "DCA disabled\n"); 2897 dca_remove_requester(&pdev->dev); 2898 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2899 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2900 } 2901 #endif 2902 2903 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2904 * would have already happened in close and is redundant. 2905 */ 2906 igb_release_hw_control(adapter); 2907 2908 #ifdef CONFIG_PCI_IOV 2909 igb_disable_sriov(pdev); 2910 #endif 2911 2912 unregister_netdev(netdev); 2913 2914 igb_clear_interrupt_scheme(adapter); 2915 2916 pci_iounmap(pdev, adapter->io_addr); 2917 if (hw->flash_address) 2918 iounmap(hw->flash_address); 2919 pci_release_selected_regions(pdev, 2920 pci_select_bars(pdev, IORESOURCE_MEM)); 2921 2922 kfree(adapter->shadow_vfta); 2923 free_netdev(netdev); 2924 2925 pci_disable_pcie_error_reporting(pdev); 2926 2927 pci_disable_device(pdev); 2928 } 2929 2930 /** 2931 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2932 * @adapter: board private structure to initialize 2933 * 2934 * This function initializes the vf specific data storage and then attempts to 2935 * allocate the VFs. The reason for ordering it this way is because it is much 2936 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2937 * the memory for the VFs. 2938 **/ 2939 static void igb_probe_vfs(struct igb_adapter *adapter) 2940 { 2941 #ifdef CONFIG_PCI_IOV 2942 struct pci_dev *pdev = adapter->pdev; 2943 struct e1000_hw *hw = &adapter->hw; 2944 2945 /* Virtualization features not supported on i210 family. */ 2946 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2947 return; 2948 2949 /* Of the below we really only want the effect of getting 2950 * IGB_FLAG_HAS_MSIX set (if available), without which 2951 * igb_enable_sriov() has no effect. 2952 */ 2953 igb_set_interrupt_capability(adapter, true); 2954 igb_reset_interrupt_capability(adapter); 2955 2956 pci_sriov_set_totalvfs(pdev, 7); 2957 igb_enable_sriov(pdev, max_vfs); 2958 2959 #endif /* CONFIG_PCI_IOV */ 2960 } 2961 2962 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2963 { 2964 struct e1000_hw *hw = &adapter->hw; 2965 u32 max_rss_queues; 2966 2967 /* Determine the maximum number of RSS queues supported. */ 2968 switch (hw->mac.type) { 2969 case e1000_i211: 2970 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2971 break; 2972 case e1000_82575: 2973 case e1000_i210: 2974 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2975 break; 2976 case e1000_i350: 2977 /* I350 cannot do RSS and SR-IOV at the same time */ 2978 if (!!adapter->vfs_allocated_count) { 2979 max_rss_queues = 1; 2980 break; 2981 } 2982 /* fall through */ 2983 case e1000_82576: 2984 if (!!adapter->vfs_allocated_count) { 2985 max_rss_queues = 2; 2986 break; 2987 } 2988 /* fall through */ 2989 case e1000_82580: 2990 case e1000_i354: 2991 default: 2992 max_rss_queues = IGB_MAX_RX_QUEUES; 2993 break; 2994 } 2995 2996 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2997 2998 igb_set_flag_queue_pairs(adapter, max_rss_queues); 2999 } 3000 3001 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3002 const u32 max_rss_queues) 3003 { 3004 struct e1000_hw *hw = &adapter->hw; 3005 3006 /* Determine if we need to pair queues. */ 3007 switch (hw->mac.type) { 3008 case e1000_82575: 3009 case e1000_i211: 3010 /* Device supports enough interrupts without queue pairing. */ 3011 break; 3012 case e1000_82576: 3013 case e1000_82580: 3014 case e1000_i350: 3015 case e1000_i354: 3016 case e1000_i210: 3017 default: 3018 /* If rss_queues > half of max_rss_queues, pair the queues in 3019 * order to conserve interrupts due to limited supply. 3020 */ 3021 if (adapter->rss_queues > (max_rss_queues / 2)) 3022 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3023 else 3024 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3025 break; 3026 } 3027 } 3028 3029 /** 3030 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3031 * @adapter: board private structure to initialize 3032 * 3033 * igb_sw_init initializes the Adapter private data structure. 3034 * Fields are initialized based on PCI device information and 3035 * OS network device settings (MTU size). 3036 **/ 3037 static int igb_sw_init(struct igb_adapter *adapter) 3038 { 3039 struct e1000_hw *hw = &adapter->hw; 3040 struct net_device *netdev = adapter->netdev; 3041 struct pci_dev *pdev = adapter->pdev; 3042 3043 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3044 3045 /* set default ring sizes */ 3046 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3047 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3048 3049 /* set default ITR values */ 3050 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3051 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3052 3053 /* set default work limits */ 3054 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3055 3056 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3057 VLAN_HLEN; 3058 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3059 3060 spin_lock_init(&adapter->stats64_lock); 3061 #ifdef CONFIG_PCI_IOV 3062 switch (hw->mac.type) { 3063 case e1000_82576: 3064 case e1000_i350: 3065 if (max_vfs > 7) { 3066 dev_warn(&pdev->dev, 3067 "Maximum of 7 VFs per PF, using max\n"); 3068 max_vfs = adapter->vfs_allocated_count = 7; 3069 } else 3070 adapter->vfs_allocated_count = max_vfs; 3071 if (adapter->vfs_allocated_count) 3072 dev_warn(&pdev->dev, 3073 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3074 break; 3075 default: 3076 break; 3077 } 3078 #endif /* CONFIG_PCI_IOV */ 3079 3080 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3081 adapter->flags |= IGB_FLAG_HAS_MSIX; 3082 3083 igb_probe_vfs(adapter); 3084 3085 igb_init_queue_configuration(adapter); 3086 3087 /* Setup and initialize a copy of the hw vlan table array */ 3088 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3089 GFP_ATOMIC); 3090 3091 /* This call may decrease the number of queues */ 3092 if (igb_init_interrupt_scheme(adapter, true)) { 3093 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3094 return -ENOMEM; 3095 } 3096 3097 /* Explicitly disable IRQ since the NIC can be in any state. */ 3098 igb_irq_disable(adapter); 3099 3100 if (hw->mac.type >= e1000_i350) 3101 adapter->flags &= ~IGB_FLAG_DMAC; 3102 3103 set_bit(__IGB_DOWN, &adapter->state); 3104 return 0; 3105 } 3106 3107 /** 3108 * igb_open - Called when a network interface is made active 3109 * @netdev: network interface device structure 3110 * 3111 * Returns 0 on success, negative value on failure 3112 * 3113 * The open entry point is called when a network interface is made 3114 * active by the system (IFF_UP). At this point all resources needed 3115 * for transmit and receive operations are allocated, the interrupt 3116 * handler is registered with the OS, the watchdog timer is started, 3117 * and the stack is notified that the interface is ready. 3118 **/ 3119 static int __igb_open(struct net_device *netdev, bool resuming) 3120 { 3121 struct igb_adapter *adapter = netdev_priv(netdev); 3122 struct e1000_hw *hw = &adapter->hw; 3123 struct pci_dev *pdev = adapter->pdev; 3124 int err; 3125 int i; 3126 3127 /* disallow open during test */ 3128 if (test_bit(__IGB_TESTING, &adapter->state)) { 3129 WARN_ON(resuming); 3130 return -EBUSY; 3131 } 3132 3133 if (!resuming) 3134 pm_runtime_get_sync(&pdev->dev); 3135 3136 netif_carrier_off(netdev); 3137 3138 /* allocate transmit descriptors */ 3139 err = igb_setup_all_tx_resources(adapter); 3140 if (err) 3141 goto err_setup_tx; 3142 3143 /* allocate receive descriptors */ 3144 err = igb_setup_all_rx_resources(adapter); 3145 if (err) 3146 goto err_setup_rx; 3147 3148 igb_power_up_link(adapter); 3149 3150 /* before we allocate an interrupt, we must be ready to handle it. 3151 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3152 * as soon as we call pci_request_irq, so we have to setup our 3153 * clean_rx handler before we do so. 3154 */ 3155 igb_configure(adapter); 3156 3157 err = igb_request_irq(adapter); 3158 if (err) 3159 goto err_req_irq; 3160 3161 /* Notify the stack of the actual queue counts. */ 3162 err = netif_set_real_num_tx_queues(adapter->netdev, 3163 adapter->num_tx_queues); 3164 if (err) 3165 goto err_set_queues; 3166 3167 err = netif_set_real_num_rx_queues(adapter->netdev, 3168 adapter->num_rx_queues); 3169 if (err) 3170 goto err_set_queues; 3171 3172 /* From here on the code is the same as igb_up() */ 3173 clear_bit(__IGB_DOWN, &adapter->state); 3174 3175 for (i = 0; i < adapter->num_q_vectors; i++) 3176 napi_enable(&(adapter->q_vector[i]->napi)); 3177 3178 /* Clear any pending interrupts. */ 3179 rd32(E1000_ICR); 3180 3181 igb_irq_enable(adapter); 3182 3183 /* notify VFs that reset has been completed */ 3184 if (adapter->vfs_allocated_count) { 3185 u32 reg_data = rd32(E1000_CTRL_EXT); 3186 3187 reg_data |= E1000_CTRL_EXT_PFRSTD; 3188 wr32(E1000_CTRL_EXT, reg_data); 3189 } 3190 3191 netif_tx_start_all_queues(netdev); 3192 3193 if (!resuming) 3194 pm_runtime_put(&pdev->dev); 3195 3196 /* start the watchdog. */ 3197 hw->mac.get_link_status = 1; 3198 schedule_work(&adapter->watchdog_task); 3199 3200 return 0; 3201 3202 err_set_queues: 3203 igb_free_irq(adapter); 3204 err_req_irq: 3205 igb_release_hw_control(adapter); 3206 igb_power_down_link(adapter); 3207 igb_free_all_rx_resources(adapter); 3208 err_setup_rx: 3209 igb_free_all_tx_resources(adapter); 3210 err_setup_tx: 3211 igb_reset(adapter); 3212 if (!resuming) 3213 pm_runtime_put(&pdev->dev); 3214 3215 return err; 3216 } 3217 3218 int igb_open(struct net_device *netdev) 3219 { 3220 return __igb_open(netdev, false); 3221 } 3222 3223 /** 3224 * igb_close - Disables a network interface 3225 * @netdev: network interface device structure 3226 * 3227 * Returns 0, this is not allowed to fail 3228 * 3229 * The close entry point is called when an interface is de-activated 3230 * by the OS. The hardware is still under the driver's control, but 3231 * needs to be disabled. A global MAC reset is issued to stop the 3232 * hardware, and all transmit and receive resources are freed. 3233 **/ 3234 static int __igb_close(struct net_device *netdev, bool suspending) 3235 { 3236 struct igb_adapter *adapter = netdev_priv(netdev); 3237 struct pci_dev *pdev = adapter->pdev; 3238 3239 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3240 3241 if (!suspending) 3242 pm_runtime_get_sync(&pdev->dev); 3243 3244 igb_down(adapter); 3245 igb_free_irq(adapter); 3246 3247 igb_free_all_tx_resources(adapter); 3248 igb_free_all_rx_resources(adapter); 3249 3250 if (!suspending) 3251 pm_runtime_put_sync(&pdev->dev); 3252 return 0; 3253 } 3254 3255 int igb_close(struct net_device *netdev) 3256 { 3257 return __igb_close(netdev, false); 3258 } 3259 3260 /** 3261 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3262 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3263 * 3264 * Return 0 on success, negative on failure 3265 **/ 3266 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3267 { 3268 struct device *dev = tx_ring->dev; 3269 int size; 3270 3271 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3272 3273 tx_ring->tx_buffer_info = vzalloc(size); 3274 if (!tx_ring->tx_buffer_info) 3275 goto err; 3276 3277 /* round up to nearest 4K */ 3278 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3279 tx_ring->size = ALIGN(tx_ring->size, 4096); 3280 3281 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3282 &tx_ring->dma, GFP_KERNEL); 3283 if (!tx_ring->desc) 3284 goto err; 3285 3286 tx_ring->next_to_use = 0; 3287 tx_ring->next_to_clean = 0; 3288 3289 return 0; 3290 3291 err: 3292 vfree(tx_ring->tx_buffer_info); 3293 tx_ring->tx_buffer_info = NULL; 3294 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3295 return -ENOMEM; 3296 } 3297 3298 /** 3299 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3300 * (Descriptors) for all queues 3301 * @adapter: board private structure 3302 * 3303 * Return 0 on success, negative on failure 3304 **/ 3305 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3306 { 3307 struct pci_dev *pdev = adapter->pdev; 3308 int i, err = 0; 3309 3310 for (i = 0; i < adapter->num_tx_queues; i++) { 3311 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3312 if (err) { 3313 dev_err(&pdev->dev, 3314 "Allocation for Tx Queue %u failed\n", i); 3315 for (i--; i >= 0; i--) 3316 igb_free_tx_resources(adapter->tx_ring[i]); 3317 break; 3318 } 3319 } 3320 3321 return err; 3322 } 3323 3324 /** 3325 * igb_setup_tctl - configure the transmit control registers 3326 * @adapter: Board private structure 3327 **/ 3328 void igb_setup_tctl(struct igb_adapter *adapter) 3329 { 3330 struct e1000_hw *hw = &adapter->hw; 3331 u32 tctl; 3332 3333 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3334 wr32(E1000_TXDCTL(0), 0); 3335 3336 /* Program the Transmit Control Register */ 3337 tctl = rd32(E1000_TCTL); 3338 tctl &= ~E1000_TCTL_CT; 3339 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3340 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3341 3342 igb_config_collision_dist(hw); 3343 3344 /* Enable transmits */ 3345 tctl |= E1000_TCTL_EN; 3346 3347 wr32(E1000_TCTL, tctl); 3348 } 3349 3350 /** 3351 * igb_configure_tx_ring - Configure transmit ring after Reset 3352 * @adapter: board private structure 3353 * @ring: tx ring to configure 3354 * 3355 * Configure a transmit ring after a reset. 3356 **/ 3357 void igb_configure_tx_ring(struct igb_adapter *adapter, 3358 struct igb_ring *ring) 3359 { 3360 struct e1000_hw *hw = &adapter->hw; 3361 u32 txdctl = 0; 3362 u64 tdba = ring->dma; 3363 int reg_idx = ring->reg_idx; 3364 3365 /* disable the queue */ 3366 wr32(E1000_TXDCTL(reg_idx), 0); 3367 wrfl(); 3368 mdelay(10); 3369 3370 wr32(E1000_TDLEN(reg_idx), 3371 ring->count * sizeof(union e1000_adv_tx_desc)); 3372 wr32(E1000_TDBAL(reg_idx), 3373 tdba & 0x00000000ffffffffULL); 3374 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3375 3376 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3377 wr32(E1000_TDH(reg_idx), 0); 3378 writel(0, ring->tail); 3379 3380 txdctl |= IGB_TX_PTHRESH; 3381 txdctl |= IGB_TX_HTHRESH << 8; 3382 txdctl |= IGB_TX_WTHRESH << 16; 3383 3384 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3385 wr32(E1000_TXDCTL(reg_idx), txdctl); 3386 } 3387 3388 /** 3389 * igb_configure_tx - Configure transmit Unit after Reset 3390 * @adapter: board private structure 3391 * 3392 * Configure the Tx unit of the MAC after a reset. 3393 **/ 3394 static void igb_configure_tx(struct igb_adapter *adapter) 3395 { 3396 int i; 3397 3398 for (i = 0; i < adapter->num_tx_queues; i++) 3399 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3400 } 3401 3402 /** 3403 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3404 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3405 * 3406 * Returns 0 on success, negative on failure 3407 **/ 3408 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3409 { 3410 struct device *dev = rx_ring->dev; 3411 int size; 3412 3413 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3414 3415 rx_ring->rx_buffer_info = vzalloc(size); 3416 if (!rx_ring->rx_buffer_info) 3417 goto err; 3418 3419 /* Round up to nearest 4K */ 3420 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3421 rx_ring->size = ALIGN(rx_ring->size, 4096); 3422 3423 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3424 &rx_ring->dma, GFP_KERNEL); 3425 if (!rx_ring->desc) 3426 goto err; 3427 3428 rx_ring->next_to_alloc = 0; 3429 rx_ring->next_to_clean = 0; 3430 rx_ring->next_to_use = 0; 3431 3432 return 0; 3433 3434 err: 3435 vfree(rx_ring->rx_buffer_info); 3436 rx_ring->rx_buffer_info = NULL; 3437 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3438 return -ENOMEM; 3439 } 3440 3441 /** 3442 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3443 * (Descriptors) for all queues 3444 * @adapter: board private structure 3445 * 3446 * Return 0 on success, negative on failure 3447 **/ 3448 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3449 { 3450 struct pci_dev *pdev = adapter->pdev; 3451 int i, err = 0; 3452 3453 for (i = 0; i < adapter->num_rx_queues; i++) { 3454 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3455 if (err) { 3456 dev_err(&pdev->dev, 3457 "Allocation for Rx Queue %u failed\n", i); 3458 for (i--; i >= 0; i--) 3459 igb_free_rx_resources(adapter->rx_ring[i]); 3460 break; 3461 } 3462 } 3463 3464 return err; 3465 } 3466 3467 /** 3468 * igb_setup_mrqc - configure the multiple receive queue control registers 3469 * @adapter: Board private structure 3470 **/ 3471 static void igb_setup_mrqc(struct igb_adapter *adapter) 3472 { 3473 struct e1000_hw *hw = &adapter->hw; 3474 u32 mrqc, rxcsum; 3475 u32 j, num_rx_queues; 3476 u32 rss_key[10]; 3477 3478 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3479 for (j = 0; j < 10; j++) 3480 wr32(E1000_RSSRK(j), rss_key[j]); 3481 3482 num_rx_queues = adapter->rss_queues; 3483 3484 switch (hw->mac.type) { 3485 case e1000_82576: 3486 /* 82576 supports 2 RSS queues for SR-IOV */ 3487 if (adapter->vfs_allocated_count) 3488 num_rx_queues = 2; 3489 break; 3490 default: 3491 break; 3492 } 3493 3494 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3495 for (j = 0; j < IGB_RETA_SIZE; j++) 3496 adapter->rss_indir_tbl[j] = 3497 (j * num_rx_queues) / IGB_RETA_SIZE; 3498 adapter->rss_indir_tbl_init = num_rx_queues; 3499 } 3500 igb_write_rss_indir_tbl(adapter); 3501 3502 /* Disable raw packet checksumming so that RSS hash is placed in 3503 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3504 * offloads as they are enabled by default 3505 */ 3506 rxcsum = rd32(E1000_RXCSUM); 3507 rxcsum |= E1000_RXCSUM_PCSD; 3508 3509 if (adapter->hw.mac.type >= e1000_82576) 3510 /* Enable Receive Checksum Offload for SCTP */ 3511 rxcsum |= E1000_RXCSUM_CRCOFL; 3512 3513 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3514 wr32(E1000_RXCSUM, rxcsum); 3515 3516 /* Generate RSS hash based on packet types, TCP/UDP 3517 * port numbers and/or IPv4/v6 src and dst addresses 3518 */ 3519 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3520 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3521 E1000_MRQC_RSS_FIELD_IPV6 | 3522 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3523 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3524 3525 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3526 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3527 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3528 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3529 3530 /* If VMDq is enabled then we set the appropriate mode for that, else 3531 * we default to RSS so that an RSS hash is calculated per packet even 3532 * if we are only using one queue 3533 */ 3534 if (adapter->vfs_allocated_count) { 3535 if (hw->mac.type > e1000_82575) { 3536 /* Set the default pool for the PF's first queue */ 3537 u32 vtctl = rd32(E1000_VT_CTL); 3538 3539 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3540 E1000_VT_CTL_DISABLE_DEF_POOL); 3541 vtctl |= adapter->vfs_allocated_count << 3542 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3543 wr32(E1000_VT_CTL, vtctl); 3544 } 3545 if (adapter->rss_queues > 1) 3546 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3547 else 3548 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3549 } else { 3550 if (hw->mac.type != e1000_i211) 3551 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3552 } 3553 igb_vmm_control(adapter); 3554 3555 wr32(E1000_MRQC, mrqc); 3556 } 3557 3558 /** 3559 * igb_setup_rctl - configure the receive control registers 3560 * @adapter: Board private structure 3561 **/ 3562 void igb_setup_rctl(struct igb_adapter *adapter) 3563 { 3564 struct e1000_hw *hw = &adapter->hw; 3565 u32 rctl; 3566 3567 rctl = rd32(E1000_RCTL); 3568 3569 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3570 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3571 3572 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3573 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3574 3575 /* enable stripping of CRC. It's unlikely this will break BMC 3576 * redirection as it did with e1000. Newer features require 3577 * that the HW strips the CRC. 3578 */ 3579 rctl |= E1000_RCTL_SECRC; 3580 3581 /* disable store bad packets and clear size bits. */ 3582 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3583 3584 /* enable LPE to allow for reception of jumbo frames */ 3585 rctl |= E1000_RCTL_LPE; 3586 3587 /* disable queue 0 to prevent tail write w/o re-config */ 3588 wr32(E1000_RXDCTL(0), 0); 3589 3590 /* Attention!!! For SR-IOV PF driver operations you must enable 3591 * queue drop for all VF and PF queues to prevent head of line blocking 3592 * if an un-trusted VF does not provide descriptors to hardware. 3593 */ 3594 if (adapter->vfs_allocated_count) { 3595 /* set all queue drop enable bits */ 3596 wr32(E1000_QDE, ALL_QUEUES); 3597 } 3598 3599 /* This is useful for sniffing bad packets. */ 3600 if (adapter->netdev->features & NETIF_F_RXALL) { 3601 /* UPE and MPE will be handled by normal PROMISC logic 3602 * in e1000e_set_rx_mode 3603 */ 3604 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3605 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3606 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3607 3608 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3609 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3610 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3611 * and that breaks VLANs. 3612 */ 3613 } 3614 3615 wr32(E1000_RCTL, rctl); 3616 } 3617 3618 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3619 int vfn) 3620 { 3621 struct e1000_hw *hw = &adapter->hw; 3622 u32 vmolr; 3623 3624 if (size > MAX_JUMBO_FRAME_SIZE) 3625 size = MAX_JUMBO_FRAME_SIZE; 3626 3627 vmolr = rd32(E1000_VMOLR(vfn)); 3628 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3629 vmolr |= size | E1000_VMOLR_LPE; 3630 wr32(E1000_VMOLR(vfn), vmolr); 3631 3632 return 0; 3633 } 3634 3635 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3636 int vfn, bool enable) 3637 { 3638 struct e1000_hw *hw = &adapter->hw; 3639 u32 val, reg; 3640 3641 if (hw->mac.type < e1000_82576) 3642 return; 3643 3644 if (hw->mac.type == e1000_i350) 3645 reg = E1000_DVMOLR(vfn); 3646 else 3647 reg = E1000_VMOLR(vfn); 3648 3649 val = rd32(reg); 3650 if (enable) 3651 val |= E1000_VMOLR_STRVLAN; 3652 else 3653 val &= ~(E1000_VMOLR_STRVLAN); 3654 wr32(reg, val); 3655 } 3656 3657 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3658 int vfn, bool aupe) 3659 { 3660 struct e1000_hw *hw = &adapter->hw; 3661 u32 vmolr; 3662 3663 /* This register exists only on 82576 and newer so if we are older then 3664 * we should exit and do nothing 3665 */ 3666 if (hw->mac.type < e1000_82576) 3667 return; 3668 3669 vmolr = rd32(E1000_VMOLR(vfn)); 3670 if (aupe) 3671 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3672 else 3673 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3674 3675 /* clear all bits that might not be set */ 3676 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3677 3678 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3679 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3680 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3681 * multicast packets 3682 */ 3683 if (vfn <= adapter->vfs_allocated_count) 3684 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3685 3686 wr32(E1000_VMOLR(vfn), vmolr); 3687 } 3688 3689 /** 3690 * igb_configure_rx_ring - Configure a receive ring after Reset 3691 * @adapter: board private structure 3692 * @ring: receive ring to be configured 3693 * 3694 * Configure the Rx unit of the MAC after a reset. 3695 **/ 3696 void igb_configure_rx_ring(struct igb_adapter *adapter, 3697 struct igb_ring *ring) 3698 { 3699 struct e1000_hw *hw = &adapter->hw; 3700 u64 rdba = ring->dma; 3701 int reg_idx = ring->reg_idx; 3702 u32 srrctl = 0, rxdctl = 0; 3703 3704 /* disable the queue */ 3705 wr32(E1000_RXDCTL(reg_idx), 0); 3706 3707 /* Set DMA base address registers */ 3708 wr32(E1000_RDBAL(reg_idx), 3709 rdba & 0x00000000ffffffffULL); 3710 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3711 wr32(E1000_RDLEN(reg_idx), 3712 ring->count * sizeof(union e1000_adv_rx_desc)); 3713 3714 /* initialize head and tail */ 3715 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3716 wr32(E1000_RDH(reg_idx), 0); 3717 writel(0, ring->tail); 3718 3719 /* set descriptor configuration */ 3720 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3721 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3722 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3723 if (hw->mac.type >= e1000_82580) 3724 srrctl |= E1000_SRRCTL_TIMESTAMP; 3725 /* Only set Drop Enable if we are supporting multiple queues */ 3726 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3727 srrctl |= E1000_SRRCTL_DROP_EN; 3728 3729 wr32(E1000_SRRCTL(reg_idx), srrctl); 3730 3731 /* set filtering for VMDQ pools */ 3732 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3733 3734 rxdctl |= IGB_RX_PTHRESH; 3735 rxdctl |= IGB_RX_HTHRESH << 8; 3736 rxdctl |= IGB_RX_WTHRESH << 16; 3737 3738 /* enable receive descriptor fetching */ 3739 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3740 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3741 } 3742 3743 /** 3744 * igb_configure_rx - Configure receive Unit after Reset 3745 * @adapter: board private structure 3746 * 3747 * Configure the Rx unit of the MAC after a reset. 3748 **/ 3749 static void igb_configure_rx(struct igb_adapter *adapter) 3750 { 3751 int i; 3752 3753 /* set the correct pool for the PF default MAC address in entry 0 */ 3754 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3755 adapter->vfs_allocated_count); 3756 3757 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3758 * the Base and Length of the Rx Descriptor Ring 3759 */ 3760 for (i = 0; i < adapter->num_rx_queues; i++) 3761 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3762 } 3763 3764 /** 3765 * igb_free_tx_resources - Free Tx Resources per Queue 3766 * @tx_ring: Tx descriptor ring for a specific queue 3767 * 3768 * Free all transmit software resources 3769 **/ 3770 void igb_free_tx_resources(struct igb_ring *tx_ring) 3771 { 3772 igb_clean_tx_ring(tx_ring); 3773 3774 vfree(tx_ring->tx_buffer_info); 3775 tx_ring->tx_buffer_info = NULL; 3776 3777 /* if not set, then don't free */ 3778 if (!tx_ring->desc) 3779 return; 3780 3781 dma_free_coherent(tx_ring->dev, tx_ring->size, 3782 tx_ring->desc, tx_ring->dma); 3783 3784 tx_ring->desc = NULL; 3785 } 3786 3787 /** 3788 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3789 * @adapter: board private structure 3790 * 3791 * Free all transmit software resources 3792 **/ 3793 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3794 { 3795 int i; 3796 3797 for (i = 0; i < adapter->num_tx_queues; i++) 3798 if (adapter->tx_ring[i]) 3799 igb_free_tx_resources(adapter->tx_ring[i]); 3800 } 3801 3802 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3803 struct igb_tx_buffer *tx_buffer) 3804 { 3805 if (tx_buffer->skb) { 3806 dev_kfree_skb_any(tx_buffer->skb); 3807 if (dma_unmap_len(tx_buffer, len)) 3808 dma_unmap_single(ring->dev, 3809 dma_unmap_addr(tx_buffer, dma), 3810 dma_unmap_len(tx_buffer, len), 3811 DMA_TO_DEVICE); 3812 } else if (dma_unmap_len(tx_buffer, len)) { 3813 dma_unmap_page(ring->dev, 3814 dma_unmap_addr(tx_buffer, dma), 3815 dma_unmap_len(tx_buffer, len), 3816 DMA_TO_DEVICE); 3817 } 3818 tx_buffer->next_to_watch = NULL; 3819 tx_buffer->skb = NULL; 3820 dma_unmap_len_set(tx_buffer, len, 0); 3821 /* buffer_info must be completely set up in the transmit path */ 3822 } 3823 3824 /** 3825 * igb_clean_tx_ring - Free Tx Buffers 3826 * @tx_ring: ring to be cleaned 3827 **/ 3828 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3829 { 3830 struct igb_tx_buffer *buffer_info; 3831 unsigned long size; 3832 u16 i; 3833 3834 if (!tx_ring->tx_buffer_info) 3835 return; 3836 /* Free all the Tx ring sk_buffs */ 3837 3838 for (i = 0; i < tx_ring->count; i++) { 3839 buffer_info = &tx_ring->tx_buffer_info[i]; 3840 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3841 } 3842 3843 netdev_tx_reset_queue(txring_txq(tx_ring)); 3844 3845 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3846 memset(tx_ring->tx_buffer_info, 0, size); 3847 3848 /* Zero out the descriptor ring */ 3849 memset(tx_ring->desc, 0, tx_ring->size); 3850 3851 tx_ring->next_to_use = 0; 3852 tx_ring->next_to_clean = 0; 3853 } 3854 3855 /** 3856 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3857 * @adapter: board private structure 3858 **/ 3859 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3860 { 3861 int i; 3862 3863 for (i = 0; i < adapter->num_tx_queues; i++) 3864 if (adapter->tx_ring[i]) 3865 igb_clean_tx_ring(adapter->tx_ring[i]); 3866 } 3867 3868 /** 3869 * igb_free_rx_resources - Free Rx Resources 3870 * @rx_ring: ring to clean the resources from 3871 * 3872 * Free all receive software resources 3873 **/ 3874 void igb_free_rx_resources(struct igb_ring *rx_ring) 3875 { 3876 igb_clean_rx_ring(rx_ring); 3877 3878 vfree(rx_ring->rx_buffer_info); 3879 rx_ring->rx_buffer_info = NULL; 3880 3881 /* if not set, then don't free */ 3882 if (!rx_ring->desc) 3883 return; 3884 3885 dma_free_coherent(rx_ring->dev, rx_ring->size, 3886 rx_ring->desc, rx_ring->dma); 3887 3888 rx_ring->desc = NULL; 3889 } 3890 3891 /** 3892 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3893 * @adapter: board private structure 3894 * 3895 * Free all receive software resources 3896 **/ 3897 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3898 { 3899 int i; 3900 3901 for (i = 0; i < adapter->num_rx_queues; i++) 3902 if (adapter->rx_ring[i]) 3903 igb_free_rx_resources(adapter->rx_ring[i]); 3904 } 3905 3906 /** 3907 * igb_clean_rx_ring - Free Rx Buffers per Queue 3908 * @rx_ring: ring to free buffers from 3909 **/ 3910 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3911 { 3912 unsigned long size; 3913 u16 i; 3914 3915 if (rx_ring->skb) 3916 dev_kfree_skb(rx_ring->skb); 3917 rx_ring->skb = NULL; 3918 3919 if (!rx_ring->rx_buffer_info) 3920 return; 3921 3922 /* Free all the Rx ring sk_buffs */ 3923 for (i = 0; i < rx_ring->count; i++) { 3924 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3925 3926 if (!buffer_info->page) 3927 continue; 3928 3929 dma_unmap_page(rx_ring->dev, 3930 buffer_info->dma, 3931 PAGE_SIZE, 3932 DMA_FROM_DEVICE); 3933 __free_page(buffer_info->page); 3934 3935 buffer_info->page = NULL; 3936 } 3937 3938 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3939 memset(rx_ring->rx_buffer_info, 0, size); 3940 3941 /* Zero out the descriptor ring */ 3942 memset(rx_ring->desc, 0, rx_ring->size); 3943 3944 rx_ring->next_to_alloc = 0; 3945 rx_ring->next_to_clean = 0; 3946 rx_ring->next_to_use = 0; 3947 } 3948 3949 /** 3950 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3951 * @adapter: board private structure 3952 **/ 3953 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3954 { 3955 int i; 3956 3957 for (i = 0; i < adapter->num_rx_queues; i++) 3958 if (adapter->rx_ring[i]) 3959 igb_clean_rx_ring(adapter->rx_ring[i]); 3960 } 3961 3962 /** 3963 * igb_set_mac - Change the Ethernet Address of the NIC 3964 * @netdev: network interface device structure 3965 * @p: pointer to an address structure 3966 * 3967 * Returns 0 on success, negative on failure 3968 **/ 3969 static int igb_set_mac(struct net_device *netdev, void *p) 3970 { 3971 struct igb_adapter *adapter = netdev_priv(netdev); 3972 struct e1000_hw *hw = &adapter->hw; 3973 struct sockaddr *addr = p; 3974 3975 if (!is_valid_ether_addr(addr->sa_data)) 3976 return -EADDRNOTAVAIL; 3977 3978 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3979 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3980 3981 /* set the correct pool for the new PF MAC address in entry 0 */ 3982 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3983 adapter->vfs_allocated_count); 3984 3985 return 0; 3986 } 3987 3988 /** 3989 * igb_write_mc_addr_list - write multicast addresses to MTA 3990 * @netdev: network interface device structure 3991 * 3992 * Writes multicast address list to the MTA hash table. 3993 * Returns: -ENOMEM on failure 3994 * 0 on no addresses written 3995 * X on writing X addresses to MTA 3996 **/ 3997 static int igb_write_mc_addr_list(struct net_device *netdev) 3998 { 3999 struct igb_adapter *adapter = netdev_priv(netdev); 4000 struct e1000_hw *hw = &adapter->hw; 4001 struct netdev_hw_addr *ha; 4002 u8 *mta_list; 4003 int i; 4004 4005 if (netdev_mc_empty(netdev)) { 4006 /* nothing to program, so clear mc list */ 4007 igb_update_mc_addr_list(hw, NULL, 0); 4008 igb_restore_vf_multicasts(adapter); 4009 return 0; 4010 } 4011 4012 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4013 if (!mta_list) 4014 return -ENOMEM; 4015 4016 /* The shared function expects a packed array of only addresses. */ 4017 i = 0; 4018 netdev_for_each_mc_addr(ha, netdev) 4019 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4020 4021 igb_update_mc_addr_list(hw, mta_list, i); 4022 kfree(mta_list); 4023 4024 return netdev_mc_count(netdev); 4025 } 4026 4027 /** 4028 * igb_write_uc_addr_list - write unicast addresses to RAR table 4029 * @netdev: network interface device structure 4030 * 4031 * Writes unicast address list to the RAR table. 4032 * Returns: -ENOMEM on failure/insufficient address space 4033 * 0 on no addresses written 4034 * X on writing X addresses to the RAR table 4035 **/ 4036 static int igb_write_uc_addr_list(struct net_device *netdev) 4037 { 4038 struct igb_adapter *adapter = netdev_priv(netdev); 4039 struct e1000_hw *hw = &adapter->hw; 4040 unsigned int vfn = adapter->vfs_allocated_count; 4041 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 4042 int count = 0; 4043 4044 /* return ENOMEM indicating insufficient memory for addresses */ 4045 if (netdev_uc_count(netdev) > rar_entries) 4046 return -ENOMEM; 4047 4048 if (!netdev_uc_empty(netdev) && rar_entries) { 4049 struct netdev_hw_addr *ha; 4050 4051 netdev_for_each_uc_addr(ha, netdev) { 4052 if (!rar_entries) 4053 break; 4054 igb_rar_set_qsel(adapter, ha->addr, 4055 rar_entries--, 4056 vfn); 4057 count++; 4058 } 4059 } 4060 /* write the addresses in reverse order to avoid write combining */ 4061 for (; rar_entries > 0 ; rar_entries--) { 4062 wr32(E1000_RAH(rar_entries), 0); 4063 wr32(E1000_RAL(rar_entries), 0); 4064 } 4065 wrfl(); 4066 4067 return count; 4068 } 4069 4070 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4071 { 4072 struct e1000_hw *hw = &adapter->hw; 4073 u32 i, pf_id; 4074 4075 switch (hw->mac.type) { 4076 case e1000_i210: 4077 case e1000_i211: 4078 case e1000_i350: 4079 /* VLAN filtering needed for VLAN prio filter */ 4080 if (adapter->netdev->features & NETIF_F_NTUPLE) 4081 break; 4082 /* fall through */ 4083 case e1000_82576: 4084 case e1000_82580: 4085 case e1000_i354: 4086 /* VLAN filtering needed for pool filtering */ 4087 if (adapter->vfs_allocated_count) 4088 break; 4089 /* fall through */ 4090 default: 4091 return 1; 4092 } 4093 4094 /* We are already in VLAN promisc, nothing to do */ 4095 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4096 return 0; 4097 4098 if (!adapter->vfs_allocated_count) 4099 goto set_vfta; 4100 4101 /* Add PF to all active pools */ 4102 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4103 4104 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4105 u32 vlvf = rd32(E1000_VLVF(i)); 4106 4107 vlvf |= BIT(pf_id); 4108 wr32(E1000_VLVF(i), vlvf); 4109 } 4110 4111 set_vfta: 4112 /* Set all bits in the VLAN filter table array */ 4113 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4114 hw->mac.ops.write_vfta(hw, i, ~0U); 4115 4116 /* Set flag so we don't redo unnecessary work */ 4117 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4118 4119 return 0; 4120 } 4121 4122 #define VFTA_BLOCK_SIZE 8 4123 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4124 { 4125 struct e1000_hw *hw = &adapter->hw; 4126 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4127 u32 vid_start = vfta_offset * 32; 4128 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4129 u32 i, vid, word, bits, pf_id; 4130 4131 /* guarantee that we don't scrub out management VLAN */ 4132 vid = adapter->mng_vlan_id; 4133 if (vid >= vid_start && vid < vid_end) 4134 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4135 4136 if (!adapter->vfs_allocated_count) 4137 goto set_vfta; 4138 4139 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4140 4141 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4142 u32 vlvf = rd32(E1000_VLVF(i)); 4143 4144 /* pull VLAN ID from VLVF */ 4145 vid = vlvf & VLAN_VID_MASK; 4146 4147 /* only concern ourselves with a certain range */ 4148 if (vid < vid_start || vid >= vid_end) 4149 continue; 4150 4151 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4152 /* record VLAN ID in VFTA */ 4153 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4154 4155 /* if PF is part of this then continue */ 4156 if (test_bit(vid, adapter->active_vlans)) 4157 continue; 4158 } 4159 4160 /* remove PF from the pool */ 4161 bits = ~BIT(pf_id); 4162 bits &= rd32(E1000_VLVF(i)); 4163 wr32(E1000_VLVF(i), bits); 4164 } 4165 4166 set_vfta: 4167 /* extract values from active_vlans and write back to VFTA */ 4168 for (i = VFTA_BLOCK_SIZE; i--;) { 4169 vid = (vfta_offset + i) * 32; 4170 word = vid / BITS_PER_LONG; 4171 bits = vid % BITS_PER_LONG; 4172 4173 vfta[i] |= adapter->active_vlans[word] >> bits; 4174 4175 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4176 } 4177 } 4178 4179 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4180 { 4181 u32 i; 4182 4183 /* We are not in VLAN promisc, nothing to do */ 4184 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4185 return; 4186 4187 /* Set flag so we don't redo unnecessary work */ 4188 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4189 4190 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4191 igb_scrub_vfta(adapter, i); 4192 } 4193 4194 /** 4195 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4196 * @netdev: network interface device structure 4197 * 4198 * The set_rx_mode entry point is called whenever the unicast or multicast 4199 * address lists or the network interface flags are updated. This routine is 4200 * responsible for configuring the hardware for proper unicast, multicast, 4201 * promiscuous mode, and all-multi behavior. 4202 **/ 4203 static void igb_set_rx_mode(struct net_device *netdev) 4204 { 4205 struct igb_adapter *adapter = netdev_priv(netdev); 4206 struct e1000_hw *hw = &adapter->hw; 4207 unsigned int vfn = adapter->vfs_allocated_count; 4208 u32 rctl = 0, vmolr = 0; 4209 int count; 4210 4211 /* Check for Promiscuous and All Multicast modes */ 4212 if (netdev->flags & IFF_PROMISC) { 4213 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4214 vmolr |= E1000_VMOLR_MPME; 4215 4216 /* enable use of UTA filter to force packets to default pool */ 4217 if (hw->mac.type == e1000_82576) 4218 vmolr |= E1000_VMOLR_ROPE; 4219 } else { 4220 if (netdev->flags & IFF_ALLMULTI) { 4221 rctl |= E1000_RCTL_MPE; 4222 vmolr |= E1000_VMOLR_MPME; 4223 } else { 4224 /* Write addresses to the MTA, if the attempt fails 4225 * then we should just turn on promiscuous mode so 4226 * that we can at least receive multicast traffic 4227 */ 4228 count = igb_write_mc_addr_list(netdev); 4229 if (count < 0) { 4230 rctl |= E1000_RCTL_MPE; 4231 vmolr |= E1000_VMOLR_MPME; 4232 } else if (count) { 4233 vmolr |= E1000_VMOLR_ROMPE; 4234 } 4235 } 4236 } 4237 4238 /* Write addresses to available RAR registers, if there is not 4239 * sufficient space to store all the addresses then enable 4240 * unicast promiscuous mode 4241 */ 4242 count = igb_write_uc_addr_list(netdev); 4243 if (count < 0) { 4244 rctl |= E1000_RCTL_UPE; 4245 vmolr |= E1000_VMOLR_ROPE; 4246 } 4247 4248 /* enable VLAN filtering by default */ 4249 rctl |= E1000_RCTL_VFE; 4250 4251 /* disable VLAN filtering for modes that require it */ 4252 if ((netdev->flags & IFF_PROMISC) || 4253 (netdev->features & NETIF_F_RXALL)) { 4254 /* if we fail to set all rules then just clear VFE */ 4255 if (igb_vlan_promisc_enable(adapter)) 4256 rctl &= ~E1000_RCTL_VFE; 4257 } else { 4258 igb_vlan_promisc_disable(adapter); 4259 } 4260 4261 /* update state of unicast, multicast, and VLAN filtering modes */ 4262 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4263 E1000_RCTL_VFE); 4264 wr32(E1000_RCTL, rctl); 4265 4266 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4267 * the VMOLR to enable the appropriate modes. Without this workaround 4268 * we will have issues with VLAN tag stripping not being done for frames 4269 * that are only arriving because we are the default pool 4270 */ 4271 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4272 return; 4273 4274 /* set UTA to appropriate mode */ 4275 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4276 4277 vmolr |= rd32(E1000_VMOLR(vfn)) & 4278 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4279 4280 /* enable Rx jumbo frames, no need for restriction */ 4281 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4282 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE; 4283 4284 wr32(E1000_VMOLR(vfn), vmolr); 4285 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE); 4286 4287 igb_restore_vf_multicasts(adapter); 4288 } 4289 4290 static void igb_check_wvbr(struct igb_adapter *adapter) 4291 { 4292 struct e1000_hw *hw = &adapter->hw; 4293 u32 wvbr = 0; 4294 4295 switch (hw->mac.type) { 4296 case e1000_82576: 4297 case e1000_i350: 4298 wvbr = rd32(E1000_WVBR); 4299 if (!wvbr) 4300 return; 4301 break; 4302 default: 4303 break; 4304 } 4305 4306 adapter->wvbr |= wvbr; 4307 } 4308 4309 #define IGB_STAGGERED_QUEUE_OFFSET 8 4310 4311 static void igb_spoof_check(struct igb_adapter *adapter) 4312 { 4313 int j; 4314 4315 if (!adapter->wvbr) 4316 return; 4317 4318 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4319 if (adapter->wvbr & BIT(j) || 4320 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4321 dev_warn(&adapter->pdev->dev, 4322 "Spoof event(s) detected on VF %d\n", j); 4323 adapter->wvbr &= 4324 ~(BIT(j) | 4325 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4326 } 4327 } 4328 } 4329 4330 /* Need to wait a few seconds after link up to get diagnostic information from 4331 * the phy 4332 */ 4333 static void igb_update_phy_info(unsigned long data) 4334 { 4335 struct igb_adapter *adapter = (struct igb_adapter *) data; 4336 igb_get_phy_info(&adapter->hw); 4337 } 4338 4339 /** 4340 * igb_has_link - check shared code for link and determine up/down 4341 * @adapter: pointer to driver private info 4342 **/ 4343 bool igb_has_link(struct igb_adapter *adapter) 4344 { 4345 struct e1000_hw *hw = &adapter->hw; 4346 bool link_active = false; 4347 4348 /* get_link_status is set on LSC (link status) interrupt or 4349 * rx sequence error interrupt. get_link_status will stay 4350 * false until the e1000_check_for_link establishes link 4351 * for copper adapters ONLY 4352 */ 4353 switch (hw->phy.media_type) { 4354 case e1000_media_type_copper: 4355 if (!hw->mac.get_link_status) 4356 return true; 4357 case e1000_media_type_internal_serdes: 4358 hw->mac.ops.check_for_link(hw); 4359 link_active = !hw->mac.get_link_status; 4360 break; 4361 default: 4362 case e1000_media_type_unknown: 4363 break; 4364 } 4365 4366 if (((hw->mac.type == e1000_i210) || 4367 (hw->mac.type == e1000_i211)) && 4368 (hw->phy.id == I210_I_PHY_ID)) { 4369 if (!netif_carrier_ok(adapter->netdev)) { 4370 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4371 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4372 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4373 adapter->link_check_timeout = jiffies; 4374 } 4375 } 4376 4377 return link_active; 4378 } 4379 4380 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4381 { 4382 bool ret = false; 4383 u32 ctrl_ext, thstat; 4384 4385 /* check for thermal sensor event on i350 copper only */ 4386 if (hw->mac.type == e1000_i350) { 4387 thstat = rd32(E1000_THSTAT); 4388 ctrl_ext = rd32(E1000_CTRL_EXT); 4389 4390 if ((hw->phy.media_type == e1000_media_type_copper) && 4391 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4392 ret = !!(thstat & event); 4393 } 4394 4395 return ret; 4396 } 4397 4398 /** 4399 * igb_check_lvmmc - check for malformed packets received 4400 * and indicated in LVMMC register 4401 * @adapter: pointer to adapter 4402 **/ 4403 static void igb_check_lvmmc(struct igb_adapter *adapter) 4404 { 4405 struct e1000_hw *hw = &adapter->hw; 4406 u32 lvmmc; 4407 4408 lvmmc = rd32(E1000_LVMMC); 4409 if (lvmmc) { 4410 if (unlikely(net_ratelimit())) { 4411 netdev_warn(adapter->netdev, 4412 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4413 lvmmc); 4414 } 4415 } 4416 } 4417 4418 /** 4419 * igb_watchdog - Timer Call-back 4420 * @data: pointer to adapter cast into an unsigned long 4421 **/ 4422 static void igb_watchdog(unsigned long data) 4423 { 4424 struct igb_adapter *adapter = (struct igb_adapter *)data; 4425 /* Do the rest outside of interrupt context */ 4426 schedule_work(&adapter->watchdog_task); 4427 } 4428 4429 static void igb_watchdog_task(struct work_struct *work) 4430 { 4431 struct igb_adapter *adapter = container_of(work, 4432 struct igb_adapter, 4433 watchdog_task); 4434 struct e1000_hw *hw = &adapter->hw; 4435 struct e1000_phy_info *phy = &hw->phy; 4436 struct net_device *netdev = adapter->netdev; 4437 u32 link; 4438 int i; 4439 u32 connsw; 4440 u16 phy_data, retry_count = 20; 4441 4442 link = igb_has_link(adapter); 4443 4444 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4445 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4446 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4447 else 4448 link = false; 4449 } 4450 4451 /* Force link down if we have fiber to swap to */ 4452 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4453 if (hw->phy.media_type == e1000_media_type_copper) { 4454 connsw = rd32(E1000_CONNSW); 4455 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4456 link = 0; 4457 } 4458 } 4459 if (link) { 4460 /* Perform a reset if the media type changed. */ 4461 if (hw->dev_spec._82575.media_changed) { 4462 hw->dev_spec._82575.media_changed = false; 4463 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4464 igb_reset(adapter); 4465 } 4466 /* Cancel scheduled suspend requests. */ 4467 pm_runtime_resume(netdev->dev.parent); 4468 4469 if (!netif_carrier_ok(netdev)) { 4470 u32 ctrl; 4471 4472 hw->mac.ops.get_speed_and_duplex(hw, 4473 &adapter->link_speed, 4474 &adapter->link_duplex); 4475 4476 ctrl = rd32(E1000_CTRL); 4477 /* Links status message must follow this format */ 4478 netdev_info(netdev, 4479 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4480 netdev->name, 4481 adapter->link_speed, 4482 adapter->link_duplex == FULL_DUPLEX ? 4483 "Full" : "Half", 4484 (ctrl & E1000_CTRL_TFCE) && 4485 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4486 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4487 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4488 4489 /* disable EEE if enabled */ 4490 if ((adapter->flags & IGB_FLAG_EEE) && 4491 (adapter->link_duplex == HALF_DUPLEX)) { 4492 dev_info(&adapter->pdev->dev, 4493 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4494 adapter->hw.dev_spec._82575.eee_disable = true; 4495 adapter->flags &= ~IGB_FLAG_EEE; 4496 } 4497 4498 /* check if SmartSpeed worked */ 4499 igb_check_downshift(hw); 4500 if (phy->speed_downgraded) 4501 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4502 4503 /* check for thermal sensor event */ 4504 if (igb_thermal_sensor_event(hw, 4505 E1000_THSTAT_LINK_THROTTLE)) 4506 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4507 4508 /* adjust timeout factor according to speed/duplex */ 4509 adapter->tx_timeout_factor = 1; 4510 switch (adapter->link_speed) { 4511 case SPEED_10: 4512 adapter->tx_timeout_factor = 14; 4513 break; 4514 case SPEED_100: 4515 /* maybe add some timeout factor ? */ 4516 break; 4517 } 4518 4519 if (adapter->link_speed != SPEED_1000) 4520 goto no_wait; 4521 4522 /* wait for Remote receiver status OK */ 4523 retry_read_status: 4524 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4525 &phy_data)) { 4526 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4527 retry_count) { 4528 msleep(100); 4529 retry_count--; 4530 goto retry_read_status; 4531 } else if (!retry_count) { 4532 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4533 } 4534 } else { 4535 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4536 } 4537 no_wait: 4538 netif_carrier_on(netdev); 4539 4540 igb_ping_all_vfs(adapter); 4541 igb_check_vf_rate_limit(adapter); 4542 4543 /* link state has changed, schedule phy info update */ 4544 if (!test_bit(__IGB_DOWN, &adapter->state)) 4545 mod_timer(&adapter->phy_info_timer, 4546 round_jiffies(jiffies + 2 * HZ)); 4547 } 4548 } else { 4549 if (netif_carrier_ok(netdev)) { 4550 adapter->link_speed = 0; 4551 adapter->link_duplex = 0; 4552 4553 /* check for thermal sensor event */ 4554 if (igb_thermal_sensor_event(hw, 4555 E1000_THSTAT_PWR_DOWN)) { 4556 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4557 } 4558 4559 /* Links status message must follow this format */ 4560 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4561 netdev->name); 4562 netif_carrier_off(netdev); 4563 4564 igb_ping_all_vfs(adapter); 4565 4566 /* link state has changed, schedule phy info update */ 4567 if (!test_bit(__IGB_DOWN, &adapter->state)) 4568 mod_timer(&adapter->phy_info_timer, 4569 round_jiffies(jiffies + 2 * HZ)); 4570 4571 /* link is down, time to check for alternate media */ 4572 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4573 igb_check_swap_media(adapter); 4574 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4575 schedule_work(&adapter->reset_task); 4576 /* return immediately */ 4577 return; 4578 } 4579 } 4580 pm_schedule_suspend(netdev->dev.parent, 4581 MSEC_PER_SEC * 5); 4582 4583 /* also check for alternate media here */ 4584 } else if (!netif_carrier_ok(netdev) && 4585 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4586 igb_check_swap_media(adapter); 4587 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4588 schedule_work(&adapter->reset_task); 4589 /* return immediately */ 4590 return; 4591 } 4592 } 4593 } 4594 4595 spin_lock(&adapter->stats64_lock); 4596 igb_update_stats(adapter, &adapter->stats64); 4597 spin_unlock(&adapter->stats64_lock); 4598 4599 for (i = 0; i < adapter->num_tx_queues; i++) { 4600 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4601 if (!netif_carrier_ok(netdev)) { 4602 /* We've lost link, so the controller stops DMA, 4603 * but we've got queued Tx work that's never going 4604 * to get done, so reset controller to flush Tx. 4605 * (Do the reset outside of interrupt context). 4606 */ 4607 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4608 adapter->tx_timeout_count++; 4609 schedule_work(&adapter->reset_task); 4610 /* return immediately since reset is imminent */ 4611 return; 4612 } 4613 } 4614 4615 /* Force detection of hung controller every watchdog period */ 4616 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4617 } 4618 4619 /* Cause software interrupt to ensure Rx ring is cleaned */ 4620 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4621 u32 eics = 0; 4622 4623 for (i = 0; i < adapter->num_q_vectors; i++) 4624 eics |= adapter->q_vector[i]->eims_value; 4625 wr32(E1000_EICS, eics); 4626 } else { 4627 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4628 } 4629 4630 igb_spoof_check(adapter); 4631 igb_ptp_rx_hang(adapter); 4632 4633 /* Check LVMMC register on i350/i354 only */ 4634 if ((adapter->hw.mac.type == e1000_i350) || 4635 (adapter->hw.mac.type == e1000_i354)) 4636 igb_check_lvmmc(adapter); 4637 4638 /* Reset the timer */ 4639 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4640 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4641 mod_timer(&adapter->watchdog_timer, 4642 round_jiffies(jiffies + HZ)); 4643 else 4644 mod_timer(&adapter->watchdog_timer, 4645 round_jiffies(jiffies + 2 * HZ)); 4646 } 4647 } 4648 4649 enum latency_range { 4650 lowest_latency = 0, 4651 low_latency = 1, 4652 bulk_latency = 2, 4653 latency_invalid = 255 4654 }; 4655 4656 /** 4657 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4658 * @q_vector: pointer to q_vector 4659 * 4660 * Stores a new ITR value based on strictly on packet size. This 4661 * algorithm is less sophisticated than that used in igb_update_itr, 4662 * due to the difficulty of synchronizing statistics across multiple 4663 * receive rings. The divisors and thresholds used by this function 4664 * were determined based on theoretical maximum wire speed and testing 4665 * data, in order to minimize response time while increasing bulk 4666 * throughput. 4667 * This functionality is controlled by ethtool's coalescing settings. 4668 * NOTE: This function is called only when operating in a multiqueue 4669 * receive environment. 4670 **/ 4671 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4672 { 4673 int new_val = q_vector->itr_val; 4674 int avg_wire_size = 0; 4675 struct igb_adapter *adapter = q_vector->adapter; 4676 unsigned int packets; 4677 4678 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4679 * ints/sec - ITR timer value of 120 ticks. 4680 */ 4681 if (adapter->link_speed != SPEED_1000) { 4682 new_val = IGB_4K_ITR; 4683 goto set_itr_val; 4684 } 4685 4686 packets = q_vector->rx.total_packets; 4687 if (packets) 4688 avg_wire_size = q_vector->rx.total_bytes / packets; 4689 4690 packets = q_vector->tx.total_packets; 4691 if (packets) 4692 avg_wire_size = max_t(u32, avg_wire_size, 4693 q_vector->tx.total_bytes / packets); 4694 4695 /* if avg_wire_size isn't set no work was done */ 4696 if (!avg_wire_size) 4697 goto clear_counts; 4698 4699 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4700 avg_wire_size += 24; 4701 4702 /* Don't starve jumbo frames */ 4703 avg_wire_size = min(avg_wire_size, 3000); 4704 4705 /* Give a little boost to mid-size frames */ 4706 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4707 new_val = avg_wire_size / 3; 4708 else 4709 new_val = avg_wire_size / 2; 4710 4711 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4712 if (new_val < IGB_20K_ITR && 4713 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4714 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4715 new_val = IGB_20K_ITR; 4716 4717 set_itr_val: 4718 if (new_val != q_vector->itr_val) { 4719 q_vector->itr_val = new_val; 4720 q_vector->set_itr = 1; 4721 } 4722 clear_counts: 4723 q_vector->rx.total_bytes = 0; 4724 q_vector->rx.total_packets = 0; 4725 q_vector->tx.total_bytes = 0; 4726 q_vector->tx.total_packets = 0; 4727 } 4728 4729 /** 4730 * igb_update_itr - update the dynamic ITR value based on statistics 4731 * @q_vector: pointer to q_vector 4732 * @ring_container: ring info to update the itr for 4733 * 4734 * Stores a new ITR value based on packets and byte 4735 * counts during the last interrupt. The advantage of per interrupt 4736 * computation is faster updates and more accurate ITR for the current 4737 * traffic pattern. Constants in this function were computed 4738 * based on theoretical maximum wire speed and thresholds were set based 4739 * on testing data as well as attempting to minimize response time 4740 * while increasing bulk throughput. 4741 * This functionality is controlled by ethtool's coalescing settings. 4742 * NOTE: These calculations are only valid when operating in a single- 4743 * queue environment. 4744 **/ 4745 static void igb_update_itr(struct igb_q_vector *q_vector, 4746 struct igb_ring_container *ring_container) 4747 { 4748 unsigned int packets = ring_container->total_packets; 4749 unsigned int bytes = ring_container->total_bytes; 4750 u8 itrval = ring_container->itr; 4751 4752 /* no packets, exit with status unchanged */ 4753 if (packets == 0) 4754 return; 4755 4756 switch (itrval) { 4757 case lowest_latency: 4758 /* handle TSO and jumbo frames */ 4759 if (bytes/packets > 8000) 4760 itrval = bulk_latency; 4761 else if ((packets < 5) && (bytes > 512)) 4762 itrval = low_latency; 4763 break; 4764 case low_latency: /* 50 usec aka 20000 ints/s */ 4765 if (bytes > 10000) { 4766 /* this if handles the TSO accounting */ 4767 if (bytes/packets > 8000) 4768 itrval = bulk_latency; 4769 else if ((packets < 10) || ((bytes/packets) > 1200)) 4770 itrval = bulk_latency; 4771 else if ((packets > 35)) 4772 itrval = lowest_latency; 4773 } else if (bytes/packets > 2000) { 4774 itrval = bulk_latency; 4775 } else if (packets <= 2 && bytes < 512) { 4776 itrval = lowest_latency; 4777 } 4778 break; 4779 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4780 if (bytes > 25000) { 4781 if (packets > 35) 4782 itrval = low_latency; 4783 } else if (bytes < 1500) { 4784 itrval = low_latency; 4785 } 4786 break; 4787 } 4788 4789 /* clear work counters since we have the values we need */ 4790 ring_container->total_bytes = 0; 4791 ring_container->total_packets = 0; 4792 4793 /* write updated itr to ring container */ 4794 ring_container->itr = itrval; 4795 } 4796 4797 static void igb_set_itr(struct igb_q_vector *q_vector) 4798 { 4799 struct igb_adapter *adapter = q_vector->adapter; 4800 u32 new_itr = q_vector->itr_val; 4801 u8 current_itr = 0; 4802 4803 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4804 if (adapter->link_speed != SPEED_1000) { 4805 current_itr = 0; 4806 new_itr = IGB_4K_ITR; 4807 goto set_itr_now; 4808 } 4809 4810 igb_update_itr(q_vector, &q_vector->tx); 4811 igb_update_itr(q_vector, &q_vector->rx); 4812 4813 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4814 4815 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4816 if (current_itr == lowest_latency && 4817 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4818 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4819 current_itr = low_latency; 4820 4821 switch (current_itr) { 4822 /* counts and packets in update_itr are dependent on these numbers */ 4823 case lowest_latency: 4824 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4825 break; 4826 case low_latency: 4827 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4828 break; 4829 case bulk_latency: 4830 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4831 break; 4832 default: 4833 break; 4834 } 4835 4836 set_itr_now: 4837 if (new_itr != q_vector->itr_val) { 4838 /* this attempts to bias the interrupt rate towards Bulk 4839 * by adding intermediate steps when interrupt rate is 4840 * increasing 4841 */ 4842 new_itr = new_itr > q_vector->itr_val ? 4843 max((new_itr * q_vector->itr_val) / 4844 (new_itr + (q_vector->itr_val >> 2)), 4845 new_itr) : new_itr; 4846 /* Don't write the value here; it resets the adapter's 4847 * internal timer, and causes us to delay far longer than 4848 * we should between interrupts. Instead, we write the ITR 4849 * value at the beginning of the next interrupt so the timing 4850 * ends up being correct. 4851 */ 4852 q_vector->itr_val = new_itr; 4853 q_vector->set_itr = 1; 4854 } 4855 } 4856 4857 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4858 u32 type_tucmd, u32 mss_l4len_idx) 4859 { 4860 struct e1000_adv_tx_context_desc *context_desc; 4861 u16 i = tx_ring->next_to_use; 4862 4863 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4864 4865 i++; 4866 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4867 4868 /* set bits to identify this as an advanced context descriptor */ 4869 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4870 4871 /* For 82575, context index must be unique per ring. */ 4872 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4873 mss_l4len_idx |= tx_ring->reg_idx << 4; 4874 4875 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4876 context_desc->seqnum_seed = 0; 4877 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4878 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4879 } 4880 4881 static int igb_tso(struct igb_ring *tx_ring, 4882 struct igb_tx_buffer *first, 4883 u8 *hdr_len) 4884 { 4885 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4886 struct sk_buff *skb = first->skb; 4887 union { 4888 struct iphdr *v4; 4889 struct ipv6hdr *v6; 4890 unsigned char *hdr; 4891 } ip; 4892 union { 4893 struct tcphdr *tcp; 4894 unsigned char *hdr; 4895 } l4; 4896 u32 paylen, l4_offset; 4897 int err; 4898 4899 if (skb->ip_summed != CHECKSUM_PARTIAL) 4900 return 0; 4901 4902 if (!skb_is_gso(skb)) 4903 return 0; 4904 4905 err = skb_cow_head(skb, 0); 4906 if (err < 0) 4907 return err; 4908 4909 ip.hdr = skb_network_header(skb); 4910 l4.hdr = skb_checksum_start(skb); 4911 4912 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4913 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4914 4915 /* initialize outer IP header fields */ 4916 if (ip.v4->version == 4) { 4917 /* IP header will have to cancel out any data that 4918 * is not a part of the outer IP header 4919 */ 4920 ip.v4->check = csum_fold(csum_add(lco_csum(skb), 4921 csum_unfold(l4.tcp->check))); 4922 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4923 4924 ip.v4->tot_len = 0; 4925 first->tx_flags |= IGB_TX_FLAGS_TSO | 4926 IGB_TX_FLAGS_CSUM | 4927 IGB_TX_FLAGS_IPV4; 4928 } else { 4929 ip.v6->payload_len = 0; 4930 first->tx_flags |= IGB_TX_FLAGS_TSO | 4931 IGB_TX_FLAGS_CSUM; 4932 } 4933 4934 /* determine offset of inner transport header */ 4935 l4_offset = l4.hdr - skb->data; 4936 4937 /* compute length of segmentation header */ 4938 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 4939 4940 /* remove payload length from inner checksum */ 4941 paylen = skb->len - l4_offset; 4942 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 4943 4944 /* update gso size and bytecount with header size */ 4945 first->gso_segs = skb_shinfo(skb)->gso_segs; 4946 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4947 4948 /* MSS L4LEN IDX */ 4949 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 4950 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4951 4952 /* VLAN MACLEN IPLEN */ 4953 vlan_macip_lens = l4.hdr - ip.hdr; 4954 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 4955 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4956 4957 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4958 4959 return 1; 4960 } 4961 4962 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 4963 { 4964 unsigned int offset = 0; 4965 4966 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 4967 4968 return offset == skb_checksum_start_offset(skb); 4969 } 4970 4971 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4972 { 4973 struct sk_buff *skb = first->skb; 4974 u32 vlan_macip_lens = 0; 4975 u32 type_tucmd = 0; 4976 4977 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4978 csum_failed: 4979 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4980 return; 4981 goto no_csum; 4982 } 4983 4984 switch (skb->csum_offset) { 4985 case offsetof(struct tcphdr, check): 4986 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4987 /* fall through */ 4988 case offsetof(struct udphdr, check): 4989 break; 4990 case offsetof(struct sctphdr, checksum): 4991 /* validate that this is actually an SCTP request */ 4992 if (((first->protocol == htons(ETH_P_IP)) && 4993 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 4994 ((first->protocol == htons(ETH_P_IPV6)) && 4995 igb_ipv6_csum_is_sctp(skb))) { 4996 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 4997 break; 4998 } 4999 default: 5000 skb_checksum_help(skb); 5001 goto csum_failed; 5002 } 5003 5004 /* update TX checksum flag */ 5005 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5006 vlan_macip_lens = skb_checksum_start_offset(skb) - 5007 skb_network_offset(skb); 5008 no_csum: 5009 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5010 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5011 5012 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5013 } 5014 5015 #define IGB_SET_FLAG(_input, _flag, _result) \ 5016 ((_flag <= _result) ? \ 5017 ((u32)(_input & _flag) * (_result / _flag)) : \ 5018 ((u32)(_input & _flag) / (_flag / _result))) 5019 5020 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5021 { 5022 /* set type for advanced descriptor with frame checksum insertion */ 5023 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5024 E1000_ADVTXD_DCMD_DEXT | 5025 E1000_ADVTXD_DCMD_IFCS; 5026 5027 /* set HW vlan bit if vlan is present */ 5028 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5029 (E1000_ADVTXD_DCMD_VLE)); 5030 5031 /* set segmentation bits for TSO */ 5032 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5033 (E1000_ADVTXD_DCMD_TSE)); 5034 5035 /* set timestamp bit if present */ 5036 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5037 (E1000_ADVTXD_MAC_TSTAMP)); 5038 5039 /* insert frame checksum */ 5040 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5041 5042 return cmd_type; 5043 } 5044 5045 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5046 union e1000_adv_tx_desc *tx_desc, 5047 u32 tx_flags, unsigned int paylen) 5048 { 5049 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5050 5051 /* 82575 requires a unique index per ring */ 5052 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5053 olinfo_status |= tx_ring->reg_idx << 4; 5054 5055 /* insert L4 checksum */ 5056 olinfo_status |= IGB_SET_FLAG(tx_flags, 5057 IGB_TX_FLAGS_CSUM, 5058 (E1000_TXD_POPTS_TXSM << 8)); 5059 5060 /* insert IPv4 checksum */ 5061 olinfo_status |= IGB_SET_FLAG(tx_flags, 5062 IGB_TX_FLAGS_IPV4, 5063 (E1000_TXD_POPTS_IXSM << 8)); 5064 5065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5066 } 5067 5068 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5069 { 5070 struct net_device *netdev = tx_ring->netdev; 5071 5072 netif_stop_subqueue(netdev, tx_ring->queue_index); 5073 5074 /* Herbert's original patch had: 5075 * smp_mb__after_netif_stop_queue(); 5076 * but since that doesn't exist yet, just open code it. 5077 */ 5078 smp_mb(); 5079 5080 /* We need to check again in a case another CPU has just 5081 * made room available. 5082 */ 5083 if (igb_desc_unused(tx_ring) < size) 5084 return -EBUSY; 5085 5086 /* A reprieve! */ 5087 netif_wake_subqueue(netdev, tx_ring->queue_index); 5088 5089 u64_stats_update_begin(&tx_ring->tx_syncp2); 5090 tx_ring->tx_stats.restart_queue2++; 5091 u64_stats_update_end(&tx_ring->tx_syncp2); 5092 5093 return 0; 5094 } 5095 5096 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5097 { 5098 if (igb_desc_unused(tx_ring) >= size) 5099 return 0; 5100 return __igb_maybe_stop_tx(tx_ring, size); 5101 } 5102 5103 static void igb_tx_map(struct igb_ring *tx_ring, 5104 struct igb_tx_buffer *first, 5105 const u8 hdr_len) 5106 { 5107 struct sk_buff *skb = first->skb; 5108 struct igb_tx_buffer *tx_buffer; 5109 union e1000_adv_tx_desc *tx_desc; 5110 struct skb_frag_struct *frag; 5111 dma_addr_t dma; 5112 unsigned int data_len, size; 5113 u32 tx_flags = first->tx_flags; 5114 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5115 u16 i = tx_ring->next_to_use; 5116 5117 tx_desc = IGB_TX_DESC(tx_ring, i); 5118 5119 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5120 5121 size = skb_headlen(skb); 5122 data_len = skb->data_len; 5123 5124 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5125 5126 tx_buffer = first; 5127 5128 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5129 if (dma_mapping_error(tx_ring->dev, dma)) 5130 goto dma_error; 5131 5132 /* record length, and DMA address */ 5133 dma_unmap_len_set(tx_buffer, len, size); 5134 dma_unmap_addr_set(tx_buffer, dma, dma); 5135 5136 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5137 5138 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5139 tx_desc->read.cmd_type_len = 5140 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5141 5142 i++; 5143 tx_desc++; 5144 if (i == tx_ring->count) { 5145 tx_desc = IGB_TX_DESC(tx_ring, 0); 5146 i = 0; 5147 } 5148 tx_desc->read.olinfo_status = 0; 5149 5150 dma += IGB_MAX_DATA_PER_TXD; 5151 size -= IGB_MAX_DATA_PER_TXD; 5152 5153 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5154 } 5155 5156 if (likely(!data_len)) 5157 break; 5158 5159 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5160 5161 i++; 5162 tx_desc++; 5163 if (i == tx_ring->count) { 5164 tx_desc = IGB_TX_DESC(tx_ring, 0); 5165 i = 0; 5166 } 5167 tx_desc->read.olinfo_status = 0; 5168 5169 size = skb_frag_size(frag); 5170 data_len -= size; 5171 5172 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5173 size, DMA_TO_DEVICE); 5174 5175 tx_buffer = &tx_ring->tx_buffer_info[i]; 5176 } 5177 5178 /* write last descriptor with RS and EOP bits */ 5179 cmd_type |= size | IGB_TXD_DCMD; 5180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5181 5182 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5183 5184 /* set the timestamp */ 5185 first->time_stamp = jiffies; 5186 5187 /* Force memory writes to complete before letting h/w know there 5188 * are new descriptors to fetch. (Only applicable for weak-ordered 5189 * memory model archs, such as IA-64). 5190 * 5191 * We also need this memory barrier to make certain all of the 5192 * status bits have been updated before next_to_watch is written. 5193 */ 5194 wmb(); 5195 5196 /* set next_to_watch value indicating a packet is present */ 5197 first->next_to_watch = tx_desc; 5198 5199 i++; 5200 if (i == tx_ring->count) 5201 i = 0; 5202 5203 tx_ring->next_to_use = i; 5204 5205 /* Make sure there is space in the ring for the next send. */ 5206 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5207 5208 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5209 writel(i, tx_ring->tail); 5210 5211 /* we need this if more than one processor can write to our tail 5212 * at a time, it synchronizes IO on IA64/Altix systems 5213 */ 5214 mmiowb(); 5215 } 5216 return; 5217 5218 dma_error: 5219 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5220 5221 /* clear dma mappings for failed tx_buffer_info map */ 5222 for (;;) { 5223 tx_buffer = &tx_ring->tx_buffer_info[i]; 5224 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 5225 if (tx_buffer == first) 5226 break; 5227 if (i == 0) 5228 i = tx_ring->count; 5229 i--; 5230 } 5231 5232 tx_ring->next_to_use = i; 5233 } 5234 5235 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5236 struct igb_ring *tx_ring) 5237 { 5238 struct igb_tx_buffer *first; 5239 int tso; 5240 u32 tx_flags = 0; 5241 unsigned short f; 5242 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5243 __be16 protocol = vlan_get_protocol(skb); 5244 u8 hdr_len = 0; 5245 5246 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5247 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5248 * + 2 desc gap to keep tail from touching head, 5249 * + 1 desc for context descriptor, 5250 * otherwise try next time 5251 */ 5252 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5253 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5254 5255 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5256 /* this is a hard error */ 5257 return NETDEV_TX_BUSY; 5258 } 5259 5260 /* record the location of the first descriptor for this packet */ 5261 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5262 first->skb = skb; 5263 first->bytecount = skb->len; 5264 first->gso_segs = 1; 5265 5266 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5267 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5268 5269 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5270 &adapter->state)) { 5271 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5272 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5273 5274 adapter->ptp_tx_skb = skb_get(skb); 5275 adapter->ptp_tx_start = jiffies; 5276 if (adapter->hw.mac.type == e1000_82576) 5277 schedule_work(&adapter->ptp_tx_work); 5278 } 5279 } 5280 5281 skb_tx_timestamp(skb); 5282 5283 if (skb_vlan_tag_present(skb)) { 5284 tx_flags |= IGB_TX_FLAGS_VLAN; 5285 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5286 } 5287 5288 /* record initial flags and protocol */ 5289 first->tx_flags = tx_flags; 5290 first->protocol = protocol; 5291 5292 tso = igb_tso(tx_ring, first, &hdr_len); 5293 if (tso < 0) 5294 goto out_drop; 5295 else if (!tso) 5296 igb_tx_csum(tx_ring, first); 5297 5298 igb_tx_map(tx_ring, first, hdr_len); 5299 5300 return NETDEV_TX_OK; 5301 5302 out_drop: 5303 igb_unmap_and_free_tx_resource(tx_ring, first); 5304 5305 return NETDEV_TX_OK; 5306 } 5307 5308 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5309 struct sk_buff *skb) 5310 { 5311 unsigned int r_idx = skb->queue_mapping; 5312 5313 if (r_idx >= adapter->num_tx_queues) 5314 r_idx = r_idx % adapter->num_tx_queues; 5315 5316 return adapter->tx_ring[r_idx]; 5317 } 5318 5319 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5320 struct net_device *netdev) 5321 { 5322 struct igb_adapter *adapter = netdev_priv(netdev); 5323 5324 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5325 * in order to meet this minimum size requirement. 5326 */ 5327 if (skb_put_padto(skb, 17)) 5328 return NETDEV_TX_OK; 5329 5330 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5331 } 5332 5333 /** 5334 * igb_tx_timeout - Respond to a Tx Hang 5335 * @netdev: network interface device structure 5336 **/ 5337 static void igb_tx_timeout(struct net_device *netdev) 5338 { 5339 struct igb_adapter *adapter = netdev_priv(netdev); 5340 struct e1000_hw *hw = &adapter->hw; 5341 5342 /* Do the reset outside of interrupt context */ 5343 adapter->tx_timeout_count++; 5344 5345 if (hw->mac.type >= e1000_82580) 5346 hw->dev_spec._82575.global_device_reset = true; 5347 5348 schedule_work(&adapter->reset_task); 5349 wr32(E1000_EICS, 5350 (adapter->eims_enable_mask & ~adapter->eims_other)); 5351 } 5352 5353 static void igb_reset_task(struct work_struct *work) 5354 { 5355 struct igb_adapter *adapter; 5356 adapter = container_of(work, struct igb_adapter, reset_task); 5357 5358 igb_dump(adapter); 5359 netdev_err(adapter->netdev, "Reset adapter\n"); 5360 igb_reinit_locked(adapter); 5361 } 5362 5363 /** 5364 * igb_get_stats64 - Get System Network Statistics 5365 * @netdev: network interface device structure 5366 * @stats: rtnl_link_stats64 pointer 5367 **/ 5368 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5369 struct rtnl_link_stats64 *stats) 5370 { 5371 struct igb_adapter *adapter = netdev_priv(netdev); 5372 5373 spin_lock(&adapter->stats64_lock); 5374 igb_update_stats(adapter, &adapter->stats64); 5375 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5376 spin_unlock(&adapter->stats64_lock); 5377 5378 return stats; 5379 } 5380 5381 /** 5382 * igb_change_mtu - Change the Maximum Transfer Unit 5383 * @netdev: network interface device structure 5384 * @new_mtu: new value for maximum frame size 5385 * 5386 * Returns 0 on success, negative on failure 5387 **/ 5388 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5389 { 5390 struct igb_adapter *adapter = netdev_priv(netdev); 5391 struct pci_dev *pdev = adapter->pdev; 5392 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5393 5394 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5395 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5396 return -EINVAL; 5397 } 5398 5399 #define MAX_STD_JUMBO_FRAME_SIZE 9238 5400 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5401 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5402 return -EINVAL; 5403 } 5404 5405 /* adjust max frame to be at least the size of a standard frame */ 5406 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5407 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5408 5409 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5410 usleep_range(1000, 2000); 5411 5412 /* igb_down has a dependency on max_frame_size */ 5413 adapter->max_frame_size = max_frame; 5414 5415 if (netif_running(netdev)) 5416 igb_down(adapter); 5417 5418 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5419 netdev->mtu, new_mtu); 5420 netdev->mtu = new_mtu; 5421 5422 if (netif_running(netdev)) 5423 igb_up(adapter); 5424 else 5425 igb_reset(adapter); 5426 5427 clear_bit(__IGB_RESETTING, &adapter->state); 5428 5429 return 0; 5430 } 5431 5432 /** 5433 * igb_update_stats - Update the board statistics counters 5434 * @adapter: board private structure 5435 **/ 5436 void igb_update_stats(struct igb_adapter *adapter, 5437 struct rtnl_link_stats64 *net_stats) 5438 { 5439 struct e1000_hw *hw = &adapter->hw; 5440 struct pci_dev *pdev = adapter->pdev; 5441 u32 reg, mpc; 5442 int i; 5443 u64 bytes, packets; 5444 unsigned int start; 5445 u64 _bytes, _packets; 5446 5447 /* Prevent stats update while adapter is being reset, or if the pci 5448 * connection is down. 5449 */ 5450 if (adapter->link_speed == 0) 5451 return; 5452 if (pci_channel_offline(pdev)) 5453 return; 5454 5455 bytes = 0; 5456 packets = 0; 5457 5458 rcu_read_lock(); 5459 for (i = 0; i < adapter->num_rx_queues; i++) { 5460 struct igb_ring *ring = adapter->rx_ring[i]; 5461 u32 rqdpc = rd32(E1000_RQDPC(i)); 5462 if (hw->mac.type >= e1000_i210) 5463 wr32(E1000_RQDPC(i), 0); 5464 5465 if (rqdpc) { 5466 ring->rx_stats.drops += rqdpc; 5467 net_stats->rx_fifo_errors += rqdpc; 5468 } 5469 5470 do { 5471 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5472 _bytes = ring->rx_stats.bytes; 5473 _packets = ring->rx_stats.packets; 5474 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5475 bytes += _bytes; 5476 packets += _packets; 5477 } 5478 5479 net_stats->rx_bytes = bytes; 5480 net_stats->rx_packets = packets; 5481 5482 bytes = 0; 5483 packets = 0; 5484 for (i = 0; i < adapter->num_tx_queues; i++) { 5485 struct igb_ring *ring = adapter->tx_ring[i]; 5486 do { 5487 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5488 _bytes = ring->tx_stats.bytes; 5489 _packets = ring->tx_stats.packets; 5490 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5491 bytes += _bytes; 5492 packets += _packets; 5493 } 5494 net_stats->tx_bytes = bytes; 5495 net_stats->tx_packets = packets; 5496 rcu_read_unlock(); 5497 5498 /* read stats registers */ 5499 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5500 adapter->stats.gprc += rd32(E1000_GPRC); 5501 adapter->stats.gorc += rd32(E1000_GORCL); 5502 rd32(E1000_GORCH); /* clear GORCL */ 5503 adapter->stats.bprc += rd32(E1000_BPRC); 5504 adapter->stats.mprc += rd32(E1000_MPRC); 5505 adapter->stats.roc += rd32(E1000_ROC); 5506 5507 adapter->stats.prc64 += rd32(E1000_PRC64); 5508 adapter->stats.prc127 += rd32(E1000_PRC127); 5509 adapter->stats.prc255 += rd32(E1000_PRC255); 5510 adapter->stats.prc511 += rd32(E1000_PRC511); 5511 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5512 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5513 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5514 adapter->stats.sec += rd32(E1000_SEC); 5515 5516 mpc = rd32(E1000_MPC); 5517 adapter->stats.mpc += mpc; 5518 net_stats->rx_fifo_errors += mpc; 5519 adapter->stats.scc += rd32(E1000_SCC); 5520 adapter->stats.ecol += rd32(E1000_ECOL); 5521 adapter->stats.mcc += rd32(E1000_MCC); 5522 adapter->stats.latecol += rd32(E1000_LATECOL); 5523 adapter->stats.dc += rd32(E1000_DC); 5524 adapter->stats.rlec += rd32(E1000_RLEC); 5525 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5526 adapter->stats.xontxc += rd32(E1000_XONTXC); 5527 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5528 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5529 adapter->stats.fcruc += rd32(E1000_FCRUC); 5530 adapter->stats.gptc += rd32(E1000_GPTC); 5531 adapter->stats.gotc += rd32(E1000_GOTCL); 5532 rd32(E1000_GOTCH); /* clear GOTCL */ 5533 adapter->stats.rnbc += rd32(E1000_RNBC); 5534 adapter->stats.ruc += rd32(E1000_RUC); 5535 adapter->stats.rfc += rd32(E1000_RFC); 5536 adapter->stats.rjc += rd32(E1000_RJC); 5537 adapter->stats.tor += rd32(E1000_TORH); 5538 adapter->stats.tot += rd32(E1000_TOTH); 5539 adapter->stats.tpr += rd32(E1000_TPR); 5540 5541 adapter->stats.ptc64 += rd32(E1000_PTC64); 5542 adapter->stats.ptc127 += rd32(E1000_PTC127); 5543 adapter->stats.ptc255 += rd32(E1000_PTC255); 5544 adapter->stats.ptc511 += rd32(E1000_PTC511); 5545 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5546 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5547 5548 adapter->stats.mptc += rd32(E1000_MPTC); 5549 adapter->stats.bptc += rd32(E1000_BPTC); 5550 5551 adapter->stats.tpt += rd32(E1000_TPT); 5552 adapter->stats.colc += rd32(E1000_COLC); 5553 5554 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5555 /* read internal phy specific stats */ 5556 reg = rd32(E1000_CTRL_EXT); 5557 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5558 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5559 5560 /* this stat has invalid values on i210/i211 */ 5561 if ((hw->mac.type != e1000_i210) && 5562 (hw->mac.type != e1000_i211)) 5563 adapter->stats.tncrs += rd32(E1000_TNCRS); 5564 } 5565 5566 adapter->stats.tsctc += rd32(E1000_TSCTC); 5567 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5568 5569 adapter->stats.iac += rd32(E1000_IAC); 5570 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5571 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5572 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5573 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5574 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5575 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5576 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5577 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5578 5579 /* Fill out the OS statistics structure */ 5580 net_stats->multicast = adapter->stats.mprc; 5581 net_stats->collisions = adapter->stats.colc; 5582 5583 /* Rx Errors */ 5584 5585 /* RLEC on some newer hardware can be incorrect so build 5586 * our own version based on RUC and ROC 5587 */ 5588 net_stats->rx_errors = adapter->stats.rxerrc + 5589 adapter->stats.crcerrs + adapter->stats.algnerrc + 5590 adapter->stats.ruc + adapter->stats.roc + 5591 adapter->stats.cexterr; 5592 net_stats->rx_length_errors = adapter->stats.ruc + 5593 adapter->stats.roc; 5594 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5595 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5596 net_stats->rx_missed_errors = adapter->stats.mpc; 5597 5598 /* Tx Errors */ 5599 net_stats->tx_errors = adapter->stats.ecol + 5600 adapter->stats.latecol; 5601 net_stats->tx_aborted_errors = adapter->stats.ecol; 5602 net_stats->tx_window_errors = adapter->stats.latecol; 5603 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5604 5605 /* Tx Dropped needs to be maintained elsewhere */ 5606 5607 /* Management Stats */ 5608 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5609 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5610 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5611 5612 /* OS2BMC Stats */ 5613 reg = rd32(E1000_MANC); 5614 if (reg & E1000_MANC_EN_BMC2OS) { 5615 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5616 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5617 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5618 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5619 } 5620 } 5621 5622 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5623 { 5624 struct e1000_hw *hw = &adapter->hw; 5625 struct ptp_clock_event event; 5626 struct timespec64 ts; 5627 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5628 5629 if (tsicr & TSINTR_SYS_WRAP) { 5630 event.type = PTP_CLOCK_PPS; 5631 if (adapter->ptp_caps.pps) 5632 ptp_clock_event(adapter->ptp_clock, &event); 5633 else 5634 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5635 ack |= TSINTR_SYS_WRAP; 5636 } 5637 5638 if (tsicr & E1000_TSICR_TXTS) { 5639 /* retrieve hardware timestamp */ 5640 schedule_work(&adapter->ptp_tx_work); 5641 ack |= E1000_TSICR_TXTS; 5642 } 5643 5644 if (tsicr & TSINTR_TT0) { 5645 spin_lock(&adapter->tmreg_lock); 5646 ts = timespec64_add(adapter->perout[0].start, 5647 adapter->perout[0].period); 5648 /* u32 conversion of tv_sec is safe until y2106 */ 5649 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5650 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5651 tsauxc = rd32(E1000_TSAUXC); 5652 tsauxc |= TSAUXC_EN_TT0; 5653 wr32(E1000_TSAUXC, tsauxc); 5654 adapter->perout[0].start = ts; 5655 spin_unlock(&adapter->tmreg_lock); 5656 ack |= TSINTR_TT0; 5657 } 5658 5659 if (tsicr & TSINTR_TT1) { 5660 spin_lock(&adapter->tmreg_lock); 5661 ts = timespec64_add(adapter->perout[1].start, 5662 adapter->perout[1].period); 5663 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5664 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5665 tsauxc = rd32(E1000_TSAUXC); 5666 tsauxc |= TSAUXC_EN_TT1; 5667 wr32(E1000_TSAUXC, tsauxc); 5668 adapter->perout[1].start = ts; 5669 spin_unlock(&adapter->tmreg_lock); 5670 ack |= TSINTR_TT1; 5671 } 5672 5673 if (tsicr & TSINTR_AUTT0) { 5674 nsec = rd32(E1000_AUXSTMPL0); 5675 sec = rd32(E1000_AUXSTMPH0); 5676 event.type = PTP_CLOCK_EXTTS; 5677 event.index = 0; 5678 event.timestamp = sec * 1000000000ULL + nsec; 5679 ptp_clock_event(adapter->ptp_clock, &event); 5680 ack |= TSINTR_AUTT0; 5681 } 5682 5683 if (tsicr & TSINTR_AUTT1) { 5684 nsec = rd32(E1000_AUXSTMPL1); 5685 sec = rd32(E1000_AUXSTMPH1); 5686 event.type = PTP_CLOCK_EXTTS; 5687 event.index = 1; 5688 event.timestamp = sec * 1000000000ULL + nsec; 5689 ptp_clock_event(adapter->ptp_clock, &event); 5690 ack |= TSINTR_AUTT1; 5691 } 5692 5693 /* acknowledge the interrupts */ 5694 wr32(E1000_TSICR, ack); 5695 } 5696 5697 static irqreturn_t igb_msix_other(int irq, void *data) 5698 { 5699 struct igb_adapter *adapter = data; 5700 struct e1000_hw *hw = &adapter->hw; 5701 u32 icr = rd32(E1000_ICR); 5702 /* reading ICR causes bit 31 of EICR to be cleared */ 5703 5704 if (icr & E1000_ICR_DRSTA) 5705 schedule_work(&adapter->reset_task); 5706 5707 if (icr & E1000_ICR_DOUTSYNC) { 5708 /* HW is reporting DMA is out of sync */ 5709 adapter->stats.doosync++; 5710 /* The DMA Out of Sync is also indication of a spoof event 5711 * in IOV mode. Check the Wrong VM Behavior register to 5712 * see if it is really a spoof event. 5713 */ 5714 igb_check_wvbr(adapter); 5715 } 5716 5717 /* Check for a mailbox event */ 5718 if (icr & E1000_ICR_VMMB) 5719 igb_msg_task(adapter); 5720 5721 if (icr & E1000_ICR_LSC) { 5722 hw->mac.get_link_status = 1; 5723 /* guard against interrupt when we're going down */ 5724 if (!test_bit(__IGB_DOWN, &adapter->state)) 5725 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5726 } 5727 5728 if (icr & E1000_ICR_TS) 5729 igb_tsync_interrupt(adapter); 5730 5731 wr32(E1000_EIMS, adapter->eims_other); 5732 5733 return IRQ_HANDLED; 5734 } 5735 5736 static void igb_write_itr(struct igb_q_vector *q_vector) 5737 { 5738 struct igb_adapter *adapter = q_vector->adapter; 5739 u32 itr_val = q_vector->itr_val & 0x7FFC; 5740 5741 if (!q_vector->set_itr) 5742 return; 5743 5744 if (!itr_val) 5745 itr_val = 0x4; 5746 5747 if (adapter->hw.mac.type == e1000_82575) 5748 itr_val |= itr_val << 16; 5749 else 5750 itr_val |= E1000_EITR_CNT_IGNR; 5751 5752 writel(itr_val, q_vector->itr_register); 5753 q_vector->set_itr = 0; 5754 } 5755 5756 static irqreturn_t igb_msix_ring(int irq, void *data) 5757 { 5758 struct igb_q_vector *q_vector = data; 5759 5760 /* Write the ITR value calculated from the previous interrupt. */ 5761 igb_write_itr(q_vector); 5762 5763 napi_schedule(&q_vector->napi); 5764 5765 return IRQ_HANDLED; 5766 } 5767 5768 #ifdef CONFIG_IGB_DCA 5769 static void igb_update_tx_dca(struct igb_adapter *adapter, 5770 struct igb_ring *tx_ring, 5771 int cpu) 5772 { 5773 struct e1000_hw *hw = &adapter->hw; 5774 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5775 5776 if (hw->mac.type != e1000_82575) 5777 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5778 5779 /* We can enable relaxed ordering for reads, but not writes when 5780 * DCA is enabled. This is due to a known issue in some chipsets 5781 * which will cause the DCA tag to be cleared. 5782 */ 5783 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5784 E1000_DCA_TXCTRL_DATA_RRO_EN | 5785 E1000_DCA_TXCTRL_DESC_DCA_EN; 5786 5787 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5788 } 5789 5790 static void igb_update_rx_dca(struct igb_adapter *adapter, 5791 struct igb_ring *rx_ring, 5792 int cpu) 5793 { 5794 struct e1000_hw *hw = &adapter->hw; 5795 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5796 5797 if (hw->mac.type != e1000_82575) 5798 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5799 5800 /* We can enable relaxed ordering for reads, but not writes when 5801 * DCA is enabled. This is due to a known issue in some chipsets 5802 * which will cause the DCA tag to be cleared. 5803 */ 5804 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5805 E1000_DCA_RXCTRL_DESC_DCA_EN; 5806 5807 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5808 } 5809 5810 static void igb_update_dca(struct igb_q_vector *q_vector) 5811 { 5812 struct igb_adapter *adapter = q_vector->adapter; 5813 int cpu = get_cpu(); 5814 5815 if (q_vector->cpu == cpu) 5816 goto out_no_update; 5817 5818 if (q_vector->tx.ring) 5819 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5820 5821 if (q_vector->rx.ring) 5822 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5823 5824 q_vector->cpu = cpu; 5825 out_no_update: 5826 put_cpu(); 5827 } 5828 5829 static void igb_setup_dca(struct igb_adapter *adapter) 5830 { 5831 struct e1000_hw *hw = &adapter->hw; 5832 int i; 5833 5834 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5835 return; 5836 5837 /* Always use CB2 mode, difference is masked in the CB driver. */ 5838 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5839 5840 for (i = 0; i < adapter->num_q_vectors; i++) { 5841 adapter->q_vector[i]->cpu = -1; 5842 igb_update_dca(adapter->q_vector[i]); 5843 } 5844 } 5845 5846 static int __igb_notify_dca(struct device *dev, void *data) 5847 { 5848 struct net_device *netdev = dev_get_drvdata(dev); 5849 struct igb_adapter *adapter = netdev_priv(netdev); 5850 struct pci_dev *pdev = adapter->pdev; 5851 struct e1000_hw *hw = &adapter->hw; 5852 unsigned long event = *(unsigned long *)data; 5853 5854 switch (event) { 5855 case DCA_PROVIDER_ADD: 5856 /* if already enabled, don't do it again */ 5857 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5858 break; 5859 if (dca_add_requester(dev) == 0) { 5860 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5861 dev_info(&pdev->dev, "DCA enabled\n"); 5862 igb_setup_dca(adapter); 5863 break; 5864 } 5865 /* Fall Through since DCA is disabled. */ 5866 case DCA_PROVIDER_REMOVE: 5867 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5868 /* without this a class_device is left 5869 * hanging around in the sysfs model 5870 */ 5871 dca_remove_requester(dev); 5872 dev_info(&pdev->dev, "DCA disabled\n"); 5873 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5874 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5875 } 5876 break; 5877 } 5878 5879 return 0; 5880 } 5881 5882 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5883 void *p) 5884 { 5885 int ret_val; 5886 5887 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5888 __igb_notify_dca); 5889 5890 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5891 } 5892 #endif /* CONFIG_IGB_DCA */ 5893 5894 #ifdef CONFIG_PCI_IOV 5895 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5896 { 5897 unsigned char mac_addr[ETH_ALEN]; 5898 5899 eth_zero_addr(mac_addr); 5900 igb_set_vf_mac(adapter, vf, mac_addr); 5901 5902 /* By default spoof check is enabled for all VFs */ 5903 adapter->vf_data[vf].spoofchk_enabled = true; 5904 5905 return 0; 5906 } 5907 5908 #endif 5909 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5910 { 5911 struct e1000_hw *hw = &adapter->hw; 5912 u32 ping; 5913 int i; 5914 5915 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5916 ping = E1000_PF_CONTROL_MSG; 5917 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5918 ping |= E1000_VT_MSGTYPE_CTS; 5919 igb_write_mbx(hw, &ping, 1, i); 5920 } 5921 } 5922 5923 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5924 { 5925 struct e1000_hw *hw = &adapter->hw; 5926 u32 vmolr = rd32(E1000_VMOLR(vf)); 5927 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5928 5929 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5930 IGB_VF_FLAG_MULTI_PROMISC); 5931 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5932 5933 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5934 vmolr |= E1000_VMOLR_MPME; 5935 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5936 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5937 } else { 5938 /* if we have hashes and we are clearing a multicast promisc 5939 * flag we need to write the hashes to the MTA as this step 5940 * was previously skipped 5941 */ 5942 if (vf_data->num_vf_mc_hashes > 30) { 5943 vmolr |= E1000_VMOLR_MPME; 5944 } else if (vf_data->num_vf_mc_hashes) { 5945 int j; 5946 5947 vmolr |= E1000_VMOLR_ROMPE; 5948 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5949 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5950 } 5951 } 5952 5953 wr32(E1000_VMOLR(vf), vmolr); 5954 5955 /* there are flags left unprocessed, likely not supported */ 5956 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5957 return -EINVAL; 5958 5959 return 0; 5960 } 5961 5962 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5963 u32 *msgbuf, u32 vf) 5964 { 5965 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5966 u16 *hash_list = (u16 *)&msgbuf[1]; 5967 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5968 int i; 5969 5970 /* salt away the number of multicast addresses assigned 5971 * to this VF for later use to restore when the PF multi cast 5972 * list changes 5973 */ 5974 vf_data->num_vf_mc_hashes = n; 5975 5976 /* only up to 30 hash values supported */ 5977 if (n > 30) 5978 n = 30; 5979 5980 /* store the hashes for later use */ 5981 for (i = 0; i < n; i++) 5982 vf_data->vf_mc_hashes[i] = hash_list[i]; 5983 5984 /* Flush and reset the mta with the new values */ 5985 igb_set_rx_mode(adapter->netdev); 5986 5987 return 0; 5988 } 5989 5990 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5991 { 5992 struct e1000_hw *hw = &adapter->hw; 5993 struct vf_data_storage *vf_data; 5994 int i, j; 5995 5996 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5997 u32 vmolr = rd32(E1000_VMOLR(i)); 5998 5999 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6000 6001 vf_data = &adapter->vf_data[i]; 6002 6003 if ((vf_data->num_vf_mc_hashes > 30) || 6004 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6005 vmolr |= E1000_VMOLR_MPME; 6006 } else if (vf_data->num_vf_mc_hashes) { 6007 vmolr |= E1000_VMOLR_ROMPE; 6008 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6009 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6010 } 6011 wr32(E1000_VMOLR(i), vmolr); 6012 } 6013 } 6014 6015 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6016 { 6017 struct e1000_hw *hw = &adapter->hw; 6018 u32 pool_mask, vlvf_mask, i; 6019 6020 /* create mask for VF and other pools */ 6021 pool_mask = E1000_VLVF_POOLSEL_MASK; 6022 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6023 6024 /* drop PF from pool bits */ 6025 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6026 adapter->vfs_allocated_count); 6027 6028 /* Find the vlan filter for this id */ 6029 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6030 u32 vlvf = rd32(E1000_VLVF(i)); 6031 u32 vfta_mask, vid, vfta; 6032 6033 /* remove the vf from the pool */ 6034 if (!(vlvf & vlvf_mask)) 6035 continue; 6036 6037 /* clear out bit from VLVF */ 6038 vlvf ^= vlvf_mask; 6039 6040 /* if other pools are present, just remove ourselves */ 6041 if (vlvf & pool_mask) 6042 goto update_vlvfb; 6043 6044 /* if PF is present, leave VFTA */ 6045 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6046 goto update_vlvf; 6047 6048 vid = vlvf & E1000_VLVF_VLANID_MASK; 6049 vfta_mask = BIT(vid % 32); 6050 6051 /* clear bit from VFTA */ 6052 vfta = adapter->shadow_vfta[vid / 32]; 6053 if (vfta & vfta_mask) 6054 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6055 update_vlvf: 6056 /* clear pool selection enable */ 6057 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6058 vlvf &= E1000_VLVF_POOLSEL_MASK; 6059 else 6060 vlvf = 0; 6061 update_vlvfb: 6062 /* clear pool bits */ 6063 wr32(E1000_VLVF(i), vlvf); 6064 } 6065 } 6066 6067 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6068 { 6069 u32 vlvf; 6070 int idx; 6071 6072 /* short cut the special case */ 6073 if (vlan == 0) 6074 return 0; 6075 6076 /* Search for the VLAN id in the VLVF entries */ 6077 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6078 vlvf = rd32(E1000_VLVF(idx)); 6079 if ((vlvf & VLAN_VID_MASK) == vlan) 6080 break; 6081 } 6082 6083 return idx; 6084 } 6085 6086 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6087 { 6088 struct e1000_hw *hw = &adapter->hw; 6089 u32 bits, pf_id; 6090 int idx; 6091 6092 idx = igb_find_vlvf_entry(hw, vid); 6093 if (!idx) 6094 return; 6095 6096 /* See if any other pools are set for this VLAN filter 6097 * entry other than the PF. 6098 */ 6099 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6100 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6101 bits &= rd32(E1000_VLVF(idx)); 6102 6103 /* Disable the filter so this falls into the default pool. */ 6104 if (!bits) { 6105 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6106 wr32(E1000_VLVF(idx), BIT(pf_id)); 6107 else 6108 wr32(E1000_VLVF(idx), 0); 6109 } 6110 } 6111 6112 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6113 bool add, u32 vf) 6114 { 6115 int pf_id = adapter->vfs_allocated_count; 6116 struct e1000_hw *hw = &adapter->hw; 6117 int err; 6118 6119 /* If VLAN overlaps with one the PF is currently monitoring make 6120 * sure that we are able to allocate a VLVF entry. This may be 6121 * redundant but it guarantees PF will maintain visibility to 6122 * the VLAN. 6123 */ 6124 if (add && test_bit(vid, adapter->active_vlans)) { 6125 err = igb_vfta_set(hw, vid, pf_id, true, false); 6126 if (err) 6127 return err; 6128 } 6129 6130 err = igb_vfta_set(hw, vid, vf, add, false); 6131 6132 if (add && !err) 6133 return err; 6134 6135 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6136 * we may need to drop the PF pool bit in order to allow us to free 6137 * up the VLVF resources. 6138 */ 6139 if (test_bit(vid, adapter->active_vlans) || 6140 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6141 igb_update_pf_vlvf(adapter, vid); 6142 6143 return err; 6144 } 6145 6146 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6147 { 6148 struct e1000_hw *hw = &adapter->hw; 6149 6150 if (vid) 6151 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6152 else 6153 wr32(E1000_VMVIR(vf), 0); 6154 } 6155 6156 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6157 u16 vlan, u8 qos) 6158 { 6159 int err; 6160 6161 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6162 if (err) 6163 return err; 6164 6165 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6166 igb_set_vmolr(adapter, vf, !vlan); 6167 6168 /* revoke access to previous VLAN */ 6169 if (vlan != adapter->vf_data[vf].pf_vlan) 6170 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6171 false, vf); 6172 6173 adapter->vf_data[vf].pf_vlan = vlan; 6174 adapter->vf_data[vf].pf_qos = qos; 6175 igb_set_vf_vlan_strip(adapter, vf, true); 6176 dev_info(&adapter->pdev->dev, 6177 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6178 if (test_bit(__IGB_DOWN, &adapter->state)) { 6179 dev_warn(&adapter->pdev->dev, 6180 "The VF VLAN has been set, but the PF device is not up.\n"); 6181 dev_warn(&adapter->pdev->dev, 6182 "Bring the PF device up before attempting to use the VF device.\n"); 6183 } 6184 6185 return err; 6186 } 6187 6188 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6189 { 6190 /* Restore tagless access via VLAN 0 */ 6191 igb_set_vf_vlan(adapter, 0, true, vf); 6192 6193 igb_set_vmvir(adapter, 0, vf); 6194 igb_set_vmolr(adapter, vf, true); 6195 6196 /* Remove any PF assigned VLAN */ 6197 if (adapter->vf_data[vf].pf_vlan) 6198 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6199 false, vf); 6200 6201 adapter->vf_data[vf].pf_vlan = 0; 6202 adapter->vf_data[vf].pf_qos = 0; 6203 igb_set_vf_vlan_strip(adapter, vf, false); 6204 6205 return 0; 6206 } 6207 6208 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 6209 int vf, u16 vlan, u8 qos) 6210 { 6211 struct igb_adapter *adapter = netdev_priv(netdev); 6212 6213 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6214 return -EINVAL; 6215 6216 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6217 igb_disable_port_vlan(adapter, vf); 6218 } 6219 6220 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6221 { 6222 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6223 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6224 int ret; 6225 6226 if (adapter->vf_data[vf].pf_vlan) 6227 return -1; 6228 6229 /* VLAN 0 is a special case, don't allow it to be removed */ 6230 if (!vid && !add) 6231 return 0; 6232 6233 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6234 if (!ret) 6235 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6236 return ret; 6237 } 6238 6239 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6240 { 6241 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6242 6243 /* clear flags - except flag that indicates PF has set the MAC */ 6244 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6245 vf_data->last_nack = jiffies; 6246 6247 /* reset vlans for device */ 6248 igb_clear_vf_vfta(adapter, vf); 6249 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6250 igb_set_vmvir(adapter, vf_data->pf_vlan | 6251 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6252 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6253 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6254 6255 /* reset multicast table array for vf */ 6256 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6257 6258 /* Flush and reset the mta with the new values */ 6259 igb_set_rx_mode(adapter->netdev); 6260 } 6261 6262 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6263 { 6264 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6265 6266 /* clear mac address as we were hotplug removed/added */ 6267 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6268 eth_zero_addr(vf_mac); 6269 6270 /* process remaining reset events */ 6271 igb_vf_reset(adapter, vf); 6272 } 6273 6274 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6275 { 6276 struct e1000_hw *hw = &adapter->hw; 6277 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6278 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6279 u32 reg, msgbuf[3]; 6280 u8 *addr = (u8 *)(&msgbuf[1]); 6281 6282 /* process all the same items cleared in a function level reset */ 6283 igb_vf_reset(adapter, vf); 6284 6285 /* set vf mac address */ 6286 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6287 6288 /* enable transmit and receive for vf */ 6289 reg = rd32(E1000_VFTE); 6290 wr32(E1000_VFTE, reg | BIT(vf)); 6291 reg = rd32(E1000_VFRE); 6292 wr32(E1000_VFRE, reg | BIT(vf)); 6293 6294 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6295 6296 /* reply to reset with ack and vf mac address */ 6297 if (!is_zero_ether_addr(vf_mac)) { 6298 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6299 memcpy(addr, vf_mac, ETH_ALEN); 6300 } else { 6301 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6302 } 6303 igb_write_mbx(hw, msgbuf, 3, vf); 6304 } 6305 6306 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6307 { 6308 /* The VF MAC Address is stored in a packed array of bytes 6309 * starting at the second 32 bit word of the msg array 6310 */ 6311 unsigned char *addr = (char *)&msg[1]; 6312 int err = -1; 6313 6314 if (is_valid_ether_addr(addr)) 6315 err = igb_set_vf_mac(adapter, vf, addr); 6316 6317 return err; 6318 } 6319 6320 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6321 { 6322 struct e1000_hw *hw = &adapter->hw; 6323 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6324 u32 msg = E1000_VT_MSGTYPE_NACK; 6325 6326 /* if device isn't clear to send it shouldn't be reading either */ 6327 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6328 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6329 igb_write_mbx(hw, &msg, 1, vf); 6330 vf_data->last_nack = jiffies; 6331 } 6332 } 6333 6334 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6335 { 6336 struct pci_dev *pdev = adapter->pdev; 6337 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6338 struct e1000_hw *hw = &adapter->hw; 6339 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6340 s32 retval; 6341 6342 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6343 6344 if (retval) { 6345 /* if receive failed revoke VF CTS stats and restart init */ 6346 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6347 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6348 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6349 return; 6350 goto out; 6351 } 6352 6353 /* this is a message we already processed, do nothing */ 6354 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6355 return; 6356 6357 /* until the vf completes a reset it should not be 6358 * allowed to start any configuration. 6359 */ 6360 if (msgbuf[0] == E1000_VF_RESET) { 6361 igb_vf_reset_msg(adapter, vf); 6362 return; 6363 } 6364 6365 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6366 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6367 return; 6368 retval = -1; 6369 goto out; 6370 } 6371 6372 switch ((msgbuf[0] & 0xFFFF)) { 6373 case E1000_VF_SET_MAC_ADDR: 6374 retval = -EINVAL; 6375 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6376 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6377 else 6378 dev_warn(&pdev->dev, 6379 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6380 vf); 6381 break; 6382 case E1000_VF_SET_PROMISC: 6383 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6384 break; 6385 case E1000_VF_SET_MULTICAST: 6386 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6387 break; 6388 case E1000_VF_SET_LPE: 6389 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6390 break; 6391 case E1000_VF_SET_VLAN: 6392 retval = -1; 6393 if (vf_data->pf_vlan) 6394 dev_warn(&pdev->dev, 6395 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6396 vf); 6397 else 6398 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6399 break; 6400 default: 6401 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6402 retval = -1; 6403 break; 6404 } 6405 6406 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6407 out: 6408 /* notify the VF of the results of what it sent us */ 6409 if (retval) 6410 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6411 else 6412 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6413 6414 igb_write_mbx(hw, msgbuf, 1, vf); 6415 } 6416 6417 static void igb_msg_task(struct igb_adapter *adapter) 6418 { 6419 struct e1000_hw *hw = &adapter->hw; 6420 u32 vf; 6421 6422 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6423 /* process any reset requests */ 6424 if (!igb_check_for_rst(hw, vf)) 6425 igb_vf_reset_event(adapter, vf); 6426 6427 /* process any messages pending */ 6428 if (!igb_check_for_msg(hw, vf)) 6429 igb_rcv_msg_from_vf(adapter, vf); 6430 6431 /* process any acks */ 6432 if (!igb_check_for_ack(hw, vf)) 6433 igb_rcv_ack_from_vf(adapter, vf); 6434 } 6435 } 6436 6437 /** 6438 * igb_set_uta - Set unicast filter table address 6439 * @adapter: board private structure 6440 * @set: boolean indicating if we are setting or clearing bits 6441 * 6442 * The unicast table address is a register array of 32-bit registers. 6443 * The table is meant to be used in a way similar to how the MTA is used 6444 * however due to certain limitations in the hardware it is necessary to 6445 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6446 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6447 **/ 6448 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6449 { 6450 struct e1000_hw *hw = &adapter->hw; 6451 u32 uta = set ? ~0 : 0; 6452 int i; 6453 6454 /* we only need to do this if VMDq is enabled */ 6455 if (!adapter->vfs_allocated_count) 6456 return; 6457 6458 for (i = hw->mac.uta_reg_count; i--;) 6459 array_wr32(E1000_UTA, i, uta); 6460 } 6461 6462 /** 6463 * igb_intr_msi - Interrupt Handler 6464 * @irq: interrupt number 6465 * @data: pointer to a network interface device structure 6466 **/ 6467 static irqreturn_t igb_intr_msi(int irq, void *data) 6468 { 6469 struct igb_adapter *adapter = data; 6470 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6471 struct e1000_hw *hw = &adapter->hw; 6472 /* read ICR disables interrupts using IAM */ 6473 u32 icr = rd32(E1000_ICR); 6474 6475 igb_write_itr(q_vector); 6476 6477 if (icr & E1000_ICR_DRSTA) 6478 schedule_work(&adapter->reset_task); 6479 6480 if (icr & E1000_ICR_DOUTSYNC) { 6481 /* HW is reporting DMA is out of sync */ 6482 adapter->stats.doosync++; 6483 } 6484 6485 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6486 hw->mac.get_link_status = 1; 6487 if (!test_bit(__IGB_DOWN, &adapter->state)) 6488 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6489 } 6490 6491 if (icr & E1000_ICR_TS) 6492 igb_tsync_interrupt(adapter); 6493 6494 napi_schedule(&q_vector->napi); 6495 6496 return IRQ_HANDLED; 6497 } 6498 6499 /** 6500 * igb_intr - Legacy Interrupt Handler 6501 * @irq: interrupt number 6502 * @data: pointer to a network interface device structure 6503 **/ 6504 static irqreturn_t igb_intr(int irq, void *data) 6505 { 6506 struct igb_adapter *adapter = data; 6507 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6508 struct e1000_hw *hw = &adapter->hw; 6509 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6510 * need for the IMC write 6511 */ 6512 u32 icr = rd32(E1000_ICR); 6513 6514 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6515 * not set, then the adapter didn't send an interrupt 6516 */ 6517 if (!(icr & E1000_ICR_INT_ASSERTED)) 6518 return IRQ_NONE; 6519 6520 igb_write_itr(q_vector); 6521 6522 if (icr & E1000_ICR_DRSTA) 6523 schedule_work(&adapter->reset_task); 6524 6525 if (icr & E1000_ICR_DOUTSYNC) { 6526 /* HW is reporting DMA is out of sync */ 6527 adapter->stats.doosync++; 6528 } 6529 6530 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6531 hw->mac.get_link_status = 1; 6532 /* guard against interrupt when we're going down */ 6533 if (!test_bit(__IGB_DOWN, &adapter->state)) 6534 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6535 } 6536 6537 if (icr & E1000_ICR_TS) 6538 igb_tsync_interrupt(adapter); 6539 6540 napi_schedule(&q_vector->napi); 6541 6542 return IRQ_HANDLED; 6543 } 6544 6545 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6546 { 6547 struct igb_adapter *adapter = q_vector->adapter; 6548 struct e1000_hw *hw = &adapter->hw; 6549 6550 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6551 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6552 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6553 igb_set_itr(q_vector); 6554 else 6555 igb_update_ring_itr(q_vector); 6556 } 6557 6558 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6559 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6560 wr32(E1000_EIMS, q_vector->eims_value); 6561 else 6562 igb_irq_enable(adapter); 6563 } 6564 } 6565 6566 /** 6567 * igb_poll - NAPI Rx polling callback 6568 * @napi: napi polling structure 6569 * @budget: count of how many packets we should handle 6570 **/ 6571 static int igb_poll(struct napi_struct *napi, int budget) 6572 { 6573 struct igb_q_vector *q_vector = container_of(napi, 6574 struct igb_q_vector, 6575 napi); 6576 bool clean_complete = true; 6577 int work_done = 0; 6578 6579 #ifdef CONFIG_IGB_DCA 6580 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6581 igb_update_dca(q_vector); 6582 #endif 6583 if (q_vector->tx.ring) 6584 clean_complete = igb_clean_tx_irq(q_vector, budget); 6585 6586 if (q_vector->rx.ring) { 6587 int cleaned = igb_clean_rx_irq(q_vector, budget); 6588 6589 work_done += cleaned; 6590 if (cleaned >= budget) 6591 clean_complete = false; 6592 } 6593 6594 /* If all work not completed, return budget and keep polling */ 6595 if (!clean_complete) 6596 return budget; 6597 6598 /* If not enough Rx work done, exit the polling mode */ 6599 napi_complete_done(napi, work_done); 6600 igb_ring_irq_enable(q_vector); 6601 6602 return 0; 6603 } 6604 6605 /** 6606 * igb_clean_tx_irq - Reclaim resources after transmit completes 6607 * @q_vector: pointer to q_vector containing needed info 6608 * @napi_budget: Used to determine if we are in netpoll 6609 * 6610 * returns true if ring is completely cleaned 6611 **/ 6612 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6613 { 6614 struct igb_adapter *adapter = q_vector->adapter; 6615 struct igb_ring *tx_ring = q_vector->tx.ring; 6616 struct igb_tx_buffer *tx_buffer; 6617 union e1000_adv_tx_desc *tx_desc; 6618 unsigned int total_bytes = 0, total_packets = 0; 6619 unsigned int budget = q_vector->tx.work_limit; 6620 unsigned int i = tx_ring->next_to_clean; 6621 6622 if (test_bit(__IGB_DOWN, &adapter->state)) 6623 return true; 6624 6625 tx_buffer = &tx_ring->tx_buffer_info[i]; 6626 tx_desc = IGB_TX_DESC(tx_ring, i); 6627 i -= tx_ring->count; 6628 6629 do { 6630 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6631 6632 /* if next_to_watch is not set then there is no work pending */ 6633 if (!eop_desc) 6634 break; 6635 6636 /* prevent any other reads prior to eop_desc */ 6637 read_barrier_depends(); 6638 6639 /* if DD is not set pending work has not been completed */ 6640 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6641 break; 6642 6643 /* clear next_to_watch to prevent false hangs */ 6644 tx_buffer->next_to_watch = NULL; 6645 6646 /* update the statistics for this packet */ 6647 total_bytes += tx_buffer->bytecount; 6648 total_packets += tx_buffer->gso_segs; 6649 6650 /* free the skb */ 6651 napi_consume_skb(tx_buffer->skb, napi_budget); 6652 6653 /* unmap skb header data */ 6654 dma_unmap_single(tx_ring->dev, 6655 dma_unmap_addr(tx_buffer, dma), 6656 dma_unmap_len(tx_buffer, len), 6657 DMA_TO_DEVICE); 6658 6659 /* clear tx_buffer data */ 6660 tx_buffer->skb = NULL; 6661 dma_unmap_len_set(tx_buffer, len, 0); 6662 6663 /* clear last DMA location and unmap remaining buffers */ 6664 while (tx_desc != eop_desc) { 6665 tx_buffer++; 6666 tx_desc++; 6667 i++; 6668 if (unlikely(!i)) { 6669 i -= tx_ring->count; 6670 tx_buffer = tx_ring->tx_buffer_info; 6671 tx_desc = IGB_TX_DESC(tx_ring, 0); 6672 } 6673 6674 /* unmap any remaining paged data */ 6675 if (dma_unmap_len(tx_buffer, len)) { 6676 dma_unmap_page(tx_ring->dev, 6677 dma_unmap_addr(tx_buffer, dma), 6678 dma_unmap_len(tx_buffer, len), 6679 DMA_TO_DEVICE); 6680 dma_unmap_len_set(tx_buffer, len, 0); 6681 } 6682 } 6683 6684 /* move us one more past the eop_desc for start of next pkt */ 6685 tx_buffer++; 6686 tx_desc++; 6687 i++; 6688 if (unlikely(!i)) { 6689 i -= tx_ring->count; 6690 tx_buffer = tx_ring->tx_buffer_info; 6691 tx_desc = IGB_TX_DESC(tx_ring, 0); 6692 } 6693 6694 /* issue prefetch for next Tx descriptor */ 6695 prefetch(tx_desc); 6696 6697 /* update budget accounting */ 6698 budget--; 6699 } while (likely(budget)); 6700 6701 netdev_tx_completed_queue(txring_txq(tx_ring), 6702 total_packets, total_bytes); 6703 i += tx_ring->count; 6704 tx_ring->next_to_clean = i; 6705 u64_stats_update_begin(&tx_ring->tx_syncp); 6706 tx_ring->tx_stats.bytes += total_bytes; 6707 tx_ring->tx_stats.packets += total_packets; 6708 u64_stats_update_end(&tx_ring->tx_syncp); 6709 q_vector->tx.total_bytes += total_bytes; 6710 q_vector->tx.total_packets += total_packets; 6711 6712 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6713 struct e1000_hw *hw = &adapter->hw; 6714 6715 /* Detect a transmit hang in hardware, this serializes the 6716 * check with the clearing of time_stamp and movement of i 6717 */ 6718 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6719 if (tx_buffer->next_to_watch && 6720 time_after(jiffies, tx_buffer->time_stamp + 6721 (adapter->tx_timeout_factor * HZ)) && 6722 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6723 6724 /* detected Tx unit hang */ 6725 dev_err(tx_ring->dev, 6726 "Detected Tx Unit Hang\n" 6727 " Tx Queue <%d>\n" 6728 " TDH <%x>\n" 6729 " TDT <%x>\n" 6730 " next_to_use <%x>\n" 6731 " next_to_clean <%x>\n" 6732 "buffer_info[next_to_clean]\n" 6733 " time_stamp <%lx>\n" 6734 " next_to_watch <%p>\n" 6735 " jiffies <%lx>\n" 6736 " desc.status <%x>\n", 6737 tx_ring->queue_index, 6738 rd32(E1000_TDH(tx_ring->reg_idx)), 6739 readl(tx_ring->tail), 6740 tx_ring->next_to_use, 6741 tx_ring->next_to_clean, 6742 tx_buffer->time_stamp, 6743 tx_buffer->next_to_watch, 6744 jiffies, 6745 tx_buffer->next_to_watch->wb.status); 6746 netif_stop_subqueue(tx_ring->netdev, 6747 tx_ring->queue_index); 6748 6749 /* we are about to reset, no point in enabling stuff */ 6750 return true; 6751 } 6752 } 6753 6754 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6755 if (unlikely(total_packets && 6756 netif_carrier_ok(tx_ring->netdev) && 6757 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6758 /* Make sure that anybody stopping the queue after this 6759 * sees the new next_to_clean. 6760 */ 6761 smp_mb(); 6762 if (__netif_subqueue_stopped(tx_ring->netdev, 6763 tx_ring->queue_index) && 6764 !(test_bit(__IGB_DOWN, &adapter->state))) { 6765 netif_wake_subqueue(tx_ring->netdev, 6766 tx_ring->queue_index); 6767 6768 u64_stats_update_begin(&tx_ring->tx_syncp); 6769 tx_ring->tx_stats.restart_queue++; 6770 u64_stats_update_end(&tx_ring->tx_syncp); 6771 } 6772 } 6773 6774 return !!budget; 6775 } 6776 6777 /** 6778 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6779 * @rx_ring: rx descriptor ring to store buffers on 6780 * @old_buff: donor buffer to have page reused 6781 * 6782 * Synchronizes page for reuse by the adapter 6783 **/ 6784 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6785 struct igb_rx_buffer *old_buff) 6786 { 6787 struct igb_rx_buffer *new_buff; 6788 u16 nta = rx_ring->next_to_alloc; 6789 6790 new_buff = &rx_ring->rx_buffer_info[nta]; 6791 6792 /* update, and store next to alloc */ 6793 nta++; 6794 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6795 6796 /* transfer page from old buffer to new buffer */ 6797 *new_buff = *old_buff; 6798 6799 /* sync the buffer for use by the device */ 6800 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6801 old_buff->page_offset, 6802 IGB_RX_BUFSZ, 6803 DMA_FROM_DEVICE); 6804 } 6805 6806 static inline bool igb_page_is_reserved(struct page *page) 6807 { 6808 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 6809 } 6810 6811 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6812 struct page *page, 6813 unsigned int truesize) 6814 { 6815 /* avoid re-using remote pages */ 6816 if (unlikely(igb_page_is_reserved(page))) 6817 return false; 6818 6819 #if (PAGE_SIZE < 8192) 6820 /* if we are only owner of page we can reuse it */ 6821 if (unlikely(page_count(page) != 1)) 6822 return false; 6823 6824 /* flip page offset to other buffer */ 6825 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6826 #else 6827 /* move offset up to the next cache line */ 6828 rx_buffer->page_offset += truesize; 6829 6830 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6831 return false; 6832 #endif 6833 6834 /* Even if we own the page, we are not allowed to use atomic_set() 6835 * This would break get_page_unless_zero() users. 6836 */ 6837 page_ref_inc(page); 6838 6839 return true; 6840 } 6841 6842 /** 6843 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6844 * @rx_ring: rx descriptor ring to transact packets on 6845 * @rx_buffer: buffer containing page to add 6846 * @rx_desc: descriptor containing length of buffer written by hardware 6847 * @skb: sk_buff to place the data into 6848 * 6849 * This function will add the data contained in rx_buffer->page to the skb. 6850 * This is done either through a direct copy if the data in the buffer is 6851 * less than the skb header size, otherwise it will just attach the page as 6852 * a frag to the skb. 6853 * 6854 * The function will then update the page offset if necessary and return 6855 * true if the buffer can be reused by the adapter. 6856 **/ 6857 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6858 struct igb_rx_buffer *rx_buffer, 6859 unsigned int size, 6860 union e1000_adv_rx_desc *rx_desc, 6861 struct sk_buff *skb) 6862 { 6863 struct page *page = rx_buffer->page; 6864 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6865 #if (PAGE_SIZE < 8192) 6866 unsigned int truesize = IGB_RX_BUFSZ; 6867 #else 6868 unsigned int truesize = SKB_DATA_ALIGN(size); 6869 #endif 6870 unsigned int pull_len; 6871 6872 if (unlikely(skb_is_nonlinear(skb))) 6873 goto add_tail_frag; 6874 6875 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 6876 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6877 va += IGB_TS_HDR_LEN; 6878 size -= IGB_TS_HDR_LEN; 6879 } 6880 6881 if (likely(size <= IGB_RX_HDR_LEN)) { 6882 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6883 6884 /* page is not reserved, we can reuse buffer as-is */ 6885 if (likely(!igb_page_is_reserved(page))) 6886 return true; 6887 6888 /* this page cannot be reused so discard it */ 6889 __free_page(page); 6890 return false; 6891 } 6892 6893 /* we need the header to contain the greater of either ETH_HLEN or 6894 * 60 bytes if the skb->len is less than 60 for skb_pad. 6895 */ 6896 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6897 6898 /* align pull length to size of long to optimize memcpy performance */ 6899 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 6900 6901 /* update all of the pointers */ 6902 va += pull_len; 6903 size -= pull_len; 6904 6905 add_tail_frag: 6906 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6907 (unsigned long)va & ~PAGE_MASK, size, truesize); 6908 6909 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6910 } 6911 6912 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6913 union e1000_adv_rx_desc *rx_desc, 6914 struct sk_buff *skb) 6915 { 6916 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6917 struct igb_rx_buffer *rx_buffer; 6918 struct page *page; 6919 6920 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6921 page = rx_buffer->page; 6922 prefetchw(page); 6923 6924 if (likely(!skb)) { 6925 void *page_addr = page_address(page) + 6926 rx_buffer->page_offset; 6927 6928 /* prefetch first cache line of first page */ 6929 prefetch(page_addr); 6930 #if L1_CACHE_BYTES < 128 6931 prefetch(page_addr + L1_CACHE_BYTES); 6932 #endif 6933 6934 /* allocate a skb to store the frags */ 6935 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6936 if (unlikely(!skb)) { 6937 rx_ring->rx_stats.alloc_failed++; 6938 return NULL; 6939 } 6940 6941 /* we will be copying header into skb->data in 6942 * pskb_may_pull so it is in our interest to prefetch 6943 * it now to avoid a possible cache miss 6944 */ 6945 prefetchw(skb->data); 6946 } 6947 6948 /* we are reusing so sync this buffer for CPU use */ 6949 dma_sync_single_range_for_cpu(rx_ring->dev, 6950 rx_buffer->dma, 6951 rx_buffer->page_offset, 6952 size, 6953 DMA_FROM_DEVICE); 6954 6955 /* pull page into skb */ 6956 if (igb_add_rx_frag(rx_ring, rx_buffer, size, rx_desc, skb)) { 6957 /* hand second half of page back to the ring */ 6958 igb_reuse_rx_page(rx_ring, rx_buffer); 6959 } else { 6960 /* we are not reusing the buffer so unmap it */ 6961 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6962 PAGE_SIZE, DMA_FROM_DEVICE); 6963 } 6964 6965 /* clear contents of rx_buffer */ 6966 rx_buffer->page = NULL; 6967 6968 return skb; 6969 } 6970 6971 static inline void igb_rx_checksum(struct igb_ring *ring, 6972 union e1000_adv_rx_desc *rx_desc, 6973 struct sk_buff *skb) 6974 { 6975 skb_checksum_none_assert(skb); 6976 6977 /* Ignore Checksum bit is set */ 6978 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6979 return; 6980 6981 /* Rx checksum disabled via ethtool */ 6982 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6983 return; 6984 6985 /* TCP/UDP checksum error bit is set */ 6986 if (igb_test_staterr(rx_desc, 6987 E1000_RXDEXT_STATERR_TCPE | 6988 E1000_RXDEXT_STATERR_IPE)) { 6989 /* work around errata with sctp packets where the TCPE aka 6990 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6991 * packets, (aka let the stack check the crc32c) 6992 */ 6993 if (!((skb->len == 60) && 6994 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6995 u64_stats_update_begin(&ring->rx_syncp); 6996 ring->rx_stats.csum_err++; 6997 u64_stats_update_end(&ring->rx_syncp); 6998 } 6999 /* let the stack verify checksum errors */ 7000 return; 7001 } 7002 /* It must be a TCP or UDP packet with a valid checksum */ 7003 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7004 E1000_RXD_STAT_UDPCS)) 7005 skb->ip_summed = CHECKSUM_UNNECESSARY; 7006 7007 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7008 le32_to_cpu(rx_desc->wb.upper.status_error)); 7009 } 7010 7011 static inline void igb_rx_hash(struct igb_ring *ring, 7012 union e1000_adv_rx_desc *rx_desc, 7013 struct sk_buff *skb) 7014 { 7015 if (ring->netdev->features & NETIF_F_RXHASH) 7016 skb_set_hash(skb, 7017 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7018 PKT_HASH_TYPE_L3); 7019 } 7020 7021 /** 7022 * igb_is_non_eop - process handling of non-EOP buffers 7023 * @rx_ring: Rx ring being processed 7024 * @rx_desc: Rx descriptor for current buffer 7025 * @skb: current socket buffer containing buffer in progress 7026 * 7027 * This function updates next to clean. If the buffer is an EOP buffer 7028 * this function exits returning false, otherwise it will place the 7029 * sk_buff in the next buffer to be chained and return true indicating 7030 * that this is in fact a non-EOP buffer. 7031 **/ 7032 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7033 union e1000_adv_rx_desc *rx_desc) 7034 { 7035 u32 ntc = rx_ring->next_to_clean + 1; 7036 7037 /* fetch, update, and store next to clean */ 7038 ntc = (ntc < rx_ring->count) ? ntc : 0; 7039 rx_ring->next_to_clean = ntc; 7040 7041 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7042 7043 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7044 return false; 7045 7046 return true; 7047 } 7048 7049 /** 7050 * igb_cleanup_headers - Correct corrupted or empty headers 7051 * @rx_ring: rx descriptor ring packet is being transacted on 7052 * @rx_desc: pointer to the EOP Rx descriptor 7053 * @skb: pointer to current skb being fixed 7054 * 7055 * Address the case where we are pulling data in on pages only 7056 * and as such no data is present in the skb header. 7057 * 7058 * In addition if skb is not at least 60 bytes we need to pad it so that 7059 * it is large enough to qualify as a valid Ethernet frame. 7060 * 7061 * Returns true if an error was encountered and skb was freed. 7062 **/ 7063 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7064 union e1000_adv_rx_desc *rx_desc, 7065 struct sk_buff *skb) 7066 { 7067 if (unlikely((igb_test_staterr(rx_desc, 7068 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7069 struct net_device *netdev = rx_ring->netdev; 7070 if (!(netdev->features & NETIF_F_RXALL)) { 7071 dev_kfree_skb_any(skb); 7072 return true; 7073 } 7074 } 7075 7076 /* if eth_skb_pad returns an error the skb was freed */ 7077 if (eth_skb_pad(skb)) 7078 return true; 7079 7080 return false; 7081 } 7082 7083 /** 7084 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7085 * @rx_ring: rx descriptor ring packet is being transacted on 7086 * @rx_desc: pointer to the EOP Rx descriptor 7087 * @skb: pointer to current skb being populated 7088 * 7089 * This function checks the ring, descriptor, and packet information in 7090 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7091 * other fields within the skb. 7092 **/ 7093 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7094 union e1000_adv_rx_desc *rx_desc, 7095 struct sk_buff *skb) 7096 { 7097 struct net_device *dev = rx_ring->netdev; 7098 7099 igb_rx_hash(rx_ring, rx_desc, skb); 7100 7101 igb_rx_checksum(rx_ring, rx_desc, skb); 7102 7103 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7104 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7105 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7106 7107 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7108 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7109 u16 vid; 7110 7111 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7112 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7113 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7114 else 7115 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7116 7117 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7118 } 7119 7120 skb_record_rx_queue(skb, rx_ring->queue_index); 7121 7122 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7123 } 7124 7125 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7126 { 7127 struct igb_ring *rx_ring = q_vector->rx.ring; 7128 struct sk_buff *skb = rx_ring->skb; 7129 unsigned int total_bytes = 0, total_packets = 0; 7130 u16 cleaned_count = igb_desc_unused(rx_ring); 7131 7132 while (likely(total_packets < budget)) { 7133 union e1000_adv_rx_desc *rx_desc; 7134 7135 /* return some buffers to hardware, one at a time is too slow */ 7136 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7137 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7138 cleaned_count = 0; 7139 } 7140 7141 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7142 7143 if (!rx_desc->wb.upper.status_error) 7144 break; 7145 7146 /* This memory barrier is needed to keep us from reading 7147 * any other fields out of the rx_desc until we know the 7148 * descriptor has been written back 7149 */ 7150 dma_rmb(); 7151 7152 /* retrieve a buffer from the ring */ 7153 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7154 7155 /* exit if we failed to retrieve a buffer */ 7156 if (!skb) 7157 break; 7158 7159 cleaned_count++; 7160 7161 /* fetch next buffer in frame if non-eop */ 7162 if (igb_is_non_eop(rx_ring, rx_desc)) 7163 continue; 7164 7165 /* verify the packet layout is correct */ 7166 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7167 skb = NULL; 7168 continue; 7169 } 7170 7171 /* probably a little skewed due to removing CRC */ 7172 total_bytes += skb->len; 7173 7174 /* populate checksum, timestamp, VLAN, and protocol */ 7175 igb_process_skb_fields(rx_ring, rx_desc, skb); 7176 7177 napi_gro_receive(&q_vector->napi, skb); 7178 7179 /* reset skb pointer */ 7180 skb = NULL; 7181 7182 /* update budget accounting */ 7183 total_packets++; 7184 } 7185 7186 /* place incomplete frames back on ring for completion */ 7187 rx_ring->skb = skb; 7188 7189 u64_stats_update_begin(&rx_ring->rx_syncp); 7190 rx_ring->rx_stats.packets += total_packets; 7191 rx_ring->rx_stats.bytes += total_bytes; 7192 u64_stats_update_end(&rx_ring->rx_syncp); 7193 q_vector->rx.total_packets += total_packets; 7194 q_vector->rx.total_bytes += total_bytes; 7195 7196 if (cleaned_count) 7197 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7198 7199 return total_packets; 7200 } 7201 7202 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7203 struct igb_rx_buffer *bi) 7204 { 7205 struct page *page = bi->page; 7206 dma_addr_t dma; 7207 7208 /* since we are recycling buffers we should seldom need to alloc */ 7209 if (likely(page)) 7210 return true; 7211 7212 /* alloc new page for storage */ 7213 page = dev_alloc_page(); 7214 if (unlikely(!page)) { 7215 rx_ring->rx_stats.alloc_failed++; 7216 return false; 7217 } 7218 7219 /* map page for use */ 7220 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7221 7222 /* if mapping failed free memory back to system since 7223 * there isn't much point in holding memory we can't use 7224 */ 7225 if (dma_mapping_error(rx_ring->dev, dma)) { 7226 __free_page(page); 7227 7228 rx_ring->rx_stats.alloc_failed++; 7229 return false; 7230 } 7231 7232 bi->dma = dma; 7233 bi->page = page; 7234 bi->page_offset = 0; 7235 7236 return true; 7237 } 7238 7239 /** 7240 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7241 * @adapter: address of board private structure 7242 **/ 7243 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7244 { 7245 union e1000_adv_rx_desc *rx_desc; 7246 struct igb_rx_buffer *bi; 7247 u16 i = rx_ring->next_to_use; 7248 7249 /* nothing to do */ 7250 if (!cleaned_count) 7251 return; 7252 7253 rx_desc = IGB_RX_DESC(rx_ring, i); 7254 bi = &rx_ring->rx_buffer_info[i]; 7255 i -= rx_ring->count; 7256 7257 do { 7258 if (!igb_alloc_mapped_page(rx_ring, bi)) 7259 break; 7260 7261 /* Refresh the desc even if buffer_addrs didn't change 7262 * because each write-back erases this info. 7263 */ 7264 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7265 7266 rx_desc++; 7267 bi++; 7268 i++; 7269 if (unlikely(!i)) { 7270 rx_desc = IGB_RX_DESC(rx_ring, 0); 7271 bi = rx_ring->rx_buffer_info; 7272 i -= rx_ring->count; 7273 } 7274 7275 /* clear the status bits for the next_to_use descriptor */ 7276 rx_desc->wb.upper.status_error = 0; 7277 7278 cleaned_count--; 7279 } while (cleaned_count); 7280 7281 i += rx_ring->count; 7282 7283 if (rx_ring->next_to_use != i) { 7284 /* record the next descriptor to use */ 7285 rx_ring->next_to_use = i; 7286 7287 /* update next to alloc since we have filled the ring */ 7288 rx_ring->next_to_alloc = i; 7289 7290 /* Force memory writes to complete before letting h/w 7291 * know there are new descriptors to fetch. (Only 7292 * applicable for weak-ordered memory model archs, 7293 * such as IA-64). 7294 */ 7295 wmb(); 7296 writel(i, rx_ring->tail); 7297 } 7298 } 7299 7300 /** 7301 * igb_mii_ioctl - 7302 * @netdev: 7303 * @ifreq: 7304 * @cmd: 7305 **/ 7306 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7307 { 7308 struct igb_adapter *adapter = netdev_priv(netdev); 7309 struct mii_ioctl_data *data = if_mii(ifr); 7310 7311 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7312 return -EOPNOTSUPP; 7313 7314 switch (cmd) { 7315 case SIOCGMIIPHY: 7316 data->phy_id = adapter->hw.phy.addr; 7317 break; 7318 case SIOCGMIIREG: 7319 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7320 &data->val_out)) 7321 return -EIO; 7322 break; 7323 case SIOCSMIIREG: 7324 default: 7325 return -EOPNOTSUPP; 7326 } 7327 return 0; 7328 } 7329 7330 /** 7331 * igb_ioctl - 7332 * @netdev: 7333 * @ifreq: 7334 * @cmd: 7335 **/ 7336 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7337 { 7338 switch (cmd) { 7339 case SIOCGMIIPHY: 7340 case SIOCGMIIREG: 7341 case SIOCSMIIREG: 7342 return igb_mii_ioctl(netdev, ifr, cmd); 7343 case SIOCGHWTSTAMP: 7344 return igb_ptp_get_ts_config(netdev, ifr); 7345 case SIOCSHWTSTAMP: 7346 return igb_ptp_set_ts_config(netdev, ifr); 7347 default: 7348 return -EOPNOTSUPP; 7349 } 7350 } 7351 7352 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7353 { 7354 struct igb_adapter *adapter = hw->back; 7355 7356 pci_read_config_word(adapter->pdev, reg, value); 7357 } 7358 7359 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7360 { 7361 struct igb_adapter *adapter = hw->back; 7362 7363 pci_write_config_word(adapter->pdev, reg, *value); 7364 } 7365 7366 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7367 { 7368 struct igb_adapter *adapter = hw->back; 7369 7370 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7371 return -E1000_ERR_CONFIG; 7372 7373 return 0; 7374 } 7375 7376 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7377 { 7378 struct igb_adapter *adapter = hw->back; 7379 7380 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7381 return -E1000_ERR_CONFIG; 7382 7383 return 0; 7384 } 7385 7386 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7387 { 7388 struct igb_adapter *adapter = netdev_priv(netdev); 7389 struct e1000_hw *hw = &adapter->hw; 7390 u32 ctrl, rctl; 7391 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7392 7393 if (enable) { 7394 /* enable VLAN tag insert/strip */ 7395 ctrl = rd32(E1000_CTRL); 7396 ctrl |= E1000_CTRL_VME; 7397 wr32(E1000_CTRL, ctrl); 7398 7399 /* Disable CFI check */ 7400 rctl = rd32(E1000_RCTL); 7401 rctl &= ~E1000_RCTL_CFIEN; 7402 wr32(E1000_RCTL, rctl); 7403 } else { 7404 /* disable VLAN tag insert/strip */ 7405 ctrl = rd32(E1000_CTRL); 7406 ctrl &= ~E1000_CTRL_VME; 7407 wr32(E1000_CTRL, ctrl); 7408 } 7409 7410 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7411 } 7412 7413 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7414 __be16 proto, u16 vid) 7415 { 7416 struct igb_adapter *adapter = netdev_priv(netdev); 7417 struct e1000_hw *hw = &adapter->hw; 7418 int pf_id = adapter->vfs_allocated_count; 7419 7420 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7421 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7422 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7423 7424 set_bit(vid, adapter->active_vlans); 7425 7426 return 0; 7427 } 7428 7429 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7430 __be16 proto, u16 vid) 7431 { 7432 struct igb_adapter *adapter = netdev_priv(netdev); 7433 int pf_id = adapter->vfs_allocated_count; 7434 struct e1000_hw *hw = &adapter->hw; 7435 7436 /* remove VID from filter table */ 7437 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7438 igb_vfta_set(hw, vid, pf_id, false, true); 7439 7440 clear_bit(vid, adapter->active_vlans); 7441 7442 return 0; 7443 } 7444 7445 static void igb_restore_vlan(struct igb_adapter *adapter) 7446 { 7447 u16 vid = 1; 7448 7449 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7450 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7451 7452 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7453 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7454 } 7455 7456 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7457 { 7458 struct pci_dev *pdev = adapter->pdev; 7459 struct e1000_mac_info *mac = &adapter->hw.mac; 7460 7461 mac->autoneg = 0; 7462 7463 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7464 * for the switch() below to work 7465 */ 7466 if ((spd & 1) || (dplx & ~1)) 7467 goto err_inval; 7468 7469 /* Fiber NIC's only allow 1000 gbps Full duplex 7470 * and 100Mbps Full duplex for 100baseFx sfp 7471 */ 7472 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7473 switch (spd + dplx) { 7474 case SPEED_10 + DUPLEX_HALF: 7475 case SPEED_10 + DUPLEX_FULL: 7476 case SPEED_100 + DUPLEX_HALF: 7477 goto err_inval; 7478 default: 7479 break; 7480 } 7481 } 7482 7483 switch (spd + dplx) { 7484 case SPEED_10 + DUPLEX_HALF: 7485 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7486 break; 7487 case SPEED_10 + DUPLEX_FULL: 7488 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7489 break; 7490 case SPEED_100 + DUPLEX_HALF: 7491 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7492 break; 7493 case SPEED_100 + DUPLEX_FULL: 7494 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7495 break; 7496 case SPEED_1000 + DUPLEX_FULL: 7497 mac->autoneg = 1; 7498 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7499 break; 7500 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7501 default: 7502 goto err_inval; 7503 } 7504 7505 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7506 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7507 7508 return 0; 7509 7510 err_inval: 7511 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7512 return -EINVAL; 7513 } 7514 7515 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7516 bool runtime) 7517 { 7518 struct net_device *netdev = pci_get_drvdata(pdev); 7519 struct igb_adapter *adapter = netdev_priv(netdev); 7520 struct e1000_hw *hw = &adapter->hw; 7521 u32 ctrl, rctl, status; 7522 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7523 #ifdef CONFIG_PM 7524 int retval = 0; 7525 #endif 7526 7527 netif_device_detach(netdev); 7528 7529 if (netif_running(netdev)) 7530 __igb_close(netdev, true); 7531 7532 igb_ptp_suspend(adapter); 7533 7534 igb_clear_interrupt_scheme(adapter); 7535 7536 #ifdef CONFIG_PM 7537 retval = pci_save_state(pdev); 7538 if (retval) 7539 return retval; 7540 #endif 7541 7542 status = rd32(E1000_STATUS); 7543 if (status & E1000_STATUS_LU) 7544 wufc &= ~E1000_WUFC_LNKC; 7545 7546 if (wufc) { 7547 igb_setup_rctl(adapter); 7548 igb_set_rx_mode(netdev); 7549 7550 /* turn on all-multi mode if wake on multicast is enabled */ 7551 if (wufc & E1000_WUFC_MC) { 7552 rctl = rd32(E1000_RCTL); 7553 rctl |= E1000_RCTL_MPE; 7554 wr32(E1000_RCTL, rctl); 7555 } 7556 7557 ctrl = rd32(E1000_CTRL); 7558 /* advertise wake from D3Cold */ 7559 #define E1000_CTRL_ADVD3WUC 0x00100000 7560 /* phy power management enable */ 7561 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7562 ctrl |= E1000_CTRL_ADVD3WUC; 7563 wr32(E1000_CTRL, ctrl); 7564 7565 /* Allow time for pending master requests to run */ 7566 igb_disable_pcie_master(hw); 7567 7568 wr32(E1000_WUC, E1000_WUC_PME_EN); 7569 wr32(E1000_WUFC, wufc); 7570 } else { 7571 wr32(E1000_WUC, 0); 7572 wr32(E1000_WUFC, 0); 7573 } 7574 7575 *enable_wake = wufc || adapter->en_mng_pt; 7576 if (!*enable_wake) 7577 igb_power_down_link(adapter); 7578 else 7579 igb_power_up_link(adapter); 7580 7581 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7582 * would have already happened in close and is redundant. 7583 */ 7584 igb_release_hw_control(adapter); 7585 7586 pci_disable_device(pdev); 7587 7588 return 0; 7589 } 7590 7591 #ifdef CONFIG_PM 7592 #ifdef CONFIG_PM_SLEEP 7593 static int igb_suspend(struct device *dev) 7594 { 7595 int retval; 7596 bool wake; 7597 struct pci_dev *pdev = to_pci_dev(dev); 7598 7599 retval = __igb_shutdown(pdev, &wake, 0); 7600 if (retval) 7601 return retval; 7602 7603 if (wake) { 7604 pci_prepare_to_sleep(pdev); 7605 } else { 7606 pci_wake_from_d3(pdev, false); 7607 pci_set_power_state(pdev, PCI_D3hot); 7608 } 7609 7610 return 0; 7611 } 7612 #endif /* CONFIG_PM_SLEEP */ 7613 7614 static int igb_resume(struct device *dev) 7615 { 7616 struct pci_dev *pdev = to_pci_dev(dev); 7617 struct net_device *netdev = pci_get_drvdata(pdev); 7618 struct igb_adapter *adapter = netdev_priv(netdev); 7619 struct e1000_hw *hw = &adapter->hw; 7620 u32 err; 7621 7622 pci_set_power_state(pdev, PCI_D0); 7623 pci_restore_state(pdev); 7624 pci_save_state(pdev); 7625 7626 if (!pci_device_is_present(pdev)) 7627 return -ENODEV; 7628 err = pci_enable_device_mem(pdev); 7629 if (err) { 7630 dev_err(&pdev->dev, 7631 "igb: Cannot enable PCI device from suspend\n"); 7632 return err; 7633 } 7634 pci_set_master(pdev); 7635 7636 pci_enable_wake(pdev, PCI_D3hot, 0); 7637 pci_enable_wake(pdev, PCI_D3cold, 0); 7638 7639 if (igb_init_interrupt_scheme(adapter, true)) { 7640 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7641 return -ENOMEM; 7642 } 7643 7644 igb_reset(adapter); 7645 7646 /* let the f/w know that the h/w is now under the control of the 7647 * driver. 7648 */ 7649 igb_get_hw_control(adapter); 7650 7651 wr32(E1000_WUS, ~0); 7652 7653 if (netdev->flags & IFF_UP) { 7654 rtnl_lock(); 7655 err = __igb_open(netdev, true); 7656 rtnl_unlock(); 7657 if (err) 7658 return err; 7659 } 7660 7661 netif_device_attach(netdev); 7662 return 0; 7663 } 7664 7665 static int igb_runtime_idle(struct device *dev) 7666 { 7667 struct pci_dev *pdev = to_pci_dev(dev); 7668 struct net_device *netdev = pci_get_drvdata(pdev); 7669 struct igb_adapter *adapter = netdev_priv(netdev); 7670 7671 if (!igb_has_link(adapter)) 7672 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7673 7674 return -EBUSY; 7675 } 7676 7677 static int igb_runtime_suspend(struct device *dev) 7678 { 7679 struct pci_dev *pdev = to_pci_dev(dev); 7680 int retval; 7681 bool wake; 7682 7683 retval = __igb_shutdown(pdev, &wake, 1); 7684 if (retval) 7685 return retval; 7686 7687 if (wake) { 7688 pci_prepare_to_sleep(pdev); 7689 } else { 7690 pci_wake_from_d3(pdev, false); 7691 pci_set_power_state(pdev, PCI_D3hot); 7692 } 7693 7694 return 0; 7695 } 7696 7697 static int igb_runtime_resume(struct device *dev) 7698 { 7699 return igb_resume(dev); 7700 } 7701 #endif /* CONFIG_PM */ 7702 7703 static void igb_shutdown(struct pci_dev *pdev) 7704 { 7705 bool wake; 7706 7707 __igb_shutdown(pdev, &wake, 0); 7708 7709 if (system_state == SYSTEM_POWER_OFF) { 7710 pci_wake_from_d3(pdev, wake); 7711 pci_set_power_state(pdev, PCI_D3hot); 7712 } 7713 } 7714 7715 #ifdef CONFIG_PCI_IOV 7716 static int igb_sriov_reinit(struct pci_dev *dev) 7717 { 7718 struct net_device *netdev = pci_get_drvdata(dev); 7719 struct igb_adapter *adapter = netdev_priv(netdev); 7720 struct pci_dev *pdev = adapter->pdev; 7721 7722 rtnl_lock(); 7723 7724 if (netif_running(netdev)) 7725 igb_close(netdev); 7726 else 7727 igb_reset(adapter); 7728 7729 igb_clear_interrupt_scheme(adapter); 7730 7731 igb_init_queue_configuration(adapter); 7732 7733 if (igb_init_interrupt_scheme(adapter, true)) { 7734 rtnl_unlock(); 7735 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7736 return -ENOMEM; 7737 } 7738 7739 if (netif_running(netdev)) 7740 igb_open(netdev); 7741 7742 rtnl_unlock(); 7743 7744 return 0; 7745 } 7746 7747 static int igb_pci_disable_sriov(struct pci_dev *dev) 7748 { 7749 int err = igb_disable_sriov(dev); 7750 7751 if (!err) 7752 err = igb_sriov_reinit(dev); 7753 7754 return err; 7755 } 7756 7757 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7758 { 7759 int err = igb_enable_sriov(dev, num_vfs); 7760 7761 if (err) 7762 goto out; 7763 7764 err = igb_sriov_reinit(dev); 7765 if (!err) 7766 return num_vfs; 7767 7768 out: 7769 return err; 7770 } 7771 7772 #endif 7773 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7774 { 7775 #ifdef CONFIG_PCI_IOV 7776 if (num_vfs == 0) 7777 return igb_pci_disable_sriov(dev); 7778 else 7779 return igb_pci_enable_sriov(dev, num_vfs); 7780 #endif 7781 return 0; 7782 } 7783 7784 #ifdef CONFIG_NET_POLL_CONTROLLER 7785 /* Polling 'interrupt' - used by things like netconsole to send skbs 7786 * without having to re-enable interrupts. It's not called while 7787 * the interrupt routine is executing. 7788 */ 7789 static void igb_netpoll(struct net_device *netdev) 7790 { 7791 struct igb_adapter *adapter = netdev_priv(netdev); 7792 struct e1000_hw *hw = &adapter->hw; 7793 struct igb_q_vector *q_vector; 7794 int i; 7795 7796 for (i = 0; i < adapter->num_q_vectors; i++) { 7797 q_vector = adapter->q_vector[i]; 7798 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7799 wr32(E1000_EIMC, q_vector->eims_value); 7800 else 7801 igb_irq_disable(adapter); 7802 napi_schedule(&q_vector->napi); 7803 } 7804 } 7805 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7806 7807 /** 7808 * igb_io_error_detected - called when PCI error is detected 7809 * @pdev: Pointer to PCI device 7810 * @state: The current pci connection state 7811 * 7812 * This function is called after a PCI bus error affecting 7813 * this device has been detected. 7814 **/ 7815 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7816 pci_channel_state_t state) 7817 { 7818 struct net_device *netdev = pci_get_drvdata(pdev); 7819 struct igb_adapter *adapter = netdev_priv(netdev); 7820 7821 netif_device_detach(netdev); 7822 7823 if (state == pci_channel_io_perm_failure) 7824 return PCI_ERS_RESULT_DISCONNECT; 7825 7826 if (netif_running(netdev)) 7827 igb_down(adapter); 7828 pci_disable_device(pdev); 7829 7830 /* Request a slot slot reset. */ 7831 return PCI_ERS_RESULT_NEED_RESET; 7832 } 7833 7834 /** 7835 * igb_io_slot_reset - called after the pci bus has been reset. 7836 * @pdev: Pointer to PCI device 7837 * 7838 * Restart the card from scratch, as if from a cold-boot. Implementation 7839 * resembles the first-half of the igb_resume routine. 7840 **/ 7841 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7842 { 7843 struct net_device *netdev = pci_get_drvdata(pdev); 7844 struct igb_adapter *adapter = netdev_priv(netdev); 7845 struct e1000_hw *hw = &adapter->hw; 7846 pci_ers_result_t result; 7847 int err; 7848 7849 if (pci_enable_device_mem(pdev)) { 7850 dev_err(&pdev->dev, 7851 "Cannot re-enable PCI device after reset.\n"); 7852 result = PCI_ERS_RESULT_DISCONNECT; 7853 } else { 7854 pci_set_master(pdev); 7855 pci_restore_state(pdev); 7856 pci_save_state(pdev); 7857 7858 pci_enable_wake(pdev, PCI_D3hot, 0); 7859 pci_enable_wake(pdev, PCI_D3cold, 0); 7860 7861 igb_reset(adapter); 7862 wr32(E1000_WUS, ~0); 7863 result = PCI_ERS_RESULT_RECOVERED; 7864 } 7865 7866 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7867 if (err) { 7868 dev_err(&pdev->dev, 7869 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7870 err); 7871 /* non-fatal, continue */ 7872 } 7873 7874 return result; 7875 } 7876 7877 /** 7878 * igb_io_resume - called when traffic can start flowing again. 7879 * @pdev: Pointer to PCI device 7880 * 7881 * This callback is called when the error recovery driver tells us that 7882 * its OK to resume normal operation. Implementation resembles the 7883 * second-half of the igb_resume routine. 7884 */ 7885 static void igb_io_resume(struct pci_dev *pdev) 7886 { 7887 struct net_device *netdev = pci_get_drvdata(pdev); 7888 struct igb_adapter *adapter = netdev_priv(netdev); 7889 7890 if (netif_running(netdev)) { 7891 if (igb_up(adapter)) { 7892 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7893 return; 7894 } 7895 } 7896 7897 netif_device_attach(netdev); 7898 7899 /* let the f/w know that the h/w is now under the control of the 7900 * driver. 7901 */ 7902 igb_get_hw_control(adapter); 7903 } 7904 7905 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7906 u8 qsel) 7907 { 7908 struct e1000_hw *hw = &adapter->hw; 7909 u32 rar_low, rar_high; 7910 7911 /* HW expects these to be in network order when they are plugged 7912 * into the registers which are little endian. In order to guarantee 7913 * that ordering we need to do an leXX_to_cpup here in order to be 7914 * ready for the byteswap that occurs with writel 7915 */ 7916 rar_low = le32_to_cpup((__le32 *)(addr)); 7917 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 7918 7919 /* Indicate to hardware the Address is Valid. */ 7920 rar_high |= E1000_RAH_AV; 7921 7922 if (hw->mac.type == e1000_82575) 7923 rar_high |= E1000_RAH_POOL_1 * qsel; 7924 else 7925 rar_high |= E1000_RAH_POOL_1 << qsel; 7926 7927 wr32(E1000_RAL(index), rar_low); 7928 wrfl(); 7929 wr32(E1000_RAH(index), rar_high); 7930 wrfl(); 7931 } 7932 7933 static int igb_set_vf_mac(struct igb_adapter *adapter, 7934 int vf, unsigned char *mac_addr) 7935 { 7936 struct e1000_hw *hw = &adapter->hw; 7937 /* VF MAC addresses start at end of receive addresses and moves 7938 * towards the first, as a result a collision should not be possible 7939 */ 7940 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7941 7942 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7943 7944 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7945 7946 return 0; 7947 } 7948 7949 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7950 { 7951 struct igb_adapter *adapter = netdev_priv(netdev); 7952 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7953 return -EINVAL; 7954 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7955 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7956 dev_info(&adapter->pdev->dev, 7957 "Reload the VF driver to make this change effective."); 7958 if (test_bit(__IGB_DOWN, &adapter->state)) { 7959 dev_warn(&adapter->pdev->dev, 7960 "The VF MAC address has been set, but the PF device is not up.\n"); 7961 dev_warn(&adapter->pdev->dev, 7962 "Bring the PF device up before attempting to use the VF device.\n"); 7963 } 7964 return igb_set_vf_mac(adapter, vf, mac); 7965 } 7966 7967 static int igb_link_mbps(int internal_link_speed) 7968 { 7969 switch (internal_link_speed) { 7970 case SPEED_100: 7971 return 100; 7972 case SPEED_1000: 7973 return 1000; 7974 default: 7975 return 0; 7976 } 7977 } 7978 7979 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7980 int link_speed) 7981 { 7982 int rf_dec, rf_int; 7983 u32 bcnrc_val; 7984 7985 if (tx_rate != 0) { 7986 /* Calculate the rate factor values to set */ 7987 rf_int = link_speed / tx_rate; 7988 rf_dec = (link_speed - (rf_int * tx_rate)); 7989 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 7990 tx_rate; 7991 7992 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7993 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7994 E1000_RTTBCNRC_RF_INT_MASK); 7995 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7996 } else { 7997 bcnrc_val = 0; 7998 } 7999 8000 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8001 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8002 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8003 */ 8004 wr32(E1000_RTTBCNRM, 0x14); 8005 wr32(E1000_RTTBCNRC, bcnrc_val); 8006 } 8007 8008 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8009 { 8010 int actual_link_speed, i; 8011 bool reset_rate = false; 8012 8013 /* VF TX rate limit was not set or not supported */ 8014 if ((adapter->vf_rate_link_speed == 0) || 8015 (adapter->hw.mac.type != e1000_82576)) 8016 return; 8017 8018 actual_link_speed = igb_link_mbps(adapter->link_speed); 8019 if (actual_link_speed != adapter->vf_rate_link_speed) { 8020 reset_rate = true; 8021 adapter->vf_rate_link_speed = 0; 8022 dev_info(&adapter->pdev->dev, 8023 "Link speed has been changed. VF Transmit rate is disabled\n"); 8024 } 8025 8026 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8027 if (reset_rate) 8028 adapter->vf_data[i].tx_rate = 0; 8029 8030 igb_set_vf_rate_limit(&adapter->hw, i, 8031 adapter->vf_data[i].tx_rate, 8032 actual_link_speed); 8033 } 8034 } 8035 8036 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8037 int min_tx_rate, int max_tx_rate) 8038 { 8039 struct igb_adapter *adapter = netdev_priv(netdev); 8040 struct e1000_hw *hw = &adapter->hw; 8041 int actual_link_speed; 8042 8043 if (hw->mac.type != e1000_82576) 8044 return -EOPNOTSUPP; 8045 8046 if (min_tx_rate) 8047 return -EINVAL; 8048 8049 actual_link_speed = igb_link_mbps(adapter->link_speed); 8050 if ((vf >= adapter->vfs_allocated_count) || 8051 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8052 (max_tx_rate < 0) || 8053 (max_tx_rate > actual_link_speed)) 8054 return -EINVAL; 8055 8056 adapter->vf_rate_link_speed = actual_link_speed; 8057 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8058 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8059 8060 return 0; 8061 } 8062 8063 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8064 bool setting) 8065 { 8066 struct igb_adapter *adapter = netdev_priv(netdev); 8067 struct e1000_hw *hw = &adapter->hw; 8068 u32 reg_val, reg_offset; 8069 8070 if (!adapter->vfs_allocated_count) 8071 return -EOPNOTSUPP; 8072 8073 if (vf >= adapter->vfs_allocated_count) 8074 return -EINVAL; 8075 8076 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8077 reg_val = rd32(reg_offset); 8078 if (setting) 8079 reg_val |= (BIT(vf) | 8080 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8081 else 8082 reg_val &= ~(BIT(vf) | 8083 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8084 wr32(reg_offset, reg_val); 8085 8086 adapter->vf_data[vf].spoofchk_enabled = setting; 8087 return 0; 8088 } 8089 8090 static int igb_ndo_get_vf_config(struct net_device *netdev, 8091 int vf, struct ifla_vf_info *ivi) 8092 { 8093 struct igb_adapter *adapter = netdev_priv(netdev); 8094 if (vf >= adapter->vfs_allocated_count) 8095 return -EINVAL; 8096 ivi->vf = vf; 8097 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8098 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8099 ivi->min_tx_rate = 0; 8100 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8101 ivi->qos = adapter->vf_data[vf].pf_qos; 8102 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8103 return 0; 8104 } 8105 8106 static void igb_vmm_control(struct igb_adapter *adapter) 8107 { 8108 struct e1000_hw *hw = &adapter->hw; 8109 u32 reg; 8110 8111 switch (hw->mac.type) { 8112 case e1000_82575: 8113 case e1000_i210: 8114 case e1000_i211: 8115 case e1000_i354: 8116 default: 8117 /* replication is not supported for 82575 */ 8118 return; 8119 case e1000_82576: 8120 /* notify HW that the MAC is adding vlan tags */ 8121 reg = rd32(E1000_DTXCTL); 8122 reg |= E1000_DTXCTL_VLAN_ADDED; 8123 wr32(E1000_DTXCTL, reg); 8124 /* Fall through */ 8125 case e1000_82580: 8126 /* enable replication vlan tag stripping */ 8127 reg = rd32(E1000_RPLOLR); 8128 reg |= E1000_RPLOLR_STRVLAN; 8129 wr32(E1000_RPLOLR, reg); 8130 /* Fall through */ 8131 case e1000_i350: 8132 /* none of the above registers are supported by i350 */ 8133 break; 8134 } 8135 8136 if (adapter->vfs_allocated_count) { 8137 igb_vmdq_set_loopback_pf(hw, true); 8138 igb_vmdq_set_replication_pf(hw, true); 8139 igb_vmdq_set_anti_spoofing_pf(hw, true, 8140 adapter->vfs_allocated_count); 8141 } else { 8142 igb_vmdq_set_loopback_pf(hw, false); 8143 igb_vmdq_set_replication_pf(hw, false); 8144 } 8145 } 8146 8147 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8148 { 8149 struct e1000_hw *hw = &adapter->hw; 8150 u32 dmac_thr; 8151 u16 hwm; 8152 8153 if (hw->mac.type > e1000_82580) { 8154 if (adapter->flags & IGB_FLAG_DMAC) { 8155 u32 reg; 8156 8157 /* force threshold to 0. */ 8158 wr32(E1000_DMCTXTH, 0); 8159 8160 /* DMA Coalescing high water mark needs to be greater 8161 * than the Rx threshold. Set hwm to PBA - max frame 8162 * size in 16B units, capping it at PBA - 6KB. 8163 */ 8164 hwm = 64 * (pba - 6); 8165 reg = rd32(E1000_FCRTC); 8166 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8167 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8168 & E1000_FCRTC_RTH_COAL_MASK); 8169 wr32(E1000_FCRTC, reg); 8170 8171 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8172 * frame size, capping it at PBA - 10KB. 8173 */ 8174 dmac_thr = pba - 10; 8175 reg = rd32(E1000_DMACR); 8176 reg &= ~E1000_DMACR_DMACTHR_MASK; 8177 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8178 & E1000_DMACR_DMACTHR_MASK); 8179 8180 /* transition to L0x or L1 if available..*/ 8181 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8182 8183 /* watchdog timer= +-1000 usec in 32usec intervals */ 8184 reg |= (1000 >> 5); 8185 8186 /* Disable BMC-to-OS Watchdog Enable */ 8187 if (hw->mac.type != e1000_i354) 8188 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8189 8190 wr32(E1000_DMACR, reg); 8191 8192 /* no lower threshold to disable 8193 * coalescing(smart fifb)-UTRESH=0 8194 */ 8195 wr32(E1000_DMCRTRH, 0); 8196 8197 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8198 8199 wr32(E1000_DMCTLX, reg); 8200 8201 /* free space in tx packet buffer to wake from 8202 * DMA coal 8203 */ 8204 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8205 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8206 8207 /* make low power state decision controlled 8208 * by DMA coal 8209 */ 8210 reg = rd32(E1000_PCIEMISC); 8211 reg &= ~E1000_PCIEMISC_LX_DECISION; 8212 wr32(E1000_PCIEMISC, reg); 8213 } /* endif adapter->dmac is not disabled */ 8214 } else if (hw->mac.type == e1000_82580) { 8215 u32 reg = rd32(E1000_PCIEMISC); 8216 8217 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8218 wr32(E1000_DMACR, 0); 8219 } 8220 } 8221 8222 /** 8223 * igb_read_i2c_byte - Reads 8 bit word over I2C 8224 * @hw: pointer to hardware structure 8225 * @byte_offset: byte offset to read 8226 * @dev_addr: device address 8227 * @data: value read 8228 * 8229 * Performs byte read operation over I2C interface at 8230 * a specified device address. 8231 **/ 8232 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8233 u8 dev_addr, u8 *data) 8234 { 8235 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8236 struct i2c_client *this_client = adapter->i2c_client; 8237 s32 status; 8238 u16 swfw_mask = 0; 8239 8240 if (!this_client) 8241 return E1000_ERR_I2C; 8242 8243 swfw_mask = E1000_SWFW_PHY0_SM; 8244 8245 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8246 return E1000_ERR_SWFW_SYNC; 8247 8248 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8249 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8250 8251 if (status < 0) 8252 return E1000_ERR_I2C; 8253 else { 8254 *data = status; 8255 return 0; 8256 } 8257 } 8258 8259 /** 8260 * igb_write_i2c_byte - Writes 8 bit word over I2C 8261 * @hw: pointer to hardware structure 8262 * @byte_offset: byte offset to write 8263 * @dev_addr: device address 8264 * @data: value to write 8265 * 8266 * Performs byte write operation over I2C interface at 8267 * a specified device address. 8268 **/ 8269 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8270 u8 dev_addr, u8 data) 8271 { 8272 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8273 struct i2c_client *this_client = adapter->i2c_client; 8274 s32 status; 8275 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8276 8277 if (!this_client) 8278 return E1000_ERR_I2C; 8279 8280 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8281 return E1000_ERR_SWFW_SYNC; 8282 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8283 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8284 8285 if (status) 8286 return E1000_ERR_I2C; 8287 else 8288 return 0; 8289 8290 } 8291 8292 int igb_reinit_queues(struct igb_adapter *adapter) 8293 { 8294 struct net_device *netdev = adapter->netdev; 8295 struct pci_dev *pdev = adapter->pdev; 8296 int err = 0; 8297 8298 if (netif_running(netdev)) 8299 igb_close(netdev); 8300 8301 igb_reset_interrupt_capability(adapter); 8302 8303 if (igb_init_interrupt_scheme(adapter, true)) { 8304 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8305 return -ENOMEM; 8306 } 8307 8308 if (netif_running(netdev)) 8309 err = igb_open(netdev); 8310 8311 return err; 8312 } 8313 /* igb_main.c */ 8314