1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 4 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static void igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_index(struct igb_adapter *, u32); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_flush_mac_table(struct igb_adapter *); 170 static int igb_available_rars(struct igb_adapter *, u8); 171 static void igb_set_default_mac_filter(struct igb_adapter *); 172 static int igb_uc_sync(struct net_device *, const unsigned char *); 173 static int igb_uc_unsync(struct net_device *, const unsigned char *); 174 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 175 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 176 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 177 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 178 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 179 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 180 bool setting); 181 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 182 struct ifla_vf_info *ivi); 183 static void igb_check_vf_rate_limit(struct igb_adapter *); 184 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 185 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 186 187 #ifdef CONFIG_PCI_IOV 188 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 189 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 190 static int igb_disable_sriov(struct pci_dev *dev); 191 static int igb_pci_disable_sriov(struct pci_dev *dev); 192 #endif 193 194 static int igb_suspend(struct device *); 195 static int igb_resume(struct device *); 196 static int igb_runtime_suspend(struct device *dev); 197 static int igb_runtime_resume(struct device *dev); 198 static int igb_runtime_idle(struct device *dev); 199 static const struct dev_pm_ops igb_pm_ops = { 200 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 201 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 202 igb_runtime_idle) 203 }; 204 static void igb_shutdown(struct pci_dev *); 205 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 206 #ifdef CONFIG_IGB_DCA 207 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 208 static struct notifier_block dca_notifier = { 209 .notifier_call = igb_notify_dca, 210 .next = NULL, 211 .priority = 0 212 }; 213 #endif 214 #ifdef CONFIG_NET_POLL_CONTROLLER 215 /* for netdump / net console */ 216 static void igb_netpoll(struct net_device *); 217 #endif 218 #ifdef CONFIG_PCI_IOV 219 static unsigned int max_vfs; 220 module_param(max_vfs, uint, 0); 221 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 222 #endif /* CONFIG_PCI_IOV */ 223 224 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227 static void igb_io_resume(struct pci_dev *); 228 229 static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233 }; 234 235 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237 static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242 #ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244 #endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248 }; 249 250 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252 MODULE_LICENSE("GPL"); 253 MODULE_VERSION(DRV_VERSION); 254 255 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256 static int debug = -1; 257 module_param(debug, int, 0); 258 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260 struct igb_reg_info { 261 u32 ofs; 262 char *name; 263 }; 264 265 static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299 }; 300 301 /* igb_regdump - register printout routine */ 302 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303 { 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365 } 366 367 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 368 static void igb_dump(struct igb_adapter *adapter) 369 { 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start\n"); 388 pr_info("%-15s %016lX %016lX\n", netdev->name, 389 netdev->state, dev_trans_start(netdev)); 390 } 391 392 /* Print Registers */ 393 dev_info(&adapter->pdev->dev, "Register Dump\n"); 394 pr_info(" Register Name Value\n"); 395 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 396 reginfo->name; reginfo++) { 397 igb_regdump(hw, reginfo); 398 } 399 400 /* Print TX Ring Summary */ 401 if (!netdev || !netif_running(netdev)) 402 goto exit; 403 404 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 405 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 406 for (n = 0; n < adapter->num_tx_queues; n++) { 407 struct igb_tx_buffer *buffer_info; 408 tx_ring = adapter->tx_ring[n]; 409 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 410 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 411 n, tx_ring->next_to_use, tx_ring->next_to_clean, 412 (u64)dma_unmap_addr(buffer_info, dma), 413 dma_unmap_len(buffer_info, len), 414 buffer_info->next_to_watch, 415 (u64)buffer_info->time_stamp); 416 } 417 418 /* Print TX Rings */ 419 if (!netif_msg_tx_done(adapter)) 420 goto rx_ring_summary; 421 422 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 423 424 /* Transmit Descriptor Formats 425 * 426 * Advanced Transmit Descriptor 427 * +--------------------------------------------------------------+ 428 * 0 | Buffer Address [63:0] | 429 * +--------------------------------------------------------------+ 430 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 431 * +--------------------------------------------------------------+ 432 * 63 46 45 40 39 38 36 35 32 31 24 15 0 433 */ 434 435 for (n = 0; n < adapter->num_tx_queues; n++) { 436 tx_ring = adapter->tx_ring[n]; 437 pr_info("------------------------------------\n"); 438 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 439 pr_info("------------------------------------\n"); 440 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 441 442 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 443 const char *next_desc; 444 struct igb_tx_buffer *buffer_info; 445 tx_desc = IGB_TX_DESC(tx_ring, i); 446 buffer_info = &tx_ring->tx_buffer_info[i]; 447 u0 = (struct my_u0 *)tx_desc; 448 if (i == tx_ring->next_to_use && 449 i == tx_ring->next_to_clean) 450 next_desc = " NTC/U"; 451 else if (i == tx_ring->next_to_use) 452 next_desc = " NTU"; 453 else if (i == tx_ring->next_to_clean) 454 next_desc = " NTC"; 455 else 456 next_desc = ""; 457 458 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 459 i, le64_to_cpu(u0->a), 460 le64_to_cpu(u0->b), 461 (u64)dma_unmap_addr(buffer_info, dma), 462 dma_unmap_len(buffer_info, len), 463 buffer_info->next_to_watch, 464 (u64)buffer_info->time_stamp, 465 buffer_info->skb, next_desc); 466 467 if (netif_msg_pktdata(adapter) && buffer_info->skb) 468 print_hex_dump(KERN_INFO, "", 469 DUMP_PREFIX_ADDRESS, 470 16, 1, buffer_info->skb->data, 471 dma_unmap_len(buffer_info, len), 472 true); 473 } 474 } 475 476 /* Print RX Rings Summary */ 477 rx_ring_summary: 478 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 479 pr_info("Queue [NTU] [NTC]\n"); 480 for (n = 0; n < adapter->num_rx_queues; n++) { 481 rx_ring = adapter->rx_ring[n]; 482 pr_info(" %5d %5X %5X\n", 483 n, rx_ring->next_to_use, rx_ring->next_to_clean); 484 } 485 486 /* Print RX Rings */ 487 if (!netif_msg_rx_status(adapter)) 488 goto exit; 489 490 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 491 492 /* Advanced Receive Descriptor (Read) Format 493 * 63 1 0 494 * +-----------------------------------------------------+ 495 * 0 | Packet Buffer Address [63:1] |A0/NSE| 496 * +----------------------------------------------+------+ 497 * 8 | Header Buffer Address [63:1] | DD | 498 * +-----------------------------------------------------+ 499 * 500 * 501 * Advanced Receive Descriptor (Write-Back) Format 502 * 503 * 63 48 47 32 31 30 21 20 17 16 4 3 0 504 * +------------------------------------------------------+ 505 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 506 * | Checksum Ident | | | | Type | Type | 507 * +------------------------------------------------------+ 508 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 509 * +------------------------------------------------------+ 510 * 63 48 47 32 31 20 19 0 511 */ 512 513 for (n = 0; n < adapter->num_rx_queues; n++) { 514 rx_ring = adapter->rx_ring[n]; 515 pr_info("------------------------------------\n"); 516 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 517 pr_info("------------------------------------\n"); 518 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 519 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 520 521 for (i = 0; i < rx_ring->count; i++) { 522 const char *next_desc; 523 struct igb_rx_buffer *buffer_info; 524 buffer_info = &rx_ring->rx_buffer_info[i]; 525 rx_desc = IGB_RX_DESC(rx_ring, i); 526 u0 = (struct my_u0 *)rx_desc; 527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 528 529 if (i == rx_ring->next_to_use) 530 next_desc = " NTU"; 531 else if (i == rx_ring->next_to_clean) 532 next_desc = " NTC"; 533 else 534 next_desc = ""; 535 536 if (staterr & E1000_RXD_STAT_DD) { 537 /* Descriptor Done */ 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 539 "RWB", i, 540 le64_to_cpu(u0->a), 541 le64_to_cpu(u0->b), 542 next_desc); 543 } else { 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 545 "R ", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 (u64)buffer_info->dma, 549 next_desc); 550 551 if (netif_msg_pktdata(adapter) && 552 buffer_info->dma && buffer_info->page) { 553 print_hex_dump(KERN_INFO, "", 554 DUMP_PREFIX_ADDRESS, 555 16, 1, 556 page_address(buffer_info->page) + 557 buffer_info->page_offset, 558 igb_rx_bufsz(rx_ring), true); 559 } 560 } 561 } 562 } 563 564 exit: 565 return; 566 } 567 568 /** 569 * igb_get_i2c_data - Reads the I2C SDA data bit 570 * @hw: pointer to hardware structure 571 * @i2cctl: Current value of I2CCTL register 572 * 573 * Returns the I2C data bit value 574 **/ 575 static int igb_get_i2c_data(void *data) 576 { 577 struct igb_adapter *adapter = (struct igb_adapter *)data; 578 struct e1000_hw *hw = &adapter->hw; 579 s32 i2cctl = rd32(E1000_I2CPARAMS); 580 581 return !!(i2cctl & E1000_I2C_DATA_IN); 582 } 583 584 /** 585 * igb_set_i2c_data - Sets the I2C data bit 586 * @data: pointer to hardware structure 587 * @state: I2C data value (0 or 1) to set 588 * 589 * Sets the I2C data bit 590 **/ 591 static void igb_set_i2c_data(void *data, int state) 592 { 593 struct igb_adapter *adapter = (struct igb_adapter *)data; 594 struct e1000_hw *hw = &adapter->hw; 595 s32 i2cctl = rd32(E1000_I2CPARAMS); 596 597 if (state) 598 i2cctl |= E1000_I2C_DATA_OUT; 599 else 600 i2cctl &= ~E1000_I2C_DATA_OUT; 601 602 i2cctl &= ~E1000_I2C_DATA_OE_N; 603 i2cctl |= E1000_I2C_CLK_OE_N; 604 wr32(E1000_I2CPARAMS, i2cctl); 605 wrfl(); 606 607 } 608 609 /** 610 * igb_set_i2c_clk - Sets the I2C SCL clock 611 * @data: pointer to hardware structure 612 * @state: state to set clock 613 * 614 * Sets the I2C clock line to state 615 **/ 616 static void igb_set_i2c_clk(void *data, int state) 617 { 618 struct igb_adapter *adapter = (struct igb_adapter *)data; 619 struct e1000_hw *hw = &adapter->hw; 620 s32 i2cctl = rd32(E1000_I2CPARAMS); 621 622 if (state) { 623 i2cctl |= E1000_I2C_CLK_OUT; 624 i2cctl &= ~E1000_I2C_CLK_OE_N; 625 } else { 626 i2cctl &= ~E1000_I2C_CLK_OUT; 627 i2cctl &= ~E1000_I2C_CLK_OE_N; 628 } 629 wr32(E1000_I2CPARAMS, i2cctl); 630 wrfl(); 631 } 632 633 /** 634 * igb_get_i2c_clk - Gets the I2C SCL clock state 635 * @data: pointer to hardware structure 636 * 637 * Gets the I2C clock state 638 **/ 639 static int igb_get_i2c_clk(void *data) 640 { 641 struct igb_adapter *adapter = (struct igb_adapter *)data; 642 struct e1000_hw *hw = &adapter->hw; 643 s32 i2cctl = rd32(E1000_I2CPARAMS); 644 645 return !!(i2cctl & E1000_I2C_CLK_IN); 646 } 647 648 static const struct i2c_algo_bit_data igb_i2c_algo = { 649 .setsda = igb_set_i2c_data, 650 .setscl = igb_set_i2c_clk, 651 .getsda = igb_get_i2c_data, 652 .getscl = igb_get_i2c_clk, 653 .udelay = 5, 654 .timeout = 20, 655 }; 656 657 /** 658 * igb_get_hw_dev - return device 659 * @hw: pointer to hardware structure 660 * 661 * used by hardware layer to print debugging information 662 **/ 663 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 664 { 665 struct igb_adapter *adapter = hw->back; 666 return adapter->netdev; 667 } 668 669 /** 670 * igb_init_module - Driver Registration Routine 671 * 672 * igb_init_module is the first routine called when the driver is 673 * loaded. All it does is register with the PCI subsystem. 674 **/ 675 static int __init igb_init_module(void) 676 { 677 int ret; 678 679 pr_info("%s - version %s\n", 680 igb_driver_string, igb_driver_version); 681 pr_info("%s\n", igb_copyright); 682 683 #ifdef CONFIG_IGB_DCA 684 dca_register_notify(&dca_notifier); 685 #endif 686 ret = pci_register_driver(&igb_driver); 687 return ret; 688 } 689 690 module_init(igb_init_module); 691 692 /** 693 * igb_exit_module - Driver Exit Cleanup Routine 694 * 695 * igb_exit_module is called just before the driver is removed 696 * from memory. 697 **/ 698 static void __exit igb_exit_module(void) 699 { 700 #ifdef CONFIG_IGB_DCA 701 dca_unregister_notify(&dca_notifier); 702 #endif 703 pci_unregister_driver(&igb_driver); 704 } 705 706 module_exit(igb_exit_module); 707 708 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 709 /** 710 * igb_cache_ring_register - Descriptor ring to register mapping 711 * @adapter: board private structure to initialize 712 * 713 * Once we know the feature-set enabled for the device, we'll cache 714 * the register offset the descriptor ring is assigned to. 715 **/ 716 static void igb_cache_ring_register(struct igb_adapter *adapter) 717 { 718 int i = 0, j = 0; 719 u32 rbase_offset = adapter->vfs_allocated_count; 720 721 switch (adapter->hw.mac.type) { 722 case e1000_82576: 723 /* The queues are allocated for virtualization such that VF 0 724 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 725 * In order to avoid collision we start at the first free queue 726 * and continue consuming queues in the same sequence 727 */ 728 if (adapter->vfs_allocated_count) { 729 for (; i < adapter->rss_queues; i++) 730 adapter->rx_ring[i]->reg_idx = rbase_offset + 731 Q_IDX_82576(i); 732 } 733 /* Fall through */ 734 case e1000_82575: 735 case e1000_82580: 736 case e1000_i350: 737 case e1000_i354: 738 case e1000_i210: 739 case e1000_i211: 740 /* Fall through */ 741 default: 742 for (; i < adapter->num_rx_queues; i++) 743 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 744 for (; j < adapter->num_tx_queues; j++) 745 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 746 break; 747 } 748 } 749 750 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 751 { 752 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 753 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 754 u32 value = 0; 755 756 if (E1000_REMOVED(hw_addr)) 757 return ~value; 758 759 value = readl(&hw_addr[reg]); 760 761 /* reads should not return all F's */ 762 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 763 struct net_device *netdev = igb->netdev; 764 hw->hw_addr = NULL; 765 netif_device_detach(netdev); 766 netdev_err(netdev, "PCIe link lost, device now detached\n"); 767 } 768 769 return value; 770 } 771 772 /** 773 * igb_write_ivar - configure ivar for given MSI-X vector 774 * @hw: pointer to the HW structure 775 * @msix_vector: vector number we are allocating to a given ring 776 * @index: row index of IVAR register to write within IVAR table 777 * @offset: column offset of in IVAR, should be multiple of 8 778 * 779 * This function is intended to handle the writing of the IVAR register 780 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 781 * each containing an cause allocation for an Rx and Tx ring, and a 782 * variable number of rows depending on the number of queues supported. 783 **/ 784 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 785 int index, int offset) 786 { 787 u32 ivar = array_rd32(E1000_IVAR0, index); 788 789 /* clear any bits that are currently set */ 790 ivar &= ~((u32)0xFF << offset); 791 792 /* write vector and valid bit */ 793 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 794 795 array_wr32(E1000_IVAR0, index, ivar); 796 } 797 798 #define IGB_N0_QUEUE -1 799 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 800 { 801 struct igb_adapter *adapter = q_vector->adapter; 802 struct e1000_hw *hw = &adapter->hw; 803 int rx_queue = IGB_N0_QUEUE; 804 int tx_queue = IGB_N0_QUEUE; 805 u32 msixbm = 0; 806 807 if (q_vector->rx.ring) 808 rx_queue = q_vector->rx.ring->reg_idx; 809 if (q_vector->tx.ring) 810 tx_queue = q_vector->tx.ring->reg_idx; 811 812 switch (hw->mac.type) { 813 case e1000_82575: 814 /* The 82575 assigns vectors using a bitmask, which matches the 815 * bitmask for the EICR/EIMS/EIMC registers. To assign one 816 * or more queues to a vector, we write the appropriate bits 817 * into the MSIXBM register for that vector. 818 */ 819 if (rx_queue > IGB_N0_QUEUE) 820 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 821 if (tx_queue > IGB_N0_QUEUE) 822 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 823 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 824 msixbm |= E1000_EIMS_OTHER; 825 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 826 q_vector->eims_value = msixbm; 827 break; 828 case e1000_82576: 829 /* 82576 uses a table that essentially consists of 2 columns 830 * with 8 rows. The ordering is column-major so we use the 831 * lower 3 bits as the row index, and the 4th bit as the 832 * column offset. 833 */ 834 if (rx_queue > IGB_N0_QUEUE) 835 igb_write_ivar(hw, msix_vector, 836 rx_queue & 0x7, 837 (rx_queue & 0x8) << 1); 838 if (tx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 tx_queue & 0x7, 841 ((tx_queue & 0x8) << 1) + 8); 842 q_vector->eims_value = BIT(msix_vector); 843 break; 844 case e1000_82580: 845 case e1000_i350: 846 case e1000_i354: 847 case e1000_i210: 848 case e1000_i211: 849 /* On 82580 and newer adapters the scheme is similar to 82576 850 * however instead of ordering column-major we have things 851 * ordered row-major. So we traverse the table by using 852 * bit 0 as the column offset, and the remaining bits as the 853 * row index. 854 */ 855 if (rx_queue > IGB_N0_QUEUE) 856 igb_write_ivar(hw, msix_vector, 857 rx_queue >> 1, 858 (rx_queue & 0x1) << 4); 859 if (tx_queue > IGB_N0_QUEUE) 860 igb_write_ivar(hw, msix_vector, 861 tx_queue >> 1, 862 ((tx_queue & 0x1) << 4) + 8); 863 q_vector->eims_value = BIT(msix_vector); 864 break; 865 default: 866 BUG(); 867 break; 868 } 869 870 /* add q_vector eims value to global eims_enable_mask */ 871 adapter->eims_enable_mask |= q_vector->eims_value; 872 873 /* configure q_vector to set itr on first interrupt */ 874 q_vector->set_itr = 1; 875 } 876 877 /** 878 * igb_configure_msix - Configure MSI-X hardware 879 * @adapter: board private structure to initialize 880 * 881 * igb_configure_msix sets up the hardware to properly 882 * generate MSI-X interrupts. 883 **/ 884 static void igb_configure_msix(struct igb_adapter *adapter) 885 { 886 u32 tmp; 887 int i, vector = 0; 888 struct e1000_hw *hw = &adapter->hw; 889 890 adapter->eims_enable_mask = 0; 891 892 /* set vector for other causes, i.e. link changes */ 893 switch (hw->mac.type) { 894 case e1000_82575: 895 tmp = rd32(E1000_CTRL_EXT); 896 /* enable MSI-X PBA support*/ 897 tmp |= E1000_CTRL_EXT_PBA_CLR; 898 899 /* Auto-Mask interrupts upon ICR read. */ 900 tmp |= E1000_CTRL_EXT_EIAME; 901 tmp |= E1000_CTRL_EXT_IRCA; 902 903 wr32(E1000_CTRL_EXT, tmp); 904 905 /* enable msix_other interrupt */ 906 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 907 adapter->eims_other = E1000_EIMS_OTHER; 908 909 break; 910 911 case e1000_82576: 912 case e1000_82580: 913 case e1000_i350: 914 case e1000_i354: 915 case e1000_i210: 916 case e1000_i211: 917 /* Turn on MSI-X capability first, or our settings 918 * won't stick. And it will take days to debug. 919 */ 920 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 921 E1000_GPIE_PBA | E1000_GPIE_EIAME | 922 E1000_GPIE_NSICR); 923 924 /* enable msix_other interrupt */ 925 adapter->eims_other = BIT(vector); 926 tmp = (vector++ | E1000_IVAR_VALID) << 8; 927 928 wr32(E1000_IVAR_MISC, tmp); 929 break; 930 default: 931 /* do nothing, since nothing else supports MSI-X */ 932 break; 933 } /* switch (hw->mac.type) */ 934 935 adapter->eims_enable_mask |= adapter->eims_other; 936 937 for (i = 0; i < adapter->num_q_vectors; i++) 938 igb_assign_vector(adapter->q_vector[i], vector++); 939 940 wrfl(); 941 } 942 943 /** 944 * igb_request_msix - Initialize MSI-X interrupts 945 * @adapter: board private structure to initialize 946 * 947 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 948 * kernel. 949 **/ 950 static int igb_request_msix(struct igb_adapter *adapter) 951 { 952 struct net_device *netdev = adapter->netdev; 953 int i, err = 0, vector = 0, free_vector = 0; 954 955 err = request_irq(adapter->msix_entries[vector].vector, 956 igb_msix_other, 0, netdev->name, adapter); 957 if (err) 958 goto err_out; 959 960 for (i = 0; i < adapter->num_q_vectors; i++) { 961 struct igb_q_vector *q_vector = adapter->q_vector[i]; 962 963 vector++; 964 965 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 966 967 if (q_vector->rx.ring && q_vector->tx.ring) 968 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 969 q_vector->rx.ring->queue_index); 970 else if (q_vector->tx.ring) 971 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 972 q_vector->tx.ring->queue_index); 973 else if (q_vector->rx.ring) 974 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 975 q_vector->rx.ring->queue_index); 976 else 977 sprintf(q_vector->name, "%s-unused", netdev->name); 978 979 err = request_irq(adapter->msix_entries[vector].vector, 980 igb_msix_ring, 0, q_vector->name, 981 q_vector); 982 if (err) 983 goto err_free; 984 } 985 986 igb_configure_msix(adapter); 987 return 0; 988 989 err_free: 990 /* free already assigned IRQs */ 991 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 992 993 vector--; 994 for (i = 0; i < vector; i++) { 995 free_irq(adapter->msix_entries[free_vector++].vector, 996 adapter->q_vector[i]); 997 } 998 err_out: 999 return err; 1000 } 1001 1002 /** 1003 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1004 * @adapter: board private structure to initialize 1005 * @v_idx: Index of vector to be freed 1006 * 1007 * This function frees the memory allocated to the q_vector. 1008 **/ 1009 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1010 { 1011 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1012 1013 adapter->q_vector[v_idx] = NULL; 1014 1015 /* igb_get_stats64() might access the rings on this vector, 1016 * we must wait a grace period before freeing it. 1017 */ 1018 if (q_vector) 1019 kfree_rcu(q_vector, rcu); 1020 } 1021 1022 /** 1023 * igb_reset_q_vector - Reset config for interrupt vector 1024 * @adapter: board private structure to initialize 1025 * @v_idx: Index of vector to be reset 1026 * 1027 * If NAPI is enabled it will delete any references to the 1028 * NAPI struct. This is preparation for igb_free_q_vector. 1029 **/ 1030 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1031 { 1032 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1033 1034 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1035 * allocated. So, q_vector is NULL so we should stop here. 1036 */ 1037 if (!q_vector) 1038 return; 1039 1040 if (q_vector->tx.ring) 1041 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1042 1043 if (q_vector->rx.ring) 1044 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1045 1046 netif_napi_del(&q_vector->napi); 1047 1048 } 1049 1050 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1051 { 1052 int v_idx = adapter->num_q_vectors; 1053 1054 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1055 pci_disable_msix(adapter->pdev); 1056 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1057 pci_disable_msi(adapter->pdev); 1058 1059 while (v_idx--) 1060 igb_reset_q_vector(adapter, v_idx); 1061 } 1062 1063 /** 1064 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1065 * @adapter: board private structure to initialize 1066 * 1067 * This function frees the memory allocated to the q_vectors. In addition if 1068 * NAPI is enabled it will delete any references to the NAPI struct prior 1069 * to freeing the q_vector. 1070 **/ 1071 static void igb_free_q_vectors(struct igb_adapter *adapter) 1072 { 1073 int v_idx = adapter->num_q_vectors; 1074 1075 adapter->num_tx_queues = 0; 1076 adapter->num_rx_queues = 0; 1077 adapter->num_q_vectors = 0; 1078 1079 while (v_idx--) { 1080 igb_reset_q_vector(adapter, v_idx); 1081 igb_free_q_vector(adapter, v_idx); 1082 } 1083 } 1084 1085 /** 1086 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1087 * @adapter: board private structure to initialize 1088 * 1089 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1090 * MSI-X interrupts allocated. 1091 */ 1092 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1093 { 1094 igb_free_q_vectors(adapter); 1095 igb_reset_interrupt_capability(adapter); 1096 } 1097 1098 /** 1099 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1100 * @adapter: board private structure to initialize 1101 * @msix: boolean value of MSIX capability 1102 * 1103 * Attempt to configure interrupts using the best available 1104 * capabilities of the hardware and kernel. 1105 **/ 1106 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1107 { 1108 int err; 1109 int numvecs, i; 1110 1111 if (!msix) 1112 goto msi_only; 1113 adapter->flags |= IGB_FLAG_HAS_MSIX; 1114 1115 /* Number of supported queues. */ 1116 adapter->num_rx_queues = adapter->rss_queues; 1117 if (adapter->vfs_allocated_count) 1118 adapter->num_tx_queues = 1; 1119 else 1120 adapter->num_tx_queues = adapter->rss_queues; 1121 1122 /* start with one vector for every Rx queue */ 1123 numvecs = adapter->num_rx_queues; 1124 1125 /* if Tx handler is separate add 1 for every Tx queue */ 1126 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1127 numvecs += adapter->num_tx_queues; 1128 1129 /* store the number of vectors reserved for queues */ 1130 adapter->num_q_vectors = numvecs; 1131 1132 /* add 1 vector for link status interrupts */ 1133 numvecs++; 1134 for (i = 0; i < numvecs; i++) 1135 adapter->msix_entries[i].entry = i; 1136 1137 err = pci_enable_msix_range(adapter->pdev, 1138 adapter->msix_entries, 1139 numvecs, 1140 numvecs); 1141 if (err > 0) 1142 return; 1143 1144 igb_reset_interrupt_capability(adapter); 1145 1146 /* If we can't do MSI-X, try MSI */ 1147 msi_only: 1148 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1149 #ifdef CONFIG_PCI_IOV 1150 /* disable SR-IOV for non MSI-X configurations */ 1151 if (adapter->vf_data) { 1152 struct e1000_hw *hw = &adapter->hw; 1153 /* disable iov and allow time for transactions to clear */ 1154 pci_disable_sriov(adapter->pdev); 1155 msleep(500); 1156 1157 kfree(adapter->vf_mac_list); 1158 adapter->vf_mac_list = NULL; 1159 kfree(adapter->vf_data); 1160 adapter->vf_data = NULL; 1161 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1162 wrfl(); 1163 msleep(100); 1164 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1165 } 1166 #endif 1167 adapter->vfs_allocated_count = 0; 1168 adapter->rss_queues = 1; 1169 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1170 adapter->num_rx_queues = 1; 1171 adapter->num_tx_queues = 1; 1172 adapter->num_q_vectors = 1; 1173 if (!pci_enable_msi(adapter->pdev)) 1174 adapter->flags |= IGB_FLAG_HAS_MSI; 1175 } 1176 1177 static void igb_add_ring(struct igb_ring *ring, 1178 struct igb_ring_container *head) 1179 { 1180 head->ring = ring; 1181 head->count++; 1182 } 1183 1184 /** 1185 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1186 * @adapter: board private structure to initialize 1187 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1188 * @v_idx: index of vector in adapter struct 1189 * @txr_count: total number of Tx rings to allocate 1190 * @txr_idx: index of first Tx ring to allocate 1191 * @rxr_count: total number of Rx rings to allocate 1192 * @rxr_idx: index of first Rx ring to allocate 1193 * 1194 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1195 **/ 1196 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1197 int v_count, int v_idx, 1198 int txr_count, int txr_idx, 1199 int rxr_count, int rxr_idx) 1200 { 1201 struct igb_q_vector *q_vector; 1202 struct igb_ring *ring; 1203 int ring_count, size; 1204 1205 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1206 if (txr_count > 1 || rxr_count > 1) 1207 return -ENOMEM; 1208 1209 ring_count = txr_count + rxr_count; 1210 size = sizeof(struct igb_q_vector) + 1211 (sizeof(struct igb_ring) * ring_count); 1212 1213 /* allocate q_vector and rings */ 1214 q_vector = adapter->q_vector[v_idx]; 1215 if (!q_vector) { 1216 q_vector = kzalloc(size, GFP_KERNEL); 1217 } else if (size > ksize(q_vector)) { 1218 kfree_rcu(q_vector, rcu); 1219 q_vector = kzalloc(size, GFP_KERNEL); 1220 } else { 1221 memset(q_vector, 0, size); 1222 } 1223 if (!q_vector) 1224 return -ENOMEM; 1225 1226 /* initialize NAPI */ 1227 netif_napi_add(adapter->netdev, &q_vector->napi, 1228 igb_poll, 64); 1229 1230 /* tie q_vector and adapter together */ 1231 adapter->q_vector[v_idx] = q_vector; 1232 q_vector->adapter = adapter; 1233 1234 /* initialize work limits */ 1235 q_vector->tx.work_limit = adapter->tx_work_limit; 1236 1237 /* initialize ITR configuration */ 1238 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1239 q_vector->itr_val = IGB_START_ITR; 1240 1241 /* initialize pointer to rings */ 1242 ring = q_vector->ring; 1243 1244 /* intialize ITR */ 1245 if (rxr_count) { 1246 /* rx or rx/tx vector */ 1247 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1248 q_vector->itr_val = adapter->rx_itr_setting; 1249 } else { 1250 /* tx only vector */ 1251 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1252 q_vector->itr_val = adapter->tx_itr_setting; 1253 } 1254 1255 if (txr_count) { 1256 /* assign generic ring traits */ 1257 ring->dev = &adapter->pdev->dev; 1258 ring->netdev = adapter->netdev; 1259 1260 /* configure backlink on ring */ 1261 ring->q_vector = q_vector; 1262 1263 /* update q_vector Tx values */ 1264 igb_add_ring(ring, &q_vector->tx); 1265 1266 /* For 82575, context index must be unique per ring. */ 1267 if (adapter->hw.mac.type == e1000_82575) 1268 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1269 1270 /* apply Tx specific ring traits */ 1271 ring->count = adapter->tx_ring_count; 1272 ring->queue_index = txr_idx; 1273 1274 u64_stats_init(&ring->tx_syncp); 1275 u64_stats_init(&ring->tx_syncp2); 1276 1277 /* assign ring to adapter */ 1278 adapter->tx_ring[txr_idx] = ring; 1279 1280 /* push pointer to next ring */ 1281 ring++; 1282 } 1283 1284 if (rxr_count) { 1285 /* assign generic ring traits */ 1286 ring->dev = &adapter->pdev->dev; 1287 ring->netdev = adapter->netdev; 1288 1289 /* configure backlink on ring */ 1290 ring->q_vector = q_vector; 1291 1292 /* update q_vector Rx values */ 1293 igb_add_ring(ring, &q_vector->rx); 1294 1295 /* set flag indicating ring supports SCTP checksum offload */ 1296 if (adapter->hw.mac.type >= e1000_82576) 1297 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1298 1299 /* On i350, i354, i210, and i211, loopback VLAN packets 1300 * have the tag byte-swapped. 1301 */ 1302 if (adapter->hw.mac.type >= e1000_i350) 1303 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1304 1305 /* apply Rx specific ring traits */ 1306 ring->count = adapter->rx_ring_count; 1307 ring->queue_index = rxr_idx; 1308 1309 u64_stats_init(&ring->rx_syncp); 1310 1311 /* assign ring to adapter */ 1312 adapter->rx_ring[rxr_idx] = ring; 1313 } 1314 1315 return 0; 1316 } 1317 1318 1319 /** 1320 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1321 * @adapter: board private structure to initialize 1322 * 1323 * We allocate one q_vector per queue interrupt. If allocation fails we 1324 * return -ENOMEM. 1325 **/ 1326 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1327 { 1328 int q_vectors = adapter->num_q_vectors; 1329 int rxr_remaining = adapter->num_rx_queues; 1330 int txr_remaining = adapter->num_tx_queues; 1331 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1332 int err; 1333 1334 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1335 for (; rxr_remaining; v_idx++) { 1336 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1337 0, 0, 1, rxr_idx); 1338 1339 if (err) 1340 goto err_out; 1341 1342 /* update counts and index */ 1343 rxr_remaining--; 1344 rxr_idx++; 1345 } 1346 } 1347 1348 for (; v_idx < q_vectors; v_idx++) { 1349 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1350 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1351 1352 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1353 tqpv, txr_idx, rqpv, rxr_idx); 1354 1355 if (err) 1356 goto err_out; 1357 1358 /* update counts and index */ 1359 rxr_remaining -= rqpv; 1360 txr_remaining -= tqpv; 1361 rxr_idx++; 1362 txr_idx++; 1363 } 1364 1365 return 0; 1366 1367 err_out: 1368 adapter->num_tx_queues = 0; 1369 adapter->num_rx_queues = 0; 1370 adapter->num_q_vectors = 0; 1371 1372 while (v_idx--) 1373 igb_free_q_vector(adapter, v_idx); 1374 1375 return -ENOMEM; 1376 } 1377 1378 /** 1379 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1380 * @adapter: board private structure to initialize 1381 * @msix: boolean value of MSIX capability 1382 * 1383 * This function initializes the interrupts and allocates all of the queues. 1384 **/ 1385 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1386 { 1387 struct pci_dev *pdev = adapter->pdev; 1388 int err; 1389 1390 igb_set_interrupt_capability(adapter, msix); 1391 1392 err = igb_alloc_q_vectors(adapter); 1393 if (err) { 1394 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1395 goto err_alloc_q_vectors; 1396 } 1397 1398 igb_cache_ring_register(adapter); 1399 1400 return 0; 1401 1402 err_alloc_q_vectors: 1403 igb_reset_interrupt_capability(adapter); 1404 return err; 1405 } 1406 1407 /** 1408 * igb_request_irq - initialize interrupts 1409 * @adapter: board private structure to initialize 1410 * 1411 * Attempts to configure interrupts using the best available 1412 * capabilities of the hardware and kernel. 1413 **/ 1414 static int igb_request_irq(struct igb_adapter *adapter) 1415 { 1416 struct net_device *netdev = adapter->netdev; 1417 struct pci_dev *pdev = adapter->pdev; 1418 int err = 0; 1419 1420 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1421 err = igb_request_msix(adapter); 1422 if (!err) 1423 goto request_done; 1424 /* fall back to MSI */ 1425 igb_free_all_tx_resources(adapter); 1426 igb_free_all_rx_resources(adapter); 1427 1428 igb_clear_interrupt_scheme(adapter); 1429 err = igb_init_interrupt_scheme(adapter, false); 1430 if (err) 1431 goto request_done; 1432 1433 igb_setup_all_tx_resources(adapter); 1434 igb_setup_all_rx_resources(adapter); 1435 igb_configure(adapter); 1436 } 1437 1438 igb_assign_vector(adapter->q_vector[0], 0); 1439 1440 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1441 err = request_irq(pdev->irq, igb_intr_msi, 0, 1442 netdev->name, adapter); 1443 if (!err) 1444 goto request_done; 1445 1446 /* fall back to legacy interrupts */ 1447 igb_reset_interrupt_capability(adapter); 1448 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1449 } 1450 1451 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1452 netdev->name, adapter); 1453 1454 if (err) 1455 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1456 err); 1457 1458 request_done: 1459 return err; 1460 } 1461 1462 static void igb_free_irq(struct igb_adapter *adapter) 1463 { 1464 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1465 int vector = 0, i; 1466 1467 free_irq(adapter->msix_entries[vector++].vector, adapter); 1468 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 free_irq(adapter->msix_entries[vector++].vector, 1471 adapter->q_vector[i]); 1472 } else { 1473 free_irq(adapter->pdev->irq, adapter); 1474 } 1475 } 1476 1477 /** 1478 * igb_irq_disable - Mask off interrupt generation on the NIC 1479 * @adapter: board private structure 1480 **/ 1481 static void igb_irq_disable(struct igb_adapter *adapter) 1482 { 1483 struct e1000_hw *hw = &adapter->hw; 1484 1485 /* we need to be careful when disabling interrupts. The VFs are also 1486 * mapped into these registers and so clearing the bits can cause 1487 * issues on the VF drivers so we only need to clear what we set 1488 */ 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 u32 regval = rd32(E1000_EIAM); 1491 1492 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1493 wr32(E1000_EIMC, adapter->eims_enable_mask); 1494 regval = rd32(E1000_EIAC); 1495 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1496 } 1497 1498 wr32(E1000_IAM, 0); 1499 wr32(E1000_IMC, ~0); 1500 wrfl(); 1501 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1502 int i; 1503 1504 for (i = 0; i < adapter->num_q_vectors; i++) 1505 synchronize_irq(adapter->msix_entries[i].vector); 1506 } else { 1507 synchronize_irq(adapter->pdev->irq); 1508 } 1509 } 1510 1511 /** 1512 * igb_irq_enable - Enable default interrupt generation settings 1513 * @adapter: board private structure 1514 **/ 1515 static void igb_irq_enable(struct igb_adapter *adapter) 1516 { 1517 struct e1000_hw *hw = &adapter->hw; 1518 1519 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1520 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1521 u32 regval = rd32(E1000_EIAC); 1522 1523 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1524 regval = rd32(E1000_EIAM); 1525 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1526 wr32(E1000_EIMS, adapter->eims_enable_mask); 1527 if (adapter->vfs_allocated_count) { 1528 wr32(E1000_MBVFIMR, 0xFF); 1529 ims |= E1000_IMS_VMMB; 1530 } 1531 wr32(E1000_IMS, ims); 1532 } else { 1533 wr32(E1000_IMS, IMS_ENABLE_MASK | 1534 E1000_IMS_DRSTA); 1535 wr32(E1000_IAM, IMS_ENABLE_MASK | 1536 E1000_IMS_DRSTA); 1537 } 1538 } 1539 1540 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1541 { 1542 struct e1000_hw *hw = &adapter->hw; 1543 u16 pf_id = adapter->vfs_allocated_count; 1544 u16 vid = adapter->hw.mng_cookie.vlan_id; 1545 u16 old_vid = adapter->mng_vlan_id; 1546 1547 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1548 /* add VID to filter table */ 1549 igb_vfta_set(hw, vid, pf_id, true, true); 1550 adapter->mng_vlan_id = vid; 1551 } else { 1552 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1553 } 1554 1555 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1556 (vid != old_vid) && 1557 !test_bit(old_vid, adapter->active_vlans)) { 1558 /* remove VID from filter table */ 1559 igb_vfta_set(hw, vid, pf_id, false, true); 1560 } 1561 } 1562 1563 /** 1564 * igb_release_hw_control - release control of the h/w to f/w 1565 * @adapter: address of board private structure 1566 * 1567 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1568 * For ASF and Pass Through versions of f/w this means that the 1569 * driver is no longer loaded. 1570 **/ 1571 static void igb_release_hw_control(struct igb_adapter *adapter) 1572 { 1573 struct e1000_hw *hw = &adapter->hw; 1574 u32 ctrl_ext; 1575 1576 /* Let firmware take over control of h/w */ 1577 ctrl_ext = rd32(E1000_CTRL_EXT); 1578 wr32(E1000_CTRL_EXT, 1579 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1580 } 1581 1582 /** 1583 * igb_get_hw_control - get control of the h/w from f/w 1584 * @adapter: address of board private structure 1585 * 1586 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1587 * For ASF and Pass Through versions of f/w this means that 1588 * the driver is loaded. 1589 **/ 1590 static void igb_get_hw_control(struct igb_adapter *adapter) 1591 { 1592 struct e1000_hw *hw = &adapter->hw; 1593 u32 ctrl_ext; 1594 1595 /* Let firmware know the driver has taken over */ 1596 ctrl_ext = rd32(E1000_CTRL_EXT); 1597 wr32(E1000_CTRL_EXT, 1598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1599 } 1600 1601 /** 1602 * igb_configure - configure the hardware for RX and TX 1603 * @adapter: private board structure 1604 **/ 1605 static void igb_configure(struct igb_adapter *adapter) 1606 { 1607 struct net_device *netdev = adapter->netdev; 1608 int i; 1609 1610 igb_get_hw_control(adapter); 1611 igb_set_rx_mode(netdev); 1612 1613 igb_restore_vlan(adapter); 1614 1615 igb_setup_tctl(adapter); 1616 igb_setup_mrqc(adapter); 1617 igb_setup_rctl(adapter); 1618 1619 igb_nfc_filter_restore(adapter); 1620 igb_configure_tx(adapter); 1621 igb_configure_rx(adapter); 1622 1623 igb_rx_fifo_flush_82575(&adapter->hw); 1624 1625 /* call igb_desc_unused which always leaves 1626 * at least 1 descriptor unused to make sure 1627 * next_to_use != next_to_clean 1628 */ 1629 for (i = 0; i < adapter->num_rx_queues; i++) { 1630 struct igb_ring *ring = adapter->rx_ring[i]; 1631 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1632 } 1633 } 1634 1635 /** 1636 * igb_power_up_link - Power up the phy/serdes link 1637 * @adapter: address of board private structure 1638 **/ 1639 void igb_power_up_link(struct igb_adapter *adapter) 1640 { 1641 igb_reset_phy(&adapter->hw); 1642 1643 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1644 igb_power_up_phy_copper(&adapter->hw); 1645 else 1646 igb_power_up_serdes_link_82575(&adapter->hw); 1647 1648 igb_setup_link(&adapter->hw); 1649 } 1650 1651 /** 1652 * igb_power_down_link - Power down the phy/serdes link 1653 * @adapter: address of board private structure 1654 */ 1655 static void igb_power_down_link(struct igb_adapter *adapter) 1656 { 1657 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1658 igb_power_down_phy_copper_82575(&adapter->hw); 1659 else 1660 igb_shutdown_serdes_link_82575(&adapter->hw); 1661 } 1662 1663 /** 1664 * Detect and switch function for Media Auto Sense 1665 * @adapter: address of the board private structure 1666 **/ 1667 static void igb_check_swap_media(struct igb_adapter *adapter) 1668 { 1669 struct e1000_hw *hw = &adapter->hw; 1670 u32 ctrl_ext, connsw; 1671 bool swap_now = false; 1672 1673 ctrl_ext = rd32(E1000_CTRL_EXT); 1674 connsw = rd32(E1000_CONNSW); 1675 1676 /* need to live swap if current media is copper and we have fiber/serdes 1677 * to go to. 1678 */ 1679 1680 if ((hw->phy.media_type == e1000_media_type_copper) && 1681 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1682 swap_now = true; 1683 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1684 /* copper signal takes time to appear */ 1685 if (adapter->copper_tries < 4) { 1686 adapter->copper_tries++; 1687 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1688 wr32(E1000_CONNSW, connsw); 1689 return; 1690 } else { 1691 adapter->copper_tries = 0; 1692 if ((connsw & E1000_CONNSW_PHYSD) && 1693 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1694 swap_now = true; 1695 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1696 wr32(E1000_CONNSW, connsw); 1697 } 1698 } 1699 } 1700 1701 if (!swap_now) 1702 return; 1703 1704 switch (hw->phy.media_type) { 1705 case e1000_media_type_copper: 1706 netdev_info(adapter->netdev, 1707 "MAS: changing media to fiber/serdes\n"); 1708 ctrl_ext |= 1709 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1710 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1711 adapter->copper_tries = 0; 1712 break; 1713 case e1000_media_type_internal_serdes: 1714 case e1000_media_type_fiber: 1715 netdev_info(adapter->netdev, 1716 "MAS: changing media to copper\n"); 1717 ctrl_ext &= 1718 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1719 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1720 break; 1721 default: 1722 /* shouldn't get here during regular operation */ 1723 netdev_err(adapter->netdev, 1724 "AMS: Invalid media type found, returning\n"); 1725 break; 1726 } 1727 wr32(E1000_CTRL_EXT, ctrl_ext); 1728 } 1729 1730 /** 1731 * igb_up - Open the interface and prepare it to handle traffic 1732 * @adapter: board private structure 1733 **/ 1734 int igb_up(struct igb_adapter *adapter) 1735 { 1736 struct e1000_hw *hw = &adapter->hw; 1737 int i; 1738 1739 /* hardware has been reset, we need to reload some things */ 1740 igb_configure(adapter); 1741 1742 clear_bit(__IGB_DOWN, &adapter->state); 1743 1744 for (i = 0; i < adapter->num_q_vectors; i++) 1745 napi_enable(&(adapter->q_vector[i]->napi)); 1746 1747 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1748 igb_configure_msix(adapter); 1749 else 1750 igb_assign_vector(adapter->q_vector[0], 0); 1751 1752 /* Clear any pending interrupts. */ 1753 rd32(E1000_ICR); 1754 igb_irq_enable(adapter); 1755 1756 /* notify VFs that reset has been completed */ 1757 if (adapter->vfs_allocated_count) { 1758 u32 reg_data = rd32(E1000_CTRL_EXT); 1759 1760 reg_data |= E1000_CTRL_EXT_PFRSTD; 1761 wr32(E1000_CTRL_EXT, reg_data); 1762 } 1763 1764 netif_tx_start_all_queues(adapter->netdev); 1765 1766 /* start the watchdog. */ 1767 hw->mac.get_link_status = 1; 1768 schedule_work(&adapter->watchdog_task); 1769 1770 if ((adapter->flags & IGB_FLAG_EEE) && 1771 (!hw->dev_spec._82575.eee_disable)) 1772 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1773 1774 return 0; 1775 } 1776 1777 void igb_down(struct igb_adapter *adapter) 1778 { 1779 struct net_device *netdev = adapter->netdev; 1780 struct e1000_hw *hw = &adapter->hw; 1781 u32 tctl, rctl; 1782 int i; 1783 1784 /* signal that we're down so the interrupt handler does not 1785 * reschedule our watchdog timer 1786 */ 1787 set_bit(__IGB_DOWN, &adapter->state); 1788 1789 /* disable receives in the hardware */ 1790 rctl = rd32(E1000_RCTL); 1791 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1792 /* flush and sleep below */ 1793 1794 netif_carrier_off(netdev); 1795 netif_tx_stop_all_queues(netdev); 1796 1797 /* disable transmits in the hardware */ 1798 tctl = rd32(E1000_TCTL); 1799 tctl &= ~E1000_TCTL_EN; 1800 wr32(E1000_TCTL, tctl); 1801 /* flush both disables and wait for them to finish */ 1802 wrfl(); 1803 usleep_range(10000, 11000); 1804 1805 igb_irq_disable(adapter); 1806 1807 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1808 1809 for (i = 0; i < adapter->num_q_vectors; i++) { 1810 if (adapter->q_vector[i]) { 1811 napi_synchronize(&adapter->q_vector[i]->napi); 1812 napi_disable(&adapter->q_vector[i]->napi); 1813 } 1814 } 1815 1816 del_timer_sync(&adapter->watchdog_timer); 1817 del_timer_sync(&adapter->phy_info_timer); 1818 1819 /* record the stats before reset*/ 1820 spin_lock(&adapter->stats64_lock); 1821 igb_update_stats(adapter); 1822 spin_unlock(&adapter->stats64_lock); 1823 1824 adapter->link_speed = 0; 1825 adapter->link_duplex = 0; 1826 1827 if (!pci_channel_offline(adapter->pdev)) 1828 igb_reset(adapter); 1829 1830 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1831 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1832 1833 igb_clean_all_tx_rings(adapter); 1834 igb_clean_all_rx_rings(adapter); 1835 #ifdef CONFIG_IGB_DCA 1836 1837 /* since we reset the hardware DCA settings were cleared */ 1838 igb_setup_dca(adapter); 1839 #endif 1840 } 1841 1842 void igb_reinit_locked(struct igb_adapter *adapter) 1843 { 1844 WARN_ON(in_interrupt()); 1845 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1846 usleep_range(1000, 2000); 1847 igb_down(adapter); 1848 igb_up(adapter); 1849 clear_bit(__IGB_RESETTING, &adapter->state); 1850 } 1851 1852 /** igb_enable_mas - Media Autosense re-enable after swap 1853 * 1854 * @adapter: adapter struct 1855 **/ 1856 static void igb_enable_mas(struct igb_adapter *adapter) 1857 { 1858 struct e1000_hw *hw = &adapter->hw; 1859 u32 connsw = rd32(E1000_CONNSW); 1860 1861 /* configure for SerDes media detect */ 1862 if ((hw->phy.media_type == e1000_media_type_copper) && 1863 (!(connsw & E1000_CONNSW_SERDESD))) { 1864 connsw |= E1000_CONNSW_ENRGSRC; 1865 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1866 wr32(E1000_CONNSW, connsw); 1867 wrfl(); 1868 } 1869 } 1870 1871 void igb_reset(struct igb_adapter *adapter) 1872 { 1873 struct pci_dev *pdev = adapter->pdev; 1874 struct e1000_hw *hw = &adapter->hw; 1875 struct e1000_mac_info *mac = &hw->mac; 1876 struct e1000_fc_info *fc = &hw->fc; 1877 u32 pba, hwm; 1878 1879 /* Repartition Pba for greater than 9k mtu 1880 * To take effect CTRL.RST is required. 1881 */ 1882 switch (mac->type) { 1883 case e1000_i350: 1884 case e1000_i354: 1885 case e1000_82580: 1886 pba = rd32(E1000_RXPBS); 1887 pba = igb_rxpbs_adjust_82580(pba); 1888 break; 1889 case e1000_82576: 1890 pba = rd32(E1000_RXPBS); 1891 pba &= E1000_RXPBS_SIZE_MASK_82576; 1892 break; 1893 case e1000_82575: 1894 case e1000_i210: 1895 case e1000_i211: 1896 default: 1897 pba = E1000_PBA_34K; 1898 break; 1899 } 1900 1901 if (mac->type == e1000_82575) { 1902 u32 min_rx_space, min_tx_space, needed_tx_space; 1903 1904 /* write Rx PBA so that hardware can report correct Tx PBA */ 1905 wr32(E1000_PBA, pba); 1906 1907 /* To maintain wire speed transmits, the Tx FIFO should be 1908 * large enough to accommodate two full transmit packets, 1909 * rounded up to the next 1KB and expressed in KB. Likewise, 1910 * the Rx FIFO should be large enough to accommodate at least 1911 * one full receive packet and is similarly rounded up and 1912 * expressed in KB. 1913 */ 1914 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1915 1916 /* The Tx FIFO also stores 16 bytes of information about the Tx 1917 * but don't include Ethernet FCS because hardware appends it. 1918 * We only need to round down to the nearest 512 byte block 1919 * count since the value we care about is 2 frames, not 1. 1920 */ 1921 min_tx_space = adapter->max_frame_size; 1922 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1923 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1924 1925 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1926 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1927 1928 /* If current Tx allocation is less than the min Tx FIFO size, 1929 * and the min Tx FIFO size is less than the current Rx FIFO 1930 * allocation, take space away from current Rx allocation. 1931 */ 1932 if (needed_tx_space < pba) { 1933 pba -= needed_tx_space; 1934 1935 /* if short on Rx space, Rx wins and must trump Tx 1936 * adjustment 1937 */ 1938 if (pba < min_rx_space) 1939 pba = min_rx_space; 1940 } 1941 1942 /* adjust PBA for jumbo frames */ 1943 wr32(E1000_PBA, pba); 1944 } 1945 1946 /* flow control settings 1947 * The high water mark must be low enough to fit one full frame 1948 * after transmitting the pause frame. As such we must have enough 1949 * space to allow for us to complete our current transmit and then 1950 * receive the frame that is in progress from the link partner. 1951 * Set it to: 1952 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1953 */ 1954 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1955 1956 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1957 fc->low_water = fc->high_water - 16; 1958 fc->pause_time = 0xFFFF; 1959 fc->send_xon = 1; 1960 fc->current_mode = fc->requested_mode; 1961 1962 /* disable receive for all VFs and wait one second */ 1963 if (adapter->vfs_allocated_count) { 1964 int i; 1965 1966 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1967 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1968 1969 /* ping all the active vfs to let them know we are going down */ 1970 igb_ping_all_vfs(adapter); 1971 1972 /* disable transmits and receives */ 1973 wr32(E1000_VFRE, 0); 1974 wr32(E1000_VFTE, 0); 1975 } 1976 1977 /* Allow time for pending master requests to run */ 1978 hw->mac.ops.reset_hw(hw); 1979 wr32(E1000_WUC, 0); 1980 1981 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1982 /* need to resetup here after media swap */ 1983 adapter->ei.get_invariants(hw); 1984 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1985 } 1986 if ((mac->type == e1000_82575) && 1987 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1988 igb_enable_mas(adapter); 1989 } 1990 if (hw->mac.ops.init_hw(hw)) 1991 dev_err(&pdev->dev, "Hardware Error\n"); 1992 1993 /* RAR registers were cleared during init_hw, clear mac table */ 1994 igb_flush_mac_table(adapter); 1995 __dev_uc_unsync(adapter->netdev, NULL); 1996 1997 /* Recover default RAR entry */ 1998 igb_set_default_mac_filter(adapter); 1999 2000 /* Flow control settings reset on hardware reset, so guarantee flow 2001 * control is off when forcing speed. 2002 */ 2003 if (!hw->mac.autoneg) 2004 igb_force_mac_fc(hw); 2005 2006 igb_init_dmac(adapter, pba); 2007 #ifdef CONFIG_IGB_HWMON 2008 /* Re-initialize the thermal sensor on i350 devices. */ 2009 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2010 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2011 /* If present, re-initialize the external thermal sensor 2012 * interface. 2013 */ 2014 if (adapter->ets) 2015 mac->ops.init_thermal_sensor_thresh(hw); 2016 } 2017 } 2018 #endif 2019 /* Re-establish EEE setting */ 2020 if (hw->phy.media_type == e1000_media_type_copper) { 2021 switch (mac->type) { 2022 case e1000_i350: 2023 case e1000_i210: 2024 case e1000_i211: 2025 igb_set_eee_i350(hw, true, true); 2026 break; 2027 case e1000_i354: 2028 igb_set_eee_i354(hw, true, true); 2029 break; 2030 default: 2031 break; 2032 } 2033 } 2034 if (!netif_running(adapter->netdev)) 2035 igb_power_down_link(adapter); 2036 2037 igb_update_mng_vlan(adapter); 2038 2039 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2040 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2041 2042 /* Re-enable PTP, where applicable. */ 2043 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2044 igb_ptp_reset(adapter); 2045 2046 igb_get_phy_info(hw); 2047 } 2048 2049 static netdev_features_t igb_fix_features(struct net_device *netdev, 2050 netdev_features_t features) 2051 { 2052 /* Since there is no support for separate Rx/Tx vlan accel 2053 * enable/disable make sure Tx flag is always in same state as Rx. 2054 */ 2055 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2056 features |= NETIF_F_HW_VLAN_CTAG_TX; 2057 else 2058 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2059 2060 return features; 2061 } 2062 2063 static int igb_set_features(struct net_device *netdev, 2064 netdev_features_t features) 2065 { 2066 netdev_features_t changed = netdev->features ^ features; 2067 struct igb_adapter *adapter = netdev_priv(netdev); 2068 2069 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2070 igb_vlan_mode(netdev, features); 2071 2072 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2073 return 0; 2074 2075 if (!(features & NETIF_F_NTUPLE)) { 2076 struct hlist_node *node2; 2077 struct igb_nfc_filter *rule; 2078 2079 spin_lock(&adapter->nfc_lock); 2080 hlist_for_each_entry_safe(rule, node2, 2081 &adapter->nfc_filter_list, nfc_node) { 2082 igb_erase_filter(adapter, rule); 2083 hlist_del(&rule->nfc_node); 2084 kfree(rule); 2085 } 2086 spin_unlock(&adapter->nfc_lock); 2087 adapter->nfc_filter_count = 0; 2088 } 2089 2090 netdev->features = features; 2091 2092 if (netif_running(netdev)) 2093 igb_reinit_locked(adapter); 2094 else 2095 igb_reset(adapter); 2096 2097 return 0; 2098 } 2099 2100 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2101 struct net_device *dev, 2102 const unsigned char *addr, u16 vid, 2103 u16 flags) 2104 { 2105 /* guarantee we can provide a unique filter for the unicast address */ 2106 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2107 struct igb_adapter *adapter = netdev_priv(dev); 2108 int vfn = adapter->vfs_allocated_count; 2109 2110 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2111 return -ENOMEM; 2112 } 2113 2114 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2115 } 2116 2117 #define IGB_MAX_MAC_HDR_LEN 127 2118 #define IGB_MAX_NETWORK_HDR_LEN 511 2119 2120 static netdev_features_t 2121 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2122 netdev_features_t features) 2123 { 2124 unsigned int network_hdr_len, mac_hdr_len; 2125 2126 /* Make certain the headers can be described by a context descriptor */ 2127 mac_hdr_len = skb_network_header(skb) - skb->data; 2128 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2129 return features & ~(NETIF_F_HW_CSUM | 2130 NETIF_F_SCTP_CRC | 2131 NETIF_F_HW_VLAN_CTAG_TX | 2132 NETIF_F_TSO | 2133 NETIF_F_TSO6); 2134 2135 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2136 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2137 return features & ~(NETIF_F_HW_CSUM | 2138 NETIF_F_SCTP_CRC | 2139 NETIF_F_TSO | 2140 NETIF_F_TSO6); 2141 2142 /* We can only support IPV4 TSO in tunnels if we can mangle the 2143 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2144 */ 2145 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2146 features &= ~NETIF_F_TSO; 2147 2148 return features; 2149 } 2150 2151 static const struct net_device_ops igb_netdev_ops = { 2152 .ndo_open = igb_open, 2153 .ndo_stop = igb_close, 2154 .ndo_start_xmit = igb_xmit_frame, 2155 .ndo_get_stats64 = igb_get_stats64, 2156 .ndo_set_rx_mode = igb_set_rx_mode, 2157 .ndo_set_mac_address = igb_set_mac, 2158 .ndo_change_mtu = igb_change_mtu, 2159 .ndo_do_ioctl = igb_ioctl, 2160 .ndo_tx_timeout = igb_tx_timeout, 2161 .ndo_validate_addr = eth_validate_addr, 2162 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2163 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2164 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2165 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2166 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2167 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2168 .ndo_get_vf_config = igb_ndo_get_vf_config, 2169 #ifdef CONFIG_NET_POLL_CONTROLLER 2170 .ndo_poll_controller = igb_netpoll, 2171 #endif 2172 .ndo_fix_features = igb_fix_features, 2173 .ndo_set_features = igb_set_features, 2174 .ndo_fdb_add = igb_ndo_fdb_add, 2175 .ndo_features_check = igb_features_check, 2176 }; 2177 2178 /** 2179 * igb_set_fw_version - Configure version string for ethtool 2180 * @adapter: adapter struct 2181 **/ 2182 void igb_set_fw_version(struct igb_adapter *adapter) 2183 { 2184 struct e1000_hw *hw = &adapter->hw; 2185 struct e1000_fw_version fw; 2186 2187 igb_get_fw_version(hw, &fw); 2188 2189 switch (hw->mac.type) { 2190 case e1000_i210: 2191 case e1000_i211: 2192 if (!(igb_get_flash_presence_i210(hw))) { 2193 snprintf(adapter->fw_version, 2194 sizeof(adapter->fw_version), 2195 "%2d.%2d-%d", 2196 fw.invm_major, fw.invm_minor, 2197 fw.invm_img_type); 2198 break; 2199 } 2200 /* fall through */ 2201 default: 2202 /* if option is rom valid, display its version too */ 2203 if (fw.or_valid) { 2204 snprintf(adapter->fw_version, 2205 sizeof(adapter->fw_version), 2206 "%d.%d, 0x%08x, %d.%d.%d", 2207 fw.eep_major, fw.eep_minor, fw.etrack_id, 2208 fw.or_major, fw.or_build, fw.or_patch); 2209 /* no option rom */ 2210 } else if (fw.etrack_id != 0X0000) { 2211 snprintf(adapter->fw_version, 2212 sizeof(adapter->fw_version), 2213 "%d.%d, 0x%08x", 2214 fw.eep_major, fw.eep_minor, fw.etrack_id); 2215 } else { 2216 snprintf(adapter->fw_version, 2217 sizeof(adapter->fw_version), 2218 "%d.%d.%d", 2219 fw.eep_major, fw.eep_minor, fw.eep_build); 2220 } 2221 break; 2222 } 2223 } 2224 2225 /** 2226 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2227 * 2228 * @adapter: adapter struct 2229 **/ 2230 static void igb_init_mas(struct igb_adapter *adapter) 2231 { 2232 struct e1000_hw *hw = &adapter->hw; 2233 u16 eeprom_data; 2234 2235 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2236 switch (hw->bus.func) { 2237 case E1000_FUNC_0: 2238 if (eeprom_data & IGB_MAS_ENABLE_0) { 2239 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2240 netdev_info(adapter->netdev, 2241 "MAS: Enabling Media Autosense for port %d\n", 2242 hw->bus.func); 2243 } 2244 break; 2245 case E1000_FUNC_1: 2246 if (eeprom_data & IGB_MAS_ENABLE_1) { 2247 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2248 netdev_info(adapter->netdev, 2249 "MAS: Enabling Media Autosense for port %d\n", 2250 hw->bus.func); 2251 } 2252 break; 2253 case E1000_FUNC_2: 2254 if (eeprom_data & IGB_MAS_ENABLE_2) { 2255 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2256 netdev_info(adapter->netdev, 2257 "MAS: Enabling Media Autosense for port %d\n", 2258 hw->bus.func); 2259 } 2260 break; 2261 case E1000_FUNC_3: 2262 if (eeprom_data & IGB_MAS_ENABLE_3) { 2263 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2264 netdev_info(adapter->netdev, 2265 "MAS: Enabling Media Autosense for port %d\n", 2266 hw->bus.func); 2267 } 2268 break; 2269 default: 2270 /* Shouldn't get here */ 2271 netdev_err(adapter->netdev, 2272 "MAS: Invalid port configuration, returning\n"); 2273 break; 2274 } 2275 } 2276 2277 /** 2278 * igb_init_i2c - Init I2C interface 2279 * @adapter: pointer to adapter structure 2280 **/ 2281 static s32 igb_init_i2c(struct igb_adapter *adapter) 2282 { 2283 s32 status = 0; 2284 2285 /* I2C interface supported on i350 devices */ 2286 if (adapter->hw.mac.type != e1000_i350) 2287 return 0; 2288 2289 /* Initialize the i2c bus which is controlled by the registers. 2290 * This bus will use the i2c_algo_bit structue that implements 2291 * the protocol through toggling of the 4 bits in the register. 2292 */ 2293 adapter->i2c_adap.owner = THIS_MODULE; 2294 adapter->i2c_algo = igb_i2c_algo; 2295 adapter->i2c_algo.data = adapter; 2296 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2297 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2298 strlcpy(adapter->i2c_adap.name, "igb BB", 2299 sizeof(adapter->i2c_adap.name)); 2300 status = i2c_bit_add_bus(&adapter->i2c_adap); 2301 return status; 2302 } 2303 2304 /** 2305 * igb_probe - Device Initialization Routine 2306 * @pdev: PCI device information struct 2307 * @ent: entry in igb_pci_tbl 2308 * 2309 * Returns 0 on success, negative on failure 2310 * 2311 * igb_probe initializes an adapter identified by a pci_dev structure. 2312 * The OS initialization, configuring of the adapter private structure, 2313 * and a hardware reset occur. 2314 **/ 2315 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2316 { 2317 struct net_device *netdev; 2318 struct igb_adapter *adapter; 2319 struct e1000_hw *hw; 2320 u16 eeprom_data = 0; 2321 s32 ret_val; 2322 static int global_quad_port_a; /* global quad port a indication */ 2323 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2324 int err, pci_using_dac; 2325 u8 part_str[E1000_PBANUM_LENGTH]; 2326 2327 /* Catch broken hardware that put the wrong VF device ID in 2328 * the PCIe SR-IOV capability. 2329 */ 2330 if (pdev->is_virtfn) { 2331 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2332 pci_name(pdev), pdev->vendor, pdev->device); 2333 return -EINVAL; 2334 } 2335 2336 err = pci_enable_device_mem(pdev); 2337 if (err) 2338 return err; 2339 2340 pci_using_dac = 0; 2341 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2342 if (!err) { 2343 pci_using_dac = 1; 2344 } else { 2345 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2346 if (err) { 2347 dev_err(&pdev->dev, 2348 "No usable DMA configuration, aborting\n"); 2349 goto err_dma; 2350 } 2351 } 2352 2353 err = pci_request_mem_regions(pdev, igb_driver_name); 2354 if (err) 2355 goto err_pci_reg; 2356 2357 pci_enable_pcie_error_reporting(pdev); 2358 2359 pci_set_master(pdev); 2360 pci_save_state(pdev); 2361 2362 err = -ENOMEM; 2363 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2364 IGB_MAX_TX_QUEUES); 2365 if (!netdev) 2366 goto err_alloc_etherdev; 2367 2368 SET_NETDEV_DEV(netdev, &pdev->dev); 2369 2370 pci_set_drvdata(pdev, netdev); 2371 adapter = netdev_priv(netdev); 2372 adapter->netdev = netdev; 2373 adapter->pdev = pdev; 2374 hw = &adapter->hw; 2375 hw->back = adapter; 2376 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2377 2378 err = -EIO; 2379 adapter->io_addr = pci_iomap(pdev, 0, 0); 2380 if (!adapter->io_addr) 2381 goto err_ioremap; 2382 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2383 hw->hw_addr = adapter->io_addr; 2384 2385 netdev->netdev_ops = &igb_netdev_ops; 2386 igb_set_ethtool_ops(netdev); 2387 netdev->watchdog_timeo = 5 * HZ; 2388 2389 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2390 2391 netdev->mem_start = pci_resource_start(pdev, 0); 2392 netdev->mem_end = pci_resource_end(pdev, 0); 2393 2394 /* PCI config space info */ 2395 hw->vendor_id = pdev->vendor; 2396 hw->device_id = pdev->device; 2397 hw->revision_id = pdev->revision; 2398 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2399 hw->subsystem_device_id = pdev->subsystem_device; 2400 2401 /* Copy the default MAC, PHY and NVM function pointers */ 2402 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2403 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2404 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2405 /* Initialize skew-specific constants */ 2406 err = ei->get_invariants(hw); 2407 if (err) 2408 goto err_sw_init; 2409 2410 /* setup the private structure */ 2411 err = igb_sw_init(adapter); 2412 if (err) 2413 goto err_sw_init; 2414 2415 igb_get_bus_info_pcie(hw); 2416 2417 hw->phy.autoneg_wait_to_complete = false; 2418 2419 /* Copper options */ 2420 if (hw->phy.media_type == e1000_media_type_copper) { 2421 hw->phy.mdix = AUTO_ALL_MODES; 2422 hw->phy.disable_polarity_correction = false; 2423 hw->phy.ms_type = e1000_ms_hw_default; 2424 } 2425 2426 if (igb_check_reset_block(hw)) 2427 dev_info(&pdev->dev, 2428 "PHY reset is blocked due to SOL/IDER session.\n"); 2429 2430 /* features is initialized to 0 in allocation, it might have bits 2431 * set by igb_sw_init so we should use an or instead of an 2432 * assignment. 2433 */ 2434 netdev->features |= NETIF_F_SG | 2435 NETIF_F_TSO | 2436 NETIF_F_TSO6 | 2437 NETIF_F_RXHASH | 2438 NETIF_F_RXCSUM | 2439 NETIF_F_HW_CSUM; 2440 2441 if (hw->mac.type >= e1000_82576) 2442 netdev->features |= NETIF_F_SCTP_CRC; 2443 2444 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2445 NETIF_F_GSO_GRE_CSUM | \ 2446 NETIF_F_GSO_IPXIP4 | \ 2447 NETIF_F_GSO_IPXIP6 | \ 2448 NETIF_F_GSO_UDP_TUNNEL | \ 2449 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2450 2451 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2452 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2453 2454 /* copy netdev features into list of user selectable features */ 2455 netdev->hw_features |= netdev->features | 2456 NETIF_F_HW_VLAN_CTAG_RX | 2457 NETIF_F_HW_VLAN_CTAG_TX | 2458 NETIF_F_RXALL; 2459 2460 if (hw->mac.type >= e1000_i350) 2461 netdev->hw_features |= NETIF_F_NTUPLE; 2462 2463 if (pci_using_dac) 2464 netdev->features |= NETIF_F_HIGHDMA; 2465 2466 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2467 netdev->mpls_features |= NETIF_F_HW_CSUM; 2468 netdev->hw_enc_features |= netdev->vlan_features; 2469 2470 /* set this bit last since it cannot be part of vlan_features */ 2471 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2472 NETIF_F_HW_VLAN_CTAG_RX | 2473 NETIF_F_HW_VLAN_CTAG_TX; 2474 2475 netdev->priv_flags |= IFF_SUPP_NOFCS; 2476 2477 netdev->priv_flags |= IFF_UNICAST_FLT; 2478 2479 /* MTU range: 68 - 9216 */ 2480 netdev->min_mtu = ETH_MIN_MTU; 2481 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2482 2483 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2484 2485 /* before reading the NVM, reset the controller to put the device in a 2486 * known good starting state 2487 */ 2488 hw->mac.ops.reset_hw(hw); 2489 2490 /* make sure the NVM is good , i211/i210 parts can have special NVM 2491 * that doesn't contain a checksum 2492 */ 2493 switch (hw->mac.type) { 2494 case e1000_i210: 2495 case e1000_i211: 2496 if (igb_get_flash_presence_i210(hw)) { 2497 if (hw->nvm.ops.validate(hw) < 0) { 2498 dev_err(&pdev->dev, 2499 "The NVM Checksum Is Not Valid\n"); 2500 err = -EIO; 2501 goto err_eeprom; 2502 } 2503 } 2504 break; 2505 default: 2506 if (hw->nvm.ops.validate(hw) < 0) { 2507 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2508 err = -EIO; 2509 goto err_eeprom; 2510 } 2511 break; 2512 } 2513 2514 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2515 /* copy the MAC address out of the NVM */ 2516 if (hw->mac.ops.read_mac_addr(hw)) 2517 dev_err(&pdev->dev, "NVM Read Error\n"); 2518 } 2519 2520 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2521 2522 if (!is_valid_ether_addr(netdev->dev_addr)) { 2523 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2524 err = -EIO; 2525 goto err_eeprom; 2526 } 2527 2528 igb_set_default_mac_filter(adapter); 2529 2530 /* get firmware version for ethtool -i */ 2531 igb_set_fw_version(adapter); 2532 2533 /* configure RXPBSIZE and TXPBSIZE */ 2534 if (hw->mac.type == e1000_i210) { 2535 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2536 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2537 } 2538 2539 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2540 (unsigned long) adapter); 2541 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2542 (unsigned long) adapter); 2543 2544 INIT_WORK(&adapter->reset_task, igb_reset_task); 2545 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2546 2547 /* Initialize link properties that are user-changeable */ 2548 adapter->fc_autoneg = true; 2549 hw->mac.autoneg = true; 2550 hw->phy.autoneg_advertised = 0x2f; 2551 2552 hw->fc.requested_mode = e1000_fc_default; 2553 hw->fc.current_mode = e1000_fc_default; 2554 2555 igb_validate_mdi_setting(hw); 2556 2557 /* By default, support wake on port A */ 2558 if (hw->bus.func == 0) 2559 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2560 2561 /* Check the NVM for wake support on non-port A ports */ 2562 if (hw->mac.type >= e1000_82580) 2563 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2564 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2565 &eeprom_data); 2566 else if (hw->bus.func == 1) 2567 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2568 2569 if (eeprom_data & IGB_EEPROM_APME) 2570 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2571 2572 /* now that we have the eeprom settings, apply the special cases where 2573 * the eeprom may be wrong or the board simply won't support wake on 2574 * lan on a particular port 2575 */ 2576 switch (pdev->device) { 2577 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2578 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2579 break; 2580 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2581 case E1000_DEV_ID_82576_FIBER: 2582 case E1000_DEV_ID_82576_SERDES: 2583 /* Wake events only supported on port A for dual fiber 2584 * regardless of eeprom setting 2585 */ 2586 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2587 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2588 break; 2589 case E1000_DEV_ID_82576_QUAD_COPPER: 2590 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2591 /* if quad port adapter, disable WoL on all but port A */ 2592 if (global_quad_port_a != 0) 2593 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2594 else 2595 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2596 /* Reset for multiple quad port adapters */ 2597 if (++global_quad_port_a == 4) 2598 global_quad_port_a = 0; 2599 break; 2600 default: 2601 /* If the device can't wake, don't set software support */ 2602 if (!device_can_wakeup(&adapter->pdev->dev)) 2603 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2604 } 2605 2606 /* initialize the wol settings based on the eeprom settings */ 2607 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2608 adapter->wol |= E1000_WUFC_MAG; 2609 2610 /* Some vendors want WoL disabled by default, but still supported */ 2611 if ((hw->mac.type == e1000_i350) && 2612 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2613 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2614 adapter->wol = 0; 2615 } 2616 2617 /* Some vendors want the ability to Use the EEPROM setting as 2618 * enable/disable only, and not for capability 2619 */ 2620 if (((hw->mac.type == e1000_i350) || 2621 (hw->mac.type == e1000_i354)) && 2622 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2623 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2624 adapter->wol = 0; 2625 } 2626 if (hw->mac.type == e1000_i350) { 2627 if (((pdev->subsystem_device == 0x5001) || 2628 (pdev->subsystem_device == 0x5002)) && 2629 (hw->bus.func == 0)) { 2630 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2631 adapter->wol = 0; 2632 } 2633 if (pdev->subsystem_device == 0x1F52) 2634 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2635 } 2636 2637 device_set_wakeup_enable(&adapter->pdev->dev, 2638 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2639 2640 /* reset the hardware with the new settings */ 2641 igb_reset(adapter); 2642 2643 /* Init the I2C interface */ 2644 err = igb_init_i2c(adapter); 2645 if (err) { 2646 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2647 goto err_eeprom; 2648 } 2649 2650 /* let the f/w know that the h/w is now under the control of the 2651 * driver. 2652 */ 2653 igb_get_hw_control(adapter); 2654 2655 strcpy(netdev->name, "eth%d"); 2656 err = register_netdev(netdev); 2657 if (err) 2658 goto err_register; 2659 2660 /* carrier off reporting is important to ethtool even BEFORE open */ 2661 netif_carrier_off(netdev); 2662 2663 #ifdef CONFIG_IGB_DCA 2664 if (dca_add_requester(&pdev->dev) == 0) { 2665 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2666 dev_info(&pdev->dev, "DCA enabled\n"); 2667 igb_setup_dca(adapter); 2668 } 2669 2670 #endif 2671 #ifdef CONFIG_IGB_HWMON 2672 /* Initialize the thermal sensor on i350 devices. */ 2673 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2674 u16 ets_word; 2675 2676 /* Read the NVM to determine if this i350 device supports an 2677 * external thermal sensor. 2678 */ 2679 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2680 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2681 adapter->ets = true; 2682 else 2683 adapter->ets = false; 2684 if (igb_sysfs_init(adapter)) 2685 dev_err(&pdev->dev, 2686 "failed to allocate sysfs resources\n"); 2687 } else { 2688 adapter->ets = false; 2689 } 2690 #endif 2691 /* Check if Media Autosense is enabled */ 2692 adapter->ei = *ei; 2693 if (hw->dev_spec._82575.mas_capable) 2694 igb_init_mas(adapter); 2695 2696 /* do hw tstamp init after resetting */ 2697 igb_ptp_init(adapter); 2698 2699 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2700 /* print bus type/speed/width info, not applicable to i354 */ 2701 if (hw->mac.type != e1000_i354) { 2702 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2703 netdev->name, 2704 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2705 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2706 "unknown"), 2707 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2708 "Width x4" : 2709 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2710 "Width x2" : 2711 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2712 "Width x1" : "unknown"), netdev->dev_addr); 2713 } 2714 2715 if ((hw->mac.type >= e1000_i210 || 2716 igb_get_flash_presence_i210(hw))) { 2717 ret_val = igb_read_part_string(hw, part_str, 2718 E1000_PBANUM_LENGTH); 2719 } else { 2720 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2721 } 2722 2723 if (ret_val) 2724 strcpy(part_str, "Unknown"); 2725 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2726 dev_info(&pdev->dev, 2727 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2728 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2729 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2730 adapter->num_rx_queues, adapter->num_tx_queues); 2731 if (hw->phy.media_type == e1000_media_type_copper) { 2732 switch (hw->mac.type) { 2733 case e1000_i350: 2734 case e1000_i210: 2735 case e1000_i211: 2736 /* Enable EEE for internal copper PHY devices */ 2737 err = igb_set_eee_i350(hw, true, true); 2738 if ((!err) && 2739 (!hw->dev_spec._82575.eee_disable)) { 2740 adapter->eee_advert = 2741 MDIO_EEE_100TX | MDIO_EEE_1000T; 2742 adapter->flags |= IGB_FLAG_EEE; 2743 } 2744 break; 2745 case e1000_i354: 2746 if ((rd32(E1000_CTRL_EXT) & 2747 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2748 err = igb_set_eee_i354(hw, true, true); 2749 if ((!err) && 2750 (!hw->dev_spec._82575.eee_disable)) { 2751 adapter->eee_advert = 2752 MDIO_EEE_100TX | MDIO_EEE_1000T; 2753 adapter->flags |= IGB_FLAG_EEE; 2754 } 2755 } 2756 break; 2757 default: 2758 break; 2759 } 2760 } 2761 pm_runtime_put_noidle(&pdev->dev); 2762 return 0; 2763 2764 err_register: 2765 igb_release_hw_control(adapter); 2766 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2767 err_eeprom: 2768 if (!igb_check_reset_block(hw)) 2769 igb_reset_phy(hw); 2770 2771 if (hw->flash_address) 2772 iounmap(hw->flash_address); 2773 err_sw_init: 2774 kfree(adapter->mac_table); 2775 kfree(adapter->shadow_vfta); 2776 igb_clear_interrupt_scheme(adapter); 2777 #ifdef CONFIG_PCI_IOV 2778 igb_disable_sriov(pdev); 2779 #endif 2780 pci_iounmap(pdev, adapter->io_addr); 2781 err_ioremap: 2782 free_netdev(netdev); 2783 err_alloc_etherdev: 2784 pci_release_mem_regions(pdev); 2785 err_pci_reg: 2786 err_dma: 2787 pci_disable_device(pdev); 2788 return err; 2789 } 2790 2791 #ifdef CONFIG_PCI_IOV 2792 static int igb_disable_sriov(struct pci_dev *pdev) 2793 { 2794 struct net_device *netdev = pci_get_drvdata(pdev); 2795 struct igb_adapter *adapter = netdev_priv(netdev); 2796 struct e1000_hw *hw = &adapter->hw; 2797 2798 /* reclaim resources allocated to VFs */ 2799 if (adapter->vf_data) { 2800 /* disable iov and allow time for transactions to clear */ 2801 if (pci_vfs_assigned(pdev)) { 2802 dev_warn(&pdev->dev, 2803 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2804 return -EPERM; 2805 } else { 2806 pci_disable_sriov(pdev); 2807 msleep(500); 2808 } 2809 2810 kfree(adapter->vf_mac_list); 2811 adapter->vf_mac_list = NULL; 2812 kfree(adapter->vf_data); 2813 adapter->vf_data = NULL; 2814 adapter->vfs_allocated_count = 0; 2815 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2816 wrfl(); 2817 msleep(100); 2818 dev_info(&pdev->dev, "IOV Disabled\n"); 2819 2820 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2821 adapter->flags |= IGB_FLAG_DMAC; 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2828 { 2829 struct net_device *netdev = pci_get_drvdata(pdev); 2830 struct igb_adapter *adapter = netdev_priv(netdev); 2831 int old_vfs = pci_num_vf(pdev); 2832 struct vf_mac_filter *mac_list; 2833 int err = 0; 2834 int num_vf_mac_filters, i; 2835 2836 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2837 err = -EPERM; 2838 goto out; 2839 } 2840 if (!num_vfs) 2841 goto out; 2842 2843 if (old_vfs) { 2844 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2845 old_vfs, max_vfs); 2846 adapter->vfs_allocated_count = old_vfs; 2847 } else 2848 adapter->vfs_allocated_count = num_vfs; 2849 2850 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2851 sizeof(struct vf_data_storage), GFP_KERNEL); 2852 2853 /* if allocation failed then we do not support SR-IOV */ 2854 if (!adapter->vf_data) { 2855 adapter->vfs_allocated_count = 0; 2856 dev_err(&pdev->dev, 2857 "Unable to allocate memory for VF Data Storage\n"); 2858 err = -ENOMEM; 2859 goto out; 2860 } 2861 2862 /* Due to the limited number of RAR entries calculate potential 2863 * number of MAC filters available for the VFs. Reserve entries 2864 * for PF default MAC, PF MAC filters and at least one RAR entry 2865 * for each VF for VF MAC. 2866 */ 2867 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 2868 (1 + IGB_PF_MAC_FILTERS_RESERVED + 2869 adapter->vfs_allocated_count); 2870 2871 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 2872 sizeof(struct vf_mac_filter), 2873 GFP_KERNEL); 2874 2875 mac_list = adapter->vf_mac_list; 2876 INIT_LIST_HEAD(&adapter->vf_macs.l); 2877 2878 if (adapter->vf_mac_list) { 2879 /* Initialize list of VF MAC filters */ 2880 for (i = 0; i < num_vf_mac_filters; i++) { 2881 mac_list->vf = -1; 2882 mac_list->free = true; 2883 list_add(&mac_list->l, &adapter->vf_macs.l); 2884 mac_list++; 2885 } 2886 } else { 2887 /* If we could not allocate memory for the VF MAC filters 2888 * we can continue without this feature but warn user. 2889 */ 2890 dev_err(&pdev->dev, 2891 "Unable to allocate memory for VF MAC filter list\n"); 2892 } 2893 2894 /* only call pci_enable_sriov() if no VFs are allocated already */ 2895 if (!old_vfs) { 2896 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2897 if (err) 2898 goto err_out; 2899 } 2900 dev_info(&pdev->dev, "%d VFs allocated\n", 2901 adapter->vfs_allocated_count); 2902 for (i = 0; i < adapter->vfs_allocated_count; i++) 2903 igb_vf_configure(adapter, i); 2904 2905 /* DMA Coalescing is not supported in IOV mode. */ 2906 adapter->flags &= ~IGB_FLAG_DMAC; 2907 goto out; 2908 2909 err_out: 2910 kfree(adapter->vf_mac_list); 2911 adapter->vf_mac_list = NULL; 2912 kfree(adapter->vf_data); 2913 adapter->vf_data = NULL; 2914 adapter->vfs_allocated_count = 0; 2915 out: 2916 return err; 2917 } 2918 2919 #endif 2920 /** 2921 * igb_remove_i2c - Cleanup I2C interface 2922 * @adapter: pointer to adapter structure 2923 **/ 2924 static void igb_remove_i2c(struct igb_adapter *adapter) 2925 { 2926 /* free the adapter bus structure */ 2927 i2c_del_adapter(&adapter->i2c_adap); 2928 } 2929 2930 /** 2931 * igb_remove - Device Removal Routine 2932 * @pdev: PCI device information struct 2933 * 2934 * igb_remove is called by the PCI subsystem to alert the driver 2935 * that it should release a PCI device. The could be caused by a 2936 * Hot-Plug event, or because the driver is going to be removed from 2937 * memory. 2938 **/ 2939 static void igb_remove(struct pci_dev *pdev) 2940 { 2941 struct net_device *netdev = pci_get_drvdata(pdev); 2942 struct igb_adapter *adapter = netdev_priv(netdev); 2943 struct e1000_hw *hw = &adapter->hw; 2944 2945 pm_runtime_get_noresume(&pdev->dev); 2946 #ifdef CONFIG_IGB_HWMON 2947 igb_sysfs_exit(adapter); 2948 #endif 2949 igb_remove_i2c(adapter); 2950 igb_ptp_stop(adapter); 2951 /* The watchdog timer may be rescheduled, so explicitly 2952 * disable watchdog from being rescheduled. 2953 */ 2954 set_bit(__IGB_DOWN, &adapter->state); 2955 del_timer_sync(&adapter->watchdog_timer); 2956 del_timer_sync(&adapter->phy_info_timer); 2957 2958 cancel_work_sync(&adapter->reset_task); 2959 cancel_work_sync(&adapter->watchdog_task); 2960 2961 #ifdef CONFIG_IGB_DCA 2962 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2963 dev_info(&pdev->dev, "DCA disabled\n"); 2964 dca_remove_requester(&pdev->dev); 2965 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2966 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2967 } 2968 #endif 2969 2970 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2971 * would have already happened in close and is redundant. 2972 */ 2973 igb_release_hw_control(adapter); 2974 2975 #ifdef CONFIG_PCI_IOV 2976 igb_disable_sriov(pdev); 2977 #endif 2978 2979 unregister_netdev(netdev); 2980 2981 igb_clear_interrupt_scheme(adapter); 2982 2983 pci_iounmap(pdev, adapter->io_addr); 2984 if (hw->flash_address) 2985 iounmap(hw->flash_address); 2986 pci_release_mem_regions(pdev); 2987 2988 kfree(adapter->mac_table); 2989 kfree(adapter->shadow_vfta); 2990 free_netdev(netdev); 2991 2992 pci_disable_pcie_error_reporting(pdev); 2993 2994 pci_disable_device(pdev); 2995 } 2996 2997 /** 2998 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2999 * @adapter: board private structure to initialize 3000 * 3001 * This function initializes the vf specific data storage and then attempts to 3002 * allocate the VFs. The reason for ordering it this way is because it is much 3003 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3004 * the memory for the VFs. 3005 **/ 3006 static void igb_probe_vfs(struct igb_adapter *adapter) 3007 { 3008 #ifdef CONFIG_PCI_IOV 3009 struct pci_dev *pdev = adapter->pdev; 3010 struct e1000_hw *hw = &adapter->hw; 3011 3012 /* Virtualization features not supported on i210 family. */ 3013 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3014 return; 3015 3016 /* Of the below we really only want the effect of getting 3017 * IGB_FLAG_HAS_MSIX set (if available), without which 3018 * igb_enable_sriov() has no effect. 3019 */ 3020 igb_set_interrupt_capability(adapter, true); 3021 igb_reset_interrupt_capability(adapter); 3022 3023 pci_sriov_set_totalvfs(pdev, 7); 3024 igb_enable_sriov(pdev, max_vfs); 3025 3026 #endif /* CONFIG_PCI_IOV */ 3027 } 3028 3029 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3030 { 3031 struct e1000_hw *hw = &adapter->hw; 3032 u32 max_rss_queues; 3033 3034 /* Determine the maximum number of RSS queues supported. */ 3035 switch (hw->mac.type) { 3036 case e1000_i211: 3037 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3038 break; 3039 case e1000_82575: 3040 case e1000_i210: 3041 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3042 break; 3043 case e1000_i350: 3044 /* I350 cannot do RSS and SR-IOV at the same time */ 3045 if (!!adapter->vfs_allocated_count) { 3046 max_rss_queues = 1; 3047 break; 3048 } 3049 /* fall through */ 3050 case e1000_82576: 3051 if (!!adapter->vfs_allocated_count) { 3052 max_rss_queues = 2; 3053 break; 3054 } 3055 /* fall through */ 3056 case e1000_82580: 3057 case e1000_i354: 3058 default: 3059 max_rss_queues = IGB_MAX_RX_QUEUES; 3060 break; 3061 } 3062 3063 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3064 3065 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3066 } 3067 3068 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3069 const u32 max_rss_queues) 3070 { 3071 struct e1000_hw *hw = &adapter->hw; 3072 3073 /* Determine if we need to pair queues. */ 3074 switch (hw->mac.type) { 3075 case e1000_82575: 3076 case e1000_i211: 3077 /* Device supports enough interrupts without queue pairing. */ 3078 break; 3079 case e1000_82576: 3080 case e1000_82580: 3081 case e1000_i350: 3082 case e1000_i354: 3083 case e1000_i210: 3084 default: 3085 /* If rss_queues > half of max_rss_queues, pair the queues in 3086 * order to conserve interrupts due to limited supply. 3087 */ 3088 if (adapter->rss_queues > (max_rss_queues / 2)) 3089 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3090 else 3091 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3092 break; 3093 } 3094 } 3095 3096 /** 3097 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3098 * @adapter: board private structure to initialize 3099 * 3100 * igb_sw_init initializes the Adapter private data structure. 3101 * Fields are initialized based on PCI device information and 3102 * OS network device settings (MTU size). 3103 **/ 3104 static int igb_sw_init(struct igb_adapter *adapter) 3105 { 3106 struct e1000_hw *hw = &adapter->hw; 3107 struct net_device *netdev = adapter->netdev; 3108 struct pci_dev *pdev = adapter->pdev; 3109 3110 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3111 3112 /* set default ring sizes */ 3113 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3114 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3115 3116 /* set default ITR values */ 3117 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3118 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3119 3120 /* set default work limits */ 3121 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3122 3123 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3124 VLAN_HLEN; 3125 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3126 3127 spin_lock_init(&adapter->nfc_lock); 3128 spin_lock_init(&adapter->stats64_lock); 3129 #ifdef CONFIG_PCI_IOV 3130 switch (hw->mac.type) { 3131 case e1000_82576: 3132 case e1000_i350: 3133 if (max_vfs > 7) { 3134 dev_warn(&pdev->dev, 3135 "Maximum of 7 VFs per PF, using max\n"); 3136 max_vfs = adapter->vfs_allocated_count = 7; 3137 } else 3138 adapter->vfs_allocated_count = max_vfs; 3139 if (adapter->vfs_allocated_count) 3140 dev_warn(&pdev->dev, 3141 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3142 break; 3143 default: 3144 break; 3145 } 3146 #endif /* CONFIG_PCI_IOV */ 3147 3148 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3149 adapter->flags |= IGB_FLAG_HAS_MSIX; 3150 3151 adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) * 3152 hw->mac.rar_entry_count, GFP_ATOMIC); 3153 if (!adapter->mac_table) 3154 return -ENOMEM; 3155 3156 igb_probe_vfs(adapter); 3157 3158 igb_init_queue_configuration(adapter); 3159 3160 /* Setup and initialize a copy of the hw vlan table array */ 3161 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3162 GFP_ATOMIC); 3163 3164 /* This call may decrease the number of queues */ 3165 if (igb_init_interrupt_scheme(adapter, true)) { 3166 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3167 return -ENOMEM; 3168 } 3169 3170 /* Explicitly disable IRQ since the NIC can be in any state. */ 3171 igb_irq_disable(adapter); 3172 3173 if (hw->mac.type >= e1000_i350) 3174 adapter->flags &= ~IGB_FLAG_DMAC; 3175 3176 set_bit(__IGB_DOWN, &adapter->state); 3177 return 0; 3178 } 3179 3180 /** 3181 * igb_open - Called when a network interface is made active 3182 * @netdev: network interface device structure 3183 * 3184 * Returns 0 on success, negative value on failure 3185 * 3186 * The open entry point is called when a network interface is made 3187 * active by the system (IFF_UP). At this point all resources needed 3188 * for transmit and receive operations are allocated, the interrupt 3189 * handler is registered with the OS, the watchdog timer is started, 3190 * and the stack is notified that the interface is ready. 3191 **/ 3192 static int __igb_open(struct net_device *netdev, bool resuming) 3193 { 3194 struct igb_adapter *adapter = netdev_priv(netdev); 3195 struct e1000_hw *hw = &adapter->hw; 3196 struct pci_dev *pdev = adapter->pdev; 3197 int err; 3198 int i; 3199 3200 /* disallow open during test */ 3201 if (test_bit(__IGB_TESTING, &adapter->state)) { 3202 WARN_ON(resuming); 3203 return -EBUSY; 3204 } 3205 3206 if (!resuming) 3207 pm_runtime_get_sync(&pdev->dev); 3208 3209 netif_carrier_off(netdev); 3210 3211 /* allocate transmit descriptors */ 3212 err = igb_setup_all_tx_resources(adapter); 3213 if (err) 3214 goto err_setup_tx; 3215 3216 /* allocate receive descriptors */ 3217 err = igb_setup_all_rx_resources(adapter); 3218 if (err) 3219 goto err_setup_rx; 3220 3221 igb_power_up_link(adapter); 3222 3223 /* before we allocate an interrupt, we must be ready to handle it. 3224 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3225 * as soon as we call pci_request_irq, so we have to setup our 3226 * clean_rx handler before we do so. 3227 */ 3228 igb_configure(adapter); 3229 3230 err = igb_request_irq(adapter); 3231 if (err) 3232 goto err_req_irq; 3233 3234 /* Notify the stack of the actual queue counts. */ 3235 err = netif_set_real_num_tx_queues(adapter->netdev, 3236 adapter->num_tx_queues); 3237 if (err) 3238 goto err_set_queues; 3239 3240 err = netif_set_real_num_rx_queues(adapter->netdev, 3241 adapter->num_rx_queues); 3242 if (err) 3243 goto err_set_queues; 3244 3245 /* From here on the code is the same as igb_up() */ 3246 clear_bit(__IGB_DOWN, &adapter->state); 3247 3248 for (i = 0; i < adapter->num_q_vectors; i++) 3249 napi_enable(&(adapter->q_vector[i]->napi)); 3250 3251 /* Clear any pending interrupts. */ 3252 rd32(E1000_ICR); 3253 3254 igb_irq_enable(adapter); 3255 3256 /* notify VFs that reset has been completed */ 3257 if (adapter->vfs_allocated_count) { 3258 u32 reg_data = rd32(E1000_CTRL_EXT); 3259 3260 reg_data |= E1000_CTRL_EXT_PFRSTD; 3261 wr32(E1000_CTRL_EXT, reg_data); 3262 } 3263 3264 netif_tx_start_all_queues(netdev); 3265 3266 if (!resuming) 3267 pm_runtime_put(&pdev->dev); 3268 3269 /* start the watchdog. */ 3270 hw->mac.get_link_status = 1; 3271 schedule_work(&adapter->watchdog_task); 3272 3273 return 0; 3274 3275 err_set_queues: 3276 igb_free_irq(adapter); 3277 err_req_irq: 3278 igb_release_hw_control(adapter); 3279 igb_power_down_link(adapter); 3280 igb_free_all_rx_resources(adapter); 3281 err_setup_rx: 3282 igb_free_all_tx_resources(adapter); 3283 err_setup_tx: 3284 igb_reset(adapter); 3285 if (!resuming) 3286 pm_runtime_put(&pdev->dev); 3287 3288 return err; 3289 } 3290 3291 int igb_open(struct net_device *netdev) 3292 { 3293 return __igb_open(netdev, false); 3294 } 3295 3296 /** 3297 * igb_close - Disables a network interface 3298 * @netdev: network interface device structure 3299 * 3300 * Returns 0, this is not allowed to fail 3301 * 3302 * The close entry point is called when an interface is de-activated 3303 * by the OS. The hardware is still under the driver's control, but 3304 * needs to be disabled. A global MAC reset is issued to stop the 3305 * hardware, and all transmit and receive resources are freed. 3306 **/ 3307 static int __igb_close(struct net_device *netdev, bool suspending) 3308 { 3309 struct igb_adapter *adapter = netdev_priv(netdev); 3310 struct pci_dev *pdev = adapter->pdev; 3311 3312 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3313 3314 if (!suspending) 3315 pm_runtime_get_sync(&pdev->dev); 3316 3317 igb_down(adapter); 3318 igb_free_irq(adapter); 3319 3320 igb_nfc_filter_exit(adapter); 3321 3322 igb_free_all_tx_resources(adapter); 3323 igb_free_all_rx_resources(adapter); 3324 3325 if (!suspending) 3326 pm_runtime_put_sync(&pdev->dev); 3327 return 0; 3328 } 3329 3330 int igb_close(struct net_device *netdev) 3331 { 3332 if (netif_device_present(netdev)) 3333 return __igb_close(netdev, false); 3334 return 0; 3335 } 3336 3337 /** 3338 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3339 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3340 * 3341 * Return 0 on success, negative on failure 3342 **/ 3343 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3344 { 3345 struct device *dev = tx_ring->dev; 3346 int size; 3347 3348 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3349 3350 tx_ring->tx_buffer_info = vmalloc(size); 3351 if (!tx_ring->tx_buffer_info) 3352 goto err; 3353 3354 /* round up to nearest 4K */ 3355 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3356 tx_ring->size = ALIGN(tx_ring->size, 4096); 3357 3358 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3359 &tx_ring->dma, GFP_KERNEL); 3360 if (!tx_ring->desc) 3361 goto err; 3362 3363 tx_ring->next_to_use = 0; 3364 tx_ring->next_to_clean = 0; 3365 3366 return 0; 3367 3368 err: 3369 vfree(tx_ring->tx_buffer_info); 3370 tx_ring->tx_buffer_info = NULL; 3371 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3372 return -ENOMEM; 3373 } 3374 3375 /** 3376 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3377 * (Descriptors) for all queues 3378 * @adapter: board private structure 3379 * 3380 * Return 0 on success, negative on failure 3381 **/ 3382 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3383 { 3384 struct pci_dev *pdev = adapter->pdev; 3385 int i, err = 0; 3386 3387 for (i = 0; i < adapter->num_tx_queues; i++) { 3388 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3389 if (err) { 3390 dev_err(&pdev->dev, 3391 "Allocation for Tx Queue %u failed\n", i); 3392 for (i--; i >= 0; i--) 3393 igb_free_tx_resources(adapter->tx_ring[i]); 3394 break; 3395 } 3396 } 3397 3398 return err; 3399 } 3400 3401 /** 3402 * igb_setup_tctl - configure the transmit control registers 3403 * @adapter: Board private structure 3404 **/ 3405 void igb_setup_tctl(struct igb_adapter *adapter) 3406 { 3407 struct e1000_hw *hw = &adapter->hw; 3408 u32 tctl; 3409 3410 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3411 wr32(E1000_TXDCTL(0), 0); 3412 3413 /* Program the Transmit Control Register */ 3414 tctl = rd32(E1000_TCTL); 3415 tctl &= ~E1000_TCTL_CT; 3416 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3417 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3418 3419 igb_config_collision_dist(hw); 3420 3421 /* Enable transmits */ 3422 tctl |= E1000_TCTL_EN; 3423 3424 wr32(E1000_TCTL, tctl); 3425 } 3426 3427 /** 3428 * igb_configure_tx_ring - Configure transmit ring after Reset 3429 * @adapter: board private structure 3430 * @ring: tx ring to configure 3431 * 3432 * Configure a transmit ring after a reset. 3433 **/ 3434 void igb_configure_tx_ring(struct igb_adapter *adapter, 3435 struct igb_ring *ring) 3436 { 3437 struct e1000_hw *hw = &adapter->hw; 3438 u32 txdctl = 0; 3439 u64 tdba = ring->dma; 3440 int reg_idx = ring->reg_idx; 3441 3442 /* disable the queue */ 3443 wr32(E1000_TXDCTL(reg_idx), 0); 3444 wrfl(); 3445 mdelay(10); 3446 3447 wr32(E1000_TDLEN(reg_idx), 3448 ring->count * sizeof(union e1000_adv_tx_desc)); 3449 wr32(E1000_TDBAL(reg_idx), 3450 tdba & 0x00000000ffffffffULL); 3451 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3452 3453 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 3454 wr32(E1000_TDH(reg_idx), 0); 3455 writel(0, ring->tail); 3456 3457 txdctl |= IGB_TX_PTHRESH; 3458 txdctl |= IGB_TX_HTHRESH << 8; 3459 txdctl |= IGB_TX_WTHRESH << 16; 3460 3461 /* reinitialize tx_buffer_info */ 3462 memset(ring->tx_buffer_info, 0, 3463 sizeof(struct igb_tx_buffer) * ring->count); 3464 3465 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3466 wr32(E1000_TXDCTL(reg_idx), txdctl); 3467 } 3468 3469 /** 3470 * igb_configure_tx - Configure transmit Unit after Reset 3471 * @adapter: board private structure 3472 * 3473 * Configure the Tx unit of the MAC after a reset. 3474 **/ 3475 static void igb_configure_tx(struct igb_adapter *adapter) 3476 { 3477 int i; 3478 3479 for (i = 0; i < adapter->num_tx_queues; i++) 3480 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3481 } 3482 3483 /** 3484 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3485 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3486 * 3487 * Returns 0 on success, negative on failure 3488 **/ 3489 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3490 { 3491 struct device *dev = rx_ring->dev; 3492 int size; 3493 3494 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3495 3496 rx_ring->rx_buffer_info = vmalloc(size); 3497 if (!rx_ring->rx_buffer_info) 3498 goto err; 3499 3500 /* Round up to nearest 4K */ 3501 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3502 rx_ring->size = ALIGN(rx_ring->size, 4096); 3503 3504 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3505 &rx_ring->dma, GFP_KERNEL); 3506 if (!rx_ring->desc) 3507 goto err; 3508 3509 rx_ring->next_to_alloc = 0; 3510 rx_ring->next_to_clean = 0; 3511 rx_ring->next_to_use = 0; 3512 3513 return 0; 3514 3515 err: 3516 vfree(rx_ring->rx_buffer_info); 3517 rx_ring->rx_buffer_info = NULL; 3518 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3519 return -ENOMEM; 3520 } 3521 3522 /** 3523 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3524 * (Descriptors) for all queues 3525 * @adapter: board private structure 3526 * 3527 * Return 0 on success, negative on failure 3528 **/ 3529 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3530 { 3531 struct pci_dev *pdev = adapter->pdev; 3532 int i, err = 0; 3533 3534 for (i = 0; i < adapter->num_rx_queues; i++) { 3535 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3536 if (err) { 3537 dev_err(&pdev->dev, 3538 "Allocation for Rx Queue %u failed\n", i); 3539 for (i--; i >= 0; i--) 3540 igb_free_rx_resources(adapter->rx_ring[i]); 3541 break; 3542 } 3543 } 3544 3545 return err; 3546 } 3547 3548 /** 3549 * igb_setup_mrqc - configure the multiple receive queue control registers 3550 * @adapter: Board private structure 3551 **/ 3552 static void igb_setup_mrqc(struct igb_adapter *adapter) 3553 { 3554 struct e1000_hw *hw = &adapter->hw; 3555 u32 mrqc, rxcsum; 3556 u32 j, num_rx_queues; 3557 u32 rss_key[10]; 3558 3559 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3560 for (j = 0; j < 10; j++) 3561 wr32(E1000_RSSRK(j), rss_key[j]); 3562 3563 num_rx_queues = adapter->rss_queues; 3564 3565 switch (hw->mac.type) { 3566 case e1000_82576: 3567 /* 82576 supports 2 RSS queues for SR-IOV */ 3568 if (adapter->vfs_allocated_count) 3569 num_rx_queues = 2; 3570 break; 3571 default: 3572 break; 3573 } 3574 3575 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3576 for (j = 0; j < IGB_RETA_SIZE; j++) 3577 adapter->rss_indir_tbl[j] = 3578 (j * num_rx_queues) / IGB_RETA_SIZE; 3579 adapter->rss_indir_tbl_init = num_rx_queues; 3580 } 3581 igb_write_rss_indir_tbl(adapter); 3582 3583 /* Disable raw packet checksumming so that RSS hash is placed in 3584 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3585 * offloads as they are enabled by default 3586 */ 3587 rxcsum = rd32(E1000_RXCSUM); 3588 rxcsum |= E1000_RXCSUM_PCSD; 3589 3590 if (adapter->hw.mac.type >= e1000_82576) 3591 /* Enable Receive Checksum Offload for SCTP */ 3592 rxcsum |= E1000_RXCSUM_CRCOFL; 3593 3594 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3595 wr32(E1000_RXCSUM, rxcsum); 3596 3597 /* Generate RSS hash based on packet types, TCP/UDP 3598 * port numbers and/or IPv4/v6 src and dst addresses 3599 */ 3600 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3601 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3602 E1000_MRQC_RSS_FIELD_IPV6 | 3603 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3604 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3605 3606 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3607 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3608 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3609 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3610 3611 /* If VMDq is enabled then we set the appropriate mode for that, else 3612 * we default to RSS so that an RSS hash is calculated per packet even 3613 * if we are only using one queue 3614 */ 3615 if (adapter->vfs_allocated_count) { 3616 if (hw->mac.type > e1000_82575) { 3617 /* Set the default pool for the PF's first queue */ 3618 u32 vtctl = rd32(E1000_VT_CTL); 3619 3620 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3621 E1000_VT_CTL_DISABLE_DEF_POOL); 3622 vtctl |= adapter->vfs_allocated_count << 3623 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3624 wr32(E1000_VT_CTL, vtctl); 3625 } 3626 if (adapter->rss_queues > 1) 3627 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3628 else 3629 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3630 } else { 3631 if (hw->mac.type != e1000_i211) 3632 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3633 } 3634 igb_vmm_control(adapter); 3635 3636 wr32(E1000_MRQC, mrqc); 3637 } 3638 3639 /** 3640 * igb_setup_rctl - configure the receive control registers 3641 * @adapter: Board private structure 3642 **/ 3643 void igb_setup_rctl(struct igb_adapter *adapter) 3644 { 3645 struct e1000_hw *hw = &adapter->hw; 3646 u32 rctl; 3647 3648 rctl = rd32(E1000_RCTL); 3649 3650 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3651 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3652 3653 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3654 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3655 3656 /* enable stripping of CRC. It's unlikely this will break BMC 3657 * redirection as it did with e1000. Newer features require 3658 * that the HW strips the CRC. 3659 */ 3660 rctl |= E1000_RCTL_SECRC; 3661 3662 /* disable store bad packets and clear size bits. */ 3663 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3664 3665 /* enable LPE to allow for reception of jumbo frames */ 3666 rctl |= E1000_RCTL_LPE; 3667 3668 /* disable queue 0 to prevent tail write w/o re-config */ 3669 wr32(E1000_RXDCTL(0), 0); 3670 3671 /* Attention!!! For SR-IOV PF driver operations you must enable 3672 * queue drop for all VF and PF queues to prevent head of line blocking 3673 * if an un-trusted VF does not provide descriptors to hardware. 3674 */ 3675 if (adapter->vfs_allocated_count) { 3676 /* set all queue drop enable bits */ 3677 wr32(E1000_QDE, ALL_QUEUES); 3678 } 3679 3680 /* This is useful for sniffing bad packets. */ 3681 if (adapter->netdev->features & NETIF_F_RXALL) { 3682 /* UPE and MPE will be handled by normal PROMISC logic 3683 * in e1000e_set_rx_mode 3684 */ 3685 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3686 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3687 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3688 3689 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3690 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3691 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3692 * and that breaks VLANs. 3693 */ 3694 } 3695 3696 wr32(E1000_RCTL, rctl); 3697 } 3698 3699 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3700 int vfn) 3701 { 3702 struct e1000_hw *hw = &adapter->hw; 3703 u32 vmolr; 3704 3705 if (size > MAX_JUMBO_FRAME_SIZE) 3706 size = MAX_JUMBO_FRAME_SIZE; 3707 3708 vmolr = rd32(E1000_VMOLR(vfn)); 3709 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3710 vmolr |= size | E1000_VMOLR_LPE; 3711 wr32(E1000_VMOLR(vfn), vmolr); 3712 3713 return 0; 3714 } 3715 3716 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3717 int vfn, bool enable) 3718 { 3719 struct e1000_hw *hw = &adapter->hw; 3720 u32 val, reg; 3721 3722 if (hw->mac.type < e1000_82576) 3723 return; 3724 3725 if (hw->mac.type == e1000_i350) 3726 reg = E1000_DVMOLR(vfn); 3727 else 3728 reg = E1000_VMOLR(vfn); 3729 3730 val = rd32(reg); 3731 if (enable) 3732 val |= E1000_VMOLR_STRVLAN; 3733 else 3734 val &= ~(E1000_VMOLR_STRVLAN); 3735 wr32(reg, val); 3736 } 3737 3738 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3739 int vfn, bool aupe) 3740 { 3741 struct e1000_hw *hw = &adapter->hw; 3742 u32 vmolr; 3743 3744 /* This register exists only on 82576 and newer so if we are older then 3745 * we should exit and do nothing 3746 */ 3747 if (hw->mac.type < e1000_82576) 3748 return; 3749 3750 vmolr = rd32(E1000_VMOLR(vfn)); 3751 if (aupe) 3752 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3753 else 3754 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3755 3756 /* clear all bits that might not be set */ 3757 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3758 3759 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3760 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3761 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3762 * multicast packets 3763 */ 3764 if (vfn <= adapter->vfs_allocated_count) 3765 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3766 3767 wr32(E1000_VMOLR(vfn), vmolr); 3768 } 3769 3770 /** 3771 * igb_configure_rx_ring - Configure a receive ring after Reset 3772 * @adapter: board private structure 3773 * @ring: receive ring to be configured 3774 * 3775 * Configure the Rx unit of the MAC after a reset. 3776 **/ 3777 void igb_configure_rx_ring(struct igb_adapter *adapter, 3778 struct igb_ring *ring) 3779 { 3780 struct e1000_hw *hw = &adapter->hw; 3781 union e1000_adv_rx_desc *rx_desc; 3782 u64 rdba = ring->dma; 3783 int reg_idx = ring->reg_idx; 3784 u32 srrctl = 0, rxdctl = 0; 3785 3786 /* disable the queue */ 3787 wr32(E1000_RXDCTL(reg_idx), 0); 3788 3789 /* Set DMA base address registers */ 3790 wr32(E1000_RDBAL(reg_idx), 3791 rdba & 0x00000000ffffffffULL); 3792 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3793 wr32(E1000_RDLEN(reg_idx), 3794 ring->count * sizeof(union e1000_adv_rx_desc)); 3795 3796 /* initialize head and tail */ 3797 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 3798 wr32(E1000_RDH(reg_idx), 0); 3799 writel(0, ring->tail); 3800 3801 /* set descriptor configuration */ 3802 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3803 if (ring_uses_large_buffer(ring)) 3804 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3805 else 3806 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3807 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3808 if (hw->mac.type >= e1000_82580) 3809 srrctl |= E1000_SRRCTL_TIMESTAMP; 3810 /* Only set Drop Enable if we are supporting multiple queues */ 3811 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3812 srrctl |= E1000_SRRCTL_DROP_EN; 3813 3814 wr32(E1000_SRRCTL(reg_idx), srrctl); 3815 3816 /* set filtering for VMDQ pools */ 3817 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3818 3819 rxdctl |= IGB_RX_PTHRESH; 3820 rxdctl |= IGB_RX_HTHRESH << 8; 3821 rxdctl |= IGB_RX_WTHRESH << 16; 3822 3823 /* initialize rx_buffer_info */ 3824 memset(ring->rx_buffer_info, 0, 3825 sizeof(struct igb_rx_buffer) * ring->count); 3826 3827 /* initialize Rx descriptor 0 */ 3828 rx_desc = IGB_RX_DESC(ring, 0); 3829 rx_desc->wb.upper.length = 0; 3830 3831 /* enable receive descriptor fetching */ 3832 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3833 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3834 } 3835 3836 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 3837 struct igb_ring *rx_ring) 3838 { 3839 /* set build_skb and buffer size flags */ 3840 clear_ring_build_skb_enabled(rx_ring); 3841 clear_ring_uses_large_buffer(rx_ring); 3842 3843 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3844 return; 3845 3846 set_ring_build_skb_enabled(rx_ring); 3847 3848 #if (PAGE_SIZE < 8192) 3849 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 3850 return; 3851 3852 set_ring_uses_large_buffer(rx_ring); 3853 #endif 3854 } 3855 3856 /** 3857 * igb_configure_rx - Configure receive Unit after Reset 3858 * @adapter: board private structure 3859 * 3860 * Configure the Rx unit of the MAC after a reset. 3861 **/ 3862 static void igb_configure_rx(struct igb_adapter *adapter) 3863 { 3864 int i; 3865 3866 /* set the correct pool for the PF default MAC address in entry 0 */ 3867 igb_set_default_mac_filter(adapter); 3868 3869 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3870 * the Base and Length of the Rx Descriptor Ring 3871 */ 3872 for (i = 0; i < adapter->num_rx_queues; i++) { 3873 struct igb_ring *rx_ring = adapter->rx_ring[i]; 3874 3875 igb_set_rx_buffer_len(adapter, rx_ring); 3876 igb_configure_rx_ring(adapter, rx_ring); 3877 } 3878 } 3879 3880 /** 3881 * igb_free_tx_resources - Free Tx Resources per Queue 3882 * @tx_ring: Tx descriptor ring for a specific queue 3883 * 3884 * Free all transmit software resources 3885 **/ 3886 void igb_free_tx_resources(struct igb_ring *tx_ring) 3887 { 3888 igb_clean_tx_ring(tx_ring); 3889 3890 vfree(tx_ring->tx_buffer_info); 3891 tx_ring->tx_buffer_info = NULL; 3892 3893 /* if not set, then don't free */ 3894 if (!tx_ring->desc) 3895 return; 3896 3897 dma_free_coherent(tx_ring->dev, tx_ring->size, 3898 tx_ring->desc, tx_ring->dma); 3899 3900 tx_ring->desc = NULL; 3901 } 3902 3903 /** 3904 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3905 * @adapter: board private structure 3906 * 3907 * Free all transmit software resources 3908 **/ 3909 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3910 { 3911 int i; 3912 3913 for (i = 0; i < adapter->num_tx_queues; i++) 3914 if (adapter->tx_ring[i]) 3915 igb_free_tx_resources(adapter->tx_ring[i]); 3916 } 3917 3918 /** 3919 * igb_clean_tx_ring - Free Tx Buffers 3920 * @tx_ring: ring to be cleaned 3921 **/ 3922 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3923 { 3924 u16 i = tx_ring->next_to_clean; 3925 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 3926 3927 while (i != tx_ring->next_to_use) { 3928 union e1000_adv_tx_desc *eop_desc, *tx_desc; 3929 3930 /* Free all the Tx ring sk_buffs */ 3931 dev_kfree_skb_any(tx_buffer->skb); 3932 3933 /* unmap skb header data */ 3934 dma_unmap_single(tx_ring->dev, 3935 dma_unmap_addr(tx_buffer, dma), 3936 dma_unmap_len(tx_buffer, len), 3937 DMA_TO_DEVICE); 3938 3939 /* check for eop_desc to determine the end of the packet */ 3940 eop_desc = tx_buffer->next_to_watch; 3941 tx_desc = IGB_TX_DESC(tx_ring, i); 3942 3943 /* unmap remaining buffers */ 3944 while (tx_desc != eop_desc) { 3945 tx_buffer++; 3946 tx_desc++; 3947 i++; 3948 if (unlikely(i == tx_ring->count)) { 3949 i = 0; 3950 tx_buffer = tx_ring->tx_buffer_info; 3951 tx_desc = IGB_TX_DESC(tx_ring, 0); 3952 } 3953 3954 /* unmap any remaining paged data */ 3955 if (dma_unmap_len(tx_buffer, len)) 3956 dma_unmap_page(tx_ring->dev, 3957 dma_unmap_addr(tx_buffer, dma), 3958 dma_unmap_len(tx_buffer, len), 3959 DMA_TO_DEVICE); 3960 } 3961 3962 /* move us one more past the eop_desc for start of next pkt */ 3963 tx_buffer++; 3964 i++; 3965 if (unlikely(i == tx_ring->count)) { 3966 i = 0; 3967 tx_buffer = tx_ring->tx_buffer_info; 3968 } 3969 } 3970 3971 /* reset BQL for queue */ 3972 netdev_tx_reset_queue(txring_txq(tx_ring)); 3973 3974 /* reset next_to_use and next_to_clean */ 3975 tx_ring->next_to_use = 0; 3976 tx_ring->next_to_clean = 0; 3977 } 3978 3979 /** 3980 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3981 * @adapter: board private structure 3982 **/ 3983 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3984 { 3985 int i; 3986 3987 for (i = 0; i < adapter->num_tx_queues; i++) 3988 if (adapter->tx_ring[i]) 3989 igb_clean_tx_ring(adapter->tx_ring[i]); 3990 } 3991 3992 /** 3993 * igb_free_rx_resources - Free Rx Resources 3994 * @rx_ring: ring to clean the resources from 3995 * 3996 * Free all receive software resources 3997 **/ 3998 void igb_free_rx_resources(struct igb_ring *rx_ring) 3999 { 4000 igb_clean_rx_ring(rx_ring); 4001 4002 vfree(rx_ring->rx_buffer_info); 4003 rx_ring->rx_buffer_info = NULL; 4004 4005 /* if not set, then don't free */ 4006 if (!rx_ring->desc) 4007 return; 4008 4009 dma_free_coherent(rx_ring->dev, rx_ring->size, 4010 rx_ring->desc, rx_ring->dma); 4011 4012 rx_ring->desc = NULL; 4013 } 4014 4015 /** 4016 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4017 * @adapter: board private structure 4018 * 4019 * Free all receive software resources 4020 **/ 4021 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4022 { 4023 int i; 4024 4025 for (i = 0; i < adapter->num_rx_queues; i++) 4026 if (adapter->rx_ring[i]) 4027 igb_free_rx_resources(adapter->rx_ring[i]); 4028 } 4029 4030 /** 4031 * igb_clean_rx_ring - Free Rx Buffers per Queue 4032 * @rx_ring: ring to free buffers from 4033 **/ 4034 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4035 { 4036 u16 i = rx_ring->next_to_clean; 4037 4038 if (rx_ring->skb) 4039 dev_kfree_skb(rx_ring->skb); 4040 rx_ring->skb = NULL; 4041 4042 /* Free all the Rx ring sk_buffs */ 4043 while (i != rx_ring->next_to_alloc) { 4044 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4045 4046 /* Invalidate cache lines that may have been written to by 4047 * device so that we avoid corrupting memory. 4048 */ 4049 dma_sync_single_range_for_cpu(rx_ring->dev, 4050 buffer_info->dma, 4051 buffer_info->page_offset, 4052 igb_rx_bufsz(rx_ring), 4053 DMA_FROM_DEVICE); 4054 4055 /* free resources associated with mapping */ 4056 dma_unmap_page_attrs(rx_ring->dev, 4057 buffer_info->dma, 4058 igb_rx_pg_size(rx_ring), 4059 DMA_FROM_DEVICE, 4060 IGB_RX_DMA_ATTR); 4061 __page_frag_cache_drain(buffer_info->page, 4062 buffer_info->pagecnt_bias); 4063 4064 i++; 4065 if (i == rx_ring->count) 4066 i = 0; 4067 } 4068 4069 rx_ring->next_to_alloc = 0; 4070 rx_ring->next_to_clean = 0; 4071 rx_ring->next_to_use = 0; 4072 } 4073 4074 /** 4075 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4076 * @adapter: board private structure 4077 **/ 4078 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4079 { 4080 int i; 4081 4082 for (i = 0; i < adapter->num_rx_queues; i++) 4083 if (adapter->rx_ring[i]) 4084 igb_clean_rx_ring(adapter->rx_ring[i]); 4085 } 4086 4087 /** 4088 * igb_set_mac - Change the Ethernet Address of the NIC 4089 * @netdev: network interface device structure 4090 * @p: pointer to an address structure 4091 * 4092 * Returns 0 on success, negative on failure 4093 **/ 4094 static int igb_set_mac(struct net_device *netdev, void *p) 4095 { 4096 struct igb_adapter *adapter = netdev_priv(netdev); 4097 struct e1000_hw *hw = &adapter->hw; 4098 struct sockaddr *addr = p; 4099 4100 if (!is_valid_ether_addr(addr->sa_data)) 4101 return -EADDRNOTAVAIL; 4102 4103 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4104 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4105 4106 /* set the correct pool for the new PF MAC address in entry 0 */ 4107 igb_set_default_mac_filter(adapter); 4108 4109 return 0; 4110 } 4111 4112 /** 4113 * igb_write_mc_addr_list - write multicast addresses to MTA 4114 * @netdev: network interface device structure 4115 * 4116 * Writes multicast address list to the MTA hash table. 4117 * Returns: -ENOMEM on failure 4118 * 0 on no addresses written 4119 * X on writing X addresses to MTA 4120 **/ 4121 static int igb_write_mc_addr_list(struct net_device *netdev) 4122 { 4123 struct igb_adapter *adapter = netdev_priv(netdev); 4124 struct e1000_hw *hw = &adapter->hw; 4125 struct netdev_hw_addr *ha; 4126 u8 *mta_list; 4127 int i; 4128 4129 if (netdev_mc_empty(netdev)) { 4130 /* nothing to program, so clear mc list */ 4131 igb_update_mc_addr_list(hw, NULL, 0); 4132 igb_restore_vf_multicasts(adapter); 4133 return 0; 4134 } 4135 4136 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4137 if (!mta_list) 4138 return -ENOMEM; 4139 4140 /* The shared function expects a packed array of only addresses. */ 4141 i = 0; 4142 netdev_for_each_mc_addr(ha, netdev) 4143 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4144 4145 igb_update_mc_addr_list(hw, mta_list, i); 4146 kfree(mta_list); 4147 4148 return netdev_mc_count(netdev); 4149 } 4150 4151 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4152 { 4153 struct e1000_hw *hw = &adapter->hw; 4154 u32 i, pf_id; 4155 4156 switch (hw->mac.type) { 4157 case e1000_i210: 4158 case e1000_i211: 4159 case e1000_i350: 4160 /* VLAN filtering needed for VLAN prio filter */ 4161 if (adapter->netdev->features & NETIF_F_NTUPLE) 4162 break; 4163 /* fall through */ 4164 case e1000_82576: 4165 case e1000_82580: 4166 case e1000_i354: 4167 /* VLAN filtering needed for pool filtering */ 4168 if (adapter->vfs_allocated_count) 4169 break; 4170 /* fall through */ 4171 default: 4172 return 1; 4173 } 4174 4175 /* We are already in VLAN promisc, nothing to do */ 4176 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4177 return 0; 4178 4179 if (!adapter->vfs_allocated_count) 4180 goto set_vfta; 4181 4182 /* Add PF to all active pools */ 4183 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4184 4185 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4186 u32 vlvf = rd32(E1000_VLVF(i)); 4187 4188 vlvf |= BIT(pf_id); 4189 wr32(E1000_VLVF(i), vlvf); 4190 } 4191 4192 set_vfta: 4193 /* Set all bits in the VLAN filter table array */ 4194 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4195 hw->mac.ops.write_vfta(hw, i, ~0U); 4196 4197 /* Set flag so we don't redo unnecessary work */ 4198 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4199 4200 return 0; 4201 } 4202 4203 #define VFTA_BLOCK_SIZE 8 4204 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4205 { 4206 struct e1000_hw *hw = &adapter->hw; 4207 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4208 u32 vid_start = vfta_offset * 32; 4209 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4210 u32 i, vid, word, bits, pf_id; 4211 4212 /* guarantee that we don't scrub out management VLAN */ 4213 vid = adapter->mng_vlan_id; 4214 if (vid >= vid_start && vid < vid_end) 4215 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4216 4217 if (!adapter->vfs_allocated_count) 4218 goto set_vfta; 4219 4220 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4221 4222 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4223 u32 vlvf = rd32(E1000_VLVF(i)); 4224 4225 /* pull VLAN ID from VLVF */ 4226 vid = vlvf & VLAN_VID_MASK; 4227 4228 /* only concern ourselves with a certain range */ 4229 if (vid < vid_start || vid >= vid_end) 4230 continue; 4231 4232 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4233 /* record VLAN ID in VFTA */ 4234 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4235 4236 /* if PF is part of this then continue */ 4237 if (test_bit(vid, adapter->active_vlans)) 4238 continue; 4239 } 4240 4241 /* remove PF from the pool */ 4242 bits = ~BIT(pf_id); 4243 bits &= rd32(E1000_VLVF(i)); 4244 wr32(E1000_VLVF(i), bits); 4245 } 4246 4247 set_vfta: 4248 /* extract values from active_vlans and write back to VFTA */ 4249 for (i = VFTA_BLOCK_SIZE; i--;) { 4250 vid = (vfta_offset + i) * 32; 4251 word = vid / BITS_PER_LONG; 4252 bits = vid % BITS_PER_LONG; 4253 4254 vfta[i] |= adapter->active_vlans[word] >> bits; 4255 4256 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4257 } 4258 } 4259 4260 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4261 { 4262 u32 i; 4263 4264 /* We are not in VLAN promisc, nothing to do */ 4265 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4266 return; 4267 4268 /* Set flag so we don't redo unnecessary work */ 4269 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4270 4271 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4272 igb_scrub_vfta(adapter, i); 4273 } 4274 4275 /** 4276 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4277 * @netdev: network interface device structure 4278 * 4279 * The set_rx_mode entry point is called whenever the unicast or multicast 4280 * address lists or the network interface flags are updated. This routine is 4281 * responsible for configuring the hardware for proper unicast, multicast, 4282 * promiscuous mode, and all-multi behavior. 4283 **/ 4284 static void igb_set_rx_mode(struct net_device *netdev) 4285 { 4286 struct igb_adapter *adapter = netdev_priv(netdev); 4287 struct e1000_hw *hw = &adapter->hw; 4288 unsigned int vfn = adapter->vfs_allocated_count; 4289 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4290 int count; 4291 4292 /* Check for Promiscuous and All Multicast modes */ 4293 if (netdev->flags & IFF_PROMISC) { 4294 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4295 vmolr |= E1000_VMOLR_MPME; 4296 4297 /* enable use of UTA filter to force packets to default pool */ 4298 if (hw->mac.type == e1000_82576) 4299 vmolr |= E1000_VMOLR_ROPE; 4300 } else { 4301 if (netdev->flags & IFF_ALLMULTI) { 4302 rctl |= E1000_RCTL_MPE; 4303 vmolr |= E1000_VMOLR_MPME; 4304 } else { 4305 /* Write addresses to the MTA, if the attempt fails 4306 * then we should just turn on promiscuous mode so 4307 * that we can at least receive multicast traffic 4308 */ 4309 count = igb_write_mc_addr_list(netdev); 4310 if (count < 0) { 4311 rctl |= E1000_RCTL_MPE; 4312 vmolr |= E1000_VMOLR_MPME; 4313 } else if (count) { 4314 vmolr |= E1000_VMOLR_ROMPE; 4315 } 4316 } 4317 } 4318 4319 /* Write addresses to available RAR registers, if there is not 4320 * sufficient space to store all the addresses then enable 4321 * unicast promiscuous mode 4322 */ 4323 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 4324 rctl |= E1000_RCTL_UPE; 4325 vmolr |= E1000_VMOLR_ROPE; 4326 } 4327 4328 /* enable VLAN filtering by default */ 4329 rctl |= E1000_RCTL_VFE; 4330 4331 /* disable VLAN filtering for modes that require it */ 4332 if ((netdev->flags & IFF_PROMISC) || 4333 (netdev->features & NETIF_F_RXALL)) { 4334 /* if we fail to set all rules then just clear VFE */ 4335 if (igb_vlan_promisc_enable(adapter)) 4336 rctl &= ~E1000_RCTL_VFE; 4337 } else { 4338 igb_vlan_promisc_disable(adapter); 4339 } 4340 4341 /* update state of unicast, multicast, and VLAN filtering modes */ 4342 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4343 E1000_RCTL_VFE); 4344 wr32(E1000_RCTL, rctl); 4345 4346 #if (PAGE_SIZE < 8192) 4347 if (!adapter->vfs_allocated_count) { 4348 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4349 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4350 } 4351 #endif 4352 wr32(E1000_RLPML, rlpml); 4353 4354 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4355 * the VMOLR to enable the appropriate modes. Without this workaround 4356 * we will have issues with VLAN tag stripping not being done for frames 4357 * that are only arriving because we are the default pool 4358 */ 4359 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4360 return; 4361 4362 /* set UTA to appropriate mode */ 4363 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4364 4365 vmolr |= rd32(E1000_VMOLR(vfn)) & 4366 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4367 4368 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4369 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4370 #if (PAGE_SIZE < 8192) 4371 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4372 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4373 else 4374 #endif 4375 vmolr |= MAX_JUMBO_FRAME_SIZE; 4376 vmolr |= E1000_VMOLR_LPE; 4377 4378 wr32(E1000_VMOLR(vfn), vmolr); 4379 4380 igb_restore_vf_multicasts(adapter); 4381 } 4382 4383 static void igb_check_wvbr(struct igb_adapter *adapter) 4384 { 4385 struct e1000_hw *hw = &adapter->hw; 4386 u32 wvbr = 0; 4387 4388 switch (hw->mac.type) { 4389 case e1000_82576: 4390 case e1000_i350: 4391 wvbr = rd32(E1000_WVBR); 4392 if (!wvbr) 4393 return; 4394 break; 4395 default: 4396 break; 4397 } 4398 4399 adapter->wvbr |= wvbr; 4400 } 4401 4402 #define IGB_STAGGERED_QUEUE_OFFSET 8 4403 4404 static void igb_spoof_check(struct igb_adapter *adapter) 4405 { 4406 int j; 4407 4408 if (!adapter->wvbr) 4409 return; 4410 4411 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4412 if (adapter->wvbr & BIT(j) || 4413 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4414 dev_warn(&adapter->pdev->dev, 4415 "Spoof event(s) detected on VF %d\n", j); 4416 adapter->wvbr &= 4417 ~(BIT(j) | 4418 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4419 } 4420 } 4421 } 4422 4423 /* Need to wait a few seconds after link up to get diagnostic information from 4424 * the phy 4425 */ 4426 static void igb_update_phy_info(unsigned long data) 4427 { 4428 struct igb_adapter *adapter = (struct igb_adapter *) data; 4429 igb_get_phy_info(&adapter->hw); 4430 } 4431 4432 /** 4433 * igb_has_link - check shared code for link and determine up/down 4434 * @adapter: pointer to driver private info 4435 **/ 4436 bool igb_has_link(struct igb_adapter *adapter) 4437 { 4438 struct e1000_hw *hw = &adapter->hw; 4439 bool link_active = false; 4440 4441 /* get_link_status is set on LSC (link status) interrupt or 4442 * rx sequence error interrupt. get_link_status will stay 4443 * false until the e1000_check_for_link establishes link 4444 * for copper adapters ONLY 4445 */ 4446 switch (hw->phy.media_type) { 4447 case e1000_media_type_copper: 4448 if (!hw->mac.get_link_status) 4449 return true; 4450 case e1000_media_type_internal_serdes: 4451 hw->mac.ops.check_for_link(hw); 4452 link_active = !hw->mac.get_link_status; 4453 break; 4454 default: 4455 case e1000_media_type_unknown: 4456 break; 4457 } 4458 4459 if (((hw->mac.type == e1000_i210) || 4460 (hw->mac.type == e1000_i211)) && 4461 (hw->phy.id == I210_I_PHY_ID)) { 4462 if (!netif_carrier_ok(adapter->netdev)) { 4463 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4464 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4465 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4466 adapter->link_check_timeout = jiffies; 4467 } 4468 } 4469 4470 return link_active; 4471 } 4472 4473 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4474 { 4475 bool ret = false; 4476 u32 ctrl_ext, thstat; 4477 4478 /* check for thermal sensor event on i350 copper only */ 4479 if (hw->mac.type == e1000_i350) { 4480 thstat = rd32(E1000_THSTAT); 4481 ctrl_ext = rd32(E1000_CTRL_EXT); 4482 4483 if ((hw->phy.media_type == e1000_media_type_copper) && 4484 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4485 ret = !!(thstat & event); 4486 } 4487 4488 return ret; 4489 } 4490 4491 /** 4492 * igb_check_lvmmc - check for malformed packets received 4493 * and indicated in LVMMC register 4494 * @adapter: pointer to adapter 4495 **/ 4496 static void igb_check_lvmmc(struct igb_adapter *adapter) 4497 { 4498 struct e1000_hw *hw = &adapter->hw; 4499 u32 lvmmc; 4500 4501 lvmmc = rd32(E1000_LVMMC); 4502 if (lvmmc) { 4503 if (unlikely(net_ratelimit())) { 4504 netdev_warn(adapter->netdev, 4505 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4506 lvmmc); 4507 } 4508 } 4509 } 4510 4511 /** 4512 * igb_watchdog - Timer Call-back 4513 * @data: pointer to adapter cast into an unsigned long 4514 **/ 4515 static void igb_watchdog(unsigned long data) 4516 { 4517 struct igb_adapter *adapter = (struct igb_adapter *)data; 4518 /* Do the rest outside of interrupt context */ 4519 schedule_work(&adapter->watchdog_task); 4520 } 4521 4522 static void igb_watchdog_task(struct work_struct *work) 4523 { 4524 struct igb_adapter *adapter = container_of(work, 4525 struct igb_adapter, 4526 watchdog_task); 4527 struct e1000_hw *hw = &adapter->hw; 4528 struct e1000_phy_info *phy = &hw->phy; 4529 struct net_device *netdev = adapter->netdev; 4530 u32 link; 4531 int i; 4532 u32 connsw; 4533 u16 phy_data, retry_count = 20; 4534 4535 link = igb_has_link(adapter); 4536 4537 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4538 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4539 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4540 else 4541 link = false; 4542 } 4543 4544 /* Force link down if we have fiber to swap to */ 4545 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4546 if (hw->phy.media_type == e1000_media_type_copper) { 4547 connsw = rd32(E1000_CONNSW); 4548 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4549 link = 0; 4550 } 4551 } 4552 if (link) { 4553 /* Perform a reset if the media type changed. */ 4554 if (hw->dev_spec._82575.media_changed) { 4555 hw->dev_spec._82575.media_changed = false; 4556 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4557 igb_reset(adapter); 4558 } 4559 /* Cancel scheduled suspend requests. */ 4560 pm_runtime_resume(netdev->dev.parent); 4561 4562 if (!netif_carrier_ok(netdev)) { 4563 u32 ctrl; 4564 4565 hw->mac.ops.get_speed_and_duplex(hw, 4566 &adapter->link_speed, 4567 &adapter->link_duplex); 4568 4569 ctrl = rd32(E1000_CTRL); 4570 /* Links status message must follow this format */ 4571 netdev_info(netdev, 4572 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4573 netdev->name, 4574 adapter->link_speed, 4575 adapter->link_duplex == FULL_DUPLEX ? 4576 "Full" : "Half", 4577 (ctrl & E1000_CTRL_TFCE) && 4578 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4579 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4580 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4581 4582 /* disable EEE if enabled */ 4583 if ((adapter->flags & IGB_FLAG_EEE) && 4584 (adapter->link_duplex == HALF_DUPLEX)) { 4585 dev_info(&adapter->pdev->dev, 4586 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4587 adapter->hw.dev_spec._82575.eee_disable = true; 4588 adapter->flags &= ~IGB_FLAG_EEE; 4589 } 4590 4591 /* check if SmartSpeed worked */ 4592 igb_check_downshift(hw); 4593 if (phy->speed_downgraded) 4594 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4595 4596 /* check for thermal sensor event */ 4597 if (igb_thermal_sensor_event(hw, 4598 E1000_THSTAT_LINK_THROTTLE)) 4599 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4600 4601 /* adjust timeout factor according to speed/duplex */ 4602 adapter->tx_timeout_factor = 1; 4603 switch (adapter->link_speed) { 4604 case SPEED_10: 4605 adapter->tx_timeout_factor = 14; 4606 break; 4607 case SPEED_100: 4608 /* maybe add some timeout factor ? */ 4609 break; 4610 } 4611 4612 if (adapter->link_speed != SPEED_1000) 4613 goto no_wait; 4614 4615 /* wait for Remote receiver status OK */ 4616 retry_read_status: 4617 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4618 &phy_data)) { 4619 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4620 retry_count) { 4621 msleep(100); 4622 retry_count--; 4623 goto retry_read_status; 4624 } else if (!retry_count) { 4625 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4626 } 4627 } else { 4628 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4629 } 4630 no_wait: 4631 netif_carrier_on(netdev); 4632 4633 igb_ping_all_vfs(adapter); 4634 igb_check_vf_rate_limit(adapter); 4635 4636 /* link state has changed, schedule phy info update */ 4637 if (!test_bit(__IGB_DOWN, &adapter->state)) 4638 mod_timer(&adapter->phy_info_timer, 4639 round_jiffies(jiffies + 2 * HZ)); 4640 } 4641 } else { 4642 if (netif_carrier_ok(netdev)) { 4643 adapter->link_speed = 0; 4644 adapter->link_duplex = 0; 4645 4646 /* check for thermal sensor event */ 4647 if (igb_thermal_sensor_event(hw, 4648 E1000_THSTAT_PWR_DOWN)) { 4649 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4650 } 4651 4652 /* Links status message must follow this format */ 4653 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4654 netdev->name); 4655 netif_carrier_off(netdev); 4656 4657 igb_ping_all_vfs(adapter); 4658 4659 /* link state has changed, schedule phy info update */ 4660 if (!test_bit(__IGB_DOWN, &adapter->state)) 4661 mod_timer(&adapter->phy_info_timer, 4662 round_jiffies(jiffies + 2 * HZ)); 4663 4664 /* link is down, time to check for alternate media */ 4665 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4666 igb_check_swap_media(adapter); 4667 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4668 schedule_work(&adapter->reset_task); 4669 /* return immediately */ 4670 return; 4671 } 4672 } 4673 pm_schedule_suspend(netdev->dev.parent, 4674 MSEC_PER_SEC * 5); 4675 4676 /* also check for alternate media here */ 4677 } else if (!netif_carrier_ok(netdev) && 4678 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4679 igb_check_swap_media(adapter); 4680 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4681 schedule_work(&adapter->reset_task); 4682 /* return immediately */ 4683 return; 4684 } 4685 } 4686 } 4687 4688 spin_lock(&adapter->stats64_lock); 4689 igb_update_stats(adapter); 4690 spin_unlock(&adapter->stats64_lock); 4691 4692 for (i = 0; i < adapter->num_tx_queues; i++) { 4693 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4694 if (!netif_carrier_ok(netdev)) { 4695 /* We've lost link, so the controller stops DMA, 4696 * but we've got queued Tx work that's never going 4697 * to get done, so reset controller to flush Tx. 4698 * (Do the reset outside of interrupt context). 4699 */ 4700 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4701 adapter->tx_timeout_count++; 4702 schedule_work(&adapter->reset_task); 4703 /* return immediately since reset is imminent */ 4704 return; 4705 } 4706 } 4707 4708 /* Force detection of hung controller every watchdog period */ 4709 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4710 } 4711 4712 /* Cause software interrupt to ensure Rx ring is cleaned */ 4713 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4714 u32 eics = 0; 4715 4716 for (i = 0; i < adapter->num_q_vectors; i++) 4717 eics |= adapter->q_vector[i]->eims_value; 4718 wr32(E1000_EICS, eics); 4719 } else { 4720 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4721 } 4722 4723 igb_spoof_check(adapter); 4724 igb_ptp_rx_hang(adapter); 4725 igb_ptp_tx_hang(adapter); 4726 4727 /* Check LVMMC register on i350/i354 only */ 4728 if ((adapter->hw.mac.type == e1000_i350) || 4729 (adapter->hw.mac.type == e1000_i354)) 4730 igb_check_lvmmc(adapter); 4731 4732 /* Reset the timer */ 4733 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4734 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4735 mod_timer(&adapter->watchdog_timer, 4736 round_jiffies(jiffies + HZ)); 4737 else 4738 mod_timer(&adapter->watchdog_timer, 4739 round_jiffies(jiffies + 2 * HZ)); 4740 } 4741 } 4742 4743 enum latency_range { 4744 lowest_latency = 0, 4745 low_latency = 1, 4746 bulk_latency = 2, 4747 latency_invalid = 255 4748 }; 4749 4750 /** 4751 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4752 * @q_vector: pointer to q_vector 4753 * 4754 * Stores a new ITR value based on strictly on packet size. This 4755 * algorithm is less sophisticated than that used in igb_update_itr, 4756 * due to the difficulty of synchronizing statistics across multiple 4757 * receive rings. The divisors and thresholds used by this function 4758 * were determined based on theoretical maximum wire speed and testing 4759 * data, in order to minimize response time while increasing bulk 4760 * throughput. 4761 * This functionality is controlled by ethtool's coalescing settings. 4762 * NOTE: This function is called only when operating in a multiqueue 4763 * receive environment. 4764 **/ 4765 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4766 { 4767 int new_val = q_vector->itr_val; 4768 int avg_wire_size = 0; 4769 struct igb_adapter *adapter = q_vector->adapter; 4770 unsigned int packets; 4771 4772 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4773 * ints/sec - ITR timer value of 120 ticks. 4774 */ 4775 if (adapter->link_speed != SPEED_1000) { 4776 new_val = IGB_4K_ITR; 4777 goto set_itr_val; 4778 } 4779 4780 packets = q_vector->rx.total_packets; 4781 if (packets) 4782 avg_wire_size = q_vector->rx.total_bytes / packets; 4783 4784 packets = q_vector->tx.total_packets; 4785 if (packets) 4786 avg_wire_size = max_t(u32, avg_wire_size, 4787 q_vector->tx.total_bytes / packets); 4788 4789 /* if avg_wire_size isn't set no work was done */ 4790 if (!avg_wire_size) 4791 goto clear_counts; 4792 4793 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4794 avg_wire_size += 24; 4795 4796 /* Don't starve jumbo frames */ 4797 avg_wire_size = min(avg_wire_size, 3000); 4798 4799 /* Give a little boost to mid-size frames */ 4800 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4801 new_val = avg_wire_size / 3; 4802 else 4803 new_val = avg_wire_size / 2; 4804 4805 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4806 if (new_val < IGB_20K_ITR && 4807 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4808 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4809 new_val = IGB_20K_ITR; 4810 4811 set_itr_val: 4812 if (new_val != q_vector->itr_val) { 4813 q_vector->itr_val = new_val; 4814 q_vector->set_itr = 1; 4815 } 4816 clear_counts: 4817 q_vector->rx.total_bytes = 0; 4818 q_vector->rx.total_packets = 0; 4819 q_vector->tx.total_bytes = 0; 4820 q_vector->tx.total_packets = 0; 4821 } 4822 4823 /** 4824 * igb_update_itr - update the dynamic ITR value based on statistics 4825 * @q_vector: pointer to q_vector 4826 * @ring_container: ring info to update the itr for 4827 * 4828 * Stores a new ITR value based on packets and byte 4829 * counts during the last interrupt. The advantage of per interrupt 4830 * computation is faster updates and more accurate ITR for the current 4831 * traffic pattern. Constants in this function were computed 4832 * based on theoretical maximum wire speed and thresholds were set based 4833 * on testing data as well as attempting to minimize response time 4834 * while increasing bulk throughput. 4835 * This functionality is controlled by ethtool's coalescing settings. 4836 * NOTE: These calculations are only valid when operating in a single- 4837 * queue environment. 4838 **/ 4839 static void igb_update_itr(struct igb_q_vector *q_vector, 4840 struct igb_ring_container *ring_container) 4841 { 4842 unsigned int packets = ring_container->total_packets; 4843 unsigned int bytes = ring_container->total_bytes; 4844 u8 itrval = ring_container->itr; 4845 4846 /* no packets, exit with status unchanged */ 4847 if (packets == 0) 4848 return; 4849 4850 switch (itrval) { 4851 case lowest_latency: 4852 /* handle TSO and jumbo frames */ 4853 if (bytes/packets > 8000) 4854 itrval = bulk_latency; 4855 else if ((packets < 5) && (bytes > 512)) 4856 itrval = low_latency; 4857 break; 4858 case low_latency: /* 50 usec aka 20000 ints/s */ 4859 if (bytes > 10000) { 4860 /* this if handles the TSO accounting */ 4861 if (bytes/packets > 8000) 4862 itrval = bulk_latency; 4863 else if ((packets < 10) || ((bytes/packets) > 1200)) 4864 itrval = bulk_latency; 4865 else if ((packets > 35)) 4866 itrval = lowest_latency; 4867 } else if (bytes/packets > 2000) { 4868 itrval = bulk_latency; 4869 } else if (packets <= 2 && bytes < 512) { 4870 itrval = lowest_latency; 4871 } 4872 break; 4873 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4874 if (bytes > 25000) { 4875 if (packets > 35) 4876 itrval = low_latency; 4877 } else if (bytes < 1500) { 4878 itrval = low_latency; 4879 } 4880 break; 4881 } 4882 4883 /* clear work counters since we have the values we need */ 4884 ring_container->total_bytes = 0; 4885 ring_container->total_packets = 0; 4886 4887 /* write updated itr to ring container */ 4888 ring_container->itr = itrval; 4889 } 4890 4891 static void igb_set_itr(struct igb_q_vector *q_vector) 4892 { 4893 struct igb_adapter *adapter = q_vector->adapter; 4894 u32 new_itr = q_vector->itr_val; 4895 u8 current_itr = 0; 4896 4897 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4898 if (adapter->link_speed != SPEED_1000) { 4899 current_itr = 0; 4900 new_itr = IGB_4K_ITR; 4901 goto set_itr_now; 4902 } 4903 4904 igb_update_itr(q_vector, &q_vector->tx); 4905 igb_update_itr(q_vector, &q_vector->rx); 4906 4907 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4908 4909 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4910 if (current_itr == lowest_latency && 4911 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4912 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4913 current_itr = low_latency; 4914 4915 switch (current_itr) { 4916 /* counts and packets in update_itr are dependent on these numbers */ 4917 case lowest_latency: 4918 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4919 break; 4920 case low_latency: 4921 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4922 break; 4923 case bulk_latency: 4924 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4925 break; 4926 default: 4927 break; 4928 } 4929 4930 set_itr_now: 4931 if (new_itr != q_vector->itr_val) { 4932 /* this attempts to bias the interrupt rate towards Bulk 4933 * by adding intermediate steps when interrupt rate is 4934 * increasing 4935 */ 4936 new_itr = new_itr > q_vector->itr_val ? 4937 max((new_itr * q_vector->itr_val) / 4938 (new_itr + (q_vector->itr_val >> 2)), 4939 new_itr) : new_itr; 4940 /* Don't write the value here; it resets the adapter's 4941 * internal timer, and causes us to delay far longer than 4942 * we should between interrupts. Instead, we write the ITR 4943 * value at the beginning of the next interrupt so the timing 4944 * ends up being correct. 4945 */ 4946 q_vector->itr_val = new_itr; 4947 q_vector->set_itr = 1; 4948 } 4949 } 4950 4951 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4952 u32 type_tucmd, u32 mss_l4len_idx) 4953 { 4954 struct e1000_adv_tx_context_desc *context_desc; 4955 u16 i = tx_ring->next_to_use; 4956 4957 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4958 4959 i++; 4960 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4961 4962 /* set bits to identify this as an advanced context descriptor */ 4963 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4964 4965 /* For 82575, context index must be unique per ring. */ 4966 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4967 mss_l4len_idx |= tx_ring->reg_idx << 4; 4968 4969 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4970 context_desc->seqnum_seed = 0; 4971 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4972 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4973 } 4974 4975 static int igb_tso(struct igb_ring *tx_ring, 4976 struct igb_tx_buffer *first, 4977 u8 *hdr_len) 4978 { 4979 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4980 struct sk_buff *skb = first->skb; 4981 union { 4982 struct iphdr *v4; 4983 struct ipv6hdr *v6; 4984 unsigned char *hdr; 4985 } ip; 4986 union { 4987 struct tcphdr *tcp; 4988 unsigned char *hdr; 4989 } l4; 4990 u32 paylen, l4_offset; 4991 int err; 4992 4993 if (skb->ip_summed != CHECKSUM_PARTIAL) 4994 return 0; 4995 4996 if (!skb_is_gso(skb)) 4997 return 0; 4998 4999 err = skb_cow_head(skb, 0); 5000 if (err < 0) 5001 return err; 5002 5003 ip.hdr = skb_network_header(skb); 5004 l4.hdr = skb_checksum_start(skb); 5005 5006 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5007 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5008 5009 /* initialize outer IP header fields */ 5010 if (ip.v4->version == 4) { 5011 unsigned char *csum_start = skb_checksum_start(skb); 5012 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5013 5014 /* IP header will have to cancel out any data that 5015 * is not a part of the outer IP header 5016 */ 5017 ip.v4->check = csum_fold(csum_partial(trans_start, 5018 csum_start - trans_start, 5019 0)); 5020 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5021 5022 ip.v4->tot_len = 0; 5023 first->tx_flags |= IGB_TX_FLAGS_TSO | 5024 IGB_TX_FLAGS_CSUM | 5025 IGB_TX_FLAGS_IPV4; 5026 } else { 5027 ip.v6->payload_len = 0; 5028 first->tx_flags |= IGB_TX_FLAGS_TSO | 5029 IGB_TX_FLAGS_CSUM; 5030 } 5031 5032 /* determine offset of inner transport header */ 5033 l4_offset = l4.hdr - skb->data; 5034 5035 /* compute length of segmentation header */ 5036 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5037 5038 /* remove payload length from inner checksum */ 5039 paylen = skb->len - l4_offset; 5040 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5041 5042 /* update gso size and bytecount with header size */ 5043 first->gso_segs = skb_shinfo(skb)->gso_segs; 5044 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5045 5046 /* MSS L4LEN IDX */ 5047 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5048 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5049 5050 /* VLAN MACLEN IPLEN */ 5051 vlan_macip_lens = l4.hdr - ip.hdr; 5052 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5053 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5054 5055 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5056 5057 return 1; 5058 } 5059 5060 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5061 { 5062 unsigned int offset = 0; 5063 5064 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5065 5066 return offset == skb_checksum_start_offset(skb); 5067 } 5068 5069 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5070 { 5071 struct sk_buff *skb = first->skb; 5072 u32 vlan_macip_lens = 0; 5073 u32 type_tucmd = 0; 5074 5075 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5076 csum_failed: 5077 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5078 return; 5079 goto no_csum; 5080 } 5081 5082 switch (skb->csum_offset) { 5083 case offsetof(struct tcphdr, check): 5084 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5085 /* fall through */ 5086 case offsetof(struct udphdr, check): 5087 break; 5088 case offsetof(struct sctphdr, checksum): 5089 /* validate that this is actually an SCTP request */ 5090 if (((first->protocol == htons(ETH_P_IP)) && 5091 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5092 ((first->protocol == htons(ETH_P_IPV6)) && 5093 igb_ipv6_csum_is_sctp(skb))) { 5094 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5095 break; 5096 } 5097 default: 5098 skb_checksum_help(skb); 5099 goto csum_failed; 5100 } 5101 5102 /* update TX checksum flag */ 5103 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5104 vlan_macip_lens = skb_checksum_start_offset(skb) - 5105 skb_network_offset(skb); 5106 no_csum: 5107 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5108 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5109 5110 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5111 } 5112 5113 #define IGB_SET_FLAG(_input, _flag, _result) \ 5114 ((_flag <= _result) ? \ 5115 ((u32)(_input & _flag) * (_result / _flag)) : \ 5116 ((u32)(_input & _flag) / (_flag / _result))) 5117 5118 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5119 { 5120 /* set type for advanced descriptor with frame checksum insertion */ 5121 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5122 E1000_ADVTXD_DCMD_DEXT | 5123 E1000_ADVTXD_DCMD_IFCS; 5124 5125 /* set HW vlan bit if vlan is present */ 5126 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5127 (E1000_ADVTXD_DCMD_VLE)); 5128 5129 /* set segmentation bits for TSO */ 5130 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5131 (E1000_ADVTXD_DCMD_TSE)); 5132 5133 /* set timestamp bit if present */ 5134 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5135 (E1000_ADVTXD_MAC_TSTAMP)); 5136 5137 /* insert frame checksum */ 5138 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5139 5140 return cmd_type; 5141 } 5142 5143 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5144 union e1000_adv_tx_desc *tx_desc, 5145 u32 tx_flags, unsigned int paylen) 5146 { 5147 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5148 5149 /* 82575 requires a unique index per ring */ 5150 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5151 olinfo_status |= tx_ring->reg_idx << 4; 5152 5153 /* insert L4 checksum */ 5154 olinfo_status |= IGB_SET_FLAG(tx_flags, 5155 IGB_TX_FLAGS_CSUM, 5156 (E1000_TXD_POPTS_TXSM << 8)); 5157 5158 /* insert IPv4 checksum */ 5159 olinfo_status |= IGB_SET_FLAG(tx_flags, 5160 IGB_TX_FLAGS_IPV4, 5161 (E1000_TXD_POPTS_IXSM << 8)); 5162 5163 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5164 } 5165 5166 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5167 { 5168 struct net_device *netdev = tx_ring->netdev; 5169 5170 netif_stop_subqueue(netdev, tx_ring->queue_index); 5171 5172 /* Herbert's original patch had: 5173 * smp_mb__after_netif_stop_queue(); 5174 * but since that doesn't exist yet, just open code it. 5175 */ 5176 smp_mb(); 5177 5178 /* We need to check again in a case another CPU has just 5179 * made room available. 5180 */ 5181 if (igb_desc_unused(tx_ring) < size) 5182 return -EBUSY; 5183 5184 /* A reprieve! */ 5185 netif_wake_subqueue(netdev, tx_ring->queue_index); 5186 5187 u64_stats_update_begin(&tx_ring->tx_syncp2); 5188 tx_ring->tx_stats.restart_queue2++; 5189 u64_stats_update_end(&tx_ring->tx_syncp2); 5190 5191 return 0; 5192 } 5193 5194 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5195 { 5196 if (igb_desc_unused(tx_ring) >= size) 5197 return 0; 5198 return __igb_maybe_stop_tx(tx_ring, size); 5199 } 5200 5201 static int igb_tx_map(struct igb_ring *tx_ring, 5202 struct igb_tx_buffer *first, 5203 const u8 hdr_len) 5204 { 5205 struct sk_buff *skb = first->skb; 5206 struct igb_tx_buffer *tx_buffer; 5207 union e1000_adv_tx_desc *tx_desc; 5208 struct skb_frag_struct *frag; 5209 dma_addr_t dma; 5210 unsigned int data_len, size; 5211 u32 tx_flags = first->tx_flags; 5212 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5213 u16 i = tx_ring->next_to_use; 5214 5215 tx_desc = IGB_TX_DESC(tx_ring, i); 5216 5217 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5218 5219 size = skb_headlen(skb); 5220 data_len = skb->data_len; 5221 5222 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5223 5224 tx_buffer = first; 5225 5226 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5227 if (dma_mapping_error(tx_ring->dev, dma)) 5228 goto dma_error; 5229 5230 /* record length, and DMA address */ 5231 dma_unmap_len_set(tx_buffer, len, size); 5232 dma_unmap_addr_set(tx_buffer, dma, dma); 5233 5234 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5235 5236 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5237 tx_desc->read.cmd_type_len = 5238 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5239 5240 i++; 5241 tx_desc++; 5242 if (i == tx_ring->count) { 5243 tx_desc = IGB_TX_DESC(tx_ring, 0); 5244 i = 0; 5245 } 5246 tx_desc->read.olinfo_status = 0; 5247 5248 dma += IGB_MAX_DATA_PER_TXD; 5249 size -= IGB_MAX_DATA_PER_TXD; 5250 5251 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5252 } 5253 5254 if (likely(!data_len)) 5255 break; 5256 5257 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5258 5259 i++; 5260 tx_desc++; 5261 if (i == tx_ring->count) { 5262 tx_desc = IGB_TX_DESC(tx_ring, 0); 5263 i = 0; 5264 } 5265 tx_desc->read.olinfo_status = 0; 5266 5267 size = skb_frag_size(frag); 5268 data_len -= size; 5269 5270 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5271 size, DMA_TO_DEVICE); 5272 5273 tx_buffer = &tx_ring->tx_buffer_info[i]; 5274 } 5275 5276 /* write last descriptor with RS and EOP bits */ 5277 cmd_type |= size | IGB_TXD_DCMD; 5278 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5279 5280 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5281 5282 /* set the timestamp */ 5283 first->time_stamp = jiffies; 5284 5285 /* Force memory writes to complete before letting h/w know there 5286 * are new descriptors to fetch. (Only applicable for weak-ordered 5287 * memory model archs, such as IA-64). 5288 * 5289 * We also need this memory barrier to make certain all of the 5290 * status bits have been updated before next_to_watch is written. 5291 */ 5292 wmb(); 5293 5294 /* set next_to_watch value indicating a packet is present */ 5295 first->next_to_watch = tx_desc; 5296 5297 i++; 5298 if (i == tx_ring->count) 5299 i = 0; 5300 5301 tx_ring->next_to_use = i; 5302 5303 /* Make sure there is space in the ring for the next send. */ 5304 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5305 5306 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5307 writel(i, tx_ring->tail); 5308 5309 /* we need this if more than one processor can write to our tail 5310 * at a time, it synchronizes IO on IA64/Altix systems 5311 */ 5312 mmiowb(); 5313 } 5314 return 0; 5315 5316 dma_error: 5317 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5318 tx_buffer = &tx_ring->tx_buffer_info[i]; 5319 5320 /* clear dma mappings for failed tx_buffer_info map */ 5321 while (tx_buffer != first) { 5322 if (dma_unmap_len(tx_buffer, len)) 5323 dma_unmap_page(tx_ring->dev, 5324 dma_unmap_addr(tx_buffer, dma), 5325 dma_unmap_len(tx_buffer, len), 5326 DMA_TO_DEVICE); 5327 dma_unmap_len_set(tx_buffer, len, 0); 5328 5329 if (i--) 5330 i += tx_ring->count; 5331 tx_buffer = &tx_ring->tx_buffer_info[i]; 5332 } 5333 5334 if (dma_unmap_len(tx_buffer, len)) 5335 dma_unmap_single(tx_ring->dev, 5336 dma_unmap_addr(tx_buffer, dma), 5337 dma_unmap_len(tx_buffer, len), 5338 DMA_TO_DEVICE); 5339 dma_unmap_len_set(tx_buffer, len, 0); 5340 5341 dev_kfree_skb_any(tx_buffer->skb); 5342 tx_buffer->skb = NULL; 5343 5344 tx_ring->next_to_use = i; 5345 5346 return -1; 5347 } 5348 5349 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5350 struct igb_ring *tx_ring) 5351 { 5352 struct igb_tx_buffer *first; 5353 int tso; 5354 u32 tx_flags = 0; 5355 unsigned short f; 5356 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5357 __be16 protocol = vlan_get_protocol(skb); 5358 u8 hdr_len = 0; 5359 5360 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5361 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5362 * + 2 desc gap to keep tail from touching head, 5363 * + 1 desc for context descriptor, 5364 * otherwise try next time 5365 */ 5366 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5367 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5368 5369 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5370 /* this is a hard error */ 5371 return NETDEV_TX_BUSY; 5372 } 5373 5374 /* record the location of the first descriptor for this packet */ 5375 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5376 first->skb = skb; 5377 first->bytecount = skb->len; 5378 first->gso_segs = 1; 5379 5380 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5381 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5382 5383 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5384 &adapter->state)) { 5385 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5386 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5387 5388 adapter->ptp_tx_skb = skb_get(skb); 5389 adapter->ptp_tx_start = jiffies; 5390 if (adapter->hw.mac.type == e1000_82576) 5391 schedule_work(&adapter->ptp_tx_work); 5392 } else { 5393 adapter->tx_hwtstamp_skipped++; 5394 } 5395 } 5396 5397 skb_tx_timestamp(skb); 5398 5399 if (skb_vlan_tag_present(skb)) { 5400 tx_flags |= IGB_TX_FLAGS_VLAN; 5401 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5402 } 5403 5404 /* record initial flags and protocol */ 5405 first->tx_flags = tx_flags; 5406 first->protocol = protocol; 5407 5408 tso = igb_tso(tx_ring, first, &hdr_len); 5409 if (tso < 0) 5410 goto out_drop; 5411 else if (!tso) 5412 igb_tx_csum(tx_ring, first); 5413 5414 if (igb_tx_map(tx_ring, first, hdr_len)) 5415 goto cleanup_tx_tstamp; 5416 5417 return NETDEV_TX_OK; 5418 5419 out_drop: 5420 dev_kfree_skb_any(first->skb); 5421 first->skb = NULL; 5422 cleanup_tx_tstamp: 5423 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 5424 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5425 5426 dev_kfree_skb_any(adapter->ptp_tx_skb); 5427 adapter->ptp_tx_skb = NULL; 5428 if (adapter->hw.mac.type == e1000_82576) 5429 cancel_work_sync(&adapter->ptp_tx_work); 5430 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 5431 } 5432 5433 return NETDEV_TX_OK; 5434 } 5435 5436 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5437 struct sk_buff *skb) 5438 { 5439 unsigned int r_idx = skb->queue_mapping; 5440 5441 if (r_idx >= adapter->num_tx_queues) 5442 r_idx = r_idx % adapter->num_tx_queues; 5443 5444 return adapter->tx_ring[r_idx]; 5445 } 5446 5447 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5448 struct net_device *netdev) 5449 { 5450 struct igb_adapter *adapter = netdev_priv(netdev); 5451 5452 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5453 * in order to meet this minimum size requirement. 5454 */ 5455 if (skb_put_padto(skb, 17)) 5456 return NETDEV_TX_OK; 5457 5458 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5459 } 5460 5461 /** 5462 * igb_tx_timeout - Respond to a Tx Hang 5463 * @netdev: network interface device structure 5464 **/ 5465 static void igb_tx_timeout(struct net_device *netdev) 5466 { 5467 struct igb_adapter *adapter = netdev_priv(netdev); 5468 struct e1000_hw *hw = &adapter->hw; 5469 5470 /* Do the reset outside of interrupt context */ 5471 adapter->tx_timeout_count++; 5472 5473 if (hw->mac.type >= e1000_82580) 5474 hw->dev_spec._82575.global_device_reset = true; 5475 5476 schedule_work(&adapter->reset_task); 5477 wr32(E1000_EICS, 5478 (adapter->eims_enable_mask & ~adapter->eims_other)); 5479 } 5480 5481 static void igb_reset_task(struct work_struct *work) 5482 { 5483 struct igb_adapter *adapter; 5484 adapter = container_of(work, struct igb_adapter, reset_task); 5485 5486 igb_dump(adapter); 5487 netdev_err(adapter->netdev, "Reset adapter\n"); 5488 igb_reinit_locked(adapter); 5489 } 5490 5491 /** 5492 * igb_get_stats64 - Get System Network Statistics 5493 * @netdev: network interface device structure 5494 * @stats: rtnl_link_stats64 pointer 5495 **/ 5496 static void igb_get_stats64(struct net_device *netdev, 5497 struct rtnl_link_stats64 *stats) 5498 { 5499 struct igb_adapter *adapter = netdev_priv(netdev); 5500 5501 spin_lock(&adapter->stats64_lock); 5502 igb_update_stats(adapter); 5503 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5504 spin_unlock(&adapter->stats64_lock); 5505 } 5506 5507 /** 5508 * igb_change_mtu - Change the Maximum Transfer Unit 5509 * @netdev: network interface device structure 5510 * @new_mtu: new value for maximum frame size 5511 * 5512 * Returns 0 on success, negative on failure 5513 **/ 5514 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5515 { 5516 struct igb_adapter *adapter = netdev_priv(netdev); 5517 struct pci_dev *pdev = adapter->pdev; 5518 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5519 5520 /* adjust max frame to be at least the size of a standard frame */ 5521 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5522 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5523 5524 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5525 usleep_range(1000, 2000); 5526 5527 /* igb_down has a dependency on max_frame_size */ 5528 adapter->max_frame_size = max_frame; 5529 5530 if (netif_running(netdev)) 5531 igb_down(adapter); 5532 5533 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5534 netdev->mtu, new_mtu); 5535 netdev->mtu = new_mtu; 5536 5537 if (netif_running(netdev)) 5538 igb_up(adapter); 5539 else 5540 igb_reset(adapter); 5541 5542 clear_bit(__IGB_RESETTING, &adapter->state); 5543 5544 return 0; 5545 } 5546 5547 /** 5548 * igb_update_stats - Update the board statistics counters 5549 * @adapter: board private structure 5550 **/ 5551 void igb_update_stats(struct igb_adapter *adapter) 5552 { 5553 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 5554 struct e1000_hw *hw = &adapter->hw; 5555 struct pci_dev *pdev = adapter->pdev; 5556 u32 reg, mpc; 5557 int i; 5558 u64 bytes, packets; 5559 unsigned int start; 5560 u64 _bytes, _packets; 5561 5562 /* Prevent stats update while adapter is being reset, or if the pci 5563 * connection is down. 5564 */ 5565 if (adapter->link_speed == 0) 5566 return; 5567 if (pci_channel_offline(pdev)) 5568 return; 5569 5570 bytes = 0; 5571 packets = 0; 5572 5573 rcu_read_lock(); 5574 for (i = 0; i < adapter->num_rx_queues; i++) { 5575 struct igb_ring *ring = adapter->rx_ring[i]; 5576 u32 rqdpc = rd32(E1000_RQDPC(i)); 5577 if (hw->mac.type >= e1000_i210) 5578 wr32(E1000_RQDPC(i), 0); 5579 5580 if (rqdpc) { 5581 ring->rx_stats.drops += rqdpc; 5582 net_stats->rx_fifo_errors += rqdpc; 5583 } 5584 5585 do { 5586 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5587 _bytes = ring->rx_stats.bytes; 5588 _packets = ring->rx_stats.packets; 5589 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5590 bytes += _bytes; 5591 packets += _packets; 5592 } 5593 5594 net_stats->rx_bytes = bytes; 5595 net_stats->rx_packets = packets; 5596 5597 bytes = 0; 5598 packets = 0; 5599 for (i = 0; i < adapter->num_tx_queues; i++) { 5600 struct igb_ring *ring = adapter->tx_ring[i]; 5601 do { 5602 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5603 _bytes = ring->tx_stats.bytes; 5604 _packets = ring->tx_stats.packets; 5605 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5606 bytes += _bytes; 5607 packets += _packets; 5608 } 5609 net_stats->tx_bytes = bytes; 5610 net_stats->tx_packets = packets; 5611 rcu_read_unlock(); 5612 5613 /* read stats registers */ 5614 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5615 adapter->stats.gprc += rd32(E1000_GPRC); 5616 adapter->stats.gorc += rd32(E1000_GORCL); 5617 rd32(E1000_GORCH); /* clear GORCL */ 5618 adapter->stats.bprc += rd32(E1000_BPRC); 5619 adapter->stats.mprc += rd32(E1000_MPRC); 5620 adapter->stats.roc += rd32(E1000_ROC); 5621 5622 adapter->stats.prc64 += rd32(E1000_PRC64); 5623 adapter->stats.prc127 += rd32(E1000_PRC127); 5624 adapter->stats.prc255 += rd32(E1000_PRC255); 5625 adapter->stats.prc511 += rd32(E1000_PRC511); 5626 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5627 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5628 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5629 adapter->stats.sec += rd32(E1000_SEC); 5630 5631 mpc = rd32(E1000_MPC); 5632 adapter->stats.mpc += mpc; 5633 net_stats->rx_fifo_errors += mpc; 5634 adapter->stats.scc += rd32(E1000_SCC); 5635 adapter->stats.ecol += rd32(E1000_ECOL); 5636 adapter->stats.mcc += rd32(E1000_MCC); 5637 adapter->stats.latecol += rd32(E1000_LATECOL); 5638 adapter->stats.dc += rd32(E1000_DC); 5639 adapter->stats.rlec += rd32(E1000_RLEC); 5640 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5641 adapter->stats.xontxc += rd32(E1000_XONTXC); 5642 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5643 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5644 adapter->stats.fcruc += rd32(E1000_FCRUC); 5645 adapter->stats.gptc += rd32(E1000_GPTC); 5646 adapter->stats.gotc += rd32(E1000_GOTCL); 5647 rd32(E1000_GOTCH); /* clear GOTCL */ 5648 adapter->stats.rnbc += rd32(E1000_RNBC); 5649 adapter->stats.ruc += rd32(E1000_RUC); 5650 adapter->stats.rfc += rd32(E1000_RFC); 5651 adapter->stats.rjc += rd32(E1000_RJC); 5652 adapter->stats.tor += rd32(E1000_TORH); 5653 adapter->stats.tot += rd32(E1000_TOTH); 5654 adapter->stats.tpr += rd32(E1000_TPR); 5655 5656 adapter->stats.ptc64 += rd32(E1000_PTC64); 5657 adapter->stats.ptc127 += rd32(E1000_PTC127); 5658 adapter->stats.ptc255 += rd32(E1000_PTC255); 5659 adapter->stats.ptc511 += rd32(E1000_PTC511); 5660 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5661 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5662 5663 adapter->stats.mptc += rd32(E1000_MPTC); 5664 adapter->stats.bptc += rd32(E1000_BPTC); 5665 5666 adapter->stats.tpt += rd32(E1000_TPT); 5667 adapter->stats.colc += rd32(E1000_COLC); 5668 5669 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5670 /* read internal phy specific stats */ 5671 reg = rd32(E1000_CTRL_EXT); 5672 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5673 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5674 5675 /* this stat has invalid values on i210/i211 */ 5676 if ((hw->mac.type != e1000_i210) && 5677 (hw->mac.type != e1000_i211)) 5678 adapter->stats.tncrs += rd32(E1000_TNCRS); 5679 } 5680 5681 adapter->stats.tsctc += rd32(E1000_TSCTC); 5682 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5683 5684 adapter->stats.iac += rd32(E1000_IAC); 5685 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5686 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5687 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5688 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5689 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5690 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5691 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5692 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5693 5694 /* Fill out the OS statistics structure */ 5695 net_stats->multicast = adapter->stats.mprc; 5696 net_stats->collisions = adapter->stats.colc; 5697 5698 /* Rx Errors */ 5699 5700 /* RLEC on some newer hardware can be incorrect so build 5701 * our own version based on RUC and ROC 5702 */ 5703 net_stats->rx_errors = adapter->stats.rxerrc + 5704 adapter->stats.crcerrs + adapter->stats.algnerrc + 5705 adapter->stats.ruc + adapter->stats.roc + 5706 adapter->stats.cexterr; 5707 net_stats->rx_length_errors = adapter->stats.ruc + 5708 adapter->stats.roc; 5709 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5710 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5711 net_stats->rx_missed_errors = adapter->stats.mpc; 5712 5713 /* Tx Errors */ 5714 net_stats->tx_errors = adapter->stats.ecol + 5715 adapter->stats.latecol; 5716 net_stats->tx_aborted_errors = adapter->stats.ecol; 5717 net_stats->tx_window_errors = adapter->stats.latecol; 5718 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5719 5720 /* Tx Dropped needs to be maintained elsewhere */ 5721 5722 /* Management Stats */ 5723 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5724 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5725 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5726 5727 /* OS2BMC Stats */ 5728 reg = rd32(E1000_MANC); 5729 if (reg & E1000_MANC_EN_BMC2OS) { 5730 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5731 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5732 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5733 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5734 } 5735 } 5736 5737 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5738 { 5739 struct e1000_hw *hw = &adapter->hw; 5740 struct ptp_clock_event event; 5741 struct timespec64 ts; 5742 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5743 5744 if (tsicr & TSINTR_SYS_WRAP) { 5745 event.type = PTP_CLOCK_PPS; 5746 if (adapter->ptp_caps.pps) 5747 ptp_clock_event(adapter->ptp_clock, &event); 5748 else 5749 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5750 ack |= TSINTR_SYS_WRAP; 5751 } 5752 5753 if (tsicr & E1000_TSICR_TXTS) { 5754 /* retrieve hardware timestamp */ 5755 schedule_work(&adapter->ptp_tx_work); 5756 ack |= E1000_TSICR_TXTS; 5757 } 5758 5759 if (tsicr & TSINTR_TT0) { 5760 spin_lock(&adapter->tmreg_lock); 5761 ts = timespec64_add(adapter->perout[0].start, 5762 adapter->perout[0].period); 5763 /* u32 conversion of tv_sec is safe until y2106 */ 5764 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5765 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5766 tsauxc = rd32(E1000_TSAUXC); 5767 tsauxc |= TSAUXC_EN_TT0; 5768 wr32(E1000_TSAUXC, tsauxc); 5769 adapter->perout[0].start = ts; 5770 spin_unlock(&adapter->tmreg_lock); 5771 ack |= TSINTR_TT0; 5772 } 5773 5774 if (tsicr & TSINTR_TT1) { 5775 spin_lock(&adapter->tmreg_lock); 5776 ts = timespec64_add(adapter->perout[1].start, 5777 adapter->perout[1].period); 5778 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5779 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5780 tsauxc = rd32(E1000_TSAUXC); 5781 tsauxc |= TSAUXC_EN_TT1; 5782 wr32(E1000_TSAUXC, tsauxc); 5783 adapter->perout[1].start = ts; 5784 spin_unlock(&adapter->tmreg_lock); 5785 ack |= TSINTR_TT1; 5786 } 5787 5788 if (tsicr & TSINTR_AUTT0) { 5789 nsec = rd32(E1000_AUXSTMPL0); 5790 sec = rd32(E1000_AUXSTMPH0); 5791 event.type = PTP_CLOCK_EXTTS; 5792 event.index = 0; 5793 event.timestamp = sec * 1000000000ULL + nsec; 5794 ptp_clock_event(adapter->ptp_clock, &event); 5795 ack |= TSINTR_AUTT0; 5796 } 5797 5798 if (tsicr & TSINTR_AUTT1) { 5799 nsec = rd32(E1000_AUXSTMPL1); 5800 sec = rd32(E1000_AUXSTMPH1); 5801 event.type = PTP_CLOCK_EXTTS; 5802 event.index = 1; 5803 event.timestamp = sec * 1000000000ULL + nsec; 5804 ptp_clock_event(adapter->ptp_clock, &event); 5805 ack |= TSINTR_AUTT1; 5806 } 5807 5808 /* acknowledge the interrupts */ 5809 wr32(E1000_TSICR, ack); 5810 } 5811 5812 static irqreturn_t igb_msix_other(int irq, void *data) 5813 { 5814 struct igb_adapter *adapter = data; 5815 struct e1000_hw *hw = &adapter->hw; 5816 u32 icr = rd32(E1000_ICR); 5817 /* reading ICR causes bit 31 of EICR to be cleared */ 5818 5819 if (icr & E1000_ICR_DRSTA) 5820 schedule_work(&adapter->reset_task); 5821 5822 if (icr & E1000_ICR_DOUTSYNC) { 5823 /* HW is reporting DMA is out of sync */ 5824 adapter->stats.doosync++; 5825 /* The DMA Out of Sync is also indication of a spoof event 5826 * in IOV mode. Check the Wrong VM Behavior register to 5827 * see if it is really a spoof event. 5828 */ 5829 igb_check_wvbr(adapter); 5830 } 5831 5832 /* Check for a mailbox event */ 5833 if (icr & E1000_ICR_VMMB) 5834 igb_msg_task(adapter); 5835 5836 if (icr & E1000_ICR_LSC) { 5837 hw->mac.get_link_status = 1; 5838 /* guard against interrupt when we're going down */ 5839 if (!test_bit(__IGB_DOWN, &adapter->state)) 5840 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5841 } 5842 5843 if (icr & E1000_ICR_TS) 5844 igb_tsync_interrupt(adapter); 5845 5846 wr32(E1000_EIMS, adapter->eims_other); 5847 5848 return IRQ_HANDLED; 5849 } 5850 5851 static void igb_write_itr(struct igb_q_vector *q_vector) 5852 { 5853 struct igb_adapter *adapter = q_vector->adapter; 5854 u32 itr_val = q_vector->itr_val & 0x7FFC; 5855 5856 if (!q_vector->set_itr) 5857 return; 5858 5859 if (!itr_val) 5860 itr_val = 0x4; 5861 5862 if (adapter->hw.mac.type == e1000_82575) 5863 itr_val |= itr_val << 16; 5864 else 5865 itr_val |= E1000_EITR_CNT_IGNR; 5866 5867 writel(itr_val, q_vector->itr_register); 5868 q_vector->set_itr = 0; 5869 } 5870 5871 static irqreturn_t igb_msix_ring(int irq, void *data) 5872 { 5873 struct igb_q_vector *q_vector = data; 5874 5875 /* Write the ITR value calculated from the previous interrupt. */ 5876 igb_write_itr(q_vector); 5877 5878 napi_schedule(&q_vector->napi); 5879 5880 return IRQ_HANDLED; 5881 } 5882 5883 #ifdef CONFIG_IGB_DCA 5884 static void igb_update_tx_dca(struct igb_adapter *adapter, 5885 struct igb_ring *tx_ring, 5886 int cpu) 5887 { 5888 struct e1000_hw *hw = &adapter->hw; 5889 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5890 5891 if (hw->mac.type != e1000_82575) 5892 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5893 5894 /* We can enable relaxed ordering for reads, but not writes when 5895 * DCA is enabled. This is due to a known issue in some chipsets 5896 * which will cause the DCA tag to be cleared. 5897 */ 5898 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5899 E1000_DCA_TXCTRL_DATA_RRO_EN | 5900 E1000_DCA_TXCTRL_DESC_DCA_EN; 5901 5902 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5903 } 5904 5905 static void igb_update_rx_dca(struct igb_adapter *adapter, 5906 struct igb_ring *rx_ring, 5907 int cpu) 5908 { 5909 struct e1000_hw *hw = &adapter->hw; 5910 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5911 5912 if (hw->mac.type != e1000_82575) 5913 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5914 5915 /* We can enable relaxed ordering for reads, but not writes when 5916 * DCA is enabled. This is due to a known issue in some chipsets 5917 * which will cause the DCA tag to be cleared. 5918 */ 5919 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5920 E1000_DCA_RXCTRL_DESC_DCA_EN; 5921 5922 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5923 } 5924 5925 static void igb_update_dca(struct igb_q_vector *q_vector) 5926 { 5927 struct igb_adapter *adapter = q_vector->adapter; 5928 int cpu = get_cpu(); 5929 5930 if (q_vector->cpu == cpu) 5931 goto out_no_update; 5932 5933 if (q_vector->tx.ring) 5934 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5935 5936 if (q_vector->rx.ring) 5937 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5938 5939 q_vector->cpu = cpu; 5940 out_no_update: 5941 put_cpu(); 5942 } 5943 5944 static void igb_setup_dca(struct igb_adapter *adapter) 5945 { 5946 struct e1000_hw *hw = &adapter->hw; 5947 int i; 5948 5949 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5950 return; 5951 5952 /* Always use CB2 mode, difference is masked in the CB driver. */ 5953 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5954 5955 for (i = 0; i < adapter->num_q_vectors; i++) { 5956 adapter->q_vector[i]->cpu = -1; 5957 igb_update_dca(adapter->q_vector[i]); 5958 } 5959 } 5960 5961 static int __igb_notify_dca(struct device *dev, void *data) 5962 { 5963 struct net_device *netdev = dev_get_drvdata(dev); 5964 struct igb_adapter *adapter = netdev_priv(netdev); 5965 struct pci_dev *pdev = adapter->pdev; 5966 struct e1000_hw *hw = &adapter->hw; 5967 unsigned long event = *(unsigned long *)data; 5968 5969 switch (event) { 5970 case DCA_PROVIDER_ADD: 5971 /* if already enabled, don't do it again */ 5972 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5973 break; 5974 if (dca_add_requester(dev) == 0) { 5975 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5976 dev_info(&pdev->dev, "DCA enabled\n"); 5977 igb_setup_dca(adapter); 5978 break; 5979 } 5980 /* Fall Through since DCA is disabled. */ 5981 case DCA_PROVIDER_REMOVE: 5982 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5983 /* without this a class_device is left 5984 * hanging around in the sysfs model 5985 */ 5986 dca_remove_requester(dev); 5987 dev_info(&pdev->dev, "DCA disabled\n"); 5988 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5989 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5990 } 5991 break; 5992 } 5993 5994 return 0; 5995 } 5996 5997 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5998 void *p) 5999 { 6000 int ret_val; 6001 6002 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 6003 __igb_notify_dca); 6004 6005 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 6006 } 6007 #endif /* CONFIG_IGB_DCA */ 6008 6009 #ifdef CONFIG_PCI_IOV 6010 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 6011 { 6012 unsigned char mac_addr[ETH_ALEN]; 6013 6014 eth_zero_addr(mac_addr); 6015 igb_set_vf_mac(adapter, vf, mac_addr); 6016 6017 /* By default spoof check is enabled for all VFs */ 6018 adapter->vf_data[vf].spoofchk_enabled = true; 6019 6020 return 0; 6021 } 6022 6023 #endif 6024 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6025 { 6026 struct e1000_hw *hw = &adapter->hw; 6027 u32 ping; 6028 int i; 6029 6030 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6031 ping = E1000_PF_CONTROL_MSG; 6032 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6033 ping |= E1000_VT_MSGTYPE_CTS; 6034 igb_write_mbx(hw, &ping, 1, i); 6035 } 6036 } 6037 6038 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6039 { 6040 struct e1000_hw *hw = &adapter->hw; 6041 u32 vmolr = rd32(E1000_VMOLR(vf)); 6042 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6043 6044 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6045 IGB_VF_FLAG_MULTI_PROMISC); 6046 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6047 6048 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6049 vmolr |= E1000_VMOLR_MPME; 6050 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6051 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6052 } else { 6053 /* if we have hashes and we are clearing a multicast promisc 6054 * flag we need to write the hashes to the MTA as this step 6055 * was previously skipped 6056 */ 6057 if (vf_data->num_vf_mc_hashes > 30) { 6058 vmolr |= E1000_VMOLR_MPME; 6059 } else if (vf_data->num_vf_mc_hashes) { 6060 int j; 6061 6062 vmolr |= E1000_VMOLR_ROMPE; 6063 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6064 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6065 } 6066 } 6067 6068 wr32(E1000_VMOLR(vf), vmolr); 6069 6070 /* there are flags left unprocessed, likely not supported */ 6071 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6072 return -EINVAL; 6073 6074 return 0; 6075 } 6076 6077 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6078 u32 *msgbuf, u32 vf) 6079 { 6080 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6081 u16 *hash_list = (u16 *)&msgbuf[1]; 6082 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6083 int i; 6084 6085 /* salt away the number of multicast addresses assigned 6086 * to this VF for later use to restore when the PF multi cast 6087 * list changes 6088 */ 6089 vf_data->num_vf_mc_hashes = n; 6090 6091 /* only up to 30 hash values supported */ 6092 if (n > 30) 6093 n = 30; 6094 6095 /* store the hashes for later use */ 6096 for (i = 0; i < n; i++) 6097 vf_data->vf_mc_hashes[i] = hash_list[i]; 6098 6099 /* Flush and reset the mta with the new values */ 6100 igb_set_rx_mode(adapter->netdev); 6101 6102 return 0; 6103 } 6104 6105 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6106 { 6107 struct e1000_hw *hw = &adapter->hw; 6108 struct vf_data_storage *vf_data; 6109 int i, j; 6110 6111 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6112 u32 vmolr = rd32(E1000_VMOLR(i)); 6113 6114 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6115 6116 vf_data = &adapter->vf_data[i]; 6117 6118 if ((vf_data->num_vf_mc_hashes > 30) || 6119 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6120 vmolr |= E1000_VMOLR_MPME; 6121 } else if (vf_data->num_vf_mc_hashes) { 6122 vmolr |= E1000_VMOLR_ROMPE; 6123 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6124 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6125 } 6126 wr32(E1000_VMOLR(i), vmolr); 6127 } 6128 } 6129 6130 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6131 { 6132 struct e1000_hw *hw = &adapter->hw; 6133 u32 pool_mask, vlvf_mask, i; 6134 6135 /* create mask for VF and other pools */ 6136 pool_mask = E1000_VLVF_POOLSEL_MASK; 6137 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6138 6139 /* drop PF from pool bits */ 6140 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6141 adapter->vfs_allocated_count); 6142 6143 /* Find the vlan filter for this id */ 6144 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6145 u32 vlvf = rd32(E1000_VLVF(i)); 6146 u32 vfta_mask, vid, vfta; 6147 6148 /* remove the vf from the pool */ 6149 if (!(vlvf & vlvf_mask)) 6150 continue; 6151 6152 /* clear out bit from VLVF */ 6153 vlvf ^= vlvf_mask; 6154 6155 /* if other pools are present, just remove ourselves */ 6156 if (vlvf & pool_mask) 6157 goto update_vlvfb; 6158 6159 /* if PF is present, leave VFTA */ 6160 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6161 goto update_vlvf; 6162 6163 vid = vlvf & E1000_VLVF_VLANID_MASK; 6164 vfta_mask = BIT(vid % 32); 6165 6166 /* clear bit from VFTA */ 6167 vfta = adapter->shadow_vfta[vid / 32]; 6168 if (vfta & vfta_mask) 6169 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6170 update_vlvf: 6171 /* clear pool selection enable */ 6172 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6173 vlvf &= E1000_VLVF_POOLSEL_MASK; 6174 else 6175 vlvf = 0; 6176 update_vlvfb: 6177 /* clear pool bits */ 6178 wr32(E1000_VLVF(i), vlvf); 6179 } 6180 } 6181 6182 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6183 { 6184 u32 vlvf; 6185 int idx; 6186 6187 /* short cut the special case */ 6188 if (vlan == 0) 6189 return 0; 6190 6191 /* Search for the VLAN id in the VLVF entries */ 6192 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6193 vlvf = rd32(E1000_VLVF(idx)); 6194 if ((vlvf & VLAN_VID_MASK) == vlan) 6195 break; 6196 } 6197 6198 return idx; 6199 } 6200 6201 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6202 { 6203 struct e1000_hw *hw = &adapter->hw; 6204 u32 bits, pf_id; 6205 int idx; 6206 6207 idx = igb_find_vlvf_entry(hw, vid); 6208 if (!idx) 6209 return; 6210 6211 /* See if any other pools are set for this VLAN filter 6212 * entry other than the PF. 6213 */ 6214 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6215 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6216 bits &= rd32(E1000_VLVF(idx)); 6217 6218 /* Disable the filter so this falls into the default pool. */ 6219 if (!bits) { 6220 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6221 wr32(E1000_VLVF(idx), BIT(pf_id)); 6222 else 6223 wr32(E1000_VLVF(idx), 0); 6224 } 6225 } 6226 6227 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6228 bool add, u32 vf) 6229 { 6230 int pf_id = adapter->vfs_allocated_count; 6231 struct e1000_hw *hw = &adapter->hw; 6232 int err; 6233 6234 /* If VLAN overlaps with one the PF is currently monitoring make 6235 * sure that we are able to allocate a VLVF entry. This may be 6236 * redundant but it guarantees PF will maintain visibility to 6237 * the VLAN. 6238 */ 6239 if (add && test_bit(vid, adapter->active_vlans)) { 6240 err = igb_vfta_set(hw, vid, pf_id, true, false); 6241 if (err) 6242 return err; 6243 } 6244 6245 err = igb_vfta_set(hw, vid, vf, add, false); 6246 6247 if (add && !err) 6248 return err; 6249 6250 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6251 * we may need to drop the PF pool bit in order to allow us to free 6252 * up the VLVF resources. 6253 */ 6254 if (test_bit(vid, adapter->active_vlans) || 6255 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6256 igb_update_pf_vlvf(adapter, vid); 6257 6258 return err; 6259 } 6260 6261 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6262 { 6263 struct e1000_hw *hw = &adapter->hw; 6264 6265 if (vid) 6266 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6267 else 6268 wr32(E1000_VMVIR(vf), 0); 6269 } 6270 6271 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6272 u16 vlan, u8 qos) 6273 { 6274 int err; 6275 6276 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6277 if (err) 6278 return err; 6279 6280 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6281 igb_set_vmolr(adapter, vf, !vlan); 6282 6283 /* revoke access to previous VLAN */ 6284 if (vlan != adapter->vf_data[vf].pf_vlan) 6285 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6286 false, vf); 6287 6288 adapter->vf_data[vf].pf_vlan = vlan; 6289 adapter->vf_data[vf].pf_qos = qos; 6290 igb_set_vf_vlan_strip(adapter, vf, true); 6291 dev_info(&adapter->pdev->dev, 6292 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6293 if (test_bit(__IGB_DOWN, &adapter->state)) { 6294 dev_warn(&adapter->pdev->dev, 6295 "The VF VLAN has been set, but the PF device is not up.\n"); 6296 dev_warn(&adapter->pdev->dev, 6297 "Bring the PF device up before attempting to use the VF device.\n"); 6298 } 6299 6300 return err; 6301 } 6302 6303 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6304 { 6305 /* Restore tagless access via VLAN 0 */ 6306 igb_set_vf_vlan(adapter, 0, true, vf); 6307 6308 igb_set_vmvir(adapter, 0, vf); 6309 igb_set_vmolr(adapter, vf, true); 6310 6311 /* Remove any PF assigned VLAN */ 6312 if (adapter->vf_data[vf].pf_vlan) 6313 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6314 false, vf); 6315 6316 adapter->vf_data[vf].pf_vlan = 0; 6317 adapter->vf_data[vf].pf_qos = 0; 6318 igb_set_vf_vlan_strip(adapter, vf, false); 6319 6320 return 0; 6321 } 6322 6323 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6324 u16 vlan, u8 qos, __be16 vlan_proto) 6325 { 6326 struct igb_adapter *adapter = netdev_priv(netdev); 6327 6328 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6329 return -EINVAL; 6330 6331 if (vlan_proto != htons(ETH_P_8021Q)) 6332 return -EPROTONOSUPPORT; 6333 6334 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6335 igb_disable_port_vlan(adapter, vf); 6336 } 6337 6338 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6339 { 6340 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6341 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6342 int ret; 6343 6344 if (adapter->vf_data[vf].pf_vlan) 6345 return -1; 6346 6347 /* VLAN 0 is a special case, don't allow it to be removed */ 6348 if (!vid && !add) 6349 return 0; 6350 6351 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6352 if (!ret) 6353 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6354 return ret; 6355 } 6356 6357 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6358 { 6359 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6360 6361 /* clear flags - except flag that indicates PF has set the MAC */ 6362 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6363 vf_data->last_nack = jiffies; 6364 6365 /* reset vlans for device */ 6366 igb_clear_vf_vfta(adapter, vf); 6367 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6368 igb_set_vmvir(adapter, vf_data->pf_vlan | 6369 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6370 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6371 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6372 6373 /* reset multicast table array for vf */ 6374 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6375 6376 /* Flush and reset the mta with the new values */ 6377 igb_set_rx_mode(adapter->netdev); 6378 } 6379 6380 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6381 { 6382 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6383 6384 /* clear mac address as we were hotplug removed/added */ 6385 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6386 eth_zero_addr(vf_mac); 6387 6388 /* process remaining reset events */ 6389 igb_vf_reset(adapter, vf); 6390 } 6391 6392 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6393 { 6394 struct e1000_hw *hw = &adapter->hw; 6395 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6396 u32 reg, msgbuf[3]; 6397 u8 *addr = (u8 *)(&msgbuf[1]); 6398 6399 /* process all the same items cleared in a function level reset */ 6400 igb_vf_reset(adapter, vf); 6401 6402 /* set vf mac address */ 6403 igb_set_vf_mac(adapter, vf, vf_mac); 6404 6405 /* enable transmit and receive for vf */ 6406 reg = rd32(E1000_VFTE); 6407 wr32(E1000_VFTE, reg | BIT(vf)); 6408 reg = rd32(E1000_VFRE); 6409 wr32(E1000_VFRE, reg | BIT(vf)); 6410 6411 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6412 6413 /* reply to reset with ack and vf mac address */ 6414 if (!is_zero_ether_addr(vf_mac)) { 6415 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6416 memcpy(addr, vf_mac, ETH_ALEN); 6417 } else { 6418 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6419 } 6420 igb_write_mbx(hw, msgbuf, 3, vf); 6421 } 6422 6423 static void igb_flush_mac_table(struct igb_adapter *adapter) 6424 { 6425 struct e1000_hw *hw = &adapter->hw; 6426 int i; 6427 6428 for (i = 0; i < hw->mac.rar_entry_count; i++) { 6429 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6430 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6431 adapter->mac_table[i].queue = 0; 6432 igb_rar_set_index(adapter, i); 6433 } 6434 } 6435 6436 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 6437 { 6438 struct e1000_hw *hw = &adapter->hw; 6439 /* do not count rar entries reserved for VFs MAC addresses */ 6440 int rar_entries = hw->mac.rar_entry_count - 6441 adapter->vfs_allocated_count; 6442 int i, count = 0; 6443 6444 for (i = 0; i < rar_entries; i++) { 6445 /* do not count default entries */ 6446 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 6447 continue; 6448 6449 /* do not count "in use" entries for different queues */ 6450 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 6451 (adapter->mac_table[i].queue != queue)) 6452 continue; 6453 6454 count++; 6455 } 6456 6457 return count; 6458 } 6459 6460 /* Set default MAC address for the PF in the first RAR entry */ 6461 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 6462 { 6463 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 6464 6465 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 6466 mac_table->queue = adapter->vfs_allocated_count; 6467 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 6468 6469 igb_rar_set_index(adapter, 0); 6470 } 6471 6472 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6473 const u8 queue) 6474 { 6475 struct e1000_hw *hw = &adapter->hw; 6476 int rar_entries = hw->mac.rar_entry_count - 6477 adapter->vfs_allocated_count; 6478 int i; 6479 6480 if (is_zero_ether_addr(addr)) 6481 return -EINVAL; 6482 6483 /* Search for the first empty entry in the MAC table. 6484 * Do not touch entries at the end of the table reserved for the VF MAC 6485 * addresses. 6486 */ 6487 for (i = 0; i < rar_entries; i++) { 6488 if (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) 6489 continue; 6490 6491 ether_addr_copy(adapter->mac_table[i].addr, addr); 6492 adapter->mac_table[i].queue = queue; 6493 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE; 6494 6495 igb_rar_set_index(adapter, i); 6496 return i; 6497 } 6498 6499 return -ENOSPC; 6500 } 6501 6502 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6503 const u8 queue) 6504 { 6505 struct e1000_hw *hw = &adapter->hw; 6506 int rar_entries = hw->mac.rar_entry_count - 6507 adapter->vfs_allocated_count; 6508 int i; 6509 6510 if (is_zero_ether_addr(addr)) 6511 return -EINVAL; 6512 6513 /* Search for matching entry in the MAC table based on given address 6514 * and queue. Do not touch entries at the end of the table reserved 6515 * for the VF MAC addresses. 6516 */ 6517 for (i = 0; i < rar_entries; i++) { 6518 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 6519 continue; 6520 if (adapter->mac_table[i].queue != queue) 6521 continue; 6522 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 6523 continue; 6524 6525 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6526 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6527 adapter->mac_table[i].queue = 0; 6528 6529 igb_rar_set_index(adapter, i); 6530 return 0; 6531 } 6532 6533 return -ENOENT; 6534 } 6535 6536 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 6537 { 6538 struct igb_adapter *adapter = netdev_priv(netdev); 6539 int ret; 6540 6541 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6542 6543 return min_t(int, ret, 0); 6544 } 6545 6546 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 6547 { 6548 struct igb_adapter *adapter = netdev_priv(netdev); 6549 6550 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6551 6552 return 0; 6553 } 6554 6555 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 6556 const u32 info, const u8 *addr) 6557 { 6558 struct pci_dev *pdev = adapter->pdev; 6559 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6560 struct list_head *pos; 6561 struct vf_mac_filter *entry = NULL; 6562 int ret = 0; 6563 6564 switch (info) { 6565 case E1000_VF_MAC_FILTER_CLR: 6566 /* remove all unicast MAC filters related to the current VF */ 6567 list_for_each(pos, &adapter->vf_macs.l) { 6568 entry = list_entry(pos, struct vf_mac_filter, l); 6569 if (entry->vf == vf) { 6570 entry->vf = -1; 6571 entry->free = true; 6572 igb_del_mac_filter(adapter, entry->vf_mac, vf); 6573 } 6574 } 6575 break; 6576 case E1000_VF_MAC_FILTER_ADD: 6577 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6578 dev_warn(&pdev->dev, 6579 "VF %d requested MAC filter but is administratively denied\n", 6580 vf); 6581 return -EINVAL; 6582 } 6583 6584 if (!is_valid_ether_addr(addr)) { 6585 dev_warn(&pdev->dev, 6586 "VF %d attempted to set invalid MAC filter\n", 6587 vf); 6588 return -EINVAL; 6589 } 6590 6591 /* try to find empty slot in the list */ 6592 list_for_each(pos, &adapter->vf_macs.l) { 6593 entry = list_entry(pos, struct vf_mac_filter, l); 6594 if (entry->free) 6595 break; 6596 } 6597 6598 if (entry && entry->free) { 6599 entry->free = false; 6600 entry->vf = vf; 6601 ether_addr_copy(entry->vf_mac, addr); 6602 6603 ret = igb_add_mac_filter(adapter, addr, vf); 6604 ret = min_t(int, ret, 0); 6605 } else { 6606 ret = -ENOSPC; 6607 } 6608 6609 if (ret == -ENOSPC) 6610 dev_warn(&pdev->dev, 6611 "VF %d has requested MAC filter but there is no space for it\n", 6612 vf); 6613 break; 6614 default: 6615 ret = -EINVAL; 6616 break; 6617 } 6618 6619 return ret; 6620 } 6621 6622 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6623 { 6624 struct pci_dev *pdev = adapter->pdev; 6625 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6626 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 6627 6628 /* The VF MAC Address is stored in a packed array of bytes 6629 * starting at the second 32 bit word of the msg array 6630 */ 6631 unsigned char *addr = (unsigned char *)&msg[1]; 6632 int ret = 0; 6633 6634 if (!info) { 6635 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6636 dev_warn(&pdev->dev, 6637 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6638 vf); 6639 return -EINVAL; 6640 } 6641 6642 if (!is_valid_ether_addr(addr)) { 6643 dev_warn(&pdev->dev, 6644 "VF %d attempted to set invalid MAC\n", 6645 vf); 6646 return -EINVAL; 6647 } 6648 6649 ret = igb_set_vf_mac(adapter, vf, addr); 6650 } else { 6651 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 6652 } 6653 6654 return ret; 6655 } 6656 6657 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6658 { 6659 struct e1000_hw *hw = &adapter->hw; 6660 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6661 u32 msg = E1000_VT_MSGTYPE_NACK; 6662 6663 /* if device isn't clear to send it shouldn't be reading either */ 6664 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6665 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6666 igb_write_mbx(hw, &msg, 1, vf); 6667 vf_data->last_nack = jiffies; 6668 } 6669 } 6670 6671 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6672 { 6673 struct pci_dev *pdev = adapter->pdev; 6674 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6675 struct e1000_hw *hw = &adapter->hw; 6676 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6677 s32 retval; 6678 6679 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6680 6681 if (retval) { 6682 /* if receive failed revoke VF CTS stats and restart init */ 6683 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6684 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6685 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6686 return; 6687 goto out; 6688 } 6689 6690 /* this is a message we already processed, do nothing */ 6691 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6692 return; 6693 6694 /* until the vf completes a reset it should not be 6695 * allowed to start any configuration. 6696 */ 6697 if (msgbuf[0] == E1000_VF_RESET) { 6698 igb_vf_reset_msg(adapter, vf); 6699 return; 6700 } 6701 6702 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6703 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6704 return; 6705 retval = -1; 6706 goto out; 6707 } 6708 6709 switch ((msgbuf[0] & 0xFFFF)) { 6710 case E1000_VF_SET_MAC_ADDR: 6711 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6712 break; 6713 case E1000_VF_SET_PROMISC: 6714 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6715 break; 6716 case E1000_VF_SET_MULTICAST: 6717 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6718 break; 6719 case E1000_VF_SET_LPE: 6720 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6721 break; 6722 case E1000_VF_SET_VLAN: 6723 retval = -1; 6724 if (vf_data->pf_vlan) 6725 dev_warn(&pdev->dev, 6726 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6727 vf); 6728 else 6729 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6730 break; 6731 default: 6732 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6733 retval = -1; 6734 break; 6735 } 6736 6737 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6738 out: 6739 /* notify the VF of the results of what it sent us */ 6740 if (retval) 6741 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6742 else 6743 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6744 6745 igb_write_mbx(hw, msgbuf, 1, vf); 6746 } 6747 6748 static void igb_msg_task(struct igb_adapter *adapter) 6749 { 6750 struct e1000_hw *hw = &adapter->hw; 6751 u32 vf; 6752 6753 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6754 /* process any reset requests */ 6755 if (!igb_check_for_rst(hw, vf)) 6756 igb_vf_reset_event(adapter, vf); 6757 6758 /* process any messages pending */ 6759 if (!igb_check_for_msg(hw, vf)) 6760 igb_rcv_msg_from_vf(adapter, vf); 6761 6762 /* process any acks */ 6763 if (!igb_check_for_ack(hw, vf)) 6764 igb_rcv_ack_from_vf(adapter, vf); 6765 } 6766 } 6767 6768 /** 6769 * igb_set_uta - Set unicast filter table address 6770 * @adapter: board private structure 6771 * @set: boolean indicating if we are setting or clearing bits 6772 * 6773 * The unicast table address is a register array of 32-bit registers. 6774 * The table is meant to be used in a way similar to how the MTA is used 6775 * however due to certain limitations in the hardware it is necessary to 6776 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6777 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6778 **/ 6779 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6780 { 6781 struct e1000_hw *hw = &adapter->hw; 6782 u32 uta = set ? ~0 : 0; 6783 int i; 6784 6785 /* we only need to do this if VMDq is enabled */ 6786 if (!adapter->vfs_allocated_count) 6787 return; 6788 6789 for (i = hw->mac.uta_reg_count; i--;) 6790 array_wr32(E1000_UTA, i, uta); 6791 } 6792 6793 /** 6794 * igb_intr_msi - Interrupt Handler 6795 * @irq: interrupt number 6796 * @data: pointer to a network interface device structure 6797 **/ 6798 static irqreturn_t igb_intr_msi(int irq, void *data) 6799 { 6800 struct igb_adapter *adapter = data; 6801 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6802 struct e1000_hw *hw = &adapter->hw; 6803 /* read ICR disables interrupts using IAM */ 6804 u32 icr = rd32(E1000_ICR); 6805 6806 igb_write_itr(q_vector); 6807 6808 if (icr & E1000_ICR_DRSTA) 6809 schedule_work(&adapter->reset_task); 6810 6811 if (icr & E1000_ICR_DOUTSYNC) { 6812 /* HW is reporting DMA is out of sync */ 6813 adapter->stats.doosync++; 6814 } 6815 6816 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6817 hw->mac.get_link_status = 1; 6818 if (!test_bit(__IGB_DOWN, &adapter->state)) 6819 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6820 } 6821 6822 if (icr & E1000_ICR_TS) 6823 igb_tsync_interrupt(adapter); 6824 6825 napi_schedule(&q_vector->napi); 6826 6827 return IRQ_HANDLED; 6828 } 6829 6830 /** 6831 * igb_intr - Legacy Interrupt Handler 6832 * @irq: interrupt number 6833 * @data: pointer to a network interface device structure 6834 **/ 6835 static irqreturn_t igb_intr(int irq, void *data) 6836 { 6837 struct igb_adapter *adapter = data; 6838 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6839 struct e1000_hw *hw = &adapter->hw; 6840 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6841 * need for the IMC write 6842 */ 6843 u32 icr = rd32(E1000_ICR); 6844 6845 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6846 * not set, then the adapter didn't send an interrupt 6847 */ 6848 if (!(icr & E1000_ICR_INT_ASSERTED)) 6849 return IRQ_NONE; 6850 6851 igb_write_itr(q_vector); 6852 6853 if (icr & E1000_ICR_DRSTA) 6854 schedule_work(&adapter->reset_task); 6855 6856 if (icr & E1000_ICR_DOUTSYNC) { 6857 /* HW is reporting DMA is out of sync */ 6858 adapter->stats.doosync++; 6859 } 6860 6861 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6862 hw->mac.get_link_status = 1; 6863 /* guard against interrupt when we're going down */ 6864 if (!test_bit(__IGB_DOWN, &adapter->state)) 6865 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6866 } 6867 6868 if (icr & E1000_ICR_TS) 6869 igb_tsync_interrupt(adapter); 6870 6871 napi_schedule(&q_vector->napi); 6872 6873 return IRQ_HANDLED; 6874 } 6875 6876 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6877 { 6878 struct igb_adapter *adapter = q_vector->adapter; 6879 struct e1000_hw *hw = &adapter->hw; 6880 6881 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6882 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6883 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6884 igb_set_itr(q_vector); 6885 else 6886 igb_update_ring_itr(q_vector); 6887 } 6888 6889 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6890 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6891 wr32(E1000_EIMS, q_vector->eims_value); 6892 else 6893 igb_irq_enable(adapter); 6894 } 6895 } 6896 6897 /** 6898 * igb_poll - NAPI Rx polling callback 6899 * @napi: napi polling structure 6900 * @budget: count of how many packets we should handle 6901 **/ 6902 static int igb_poll(struct napi_struct *napi, int budget) 6903 { 6904 struct igb_q_vector *q_vector = container_of(napi, 6905 struct igb_q_vector, 6906 napi); 6907 bool clean_complete = true; 6908 int work_done = 0; 6909 6910 #ifdef CONFIG_IGB_DCA 6911 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6912 igb_update_dca(q_vector); 6913 #endif 6914 if (q_vector->tx.ring) 6915 clean_complete = igb_clean_tx_irq(q_vector, budget); 6916 6917 if (q_vector->rx.ring) { 6918 int cleaned = igb_clean_rx_irq(q_vector, budget); 6919 6920 work_done += cleaned; 6921 if (cleaned >= budget) 6922 clean_complete = false; 6923 } 6924 6925 /* If all work not completed, return budget and keep polling */ 6926 if (!clean_complete) 6927 return budget; 6928 6929 /* If not enough Rx work done, exit the polling mode */ 6930 napi_complete_done(napi, work_done); 6931 igb_ring_irq_enable(q_vector); 6932 6933 return 0; 6934 } 6935 6936 /** 6937 * igb_clean_tx_irq - Reclaim resources after transmit completes 6938 * @q_vector: pointer to q_vector containing needed info 6939 * @napi_budget: Used to determine if we are in netpoll 6940 * 6941 * returns true if ring is completely cleaned 6942 **/ 6943 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6944 { 6945 struct igb_adapter *adapter = q_vector->adapter; 6946 struct igb_ring *tx_ring = q_vector->tx.ring; 6947 struct igb_tx_buffer *tx_buffer; 6948 union e1000_adv_tx_desc *tx_desc; 6949 unsigned int total_bytes = 0, total_packets = 0; 6950 unsigned int budget = q_vector->tx.work_limit; 6951 unsigned int i = tx_ring->next_to_clean; 6952 6953 if (test_bit(__IGB_DOWN, &adapter->state)) 6954 return true; 6955 6956 tx_buffer = &tx_ring->tx_buffer_info[i]; 6957 tx_desc = IGB_TX_DESC(tx_ring, i); 6958 i -= tx_ring->count; 6959 6960 do { 6961 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6962 6963 /* if next_to_watch is not set then there is no work pending */ 6964 if (!eop_desc) 6965 break; 6966 6967 /* prevent any other reads prior to eop_desc */ 6968 read_barrier_depends(); 6969 6970 /* if DD is not set pending work has not been completed */ 6971 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6972 break; 6973 6974 /* clear next_to_watch to prevent false hangs */ 6975 tx_buffer->next_to_watch = NULL; 6976 6977 /* update the statistics for this packet */ 6978 total_bytes += tx_buffer->bytecount; 6979 total_packets += tx_buffer->gso_segs; 6980 6981 /* free the skb */ 6982 napi_consume_skb(tx_buffer->skb, napi_budget); 6983 6984 /* unmap skb header data */ 6985 dma_unmap_single(tx_ring->dev, 6986 dma_unmap_addr(tx_buffer, dma), 6987 dma_unmap_len(tx_buffer, len), 6988 DMA_TO_DEVICE); 6989 6990 /* clear tx_buffer data */ 6991 dma_unmap_len_set(tx_buffer, len, 0); 6992 6993 /* clear last DMA location and unmap remaining buffers */ 6994 while (tx_desc != eop_desc) { 6995 tx_buffer++; 6996 tx_desc++; 6997 i++; 6998 if (unlikely(!i)) { 6999 i -= tx_ring->count; 7000 tx_buffer = tx_ring->tx_buffer_info; 7001 tx_desc = IGB_TX_DESC(tx_ring, 0); 7002 } 7003 7004 /* unmap any remaining paged data */ 7005 if (dma_unmap_len(tx_buffer, len)) { 7006 dma_unmap_page(tx_ring->dev, 7007 dma_unmap_addr(tx_buffer, dma), 7008 dma_unmap_len(tx_buffer, len), 7009 DMA_TO_DEVICE); 7010 dma_unmap_len_set(tx_buffer, len, 0); 7011 } 7012 } 7013 7014 /* move us one more past the eop_desc for start of next pkt */ 7015 tx_buffer++; 7016 tx_desc++; 7017 i++; 7018 if (unlikely(!i)) { 7019 i -= tx_ring->count; 7020 tx_buffer = tx_ring->tx_buffer_info; 7021 tx_desc = IGB_TX_DESC(tx_ring, 0); 7022 } 7023 7024 /* issue prefetch for next Tx descriptor */ 7025 prefetch(tx_desc); 7026 7027 /* update budget accounting */ 7028 budget--; 7029 } while (likely(budget)); 7030 7031 netdev_tx_completed_queue(txring_txq(tx_ring), 7032 total_packets, total_bytes); 7033 i += tx_ring->count; 7034 tx_ring->next_to_clean = i; 7035 u64_stats_update_begin(&tx_ring->tx_syncp); 7036 tx_ring->tx_stats.bytes += total_bytes; 7037 tx_ring->tx_stats.packets += total_packets; 7038 u64_stats_update_end(&tx_ring->tx_syncp); 7039 q_vector->tx.total_bytes += total_bytes; 7040 q_vector->tx.total_packets += total_packets; 7041 7042 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7043 struct e1000_hw *hw = &adapter->hw; 7044 7045 /* Detect a transmit hang in hardware, this serializes the 7046 * check with the clearing of time_stamp and movement of i 7047 */ 7048 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7049 if (tx_buffer->next_to_watch && 7050 time_after(jiffies, tx_buffer->time_stamp + 7051 (adapter->tx_timeout_factor * HZ)) && 7052 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7053 7054 /* detected Tx unit hang */ 7055 dev_err(tx_ring->dev, 7056 "Detected Tx Unit Hang\n" 7057 " Tx Queue <%d>\n" 7058 " TDH <%x>\n" 7059 " TDT <%x>\n" 7060 " next_to_use <%x>\n" 7061 " next_to_clean <%x>\n" 7062 "buffer_info[next_to_clean]\n" 7063 " time_stamp <%lx>\n" 7064 " next_to_watch <%p>\n" 7065 " jiffies <%lx>\n" 7066 " desc.status <%x>\n", 7067 tx_ring->queue_index, 7068 rd32(E1000_TDH(tx_ring->reg_idx)), 7069 readl(tx_ring->tail), 7070 tx_ring->next_to_use, 7071 tx_ring->next_to_clean, 7072 tx_buffer->time_stamp, 7073 tx_buffer->next_to_watch, 7074 jiffies, 7075 tx_buffer->next_to_watch->wb.status); 7076 netif_stop_subqueue(tx_ring->netdev, 7077 tx_ring->queue_index); 7078 7079 /* we are about to reset, no point in enabling stuff */ 7080 return true; 7081 } 7082 } 7083 7084 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7085 if (unlikely(total_packets && 7086 netif_carrier_ok(tx_ring->netdev) && 7087 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7088 /* Make sure that anybody stopping the queue after this 7089 * sees the new next_to_clean. 7090 */ 7091 smp_mb(); 7092 if (__netif_subqueue_stopped(tx_ring->netdev, 7093 tx_ring->queue_index) && 7094 !(test_bit(__IGB_DOWN, &adapter->state))) { 7095 netif_wake_subqueue(tx_ring->netdev, 7096 tx_ring->queue_index); 7097 7098 u64_stats_update_begin(&tx_ring->tx_syncp); 7099 tx_ring->tx_stats.restart_queue++; 7100 u64_stats_update_end(&tx_ring->tx_syncp); 7101 } 7102 } 7103 7104 return !!budget; 7105 } 7106 7107 /** 7108 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7109 * @rx_ring: rx descriptor ring to store buffers on 7110 * @old_buff: donor buffer to have page reused 7111 * 7112 * Synchronizes page for reuse by the adapter 7113 **/ 7114 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7115 struct igb_rx_buffer *old_buff) 7116 { 7117 struct igb_rx_buffer *new_buff; 7118 u16 nta = rx_ring->next_to_alloc; 7119 7120 new_buff = &rx_ring->rx_buffer_info[nta]; 7121 7122 /* update, and store next to alloc */ 7123 nta++; 7124 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7125 7126 /* Transfer page from old buffer to new buffer. 7127 * Move each member individually to avoid possible store 7128 * forwarding stalls. 7129 */ 7130 new_buff->dma = old_buff->dma; 7131 new_buff->page = old_buff->page; 7132 new_buff->page_offset = old_buff->page_offset; 7133 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7134 } 7135 7136 static inline bool igb_page_is_reserved(struct page *page) 7137 { 7138 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7139 } 7140 7141 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7142 { 7143 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7144 struct page *page = rx_buffer->page; 7145 7146 /* avoid re-using remote pages */ 7147 if (unlikely(igb_page_is_reserved(page))) 7148 return false; 7149 7150 #if (PAGE_SIZE < 8192) 7151 /* if we are only owner of page we can reuse it */ 7152 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7153 return false; 7154 #else 7155 #define IGB_LAST_OFFSET \ 7156 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7157 7158 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7159 return false; 7160 #endif 7161 7162 /* If we have drained the page fragment pool we need to update 7163 * the pagecnt_bias and page count so that we fully restock the 7164 * number of references the driver holds. 7165 */ 7166 if (unlikely(!pagecnt_bias)) { 7167 page_ref_add(page, USHRT_MAX); 7168 rx_buffer->pagecnt_bias = USHRT_MAX; 7169 } 7170 7171 return true; 7172 } 7173 7174 /** 7175 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7176 * @rx_ring: rx descriptor ring to transact packets on 7177 * @rx_buffer: buffer containing page to add 7178 * @skb: sk_buff to place the data into 7179 * @size: size of buffer to be added 7180 * 7181 * This function will add the data contained in rx_buffer->page to the skb. 7182 **/ 7183 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7184 struct igb_rx_buffer *rx_buffer, 7185 struct sk_buff *skb, 7186 unsigned int size) 7187 { 7188 #if (PAGE_SIZE < 8192) 7189 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7190 #else 7191 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7192 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7193 SKB_DATA_ALIGN(size); 7194 #endif 7195 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7196 rx_buffer->page_offset, size, truesize); 7197 #if (PAGE_SIZE < 8192) 7198 rx_buffer->page_offset ^= truesize; 7199 #else 7200 rx_buffer->page_offset += truesize; 7201 #endif 7202 } 7203 7204 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 7205 struct igb_rx_buffer *rx_buffer, 7206 union e1000_adv_rx_desc *rx_desc, 7207 unsigned int size) 7208 { 7209 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7210 #if (PAGE_SIZE < 8192) 7211 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7212 #else 7213 unsigned int truesize = SKB_DATA_ALIGN(size); 7214 #endif 7215 unsigned int headlen; 7216 struct sk_buff *skb; 7217 7218 /* prefetch first cache line of first page */ 7219 prefetch(va); 7220 #if L1_CACHE_BYTES < 128 7221 prefetch(va + L1_CACHE_BYTES); 7222 #endif 7223 7224 /* allocate a skb to store the frags */ 7225 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 7226 if (unlikely(!skb)) 7227 return NULL; 7228 7229 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 7230 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 7231 va += IGB_TS_HDR_LEN; 7232 size -= IGB_TS_HDR_LEN; 7233 } 7234 7235 /* Determine available headroom for copy */ 7236 headlen = size; 7237 if (headlen > IGB_RX_HDR_LEN) 7238 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7239 7240 /* align pull length to size of long to optimize memcpy performance */ 7241 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7242 7243 /* update all of the pointers */ 7244 size -= headlen; 7245 if (size) { 7246 skb_add_rx_frag(skb, 0, rx_buffer->page, 7247 (va + headlen) - page_address(rx_buffer->page), 7248 size, truesize); 7249 #if (PAGE_SIZE < 8192) 7250 rx_buffer->page_offset ^= truesize; 7251 #else 7252 rx_buffer->page_offset += truesize; 7253 #endif 7254 } else { 7255 rx_buffer->pagecnt_bias++; 7256 } 7257 7258 return skb; 7259 } 7260 7261 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7262 struct igb_rx_buffer *rx_buffer, 7263 union e1000_adv_rx_desc *rx_desc, 7264 unsigned int size) 7265 { 7266 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7267 #if (PAGE_SIZE < 8192) 7268 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7269 #else 7270 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7271 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7272 #endif 7273 struct sk_buff *skb; 7274 7275 /* prefetch first cache line of first page */ 7276 prefetch(va); 7277 #if L1_CACHE_BYTES < 128 7278 prefetch(va + L1_CACHE_BYTES); 7279 #endif 7280 7281 /* build an skb around the page buffer */ 7282 skb = build_skb(va - IGB_SKB_PAD, truesize); 7283 if (unlikely(!skb)) 7284 return NULL; 7285 7286 /* update pointers within the skb to store the data */ 7287 skb_reserve(skb, IGB_SKB_PAD); 7288 __skb_put(skb, size); 7289 7290 /* pull timestamp out of packet data */ 7291 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7292 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7293 __skb_pull(skb, IGB_TS_HDR_LEN); 7294 } 7295 7296 /* update buffer offset */ 7297 #if (PAGE_SIZE < 8192) 7298 rx_buffer->page_offset ^= truesize; 7299 #else 7300 rx_buffer->page_offset += truesize; 7301 #endif 7302 7303 return skb; 7304 } 7305 7306 static inline void igb_rx_checksum(struct igb_ring *ring, 7307 union e1000_adv_rx_desc *rx_desc, 7308 struct sk_buff *skb) 7309 { 7310 skb_checksum_none_assert(skb); 7311 7312 /* Ignore Checksum bit is set */ 7313 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 7314 return; 7315 7316 /* Rx checksum disabled via ethtool */ 7317 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 7318 return; 7319 7320 /* TCP/UDP checksum error bit is set */ 7321 if (igb_test_staterr(rx_desc, 7322 E1000_RXDEXT_STATERR_TCPE | 7323 E1000_RXDEXT_STATERR_IPE)) { 7324 /* work around errata with sctp packets where the TCPE aka 7325 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7326 * packets, (aka let the stack check the crc32c) 7327 */ 7328 if (!((skb->len == 60) && 7329 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7330 u64_stats_update_begin(&ring->rx_syncp); 7331 ring->rx_stats.csum_err++; 7332 u64_stats_update_end(&ring->rx_syncp); 7333 } 7334 /* let the stack verify checksum errors */ 7335 return; 7336 } 7337 /* It must be a TCP or UDP packet with a valid checksum */ 7338 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7339 E1000_RXD_STAT_UDPCS)) 7340 skb->ip_summed = CHECKSUM_UNNECESSARY; 7341 7342 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7343 le32_to_cpu(rx_desc->wb.upper.status_error)); 7344 } 7345 7346 static inline void igb_rx_hash(struct igb_ring *ring, 7347 union e1000_adv_rx_desc *rx_desc, 7348 struct sk_buff *skb) 7349 { 7350 if (ring->netdev->features & NETIF_F_RXHASH) 7351 skb_set_hash(skb, 7352 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7353 PKT_HASH_TYPE_L3); 7354 } 7355 7356 /** 7357 * igb_is_non_eop - process handling of non-EOP buffers 7358 * @rx_ring: Rx ring being processed 7359 * @rx_desc: Rx descriptor for current buffer 7360 * @skb: current socket buffer containing buffer in progress 7361 * 7362 * This function updates next to clean. If the buffer is an EOP buffer 7363 * this function exits returning false, otherwise it will place the 7364 * sk_buff in the next buffer to be chained and return true indicating 7365 * that this is in fact a non-EOP buffer. 7366 **/ 7367 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7368 union e1000_adv_rx_desc *rx_desc) 7369 { 7370 u32 ntc = rx_ring->next_to_clean + 1; 7371 7372 /* fetch, update, and store next to clean */ 7373 ntc = (ntc < rx_ring->count) ? ntc : 0; 7374 rx_ring->next_to_clean = ntc; 7375 7376 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7377 7378 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7379 return false; 7380 7381 return true; 7382 } 7383 7384 /** 7385 * igb_cleanup_headers - Correct corrupted or empty headers 7386 * @rx_ring: rx descriptor ring packet is being transacted on 7387 * @rx_desc: pointer to the EOP Rx descriptor 7388 * @skb: pointer to current skb being fixed 7389 * 7390 * Address the case where we are pulling data in on pages only 7391 * and as such no data is present in the skb header. 7392 * 7393 * In addition if skb is not at least 60 bytes we need to pad it so that 7394 * it is large enough to qualify as a valid Ethernet frame. 7395 * 7396 * Returns true if an error was encountered and skb was freed. 7397 **/ 7398 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7399 union e1000_adv_rx_desc *rx_desc, 7400 struct sk_buff *skb) 7401 { 7402 if (unlikely((igb_test_staterr(rx_desc, 7403 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7404 struct net_device *netdev = rx_ring->netdev; 7405 if (!(netdev->features & NETIF_F_RXALL)) { 7406 dev_kfree_skb_any(skb); 7407 return true; 7408 } 7409 } 7410 7411 /* if eth_skb_pad returns an error the skb was freed */ 7412 if (eth_skb_pad(skb)) 7413 return true; 7414 7415 return false; 7416 } 7417 7418 /** 7419 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7420 * @rx_ring: rx descriptor ring packet is being transacted on 7421 * @rx_desc: pointer to the EOP Rx descriptor 7422 * @skb: pointer to current skb being populated 7423 * 7424 * This function checks the ring, descriptor, and packet information in 7425 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7426 * other fields within the skb. 7427 **/ 7428 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7429 union e1000_adv_rx_desc *rx_desc, 7430 struct sk_buff *skb) 7431 { 7432 struct net_device *dev = rx_ring->netdev; 7433 7434 igb_rx_hash(rx_ring, rx_desc, skb); 7435 7436 igb_rx_checksum(rx_ring, rx_desc, skb); 7437 7438 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7439 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7440 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7441 7442 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7443 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7444 u16 vid; 7445 7446 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7447 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7448 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7449 else 7450 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7451 7452 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7453 } 7454 7455 skb_record_rx_queue(skb, rx_ring->queue_index); 7456 7457 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7458 } 7459 7460 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 7461 const unsigned int size) 7462 { 7463 struct igb_rx_buffer *rx_buffer; 7464 7465 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 7466 prefetchw(rx_buffer->page); 7467 7468 /* we are reusing so sync this buffer for CPU use */ 7469 dma_sync_single_range_for_cpu(rx_ring->dev, 7470 rx_buffer->dma, 7471 rx_buffer->page_offset, 7472 size, 7473 DMA_FROM_DEVICE); 7474 7475 rx_buffer->pagecnt_bias--; 7476 7477 return rx_buffer; 7478 } 7479 7480 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 7481 struct igb_rx_buffer *rx_buffer) 7482 { 7483 if (igb_can_reuse_rx_page(rx_buffer)) { 7484 /* hand second half of page back to the ring */ 7485 igb_reuse_rx_page(rx_ring, rx_buffer); 7486 } else { 7487 /* We are not reusing the buffer so unmap it and free 7488 * any references we are holding to it 7489 */ 7490 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 7491 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 7492 IGB_RX_DMA_ATTR); 7493 __page_frag_cache_drain(rx_buffer->page, 7494 rx_buffer->pagecnt_bias); 7495 } 7496 7497 /* clear contents of rx_buffer */ 7498 rx_buffer->page = NULL; 7499 } 7500 7501 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7502 { 7503 struct igb_ring *rx_ring = q_vector->rx.ring; 7504 struct sk_buff *skb = rx_ring->skb; 7505 unsigned int total_bytes = 0, total_packets = 0; 7506 u16 cleaned_count = igb_desc_unused(rx_ring); 7507 7508 while (likely(total_packets < budget)) { 7509 union e1000_adv_rx_desc *rx_desc; 7510 struct igb_rx_buffer *rx_buffer; 7511 unsigned int size; 7512 7513 /* return some buffers to hardware, one at a time is too slow */ 7514 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7515 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7516 cleaned_count = 0; 7517 } 7518 7519 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7520 size = le16_to_cpu(rx_desc->wb.upper.length); 7521 if (!size) 7522 break; 7523 7524 /* This memory barrier is needed to keep us from reading 7525 * any other fields out of the rx_desc until we know the 7526 * descriptor has been written back 7527 */ 7528 dma_rmb(); 7529 7530 rx_buffer = igb_get_rx_buffer(rx_ring, size); 7531 7532 /* retrieve a buffer from the ring */ 7533 if (skb) 7534 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 7535 else if (ring_uses_build_skb(rx_ring)) 7536 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 7537 else 7538 skb = igb_construct_skb(rx_ring, rx_buffer, 7539 rx_desc, size); 7540 7541 /* exit if we failed to retrieve a buffer */ 7542 if (!skb) { 7543 rx_ring->rx_stats.alloc_failed++; 7544 rx_buffer->pagecnt_bias++; 7545 break; 7546 } 7547 7548 igb_put_rx_buffer(rx_ring, rx_buffer); 7549 cleaned_count++; 7550 7551 /* fetch next buffer in frame if non-eop */ 7552 if (igb_is_non_eop(rx_ring, rx_desc)) 7553 continue; 7554 7555 /* verify the packet layout is correct */ 7556 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7557 skb = NULL; 7558 continue; 7559 } 7560 7561 /* probably a little skewed due to removing CRC */ 7562 total_bytes += skb->len; 7563 7564 /* populate checksum, timestamp, VLAN, and protocol */ 7565 igb_process_skb_fields(rx_ring, rx_desc, skb); 7566 7567 napi_gro_receive(&q_vector->napi, skb); 7568 7569 /* reset skb pointer */ 7570 skb = NULL; 7571 7572 /* update budget accounting */ 7573 total_packets++; 7574 } 7575 7576 /* place incomplete frames back on ring for completion */ 7577 rx_ring->skb = skb; 7578 7579 u64_stats_update_begin(&rx_ring->rx_syncp); 7580 rx_ring->rx_stats.packets += total_packets; 7581 rx_ring->rx_stats.bytes += total_bytes; 7582 u64_stats_update_end(&rx_ring->rx_syncp); 7583 q_vector->rx.total_packets += total_packets; 7584 q_vector->rx.total_bytes += total_bytes; 7585 7586 if (cleaned_count) 7587 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7588 7589 return total_packets; 7590 } 7591 7592 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 7593 { 7594 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 7595 } 7596 7597 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7598 struct igb_rx_buffer *bi) 7599 { 7600 struct page *page = bi->page; 7601 dma_addr_t dma; 7602 7603 /* since we are recycling buffers we should seldom need to alloc */ 7604 if (likely(page)) 7605 return true; 7606 7607 /* alloc new page for storage */ 7608 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 7609 if (unlikely(!page)) { 7610 rx_ring->rx_stats.alloc_failed++; 7611 return false; 7612 } 7613 7614 /* map page for use */ 7615 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 7616 igb_rx_pg_size(rx_ring), 7617 DMA_FROM_DEVICE, 7618 IGB_RX_DMA_ATTR); 7619 7620 /* if mapping failed free memory back to system since 7621 * there isn't much point in holding memory we can't use 7622 */ 7623 if (dma_mapping_error(rx_ring->dev, dma)) { 7624 __free_pages(page, igb_rx_pg_order(rx_ring)); 7625 7626 rx_ring->rx_stats.alloc_failed++; 7627 return false; 7628 } 7629 7630 bi->dma = dma; 7631 bi->page = page; 7632 bi->page_offset = igb_rx_offset(rx_ring); 7633 bi->pagecnt_bias = 1; 7634 7635 return true; 7636 } 7637 7638 /** 7639 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7640 * @adapter: address of board private structure 7641 **/ 7642 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7643 { 7644 union e1000_adv_rx_desc *rx_desc; 7645 struct igb_rx_buffer *bi; 7646 u16 i = rx_ring->next_to_use; 7647 u16 bufsz; 7648 7649 /* nothing to do */ 7650 if (!cleaned_count) 7651 return; 7652 7653 rx_desc = IGB_RX_DESC(rx_ring, i); 7654 bi = &rx_ring->rx_buffer_info[i]; 7655 i -= rx_ring->count; 7656 7657 bufsz = igb_rx_bufsz(rx_ring); 7658 7659 do { 7660 if (!igb_alloc_mapped_page(rx_ring, bi)) 7661 break; 7662 7663 /* sync the buffer for use by the device */ 7664 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 7665 bi->page_offset, bufsz, 7666 DMA_FROM_DEVICE); 7667 7668 /* Refresh the desc even if buffer_addrs didn't change 7669 * because each write-back erases this info. 7670 */ 7671 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7672 7673 rx_desc++; 7674 bi++; 7675 i++; 7676 if (unlikely(!i)) { 7677 rx_desc = IGB_RX_DESC(rx_ring, 0); 7678 bi = rx_ring->rx_buffer_info; 7679 i -= rx_ring->count; 7680 } 7681 7682 /* clear the length for the next_to_use descriptor */ 7683 rx_desc->wb.upper.length = 0; 7684 7685 cleaned_count--; 7686 } while (cleaned_count); 7687 7688 i += rx_ring->count; 7689 7690 if (rx_ring->next_to_use != i) { 7691 /* record the next descriptor to use */ 7692 rx_ring->next_to_use = i; 7693 7694 /* update next to alloc since we have filled the ring */ 7695 rx_ring->next_to_alloc = i; 7696 7697 /* Force memory writes to complete before letting h/w 7698 * know there are new descriptors to fetch. (Only 7699 * applicable for weak-ordered memory model archs, 7700 * such as IA-64). 7701 */ 7702 wmb(); 7703 writel(i, rx_ring->tail); 7704 } 7705 } 7706 7707 /** 7708 * igb_mii_ioctl - 7709 * @netdev: 7710 * @ifreq: 7711 * @cmd: 7712 **/ 7713 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7714 { 7715 struct igb_adapter *adapter = netdev_priv(netdev); 7716 struct mii_ioctl_data *data = if_mii(ifr); 7717 7718 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7719 return -EOPNOTSUPP; 7720 7721 switch (cmd) { 7722 case SIOCGMIIPHY: 7723 data->phy_id = adapter->hw.phy.addr; 7724 break; 7725 case SIOCGMIIREG: 7726 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7727 &data->val_out)) 7728 return -EIO; 7729 break; 7730 case SIOCSMIIREG: 7731 default: 7732 return -EOPNOTSUPP; 7733 } 7734 return 0; 7735 } 7736 7737 /** 7738 * igb_ioctl - 7739 * @netdev: 7740 * @ifreq: 7741 * @cmd: 7742 **/ 7743 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7744 { 7745 switch (cmd) { 7746 case SIOCGMIIPHY: 7747 case SIOCGMIIREG: 7748 case SIOCSMIIREG: 7749 return igb_mii_ioctl(netdev, ifr, cmd); 7750 case SIOCGHWTSTAMP: 7751 return igb_ptp_get_ts_config(netdev, ifr); 7752 case SIOCSHWTSTAMP: 7753 return igb_ptp_set_ts_config(netdev, ifr); 7754 default: 7755 return -EOPNOTSUPP; 7756 } 7757 } 7758 7759 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7760 { 7761 struct igb_adapter *adapter = hw->back; 7762 7763 pci_read_config_word(adapter->pdev, reg, value); 7764 } 7765 7766 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7767 { 7768 struct igb_adapter *adapter = hw->back; 7769 7770 pci_write_config_word(adapter->pdev, reg, *value); 7771 } 7772 7773 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7774 { 7775 struct igb_adapter *adapter = hw->back; 7776 7777 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7778 return -E1000_ERR_CONFIG; 7779 7780 return 0; 7781 } 7782 7783 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7784 { 7785 struct igb_adapter *adapter = hw->back; 7786 7787 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7788 return -E1000_ERR_CONFIG; 7789 7790 return 0; 7791 } 7792 7793 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7794 { 7795 struct igb_adapter *adapter = netdev_priv(netdev); 7796 struct e1000_hw *hw = &adapter->hw; 7797 u32 ctrl, rctl; 7798 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7799 7800 if (enable) { 7801 /* enable VLAN tag insert/strip */ 7802 ctrl = rd32(E1000_CTRL); 7803 ctrl |= E1000_CTRL_VME; 7804 wr32(E1000_CTRL, ctrl); 7805 7806 /* Disable CFI check */ 7807 rctl = rd32(E1000_RCTL); 7808 rctl &= ~E1000_RCTL_CFIEN; 7809 wr32(E1000_RCTL, rctl); 7810 } else { 7811 /* disable VLAN tag insert/strip */ 7812 ctrl = rd32(E1000_CTRL); 7813 ctrl &= ~E1000_CTRL_VME; 7814 wr32(E1000_CTRL, ctrl); 7815 } 7816 7817 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7818 } 7819 7820 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7821 __be16 proto, u16 vid) 7822 { 7823 struct igb_adapter *adapter = netdev_priv(netdev); 7824 struct e1000_hw *hw = &adapter->hw; 7825 int pf_id = adapter->vfs_allocated_count; 7826 7827 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7828 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7829 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7830 7831 set_bit(vid, adapter->active_vlans); 7832 7833 return 0; 7834 } 7835 7836 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7837 __be16 proto, u16 vid) 7838 { 7839 struct igb_adapter *adapter = netdev_priv(netdev); 7840 int pf_id = adapter->vfs_allocated_count; 7841 struct e1000_hw *hw = &adapter->hw; 7842 7843 /* remove VID from filter table */ 7844 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7845 igb_vfta_set(hw, vid, pf_id, false, true); 7846 7847 clear_bit(vid, adapter->active_vlans); 7848 7849 return 0; 7850 } 7851 7852 static void igb_restore_vlan(struct igb_adapter *adapter) 7853 { 7854 u16 vid = 1; 7855 7856 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7857 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7858 7859 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7860 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7861 } 7862 7863 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7864 { 7865 struct pci_dev *pdev = adapter->pdev; 7866 struct e1000_mac_info *mac = &adapter->hw.mac; 7867 7868 mac->autoneg = 0; 7869 7870 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7871 * for the switch() below to work 7872 */ 7873 if ((spd & 1) || (dplx & ~1)) 7874 goto err_inval; 7875 7876 /* Fiber NIC's only allow 1000 gbps Full duplex 7877 * and 100Mbps Full duplex for 100baseFx sfp 7878 */ 7879 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7880 switch (spd + dplx) { 7881 case SPEED_10 + DUPLEX_HALF: 7882 case SPEED_10 + DUPLEX_FULL: 7883 case SPEED_100 + DUPLEX_HALF: 7884 goto err_inval; 7885 default: 7886 break; 7887 } 7888 } 7889 7890 switch (spd + dplx) { 7891 case SPEED_10 + DUPLEX_HALF: 7892 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7893 break; 7894 case SPEED_10 + DUPLEX_FULL: 7895 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7896 break; 7897 case SPEED_100 + DUPLEX_HALF: 7898 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7899 break; 7900 case SPEED_100 + DUPLEX_FULL: 7901 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7902 break; 7903 case SPEED_1000 + DUPLEX_FULL: 7904 mac->autoneg = 1; 7905 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7906 break; 7907 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7908 default: 7909 goto err_inval; 7910 } 7911 7912 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7913 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7914 7915 return 0; 7916 7917 err_inval: 7918 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7919 return -EINVAL; 7920 } 7921 7922 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7923 bool runtime) 7924 { 7925 struct net_device *netdev = pci_get_drvdata(pdev); 7926 struct igb_adapter *adapter = netdev_priv(netdev); 7927 struct e1000_hw *hw = &adapter->hw; 7928 u32 ctrl, rctl, status; 7929 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7930 #ifdef CONFIG_PM 7931 int retval = 0; 7932 #endif 7933 7934 rtnl_lock(); 7935 netif_device_detach(netdev); 7936 7937 if (netif_running(netdev)) 7938 __igb_close(netdev, true); 7939 7940 igb_ptp_suspend(adapter); 7941 7942 igb_clear_interrupt_scheme(adapter); 7943 rtnl_unlock(); 7944 7945 #ifdef CONFIG_PM 7946 retval = pci_save_state(pdev); 7947 if (retval) 7948 return retval; 7949 #endif 7950 7951 status = rd32(E1000_STATUS); 7952 if (status & E1000_STATUS_LU) 7953 wufc &= ~E1000_WUFC_LNKC; 7954 7955 if (wufc) { 7956 igb_setup_rctl(adapter); 7957 igb_set_rx_mode(netdev); 7958 7959 /* turn on all-multi mode if wake on multicast is enabled */ 7960 if (wufc & E1000_WUFC_MC) { 7961 rctl = rd32(E1000_RCTL); 7962 rctl |= E1000_RCTL_MPE; 7963 wr32(E1000_RCTL, rctl); 7964 } 7965 7966 ctrl = rd32(E1000_CTRL); 7967 /* advertise wake from D3Cold */ 7968 #define E1000_CTRL_ADVD3WUC 0x00100000 7969 /* phy power management enable */ 7970 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7971 ctrl |= E1000_CTRL_ADVD3WUC; 7972 wr32(E1000_CTRL, ctrl); 7973 7974 /* Allow time for pending master requests to run */ 7975 igb_disable_pcie_master(hw); 7976 7977 wr32(E1000_WUC, E1000_WUC_PME_EN); 7978 wr32(E1000_WUFC, wufc); 7979 } else { 7980 wr32(E1000_WUC, 0); 7981 wr32(E1000_WUFC, 0); 7982 } 7983 7984 *enable_wake = wufc || adapter->en_mng_pt; 7985 if (!*enable_wake) 7986 igb_power_down_link(adapter); 7987 else 7988 igb_power_up_link(adapter); 7989 7990 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7991 * would have already happened in close and is redundant. 7992 */ 7993 igb_release_hw_control(adapter); 7994 7995 pci_disable_device(pdev); 7996 7997 return 0; 7998 } 7999 8000 static void igb_deliver_wake_packet(struct net_device *netdev) 8001 { 8002 struct igb_adapter *adapter = netdev_priv(netdev); 8003 struct e1000_hw *hw = &adapter->hw; 8004 struct sk_buff *skb; 8005 u32 wupl; 8006 8007 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 8008 8009 /* WUPM stores only the first 128 bytes of the wake packet. 8010 * Read the packet only if we have the whole thing. 8011 */ 8012 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8013 return; 8014 8015 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8016 if (!skb) 8017 return; 8018 8019 skb_put(skb, wupl); 8020 8021 /* Ensure reads are 32-bit aligned */ 8022 wupl = roundup(wupl, 4); 8023 8024 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8025 8026 skb->protocol = eth_type_trans(skb, netdev); 8027 netif_rx(skb); 8028 } 8029 8030 static int __maybe_unused igb_suspend(struct device *dev) 8031 { 8032 int retval; 8033 bool wake; 8034 struct pci_dev *pdev = to_pci_dev(dev); 8035 8036 retval = __igb_shutdown(pdev, &wake, 0); 8037 if (retval) 8038 return retval; 8039 8040 if (wake) { 8041 pci_prepare_to_sleep(pdev); 8042 } else { 8043 pci_wake_from_d3(pdev, false); 8044 pci_set_power_state(pdev, PCI_D3hot); 8045 } 8046 8047 return 0; 8048 } 8049 8050 static int __maybe_unused igb_resume(struct device *dev) 8051 { 8052 struct pci_dev *pdev = to_pci_dev(dev); 8053 struct net_device *netdev = pci_get_drvdata(pdev); 8054 struct igb_adapter *adapter = netdev_priv(netdev); 8055 struct e1000_hw *hw = &adapter->hw; 8056 u32 err, val; 8057 8058 pci_set_power_state(pdev, PCI_D0); 8059 pci_restore_state(pdev); 8060 pci_save_state(pdev); 8061 8062 if (!pci_device_is_present(pdev)) 8063 return -ENODEV; 8064 err = pci_enable_device_mem(pdev); 8065 if (err) { 8066 dev_err(&pdev->dev, 8067 "igb: Cannot enable PCI device from suspend\n"); 8068 return err; 8069 } 8070 pci_set_master(pdev); 8071 8072 pci_enable_wake(pdev, PCI_D3hot, 0); 8073 pci_enable_wake(pdev, PCI_D3cold, 0); 8074 8075 if (igb_init_interrupt_scheme(adapter, true)) { 8076 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8077 return -ENOMEM; 8078 } 8079 8080 igb_reset(adapter); 8081 8082 /* let the f/w know that the h/w is now under the control of the 8083 * driver. 8084 */ 8085 igb_get_hw_control(adapter); 8086 8087 val = rd32(E1000_WUS); 8088 if (val & WAKE_PKT_WUS) 8089 igb_deliver_wake_packet(netdev); 8090 8091 wr32(E1000_WUS, ~0); 8092 8093 rtnl_lock(); 8094 if (!err && netif_running(netdev)) 8095 err = __igb_open(netdev, true); 8096 8097 if (!err) 8098 netif_device_attach(netdev); 8099 rtnl_unlock(); 8100 8101 return err; 8102 } 8103 8104 static int __maybe_unused igb_runtime_idle(struct device *dev) 8105 { 8106 struct pci_dev *pdev = to_pci_dev(dev); 8107 struct net_device *netdev = pci_get_drvdata(pdev); 8108 struct igb_adapter *adapter = netdev_priv(netdev); 8109 8110 if (!igb_has_link(adapter)) 8111 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8112 8113 return -EBUSY; 8114 } 8115 8116 static int __maybe_unused igb_runtime_suspend(struct device *dev) 8117 { 8118 struct pci_dev *pdev = to_pci_dev(dev); 8119 int retval; 8120 bool wake; 8121 8122 retval = __igb_shutdown(pdev, &wake, 1); 8123 if (retval) 8124 return retval; 8125 8126 if (wake) { 8127 pci_prepare_to_sleep(pdev); 8128 } else { 8129 pci_wake_from_d3(pdev, false); 8130 pci_set_power_state(pdev, PCI_D3hot); 8131 } 8132 8133 return 0; 8134 } 8135 8136 static int __maybe_unused igb_runtime_resume(struct device *dev) 8137 { 8138 return igb_resume(dev); 8139 } 8140 8141 static void igb_shutdown(struct pci_dev *pdev) 8142 { 8143 bool wake; 8144 8145 __igb_shutdown(pdev, &wake, 0); 8146 8147 if (system_state == SYSTEM_POWER_OFF) { 8148 pci_wake_from_d3(pdev, wake); 8149 pci_set_power_state(pdev, PCI_D3hot); 8150 } 8151 } 8152 8153 #ifdef CONFIG_PCI_IOV 8154 static int igb_sriov_reinit(struct pci_dev *dev) 8155 { 8156 struct net_device *netdev = pci_get_drvdata(dev); 8157 struct igb_adapter *adapter = netdev_priv(netdev); 8158 struct pci_dev *pdev = adapter->pdev; 8159 8160 rtnl_lock(); 8161 8162 if (netif_running(netdev)) 8163 igb_close(netdev); 8164 else 8165 igb_reset(adapter); 8166 8167 igb_clear_interrupt_scheme(adapter); 8168 8169 igb_init_queue_configuration(adapter); 8170 8171 if (igb_init_interrupt_scheme(adapter, true)) { 8172 rtnl_unlock(); 8173 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8174 return -ENOMEM; 8175 } 8176 8177 if (netif_running(netdev)) 8178 igb_open(netdev); 8179 8180 rtnl_unlock(); 8181 8182 return 0; 8183 } 8184 8185 static int igb_pci_disable_sriov(struct pci_dev *dev) 8186 { 8187 int err = igb_disable_sriov(dev); 8188 8189 if (!err) 8190 err = igb_sriov_reinit(dev); 8191 8192 return err; 8193 } 8194 8195 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8196 { 8197 int err = igb_enable_sriov(dev, num_vfs); 8198 8199 if (err) 8200 goto out; 8201 8202 err = igb_sriov_reinit(dev); 8203 if (!err) 8204 return num_vfs; 8205 8206 out: 8207 return err; 8208 } 8209 8210 #endif 8211 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8212 { 8213 #ifdef CONFIG_PCI_IOV 8214 if (num_vfs == 0) 8215 return igb_pci_disable_sriov(dev); 8216 else 8217 return igb_pci_enable_sriov(dev, num_vfs); 8218 #endif 8219 return 0; 8220 } 8221 8222 #ifdef CONFIG_NET_POLL_CONTROLLER 8223 /* Polling 'interrupt' - used by things like netconsole to send skbs 8224 * without having to re-enable interrupts. It's not called while 8225 * the interrupt routine is executing. 8226 */ 8227 static void igb_netpoll(struct net_device *netdev) 8228 { 8229 struct igb_adapter *adapter = netdev_priv(netdev); 8230 struct e1000_hw *hw = &adapter->hw; 8231 struct igb_q_vector *q_vector; 8232 int i; 8233 8234 for (i = 0; i < adapter->num_q_vectors; i++) { 8235 q_vector = adapter->q_vector[i]; 8236 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8237 wr32(E1000_EIMC, q_vector->eims_value); 8238 else 8239 igb_irq_disable(adapter); 8240 napi_schedule(&q_vector->napi); 8241 } 8242 } 8243 #endif /* CONFIG_NET_POLL_CONTROLLER */ 8244 8245 /** 8246 * igb_io_error_detected - called when PCI error is detected 8247 * @pdev: Pointer to PCI device 8248 * @state: The current pci connection state 8249 * 8250 * This function is called after a PCI bus error affecting 8251 * this device has been detected. 8252 **/ 8253 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8254 pci_channel_state_t state) 8255 { 8256 struct net_device *netdev = pci_get_drvdata(pdev); 8257 struct igb_adapter *adapter = netdev_priv(netdev); 8258 8259 netif_device_detach(netdev); 8260 8261 if (state == pci_channel_io_perm_failure) 8262 return PCI_ERS_RESULT_DISCONNECT; 8263 8264 if (netif_running(netdev)) 8265 igb_down(adapter); 8266 pci_disable_device(pdev); 8267 8268 /* Request a slot slot reset. */ 8269 return PCI_ERS_RESULT_NEED_RESET; 8270 } 8271 8272 /** 8273 * igb_io_slot_reset - called after the pci bus has been reset. 8274 * @pdev: Pointer to PCI device 8275 * 8276 * Restart the card from scratch, as if from a cold-boot. Implementation 8277 * resembles the first-half of the igb_resume routine. 8278 **/ 8279 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8280 { 8281 struct net_device *netdev = pci_get_drvdata(pdev); 8282 struct igb_adapter *adapter = netdev_priv(netdev); 8283 struct e1000_hw *hw = &adapter->hw; 8284 pci_ers_result_t result; 8285 int err; 8286 8287 if (pci_enable_device_mem(pdev)) { 8288 dev_err(&pdev->dev, 8289 "Cannot re-enable PCI device after reset.\n"); 8290 result = PCI_ERS_RESULT_DISCONNECT; 8291 } else { 8292 pci_set_master(pdev); 8293 pci_restore_state(pdev); 8294 pci_save_state(pdev); 8295 8296 pci_enable_wake(pdev, PCI_D3hot, 0); 8297 pci_enable_wake(pdev, PCI_D3cold, 0); 8298 8299 /* In case of PCI error, adapter lose its HW address 8300 * so we should re-assign it here. 8301 */ 8302 hw->hw_addr = adapter->io_addr; 8303 8304 igb_reset(adapter); 8305 wr32(E1000_WUS, ~0); 8306 result = PCI_ERS_RESULT_RECOVERED; 8307 } 8308 8309 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8310 if (err) { 8311 dev_err(&pdev->dev, 8312 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8313 err); 8314 /* non-fatal, continue */ 8315 } 8316 8317 return result; 8318 } 8319 8320 /** 8321 * igb_io_resume - called when traffic can start flowing again. 8322 * @pdev: Pointer to PCI device 8323 * 8324 * This callback is called when the error recovery driver tells us that 8325 * its OK to resume normal operation. Implementation resembles the 8326 * second-half of the igb_resume routine. 8327 */ 8328 static void igb_io_resume(struct pci_dev *pdev) 8329 { 8330 struct net_device *netdev = pci_get_drvdata(pdev); 8331 struct igb_adapter *adapter = netdev_priv(netdev); 8332 8333 if (netif_running(netdev)) { 8334 if (igb_up(adapter)) { 8335 dev_err(&pdev->dev, "igb_up failed after reset\n"); 8336 return; 8337 } 8338 } 8339 8340 netif_device_attach(netdev); 8341 8342 /* let the f/w know that the h/w is now under the control of the 8343 * driver. 8344 */ 8345 igb_get_hw_control(adapter); 8346 } 8347 8348 /** 8349 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 8350 * @adapter: Pointer to adapter structure 8351 * @index: Index of the RAR entry which need to be synced with MAC table 8352 **/ 8353 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 8354 { 8355 struct e1000_hw *hw = &adapter->hw; 8356 u32 rar_low, rar_high; 8357 u8 *addr = adapter->mac_table[index].addr; 8358 8359 /* HW expects these to be in network order when they are plugged 8360 * into the registers which are little endian. In order to guarantee 8361 * that ordering we need to do an leXX_to_cpup here in order to be 8362 * ready for the byteswap that occurs with writel 8363 */ 8364 rar_low = le32_to_cpup((__le32 *)(addr)); 8365 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 8366 8367 /* Indicate to hardware the Address is Valid. */ 8368 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 8369 rar_high |= E1000_RAH_AV; 8370 8371 if (hw->mac.type == e1000_82575) 8372 rar_high |= E1000_RAH_POOL_1 * 8373 adapter->mac_table[index].queue; 8374 else 8375 rar_high |= E1000_RAH_POOL_1 << 8376 adapter->mac_table[index].queue; 8377 } 8378 8379 wr32(E1000_RAL(index), rar_low); 8380 wrfl(); 8381 wr32(E1000_RAH(index), rar_high); 8382 wrfl(); 8383 } 8384 8385 static int igb_set_vf_mac(struct igb_adapter *adapter, 8386 int vf, unsigned char *mac_addr) 8387 { 8388 struct e1000_hw *hw = &adapter->hw; 8389 /* VF MAC addresses start at end of receive addresses and moves 8390 * towards the first, as a result a collision should not be possible 8391 */ 8392 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 8393 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 8394 8395 ether_addr_copy(vf_mac_addr, mac_addr); 8396 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 8397 adapter->mac_table[rar_entry].queue = vf; 8398 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 8399 igb_rar_set_index(adapter, rar_entry); 8400 8401 return 0; 8402 } 8403 8404 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 8405 { 8406 struct igb_adapter *adapter = netdev_priv(netdev); 8407 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 8408 return -EINVAL; 8409 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 8410 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 8411 dev_info(&adapter->pdev->dev, 8412 "Reload the VF driver to make this change effective."); 8413 if (test_bit(__IGB_DOWN, &adapter->state)) { 8414 dev_warn(&adapter->pdev->dev, 8415 "The VF MAC address has been set, but the PF device is not up.\n"); 8416 dev_warn(&adapter->pdev->dev, 8417 "Bring the PF device up before attempting to use the VF device.\n"); 8418 } 8419 return igb_set_vf_mac(adapter, vf, mac); 8420 } 8421 8422 static int igb_link_mbps(int internal_link_speed) 8423 { 8424 switch (internal_link_speed) { 8425 case SPEED_100: 8426 return 100; 8427 case SPEED_1000: 8428 return 1000; 8429 default: 8430 return 0; 8431 } 8432 } 8433 8434 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 8435 int link_speed) 8436 { 8437 int rf_dec, rf_int; 8438 u32 bcnrc_val; 8439 8440 if (tx_rate != 0) { 8441 /* Calculate the rate factor values to set */ 8442 rf_int = link_speed / tx_rate; 8443 rf_dec = (link_speed - (rf_int * tx_rate)); 8444 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8445 tx_rate; 8446 8447 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8448 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8449 E1000_RTTBCNRC_RF_INT_MASK); 8450 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8451 } else { 8452 bcnrc_val = 0; 8453 } 8454 8455 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8456 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8457 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8458 */ 8459 wr32(E1000_RTTBCNRM, 0x14); 8460 wr32(E1000_RTTBCNRC, bcnrc_val); 8461 } 8462 8463 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8464 { 8465 int actual_link_speed, i; 8466 bool reset_rate = false; 8467 8468 /* VF TX rate limit was not set or not supported */ 8469 if ((adapter->vf_rate_link_speed == 0) || 8470 (adapter->hw.mac.type != e1000_82576)) 8471 return; 8472 8473 actual_link_speed = igb_link_mbps(adapter->link_speed); 8474 if (actual_link_speed != adapter->vf_rate_link_speed) { 8475 reset_rate = true; 8476 adapter->vf_rate_link_speed = 0; 8477 dev_info(&adapter->pdev->dev, 8478 "Link speed has been changed. VF Transmit rate is disabled\n"); 8479 } 8480 8481 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8482 if (reset_rate) 8483 adapter->vf_data[i].tx_rate = 0; 8484 8485 igb_set_vf_rate_limit(&adapter->hw, i, 8486 adapter->vf_data[i].tx_rate, 8487 actual_link_speed); 8488 } 8489 } 8490 8491 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8492 int min_tx_rate, int max_tx_rate) 8493 { 8494 struct igb_adapter *adapter = netdev_priv(netdev); 8495 struct e1000_hw *hw = &adapter->hw; 8496 int actual_link_speed; 8497 8498 if (hw->mac.type != e1000_82576) 8499 return -EOPNOTSUPP; 8500 8501 if (min_tx_rate) 8502 return -EINVAL; 8503 8504 actual_link_speed = igb_link_mbps(adapter->link_speed); 8505 if ((vf >= adapter->vfs_allocated_count) || 8506 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8507 (max_tx_rate < 0) || 8508 (max_tx_rate > actual_link_speed)) 8509 return -EINVAL; 8510 8511 adapter->vf_rate_link_speed = actual_link_speed; 8512 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8513 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8514 8515 return 0; 8516 } 8517 8518 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8519 bool setting) 8520 { 8521 struct igb_adapter *adapter = netdev_priv(netdev); 8522 struct e1000_hw *hw = &adapter->hw; 8523 u32 reg_val, reg_offset; 8524 8525 if (!adapter->vfs_allocated_count) 8526 return -EOPNOTSUPP; 8527 8528 if (vf >= adapter->vfs_allocated_count) 8529 return -EINVAL; 8530 8531 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8532 reg_val = rd32(reg_offset); 8533 if (setting) 8534 reg_val |= (BIT(vf) | 8535 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8536 else 8537 reg_val &= ~(BIT(vf) | 8538 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8539 wr32(reg_offset, reg_val); 8540 8541 adapter->vf_data[vf].spoofchk_enabled = setting; 8542 return 0; 8543 } 8544 8545 static int igb_ndo_get_vf_config(struct net_device *netdev, 8546 int vf, struct ifla_vf_info *ivi) 8547 { 8548 struct igb_adapter *adapter = netdev_priv(netdev); 8549 if (vf >= adapter->vfs_allocated_count) 8550 return -EINVAL; 8551 ivi->vf = vf; 8552 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8553 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8554 ivi->min_tx_rate = 0; 8555 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8556 ivi->qos = adapter->vf_data[vf].pf_qos; 8557 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8558 return 0; 8559 } 8560 8561 static void igb_vmm_control(struct igb_adapter *adapter) 8562 { 8563 struct e1000_hw *hw = &adapter->hw; 8564 u32 reg; 8565 8566 switch (hw->mac.type) { 8567 case e1000_82575: 8568 case e1000_i210: 8569 case e1000_i211: 8570 case e1000_i354: 8571 default: 8572 /* replication is not supported for 82575 */ 8573 return; 8574 case e1000_82576: 8575 /* notify HW that the MAC is adding vlan tags */ 8576 reg = rd32(E1000_DTXCTL); 8577 reg |= E1000_DTXCTL_VLAN_ADDED; 8578 wr32(E1000_DTXCTL, reg); 8579 /* Fall through */ 8580 case e1000_82580: 8581 /* enable replication vlan tag stripping */ 8582 reg = rd32(E1000_RPLOLR); 8583 reg |= E1000_RPLOLR_STRVLAN; 8584 wr32(E1000_RPLOLR, reg); 8585 /* Fall through */ 8586 case e1000_i350: 8587 /* none of the above registers are supported by i350 */ 8588 break; 8589 } 8590 8591 if (adapter->vfs_allocated_count) { 8592 igb_vmdq_set_loopback_pf(hw, true); 8593 igb_vmdq_set_replication_pf(hw, true); 8594 igb_vmdq_set_anti_spoofing_pf(hw, true, 8595 adapter->vfs_allocated_count); 8596 } else { 8597 igb_vmdq_set_loopback_pf(hw, false); 8598 igb_vmdq_set_replication_pf(hw, false); 8599 } 8600 } 8601 8602 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8603 { 8604 struct e1000_hw *hw = &adapter->hw; 8605 u32 dmac_thr; 8606 u16 hwm; 8607 8608 if (hw->mac.type > e1000_82580) { 8609 if (adapter->flags & IGB_FLAG_DMAC) { 8610 u32 reg; 8611 8612 /* force threshold to 0. */ 8613 wr32(E1000_DMCTXTH, 0); 8614 8615 /* DMA Coalescing high water mark needs to be greater 8616 * than the Rx threshold. Set hwm to PBA - max frame 8617 * size in 16B units, capping it at PBA - 6KB. 8618 */ 8619 hwm = 64 * (pba - 6); 8620 reg = rd32(E1000_FCRTC); 8621 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8622 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8623 & E1000_FCRTC_RTH_COAL_MASK); 8624 wr32(E1000_FCRTC, reg); 8625 8626 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8627 * frame size, capping it at PBA - 10KB. 8628 */ 8629 dmac_thr = pba - 10; 8630 reg = rd32(E1000_DMACR); 8631 reg &= ~E1000_DMACR_DMACTHR_MASK; 8632 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8633 & E1000_DMACR_DMACTHR_MASK); 8634 8635 /* transition to L0x or L1 if available..*/ 8636 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8637 8638 /* watchdog timer= +-1000 usec in 32usec intervals */ 8639 reg |= (1000 >> 5); 8640 8641 /* Disable BMC-to-OS Watchdog Enable */ 8642 if (hw->mac.type != e1000_i354) 8643 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8644 8645 wr32(E1000_DMACR, reg); 8646 8647 /* no lower threshold to disable 8648 * coalescing(smart fifb)-UTRESH=0 8649 */ 8650 wr32(E1000_DMCRTRH, 0); 8651 8652 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8653 8654 wr32(E1000_DMCTLX, reg); 8655 8656 /* free space in tx packet buffer to wake from 8657 * DMA coal 8658 */ 8659 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8660 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8661 8662 /* make low power state decision controlled 8663 * by DMA coal 8664 */ 8665 reg = rd32(E1000_PCIEMISC); 8666 reg &= ~E1000_PCIEMISC_LX_DECISION; 8667 wr32(E1000_PCIEMISC, reg); 8668 } /* endif adapter->dmac is not disabled */ 8669 } else if (hw->mac.type == e1000_82580) { 8670 u32 reg = rd32(E1000_PCIEMISC); 8671 8672 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8673 wr32(E1000_DMACR, 0); 8674 } 8675 } 8676 8677 /** 8678 * igb_read_i2c_byte - Reads 8 bit word over I2C 8679 * @hw: pointer to hardware structure 8680 * @byte_offset: byte offset to read 8681 * @dev_addr: device address 8682 * @data: value read 8683 * 8684 * Performs byte read operation over I2C interface at 8685 * a specified device address. 8686 **/ 8687 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8688 u8 dev_addr, u8 *data) 8689 { 8690 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8691 struct i2c_client *this_client = adapter->i2c_client; 8692 s32 status; 8693 u16 swfw_mask = 0; 8694 8695 if (!this_client) 8696 return E1000_ERR_I2C; 8697 8698 swfw_mask = E1000_SWFW_PHY0_SM; 8699 8700 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8701 return E1000_ERR_SWFW_SYNC; 8702 8703 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8704 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8705 8706 if (status < 0) 8707 return E1000_ERR_I2C; 8708 else { 8709 *data = status; 8710 return 0; 8711 } 8712 } 8713 8714 /** 8715 * igb_write_i2c_byte - Writes 8 bit word over I2C 8716 * @hw: pointer to hardware structure 8717 * @byte_offset: byte offset to write 8718 * @dev_addr: device address 8719 * @data: value to write 8720 * 8721 * Performs byte write operation over I2C interface at 8722 * a specified device address. 8723 **/ 8724 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8725 u8 dev_addr, u8 data) 8726 { 8727 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8728 struct i2c_client *this_client = adapter->i2c_client; 8729 s32 status; 8730 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8731 8732 if (!this_client) 8733 return E1000_ERR_I2C; 8734 8735 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8736 return E1000_ERR_SWFW_SYNC; 8737 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8738 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8739 8740 if (status) 8741 return E1000_ERR_I2C; 8742 else 8743 return 0; 8744 8745 } 8746 8747 int igb_reinit_queues(struct igb_adapter *adapter) 8748 { 8749 struct net_device *netdev = adapter->netdev; 8750 struct pci_dev *pdev = adapter->pdev; 8751 int err = 0; 8752 8753 if (netif_running(netdev)) 8754 igb_close(netdev); 8755 8756 igb_reset_interrupt_capability(adapter); 8757 8758 if (igb_init_interrupt_scheme(adapter, true)) { 8759 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8760 return -ENOMEM; 8761 } 8762 8763 if (netif_running(netdev)) 8764 err = igb_open(netdev); 8765 8766 return err; 8767 } 8768 8769 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 8770 { 8771 struct igb_nfc_filter *rule; 8772 8773 spin_lock(&adapter->nfc_lock); 8774 8775 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8776 igb_erase_filter(adapter, rule); 8777 8778 spin_unlock(&adapter->nfc_lock); 8779 } 8780 8781 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 8782 { 8783 struct igb_nfc_filter *rule; 8784 8785 spin_lock(&adapter->nfc_lock); 8786 8787 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8788 igb_add_filter(adapter, rule); 8789 8790 spin_unlock(&adapter->nfc_lock); 8791 } 8792 /* igb_main.c */ 8793