1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 4 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static void igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 170 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 171 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 172 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 173 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 174 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 175 bool setting); 176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 177 struct ifla_vf_info *ivi); 178 static void igb_check_vf_rate_limit(struct igb_adapter *); 179 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 180 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 181 182 #ifdef CONFIG_PCI_IOV 183 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185 static int igb_disable_sriov(struct pci_dev *dev); 186 static int igb_pci_disable_sriov(struct pci_dev *dev); 187 #endif 188 189 #ifdef CONFIG_PM 190 #ifdef CONFIG_PM_SLEEP 191 static int igb_suspend(struct device *); 192 #endif 193 static int igb_resume(struct device *); 194 static int igb_runtime_suspend(struct device *dev); 195 static int igb_runtime_resume(struct device *dev); 196 static int igb_runtime_idle(struct device *dev); 197 static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201 }; 202 #endif 203 static void igb_shutdown(struct pci_dev *); 204 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205 #ifdef CONFIG_IGB_DCA 206 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207 static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211 }; 212 #endif 213 #ifdef CONFIG_NET_POLL_CONTROLLER 214 /* for netdump / net console */ 215 static void igb_netpoll(struct net_device *); 216 #endif 217 #ifdef CONFIG_PCI_IOV 218 static unsigned int max_vfs; 219 module_param(max_vfs, uint, 0); 220 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 221 #endif /* CONFIG_PCI_IOV */ 222 223 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 224 pci_channel_state_t); 225 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 226 static void igb_io_resume(struct pci_dev *); 227 228 static const struct pci_error_handlers igb_err_handler = { 229 .error_detected = igb_io_error_detected, 230 .slot_reset = igb_io_slot_reset, 231 .resume = igb_io_resume, 232 }; 233 234 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 235 236 static struct pci_driver igb_driver = { 237 .name = igb_driver_name, 238 .id_table = igb_pci_tbl, 239 .probe = igb_probe, 240 .remove = igb_remove, 241 #ifdef CONFIG_PM 242 .driver.pm = &igb_pm_ops, 243 #endif 244 .shutdown = igb_shutdown, 245 .sriov_configure = igb_pci_sriov_configure, 246 .err_handler = &igb_err_handler 247 }; 248 249 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 250 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 251 MODULE_LICENSE("GPL"); 252 MODULE_VERSION(DRV_VERSION); 253 254 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 255 static int debug = -1; 256 module_param(debug, int, 0); 257 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 258 259 struct igb_reg_info { 260 u32 ofs; 261 char *name; 262 }; 263 264 static const struct igb_reg_info igb_reg_info_tbl[] = { 265 266 /* General Registers */ 267 {E1000_CTRL, "CTRL"}, 268 {E1000_STATUS, "STATUS"}, 269 {E1000_CTRL_EXT, "CTRL_EXT"}, 270 271 /* Interrupt Registers */ 272 {E1000_ICR, "ICR"}, 273 274 /* RX Registers */ 275 {E1000_RCTL, "RCTL"}, 276 {E1000_RDLEN(0), "RDLEN"}, 277 {E1000_RDH(0), "RDH"}, 278 {E1000_RDT(0), "RDT"}, 279 {E1000_RXDCTL(0), "RXDCTL"}, 280 {E1000_RDBAL(0), "RDBAL"}, 281 {E1000_RDBAH(0), "RDBAH"}, 282 283 /* TX Registers */ 284 {E1000_TCTL, "TCTL"}, 285 {E1000_TDBAL(0), "TDBAL"}, 286 {E1000_TDBAH(0), "TDBAH"}, 287 {E1000_TDLEN(0), "TDLEN"}, 288 {E1000_TDH(0), "TDH"}, 289 {E1000_TDT(0), "TDT"}, 290 {E1000_TXDCTL(0), "TXDCTL"}, 291 {E1000_TDFH, "TDFH"}, 292 {E1000_TDFT, "TDFT"}, 293 {E1000_TDFHS, "TDFHS"}, 294 {E1000_TDFPC, "TDFPC"}, 295 296 /* List Terminator */ 297 {} 298 }; 299 300 /* igb_regdump - register printout routine */ 301 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 302 { 303 int n = 0; 304 char rname[16]; 305 u32 regs[8]; 306 307 switch (reginfo->ofs) { 308 case E1000_RDLEN(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDLEN(n)); 311 break; 312 case E1000_RDH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDH(n)); 315 break; 316 case E1000_RDT(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDT(n)); 319 break; 320 case E1000_RXDCTL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RXDCTL(n)); 323 break; 324 case E1000_RDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_RDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAH(n)); 331 break; 332 case E1000_TDBAL(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_RDBAL(n)); 335 break; 336 case E1000_TDBAH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDBAH(n)); 339 break; 340 case E1000_TDLEN(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDLEN(n)); 343 break; 344 case E1000_TDH(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDH(n)); 347 break; 348 case E1000_TDT(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TDT(n)); 351 break; 352 case E1000_TXDCTL(0): 353 for (n = 0; n < 4; n++) 354 regs[n] = rd32(E1000_TXDCTL(n)); 355 break; 356 default: 357 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 358 return; 359 } 360 361 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 362 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 363 regs[2], regs[3]); 364 } 365 366 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 367 static void igb_dump(struct igb_adapter *adapter) 368 { 369 struct net_device *netdev = adapter->netdev; 370 struct e1000_hw *hw = &adapter->hw; 371 struct igb_reg_info *reginfo; 372 struct igb_ring *tx_ring; 373 union e1000_adv_tx_desc *tx_desc; 374 struct my_u0 { u64 a; u64 b; } *u0; 375 struct igb_ring *rx_ring; 376 union e1000_adv_rx_desc *rx_desc; 377 u32 staterr; 378 u16 i, n; 379 380 if (!netif_msg_hw(adapter)) 381 return; 382 383 /* Print netdevice Info */ 384 if (netdev) { 385 dev_info(&adapter->pdev->dev, "Net device Info\n"); 386 pr_info("Device Name state trans_start\n"); 387 pr_info("%-15s %016lX %016lX\n", netdev->name, 388 netdev->state, dev_trans_start(netdev)); 389 } 390 391 /* Print Registers */ 392 dev_info(&adapter->pdev->dev, "Register Dump\n"); 393 pr_info(" Register Name Value\n"); 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 395 reginfo->name; reginfo++) { 396 igb_regdump(hw, reginfo); 397 } 398 399 /* Print TX Ring Summary */ 400 if (!netdev || !netif_running(netdev)) 401 goto exit; 402 403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 405 for (n = 0; n < adapter->num_tx_queues; n++) { 406 struct igb_tx_buffer *buffer_info; 407 tx_ring = adapter->tx_ring[n]; 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 410 n, tx_ring->next_to_use, tx_ring->next_to_clean, 411 (u64)dma_unmap_addr(buffer_info, dma), 412 dma_unmap_len(buffer_info, len), 413 buffer_info->next_to_watch, 414 (u64)buffer_info->time_stamp); 415 } 416 417 /* Print TX Rings */ 418 if (!netif_msg_tx_done(adapter)) 419 goto rx_ring_summary; 420 421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 422 423 /* Transmit Descriptor Formats 424 * 425 * Advanced Transmit Descriptor 426 * +--------------------------------------------------------------+ 427 * 0 | Buffer Address [63:0] | 428 * +--------------------------------------------------------------+ 429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 430 * +--------------------------------------------------------------+ 431 * 63 46 45 40 39 38 36 35 32 31 24 15 0 432 */ 433 434 for (n = 0; n < adapter->num_tx_queues; n++) { 435 tx_ring = adapter->tx_ring[n]; 436 pr_info("------------------------------------\n"); 437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 438 pr_info("------------------------------------\n"); 439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 440 441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 442 const char *next_desc; 443 struct igb_tx_buffer *buffer_info; 444 tx_desc = IGB_TX_DESC(tx_ring, i); 445 buffer_info = &tx_ring->tx_buffer_info[i]; 446 u0 = (struct my_u0 *)tx_desc; 447 if (i == tx_ring->next_to_use && 448 i == tx_ring->next_to_clean) 449 next_desc = " NTC/U"; 450 else if (i == tx_ring->next_to_use) 451 next_desc = " NTU"; 452 else if (i == tx_ring->next_to_clean) 453 next_desc = " NTC"; 454 else 455 next_desc = ""; 456 457 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 458 i, le64_to_cpu(u0->a), 459 le64_to_cpu(u0->b), 460 (u64)dma_unmap_addr(buffer_info, dma), 461 dma_unmap_len(buffer_info, len), 462 buffer_info->next_to_watch, 463 (u64)buffer_info->time_stamp, 464 buffer_info->skb, next_desc); 465 466 if (netif_msg_pktdata(adapter) && buffer_info->skb) 467 print_hex_dump(KERN_INFO, "", 468 DUMP_PREFIX_ADDRESS, 469 16, 1, buffer_info->skb->data, 470 dma_unmap_len(buffer_info, len), 471 true); 472 } 473 } 474 475 /* Print RX Rings Summary */ 476 rx_ring_summary: 477 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 478 pr_info("Queue [NTU] [NTC]\n"); 479 for (n = 0; n < adapter->num_rx_queues; n++) { 480 rx_ring = adapter->rx_ring[n]; 481 pr_info(" %5d %5X %5X\n", 482 n, rx_ring->next_to_use, rx_ring->next_to_clean); 483 } 484 485 /* Print RX Rings */ 486 if (!netif_msg_rx_status(adapter)) 487 goto exit; 488 489 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 490 491 /* Advanced Receive Descriptor (Read) Format 492 * 63 1 0 493 * +-----------------------------------------------------+ 494 * 0 | Packet Buffer Address [63:1] |A0/NSE| 495 * +----------------------------------------------+------+ 496 * 8 | Header Buffer Address [63:1] | DD | 497 * +-----------------------------------------------------+ 498 * 499 * 500 * Advanced Receive Descriptor (Write-Back) Format 501 * 502 * 63 48 47 32 31 30 21 20 17 16 4 3 0 503 * +------------------------------------------------------+ 504 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 505 * | Checksum Ident | | | | Type | Type | 506 * +------------------------------------------------------+ 507 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 508 * +------------------------------------------------------+ 509 * 63 48 47 32 31 20 19 0 510 */ 511 512 for (n = 0; n < adapter->num_rx_queues; n++) { 513 rx_ring = adapter->rx_ring[n]; 514 pr_info("------------------------------------\n"); 515 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 516 pr_info("------------------------------------\n"); 517 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 igb_rx_bufsz(rx_ring), true); 558 } 559 } 560 } 561 } 562 563 exit: 564 return; 565 } 566 567 /** 568 * igb_get_i2c_data - Reads the I2C SDA data bit 569 * @hw: pointer to hardware structure 570 * @i2cctl: Current value of I2CCTL register 571 * 572 * Returns the I2C data bit value 573 **/ 574 static int igb_get_i2c_data(void *data) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 return !!(i2cctl & E1000_I2C_DATA_IN); 581 } 582 583 /** 584 * igb_set_i2c_data - Sets the I2C data bit 585 * @data: pointer to hardware structure 586 * @state: I2C data value (0 or 1) to set 587 * 588 * Sets the I2C data bit 589 **/ 590 static void igb_set_i2c_data(void *data, int state) 591 { 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 if (state) 597 i2cctl |= E1000_I2C_DATA_OUT; 598 else 599 i2cctl &= ~E1000_I2C_DATA_OUT; 600 601 i2cctl &= ~E1000_I2C_DATA_OE_N; 602 i2cctl |= E1000_I2C_CLK_OE_N; 603 wr32(E1000_I2CPARAMS, i2cctl); 604 wrfl(); 605 606 } 607 608 /** 609 * igb_set_i2c_clk - Sets the I2C SCL clock 610 * @data: pointer to hardware structure 611 * @state: state to set clock 612 * 613 * Sets the I2C clock line to state 614 **/ 615 static void igb_set_i2c_clk(void *data, int state) 616 { 617 struct igb_adapter *adapter = (struct igb_adapter *)data; 618 struct e1000_hw *hw = &adapter->hw; 619 s32 i2cctl = rd32(E1000_I2CPARAMS); 620 621 if (state) { 622 i2cctl |= E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } else { 625 i2cctl &= ~E1000_I2C_CLK_OUT; 626 i2cctl &= ~E1000_I2C_CLK_OE_N; 627 } 628 wr32(E1000_I2CPARAMS, i2cctl); 629 wrfl(); 630 } 631 632 /** 633 * igb_get_i2c_clk - Gets the I2C SCL clock state 634 * @data: pointer to hardware structure 635 * 636 * Gets the I2C clock state 637 **/ 638 static int igb_get_i2c_clk(void *data) 639 { 640 struct igb_adapter *adapter = (struct igb_adapter *)data; 641 struct e1000_hw *hw = &adapter->hw; 642 s32 i2cctl = rd32(E1000_I2CPARAMS); 643 644 return !!(i2cctl & E1000_I2C_CLK_IN); 645 } 646 647 static const struct i2c_algo_bit_data igb_i2c_algo = { 648 .setsda = igb_set_i2c_data, 649 .setscl = igb_set_i2c_clk, 650 .getsda = igb_get_i2c_data, 651 .getscl = igb_get_i2c_clk, 652 .udelay = 5, 653 .timeout = 20, 654 }; 655 656 /** 657 * igb_get_hw_dev - return device 658 * @hw: pointer to hardware structure 659 * 660 * used by hardware layer to print debugging information 661 **/ 662 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 663 { 664 struct igb_adapter *adapter = hw->back; 665 return adapter->netdev; 666 } 667 668 /** 669 * igb_init_module - Driver Registration Routine 670 * 671 * igb_init_module is the first routine called when the driver is 672 * loaded. All it does is register with the PCI subsystem. 673 **/ 674 static int __init igb_init_module(void) 675 { 676 int ret; 677 678 pr_info("%s - version %s\n", 679 igb_driver_string, igb_driver_version); 680 pr_info("%s\n", igb_copyright); 681 682 #ifdef CONFIG_IGB_DCA 683 dca_register_notify(&dca_notifier); 684 #endif 685 ret = pci_register_driver(&igb_driver); 686 return ret; 687 } 688 689 module_init(igb_init_module); 690 691 /** 692 * igb_exit_module - Driver Exit Cleanup Routine 693 * 694 * igb_exit_module is called just before the driver is removed 695 * from memory. 696 **/ 697 static void __exit igb_exit_module(void) 698 { 699 #ifdef CONFIG_IGB_DCA 700 dca_unregister_notify(&dca_notifier); 701 #endif 702 pci_unregister_driver(&igb_driver); 703 } 704 705 module_exit(igb_exit_module); 706 707 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 708 /** 709 * igb_cache_ring_register - Descriptor ring to register mapping 710 * @adapter: board private structure to initialize 711 * 712 * Once we know the feature-set enabled for the device, we'll cache 713 * the register offset the descriptor ring is assigned to. 714 **/ 715 static void igb_cache_ring_register(struct igb_adapter *adapter) 716 { 717 int i = 0, j = 0; 718 u32 rbase_offset = adapter->vfs_allocated_count; 719 720 switch (adapter->hw.mac.type) { 721 case e1000_82576: 722 /* The queues are allocated for virtualization such that VF 0 723 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 724 * In order to avoid collision we start at the first free queue 725 * and continue consuming queues in the same sequence 726 */ 727 if (adapter->vfs_allocated_count) { 728 for (; i < adapter->rss_queues; i++) 729 adapter->rx_ring[i]->reg_idx = rbase_offset + 730 Q_IDX_82576(i); 731 } 732 /* Fall through */ 733 case e1000_82575: 734 case e1000_82580: 735 case e1000_i350: 736 case e1000_i354: 737 case e1000_i210: 738 case e1000_i211: 739 /* Fall through */ 740 default: 741 for (; i < adapter->num_rx_queues; i++) 742 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 743 for (; j < adapter->num_tx_queues; j++) 744 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 745 break; 746 } 747 } 748 749 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 750 { 751 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 752 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 753 u32 value = 0; 754 755 if (E1000_REMOVED(hw_addr)) 756 return ~value; 757 758 value = readl(&hw_addr[reg]); 759 760 /* reads should not return all F's */ 761 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 762 struct net_device *netdev = igb->netdev; 763 hw->hw_addr = NULL; 764 netif_device_detach(netdev); 765 netdev_err(netdev, "PCIe link lost, device now detached\n"); 766 } 767 768 return value; 769 } 770 771 /** 772 * igb_write_ivar - configure ivar for given MSI-X vector 773 * @hw: pointer to the HW structure 774 * @msix_vector: vector number we are allocating to a given ring 775 * @index: row index of IVAR register to write within IVAR table 776 * @offset: column offset of in IVAR, should be multiple of 8 777 * 778 * This function is intended to handle the writing of the IVAR register 779 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 780 * each containing an cause allocation for an Rx and Tx ring, and a 781 * variable number of rows depending on the number of queues supported. 782 **/ 783 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 784 int index, int offset) 785 { 786 u32 ivar = array_rd32(E1000_IVAR0, index); 787 788 /* clear any bits that are currently set */ 789 ivar &= ~((u32)0xFF << offset); 790 791 /* write vector and valid bit */ 792 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 793 794 array_wr32(E1000_IVAR0, index, ivar); 795 } 796 797 #define IGB_N0_QUEUE -1 798 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 799 { 800 struct igb_adapter *adapter = q_vector->adapter; 801 struct e1000_hw *hw = &adapter->hw; 802 int rx_queue = IGB_N0_QUEUE; 803 int tx_queue = IGB_N0_QUEUE; 804 u32 msixbm = 0; 805 806 if (q_vector->rx.ring) 807 rx_queue = q_vector->rx.ring->reg_idx; 808 if (q_vector->tx.ring) 809 tx_queue = q_vector->tx.ring->reg_idx; 810 811 switch (hw->mac.type) { 812 case e1000_82575: 813 /* The 82575 assigns vectors using a bitmask, which matches the 814 * bitmask for the EICR/EIMS/EIMC registers. To assign one 815 * or more queues to a vector, we write the appropriate bits 816 * into the MSIXBM register for that vector. 817 */ 818 if (rx_queue > IGB_N0_QUEUE) 819 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 820 if (tx_queue > IGB_N0_QUEUE) 821 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 822 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 823 msixbm |= E1000_EIMS_OTHER; 824 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 825 q_vector->eims_value = msixbm; 826 break; 827 case e1000_82576: 828 /* 82576 uses a table that essentially consists of 2 columns 829 * with 8 rows. The ordering is column-major so we use the 830 * lower 3 bits as the row index, and the 4th bit as the 831 * column offset. 832 */ 833 if (rx_queue > IGB_N0_QUEUE) 834 igb_write_ivar(hw, msix_vector, 835 rx_queue & 0x7, 836 (rx_queue & 0x8) << 1); 837 if (tx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 tx_queue & 0x7, 840 ((tx_queue & 0x8) << 1) + 8); 841 q_vector->eims_value = BIT(msix_vector); 842 break; 843 case e1000_82580: 844 case e1000_i350: 845 case e1000_i354: 846 case e1000_i210: 847 case e1000_i211: 848 /* On 82580 and newer adapters the scheme is similar to 82576 849 * however instead of ordering column-major we have things 850 * ordered row-major. So we traverse the table by using 851 * bit 0 as the column offset, and the remaining bits as the 852 * row index. 853 */ 854 if (rx_queue > IGB_N0_QUEUE) 855 igb_write_ivar(hw, msix_vector, 856 rx_queue >> 1, 857 (rx_queue & 0x1) << 4); 858 if (tx_queue > IGB_N0_QUEUE) 859 igb_write_ivar(hw, msix_vector, 860 tx_queue >> 1, 861 ((tx_queue & 0x1) << 4) + 8); 862 q_vector->eims_value = BIT(msix_vector); 863 break; 864 default: 865 BUG(); 866 break; 867 } 868 869 /* add q_vector eims value to global eims_enable_mask */ 870 adapter->eims_enable_mask |= q_vector->eims_value; 871 872 /* configure q_vector to set itr on first interrupt */ 873 q_vector->set_itr = 1; 874 } 875 876 /** 877 * igb_configure_msix - Configure MSI-X hardware 878 * @adapter: board private structure to initialize 879 * 880 * igb_configure_msix sets up the hardware to properly 881 * generate MSI-X interrupts. 882 **/ 883 static void igb_configure_msix(struct igb_adapter *adapter) 884 { 885 u32 tmp; 886 int i, vector = 0; 887 struct e1000_hw *hw = &adapter->hw; 888 889 adapter->eims_enable_mask = 0; 890 891 /* set vector for other causes, i.e. link changes */ 892 switch (hw->mac.type) { 893 case e1000_82575: 894 tmp = rd32(E1000_CTRL_EXT); 895 /* enable MSI-X PBA support*/ 896 tmp |= E1000_CTRL_EXT_PBA_CLR; 897 898 /* Auto-Mask interrupts upon ICR read. */ 899 tmp |= E1000_CTRL_EXT_EIAME; 900 tmp |= E1000_CTRL_EXT_IRCA; 901 902 wr32(E1000_CTRL_EXT, tmp); 903 904 /* enable msix_other interrupt */ 905 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 906 adapter->eims_other = E1000_EIMS_OTHER; 907 908 break; 909 910 case e1000_82576: 911 case e1000_82580: 912 case e1000_i350: 913 case e1000_i354: 914 case e1000_i210: 915 case e1000_i211: 916 /* Turn on MSI-X capability first, or our settings 917 * won't stick. And it will take days to debug. 918 */ 919 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 920 E1000_GPIE_PBA | E1000_GPIE_EIAME | 921 E1000_GPIE_NSICR); 922 923 /* enable msix_other interrupt */ 924 adapter->eims_other = BIT(vector); 925 tmp = (vector++ | E1000_IVAR_VALID) << 8; 926 927 wr32(E1000_IVAR_MISC, tmp); 928 break; 929 default: 930 /* do nothing, since nothing else supports MSI-X */ 931 break; 932 } /* switch (hw->mac.type) */ 933 934 adapter->eims_enable_mask |= adapter->eims_other; 935 936 for (i = 0; i < adapter->num_q_vectors; i++) 937 igb_assign_vector(adapter->q_vector[i], vector++); 938 939 wrfl(); 940 } 941 942 /** 943 * igb_request_msix - Initialize MSI-X interrupts 944 * @adapter: board private structure to initialize 945 * 946 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 947 * kernel. 948 **/ 949 static int igb_request_msix(struct igb_adapter *adapter) 950 { 951 struct net_device *netdev = adapter->netdev; 952 int i, err = 0, vector = 0, free_vector = 0; 953 954 err = request_irq(adapter->msix_entries[vector].vector, 955 igb_msix_other, 0, netdev->name, adapter); 956 if (err) 957 goto err_out; 958 959 for (i = 0; i < adapter->num_q_vectors; i++) { 960 struct igb_q_vector *q_vector = adapter->q_vector[i]; 961 962 vector++; 963 964 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 965 966 if (q_vector->rx.ring && q_vector->tx.ring) 967 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 968 q_vector->rx.ring->queue_index); 969 else if (q_vector->tx.ring) 970 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 971 q_vector->tx.ring->queue_index); 972 else if (q_vector->rx.ring) 973 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 974 q_vector->rx.ring->queue_index); 975 else 976 sprintf(q_vector->name, "%s-unused", netdev->name); 977 978 err = request_irq(adapter->msix_entries[vector].vector, 979 igb_msix_ring, 0, q_vector->name, 980 q_vector); 981 if (err) 982 goto err_free; 983 } 984 985 igb_configure_msix(adapter); 986 return 0; 987 988 err_free: 989 /* free already assigned IRQs */ 990 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 991 992 vector--; 993 for (i = 0; i < vector; i++) { 994 free_irq(adapter->msix_entries[free_vector++].vector, 995 adapter->q_vector[i]); 996 } 997 err_out: 998 return err; 999 } 1000 1001 /** 1002 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1003 * @adapter: board private structure to initialize 1004 * @v_idx: Index of vector to be freed 1005 * 1006 * This function frees the memory allocated to the q_vector. 1007 **/ 1008 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1009 { 1010 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1011 1012 adapter->q_vector[v_idx] = NULL; 1013 1014 /* igb_get_stats64() might access the rings on this vector, 1015 * we must wait a grace period before freeing it. 1016 */ 1017 if (q_vector) 1018 kfree_rcu(q_vector, rcu); 1019 } 1020 1021 /** 1022 * igb_reset_q_vector - Reset config for interrupt vector 1023 * @adapter: board private structure to initialize 1024 * @v_idx: Index of vector to be reset 1025 * 1026 * If NAPI is enabled it will delete any references to the 1027 * NAPI struct. This is preparation for igb_free_q_vector. 1028 **/ 1029 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1030 { 1031 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1032 1033 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1034 * allocated. So, q_vector is NULL so we should stop here. 1035 */ 1036 if (!q_vector) 1037 return; 1038 1039 if (q_vector->tx.ring) 1040 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1041 1042 if (q_vector->rx.ring) 1043 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1044 1045 netif_napi_del(&q_vector->napi); 1046 1047 } 1048 1049 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1050 { 1051 int v_idx = adapter->num_q_vectors; 1052 1053 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1054 pci_disable_msix(adapter->pdev); 1055 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1056 pci_disable_msi(adapter->pdev); 1057 1058 while (v_idx--) 1059 igb_reset_q_vector(adapter, v_idx); 1060 } 1061 1062 /** 1063 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1064 * @adapter: board private structure to initialize 1065 * 1066 * This function frees the memory allocated to the q_vectors. In addition if 1067 * NAPI is enabled it will delete any references to the NAPI struct prior 1068 * to freeing the q_vector. 1069 **/ 1070 static void igb_free_q_vectors(struct igb_adapter *adapter) 1071 { 1072 int v_idx = adapter->num_q_vectors; 1073 1074 adapter->num_tx_queues = 0; 1075 adapter->num_rx_queues = 0; 1076 adapter->num_q_vectors = 0; 1077 1078 while (v_idx--) { 1079 igb_reset_q_vector(adapter, v_idx); 1080 igb_free_q_vector(adapter, v_idx); 1081 } 1082 } 1083 1084 /** 1085 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1086 * @adapter: board private structure to initialize 1087 * 1088 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1089 * MSI-X interrupts allocated. 1090 */ 1091 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1092 { 1093 igb_free_q_vectors(adapter); 1094 igb_reset_interrupt_capability(adapter); 1095 } 1096 1097 /** 1098 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1099 * @adapter: board private structure to initialize 1100 * @msix: boolean value of MSIX capability 1101 * 1102 * Attempt to configure interrupts using the best available 1103 * capabilities of the hardware and kernel. 1104 **/ 1105 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1106 { 1107 int err; 1108 int numvecs, i; 1109 1110 if (!msix) 1111 goto msi_only; 1112 adapter->flags |= IGB_FLAG_HAS_MSIX; 1113 1114 /* Number of supported queues. */ 1115 adapter->num_rx_queues = adapter->rss_queues; 1116 if (adapter->vfs_allocated_count) 1117 adapter->num_tx_queues = 1; 1118 else 1119 adapter->num_tx_queues = adapter->rss_queues; 1120 1121 /* start with one vector for every Rx queue */ 1122 numvecs = adapter->num_rx_queues; 1123 1124 /* if Tx handler is separate add 1 for every Tx queue */ 1125 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1126 numvecs += adapter->num_tx_queues; 1127 1128 /* store the number of vectors reserved for queues */ 1129 adapter->num_q_vectors = numvecs; 1130 1131 /* add 1 vector for link status interrupts */ 1132 numvecs++; 1133 for (i = 0; i < numvecs; i++) 1134 adapter->msix_entries[i].entry = i; 1135 1136 err = pci_enable_msix_range(adapter->pdev, 1137 adapter->msix_entries, 1138 numvecs, 1139 numvecs); 1140 if (err > 0) 1141 return; 1142 1143 igb_reset_interrupt_capability(adapter); 1144 1145 /* If we can't do MSI-X, try MSI */ 1146 msi_only: 1147 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1148 #ifdef CONFIG_PCI_IOV 1149 /* disable SR-IOV for non MSI-X configurations */ 1150 if (adapter->vf_data) { 1151 struct e1000_hw *hw = &adapter->hw; 1152 /* disable iov and allow time for transactions to clear */ 1153 pci_disable_sriov(adapter->pdev); 1154 msleep(500); 1155 1156 kfree(adapter->vf_data); 1157 adapter->vf_data = NULL; 1158 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1159 wrfl(); 1160 msleep(100); 1161 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1162 } 1163 #endif 1164 adapter->vfs_allocated_count = 0; 1165 adapter->rss_queues = 1; 1166 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1167 adapter->num_rx_queues = 1; 1168 adapter->num_tx_queues = 1; 1169 adapter->num_q_vectors = 1; 1170 if (!pci_enable_msi(adapter->pdev)) 1171 adapter->flags |= IGB_FLAG_HAS_MSI; 1172 } 1173 1174 static void igb_add_ring(struct igb_ring *ring, 1175 struct igb_ring_container *head) 1176 { 1177 head->ring = ring; 1178 head->count++; 1179 } 1180 1181 /** 1182 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1183 * @adapter: board private structure to initialize 1184 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1185 * @v_idx: index of vector in adapter struct 1186 * @txr_count: total number of Tx rings to allocate 1187 * @txr_idx: index of first Tx ring to allocate 1188 * @rxr_count: total number of Rx rings to allocate 1189 * @rxr_idx: index of first Rx ring to allocate 1190 * 1191 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1192 **/ 1193 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1194 int v_count, int v_idx, 1195 int txr_count, int txr_idx, 1196 int rxr_count, int rxr_idx) 1197 { 1198 struct igb_q_vector *q_vector; 1199 struct igb_ring *ring; 1200 int ring_count, size; 1201 1202 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1203 if (txr_count > 1 || rxr_count > 1) 1204 return -ENOMEM; 1205 1206 ring_count = txr_count + rxr_count; 1207 size = sizeof(struct igb_q_vector) + 1208 (sizeof(struct igb_ring) * ring_count); 1209 1210 /* allocate q_vector and rings */ 1211 q_vector = adapter->q_vector[v_idx]; 1212 if (!q_vector) { 1213 q_vector = kzalloc(size, GFP_KERNEL); 1214 } else if (size > ksize(q_vector)) { 1215 kfree_rcu(q_vector, rcu); 1216 q_vector = kzalloc(size, GFP_KERNEL); 1217 } else { 1218 memset(q_vector, 0, size); 1219 } 1220 if (!q_vector) 1221 return -ENOMEM; 1222 1223 /* initialize NAPI */ 1224 netif_napi_add(adapter->netdev, &q_vector->napi, 1225 igb_poll, 64); 1226 1227 /* tie q_vector and adapter together */ 1228 adapter->q_vector[v_idx] = q_vector; 1229 q_vector->adapter = adapter; 1230 1231 /* initialize work limits */ 1232 q_vector->tx.work_limit = adapter->tx_work_limit; 1233 1234 /* initialize ITR configuration */ 1235 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1236 q_vector->itr_val = IGB_START_ITR; 1237 1238 /* initialize pointer to rings */ 1239 ring = q_vector->ring; 1240 1241 /* intialize ITR */ 1242 if (rxr_count) { 1243 /* rx or rx/tx vector */ 1244 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1245 q_vector->itr_val = adapter->rx_itr_setting; 1246 } else { 1247 /* tx only vector */ 1248 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1249 q_vector->itr_val = adapter->tx_itr_setting; 1250 } 1251 1252 if (txr_count) { 1253 /* assign generic ring traits */ 1254 ring->dev = &adapter->pdev->dev; 1255 ring->netdev = adapter->netdev; 1256 1257 /* configure backlink on ring */ 1258 ring->q_vector = q_vector; 1259 1260 /* update q_vector Tx values */ 1261 igb_add_ring(ring, &q_vector->tx); 1262 1263 /* For 82575, context index must be unique per ring. */ 1264 if (adapter->hw.mac.type == e1000_82575) 1265 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1266 1267 /* apply Tx specific ring traits */ 1268 ring->count = adapter->tx_ring_count; 1269 ring->queue_index = txr_idx; 1270 1271 u64_stats_init(&ring->tx_syncp); 1272 u64_stats_init(&ring->tx_syncp2); 1273 1274 /* assign ring to adapter */ 1275 adapter->tx_ring[txr_idx] = ring; 1276 1277 /* push pointer to next ring */ 1278 ring++; 1279 } 1280 1281 if (rxr_count) { 1282 /* assign generic ring traits */ 1283 ring->dev = &adapter->pdev->dev; 1284 ring->netdev = adapter->netdev; 1285 1286 /* configure backlink on ring */ 1287 ring->q_vector = q_vector; 1288 1289 /* update q_vector Rx values */ 1290 igb_add_ring(ring, &q_vector->rx); 1291 1292 /* set flag indicating ring supports SCTP checksum offload */ 1293 if (adapter->hw.mac.type >= e1000_82576) 1294 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1295 1296 /* On i350, i354, i210, and i211, loopback VLAN packets 1297 * have the tag byte-swapped. 1298 */ 1299 if (adapter->hw.mac.type >= e1000_i350) 1300 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1301 1302 /* apply Rx specific ring traits */ 1303 ring->count = adapter->rx_ring_count; 1304 ring->queue_index = rxr_idx; 1305 1306 u64_stats_init(&ring->rx_syncp); 1307 1308 /* assign ring to adapter */ 1309 adapter->rx_ring[rxr_idx] = ring; 1310 } 1311 1312 return 0; 1313 } 1314 1315 1316 /** 1317 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1318 * @adapter: board private structure to initialize 1319 * 1320 * We allocate one q_vector per queue interrupt. If allocation fails we 1321 * return -ENOMEM. 1322 **/ 1323 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1324 { 1325 int q_vectors = adapter->num_q_vectors; 1326 int rxr_remaining = adapter->num_rx_queues; 1327 int txr_remaining = adapter->num_tx_queues; 1328 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1329 int err; 1330 1331 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1332 for (; rxr_remaining; v_idx++) { 1333 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1334 0, 0, 1, rxr_idx); 1335 1336 if (err) 1337 goto err_out; 1338 1339 /* update counts and index */ 1340 rxr_remaining--; 1341 rxr_idx++; 1342 } 1343 } 1344 1345 for (; v_idx < q_vectors; v_idx++) { 1346 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1347 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1348 1349 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1350 tqpv, txr_idx, rqpv, rxr_idx); 1351 1352 if (err) 1353 goto err_out; 1354 1355 /* update counts and index */ 1356 rxr_remaining -= rqpv; 1357 txr_remaining -= tqpv; 1358 rxr_idx++; 1359 txr_idx++; 1360 } 1361 1362 return 0; 1363 1364 err_out: 1365 adapter->num_tx_queues = 0; 1366 adapter->num_rx_queues = 0; 1367 adapter->num_q_vectors = 0; 1368 1369 while (v_idx--) 1370 igb_free_q_vector(adapter, v_idx); 1371 1372 return -ENOMEM; 1373 } 1374 1375 /** 1376 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1377 * @adapter: board private structure to initialize 1378 * @msix: boolean value of MSIX capability 1379 * 1380 * This function initializes the interrupts and allocates all of the queues. 1381 **/ 1382 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1383 { 1384 struct pci_dev *pdev = adapter->pdev; 1385 int err; 1386 1387 igb_set_interrupt_capability(adapter, msix); 1388 1389 err = igb_alloc_q_vectors(adapter); 1390 if (err) { 1391 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1392 goto err_alloc_q_vectors; 1393 } 1394 1395 igb_cache_ring_register(adapter); 1396 1397 return 0; 1398 1399 err_alloc_q_vectors: 1400 igb_reset_interrupt_capability(adapter); 1401 return err; 1402 } 1403 1404 /** 1405 * igb_request_irq - initialize interrupts 1406 * @adapter: board private structure to initialize 1407 * 1408 * Attempts to configure interrupts using the best available 1409 * capabilities of the hardware and kernel. 1410 **/ 1411 static int igb_request_irq(struct igb_adapter *adapter) 1412 { 1413 struct net_device *netdev = adapter->netdev; 1414 struct pci_dev *pdev = adapter->pdev; 1415 int err = 0; 1416 1417 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1418 err = igb_request_msix(adapter); 1419 if (!err) 1420 goto request_done; 1421 /* fall back to MSI */ 1422 igb_free_all_tx_resources(adapter); 1423 igb_free_all_rx_resources(adapter); 1424 1425 igb_clear_interrupt_scheme(adapter); 1426 err = igb_init_interrupt_scheme(adapter, false); 1427 if (err) 1428 goto request_done; 1429 1430 igb_setup_all_tx_resources(adapter); 1431 igb_setup_all_rx_resources(adapter); 1432 igb_configure(adapter); 1433 } 1434 1435 igb_assign_vector(adapter->q_vector[0], 0); 1436 1437 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1438 err = request_irq(pdev->irq, igb_intr_msi, 0, 1439 netdev->name, adapter); 1440 if (!err) 1441 goto request_done; 1442 1443 /* fall back to legacy interrupts */ 1444 igb_reset_interrupt_capability(adapter); 1445 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1446 } 1447 1448 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1449 netdev->name, adapter); 1450 1451 if (err) 1452 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1453 err); 1454 1455 request_done: 1456 return err; 1457 } 1458 1459 static void igb_free_irq(struct igb_adapter *adapter) 1460 { 1461 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1462 int vector = 0, i; 1463 1464 free_irq(adapter->msix_entries[vector++].vector, adapter); 1465 1466 for (i = 0; i < adapter->num_q_vectors; i++) 1467 free_irq(adapter->msix_entries[vector++].vector, 1468 adapter->q_vector[i]); 1469 } else { 1470 free_irq(adapter->pdev->irq, adapter); 1471 } 1472 } 1473 1474 /** 1475 * igb_irq_disable - Mask off interrupt generation on the NIC 1476 * @adapter: board private structure 1477 **/ 1478 static void igb_irq_disable(struct igb_adapter *adapter) 1479 { 1480 struct e1000_hw *hw = &adapter->hw; 1481 1482 /* we need to be careful when disabling interrupts. The VFs are also 1483 * mapped into these registers and so clearing the bits can cause 1484 * issues on the VF drivers so we only need to clear what we set 1485 */ 1486 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1487 u32 regval = rd32(E1000_EIAM); 1488 1489 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1490 wr32(E1000_EIMC, adapter->eims_enable_mask); 1491 regval = rd32(E1000_EIAC); 1492 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1493 } 1494 1495 wr32(E1000_IAM, 0); 1496 wr32(E1000_IMC, ~0); 1497 wrfl(); 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 int i; 1500 1501 for (i = 0; i < adapter->num_q_vectors; i++) 1502 synchronize_irq(adapter->msix_entries[i].vector); 1503 } else { 1504 synchronize_irq(adapter->pdev->irq); 1505 } 1506 } 1507 1508 /** 1509 * igb_irq_enable - Enable default interrupt generation settings 1510 * @adapter: board private structure 1511 **/ 1512 static void igb_irq_enable(struct igb_adapter *adapter) 1513 { 1514 struct e1000_hw *hw = &adapter->hw; 1515 1516 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1517 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1518 u32 regval = rd32(E1000_EIAC); 1519 1520 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1521 regval = rd32(E1000_EIAM); 1522 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1523 wr32(E1000_EIMS, adapter->eims_enable_mask); 1524 if (adapter->vfs_allocated_count) { 1525 wr32(E1000_MBVFIMR, 0xFF); 1526 ims |= E1000_IMS_VMMB; 1527 } 1528 wr32(E1000_IMS, ims); 1529 } else { 1530 wr32(E1000_IMS, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 wr32(E1000_IAM, IMS_ENABLE_MASK | 1533 E1000_IMS_DRSTA); 1534 } 1535 } 1536 1537 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1538 { 1539 struct e1000_hw *hw = &adapter->hw; 1540 u16 pf_id = adapter->vfs_allocated_count; 1541 u16 vid = adapter->hw.mng_cookie.vlan_id; 1542 u16 old_vid = adapter->mng_vlan_id; 1543 1544 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1545 /* add VID to filter table */ 1546 igb_vfta_set(hw, vid, pf_id, true, true); 1547 adapter->mng_vlan_id = vid; 1548 } else { 1549 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1550 } 1551 1552 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1553 (vid != old_vid) && 1554 !test_bit(old_vid, adapter->active_vlans)) { 1555 /* remove VID from filter table */ 1556 igb_vfta_set(hw, vid, pf_id, false, true); 1557 } 1558 } 1559 1560 /** 1561 * igb_release_hw_control - release control of the h/w to f/w 1562 * @adapter: address of board private structure 1563 * 1564 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1565 * For ASF and Pass Through versions of f/w this means that the 1566 * driver is no longer loaded. 1567 **/ 1568 static void igb_release_hw_control(struct igb_adapter *adapter) 1569 { 1570 struct e1000_hw *hw = &adapter->hw; 1571 u32 ctrl_ext; 1572 1573 /* Let firmware take over control of h/w */ 1574 ctrl_ext = rd32(E1000_CTRL_EXT); 1575 wr32(E1000_CTRL_EXT, 1576 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1577 } 1578 1579 /** 1580 * igb_get_hw_control - get control of the h/w from f/w 1581 * @adapter: address of board private structure 1582 * 1583 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1584 * For ASF and Pass Through versions of f/w this means that 1585 * the driver is loaded. 1586 **/ 1587 static void igb_get_hw_control(struct igb_adapter *adapter) 1588 { 1589 struct e1000_hw *hw = &adapter->hw; 1590 u32 ctrl_ext; 1591 1592 /* Let firmware know the driver has taken over */ 1593 ctrl_ext = rd32(E1000_CTRL_EXT); 1594 wr32(E1000_CTRL_EXT, 1595 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1596 } 1597 1598 /** 1599 * igb_configure - configure the hardware for RX and TX 1600 * @adapter: private board structure 1601 **/ 1602 static void igb_configure(struct igb_adapter *adapter) 1603 { 1604 struct net_device *netdev = adapter->netdev; 1605 int i; 1606 1607 igb_get_hw_control(adapter); 1608 igb_set_rx_mode(netdev); 1609 1610 igb_restore_vlan(adapter); 1611 1612 igb_setup_tctl(adapter); 1613 igb_setup_mrqc(adapter); 1614 igb_setup_rctl(adapter); 1615 1616 igb_nfc_filter_restore(adapter); 1617 igb_configure_tx(adapter); 1618 igb_configure_rx(adapter); 1619 1620 igb_rx_fifo_flush_82575(&adapter->hw); 1621 1622 /* call igb_desc_unused which always leaves 1623 * at least 1 descriptor unused to make sure 1624 * next_to_use != next_to_clean 1625 */ 1626 for (i = 0; i < adapter->num_rx_queues; i++) { 1627 struct igb_ring *ring = adapter->rx_ring[i]; 1628 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1629 } 1630 } 1631 1632 /** 1633 * igb_power_up_link - Power up the phy/serdes link 1634 * @adapter: address of board private structure 1635 **/ 1636 void igb_power_up_link(struct igb_adapter *adapter) 1637 { 1638 igb_reset_phy(&adapter->hw); 1639 1640 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1641 igb_power_up_phy_copper(&adapter->hw); 1642 else 1643 igb_power_up_serdes_link_82575(&adapter->hw); 1644 1645 igb_setup_link(&adapter->hw); 1646 } 1647 1648 /** 1649 * igb_power_down_link - Power down the phy/serdes link 1650 * @adapter: address of board private structure 1651 */ 1652 static void igb_power_down_link(struct igb_adapter *adapter) 1653 { 1654 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1655 igb_power_down_phy_copper_82575(&adapter->hw); 1656 else 1657 igb_shutdown_serdes_link_82575(&adapter->hw); 1658 } 1659 1660 /** 1661 * Detect and switch function for Media Auto Sense 1662 * @adapter: address of the board private structure 1663 **/ 1664 static void igb_check_swap_media(struct igb_adapter *adapter) 1665 { 1666 struct e1000_hw *hw = &adapter->hw; 1667 u32 ctrl_ext, connsw; 1668 bool swap_now = false; 1669 1670 ctrl_ext = rd32(E1000_CTRL_EXT); 1671 connsw = rd32(E1000_CONNSW); 1672 1673 /* need to live swap if current media is copper and we have fiber/serdes 1674 * to go to. 1675 */ 1676 1677 if ((hw->phy.media_type == e1000_media_type_copper) && 1678 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1679 swap_now = true; 1680 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1681 /* copper signal takes time to appear */ 1682 if (adapter->copper_tries < 4) { 1683 adapter->copper_tries++; 1684 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1685 wr32(E1000_CONNSW, connsw); 1686 return; 1687 } else { 1688 adapter->copper_tries = 0; 1689 if ((connsw & E1000_CONNSW_PHYSD) && 1690 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1691 swap_now = true; 1692 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1693 wr32(E1000_CONNSW, connsw); 1694 } 1695 } 1696 } 1697 1698 if (!swap_now) 1699 return; 1700 1701 switch (hw->phy.media_type) { 1702 case e1000_media_type_copper: 1703 netdev_info(adapter->netdev, 1704 "MAS: changing media to fiber/serdes\n"); 1705 ctrl_ext |= 1706 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1707 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1708 adapter->copper_tries = 0; 1709 break; 1710 case e1000_media_type_internal_serdes: 1711 case e1000_media_type_fiber: 1712 netdev_info(adapter->netdev, 1713 "MAS: changing media to copper\n"); 1714 ctrl_ext &= 1715 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1716 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1717 break; 1718 default: 1719 /* shouldn't get here during regular operation */ 1720 netdev_err(adapter->netdev, 1721 "AMS: Invalid media type found, returning\n"); 1722 break; 1723 } 1724 wr32(E1000_CTRL_EXT, ctrl_ext); 1725 } 1726 1727 /** 1728 * igb_up - Open the interface and prepare it to handle traffic 1729 * @adapter: board private structure 1730 **/ 1731 int igb_up(struct igb_adapter *adapter) 1732 { 1733 struct e1000_hw *hw = &adapter->hw; 1734 int i; 1735 1736 /* hardware has been reset, we need to reload some things */ 1737 igb_configure(adapter); 1738 1739 clear_bit(__IGB_DOWN, &adapter->state); 1740 1741 for (i = 0; i < adapter->num_q_vectors; i++) 1742 napi_enable(&(adapter->q_vector[i]->napi)); 1743 1744 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1745 igb_configure_msix(adapter); 1746 else 1747 igb_assign_vector(adapter->q_vector[0], 0); 1748 1749 /* Clear any pending interrupts. */ 1750 rd32(E1000_ICR); 1751 igb_irq_enable(adapter); 1752 1753 /* notify VFs that reset has been completed */ 1754 if (adapter->vfs_allocated_count) { 1755 u32 reg_data = rd32(E1000_CTRL_EXT); 1756 1757 reg_data |= E1000_CTRL_EXT_PFRSTD; 1758 wr32(E1000_CTRL_EXT, reg_data); 1759 } 1760 1761 netif_tx_start_all_queues(adapter->netdev); 1762 1763 /* start the watchdog. */ 1764 hw->mac.get_link_status = 1; 1765 schedule_work(&adapter->watchdog_task); 1766 1767 if ((adapter->flags & IGB_FLAG_EEE) && 1768 (!hw->dev_spec._82575.eee_disable)) 1769 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1770 1771 return 0; 1772 } 1773 1774 void igb_down(struct igb_adapter *adapter) 1775 { 1776 struct net_device *netdev = adapter->netdev; 1777 struct e1000_hw *hw = &adapter->hw; 1778 u32 tctl, rctl; 1779 int i; 1780 1781 /* signal that we're down so the interrupt handler does not 1782 * reschedule our watchdog timer 1783 */ 1784 set_bit(__IGB_DOWN, &adapter->state); 1785 1786 /* disable receives in the hardware */ 1787 rctl = rd32(E1000_RCTL); 1788 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1789 /* flush and sleep below */ 1790 1791 netif_carrier_off(netdev); 1792 netif_tx_stop_all_queues(netdev); 1793 1794 /* disable transmits in the hardware */ 1795 tctl = rd32(E1000_TCTL); 1796 tctl &= ~E1000_TCTL_EN; 1797 wr32(E1000_TCTL, tctl); 1798 /* flush both disables and wait for them to finish */ 1799 wrfl(); 1800 usleep_range(10000, 11000); 1801 1802 igb_irq_disable(adapter); 1803 1804 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1805 1806 for (i = 0; i < adapter->num_q_vectors; i++) { 1807 if (adapter->q_vector[i]) { 1808 napi_synchronize(&adapter->q_vector[i]->napi); 1809 napi_disable(&adapter->q_vector[i]->napi); 1810 } 1811 } 1812 1813 del_timer_sync(&adapter->watchdog_timer); 1814 del_timer_sync(&adapter->phy_info_timer); 1815 1816 /* record the stats before reset*/ 1817 spin_lock(&adapter->stats64_lock); 1818 igb_update_stats(adapter, &adapter->stats64); 1819 spin_unlock(&adapter->stats64_lock); 1820 1821 adapter->link_speed = 0; 1822 adapter->link_duplex = 0; 1823 1824 if (!pci_channel_offline(adapter->pdev)) 1825 igb_reset(adapter); 1826 1827 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1828 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1829 1830 igb_clean_all_tx_rings(adapter); 1831 igb_clean_all_rx_rings(adapter); 1832 #ifdef CONFIG_IGB_DCA 1833 1834 /* since we reset the hardware DCA settings were cleared */ 1835 igb_setup_dca(adapter); 1836 #endif 1837 } 1838 1839 void igb_reinit_locked(struct igb_adapter *adapter) 1840 { 1841 WARN_ON(in_interrupt()); 1842 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1843 usleep_range(1000, 2000); 1844 igb_down(adapter); 1845 igb_up(adapter); 1846 clear_bit(__IGB_RESETTING, &adapter->state); 1847 } 1848 1849 /** igb_enable_mas - Media Autosense re-enable after swap 1850 * 1851 * @adapter: adapter struct 1852 **/ 1853 static void igb_enable_mas(struct igb_adapter *adapter) 1854 { 1855 struct e1000_hw *hw = &adapter->hw; 1856 u32 connsw = rd32(E1000_CONNSW); 1857 1858 /* configure for SerDes media detect */ 1859 if ((hw->phy.media_type == e1000_media_type_copper) && 1860 (!(connsw & E1000_CONNSW_SERDESD))) { 1861 connsw |= E1000_CONNSW_ENRGSRC; 1862 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1863 wr32(E1000_CONNSW, connsw); 1864 wrfl(); 1865 } 1866 } 1867 1868 void igb_reset(struct igb_adapter *adapter) 1869 { 1870 struct pci_dev *pdev = adapter->pdev; 1871 struct e1000_hw *hw = &adapter->hw; 1872 struct e1000_mac_info *mac = &hw->mac; 1873 struct e1000_fc_info *fc = &hw->fc; 1874 u32 pba, hwm; 1875 1876 /* Repartition Pba for greater than 9k mtu 1877 * To take effect CTRL.RST is required. 1878 */ 1879 switch (mac->type) { 1880 case e1000_i350: 1881 case e1000_i354: 1882 case e1000_82580: 1883 pba = rd32(E1000_RXPBS); 1884 pba = igb_rxpbs_adjust_82580(pba); 1885 break; 1886 case e1000_82576: 1887 pba = rd32(E1000_RXPBS); 1888 pba &= E1000_RXPBS_SIZE_MASK_82576; 1889 break; 1890 case e1000_82575: 1891 case e1000_i210: 1892 case e1000_i211: 1893 default: 1894 pba = E1000_PBA_34K; 1895 break; 1896 } 1897 1898 if (mac->type == e1000_82575) { 1899 u32 min_rx_space, min_tx_space, needed_tx_space; 1900 1901 /* write Rx PBA so that hardware can report correct Tx PBA */ 1902 wr32(E1000_PBA, pba); 1903 1904 /* To maintain wire speed transmits, the Tx FIFO should be 1905 * large enough to accommodate two full transmit packets, 1906 * rounded up to the next 1KB and expressed in KB. Likewise, 1907 * the Rx FIFO should be large enough to accommodate at least 1908 * one full receive packet and is similarly rounded up and 1909 * expressed in KB. 1910 */ 1911 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1912 1913 /* The Tx FIFO also stores 16 bytes of information about the Tx 1914 * but don't include Ethernet FCS because hardware appends it. 1915 * We only need to round down to the nearest 512 byte block 1916 * count since the value we care about is 2 frames, not 1. 1917 */ 1918 min_tx_space = adapter->max_frame_size; 1919 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1920 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1921 1922 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1923 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1924 1925 /* If current Tx allocation is less than the min Tx FIFO size, 1926 * and the min Tx FIFO size is less than the current Rx FIFO 1927 * allocation, take space away from current Rx allocation. 1928 */ 1929 if (needed_tx_space < pba) { 1930 pba -= needed_tx_space; 1931 1932 /* if short on Rx space, Rx wins and must trump Tx 1933 * adjustment 1934 */ 1935 if (pba < min_rx_space) 1936 pba = min_rx_space; 1937 } 1938 1939 /* adjust PBA for jumbo frames */ 1940 wr32(E1000_PBA, pba); 1941 } 1942 1943 /* flow control settings 1944 * The high water mark must be low enough to fit one full frame 1945 * after transmitting the pause frame. As such we must have enough 1946 * space to allow for us to complete our current transmit and then 1947 * receive the frame that is in progress from the link partner. 1948 * Set it to: 1949 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1950 */ 1951 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1952 1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1954 fc->low_water = fc->high_water - 16; 1955 fc->pause_time = 0xFFFF; 1956 fc->send_xon = 1; 1957 fc->current_mode = fc->requested_mode; 1958 1959 /* disable receive for all VFs and wait one second */ 1960 if (adapter->vfs_allocated_count) { 1961 int i; 1962 1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1965 1966 /* ping all the active vfs to let them know we are going down */ 1967 igb_ping_all_vfs(adapter); 1968 1969 /* disable transmits and receives */ 1970 wr32(E1000_VFRE, 0); 1971 wr32(E1000_VFTE, 0); 1972 } 1973 1974 /* Allow time for pending master requests to run */ 1975 hw->mac.ops.reset_hw(hw); 1976 wr32(E1000_WUC, 0); 1977 1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1979 /* need to resetup here after media swap */ 1980 adapter->ei.get_invariants(hw); 1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1982 } 1983 if ((mac->type == e1000_82575) && 1984 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1985 igb_enable_mas(adapter); 1986 } 1987 if (hw->mac.ops.init_hw(hw)) 1988 dev_err(&pdev->dev, "Hardware Error\n"); 1989 1990 /* Flow control settings reset on hardware reset, so guarantee flow 1991 * control is off when forcing speed. 1992 */ 1993 if (!hw->mac.autoneg) 1994 igb_force_mac_fc(hw); 1995 1996 igb_init_dmac(adapter, pba); 1997 #ifdef CONFIG_IGB_HWMON 1998 /* Re-initialize the thermal sensor on i350 devices. */ 1999 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2000 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2001 /* If present, re-initialize the external thermal sensor 2002 * interface. 2003 */ 2004 if (adapter->ets) 2005 mac->ops.init_thermal_sensor_thresh(hw); 2006 } 2007 } 2008 #endif 2009 /* Re-establish EEE setting */ 2010 if (hw->phy.media_type == e1000_media_type_copper) { 2011 switch (mac->type) { 2012 case e1000_i350: 2013 case e1000_i210: 2014 case e1000_i211: 2015 igb_set_eee_i350(hw, true, true); 2016 break; 2017 case e1000_i354: 2018 igb_set_eee_i354(hw, true, true); 2019 break; 2020 default: 2021 break; 2022 } 2023 } 2024 if (!netif_running(adapter->netdev)) 2025 igb_power_down_link(adapter); 2026 2027 igb_update_mng_vlan(adapter); 2028 2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2031 2032 /* Re-enable PTP, where applicable. */ 2033 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2034 igb_ptp_reset(adapter); 2035 2036 igb_get_phy_info(hw); 2037 } 2038 2039 static netdev_features_t igb_fix_features(struct net_device *netdev, 2040 netdev_features_t features) 2041 { 2042 /* Since there is no support for separate Rx/Tx vlan accel 2043 * enable/disable make sure Tx flag is always in same state as Rx. 2044 */ 2045 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2046 features |= NETIF_F_HW_VLAN_CTAG_TX; 2047 else 2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2049 2050 return features; 2051 } 2052 2053 static int igb_set_features(struct net_device *netdev, 2054 netdev_features_t features) 2055 { 2056 netdev_features_t changed = netdev->features ^ features; 2057 struct igb_adapter *adapter = netdev_priv(netdev); 2058 2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2060 igb_vlan_mode(netdev, features); 2061 2062 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2063 return 0; 2064 2065 if (!(features & NETIF_F_NTUPLE)) { 2066 struct hlist_node *node2; 2067 struct igb_nfc_filter *rule; 2068 2069 spin_lock(&adapter->nfc_lock); 2070 hlist_for_each_entry_safe(rule, node2, 2071 &adapter->nfc_filter_list, nfc_node) { 2072 igb_erase_filter(adapter, rule); 2073 hlist_del(&rule->nfc_node); 2074 kfree(rule); 2075 } 2076 spin_unlock(&adapter->nfc_lock); 2077 adapter->nfc_filter_count = 0; 2078 } 2079 2080 netdev->features = features; 2081 2082 if (netif_running(netdev)) 2083 igb_reinit_locked(adapter); 2084 else 2085 igb_reset(adapter); 2086 2087 return 0; 2088 } 2089 2090 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2091 struct net_device *dev, 2092 const unsigned char *addr, u16 vid, 2093 u16 flags) 2094 { 2095 /* guarantee we can provide a unique filter for the unicast address */ 2096 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2097 struct igb_adapter *adapter = netdev_priv(dev); 2098 struct e1000_hw *hw = &adapter->hw; 2099 int vfn = adapter->vfs_allocated_count; 2100 int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 2101 2102 if (netdev_uc_count(dev) >= rar_entries) 2103 return -ENOMEM; 2104 } 2105 2106 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2107 } 2108 2109 #define IGB_MAX_MAC_HDR_LEN 127 2110 #define IGB_MAX_NETWORK_HDR_LEN 511 2111 2112 static netdev_features_t 2113 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2114 netdev_features_t features) 2115 { 2116 unsigned int network_hdr_len, mac_hdr_len; 2117 2118 /* Make certain the headers can be described by a context descriptor */ 2119 mac_hdr_len = skb_network_header(skb) - skb->data; 2120 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2121 return features & ~(NETIF_F_HW_CSUM | 2122 NETIF_F_SCTP_CRC | 2123 NETIF_F_HW_VLAN_CTAG_TX | 2124 NETIF_F_TSO | 2125 NETIF_F_TSO6); 2126 2127 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2128 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2129 return features & ~(NETIF_F_HW_CSUM | 2130 NETIF_F_SCTP_CRC | 2131 NETIF_F_TSO | 2132 NETIF_F_TSO6); 2133 2134 /* We can only support IPV4 TSO in tunnels if we can mangle the 2135 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2136 */ 2137 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2138 features &= ~NETIF_F_TSO; 2139 2140 return features; 2141 } 2142 2143 static const struct net_device_ops igb_netdev_ops = { 2144 .ndo_open = igb_open, 2145 .ndo_stop = igb_close, 2146 .ndo_start_xmit = igb_xmit_frame, 2147 .ndo_get_stats64 = igb_get_stats64, 2148 .ndo_set_rx_mode = igb_set_rx_mode, 2149 .ndo_set_mac_address = igb_set_mac, 2150 .ndo_change_mtu = igb_change_mtu, 2151 .ndo_do_ioctl = igb_ioctl, 2152 .ndo_tx_timeout = igb_tx_timeout, 2153 .ndo_validate_addr = eth_validate_addr, 2154 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2155 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2156 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2157 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2158 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2159 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2160 .ndo_get_vf_config = igb_ndo_get_vf_config, 2161 #ifdef CONFIG_NET_POLL_CONTROLLER 2162 .ndo_poll_controller = igb_netpoll, 2163 #endif 2164 .ndo_fix_features = igb_fix_features, 2165 .ndo_set_features = igb_set_features, 2166 .ndo_fdb_add = igb_ndo_fdb_add, 2167 .ndo_features_check = igb_features_check, 2168 }; 2169 2170 /** 2171 * igb_set_fw_version - Configure version string for ethtool 2172 * @adapter: adapter struct 2173 **/ 2174 void igb_set_fw_version(struct igb_adapter *adapter) 2175 { 2176 struct e1000_hw *hw = &adapter->hw; 2177 struct e1000_fw_version fw; 2178 2179 igb_get_fw_version(hw, &fw); 2180 2181 switch (hw->mac.type) { 2182 case e1000_i210: 2183 case e1000_i211: 2184 if (!(igb_get_flash_presence_i210(hw))) { 2185 snprintf(adapter->fw_version, 2186 sizeof(adapter->fw_version), 2187 "%2d.%2d-%d", 2188 fw.invm_major, fw.invm_minor, 2189 fw.invm_img_type); 2190 break; 2191 } 2192 /* fall through */ 2193 default: 2194 /* if option is rom valid, display its version too */ 2195 if (fw.or_valid) { 2196 snprintf(adapter->fw_version, 2197 sizeof(adapter->fw_version), 2198 "%d.%d, 0x%08x, %d.%d.%d", 2199 fw.eep_major, fw.eep_minor, fw.etrack_id, 2200 fw.or_major, fw.or_build, fw.or_patch); 2201 /* no option rom */ 2202 } else if (fw.etrack_id != 0X0000) { 2203 snprintf(adapter->fw_version, 2204 sizeof(adapter->fw_version), 2205 "%d.%d, 0x%08x", 2206 fw.eep_major, fw.eep_minor, fw.etrack_id); 2207 } else { 2208 snprintf(adapter->fw_version, 2209 sizeof(adapter->fw_version), 2210 "%d.%d.%d", 2211 fw.eep_major, fw.eep_minor, fw.eep_build); 2212 } 2213 break; 2214 } 2215 } 2216 2217 /** 2218 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2219 * 2220 * @adapter: adapter struct 2221 **/ 2222 static void igb_init_mas(struct igb_adapter *adapter) 2223 { 2224 struct e1000_hw *hw = &adapter->hw; 2225 u16 eeprom_data; 2226 2227 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2228 switch (hw->bus.func) { 2229 case E1000_FUNC_0: 2230 if (eeprom_data & IGB_MAS_ENABLE_0) { 2231 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2232 netdev_info(adapter->netdev, 2233 "MAS: Enabling Media Autosense for port %d\n", 2234 hw->bus.func); 2235 } 2236 break; 2237 case E1000_FUNC_1: 2238 if (eeprom_data & IGB_MAS_ENABLE_1) { 2239 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2240 netdev_info(adapter->netdev, 2241 "MAS: Enabling Media Autosense for port %d\n", 2242 hw->bus.func); 2243 } 2244 break; 2245 case E1000_FUNC_2: 2246 if (eeprom_data & IGB_MAS_ENABLE_2) { 2247 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2248 netdev_info(adapter->netdev, 2249 "MAS: Enabling Media Autosense for port %d\n", 2250 hw->bus.func); 2251 } 2252 break; 2253 case E1000_FUNC_3: 2254 if (eeprom_data & IGB_MAS_ENABLE_3) { 2255 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2256 netdev_info(adapter->netdev, 2257 "MAS: Enabling Media Autosense for port %d\n", 2258 hw->bus.func); 2259 } 2260 break; 2261 default: 2262 /* Shouldn't get here */ 2263 netdev_err(adapter->netdev, 2264 "MAS: Invalid port configuration, returning\n"); 2265 break; 2266 } 2267 } 2268 2269 /** 2270 * igb_init_i2c - Init I2C interface 2271 * @adapter: pointer to adapter structure 2272 **/ 2273 static s32 igb_init_i2c(struct igb_adapter *adapter) 2274 { 2275 s32 status = 0; 2276 2277 /* I2C interface supported on i350 devices */ 2278 if (adapter->hw.mac.type != e1000_i350) 2279 return 0; 2280 2281 /* Initialize the i2c bus which is controlled by the registers. 2282 * This bus will use the i2c_algo_bit structue that implements 2283 * the protocol through toggling of the 4 bits in the register. 2284 */ 2285 adapter->i2c_adap.owner = THIS_MODULE; 2286 adapter->i2c_algo = igb_i2c_algo; 2287 adapter->i2c_algo.data = adapter; 2288 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2289 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2290 strlcpy(adapter->i2c_adap.name, "igb BB", 2291 sizeof(adapter->i2c_adap.name)); 2292 status = i2c_bit_add_bus(&adapter->i2c_adap); 2293 return status; 2294 } 2295 2296 /** 2297 * igb_probe - Device Initialization Routine 2298 * @pdev: PCI device information struct 2299 * @ent: entry in igb_pci_tbl 2300 * 2301 * Returns 0 on success, negative on failure 2302 * 2303 * igb_probe initializes an adapter identified by a pci_dev structure. 2304 * The OS initialization, configuring of the adapter private structure, 2305 * and a hardware reset occur. 2306 **/ 2307 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2308 { 2309 struct net_device *netdev; 2310 struct igb_adapter *adapter; 2311 struct e1000_hw *hw; 2312 u16 eeprom_data = 0; 2313 s32 ret_val; 2314 static int global_quad_port_a; /* global quad port a indication */ 2315 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2316 int err, pci_using_dac; 2317 u8 part_str[E1000_PBANUM_LENGTH]; 2318 2319 /* Catch broken hardware that put the wrong VF device ID in 2320 * the PCIe SR-IOV capability. 2321 */ 2322 if (pdev->is_virtfn) { 2323 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2324 pci_name(pdev), pdev->vendor, pdev->device); 2325 return -EINVAL; 2326 } 2327 2328 err = pci_enable_device_mem(pdev); 2329 if (err) 2330 return err; 2331 2332 pci_using_dac = 0; 2333 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2334 if (!err) { 2335 pci_using_dac = 1; 2336 } else { 2337 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2338 if (err) { 2339 dev_err(&pdev->dev, 2340 "No usable DMA configuration, aborting\n"); 2341 goto err_dma; 2342 } 2343 } 2344 2345 err = pci_request_mem_regions(pdev, igb_driver_name); 2346 if (err) 2347 goto err_pci_reg; 2348 2349 pci_enable_pcie_error_reporting(pdev); 2350 2351 pci_set_master(pdev); 2352 pci_save_state(pdev); 2353 2354 err = -ENOMEM; 2355 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2356 IGB_MAX_TX_QUEUES); 2357 if (!netdev) 2358 goto err_alloc_etherdev; 2359 2360 SET_NETDEV_DEV(netdev, &pdev->dev); 2361 2362 pci_set_drvdata(pdev, netdev); 2363 adapter = netdev_priv(netdev); 2364 adapter->netdev = netdev; 2365 adapter->pdev = pdev; 2366 hw = &adapter->hw; 2367 hw->back = adapter; 2368 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2369 2370 err = -EIO; 2371 adapter->io_addr = pci_iomap(pdev, 0, 0); 2372 if (!adapter->io_addr) 2373 goto err_ioremap; 2374 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2375 hw->hw_addr = adapter->io_addr; 2376 2377 netdev->netdev_ops = &igb_netdev_ops; 2378 igb_set_ethtool_ops(netdev); 2379 netdev->watchdog_timeo = 5 * HZ; 2380 2381 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2382 2383 netdev->mem_start = pci_resource_start(pdev, 0); 2384 netdev->mem_end = pci_resource_end(pdev, 0); 2385 2386 /* PCI config space info */ 2387 hw->vendor_id = pdev->vendor; 2388 hw->device_id = pdev->device; 2389 hw->revision_id = pdev->revision; 2390 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2391 hw->subsystem_device_id = pdev->subsystem_device; 2392 2393 /* Copy the default MAC, PHY and NVM function pointers */ 2394 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2395 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2396 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2397 /* Initialize skew-specific constants */ 2398 err = ei->get_invariants(hw); 2399 if (err) 2400 goto err_sw_init; 2401 2402 /* setup the private structure */ 2403 err = igb_sw_init(adapter); 2404 if (err) 2405 goto err_sw_init; 2406 2407 igb_get_bus_info_pcie(hw); 2408 2409 hw->phy.autoneg_wait_to_complete = false; 2410 2411 /* Copper options */ 2412 if (hw->phy.media_type == e1000_media_type_copper) { 2413 hw->phy.mdix = AUTO_ALL_MODES; 2414 hw->phy.disable_polarity_correction = false; 2415 hw->phy.ms_type = e1000_ms_hw_default; 2416 } 2417 2418 if (igb_check_reset_block(hw)) 2419 dev_info(&pdev->dev, 2420 "PHY reset is blocked due to SOL/IDER session.\n"); 2421 2422 /* features is initialized to 0 in allocation, it might have bits 2423 * set by igb_sw_init so we should use an or instead of an 2424 * assignment. 2425 */ 2426 netdev->features |= NETIF_F_SG | 2427 NETIF_F_TSO | 2428 NETIF_F_TSO6 | 2429 NETIF_F_RXHASH | 2430 NETIF_F_RXCSUM | 2431 NETIF_F_HW_CSUM; 2432 2433 if (hw->mac.type >= e1000_82576) 2434 netdev->features |= NETIF_F_SCTP_CRC; 2435 2436 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2437 NETIF_F_GSO_GRE_CSUM | \ 2438 NETIF_F_GSO_IPXIP4 | \ 2439 NETIF_F_GSO_IPXIP6 | \ 2440 NETIF_F_GSO_UDP_TUNNEL | \ 2441 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2442 2443 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2444 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2445 2446 /* copy netdev features into list of user selectable features */ 2447 netdev->hw_features |= netdev->features | 2448 NETIF_F_HW_VLAN_CTAG_RX | 2449 NETIF_F_HW_VLAN_CTAG_TX | 2450 NETIF_F_RXALL; 2451 2452 if (hw->mac.type >= e1000_i350) 2453 netdev->hw_features |= NETIF_F_NTUPLE; 2454 2455 if (pci_using_dac) 2456 netdev->features |= NETIF_F_HIGHDMA; 2457 2458 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2459 netdev->mpls_features |= NETIF_F_HW_CSUM; 2460 netdev->hw_enc_features |= netdev->vlan_features; 2461 2462 /* set this bit last since it cannot be part of vlan_features */ 2463 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2464 NETIF_F_HW_VLAN_CTAG_RX | 2465 NETIF_F_HW_VLAN_CTAG_TX; 2466 2467 netdev->priv_flags |= IFF_SUPP_NOFCS; 2468 2469 netdev->priv_flags |= IFF_UNICAST_FLT; 2470 2471 /* MTU range: 68 - 9216 */ 2472 netdev->min_mtu = ETH_MIN_MTU; 2473 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2474 2475 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2476 2477 /* before reading the NVM, reset the controller to put the device in a 2478 * known good starting state 2479 */ 2480 hw->mac.ops.reset_hw(hw); 2481 2482 /* make sure the NVM is good , i211/i210 parts can have special NVM 2483 * that doesn't contain a checksum 2484 */ 2485 switch (hw->mac.type) { 2486 case e1000_i210: 2487 case e1000_i211: 2488 if (igb_get_flash_presence_i210(hw)) { 2489 if (hw->nvm.ops.validate(hw) < 0) { 2490 dev_err(&pdev->dev, 2491 "The NVM Checksum Is Not Valid\n"); 2492 err = -EIO; 2493 goto err_eeprom; 2494 } 2495 } 2496 break; 2497 default: 2498 if (hw->nvm.ops.validate(hw) < 0) { 2499 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2500 err = -EIO; 2501 goto err_eeprom; 2502 } 2503 break; 2504 } 2505 2506 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2507 /* copy the MAC address out of the NVM */ 2508 if (hw->mac.ops.read_mac_addr(hw)) 2509 dev_err(&pdev->dev, "NVM Read Error\n"); 2510 } 2511 2512 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2513 2514 if (!is_valid_ether_addr(netdev->dev_addr)) { 2515 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2516 err = -EIO; 2517 goto err_eeprom; 2518 } 2519 2520 /* get firmware version for ethtool -i */ 2521 igb_set_fw_version(adapter); 2522 2523 /* configure RXPBSIZE and TXPBSIZE */ 2524 if (hw->mac.type == e1000_i210) { 2525 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2526 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2527 } 2528 2529 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2530 (unsigned long) adapter); 2531 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2532 (unsigned long) adapter); 2533 2534 INIT_WORK(&adapter->reset_task, igb_reset_task); 2535 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2536 2537 /* Initialize link properties that are user-changeable */ 2538 adapter->fc_autoneg = true; 2539 hw->mac.autoneg = true; 2540 hw->phy.autoneg_advertised = 0x2f; 2541 2542 hw->fc.requested_mode = e1000_fc_default; 2543 hw->fc.current_mode = e1000_fc_default; 2544 2545 igb_validate_mdi_setting(hw); 2546 2547 /* By default, support wake on port A */ 2548 if (hw->bus.func == 0) 2549 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2550 2551 /* Check the NVM for wake support on non-port A ports */ 2552 if (hw->mac.type >= e1000_82580) 2553 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2554 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2555 &eeprom_data); 2556 else if (hw->bus.func == 1) 2557 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2558 2559 if (eeprom_data & IGB_EEPROM_APME) 2560 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2561 2562 /* now that we have the eeprom settings, apply the special cases where 2563 * the eeprom may be wrong or the board simply won't support wake on 2564 * lan on a particular port 2565 */ 2566 switch (pdev->device) { 2567 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2568 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2569 break; 2570 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2571 case E1000_DEV_ID_82576_FIBER: 2572 case E1000_DEV_ID_82576_SERDES: 2573 /* Wake events only supported on port A for dual fiber 2574 * regardless of eeprom setting 2575 */ 2576 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2577 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2578 break; 2579 case E1000_DEV_ID_82576_QUAD_COPPER: 2580 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2581 /* if quad port adapter, disable WoL on all but port A */ 2582 if (global_quad_port_a != 0) 2583 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2584 else 2585 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2586 /* Reset for multiple quad port adapters */ 2587 if (++global_quad_port_a == 4) 2588 global_quad_port_a = 0; 2589 break; 2590 default: 2591 /* If the device can't wake, don't set software support */ 2592 if (!device_can_wakeup(&adapter->pdev->dev)) 2593 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2594 } 2595 2596 /* initialize the wol settings based on the eeprom settings */ 2597 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2598 adapter->wol |= E1000_WUFC_MAG; 2599 2600 /* Some vendors want WoL disabled by default, but still supported */ 2601 if ((hw->mac.type == e1000_i350) && 2602 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2603 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2604 adapter->wol = 0; 2605 } 2606 2607 /* Some vendors want the ability to Use the EEPROM setting as 2608 * enable/disable only, and not for capability 2609 */ 2610 if (((hw->mac.type == e1000_i350) || 2611 (hw->mac.type == e1000_i354)) && 2612 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2613 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2614 adapter->wol = 0; 2615 } 2616 if (hw->mac.type == e1000_i350) { 2617 if (((pdev->subsystem_device == 0x5001) || 2618 (pdev->subsystem_device == 0x5002)) && 2619 (hw->bus.func == 0)) { 2620 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2621 adapter->wol = 0; 2622 } 2623 if (pdev->subsystem_device == 0x1F52) 2624 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2625 } 2626 2627 device_set_wakeup_enable(&adapter->pdev->dev, 2628 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2629 2630 /* reset the hardware with the new settings */ 2631 igb_reset(adapter); 2632 2633 /* Init the I2C interface */ 2634 err = igb_init_i2c(adapter); 2635 if (err) { 2636 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2637 goto err_eeprom; 2638 } 2639 2640 /* let the f/w know that the h/w is now under the control of the 2641 * driver. 2642 */ 2643 igb_get_hw_control(adapter); 2644 2645 strcpy(netdev->name, "eth%d"); 2646 err = register_netdev(netdev); 2647 if (err) 2648 goto err_register; 2649 2650 /* carrier off reporting is important to ethtool even BEFORE open */ 2651 netif_carrier_off(netdev); 2652 2653 #ifdef CONFIG_IGB_DCA 2654 if (dca_add_requester(&pdev->dev) == 0) { 2655 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2656 dev_info(&pdev->dev, "DCA enabled\n"); 2657 igb_setup_dca(adapter); 2658 } 2659 2660 #endif 2661 #ifdef CONFIG_IGB_HWMON 2662 /* Initialize the thermal sensor on i350 devices. */ 2663 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2664 u16 ets_word; 2665 2666 /* Read the NVM to determine if this i350 device supports an 2667 * external thermal sensor. 2668 */ 2669 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2670 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2671 adapter->ets = true; 2672 else 2673 adapter->ets = false; 2674 if (igb_sysfs_init(adapter)) 2675 dev_err(&pdev->dev, 2676 "failed to allocate sysfs resources\n"); 2677 } else { 2678 adapter->ets = false; 2679 } 2680 #endif 2681 /* Check if Media Autosense is enabled */ 2682 adapter->ei = *ei; 2683 if (hw->dev_spec._82575.mas_capable) 2684 igb_init_mas(adapter); 2685 2686 /* do hw tstamp init after resetting */ 2687 igb_ptp_init(adapter); 2688 2689 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2690 /* print bus type/speed/width info, not applicable to i354 */ 2691 if (hw->mac.type != e1000_i354) { 2692 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2693 netdev->name, 2694 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2695 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2696 "unknown"), 2697 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2698 "Width x4" : 2699 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2700 "Width x2" : 2701 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2702 "Width x1" : "unknown"), netdev->dev_addr); 2703 } 2704 2705 if ((hw->mac.type >= e1000_i210 || 2706 igb_get_flash_presence_i210(hw))) { 2707 ret_val = igb_read_part_string(hw, part_str, 2708 E1000_PBANUM_LENGTH); 2709 } else { 2710 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2711 } 2712 2713 if (ret_val) 2714 strcpy(part_str, "Unknown"); 2715 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2716 dev_info(&pdev->dev, 2717 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2718 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2719 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2720 adapter->num_rx_queues, adapter->num_tx_queues); 2721 if (hw->phy.media_type == e1000_media_type_copper) { 2722 switch (hw->mac.type) { 2723 case e1000_i350: 2724 case e1000_i210: 2725 case e1000_i211: 2726 /* Enable EEE for internal copper PHY devices */ 2727 err = igb_set_eee_i350(hw, true, true); 2728 if ((!err) && 2729 (!hw->dev_spec._82575.eee_disable)) { 2730 adapter->eee_advert = 2731 MDIO_EEE_100TX | MDIO_EEE_1000T; 2732 adapter->flags |= IGB_FLAG_EEE; 2733 } 2734 break; 2735 case e1000_i354: 2736 if ((rd32(E1000_CTRL_EXT) & 2737 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2738 err = igb_set_eee_i354(hw, true, true); 2739 if ((!err) && 2740 (!hw->dev_spec._82575.eee_disable)) { 2741 adapter->eee_advert = 2742 MDIO_EEE_100TX | MDIO_EEE_1000T; 2743 adapter->flags |= IGB_FLAG_EEE; 2744 } 2745 } 2746 break; 2747 default: 2748 break; 2749 } 2750 } 2751 pm_runtime_put_noidle(&pdev->dev); 2752 return 0; 2753 2754 err_register: 2755 igb_release_hw_control(adapter); 2756 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2757 err_eeprom: 2758 if (!igb_check_reset_block(hw)) 2759 igb_reset_phy(hw); 2760 2761 if (hw->flash_address) 2762 iounmap(hw->flash_address); 2763 err_sw_init: 2764 kfree(adapter->shadow_vfta); 2765 igb_clear_interrupt_scheme(adapter); 2766 #ifdef CONFIG_PCI_IOV 2767 igb_disable_sriov(pdev); 2768 #endif 2769 pci_iounmap(pdev, adapter->io_addr); 2770 err_ioremap: 2771 free_netdev(netdev); 2772 err_alloc_etherdev: 2773 pci_release_mem_regions(pdev); 2774 err_pci_reg: 2775 err_dma: 2776 pci_disable_device(pdev); 2777 return err; 2778 } 2779 2780 #ifdef CONFIG_PCI_IOV 2781 static int igb_disable_sriov(struct pci_dev *pdev) 2782 { 2783 struct net_device *netdev = pci_get_drvdata(pdev); 2784 struct igb_adapter *adapter = netdev_priv(netdev); 2785 struct e1000_hw *hw = &adapter->hw; 2786 2787 /* reclaim resources allocated to VFs */ 2788 if (adapter->vf_data) { 2789 /* disable iov and allow time for transactions to clear */ 2790 if (pci_vfs_assigned(pdev)) { 2791 dev_warn(&pdev->dev, 2792 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2793 return -EPERM; 2794 } else { 2795 pci_disable_sriov(pdev); 2796 msleep(500); 2797 } 2798 2799 kfree(adapter->vf_data); 2800 adapter->vf_data = NULL; 2801 adapter->vfs_allocated_count = 0; 2802 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2803 wrfl(); 2804 msleep(100); 2805 dev_info(&pdev->dev, "IOV Disabled\n"); 2806 2807 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2808 adapter->flags |= IGB_FLAG_DMAC; 2809 } 2810 2811 return 0; 2812 } 2813 2814 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2815 { 2816 struct net_device *netdev = pci_get_drvdata(pdev); 2817 struct igb_adapter *adapter = netdev_priv(netdev); 2818 int old_vfs = pci_num_vf(pdev); 2819 int err = 0; 2820 int i; 2821 2822 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2823 err = -EPERM; 2824 goto out; 2825 } 2826 if (!num_vfs) 2827 goto out; 2828 2829 if (old_vfs) { 2830 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2831 old_vfs, max_vfs); 2832 adapter->vfs_allocated_count = old_vfs; 2833 } else 2834 adapter->vfs_allocated_count = num_vfs; 2835 2836 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2837 sizeof(struct vf_data_storage), GFP_KERNEL); 2838 2839 /* if allocation failed then we do not support SR-IOV */ 2840 if (!adapter->vf_data) { 2841 adapter->vfs_allocated_count = 0; 2842 dev_err(&pdev->dev, 2843 "Unable to allocate memory for VF Data Storage\n"); 2844 err = -ENOMEM; 2845 goto out; 2846 } 2847 2848 /* only call pci_enable_sriov() if no VFs are allocated already */ 2849 if (!old_vfs) { 2850 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2851 if (err) 2852 goto err_out; 2853 } 2854 dev_info(&pdev->dev, "%d VFs allocated\n", 2855 adapter->vfs_allocated_count); 2856 for (i = 0; i < adapter->vfs_allocated_count; i++) 2857 igb_vf_configure(adapter, i); 2858 2859 /* DMA Coalescing is not supported in IOV mode. */ 2860 adapter->flags &= ~IGB_FLAG_DMAC; 2861 goto out; 2862 2863 err_out: 2864 kfree(adapter->vf_data); 2865 adapter->vf_data = NULL; 2866 adapter->vfs_allocated_count = 0; 2867 out: 2868 return err; 2869 } 2870 2871 #endif 2872 /** 2873 * igb_remove_i2c - Cleanup I2C interface 2874 * @adapter: pointer to adapter structure 2875 **/ 2876 static void igb_remove_i2c(struct igb_adapter *adapter) 2877 { 2878 /* free the adapter bus structure */ 2879 i2c_del_adapter(&adapter->i2c_adap); 2880 } 2881 2882 /** 2883 * igb_remove - Device Removal Routine 2884 * @pdev: PCI device information struct 2885 * 2886 * igb_remove is called by the PCI subsystem to alert the driver 2887 * that it should release a PCI device. The could be caused by a 2888 * Hot-Plug event, or because the driver is going to be removed from 2889 * memory. 2890 **/ 2891 static void igb_remove(struct pci_dev *pdev) 2892 { 2893 struct net_device *netdev = pci_get_drvdata(pdev); 2894 struct igb_adapter *adapter = netdev_priv(netdev); 2895 struct e1000_hw *hw = &adapter->hw; 2896 2897 pm_runtime_get_noresume(&pdev->dev); 2898 #ifdef CONFIG_IGB_HWMON 2899 igb_sysfs_exit(adapter); 2900 #endif 2901 igb_remove_i2c(adapter); 2902 igb_ptp_stop(adapter); 2903 /* The watchdog timer may be rescheduled, so explicitly 2904 * disable watchdog from being rescheduled. 2905 */ 2906 set_bit(__IGB_DOWN, &adapter->state); 2907 del_timer_sync(&adapter->watchdog_timer); 2908 del_timer_sync(&adapter->phy_info_timer); 2909 2910 cancel_work_sync(&adapter->reset_task); 2911 cancel_work_sync(&adapter->watchdog_task); 2912 2913 #ifdef CONFIG_IGB_DCA 2914 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2915 dev_info(&pdev->dev, "DCA disabled\n"); 2916 dca_remove_requester(&pdev->dev); 2917 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2918 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2919 } 2920 #endif 2921 2922 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2923 * would have already happened in close and is redundant. 2924 */ 2925 igb_release_hw_control(adapter); 2926 2927 #ifdef CONFIG_PCI_IOV 2928 igb_disable_sriov(pdev); 2929 #endif 2930 2931 unregister_netdev(netdev); 2932 2933 igb_clear_interrupt_scheme(adapter); 2934 2935 pci_iounmap(pdev, adapter->io_addr); 2936 if (hw->flash_address) 2937 iounmap(hw->flash_address); 2938 pci_release_mem_regions(pdev); 2939 2940 kfree(adapter->shadow_vfta); 2941 free_netdev(netdev); 2942 2943 pci_disable_pcie_error_reporting(pdev); 2944 2945 pci_disable_device(pdev); 2946 } 2947 2948 /** 2949 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2950 * @adapter: board private structure to initialize 2951 * 2952 * This function initializes the vf specific data storage and then attempts to 2953 * allocate the VFs. The reason for ordering it this way is because it is much 2954 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2955 * the memory for the VFs. 2956 **/ 2957 static void igb_probe_vfs(struct igb_adapter *adapter) 2958 { 2959 #ifdef CONFIG_PCI_IOV 2960 struct pci_dev *pdev = adapter->pdev; 2961 struct e1000_hw *hw = &adapter->hw; 2962 2963 /* Virtualization features not supported on i210 family. */ 2964 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2965 return; 2966 2967 /* Of the below we really only want the effect of getting 2968 * IGB_FLAG_HAS_MSIX set (if available), without which 2969 * igb_enable_sriov() has no effect. 2970 */ 2971 igb_set_interrupt_capability(adapter, true); 2972 igb_reset_interrupt_capability(adapter); 2973 2974 pci_sriov_set_totalvfs(pdev, 7); 2975 igb_enable_sriov(pdev, max_vfs); 2976 2977 #endif /* CONFIG_PCI_IOV */ 2978 } 2979 2980 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2981 { 2982 struct e1000_hw *hw = &adapter->hw; 2983 u32 max_rss_queues; 2984 2985 /* Determine the maximum number of RSS queues supported. */ 2986 switch (hw->mac.type) { 2987 case e1000_i211: 2988 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2989 break; 2990 case e1000_82575: 2991 case e1000_i210: 2992 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2993 break; 2994 case e1000_i350: 2995 /* I350 cannot do RSS and SR-IOV at the same time */ 2996 if (!!adapter->vfs_allocated_count) { 2997 max_rss_queues = 1; 2998 break; 2999 } 3000 /* fall through */ 3001 case e1000_82576: 3002 if (!!adapter->vfs_allocated_count) { 3003 max_rss_queues = 2; 3004 break; 3005 } 3006 /* fall through */ 3007 case e1000_82580: 3008 case e1000_i354: 3009 default: 3010 max_rss_queues = IGB_MAX_RX_QUEUES; 3011 break; 3012 } 3013 3014 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3015 3016 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3017 } 3018 3019 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3020 const u32 max_rss_queues) 3021 { 3022 struct e1000_hw *hw = &adapter->hw; 3023 3024 /* Determine if we need to pair queues. */ 3025 switch (hw->mac.type) { 3026 case e1000_82575: 3027 case e1000_i211: 3028 /* Device supports enough interrupts without queue pairing. */ 3029 break; 3030 case e1000_82576: 3031 case e1000_82580: 3032 case e1000_i350: 3033 case e1000_i354: 3034 case e1000_i210: 3035 default: 3036 /* If rss_queues > half of max_rss_queues, pair the queues in 3037 * order to conserve interrupts due to limited supply. 3038 */ 3039 if (adapter->rss_queues > (max_rss_queues / 2)) 3040 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3041 else 3042 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3043 break; 3044 } 3045 } 3046 3047 /** 3048 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3049 * @adapter: board private structure to initialize 3050 * 3051 * igb_sw_init initializes the Adapter private data structure. 3052 * Fields are initialized based on PCI device information and 3053 * OS network device settings (MTU size). 3054 **/ 3055 static int igb_sw_init(struct igb_adapter *adapter) 3056 { 3057 struct e1000_hw *hw = &adapter->hw; 3058 struct net_device *netdev = adapter->netdev; 3059 struct pci_dev *pdev = adapter->pdev; 3060 3061 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3062 3063 /* set default ring sizes */ 3064 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3065 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3066 3067 /* set default ITR values */ 3068 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3069 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3070 3071 /* set default work limits */ 3072 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3073 3074 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3075 VLAN_HLEN; 3076 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3077 3078 spin_lock_init(&adapter->nfc_lock); 3079 spin_lock_init(&adapter->stats64_lock); 3080 #ifdef CONFIG_PCI_IOV 3081 switch (hw->mac.type) { 3082 case e1000_82576: 3083 case e1000_i350: 3084 if (max_vfs > 7) { 3085 dev_warn(&pdev->dev, 3086 "Maximum of 7 VFs per PF, using max\n"); 3087 max_vfs = adapter->vfs_allocated_count = 7; 3088 } else 3089 adapter->vfs_allocated_count = max_vfs; 3090 if (adapter->vfs_allocated_count) 3091 dev_warn(&pdev->dev, 3092 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3093 break; 3094 default: 3095 break; 3096 } 3097 #endif /* CONFIG_PCI_IOV */ 3098 3099 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3100 adapter->flags |= IGB_FLAG_HAS_MSIX; 3101 3102 igb_probe_vfs(adapter); 3103 3104 igb_init_queue_configuration(adapter); 3105 3106 /* Setup and initialize a copy of the hw vlan table array */ 3107 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3108 GFP_ATOMIC); 3109 3110 /* This call may decrease the number of queues */ 3111 if (igb_init_interrupt_scheme(adapter, true)) { 3112 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3113 return -ENOMEM; 3114 } 3115 3116 /* Explicitly disable IRQ since the NIC can be in any state. */ 3117 igb_irq_disable(adapter); 3118 3119 if (hw->mac.type >= e1000_i350) 3120 adapter->flags &= ~IGB_FLAG_DMAC; 3121 3122 set_bit(__IGB_DOWN, &adapter->state); 3123 return 0; 3124 } 3125 3126 /** 3127 * igb_open - Called when a network interface is made active 3128 * @netdev: network interface device structure 3129 * 3130 * Returns 0 on success, negative value on failure 3131 * 3132 * The open entry point is called when a network interface is made 3133 * active by the system (IFF_UP). At this point all resources needed 3134 * for transmit and receive operations are allocated, the interrupt 3135 * handler is registered with the OS, the watchdog timer is started, 3136 * and the stack is notified that the interface is ready. 3137 **/ 3138 static int __igb_open(struct net_device *netdev, bool resuming) 3139 { 3140 struct igb_adapter *adapter = netdev_priv(netdev); 3141 struct e1000_hw *hw = &adapter->hw; 3142 struct pci_dev *pdev = adapter->pdev; 3143 int err; 3144 int i; 3145 3146 /* disallow open during test */ 3147 if (test_bit(__IGB_TESTING, &adapter->state)) { 3148 WARN_ON(resuming); 3149 return -EBUSY; 3150 } 3151 3152 if (!resuming) 3153 pm_runtime_get_sync(&pdev->dev); 3154 3155 netif_carrier_off(netdev); 3156 3157 /* allocate transmit descriptors */ 3158 err = igb_setup_all_tx_resources(adapter); 3159 if (err) 3160 goto err_setup_tx; 3161 3162 /* allocate receive descriptors */ 3163 err = igb_setup_all_rx_resources(adapter); 3164 if (err) 3165 goto err_setup_rx; 3166 3167 igb_power_up_link(adapter); 3168 3169 /* before we allocate an interrupt, we must be ready to handle it. 3170 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3171 * as soon as we call pci_request_irq, so we have to setup our 3172 * clean_rx handler before we do so. 3173 */ 3174 igb_configure(adapter); 3175 3176 err = igb_request_irq(adapter); 3177 if (err) 3178 goto err_req_irq; 3179 3180 /* Notify the stack of the actual queue counts. */ 3181 err = netif_set_real_num_tx_queues(adapter->netdev, 3182 adapter->num_tx_queues); 3183 if (err) 3184 goto err_set_queues; 3185 3186 err = netif_set_real_num_rx_queues(adapter->netdev, 3187 adapter->num_rx_queues); 3188 if (err) 3189 goto err_set_queues; 3190 3191 /* From here on the code is the same as igb_up() */ 3192 clear_bit(__IGB_DOWN, &adapter->state); 3193 3194 for (i = 0; i < adapter->num_q_vectors; i++) 3195 napi_enable(&(adapter->q_vector[i]->napi)); 3196 3197 /* Clear any pending interrupts. */ 3198 rd32(E1000_ICR); 3199 3200 igb_irq_enable(adapter); 3201 3202 /* notify VFs that reset has been completed */ 3203 if (adapter->vfs_allocated_count) { 3204 u32 reg_data = rd32(E1000_CTRL_EXT); 3205 3206 reg_data |= E1000_CTRL_EXT_PFRSTD; 3207 wr32(E1000_CTRL_EXT, reg_data); 3208 } 3209 3210 netif_tx_start_all_queues(netdev); 3211 3212 if (!resuming) 3213 pm_runtime_put(&pdev->dev); 3214 3215 /* start the watchdog. */ 3216 hw->mac.get_link_status = 1; 3217 schedule_work(&adapter->watchdog_task); 3218 3219 return 0; 3220 3221 err_set_queues: 3222 igb_free_irq(adapter); 3223 err_req_irq: 3224 igb_release_hw_control(adapter); 3225 igb_power_down_link(adapter); 3226 igb_free_all_rx_resources(adapter); 3227 err_setup_rx: 3228 igb_free_all_tx_resources(adapter); 3229 err_setup_tx: 3230 igb_reset(adapter); 3231 if (!resuming) 3232 pm_runtime_put(&pdev->dev); 3233 3234 return err; 3235 } 3236 3237 int igb_open(struct net_device *netdev) 3238 { 3239 return __igb_open(netdev, false); 3240 } 3241 3242 /** 3243 * igb_close - Disables a network interface 3244 * @netdev: network interface device structure 3245 * 3246 * Returns 0, this is not allowed to fail 3247 * 3248 * The close entry point is called when an interface is de-activated 3249 * by the OS. The hardware is still under the driver's control, but 3250 * needs to be disabled. A global MAC reset is issued to stop the 3251 * hardware, and all transmit and receive resources are freed. 3252 **/ 3253 static int __igb_close(struct net_device *netdev, bool suspending) 3254 { 3255 struct igb_adapter *adapter = netdev_priv(netdev); 3256 struct pci_dev *pdev = adapter->pdev; 3257 3258 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3259 3260 if (!suspending) 3261 pm_runtime_get_sync(&pdev->dev); 3262 3263 igb_down(adapter); 3264 igb_free_irq(adapter); 3265 3266 igb_nfc_filter_exit(adapter); 3267 3268 igb_free_all_tx_resources(adapter); 3269 igb_free_all_rx_resources(adapter); 3270 3271 if (!suspending) 3272 pm_runtime_put_sync(&pdev->dev); 3273 return 0; 3274 } 3275 3276 int igb_close(struct net_device *netdev) 3277 { 3278 if (netif_device_present(netdev)) 3279 return __igb_close(netdev, false); 3280 return 0; 3281 } 3282 3283 /** 3284 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3285 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3286 * 3287 * Return 0 on success, negative on failure 3288 **/ 3289 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3290 { 3291 struct device *dev = tx_ring->dev; 3292 int size; 3293 3294 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3295 3296 tx_ring->tx_buffer_info = vmalloc(size); 3297 if (!tx_ring->tx_buffer_info) 3298 goto err; 3299 3300 /* round up to nearest 4K */ 3301 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3302 tx_ring->size = ALIGN(tx_ring->size, 4096); 3303 3304 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3305 &tx_ring->dma, GFP_KERNEL); 3306 if (!tx_ring->desc) 3307 goto err; 3308 3309 tx_ring->next_to_use = 0; 3310 tx_ring->next_to_clean = 0; 3311 3312 return 0; 3313 3314 err: 3315 vfree(tx_ring->tx_buffer_info); 3316 tx_ring->tx_buffer_info = NULL; 3317 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3318 return -ENOMEM; 3319 } 3320 3321 /** 3322 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3323 * (Descriptors) for all queues 3324 * @adapter: board private structure 3325 * 3326 * Return 0 on success, negative on failure 3327 **/ 3328 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3329 { 3330 struct pci_dev *pdev = adapter->pdev; 3331 int i, err = 0; 3332 3333 for (i = 0; i < adapter->num_tx_queues; i++) { 3334 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3335 if (err) { 3336 dev_err(&pdev->dev, 3337 "Allocation for Tx Queue %u failed\n", i); 3338 for (i--; i >= 0; i--) 3339 igb_free_tx_resources(adapter->tx_ring[i]); 3340 break; 3341 } 3342 } 3343 3344 return err; 3345 } 3346 3347 /** 3348 * igb_setup_tctl - configure the transmit control registers 3349 * @adapter: Board private structure 3350 **/ 3351 void igb_setup_tctl(struct igb_adapter *adapter) 3352 { 3353 struct e1000_hw *hw = &adapter->hw; 3354 u32 tctl; 3355 3356 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3357 wr32(E1000_TXDCTL(0), 0); 3358 3359 /* Program the Transmit Control Register */ 3360 tctl = rd32(E1000_TCTL); 3361 tctl &= ~E1000_TCTL_CT; 3362 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3363 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3364 3365 igb_config_collision_dist(hw); 3366 3367 /* Enable transmits */ 3368 tctl |= E1000_TCTL_EN; 3369 3370 wr32(E1000_TCTL, tctl); 3371 } 3372 3373 /** 3374 * igb_configure_tx_ring - Configure transmit ring after Reset 3375 * @adapter: board private structure 3376 * @ring: tx ring to configure 3377 * 3378 * Configure a transmit ring after a reset. 3379 **/ 3380 void igb_configure_tx_ring(struct igb_adapter *adapter, 3381 struct igb_ring *ring) 3382 { 3383 struct e1000_hw *hw = &adapter->hw; 3384 u32 txdctl = 0; 3385 u64 tdba = ring->dma; 3386 int reg_idx = ring->reg_idx; 3387 3388 /* disable the queue */ 3389 wr32(E1000_TXDCTL(reg_idx), 0); 3390 wrfl(); 3391 mdelay(10); 3392 3393 wr32(E1000_TDLEN(reg_idx), 3394 ring->count * sizeof(union e1000_adv_tx_desc)); 3395 wr32(E1000_TDBAL(reg_idx), 3396 tdba & 0x00000000ffffffffULL); 3397 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3398 3399 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 3400 wr32(E1000_TDH(reg_idx), 0); 3401 writel(0, ring->tail); 3402 3403 txdctl |= IGB_TX_PTHRESH; 3404 txdctl |= IGB_TX_HTHRESH << 8; 3405 txdctl |= IGB_TX_WTHRESH << 16; 3406 3407 /* reinitialize tx_buffer_info */ 3408 memset(ring->tx_buffer_info, 0, 3409 sizeof(struct igb_tx_buffer) * ring->count); 3410 3411 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3412 wr32(E1000_TXDCTL(reg_idx), txdctl); 3413 } 3414 3415 /** 3416 * igb_configure_tx - Configure transmit Unit after Reset 3417 * @adapter: board private structure 3418 * 3419 * Configure the Tx unit of the MAC after a reset. 3420 **/ 3421 static void igb_configure_tx(struct igb_adapter *adapter) 3422 { 3423 int i; 3424 3425 for (i = 0; i < adapter->num_tx_queues; i++) 3426 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3427 } 3428 3429 /** 3430 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3431 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3432 * 3433 * Returns 0 on success, negative on failure 3434 **/ 3435 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3436 { 3437 struct device *dev = rx_ring->dev; 3438 int size; 3439 3440 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3441 3442 rx_ring->rx_buffer_info = vmalloc(size); 3443 if (!rx_ring->rx_buffer_info) 3444 goto err; 3445 3446 /* Round up to nearest 4K */ 3447 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3448 rx_ring->size = ALIGN(rx_ring->size, 4096); 3449 3450 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3451 &rx_ring->dma, GFP_KERNEL); 3452 if (!rx_ring->desc) 3453 goto err; 3454 3455 rx_ring->next_to_alloc = 0; 3456 rx_ring->next_to_clean = 0; 3457 rx_ring->next_to_use = 0; 3458 3459 return 0; 3460 3461 err: 3462 vfree(rx_ring->rx_buffer_info); 3463 rx_ring->rx_buffer_info = NULL; 3464 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3465 return -ENOMEM; 3466 } 3467 3468 /** 3469 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3470 * (Descriptors) for all queues 3471 * @adapter: board private structure 3472 * 3473 * Return 0 on success, negative on failure 3474 **/ 3475 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3476 { 3477 struct pci_dev *pdev = adapter->pdev; 3478 int i, err = 0; 3479 3480 for (i = 0; i < adapter->num_rx_queues; i++) { 3481 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3482 if (err) { 3483 dev_err(&pdev->dev, 3484 "Allocation for Rx Queue %u failed\n", i); 3485 for (i--; i >= 0; i--) 3486 igb_free_rx_resources(adapter->rx_ring[i]); 3487 break; 3488 } 3489 } 3490 3491 return err; 3492 } 3493 3494 /** 3495 * igb_setup_mrqc - configure the multiple receive queue control registers 3496 * @adapter: Board private structure 3497 **/ 3498 static void igb_setup_mrqc(struct igb_adapter *adapter) 3499 { 3500 struct e1000_hw *hw = &adapter->hw; 3501 u32 mrqc, rxcsum; 3502 u32 j, num_rx_queues; 3503 u32 rss_key[10]; 3504 3505 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3506 for (j = 0; j < 10; j++) 3507 wr32(E1000_RSSRK(j), rss_key[j]); 3508 3509 num_rx_queues = adapter->rss_queues; 3510 3511 switch (hw->mac.type) { 3512 case e1000_82576: 3513 /* 82576 supports 2 RSS queues for SR-IOV */ 3514 if (adapter->vfs_allocated_count) 3515 num_rx_queues = 2; 3516 break; 3517 default: 3518 break; 3519 } 3520 3521 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3522 for (j = 0; j < IGB_RETA_SIZE; j++) 3523 adapter->rss_indir_tbl[j] = 3524 (j * num_rx_queues) / IGB_RETA_SIZE; 3525 adapter->rss_indir_tbl_init = num_rx_queues; 3526 } 3527 igb_write_rss_indir_tbl(adapter); 3528 3529 /* Disable raw packet checksumming so that RSS hash is placed in 3530 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3531 * offloads as they are enabled by default 3532 */ 3533 rxcsum = rd32(E1000_RXCSUM); 3534 rxcsum |= E1000_RXCSUM_PCSD; 3535 3536 if (adapter->hw.mac.type >= e1000_82576) 3537 /* Enable Receive Checksum Offload for SCTP */ 3538 rxcsum |= E1000_RXCSUM_CRCOFL; 3539 3540 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3541 wr32(E1000_RXCSUM, rxcsum); 3542 3543 /* Generate RSS hash based on packet types, TCP/UDP 3544 * port numbers and/or IPv4/v6 src and dst addresses 3545 */ 3546 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3547 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3548 E1000_MRQC_RSS_FIELD_IPV6 | 3549 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3550 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3551 3552 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3553 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3554 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3555 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3556 3557 /* If VMDq is enabled then we set the appropriate mode for that, else 3558 * we default to RSS so that an RSS hash is calculated per packet even 3559 * if we are only using one queue 3560 */ 3561 if (adapter->vfs_allocated_count) { 3562 if (hw->mac.type > e1000_82575) { 3563 /* Set the default pool for the PF's first queue */ 3564 u32 vtctl = rd32(E1000_VT_CTL); 3565 3566 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3567 E1000_VT_CTL_DISABLE_DEF_POOL); 3568 vtctl |= adapter->vfs_allocated_count << 3569 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3570 wr32(E1000_VT_CTL, vtctl); 3571 } 3572 if (adapter->rss_queues > 1) 3573 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3574 else 3575 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3576 } else { 3577 if (hw->mac.type != e1000_i211) 3578 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3579 } 3580 igb_vmm_control(adapter); 3581 3582 wr32(E1000_MRQC, mrqc); 3583 } 3584 3585 /** 3586 * igb_setup_rctl - configure the receive control registers 3587 * @adapter: Board private structure 3588 **/ 3589 void igb_setup_rctl(struct igb_adapter *adapter) 3590 { 3591 struct e1000_hw *hw = &adapter->hw; 3592 u32 rctl; 3593 3594 rctl = rd32(E1000_RCTL); 3595 3596 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3597 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3598 3599 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3600 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3601 3602 /* enable stripping of CRC. It's unlikely this will break BMC 3603 * redirection as it did with e1000. Newer features require 3604 * that the HW strips the CRC. 3605 */ 3606 rctl |= E1000_RCTL_SECRC; 3607 3608 /* disable store bad packets and clear size bits. */ 3609 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3610 3611 /* enable LPE to allow for reception of jumbo frames */ 3612 rctl |= E1000_RCTL_LPE; 3613 3614 /* disable queue 0 to prevent tail write w/o re-config */ 3615 wr32(E1000_RXDCTL(0), 0); 3616 3617 /* Attention!!! For SR-IOV PF driver operations you must enable 3618 * queue drop for all VF and PF queues to prevent head of line blocking 3619 * if an un-trusted VF does not provide descriptors to hardware. 3620 */ 3621 if (adapter->vfs_allocated_count) { 3622 /* set all queue drop enable bits */ 3623 wr32(E1000_QDE, ALL_QUEUES); 3624 } 3625 3626 /* This is useful for sniffing bad packets. */ 3627 if (adapter->netdev->features & NETIF_F_RXALL) { 3628 /* UPE and MPE will be handled by normal PROMISC logic 3629 * in e1000e_set_rx_mode 3630 */ 3631 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3632 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3633 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3634 3635 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3636 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3637 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3638 * and that breaks VLANs. 3639 */ 3640 } 3641 3642 wr32(E1000_RCTL, rctl); 3643 } 3644 3645 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3646 int vfn) 3647 { 3648 struct e1000_hw *hw = &adapter->hw; 3649 u32 vmolr; 3650 3651 if (size > MAX_JUMBO_FRAME_SIZE) 3652 size = MAX_JUMBO_FRAME_SIZE; 3653 3654 vmolr = rd32(E1000_VMOLR(vfn)); 3655 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3656 vmolr |= size | E1000_VMOLR_LPE; 3657 wr32(E1000_VMOLR(vfn), vmolr); 3658 3659 return 0; 3660 } 3661 3662 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3663 int vfn, bool enable) 3664 { 3665 struct e1000_hw *hw = &adapter->hw; 3666 u32 val, reg; 3667 3668 if (hw->mac.type < e1000_82576) 3669 return; 3670 3671 if (hw->mac.type == e1000_i350) 3672 reg = E1000_DVMOLR(vfn); 3673 else 3674 reg = E1000_VMOLR(vfn); 3675 3676 val = rd32(reg); 3677 if (enable) 3678 val |= E1000_VMOLR_STRVLAN; 3679 else 3680 val &= ~(E1000_VMOLR_STRVLAN); 3681 wr32(reg, val); 3682 } 3683 3684 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3685 int vfn, bool aupe) 3686 { 3687 struct e1000_hw *hw = &adapter->hw; 3688 u32 vmolr; 3689 3690 /* This register exists only on 82576 and newer so if we are older then 3691 * we should exit and do nothing 3692 */ 3693 if (hw->mac.type < e1000_82576) 3694 return; 3695 3696 vmolr = rd32(E1000_VMOLR(vfn)); 3697 if (aupe) 3698 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3699 else 3700 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3701 3702 /* clear all bits that might not be set */ 3703 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3704 3705 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3706 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3707 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3708 * multicast packets 3709 */ 3710 if (vfn <= adapter->vfs_allocated_count) 3711 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3712 3713 wr32(E1000_VMOLR(vfn), vmolr); 3714 } 3715 3716 /** 3717 * igb_configure_rx_ring - Configure a receive ring after Reset 3718 * @adapter: board private structure 3719 * @ring: receive ring to be configured 3720 * 3721 * Configure the Rx unit of the MAC after a reset. 3722 **/ 3723 void igb_configure_rx_ring(struct igb_adapter *adapter, 3724 struct igb_ring *ring) 3725 { 3726 struct e1000_hw *hw = &adapter->hw; 3727 union e1000_adv_rx_desc *rx_desc; 3728 u64 rdba = ring->dma; 3729 int reg_idx = ring->reg_idx; 3730 u32 srrctl = 0, rxdctl = 0; 3731 3732 /* disable the queue */ 3733 wr32(E1000_RXDCTL(reg_idx), 0); 3734 3735 /* Set DMA base address registers */ 3736 wr32(E1000_RDBAL(reg_idx), 3737 rdba & 0x00000000ffffffffULL); 3738 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3739 wr32(E1000_RDLEN(reg_idx), 3740 ring->count * sizeof(union e1000_adv_rx_desc)); 3741 3742 /* initialize head and tail */ 3743 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 3744 wr32(E1000_RDH(reg_idx), 0); 3745 writel(0, ring->tail); 3746 3747 /* set descriptor configuration */ 3748 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3749 if (ring_uses_large_buffer(ring)) 3750 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3751 else 3752 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3753 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3754 if (hw->mac.type >= e1000_82580) 3755 srrctl |= E1000_SRRCTL_TIMESTAMP; 3756 /* Only set Drop Enable if we are supporting multiple queues */ 3757 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3758 srrctl |= E1000_SRRCTL_DROP_EN; 3759 3760 wr32(E1000_SRRCTL(reg_idx), srrctl); 3761 3762 /* set filtering for VMDQ pools */ 3763 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3764 3765 rxdctl |= IGB_RX_PTHRESH; 3766 rxdctl |= IGB_RX_HTHRESH << 8; 3767 rxdctl |= IGB_RX_WTHRESH << 16; 3768 3769 /* initialize rx_buffer_info */ 3770 memset(ring->rx_buffer_info, 0, 3771 sizeof(struct igb_rx_buffer) * ring->count); 3772 3773 /* initialize Rx descriptor 0 */ 3774 rx_desc = IGB_RX_DESC(ring, 0); 3775 rx_desc->wb.upper.length = 0; 3776 3777 /* enable receive descriptor fetching */ 3778 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3779 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3780 } 3781 3782 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 3783 struct igb_ring *rx_ring) 3784 { 3785 /* set build_skb and buffer size flags */ 3786 clear_ring_build_skb_enabled(rx_ring); 3787 clear_ring_uses_large_buffer(rx_ring); 3788 3789 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3790 return; 3791 3792 set_ring_build_skb_enabled(rx_ring); 3793 3794 #if (PAGE_SIZE < 8192) 3795 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 3796 return; 3797 3798 set_ring_uses_large_buffer(rx_ring); 3799 #endif 3800 } 3801 3802 /** 3803 * igb_configure_rx - Configure receive Unit after Reset 3804 * @adapter: board private structure 3805 * 3806 * Configure the Rx unit of the MAC after a reset. 3807 **/ 3808 static void igb_configure_rx(struct igb_adapter *adapter) 3809 { 3810 int i; 3811 3812 /* set the correct pool for the PF default MAC address in entry 0 */ 3813 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3814 adapter->vfs_allocated_count); 3815 3816 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3817 * the Base and Length of the Rx Descriptor Ring 3818 */ 3819 for (i = 0; i < adapter->num_rx_queues; i++) { 3820 struct igb_ring *rx_ring = adapter->rx_ring[i]; 3821 3822 igb_set_rx_buffer_len(adapter, rx_ring); 3823 igb_configure_rx_ring(adapter, rx_ring); 3824 } 3825 } 3826 3827 /** 3828 * igb_free_tx_resources - Free Tx Resources per Queue 3829 * @tx_ring: Tx descriptor ring for a specific queue 3830 * 3831 * Free all transmit software resources 3832 **/ 3833 void igb_free_tx_resources(struct igb_ring *tx_ring) 3834 { 3835 igb_clean_tx_ring(tx_ring); 3836 3837 vfree(tx_ring->tx_buffer_info); 3838 tx_ring->tx_buffer_info = NULL; 3839 3840 /* if not set, then don't free */ 3841 if (!tx_ring->desc) 3842 return; 3843 3844 dma_free_coherent(tx_ring->dev, tx_ring->size, 3845 tx_ring->desc, tx_ring->dma); 3846 3847 tx_ring->desc = NULL; 3848 } 3849 3850 /** 3851 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3852 * @adapter: board private structure 3853 * 3854 * Free all transmit software resources 3855 **/ 3856 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3857 { 3858 int i; 3859 3860 for (i = 0; i < adapter->num_tx_queues; i++) 3861 if (adapter->tx_ring[i]) 3862 igb_free_tx_resources(adapter->tx_ring[i]); 3863 } 3864 3865 /** 3866 * igb_clean_tx_ring - Free Tx Buffers 3867 * @tx_ring: ring to be cleaned 3868 **/ 3869 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3870 { 3871 u16 i = tx_ring->next_to_clean; 3872 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 3873 3874 while (i != tx_ring->next_to_use) { 3875 union e1000_adv_tx_desc *eop_desc, *tx_desc; 3876 3877 /* Free all the Tx ring sk_buffs */ 3878 dev_kfree_skb_any(tx_buffer->skb); 3879 3880 /* unmap skb header data */ 3881 dma_unmap_single(tx_ring->dev, 3882 dma_unmap_addr(tx_buffer, dma), 3883 dma_unmap_len(tx_buffer, len), 3884 DMA_TO_DEVICE); 3885 3886 /* check for eop_desc to determine the end of the packet */ 3887 eop_desc = tx_buffer->next_to_watch; 3888 tx_desc = IGB_TX_DESC(tx_ring, i); 3889 3890 /* unmap remaining buffers */ 3891 while (tx_desc != eop_desc) { 3892 tx_buffer++; 3893 tx_desc++; 3894 i++; 3895 if (unlikely(i == tx_ring->count)) { 3896 i = 0; 3897 tx_buffer = tx_ring->tx_buffer_info; 3898 tx_desc = IGB_TX_DESC(tx_ring, 0); 3899 } 3900 3901 /* unmap any remaining paged data */ 3902 if (dma_unmap_len(tx_buffer, len)) 3903 dma_unmap_page(tx_ring->dev, 3904 dma_unmap_addr(tx_buffer, dma), 3905 dma_unmap_len(tx_buffer, len), 3906 DMA_TO_DEVICE); 3907 } 3908 3909 /* move us one more past the eop_desc for start of next pkt */ 3910 tx_buffer++; 3911 i++; 3912 if (unlikely(i == tx_ring->count)) { 3913 i = 0; 3914 tx_buffer = tx_ring->tx_buffer_info; 3915 } 3916 } 3917 3918 /* reset BQL for queue */ 3919 netdev_tx_reset_queue(txring_txq(tx_ring)); 3920 3921 /* reset next_to_use and next_to_clean */ 3922 tx_ring->next_to_use = 0; 3923 tx_ring->next_to_clean = 0; 3924 } 3925 3926 /** 3927 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3928 * @adapter: board private structure 3929 **/ 3930 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3931 { 3932 int i; 3933 3934 for (i = 0; i < adapter->num_tx_queues; i++) 3935 if (adapter->tx_ring[i]) 3936 igb_clean_tx_ring(adapter->tx_ring[i]); 3937 } 3938 3939 /** 3940 * igb_free_rx_resources - Free Rx Resources 3941 * @rx_ring: ring to clean the resources from 3942 * 3943 * Free all receive software resources 3944 **/ 3945 void igb_free_rx_resources(struct igb_ring *rx_ring) 3946 { 3947 igb_clean_rx_ring(rx_ring); 3948 3949 vfree(rx_ring->rx_buffer_info); 3950 rx_ring->rx_buffer_info = NULL; 3951 3952 /* if not set, then don't free */ 3953 if (!rx_ring->desc) 3954 return; 3955 3956 dma_free_coherent(rx_ring->dev, rx_ring->size, 3957 rx_ring->desc, rx_ring->dma); 3958 3959 rx_ring->desc = NULL; 3960 } 3961 3962 /** 3963 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3964 * @adapter: board private structure 3965 * 3966 * Free all receive software resources 3967 **/ 3968 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3969 { 3970 int i; 3971 3972 for (i = 0; i < adapter->num_rx_queues; i++) 3973 if (adapter->rx_ring[i]) 3974 igb_free_rx_resources(adapter->rx_ring[i]); 3975 } 3976 3977 /** 3978 * igb_clean_rx_ring - Free Rx Buffers per Queue 3979 * @rx_ring: ring to free buffers from 3980 **/ 3981 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3982 { 3983 u16 i = rx_ring->next_to_clean; 3984 3985 if (rx_ring->skb) 3986 dev_kfree_skb(rx_ring->skb); 3987 rx_ring->skb = NULL; 3988 3989 /* Free all the Rx ring sk_buffs */ 3990 while (i != rx_ring->next_to_alloc) { 3991 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3992 3993 /* Invalidate cache lines that may have been written to by 3994 * device so that we avoid corrupting memory. 3995 */ 3996 dma_sync_single_range_for_cpu(rx_ring->dev, 3997 buffer_info->dma, 3998 buffer_info->page_offset, 3999 igb_rx_bufsz(rx_ring), 4000 DMA_FROM_DEVICE); 4001 4002 /* free resources associated with mapping */ 4003 dma_unmap_page_attrs(rx_ring->dev, 4004 buffer_info->dma, 4005 igb_rx_pg_size(rx_ring), 4006 DMA_FROM_DEVICE, 4007 IGB_RX_DMA_ATTR); 4008 __page_frag_cache_drain(buffer_info->page, 4009 buffer_info->pagecnt_bias); 4010 4011 i++; 4012 if (i == rx_ring->count) 4013 i = 0; 4014 } 4015 4016 rx_ring->next_to_alloc = 0; 4017 rx_ring->next_to_clean = 0; 4018 rx_ring->next_to_use = 0; 4019 } 4020 4021 /** 4022 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4023 * @adapter: board private structure 4024 **/ 4025 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4026 { 4027 int i; 4028 4029 for (i = 0; i < adapter->num_rx_queues; i++) 4030 if (adapter->rx_ring[i]) 4031 igb_clean_rx_ring(adapter->rx_ring[i]); 4032 } 4033 4034 /** 4035 * igb_set_mac - Change the Ethernet Address of the NIC 4036 * @netdev: network interface device structure 4037 * @p: pointer to an address structure 4038 * 4039 * Returns 0 on success, negative on failure 4040 **/ 4041 static int igb_set_mac(struct net_device *netdev, void *p) 4042 { 4043 struct igb_adapter *adapter = netdev_priv(netdev); 4044 struct e1000_hw *hw = &adapter->hw; 4045 struct sockaddr *addr = p; 4046 4047 if (!is_valid_ether_addr(addr->sa_data)) 4048 return -EADDRNOTAVAIL; 4049 4050 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4051 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4052 4053 /* set the correct pool for the new PF MAC address in entry 0 */ 4054 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 4055 adapter->vfs_allocated_count); 4056 4057 return 0; 4058 } 4059 4060 /** 4061 * igb_write_mc_addr_list - write multicast addresses to MTA 4062 * @netdev: network interface device structure 4063 * 4064 * Writes multicast address list to the MTA hash table. 4065 * Returns: -ENOMEM on failure 4066 * 0 on no addresses written 4067 * X on writing X addresses to MTA 4068 **/ 4069 static int igb_write_mc_addr_list(struct net_device *netdev) 4070 { 4071 struct igb_adapter *adapter = netdev_priv(netdev); 4072 struct e1000_hw *hw = &adapter->hw; 4073 struct netdev_hw_addr *ha; 4074 u8 *mta_list; 4075 int i; 4076 4077 if (netdev_mc_empty(netdev)) { 4078 /* nothing to program, so clear mc list */ 4079 igb_update_mc_addr_list(hw, NULL, 0); 4080 igb_restore_vf_multicasts(adapter); 4081 return 0; 4082 } 4083 4084 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4085 if (!mta_list) 4086 return -ENOMEM; 4087 4088 /* The shared function expects a packed array of only addresses. */ 4089 i = 0; 4090 netdev_for_each_mc_addr(ha, netdev) 4091 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4092 4093 igb_update_mc_addr_list(hw, mta_list, i); 4094 kfree(mta_list); 4095 4096 return netdev_mc_count(netdev); 4097 } 4098 4099 /** 4100 * igb_write_uc_addr_list - write unicast addresses to RAR table 4101 * @netdev: network interface device structure 4102 * 4103 * Writes unicast address list to the RAR table. 4104 * Returns: -ENOMEM on failure/insufficient address space 4105 * 0 on no addresses written 4106 * X on writing X addresses to the RAR table 4107 **/ 4108 static int igb_write_uc_addr_list(struct net_device *netdev) 4109 { 4110 struct igb_adapter *adapter = netdev_priv(netdev); 4111 struct e1000_hw *hw = &adapter->hw; 4112 unsigned int vfn = adapter->vfs_allocated_count; 4113 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 4114 int count = 0; 4115 4116 /* return ENOMEM indicating insufficient memory for addresses */ 4117 if (netdev_uc_count(netdev) > rar_entries) 4118 return -ENOMEM; 4119 4120 if (!netdev_uc_empty(netdev) && rar_entries) { 4121 struct netdev_hw_addr *ha; 4122 4123 netdev_for_each_uc_addr(ha, netdev) { 4124 if (!rar_entries) 4125 break; 4126 igb_rar_set_qsel(adapter, ha->addr, 4127 rar_entries--, 4128 vfn); 4129 count++; 4130 } 4131 } 4132 /* write the addresses in reverse order to avoid write combining */ 4133 for (; rar_entries > 0 ; rar_entries--) { 4134 wr32(E1000_RAH(rar_entries), 0); 4135 wr32(E1000_RAL(rar_entries), 0); 4136 } 4137 wrfl(); 4138 4139 return count; 4140 } 4141 4142 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4143 { 4144 struct e1000_hw *hw = &adapter->hw; 4145 u32 i, pf_id; 4146 4147 switch (hw->mac.type) { 4148 case e1000_i210: 4149 case e1000_i211: 4150 case e1000_i350: 4151 /* VLAN filtering needed for VLAN prio filter */ 4152 if (adapter->netdev->features & NETIF_F_NTUPLE) 4153 break; 4154 /* fall through */ 4155 case e1000_82576: 4156 case e1000_82580: 4157 case e1000_i354: 4158 /* VLAN filtering needed for pool filtering */ 4159 if (adapter->vfs_allocated_count) 4160 break; 4161 /* fall through */ 4162 default: 4163 return 1; 4164 } 4165 4166 /* We are already in VLAN promisc, nothing to do */ 4167 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4168 return 0; 4169 4170 if (!adapter->vfs_allocated_count) 4171 goto set_vfta; 4172 4173 /* Add PF to all active pools */ 4174 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4175 4176 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4177 u32 vlvf = rd32(E1000_VLVF(i)); 4178 4179 vlvf |= BIT(pf_id); 4180 wr32(E1000_VLVF(i), vlvf); 4181 } 4182 4183 set_vfta: 4184 /* Set all bits in the VLAN filter table array */ 4185 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4186 hw->mac.ops.write_vfta(hw, i, ~0U); 4187 4188 /* Set flag so we don't redo unnecessary work */ 4189 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4190 4191 return 0; 4192 } 4193 4194 #define VFTA_BLOCK_SIZE 8 4195 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4196 { 4197 struct e1000_hw *hw = &adapter->hw; 4198 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4199 u32 vid_start = vfta_offset * 32; 4200 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4201 u32 i, vid, word, bits, pf_id; 4202 4203 /* guarantee that we don't scrub out management VLAN */ 4204 vid = adapter->mng_vlan_id; 4205 if (vid >= vid_start && vid < vid_end) 4206 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4207 4208 if (!adapter->vfs_allocated_count) 4209 goto set_vfta; 4210 4211 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4212 4213 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4214 u32 vlvf = rd32(E1000_VLVF(i)); 4215 4216 /* pull VLAN ID from VLVF */ 4217 vid = vlvf & VLAN_VID_MASK; 4218 4219 /* only concern ourselves with a certain range */ 4220 if (vid < vid_start || vid >= vid_end) 4221 continue; 4222 4223 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4224 /* record VLAN ID in VFTA */ 4225 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4226 4227 /* if PF is part of this then continue */ 4228 if (test_bit(vid, adapter->active_vlans)) 4229 continue; 4230 } 4231 4232 /* remove PF from the pool */ 4233 bits = ~BIT(pf_id); 4234 bits &= rd32(E1000_VLVF(i)); 4235 wr32(E1000_VLVF(i), bits); 4236 } 4237 4238 set_vfta: 4239 /* extract values from active_vlans and write back to VFTA */ 4240 for (i = VFTA_BLOCK_SIZE; i--;) { 4241 vid = (vfta_offset + i) * 32; 4242 word = vid / BITS_PER_LONG; 4243 bits = vid % BITS_PER_LONG; 4244 4245 vfta[i] |= adapter->active_vlans[word] >> bits; 4246 4247 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4248 } 4249 } 4250 4251 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4252 { 4253 u32 i; 4254 4255 /* We are not in VLAN promisc, nothing to do */ 4256 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4257 return; 4258 4259 /* Set flag so we don't redo unnecessary work */ 4260 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4261 4262 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4263 igb_scrub_vfta(adapter, i); 4264 } 4265 4266 /** 4267 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4268 * @netdev: network interface device structure 4269 * 4270 * The set_rx_mode entry point is called whenever the unicast or multicast 4271 * address lists or the network interface flags are updated. This routine is 4272 * responsible for configuring the hardware for proper unicast, multicast, 4273 * promiscuous mode, and all-multi behavior. 4274 **/ 4275 static void igb_set_rx_mode(struct net_device *netdev) 4276 { 4277 struct igb_adapter *adapter = netdev_priv(netdev); 4278 struct e1000_hw *hw = &adapter->hw; 4279 unsigned int vfn = adapter->vfs_allocated_count; 4280 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4281 int count; 4282 4283 /* Check for Promiscuous and All Multicast modes */ 4284 if (netdev->flags & IFF_PROMISC) { 4285 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4286 vmolr |= E1000_VMOLR_MPME; 4287 4288 /* enable use of UTA filter to force packets to default pool */ 4289 if (hw->mac.type == e1000_82576) 4290 vmolr |= E1000_VMOLR_ROPE; 4291 } else { 4292 if (netdev->flags & IFF_ALLMULTI) { 4293 rctl |= E1000_RCTL_MPE; 4294 vmolr |= E1000_VMOLR_MPME; 4295 } else { 4296 /* Write addresses to the MTA, if the attempt fails 4297 * then we should just turn on promiscuous mode so 4298 * that we can at least receive multicast traffic 4299 */ 4300 count = igb_write_mc_addr_list(netdev); 4301 if (count < 0) { 4302 rctl |= E1000_RCTL_MPE; 4303 vmolr |= E1000_VMOLR_MPME; 4304 } else if (count) { 4305 vmolr |= E1000_VMOLR_ROMPE; 4306 } 4307 } 4308 } 4309 4310 /* Write addresses to available RAR registers, if there is not 4311 * sufficient space to store all the addresses then enable 4312 * unicast promiscuous mode 4313 */ 4314 count = igb_write_uc_addr_list(netdev); 4315 if (count < 0) { 4316 rctl |= E1000_RCTL_UPE; 4317 vmolr |= E1000_VMOLR_ROPE; 4318 } 4319 4320 /* enable VLAN filtering by default */ 4321 rctl |= E1000_RCTL_VFE; 4322 4323 /* disable VLAN filtering for modes that require it */ 4324 if ((netdev->flags & IFF_PROMISC) || 4325 (netdev->features & NETIF_F_RXALL)) { 4326 /* if we fail to set all rules then just clear VFE */ 4327 if (igb_vlan_promisc_enable(adapter)) 4328 rctl &= ~E1000_RCTL_VFE; 4329 } else { 4330 igb_vlan_promisc_disable(adapter); 4331 } 4332 4333 /* update state of unicast, multicast, and VLAN filtering modes */ 4334 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4335 E1000_RCTL_VFE); 4336 wr32(E1000_RCTL, rctl); 4337 4338 #if (PAGE_SIZE < 8192) 4339 if (!adapter->vfs_allocated_count) { 4340 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4341 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4342 } 4343 #endif 4344 wr32(E1000_RLPML, rlpml); 4345 4346 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4347 * the VMOLR to enable the appropriate modes. Without this workaround 4348 * we will have issues with VLAN tag stripping not being done for frames 4349 * that are only arriving because we are the default pool 4350 */ 4351 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4352 return; 4353 4354 /* set UTA to appropriate mode */ 4355 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4356 4357 vmolr |= rd32(E1000_VMOLR(vfn)) & 4358 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4359 4360 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4361 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4362 #if (PAGE_SIZE < 8192) 4363 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4364 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4365 else 4366 #endif 4367 vmolr |= MAX_JUMBO_FRAME_SIZE; 4368 vmolr |= E1000_VMOLR_LPE; 4369 4370 wr32(E1000_VMOLR(vfn), vmolr); 4371 4372 igb_restore_vf_multicasts(adapter); 4373 } 4374 4375 static void igb_check_wvbr(struct igb_adapter *adapter) 4376 { 4377 struct e1000_hw *hw = &adapter->hw; 4378 u32 wvbr = 0; 4379 4380 switch (hw->mac.type) { 4381 case e1000_82576: 4382 case e1000_i350: 4383 wvbr = rd32(E1000_WVBR); 4384 if (!wvbr) 4385 return; 4386 break; 4387 default: 4388 break; 4389 } 4390 4391 adapter->wvbr |= wvbr; 4392 } 4393 4394 #define IGB_STAGGERED_QUEUE_OFFSET 8 4395 4396 static void igb_spoof_check(struct igb_adapter *adapter) 4397 { 4398 int j; 4399 4400 if (!adapter->wvbr) 4401 return; 4402 4403 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4404 if (adapter->wvbr & BIT(j) || 4405 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4406 dev_warn(&adapter->pdev->dev, 4407 "Spoof event(s) detected on VF %d\n", j); 4408 adapter->wvbr &= 4409 ~(BIT(j) | 4410 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4411 } 4412 } 4413 } 4414 4415 /* Need to wait a few seconds after link up to get diagnostic information from 4416 * the phy 4417 */ 4418 static void igb_update_phy_info(unsigned long data) 4419 { 4420 struct igb_adapter *adapter = (struct igb_adapter *) data; 4421 igb_get_phy_info(&adapter->hw); 4422 } 4423 4424 /** 4425 * igb_has_link - check shared code for link and determine up/down 4426 * @adapter: pointer to driver private info 4427 **/ 4428 bool igb_has_link(struct igb_adapter *adapter) 4429 { 4430 struct e1000_hw *hw = &adapter->hw; 4431 bool link_active = false; 4432 4433 /* get_link_status is set on LSC (link status) interrupt or 4434 * rx sequence error interrupt. get_link_status will stay 4435 * false until the e1000_check_for_link establishes link 4436 * for copper adapters ONLY 4437 */ 4438 switch (hw->phy.media_type) { 4439 case e1000_media_type_copper: 4440 if (!hw->mac.get_link_status) 4441 return true; 4442 case e1000_media_type_internal_serdes: 4443 hw->mac.ops.check_for_link(hw); 4444 link_active = !hw->mac.get_link_status; 4445 break; 4446 default: 4447 case e1000_media_type_unknown: 4448 break; 4449 } 4450 4451 if (((hw->mac.type == e1000_i210) || 4452 (hw->mac.type == e1000_i211)) && 4453 (hw->phy.id == I210_I_PHY_ID)) { 4454 if (!netif_carrier_ok(adapter->netdev)) { 4455 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4456 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4457 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4458 adapter->link_check_timeout = jiffies; 4459 } 4460 } 4461 4462 return link_active; 4463 } 4464 4465 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4466 { 4467 bool ret = false; 4468 u32 ctrl_ext, thstat; 4469 4470 /* check for thermal sensor event on i350 copper only */ 4471 if (hw->mac.type == e1000_i350) { 4472 thstat = rd32(E1000_THSTAT); 4473 ctrl_ext = rd32(E1000_CTRL_EXT); 4474 4475 if ((hw->phy.media_type == e1000_media_type_copper) && 4476 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4477 ret = !!(thstat & event); 4478 } 4479 4480 return ret; 4481 } 4482 4483 /** 4484 * igb_check_lvmmc - check for malformed packets received 4485 * and indicated in LVMMC register 4486 * @adapter: pointer to adapter 4487 **/ 4488 static void igb_check_lvmmc(struct igb_adapter *adapter) 4489 { 4490 struct e1000_hw *hw = &adapter->hw; 4491 u32 lvmmc; 4492 4493 lvmmc = rd32(E1000_LVMMC); 4494 if (lvmmc) { 4495 if (unlikely(net_ratelimit())) { 4496 netdev_warn(adapter->netdev, 4497 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4498 lvmmc); 4499 } 4500 } 4501 } 4502 4503 /** 4504 * igb_watchdog - Timer Call-back 4505 * @data: pointer to adapter cast into an unsigned long 4506 **/ 4507 static void igb_watchdog(unsigned long data) 4508 { 4509 struct igb_adapter *adapter = (struct igb_adapter *)data; 4510 /* Do the rest outside of interrupt context */ 4511 schedule_work(&adapter->watchdog_task); 4512 } 4513 4514 static void igb_watchdog_task(struct work_struct *work) 4515 { 4516 struct igb_adapter *adapter = container_of(work, 4517 struct igb_adapter, 4518 watchdog_task); 4519 struct e1000_hw *hw = &adapter->hw; 4520 struct e1000_phy_info *phy = &hw->phy; 4521 struct net_device *netdev = adapter->netdev; 4522 u32 link; 4523 int i; 4524 u32 connsw; 4525 u16 phy_data, retry_count = 20; 4526 4527 link = igb_has_link(adapter); 4528 4529 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4530 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4531 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4532 else 4533 link = false; 4534 } 4535 4536 /* Force link down if we have fiber to swap to */ 4537 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4538 if (hw->phy.media_type == e1000_media_type_copper) { 4539 connsw = rd32(E1000_CONNSW); 4540 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4541 link = 0; 4542 } 4543 } 4544 if (link) { 4545 /* Perform a reset if the media type changed. */ 4546 if (hw->dev_spec._82575.media_changed) { 4547 hw->dev_spec._82575.media_changed = false; 4548 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4549 igb_reset(adapter); 4550 } 4551 /* Cancel scheduled suspend requests. */ 4552 pm_runtime_resume(netdev->dev.parent); 4553 4554 if (!netif_carrier_ok(netdev)) { 4555 u32 ctrl; 4556 4557 hw->mac.ops.get_speed_and_duplex(hw, 4558 &adapter->link_speed, 4559 &adapter->link_duplex); 4560 4561 ctrl = rd32(E1000_CTRL); 4562 /* Links status message must follow this format */ 4563 netdev_info(netdev, 4564 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4565 netdev->name, 4566 adapter->link_speed, 4567 adapter->link_duplex == FULL_DUPLEX ? 4568 "Full" : "Half", 4569 (ctrl & E1000_CTRL_TFCE) && 4570 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4571 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4572 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4573 4574 /* disable EEE if enabled */ 4575 if ((adapter->flags & IGB_FLAG_EEE) && 4576 (adapter->link_duplex == HALF_DUPLEX)) { 4577 dev_info(&adapter->pdev->dev, 4578 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4579 adapter->hw.dev_spec._82575.eee_disable = true; 4580 adapter->flags &= ~IGB_FLAG_EEE; 4581 } 4582 4583 /* check if SmartSpeed worked */ 4584 igb_check_downshift(hw); 4585 if (phy->speed_downgraded) 4586 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4587 4588 /* check for thermal sensor event */ 4589 if (igb_thermal_sensor_event(hw, 4590 E1000_THSTAT_LINK_THROTTLE)) 4591 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4592 4593 /* adjust timeout factor according to speed/duplex */ 4594 adapter->tx_timeout_factor = 1; 4595 switch (adapter->link_speed) { 4596 case SPEED_10: 4597 adapter->tx_timeout_factor = 14; 4598 break; 4599 case SPEED_100: 4600 /* maybe add some timeout factor ? */ 4601 break; 4602 } 4603 4604 if (adapter->link_speed != SPEED_1000) 4605 goto no_wait; 4606 4607 /* wait for Remote receiver status OK */ 4608 retry_read_status: 4609 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4610 &phy_data)) { 4611 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4612 retry_count) { 4613 msleep(100); 4614 retry_count--; 4615 goto retry_read_status; 4616 } else if (!retry_count) { 4617 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4618 } 4619 } else { 4620 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4621 } 4622 no_wait: 4623 netif_carrier_on(netdev); 4624 4625 igb_ping_all_vfs(adapter); 4626 igb_check_vf_rate_limit(adapter); 4627 4628 /* link state has changed, schedule phy info update */ 4629 if (!test_bit(__IGB_DOWN, &adapter->state)) 4630 mod_timer(&adapter->phy_info_timer, 4631 round_jiffies(jiffies + 2 * HZ)); 4632 } 4633 } else { 4634 if (netif_carrier_ok(netdev)) { 4635 adapter->link_speed = 0; 4636 adapter->link_duplex = 0; 4637 4638 /* check for thermal sensor event */ 4639 if (igb_thermal_sensor_event(hw, 4640 E1000_THSTAT_PWR_DOWN)) { 4641 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4642 } 4643 4644 /* Links status message must follow this format */ 4645 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4646 netdev->name); 4647 netif_carrier_off(netdev); 4648 4649 igb_ping_all_vfs(adapter); 4650 4651 /* link state has changed, schedule phy info update */ 4652 if (!test_bit(__IGB_DOWN, &adapter->state)) 4653 mod_timer(&adapter->phy_info_timer, 4654 round_jiffies(jiffies + 2 * HZ)); 4655 4656 /* link is down, time to check for alternate media */ 4657 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4658 igb_check_swap_media(adapter); 4659 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4660 schedule_work(&adapter->reset_task); 4661 /* return immediately */ 4662 return; 4663 } 4664 } 4665 pm_schedule_suspend(netdev->dev.parent, 4666 MSEC_PER_SEC * 5); 4667 4668 /* also check for alternate media here */ 4669 } else if (!netif_carrier_ok(netdev) && 4670 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4671 igb_check_swap_media(adapter); 4672 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4673 schedule_work(&adapter->reset_task); 4674 /* return immediately */ 4675 return; 4676 } 4677 } 4678 } 4679 4680 spin_lock(&adapter->stats64_lock); 4681 igb_update_stats(adapter, &adapter->stats64); 4682 spin_unlock(&adapter->stats64_lock); 4683 4684 for (i = 0; i < adapter->num_tx_queues; i++) { 4685 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4686 if (!netif_carrier_ok(netdev)) { 4687 /* We've lost link, so the controller stops DMA, 4688 * but we've got queued Tx work that's never going 4689 * to get done, so reset controller to flush Tx. 4690 * (Do the reset outside of interrupt context). 4691 */ 4692 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4693 adapter->tx_timeout_count++; 4694 schedule_work(&adapter->reset_task); 4695 /* return immediately since reset is imminent */ 4696 return; 4697 } 4698 } 4699 4700 /* Force detection of hung controller every watchdog period */ 4701 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4702 } 4703 4704 /* Cause software interrupt to ensure Rx ring is cleaned */ 4705 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4706 u32 eics = 0; 4707 4708 for (i = 0; i < adapter->num_q_vectors; i++) 4709 eics |= adapter->q_vector[i]->eims_value; 4710 wr32(E1000_EICS, eics); 4711 } else { 4712 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4713 } 4714 4715 igb_spoof_check(adapter); 4716 igb_ptp_rx_hang(adapter); 4717 4718 /* Check LVMMC register on i350/i354 only */ 4719 if ((adapter->hw.mac.type == e1000_i350) || 4720 (adapter->hw.mac.type == e1000_i354)) 4721 igb_check_lvmmc(adapter); 4722 4723 /* Reset the timer */ 4724 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4725 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4726 mod_timer(&adapter->watchdog_timer, 4727 round_jiffies(jiffies + HZ)); 4728 else 4729 mod_timer(&adapter->watchdog_timer, 4730 round_jiffies(jiffies + 2 * HZ)); 4731 } 4732 } 4733 4734 enum latency_range { 4735 lowest_latency = 0, 4736 low_latency = 1, 4737 bulk_latency = 2, 4738 latency_invalid = 255 4739 }; 4740 4741 /** 4742 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4743 * @q_vector: pointer to q_vector 4744 * 4745 * Stores a new ITR value based on strictly on packet size. This 4746 * algorithm is less sophisticated than that used in igb_update_itr, 4747 * due to the difficulty of synchronizing statistics across multiple 4748 * receive rings. The divisors and thresholds used by this function 4749 * were determined based on theoretical maximum wire speed and testing 4750 * data, in order to minimize response time while increasing bulk 4751 * throughput. 4752 * This functionality is controlled by ethtool's coalescing settings. 4753 * NOTE: This function is called only when operating in a multiqueue 4754 * receive environment. 4755 **/ 4756 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4757 { 4758 int new_val = q_vector->itr_val; 4759 int avg_wire_size = 0; 4760 struct igb_adapter *adapter = q_vector->adapter; 4761 unsigned int packets; 4762 4763 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4764 * ints/sec - ITR timer value of 120 ticks. 4765 */ 4766 if (adapter->link_speed != SPEED_1000) { 4767 new_val = IGB_4K_ITR; 4768 goto set_itr_val; 4769 } 4770 4771 packets = q_vector->rx.total_packets; 4772 if (packets) 4773 avg_wire_size = q_vector->rx.total_bytes / packets; 4774 4775 packets = q_vector->tx.total_packets; 4776 if (packets) 4777 avg_wire_size = max_t(u32, avg_wire_size, 4778 q_vector->tx.total_bytes / packets); 4779 4780 /* if avg_wire_size isn't set no work was done */ 4781 if (!avg_wire_size) 4782 goto clear_counts; 4783 4784 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4785 avg_wire_size += 24; 4786 4787 /* Don't starve jumbo frames */ 4788 avg_wire_size = min(avg_wire_size, 3000); 4789 4790 /* Give a little boost to mid-size frames */ 4791 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4792 new_val = avg_wire_size / 3; 4793 else 4794 new_val = avg_wire_size / 2; 4795 4796 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4797 if (new_val < IGB_20K_ITR && 4798 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4799 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4800 new_val = IGB_20K_ITR; 4801 4802 set_itr_val: 4803 if (new_val != q_vector->itr_val) { 4804 q_vector->itr_val = new_val; 4805 q_vector->set_itr = 1; 4806 } 4807 clear_counts: 4808 q_vector->rx.total_bytes = 0; 4809 q_vector->rx.total_packets = 0; 4810 q_vector->tx.total_bytes = 0; 4811 q_vector->tx.total_packets = 0; 4812 } 4813 4814 /** 4815 * igb_update_itr - update the dynamic ITR value based on statistics 4816 * @q_vector: pointer to q_vector 4817 * @ring_container: ring info to update the itr for 4818 * 4819 * Stores a new ITR value based on packets and byte 4820 * counts during the last interrupt. The advantage of per interrupt 4821 * computation is faster updates and more accurate ITR for the current 4822 * traffic pattern. Constants in this function were computed 4823 * based on theoretical maximum wire speed and thresholds were set based 4824 * on testing data as well as attempting to minimize response time 4825 * while increasing bulk throughput. 4826 * This functionality is controlled by ethtool's coalescing settings. 4827 * NOTE: These calculations are only valid when operating in a single- 4828 * queue environment. 4829 **/ 4830 static void igb_update_itr(struct igb_q_vector *q_vector, 4831 struct igb_ring_container *ring_container) 4832 { 4833 unsigned int packets = ring_container->total_packets; 4834 unsigned int bytes = ring_container->total_bytes; 4835 u8 itrval = ring_container->itr; 4836 4837 /* no packets, exit with status unchanged */ 4838 if (packets == 0) 4839 return; 4840 4841 switch (itrval) { 4842 case lowest_latency: 4843 /* handle TSO and jumbo frames */ 4844 if (bytes/packets > 8000) 4845 itrval = bulk_latency; 4846 else if ((packets < 5) && (bytes > 512)) 4847 itrval = low_latency; 4848 break; 4849 case low_latency: /* 50 usec aka 20000 ints/s */ 4850 if (bytes > 10000) { 4851 /* this if handles the TSO accounting */ 4852 if (bytes/packets > 8000) 4853 itrval = bulk_latency; 4854 else if ((packets < 10) || ((bytes/packets) > 1200)) 4855 itrval = bulk_latency; 4856 else if ((packets > 35)) 4857 itrval = lowest_latency; 4858 } else if (bytes/packets > 2000) { 4859 itrval = bulk_latency; 4860 } else if (packets <= 2 && bytes < 512) { 4861 itrval = lowest_latency; 4862 } 4863 break; 4864 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4865 if (bytes > 25000) { 4866 if (packets > 35) 4867 itrval = low_latency; 4868 } else if (bytes < 1500) { 4869 itrval = low_latency; 4870 } 4871 break; 4872 } 4873 4874 /* clear work counters since we have the values we need */ 4875 ring_container->total_bytes = 0; 4876 ring_container->total_packets = 0; 4877 4878 /* write updated itr to ring container */ 4879 ring_container->itr = itrval; 4880 } 4881 4882 static void igb_set_itr(struct igb_q_vector *q_vector) 4883 { 4884 struct igb_adapter *adapter = q_vector->adapter; 4885 u32 new_itr = q_vector->itr_val; 4886 u8 current_itr = 0; 4887 4888 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4889 if (adapter->link_speed != SPEED_1000) { 4890 current_itr = 0; 4891 new_itr = IGB_4K_ITR; 4892 goto set_itr_now; 4893 } 4894 4895 igb_update_itr(q_vector, &q_vector->tx); 4896 igb_update_itr(q_vector, &q_vector->rx); 4897 4898 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4899 4900 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4901 if (current_itr == lowest_latency && 4902 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4903 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4904 current_itr = low_latency; 4905 4906 switch (current_itr) { 4907 /* counts and packets in update_itr are dependent on these numbers */ 4908 case lowest_latency: 4909 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4910 break; 4911 case low_latency: 4912 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4913 break; 4914 case bulk_latency: 4915 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4916 break; 4917 default: 4918 break; 4919 } 4920 4921 set_itr_now: 4922 if (new_itr != q_vector->itr_val) { 4923 /* this attempts to bias the interrupt rate towards Bulk 4924 * by adding intermediate steps when interrupt rate is 4925 * increasing 4926 */ 4927 new_itr = new_itr > q_vector->itr_val ? 4928 max((new_itr * q_vector->itr_val) / 4929 (new_itr + (q_vector->itr_val >> 2)), 4930 new_itr) : new_itr; 4931 /* Don't write the value here; it resets the adapter's 4932 * internal timer, and causes us to delay far longer than 4933 * we should between interrupts. Instead, we write the ITR 4934 * value at the beginning of the next interrupt so the timing 4935 * ends up being correct. 4936 */ 4937 q_vector->itr_val = new_itr; 4938 q_vector->set_itr = 1; 4939 } 4940 } 4941 4942 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4943 u32 type_tucmd, u32 mss_l4len_idx) 4944 { 4945 struct e1000_adv_tx_context_desc *context_desc; 4946 u16 i = tx_ring->next_to_use; 4947 4948 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4949 4950 i++; 4951 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4952 4953 /* set bits to identify this as an advanced context descriptor */ 4954 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4955 4956 /* For 82575, context index must be unique per ring. */ 4957 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4958 mss_l4len_idx |= tx_ring->reg_idx << 4; 4959 4960 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4961 context_desc->seqnum_seed = 0; 4962 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4963 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4964 } 4965 4966 static int igb_tso(struct igb_ring *tx_ring, 4967 struct igb_tx_buffer *first, 4968 u8 *hdr_len) 4969 { 4970 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4971 struct sk_buff *skb = first->skb; 4972 union { 4973 struct iphdr *v4; 4974 struct ipv6hdr *v6; 4975 unsigned char *hdr; 4976 } ip; 4977 union { 4978 struct tcphdr *tcp; 4979 unsigned char *hdr; 4980 } l4; 4981 u32 paylen, l4_offset; 4982 int err; 4983 4984 if (skb->ip_summed != CHECKSUM_PARTIAL) 4985 return 0; 4986 4987 if (!skb_is_gso(skb)) 4988 return 0; 4989 4990 err = skb_cow_head(skb, 0); 4991 if (err < 0) 4992 return err; 4993 4994 ip.hdr = skb_network_header(skb); 4995 l4.hdr = skb_checksum_start(skb); 4996 4997 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4998 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4999 5000 /* initialize outer IP header fields */ 5001 if (ip.v4->version == 4) { 5002 unsigned char *csum_start = skb_checksum_start(skb); 5003 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5004 5005 /* IP header will have to cancel out any data that 5006 * is not a part of the outer IP header 5007 */ 5008 ip.v4->check = csum_fold(csum_partial(trans_start, 5009 csum_start - trans_start, 5010 0)); 5011 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5012 5013 ip.v4->tot_len = 0; 5014 first->tx_flags |= IGB_TX_FLAGS_TSO | 5015 IGB_TX_FLAGS_CSUM | 5016 IGB_TX_FLAGS_IPV4; 5017 } else { 5018 ip.v6->payload_len = 0; 5019 first->tx_flags |= IGB_TX_FLAGS_TSO | 5020 IGB_TX_FLAGS_CSUM; 5021 } 5022 5023 /* determine offset of inner transport header */ 5024 l4_offset = l4.hdr - skb->data; 5025 5026 /* compute length of segmentation header */ 5027 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5028 5029 /* remove payload length from inner checksum */ 5030 paylen = skb->len - l4_offset; 5031 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5032 5033 /* update gso size and bytecount with header size */ 5034 first->gso_segs = skb_shinfo(skb)->gso_segs; 5035 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5036 5037 /* MSS L4LEN IDX */ 5038 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5039 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5040 5041 /* VLAN MACLEN IPLEN */ 5042 vlan_macip_lens = l4.hdr - ip.hdr; 5043 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5044 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5045 5046 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5047 5048 return 1; 5049 } 5050 5051 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5052 { 5053 unsigned int offset = 0; 5054 5055 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5056 5057 return offset == skb_checksum_start_offset(skb); 5058 } 5059 5060 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5061 { 5062 struct sk_buff *skb = first->skb; 5063 u32 vlan_macip_lens = 0; 5064 u32 type_tucmd = 0; 5065 5066 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5067 csum_failed: 5068 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5069 return; 5070 goto no_csum; 5071 } 5072 5073 switch (skb->csum_offset) { 5074 case offsetof(struct tcphdr, check): 5075 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5076 /* fall through */ 5077 case offsetof(struct udphdr, check): 5078 break; 5079 case offsetof(struct sctphdr, checksum): 5080 /* validate that this is actually an SCTP request */ 5081 if (((first->protocol == htons(ETH_P_IP)) && 5082 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5083 ((first->protocol == htons(ETH_P_IPV6)) && 5084 igb_ipv6_csum_is_sctp(skb))) { 5085 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5086 break; 5087 } 5088 default: 5089 skb_checksum_help(skb); 5090 goto csum_failed; 5091 } 5092 5093 /* update TX checksum flag */ 5094 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5095 vlan_macip_lens = skb_checksum_start_offset(skb) - 5096 skb_network_offset(skb); 5097 no_csum: 5098 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5099 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5100 5101 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5102 } 5103 5104 #define IGB_SET_FLAG(_input, _flag, _result) \ 5105 ((_flag <= _result) ? \ 5106 ((u32)(_input & _flag) * (_result / _flag)) : \ 5107 ((u32)(_input & _flag) / (_flag / _result))) 5108 5109 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5110 { 5111 /* set type for advanced descriptor with frame checksum insertion */ 5112 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5113 E1000_ADVTXD_DCMD_DEXT | 5114 E1000_ADVTXD_DCMD_IFCS; 5115 5116 /* set HW vlan bit if vlan is present */ 5117 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5118 (E1000_ADVTXD_DCMD_VLE)); 5119 5120 /* set segmentation bits for TSO */ 5121 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5122 (E1000_ADVTXD_DCMD_TSE)); 5123 5124 /* set timestamp bit if present */ 5125 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5126 (E1000_ADVTXD_MAC_TSTAMP)); 5127 5128 /* insert frame checksum */ 5129 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5130 5131 return cmd_type; 5132 } 5133 5134 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5135 union e1000_adv_tx_desc *tx_desc, 5136 u32 tx_flags, unsigned int paylen) 5137 { 5138 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5139 5140 /* 82575 requires a unique index per ring */ 5141 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5142 olinfo_status |= tx_ring->reg_idx << 4; 5143 5144 /* insert L4 checksum */ 5145 olinfo_status |= IGB_SET_FLAG(tx_flags, 5146 IGB_TX_FLAGS_CSUM, 5147 (E1000_TXD_POPTS_TXSM << 8)); 5148 5149 /* insert IPv4 checksum */ 5150 olinfo_status |= IGB_SET_FLAG(tx_flags, 5151 IGB_TX_FLAGS_IPV4, 5152 (E1000_TXD_POPTS_IXSM << 8)); 5153 5154 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5155 } 5156 5157 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5158 { 5159 struct net_device *netdev = tx_ring->netdev; 5160 5161 netif_stop_subqueue(netdev, tx_ring->queue_index); 5162 5163 /* Herbert's original patch had: 5164 * smp_mb__after_netif_stop_queue(); 5165 * but since that doesn't exist yet, just open code it. 5166 */ 5167 smp_mb(); 5168 5169 /* We need to check again in a case another CPU has just 5170 * made room available. 5171 */ 5172 if (igb_desc_unused(tx_ring) < size) 5173 return -EBUSY; 5174 5175 /* A reprieve! */ 5176 netif_wake_subqueue(netdev, tx_ring->queue_index); 5177 5178 u64_stats_update_begin(&tx_ring->tx_syncp2); 5179 tx_ring->tx_stats.restart_queue2++; 5180 u64_stats_update_end(&tx_ring->tx_syncp2); 5181 5182 return 0; 5183 } 5184 5185 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5186 { 5187 if (igb_desc_unused(tx_ring) >= size) 5188 return 0; 5189 return __igb_maybe_stop_tx(tx_ring, size); 5190 } 5191 5192 static void igb_tx_map(struct igb_ring *tx_ring, 5193 struct igb_tx_buffer *first, 5194 const u8 hdr_len) 5195 { 5196 struct sk_buff *skb = first->skb; 5197 struct igb_tx_buffer *tx_buffer; 5198 union e1000_adv_tx_desc *tx_desc; 5199 struct skb_frag_struct *frag; 5200 dma_addr_t dma; 5201 unsigned int data_len, size; 5202 u32 tx_flags = first->tx_flags; 5203 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5204 u16 i = tx_ring->next_to_use; 5205 5206 tx_desc = IGB_TX_DESC(tx_ring, i); 5207 5208 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5209 5210 size = skb_headlen(skb); 5211 data_len = skb->data_len; 5212 5213 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5214 5215 tx_buffer = first; 5216 5217 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5218 if (dma_mapping_error(tx_ring->dev, dma)) 5219 goto dma_error; 5220 5221 /* record length, and DMA address */ 5222 dma_unmap_len_set(tx_buffer, len, size); 5223 dma_unmap_addr_set(tx_buffer, dma, dma); 5224 5225 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5226 5227 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5228 tx_desc->read.cmd_type_len = 5229 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5230 5231 i++; 5232 tx_desc++; 5233 if (i == tx_ring->count) { 5234 tx_desc = IGB_TX_DESC(tx_ring, 0); 5235 i = 0; 5236 } 5237 tx_desc->read.olinfo_status = 0; 5238 5239 dma += IGB_MAX_DATA_PER_TXD; 5240 size -= IGB_MAX_DATA_PER_TXD; 5241 5242 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5243 } 5244 5245 if (likely(!data_len)) 5246 break; 5247 5248 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5249 5250 i++; 5251 tx_desc++; 5252 if (i == tx_ring->count) { 5253 tx_desc = IGB_TX_DESC(tx_ring, 0); 5254 i = 0; 5255 } 5256 tx_desc->read.olinfo_status = 0; 5257 5258 size = skb_frag_size(frag); 5259 data_len -= size; 5260 5261 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5262 size, DMA_TO_DEVICE); 5263 5264 tx_buffer = &tx_ring->tx_buffer_info[i]; 5265 } 5266 5267 /* write last descriptor with RS and EOP bits */ 5268 cmd_type |= size | IGB_TXD_DCMD; 5269 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5270 5271 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5272 5273 /* set the timestamp */ 5274 first->time_stamp = jiffies; 5275 5276 /* Force memory writes to complete before letting h/w know there 5277 * are new descriptors to fetch. (Only applicable for weak-ordered 5278 * memory model archs, such as IA-64). 5279 * 5280 * We also need this memory barrier to make certain all of the 5281 * status bits have been updated before next_to_watch is written. 5282 */ 5283 wmb(); 5284 5285 /* set next_to_watch value indicating a packet is present */ 5286 first->next_to_watch = tx_desc; 5287 5288 i++; 5289 if (i == tx_ring->count) 5290 i = 0; 5291 5292 tx_ring->next_to_use = i; 5293 5294 /* Make sure there is space in the ring for the next send. */ 5295 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5296 5297 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5298 writel(i, tx_ring->tail); 5299 5300 /* we need this if more than one processor can write to our tail 5301 * at a time, it synchronizes IO on IA64/Altix systems 5302 */ 5303 mmiowb(); 5304 } 5305 return; 5306 5307 dma_error: 5308 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5309 tx_buffer = &tx_ring->tx_buffer_info[i]; 5310 5311 /* clear dma mappings for failed tx_buffer_info map */ 5312 while (tx_buffer != first) { 5313 if (dma_unmap_len(tx_buffer, len)) 5314 dma_unmap_page(tx_ring->dev, 5315 dma_unmap_addr(tx_buffer, dma), 5316 dma_unmap_len(tx_buffer, len), 5317 DMA_TO_DEVICE); 5318 dma_unmap_len_set(tx_buffer, len, 0); 5319 5320 if (i--) 5321 i += tx_ring->count; 5322 tx_buffer = &tx_ring->tx_buffer_info[i]; 5323 } 5324 5325 if (dma_unmap_len(tx_buffer, len)) 5326 dma_unmap_single(tx_ring->dev, 5327 dma_unmap_addr(tx_buffer, dma), 5328 dma_unmap_len(tx_buffer, len), 5329 DMA_TO_DEVICE); 5330 dma_unmap_len_set(tx_buffer, len, 0); 5331 5332 dev_kfree_skb_any(tx_buffer->skb); 5333 tx_buffer->skb = NULL; 5334 5335 tx_ring->next_to_use = i; 5336 } 5337 5338 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5339 struct igb_ring *tx_ring) 5340 { 5341 struct igb_tx_buffer *first; 5342 int tso; 5343 u32 tx_flags = 0; 5344 unsigned short f; 5345 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5346 __be16 protocol = vlan_get_protocol(skb); 5347 u8 hdr_len = 0; 5348 5349 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5350 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5351 * + 2 desc gap to keep tail from touching head, 5352 * + 1 desc for context descriptor, 5353 * otherwise try next time 5354 */ 5355 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5356 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5357 5358 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5359 /* this is a hard error */ 5360 return NETDEV_TX_BUSY; 5361 } 5362 5363 /* record the location of the first descriptor for this packet */ 5364 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5365 first->skb = skb; 5366 first->bytecount = skb->len; 5367 first->gso_segs = 1; 5368 5369 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5370 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5371 5372 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5373 &adapter->state)) { 5374 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5375 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5376 5377 adapter->ptp_tx_skb = skb_get(skb); 5378 adapter->ptp_tx_start = jiffies; 5379 if (adapter->hw.mac.type == e1000_82576) 5380 schedule_work(&adapter->ptp_tx_work); 5381 } 5382 } 5383 5384 skb_tx_timestamp(skb); 5385 5386 if (skb_vlan_tag_present(skb)) { 5387 tx_flags |= IGB_TX_FLAGS_VLAN; 5388 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5389 } 5390 5391 /* record initial flags and protocol */ 5392 first->tx_flags = tx_flags; 5393 first->protocol = protocol; 5394 5395 tso = igb_tso(tx_ring, first, &hdr_len); 5396 if (tso < 0) 5397 goto out_drop; 5398 else if (!tso) 5399 igb_tx_csum(tx_ring, first); 5400 5401 igb_tx_map(tx_ring, first, hdr_len); 5402 5403 return NETDEV_TX_OK; 5404 5405 out_drop: 5406 dev_kfree_skb_any(first->skb); 5407 first->skb = NULL; 5408 5409 return NETDEV_TX_OK; 5410 } 5411 5412 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5413 struct sk_buff *skb) 5414 { 5415 unsigned int r_idx = skb->queue_mapping; 5416 5417 if (r_idx >= adapter->num_tx_queues) 5418 r_idx = r_idx % adapter->num_tx_queues; 5419 5420 return adapter->tx_ring[r_idx]; 5421 } 5422 5423 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5424 struct net_device *netdev) 5425 { 5426 struct igb_adapter *adapter = netdev_priv(netdev); 5427 5428 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5429 * in order to meet this minimum size requirement. 5430 */ 5431 if (skb_put_padto(skb, 17)) 5432 return NETDEV_TX_OK; 5433 5434 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5435 } 5436 5437 /** 5438 * igb_tx_timeout - Respond to a Tx Hang 5439 * @netdev: network interface device structure 5440 **/ 5441 static void igb_tx_timeout(struct net_device *netdev) 5442 { 5443 struct igb_adapter *adapter = netdev_priv(netdev); 5444 struct e1000_hw *hw = &adapter->hw; 5445 5446 /* Do the reset outside of interrupt context */ 5447 adapter->tx_timeout_count++; 5448 5449 if (hw->mac.type >= e1000_82580) 5450 hw->dev_spec._82575.global_device_reset = true; 5451 5452 schedule_work(&adapter->reset_task); 5453 wr32(E1000_EICS, 5454 (adapter->eims_enable_mask & ~adapter->eims_other)); 5455 } 5456 5457 static void igb_reset_task(struct work_struct *work) 5458 { 5459 struct igb_adapter *adapter; 5460 adapter = container_of(work, struct igb_adapter, reset_task); 5461 5462 igb_dump(adapter); 5463 netdev_err(adapter->netdev, "Reset adapter\n"); 5464 igb_reinit_locked(adapter); 5465 } 5466 5467 /** 5468 * igb_get_stats64 - Get System Network Statistics 5469 * @netdev: network interface device structure 5470 * @stats: rtnl_link_stats64 pointer 5471 **/ 5472 static void igb_get_stats64(struct net_device *netdev, 5473 struct rtnl_link_stats64 *stats) 5474 { 5475 struct igb_adapter *adapter = netdev_priv(netdev); 5476 5477 spin_lock(&adapter->stats64_lock); 5478 igb_update_stats(adapter, &adapter->stats64); 5479 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5480 spin_unlock(&adapter->stats64_lock); 5481 } 5482 5483 /** 5484 * igb_change_mtu - Change the Maximum Transfer Unit 5485 * @netdev: network interface device structure 5486 * @new_mtu: new value for maximum frame size 5487 * 5488 * Returns 0 on success, negative on failure 5489 **/ 5490 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5491 { 5492 struct igb_adapter *adapter = netdev_priv(netdev); 5493 struct pci_dev *pdev = adapter->pdev; 5494 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5495 5496 /* adjust max frame to be at least the size of a standard frame */ 5497 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5498 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5499 5500 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5501 usleep_range(1000, 2000); 5502 5503 /* igb_down has a dependency on max_frame_size */ 5504 adapter->max_frame_size = max_frame; 5505 5506 if (netif_running(netdev)) 5507 igb_down(adapter); 5508 5509 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5510 netdev->mtu, new_mtu); 5511 netdev->mtu = new_mtu; 5512 5513 if (netif_running(netdev)) 5514 igb_up(adapter); 5515 else 5516 igb_reset(adapter); 5517 5518 clear_bit(__IGB_RESETTING, &adapter->state); 5519 5520 return 0; 5521 } 5522 5523 /** 5524 * igb_update_stats - Update the board statistics counters 5525 * @adapter: board private structure 5526 **/ 5527 void igb_update_stats(struct igb_adapter *adapter, 5528 struct rtnl_link_stats64 *net_stats) 5529 { 5530 struct e1000_hw *hw = &adapter->hw; 5531 struct pci_dev *pdev = adapter->pdev; 5532 u32 reg, mpc; 5533 int i; 5534 u64 bytes, packets; 5535 unsigned int start; 5536 u64 _bytes, _packets; 5537 5538 /* Prevent stats update while adapter is being reset, or if the pci 5539 * connection is down. 5540 */ 5541 if (adapter->link_speed == 0) 5542 return; 5543 if (pci_channel_offline(pdev)) 5544 return; 5545 5546 bytes = 0; 5547 packets = 0; 5548 5549 rcu_read_lock(); 5550 for (i = 0; i < adapter->num_rx_queues; i++) { 5551 struct igb_ring *ring = adapter->rx_ring[i]; 5552 u32 rqdpc = rd32(E1000_RQDPC(i)); 5553 if (hw->mac.type >= e1000_i210) 5554 wr32(E1000_RQDPC(i), 0); 5555 5556 if (rqdpc) { 5557 ring->rx_stats.drops += rqdpc; 5558 net_stats->rx_fifo_errors += rqdpc; 5559 } 5560 5561 do { 5562 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5563 _bytes = ring->rx_stats.bytes; 5564 _packets = ring->rx_stats.packets; 5565 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5566 bytes += _bytes; 5567 packets += _packets; 5568 } 5569 5570 net_stats->rx_bytes = bytes; 5571 net_stats->rx_packets = packets; 5572 5573 bytes = 0; 5574 packets = 0; 5575 for (i = 0; i < adapter->num_tx_queues; i++) { 5576 struct igb_ring *ring = adapter->tx_ring[i]; 5577 do { 5578 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5579 _bytes = ring->tx_stats.bytes; 5580 _packets = ring->tx_stats.packets; 5581 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5582 bytes += _bytes; 5583 packets += _packets; 5584 } 5585 net_stats->tx_bytes = bytes; 5586 net_stats->tx_packets = packets; 5587 rcu_read_unlock(); 5588 5589 /* read stats registers */ 5590 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5591 adapter->stats.gprc += rd32(E1000_GPRC); 5592 adapter->stats.gorc += rd32(E1000_GORCL); 5593 rd32(E1000_GORCH); /* clear GORCL */ 5594 adapter->stats.bprc += rd32(E1000_BPRC); 5595 adapter->stats.mprc += rd32(E1000_MPRC); 5596 adapter->stats.roc += rd32(E1000_ROC); 5597 5598 adapter->stats.prc64 += rd32(E1000_PRC64); 5599 adapter->stats.prc127 += rd32(E1000_PRC127); 5600 adapter->stats.prc255 += rd32(E1000_PRC255); 5601 adapter->stats.prc511 += rd32(E1000_PRC511); 5602 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5603 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5604 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5605 adapter->stats.sec += rd32(E1000_SEC); 5606 5607 mpc = rd32(E1000_MPC); 5608 adapter->stats.mpc += mpc; 5609 net_stats->rx_fifo_errors += mpc; 5610 adapter->stats.scc += rd32(E1000_SCC); 5611 adapter->stats.ecol += rd32(E1000_ECOL); 5612 adapter->stats.mcc += rd32(E1000_MCC); 5613 adapter->stats.latecol += rd32(E1000_LATECOL); 5614 adapter->stats.dc += rd32(E1000_DC); 5615 adapter->stats.rlec += rd32(E1000_RLEC); 5616 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5617 adapter->stats.xontxc += rd32(E1000_XONTXC); 5618 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5619 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5620 adapter->stats.fcruc += rd32(E1000_FCRUC); 5621 adapter->stats.gptc += rd32(E1000_GPTC); 5622 adapter->stats.gotc += rd32(E1000_GOTCL); 5623 rd32(E1000_GOTCH); /* clear GOTCL */ 5624 adapter->stats.rnbc += rd32(E1000_RNBC); 5625 adapter->stats.ruc += rd32(E1000_RUC); 5626 adapter->stats.rfc += rd32(E1000_RFC); 5627 adapter->stats.rjc += rd32(E1000_RJC); 5628 adapter->stats.tor += rd32(E1000_TORH); 5629 adapter->stats.tot += rd32(E1000_TOTH); 5630 adapter->stats.tpr += rd32(E1000_TPR); 5631 5632 adapter->stats.ptc64 += rd32(E1000_PTC64); 5633 adapter->stats.ptc127 += rd32(E1000_PTC127); 5634 adapter->stats.ptc255 += rd32(E1000_PTC255); 5635 adapter->stats.ptc511 += rd32(E1000_PTC511); 5636 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5637 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5638 5639 adapter->stats.mptc += rd32(E1000_MPTC); 5640 adapter->stats.bptc += rd32(E1000_BPTC); 5641 5642 adapter->stats.tpt += rd32(E1000_TPT); 5643 adapter->stats.colc += rd32(E1000_COLC); 5644 5645 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5646 /* read internal phy specific stats */ 5647 reg = rd32(E1000_CTRL_EXT); 5648 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5649 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5650 5651 /* this stat has invalid values on i210/i211 */ 5652 if ((hw->mac.type != e1000_i210) && 5653 (hw->mac.type != e1000_i211)) 5654 adapter->stats.tncrs += rd32(E1000_TNCRS); 5655 } 5656 5657 adapter->stats.tsctc += rd32(E1000_TSCTC); 5658 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5659 5660 adapter->stats.iac += rd32(E1000_IAC); 5661 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5662 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5663 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5664 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5665 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5666 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5667 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5668 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5669 5670 /* Fill out the OS statistics structure */ 5671 net_stats->multicast = adapter->stats.mprc; 5672 net_stats->collisions = adapter->stats.colc; 5673 5674 /* Rx Errors */ 5675 5676 /* RLEC on some newer hardware can be incorrect so build 5677 * our own version based on RUC and ROC 5678 */ 5679 net_stats->rx_errors = adapter->stats.rxerrc + 5680 adapter->stats.crcerrs + adapter->stats.algnerrc + 5681 adapter->stats.ruc + adapter->stats.roc + 5682 adapter->stats.cexterr; 5683 net_stats->rx_length_errors = adapter->stats.ruc + 5684 adapter->stats.roc; 5685 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5686 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5687 net_stats->rx_missed_errors = adapter->stats.mpc; 5688 5689 /* Tx Errors */ 5690 net_stats->tx_errors = adapter->stats.ecol + 5691 adapter->stats.latecol; 5692 net_stats->tx_aborted_errors = adapter->stats.ecol; 5693 net_stats->tx_window_errors = adapter->stats.latecol; 5694 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5695 5696 /* Tx Dropped needs to be maintained elsewhere */ 5697 5698 /* Management Stats */ 5699 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5700 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5701 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5702 5703 /* OS2BMC Stats */ 5704 reg = rd32(E1000_MANC); 5705 if (reg & E1000_MANC_EN_BMC2OS) { 5706 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5707 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5708 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5709 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5710 } 5711 } 5712 5713 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5714 { 5715 struct e1000_hw *hw = &adapter->hw; 5716 struct ptp_clock_event event; 5717 struct timespec64 ts; 5718 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5719 5720 if (tsicr & TSINTR_SYS_WRAP) { 5721 event.type = PTP_CLOCK_PPS; 5722 if (adapter->ptp_caps.pps) 5723 ptp_clock_event(adapter->ptp_clock, &event); 5724 else 5725 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5726 ack |= TSINTR_SYS_WRAP; 5727 } 5728 5729 if (tsicr & E1000_TSICR_TXTS) { 5730 /* retrieve hardware timestamp */ 5731 schedule_work(&adapter->ptp_tx_work); 5732 ack |= E1000_TSICR_TXTS; 5733 } 5734 5735 if (tsicr & TSINTR_TT0) { 5736 spin_lock(&adapter->tmreg_lock); 5737 ts = timespec64_add(adapter->perout[0].start, 5738 adapter->perout[0].period); 5739 /* u32 conversion of tv_sec is safe until y2106 */ 5740 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5741 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5742 tsauxc = rd32(E1000_TSAUXC); 5743 tsauxc |= TSAUXC_EN_TT0; 5744 wr32(E1000_TSAUXC, tsauxc); 5745 adapter->perout[0].start = ts; 5746 spin_unlock(&adapter->tmreg_lock); 5747 ack |= TSINTR_TT0; 5748 } 5749 5750 if (tsicr & TSINTR_TT1) { 5751 spin_lock(&adapter->tmreg_lock); 5752 ts = timespec64_add(adapter->perout[1].start, 5753 adapter->perout[1].period); 5754 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5755 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5756 tsauxc = rd32(E1000_TSAUXC); 5757 tsauxc |= TSAUXC_EN_TT1; 5758 wr32(E1000_TSAUXC, tsauxc); 5759 adapter->perout[1].start = ts; 5760 spin_unlock(&adapter->tmreg_lock); 5761 ack |= TSINTR_TT1; 5762 } 5763 5764 if (tsicr & TSINTR_AUTT0) { 5765 nsec = rd32(E1000_AUXSTMPL0); 5766 sec = rd32(E1000_AUXSTMPH0); 5767 event.type = PTP_CLOCK_EXTTS; 5768 event.index = 0; 5769 event.timestamp = sec * 1000000000ULL + nsec; 5770 ptp_clock_event(adapter->ptp_clock, &event); 5771 ack |= TSINTR_AUTT0; 5772 } 5773 5774 if (tsicr & TSINTR_AUTT1) { 5775 nsec = rd32(E1000_AUXSTMPL1); 5776 sec = rd32(E1000_AUXSTMPH1); 5777 event.type = PTP_CLOCK_EXTTS; 5778 event.index = 1; 5779 event.timestamp = sec * 1000000000ULL + nsec; 5780 ptp_clock_event(adapter->ptp_clock, &event); 5781 ack |= TSINTR_AUTT1; 5782 } 5783 5784 /* acknowledge the interrupts */ 5785 wr32(E1000_TSICR, ack); 5786 } 5787 5788 static irqreturn_t igb_msix_other(int irq, void *data) 5789 { 5790 struct igb_adapter *adapter = data; 5791 struct e1000_hw *hw = &adapter->hw; 5792 u32 icr = rd32(E1000_ICR); 5793 /* reading ICR causes bit 31 of EICR to be cleared */ 5794 5795 if (icr & E1000_ICR_DRSTA) 5796 schedule_work(&adapter->reset_task); 5797 5798 if (icr & E1000_ICR_DOUTSYNC) { 5799 /* HW is reporting DMA is out of sync */ 5800 adapter->stats.doosync++; 5801 /* The DMA Out of Sync is also indication of a spoof event 5802 * in IOV mode. Check the Wrong VM Behavior register to 5803 * see if it is really a spoof event. 5804 */ 5805 igb_check_wvbr(adapter); 5806 } 5807 5808 /* Check for a mailbox event */ 5809 if (icr & E1000_ICR_VMMB) 5810 igb_msg_task(adapter); 5811 5812 if (icr & E1000_ICR_LSC) { 5813 hw->mac.get_link_status = 1; 5814 /* guard against interrupt when we're going down */ 5815 if (!test_bit(__IGB_DOWN, &adapter->state)) 5816 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5817 } 5818 5819 if (icr & E1000_ICR_TS) 5820 igb_tsync_interrupt(adapter); 5821 5822 wr32(E1000_EIMS, adapter->eims_other); 5823 5824 return IRQ_HANDLED; 5825 } 5826 5827 static void igb_write_itr(struct igb_q_vector *q_vector) 5828 { 5829 struct igb_adapter *adapter = q_vector->adapter; 5830 u32 itr_val = q_vector->itr_val & 0x7FFC; 5831 5832 if (!q_vector->set_itr) 5833 return; 5834 5835 if (!itr_val) 5836 itr_val = 0x4; 5837 5838 if (adapter->hw.mac.type == e1000_82575) 5839 itr_val |= itr_val << 16; 5840 else 5841 itr_val |= E1000_EITR_CNT_IGNR; 5842 5843 writel(itr_val, q_vector->itr_register); 5844 q_vector->set_itr = 0; 5845 } 5846 5847 static irqreturn_t igb_msix_ring(int irq, void *data) 5848 { 5849 struct igb_q_vector *q_vector = data; 5850 5851 /* Write the ITR value calculated from the previous interrupt. */ 5852 igb_write_itr(q_vector); 5853 5854 napi_schedule(&q_vector->napi); 5855 5856 return IRQ_HANDLED; 5857 } 5858 5859 #ifdef CONFIG_IGB_DCA 5860 static void igb_update_tx_dca(struct igb_adapter *adapter, 5861 struct igb_ring *tx_ring, 5862 int cpu) 5863 { 5864 struct e1000_hw *hw = &adapter->hw; 5865 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5866 5867 if (hw->mac.type != e1000_82575) 5868 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5869 5870 /* We can enable relaxed ordering for reads, but not writes when 5871 * DCA is enabled. This is due to a known issue in some chipsets 5872 * which will cause the DCA tag to be cleared. 5873 */ 5874 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5875 E1000_DCA_TXCTRL_DATA_RRO_EN | 5876 E1000_DCA_TXCTRL_DESC_DCA_EN; 5877 5878 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5879 } 5880 5881 static void igb_update_rx_dca(struct igb_adapter *adapter, 5882 struct igb_ring *rx_ring, 5883 int cpu) 5884 { 5885 struct e1000_hw *hw = &adapter->hw; 5886 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5887 5888 if (hw->mac.type != e1000_82575) 5889 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5890 5891 /* We can enable relaxed ordering for reads, but not writes when 5892 * DCA is enabled. This is due to a known issue in some chipsets 5893 * which will cause the DCA tag to be cleared. 5894 */ 5895 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5896 E1000_DCA_RXCTRL_DESC_DCA_EN; 5897 5898 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5899 } 5900 5901 static void igb_update_dca(struct igb_q_vector *q_vector) 5902 { 5903 struct igb_adapter *adapter = q_vector->adapter; 5904 int cpu = get_cpu(); 5905 5906 if (q_vector->cpu == cpu) 5907 goto out_no_update; 5908 5909 if (q_vector->tx.ring) 5910 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5911 5912 if (q_vector->rx.ring) 5913 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5914 5915 q_vector->cpu = cpu; 5916 out_no_update: 5917 put_cpu(); 5918 } 5919 5920 static void igb_setup_dca(struct igb_adapter *adapter) 5921 { 5922 struct e1000_hw *hw = &adapter->hw; 5923 int i; 5924 5925 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5926 return; 5927 5928 /* Always use CB2 mode, difference is masked in the CB driver. */ 5929 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5930 5931 for (i = 0; i < adapter->num_q_vectors; i++) { 5932 adapter->q_vector[i]->cpu = -1; 5933 igb_update_dca(adapter->q_vector[i]); 5934 } 5935 } 5936 5937 static int __igb_notify_dca(struct device *dev, void *data) 5938 { 5939 struct net_device *netdev = dev_get_drvdata(dev); 5940 struct igb_adapter *adapter = netdev_priv(netdev); 5941 struct pci_dev *pdev = adapter->pdev; 5942 struct e1000_hw *hw = &adapter->hw; 5943 unsigned long event = *(unsigned long *)data; 5944 5945 switch (event) { 5946 case DCA_PROVIDER_ADD: 5947 /* if already enabled, don't do it again */ 5948 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5949 break; 5950 if (dca_add_requester(dev) == 0) { 5951 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5952 dev_info(&pdev->dev, "DCA enabled\n"); 5953 igb_setup_dca(adapter); 5954 break; 5955 } 5956 /* Fall Through since DCA is disabled. */ 5957 case DCA_PROVIDER_REMOVE: 5958 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5959 /* without this a class_device is left 5960 * hanging around in the sysfs model 5961 */ 5962 dca_remove_requester(dev); 5963 dev_info(&pdev->dev, "DCA disabled\n"); 5964 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5965 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5966 } 5967 break; 5968 } 5969 5970 return 0; 5971 } 5972 5973 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5974 void *p) 5975 { 5976 int ret_val; 5977 5978 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5979 __igb_notify_dca); 5980 5981 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5982 } 5983 #endif /* CONFIG_IGB_DCA */ 5984 5985 #ifdef CONFIG_PCI_IOV 5986 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5987 { 5988 unsigned char mac_addr[ETH_ALEN]; 5989 5990 eth_zero_addr(mac_addr); 5991 igb_set_vf_mac(adapter, vf, mac_addr); 5992 5993 /* By default spoof check is enabled for all VFs */ 5994 adapter->vf_data[vf].spoofchk_enabled = true; 5995 5996 return 0; 5997 } 5998 5999 #endif 6000 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6001 { 6002 struct e1000_hw *hw = &adapter->hw; 6003 u32 ping; 6004 int i; 6005 6006 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6007 ping = E1000_PF_CONTROL_MSG; 6008 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6009 ping |= E1000_VT_MSGTYPE_CTS; 6010 igb_write_mbx(hw, &ping, 1, i); 6011 } 6012 } 6013 6014 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6015 { 6016 struct e1000_hw *hw = &adapter->hw; 6017 u32 vmolr = rd32(E1000_VMOLR(vf)); 6018 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6019 6020 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6021 IGB_VF_FLAG_MULTI_PROMISC); 6022 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6023 6024 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6025 vmolr |= E1000_VMOLR_MPME; 6026 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6027 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6028 } else { 6029 /* if we have hashes and we are clearing a multicast promisc 6030 * flag we need to write the hashes to the MTA as this step 6031 * was previously skipped 6032 */ 6033 if (vf_data->num_vf_mc_hashes > 30) { 6034 vmolr |= E1000_VMOLR_MPME; 6035 } else if (vf_data->num_vf_mc_hashes) { 6036 int j; 6037 6038 vmolr |= E1000_VMOLR_ROMPE; 6039 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6040 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6041 } 6042 } 6043 6044 wr32(E1000_VMOLR(vf), vmolr); 6045 6046 /* there are flags left unprocessed, likely not supported */ 6047 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6048 return -EINVAL; 6049 6050 return 0; 6051 } 6052 6053 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6054 u32 *msgbuf, u32 vf) 6055 { 6056 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6057 u16 *hash_list = (u16 *)&msgbuf[1]; 6058 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6059 int i; 6060 6061 /* salt away the number of multicast addresses assigned 6062 * to this VF for later use to restore when the PF multi cast 6063 * list changes 6064 */ 6065 vf_data->num_vf_mc_hashes = n; 6066 6067 /* only up to 30 hash values supported */ 6068 if (n > 30) 6069 n = 30; 6070 6071 /* store the hashes for later use */ 6072 for (i = 0; i < n; i++) 6073 vf_data->vf_mc_hashes[i] = hash_list[i]; 6074 6075 /* Flush and reset the mta with the new values */ 6076 igb_set_rx_mode(adapter->netdev); 6077 6078 return 0; 6079 } 6080 6081 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6082 { 6083 struct e1000_hw *hw = &adapter->hw; 6084 struct vf_data_storage *vf_data; 6085 int i, j; 6086 6087 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6088 u32 vmolr = rd32(E1000_VMOLR(i)); 6089 6090 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6091 6092 vf_data = &adapter->vf_data[i]; 6093 6094 if ((vf_data->num_vf_mc_hashes > 30) || 6095 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6096 vmolr |= E1000_VMOLR_MPME; 6097 } else if (vf_data->num_vf_mc_hashes) { 6098 vmolr |= E1000_VMOLR_ROMPE; 6099 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6100 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6101 } 6102 wr32(E1000_VMOLR(i), vmolr); 6103 } 6104 } 6105 6106 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6107 { 6108 struct e1000_hw *hw = &adapter->hw; 6109 u32 pool_mask, vlvf_mask, i; 6110 6111 /* create mask for VF and other pools */ 6112 pool_mask = E1000_VLVF_POOLSEL_MASK; 6113 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6114 6115 /* drop PF from pool bits */ 6116 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6117 adapter->vfs_allocated_count); 6118 6119 /* Find the vlan filter for this id */ 6120 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6121 u32 vlvf = rd32(E1000_VLVF(i)); 6122 u32 vfta_mask, vid, vfta; 6123 6124 /* remove the vf from the pool */ 6125 if (!(vlvf & vlvf_mask)) 6126 continue; 6127 6128 /* clear out bit from VLVF */ 6129 vlvf ^= vlvf_mask; 6130 6131 /* if other pools are present, just remove ourselves */ 6132 if (vlvf & pool_mask) 6133 goto update_vlvfb; 6134 6135 /* if PF is present, leave VFTA */ 6136 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6137 goto update_vlvf; 6138 6139 vid = vlvf & E1000_VLVF_VLANID_MASK; 6140 vfta_mask = BIT(vid % 32); 6141 6142 /* clear bit from VFTA */ 6143 vfta = adapter->shadow_vfta[vid / 32]; 6144 if (vfta & vfta_mask) 6145 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6146 update_vlvf: 6147 /* clear pool selection enable */ 6148 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6149 vlvf &= E1000_VLVF_POOLSEL_MASK; 6150 else 6151 vlvf = 0; 6152 update_vlvfb: 6153 /* clear pool bits */ 6154 wr32(E1000_VLVF(i), vlvf); 6155 } 6156 } 6157 6158 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6159 { 6160 u32 vlvf; 6161 int idx; 6162 6163 /* short cut the special case */ 6164 if (vlan == 0) 6165 return 0; 6166 6167 /* Search for the VLAN id in the VLVF entries */ 6168 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6169 vlvf = rd32(E1000_VLVF(idx)); 6170 if ((vlvf & VLAN_VID_MASK) == vlan) 6171 break; 6172 } 6173 6174 return idx; 6175 } 6176 6177 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6178 { 6179 struct e1000_hw *hw = &adapter->hw; 6180 u32 bits, pf_id; 6181 int idx; 6182 6183 idx = igb_find_vlvf_entry(hw, vid); 6184 if (!idx) 6185 return; 6186 6187 /* See if any other pools are set for this VLAN filter 6188 * entry other than the PF. 6189 */ 6190 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6191 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6192 bits &= rd32(E1000_VLVF(idx)); 6193 6194 /* Disable the filter so this falls into the default pool. */ 6195 if (!bits) { 6196 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6197 wr32(E1000_VLVF(idx), BIT(pf_id)); 6198 else 6199 wr32(E1000_VLVF(idx), 0); 6200 } 6201 } 6202 6203 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6204 bool add, u32 vf) 6205 { 6206 int pf_id = adapter->vfs_allocated_count; 6207 struct e1000_hw *hw = &adapter->hw; 6208 int err; 6209 6210 /* If VLAN overlaps with one the PF is currently monitoring make 6211 * sure that we are able to allocate a VLVF entry. This may be 6212 * redundant but it guarantees PF will maintain visibility to 6213 * the VLAN. 6214 */ 6215 if (add && test_bit(vid, adapter->active_vlans)) { 6216 err = igb_vfta_set(hw, vid, pf_id, true, false); 6217 if (err) 6218 return err; 6219 } 6220 6221 err = igb_vfta_set(hw, vid, vf, add, false); 6222 6223 if (add && !err) 6224 return err; 6225 6226 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6227 * we may need to drop the PF pool bit in order to allow us to free 6228 * up the VLVF resources. 6229 */ 6230 if (test_bit(vid, adapter->active_vlans) || 6231 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6232 igb_update_pf_vlvf(adapter, vid); 6233 6234 return err; 6235 } 6236 6237 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6238 { 6239 struct e1000_hw *hw = &adapter->hw; 6240 6241 if (vid) 6242 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6243 else 6244 wr32(E1000_VMVIR(vf), 0); 6245 } 6246 6247 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6248 u16 vlan, u8 qos) 6249 { 6250 int err; 6251 6252 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6253 if (err) 6254 return err; 6255 6256 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6257 igb_set_vmolr(adapter, vf, !vlan); 6258 6259 /* revoke access to previous VLAN */ 6260 if (vlan != adapter->vf_data[vf].pf_vlan) 6261 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6262 false, vf); 6263 6264 adapter->vf_data[vf].pf_vlan = vlan; 6265 adapter->vf_data[vf].pf_qos = qos; 6266 igb_set_vf_vlan_strip(adapter, vf, true); 6267 dev_info(&adapter->pdev->dev, 6268 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6269 if (test_bit(__IGB_DOWN, &adapter->state)) { 6270 dev_warn(&adapter->pdev->dev, 6271 "The VF VLAN has been set, but the PF device is not up.\n"); 6272 dev_warn(&adapter->pdev->dev, 6273 "Bring the PF device up before attempting to use the VF device.\n"); 6274 } 6275 6276 return err; 6277 } 6278 6279 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6280 { 6281 /* Restore tagless access via VLAN 0 */ 6282 igb_set_vf_vlan(adapter, 0, true, vf); 6283 6284 igb_set_vmvir(adapter, 0, vf); 6285 igb_set_vmolr(adapter, vf, true); 6286 6287 /* Remove any PF assigned VLAN */ 6288 if (adapter->vf_data[vf].pf_vlan) 6289 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6290 false, vf); 6291 6292 adapter->vf_data[vf].pf_vlan = 0; 6293 adapter->vf_data[vf].pf_qos = 0; 6294 igb_set_vf_vlan_strip(adapter, vf, false); 6295 6296 return 0; 6297 } 6298 6299 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6300 u16 vlan, u8 qos, __be16 vlan_proto) 6301 { 6302 struct igb_adapter *adapter = netdev_priv(netdev); 6303 6304 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6305 return -EINVAL; 6306 6307 if (vlan_proto != htons(ETH_P_8021Q)) 6308 return -EPROTONOSUPPORT; 6309 6310 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6311 igb_disable_port_vlan(adapter, vf); 6312 } 6313 6314 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6315 { 6316 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6317 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6318 int ret; 6319 6320 if (adapter->vf_data[vf].pf_vlan) 6321 return -1; 6322 6323 /* VLAN 0 is a special case, don't allow it to be removed */ 6324 if (!vid && !add) 6325 return 0; 6326 6327 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6328 if (!ret) 6329 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6330 return ret; 6331 } 6332 6333 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6334 { 6335 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6336 6337 /* clear flags - except flag that indicates PF has set the MAC */ 6338 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6339 vf_data->last_nack = jiffies; 6340 6341 /* reset vlans for device */ 6342 igb_clear_vf_vfta(adapter, vf); 6343 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6344 igb_set_vmvir(adapter, vf_data->pf_vlan | 6345 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6346 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6347 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6348 6349 /* reset multicast table array for vf */ 6350 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6351 6352 /* Flush and reset the mta with the new values */ 6353 igb_set_rx_mode(adapter->netdev); 6354 } 6355 6356 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6357 { 6358 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6359 6360 /* clear mac address as we were hotplug removed/added */ 6361 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6362 eth_zero_addr(vf_mac); 6363 6364 /* process remaining reset events */ 6365 igb_vf_reset(adapter, vf); 6366 } 6367 6368 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6369 { 6370 struct e1000_hw *hw = &adapter->hw; 6371 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6372 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6373 u32 reg, msgbuf[3]; 6374 u8 *addr = (u8 *)(&msgbuf[1]); 6375 6376 /* process all the same items cleared in a function level reset */ 6377 igb_vf_reset(adapter, vf); 6378 6379 /* set vf mac address */ 6380 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6381 6382 /* enable transmit and receive for vf */ 6383 reg = rd32(E1000_VFTE); 6384 wr32(E1000_VFTE, reg | BIT(vf)); 6385 reg = rd32(E1000_VFRE); 6386 wr32(E1000_VFRE, reg | BIT(vf)); 6387 6388 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6389 6390 /* reply to reset with ack and vf mac address */ 6391 if (!is_zero_ether_addr(vf_mac)) { 6392 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6393 memcpy(addr, vf_mac, ETH_ALEN); 6394 } else { 6395 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6396 } 6397 igb_write_mbx(hw, msgbuf, 3, vf); 6398 } 6399 6400 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6401 { 6402 /* The VF MAC Address is stored in a packed array of bytes 6403 * starting at the second 32 bit word of the msg array 6404 */ 6405 unsigned char *addr = (char *)&msg[1]; 6406 int err = -1; 6407 6408 if (is_valid_ether_addr(addr)) 6409 err = igb_set_vf_mac(adapter, vf, addr); 6410 6411 return err; 6412 } 6413 6414 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6415 { 6416 struct e1000_hw *hw = &adapter->hw; 6417 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6418 u32 msg = E1000_VT_MSGTYPE_NACK; 6419 6420 /* if device isn't clear to send it shouldn't be reading either */ 6421 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6422 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6423 igb_write_mbx(hw, &msg, 1, vf); 6424 vf_data->last_nack = jiffies; 6425 } 6426 } 6427 6428 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6429 { 6430 struct pci_dev *pdev = adapter->pdev; 6431 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6432 struct e1000_hw *hw = &adapter->hw; 6433 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6434 s32 retval; 6435 6436 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6437 6438 if (retval) { 6439 /* if receive failed revoke VF CTS stats and restart init */ 6440 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6441 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6442 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6443 return; 6444 goto out; 6445 } 6446 6447 /* this is a message we already processed, do nothing */ 6448 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6449 return; 6450 6451 /* until the vf completes a reset it should not be 6452 * allowed to start any configuration. 6453 */ 6454 if (msgbuf[0] == E1000_VF_RESET) { 6455 igb_vf_reset_msg(adapter, vf); 6456 return; 6457 } 6458 6459 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6460 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6461 return; 6462 retval = -1; 6463 goto out; 6464 } 6465 6466 switch ((msgbuf[0] & 0xFFFF)) { 6467 case E1000_VF_SET_MAC_ADDR: 6468 retval = -EINVAL; 6469 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6470 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6471 else 6472 dev_warn(&pdev->dev, 6473 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6474 vf); 6475 break; 6476 case E1000_VF_SET_PROMISC: 6477 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6478 break; 6479 case E1000_VF_SET_MULTICAST: 6480 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6481 break; 6482 case E1000_VF_SET_LPE: 6483 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6484 break; 6485 case E1000_VF_SET_VLAN: 6486 retval = -1; 6487 if (vf_data->pf_vlan) 6488 dev_warn(&pdev->dev, 6489 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6490 vf); 6491 else 6492 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6493 break; 6494 default: 6495 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6496 retval = -1; 6497 break; 6498 } 6499 6500 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6501 out: 6502 /* notify the VF of the results of what it sent us */ 6503 if (retval) 6504 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6505 else 6506 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6507 6508 igb_write_mbx(hw, msgbuf, 1, vf); 6509 } 6510 6511 static void igb_msg_task(struct igb_adapter *adapter) 6512 { 6513 struct e1000_hw *hw = &adapter->hw; 6514 u32 vf; 6515 6516 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6517 /* process any reset requests */ 6518 if (!igb_check_for_rst(hw, vf)) 6519 igb_vf_reset_event(adapter, vf); 6520 6521 /* process any messages pending */ 6522 if (!igb_check_for_msg(hw, vf)) 6523 igb_rcv_msg_from_vf(adapter, vf); 6524 6525 /* process any acks */ 6526 if (!igb_check_for_ack(hw, vf)) 6527 igb_rcv_ack_from_vf(adapter, vf); 6528 } 6529 } 6530 6531 /** 6532 * igb_set_uta - Set unicast filter table address 6533 * @adapter: board private structure 6534 * @set: boolean indicating if we are setting or clearing bits 6535 * 6536 * The unicast table address is a register array of 32-bit registers. 6537 * The table is meant to be used in a way similar to how the MTA is used 6538 * however due to certain limitations in the hardware it is necessary to 6539 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6540 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6541 **/ 6542 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6543 { 6544 struct e1000_hw *hw = &adapter->hw; 6545 u32 uta = set ? ~0 : 0; 6546 int i; 6547 6548 /* we only need to do this if VMDq is enabled */ 6549 if (!adapter->vfs_allocated_count) 6550 return; 6551 6552 for (i = hw->mac.uta_reg_count; i--;) 6553 array_wr32(E1000_UTA, i, uta); 6554 } 6555 6556 /** 6557 * igb_intr_msi - Interrupt Handler 6558 * @irq: interrupt number 6559 * @data: pointer to a network interface device structure 6560 **/ 6561 static irqreturn_t igb_intr_msi(int irq, void *data) 6562 { 6563 struct igb_adapter *adapter = data; 6564 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6565 struct e1000_hw *hw = &adapter->hw; 6566 /* read ICR disables interrupts using IAM */ 6567 u32 icr = rd32(E1000_ICR); 6568 6569 igb_write_itr(q_vector); 6570 6571 if (icr & E1000_ICR_DRSTA) 6572 schedule_work(&adapter->reset_task); 6573 6574 if (icr & E1000_ICR_DOUTSYNC) { 6575 /* HW is reporting DMA is out of sync */ 6576 adapter->stats.doosync++; 6577 } 6578 6579 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6580 hw->mac.get_link_status = 1; 6581 if (!test_bit(__IGB_DOWN, &adapter->state)) 6582 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6583 } 6584 6585 if (icr & E1000_ICR_TS) 6586 igb_tsync_interrupt(adapter); 6587 6588 napi_schedule(&q_vector->napi); 6589 6590 return IRQ_HANDLED; 6591 } 6592 6593 /** 6594 * igb_intr - Legacy Interrupt Handler 6595 * @irq: interrupt number 6596 * @data: pointer to a network interface device structure 6597 **/ 6598 static irqreturn_t igb_intr(int irq, void *data) 6599 { 6600 struct igb_adapter *adapter = data; 6601 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6602 struct e1000_hw *hw = &adapter->hw; 6603 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6604 * need for the IMC write 6605 */ 6606 u32 icr = rd32(E1000_ICR); 6607 6608 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6609 * not set, then the adapter didn't send an interrupt 6610 */ 6611 if (!(icr & E1000_ICR_INT_ASSERTED)) 6612 return IRQ_NONE; 6613 6614 igb_write_itr(q_vector); 6615 6616 if (icr & E1000_ICR_DRSTA) 6617 schedule_work(&adapter->reset_task); 6618 6619 if (icr & E1000_ICR_DOUTSYNC) { 6620 /* HW is reporting DMA is out of sync */ 6621 adapter->stats.doosync++; 6622 } 6623 6624 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6625 hw->mac.get_link_status = 1; 6626 /* guard against interrupt when we're going down */ 6627 if (!test_bit(__IGB_DOWN, &adapter->state)) 6628 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6629 } 6630 6631 if (icr & E1000_ICR_TS) 6632 igb_tsync_interrupt(adapter); 6633 6634 napi_schedule(&q_vector->napi); 6635 6636 return IRQ_HANDLED; 6637 } 6638 6639 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6640 { 6641 struct igb_adapter *adapter = q_vector->adapter; 6642 struct e1000_hw *hw = &adapter->hw; 6643 6644 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6645 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6646 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6647 igb_set_itr(q_vector); 6648 else 6649 igb_update_ring_itr(q_vector); 6650 } 6651 6652 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6653 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6654 wr32(E1000_EIMS, q_vector->eims_value); 6655 else 6656 igb_irq_enable(adapter); 6657 } 6658 } 6659 6660 /** 6661 * igb_poll - NAPI Rx polling callback 6662 * @napi: napi polling structure 6663 * @budget: count of how many packets we should handle 6664 **/ 6665 static int igb_poll(struct napi_struct *napi, int budget) 6666 { 6667 struct igb_q_vector *q_vector = container_of(napi, 6668 struct igb_q_vector, 6669 napi); 6670 bool clean_complete = true; 6671 int work_done = 0; 6672 6673 #ifdef CONFIG_IGB_DCA 6674 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6675 igb_update_dca(q_vector); 6676 #endif 6677 if (q_vector->tx.ring) 6678 clean_complete = igb_clean_tx_irq(q_vector, budget); 6679 6680 if (q_vector->rx.ring) { 6681 int cleaned = igb_clean_rx_irq(q_vector, budget); 6682 6683 work_done += cleaned; 6684 if (cleaned >= budget) 6685 clean_complete = false; 6686 } 6687 6688 /* If all work not completed, return budget and keep polling */ 6689 if (!clean_complete) 6690 return budget; 6691 6692 /* If not enough Rx work done, exit the polling mode */ 6693 napi_complete_done(napi, work_done); 6694 igb_ring_irq_enable(q_vector); 6695 6696 return 0; 6697 } 6698 6699 /** 6700 * igb_clean_tx_irq - Reclaim resources after transmit completes 6701 * @q_vector: pointer to q_vector containing needed info 6702 * @napi_budget: Used to determine if we are in netpoll 6703 * 6704 * returns true if ring is completely cleaned 6705 **/ 6706 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6707 { 6708 struct igb_adapter *adapter = q_vector->adapter; 6709 struct igb_ring *tx_ring = q_vector->tx.ring; 6710 struct igb_tx_buffer *tx_buffer; 6711 union e1000_adv_tx_desc *tx_desc; 6712 unsigned int total_bytes = 0, total_packets = 0; 6713 unsigned int budget = q_vector->tx.work_limit; 6714 unsigned int i = tx_ring->next_to_clean; 6715 6716 if (test_bit(__IGB_DOWN, &adapter->state)) 6717 return true; 6718 6719 tx_buffer = &tx_ring->tx_buffer_info[i]; 6720 tx_desc = IGB_TX_DESC(tx_ring, i); 6721 i -= tx_ring->count; 6722 6723 do { 6724 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6725 6726 /* if next_to_watch is not set then there is no work pending */ 6727 if (!eop_desc) 6728 break; 6729 6730 /* prevent any other reads prior to eop_desc */ 6731 read_barrier_depends(); 6732 6733 /* if DD is not set pending work has not been completed */ 6734 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6735 break; 6736 6737 /* clear next_to_watch to prevent false hangs */ 6738 tx_buffer->next_to_watch = NULL; 6739 6740 /* update the statistics for this packet */ 6741 total_bytes += tx_buffer->bytecount; 6742 total_packets += tx_buffer->gso_segs; 6743 6744 /* free the skb */ 6745 napi_consume_skb(tx_buffer->skb, napi_budget); 6746 6747 /* unmap skb header data */ 6748 dma_unmap_single(tx_ring->dev, 6749 dma_unmap_addr(tx_buffer, dma), 6750 dma_unmap_len(tx_buffer, len), 6751 DMA_TO_DEVICE); 6752 6753 /* clear tx_buffer data */ 6754 dma_unmap_len_set(tx_buffer, len, 0); 6755 6756 /* clear last DMA location and unmap remaining buffers */ 6757 while (tx_desc != eop_desc) { 6758 tx_buffer++; 6759 tx_desc++; 6760 i++; 6761 if (unlikely(!i)) { 6762 i -= tx_ring->count; 6763 tx_buffer = tx_ring->tx_buffer_info; 6764 tx_desc = IGB_TX_DESC(tx_ring, 0); 6765 } 6766 6767 /* unmap any remaining paged data */ 6768 if (dma_unmap_len(tx_buffer, len)) { 6769 dma_unmap_page(tx_ring->dev, 6770 dma_unmap_addr(tx_buffer, dma), 6771 dma_unmap_len(tx_buffer, len), 6772 DMA_TO_DEVICE); 6773 dma_unmap_len_set(tx_buffer, len, 0); 6774 } 6775 } 6776 6777 /* move us one more past the eop_desc for start of next pkt */ 6778 tx_buffer++; 6779 tx_desc++; 6780 i++; 6781 if (unlikely(!i)) { 6782 i -= tx_ring->count; 6783 tx_buffer = tx_ring->tx_buffer_info; 6784 tx_desc = IGB_TX_DESC(tx_ring, 0); 6785 } 6786 6787 /* issue prefetch for next Tx descriptor */ 6788 prefetch(tx_desc); 6789 6790 /* update budget accounting */ 6791 budget--; 6792 } while (likely(budget)); 6793 6794 netdev_tx_completed_queue(txring_txq(tx_ring), 6795 total_packets, total_bytes); 6796 i += tx_ring->count; 6797 tx_ring->next_to_clean = i; 6798 u64_stats_update_begin(&tx_ring->tx_syncp); 6799 tx_ring->tx_stats.bytes += total_bytes; 6800 tx_ring->tx_stats.packets += total_packets; 6801 u64_stats_update_end(&tx_ring->tx_syncp); 6802 q_vector->tx.total_bytes += total_bytes; 6803 q_vector->tx.total_packets += total_packets; 6804 6805 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6806 struct e1000_hw *hw = &adapter->hw; 6807 6808 /* Detect a transmit hang in hardware, this serializes the 6809 * check with the clearing of time_stamp and movement of i 6810 */ 6811 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6812 if (tx_buffer->next_to_watch && 6813 time_after(jiffies, tx_buffer->time_stamp + 6814 (adapter->tx_timeout_factor * HZ)) && 6815 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6816 6817 /* detected Tx unit hang */ 6818 dev_err(tx_ring->dev, 6819 "Detected Tx Unit Hang\n" 6820 " Tx Queue <%d>\n" 6821 " TDH <%x>\n" 6822 " TDT <%x>\n" 6823 " next_to_use <%x>\n" 6824 " next_to_clean <%x>\n" 6825 "buffer_info[next_to_clean]\n" 6826 " time_stamp <%lx>\n" 6827 " next_to_watch <%p>\n" 6828 " jiffies <%lx>\n" 6829 " desc.status <%x>\n", 6830 tx_ring->queue_index, 6831 rd32(E1000_TDH(tx_ring->reg_idx)), 6832 readl(tx_ring->tail), 6833 tx_ring->next_to_use, 6834 tx_ring->next_to_clean, 6835 tx_buffer->time_stamp, 6836 tx_buffer->next_to_watch, 6837 jiffies, 6838 tx_buffer->next_to_watch->wb.status); 6839 netif_stop_subqueue(tx_ring->netdev, 6840 tx_ring->queue_index); 6841 6842 /* we are about to reset, no point in enabling stuff */ 6843 return true; 6844 } 6845 } 6846 6847 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6848 if (unlikely(total_packets && 6849 netif_carrier_ok(tx_ring->netdev) && 6850 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6851 /* Make sure that anybody stopping the queue after this 6852 * sees the new next_to_clean. 6853 */ 6854 smp_mb(); 6855 if (__netif_subqueue_stopped(tx_ring->netdev, 6856 tx_ring->queue_index) && 6857 !(test_bit(__IGB_DOWN, &adapter->state))) { 6858 netif_wake_subqueue(tx_ring->netdev, 6859 tx_ring->queue_index); 6860 6861 u64_stats_update_begin(&tx_ring->tx_syncp); 6862 tx_ring->tx_stats.restart_queue++; 6863 u64_stats_update_end(&tx_ring->tx_syncp); 6864 } 6865 } 6866 6867 return !!budget; 6868 } 6869 6870 /** 6871 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6872 * @rx_ring: rx descriptor ring to store buffers on 6873 * @old_buff: donor buffer to have page reused 6874 * 6875 * Synchronizes page for reuse by the adapter 6876 **/ 6877 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6878 struct igb_rx_buffer *old_buff) 6879 { 6880 struct igb_rx_buffer *new_buff; 6881 u16 nta = rx_ring->next_to_alloc; 6882 6883 new_buff = &rx_ring->rx_buffer_info[nta]; 6884 6885 /* update, and store next to alloc */ 6886 nta++; 6887 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6888 6889 /* Transfer page from old buffer to new buffer. 6890 * Move each member individually to avoid possible store 6891 * forwarding stalls. 6892 */ 6893 new_buff->dma = old_buff->dma; 6894 new_buff->page = old_buff->page; 6895 new_buff->page_offset = old_buff->page_offset; 6896 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 6897 } 6898 6899 static inline bool igb_page_is_reserved(struct page *page) 6900 { 6901 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 6902 } 6903 6904 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 6905 { 6906 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 6907 struct page *page = rx_buffer->page; 6908 6909 /* avoid re-using remote pages */ 6910 if (unlikely(igb_page_is_reserved(page))) 6911 return false; 6912 6913 #if (PAGE_SIZE < 8192) 6914 /* if we are only owner of page we can reuse it */ 6915 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 6916 return false; 6917 #else 6918 #define IGB_LAST_OFFSET \ 6919 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 6920 6921 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 6922 return false; 6923 #endif 6924 6925 /* If we have drained the page fragment pool we need to update 6926 * the pagecnt_bias and page count so that we fully restock the 6927 * number of references the driver holds. 6928 */ 6929 if (unlikely(!pagecnt_bias)) { 6930 page_ref_add(page, USHRT_MAX); 6931 rx_buffer->pagecnt_bias = USHRT_MAX; 6932 } 6933 6934 return true; 6935 } 6936 6937 /** 6938 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6939 * @rx_ring: rx descriptor ring to transact packets on 6940 * @rx_buffer: buffer containing page to add 6941 * @skb: sk_buff to place the data into 6942 * @size: size of buffer to be added 6943 * 6944 * This function will add the data contained in rx_buffer->page to the skb. 6945 **/ 6946 static void igb_add_rx_frag(struct igb_ring *rx_ring, 6947 struct igb_rx_buffer *rx_buffer, 6948 struct sk_buff *skb, 6949 unsigned int size) 6950 { 6951 #if (PAGE_SIZE < 8192) 6952 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 6953 #else 6954 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 6955 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 6956 SKB_DATA_ALIGN(size); 6957 #endif 6958 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 6959 rx_buffer->page_offset, size, truesize); 6960 #if (PAGE_SIZE < 8192) 6961 rx_buffer->page_offset ^= truesize; 6962 #else 6963 rx_buffer->page_offset += truesize; 6964 #endif 6965 } 6966 6967 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 6968 struct igb_rx_buffer *rx_buffer, 6969 union e1000_adv_rx_desc *rx_desc, 6970 unsigned int size) 6971 { 6972 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 6973 #if (PAGE_SIZE < 8192) 6974 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 6975 #else 6976 unsigned int truesize = SKB_DATA_ALIGN(size); 6977 #endif 6978 unsigned int headlen; 6979 struct sk_buff *skb; 6980 6981 /* prefetch first cache line of first page */ 6982 prefetch(va); 6983 #if L1_CACHE_BYTES < 128 6984 prefetch(va + L1_CACHE_BYTES); 6985 #endif 6986 6987 /* allocate a skb to store the frags */ 6988 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6989 if (unlikely(!skb)) 6990 return NULL; 6991 6992 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 6993 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6994 va += IGB_TS_HDR_LEN; 6995 size -= IGB_TS_HDR_LEN; 6996 } 6997 6998 /* Determine available headroom for copy */ 6999 headlen = size; 7000 if (headlen > IGB_RX_HDR_LEN) 7001 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7002 7003 /* align pull length to size of long to optimize memcpy performance */ 7004 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7005 7006 /* update all of the pointers */ 7007 size -= headlen; 7008 if (size) { 7009 skb_add_rx_frag(skb, 0, rx_buffer->page, 7010 (va + headlen) - page_address(rx_buffer->page), 7011 size, truesize); 7012 #if (PAGE_SIZE < 8192) 7013 rx_buffer->page_offset ^= truesize; 7014 #else 7015 rx_buffer->page_offset += truesize; 7016 #endif 7017 } else { 7018 rx_buffer->pagecnt_bias++; 7019 } 7020 7021 return skb; 7022 } 7023 7024 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7025 struct igb_rx_buffer *rx_buffer, 7026 union e1000_adv_rx_desc *rx_desc, 7027 unsigned int size) 7028 { 7029 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7030 #if (PAGE_SIZE < 8192) 7031 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7032 #else 7033 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7034 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7035 #endif 7036 struct sk_buff *skb; 7037 7038 /* prefetch first cache line of first page */ 7039 prefetch(va); 7040 #if L1_CACHE_BYTES < 128 7041 prefetch(va + L1_CACHE_BYTES); 7042 #endif 7043 7044 /* build an skb around the page buffer */ 7045 skb = build_skb(va - IGB_SKB_PAD, truesize); 7046 if (unlikely(!skb)) 7047 return NULL; 7048 7049 /* update pointers within the skb to store the data */ 7050 skb_reserve(skb, IGB_SKB_PAD); 7051 __skb_put(skb, size); 7052 7053 /* pull timestamp out of packet data */ 7054 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7055 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7056 __skb_pull(skb, IGB_TS_HDR_LEN); 7057 } 7058 7059 /* update buffer offset */ 7060 #if (PAGE_SIZE < 8192) 7061 rx_buffer->page_offset ^= truesize; 7062 #else 7063 rx_buffer->page_offset += truesize; 7064 #endif 7065 7066 return skb; 7067 } 7068 7069 static inline void igb_rx_checksum(struct igb_ring *ring, 7070 union e1000_adv_rx_desc *rx_desc, 7071 struct sk_buff *skb) 7072 { 7073 skb_checksum_none_assert(skb); 7074 7075 /* Ignore Checksum bit is set */ 7076 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 7077 return; 7078 7079 /* Rx checksum disabled via ethtool */ 7080 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 7081 return; 7082 7083 /* TCP/UDP checksum error bit is set */ 7084 if (igb_test_staterr(rx_desc, 7085 E1000_RXDEXT_STATERR_TCPE | 7086 E1000_RXDEXT_STATERR_IPE)) { 7087 /* work around errata with sctp packets where the TCPE aka 7088 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7089 * packets, (aka let the stack check the crc32c) 7090 */ 7091 if (!((skb->len == 60) && 7092 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7093 u64_stats_update_begin(&ring->rx_syncp); 7094 ring->rx_stats.csum_err++; 7095 u64_stats_update_end(&ring->rx_syncp); 7096 } 7097 /* let the stack verify checksum errors */ 7098 return; 7099 } 7100 /* It must be a TCP or UDP packet with a valid checksum */ 7101 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7102 E1000_RXD_STAT_UDPCS)) 7103 skb->ip_summed = CHECKSUM_UNNECESSARY; 7104 7105 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7106 le32_to_cpu(rx_desc->wb.upper.status_error)); 7107 } 7108 7109 static inline void igb_rx_hash(struct igb_ring *ring, 7110 union e1000_adv_rx_desc *rx_desc, 7111 struct sk_buff *skb) 7112 { 7113 if (ring->netdev->features & NETIF_F_RXHASH) 7114 skb_set_hash(skb, 7115 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7116 PKT_HASH_TYPE_L3); 7117 } 7118 7119 /** 7120 * igb_is_non_eop - process handling of non-EOP buffers 7121 * @rx_ring: Rx ring being processed 7122 * @rx_desc: Rx descriptor for current buffer 7123 * @skb: current socket buffer containing buffer in progress 7124 * 7125 * This function updates next to clean. If the buffer is an EOP buffer 7126 * this function exits returning false, otherwise it will place the 7127 * sk_buff in the next buffer to be chained and return true indicating 7128 * that this is in fact a non-EOP buffer. 7129 **/ 7130 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7131 union e1000_adv_rx_desc *rx_desc) 7132 { 7133 u32 ntc = rx_ring->next_to_clean + 1; 7134 7135 /* fetch, update, and store next to clean */ 7136 ntc = (ntc < rx_ring->count) ? ntc : 0; 7137 rx_ring->next_to_clean = ntc; 7138 7139 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7140 7141 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7142 return false; 7143 7144 return true; 7145 } 7146 7147 /** 7148 * igb_cleanup_headers - Correct corrupted or empty headers 7149 * @rx_ring: rx descriptor ring packet is being transacted on 7150 * @rx_desc: pointer to the EOP Rx descriptor 7151 * @skb: pointer to current skb being fixed 7152 * 7153 * Address the case where we are pulling data in on pages only 7154 * and as such no data is present in the skb header. 7155 * 7156 * In addition if skb is not at least 60 bytes we need to pad it so that 7157 * it is large enough to qualify as a valid Ethernet frame. 7158 * 7159 * Returns true if an error was encountered and skb was freed. 7160 **/ 7161 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7162 union e1000_adv_rx_desc *rx_desc, 7163 struct sk_buff *skb) 7164 { 7165 if (unlikely((igb_test_staterr(rx_desc, 7166 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7167 struct net_device *netdev = rx_ring->netdev; 7168 if (!(netdev->features & NETIF_F_RXALL)) { 7169 dev_kfree_skb_any(skb); 7170 return true; 7171 } 7172 } 7173 7174 /* if eth_skb_pad returns an error the skb was freed */ 7175 if (eth_skb_pad(skb)) 7176 return true; 7177 7178 return false; 7179 } 7180 7181 /** 7182 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7183 * @rx_ring: rx descriptor ring packet is being transacted on 7184 * @rx_desc: pointer to the EOP Rx descriptor 7185 * @skb: pointer to current skb being populated 7186 * 7187 * This function checks the ring, descriptor, and packet information in 7188 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7189 * other fields within the skb. 7190 **/ 7191 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7192 union e1000_adv_rx_desc *rx_desc, 7193 struct sk_buff *skb) 7194 { 7195 struct net_device *dev = rx_ring->netdev; 7196 7197 igb_rx_hash(rx_ring, rx_desc, skb); 7198 7199 igb_rx_checksum(rx_ring, rx_desc, skb); 7200 7201 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7202 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7203 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7204 7205 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7206 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7207 u16 vid; 7208 7209 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7210 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7211 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7212 else 7213 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7214 7215 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7216 } 7217 7218 skb_record_rx_queue(skb, rx_ring->queue_index); 7219 7220 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7221 } 7222 7223 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 7224 const unsigned int size) 7225 { 7226 struct igb_rx_buffer *rx_buffer; 7227 7228 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 7229 prefetchw(rx_buffer->page); 7230 7231 /* we are reusing so sync this buffer for CPU use */ 7232 dma_sync_single_range_for_cpu(rx_ring->dev, 7233 rx_buffer->dma, 7234 rx_buffer->page_offset, 7235 size, 7236 DMA_FROM_DEVICE); 7237 7238 rx_buffer->pagecnt_bias--; 7239 7240 return rx_buffer; 7241 } 7242 7243 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 7244 struct igb_rx_buffer *rx_buffer) 7245 { 7246 if (igb_can_reuse_rx_page(rx_buffer)) { 7247 /* hand second half of page back to the ring */ 7248 igb_reuse_rx_page(rx_ring, rx_buffer); 7249 } else { 7250 /* We are not reusing the buffer so unmap it and free 7251 * any references we are holding to it 7252 */ 7253 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 7254 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 7255 IGB_RX_DMA_ATTR); 7256 __page_frag_cache_drain(rx_buffer->page, 7257 rx_buffer->pagecnt_bias); 7258 } 7259 7260 /* clear contents of rx_buffer */ 7261 rx_buffer->page = NULL; 7262 } 7263 7264 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7265 { 7266 struct igb_ring *rx_ring = q_vector->rx.ring; 7267 struct sk_buff *skb = rx_ring->skb; 7268 unsigned int total_bytes = 0, total_packets = 0; 7269 u16 cleaned_count = igb_desc_unused(rx_ring); 7270 7271 while (likely(total_packets < budget)) { 7272 union e1000_adv_rx_desc *rx_desc; 7273 struct igb_rx_buffer *rx_buffer; 7274 unsigned int size; 7275 7276 /* return some buffers to hardware, one at a time is too slow */ 7277 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7278 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7279 cleaned_count = 0; 7280 } 7281 7282 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7283 size = le16_to_cpu(rx_desc->wb.upper.length); 7284 if (!size) 7285 break; 7286 7287 /* This memory barrier is needed to keep us from reading 7288 * any other fields out of the rx_desc until we know the 7289 * descriptor has been written back 7290 */ 7291 dma_rmb(); 7292 7293 rx_buffer = igb_get_rx_buffer(rx_ring, size); 7294 7295 /* retrieve a buffer from the ring */ 7296 if (skb) 7297 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 7298 else if (ring_uses_build_skb(rx_ring)) 7299 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 7300 else 7301 skb = igb_construct_skb(rx_ring, rx_buffer, 7302 rx_desc, size); 7303 7304 /* exit if we failed to retrieve a buffer */ 7305 if (!skb) { 7306 rx_ring->rx_stats.alloc_failed++; 7307 rx_buffer->pagecnt_bias++; 7308 break; 7309 } 7310 7311 igb_put_rx_buffer(rx_ring, rx_buffer); 7312 cleaned_count++; 7313 7314 /* fetch next buffer in frame if non-eop */ 7315 if (igb_is_non_eop(rx_ring, rx_desc)) 7316 continue; 7317 7318 /* verify the packet layout is correct */ 7319 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7320 skb = NULL; 7321 continue; 7322 } 7323 7324 /* probably a little skewed due to removing CRC */ 7325 total_bytes += skb->len; 7326 7327 /* populate checksum, timestamp, VLAN, and protocol */ 7328 igb_process_skb_fields(rx_ring, rx_desc, skb); 7329 7330 napi_gro_receive(&q_vector->napi, skb); 7331 7332 /* reset skb pointer */ 7333 skb = NULL; 7334 7335 /* update budget accounting */ 7336 total_packets++; 7337 } 7338 7339 /* place incomplete frames back on ring for completion */ 7340 rx_ring->skb = skb; 7341 7342 u64_stats_update_begin(&rx_ring->rx_syncp); 7343 rx_ring->rx_stats.packets += total_packets; 7344 rx_ring->rx_stats.bytes += total_bytes; 7345 u64_stats_update_end(&rx_ring->rx_syncp); 7346 q_vector->rx.total_packets += total_packets; 7347 q_vector->rx.total_bytes += total_bytes; 7348 7349 if (cleaned_count) 7350 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7351 7352 return total_packets; 7353 } 7354 7355 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 7356 { 7357 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 7358 } 7359 7360 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7361 struct igb_rx_buffer *bi) 7362 { 7363 struct page *page = bi->page; 7364 dma_addr_t dma; 7365 7366 /* since we are recycling buffers we should seldom need to alloc */ 7367 if (likely(page)) 7368 return true; 7369 7370 /* alloc new page for storage */ 7371 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 7372 if (unlikely(!page)) { 7373 rx_ring->rx_stats.alloc_failed++; 7374 return false; 7375 } 7376 7377 /* map page for use */ 7378 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 7379 igb_rx_pg_size(rx_ring), 7380 DMA_FROM_DEVICE, 7381 IGB_RX_DMA_ATTR); 7382 7383 /* if mapping failed free memory back to system since 7384 * there isn't much point in holding memory we can't use 7385 */ 7386 if (dma_mapping_error(rx_ring->dev, dma)) { 7387 __free_pages(page, igb_rx_pg_order(rx_ring)); 7388 7389 rx_ring->rx_stats.alloc_failed++; 7390 return false; 7391 } 7392 7393 bi->dma = dma; 7394 bi->page = page; 7395 bi->page_offset = igb_rx_offset(rx_ring); 7396 bi->pagecnt_bias = 1; 7397 7398 return true; 7399 } 7400 7401 /** 7402 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7403 * @adapter: address of board private structure 7404 **/ 7405 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7406 { 7407 union e1000_adv_rx_desc *rx_desc; 7408 struct igb_rx_buffer *bi; 7409 u16 i = rx_ring->next_to_use; 7410 u16 bufsz; 7411 7412 /* nothing to do */ 7413 if (!cleaned_count) 7414 return; 7415 7416 rx_desc = IGB_RX_DESC(rx_ring, i); 7417 bi = &rx_ring->rx_buffer_info[i]; 7418 i -= rx_ring->count; 7419 7420 bufsz = igb_rx_bufsz(rx_ring); 7421 7422 do { 7423 if (!igb_alloc_mapped_page(rx_ring, bi)) 7424 break; 7425 7426 /* sync the buffer for use by the device */ 7427 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 7428 bi->page_offset, bufsz, 7429 DMA_FROM_DEVICE); 7430 7431 /* Refresh the desc even if buffer_addrs didn't change 7432 * because each write-back erases this info. 7433 */ 7434 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7435 7436 rx_desc++; 7437 bi++; 7438 i++; 7439 if (unlikely(!i)) { 7440 rx_desc = IGB_RX_DESC(rx_ring, 0); 7441 bi = rx_ring->rx_buffer_info; 7442 i -= rx_ring->count; 7443 } 7444 7445 /* clear the length for the next_to_use descriptor */ 7446 rx_desc->wb.upper.length = 0; 7447 7448 cleaned_count--; 7449 } while (cleaned_count); 7450 7451 i += rx_ring->count; 7452 7453 if (rx_ring->next_to_use != i) { 7454 /* record the next descriptor to use */ 7455 rx_ring->next_to_use = i; 7456 7457 /* update next to alloc since we have filled the ring */ 7458 rx_ring->next_to_alloc = i; 7459 7460 /* Force memory writes to complete before letting h/w 7461 * know there are new descriptors to fetch. (Only 7462 * applicable for weak-ordered memory model archs, 7463 * such as IA-64). 7464 */ 7465 wmb(); 7466 writel(i, rx_ring->tail); 7467 } 7468 } 7469 7470 /** 7471 * igb_mii_ioctl - 7472 * @netdev: 7473 * @ifreq: 7474 * @cmd: 7475 **/ 7476 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7477 { 7478 struct igb_adapter *adapter = netdev_priv(netdev); 7479 struct mii_ioctl_data *data = if_mii(ifr); 7480 7481 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7482 return -EOPNOTSUPP; 7483 7484 switch (cmd) { 7485 case SIOCGMIIPHY: 7486 data->phy_id = adapter->hw.phy.addr; 7487 break; 7488 case SIOCGMIIREG: 7489 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7490 &data->val_out)) 7491 return -EIO; 7492 break; 7493 case SIOCSMIIREG: 7494 default: 7495 return -EOPNOTSUPP; 7496 } 7497 return 0; 7498 } 7499 7500 /** 7501 * igb_ioctl - 7502 * @netdev: 7503 * @ifreq: 7504 * @cmd: 7505 **/ 7506 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7507 { 7508 switch (cmd) { 7509 case SIOCGMIIPHY: 7510 case SIOCGMIIREG: 7511 case SIOCSMIIREG: 7512 return igb_mii_ioctl(netdev, ifr, cmd); 7513 case SIOCGHWTSTAMP: 7514 return igb_ptp_get_ts_config(netdev, ifr); 7515 case SIOCSHWTSTAMP: 7516 return igb_ptp_set_ts_config(netdev, ifr); 7517 default: 7518 return -EOPNOTSUPP; 7519 } 7520 } 7521 7522 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7523 { 7524 struct igb_adapter *adapter = hw->back; 7525 7526 pci_read_config_word(adapter->pdev, reg, value); 7527 } 7528 7529 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7530 { 7531 struct igb_adapter *adapter = hw->back; 7532 7533 pci_write_config_word(adapter->pdev, reg, *value); 7534 } 7535 7536 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7537 { 7538 struct igb_adapter *adapter = hw->back; 7539 7540 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7541 return -E1000_ERR_CONFIG; 7542 7543 return 0; 7544 } 7545 7546 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7547 { 7548 struct igb_adapter *adapter = hw->back; 7549 7550 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7551 return -E1000_ERR_CONFIG; 7552 7553 return 0; 7554 } 7555 7556 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7557 { 7558 struct igb_adapter *adapter = netdev_priv(netdev); 7559 struct e1000_hw *hw = &adapter->hw; 7560 u32 ctrl, rctl; 7561 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7562 7563 if (enable) { 7564 /* enable VLAN tag insert/strip */ 7565 ctrl = rd32(E1000_CTRL); 7566 ctrl |= E1000_CTRL_VME; 7567 wr32(E1000_CTRL, ctrl); 7568 7569 /* Disable CFI check */ 7570 rctl = rd32(E1000_RCTL); 7571 rctl &= ~E1000_RCTL_CFIEN; 7572 wr32(E1000_RCTL, rctl); 7573 } else { 7574 /* disable VLAN tag insert/strip */ 7575 ctrl = rd32(E1000_CTRL); 7576 ctrl &= ~E1000_CTRL_VME; 7577 wr32(E1000_CTRL, ctrl); 7578 } 7579 7580 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7581 } 7582 7583 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7584 __be16 proto, u16 vid) 7585 { 7586 struct igb_adapter *adapter = netdev_priv(netdev); 7587 struct e1000_hw *hw = &adapter->hw; 7588 int pf_id = adapter->vfs_allocated_count; 7589 7590 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7591 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7592 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7593 7594 set_bit(vid, adapter->active_vlans); 7595 7596 return 0; 7597 } 7598 7599 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7600 __be16 proto, u16 vid) 7601 { 7602 struct igb_adapter *adapter = netdev_priv(netdev); 7603 int pf_id = adapter->vfs_allocated_count; 7604 struct e1000_hw *hw = &adapter->hw; 7605 7606 /* remove VID from filter table */ 7607 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7608 igb_vfta_set(hw, vid, pf_id, false, true); 7609 7610 clear_bit(vid, adapter->active_vlans); 7611 7612 return 0; 7613 } 7614 7615 static void igb_restore_vlan(struct igb_adapter *adapter) 7616 { 7617 u16 vid = 1; 7618 7619 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7620 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7621 7622 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7623 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7624 } 7625 7626 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7627 { 7628 struct pci_dev *pdev = adapter->pdev; 7629 struct e1000_mac_info *mac = &adapter->hw.mac; 7630 7631 mac->autoneg = 0; 7632 7633 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7634 * for the switch() below to work 7635 */ 7636 if ((spd & 1) || (dplx & ~1)) 7637 goto err_inval; 7638 7639 /* Fiber NIC's only allow 1000 gbps Full duplex 7640 * and 100Mbps Full duplex for 100baseFx sfp 7641 */ 7642 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7643 switch (spd + dplx) { 7644 case SPEED_10 + DUPLEX_HALF: 7645 case SPEED_10 + DUPLEX_FULL: 7646 case SPEED_100 + DUPLEX_HALF: 7647 goto err_inval; 7648 default: 7649 break; 7650 } 7651 } 7652 7653 switch (spd + dplx) { 7654 case SPEED_10 + DUPLEX_HALF: 7655 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7656 break; 7657 case SPEED_10 + DUPLEX_FULL: 7658 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7659 break; 7660 case SPEED_100 + DUPLEX_HALF: 7661 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7662 break; 7663 case SPEED_100 + DUPLEX_FULL: 7664 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7665 break; 7666 case SPEED_1000 + DUPLEX_FULL: 7667 mac->autoneg = 1; 7668 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7669 break; 7670 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7671 default: 7672 goto err_inval; 7673 } 7674 7675 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7676 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7677 7678 return 0; 7679 7680 err_inval: 7681 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7682 return -EINVAL; 7683 } 7684 7685 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7686 bool runtime) 7687 { 7688 struct net_device *netdev = pci_get_drvdata(pdev); 7689 struct igb_adapter *adapter = netdev_priv(netdev); 7690 struct e1000_hw *hw = &adapter->hw; 7691 u32 ctrl, rctl, status; 7692 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7693 #ifdef CONFIG_PM 7694 int retval = 0; 7695 #endif 7696 7697 rtnl_lock(); 7698 netif_device_detach(netdev); 7699 7700 if (netif_running(netdev)) 7701 __igb_close(netdev, true); 7702 7703 igb_ptp_suspend(adapter); 7704 7705 igb_clear_interrupt_scheme(adapter); 7706 rtnl_unlock(); 7707 7708 #ifdef CONFIG_PM 7709 retval = pci_save_state(pdev); 7710 if (retval) 7711 return retval; 7712 #endif 7713 7714 status = rd32(E1000_STATUS); 7715 if (status & E1000_STATUS_LU) 7716 wufc &= ~E1000_WUFC_LNKC; 7717 7718 if (wufc) { 7719 igb_setup_rctl(adapter); 7720 igb_set_rx_mode(netdev); 7721 7722 /* turn on all-multi mode if wake on multicast is enabled */ 7723 if (wufc & E1000_WUFC_MC) { 7724 rctl = rd32(E1000_RCTL); 7725 rctl |= E1000_RCTL_MPE; 7726 wr32(E1000_RCTL, rctl); 7727 } 7728 7729 ctrl = rd32(E1000_CTRL); 7730 /* advertise wake from D3Cold */ 7731 #define E1000_CTRL_ADVD3WUC 0x00100000 7732 /* phy power management enable */ 7733 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7734 ctrl |= E1000_CTRL_ADVD3WUC; 7735 wr32(E1000_CTRL, ctrl); 7736 7737 /* Allow time for pending master requests to run */ 7738 igb_disable_pcie_master(hw); 7739 7740 wr32(E1000_WUC, E1000_WUC_PME_EN); 7741 wr32(E1000_WUFC, wufc); 7742 } else { 7743 wr32(E1000_WUC, 0); 7744 wr32(E1000_WUFC, 0); 7745 } 7746 7747 *enable_wake = wufc || adapter->en_mng_pt; 7748 if (!*enable_wake) 7749 igb_power_down_link(adapter); 7750 else 7751 igb_power_up_link(adapter); 7752 7753 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7754 * would have already happened in close and is redundant. 7755 */ 7756 igb_release_hw_control(adapter); 7757 7758 pci_disable_device(pdev); 7759 7760 return 0; 7761 } 7762 7763 #ifdef CONFIG_PM 7764 #ifdef CONFIG_PM_SLEEP 7765 static int igb_suspend(struct device *dev) 7766 { 7767 int retval; 7768 bool wake; 7769 struct pci_dev *pdev = to_pci_dev(dev); 7770 7771 retval = __igb_shutdown(pdev, &wake, 0); 7772 if (retval) 7773 return retval; 7774 7775 if (wake) { 7776 pci_prepare_to_sleep(pdev); 7777 } else { 7778 pci_wake_from_d3(pdev, false); 7779 pci_set_power_state(pdev, PCI_D3hot); 7780 } 7781 7782 return 0; 7783 } 7784 #endif /* CONFIG_PM_SLEEP */ 7785 7786 static int igb_resume(struct device *dev) 7787 { 7788 struct pci_dev *pdev = to_pci_dev(dev); 7789 struct net_device *netdev = pci_get_drvdata(pdev); 7790 struct igb_adapter *adapter = netdev_priv(netdev); 7791 struct e1000_hw *hw = &adapter->hw; 7792 u32 err; 7793 7794 pci_set_power_state(pdev, PCI_D0); 7795 pci_restore_state(pdev); 7796 pci_save_state(pdev); 7797 7798 if (!pci_device_is_present(pdev)) 7799 return -ENODEV; 7800 err = pci_enable_device_mem(pdev); 7801 if (err) { 7802 dev_err(&pdev->dev, 7803 "igb: Cannot enable PCI device from suspend\n"); 7804 return err; 7805 } 7806 pci_set_master(pdev); 7807 7808 pci_enable_wake(pdev, PCI_D3hot, 0); 7809 pci_enable_wake(pdev, PCI_D3cold, 0); 7810 7811 if (igb_init_interrupt_scheme(adapter, true)) { 7812 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7813 return -ENOMEM; 7814 } 7815 7816 igb_reset(adapter); 7817 7818 /* let the f/w know that the h/w is now under the control of the 7819 * driver. 7820 */ 7821 igb_get_hw_control(adapter); 7822 7823 wr32(E1000_WUS, ~0); 7824 7825 rtnl_lock(); 7826 if (!err && netif_running(netdev)) 7827 err = __igb_open(netdev, true); 7828 7829 if (!err) 7830 netif_device_attach(netdev); 7831 rtnl_unlock(); 7832 7833 return err; 7834 } 7835 7836 static int igb_runtime_idle(struct device *dev) 7837 { 7838 struct pci_dev *pdev = to_pci_dev(dev); 7839 struct net_device *netdev = pci_get_drvdata(pdev); 7840 struct igb_adapter *adapter = netdev_priv(netdev); 7841 7842 if (!igb_has_link(adapter)) 7843 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7844 7845 return -EBUSY; 7846 } 7847 7848 static int igb_runtime_suspend(struct device *dev) 7849 { 7850 struct pci_dev *pdev = to_pci_dev(dev); 7851 int retval; 7852 bool wake; 7853 7854 retval = __igb_shutdown(pdev, &wake, 1); 7855 if (retval) 7856 return retval; 7857 7858 if (wake) { 7859 pci_prepare_to_sleep(pdev); 7860 } else { 7861 pci_wake_from_d3(pdev, false); 7862 pci_set_power_state(pdev, PCI_D3hot); 7863 } 7864 7865 return 0; 7866 } 7867 7868 static int igb_runtime_resume(struct device *dev) 7869 { 7870 return igb_resume(dev); 7871 } 7872 #endif /* CONFIG_PM */ 7873 7874 static void igb_shutdown(struct pci_dev *pdev) 7875 { 7876 bool wake; 7877 7878 __igb_shutdown(pdev, &wake, 0); 7879 7880 if (system_state == SYSTEM_POWER_OFF) { 7881 pci_wake_from_d3(pdev, wake); 7882 pci_set_power_state(pdev, PCI_D3hot); 7883 } 7884 } 7885 7886 #ifdef CONFIG_PCI_IOV 7887 static int igb_sriov_reinit(struct pci_dev *dev) 7888 { 7889 struct net_device *netdev = pci_get_drvdata(dev); 7890 struct igb_adapter *adapter = netdev_priv(netdev); 7891 struct pci_dev *pdev = adapter->pdev; 7892 7893 rtnl_lock(); 7894 7895 if (netif_running(netdev)) 7896 igb_close(netdev); 7897 else 7898 igb_reset(adapter); 7899 7900 igb_clear_interrupt_scheme(adapter); 7901 7902 igb_init_queue_configuration(adapter); 7903 7904 if (igb_init_interrupt_scheme(adapter, true)) { 7905 rtnl_unlock(); 7906 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7907 return -ENOMEM; 7908 } 7909 7910 if (netif_running(netdev)) 7911 igb_open(netdev); 7912 7913 rtnl_unlock(); 7914 7915 return 0; 7916 } 7917 7918 static int igb_pci_disable_sriov(struct pci_dev *dev) 7919 { 7920 int err = igb_disable_sriov(dev); 7921 7922 if (!err) 7923 err = igb_sriov_reinit(dev); 7924 7925 return err; 7926 } 7927 7928 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7929 { 7930 int err = igb_enable_sriov(dev, num_vfs); 7931 7932 if (err) 7933 goto out; 7934 7935 err = igb_sriov_reinit(dev); 7936 if (!err) 7937 return num_vfs; 7938 7939 out: 7940 return err; 7941 } 7942 7943 #endif 7944 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7945 { 7946 #ifdef CONFIG_PCI_IOV 7947 if (num_vfs == 0) 7948 return igb_pci_disable_sriov(dev); 7949 else 7950 return igb_pci_enable_sriov(dev, num_vfs); 7951 #endif 7952 return 0; 7953 } 7954 7955 #ifdef CONFIG_NET_POLL_CONTROLLER 7956 /* Polling 'interrupt' - used by things like netconsole to send skbs 7957 * without having to re-enable interrupts. It's not called while 7958 * the interrupt routine is executing. 7959 */ 7960 static void igb_netpoll(struct net_device *netdev) 7961 { 7962 struct igb_adapter *adapter = netdev_priv(netdev); 7963 struct e1000_hw *hw = &adapter->hw; 7964 struct igb_q_vector *q_vector; 7965 int i; 7966 7967 for (i = 0; i < adapter->num_q_vectors; i++) { 7968 q_vector = adapter->q_vector[i]; 7969 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7970 wr32(E1000_EIMC, q_vector->eims_value); 7971 else 7972 igb_irq_disable(adapter); 7973 napi_schedule(&q_vector->napi); 7974 } 7975 } 7976 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7977 7978 /** 7979 * igb_io_error_detected - called when PCI error is detected 7980 * @pdev: Pointer to PCI device 7981 * @state: The current pci connection state 7982 * 7983 * This function is called after a PCI bus error affecting 7984 * this device has been detected. 7985 **/ 7986 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7987 pci_channel_state_t state) 7988 { 7989 struct net_device *netdev = pci_get_drvdata(pdev); 7990 struct igb_adapter *adapter = netdev_priv(netdev); 7991 7992 netif_device_detach(netdev); 7993 7994 if (state == pci_channel_io_perm_failure) 7995 return PCI_ERS_RESULT_DISCONNECT; 7996 7997 if (netif_running(netdev)) 7998 igb_down(adapter); 7999 pci_disable_device(pdev); 8000 8001 /* Request a slot slot reset. */ 8002 return PCI_ERS_RESULT_NEED_RESET; 8003 } 8004 8005 /** 8006 * igb_io_slot_reset - called after the pci bus has been reset. 8007 * @pdev: Pointer to PCI device 8008 * 8009 * Restart the card from scratch, as if from a cold-boot. Implementation 8010 * resembles the first-half of the igb_resume routine. 8011 **/ 8012 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8013 { 8014 struct net_device *netdev = pci_get_drvdata(pdev); 8015 struct igb_adapter *adapter = netdev_priv(netdev); 8016 struct e1000_hw *hw = &adapter->hw; 8017 pci_ers_result_t result; 8018 int err; 8019 8020 if (pci_enable_device_mem(pdev)) { 8021 dev_err(&pdev->dev, 8022 "Cannot re-enable PCI device after reset.\n"); 8023 result = PCI_ERS_RESULT_DISCONNECT; 8024 } else { 8025 pci_set_master(pdev); 8026 pci_restore_state(pdev); 8027 pci_save_state(pdev); 8028 8029 pci_enable_wake(pdev, PCI_D3hot, 0); 8030 pci_enable_wake(pdev, PCI_D3cold, 0); 8031 8032 /* In case of PCI error, adapter lose its HW address 8033 * so we should re-assign it here. 8034 */ 8035 hw->hw_addr = adapter->io_addr; 8036 8037 igb_reset(adapter); 8038 wr32(E1000_WUS, ~0); 8039 result = PCI_ERS_RESULT_RECOVERED; 8040 } 8041 8042 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8043 if (err) { 8044 dev_err(&pdev->dev, 8045 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8046 err); 8047 /* non-fatal, continue */ 8048 } 8049 8050 return result; 8051 } 8052 8053 /** 8054 * igb_io_resume - called when traffic can start flowing again. 8055 * @pdev: Pointer to PCI device 8056 * 8057 * This callback is called when the error recovery driver tells us that 8058 * its OK to resume normal operation. Implementation resembles the 8059 * second-half of the igb_resume routine. 8060 */ 8061 static void igb_io_resume(struct pci_dev *pdev) 8062 { 8063 struct net_device *netdev = pci_get_drvdata(pdev); 8064 struct igb_adapter *adapter = netdev_priv(netdev); 8065 8066 if (netif_running(netdev)) { 8067 if (igb_up(adapter)) { 8068 dev_err(&pdev->dev, "igb_up failed after reset\n"); 8069 return; 8070 } 8071 } 8072 8073 netif_device_attach(netdev); 8074 8075 /* let the f/w know that the h/w is now under the control of the 8076 * driver. 8077 */ 8078 igb_get_hw_control(adapter); 8079 } 8080 8081 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 8082 u8 qsel) 8083 { 8084 struct e1000_hw *hw = &adapter->hw; 8085 u32 rar_low, rar_high; 8086 8087 /* HW expects these to be in network order when they are plugged 8088 * into the registers which are little endian. In order to guarantee 8089 * that ordering we need to do an leXX_to_cpup here in order to be 8090 * ready for the byteswap that occurs with writel 8091 */ 8092 rar_low = le32_to_cpup((__le32 *)(addr)); 8093 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 8094 8095 /* Indicate to hardware the Address is Valid. */ 8096 rar_high |= E1000_RAH_AV; 8097 8098 if (hw->mac.type == e1000_82575) 8099 rar_high |= E1000_RAH_POOL_1 * qsel; 8100 else 8101 rar_high |= E1000_RAH_POOL_1 << qsel; 8102 8103 wr32(E1000_RAL(index), rar_low); 8104 wrfl(); 8105 wr32(E1000_RAH(index), rar_high); 8106 wrfl(); 8107 } 8108 8109 static int igb_set_vf_mac(struct igb_adapter *adapter, 8110 int vf, unsigned char *mac_addr) 8111 { 8112 struct e1000_hw *hw = &adapter->hw; 8113 /* VF MAC addresses start at end of receive addresses and moves 8114 * towards the first, as a result a collision should not be possible 8115 */ 8116 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 8117 8118 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 8119 8120 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 8121 8122 return 0; 8123 } 8124 8125 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 8126 { 8127 struct igb_adapter *adapter = netdev_priv(netdev); 8128 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 8129 return -EINVAL; 8130 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 8131 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 8132 dev_info(&adapter->pdev->dev, 8133 "Reload the VF driver to make this change effective."); 8134 if (test_bit(__IGB_DOWN, &adapter->state)) { 8135 dev_warn(&adapter->pdev->dev, 8136 "The VF MAC address has been set, but the PF device is not up.\n"); 8137 dev_warn(&adapter->pdev->dev, 8138 "Bring the PF device up before attempting to use the VF device.\n"); 8139 } 8140 return igb_set_vf_mac(adapter, vf, mac); 8141 } 8142 8143 static int igb_link_mbps(int internal_link_speed) 8144 { 8145 switch (internal_link_speed) { 8146 case SPEED_100: 8147 return 100; 8148 case SPEED_1000: 8149 return 1000; 8150 default: 8151 return 0; 8152 } 8153 } 8154 8155 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 8156 int link_speed) 8157 { 8158 int rf_dec, rf_int; 8159 u32 bcnrc_val; 8160 8161 if (tx_rate != 0) { 8162 /* Calculate the rate factor values to set */ 8163 rf_int = link_speed / tx_rate; 8164 rf_dec = (link_speed - (rf_int * tx_rate)); 8165 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8166 tx_rate; 8167 8168 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8169 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8170 E1000_RTTBCNRC_RF_INT_MASK); 8171 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8172 } else { 8173 bcnrc_val = 0; 8174 } 8175 8176 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8177 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8178 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8179 */ 8180 wr32(E1000_RTTBCNRM, 0x14); 8181 wr32(E1000_RTTBCNRC, bcnrc_val); 8182 } 8183 8184 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8185 { 8186 int actual_link_speed, i; 8187 bool reset_rate = false; 8188 8189 /* VF TX rate limit was not set or not supported */ 8190 if ((adapter->vf_rate_link_speed == 0) || 8191 (adapter->hw.mac.type != e1000_82576)) 8192 return; 8193 8194 actual_link_speed = igb_link_mbps(adapter->link_speed); 8195 if (actual_link_speed != adapter->vf_rate_link_speed) { 8196 reset_rate = true; 8197 adapter->vf_rate_link_speed = 0; 8198 dev_info(&adapter->pdev->dev, 8199 "Link speed has been changed. VF Transmit rate is disabled\n"); 8200 } 8201 8202 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8203 if (reset_rate) 8204 adapter->vf_data[i].tx_rate = 0; 8205 8206 igb_set_vf_rate_limit(&adapter->hw, i, 8207 adapter->vf_data[i].tx_rate, 8208 actual_link_speed); 8209 } 8210 } 8211 8212 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8213 int min_tx_rate, int max_tx_rate) 8214 { 8215 struct igb_adapter *adapter = netdev_priv(netdev); 8216 struct e1000_hw *hw = &adapter->hw; 8217 int actual_link_speed; 8218 8219 if (hw->mac.type != e1000_82576) 8220 return -EOPNOTSUPP; 8221 8222 if (min_tx_rate) 8223 return -EINVAL; 8224 8225 actual_link_speed = igb_link_mbps(adapter->link_speed); 8226 if ((vf >= adapter->vfs_allocated_count) || 8227 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8228 (max_tx_rate < 0) || 8229 (max_tx_rate > actual_link_speed)) 8230 return -EINVAL; 8231 8232 adapter->vf_rate_link_speed = actual_link_speed; 8233 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8234 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8235 8236 return 0; 8237 } 8238 8239 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8240 bool setting) 8241 { 8242 struct igb_adapter *adapter = netdev_priv(netdev); 8243 struct e1000_hw *hw = &adapter->hw; 8244 u32 reg_val, reg_offset; 8245 8246 if (!adapter->vfs_allocated_count) 8247 return -EOPNOTSUPP; 8248 8249 if (vf >= adapter->vfs_allocated_count) 8250 return -EINVAL; 8251 8252 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8253 reg_val = rd32(reg_offset); 8254 if (setting) 8255 reg_val |= (BIT(vf) | 8256 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8257 else 8258 reg_val &= ~(BIT(vf) | 8259 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8260 wr32(reg_offset, reg_val); 8261 8262 adapter->vf_data[vf].spoofchk_enabled = setting; 8263 return 0; 8264 } 8265 8266 static int igb_ndo_get_vf_config(struct net_device *netdev, 8267 int vf, struct ifla_vf_info *ivi) 8268 { 8269 struct igb_adapter *adapter = netdev_priv(netdev); 8270 if (vf >= adapter->vfs_allocated_count) 8271 return -EINVAL; 8272 ivi->vf = vf; 8273 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8274 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8275 ivi->min_tx_rate = 0; 8276 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8277 ivi->qos = adapter->vf_data[vf].pf_qos; 8278 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8279 return 0; 8280 } 8281 8282 static void igb_vmm_control(struct igb_adapter *adapter) 8283 { 8284 struct e1000_hw *hw = &adapter->hw; 8285 u32 reg; 8286 8287 switch (hw->mac.type) { 8288 case e1000_82575: 8289 case e1000_i210: 8290 case e1000_i211: 8291 case e1000_i354: 8292 default: 8293 /* replication is not supported for 82575 */ 8294 return; 8295 case e1000_82576: 8296 /* notify HW that the MAC is adding vlan tags */ 8297 reg = rd32(E1000_DTXCTL); 8298 reg |= E1000_DTXCTL_VLAN_ADDED; 8299 wr32(E1000_DTXCTL, reg); 8300 /* Fall through */ 8301 case e1000_82580: 8302 /* enable replication vlan tag stripping */ 8303 reg = rd32(E1000_RPLOLR); 8304 reg |= E1000_RPLOLR_STRVLAN; 8305 wr32(E1000_RPLOLR, reg); 8306 /* Fall through */ 8307 case e1000_i350: 8308 /* none of the above registers are supported by i350 */ 8309 break; 8310 } 8311 8312 if (adapter->vfs_allocated_count) { 8313 igb_vmdq_set_loopback_pf(hw, true); 8314 igb_vmdq_set_replication_pf(hw, true); 8315 igb_vmdq_set_anti_spoofing_pf(hw, true, 8316 adapter->vfs_allocated_count); 8317 } else { 8318 igb_vmdq_set_loopback_pf(hw, false); 8319 igb_vmdq_set_replication_pf(hw, false); 8320 } 8321 } 8322 8323 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8324 { 8325 struct e1000_hw *hw = &adapter->hw; 8326 u32 dmac_thr; 8327 u16 hwm; 8328 8329 if (hw->mac.type > e1000_82580) { 8330 if (adapter->flags & IGB_FLAG_DMAC) { 8331 u32 reg; 8332 8333 /* force threshold to 0. */ 8334 wr32(E1000_DMCTXTH, 0); 8335 8336 /* DMA Coalescing high water mark needs to be greater 8337 * than the Rx threshold. Set hwm to PBA - max frame 8338 * size in 16B units, capping it at PBA - 6KB. 8339 */ 8340 hwm = 64 * (pba - 6); 8341 reg = rd32(E1000_FCRTC); 8342 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8343 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8344 & E1000_FCRTC_RTH_COAL_MASK); 8345 wr32(E1000_FCRTC, reg); 8346 8347 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8348 * frame size, capping it at PBA - 10KB. 8349 */ 8350 dmac_thr = pba - 10; 8351 reg = rd32(E1000_DMACR); 8352 reg &= ~E1000_DMACR_DMACTHR_MASK; 8353 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8354 & E1000_DMACR_DMACTHR_MASK); 8355 8356 /* transition to L0x or L1 if available..*/ 8357 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8358 8359 /* watchdog timer= +-1000 usec in 32usec intervals */ 8360 reg |= (1000 >> 5); 8361 8362 /* Disable BMC-to-OS Watchdog Enable */ 8363 if (hw->mac.type != e1000_i354) 8364 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8365 8366 wr32(E1000_DMACR, reg); 8367 8368 /* no lower threshold to disable 8369 * coalescing(smart fifb)-UTRESH=0 8370 */ 8371 wr32(E1000_DMCRTRH, 0); 8372 8373 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8374 8375 wr32(E1000_DMCTLX, reg); 8376 8377 /* free space in tx packet buffer to wake from 8378 * DMA coal 8379 */ 8380 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8381 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8382 8383 /* make low power state decision controlled 8384 * by DMA coal 8385 */ 8386 reg = rd32(E1000_PCIEMISC); 8387 reg &= ~E1000_PCIEMISC_LX_DECISION; 8388 wr32(E1000_PCIEMISC, reg); 8389 } /* endif adapter->dmac is not disabled */ 8390 } else if (hw->mac.type == e1000_82580) { 8391 u32 reg = rd32(E1000_PCIEMISC); 8392 8393 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8394 wr32(E1000_DMACR, 0); 8395 } 8396 } 8397 8398 /** 8399 * igb_read_i2c_byte - Reads 8 bit word over I2C 8400 * @hw: pointer to hardware structure 8401 * @byte_offset: byte offset to read 8402 * @dev_addr: device address 8403 * @data: value read 8404 * 8405 * Performs byte read operation over I2C interface at 8406 * a specified device address. 8407 **/ 8408 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8409 u8 dev_addr, u8 *data) 8410 { 8411 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8412 struct i2c_client *this_client = adapter->i2c_client; 8413 s32 status; 8414 u16 swfw_mask = 0; 8415 8416 if (!this_client) 8417 return E1000_ERR_I2C; 8418 8419 swfw_mask = E1000_SWFW_PHY0_SM; 8420 8421 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8422 return E1000_ERR_SWFW_SYNC; 8423 8424 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8425 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8426 8427 if (status < 0) 8428 return E1000_ERR_I2C; 8429 else { 8430 *data = status; 8431 return 0; 8432 } 8433 } 8434 8435 /** 8436 * igb_write_i2c_byte - Writes 8 bit word over I2C 8437 * @hw: pointer to hardware structure 8438 * @byte_offset: byte offset to write 8439 * @dev_addr: device address 8440 * @data: value to write 8441 * 8442 * Performs byte write operation over I2C interface at 8443 * a specified device address. 8444 **/ 8445 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8446 u8 dev_addr, u8 data) 8447 { 8448 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8449 struct i2c_client *this_client = adapter->i2c_client; 8450 s32 status; 8451 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8452 8453 if (!this_client) 8454 return E1000_ERR_I2C; 8455 8456 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8457 return E1000_ERR_SWFW_SYNC; 8458 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8459 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8460 8461 if (status) 8462 return E1000_ERR_I2C; 8463 else 8464 return 0; 8465 8466 } 8467 8468 int igb_reinit_queues(struct igb_adapter *adapter) 8469 { 8470 struct net_device *netdev = adapter->netdev; 8471 struct pci_dev *pdev = adapter->pdev; 8472 int err = 0; 8473 8474 if (netif_running(netdev)) 8475 igb_close(netdev); 8476 8477 igb_reset_interrupt_capability(adapter); 8478 8479 if (igb_init_interrupt_scheme(adapter, true)) { 8480 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8481 return -ENOMEM; 8482 } 8483 8484 if (netif_running(netdev)) 8485 err = igb_open(netdev); 8486 8487 return err; 8488 } 8489 8490 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 8491 { 8492 struct igb_nfc_filter *rule; 8493 8494 spin_lock(&adapter->nfc_lock); 8495 8496 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8497 igb_erase_filter(adapter, rule); 8498 8499 spin_unlock(&adapter->nfc_lock); 8500 } 8501 8502 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 8503 { 8504 struct igb_nfc_filter *rule; 8505 8506 spin_lock(&adapter->nfc_lock); 8507 8508 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8509 igb_add_filter(adapter, rule); 8510 8511 spin_unlock(&adapter->nfc_lock); 8512 } 8513 /* igb_main.c */ 8514