1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static void igb_init_queue_configuration(struct igb_adapter *adapter); 113 static int igb_sw_init(struct igb_adapter *); 114 int igb_open(struct net_device *); 115 int igb_close(struct net_device *); 116 static void igb_configure(struct igb_adapter *); 117 static void igb_configure_tx(struct igb_adapter *); 118 static void igb_configure_rx(struct igb_adapter *); 119 static void igb_clean_all_tx_rings(struct igb_adapter *); 120 static void igb_clean_all_rx_rings(struct igb_adapter *); 121 static void igb_clean_tx_ring(struct igb_ring *); 122 static void igb_clean_rx_ring(struct igb_ring *); 123 static void igb_set_rx_mode(struct net_device *); 124 static void igb_update_phy_info(struct timer_list *); 125 static void igb_watchdog(struct timer_list *); 126 static void igb_watchdog_task(struct work_struct *); 127 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 128 static void igb_get_stats64(struct net_device *dev, 129 struct rtnl_link_stats64 *stats); 130 static int igb_change_mtu(struct net_device *, int); 131 static int igb_set_mac(struct net_device *, void *); 132 static void igb_set_uta(struct igb_adapter *adapter, bool set); 133 static irqreturn_t igb_intr(int irq, void *); 134 static irqreturn_t igb_intr_msi(int irq, void *); 135 static irqreturn_t igb_msix_other(int irq, void *); 136 static irqreturn_t igb_msix_ring(int irq, void *); 137 #ifdef CONFIG_IGB_DCA 138 static void igb_update_dca(struct igb_q_vector *); 139 static void igb_setup_dca(struct igb_adapter *); 140 #endif /* CONFIG_IGB_DCA */ 141 static int igb_poll(struct napi_struct *, int); 142 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 143 static int igb_clean_rx_irq(struct igb_q_vector *, int); 144 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 145 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 146 static void igb_reset_task(struct work_struct *); 147 static void igb_vlan_mode(struct net_device *netdev, 148 netdev_features_t features); 149 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 150 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 151 static void igb_restore_vlan(struct igb_adapter *); 152 static void igb_rar_set_index(struct igb_adapter *, u32); 153 static void igb_ping_all_vfs(struct igb_adapter *); 154 static void igb_msg_task(struct igb_adapter *); 155 static void igb_vmm_control(struct igb_adapter *); 156 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 157 static void igb_flush_mac_table(struct igb_adapter *); 158 static int igb_available_rars(struct igb_adapter *, u8); 159 static void igb_set_default_mac_filter(struct igb_adapter *); 160 static int igb_uc_sync(struct net_device *, const unsigned char *); 161 static int igb_uc_unsync(struct net_device *, const unsigned char *); 162 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 163 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 164 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 165 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 166 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 167 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 168 bool setting); 169 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 170 bool setting); 171 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 172 struct ifla_vf_info *ivi); 173 static void igb_check_vf_rate_limit(struct igb_adapter *); 174 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 175 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 176 177 #ifdef CONFIG_PCI_IOV 178 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 179 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 180 #endif 181 182 static int igb_suspend(struct device *); 183 static int igb_resume(struct device *); 184 static int igb_runtime_suspend(struct device *dev); 185 static int igb_runtime_resume(struct device *dev); 186 static int igb_runtime_idle(struct device *dev); 187 static const struct dev_pm_ops igb_pm_ops = { 188 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 189 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 190 igb_runtime_idle) 191 }; 192 static void igb_shutdown(struct pci_dev *); 193 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 194 #ifdef CONFIG_IGB_DCA 195 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 196 static struct notifier_block dca_notifier = { 197 .notifier_call = igb_notify_dca, 198 .next = NULL, 199 .priority = 0 200 }; 201 #endif 202 #ifdef CONFIG_PCI_IOV 203 static unsigned int max_vfs; 204 module_param(max_vfs, uint, 0); 205 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 206 #endif /* CONFIG_PCI_IOV */ 207 208 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 209 pci_channel_state_t); 210 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 211 static void igb_io_resume(struct pci_dev *); 212 213 static const struct pci_error_handlers igb_err_handler = { 214 .error_detected = igb_io_error_detected, 215 .slot_reset = igb_io_slot_reset, 216 .resume = igb_io_resume, 217 }; 218 219 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 220 221 static struct pci_driver igb_driver = { 222 .name = igb_driver_name, 223 .id_table = igb_pci_tbl, 224 .probe = igb_probe, 225 .remove = igb_remove, 226 #ifdef CONFIG_PM 227 .driver.pm = &igb_pm_ops, 228 #endif 229 .shutdown = igb_shutdown, 230 .sriov_configure = igb_pci_sriov_configure, 231 .err_handler = &igb_err_handler 232 }; 233 234 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 235 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 236 MODULE_LICENSE("GPL v2"); 237 238 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 239 static int debug = -1; 240 module_param(debug, int, 0); 241 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 242 243 struct igb_reg_info { 244 u32 ofs; 245 char *name; 246 }; 247 248 static const struct igb_reg_info igb_reg_info_tbl[] = { 249 250 /* General Registers */ 251 {E1000_CTRL, "CTRL"}, 252 {E1000_STATUS, "STATUS"}, 253 {E1000_CTRL_EXT, "CTRL_EXT"}, 254 255 /* Interrupt Registers */ 256 {E1000_ICR, "ICR"}, 257 258 /* RX Registers */ 259 {E1000_RCTL, "RCTL"}, 260 {E1000_RDLEN(0), "RDLEN"}, 261 {E1000_RDH(0), "RDH"}, 262 {E1000_RDT(0), "RDT"}, 263 {E1000_RXDCTL(0), "RXDCTL"}, 264 {E1000_RDBAL(0), "RDBAL"}, 265 {E1000_RDBAH(0), "RDBAH"}, 266 267 /* TX Registers */ 268 {E1000_TCTL, "TCTL"}, 269 {E1000_TDBAL(0), "TDBAL"}, 270 {E1000_TDBAH(0), "TDBAH"}, 271 {E1000_TDLEN(0), "TDLEN"}, 272 {E1000_TDH(0), "TDH"}, 273 {E1000_TDT(0), "TDT"}, 274 {E1000_TXDCTL(0), "TXDCTL"}, 275 {E1000_TDFH, "TDFH"}, 276 {E1000_TDFT, "TDFT"}, 277 {E1000_TDFHS, "TDFHS"}, 278 {E1000_TDFPC, "TDFPC"}, 279 280 /* List Terminator */ 281 {} 282 }; 283 284 /* igb_regdump - register printout routine */ 285 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 286 { 287 int n = 0; 288 char rname[16]; 289 u32 regs[8]; 290 291 switch (reginfo->ofs) { 292 case E1000_RDLEN(0): 293 for (n = 0; n < 4; n++) 294 regs[n] = rd32(E1000_RDLEN(n)); 295 break; 296 case E1000_RDH(0): 297 for (n = 0; n < 4; n++) 298 regs[n] = rd32(E1000_RDH(n)); 299 break; 300 case E1000_RDT(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDT(n)); 303 break; 304 case E1000_RXDCTL(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RXDCTL(n)); 307 break; 308 case E1000_RDBAL(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDBAL(n)); 311 break; 312 case E1000_RDBAH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDBAH(n)); 315 break; 316 case E1000_TDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_TDBAL(n)); 319 break; 320 case E1000_TDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_TDBAH(n)); 323 break; 324 case E1000_TDLEN(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_TDLEN(n)); 327 break; 328 case E1000_TDH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDH(n)); 331 break; 332 case E1000_TDT(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDT(n)); 335 break; 336 case E1000_TXDCTL(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TXDCTL(n)); 339 break; 340 default: 341 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 342 return; 343 } 344 345 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 346 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 347 regs[2], regs[3]); 348 } 349 350 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 351 static void igb_dump(struct igb_adapter *adapter) 352 { 353 struct net_device *netdev = adapter->netdev; 354 struct e1000_hw *hw = &adapter->hw; 355 struct igb_reg_info *reginfo; 356 struct igb_ring *tx_ring; 357 union e1000_adv_tx_desc *tx_desc; 358 struct my_u0 { __le64 a; __le64 b; } *u0; 359 struct igb_ring *rx_ring; 360 union e1000_adv_rx_desc *rx_desc; 361 u32 staterr; 362 u16 i, n; 363 364 if (!netif_msg_hw(adapter)) 365 return; 366 367 /* Print netdevice Info */ 368 if (netdev) { 369 dev_info(&adapter->pdev->dev, "Net device Info\n"); 370 pr_info("Device Name state trans_start\n"); 371 pr_info("%-15s %016lX %016lX\n", netdev->name, 372 netdev->state, dev_trans_start(netdev)); 373 } 374 375 /* Print Registers */ 376 dev_info(&adapter->pdev->dev, "Register Dump\n"); 377 pr_info(" Register Name Value\n"); 378 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 379 reginfo->name; reginfo++) { 380 igb_regdump(hw, reginfo); 381 } 382 383 /* Print TX Ring Summary */ 384 if (!netdev || !netif_running(netdev)) 385 goto exit; 386 387 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 388 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 389 for (n = 0; n < adapter->num_tx_queues; n++) { 390 struct igb_tx_buffer *buffer_info; 391 tx_ring = adapter->tx_ring[n]; 392 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 393 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 394 n, tx_ring->next_to_use, tx_ring->next_to_clean, 395 (u64)dma_unmap_addr(buffer_info, dma), 396 dma_unmap_len(buffer_info, len), 397 buffer_info->next_to_watch, 398 (u64)buffer_info->time_stamp); 399 } 400 401 /* Print TX Rings */ 402 if (!netif_msg_tx_done(adapter)) 403 goto rx_ring_summary; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 406 407 /* Transmit Descriptor Formats 408 * 409 * Advanced Transmit Descriptor 410 * +--------------------------------------------------------------+ 411 * 0 | Buffer Address [63:0] | 412 * +--------------------------------------------------------------+ 413 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 414 * +--------------------------------------------------------------+ 415 * 63 46 45 40 39 38 36 35 32 31 24 15 0 416 */ 417 418 for (n = 0; n < adapter->num_tx_queues; n++) { 419 tx_ring = adapter->tx_ring[n]; 420 pr_info("------------------------------------\n"); 421 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 422 pr_info("------------------------------------\n"); 423 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 424 425 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 426 const char *next_desc; 427 struct igb_tx_buffer *buffer_info; 428 tx_desc = IGB_TX_DESC(tx_ring, i); 429 buffer_info = &tx_ring->tx_buffer_info[i]; 430 u0 = (struct my_u0 *)tx_desc; 431 if (i == tx_ring->next_to_use && 432 i == tx_ring->next_to_clean) 433 next_desc = " NTC/U"; 434 else if (i == tx_ring->next_to_use) 435 next_desc = " NTU"; 436 else if (i == tx_ring->next_to_clean) 437 next_desc = " NTC"; 438 else 439 next_desc = ""; 440 441 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 442 i, le64_to_cpu(u0->a), 443 le64_to_cpu(u0->b), 444 (u64)dma_unmap_addr(buffer_info, dma), 445 dma_unmap_len(buffer_info, len), 446 buffer_info->next_to_watch, 447 (u64)buffer_info->time_stamp, 448 buffer_info->skb, next_desc); 449 450 if (netif_msg_pktdata(adapter) && buffer_info->skb) 451 print_hex_dump(KERN_INFO, "", 452 DUMP_PREFIX_ADDRESS, 453 16, 1, buffer_info->skb->data, 454 dma_unmap_len(buffer_info, len), 455 true); 456 } 457 } 458 459 /* Print RX Rings Summary */ 460 rx_ring_summary: 461 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 462 pr_info("Queue [NTU] [NTC]\n"); 463 for (n = 0; n < adapter->num_rx_queues; n++) { 464 rx_ring = adapter->rx_ring[n]; 465 pr_info(" %5d %5X %5X\n", 466 n, rx_ring->next_to_use, rx_ring->next_to_clean); 467 } 468 469 /* Print RX Rings */ 470 if (!netif_msg_rx_status(adapter)) 471 goto exit; 472 473 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 474 475 /* Advanced Receive Descriptor (Read) Format 476 * 63 1 0 477 * +-----------------------------------------------------+ 478 * 0 | Packet Buffer Address [63:1] |A0/NSE| 479 * +----------------------------------------------+------+ 480 * 8 | Header Buffer Address [63:1] | DD | 481 * +-----------------------------------------------------+ 482 * 483 * 484 * Advanced Receive Descriptor (Write-Back) Format 485 * 486 * 63 48 47 32 31 30 21 20 17 16 4 3 0 487 * +------------------------------------------------------+ 488 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 489 * | Checksum Ident | | | | Type | Type | 490 * +------------------------------------------------------+ 491 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 492 * +------------------------------------------------------+ 493 * 63 48 47 32 31 20 19 0 494 */ 495 496 for (n = 0; n < adapter->num_rx_queues; n++) { 497 rx_ring = adapter->rx_ring[n]; 498 pr_info("------------------------------------\n"); 499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 500 pr_info("------------------------------------\n"); 501 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 502 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 503 504 for (i = 0; i < rx_ring->count; i++) { 505 const char *next_desc; 506 struct igb_rx_buffer *buffer_info; 507 buffer_info = &rx_ring->rx_buffer_info[i]; 508 rx_desc = IGB_RX_DESC(rx_ring, i); 509 u0 = (struct my_u0 *)rx_desc; 510 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 511 512 if (i == rx_ring->next_to_use) 513 next_desc = " NTU"; 514 else if (i == rx_ring->next_to_clean) 515 next_desc = " NTC"; 516 else 517 next_desc = ""; 518 519 if (staterr & E1000_RXD_STAT_DD) { 520 /* Descriptor Done */ 521 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 522 "RWB", i, 523 le64_to_cpu(u0->a), 524 le64_to_cpu(u0->b), 525 next_desc); 526 } else { 527 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 528 "R ", i, 529 le64_to_cpu(u0->a), 530 le64_to_cpu(u0->b), 531 (u64)buffer_info->dma, 532 next_desc); 533 534 if (netif_msg_pktdata(adapter) && 535 buffer_info->dma && buffer_info->page) { 536 print_hex_dump(KERN_INFO, "", 537 DUMP_PREFIX_ADDRESS, 538 16, 1, 539 page_address(buffer_info->page) + 540 buffer_info->page_offset, 541 igb_rx_bufsz(rx_ring), true); 542 } 543 } 544 } 545 } 546 547 exit: 548 return; 549 } 550 551 /** 552 * igb_get_i2c_data - Reads the I2C SDA data bit 553 * @data: opaque pointer to adapter struct 554 * 555 * Returns the I2C data bit value 556 **/ 557 static int igb_get_i2c_data(void *data) 558 { 559 struct igb_adapter *adapter = (struct igb_adapter *)data; 560 struct e1000_hw *hw = &adapter->hw; 561 s32 i2cctl = rd32(E1000_I2CPARAMS); 562 563 return !!(i2cctl & E1000_I2C_DATA_IN); 564 } 565 566 /** 567 * igb_set_i2c_data - Sets the I2C data bit 568 * @data: pointer to hardware structure 569 * @state: I2C data value (0 or 1) to set 570 * 571 * Sets the I2C data bit 572 **/ 573 static void igb_set_i2c_data(void *data, int state) 574 { 575 struct igb_adapter *adapter = (struct igb_adapter *)data; 576 struct e1000_hw *hw = &adapter->hw; 577 s32 i2cctl = rd32(E1000_I2CPARAMS); 578 579 if (state) { 580 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 581 } else { 582 i2cctl &= ~E1000_I2C_DATA_OE_N; 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 } 585 586 wr32(E1000_I2CPARAMS, i2cctl); 587 wrfl(); 588 } 589 590 /** 591 * igb_set_i2c_clk - Sets the I2C SCL clock 592 * @data: pointer to hardware structure 593 * @state: state to set clock 594 * 595 * Sets the I2C clock line to state 596 **/ 597 static void igb_set_i2c_clk(void *data, int state) 598 { 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) { 604 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 605 } else { 606 i2cctl &= ~E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } 609 wr32(E1000_I2CPARAMS, i2cctl); 610 wrfl(); 611 } 612 613 /** 614 * igb_get_i2c_clk - Gets the I2C SCL clock state 615 * @data: pointer to hardware structure 616 * 617 * Gets the I2C clock state 618 **/ 619 static int igb_get_i2c_clk(void *data) 620 { 621 struct igb_adapter *adapter = (struct igb_adapter *)data; 622 struct e1000_hw *hw = &adapter->hw; 623 s32 i2cctl = rd32(E1000_I2CPARAMS); 624 625 return !!(i2cctl & E1000_I2C_CLK_IN); 626 } 627 628 static const struct i2c_algo_bit_data igb_i2c_algo = { 629 .setsda = igb_set_i2c_data, 630 .setscl = igb_set_i2c_clk, 631 .getsda = igb_get_i2c_data, 632 .getscl = igb_get_i2c_clk, 633 .udelay = 5, 634 .timeout = 20, 635 }; 636 637 /** 638 * igb_get_hw_dev - return device 639 * @hw: pointer to hardware structure 640 * 641 * used by hardware layer to print debugging information 642 **/ 643 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 644 { 645 struct igb_adapter *adapter = hw->back; 646 return adapter->netdev; 647 } 648 649 /** 650 * igb_init_module - Driver Registration Routine 651 * 652 * igb_init_module is the first routine called when the driver is 653 * loaded. All it does is register with the PCI subsystem. 654 **/ 655 static int __init igb_init_module(void) 656 { 657 int ret; 658 659 pr_info("%s\n", igb_driver_string); 660 pr_info("%s\n", igb_copyright); 661 662 #ifdef CONFIG_IGB_DCA 663 dca_register_notify(&dca_notifier); 664 #endif 665 ret = pci_register_driver(&igb_driver); 666 return ret; 667 } 668 669 module_init(igb_init_module); 670 671 /** 672 * igb_exit_module - Driver Exit Cleanup Routine 673 * 674 * igb_exit_module is called just before the driver is removed 675 * from memory. 676 **/ 677 static void __exit igb_exit_module(void) 678 { 679 #ifdef CONFIG_IGB_DCA 680 dca_unregister_notify(&dca_notifier); 681 #endif 682 pci_unregister_driver(&igb_driver); 683 } 684 685 module_exit(igb_exit_module); 686 687 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 688 /** 689 * igb_cache_ring_register - Descriptor ring to register mapping 690 * @adapter: board private structure to initialize 691 * 692 * Once we know the feature-set enabled for the device, we'll cache 693 * the register offset the descriptor ring is assigned to. 694 **/ 695 static void igb_cache_ring_register(struct igb_adapter *adapter) 696 { 697 int i = 0, j = 0; 698 u32 rbase_offset = adapter->vfs_allocated_count; 699 700 switch (adapter->hw.mac.type) { 701 case e1000_82576: 702 /* The queues are allocated for virtualization such that VF 0 703 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 704 * In order to avoid collision we start at the first free queue 705 * and continue consuming queues in the same sequence 706 */ 707 if (adapter->vfs_allocated_count) { 708 for (; i < adapter->rss_queues; i++) 709 adapter->rx_ring[i]->reg_idx = rbase_offset + 710 Q_IDX_82576(i); 711 } 712 fallthrough; 713 case e1000_82575: 714 case e1000_82580: 715 case e1000_i350: 716 case e1000_i354: 717 case e1000_i210: 718 case e1000_i211: 719 default: 720 for (; i < adapter->num_rx_queues; i++) 721 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 722 for (; j < adapter->num_tx_queues; j++) 723 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 724 break; 725 } 726 } 727 728 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 729 { 730 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 731 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 732 u32 value = 0; 733 734 if (E1000_REMOVED(hw_addr)) 735 return ~value; 736 737 value = readl(&hw_addr[reg]); 738 739 /* reads should not return all F's */ 740 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 741 struct net_device *netdev = igb->netdev; 742 hw->hw_addr = NULL; 743 netdev_err(netdev, "PCIe link lost\n"); 744 WARN(pci_device_is_present(igb->pdev), 745 "igb: Failed to read reg 0x%x!\n", reg); 746 } 747 748 return value; 749 } 750 751 /** 752 * igb_write_ivar - configure ivar for given MSI-X vector 753 * @hw: pointer to the HW structure 754 * @msix_vector: vector number we are allocating to a given ring 755 * @index: row index of IVAR register to write within IVAR table 756 * @offset: column offset of in IVAR, should be multiple of 8 757 * 758 * This function is intended to handle the writing of the IVAR register 759 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 760 * each containing an cause allocation for an Rx and Tx ring, and a 761 * variable number of rows depending on the number of queues supported. 762 **/ 763 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 764 int index, int offset) 765 { 766 u32 ivar = array_rd32(E1000_IVAR0, index); 767 768 /* clear any bits that are currently set */ 769 ivar &= ~((u32)0xFF << offset); 770 771 /* write vector and valid bit */ 772 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 773 774 array_wr32(E1000_IVAR0, index, ivar); 775 } 776 777 #define IGB_N0_QUEUE -1 778 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 779 { 780 struct igb_adapter *adapter = q_vector->adapter; 781 struct e1000_hw *hw = &adapter->hw; 782 int rx_queue = IGB_N0_QUEUE; 783 int tx_queue = IGB_N0_QUEUE; 784 u32 msixbm = 0; 785 786 if (q_vector->rx.ring) 787 rx_queue = q_vector->rx.ring->reg_idx; 788 if (q_vector->tx.ring) 789 tx_queue = q_vector->tx.ring->reg_idx; 790 791 switch (hw->mac.type) { 792 case e1000_82575: 793 /* The 82575 assigns vectors using a bitmask, which matches the 794 * bitmask for the EICR/EIMS/EIMC registers. To assign one 795 * or more queues to a vector, we write the appropriate bits 796 * into the MSIXBM register for that vector. 797 */ 798 if (rx_queue > IGB_N0_QUEUE) 799 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 800 if (tx_queue > IGB_N0_QUEUE) 801 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 802 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 803 msixbm |= E1000_EIMS_OTHER; 804 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 805 q_vector->eims_value = msixbm; 806 break; 807 case e1000_82576: 808 /* 82576 uses a table that essentially consists of 2 columns 809 * with 8 rows. The ordering is column-major so we use the 810 * lower 3 bits as the row index, and the 4th bit as the 811 * column offset. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 igb_write_ivar(hw, msix_vector, 815 rx_queue & 0x7, 816 (rx_queue & 0x8) << 1); 817 if (tx_queue > IGB_N0_QUEUE) 818 igb_write_ivar(hw, msix_vector, 819 tx_queue & 0x7, 820 ((tx_queue & 0x8) << 1) + 8); 821 q_vector->eims_value = BIT(msix_vector); 822 break; 823 case e1000_82580: 824 case e1000_i350: 825 case e1000_i354: 826 case e1000_i210: 827 case e1000_i211: 828 /* On 82580 and newer adapters the scheme is similar to 82576 829 * however instead of ordering column-major we have things 830 * ordered row-major. So we traverse the table by using 831 * bit 0 as the column offset, and the remaining bits as the 832 * row index. 833 */ 834 if (rx_queue > IGB_N0_QUEUE) 835 igb_write_ivar(hw, msix_vector, 836 rx_queue >> 1, 837 (rx_queue & 0x1) << 4); 838 if (tx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 tx_queue >> 1, 841 ((tx_queue & 0x1) << 4) + 8); 842 q_vector->eims_value = BIT(msix_vector); 843 break; 844 default: 845 BUG(); 846 break; 847 } 848 849 /* add q_vector eims value to global eims_enable_mask */ 850 adapter->eims_enable_mask |= q_vector->eims_value; 851 852 /* configure q_vector to set itr on first interrupt */ 853 q_vector->set_itr = 1; 854 } 855 856 /** 857 * igb_configure_msix - Configure MSI-X hardware 858 * @adapter: board private structure to initialize 859 * 860 * igb_configure_msix sets up the hardware to properly 861 * generate MSI-X interrupts. 862 **/ 863 static void igb_configure_msix(struct igb_adapter *adapter) 864 { 865 u32 tmp; 866 int i, vector = 0; 867 struct e1000_hw *hw = &adapter->hw; 868 869 adapter->eims_enable_mask = 0; 870 871 /* set vector for other causes, i.e. link changes */ 872 switch (hw->mac.type) { 873 case e1000_82575: 874 tmp = rd32(E1000_CTRL_EXT); 875 /* enable MSI-X PBA support*/ 876 tmp |= E1000_CTRL_EXT_PBA_CLR; 877 878 /* Auto-Mask interrupts upon ICR read. */ 879 tmp |= E1000_CTRL_EXT_EIAME; 880 tmp |= E1000_CTRL_EXT_IRCA; 881 882 wr32(E1000_CTRL_EXT, tmp); 883 884 /* enable msix_other interrupt */ 885 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 886 adapter->eims_other = E1000_EIMS_OTHER; 887 888 break; 889 890 case e1000_82576: 891 case e1000_82580: 892 case e1000_i350: 893 case e1000_i354: 894 case e1000_i210: 895 case e1000_i211: 896 /* Turn on MSI-X capability first, or our settings 897 * won't stick. And it will take days to debug. 898 */ 899 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 900 E1000_GPIE_PBA | E1000_GPIE_EIAME | 901 E1000_GPIE_NSICR); 902 903 /* enable msix_other interrupt */ 904 adapter->eims_other = BIT(vector); 905 tmp = (vector++ | E1000_IVAR_VALID) << 8; 906 907 wr32(E1000_IVAR_MISC, tmp); 908 break; 909 default: 910 /* do nothing, since nothing else supports MSI-X */ 911 break; 912 } /* switch (hw->mac.type) */ 913 914 adapter->eims_enable_mask |= adapter->eims_other; 915 916 for (i = 0; i < adapter->num_q_vectors; i++) 917 igb_assign_vector(adapter->q_vector[i], vector++); 918 919 wrfl(); 920 } 921 922 /** 923 * igb_request_msix - Initialize MSI-X interrupts 924 * @adapter: board private structure to initialize 925 * 926 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 927 * kernel. 928 **/ 929 static int igb_request_msix(struct igb_adapter *adapter) 930 { 931 unsigned int num_q_vectors = adapter->num_q_vectors; 932 struct net_device *netdev = adapter->netdev; 933 int i, err = 0, vector = 0, free_vector = 0; 934 935 err = request_irq(adapter->msix_entries[vector].vector, 936 igb_msix_other, 0, netdev->name, adapter); 937 if (err) 938 goto err_out; 939 940 if (num_q_vectors > MAX_Q_VECTORS) { 941 num_q_vectors = MAX_Q_VECTORS; 942 dev_warn(&adapter->pdev->dev, 943 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 944 adapter->num_q_vectors, MAX_Q_VECTORS); 945 } 946 for (i = 0; i < num_q_vectors; i++) { 947 struct igb_q_vector *q_vector = adapter->q_vector[i]; 948 949 vector++; 950 951 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 952 953 if (q_vector->rx.ring && q_vector->tx.ring) 954 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 955 q_vector->rx.ring->queue_index); 956 else if (q_vector->tx.ring) 957 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 958 q_vector->tx.ring->queue_index); 959 else if (q_vector->rx.ring) 960 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 961 q_vector->rx.ring->queue_index); 962 else 963 sprintf(q_vector->name, "%s-unused", netdev->name); 964 965 err = request_irq(adapter->msix_entries[vector].vector, 966 igb_msix_ring, 0, q_vector->name, 967 q_vector); 968 if (err) 969 goto err_free; 970 } 971 972 igb_configure_msix(adapter); 973 return 0; 974 975 err_free: 976 /* free already assigned IRQs */ 977 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 978 979 vector--; 980 for (i = 0; i < vector; i++) { 981 free_irq(adapter->msix_entries[free_vector++].vector, 982 adapter->q_vector[i]); 983 } 984 err_out: 985 return err; 986 } 987 988 /** 989 * igb_free_q_vector - Free memory allocated for specific interrupt vector 990 * @adapter: board private structure to initialize 991 * @v_idx: Index of vector to be freed 992 * 993 * This function frees the memory allocated to the q_vector. 994 **/ 995 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 996 { 997 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 998 999 adapter->q_vector[v_idx] = NULL; 1000 1001 /* igb_get_stats64() might access the rings on this vector, 1002 * we must wait a grace period before freeing it. 1003 */ 1004 if (q_vector) 1005 kfree_rcu(q_vector, rcu); 1006 } 1007 1008 /** 1009 * igb_reset_q_vector - Reset config for interrupt vector 1010 * @adapter: board private structure to initialize 1011 * @v_idx: Index of vector to be reset 1012 * 1013 * If NAPI is enabled it will delete any references to the 1014 * NAPI struct. This is preparation for igb_free_q_vector. 1015 **/ 1016 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1017 { 1018 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1019 1020 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1021 * allocated. So, q_vector is NULL so we should stop here. 1022 */ 1023 if (!q_vector) 1024 return; 1025 1026 if (q_vector->tx.ring) 1027 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1028 1029 if (q_vector->rx.ring) 1030 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1031 1032 netif_napi_del(&q_vector->napi); 1033 1034 } 1035 1036 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1037 { 1038 int v_idx = adapter->num_q_vectors; 1039 1040 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1041 pci_disable_msix(adapter->pdev); 1042 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1043 pci_disable_msi(adapter->pdev); 1044 1045 while (v_idx--) 1046 igb_reset_q_vector(adapter, v_idx); 1047 } 1048 1049 /** 1050 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1051 * @adapter: board private structure to initialize 1052 * 1053 * This function frees the memory allocated to the q_vectors. In addition if 1054 * NAPI is enabled it will delete any references to the NAPI struct prior 1055 * to freeing the q_vector. 1056 **/ 1057 static void igb_free_q_vectors(struct igb_adapter *adapter) 1058 { 1059 int v_idx = adapter->num_q_vectors; 1060 1061 adapter->num_tx_queues = 0; 1062 adapter->num_rx_queues = 0; 1063 adapter->num_q_vectors = 0; 1064 1065 while (v_idx--) { 1066 igb_reset_q_vector(adapter, v_idx); 1067 igb_free_q_vector(adapter, v_idx); 1068 } 1069 } 1070 1071 /** 1072 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1073 * @adapter: board private structure to initialize 1074 * 1075 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1076 * MSI-X interrupts allocated. 1077 */ 1078 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1079 { 1080 igb_free_q_vectors(adapter); 1081 igb_reset_interrupt_capability(adapter); 1082 } 1083 1084 /** 1085 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1086 * @adapter: board private structure to initialize 1087 * @msix: boolean value of MSIX capability 1088 * 1089 * Attempt to configure interrupts using the best available 1090 * capabilities of the hardware and kernel. 1091 **/ 1092 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1093 { 1094 int err; 1095 int numvecs, i; 1096 1097 if (!msix) 1098 goto msi_only; 1099 adapter->flags |= IGB_FLAG_HAS_MSIX; 1100 1101 /* Number of supported queues. */ 1102 adapter->num_rx_queues = adapter->rss_queues; 1103 if (adapter->vfs_allocated_count) 1104 adapter->num_tx_queues = 1; 1105 else 1106 adapter->num_tx_queues = adapter->rss_queues; 1107 1108 /* start with one vector for every Rx queue */ 1109 numvecs = adapter->num_rx_queues; 1110 1111 /* if Tx handler is separate add 1 for every Tx queue */ 1112 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1113 numvecs += adapter->num_tx_queues; 1114 1115 /* store the number of vectors reserved for queues */ 1116 adapter->num_q_vectors = numvecs; 1117 1118 /* add 1 vector for link status interrupts */ 1119 numvecs++; 1120 for (i = 0; i < numvecs; i++) 1121 adapter->msix_entries[i].entry = i; 1122 1123 err = pci_enable_msix_range(adapter->pdev, 1124 adapter->msix_entries, 1125 numvecs, 1126 numvecs); 1127 if (err > 0) 1128 return; 1129 1130 igb_reset_interrupt_capability(adapter); 1131 1132 /* If we can't do MSI-X, try MSI */ 1133 msi_only: 1134 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1135 #ifdef CONFIG_PCI_IOV 1136 /* disable SR-IOV for non MSI-X configurations */ 1137 if (adapter->vf_data) { 1138 struct e1000_hw *hw = &adapter->hw; 1139 /* disable iov and allow time for transactions to clear */ 1140 pci_disable_sriov(adapter->pdev); 1141 msleep(500); 1142 1143 kfree(adapter->vf_mac_list); 1144 adapter->vf_mac_list = NULL; 1145 kfree(adapter->vf_data); 1146 adapter->vf_data = NULL; 1147 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1148 wrfl(); 1149 msleep(100); 1150 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1151 } 1152 #endif 1153 adapter->vfs_allocated_count = 0; 1154 adapter->rss_queues = 1; 1155 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1156 adapter->num_rx_queues = 1; 1157 adapter->num_tx_queues = 1; 1158 adapter->num_q_vectors = 1; 1159 if (!pci_enable_msi(adapter->pdev)) 1160 adapter->flags |= IGB_FLAG_HAS_MSI; 1161 } 1162 1163 static void igb_add_ring(struct igb_ring *ring, 1164 struct igb_ring_container *head) 1165 { 1166 head->ring = ring; 1167 head->count++; 1168 } 1169 1170 /** 1171 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1172 * @adapter: board private structure to initialize 1173 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1174 * @v_idx: index of vector in adapter struct 1175 * @txr_count: total number of Tx rings to allocate 1176 * @txr_idx: index of first Tx ring to allocate 1177 * @rxr_count: total number of Rx rings to allocate 1178 * @rxr_idx: index of first Rx ring to allocate 1179 * 1180 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1181 **/ 1182 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1183 int v_count, int v_idx, 1184 int txr_count, int txr_idx, 1185 int rxr_count, int rxr_idx) 1186 { 1187 struct igb_q_vector *q_vector; 1188 struct igb_ring *ring; 1189 int ring_count; 1190 size_t size; 1191 1192 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1193 if (txr_count > 1 || rxr_count > 1) 1194 return -ENOMEM; 1195 1196 ring_count = txr_count + rxr_count; 1197 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1198 1199 /* allocate q_vector and rings */ 1200 q_vector = adapter->q_vector[v_idx]; 1201 if (!q_vector) { 1202 q_vector = kzalloc(size, GFP_KERNEL); 1203 } else if (size > ksize(q_vector)) { 1204 struct igb_q_vector *new_q_vector; 1205 1206 new_q_vector = kzalloc(size, GFP_KERNEL); 1207 if (new_q_vector) 1208 kfree_rcu(q_vector, rcu); 1209 q_vector = new_q_vector; 1210 } else { 1211 memset(q_vector, 0, size); 1212 } 1213 if (!q_vector) 1214 return -ENOMEM; 1215 1216 /* initialize NAPI */ 1217 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 ring->cbs_enable = false; 1264 ring->idleslope = 0; 1265 ring->sendslope = 0; 1266 ring->hicredit = 0; 1267 ring->locredit = 0; 1268 1269 u64_stats_init(&ring->tx_syncp); 1270 u64_stats_init(&ring->tx_syncp2); 1271 1272 /* assign ring to adapter */ 1273 adapter->tx_ring[txr_idx] = ring; 1274 1275 /* push pointer to next ring */ 1276 ring++; 1277 } 1278 1279 if (rxr_count) { 1280 /* assign generic ring traits */ 1281 ring->dev = &adapter->pdev->dev; 1282 ring->netdev = adapter->netdev; 1283 1284 /* configure backlink on ring */ 1285 ring->q_vector = q_vector; 1286 1287 /* update q_vector Rx values */ 1288 igb_add_ring(ring, &q_vector->rx); 1289 1290 /* set flag indicating ring supports SCTP checksum offload */ 1291 if (adapter->hw.mac.type >= e1000_82576) 1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1293 1294 /* On i350, i354, i210, and i211, loopback VLAN packets 1295 * have the tag byte-swapped. 1296 */ 1297 if (adapter->hw.mac.type >= e1000_i350) 1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1299 1300 /* apply Rx specific ring traits */ 1301 ring->count = adapter->rx_ring_count; 1302 ring->queue_index = rxr_idx; 1303 1304 u64_stats_init(&ring->rx_syncp); 1305 1306 /* assign ring to adapter */ 1307 adapter->rx_ring[rxr_idx] = ring; 1308 } 1309 1310 return 0; 1311 } 1312 1313 1314 /** 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1316 * @adapter: board private structure to initialize 1317 * 1318 * We allocate one q_vector per queue interrupt. If allocation fails we 1319 * return -ENOMEM. 1320 **/ 1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1322 { 1323 int q_vectors = adapter->num_q_vectors; 1324 int rxr_remaining = adapter->num_rx_queues; 1325 int txr_remaining = adapter->num_tx_queues; 1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1327 int err; 1328 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1330 for (; rxr_remaining; v_idx++) { 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 0, 0, 1, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining--; 1339 rxr_idx++; 1340 } 1341 } 1342 1343 for (; v_idx < q_vectors; v_idx++) { 1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1346 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1348 tqpv, txr_idx, rqpv, rxr_idx); 1349 1350 if (err) 1351 goto err_out; 1352 1353 /* update counts and index */ 1354 rxr_remaining -= rqpv; 1355 txr_remaining -= tqpv; 1356 rxr_idx++; 1357 txr_idx++; 1358 } 1359 1360 return 0; 1361 1362 err_out: 1363 adapter->num_tx_queues = 0; 1364 adapter->num_rx_queues = 0; 1365 adapter->num_q_vectors = 0; 1366 1367 while (v_idx--) 1368 igb_free_q_vector(adapter, v_idx); 1369 1370 return -ENOMEM; 1371 } 1372 1373 /** 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1375 * @adapter: board private structure to initialize 1376 * @msix: boolean value of MSIX capability 1377 * 1378 * This function initializes the interrupts and allocates all of the queues. 1379 **/ 1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1381 { 1382 struct pci_dev *pdev = adapter->pdev; 1383 int err; 1384 1385 igb_set_interrupt_capability(adapter, msix); 1386 1387 err = igb_alloc_q_vectors(adapter); 1388 if (err) { 1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1390 goto err_alloc_q_vectors; 1391 } 1392 1393 igb_cache_ring_register(adapter); 1394 1395 return 0; 1396 1397 err_alloc_q_vectors: 1398 igb_reset_interrupt_capability(adapter); 1399 return err; 1400 } 1401 1402 /** 1403 * igb_request_irq - initialize interrupts 1404 * @adapter: board private structure to initialize 1405 * 1406 * Attempts to configure interrupts using the best available 1407 * capabilities of the hardware and kernel. 1408 **/ 1409 static int igb_request_irq(struct igb_adapter *adapter) 1410 { 1411 struct net_device *netdev = adapter->netdev; 1412 struct pci_dev *pdev = adapter->pdev; 1413 int err = 0; 1414 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1416 err = igb_request_msix(adapter); 1417 if (!err) 1418 goto request_done; 1419 /* fall back to MSI */ 1420 igb_free_all_tx_resources(adapter); 1421 igb_free_all_rx_resources(adapter); 1422 1423 igb_clear_interrupt_scheme(adapter); 1424 err = igb_init_interrupt_scheme(adapter, false); 1425 if (err) 1426 goto request_done; 1427 1428 igb_setup_all_tx_resources(adapter); 1429 igb_setup_all_rx_resources(adapter); 1430 igb_configure(adapter); 1431 } 1432 1433 igb_assign_vector(adapter->q_vector[0], 0); 1434 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1436 err = request_irq(pdev->irq, igb_intr_msi, 0, 1437 netdev->name, adapter); 1438 if (!err) 1439 goto request_done; 1440 1441 /* fall back to legacy interrupts */ 1442 igb_reset_interrupt_capability(adapter); 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1444 } 1445 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1447 netdev->name, adapter); 1448 1449 if (err) 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1451 err); 1452 1453 request_done: 1454 return err; 1455 } 1456 1457 static void igb_free_irq(struct igb_adapter *adapter) 1458 { 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1460 int vector = 0, i; 1461 1462 free_irq(adapter->msix_entries[vector++].vector, adapter); 1463 1464 for (i = 0; i < adapter->num_q_vectors; i++) 1465 free_irq(adapter->msix_entries[vector++].vector, 1466 adapter->q_vector[i]); 1467 } else { 1468 free_irq(adapter->pdev->irq, adapter); 1469 } 1470 } 1471 1472 /** 1473 * igb_irq_disable - Mask off interrupt generation on the NIC 1474 * @adapter: board private structure 1475 **/ 1476 static void igb_irq_disable(struct igb_adapter *adapter) 1477 { 1478 struct e1000_hw *hw = &adapter->hw; 1479 1480 /* we need to be careful when disabling interrupts. The VFs are also 1481 * mapped into these registers and so clearing the bits can cause 1482 * issues on the VF drivers so we only need to clear what we set 1483 */ 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 regval = rd32(E1000_EIAM); 1486 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1488 wr32(E1000_EIMC, adapter->eims_enable_mask); 1489 regval = rd32(E1000_EIAC); 1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1491 } 1492 1493 wr32(E1000_IAM, 0); 1494 wr32(E1000_IMC, ~0); 1495 wrfl(); 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1497 int i; 1498 1499 for (i = 0; i < adapter->num_q_vectors; i++) 1500 synchronize_irq(adapter->msix_entries[i].vector); 1501 } else { 1502 synchronize_irq(adapter->pdev->irq); 1503 } 1504 } 1505 1506 /** 1507 * igb_irq_enable - Enable default interrupt generation settings 1508 * @adapter: board private structure 1509 **/ 1510 static void igb_irq_enable(struct igb_adapter *adapter) 1511 { 1512 struct e1000_hw *hw = &adapter->hw; 1513 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1516 u32 regval = rd32(E1000_EIAC); 1517 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1519 regval = rd32(E1000_EIAM); 1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1521 wr32(E1000_EIMS, adapter->eims_enable_mask); 1522 if (adapter->vfs_allocated_count) { 1523 wr32(E1000_MBVFIMR, 0xFF); 1524 ims |= E1000_IMS_VMMB; 1525 } 1526 wr32(E1000_IMS, ims); 1527 } else { 1528 wr32(E1000_IMS, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 wr32(E1000_IAM, IMS_ENABLE_MASK | 1531 E1000_IMS_DRSTA); 1532 } 1533 } 1534 1535 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1536 { 1537 struct e1000_hw *hw = &adapter->hw; 1538 u16 pf_id = adapter->vfs_allocated_count; 1539 u16 vid = adapter->hw.mng_cookie.vlan_id; 1540 u16 old_vid = adapter->mng_vlan_id; 1541 1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1543 /* add VID to filter table */ 1544 igb_vfta_set(hw, vid, pf_id, true, true); 1545 adapter->mng_vlan_id = vid; 1546 } else { 1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1548 } 1549 1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1551 (vid != old_vid) && 1552 !test_bit(old_vid, adapter->active_vlans)) { 1553 /* remove VID from filter table */ 1554 igb_vfta_set(hw, vid, pf_id, false, true); 1555 } 1556 } 1557 1558 /** 1559 * igb_release_hw_control - release control of the h/w to f/w 1560 * @adapter: address of board private structure 1561 * 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1563 * For ASF and Pass Through versions of f/w this means that the 1564 * driver is no longer loaded. 1565 **/ 1566 static void igb_release_hw_control(struct igb_adapter *adapter) 1567 { 1568 struct e1000_hw *hw = &adapter->hw; 1569 u32 ctrl_ext; 1570 1571 /* Let firmware take over control of h/w */ 1572 ctrl_ext = rd32(E1000_CTRL_EXT); 1573 wr32(E1000_CTRL_EXT, 1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1575 } 1576 1577 /** 1578 * igb_get_hw_control - get control of the h/w from f/w 1579 * @adapter: address of board private structure 1580 * 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1582 * For ASF and Pass Through versions of f/w this means that 1583 * the driver is loaded. 1584 **/ 1585 static void igb_get_hw_control(struct igb_adapter *adapter) 1586 { 1587 struct e1000_hw *hw = &adapter->hw; 1588 u32 ctrl_ext; 1589 1590 /* Let firmware know the driver has taken over */ 1591 ctrl_ext = rd32(E1000_CTRL_EXT); 1592 wr32(E1000_CTRL_EXT, 1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1594 } 1595 1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1597 { 1598 struct net_device *netdev = adapter->netdev; 1599 struct e1000_hw *hw = &adapter->hw; 1600 1601 WARN_ON(hw->mac.type != e1000_i210); 1602 1603 if (enable) 1604 adapter->flags |= IGB_FLAG_FQTSS; 1605 else 1606 adapter->flags &= ~IGB_FLAG_FQTSS; 1607 1608 if (netif_running(netdev)) 1609 schedule_work(&adapter->reset_task); 1610 } 1611 1612 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1613 { 1614 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1615 } 1616 1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1618 enum tx_queue_prio prio) 1619 { 1620 u32 val; 1621 1622 WARN_ON(hw->mac.type != e1000_i210); 1623 WARN_ON(queue < 0 || queue > 4); 1624 1625 val = rd32(E1000_I210_TXDCTL(queue)); 1626 1627 if (prio == TX_QUEUE_PRIO_HIGH) 1628 val |= E1000_TXDCTL_PRIORITY; 1629 else 1630 val &= ~E1000_TXDCTL_PRIORITY; 1631 1632 wr32(E1000_I210_TXDCTL(queue), val); 1633 } 1634 1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1636 { 1637 u32 val; 1638 1639 WARN_ON(hw->mac.type != e1000_i210); 1640 WARN_ON(queue < 0 || queue > 1); 1641 1642 val = rd32(E1000_I210_TQAVCC(queue)); 1643 1644 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1645 val |= E1000_TQAVCC_QUEUEMODE; 1646 else 1647 val &= ~E1000_TQAVCC_QUEUEMODE; 1648 1649 wr32(E1000_I210_TQAVCC(queue), val); 1650 } 1651 1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1653 { 1654 int i; 1655 1656 for (i = 0; i < adapter->num_tx_queues; i++) { 1657 if (adapter->tx_ring[i]->cbs_enable) 1658 return true; 1659 } 1660 1661 return false; 1662 } 1663 1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1665 { 1666 int i; 1667 1668 for (i = 0; i < adapter->num_tx_queues; i++) { 1669 if (adapter->tx_ring[i]->launchtime_enable) 1670 return true; 1671 } 1672 1673 return false; 1674 } 1675 1676 /** 1677 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1678 * @adapter: pointer to adapter struct 1679 * @queue: queue number 1680 * 1681 * Configure CBS and Launchtime for a given hardware queue. 1682 * Parameters are retrieved from the correct Tx ring, so 1683 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1684 * for setting those correctly prior to this function being called. 1685 **/ 1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1687 { 1688 struct net_device *netdev = adapter->netdev; 1689 struct e1000_hw *hw = &adapter->hw; 1690 struct igb_ring *ring; 1691 u32 tqavcc, tqavctrl; 1692 u16 value; 1693 1694 WARN_ON(hw->mac.type != e1000_i210); 1695 WARN_ON(queue < 0 || queue > 1); 1696 ring = adapter->tx_ring[queue]; 1697 1698 /* If any of the Qav features is enabled, configure queues as SR and 1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1700 * as SP. 1701 */ 1702 if (ring->cbs_enable || ring->launchtime_enable) { 1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1705 } else { 1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1708 } 1709 1710 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1711 if (ring->cbs_enable || queue == 0) { 1712 /* i210 does not allow the queue 0 to be in the Strict 1713 * Priority mode while the Qav mode is enabled, so, 1714 * instead of disabling strict priority mode, we give 1715 * queue 0 the maximum of credits possible. 1716 * 1717 * See section 8.12.19 of the i210 datasheet, "Note: 1718 * Queue0 QueueMode must be set to 1b when 1719 * TransmitMode is set to Qav." 1720 */ 1721 if (queue == 0 && !ring->cbs_enable) { 1722 /* max "linkspeed" idleslope in kbps */ 1723 ring->idleslope = 1000000; 1724 ring->hicredit = ETH_FRAME_LEN; 1725 } 1726 1727 /* Always set data transfer arbitration to credit-based 1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1729 * the queues. 1730 */ 1731 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1733 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1734 1735 /* According to i210 datasheet section 7.2.7.7, we should set 1736 * the 'idleSlope' field from TQAVCC register following the 1737 * equation: 1738 * 1739 * For 100 Mbps link speed: 1740 * 1741 * value = BW * 0x7735 * 0.2 (E1) 1742 * 1743 * For 1000Mbps link speed: 1744 * 1745 * value = BW * 0x7735 * 2 (E2) 1746 * 1747 * E1 and E2 can be merged into one equation as shown below. 1748 * Note that 'link-speed' is in Mbps. 1749 * 1750 * value = BW * 0x7735 * 2 * link-speed 1751 * -------------- (E3) 1752 * 1000 1753 * 1754 * 'BW' is the percentage bandwidth out of full link speed 1755 * which can be found with the following equation. Note that 1756 * idleSlope here is the parameter from this function which 1757 * is in kbps. 1758 * 1759 * BW = idleSlope 1760 * ----------------- (E4) 1761 * link-speed * 1000 1762 * 1763 * That said, we can come up with a generic equation to 1764 * calculate the value we should set it TQAVCC register by 1765 * replacing 'BW' in E3 by E4. The resulting equation is: 1766 * 1767 * value = idleSlope * 0x7735 * 2 * link-speed 1768 * ----------------- -------------- (E5) 1769 * link-speed * 1000 1000 1770 * 1771 * 'link-speed' is present in both sides of the fraction so 1772 * it is canceled out. The final equation is the following: 1773 * 1774 * value = idleSlope * 61034 1775 * ----------------- (E6) 1776 * 1000000 1777 * 1778 * NOTE: For i210, given the above, we can see that idleslope 1779 * is represented in 16.38431 kbps units by the value at 1780 * the TQAVCC register (1Gbps / 61034), which reduces 1781 * the granularity for idleslope increments. 1782 * For instance, if you want to configure a 2576kbps 1783 * idleslope, the value to be written on the register 1784 * would have to be 157.23. If rounded down, you end 1785 * up with less bandwidth available than originally 1786 * required (~2572 kbps). If rounded up, you end up 1787 * with a higher bandwidth (~2589 kbps). Below the 1788 * approach we take is to always round up the 1789 * calculated value, so the resulting bandwidth might 1790 * be slightly higher for some configurations. 1791 */ 1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1793 1794 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1796 tqavcc |= value; 1797 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1798 1799 wr32(E1000_I210_TQAVHC(queue), 1800 0x80000000 + ring->hicredit * 0x7735); 1801 } else { 1802 1803 /* Set idleSlope to zero. */ 1804 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1806 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1807 1808 /* Set hiCredit to zero. */ 1809 wr32(E1000_I210_TQAVHC(queue), 0); 1810 1811 /* If CBS is not enabled for any queues anymore, then return to 1812 * the default state of Data Transmission Arbitration on 1813 * TQAVCTRL. 1814 */ 1815 if (!is_any_cbs_enabled(adapter)) { 1816 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } 1820 } 1821 1822 /* If LaunchTime is enabled, set DataTranTIM. */ 1823 if (ring->launchtime_enable) { 1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1825 * for any of the SR queues, and configure fetchtime delta. 1826 * XXX NOTE: 1827 * - LaunchTime will be enabled for all SR queues. 1828 * - A fixed offset can be added relative to the launch 1829 * time of all packets if configured at reg LAUNCH_OS0. 1830 * We are keeping it as 0 for now (default value). 1831 */ 1832 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1834 E1000_TQAVCTRL_FETCHTIME_DELTA; 1835 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1836 } else { 1837 /* If Launchtime is not enabled for any SR queues anymore, 1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1839 * effectively disabling Launchtime. 1840 */ 1841 if (!is_any_txtime_enabled(adapter)) { 1842 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1845 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1846 } 1847 } 1848 1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1850 * CBS are not configurable by software so we don't do any 'controller 1851 * configuration' in respect to these parameters. 1852 */ 1853 1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1855 ring->cbs_enable ? "enabled" : "disabled", 1856 ring->launchtime_enable ? "enabled" : "disabled", 1857 queue, 1858 ring->idleslope, ring->sendslope, 1859 ring->hicredit, ring->locredit); 1860 } 1861 1862 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1863 bool enable) 1864 { 1865 struct igb_ring *ring; 1866 1867 if (queue < 0 || queue > adapter->num_tx_queues) 1868 return -EINVAL; 1869 1870 ring = adapter->tx_ring[queue]; 1871 ring->launchtime_enable = enable; 1872 1873 return 0; 1874 } 1875 1876 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1877 bool enable, int idleslope, int sendslope, 1878 int hicredit, int locredit) 1879 { 1880 struct igb_ring *ring; 1881 1882 if (queue < 0 || queue > adapter->num_tx_queues) 1883 return -EINVAL; 1884 1885 ring = adapter->tx_ring[queue]; 1886 1887 ring->cbs_enable = enable; 1888 ring->idleslope = idleslope; 1889 ring->sendslope = sendslope; 1890 ring->hicredit = hicredit; 1891 ring->locredit = locredit; 1892 1893 return 0; 1894 } 1895 1896 /** 1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1898 * @adapter: pointer to adapter struct 1899 * 1900 * Configure TQAVCTRL register switching the controller's Tx mode 1901 * if FQTSS mode is enabled or disabled. Additionally, will issue 1902 * a call to igb_config_tx_modes() per queue so any previously saved 1903 * Tx parameters are applied. 1904 **/ 1905 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1906 { 1907 struct net_device *netdev = adapter->netdev; 1908 struct e1000_hw *hw = &adapter->hw; 1909 u32 val; 1910 1911 /* Only i210 controller supports changing the transmission mode. */ 1912 if (hw->mac.type != e1000_i210) 1913 return; 1914 1915 if (is_fqtss_enabled(adapter)) { 1916 int i, max_queue; 1917 1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1920 * so SP queues wait for SR ones. 1921 */ 1922 val = rd32(E1000_I210_TQAVCTRL); 1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1925 wr32(E1000_I210_TQAVCTRL, val); 1926 1927 /* Configure Tx and Rx packet buffers sizes as described in 1928 * i210 datasheet section 7.2.7.7. 1929 */ 1930 val = rd32(E1000_TXPBS); 1931 val &= ~I210_TXPBSIZE_MASK; 1932 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1933 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1934 wr32(E1000_TXPBS, val); 1935 1936 val = rd32(E1000_RXPBS); 1937 val &= ~I210_RXPBSIZE_MASK; 1938 val |= I210_RXPBSIZE_PB_30KB; 1939 wr32(E1000_RXPBS, val); 1940 1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1942 * register should not exceed the buffer size programmed in 1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1944 * so according to the datasheet we should set MAX_TPKT_SIZE to 1945 * 4kB / 64. 1946 * 1947 * However, when we do so, no frame from queue 2 and 3 are 1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1949 * or _equal_ to the buffer size programmed in TXPBS. For this 1950 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1951 */ 1952 val = (4096 - 1) / 64; 1953 wr32(E1000_I210_DTXMXPKTSZ, val); 1954 1955 /* Since FQTSS mode is enabled, apply any CBS configuration 1956 * previously set. If no previous CBS configuration has been 1957 * done, then the initial configuration is applied, which means 1958 * CBS is disabled. 1959 */ 1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1962 1963 for (i = 0; i < max_queue; i++) { 1964 igb_config_tx_modes(adapter, i); 1965 } 1966 } else { 1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1970 1971 val = rd32(E1000_I210_TQAVCTRL); 1972 /* According to Section 8.12.21, the other flags we've set when 1973 * enabling FQTSS are not relevant when disabling FQTSS so we 1974 * don't set they here. 1975 */ 1976 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1977 wr32(E1000_I210_TQAVCTRL, val); 1978 } 1979 1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1981 "enabled" : "disabled"); 1982 } 1983 1984 /** 1985 * igb_configure - configure the hardware for RX and TX 1986 * @adapter: private board structure 1987 **/ 1988 static void igb_configure(struct igb_adapter *adapter) 1989 { 1990 struct net_device *netdev = adapter->netdev; 1991 int i; 1992 1993 igb_get_hw_control(adapter); 1994 igb_set_rx_mode(netdev); 1995 igb_setup_tx_mode(adapter); 1996 1997 igb_restore_vlan(adapter); 1998 1999 igb_setup_tctl(adapter); 2000 igb_setup_mrqc(adapter); 2001 igb_setup_rctl(adapter); 2002 2003 igb_nfc_filter_restore(adapter); 2004 igb_configure_tx(adapter); 2005 igb_configure_rx(adapter); 2006 2007 igb_rx_fifo_flush_82575(&adapter->hw); 2008 2009 /* call igb_desc_unused which always leaves 2010 * at least 1 descriptor unused to make sure 2011 * next_to_use != next_to_clean 2012 */ 2013 for (i = 0; i < adapter->num_rx_queues; i++) { 2014 struct igb_ring *ring = adapter->rx_ring[i]; 2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2016 } 2017 } 2018 2019 /** 2020 * igb_power_up_link - Power up the phy/serdes link 2021 * @adapter: address of board private structure 2022 **/ 2023 void igb_power_up_link(struct igb_adapter *adapter) 2024 { 2025 igb_reset_phy(&adapter->hw); 2026 2027 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2028 igb_power_up_phy_copper(&adapter->hw); 2029 else 2030 igb_power_up_serdes_link_82575(&adapter->hw); 2031 2032 igb_setup_link(&adapter->hw); 2033 } 2034 2035 /** 2036 * igb_power_down_link - Power down the phy/serdes link 2037 * @adapter: address of board private structure 2038 */ 2039 static void igb_power_down_link(struct igb_adapter *adapter) 2040 { 2041 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2042 igb_power_down_phy_copper_82575(&adapter->hw); 2043 else 2044 igb_shutdown_serdes_link_82575(&adapter->hw); 2045 } 2046 2047 /** 2048 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2049 * @adapter: address of the board private structure 2050 **/ 2051 static void igb_check_swap_media(struct igb_adapter *adapter) 2052 { 2053 struct e1000_hw *hw = &adapter->hw; 2054 u32 ctrl_ext, connsw; 2055 bool swap_now = false; 2056 2057 ctrl_ext = rd32(E1000_CTRL_EXT); 2058 connsw = rd32(E1000_CONNSW); 2059 2060 /* need to live swap if current media is copper and we have fiber/serdes 2061 * to go to. 2062 */ 2063 2064 if ((hw->phy.media_type == e1000_media_type_copper) && 2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2066 swap_now = true; 2067 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2068 !(connsw & E1000_CONNSW_SERDESD)) { 2069 /* copper signal takes time to appear */ 2070 if (adapter->copper_tries < 4) { 2071 adapter->copper_tries++; 2072 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 return; 2075 } else { 2076 adapter->copper_tries = 0; 2077 if ((connsw & E1000_CONNSW_PHYSD) && 2078 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2079 swap_now = true; 2080 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2081 wr32(E1000_CONNSW, connsw); 2082 } 2083 } 2084 } 2085 2086 if (!swap_now) 2087 return; 2088 2089 switch (hw->phy.media_type) { 2090 case e1000_media_type_copper: 2091 netdev_info(adapter->netdev, 2092 "MAS: changing media to fiber/serdes\n"); 2093 ctrl_ext |= 2094 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2095 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2096 adapter->copper_tries = 0; 2097 break; 2098 case e1000_media_type_internal_serdes: 2099 case e1000_media_type_fiber: 2100 netdev_info(adapter->netdev, 2101 "MAS: changing media to copper\n"); 2102 ctrl_ext &= 2103 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2104 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2105 break; 2106 default: 2107 /* shouldn't get here during regular operation */ 2108 netdev_err(adapter->netdev, 2109 "AMS: Invalid media type found, returning\n"); 2110 break; 2111 } 2112 wr32(E1000_CTRL_EXT, ctrl_ext); 2113 } 2114 2115 /** 2116 * igb_up - Open the interface and prepare it to handle traffic 2117 * @adapter: board private structure 2118 **/ 2119 int igb_up(struct igb_adapter *adapter) 2120 { 2121 struct e1000_hw *hw = &adapter->hw; 2122 int i; 2123 2124 /* hardware has been reset, we need to reload some things */ 2125 igb_configure(adapter); 2126 2127 clear_bit(__IGB_DOWN, &adapter->state); 2128 2129 for (i = 0; i < adapter->num_q_vectors; i++) 2130 napi_enable(&(adapter->q_vector[i]->napi)); 2131 2132 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2133 igb_configure_msix(adapter); 2134 else 2135 igb_assign_vector(adapter->q_vector[0], 0); 2136 2137 /* Clear any pending interrupts. */ 2138 rd32(E1000_TSICR); 2139 rd32(E1000_ICR); 2140 igb_irq_enable(adapter); 2141 2142 /* notify VFs that reset has been completed */ 2143 if (adapter->vfs_allocated_count) { 2144 u32 reg_data = rd32(E1000_CTRL_EXT); 2145 2146 reg_data |= E1000_CTRL_EXT_PFRSTD; 2147 wr32(E1000_CTRL_EXT, reg_data); 2148 } 2149 2150 netif_tx_start_all_queues(adapter->netdev); 2151 2152 /* start the watchdog. */ 2153 hw->mac.get_link_status = 1; 2154 schedule_work(&adapter->watchdog_task); 2155 2156 if ((adapter->flags & IGB_FLAG_EEE) && 2157 (!hw->dev_spec._82575.eee_disable)) 2158 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2159 2160 return 0; 2161 } 2162 2163 void igb_down(struct igb_adapter *adapter) 2164 { 2165 struct net_device *netdev = adapter->netdev; 2166 struct e1000_hw *hw = &adapter->hw; 2167 u32 tctl, rctl; 2168 int i; 2169 2170 /* signal that we're down so the interrupt handler does not 2171 * reschedule our watchdog timer 2172 */ 2173 set_bit(__IGB_DOWN, &adapter->state); 2174 2175 /* disable receives in the hardware */ 2176 rctl = rd32(E1000_RCTL); 2177 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2178 /* flush and sleep below */ 2179 2180 igb_nfc_filter_exit(adapter); 2181 2182 netif_carrier_off(netdev); 2183 netif_tx_stop_all_queues(netdev); 2184 2185 /* disable transmits in the hardware */ 2186 tctl = rd32(E1000_TCTL); 2187 tctl &= ~E1000_TCTL_EN; 2188 wr32(E1000_TCTL, tctl); 2189 /* flush both disables and wait for them to finish */ 2190 wrfl(); 2191 usleep_range(10000, 11000); 2192 2193 igb_irq_disable(adapter); 2194 2195 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2196 2197 for (i = 0; i < adapter->num_q_vectors; i++) { 2198 if (adapter->q_vector[i]) { 2199 napi_synchronize(&adapter->q_vector[i]->napi); 2200 napi_disable(&adapter->q_vector[i]->napi); 2201 } 2202 } 2203 2204 del_timer_sync(&adapter->watchdog_timer); 2205 del_timer_sync(&adapter->phy_info_timer); 2206 2207 /* record the stats before reset*/ 2208 spin_lock(&adapter->stats64_lock); 2209 igb_update_stats(adapter); 2210 spin_unlock(&adapter->stats64_lock); 2211 2212 adapter->link_speed = 0; 2213 adapter->link_duplex = 0; 2214 2215 if (!pci_channel_offline(adapter->pdev)) 2216 igb_reset(adapter); 2217 2218 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2219 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2220 2221 igb_clean_all_tx_rings(adapter); 2222 igb_clean_all_rx_rings(adapter); 2223 #ifdef CONFIG_IGB_DCA 2224 2225 /* since we reset the hardware DCA settings were cleared */ 2226 igb_setup_dca(adapter); 2227 #endif 2228 } 2229 2230 void igb_reinit_locked(struct igb_adapter *adapter) 2231 { 2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2233 usleep_range(1000, 2000); 2234 igb_down(adapter); 2235 igb_up(adapter); 2236 clear_bit(__IGB_RESETTING, &adapter->state); 2237 } 2238 2239 /** igb_enable_mas - Media Autosense re-enable after swap 2240 * 2241 * @adapter: adapter struct 2242 **/ 2243 static void igb_enable_mas(struct igb_adapter *adapter) 2244 { 2245 struct e1000_hw *hw = &adapter->hw; 2246 u32 connsw = rd32(E1000_CONNSW); 2247 2248 /* configure for SerDes media detect */ 2249 if ((hw->phy.media_type == e1000_media_type_copper) && 2250 (!(connsw & E1000_CONNSW_SERDESD))) { 2251 connsw |= E1000_CONNSW_ENRGSRC; 2252 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2253 wr32(E1000_CONNSW, connsw); 2254 wrfl(); 2255 } 2256 } 2257 2258 #ifdef CONFIG_IGB_HWMON 2259 /** 2260 * igb_set_i2c_bb - Init I2C interface 2261 * @hw: pointer to hardware structure 2262 **/ 2263 static void igb_set_i2c_bb(struct e1000_hw *hw) 2264 { 2265 u32 ctrl_ext; 2266 s32 i2cctl; 2267 2268 ctrl_ext = rd32(E1000_CTRL_EXT); 2269 ctrl_ext |= E1000_CTRL_I2C_ENA; 2270 wr32(E1000_CTRL_EXT, ctrl_ext); 2271 wrfl(); 2272 2273 i2cctl = rd32(E1000_I2CPARAMS); 2274 i2cctl |= E1000_I2CBB_EN 2275 | E1000_I2C_CLK_OE_N 2276 | E1000_I2C_DATA_OE_N; 2277 wr32(E1000_I2CPARAMS, i2cctl); 2278 wrfl(); 2279 } 2280 #endif 2281 2282 void igb_reset(struct igb_adapter *adapter) 2283 { 2284 struct pci_dev *pdev = adapter->pdev; 2285 struct e1000_hw *hw = &adapter->hw; 2286 struct e1000_mac_info *mac = &hw->mac; 2287 struct e1000_fc_info *fc = &hw->fc; 2288 u32 pba, hwm; 2289 2290 /* Repartition Pba for greater than 9k mtu 2291 * To take effect CTRL.RST is required. 2292 */ 2293 switch (mac->type) { 2294 case e1000_i350: 2295 case e1000_i354: 2296 case e1000_82580: 2297 pba = rd32(E1000_RXPBS); 2298 pba = igb_rxpbs_adjust_82580(pba); 2299 break; 2300 case e1000_82576: 2301 pba = rd32(E1000_RXPBS); 2302 pba &= E1000_RXPBS_SIZE_MASK_82576; 2303 break; 2304 case e1000_82575: 2305 case e1000_i210: 2306 case e1000_i211: 2307 default: 2308 pba = E1000_PBA_34K; 2309 break; 2310 } 2311 2312 if (mac->type == e1000_82575) { 2313 u32 min_rx_space, min_tx_space, needed_tx_space; 2314 2315 /* write Rx PBA so that hardware can report correct Tx PBA */ 2316 wr32(E1000_PBA, pba); 2317 2318 /* To maintain wire speed transmits, the Tx FIFO should be 2319 * large enough to accommodate two full transmit packets, 2320 * rounded up to the next 1KB and expressed in KB. Likewise, 2321 * the Rx FIFO should be large enough to accommodate at least 2322 * one full receive packet and is similarly rounded up and 2323 * expressed in KB. 2324 */ 2325 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2326 2327 /* The Tx FIFO also stores 16 bytes of information about the Tx 2328 * but don't include Ethernet FCS because hardware appends it. 2329 * We only need to round down to the nearest 512 byte block 2330 * count since the value we care about is 2 frames, not 1. 2331 */ 2332 min_tx_space = adapter->max_frame_size; 2333 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2334 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2335 2336 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2337 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2338 2339 /* If current Tx allocation is less than the min Tx FIFO size, 2340 * and the min Tx FIFO size is less than the current Rx FIFO 2341 * allocation, take space away from current Rx allocation. 2342 */ 2343 if (needed_tx_space < pba) { 2344 pba -= needed_tx_space; 2345 2346 /* if short on Rx space, Rx wins and must trump Tx 2347 * adjustment 2348 */ 2349 if (pba < min_rx_space) 2350 pba = min_rx_space; 2351 } 2352 2353 /* adjust PBA for jumbo frames */ 2354 wr32(E1000_PBA, pba); 2355 } 2356 2357 /* flow control settings 2358 * The high water mark must be low enough to fit one full frame 2359 * after transmitting the pause frame. As such we must have enough 2360 * space to allow for us to complete our current transmit and then 2361 * receive the frame that is in progress from the link partner. 2362 * Set it to: 2363 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2364 */ 2365 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2366 2367 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2368 fc->low_water = fc->high_water - 16; 2369 fc->pause_time = 0xFFFF; 2370 fc->send_xon = 1; 2371 fc->current_mode = fc->requested_mode; 2372 2373 /* disable receive for all VFs and wait one second */ 2374 if (adapter->vfs_allocated_count) { 2375 int i; 2376 2377 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2378 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2379 2380 /* ping all the active vfs to let them know we are going down */ 2381 igb_ping_all_vfs(adapter); 2382 2383 /* disable transmits and receives */ 2384 wr32(E1000_VFRE, 0); 2385 wr32(E1000_VFTE, 0); 2386 } 2387 2388 /* Allow time for pending master requests to run */ 2389 hw->mac.ops.reset_hw(hw); 2390 wr32(E1000_WUC, 0); 2391 2392 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2393 /* need to resetup here after media swap */ 2394 adapter->ei.get_invariants(hw); 2395 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2396 } 2397 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2398 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2399 igb_enable_mas(adapter); 2400 } 2401 if (hw->mac.ops.init_hw(hw)) 2402 dev_err(&pdev->dev, "Hardware Error\n"); 2403 2404 /* RAR registers were cleared during init_hw, clear mac table */ 2405 igb_flush_mac_table(adapter); 2406 __dev_uc_unsync(adapter->netdev, NULL); 2407 2408 /* Recover default RAR entry */ 2409 igb_set_default_mac_filter(adapter); 2410 2411 /* Flow control settings reset on hardware reset, so guarantee flow 2412 * control is off when forcing speed. 2413 */ 2414 if (!hw->mac.autoneg) 2415 igb_force_mac_fc(hw); 2416 2417 igb_init_dmac(adapter, pba); 2418 #ifdef CONFIG_IGB_HWMON 2419 /* Re-initialize the thermal sensor on i350 devices. */ 2420 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2421 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2422 /* If present, re-initialize the external thermal sensor 2423 * interface. 2424 */ 2425 if (adapter->ets) 2426 igb_set_i2c_bb(hw); 2427 mac->ops.init_thermal_sensor_thresh(hw); 2428 } 2429 } 2430 #endif 2431 /* Re-establish EEE setting */ 2432 if (hw->phy.media_type == e1000_media_type_copper) { 2433 switch (mac->type) { 2434 case e1000_i350: 2435 case e1000_i210: 2436 case e1000_i211: 2437 igb_set_eee_i350(hw, true, true); 2438 break; 2439 case e1000_i354: 2440 igb_set_eee_i354(hw, true, true); 2441 break; 2442 default: 2443 break; 2444 } 2445 } 2446 if (!netif_running(adapter->netdev)) 2447 igb_power_down_link(adapter); 2448 2449 igb_update_mng_vlan(adapter); 2450 2451 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2452 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2453 2454 /* Re-enable PTP, where applicable. */ 2455 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2456 igb_ptp_reset(adapter); 2457 2458 igb_get_phy_info(hw); 2459 } 2460 2461 static netdev_features_t igb_fix_features(struct net_device *netdev, 2462 netdev_features_t features) 2463 { 2464 /* Since there is no support for separate Rx/Tx vlan accel 2465 * enable/disable make sure Tx flag is always in same state as Rx. 2466 */ 2467 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2468 features |= NETIF_F_HW_VLAN_CTAG_TX; 2469 else 2470 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2471 2472 return features; 2473 } 2474 2475 static int igb_set_features(struct net_device *netdev, 2476 netdev_features_t features) 2477 { 2478 netdev_features_t changed = netdev->features ^ features; 2479 struct igb_adapter *adapter = netdev_priv(netdev); 2480 2481 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2482 igb_vlan_mode(netdev, features); 2483 2484 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2485 return 0; 2486 2487 if (!(features & NETIF_F_NTUPLE)) { 2488 struct hlist_node *node2; 2489 struct igb_nfc_filter *rule; 2490 2491 spin_lock(&adapter->nfc_lock); 2492 hlist_for_each_entry_safe(rule, node2, 2493 &adapter->nfc_filter_list, nfc_node) { 2494 igb_erase_filter(adapter, rule); 2495 hlist_del(&rule->nfc_node); 2496 kfree(rule); 2497 } 2498 spin_unlock(&adapter->nfc_lock); 2499 adapter->nfc_filter_count = 0; 2500 } 2501 2502 netdev->features = features; 2503 2504 if (netif_running(netdev)) 2505 igb_reinit_locked(adapter); 2506 else 2507 igb_reset(adapter); 2508 2509 return 1; 2510 } 2511 2512 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2513 struct net_device *dev, 2514 const unsigned char *addr, u16 vid, 2515 u16 flags, 2516 struct netlink_ext_ack *extack) 2517 { 2518 /* guarantee we can provide a unique filter for the unicast address */ 2519 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2520 struct igb_adapter *adapter = netdev_priv(dev); 2521 int vfn = adapter->vfs_allocated_count; 2522 2523 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2524 return -ENOMEM; 2525 } 2526 2527 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2528 } 2529 2530 #define IGB_MAX_MAC_HDR_LEN 127 2531 #define IGB_MAX_NETWORK_HDR_LEN 511 2532 2533 static netdev_features_t 2534 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2535 netdev_features_t features) 2536 { 2537 unsigned int network_hdr_len, mac_hdr_len; 2538 2539 /* Make certain the headers can be described by a context descriptor */ 2540 mac_hdr_len = skb_network_header(skb) - skb->data; 2541 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2542 return features & ~(NETIF_F_HW_CSUM | 2543 NETIF_F_SCTP_CRC | 2544 NETIF_F_GSO_UDP_L4 | 2545 NETIF_F_HW_VLAN_CTAG_TX | 2546 NETIF_F_TSO | 2547 NETIF_F_TSO6); 2548 2549 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2550 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2551 return features & ~(NETIF_F_HW_CSUM | 2552 NETIF_F_SCTP_CRC | 2553 NETIF_F_GSO_UDP_L4 | 2554 NETIF_F_TSO | 2555 NETIF_F_TSO6); 2556 2557 /* We can only support IPV4 TSO in tunnels if we can mangle the 2558 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2559 */ 2560 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2561 features &= ~NETIF_F_TSO; 2562 2563 return features; 2564 } 2565 2566 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2567 { 2568 if (!is_fqtss_enabled(adapter)) { 2569 enable_fqtss(adapter, true); 2570 return; 2571 } 2572 2573 igb_config_tx_modes(adapter, queue); 2574 2575 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2576 enable_fqtss(adapter, false); 2577 } 2578 2579 static int igb_offload_cbs(struct igb_adapter *adapter, 2580 struct tc_cbs_qopt_offload *qopt) 2581 { 2582 struct e1000_hw *hw = &adapter->hw; 2583 int err; 2584 2585 /* CBS offloading is only supported by i210 controller. */ 2586 if (hw->mac.type != e1000_i210) 2587 return -EOPNOTSUPP; 2588 2589 /* CBS offloading is only supported by queue 0 and queue 1. */ 2590 if (qopt->queue < 0 || qopt->queue > 1) 2591 return -EINVAL; 2592 2593 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2594 qopt->idleslope, qopt->sendslope, 2595 qopt->hicredit, qopt->locredit); 2596 if (err) 2597 return err; 2598 2599 igb_offload_apply(adapter, qopt->queue); 2600 2601 return 0; 2602 } 2603 2604 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2605 #define VLAN_PRIO_FULL_MASK (0x07) 2606 2607 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2608 struct flow_cls_offload *f, 2609 int traffic_class, 2610 struct igb_nfc_filter *input) 2611 { 2612 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2613 struct flow_dissector *dissector = rule->match.dissector; 2614 struct netlink_ext_ack *extack = f->common.extack; 2615 2616 if (dissector->used_keys & 2617 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2618 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2619 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2620 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2621 NL_SET_ERR_MSG_MOD(extack, 2622 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2623 return -EOPNOTSUPP; 2624 } 2625 2626 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2627 struct flow_match_eth_addrs match; 2628 2629 flow_rule_match_eth_addrs(rule, &match); 2630 if (!is_zero_ether_addr(match.mask->dst)) { 2631 if (!is_broadcast_ether_addr(match.mask->dst)) { 2632 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2633 return -EINVAL; 2634 } 2635 2636 input->filter.match_flags |= 2637 IGB_FILTER_FLAG_DST_MAC_ADDR; 2638 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2639 } 2640 2641 if (!is_zero_ether_addr(match.mask->src)) { 2642 if (!is_broadcast_ether_addr(match.mask->src)) { 2643 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2644 return -EINVAL; 2645 } 2646 2647 input->filter.match_flags |= 2648 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2649 ether_addr_copy(input->filter.src_addr, match.key->src); 2650 } 2651 } 2652 2653 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2654 struct flow_match_basic match; 2655 2656 flow_rule_match_basic(rule, &match); 2657 if (match.mask->n_proto) { 2658 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2659 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2660 return -EINVAL; 2661 } 2662 2663 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2664 input->filter.etype = match.key->n_proto; 2665 } 2666 } 2667 2668 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2669 struct flow_match_vlan match; 2670 2671 flow_rule_match_vlan(rule, &match); 2672 if (match.mask->vlan_priority) { 2673 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2674 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2675 return -EINVAL; 2676 } 2677 2678 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2679 input->filter.vlan_tci = 2680 (__force __be16)match.key->vlan_priority; 2681 } 2682 } 2683 2684 input->action = traffic_class; 2685 input->cookie = f->cookie; 2686 2687 return 0; 2688 } 2689 2690 static int igb_configure_clsflower(struct igb_adapter *adapter, 2691 struct flow_cls_offload *cls_flower) 2692 { 2693 struct netlink_ext_ack *extack = cls_flower->common.extack; 2694 struct igb_nfc_filter *filter, *f; 2695 int err, tc; 2696 2697 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2698 if (tc < 0) { 2699 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2700 return -EINVAL; 2701 } 2702 2703 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2704 if (!filter) 2705 return -ENOMEM; 2706 2707 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2708 if (err < 0) 2709 goto err_parse; 2710 2711 spin_lock(&adapter->nfc_lock); 2712 2713 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2714 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2715 err = -EEXIST; 2716 NL_SET_ERR_MSG_MOD(extack, 2717 "This filter is already set in ethtool"); 2718 goto err_locked; 2719 } 2720 } 2721 2722 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2723 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2724 err = -EEXIST; 2725 NL_SET_ERR_MSG_MOD(extack, 2726 "This filter is already set in cls_flower"); 2727 goto err_locked; 2728 } 2729 } 2730 2731 err = igb_add_filter(adapter, filter); 2732 if (err < 0) { 2733 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2734 goto err_locked; 2735 } 2736 2737 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2738 2739 spin_unlock(&adapter->nfc_lock); 2740 2741 return 0; 2742 2743 err_locked: 2744 spin_unlock(&adapter->nfc_lock); 2745 2746 err_parse: 2747 kfree(filter); 2748 2749 return err; 2750 } 2751 2752 static int igb_delete_clsflower(struct igb_adapter *adapter, 2753 struct flow_cls_offload *cls_flower) 2754 { 2755 struct igb_nfc_filter *filter; 2756 int err; 2757 2758 spin_lock(&adapter->nfc_lock); 2759 2760 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2761 if (filter->cookie == cls_flower->cookie) 2762 break; 2763 2764 if (!filter) { 2765 err = -ENOENT; 2766 goto out; 2767 } 2768 2769 err = igb_erase_filter(adapter, filter); 2770 if (err < 0) 2771 goto out; 2772 2773 hlist_del(&filter->nfc_node); 2774 kfree(filter); 2775 2776 out: 2777 spin_unlock(&adapter->nfc_lock); 2778 2779 return err; 2780 } 2781 2782 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2783 struct flow_cls_offload *cls_flower) 2784 { 2785 switch (cls_flower->command) { 2786 case FLOW_CLS_REPLACE: 2787 return igb_configure_clsflower(adapter, cls_flower); 2788 case FLOW_CLS_DESTROY: 2789 return igb_delete_clsflower(adapter, cls_flower); 2790 case FLOW_CLS_STATS: 2791 return -EOPNOTSUPP; 2792 default: 2793 return -EOPNOTSUPP; 2794 } 2795 } 2796 2797 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2798 void *cb_priv) 2799 { 2800 struct igb_adapter *adapter = cb_priv; 2801 2802 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2803 return -EOPNOTSUPP; 2804 2805 switch (type) { 2806 case TC_SETUP_CLSFLOWER: 2807 return igb_setup_tc_cls_flower(adapter, type_data); 2808 2809 default: 2810 return -EOPNOTSUPP; 2811 } 2812 } 2813 2814 static int igb_offload_txtime(struct igb_adapter *adapter, 2815 struct tc_etf_qopt_offload *qopt) 2816 { 2817 struct e1000_hw *hw = &adapter->hw; 2818 int err; 2819 2820 /* Launchtime offloading is only supported by i210 controller. */ 2821 if (hw->mac.type != e1000_i210) 2822 return -EOPNOTSUPP; 2823 2824 /* Launchtime offloading is only supported by queues 0 and 1. */ 2825 if (qopt->queue < 0 || qopt->queue > 1) 2826 return -EINVAL; 2827 2828 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2829 if (err) 2830 return err; 2831 2832 igb_offload_apply(adapter, qopt->queue); 2833 2834 return 0; 2835 } 2836 2837 static int igb_tc_query_caps(struct igb_adapter *adapter, 2838 struct tc_query_caps_base *base) 2839 { 2840 switch (base->type) { 2841 case TC_SETUP_QDISC_TAPRIO: { 2842 struct tc_taprio_caps *caps = base->caps; 2843 2844 caps->broken_mqprio = true; 2845 2846 return 0; 2847 } 2848 default: 2849 return -EOPNOTSUPP; 2850 } 2851 } 2852 2853 static LIST_HEAD(igb_block_cb_list); 2854 2855 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2856 void *type_data) 2857 { 2858 struct igb_adapter *adapter = netdev_priv(dev); 2859 2860 switch (type) { 2861 case TC_QUERY_CAPS: 2862 return igb_tc_query_caps(adapter, type_data); 2863 case TC_SETUP_QDISC_CBS: 2864 return igb_offload_cbs(adapter, type_data); 2865 case TC_SETUP_BLOCK: 2866 return flow_block_cb_setup_simple(type_data, 2867 &igb_block_cb_list, 2868 igb_setup_tc_block_cb, 2869 adapter, adapter, true); 2870 2871 case TC_SETUP_QDISC_ETF: 2872 return igb_offload_txtime(adapter, type_data); 2873 2874 default: 2875 return -EOPNOTSUPP; 2876 } 2877 } 2878 2879 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2880 { 2881 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2882 struct igb_adapter *adapter = netdev_priv(dev); 2883 struct bpf_prog *prog = bpf->prog, *old_prog; 2884 bool running = netif_running(dev); 2885 bool need_reset; 2886 2887 /* verify igb ring attributes are sufficient for XDP */ 2888 for (i = 0; i < adapter->num_rx_queues; i++) { 2889 struct igb_ring *ring = adapter->rx_ring[i]; 2890 2891 if (frame_size > igb_rx_bufsz(ring)) { 2892 NL_SET_ERR_MSG_MOD(bpf->extack, 2893 "The RX buffer size is too small for the frame size"); 2894 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2895 igb_rx_bufsz(ring), frame_size); 2896 return -EINVAL; 2897 } 2898 } 2899 2900 old_prog = xchg(&adapter->xdp_prog, prog); 2901 need_reset = (!!prog != !!old_prog); 2902 2903 /* device is up and bpf is added/removed, must setup the RX queues */ 2904 if (need_reset && running) { 2905 igb_close(dev); 2906 } else { 2907 for (i = 0; i < adapter->num_rx_queues; i++) 2908 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2909 adapter->xdp_prog); 2910 } 2911 2912 if (old_prog) 2913 bpf_prog_put(old_prog); 2914 2915 /* bpf is just replaced, RXQ and MTU are already setup */ 2916 if (!need_reset) { 2917 return 0; 2918 } else { 2919 if (prog) 2920 xdp_features_set_redirect_target(dev, true); 2921 else 2922 xdp_features_clear_redirect_target(dev); 2923 } 2924 2925 if (running) 2926 igb_open(dev); 2927 2928 return 0; 2929 } 2930 2931 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2932 { 2933 switch (xdp->command) { 2934 case XDP_SETUP_PROG: 2935 return igb_xdp_setup(dev, xdp); 2936 default: 2937 return -EINVAL; 2938 } 2939 } 2940 2941 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2942 { 2943 /* Force memory writes to complete before letting h/w know there 2944 * are new descriptors to fetch. 2945 */ 2946 wmb(); 2947 writel(ring->next_to_use, ring->tail); 2948 } 2949 2950 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2951 { 2952 unsigned int r_idx = smp_processor_id(); 2953 2954 if (r_idx >= adapter->num_tx_queues) 2955 r_idx = r_idx % adapter->num_tx_queues; 2956 2957 return adapter->tx_ring[r_idx]; 2958 } 2959 2960 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2961 { 2962 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2963 int cpu = smp_processor_id(); 2964 struct igb_ring *tx_ring; 2965 struct netdev_queue *nq; 2966 u32 ret; 2967 2968 if (unlikely(!xdpf)) 2969 return IGB_XDP_CONSUMED; 2970 2971 /* During program transitions its possible adapter->xdp_prog is assigned 2972 * but ring has not been configured yet. In this case simply abort xmit. 2973 */ 2974 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2975 if (unlikely(!tx_ring)) 2976 return IGB_XDP_CONSUMED; 2977 2978 nq = txring_txq(tx_ring); 2979 __netif_tx_lock(nq, cpu); 2980 /* Avoid transmit queue timeout since we share it with the slow path */ 2981 txq_trans_cond_update(nq); 2982 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2983 __netif_tx_unlock(nq); 2984 2985 return ret; 2986 } 2987 2988 static int igb_xdp_xmit(struct net_device *dev, int n, 2989 struct xdp_frame **frames, u32 flags) 2990 { 2991 struct igb_adapter *adapter = netdev_priv(dev); 2992 int cpu = smp_processor_id(); 2993 struct igb_ring *tx_ring; 2994 struct netdev_queue *nq; 2995 int nxmit = 0; 2996 int i; 2997 2998 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2999 return -ENETDOWN; 3000 3001 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3002 return -EINVAL; 3003 3004 /* During program transitions its possible adapter->xdp_prog is assigned 3005 * but ring has not been configured yet. In this case simply abort xmit. 3006 */ 3007 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 3008 if (unlikely(!tx_ring)) 3009 return -ENXIO; 3010 3011 nq = txring_txq(tx_ring); 3012 __netif_tx_lock(nq, cpu); 3013 3014 /* Avoid transmit queue timeout since we share it with the slow path */ 3015 txq_trans_cond_update(nq); 3016 3017 for (i = 0; i < n; i++) { 3018 struct xdp_frame *xdpf = frames[i]; 3019 int err; 3020 3021 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3022 if (err != IGB_XDP_TX) 3023 break; 3024 nxmit++; 3025 } 3026 3027 __netif_tx_unlock(nq); 3028 3029 if (unlikely(flags & XDP_XMIT_FLUSH)) 3030 igb_xdp_ring_update_tail(tx_ring); 3031 3032 return nxmit; 3033 } 3034 3035 static const struct net_device_ops igb_netdev_ops = { 3036 .ndo_open = igb_open, 3037 .ndo_stop = igb_close, 3038 .ndo_start_xmit = igb_xmit_frame, 3039 .ndo_get_stats64 = igb_get_stats64, 3040 .ndo_set_rx_mode = igb_set_rx_mode, 3041 .ndo_set_mac_address = igb_set_mac, 3042 .ndo_change_mtu = igb_change_mtu, 3043 .ndo_eth_ioctl = igb_ioctl, 3044 .ndo_tx_timeout = igb_tx_timeout, 3045 .ndo_validate_addr = eth_validate_addr, 3046 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3047 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3048 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3049 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3050 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3051 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3052 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3053 .ndo_get_vf_config = igb_ndo_get_vf_config, 3054 .ndo_fix_features = igb_fix_features, 3055 .ndo_set_features = igb_set_features, 3056 .ndo_fdb_add = igb_ndo_fdb_add, 3057 .ndo_features_check = igb_features_check, 3058 .ndo_setup_tc = igb_setup_tc, 3059 .ndo_bpf = igb_xdp, 3060 .ndo_xdp_xmit = igb_xdp_xmit, 3061 }; 3062 3063 /** 3064 * igb_set_fw_version - Configure version string for ethtool 3065 * @adapter: adapter struct 3066 **/ 3067 void igb_set_fw_version(struct igb_adapter *adapter) 3068 { 3069 struct e1000_hw *hw = &adapter->hw; 3070 struct e1000_fw_version fw; 3071 3072 igb_get_fw_version(hw, &fw); 3073 3074 switch (hw->mac.type) { 3075 case e1000_i210: 3076 case e1000_i211: 3077 if (!(igb_get_flash_presence_i210(hw))) { 3078 snprintf(adapter->fw_version, 3079 sizeof(adapter->fw_version), 3080 "%2d.%2d-%d", 3081 fw.invm_major, fw.invm_minor, 3082 fw.invm_img_type); 3083 break; 3084 } 3085 fallthrough; 3086 default: 3087 /* if option is rom valid, display its version too */ 3088 if (fw.or_valid) { 3089 snprintf(adapter->fw_version, 3090 sizeof(adapter->fw_version), 3091 "%d.%d, 0x%08x, %d.%d.%d", 3092 fw.eep_major, fw.eep_minor, fw.etrack_id, 3093 fw.or_major, fw.or_build, fw.or_patch); 3094 /* no option rom */ 3095 } else if (fw.etrack_id != 0X0000) { 3096 snprintf(adapter->fw_version, 3097 sizeof(adapter->fw_version), 3098 "%d.%d, 0x%08x", 3099 fw.eep_major, fw.eep_minor, fw.etrack_id); 3100 } else { 3101 snprintf(adapter->fw_version, 3102 sizeof(adapter->fw_version), 3103 "%d.%d.%d", 3104 fw.eep_major, fw.eep_minor, fw.eep_build); 3105 } 3106 break; 3107 } 3108 } 3109 3110 /** 3111 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3112 * 3113 * @adapter: adapter struct 3114 **/ 3115 static void igb_init_mas(struct igb_adapter *adapter) 3116 { 3117 struct e1000_hw *hw = &adapter->hw; 3118 u16 eeprom_data; 3119 3120 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3121 switch (hw->bus.func) { 3122 case E1000_FUNC_0: 3123 if (eeprom_data & IGB_MAS_ENABLE_0) { 3124 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3125 netdev_info(adapter->netdev, 3126 "MAS: Enabling Media Autosense for port %d\n", 3127 hw->bus.func); 3128 } 3129 break; 3130 case E1000_FUNC_1: 3131 if (eeprom_data & IGB_MAS_ENABLE_1) { 3132 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3133 netdev_info(adapter->netdev, 3134 "MAS: Enabling Media Autosense for port %d\n", 3135 hw->bus.func); 3136 } 3137 break; 3138 case E1000_FUNC_2: 3139 if (eeprom_data & IGB_MAS_ENABLE_2) { 3140 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3141 netdev_info(adapter->netdev, 3142 "MAS: Enabling Media Autosense for port %d\n", 3143 hw->bus.func); 3144 } 3145 break; 3146 case E1000_FUNC_3: 3147 if (eeprom_data & IGB_MAS_ENABLE_3) { 3148 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3149 netdev_info(adapter->netdev, 3150 "MAS: Enabling Media Autosense for port %d\n", 3151 hw->bus.func); 3152 } 3153 break; 3154 default: 3155 /* Shouldn't get here */ 3156 netdev_err(adapter->netdev, 3157 "MAS: Invalid port configuration, returning\n"); 3158 break; 3159 } 3160 } 3161 3162 /** 3163 * igb_init_i2c - Init I2C interface 3164 * @adapter: pointer to adapter structure 3165 **/ 3166 static s32 igb_init_i2c(struct igb_adapter *adapter) 3167 { 3168 s32 status = 0; 3169 3170 /* I2C interface supported on i350 devices */ 3171 if (adapter->hw.mac.type != e1000_i350) 3172 return 0; 3173 3174 /* Initialize the i2c bus which is controlled by the registers. 3175 * This bus will use the i2c_algo_bit structure that implements 3176 * the protocol through toggling of the 4 bits in the register. 3177 */ 3178 adapter->i2c_adap.owner = THIS_MODULE; 3179 adapter->i2c_algo = igb_i2c_algo; 3180 adapter->i2c_algo.data = adapter; 3181 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3182 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3183 strscpy(adapter->i2c_adap.name, "igb BB", 3184 sizeof(adapter->i2c_adap.name)); 3185 status = i2c_bit_add_bus(&adapter->i2c_adap); 3186 return status; 3187 } 3188 3189 /** 3190 * igb_probe - Device Initialization Routine 3191 * @pdev: PCI device information struct 3192 * @ent: entry in igb_pci_tbl 3193 * 3194 * Returns 0 on success, negative on failure 3195 * 3196 * igb_probe initializes an adapter identified by a pci_dev structure. 3197 * The OS initialization, configuring of the adapter private structure, 3198 * and a hardware reset occur. 3199 **/ 3200 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3201 { 3202 struct net_device *netdev; 3203 struct igb_adapter *adapter; 3204 struct e1000_hw *hw; 3205 u16 eeprom_data = 0; 3206 s32 ret_val; 3207 static int global_quad_port_a; /* global quad port a indication */ 3208 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3209 u8 part_str[E1000_PBANUM_LENGTH]; 3210 int err; 3211 3212 /* Catch broken hardware that put the wrong VF device ID in 3213 * the PCIe SR-IOV capability. 3214 */ 3215 if (pdev->is_virtfn) { 3216 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3217 pci_name(pdev), pdev->vendor, pdev->device); 3218 return -EINVAL; 3219 } 3220 3221 err = pci_enable_device_mem(pdev); 3222 if (err) 3223 return err; 3224 3225 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3226 if (err) { 3227 dev_err(&pdev->dev, 3228 "No usable DMA configuration, aborting\n"); 3229 goto err_dma; 3230 } 3231 3232 err = pci_request_mem_regions(pdev, igb_driver_name); 3233 if (err) 3234 goto err_pci_reg; 3235 3236 pci_set_master(pdev); 3237 pci_save_state(pdev); 3238 3239 err = -ENOMEM; 3240 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3241 IGB_MAX_TX_QUEUES); 3242 if (!netdev) 3243 goto err_alloc_etherdev; 3244 3245 SET_NETDEV_DEV(netdev, &pdev->dev); 3246 3247 pci_set_drvdata(pdev, netdev); 3248 adapter = netdev_priv(netdev); 3249 adapter->netdev = netdev; 3250 adapter->pdev = pdev; 3251 hw = &adapter->hw; 3252 hw->back = adapter; 3253 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3254 3255 err = -EIO; 3256 adapter->io_addr = pci_iomap(pdev, 0, 0); 3257 if (!adapter->io_addr) 3258 goto err_ioremap; 3259 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3260 hw->hw_addr = adapter->io_addr; 3261 3262 netdev->netdev_ops = &igb_netdev_ops; 3263 igb_set_ethtool_ops(netdev); 3264 netdev->watchdog_timeo = 5 * HZ; 3265 3266 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3267 3268 netdev->mem_start = pci_resource_start(pdev, 0); 3269 netdev->mem_end = pci_resource_end(pdev, 0); 3270 3271 /* PCI config space info */ 3272 hw->vendor_id = pdev->vendor; 3273 hw->device_id = pdev->device; 3274 hw->revision_id = pdev->revision; 3275 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3276 hw->subsystem_device_id = pdev->subsystem_device; 3277 3278 /* Copy the default MAC, PHY and NVM function pointers */ 3279 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3280 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3281 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3282 /* Initialize skew-specific constants */ 3283 err = ei->get_invariants(hw); 3284 if (err) 3285 goto err_sw_init; 3286 3287 /* setup the private structure */ 3288 err = igb_sw_init(adapter); 3289 if (err) 3290 goto err_sw_init; 3291 3292 igb_get_bus_info_pcie(hw); 3293 3294 hw->phy.autoneg_wait_to_complete = false; 3295 3296 /* Copper options */ 3297 if (hw->phy.media_type == e1000_media_type_copper) { 3298 hw->phy.mdix = AUTO_ALL_MODES; 3299 hw->phy.disable_polarity_correction = false; 3300 hw->phy.ms_type = e1000_ms_hw_default; 3301 } 3302 3303 if (igb_check_reset_block(hw)) 3304 dev_info(&pdev->dev, 3305 "PHY reset is blocked due to SOL/IDER session.\n"); 3306 3307 /* features is initialized to 0 in allocation, it might have bits 3308 * set by igb_sw_init so we should use an or instead of an 3309 * assignment. 3310 */ 3311 netdev->features |= NETIF_F_SG | 3312 NETIF_F_TSO | 3313 NETIF_F_TSO6 | 3314 NETIF_F_RXHASH | 3315 NETIF_F_RXCSUM | 3316 NETIF_F_HW_CSUM; 3317 3318 if (hw->mac.type >= e1000_82576) 3319 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3320 3321 if (hw->mac.type >= e1000_i350) 3322 netdev->features |= NETIF_F_HW_TC; 3323 3324 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3325 NETIF_F_GSO_GRE_CSUM | \ 3326 NETIF_F_GSO_IPXIP4 | \ 3327 NETIF_F_GSO_IPXIP6 | \ 3328 NETIF_F_GSO_UDP_TUNNEL | \ 3329 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3330 3331 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3332 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3333 3334 /* copy netdev features into list of user selectable features */ 3335 netdev->hw_features |= netdev->features | 3336 NETIF_F_HW_VLAN_CTAG_RX | 3337 NETIF_F_HW_VLAN_CTAG_TX | 3338 NETIF_F_RXALL; 3339 3340 if (hw->mac.type >= e1000_i350) 3341 netdev->hw_features |= NETIF_F_NTUPLE; 3342 3343 netdev->features |= NETIF_F_HIGHDMA; 3344 3345 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3346 netdev->mpls_features |= NETIF_F_HW_CSUM; 3347 netdev->hw_enc_features |= netdev->vlan_features; 3348 3349 /* set this bit last since it cannot be part of vlan_features */ 3350 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3351 NETIF_F_HW_VLAN_CTAG_RX | 3352 NETIF_F_HW_VLAN_CTAG_TX; 3353 3354 netdev->priv_flags |= IFF_SUPP_NOFCS; 3355 3356 netdev->priv_flags |= IFF_UNICAST_FLT; 3357 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3358 3359 /* MTU range: 68 - 9216 */ 3360 netdev->min_mtu = ETH_MIN_MTU; 3361 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3362 3363 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3364 3365 /* before reading the NVM, reset the controller to put the device in a 3366 * known good starting state 3367 */ 3368 hw->mac.ops.reset_hw(hw); 3369 3370 /* make sure the NVM is good , i211/i210 parts can have special NVM 3371 * that doesn't contain a checksum 3372 */ 3373 switch (hw->mac.type) { 3374 case e1000_i210: 3375 case e1000_i211: 3376 if (igb_get_flash_presence_i210(hw)) { 3377 if (hw->nvm.ops.validate(hw) < 0) { 3378 dev_err(&pdev->dev, 3379 "The NVM Checksum Is Not Valid\n"); 3380 err = -EIO; 3381 goto err_eeprom; 3382 } 3383 } 3384 break; 3385 default: 3386 if (hw->nvm.ops.validate(hw) < 0) { 3387 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3388 err = -EIO; 3389 goto err_eeprom; 3390 } 3391 break; 3392 } 3393 3394 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3395 /* copy the MAC address out of the NVM */ 3396 if (hw->mac.ops.read_mac_addr(hw)) 3397 dev_err(&pdev->dev, "NVM Read Error\n"); 3398 } 3399 3400 eth_hw_addr_set(netdev, hw->mac.addr); 3401 3402 if (!is_valid_ether_addr(netdev->dev_addr)) { 3403 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3404 err = -EIO; 3405 goto err_eeprom; 3406 } 3407 3408 igb_set_default_mac_filter(adapter); 3409 3410 /* get firmware version for ethtool -i */ 3411 igb_set_fw_version(adapter); 3412 3413 /* configure RXPBSIZE and TXPBSIZE */ 3414 if (hw->mac.type == e1000_i210) { 3415 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3416 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3417 } 3418 3419 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3420 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3421 3422 INIT_WORK(&adapter->reset_task, igb_reset_task); 3423 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3424 3425 /* Initialize link properties that are user-changeable */ 3426 adapter->fc_autoneg = true; 3427 hw->mac.autoneg = true; 3428 hw->phy.autoneg_advertised = 0x2f; 3429 3430 hw->fc.requested_mode = e1000_fc_default; 3431 hw->fc.current_mode = e1000_fc_default; 3432 3433 igb_validate_mdi_setting(hw); 3434 3435 /* By default, support wake on port A */ 3436 if (hw->bus.func == 0) 3437 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3438 3439 /* Check the NVM for wake support on non-port A ports */ 3440 if (hw->mac.type >= e1000_82580) 3441 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3442 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3443 &eeprom_data); 3444 else if (hw->bus.func == 1) 3445 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3446 3447 if (eeprom_data & IGB_EEPROM_APME) 3448 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3449 3450 /* now that we have the eeprom settings, apply the special cases where 3451 * the eeprom may be wrong or the board simply won't support wake on 3452 * lan on a particular port 3453 */ 3454 switch (pdev->device) { 3455 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3456 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3457 break; 3458 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3459 case E1000_DEV_ID_82576_FIBER: 3460 case E1000_DEV_ID_82576_SERDES: 3461 /* Wake events only supported on port A for dual fiber 3462 * regardless of eeprom setting 3463 */ 3464 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3465 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3466 break; 3467 case E1000_DEV_ID_82576_QUAD_COPPER: 3468 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3469 /* if quad port adapter, disable WoL on all but port A */ 3470 if (global_quad_port_a != 0) 3471 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3472 else 3473 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3474 /* Reset for multiple quad port adapters */ 3475 if (++global_quad_port_a == 4) 3476 global_quad_port_a = 0; 3477 break; 3478 default: 3479 /* If the device can't wake, don't set software support */ 3480 if (!device_can_wakeup(&adapter->pdev->dev)) 3481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3482 } 3483 3484 /* initialize the wol settings based on the eeprom settings */ 3485 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3486 adapter->wol |= E1000_WUFC_MAG; 3487 3488 /* Some vendors want WoL disabled by default, but still supported */ 3489 if ((hw->mac.type == e1000_i350) && 3490 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3491 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3492 adapter->wol = 0; 3493 } 3494 3495 /* Some vendors want the ability to Use the EEPROM setting as 3496 * enable/disable only, and not for capability 3497 */ 3498 if (((hw->mac.type == e1000_i350) || 3499 (hw->mac.type == e1000_i354)) && 3500 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3501 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3502 adapter->wol = 0; 3503 } 3504 if (hw->mac.type == e1000_i350) { 3505 if (((pdev->subsystem_device == 0x5001) || 3506 (pdev->subsystem_device == 0x5002)) && 3507 (hw->bus.func == 0)) { 3508 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3509 adapter->wol = 0; 3510 } 3511 if (pdev->subsystem_device == 0x1F52) 3512 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3513 } 3514 3515 device_set_wakeup_enable(&adapter->pdev->dev, 3516 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3517 3518 /* reset the hardware with the new settings */ 3519 igb_reset(adapter); 3520 3521 /* Init the I2C interface */ 3522 err = igb_init_i2c(adapter); 3523 if (err) { 3524 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3525 goto err_eeprom; 3526 } 3527 3528 /* let the f/w know that the h/w is now under the control of the 3529 * driver. 3530 */ 3531 igb_get_hw_control(adapter); 3532 3533 strcpy(netdev->name, "eth%d"); 3534 err = register_netdev(netdev); 3535 if (err) 3536 goto err_register; 3537 3538 /* carrier off reporting is important to ethtool even BEFORE open */ 3539 netif_carrier_off(netdev); 3540 3541 #ifdef CONFIG_IGB_DCA 3542 if (dca_add_requester(&pdev->dev) == 0) { 3543 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3544 dev_info(&pdev->dev, "DCA enabled\n"); 3545 igb_setup_dca(adapter); 3546 } 3547 3548 #endif 3549 #ifdef CONFIG_IGB_HWMON 3550 /* Initialize the thermal sensor on i350 devices. */ 3551 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3552 u16 ets_word; 3553 3554 /* Read the NVM to determine if this i350 device supports an 3555 * external thermal sensor. 3556 */ 3557 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3558 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3559 adapter->ets = true; 3560 else 3561 adapter->ets = false; 3562 /* Only enable I2C bit banging if an external thermal 3563 * sensor is supported. 3564 */ 3565 if (adapter->ets) 3566 igb_set_i2c_bb(hw); 3567 hw->mac.ops.init_thermal_sensor_thresh(hw); 3568 if (igb_sysfs_init(adapter)) 3569 dev_err(&pdev->dev, 3570 "failed to allocate sysfs resources\n"); 3571 } else { 3572 adapter->ets = false; 3573 } 3574 #endif 3575 /* Check if Media Autosense is enabled */ 3576 adapter->ei = *ei; 3577 if (hw->dev_spec._82575.mas_capable) 3578 igb_init_mas(adapter); 3579 3580 /* do hw tstamp init after resetting */ 3581 igb_ptp_init(adapter); 3582 3583 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3584 /* print bus type/speed/width info, not applicable to i354 */ 3585 if (hw->mac.type != e1000_i354) { 3586 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3587 netdev->name, 3588 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3589 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3590 "unknown"), 3591 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3592 "Width x4" : 3593 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3594 "Width x2" : 3595 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3596 "Width x1" : "unknown"), netdev->dev_addr); 3597 } 3598 3599 if ((hw->mac.type == e1000_82576 && 3600 rd32(E1000_EECD) & E1000_EECD_PRES) || 3601 (hw->mac.type >= e1000_i210 || 3602 igb_get_flash_presence_i210(hw))) { 3603 ret_val = igb_read_part_string(hw, part_str, 3604 E1000_PBANUM_LENGTH); 3605 } else { 3606 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3607 } 3608 3609 if (ret_val) 3610 strcpy(part_str, "Unknown"); 3611 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3612 dev_info(&pdev->dev, 3613 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3614 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3615 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3616 adapter->num_rx_queues, adapter->num_tx_queues); 3617 if (hw->phy.media_type == e1000_media_type_copper) { 3618 switch (hw->mac.type) { 3619 case e1000_i350: 3620 case e1000_i210: 3621 case e1000_i211: 3622 /* Enable EEE for internal copper PHY devices */ 3623 err = igb_set_eee_i350(hw, true, true); 3624 if ((!err) && 3625 (!hw->dev_spec._82575.eee_disable)) { 3626 adapter->eee_advert = 3627 MDIO_EEE_100TX | MDIO_EEE_1000T; 3628 adapter->flags |= IGB_FLAG_EEE; 3629 } 3630 break; 3631 case e1000_i354: 3632 if ((rd32(E1000_CTRL_EXT) & 3633 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3634 err = igb_set_eee_i354(hw, true, true); 3635 if ((!err) && 3636 (!hw->dev_spec._82575.eee_disable)) { 3637 adapter->eee_advert = 3638 MDIO_EEE_100TX | MDIO_EEE_1000T; 3639 adapter->flags |= IGB_FLAG_EEE; 3640 } 3641 } 3642 break; 3643 default: 3644 break; 3645 } 3646 } 3647 3648 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3649 3650 pm_runtime_put_noidle(&pdev->dev); 3651 return 0; 3652 3653 err_register: 3654 igb_release_hw_control(adapter); 3655 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3656 err_eeprom: 3657 if (!igb_check_reset_block(hw)) 3658 igb_reset_phy(hw); 3659 3660 if (hw->flash_address) 3661 iounmap(hw->flash_address); 3662 err_sw_init: 3663 kfree(adapter->mac_table); 3664 kfree(adapter->shadow_vfta); 3665 igb_clear_interrupt_scheme(adapter); 3666 #ifdef CONFIG_PCI_IOV 3667 igb_disable_sriov(pdev, false); 3668 #endif 3669 pci_iounmap(pdev, adapter->io_addr); 3670 err_ioremap: 3671 free_netdev(netdev); 3672 err_alloc_etherdev: 3673 pci_release_mem_regions(pdev); 3674 err_pci_reg: 3675 err_dma: 3676 pci_disable_device(pdev); 3677 return err; 3678 } 3679 3680 #ifdef CONFIG_PCI_IOV 3681 static int igb_sriov_reinit(struct pci_dev *dev) 3682 { 3683 struct net_device *netdev = pci_get_drvdata(dev); 3684 struct igb_adapter *adapter = netdev_priv(netdev); 3685 struct pci_dev *pdev = adapter->pdev; 3686 3687 rtnl_lock(); 3688 3689 if (netif_running(netdev)) 3690 igb_close(netdev); 3691 else 3692 igb_reset(adapter); 3693 3694 igb_clear_interrupt_scheme(adapter); 3695 3696 igb_init_queue_configuration(adapter); 3697 3698 if (igb_init_interrupt_scheme(adapter, true)) { 3699 rtnl_unlock(); 3700 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3701 return -ENOMEM; 3702 } 3703 3704 if (netif_running(netdev)) 3705 igb_open(netdev); 3706 3707 rtnl_unlock(); 3708 3709 return 0; 3710 } 3711 3712 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3713 { 3714 struct net_device *netdev = pci_get_drvdata(pdev); 3715 struct igb_adapter *adapter = netdev_priv(netdev); 3716 struct e1000_hw *hw = &adapter->hw; 3717 unsigned long flags; 3718 3719 /* reclaim resources allocated to VFs */ 3720 if (adapter->vf_data) { 3721 /* disable iov and allow time for transactions to clear */ 3722 if (pci_vfs_assigned(pdev)) { 3723 dev_warn(&pdev->dev, 3724 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3725 return -EPERM; 3726 } else { 3727 pci_disable_sriov(pdev); 3728 msleep(500); 3729 } 3730 spin_lock_irqsave(&adapter->vfs_lock, flags); 3731 kfree(adapter->vf_mac_list); 3732 adapter->vf_mac_list = NULL; 3733 kfree(adapter->vf_data); 3734 adapter->vf_data = NULL; 3735 adapter->vfs_allocated_count = 0; 3736 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3737 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3738 wrfl(); 3739 msleep(100); 3740 dev_info(&pdev->dev, "IOV Disabled\n"); 3741 3742 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3743 adapter->flags |= IGB_FLAG_DMAC; 3744 } 3745 3746 return reinit ? igb_sriov_reinit(pdev) : 0; 3747 } 3748 3749 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3750 { 3751 struct net_device *netdev = pci_get_drvdata(pdev); 3752 struct igb_adapter *adapter = netdev_priv(netdev); 3753 int old_vfs = pci_num_vf(pdev); 3754 struct vf_mac_filter *mac_list; 3755 int err = 0; 3756 int num_vf_mac_filters, i; 3757 3758 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3759 err = -EPERM; 3760 goto out; 3761 } 3762 if (!num_vfs) 3763 goto out; 3764 3765 if (old_vfs) { 3766 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3767 old_vfs, max_vfs); 3768 adapter->vfs_allocated_count = old_vfs; 3769 } else 3770 adapter->vfs_allocated_count = num_vfs; 3771 3772 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3773 sizeof(struct vf_data_storage), GFP_KERNEL); 3774 3775 /* if allocation failed then we do not support SR-IOV */ 3776 if (!adapter->vf_data) { 3777 adapter->vfs_allocated_count = 0; 3778 err = -ENOMEM; 3779 goto out; 3780 } 3781 3782 /* Due to the limited number of RAR entries calculate potential 3783 * number of MAC filters available for the VFs. Reserve entries 3784 * for PF default MAC, PF MAC filters and at least one RAR entry 3785 * for each VF for VF MAC. 3786 */ 3787 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3788 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3789 adapter->vfs_allocated_count); 3790 3791 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3792 sizeof(struct vf_mac_filter), 3793 GFP_KERNEL); 3794 3795 mac_list = adapter->vf_mac_list; 3796 INIT_LIST_HEAD(&adapter->vf_macs.l); 3797 3798 if (adapter->vf_mac_list) { 3799 /* Initialize list of VF MAC filters */ 3800 for (i = 0; i < num_vf_mac_filters; i++) { 3801 mac_list->vf = -1; 3802 mac_list->free = true; 3803 list_add(&mac_list->l, &adapter->vf_macs.l); 3804 mac_list++; 3805 } 3806 } else { 3807 /* If we could not allocate memory for the VF MAC filters 3808 * we can continue without this feature but warn user. 3809 */ 3810 dev_err(&pdev->dev, 3811 "Unable to allocate memory for VF MAC filter list\n"); 3812 } 3813 3814 dev_info(&pdev->dev, "%d VFs allocated\n", 3815 adapter->vfs_allocated_count); 3816 for (i = 0; i < adapter->vfs_allocated_count; i++) 3817 igb_vf_configure(adapter, i); 3818 3819 /* DMA Coalescing is not supported in IOV mode. */ 3820 adapter->flags &= ~IGB_FLAG_DMAC; 3821 3822 if (reinit) { 3823 err = igb_sriov_reinit(pdev); 3824 if (err) 3825 goto err_out; 3826 } 3827 3828 /* only call pci_enable_sriov() if no VFs are allocated already */ 3829 if (!old_vfs) 3830 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3831 3832 goto out; 3833 3834 err_out: 3835 kfree(adapter->vf_mac_list); 3836 adapter->vf_mac_list = NULL; 3837 kfree(adapter->vf_data); 3838 adapter->vf_data = NULL; 3839 adapter->vfs_allocated_count = 0; 3840 out: 3841 return err; 3842 } 3843 3844 #endif 3845 /** 3846 * igb_remove_i2c - Cleanup I2C interface 3847 * @adapter: pointer to adapter structure 3848 **/ 3849 static void igb_remove_i2c(struct igb_adapter *adapter) 3850 { 3851 /* free the adapter bus structure */ 3852 i2c_del_adapter(&adapter->i2c_adap); 3853 } 3854 3855 /** 3856 * igb_remove - Device Removal Routine 3857 * @pdev: PCI device information struct 3858 * 3859 * igb_remove is called by the PCI subsystem to alert the driver 3860 * that it should release a PCI device. The could be caused by a 3861 * Hot-Plug event, or because the driver is going to be removed from 3862 * memory. 3863 **/ 3864 static void igb_remove(struct pci_dev *pdev) 3865 { 3866 struct net_device *netdev = pci_get_drvdata(pdev); 3867 struct igb_adapter *adapter = netdev_priv(netdev); 3868 struct e1000_hw *hw = &adapter->hw; 3869 3870 pm_runtime_get_noresume(&pdev->dev); 3871 #ifdef CONFIG_IGB_HWMON 3872 igb_sysfs_exit(adapter); 3873 #endif 3874 igb_remove_i2c(adapter); 3875 igb_ptp_stop(adapter); 3876 /* The watchdog timer may be rescheduled, so explicitly 3877 * disable watchdog from being rescheduled. 3878 */ 3879 set_bit(__IGB_DOWN, &adapter->state); 3880 del_timer_sync(&adapter->watchdog_timer); 3881 del_timer_sync(&adapter->phy_info_timer); 3882 3883 cancel_work_sync(&adapter->reset_task); 3884 cancel_work_sync(&adapter->watchdog_task); 3885 3886 #ifdef CONFIG_IGB_DCA 3887 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3888 dev_info(&pdev->dev, "DCA disabled\n"); 3889 dca_remove_requester(&pdev->dev); 3890 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3891 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3892 } 3893 #endif 3894 3895 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3896 * would have already happened in close and is redundant. 3897 */ 3898 igb_release_hw_control(adapter); 3899 3900 #ifdef CONFIG_PCI_IOV 3901 igb_disable_sriov(pdev, false); 3902 #endif 3903 3904 unregister_netdev(netdev); 3905 3906 igb_clear_interrupt_scheme(adapter); 3907 3908 pci_iounmap(pdev, adapter->io_addr); 3909 if (hw->flash_address) 3910 iounmap(hw->flash_address); 3911 pci_release_mem_regions(pdev); 3912 3913 kfree(adapter->mac_table); 3914 kfree(adapter->shadow_vfta); 3915 free_netdev(netdev); 3916 3917 pci_disable_device(pdev); 3918 } 3919 3920 /** 3921 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3922 * @adapter: board private structure to initialize 3923 * 3924 * This function initializes the vf specific data storage and then attempts to 3925 * allocate the VFs. The reason for ordering it this way is because it is much 3926 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3927 * the memory for the VFs. 3928 **/ 3929 static void igb_probe_vfs(struct igb_adapter *adapter) 3930 { 3931 #ifdef CONFIG_PCI_IOV 3932 struct pci_dev *pdev = adapter->pdev; 3933 struct e1000_hw *hw = &adapter->hw; 3934 3935 /* Virtualization features not supported on i210 family. */ 3936 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3937 return; 3938 3939 /* Of the below we really only want the effect of getting 3940 * IGB_FLAG_HAS_MSIX set (if available), without which 3941 * igb_enable_sriov() has no effect. 3942 */ 3943 igb_set_interrupt_capability(adapter, true); 3944 igb_reset_interrupt_capability(adapter); 3945 3946 pci_sriov_set_totalvfs(pdev, 7); 3947 igb_enable_sriov(pdev, max_vfs, false); 3948 3949 #endif /* CONFIG_PCI_IOV */ 3950 } 3951 3952 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3953 { 3954 struct e1000_hw *hw = &adapter->hw; 3955 unsigned int max_rss_queues; 3956 3957 /* Determine the maximum number of RSS queues supported. */ 3958 switch (hw->mac.type) { 3959 case e1000_i211: 3960 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3961 break; 3962 case e1000_82575: 3963 case e1000_i210: 3964 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3965 break; 3966 case e1000_i350: 3967 /* I350 cannot do RSS and SR-IOV at the same time */ 3968 if (!!adapter->vfs_allocated_count) { 3969 max_rss_queues = 1; 3970 break; 3971 } 3972 fallthrough; 3973 case e1000_82576: 3974 if (!!adapter->vfs_allocated_count) { 3975 max_rss_queues = 2; 3976 break; 3977 } 3978 fallthrough; 3979 case e1000_82580: 3980 case e1000_i354: 3981 default: 3982 max_rss_queues = IGB_MAX_RX_QUEUES; 3983 break; 3984 } 3985 3986 return max_rss_queues; 3987 } 3988 3989 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3990 { 3991 u32 max_rss_queues; 3992 3993 max_rss_queues = igb_get_max_rss_queues(adapter); 3994 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3995 3996 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3997 } 3998 3999 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4000 const u32 max_rss_queues) 4001 { 4002 struct e1000_hw *hw = &adapter->hw; 4003 4004 /* Determine if we need to pair queues. */ 4005 switch (hw->mac.type) { 4006 case e1000_82575: 4007 case e1000_i211: 4008 /* Device supports enough interrupts without queue pairing. */ 4009 break; 4010 case e1000_82576: 4011 case e1000_82580: 4012 case e1000_i350: 4013 case e1000_i354: 4014 case e1000_i210: 4015 default: 4016 /* If rss_queues > half of max_rss_queues, pair the queues in 4017 * order to conserve interrupts due to limited supply. 4018 */ 4019 if (adapter->rss_queues > (max_rss_queues / 2)) 4020 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4021 else 4022 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4023 break; 4024 } 4025 } 4026 4027 /** 4028 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4029 * @adapter: board private structure to initialize 4030 * 4031 * igb_sw_init initializes the Adapter private data structure. 4032 * Fields are initialized based on PCI device information and 4033 * OS network device settings (MTU size). 4034 **/ 4035 static int igb_sw_init(struct igb_adapter *adapter) 4036 { 4037 struct e1000_hw *hw = &adapter->hw; 4038 struct net_device *netdev = adapter->netdev; 4039 struct pci_dev *pdev = adapter->pdev; 4040 4041 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4042 4043 /* set default ring sizes */ 4044 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4045 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4046 4047 /* set default ITR values */ 4048 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4049 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4050 4051 /* set default work limits */ 4052 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4053 4054 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4055 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4056 4057 spin_lock_init(&adapter->nfc_lock); 4058 spin_lock_init(&adapter->stats64_lock); 4059 4060 /* init spinlock to avoid concurrency of VF resources */ 4061 spin_lock_init(&adapter->vfs_lock); 4062 #ifdef CONFIG_PCI_IOV 4063 switch (hw->mac.type) { 4064 case e1000_82576: 4065 case e1000_i350: 4066 if (max_vfs > 7) { 4067 dev_warn(&pdev->dev, 4068 "Maximum of 7 VFs per PF, using max\n"); 4069 max_vfs = adapter->vfs_allocated_count = 7; 4070 } else 4071 adapter->vfs_allocated_count = max_vfs; 4072 if (adapter->vfs_allocated_count) 4073 dev_warn(&pdev->dev, 4074 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4075 break; 4076 default: 4077 break; 4078 } 4079 #endif /* CONFIG_PCI_IOV */ 4080 4081 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4082 adapter->flags |= IGB_FLAG_HAS_MSIX; 4083 4084 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 4085 sizeof(struct igb_mac_addr), 4086 GFP_KERNEL); 4087 if (!adapter->mac_table) 4088 return -ENOMEM; 4089 4090 igb_probe_vfs(adapter); 4091 4092 igb_init_queue_configuration(adapter); 4093 4094 /* Setup and initialize a copy of the hw vlan table array */ 4095 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4096 GFP_KERNEL); 4097 if (!adapter->shadow_vfta) 4098 return -ENOMEM; 4099 4100 /* This call may decrease the number of queues */ 4101 if (igb_init_interrupt_scheme(adapter, true)) { 4102 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4103 return -ENOMEM; 4104 } 4105 4106 /* Explicitly disable IRQ since the NIC can be in any state. */ 4107 igb_irq_disable(adapter); 4108 4109 if (hw->mac.type >= e1000_i350) 4110 adapter->flags &= ~IGB_FLAG_DMAC; 4111 4112 set_bit(__IGB_DOWN, &adapter->state); 4113 return 0; 4114 } 4115 4116 /** 4117 * __igb_open - Called when a network interface is made active 4118 * @netdev: network interface device structure 4119 * @resuming: indicates whether we are in a resume call 4120 * 4121 * Returns 0 on success, negative value on failure 4122 * 4123 * The open entry point is called when a network interface is made 4124 * active by the system (IFF_UP). At this point all resources needed 4125 * for transmit and receive operations are allocated, the interrupt 4126 * handler is registered with the OS, the watchdog timer is started, 4127 * and the stack is notified that the interface is ready. 4128 **/ 4129 static int __igb_open(struct net_device *netdev, bool resuming) 4130 { 4131 struct igb_adapter *adapter = netdev_priv(netdev); 4132 struct e1000_hw *hw = &adapter->hw; 4133 struct pci_dev *pdev = adapter->pdev; 4134 int err; 4135 int i; 4136 4137 /* disallow open during test */ 4138 if (test_bit(__IGB_TESTING, &adapter->state)) { 4139 WARN_ON(resuming); 4140 return -EBUSY; 4141 } 4142 4143 if (!resuming) 4144 pm_runtime_get_sync(&pdev->dev); 4145 4146 netif_carrier_off(netdev); 4147 4148 /* allocate transmit descriptors */ 4149 err = igb_setup_all_tx_resources(adapter); 4150 if (err) 4151 goto err_setup_tx; 4152 4153 /* allocate receive descriptors */ 4154 err = igb_setup_all_rx_resources(adapter); 4155 if (err) 4156 goto err_setup_rx; 4157 4158 igb_power_up_link(adapter); 4159 4160 /* before we allocate an interrupt, we must be ready to handle it. 4161 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4162 * as soon as we call pci_request_irq, so we have to setup our 4163 * clean_rx handler before we do so. 4164 */ 4165 igb_configure(adapter); 4166 4167 err = igb_request_irq(adapter); 4168 if (err) 4169 goto err_req_irq; 4170 4171 /* Notify the stack of the actual queue counts. */ 4172 err = netif_set_real_num_tx_queues(adapter->netdev, 4173 adapter->num_tx_queues); 4174 if (err) 4175 goto err_set_queues; 4176 4177 err = netif_set_real_num_rx_queues(adapter->netdev, 4178 adapter->num_rx_queues); 4179 if (err) 4180 goto err_set_queues; 4181 4182 /* From here on the code is the same as igb_up() */ 4183 clear_bit(__IGB_DOWN, &adapter->state); 4184 4185 for (i = 0; i < adapter->num_q_vectors; i++) 4186 napi_enable(&(adapter->q_vector[i]->napi)); 4187 4188 /* Clear any pending interrupts. */ 4189 rd32(E1000_TSICR); 4190 rd32(E1000_ICR); 4191 4192 igb_irq_enable(adapter); 4193 4194 /* notify VFs that reset has been completed */ 4195 if (adapter->vfs_allocated_count) { 4196 u32 reg_data = rd32(E1000_CTRL_EXT); 4197 4198 reg_data |= E1000_CTRL_EXT_PFRSTD; 4199 wr32(E1000_CTRL_EXT, reg_data); 4200 } 4201 4202 netif_tx_start_all_queues(netdev); 4203 4204 if (!resuming) 4205 pm_runtime_put(&pdev->dev); 4206 4207 /* start the watchdog. */ 4208 hw->mac.get_link_status = 1; 4209 schedule_work(&adapter->watchdog_task); 4210 4211 return 0; 4212 4213 err_set_queues: 4214 igb_free_irq(adapter); 4215 err_req_irq: 4216 igb_release_hw_control(adapter); 4217 igb_power_down_link(adapter); 4218 igb_free_all_rx_resources(adapter); 4219 err_setup_rx: 4220 igb_free_all_tx_resources(adapter); 4221 err_setup_tx: 4222 igb_reset(adapter); 4223 if (!resuming) 4224 pm_runtime_put(&pdev->dev); 4225 4226 return err; 4227 } 4228 4229 int igb_open(struct net_device *netdev) 4230 { 4231 return __igb_open(netdev, false); 4232 } 4233 4234 /** 4235 * __igb_close - Disables a network interface 4236 * @netdev: network interface device structure 4237 * @suspending: indicates we are in a suspend call 4238 * 4239 * Returns 0, this is not allowed to fail 4240 * 4241 * The close entry point is called when an interface is de-activated 4242 * by the OS. The hardware is still under the driver's control, but 4243 * needs to be disabled. A global MAC reset is issued to stop the 4244 * hardware, and all transmit and receive resources are freed. 4245 **/ 4246 static int __igb_close(struct net_device *netdev, bool suspending) 4247 { 4248 struct igb_adapter *adapter = netdev_priv(netdev); 4249 struct pci_dev *pdev = adapter->pdev; 4250 4251 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4252 4253 if (!suspending) 4254 pm_runtime_get_sync(&pdev->dev); 4255 4256 igb_down(adapter); 4257 igb_free_irq(adapter); 4258 4259 igb_free_all_tx_resources(adapter); 4260 igb_free_all_rx_resources(adapter); 4261 4262 if (!suspending) 4263 pm_runtime_put_sync(&pdev->dev); 4264 return 0; 4265 } 4266 4267 int igb_close(struct net_device *netdev) 4268 { 4269 if (netif_device_present(netdev) || netdev->dismantle) 4270 return __igb_close(netdev, false); 4271 return 0; 4272 } 4273 4274 /** 4275 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4276 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4277 * 4278 * Return 0 on success, negative on failure 4279 **/ 4280 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4281 { 4282 struct device *dev = tx_ring->dev; 4283 int size; 4284 4285 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4286 4287 tx_ring->tx_buffer_info = vmalloc(size); 4288 if (!tx_ring->tx_buffer_info) 4289 goto err; 4290 4291 /* round up to nearest 4K */ 4292 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4293 tx_ring->size = ALIGN(tx_ring->size, 4096); 4294 4295 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4296 &tx_ring->dma, GFP_KERNEL); 4297 if (!tx_ring->desc) 4298 goto err; 4299 4300 tx_ring->next_to_use = 0; 4301 tx_ring->next_to_clean = 0; 4302 4303 return 0; 4304 4305 err: 4306 vfree(tx_ring->tx_buffer_info); 4307 tx_ring->tx_buffer_info = NULL; 4308 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4309 return -ENOMEM; 4310 } 4311 4312 /** 4313 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4314 * (Descriptors) for all queues 4315 * @adapter: board private structure 4316 * 4317 * Return 0 on success, negative on failure 4318 **/ 4319 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4320 { 4321 struct pci_dev *pdev = adapter->pdev; 4322 int i, err = 0; 4323 4324 for (i = 0; i < adapter->num_tx_queues; i++) { 4325 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4326 if (err) { 4327 dev_err(&pdev->dev, 4328 "Allocation for Tx Queue %u failed\n", i); 4329 for (i--; i >= 0; i--) 4330 igb_free_tx_resources(adapter->tx_ring[i]); 4331 break; 4332 } 4333 } 4334 4335 return err; 4336 } 4337 4338 /** 4339 * igb_setup_tctl - configure the transmit control registers 4340 * @adapter: Board private structure 4341 **/ 4342 void igb_setup_tctl(struct igb_adapter *adapter) 4343 { 4344 struct e1000_hw *hw = &adapter->hw; 4345 u32 tctl; 4346 4347 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4348 wr32(E1000_TXDCTL(0), 0); 4349 4350 /* Program the Transmit Control Register */ 4351 tctl = rd32(E1000_TCTL); 4352 tctl &= ~E1000_TCTL_CT; 4353 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4354 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4355 4356 igb_config_collision_dist(hw); 4357 4358 /* Enable transmits */ 4359 tctl |= E1000_TCTL_EN; 4360 4361 wr32(E1000_TCTL, tctl); 4362 } 4363 4364 /** 4365 * igb_configure_tx_ring - Configure transmit ring after Reset 4366 * @adapter: board private structure 4367 * @ring: tx ring to configure 4368 * 4369 * Configure a transmit ring after a reset. 4370 **/ 4371 void igb_configure_tx_ring(struct igb_adapter *adapter, 4372 struct igb_ring *ring) 4373 { 4374 struct e1000_hw *hw = &adapter->hw; 4375 u32 txdctl = 0; 4376 u64 tdba = ring->dma; 4377 int reg_idx = ring->reg_idx; 4378 4379 wr32(E1000_TDLEN(reg_idx), 4380 ring->count * sizeof(union e1000_adv_tx_desc)); 4381 wr32(E1000_TDBAL(reg_idx), 4382 tdba & 0x00000000ffffffffULL); 4383 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4384 4385 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4386 wr32(E1000_TDH(reg_idx), 0); 4387 writel(0, ring->tail); 4388 4389 txdctl |= IGB_TX_PTHRESH; 4390 txdctl |= IGB_TX_HTHRESH << 8; 4391 txdctl |= IGB_TX_WTHRESH << 16; 4392 4393 /* reinitialize tx_buffer_info */ 4394 memset(ring->tx_buffer_info, 0, 4395 sizeof(struct igb_tx_buffer) * ring->count); 4396 4397 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4398 wr32(E1000_TXDCTL(reg_idx), txdctl); 4399 } 4400 4401 /** 4402 * igb_configure_tx - Configure transmit Unit after Reset 4403 * @adapter: board private structure 4404 * 4405 * Configure the Tx unit of the MAC after a reset. 4406 **/ 4407 static void igb_configure_tx(struct igb_adapter *adapter) 4408 { 4409 struct e1000_hw *hw = &adapter->hw; 4410 int i; 4411 4412 /* disable the queues */ 4413 for (i = 0; i < adapter->num_tx_queues; i++) 4414 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4415 4416 wrfl(); 4417 usleep_range(10000, 20000); 4418 4419 for (i = 0; i < adapter->num_tx_queues; i++) 4420 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4421 } 4422 4423 /** 4424 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4425 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4426 * 4427 * Returns 0 on success, negative on failure 4428 **/ 4429 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4430 { 4431 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4432 struct device *dev = rx_ring->dev; 4433 int size, res; 4434 4435 /* XDP RX-queue info */ 4436 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4437 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4438 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4439 rx_ring->queue_index, 0); 4440 if (res < 0) { 4441 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4442 rx_ring->queue_index); 4443 return res; 4444 } 4445 4446 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4447 4448 rx_ring->rx_buffer_info = vmalloc(size); 4449 if (!rx_ring->rx_buffer_info) 4450 goto err; 4451 4452 /* Round up to nearest 4K */ 4453 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4454 rx_ring->size = ALIGN(rx_ring->size, 4096); 4455 4456 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4457 &rx_ring->dma, GFP_KERNEL); 4458 if (!rx_ring->desc) 4459 goto err; 4460 4461 rx_ring->next_to_alloc = 0; 4462 rx_ring->next_to_clean = 0; 4463 rx_ring->next_to_use = 0; 4464 4465 rx_ring->xdp_prog = adapter->xdp_prog; 4466 4467 return 0; 4468 4469 err: 4470 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4471 vfree(rx_ring->rx_buffer_info); 4472 rx_ring->rx_buffer_info = NULL; 4473 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4474 return -ENOMEM; 4475 } 4476 4477 /** 4478 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4479 * (Descriptors) for all queues 4480 * @adapter: board private structure 4481 * 4482 * Return 0 on success, negative on failure 4483 **/ 4484 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4485 { 4486 struct pci_dev *pdev = adapter->pdev; 4487 int i, err = 0; 4488 4489 for (i = 0; i < adapter->num_rx_queues; i++) { 4490 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4491 if (err) { 4492 dev_err(&pdev->dev, 4493 "Allocation for Rx Queue %u failed\n", i); 4494 for (i--; i >= 0; i--) 4495 igb_free_rx_resources(adapter->rx_ring[i]); 4496 break; 4497 } 4498 } 4499 4500 return err; 4501 } 4502 4503 /** 4504 * igb_setup_mrqc - configure the multiple receive queue control registers 4505 * @adapter: Board private structure 4506 **/ 4507 static void igb_setup_mrqc(struct igb_adapter *adapter) 4508 { 4509 struct e1000_hw *hw = &adapter->hw; 4510 u32 mrqc, rxcsum; 4511 u32 j, num_rx_queues; 4512 u32 rss_key[10]; 4513 4514 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4515 for (j = 0; j < 10; j++) 4516 wr32(E1000_RSSRK(j), rss_key[j]); 4517 4518 num_rx_queues = adapter->rss_queues; 4519 4520 switch (hw->mac.type) { 4521 case e1000_82576: 4522 /* 82576 supports 2 RSS queues for SR-IOV */ 4523 if (adapter->vfs_allocated_count) 4524 num_rx_queues = 2; 4525 break; 4526 default: 4527 break; 4528 } 4529 4530 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4531 for (j = 0; j < IGB_RETA_SIZE; j++) 4532 adapter->rss_indir_tbl[j] = 4533 (j * num_rx_queues) / IGB_RETA_SIZE; 4534 adapter->rss_indir_tbl_init = num_rx_queues; 4535 } 4536 igb_write_rss_indir_tbl(adapter); 4537 4538 /* Disable raw packet checksumming so that RSS hash is placed in 4539 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4540 * offloads as they are enabled by default 4541 */ 4542 rxcsum = rd32(E1000_RXCSUM); 4543 rxcsum |= E1000_RXCSUM_PCSD; 4544 4545 if (adapter->hw.mac.type >= e1000_82576) 4546 /* Enable Receive Checksum Offload for SCTP */ 4547 rxcsum |= E1000_RXCSUM_CRCOFL; 4548 4549 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4550 wr32(E1000_RXCSUM, rxcsum); 4551 4552 /* Generate RSS hash based on packet types, TCP/UDP 4553 * port numbers and/or IPv4/v6 src and dst addresses 4554 */ 4555 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4556 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4557 E1000_MRQC_RSS_FIELD_IPV6 | 4558 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4559 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4560 4561 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4562 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4563 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4564 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4565 4566 /* If VMDq is enabled then we set the appropriate mode for that, else 4567 * we default to RSS so that an RSS hash is calculated per packet even 4568 * if we are only using one queue 4569 */ 4570 if (adapter->vfs_allocated_count) { 4571 if (hw->mac.type > e1000_82575) { 4572 /* Set the default pool for the PF's first queue */ 4573 u32 vtctl = rd32(E1000_VT_CTL); 4574 4575 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4576 E1000_VT_CTL_DISABLE_DEF_POOL); 4577 vtctl |= adapter->vfs_allocated_count << 4578 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4579 wr32(E1000_VT_CTL, vtctl); 4580 } 4581 if (adapter->rss_queues > 1) 4582 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4583 else 4584 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4585 } else { 4586 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4587 } 4588 igb_vmm_control(adapter); 4589 4590 wr32(E1000_MRQC, mrqc); 4591 } 4592 4593 /** 4594 * igb_setup_rctl - configure the receive control registers 4595 * @adapter: Board private structure 4596 **/ 4597 void igb_setup_rctl(struct igb_adapter *adapter) 4598 { 4599 struct e1000_hw *hw = &adapter->hw; 4600 u32 rctl; 4601 4602 rctl = rd32(E1000_RCTL); 4603 4604 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4605 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4606 4607 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4608 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4609 4610 /* enable stripping of CRC. It's unlikely this will break BMC 4611 * redirection as it did with e1000. Newer features require 4612 * that the HW strips the CRC. 4613 */ 4614 rctl |= E1000_RCTL_SECRC; 4615 4616 /* disable store bad packets and clear size bits. */ 4617 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4618 4619 /* enable LPE to allow for reception of jumbo frames */ 4620 rctl |= E1000_RCTL_LPE; 4621 4622 /* disable queue 0 to prevent tail write w/o re-config */ 4623 wr32(E1000_RXDCTL(0), 0); 4624 4625 /* Attention!!! For SR-IOV PF driver operations you must enable 4626 * queue drop for all VF and PF queues to prevent head of line blocking 4627 * if an un-trusted VF does not provide descriptors to hardware. 4628 */ 4629 if (adapter->vfs_allocated_count) { 4630 /* set all queue drop enable bits */ 4631 wr32(E1000_QDE, ALL_QUEUES); 4632 } 4633 4634 /* This is useful for sniffing bad packets. */ 4635 if (adapter->netdev->features & NETIF_F_RXALL) { 4636 /* UPE and MPE will be handled by normal PROMISC logic 4637 * in e1000e_set_rx_mode 4638 */ 4639 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4640 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4641 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4642 4643 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4644 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4645 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4646 * and that breaks VLANs. 4647 */ 4648 } 4649 4650 wr32(E1000_RCTL, rctl); 4651 } 4652 4653 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4654 int vfn) 4655 { 4656 struct e1000_hw *hw = &adapter->hw; 4657 u32 vmolr; 4658 4659 if (size > MAX_JUMBO_FRAME_SIZE) 4660 size = MAX_JUMBO_FRAME_SIZE; 4661 4662 vmolr = rd32(E1000_VMOLR(vfn)); 4663 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4664 vmolr |= size | E1000_VMOLR_LPE; 4665 wr32(E1000_VMOLR(vfn), vmolr); 4666 4667 return 0; 4668 } 4669 4670 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4671 int vfn, bool enable) 4672 { 4673 struct e1000_hw *hw = &adapter->hw; 4674 u32 val, reg; 4675 4676 if (hw->mac.type < e1000_82576) 4677 return; 4678 4679 if (hw->mac.type == e1000_i350) 4680 reg = E1000_DVMOLR(vfn); 4681 else 4682 reg = E1000_VMOLR(vfn); 4683 4684 val = rd32(reg); 4685 if (enable) 4686 val |= E1000_VMOLR_STRVLAN; 4687 else 4688 val &= ~(E1000_VMOLR_STRVLAN); 4689 wr32(reg, val); 4690 } 4691 4692 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4693 int vfn, bool aupe) 4694 { 4695 struct e1000_hw *hw = &adapter->hw; 4696 u32 vmolr; 4697 4698 /* This register exists only on 82576 and newer so if we are older then 4699 * we should exit and do nothing 4700 */ 4701 if (hw->mac.type < e1000_82576) 4702 return; 4703 4704 vmolr = rd32(E1000_VMOLR(vfn)); 4705 if (aupe) 4706 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4707 else 4708 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4709 4710 /* clear all bits that might not be set */ 4711 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4712 4713 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4714 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4715 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4716 * multicast packets 4717 */ 4718 if (vfn <= adapter->vfs_allocated_count) 4719 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4720 4721 wr32(E1000_VMOLR(vfn), vmolr); 4722 } 4723 4724 /** 4725 * igb_setup_srrctl - configure the split and replication receive control 4726 * registers 4727 * @adapter: Board private structure 4728 * @ring: receive ring to be configured 4729 **/ 4730 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4731 { 4732 struct e1000_hw *hw = &adapter->hw; 4733 int reg_idx = ring->reg_idx; 4734 u32 srrctl = 0; 4735 4736 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4737 if (ring_uses_large_buffer(ring)) 4738 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4739 else 4740 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4741 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4742 if (hw->mac.type >= e1000_82580) 4743 srrctl |= E1000_SRRCTL_TIMESTAMP; 4744 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4745 * queues and rx flow control is disabled 4746 */ 4747 if (adapter->vfs_allocated_count || 4748 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4749 adapter->num_rx_queues > 1)) 4750 srrctl |= E1000_SRRCTL_DROP_EN; 4751 4752 wr32(E1000_SRRCTL(reg_idx), srrctl); 4753 } 4754 4755 /** 4756 * igb_configure_rx_ring - Configure a receive ring after Reset 4757 * @adapter: board private structure 4758 * @ring: receive ring to be configured 4759 * 4760 * Configure the Rx unit of the MAC after a reset. 4761 **/ 4762 void igb_configure_rx_ring(struct igb_adapter *adapter, 4763 struct igb_ring *ring) 4764 { 4765 struct e1000_hw *hw = &adapter->hw; 4766 union e1000_adv_rx_desc *rx_desc; 4767 u64 rdba = ring->dma; 4768 int reg_idx = ring->reg_idx; 4769 u32 rxdctl = 0; 4770 4771 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4772 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4773 MEM_TYPE_PAGE_SHARED, NULL)); 4774 4775 /* disable the queue */ 4776 wr32(E1000_RXDCTL(reg_idx), 0); 4777 4778 /* Set DMA base address registers */ 4779 wr32(E1000_RDBAL(reg_idx), 4780 rdba & 0x00000000ffffffffULL); 4781 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4782 wr32(E1000_RDLEN(reg_idx), 4783 ring->count * sizeof(union e1000_adv_rx_desc)); 4784 4785 /* initialize head and tail */ 4786 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4787 wr32(E1000_RDH(reg_idx), 0); 4788 writel(0, ring->tail); 4789 4790 /* set descriptor configuration */ 4791 igb_setup_srrctl(adapter, ring); 4792 4793 /* set filtering for VMDQ pools */ 4794 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4795 4796 rxdctl |= IGB_RX_PTHRESH; 4797 rxdctl |= IGB_RX_HTHRESH << 8; 4798 rxdctl |= IGB_RX_WTHRESH << 16; 4799 4800 /* initialize rx_buffer_info */ 4801 memset(ring->rx_buffer_info, 0, 4802 sizeof(struct igb_rx_buffer) * ring->count); 4803 4804 /* initialize Rx descriptor 0 */ 4805 rx_desc = IGB_RX_DESC(ring, 0); 4806 rx_desc->wb.upper.length = 0; 4807 4808 /* enable receive descriptor fetching */ 4809 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4810 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4811 } 4812 4813 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4814 struct igb_ring *rx_ring) 4815 { 4816 /* set build_skb and buffer size flags */ 4817 clear_ring_build_skb_enabled(rx_ring); 4818 clear_ring_uses_large_buffer(rx_ring); 4819 4820 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4821 return; 4822 4823 set_ring_build_skb_enabled(rx_ring); 4824 4825 #if (PAGE_SIZE < 8192) 4826 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4827 return; 4828 4829 set_ring_uses_large_buffer(rx_ring); 4830 #endif 4831 } 4832 4833 /** 4834 * igb_configure_rx - Configure receive Unit after Reset 4835 * @adapter: board private structure 4836 * 4837 * Configure the Rx unit of the MAC after a reset. 4838 **/ 4839 static void igb_configure_rx(struct igb_adapter *adapter) 4840 { 4841 int i; 4842 4843 /* set the correct pool for the PF default MAC address in entry 0 */ 4844 igb_set_default_mac_filter(adapter); 4845 4846 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4847 * the Base and Length of the Rx Descriptor Ring 4848 */ 4849 for (i = 0; i < adapter->num_rx_queues; i++) { 4850 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4851 4852 igb_set_rx_buffer_len(adapter, rx_ring); 4853 igb_configure_rx_ring(adapter, rx_ring); 4854 } 4855 } 4856 4857 /** 4858 * igb_free_tx_resources - Free Tx Resources per Queue 4859 * @tx_ring: Tx descriptor ring for a specific queue 4860 * 4861 * Free all transmit software resources 4862 **/ 4863 void igb_free_tx_resources(struct igb_ring *tx_ring) 4864 { 4865 igb_clean_tx_ring(tx_ring); 4866 4867 vfree(tx_ring->tx_buffer_info); 4868 tx_ring->tx_buffer_info = NULL; 4869 4870 /* if not set, then don't free */ 4871 if (!tx_ring->desc) 4872 return; 4873 4874 dma_free_coherent(tx_ring->dev, tx_ring->size, 4875 tx_ring->desc, tx_ring->dma); 4876 4877 tx_ring->desc = NULL; 4878 } 4879 4880 /** 4881 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4882 * @adapter: board private structure 4883 * 4884 * Free all transmit software resources 4885 **/ 4886 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4887 { 4888 int i; 4889 4890 for (i = 0; i < adapter->num_tx_queues; i++) 4891 if (adapter->tx_ring[i]) 4892 igb_free_tx_resources(adapter->tx_ring[i]); 4893 } 4894 4895 /** 4896 * igb_clean_tx_ring - Free Tx Buffers 4897 * @tx_ring: ring to be cleaned 4898 **/ 4899 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4900 { 4901 u16 i = tx_ring->next_to_clean; 4902 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4903 4904 while (i != tx_ring->next_to_use) { 4905 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4906 4907 /* Free all the Tx ring sk_buffs or xdp frames */ 4908 if (tx_buffer->type == IGB_TYPE_SKB) 4909 dev_kfree_skb_any(tx_buffer->skb); 4910 else 4911 xdp_return_frame(tx_buffer->xdpf); 4912 4913 /* unmap skb header data */ 4914 dma_unmap_single(tx_ring->dev, 4915 dma_unmap_addr(tx_buffer, dma), 4916 dma_unmap_len(tx_buffer, len), 4917 DMA_TO_DEVICE); 4918 4919 /* check for eop_desc to determine the end of the packet */ 4920 eop_desc = tx_buffer->next_to_watch; 4921 tx_desc = IGB_TX_DESC(tx_ring, i); 4922 4923 /* unmap remaining buffers */ 4924 while (tx_desc != eop_desc) { 4925 tx_buffer++; 4926 tx_desc++; 4927 i++; 4928 if (unlikely(i == tx_ring->count)) { 4929 i = 0; 4930 tx_buffer = tx_ring->tx_buffer_info; 4931 tx_desc = IGB_TX_DESC(tx_ring, 0); 4932 } 4933 4934 /* unmap any remaining paged data */ 4935 if (dma_unmap_len(tx_buffer, len)) 4936 dma_unmap_page(tx_ring->dev, 4937 dma_unmap_addr(tx_buffer, dma), 4938 dma_unmap_len(tx_buffer, len), 4939 DMA_TO_DEVICE); 4940 } 4941 4942 tx_buffer->next_to_watch = NULL; 4943 4944 /* move us one more past the eop_desc for start of next pkt */ 4945 tx_buffer++; 4946 i++; 4947 if (unlikely(i == tx_ring->count)) { 4948 i = 0; 4949 tx_buffer = tx_ring->tx_buffer_info; 4950 } 4951 } 4952 4953 /* reset BQL for queue */ 4954 netdev_tx_reset_queue(txring_txq(tx_ring)); 4955 4956 /* reset next_to_use and next_to_clean */ 4957 tx_ring->next_to_use = 0; 4958 tx_ring->next_to_clean = 0; 4959 } 4960 4961 /** 4962 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4963 * @adapter: board private structure 4964 **/ 4965 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4966 { 4967 int i; 4968 4969 for (i = 0; i < adapter->num_tx_queues; i++) 4970 if (adapter->tx_ring[i]) 4971 igb_clean_tx_ring(adapter->tx_ring[i]); 4972 } 4973 4974 /** 4975 * igb_free_rx_resources - Free Rx Resources 4976 * @rx_ring: ring to clean the resources from 4977 * 4978 * Free all receive software resources 4979 **/ 4980 void igb_free_rx_resources(struct igb_ring *rx_ring) 4981 { 4982 igb_clean_rx_ring(rx_ring); 4983 4984 rx_ring->xdp_prog = NULL; 4985 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4986 vfree(rx_ring->rx_buffer_info); 4987 rx_ring->rx_buffer_info = NULL; 4988 4989 /* if not set, then don't free */ 4990 if (!rx_ring->desc) 4991 return; 4992 4993 dma_free_coherent(rx_ring->dev, rx_ring->size, 4994 rx_ring->desc, rx_ring->dma); 4995 4996 rx_ring->desc = NULL; 4997 } 4998 4999 /** 5000 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5001 * @adapter: board private structure 5002 * 5003 * Free all receive software resources 5004 **/ 5005 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5006 { 5007 int i; 5008 5009 for (i = 0; i < adapter->num_rx_queues; i++) 5010 if (adapter->rx_ring[i]) 5011 igb_free_rx_resources(adapter->rx_ring[i]); 5012 } 5013 5014 /** 5015 * igb_clean_rx_ring - Free Rx Buffers per Queue 5016 * @rx_ring: ring to free buffers from 5017 **/ 5018 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 5019 { 5020 u16 i = rx_ring->next_to_clean; 5021 5022 dev_kfree_skb(rx_ring->skb); 5023 rx_ring->skb = NULL; 5024 5025 /* Free all the Rx ring sk_buffs */ 5026 while (i != rx_ring->next_to_alloc) { 5027 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5028 5029 /* Invalidate cache lines that may have been written to by 5030 * device so that we avoid corrupting memory. 5031 */ 5032 dma_sync_single_range_for_cpu(rx_ring->dev, 5033 buffer_info->dma, 5034 buffer_info->page_offset, 5035 igb_rx_bufsz(rx_ring), 5036 DMA_FROM_DEVICE); 5037 5038 /* free resources associated with mapping */ 5039 dma_unmap_page_attrs(rx_ring->dev, 5040 buffer_info->dma, 5041 igb_rx_pg_size(rx_ring), 5042 DMA_FROM_DEVICE, 5043 IGB_RX_DMA_ATTR); 5044 __page_frag_cache_drain(buffer_info->page, 5045 buffer_info->pagecnt_bias); 5046 5047 i++; 5048 if (i == rx_ring->count) 5049 i = 0; 5050 } 5051 5052 rx_ring->next_to_alloc = 0; 5053 rx_ring->next_to_clean = 0; 5054 rx_ring->next_to_use = 0; 5055 } 5056 5057 /** 5058 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5059 * @adapter: board private structure 5060 **/ 5061 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5062 { 5063 int i; 5064 5065 for (i = 0; i < adapter->num_rx_queues; i++) 5066 if (adapter->rx_ring[i]) 5067 igb_clean_rx_ring(adapter->rx_ring[i]); 5068 } 5069 5070 /** 5071 * igb_set_mac - Change the Ethernet Address of the NIC 5072 * @netdev: network interface device structure 5073 * @p: pointer to an address structure 5074 * 5075 * Returns 0 on success, negative on failure 5076 **/ 5077 static int igb_set_mac(struct net_device *netdev, void *p) 5078 { 5079 struct igb_adapter *adapter = netdev_priv(netdev); 5080 struct e1000_hw *hw = &adapter->hw; 5081 struct sockaddr *addr = p; 5082 5083 if (!is_valid_ether_addr(addr->sa_data)) 5084 return -EADDRNOTAVAIL; 5085 5086 eth_hw_addr_set(netdev, addr->sa_data); 5087 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5088 5089 /* set the correct pool for the new PF MAC address in entry 0 */ 5090 igb_set_default_mac_filter(adapter); 5091 5092 return 0; 5093 } 5094 5095 /** 5096 * igb_write_mc_addr_list - write multicast addresses to MTA 5097 * @netdev: network interface device structure 5098 * 5099 * Writes multicast address list to the MTA hash table. 5100 * Returns: -ENOMEM on failure 5101 * 0 on no addresses written 5102 * X on writing X addresses to MTA 5103 **/ 5104 static int igb_write_mc_addr_list(struct net_device *netdev) 5105 { 5106 struct igb_adapter *adapter = netdev_priv(netdev); 5107 struct e1000_hw *hw = &adapter->hw; 5108 struct netdev_hw_addr *ha; 5109 u8 *mta_list; 5110 int i; 5111 5112 if (netdev_mc_empty(netdev)) { 5113 /* nothing to program, so clear mc list */ 5114 igb_update_mc_addr_list(hw, NULL, 0); 5115 igb_restore_vf_multicasts(adapter); 5116 return 0; 5117 } 5118 5119 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5120 if (!mta_list) 5121 return -ENOMEM; 5122 5123 /* The shared function expects a packed array of only addresses. */ 5124 i = 0; 5125 netdev_for_each_mc_addr(ha, netdev) 5126 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5127 5128 igb_update_mc_addr_list(hw, mta_list, i); 5129 kfree(mta_list); 5130 5131 return netdev_mc_count(netdev); 5132 } 5133 5134 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5135 { 5136 struct e1000_hw *hw = &adapter->hw; 5137 u32 i, pf_id; 5138 5139 switch (hw->mac.type) { 5140 case e1000_i210: 5141 case e1000_i211: 5142 case e1000_i350: 5143 /* VLAN filtering needed for VLAN prio filter */ 5144 if (adapter->netdev->features & NETIF_F_NTUPLE) 5145 break; 5146 fallthrough; 5147 case e1000_82576: 5148 case e1000_82580: 5149 case e1000_i354: 5150 /* VLAN filtering needed for pool filtering */ 5151 if (adapter->vfs_allocated_count) 5152 break; 5153 fallthrough; 5154 default: 5155 return 1; 5156 } 5157 5158 /* We are already in VLAN promisc, nothing to do */ 5159 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5160 return 0; 5161 5162 if (!adapter->vfs_allocated_count) 5163 goto set_vfta; 5164 5165 /* Add PF to all active pools */ 5166 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5167 5168 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5169 u32 vlvf = rd32(E1000_VLVF(i)); 5170 5171 vlvf |= BIT(pf_id); 5172 wr32(E1000_VLVF(i), vlvf); 5173 } 5174 5175 set_vfta: 5176 /* Set all bits in the VLAN filter table array */ 5177 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5178 hw->mac.ops.write_vfta(hw, i, ~0U); 5179 5180 /* Set flag so we don't redo unnecessary work */ 5181 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5182 5183 return 0; 5184 } 5185 5186 #define VFTA_BLOCK_SIZE 8 5187 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5188 { 5189 struct e1000_hw *hw = &adapter->hw; 5190 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5191 u32 vid_start = vfta_offset * 32; 5192 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5193 u32 i, vid, word, bits, pf_id; 5194 5195 /* guarantee that we don't scrub out management VLAN */ 5196 vid = adapter->mng_vlan_id; 5197 if (vid >= vid_start && vid < vid_end) 5198 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5199 5200 if (!adapter->vfs_allocated_count) 5201 goto set_vfta; 5202 5203 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5204 5205 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5206 u32 vlvf = rd32(E1000_VLVF(i)); 5207 5208 /* pull VLAN ID from VLVF */ 5209 vid = vlvf & VLAN_VID_MASK; 5210 5211 /* only concern ourselves with a certain range */ 5212 if (vid < vid_start || vid >= vid_end) 5213 continue; 5214 5215 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5216 /* record VLAN ID in VFTA */ 5217 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5218 5219 /* if PF is part of this then continue */ 5220 if (test_bit(vid, adapter->active_vlans)) 5221 continue; 5222 } 5223 5224 /* remove PF from the pool */ 5225 bits = ~BIT(pf_id); 5226 bits &= rd32(E1000_VLVF(i)); 5227 wr32(E1000_VLVF(i), bits); 5228 } 5229 5230 set_vfta: 5231 /* extract values from active_vlans and write back to VFTA */ 5232 for (i = VFTA_BLOCK_SIZE; i--;) { 5233 vid = (vfta_offset + i) * 32; 5234 word = vid / BITS_PER_LONG; 5235 bits = vid % BITS_PER_LONG; 5236 5237 vfta[i] |= adapter->active_vlans[word] >> bits; 5238 5239 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5240 } 5241 } 5242 5243 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5244 { 5245 u32 i; 5246 5247 /* We are not in VLAN promisc, nothing to do */ 5248 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5249 return; 5250 5251 /* Set flag so we don't redo unnecessary work */ 5252 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5253 5254 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5255 igb_scrub_vfta(adapter, i); 5256 } 5257 5258 /** 5259 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5260 * @netdev: network interface device structure 5261 * 5262 * The set_rx_mode entry point is called whenever the unicast or multicast 5263 * address lists or the network interface flags are updated. This routine is 5264 * responsible for configuring the hardware for proper unicast, multicast, 5265 * promiscuous mode, and all-multi behavior. 5266 **/ 5267 static void igb_set_rx_mode(struct net_device *netdev) 5268 { 5269 struct igb_adapter *adapter = netdev_priv(netdev); 5270 struct e1000_hw *hw = &adapter->hw; 5271 unsigned int vfn = adapter->vfs_allocated_count; 5272 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5273 int count; 5274 5275 /* Check for Promiscuous and All Multicast modes */ 5276 if (netdev->flags & IFF_PROMISC) { 5277 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5278 vmolr |= E1000_VMOLR_MPME; 5279 5280 /* enable use of UTA filter to force packets to default pool */ 5281 if (hw->mac.type == e1000_82576) 5282 vmolr |= E1000_VMOLR_ROPE; 5283 } else { 5284 if (netdev->flags & IFF_ALLMULTI) { 5285 rctl |= E1000_RCTL_MPE; 5286 vmolr |= E1000_VMOLR_MPME; 5287 } else { 5288 /* Write addresses to the MTA, if the attempt fails 5289 * then we should just turn on promiscuous mode so 5290 * that we can at least receive multicast traffic 5291 */ 5292 count = igb_write_mc_addr_list(netdev); 5293 if (count < 0) { 5294 rctl |= E1000_RCTL_MPE; 5295 vmolr |= E1000_VMOLR_MPME; 5296 } else if (count) { 5297 vmolr |= E1000_VMOLR_ROMPE; 5298 } 5299 } 5300 } 5301 5302 /* Write addresses to available RAR registers, if there is not 5303 * sufficient space to store all the addresses then enable 5304 * unicast promiscuous mode 5305 */ 5306 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5307 rctl |= E1000_RCTL_UPE; 5308 vmolr |= E1000_VMOLR_ROPE; 5309 } 5310 5311 /* enable VLAN filtering by default */ 5312 rctl |= E1000_RCTL_VFE; 5313 5314 /* disable VLAN filtering for modes that require it */ 5315 if ((netdev->flags & IFF_PROMISC) || 5316 (netdev->features & NETIF_F_RXALL)) { 5317 /* if we fail to set all rules then just clear VFE */ 5318 if (igb_vlan_promisc_enable(adapter)) 5319 rctl &= ~E1000_RCTL_VFE; 5320 } else { 5321 igb_vlan_promisc_disable(adapter); 5322 } 5323 5324 /* update state of unicast, multicast, and VLAN filtering modes */ 5325 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5326 E1000_RCTL_VFE); 5327 wr32(E1000_RCTL, rctl); 5328 5329 #if (PAGE_SIZE < 8192) 5330 if (!adapter->vfs_allocated_count) { 5331 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5332 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5333 } 5334 #endif 5335 wr32(E1000_RLPML, rlpml); 5336 5337 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5338 * the VMOLR to enable the appropriate modes. Without this workaround 5339 * we will have issues with VLAN tag stripping not being done for frames 5340 * that are only arriving because we are the default pool 5341 */ 5342 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5343 return; 5344 5345 /* set UTA to appropriate mode */ 5346 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5347 5348 vmolr |= rd32(E1000_VMOLR(vfn)) & 5349 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5350 5351 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5352 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5353 #if (PAGE_SIZE < 8192) 5354 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5355 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5356 else 5357 #endif 5358 vmolr |= MAX_JUMBO_FRAME_SIZE; 5359 vmolr |= E1000_VMOLR_LPE; 5360 5361 wr32(E1000_VMOLR(vfn), vmolr); 5362 5363 igb_restore_vf_multicasts(adapter); 5364 } 5365 5366 static void igb_check_wvbr(struct igb_adapter *adapter) 5367 { 5368 struct e1000_hw *hw = &adapter->hw; 5369 u32 wvbr = 0; 5370 5371 switch (hw->mac.type) { 5372 case e1000_82576: 5373 case e1000_i350: 5374 wvbr = rd32(E1000_WVBR); 5375 if (!wvbr) 5376 return; 5377 break; 5378 default: 5379 break; 5380 } 5381 5382 adapter->wvbr |= wvbr; 5383 } 5384 5385 #define IGB_STAGGERED_QUEUE_OFFSET 8 5386 5387 static void igb_spoof_check(struct igb_adapter *adapter) 5388 { 5389 int j; 5390 5391 if (!adapter->wvbr) 5392 return; 5393 5394 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5395 if (adapter->wvbr & BIT(j) || 5396 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5397 dev_warn(&adapter->pdev->dev, 5398 "Spoof event(s) detected on VF %d\n", j); 5399 adapter->wvbr &= 5400 ~(BIT(j) | 5401 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5402 } 5403 } 5404 } 5405 5406 /* Need to wait a few seconds after link up to get diagnostic information from 5407 * the phy 5408 */ 5409 static void igb_update_phy_info(struct timer_list *t) 5410 { 5411 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5412 igb_get_phy_info(&adapter->hw); 5413 } 5414 5415 /** 5416 * igb_has_link - check shared code for link and determine up/down 5417 * @adapter: pointer to driver private info 5418 **/ 5419 bool igb_has_link(struct igb_adapter *adapter) 5420 { 5421 struct e1000_hw *hw = &adapter->hw; 5422 bool link_active = false; 5423 5424 /* get_link_status is set on LSC (link status) interrupt or 5425 * rx sequence error interrupt. get_link_status will stay 5426 * false until the e1000_check_for_link establishes link 5427 * for copper adapters ONLY 5428 */ 5429 switch (hw->phy.media_type) { 5430 case e1000_media_type_copper: 5431 if (!hw->mac.get_link_status) 5432 return true; 5433 fallthrough; 5434 case e1000_media_type_internal_serdes: 5435 hw->mac.ops.check_for_link(hw); 5436 link_active = !hw->mac.get_link_status; 5437 break; 5438 default: 5439 case e1000_media_type_unknown: 5440 break; 5441 } 5442 5443 if (((hw->mac.type == e1000_i210) || 5444 (hw->mac.type == e1000_i211)) && 5445 (hw->phy.id == I210_I_PHY_ID)) { 5446 if (!netif_carrier_ok(adapter->netdev)) { 5447 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5448 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5449 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5450 adapter->link_check_timeout = jiffies; 5451 } 5452 } 5453 5454 return link_active; 5455 } 5456 5457 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5458 { 5459 bool ret = false; 5460 u32 ctrl_ext, thstat; 5461 5462 /* check for thermal sensor event on i350 copper only */ 5463 if (hw->mac.type == e1000_i350) { 5464 thstat = rd32(E1000_THSTAT); 5465 ctrl_ext = rd32(E1000_CTRL_EXT); 5466 5467 if ((hw->phy.media_type == e1000_media_type_copper) && 5468 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5469 ret = !!(thstat & event); 5470 } 5471 5472 return ret; 5473 } 5474 5475 /** 5476 * igb_check_lvmmc - check for malformed packets received 5477 * and indicated in LVMMC register 5478 * @adapter: pointer to adapter 5479 **/ 5480 static void igb_check_lvmmc(struct igb_adapter *adapter) 5481 { 5482 struct e1000_hw *hw = &adapter->hw; 5483 u32 lvmmc; 5484 5485 lvmmc = rd32(E1000_LVMMC); 5486 if (lvmmc) { 5487 if (unlikely(net_ratelimit())) { 5488 netdev_warn(adapter->netdev, 5489 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5490 lvmmc); 5491 } 5492 } 5493 } 5494 5495 /** 5496 * igb_watchdog - Timer Call-back 5497 * @t: pointer to timer_list containing our private info pointer 5498 **/ 5499 static void igb_watchdog(struct timer_list *t) 5500 { 5501 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5502 /* Do the rest outside of interrupt context */ 5503 schedule_work(&adapter->watchdog_task); 5504 } 5505 5506 static void igb_watchdog_task(struct work_struct *work) 5507 { 5508 struct igb_adapter *adapter = container_of(work, 5509 struct igb_adapter, 5510 watchdog_task); 5511 struct e1000_hw *hw = &adapter->hw; 5512 struct e1000_phy_info *phy = &hw->phy; 5513 struct net_device *netdev = adapter->netdev; 5514 u32 link; 5515 int i; 5516 u32 connsw; 5517 u16 phy_data, retry_count = 20; 5518 5519 link = igb_has_link(adapter); 5520 5521 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5522 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5523 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5524 else 5525 link = false; 5526 } 5527 5528 /* Force link down if we have fiber to swap to */ 5529 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5530 if (hw->phy.media_type == e1000_media_type_copper) { 5531 connsw = rd32(E1000_CONNSW); 5532 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5533 link = 0; 5534 } 5535 } 5536 if (link) { 5537 /* Perform a reset if the media type changed. */ 5538 if (hw->dev_spec._82575.media_changed) { 5539 hw->dev_spec._82575.media_changed = false; 5540 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5541 igb_reset(adapter); 5542 } 5543 /* Cancel scheduled suspend requests. */ 5544 pm_runtime_resume(netdev->dev.parent); 5545 5546 if (!netif_carrier_ok(netdev)) { 5547 u32 ctrl; 5548 5549 hw->mac.ops.get_speed_and_duplex(hw, 5550 &adapter->link_speed, 5551 &adapter->link_duplex); 5552 5553 ctrl = rd32(E1000_CTRL); 5554 /* Links status message must follow this format */ 5555 netdev_info(netdev, 5556 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5557 netdev->name, 5558 adapter->link_speed, 5559 adapter->link_duplex == FULL_DUPLEX ? 5560 "Full" : "Half", 5561 (ctrl & E1000_CTRL_TFCE) && 5562 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5563 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5564 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5565 5566 /* disable EEE if enabled */ 5567 if ((adapter->flags & IGB_FLAG_EEE) && 5568 (adapter->link_duplex == HALF_DUPLEX)) { 5569 dev_info(&adapter->pdev->dev, 5570 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5571 adapter->hw.dev_spec._82575.eee_disable = true; 5572 adapter->flags &= ~IGB_FLAG_EEE; 5573 } 5574 5575 /* check if SmartSpeed worked */ 5576 igb_check_downshift(hw); 5577 if (phy->speed_downgraded) 5578 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5579 5580 /* check for thermal sensor event */ 5581 if (igb_thermal_sensor_event(hw, 5582 E1000_THSTAT_LINK_THROTTLE)) 5583 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5584 5585 /* adjust timeout factor according to speed/duplex */ 5586 adapter->tx_timeout_factor = 1; 5587 switch (adapter->link_speed) { 5588 case SPEED_10: 5589 adapter->tx_timeout_factor = 14; 5590 break; 5591 case SPEED_100: 5592 /* maybe add some timeout factor ? */ 5593 break; 5594 } 5595 5596 if (adapter->link_speed != SPEED_1000 || 5597 !hw->phy.ops.read_reg) 5598 goto no_wait; 5599 5600 /* wait for Remote receiver status OK */ 5601 retry_read_status: 5602 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5603 &phy_data)) { 5604 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5605 retry_count) { 5606 msleep(100); 5607 retry_count--; 5608 goto retry_read_status; 5609 } else if (!retry_count) { 5610 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5611 } 5612 } else { 5613 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5614 } 5615 no_wait: 5616 netif_carrier_on(netdev); 5617 5618 igb_ping_all_vfs(adapter); 5619 igb_check_vf_rate_limit(adapter); 5620 5621 /* link state has changed, schedule phy info update */ 5622 if (!test_bit(__IGB_DOWN, &adapter->state)) 5623 mod_timer(&adapter->phy_info_timer, 5624 round_jiffies(jiffies + 2 * HZ)); 5625 } 5626 } else { 5627 if (netif_carrier_ok(netdev)) { 5628 adapter->link_speed = 0; 5629 adapter->link_duplex = 0; 5630 5631 /* check for thermal sensor event */ 5632 if (igb_thermal_sensor_event(hw, 5633 E1000_THSTAT_PWR_DOWN)) { 5634 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5635 } 5636 5637 /* Links status message must follow this format */ 5638 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5639 netdev->name); 5640 netif_carrier_off(netdev); 5641 5642 igb_ping_all_vfs(adapter); 5643 5644 /* link state has changed, schedule phy info update */ 5645 if (!test_bit(__IGB_DOWN, &adapter->state)) 5646 mod_timer(&adapter->phy_info_timer, 5647 round_jiffies(jiffies + 2 * HZ)); 5648 5649 /* link is down, time to check for alternate media */ 5650 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5651 igb_check_swap_media(adapter); 5652 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5653 schedule_work(&adapter->reset_task); 5654 /* return immediately */ 5655 return; 5656 } 5657 } 5658 pm_schedule_suspend(netdev->dev.parent, 5659 MSEC_PER_SEC * 5); 5660 5661 /* also check for alternate media here */ 5662 } else if (!netif_carrier_ok(netdev) && 5663 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5664 igb_check_swap_media(adapter); 5665 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5666 schedule_work(&adapter->reset_task); 5667 /* return immediately */ 5668 return; 5669 } 5670 } 5671 } 5672 5673 spin_lock(&adapter->stats64_lock); 5674 igb_update_stats(adapter); 5675 spin_unlock(&adapter->stats64_lock); 5676 5677 for (i = 0; i < adapter->num_tx_queues; i++) { 5678 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5679 if (!netif_carrier_ok(netdev)) { 5680 /* We've lost link, so the controller stops DMA, 5681 * but we've got queued Tx work that's never going 5682 * to get done, so reset controller to flush Tx. 5683 * (Do the reset outside of interrupt context). 5684 */ 5685 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5686 adapter->tx_timeout_count++; 5687 schedule_work(&adapter->reset_task); 5688 /* return immediately since reset is imminent */ 5689 return; 5690 } 5691 } 5692 5693 /* Force detection of hung controller every watchdog period */ 5694 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5695 } 5696 5697 /* Cause software interrupt to ensure Rx ring is cleaned */ 5698 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5699 u32 eics = 0; 5700 5701 for (i = 0; i < adapter->num_q_vectors; i++) 5702 eics |= adapter->q_vector[i]->eims_value; 5703 wr32(E1000_EICS, eics); 5704 } else { 5705 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5706 } 5707 5708 igb_spoof_check(adapter); 5709 igb_ptp_rx_hang(adapter); 5710 igb_ptp_tx_hang(adapter); 5711 5712 /* Check LVMMC register on i350/i354 only */ 5713 if ((adapter->hw.mac.type == e1000_i350) || 5714 (adapter->hw.mac.type == e1000_i354)) 5715 igb_check_lvmmc(adapter); 5716 5717 /* Reset the timer */ 5718 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5719 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5720 mod_timer(&adapter->watchdog_timer, 5721 round_jiffies(jiffies + HZ)); 5722 else 5723 mod_timer(&adapter->watchdog_timer, 5724 round_jiffies(jiffies + 2 * HZ)); 5725 } 5726 } 5727 5728 enum latency_range { 5729 lowest_latency = 0, 5730 low_latency = 1, 5731 bulk_latency = 2, 5732 latency_invalid = 255 5733 }; 5734 5735 /** 5736 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5737 * @q_vector: pointer to q_vector 5738 * 5739 * Stores a new ITR value based on strictly on packet size. This 5740 * algorithm is less sophisticated than that used in igb_update_itr, 5741 * due to the difficulty of synchronizing statistics across multiple 5742 * receive rings. The divisors and thresholds used by this function 5743 * were determined based on theoretical maximum wire speed and testing 5744 * data, in order to minimize response time while increasing bulk 5745 * throughput. 5746 * This functionality is controlled by ethtool's coalescing settings. 5747 * NOTE: This function is called only when operating in a multiqueue 5748 * receive environment. 5749 **/ 5750 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5751 { 5752 int new_val = q_vector->itr_val; 5753 int avg_wire_size = 0; 5754 struct igb_adapter *adapter = q_vector->adapter; 5755 unsigned int packets; 5756 5757 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5758 * ints/sec - ITR timer value of 120 ticks. 5759 */ 5760 if (adapter->link_speed != SPEED_1000) { 5761 new_val = IGB_4K_ITR; 5762 goto set_itr_val; 5763 } 5764 5765 packets = q_vector->rx.total_packets; 5766 if (packets) 5767 avg_wire_size = q_vector->rx.total_bytes / packets; 5768 5769 packets = q_vector->tx.total_packets; 5770 if (packets) 5771 avg_wire_size = max_t(u32, avg_wire_size, 5772 q_vector->tx.total_bytes / packets); 5773 5774 /* if avg_wire_size isn't set no work was done */ 5775 if (!avg_wire_size) 5776 goto clear_counts; 5777 5778 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5779 avg_wire_size += 24; 5780 5781 /* Don't starve jumbo frames */ 5782 avg_wire_size = min(avg_wire_size, 3000); 5783 5784 /* Give a little boost to mid-size frames */ 5785 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5786 new_val = avg_wire_size / 3; 5787 else 5788 new_val = avg_wire_size / 2; 5789 5790 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5791 if (new_val < IGB_20K_ITR && 5792 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5793 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5794 new_val = IGB_20K_ITR; 5795 5796 set_itr_val: 5797 if (new_val != q_vector->itr_val) { 5798 q_vector->itr_val = new_val; 5799 q_vector->set_itr = 1; 5800 } 5801 clear_counts: 5802 q_vector->rx.total_bytes = 0; 5803 q_vector->rx.total_packets = 0; 5804 q_vector->tx.total_bytes = 0; 5805 q_vector->tx.total_packets = 0; 5806 } 5807 5808 /** 5809 * igb_update_itr - update the dynamic ITR value based on statistics 5810 * @q_vector: pointer to q_vector 5811 * @ring_container: ring info to update the itr for 5812 * 5813 * Stores a new ITR value based on packets and byte 5814 * counts during the last interrupt. The advantage of per interrupt 5815 * computation is faster updates and more accurate ITR for the current 5816 * traffic pattern. Constants in this function were computed 5817 * based on theoretical maximum wire speed and thresholds were set based 5818 * on testing data as well as attempting to minimize response time 5819 * while increasing bulk throughput. 5820 * This functionality is controlled by ethtool's coalescing settings. 5821 * NOTE: These calculations are only valid when operating in a single- 5822 * queue environment. 5823 **/ 5824 static void igb_update_itr(struct igb_q_vector *q_vector, 5825 struct igb_ring_container *ring_container) 5826 { 5827 unsigned int packets = ring_container->total_packets; 5828 unsigned int bytes = ring_container->total_bytes; 5829 u8 itrval = ring_container->itr; 5830 5831 /* no packets, exit with status unchanged */ 5832 if (packets == 0) 5833 return; 5834 5835 switch (itrval) { 5836 case lowest_latency: 5837 /* handle TSO and jumbo frames */ 5838 if (bytes/packets > 8000) 5839 itrval = bulk_latency; 5840 else if ((packets < 5) && (bytes > 512)) 5841 itrval = low_latency; 5842 break; 5843 case low_latency: /* 50 usec aka 20000 ints/s */ 5844 if (bytes > 10000) { 5845 /* this if handles the TSO accounting */ 5846 if (bytes/packets > 8000) 5847 itrval = bulk_latency; 5848 else if ((packets < 10) || ((bytes/packets) > 1200)) 5849 itrval = bulk_latency; 5850 else if ((packets > 35)) 5851 itrval = lowest_latency; 5852 } else if (bytes/packets > 2000) { 5853 itrval = bulk_latency; 5854 } else if (packets <= 2 && bytes < 512) { 5855 itrval = lowest_latency; 5856 } 5857 break; 5858 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5859 if (bytes > 25000) { 5860 if (packets > 35) 5861 itrval = low_latency; 5862 } else if (bytes < 1500) { 5863 itrval = low_latency; 5864 } 5865 break; 5866 } 5867 5868 /* clear work counters since we have the values we need */ 5869 ring_container->total_bytes = 0; 5870 ring_container->total_packets = 0; 5871 5872 /* write updated itr to ring container */ 5873 ring_container->itr = itrval; 5874 } 5875 5876 static void igb_set_itr(struct igb_q_vector *q_vector) 5877 { 5878 struct igb_adapter *adapter = q_vector->adapter; 5879 u32 new_itr = q_vector->itr_val; 5880 u8 current_itr = 0; 5881 5882 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5883 if (adapter->link_speed != SPEED_1000) { 5884 current_itr = 0; 5885 new_itr = IGB_4K_ITR; 5886 goto set_itr_now; 5887 } 5888 5889 igb_update_itr(q_vector, &q_vector->tx); 5890 igb_update_itr(q_vector, &q_vector->rx); 5891 5892 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5893 5894 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5895 if (current_itr == lowest_latency && 5896 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5897 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5898 current_itr = low_latency; 5899 5900 switch (current_itr) { 5901 /* counts and packets in update_itr are dependent on these numbers */ 5902 case lowest_latency: 5903 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5904 break; 5905 case low_latency: 5906 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5907 break; 5908 case bulk_latency: 5909 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5910 break; 5911 default: 5912 break; 5913 } 5914 5915 set_itr_now: 5916 if (new_itr != q_vector->itr_val) { 5917 /* this attempts to bias the interrupt rate towards Bulk 5918 * by adding intermediate steps when interrupt rate is 5919 * increasing 5920 */ 5921 new_itr = new_itr > q_vector->itr_val ? 5922 max((new_itr * q_vector->itr_val) / 5923 (new_itr + (q_vector->itr_val >> 2)), 5924 new_itr) : new_itr; 5925 /* Don't write the value here; it resets the adapter's 5926 * internal timer, and causes us to delay far longer than 5927 * we should between interrupts. Instead, we write the ITR 5928 * value at the beginning of the next interrupt so the timing 5929 * ends up being correct. 5930 */ 5931 q_vector->itr_val = new_itr; 5932 q_vector->set_itr = 1; 5933 } 5934 } 5935 5936 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5937 struct igb_tx_buffer *first, 5938 u32 vlan_macip_lens, u32 type_tucmd, 5939 u32 mss_l4len_idx) 5940 { 5941 struct e1000_adv_tx_context_desc *context_desc; 5942 u16 i = tx_ring->next_to_use; 5943 struct timespec64 ts; 5944 5945 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5946 5947 i++; 5948 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5949 5950 /* set bits to identify this as an advanced context descriptor */ 5951 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5952 5953 /* For 82575, context index must be unique per ring. */ 5954 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5955 mss_l4len_idx |= tx_ring->reg_idx << 4; 5956 5957 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5958 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5959 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5960 5961 /* We assume there is always a valid tx time available. Invalid times 5962 * should have been handled by the upper layers. 5963 */ 5964 if (tx_ring->launchtime_enable) { 5965 ts = ktime_to_timespec64(first->skb->tstamp); 5966 skb_txtime_consumed(first->skb); 5967 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5968 } else { 5969 context_desc->seqnum_seed = 0; 5970 } 5971 } 5972 5973 static int igb_tso(struct igb_ring *tx_ring, 5974 struct igb_tx_buffer *first, 5975 u8 *hdr_len) 5976 { 5977 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5978 struct sk_buff *skb = first->skb; 5979 union { 5980 struct iphdr *v4; 5981 struct ipv6hdr *v6; 5982 unsigned char *hdr; 5983 } ip; 5984 union { 5985 struct tcphdr *tcp; 5986 struct udphdr *udp; 5987 unsigned char *hdr; 5988 } l4; 5989 u32 paylen, l4_offset; 5990 int err; 5991 5992 if (skb->ip_summed != CHECKSUM_PARTIAL) 5993 return 0; 5994 5995 if (!skb_is_gso(skb)) 5996 return 0; 5997 5998 err = skb_cow_head(skb, 0); 5999 if (err < 0) 6000 return err; 6001 6002 ip.hdr = skb_network_header(skb); 6003 l4.hdr = skb_checksum_start(skb); 6004 6005 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6006 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6007 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6008 6009 /* initialize outer IP header fields */ 6010 if (ip.v4->version == 4) { 6011 unsigned char *csum_start = skb_checksum_start(skb); 6012 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6013 6014 /* IP header will have to cancel out any data that 6015 * is not a part of the outer IP header 6016 */ 6017 ip.v4->check = csum_fold(csum_partial(trans_start, 6018 csum_start - trans_start, 6019 0)); 6020 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6021 6022 ip.v4->tot_len = 0; 6023 first->tx_flags |= IGB_TX_FLAGS_TSO | 6024 IGB_TX_FLAGS_CSUM | 6025 IGB_TX_FLAGS_IPV4; 6026 } else { 6027 ip.v6->payload_len = 0; 6028 first->tx_flags |= IGB_TX_FLAGS_TSO | 6029 IGB_TX_FLAGS_CSUM; 6030 } 6031 6032 /* determine offset of inner transport header */ 6033 l4_offset = l4.hdr - skb->data; 6034 6035 /* remove payload length from inner checksum */ 6036 paylen = skb->len - l4_offset; 6037 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6038 /* compute length of segmentation header */ 6039 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6040 csum_replace_by_diff(&l4.tcp->check, 6041 (__force __wsum)htonl(paylen)); 6042 } else { 6043 /* compute length of segmentation header */ 6044 *hdr_len = sizeof(*l4.udp) + l4_offset; 6045 csum_replace_by_diff(&l4.udp->check, 6046 (__force __wsum)htonl(paylen)); 6047 } 6048 6049 /* update gso size and bytecount with header size */ 6050 first->gso_segs = skb_shinfo(skb)->gso_segs; 6051 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6052 6053 /* MSS L4LEN IDX */ 6054 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6055 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6056 6057 /* VLAN MACLEN IPLEN */ 6058 vlan_macip_lens = l4.hdr - ip.hdr; 6059 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6060 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6061 6062 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6063 type_tucmd, mss_l4len_idx); 6064 6065 return 1; 6066 } 6067 6068 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6069 { 6070 struct sk_buff *skb = first->skb; 6071 u32 vlan_macip_lens = 0; 6072 u32 type_tucmd = 0; 6073 6074 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6075 csum_failed: 6076 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6077 !tx_ring->launchtime_enable) 6078 return; 6079 goto no_csum; 6080 } 6081 6082 switch (skb->csum_offset) { 6083 case offsetof(struct tcphdr, check): 6084 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6085 fallthrough; 6086 case offsetof(struct udphdr, check): 6087 break; 6088 case offsetof(struct sctphdr, checksum): 6089 /* validate that this is actually an SCTP request */ 6090 if (skb_csum_is_sctp(skb)) { 6091 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6092 break; 6093 } 6094 fallthrough; 6095 default: 6096 skb_checksum_help(skb); 6097 goto csum_failed; 6098 } 6099 6100 /* update TX checksum flag */ 6101 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6102 vlan_macip_lens = skb_checksum_start_offset(skb) - 6103 skb_network_offset(skb); 6104 no_csum: 6105 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6106 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6107 6108 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6109 } 6110 6111 #define IGB_SET_FLAG(_input, _flag, _result) \ 6112 ((_flag <= _result) ? \ 6113 ((u32)(_input & _flag) * (_result / _flag)) : \ 6114 ((u32)(_input & _flag) / (_flag / _result))) 6115 6116 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6117 { 6118 /* set type for advanced descriptor with frame checksum insertion */ 6119 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6120 E1000_ADVTXD_DCMD_DEXT | 6121 E1000_ADVTXD_DCMD_IFCS; 6122 6123 /* set HW vlan bit if vlan is present */ 6124 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6125 (E1000_ADVTXD_DCMD_VLE)); 6126 6127 /* set segmentation bits for TSO */ 6128 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6129 (E1000_ADVTXD_DCMD_TSE)); 6130 6131 /* set timestamp bit if present */ 6132 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6133 (E1000_ADVTXD_MAC_TSTAMP)); 6134 6135 /* insert frame checksum */ 6136 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6137 6138 return cmd_type; 6139 } 6140 6141 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6142 union e1000_adv_tx_desc *tx_desc, 6143 u32 tx_flags, unsigned int paylen) 6144 { 6145 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6146 6147 /* 82575 requires a unique index per ring */ 6148 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6149 olinfo_status |= tx_ring->reg_idx << 4; 6150 6151 /* insert L4 checksum */ 6152 olinfo_status |= IGB_SET_FLAG(tx_flags, 6153 IGB_TX_FLAGS_CSUM, 6154 (E1000_TXD_POPTS_TXSM << 8)); 6155 6156 /* insert IPv4 checksum */ 6157 olinfo_status |= IGB_SET_FLAG(tx_flags, 6158 IGB_TX_FLAGS_IPV4, 6159 (E1000_TXD_POPTS_IXSM << 8)); 6160 6161 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6162 } 6163 6164 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6165 { 6166 struct net_device *netdev = tx_ring->netdev; 6167 6168 netif_stop_subqueue(netdev, tx_ring->queue_index); 6169 6170 /* Herbert's original patch had: 6171 * smp_mb__after_netif_stop_queue(); 6172 * but since that doesn't exist yet, just open code it. 6173 */ 6174 smp_mb(); 6175 6176 /* We need to check again in a case another CPU has just 6177 * made room available. 6178 */ 6179 if (igb_desc_unused(tx_ring) < size) 6180 return -EBUSY; 6181 6182 /* A reprieve! */ 6183 netif_wake_subqueue(netdev, tx_ring->queue_index); 6184 6185 u64_stats_update_begin(&tx_ring->tx_syncp2); 6186 tx_ring->tx_stats.restart_queue2++; 6187 u64_stats_update_end(&tx_ring->tx_syncp2); 6188 6189 return 0; 6190 } 6191 6192 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6193 { 6194 if (igb_desc_unused(tx_ring) >= size) 6195 return 0; 6196 return __igb_maybe_stop_tx(tx_ring, size); 6197 } 6198 6199 static int igb_tx_map(struct igb_ring *tx_ring, 6200 struct igb_tx_buffer *first, 6201 const u8 hdr_len) 6202 { 6203 struct sk_buff *skb = first->skb; 6204 struct igb_tx_buffer *tx_buffer; 6205 union e1000_adv_tx_desc *tx_desc; 6206 skb_frag_t *frag; 6207 dma_addr_t dma; 6208 unsigned int data_len, size; 6209 u32 tx_flags = first->tx_flags; 6210 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6211 u16 i = tx_ring->next_to_use; 6212 6213 tx_desc = IGB_TX_DESC(tx_ring, i); 6214 6215 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6216 6217 size = skb_headlen(skb); 6218 data_len = skb->data_len; 6219 6220 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6221 6222 tx_buffer = first; 6223 6224 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6225 if (dma_mapping_error(tx_ring->dev, dma)) 6226 goto dma_error; 6227 6228 /* record length, and DMA address */ 6229 dma_unmap_len_set(tx_buffer, len, size); 6230 dma_unmap_addr_set(tx_buffer, dma, dma); 6231 6232 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6233 6234 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6235 tx_desc->read.cmd_type_len = 6236 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6237 6238 i++; 6239 tx_desc++; 6240 if (i == tx_ring->count) { 6241 tx_desc = IGB_TX_DESC(tx_ring, 0); 6242 i = 0; 6243 } 6244 tx_desc->read.olinfo_status = 0; 6245 6246 dma += IGB_MAX_DATA_PER_TXD; 6247 size -= IGB_MAX_DATA_PER_TXD; 6248 6249 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6250 } 6251 6252 if (likely(!data_len)) 6253 break; 6254 6255 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6256 6257 i++; 6258 tx_desc++; 6259 if (i == tx_ring->count) { 6260 tx_desc = IGB_TX_DESC(tx_ring, 0); 6261 i = 0; 6262 } 6263 tx_desc->read.olinfo_status = 0; 6264 6265 size = skb_frag_size(frag); 6266 data_len -= size; 6267 6268 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6269 size, DMA_TO_DEVICE); 6270 6271 tx_buffer = &tx_ring->tx_buffer_info[i]; 6272 } 6273 6274 /* write last descriptor with RS and EOP bits */ 6275 cmd_type |= size | IGB_TXD_DCMD; 6276 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6277 6278 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6279 6280 /* set the timestamp */ 6281 first->time_stamp = jiffies; 6282 6283 skb_tx_timestamp(skb); 6284 6285 /* Force memory writes to complete before letting h/w know there 6286 * are new descriptors to fetch. (Only applicable for weak-ordered 6287 * memory model archs, such as IA-64). 6288 * 6289 * We also need this memory barrier to make certain all of the 6290 * status bits have been updated before next_to_watch is written. 6291 */ 6292 dma_wmb(); 6293 6294 /* set next_to_watch value indicating a packet is present */ 6295 first->next_to_watch = tx_desc; 6296 6297 i++; 6298 if (i == tx_ring->count) 6299 i = 0; 6300 6301 tx_ring->next_to_use = i; 6302 6303 /* Make sure there is space in the ring for the next send. */ 6304 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6305 6306 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6307 writel(i, tx_ring->tail); 6308 } 6309 return 0; 6310 6311 dma_error: 6312 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6313 tx_buffer = &tx_ring->tx_buffer_info[i]; 6314 6315 /* clear dma mappings for failed tx_buffer_info map */ 6316 while (tx_buffer != first) { 6317 if (dma_unmap_len(tx_buffer, len)) 6318 dma_unmap_page(tx_ring->dev, 6319 dma_unmap_addr(tx_buffer, dma), 6320 dma_unmap_len(tx_buffer, len), 6321 DMA_TO_DEVICE); 6322 dma_unmap_len_set(tx_buffer, len, 0); 6323 6324 if (i-- == 0) 6325 i += tx_ring->count; 6326 tx_buffer = &tx_ring->tx_buffer_info[i]; 6327 } 6328 6329 if (dma_unmap_len(tx_buffer, len)) 6330 dma_unmap_single(tx_ring->dev, 6331 dma_unmap_addr(tx_buffer, dma), 6332 dma_unmap_len(tx_buffer, len), 6333 DMA_TO_DEVICE); 6334 dma_unmap_len_set(tx_buffer, len, 0); 6335 6336 dev_kfree_skb_any(tx_buffer->skb); 6337 tx_buffer->skb = NULL; 6338 6339 tx_ring->next_to_use = i; 6340 6341 return -1; 6342 } 6343 6344 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6345 struct igb_ring *tx_ring, 6346 struct xdp_frame *xdpf) 6347 { 6348 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6349 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6350 u16 count, i, index = tx_ring->next_to_use; 6351 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6352 struct igb_tx_buffer *tx_buffer = tx_head; 6353 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6354 u32 len = xdpf->len, cmd_type, olinfo_status; 6355 void *data = xdpf->data; 6356 6357 count = TXD_USE_COUNT(len); 6358 for (i = 0; i < nr_frags; i++) 6359 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6360 6361 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6362 return IGB_XDP_CONSUMED; 6363 6364 i = 0; 6365 /* record the location of the first descriptor for this packet */ 6366 tx_head->bytecount = xdp_get_frame_len(xdpf); 6367 tx_head->type = IGB_TYPE_XDP; 6368 tx_head->gso_segs = 1; 6369 tx_head->xdpf = xdpf; 6370 6371 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6372 /* 82575 requires a unique index per ring */ 6373 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6374 olinfo_status |= tx_ring->reg_idx << 4; 6375 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6376 6377 for (;;) { 6378 dma_addr_t dma; 6379 6380 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6381 if (dma_mapping_error(tx_ring->dev, dma)) 6382 goto unmap; 6383 6384 /* record length, and DMA address */ 6385 dma_unmap_len_set(tx_buffer, len, len); 6386 dma_unmap_addr_set(tx_buffer, dma, dma); 6387 6388 /* put descriptor type bits */ 6389 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6390 E1000_ADVTXD_DCMD_IFCS | len; 6391 6392 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6393 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6394 6395 tx_buffer->protocol = 0; 6396 6397 if (++index == tx_ring->count) 6398 index = 0; 6399 6400 if (i == nr_frags) 6401 break; 6402 6403 tx_buffer = &tx_ring->tx_buffer_info[index]; 6404 tx_desc = IGB_TX_DESC(tx_ring, index); 6405 tx_desc->read.olinfo_status = 0; 6406 6407 data = skb_frag_address(&sinfo->frags[i]); 6408 len = skb_frag_size(&sinfo->frags[i]); 6409 i++; 6410 } 6411 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6412 6413 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6414 /* set the timestamp */ 6415 tx_head->time_stamp = jiffies; 6416 6417 /* Avoid any potential race with xdp_xmit and cleanup */ 6418 smp_wmb(); 6419 6420 /* set next_to_watch value indicating a packet is present */ 6421 tx_head->next_to_watch = tx_desc; 6422 tx_ring->next_to_use = index; 6423 6424 /* Make sure there is space in the ring for the next send. */ 6425 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6426 6427 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6428 writel(index, tx_ring->tail); 6429 6430 return IGB_XDP_TX; 6431 6432 unmap: 6433 for (;;) { 6434 tx_buffer = &tx_ring->tx_buffer_info[index]; 6435 if (dma_unmap_len(tx_buffer, len)) 6436 dma_unmap_page(tx_ring->dev, 6437 dma_unmap_addr(tx_buffer, dma), 6438 dma_unmap_len(tx_buffer, len), 6439 DMA_TO_DEVICE); 6440 dma_unmap_len_set(tx_buffer, len, 0); 6441 if (tx_buffer == tx_head) 6442 break; 6443 6444 if (!index) 6445 index += tx_ring->count; 6446 index--; 6447 } 6448 6449 return IGB_XDP_CONSUMED; 6450 } 6451 6452 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6453 struct igb_ring *tx_ring) 6454 { 6455 struct igb_tx_buffer *first; 6456 int tso; 6457 u32 tx_flags = 0; 6458 unsigned short f; 6459 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6460 __be16 protocol = vlan_get_protocol(skb); 6461 u8 hdr_len = 0; 6462 6463 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6464 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6465 * + 2 desc gap to keep tail from touching head, 6466 * + 1 desc for context descriptor, 6467 * otherwise try next time 6468 */ 6469 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6470 count += TXD_USE_COUNT(skb_frag_size( 6471 &skb_shinfo(skb)->frags[f])); 6472 6473 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6474 /* this is a hard error */ 6475 return NETDEV_TX_BUSY; 6476 } 6477 6478 /* record the location of the first descriptor for this packet */ 6479 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6480 first->type = IGB_TYPE_SKB; 6481 first->skb = skb; 6482 first->bytecount = skb->len; 6483 first->gso_segs = 1; 6484 6485 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6486 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6487 6488 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6489 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6490 &adapter->state)) { 6491 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6492 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6493 6494 adapter->ptp_tx_skb = skb_get(skb); 6495 adapter->ptp_tx_start = jiffies; 6496 if (adapter->hw.mac.type == e1000_82576) 6497 schedule_work(&adapter->ptp_tx_work); 6498 } else { 6499 adapter->tx_hwtstamp_skipped++; 6500 } 6501 } 6502 6503 if (skb_vlan_tag_present(skb)) { 6504 tx_flags |= IGB_TX_FLAGS_VLAN; 6505 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6506 } 6507 6508 /* record initial flags and protocol */ 6509 first->tx_flags = tx_flags; 6510 first->protocol = protocol; 6511 6512 tso = igb_tso(tx_ring, first, &hdr_len); 6513 if (tso < 0) 6514 goto out_drop; 6515 else if (!tso) 6516 igb_tx_csum(tx_ring, first); 6517 6518 if (igb_tx_map(tx_ring, first, hdr_len)) 6519 goto cleanup_tx_tstamp; 6520 6521 return NETDEV_TX_OK; 6522 6523 out_drop: 6524 dev_kfree_skb_any(first->skb); 6525 first->skb = NULL; 6526 cleanup_tx_tstamp: 6527 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6528 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6529 6530 dev_kfree_skb_any(adapter->ptp_tx_skb); 6531 adapter->ptp_tx_skb = NULL; 6532 if (adapter->hw.mac.type == e1000_82576) 6533 cancel_work_sync(&adapter->ptp_tx_work); 6534 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6535 } 6536 6537 return NETDEV_TX_OK; 6538 } 6539 6540 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6541 struct sk_buff *skb) 6542 { 6543 unsigned int r_idx = skb->queue_mapping; 6544 6545 if (r_idx >= adapter->num_tx_queues) 6546 r_idx = r_idx % adapter->num_tx_queues; 6547 6548 return adapter->tx_ring[r_idx]; 6549 } 6550 6551 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6552 struct net_device *netdev) 6553 { 6554 struct igb_adapter *adapter = netdev_priv(netdev); 6555 6556 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6557 * in order to meet this minimum size requirement. 6558 */ 6559 if (skb_put_padto(skb, 17)) 6560 return NETDEV_TX_OK; 6561 6562 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6563 } 6564 6565 /** 6566 * igb_tx_timeout - Respond to a Tx Hang 6567 * @netdev: network interface device structure 6568 * @txqueue: number of the Tx queue that hung (unused) 6569 **/ 6570 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6571 { 6572 struct igb_adapter *adapter = netdev_priv(netdev); 6573 struct e1000_hw *hw = &adapter->hw; 6574 6575 /* Do the reset outside of interrupt context */ 6576 adapter->tx_timeout_count++; 6577 6578 if (hw->mac.type >= e1000_82580) 6579 hw->dev_spec._82575.global_device_reset = true; 6580 6581 schedule_work(&adapter->reset_task); 6582 wr32(E1000_EICS, 6583 (adapter->eims_enable_mask & ~adapter->eims_other)); 6584 } 6585 6586 static void igb_reset_task(struct work_struct *work) 6587 { 6588 struct igb_adapter *adapter; 6589 adapter = container_of(work, struct igb_adapter, reset_task); 6590 6591 rtnl_lock(); 6592 /* If we're already down or resetting, just bail */ 6593 if (test_bit(__IGB_DOWN, &adapter->state) || 6594 test_bit(__IGB_RESETTING, &adapter->state)) { 6595 rtnl_unlock(); 6596 return; 6597 } 6598 6599 igb_dump(adapter); 6600 netdev_err(adapter->netdev, "Reset adapter\n"); 6601 igb_reinit_locked(adapter); 6602 rtnl_unlock(); 6603 } 6604 6605 /** 6606 * igb_get_stats64 - Get System Network Statistics 6607 * @netdev: network interface device structure 6608 * @stats: rtnl_link_stats64 pointer 6609 **/ 6610 static void igb_get_stats64(struct net_device *netdev, 6611 struct rtnl_link_stats64 *stats) 6612 { 6613 struct igb_adapter *adapter = netdev_priv(netdev); 6614 6615 spin_lock(&adapter->stats64_lock); 6616 igb_update_stats(adapter); 6617 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6618 spin_unlock(&adapter->stats64_lock); 6619 } 6620 6621 /** 6622 * igb_change_mtu - Change the Maximum Transfer Unit 6623 * @netdev: network interface device structure 6624 * @new_mtu: new value for maximum frame size 6625 * 6626 * Returns 0 on success, negative on failure 6627 **/ 6628 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6629 { 6630 struct igb_adapter *adapter = netdev_priv(netdev); 6631 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6632 6633 if (adapter->xdp_prog) { 6634 int i; 6635 6636 for (i = 0; i < adapter->num_rx_queues; i++) { 6637 struct igb_ring *ring = adapter->rx_ring[i]; 6638 6639 if (max_frame > igb_rx_bufsz(ring)) { 6640 netdev_warn(adapter->netdev, 6641 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6642 max_frame); 6643 return -EINVAL; 6644 } 6645 } 6646 } 6647 6648 /* adjust max frame to be at least the size of a standard frame */ 6649 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6650 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6651 6652 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6653 usleep_range(1000, 2000); 6654 6655 /* igb_down has a dependency on max_frame_size */ 6656 adapter->max_frame_size = max_frame; 6657 6658 if (netif_running(netdev)) 6659 igb_down(adapter); 6660 6661 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6662 netdev->mtu, new_mtu); 6663 netdev->mtu = new_mtu; 6664 6665 if (netif_running(netdev)) 6666 igb_up(adapter); 6667 else 6668 igb_reset(adapter); 6669 6670 clear_bit(__IGB_RESETTING, &adapter->state); 6671 6672 return 0; 6673 } 6674 6675 /** 6676 * igb_update_stats - Update the board statistics counters 6677 * @adapter: board private structure 6678 **/ 6679 void igb_update_stats(struct igb_adapter *adapter) 6680 { 6681 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6682 struct e1000_hw *hw = &adapter->hw; 6683 struct pci_dev *pdev = adapter->pdev; 6684 u32 reg, mpc; 6685 int i; 6686 u64 bytes, packets; 6687 unsigned int start; 6688 u64 _bytes, _packets; 6689 6690 /* Prevent stats update while adapter is being reset, or if the pci 6691 * connection is down. 6692 */ 6693 if (adapter->link_speed == 0) 6694 return; 6695 if (pci_channel_offline(pdev)) 6696 return; 6697 6698 bytes = 0; 6699 packets = 0; 6700 6701 rcu_read_lock(); 6702 for (i = 0; i < adapter->num_rx_queues; i++) { 6703 struct igb_ring *ring = adapter->rx_ring[i]; 6704 u32 rqdpc = rd32(E1000_RQDPC(i)); 6705 if (hw->mac.type >= e1000_i210) 6706 wr32(E1000_RQDPC(i), 0); 6707 6708 if (rqdpc) { 6709 ring->rx_stats.drops += rqdpc; 6710 net_stats->rx_fifo_errors += rqdpc; 6711 } 6712 6713 do { 6714 start = u64_stats_fetch_begin(&ring->rx_syncp); 6715 _bytes = ring->rx_stats.bytes; 6716 _packets = ring->rx_stats.packets; 6717 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6718 bytes += _bytes; 6719 packets += _packets; 6720 } 6721 6722 net_stats->rx_bytes = bytes; 6723 net_stats->rx_packets = packets; 6724 6725 bytes = 0; 6726 packets = 0; 6727 for (i = 0; i < adapter->num_tx_queues; i++) { 6728 struct igb_ring *ring = adapter->tx_ring[i]; 6729 do { 6730 start = u64_stats_fetch_begin(&ring->tx_syncp); 6731 _bytes = ring->tx_stats.bytes; 6732 _packets = ring->tx_stats.packets; 6733 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6734 bytes += _bytes; 6735 packets += _packets; 6736 } 6737 net_stats->tx_bytes = bytes; 6738 net_stats->tx_packets = packets; 6739 rcu_read_unlock(); 6740 6741 /* read stats registers */ 6742 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6743 adapter->stats.gprc += rd32(E1000_GPRC); 6744 adapter->stats.gorc += rd32(E1000_GORCL); 6745 rd32(E1000_GORCH); /* clear GORCL */ 6746 adapter->stats.bprc += rd32(E1000_BPRC); 6747 adapter->stats.mprc += rd32(E1000_MPRC); 6748 adapter->stats.roc += rd32(E1000_ROC); 6749 6750 adapter->stats.prc64 += rd32(E1000_PRC64); 6751 adapter->stats.prc127 += rd32(E1000_PRC127); 6752 adapter->stats.prc255 += rd32(E1000_PRC255); 6753 adapter->stats.prc511 += rd32(E1000_PRC511); 6754 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6755 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6756 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6757 adapter->stats.sec += rd32(E1000_SEC); 6758 6759 mpc = rd32(E1000_MPC); 6760 adapter->stats.mpc += mpc; 6761 net_stats->rx_fifo_errors += mpc; 6762 adapter->stats.scc += rd32(E1000_SCC); 6763 adapter->stats.ecol += rd32(E1000_ECOL); 6764 adapter->stats.mcc += rd32(E1000_MCC); 6765 adapter->stats.latecol += rd32(E1000_LATECOL); 6766 adapter->stats.dc += rd32(E1000_DC); 6767 adapter->stats.rlec += rd32(E1000_RLEC); 6768 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6769 adapter->stats.xontxc += rd32(E1000_XONTXC); 6770 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6771 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6772 adapter->stats.fcruc += rd32(E1000_FCRUC); 6773 adapter->stats.gptc += rd32(E1000_GPTC); 6774 adapter->stats.gotc += rd32(E1000_GOTCL); 6775 rd32(E1000_GOTCH); /* clear GOTCL */ 6776 adapter->stats.rnbc += rd32(E1000_RNBC); 6777 adapter->stats.ruc += rd32(E1000_RUC); 6778 adapter->stats.rfc += rd32(E1000_RFC); 6779 adapter->stats.rjc += rd32(E1000_RJC); 6780 adapter->stats.tor += rd32(E1000_TORH); 6781 adapter->stats.tot += rd32(E1000_TOTH); 6782 adapter->stats.tpr += rd32(E1000_TPR); 6783 6784 adapter->stats.ptc64 += rd32(E1000_PTC64); 6785 adapter->stats.ptc127 += rd32(E1000_PTC127); 6786 adapter->stats.ptc255 += rd32(E1000_PTC255); 6787 adapter->stats.ptc511 += rd32(E1000_PTC511); 6788 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6789 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6790 6791 adapter->stats.mptc += rd32(E1000_MPTC); 6792 adapter->stats.bptc += rd32(E1000_BPTC); 6793 6794 adapter->stats.tpt += rd32(E1000_TPT); 6795 adapter->stats.colc += rd32(E1000_COLC); 6796 6797 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6798 /* read internal phy specific stats */ 6799 reg = rd32(E1000_CTRL_EXT); 6800 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6801 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6802 6803 /* this stat has invalid values on i210/i211 */ 6804 if ((hw->mac.type != e1000_i210) && 6805 (hw->mac.type != e1000_i211)) 6806 adapter->stats.tncrs += rd32(E1000_TNCRS); 6807 } 6808 6809 adapter->stats.tsctc += rd32(E1000_TSCTC); 6810 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6811 6812 adapter->stats.iac += rd32(E1000_IAC); 6813 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6814 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6815 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6816 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6817 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6818 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6819 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6820 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6821 6822 /* Fill out the OS statistics structure */ 6823 net_stats->multicast = adapter->stats.mprc; 6824 net_stats->collisions = adapter->stats.colc; 6825 6826 /* Rx Errors */ 6827 6828 /* RLEC on some newer hardware can be incorrect so build 6829 * our own version based on RUC and ROC 6830 */ 6831 net_stats->rx_errors = adapter->stats.rxerrc + 6832 adapter->stats.crcerrs + adapter->stats.algnerrc + 6833 adapter->stats.ruc + adapter->stats.roc + 6834 adapter->stats.cexterr; 6835 net_stats->rx_length_errors = adapter->stats.ruc + 6836 adapter->stats.roc; 6837 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6838 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6839 net_stats->rx_missed_errors = adapter->stats.mpc; 6840 6841 /* Tx Errors */ 6842 net_stats->tx_errors = adapter->stats.ecol + 6843 adapter->stats.latecol; 6844 net_stats->tx_aborted_errors = adapter->stats.ecol; 6845 net_stats->tx_window_errors = adapter->stats.latecol; 6846 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6847 6848 /* Tx Dropped needs to be maintained elsewhere */ 6849 6850 /* Management Stats */ 6851 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6852 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6853 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6854 6855 /* OS2BMC Stats */ 6856 reg = rd32(E1000_MANC); 6857 if (reg & E1000_MANC_EN_BMC2OS) { 6858 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6859 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6860 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6861 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6862 } 6863 } 6864 6865 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6866 { 6867 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6868 struct e1000_hw *hw = &adapter->hw; 6869 struct timespec64 ts; 6870 u32 tsauxc; 6871 6872 if (pin < 0 || pin >= IGB_N_SDP) 6873 return; 6874 6875 spin_lock(&adapter->tmreg_lock); 6876 6877 if (hw->mac.type == e1000_82580 || 6878 hw->mac.type == e1000_i354 || 6879 hw->mac.type == e1000_i350) { 6880 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6881 u32 systiml, systimh, level_mask, level, rem; 6882 u64 systim, now; 6883 6884 /* read systim registers in sequence */ 6885 rd32(E1000_SYSTIMR); 6886 systiml = rd32(E1000_SYSTIML); 6887 systimh = rd32(E1000_SYSTIMH); 6888 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6889 now = timecounter_cyc2time(&adapter->tc, systim); 6890 6891 if (pin < 2) { 6892 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6893 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6894 } else { 6895 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6896 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6897 } 6898 6899 div_u64_rem(now, ns, &rem); 6900 systim = systim + (ns - rem); 6901 6902 /* synchronize pin level with rising/falling edges */ 6903 div_u64_rem(now, ns << 1, &rem); 6904 if (rem < ns) { 6905 /* first half of period */ 6906 if (level == 0) { 6907 /* output is already low, skip this period */ 6908 systim += ns; 6909 pr_notice("igb: periodic output on %s missed falling edge\n", 6910 adapter->sdp_config[pin].name); 6911 } 6912 } else { 6913 /* second half of period */ 6914 if (level == 1) { 6915 /* output is already high, skip this period */ 6916 systim += ns; 6917 pr_notice("igb: periodic output on %s missed rising edge\n", 6918 adapter->sdp_config[pin].name); 6919 } 6920 } 6921 6922 /* for this chip family tv_sec is the upper part of the binary value, 6923 * so not seconds 6924 */ 6925 ts.tv_nsec = (u32)systim; 6926 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 6927 } else { 6928 ts = timespec64_add(adapter->perout[tsintr_tt].start, 6929 adapter->perout[tsintr_tt].period); 6930 } 6931 6932 /* u32 conversion of tv_sec is safe until y2106 */ 6933 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 6934 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 6935 tsauxc = rd32(E1000_TSAUXC); 6936 tsauxc |= TSAUXC_EN_TT0; 6937 wr32(E1000_TSAUXC, tsauxc); 6938 adapter->perout[tsintr_tt].start = ts; 6939 6940 spin_unlock(&adapter->tmreg_lock); 6941 } 6942 6943 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 6944 { 6945 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 6946 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 6947 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 6948 struct e1000_hw *hw = &adapter->hw; 6949 struct ptp_clock_event event; 6950 struct timespec64 ts; 6951 6952 if (pin < 0 || pin >= IGB_N_SDP) 6953 return; 6954 6955 if (hw->mac.type == e1000_82580 || 6956 hw->mac.type == e1000_i354 || 6957 hw->mac.type == e1000_i350) { 6958 s64 ns = rd32(auxstmpl); 6959 6960 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32; 6961 ts = ns_to_timespec64(ns); 6962 } else { 6963 ts.tv_nsec = rd32(auxstmpl); 6964 ts.tv_sec = rd32(auxstmph); 6965 } 6966 6967 event.type = PTP_CLOCK_EXTTS; 6968 event.index = tsintr_tt; 6969 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 6970 ptp_clock_event(adapter->ptp_clock, &event); 6971 } 6972 6973 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6974 { 6975 struct e1000_hw *hw = &adapter->hw; 6976 u32 ack = 0, tsicr = rd32(E1000_TSICR); 6977 struct ptp_clock_event event; 6978 6979 if (tsicr & TSINTR_SYS_WRAP) { 6980 event.type = PTP_CLOCK_PPS; 6981 if (adapter->ptp_caps.pps) 6982 ptp_clock_event(adapter->ptp_clock, &event); 6983 ack |= TSINTR_SYS_WRAP; 6984 } 6985 6986 if (tsicr & E1000_TSICR_TXTS) { 6987 /* retrieve hardware timestamp */ 6988 schedule_work(&adapter->ptp_tx_work); 6989 ack |= E1000_TSICR_TXTS; 6990 } 6991 6992 if (tsicr & TSINTR_TT0) { 6993 igb_perout(adapter, 0); 6994 ack |= TSINTR_TT0; 6995 } 6996 6997 if (tsicr & TSINTR_TT1) { 6998 igb_perout(adapter, 1); 6999 ack |= TSINTR_TT1; 7000 } 7001 7002 if (tsicr & TSINTR_AUTT0) { 7003 igb_extts(adapter, 0); 7004 ack |= TSINTR_AUTT0; 7005 } 7006 7007 if (tsicr & TSINTR_AUTT1) { 7008 igb_extts(adapter, 1); 7009 ack |= TSINTR_AUTT1; 7010 } 7011 7012 /* acknowledge the interrupts */ 7013 wr32(E1000_TSICR, ack); 7014 } 7015 7016 static irqreturn_t igb_msix_other(int irq, void *data) 7017 { 7018 struct igb_adapter *adapter = data; 7019 struct e1000_hw *hw = &adapter->hw; 7020 u32 icr = rd32(E1000_ICR); 7021 /* reading ICR causes bit 31 of EICR to be cleared */ 7022 7023 if (icr & E1000_ICR_DRSTA) 7024 schedule_work(&adapter->reset_task); 7025 7026 if (icr & E1000_ICR_DOUTSYNC) { 7027 /* HW is reporting DMA is out of sync */ 7028 adapter->stats.doosync++; 7029 /* The DMA Out of Sync is also indication of a spoof event 7030 * in IOV mode. Check the Wrong VM Behavior register to 7031 * see if it is really a spoof event. 7032 */ 7033 igb_check_wvbr(adapter); 7034 } 7035 7036 /* Check for a mailbox event */ 7037 if (icr & E1000_ICR_VMMB) 7038 igb_msg_task(adapter); 7039 7040 if (icr & E1000_ICR_LSC) { 7041 hw->mac.get_link_status = 1; 7042 /* guard against interrupt when we're going down */ 7043 if (!test_bit(__IGB_DOWN, &adapter->state)) 7044 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7045 } 7046 7047 if (icr & E1000_ICR_TS) 7048 igb_tsync_interrupt(adapter); 7049 7050 wr32(E1000_EIMS, adapter->eims_other); 7051 7052 return IRQ_HANDLED; 7053 } 7054 7055 static void igb_write_itr(struct igb_q_vector *q_vector) 7056 { 7057 struct igb_adapter *adapter = q_vector->adapter; 7058 u32 itr_val = q_vector->itr_val & 0x7FFC; 7059 7060 if (!q_vector->set_itr) 7061 return; 7062 7063 if (!itr_val) 7064 itr_val = 0x4; 7065 7066 if (adapter->hw.mac.type == e1000_82575) 7067 itr_val |= itr_val << 16; 7068 else 7069 itr_val |= E1000_EITR_CNT_IGNR; 7070 7071 writel(itr_val, q_vector->itr_register); 7072 q_vector->set_itr = 0; 7073 } 7074 7075 static irqreturn_t igb_msix_ring(int irq, void *data) 7076 { 7077 struct igb_q_vector *q_vector = data; 7078 7079 /* Write the ITR value calculated from the previous interrupt. */ 7080 igb_write_itr(q_vector); 7081 7082 napi_schedule(&q_vector->napi); 7083 7084 return IRQ_HANDLED; 7085 } 7086 7087 #ifdef CONFIG_IGB_DCA 7088 static void igb_update_tx_dca(struct igb_adapter *adapter, 7089 struct igb_ring *tx_ring, 7090 int cpu) 7091 { 7092 struct e1000_hw *hw = &adapter->hw; 7093 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7094 7095 if (hw->mac.type != e1000_82575) 7096 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7097 7098 /* We can enable relaxed ordering for reads, but not writes when 7099 * DCA is enabled. This is due to a known issue in some chipsets 7100 * which will cause the DCA tag to be cleared. 7101 */ 7102 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7103 E1000_DCA_TXCTRL_DATA_RRO_EN | 7104 E1000_DCA_TXCTRL_DESC_DCA_EN; 7105 7106 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7107 } 7108 7109 static void igb_update_rx_dca(struct igb_adapter *adapter, 7110 struct igb_ring *rx_ring, 7111 int cpu) 7112 { 7113 struct e1000_hw *hw = &adapter->hw; 7114 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7115 7116 if (hw->mac.type != e1000_82575) 7117 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7118 7119 /* We can enable relaxed ordering for reads, but not writes when 7120 * DCA is enabled. This is due to a known issue in some chipsets 7121 * which will cause the DCA tag to be cleared. 7122 */ 7123 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7124 E1000_DCA_RXCTRL_DESC_DCA_EN; 7125 7126 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7127 } 7128 7129 static void igb_update_dca(struct igb_q_vector *q_vector) 7130 { 7131 struct igb_adapter *adapter = q_vector->adapter; 7132 int cpu = get_cpu(); 7133 7134 if (q_vector->cpu == cpu) 7135 goto out_no_update; 7136 7137 if (q_vector->tx.ring) 7138 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7139 7140 if (q_vector->rx.ring) 7141 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7142 7143 q_vector->cpu = cpu; 7144 out_no_update: 7145 put_cpu(); 7146 } 7147 7148 static void igb_setup_dca(struct igb_adapter *adapter) 7149 { 7150 struct e1000_hw *hw = &adapter->hw; 7151 int i; 7152 7153 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7154 return; 7155 7156 /* Always use CB2 mode, difference is masked in the CB driver. */ 7157 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7158 7159 for (i = 0; i < adapter->num_q_vectors; i++) { 7160 adapter->q_vector[i]->cpu = -1; 7161 igb_update_dca(adapter->q_vector[i]); 7162 } 7163 } 7164 7165 static int __igb_notify_dca(struct device *dev, void *data) 7166 { 7167 struct net_device *netdev = dev_get_drvdata(dev); 7168 struct igb_adapter *adapter = netdev_priv(netdev); 7169 struct pci_dev *pdev = adapter->pdev; 7170 struct e1000_hw *hw = &adapter->hw; 7171 unsigned long event = *(unsigned long *)data; 7172 7173 switch (event) { 7174 case DCA_PROVIDER_ADD: 7175 /* if already enabled, don't do it again */ 7176 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7177 break; 7178 if (dca_add_requester(dev) == 0) { 7179 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7180 dev_info(&pdev->dev, "DCA enabled\n"); 7181 igb_setup_dca(adapter); 7182 break; 7183 } 7184 fallthrough; /* since DCA is disabled. */ 7185 case DCA_PROVIDER_REMOVE: 7186 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7187 /* without this a class_device is left 7188 * hanging around in the sysfs model 7189 */ 7190 dca_remove_requester(dev); 7191 dev_info(&pdev->dev, "DCA disabled\n"); 7192 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7193 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7194 } 7195 break; 7196 } 7197 7198 return 0; 7199 } 7200 7201 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7202 void *p) 7203 { 7204 int ret_val; 7205 7206 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7207 __igb_notify_dca); 7208 7209 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7210 } 7211 #endif /* CONFIG_IGB_DCA */ 7212 7213 #ifdef CONFIG_PCI_IOV 7214 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7215 { 7216 unsigned char mac_addr[ETH_ALEN]; 7217 7218 eth_zero_addr(mac_addr); 7219 igb_set_vf_mac(adapter, vf, mac_addr); 7220 7221 /* By default spoof check is enabled for all VFs */ 7222 adapter->vf_data[vf].spoofchk_enabled = true; 7223 7224 /* By default VFs are not trusted */ 7225 adapter->vf_data[vf].trusted = false; 7226 7227 return 0; 7228 } 7229 7230 #endif 7231 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7232 { 7233 struct e1000_hw *hw = &adapter->hw; 7234 u32 ping; 7235 int i; 7236 7237 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7238 ping = E1000_PF_CONTROL_MSG; 7239 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7240 ping |= E1000_VT_MSGTYPE_CTS; 7241 igb_write_mbx(hw, &ping, 1, i); 7242 } 7243 } 7244 7245 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7246 { 7247 struct e1000_hw *hw = &adapter->hw; 7248 u32 vmolr = rd32(E1000_VMOLR(vf)); 7249 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7250 7251 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7252 IGB_VF_FLAG_MULTI_PROMISC); 7253 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7254 7255 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7256 vmolr |= E1000_VMOLR_MPME; 7257 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7258 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7259 } else { 7260 /* if we have hashes and we are clearing a multicast promisc 7261 * flag we need to write the hashes to the MTA as this step 7262 * was previously skipped 7263 */ 7264 if (vf_data->num_vf_mc_hashes > 30) { 7265 vmolr |= E1000_VMOLR_MPME; 7266 } else if (vf_data->num_vf_mc_hashes) { 7267 int j; 7268 7269 vmolr |= E1000_VMOLR_ROMPE; 7270 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7271 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7272 } 7273 } 7274 7275 wr32(E1000_VMOLR(vf), vmolr); 7276 7277 /* there are flags left unprocessed, likely not supported */ 7278 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7279 return -EINVAL; 7280 7281 return 0; 7282 } 7283 7284 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7285 u32 *msgbuf, u32 vf) 7286 { 7287 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7288 u16 *hash_list = (u16 *)&msgbuf[1]; 7289 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7290 int i; 7291 7292 /* salt away the number of multicast addresses assigned 7293 * to this VF for later use to restore when the PF multi cast 7294 * list changes 7295 */ 7296 vf_data->num_vf_mc_hashes = n; 7297 7298 /* only up to 30 hash values supported */ 7299 if (n > 30) 7300 n = 30; 7301 7302 /* store the hashes for later use */ 7303 for (i = 0; i < n; i++) 7304 vf_data->vf_mc_hashes[i] = hash_list[i]; 7305 7306 /* Flush and reset the mta with the new values */ 7307 igb_set_rx_mode(adapter->netdev); 7308 7309 return 0; 7310 } 7311 7312 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7313 { 7314 struct e1000_hw *hw = &adapter->hw; 7315 struct vf_data_storage *vf_data; 7316 int i, j; 7317 7318 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7319 u32 vmolr = rd32(E1000_VMOLR(i)); 7320 7321 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7322 7323 vf_data = &adapter->vf_data[i]; 7324 7325 if ((vf_data->num_vf_mc_hashes > 30) || 7326 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7327 vmolr |= E1000_VMOLR_MPME; 7328 } else if (vf_data->num_vf_mc_hashes) { 7329 vmolr |= E1000_VMOLR_ROMPE; 7330 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7331 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7332 } 7333 wr32(E1000_VMOLR(i), vmolr); 7334 } 7335 } 7336 7337 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7338 { 7339 struct e1000_hw *hw = &adapter->hw; 7340 u32 pool_mask, vlvf_mask, i; 7341 7342 /* create mask for VF and other pools */ 7343 pool_mask = E1000_VLVF_POOLSEL_MASK; 7344 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7345 7346 /* drop PF from pool bits */ 7347 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7348 adapter->vfs_allocated_count); 7349 7350 /* Find the vlan filter for this id */ 7351 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7352 u32 vlvf = rd32(E1000_VLVF(i)); 7353 u32 vfta_mask, vid, vfta; 7354 7355 /* remove the vf from the pool */ 7356 if (!(vlvf & vlvf_mask)) 7357 continue; 7358 7359 /* clear out bit from VLVF */ 7360 vlvf ^= vlvf_mask; 7361 7362 /* if other pools are present, just remove ourselves */ 7363 if (vlvf & pool_mask) 7364 goto update_vlvfb; 7365 7366 /* if PF is present, leave VFTA */ 7367 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7368 goto update_vlvf; 7369 7370 vid = vlvf & E1000_VLVF_VLANID_MASK; 7371 vfta_mask = BIT(vid % 32); 7372 7373 /* clear bit from VFTA */ 7374 vfta = adapter->shadow_vfta[vid / 32]; 7375 if (vfta & vfta_mask) 7376 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7377 update_vlvf: 7378 /* clear pool selection enable */ 7379 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7380 vlvf &= E1000_VLVF_POOLSEL_MASK; 7381 else 7382 vlvf = 0; 7383 update_vlvfb: 7384 /* clear pool bits */ 7385 wr32(E1000_VLVF(i), vlvf); 7386 } 7387 } 7388 7389 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7390 { 7391 u32 vlvf; 7392 int idx; 7393 7394 /* short cut the special case */ 7395 if (vlan == 0) 7396 return 0; 7397 7398 /* Search for the VLAN id in the VLVF entries */ 7399 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7400 vlvf = rd32(E1000_VLVF(idx)); 7401 if ((vlvf & VLAN_VID_MASK) == vlan) 7402 break; 7403 } 7404 7405 return idx; 7406 } 7407 7408 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7409 { 7410 struct e1000_hw *hw = &adapter->hw; 7411 u32 bits, pf_id; 7412 int idx; 7413 7414 idx = igb_find_vlvf_entry(hw, vid); 7415 if (!idx) 7416 return; 7417 7418 /* See if any other pools are set for this VLAN filter 7419 * entry other than the PF. 7420 */ 7421 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7422 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7423 bits &= rd32(E1000_VLVF(idx)); 7424 7425 /* Disable the filter so this falls into the default pool. */ 7426 if (!bits) { 7427 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7428 wr32(E1000_VLVF(idx), BIT(pf_id)); 7429 else 7430 wr32(E1000_VLVF(idx), 0); 7431 } 7432 } 7433 7434 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7435 bool add, u32 vf) 7436 { 7437 int pf_id = adapter->vfs_allocated_count; 7438 struct e1000_hw *hw = &adapter->hw; 7439 int err; 7440 7441 /* If VLAN overlaps with one the PF is currently monitoring make 7442 * sure that we are able to allocate a VLVF entry. This may be 7443 * redundant but it guarantees PF will maintain visibility to 7444 * the VLAN. 7445 */ 7446 if (add && test_bit(vid, adapter->active_vlans)) { 7447 err = igb_vfta_set(hw, vid, pf_id, true, false); 7448 if (err) 7449 return err; 7450 } 7451 7452 err = igb_vfta_set(hw, vid, vf, add, false); 7453 7454 if (add && !err) 7455 return err; 7456 7457 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7458 * we may need to drop the PF pool bit in order to allow us to free 7459 * up the VLVF resources. 7460 */ 7461 if (test_bit(vid, adapter->active_vlans) || 7462 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7463 igb_update_pf_vlvf(adapter, vid); 7464 7465 return err; 7466 } 7467 7468 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7469 { 7470 struct e1000_hw *hw = &adapter->hw; 7471 7472 if (vid) 7473 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7474 else 7475 wr32(E1000_VMVIR(vf), 0); 7476 } 7477 7478 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7479 u16 vlan, u8 qos) 7480 { 7481 int err; 7482 7483 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7484 if (err) 7485 return err; 7486 7487 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7488 igb_set_vmolr(adapter, vf, !vlan); 7489 7490 /* revoke access to previous VLAN */ 7491 if (vlan != adapter->vf_data[vf].pf_vlan) 7492 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7493 false, vf); 7494 7495 adapter->vf_data[vf].pf_vlan = vlan; 7496 adapter->vf_data[vf].pf_qos = qos; 7497 igb_set_vf_vlan_strip(adapter, vf, true); 7498 dev_info(&adapter->pdev->dev, 7499 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7500 if (test_bit(__IGB_DOWN, &adapter->state)) { 7501 dev_warn(&adapter->pdev->dev, 7502 "The VF VLAN has been set, but the PF device is not up.\n"); 7503 dev_warn(&adapter->pdev->dev, 7504 "Bring the PF device up before attempting to use the VF device.\n"); 7505 } 7506 7507 return err; 7508 } 7509 7510 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7511 { 7512 /* Restore tagless access via VLAN 0 */ 7513 igb_set_vf_vlan(adapter, 0, true, vf); 7514 7515 igb_set_vmvir(adapter, 0, vf); 7516 igb_set_vmolr(adapter, vf, true); 7517 7518 /* Remove any PF assigned VLAN */ 7519 if (adapter->vf_data[vf].pf_vlan) 7520 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7521 false, vf); 7522 7523 adapter->vf_data[vf].pf_vlan = 0; 7524 adapter->vf_data[vf].pf_qos = 0; 7525 igb_set_vf_vlan_strip(adapter, vf, false); 7526 7527 return 0; 7528 } 7529 7530 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7531 u16 vlan, u8 qos, __be16 vlan_proto) 7532 { 7533 struct igb_adapter *adapter = netdev_priv(netdev); 7534 7535 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7536 return -EINVAL; 7537 7538 if (vlan_proto != htons(ETH_P_8021Q)) 7539 return -EPROTONOSUPPORT; 7540 7541 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7542 igb_disable_port_vlan(adapter, vf); 7543 } 7544 7545 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7546 { 7547 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7548 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7549 int ret; 7550 7551 if (adapter->vf_data[vf].pf_vlan) 7552 return -1; 7553 7554 /* VLAN 0 is a special case, don't allow it to be removed */ 7555 if (!vid && !add) 7556 return 0; 7557 7558 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7559 if (!ret) 7560 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7561 return ret; 7562 } 7563 7564 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7565 { 7566 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7567 7568 /* clear flags - except flag that indicates PF has set the MAC */ 7569 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7570 vf_data->last_nack = jiffies; 7571 7572 /* reset vlans for device */ 7573 igb_clear_vf_vfta(adapter, vf); 7574 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7575 igb_set_vmvir(adapter, vf_data->pf_vlan | 7576 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7577 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7578 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7579 7580 /* reset multicast table array for vf */ 7581 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7582 7583 /* Flush and reset the mta with the new values */ 7584 igb_set_rx_mode(adapter->netdev); 7585 } 7586 7587 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7588 { 7589 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7590 7591 /* clear mac address as we were hotplug removed/added */ 7592 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7593 eth_zero_addr(vf_mac); 7594 7595 /* process remaining reset events */ 7596 igb_vf_reset(adapter, vf); 7597 } 7598 7599 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7600 { 7601 struct e1000_hw *hw = &adapter->hw; 7602 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7603 u32 reg, msgbuf[3] = {}; 7604 u8 *addr = (u8 *)(&msgbuf[1]); 7605 7606 /* process all the same items cleared in a function level reset */ 7607 igb_vf_reset(adapter, vf); 7608 7609 /* set vf mac address */ 7610 igb_set_vf_mac(adapter, vf, vf_mac); 7611 7612 /* enable transmit and receive for vf */ 7613 reg = rd32(E1000_VFTE); 7614 wr32(E1000_VFTE, reg | BIT(vf)); 7615 reg = rd32(E1000_VFRE); 7616 wr32(E1000_VFRE, reg | BIT(vf)); 7617 7618 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7619 7620 /* reply to reset with ack and vf mac address */ 7621 if (!is_zero_ether_addr(vf_mac)) { 7622 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7623 memcpy(addr, vf_mac, ETH_ALEN); 7624 } else { 7625 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7626 } 7627 igb_write_mbx(hw, msgbuf, 3, vf); 7628 } 7629 7630 static void igb_flush_mac_table(struct igb_adapter *adapter) 7631 { 7632 struct e1000_hw *hw = &adapter->hw; 7633 int i; 7634 7635 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7636 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7637 eth_zero_addr(adapter->mac_table[i].addr); 7638 adapter->mac_table[i].queue = 0; 7639 igb_rar_set_index(adapter, i); 7640 } 7641 } 7642 7643 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7644 { 7645 struct e1000_hw *hw = &adapter->hw; 7646 /* do not count rar entries reserved for VFs MAC addresses */ 7647 int rar_entries = hw->mac.rar_entry_count - 7648 adapter->vfs_allocated_count; 7649 int i, count = 0; 7650 7651 for (i = 0; i < rar_entries; i++) { 7652 /* do not count default entries */ 7653 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7654 continue; 7655 7656 /* do not count "in use" entries for different queues */ 7657 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7658 (adapter->mac_table[i].queue != queue)) 7659 continue; 7660 7661 count++; 7662 } 7663 7664 return count; 7665 } 7666 7667 /* Set default MAC address for the PF in the first RAR entry */ 7668 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7669 { 7670 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7671 7672 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7673 mac_table->queue = adapter->vfs_allocated_count; 7674 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7675 7676 igb_rar_set_index(adapter, 0); 7677 } 7678 7679 /* If the filter to be added and an already existing filter express 7680 * the same address and address type, it should be possible to only 7681 * override the other configurations, for example the queue to steer 7682 * traffic. 7683 */ 7684 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7685 const u8 *addr, const u8 flags) 7686 { 7687 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7688 return true; 7689 7690 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7691 (flags & IGB_MAC_STATE_SRC_ADDR)) 7692 return false; 7693 7694 if (!ether_addr_equal(addr, entry->addr)) 7695 return false; 7696 7697 return true; 7698 } 7699 7700 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7701 * 'flags' is used to indicate what kind of match is made, match is by 7702 * default for the destination address, if matching by source address 7703 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7704 */ 7705 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7706 const u8 *addr, const u8 queue, 7707 const u8 flags) 7708 { 7709 struct e1000_hw *hw = &adapter->hw; 7710 int rar_entries = hw->mac.rar_entry_count - 7711 adapter->vfs_allocated_count; 7712 int i; 7713 7714 if (is_zero_ether_addr(addr)) 7715 return -EINVAL; 7716 7717 /* Search for the first empty entry in the MAC table. 7718 * Do not touch entries at the end of the table reserved for the VF MAC 7719 * addresses. 7720 */ 7721 for (i = 0; i < rar_entries; i++) { 7722 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7723 addr, flags)) 7724 continue; 7725 7726 ether_addr_copy(adapter->mac_table[i].addr, addr); 7727 adapter->mac_table[i].queue = queue; 7728 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7729 7730 igb_rar_set_index(adapter, i); 7731 return i; 7732 } 7733 7734 return -ENOSPC; 7735 } 7736 7737 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7738 const u8 queue) 7739 { 7740 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7741 } 7742 7743 /* Remove a MAC filter for 'addr' directing matching traffic to 7744 * 'queue', 'flags' is used to indicate what kind of match need to be 7745 * removed, match is by default for the destination address, if 7746 * matching by source address is to be removed the flag 7747 * IGB_MAC_STATE_SRC_ADDR can be used. 7748 */ 7749 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7750 const u8 *addr, const u8 queue, 7751 const u8 flags) 7752 { 7753 struct e1000_hw *hw = &adapter->hw; 7754 int rar_entries = hw->mac.rar_entry_count - 7755 adapter->vfs_allocated_count; 7756 int i; 7757 7758 if (is_zero_ether_addr(addr)) 7759 return -EINVAL; 7760 7761 /* Search for matching entry in the MAC table based on given address 7762 * and queue. Do not touch entries at the end of the table reserved 7763 * for the VF MAC addresses. 7764 */ 7765 for (i = 0; i < rar_entries; i++) { 7766 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7767 continue; 7768 if ((adapter->mac_table[i].state & flags) != flags) 7769 continue; 7770 if (adapter->mac_table[i].queue != queue) 7771 continue; 7772 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7773 continue; 7774 7775 /* When a filter for the default address is "deleted", 7776 * we return it to its initial configuration 7777 */ 7778 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7779 adapter->mac_table[i].state = 7780 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7781 adapter->mac_table[i].queue = 7782 adapter->vfs_allocated_count; 7783 } else { 7784 adapter->mac_table[i].state = 0; 7785 adapter->mac_table[i].queue = 0; 7786 eth_zero_addr(adapter->mac_table[i].addr); 7787 } 7788 7789 igb_rar_set_index(adapter, i); 7790 return 0; 7791 } 7792 7793 return -ENOENT; 7794 } 7795 7796 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7797 const u8 queue) 7798 { 7799 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7800 } 7801 7802 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7803 const u8 *addr, u8 queue, u8 flags) 7804 { 7805 struct e1000_hw *hw = &adapter->hw; 7806 7807 /* In theory, this should be supported on 82575 as well, but 7808 * that part wasn't easily accessible during development. 7809 */ 7810 if (hw->mac.type != e1000_i210) 7811 return -EOPNOTSUPP; 7812 7813 return igb_add_mac_filter_flags(adapter, addr, queue, 7814 IGB_MAC_STATE_QUEUE_STEERING | flags); 7815 } 7816 7817 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7818 const u8 *addr, u8 queue, u8 flags) 7819 { 7820 return igb_del_mac_filter_flags(adapter, addr, queue, 7821 IGB_MAC_STATE_QUEUE_STEERING | flags); 7822 } 7823 7824 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7825 { 7826 struct igb_adapter *adapter = netdev_priv(netdev); 7827 int ret; 7828 7829 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7830 7831 return min_t(int, ret, 0); 7832 } 7833 7834 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7835 { 7836 struct igb_adapter *adapter = netdev_priv(netdev); 7837 7838 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7839 7840 return 0; 7841 } 7842 7843 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7844 const u32 info, const u8 *addr) 7845 { 7846 struct pci_dev *pdev = adapter->pdev; 7847 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7848 struct list_head *pos; 7849 struct vf_mac_filter *entry = NULL; 7850 int ret = 0; 7851 7852 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7853 !vf_data->trusted) { 7854 dev_warn(&pdev->dev, 7855 "VF %d requested MAC filter but is administratively denied\n", 7856 vf); 7857 return -EINVAL; 7858 } 7859 if (!is_valid_ether_addr(addr)) { 7860 dev_warn(&pdev->dev, 7861 "VF %d attempted to set invalid MAC filter\n", 7862 vf); 7863 return -EINVAL; 7864 } 7865 7866 switch (info) { 7867 case E1000_VF_MAC_FILTER_CLR: 7868 /* remove all unicast MAC filters related to the current VF */ 7869 list_for_each(pos, &adapter->vf_macs.l) { 7870 entry = list_entry(pos, struct vf_mac_filter, l); 7871 if (entry->vf == vf) { 7872 entry->vf = -1; 7873 entry->free = true; 7874 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7875 } 7876 } 7877 break; 7878 case E1000_VF_MAC_FILTER_ADD: 7879 /* try to find empty slot in the list */ 7880 list_for_each(pos, &adapter->vf_macs.l) { 7881 entry = list_entry(pos, struct vf_mac_filter, l); 7882 if (entry->free) 7883 break; 7884 } 7885 7886 if (entry && entry->free) { 7887 entry->free = false; 7888 entry->vf = vf; 7889 ether_addr_copy(entry->vf_mac, addr); 7890 7891 ret = igb_add_mac_filter(adapter, addr, vf); 7892 ret = min_t(int, ret, 0); 7893 } else { 7894 ret = -ENOSPC; 7895 } 7896 7897 if (ret == -ENOSPC) 7898 dev_warn(&pdev->dev, 7899 "VF %d has requested MAC filter but there is no space for it\n", 7900 vf); 7901 break; 7902 default: 7903 ret = -EINVAL; 7904 break; 7905 } 7906 7907 return ret; 7908 } 7909 7910 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7911 { 7912 struct pci_dev *pdev = adapter->pdev; 7913 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7914 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7915 7916 /* The VF MAC Address is stored in a packed array of bytes 7917 * starting at the second 32 bit word of the msg array 7918 */ 7919 unsigned char *addr = (unsigned char *)&msg[1]; 7920 int ret = 0; 7921 7922 if (!info) { 7923 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7924 !vf_data->trusted) { 7925 dev_warn(&pdev->dev, 7926 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7927 vf); 7928 return -EINVAL; 7929 } 7930 7931 if (!is_valid_ether_addr(addr)) { 7932 dev_warn(&pdev->dev, 7933 "VF %d attempted to set invalid MAC\n", 7934 vf); 7935 return -EINVAL; 7936 } 7937 7938 ret = igb_set_vf_mac(adapter, vf, addr); 7939 } else { 7940 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7941 } 7942 7943 return ret; 7944 } 7945 7946 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7947 { 7948 struct e1000_hw *hw = &adapter->hw; 7949 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7950 u32 msg = E1000_VT_MSGTYPE_NACK; 7951 7952 /* if device isn't clear to send it shouldn't be reading either */ 7953 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7954 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7955 igb_write_mbx(hw, &msg, 1, vf); 7956 vf_data->last_nack = jiffies; 7957 } 7958 } 7959 7960 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7961 { 7962 struct pci_dev *pdev = adapter->pdev; 7963 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7964 struct e1000_hw *hw = &adapter->hw; 7965 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7966 s32 retval; 7967 7968 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7969 7970 if (retval) { 7971 /* if receive failed revoke VF CTS stats and restart init */ 7972 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7973 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7974 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7975 goto unlock; 7976 goto out; 7977 } 7978 7979 /* this is a message we already processed, do nothing */ 7980 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7981 goto unlock; 7982 7983 /* until the vf completes a reset it should not be 7984 * allowed to start any configuration. 7985 */ 7986 if (msgbuf[0] == E1000_VF_RESET) { 7987 /* unlocks mailbox */ 7988 igb_vf_reset_msg(adapter, vf); 7989 return; 7990 } 7991 7992 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7993 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7994 goto unlock; 7995 retval = -1; 7996 goto out; 7997 } 7998 7999 switch ((msgbuf[0] & 0xFFFF)) { 8000 case E1000_VF_SET_MAC_ADDR: 8001 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8002 break; 8003 case E1000_VF_SET_PROMISC: 8004 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8005 break; 8006 case E1000_VF_SET_MULTICAST: 8007 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8008 break; 8009 case E1000_VF_SET_LPE: 8010 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8011 break; 8012 case E1000_VF_SET_VLAN: 8013 retval = -1; 8014 if (vf_data->pf_vlan) 8015 dev_warn(&pdev->dev, 8016 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8017 vf); 8018 else 8019 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8020 break; 8021 default: 8022 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8023 retval = -1; 8024 break; 8025 } 8026 8027 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8028 out: 8029 /* notify the VF of the results of what it sent us */ 8030 if (retval) 8031 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8032 else 8033 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8034 8035 /* unlocks mailbox */ 8036 igb_write_mbx(hw, msgbuf, 1, vf); 8037 return; 8038 8039 unlock: 8040 igb_unlock_mbx(hw, vf); 8041 } 8042 8043 static void igb_msg_task(struct igb_adapter *adapter) 8044 { 8045 struct e1000_hw *hw = &adapter->hw; 8046 unsigned long flags; 8047 u32 vf; 8048 8049 spin_lock_irqsave(&adapter->vfs_lock, flags); 8050 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8051 /* process any reset requests */ 8052 if (!igb_check_for_rst(hw, vf)) 8053 igb_vf_reset_event(adapter, vf); 8054 8055 /* process any messages pending */ 8056 if (!igb_check_for_msg(hw, vf)) 8057 igb_rcv_msg_from_vf(adapter, vf); 8058 8059 /* process any acks */ 8060 if (!igb_check_for_ack(hw, vf)) 8061 igb_rcv_ack_from_vf(adapter, vf); 8062 } 8063 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8064 } 8065 8066 /** 8067 * igb_set_uta - Set unicast filter table address 8068 * @adapter: board private structure 8069 * @set: boolean indicating if we are setting or clearing bits 8070 * 8071 * The unicast table address is a register array of 32-bit registers. 8072 * The table is meant to be used in a way similar to how the MTA is used 8073 * however due to certain limitations in the hardware it is necessary to 8074 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8075 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8076 **/ 8077 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8078 { 8079 struct e1000_hw *hw = &adapter->hw; 8080 u32 uta = set ? ~0 : 0; 8081 int i; 8082 8083 /* we only need to do this if VMDq is enabled */ 8084 if (!adapter->vfs_allocated_count) 8085 return; 8086 8087 for (i = hw->mac.uta_reg_count; i--;) 8088 array_wr32(E1000_UTA, i, uta); 8089 } 8090 8091 /** 8092 * igb_intr_msi - Interrupt Handler 8093 * @irq: interrupt number 8094 * @data: pointer to a network interface device structure 8095 **/ 8096 static irqreturn_t igb_intr_msi(int irq, void *data) 8097 { 8098 struct igb_adapter *adapter = data; 8099 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8100 struct e1000_hw *hw = &adapter->hw; 8101 /* read ICR disables interrupts using IAM */ 8102 u32 icr = rd32(E1000_ICR); 8103 8104 igb_write_itr(q_vector); 8105 8106 if (icr & E1000_ICR_DRSTA) 8107 schedule_work(&adapter->reset_task); 8108 8109 if (icr & E1000_ICR_DOUTSYNC) { 8110 /* HW is reporting DMA is out of sync */ 8111 adapter->stats.doosync++; 8112 } 8113 8114 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8115 hw->mac.get_link_status = 1; 8116 if (!test_bit(__IGB_DOWN, &adapter->state)) 8117 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8118 } 8119 8120 if (icr & E1000_ICR_TS) 8121 igb_tsync_interrupt(adapter); 8122 8123 napi_schedule(&q_vector->napi); 8124 8125 return IRQ_HANDLED; 8126 } 8127 8128 /** 8129 * igb_intr - Legacy Interrupt Handler 8130 * @irq: interrupt number 8131 * @data: pointer to a network interface device structure 8132 **/ 8133 static irqreturn_t igb_intr(int irq, void *data) 8134 { 8135 struct igb_adapter *adapter = data; 8136 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8137 struct e1000_hw *hw = &adapter->hw; 8138 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8139 * need for the IMC write 8140 */ 8141 u32 icr = rd32(E1000_ICR); 8142 8143 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8144 * not set, then the adapter didn't send an interrupt 8145 */ 8146 if (!(icr & E1000_ICR_INT_ASSERTED)) 8147 return IRQ_NONE; 8148 8149 igb_write_itr(q_vector); 8150 8151 if (icr & E1000_ICR_DRSTA) 8152 schedule_work(&adapter->reset_task); 8153 8154 if (icr & E1000_ICR_DOUTSYNC) { 8155 /* HW is reporting DMA is out of sync */ 8156 adapter->stats.doosync++; 8157 } 8158 8159 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8160 hw->mac.get_link_status = 1; 8161 /* guard against interrupt when we're going down */ 8162 if (!test_bit(__IGB_DOWN, &adapter->state)) 8163 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8164 } 8165 8166 if (icr & E1000_ICR_TS) 8167 igb_tsync_interrupt(adapter); 8168 8169 napi_schedule(&q_vector->napi); 8170 8171 return IRQ_HANDLED; 8172 } 8173 8174 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8175 { 8176 struct igb_adapter *adapter = q_vector->adapter; 8177 struct e1000_hw *hw = &adapter->hw; 8178 8179 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8180 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8181 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8182 igb_set_itr(q_vector); 8183 else 8184 igb_update_ring_itr(q_vector); 8185 } 8186 8187 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8188 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8189 wr32(E1000_EIMS, q_vector->eims_value); 8190 else 8191 igb_irq_enable(adapter); 8192 } 8193 } 8194 8195 /** 8196 * igb_poll - NAPI Rx polling callback 8197 * @napi: napi polling structure 8198 * @budget: count of how many packets we should handle 8199 **/ 8200 static int igb_poll(struct napi_struct *napi, int budget) 8201 { 8202 struct igb_q_vector *q_vector = container_of(napi, 8203 struct igb_q_vector, 8204 napi); 8205 bool clean_complete = true; 8206 int work_done = 0; 8207 8208 #ifdef CONFIG_IGB_DCA 8209 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8210 igb_update_dca(q_vector); 8211 #endif 8212 if (q_vector->tx.ring) 8213 clean_complete = igb_clean_tx_irq(q_vector, budget); 8214 8215 if (q_vector->rx.ring) { 8216 int cleaned = igb_clean_rx_irq(q_vector, budget); 8217 8218 work_done += cleaned; 8219 if (cleaned >= budget) 8220 clean_complete = false; 8221 } 8222 8223 /* If all work not completed, return budget and keep polling */ 8224 if (!clean_complete) 8225 return budget; 8226 8227 /* Exit the polling mode, but don't re-enable interrupts if stack might 8228 * poll us due to busy-polling 8229 */ 8230 if (likely(napi_complete_done(napi, work_done))) 8231 igb_ring_irq_enable(q_vector); 8232 8233 return work_done; 8234 } 8235 8236 /** 8237 * igb_clean_tx_irq - Reclaim resources after transmit completes 8238 * @q_vector: pointer to q_vector containing needed info 8239 * @napi_budget: Used to determine if we are in netpoll 8240 * 8241 * returns true if ring is completely cleaned 8242 **/ 8243 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8244 { 8245 struct igb_adapter *adapter = q_vector->adapter; 8246 struct igb_ring *tx_ring = q_vector->tx.ring; 8247 struct igb_tx_buffer *tx_buffer; 8248 union e1000_adv_tx_desc *tx_desc; 8249 unsigned int total_bytes = 0, total_packets = 0; 8250 unsigned int budget = q_vector->tx.work_limit; 8251 unsigned int i = tx_ring->next_to_clean; 8252 8253 if (test_bit(__IGB_DOWN, &adapter->state)) 8254 return true; 8255 8256 tx_buffer = &tx_ring->tx_buffer_info[i]; 8257 tx_desc = IGB_TX_DESC(tx_ring, i); 8258 i -= tx_ring->count; 8259 8260 do { 8261 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8262 8263 /* if next_to_watch is not set then there is no work pending */ 8264 if (!eop_desc) 8265 break; 8266 8267 /* prevent any other reads prior to eop_desc */ 8268 smp_rmb(); 8269 8270 /* if DD is not set pending work has not been completed */ 8271 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8272 break; 8273 8274 /* clear next_to_watch to prevent false hangs */ 8275 tx_buffer->next_to_watch = NULL; 8276 8277 /* update the statistics for this packet */ 8278 total_bytes += tx_buffer->bytecount; 8279 total_packets += tx_buffer->gso_segs; 8280 8281 /* free the skb */ 8282 if (tx_buffer->type == IGB_TYPE_SKB) 8283 napi_consume_skb(tx_buffer->skb, napi_budget); 8284 else 8285 xdp_return_frame(tx_buffer->xdpf); 8286 8287 /* unmap skb header data */ 8288 dma_unmap_single(tx_ring->dev, 8289 dma_unmap_addr(tx_buffer, dma), 8290 dma_unmap_len(tx_buffer, len), 8291 DMA_TO_DEVICE); 8292 8293 /* clear tx_buffer data */ 8294 dma_unmap_len_set(tx_buffer, len, 0); 8295 8296 /* clear last DMA location and unmap remaining buffers */ 8297 while (tx_desc != eop_desc) { 8298 tx_buffer++; 8299 tx_desc++; 8300 i++; 8301 if (unlikely(!i)) { 8302 i -= tx_ring->count; 8303 tx_buffer = tx_ring->tx_buffer_info; 8304 tx_desc = IGB_TX_DESC(tx_ring, 0); 8305 } 8306 8307 /* unmap any remaining paged data */ 8308 if (dma_unmap_len(tx_buffer, len)) { 8309 dma_unmap_page(tx_ring->dev, 8310 dma_unmap_addr(tx_buffer, dma), 8311 dma_unmap_len(tx_buffer, len), 8312 DMA_TO_DEVICE); 8313 dma_unmap_len_set(tx_buffer, len, 0); 8314 } 8315 } 8316 8317 /* move us one more past the eop_desc for start of next pkt */ 8318 tx_buffer++; 8319 tx_desc++; 8320 i++; 8321 if (unlikely(!i)) { 8322 i -= tx_ring->count; 8323 tx_buffer = tx_ring->tx_buffer_info; 8324 tx_desc = IGB_TX_DESC(tx_ring, 0); 8325 } 8326 8327 /* issue prefetch for next Tx descriptor */ 8328 prefetch(tx_desc); 8329 8330 /* update budget accounting */ 8331 budget--; 8332 } while (likely(budget)); 8333 8334 netdev_tx_completed_queue(txring_txq(tx_ring), 8335 total_packets, total_bytes); 8336 i += tx_ring->count; 8337 tx_ring->next_to_clean = i; 8338 u64_stats_update_begin(&tx_ring->tx_syncp); 8339 tx_ring->tx_stats.bytes += total_bytes; 8340 tx_ring->tx_stats.packets += total_packets; 8341 u64_stats_update_end(&tx_ring->tx_syncp); 8342 q_vector->tx.total_bytes += total_bytes; 8343 q_vector->tx.total_packets += total_packets; 8344 8345 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8346 struct e1000_hw *hw = &adapter->hw; 8347 8348 /* Detect a transmit hang in hardware, this serializes the 8349 * check with the clearing of time_stamp and movement of i 8350 */ 8351 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8352 if (tx_buffer->next_to_watch && 8353 time_after(jiffies, tx_buffer->time_stamp + 8354 (adapter->tx_timeout_factor * HZ)) && 8355 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8356 8357 /* detected Tx unit hang */ 8358 dev_err(tx_ring->dev, 8359 "Detected Tx Unit Hang\n" 8360 " Tx Queue <%d>\n" 8361 " TDH <%x>\n" 8362 " TDT <%x>\n" 8363 " next_to_use <%x>\n" 8364 " next_to_clean <%x>\n" 8365 "buffer_info[next_to_clean]\n" 8366 " time_stamp <%lx>\n" 8367 " next_to_watch <%p>\n" 8368 " jiffies <%lx>\n" 8369 " desc.status <%x>\n", 8370 tx_ring->queue_index, 8371 rd32(E1000_TDH(tx_ring->reg_idx)), 8372 readl(tx_ring->tail), 8373 tx_ring->next_to_use, 8374 tx_ring->next_to_clean, 8375 tx_buffer->time_stamp, 8376 tx_buffer->next_to_watch, 8377 jiffies, 8378 tx_buffer->next_to_watch->wb.status); 8379 netif_stop_subqueue(tx_ring->netdev, 8380 tx_ring->queue_index); 8381 8382 /* we are about to reset, no point in enabling stuff */ 8383 return true; 8384 } 8385 } 8386 8387 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8388 if (unlikely(total_packets && 8389 netif_carrier_ok(tx_ring->netdev) && 8390 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8391 /* Make sure that anybody stopping the queue after this 8392 * sees the new next_to_clean. 8393 */ 8394 smp_mb(); 8395 if (__netif_subqueue_stopped(tx_ring->netdev, 8396 tx_ring->queue_index) && 8397 !(test_bit(__IGB_DOWN, &adapter->state))) { 8398 netif_wake_subqueue(tx_ring->netdev, 8399 tx_ring->queue_index); 8400 8401 u64_stats_update_begin(&tx_ring->tx_syncp); 8402 tx_ring->tx_stats.restart_queue++; 8403 u64_stats_update_end(&tx_ring->tx_syncp); 8404 } 8405 } 8406 8407 return !!budget; 8408 } 8409 8410 /** 8411 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8412 * @rx_ring: rx descriptor ring to store buffers on 8413 * @old_buff: donor buffer to have page reused 8414 * 8415 * Synchronizes page for reuse by the adapter 8416 **/ 8417 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8418 struct igb_rx_buffer *old_buff) 8419 { 8420 struct igb_rx_buffer *new_buff; 8421 u16 nta = rx_ring->next_to_alloc; 8422 8423 new_buff = &rx_ring->rx_buffer_info[nta]; 8424 8425 /* update, and store next to alloc */ 8426 nta++; 8427 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8428 8429 /* Transfer page from old buffer to new buffer. 8430 * Move each member individually to avoid possible store 8431 * forwarding stalls. 8432 */ 8433 new_buff->dma = old_buff->dma; 8434 new_buff->page = old_buff->page; 8435 new_buff->page_offset = old_buff->page_offset; 8436 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8437 } 8438 8439 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8440 int rx_buf_pgcnt) 8441 { 8442 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8443 struct page *page = rx_buffer->page; 8444 8445 /* avoid re-using remote and pfmemalloc pages */ 8446 if (!dev_page_is_reusable(page)) 8447 return false; 8448 8449 #if (PAGE_SIZE < 8192) 8450 /* if we are only owner of page we can reuse it */ 8451 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8452 return false; 8453 #else 8454 #define IGB_LAST_OFFSET \ 8455 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8456 8457 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8458 return false; 8459 #endif 8460 8461 /* If we have drained the page fragment pool we need to update 8462 * the pagecnt_bias and page count so that we fully restock the 8463 * number of references the driver holds. 8464 */ 8465 if (unlikely(pagecnt_bias == 1)) { 8466 page_ref_add(page, USHRT_MAX - 1); 8467 rx_buffer->pagecnt_bias = USHRT_MAX; 8468 } 8469 8470 return true; 8471 } 8472 8473 /** 8474 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8475 * @rx_ring: rx descriptor ring to transact packets on 8476 * @rx_buffer: buffer containing page to add 8477 * @skb: sk_buff to place the data into 8478 * @size: size of buffer to be added 8479 * 8480 * This function will add the data contained in rx_buffer->page to the skb. 8481 **/ 8482 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8483 struct igb_rx_buffer *rx_buffer, 8484 struct sk_buff *skb, 8485 unsigned int size) 8486 { 8487 #if (PAGE_SIZE < 8192) 8488 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8489 #else 8490 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8491 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8492 SKB_DATA_ALIGN(size); 8493 #endif 8494 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8495 rx_buffer->page_offset, size, truesize); 8496 #if (PAGE_SIZE < 8192) 8497 rx_buffer->page_offset ^= truesize; 8498 #else 8499 rx_buffer->page_offset += truesize; 8500 #endif 8501 } 8502 8503 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8504 struct igb_rx_buffer *rx_buffer, 8505 struct xdp_buff *xdp, 8506 ktime_t timestamp) 8507 { 8508 #if (PAGE_SIZE < 8192) 8509 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8510 #else 8511 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8512 xdp->data_hard_start); 8513 #endif 8514 unsigned int size = xdp->data_end - xdp->data; 8515 unsigned int headlen; 8516 struct sk_buff *skb; 8517 8518 /* prefetch first cache line of first page */ 8519 net_prefetch(xdp->data); 8520 8521 /* allocate a skb to store the frags */ 8522 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8523 if (unlikely(!skb)) 8524 return NULL; 8525 8526 if (timestamp) 8527 skb_hwtstamps(skb)->hwtstamp = timestamp; 8528 8529 /* Determine available headroom for copy */ 8530 headlen = size; 8531 if (headlen > IGB_RX_HDR_LEN) 8532 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8533 8534 /* align pull length to size of long to optimize memcpy performance */ 8535 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8536 8537 /* update all of the pointers */ 8538 size -= headlen; 8539 if (size) { 8540 skb_add_rx_frag(skb, 0, rx_buffer->page, 8541 (xdp->data + headlen) - page_address(rx_buffer->page), 8542 size, truesize); 8543 #if (PAGE_SIZE < 8192) 8544 rx_buffer->page_offset ^= truesize; 8545 #else 8546 rx_buffer->page_offset += truesize; 8547 #endif 8548 } else { 8549 rx_buffer->pagecnt_bias++; 8550 } 8551 8552 return skb; 8553 } 8554 8555 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8556 struct igb_rx_buffer *rx_buffer, 8557 struct xdp_buff *xdp, 8558 ktime_t timestamp) 8559 { 8560 #if (PAGE_SIZE < 8192) 8561 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8562 #else 8563 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8564 SKB_DATA_ALIGN(xdp->data_end - 8565 xdp->data_hard_start); 8566 #endif 8567 unsigned int metasize = xdp->data - xdp->data_meta; 8568 struct sk_buff *skb; 8569 8570 /* prefetch first cache line of first page */ 8571 net_prefetch(xdp->data_meta); 8572 8573 /* build an skb around the page buffer */ 8574 skb = napi_build_skb(xdp->data_hard_start, truesize); 8575 if (unlikely(!skb)) 8576 return NULL; 8577 8578 /* update pointers within the skb to store the data */ 8579 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8580 __skb_put(skb, xdp->data_end - xdp->data); 8581 8582 if (metasize) 8583 skb_metadata_set(skb, metasize); 8584 8585 if (timestamp) 8586 skb_hwtstamps(skb)->hwtstamp = timestamp; 8587 8588 /* update buffer offset */ 8589 #if (PAGE_SIZE < 8192) 8590 rx_buffer->page_offset ^= truesize; 8591 #else 8592 rx_buffer->page_offset += truesize; 8593 #endif 8594 8595 return skb; 8596 } 8597 8598 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8599 struct igb_ring *rx_ring, 8600 struct xdp_buff *xdp) 8601 { 8602 int err, result = IGB_XDP_PASS; 8603 struct bpf_prog *xdp_prog; 8604 u32 act; 8605 8606 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8607 8608 if (!xdp_prog) 8609 goto xdp_out; 8610 8611 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8612 8613 act = bpf_prog_run_xdp(xdp_prog, xdp); 8614 switch (act) { 8615 case XDP_PASS: 8616 break; 8617 case XDP_TX: 8618 result = igb_xdp_xmit_back(adapter, xdp); 8619 if (result == IGB_XDP_CONSUMED) 8620 goto out_failure; 8621 break; 8622 case XDP_REDIRECT: 8623 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8624 if (err) 8625 goto out_failure; 8626 result = IGB_XDP_REDIR; 8627 break; 8628 default: 8629 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8630 fallthrough; 8631 case XDP_ABORTED: 8632 out_failure: 8633 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8634 fallthrough; 8635 case XDP_DROP: 8636 result = IGB_XDP_CONSUMED; 8637 break; 8638 } 8639 xdp_out: 8640 return ERR_PTR(-result); 8641 } 8642 8643 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8644 unsigned int size) 8645 { 8646 unsigned int truesize; 8647 8648 #if (PAGE_SIZE < 8192) 8649 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8650 #else 8651 truesize = ring_uses_build_skb(rx_ring) ? 8652 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8653 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8654 SKB_DATA_ALIGN(size); 8655 #endif 8656 return truesize; 8657 } 8658 8659 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8660 struct igb_rx_buffer *rx_buffer, 8661 unsigned int size) 8662 { 8663 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8664 #if (PAGE_SIZE < 8192) 8665 rx_buffer->page_offset ^= truesize; 8666 #else 8667 rx_buffer->page_offset += truesize; 8668 #endif 8669 } 8670 8671 static inline void igb_rx_checksum(struct igb_ring *ring, 8672 union e1000_adv_rx_desc *rx_desc, 8673 struct sk_buff *skb) 8674 { 8675 skb_checksum_none_assert(skb); 8676 8677 /* Ignore Checksum bit is set */ 8678 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8679 return; 8680 8681 /* Rx checksum disabled via ethtool */ 8682 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8683 return; 8684 8685 /* TCP/UDP checksum error bit is set */ 8686 if (igb_test_staterr(rx_desc, 8687 E1000_RXDEXT_STATERR_TCPE | 8688 E1000_RXDEXT_STATERR_IPE)) { 8689 /* work around errata with sctp packets where the TCPE aka 8690 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8691 * packets, (aka let the stack check the crc32c) 8692 */ 8693 if (!((skb->len == 60) && 8694 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8695 u64_stats_update_begin(&ring->rx_syncp); 8696 ring->rx_stats.csum_err++; 8697 u64_stats_update_end(&ring->rx_syncp); 8698 } 8699 /* let the stack verify checksum errors */ 8700 return; 8701 } 8702 /* It must be a TCP or UDP packet with a valid checksum */ 8703 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8704 E1000_RXD_STAT_UDPCS)) 8705 skb->ip_summed = CHECKSUM_UNNECESSARY; 8706 8707 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8708 le32_to_cpu(rx_desc->wb.upper.status_error)); 8709 } 8710 8711 static inline void igb_rx_hash(struct igb_ring *ring, 8712 union e1000_adv_rx_desc *rx_desc, 8713 struct sk_buff *skb) 8714 { 8715 if (ring->netdev->features & NETIF_F_RXHASH) 8716 skb_set_hash(skb, 8717 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8718 PKT_HASH_TYPE_L3); 8719 } 8720 8721 /** 8722 * igb_is_non_eop - process handling of non-EOP buffers 8723 * @rx_ring: Rx ring being processed 8724 * @rx_desc: Rx descriptor for current buffer 8725 * 8726 * This function updates next to clean. If the buffer is an EOP buffer 8727 * this function exits returning false, otherwise it will place the 8728 * sk_buff in the next buffer to be chained and return true indicating 8729 * that this is in fact a non-EOP buffer. 8730 **/ 8731 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8732 union e1000_adv_rx_desc *rx_desc) 8733 { 8734 u32 ntc = rx_ring->next_to_clean + 1; 8735 8736 /* fetch, update, and store next to clean */ 8737 ntc = (ntc < rx_ring->count) ? ntc : 0; 8738 rx_ring->next_to_clean = ntc; 8739 8740 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8741 8742 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8743 return false; 8744 8745 return true; 8746 } 8747 8748 /** 8749 * igb_cleanup_headers - Correct corrupted or empty headers 8750 * @rx_ring: rx descriptor ring packet is being transacted on 8751 * @rx_desc: pointer to the EOP Rx descriptor 8752 * @skb: pointer to current skb being fixed 8753 * 8754 * Address the case where we are pulling data in on pages only 8755 * and as such no data is present in the skb header. 8756 * 8757 * In addition if skb is not at least 60 bytes we need to pad it so that 8758 * it is large enough to qualify as a valid Ethernet frame. 8759 * 8760 * Returns true if an error was encountered and skb was freed. 8761 **/ 8762 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8763 union e1000_adv_rx_desc *rx_desc, 8764 struct sk_buff *skb) 8765 { 8766 /* XDP packets use error pointer so abort at this point */ 8767 if (IS_ERR(skb)) 8768 return true; 8769 8770 if (unlikely((igb_test_staterr(rx_desc, 8771 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8772 struct net_device *netdev = rx_ring->netdev; 8773 if (!(netdev->features & NETIF_F_RXALL)) { 8774 dev_kfree_skb_any(skb); 8775 return true; 8776 } 8777 } 8778 8779 /* if eth_skb_pad returns an error the skb was freed */ 8780 if (eth_skb_pad(skb)) 8781 return true; 8782 8783 return false; 8784 } 8785 8786 /** 8787 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8788 * @rx_ring: rx descriptor ring packet is being transacted on 8789 * @rx_desc: pointer to the EOP Rx descriptor 8790 * @skb: pointer to current skb being populated 8791 * 8792 * This function checks the ring, descriptor, and packet information in 8793 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8794 * other fields within the skb. 8795 **/ 8796 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8797 union e1000_adv_rx_desc *rx_desc, 8798 struct sk_buff *skb) 8799 { 8800 struct net_device *dev = rx_ring->netdev; 8801 8802 igb_rx_hash(rx_ring, rx_desc, skb); 8803 8804 igb_rx_checksum(rx_ring, rx_desc, skb); 8805 8806 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8807 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8808 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8809 8810 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8811 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8812 u16 vid; 8813 8814 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8815 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8816 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8817 else 8818 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8819 8820 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8821 } 8822 8823 skb_record_rx_queue(skb, rx_ring->queue_index); 8824 8825 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8826 } 8827 8828 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8829 { 8830 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8831 } 8832 8833 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8834 const unsigned int size, int *rx_buf_pgcnt) 8835 { 8836 struct igb_rx_buffer *rx_buffer; 8837 8838 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8839 *rx_buf_pgcnt = 8840 #if (PAGE_SIZE < 8192) 8841 page_count(rx_buffer->page); 8842 #else 8843 0; 8844 #endif 8845 prefetchw(rx_buffer->page); 8846 8847 /* we are reusing so sync this buffer for CPU use */ 8848 dma_sync_single_range_for_cpu(rx_ring->dev, 8849 rx_buffer->dma, 8850 rx_buffer->page_offset, 8851 size, 8852 DMA_FROM_DEVICE); 8853 8854 rx_buffer->pagecnt_bias--; 8855 8856 return rx_buffer; 8857 } 8858 8859 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8860 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8861 { 8862 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8863 /* hand second half of page back to the ring */ 8864 igb_reuse_rx_page(rx_ring, rx_buffer); 8865 } else { 8866 /* We are not reusing the buffer so unmap it and free 8867 * any references we are holding to it 8868 */ 8869 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8870 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8871 IGB_RX_DMA_ATTR); 8872 __page_frag_cache_drain(rx_buffer->page, 8873 rx_buffer->pagecnt_bias); 8874 } 8875 8876 /* clear contents of rx_buffer */ 8877 rx_buffer->page = NULL; 8878 } 8879 8880 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8881 { 8882 struct igb_adapter *adapter = q_vector->adapter; 8883 struct igb_ring *rx_ring = q_vector->rx.ring; 8884 struct sk_buff *skb = rx_ring->skb; 8885 unsigned int total_bytes = 0, total_packets = 0; 8886 u16 cleaned_count = igb_desc_unused(rx_ring); 8887 unsigned int xdp_xmit = 0; 8888 struct xdp_buff xdp; 8889 u32 frame_sz = 0; 8890 int rx_buf_pgcnt; 8891 8892 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8893 #if (PAGE_SIZE < 8192) 8894 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8895 #endif 8896 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 8897 8898 while (likely(total_packets < budget)) { 8899 union e1000_adv_rx_desc *rx_desc; 8900 struct igb_rx_buffer *rx_buffer; 8901 ktime_t timestamp = 0; 8902 int pkt_offset = 0; 8903 unsigned int size; 8904 void *pktbuf; 8905 8906 /* return some buffers to hardware, one at a time is too slow */ 8907 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8908 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8909 cleaned_count = 0; 8910 } 8911 8912 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8913 size = le16_to_cpu(rx_desc->wb.upper.length); 8914 if (!size) 8915 break; 8916 8917 /* This memory barrier is needed to keep us from reading 8918 * any other fields out of the rx_desc until we know the 8919 * descriptor has been written back 8920 */ 8921 dma_rmb(); 8922 8923 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 8924 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 8925 8926 /* pull rx packet timestamp if available and valid */ 8927 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8928 int ts_hdr_len; 8929 8930 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 8931 pktbuf, ×tamp); 8932 8933 pkt_offset += ts_hdr_len; 8934 size -= ts_hdr_len; 8935 } 8936 8937 /* retrieve a buffer from the ring */ 8938 if (!skb) { 8939 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 8940 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 8941 8942 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 8943 xdp_buff_clear_frags_flag(&xdp); 8944 #if (PAGE_SIZE > 4096) 8945 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8946 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8947 #endif 8948 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8949 } 8950 8951 if (IS_ERR(skb)) { 8952 unsigned int xdp_res = -PTR_ERR(skb); 8953 8954 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8955 xdp_xmit |= xdp_res; 8956 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8957 } else { 8958 rx_buffer->pagecnt_bias++; 8959 } 8960 total_packets++; 8961 total_bytes += size; 8962 } else if (skb) 8963 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8964 else if (ring_uses_build_skb(rx_ring)) 8965 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 8966 timestamp); 8967 else 8968 skb = igb_construct_skb(rx_ring, rx_buffer, 8969 &xdp, timestamp); 8970 8971 /* exit if we failed to retrieve a buffer */ 8972 if (!skb) { 8973 rx_ring->rx_stats.alloc_failed++; 8974 rx_buffer->pagecnt_bias++; 8975 break; 8976 } 8977 8978 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 8979 cleaned_count++; 8980 8981 /* fetch next buffer in frame if non-eop */ 8982 if (igb_is_non_eop(rx_ring, rx_desc)) 8983 continue; 8984 8985 /* verify the packet layout is correct */ 8986 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8987 skb = NULL; 8988 continue; 8989 } 8990 8991 /* probably a little skewed due to removing CRC */ 8992 total_bytes += skb->len; 8993 8994 /* populate checksum, timestamp, VLAN, and protocol */ 8995 igb_process_skb_fields(rx_ring, rx_desc, skb); 8996 8997 napi_gro_receive(&q_vector->napi, skb); 8998 8999 /* reset skb pointer */ 9000 skb = NULL; 9001 9002 /* update budget accounting */ 9003 total_packets++; 9004 } 9005 9006 /* place incomplete frames back on ring for completion */ 9007 rx_ring->skb = skb; 9008 9009 if (xdp_xmit & IGB_XDP_REDIR) 9010 xdp_do_flush(); 9011 9012 if (xdp_xmit & IGB_XDP_TX) { 9013 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 9014 9015 igb_xdp_ring_update_tail(tx_ring); 9016 } 9017 9018 u64_stats_update_begin(&rx_ring->rx_syncp); 9019 rx_ring->rx_stats.packets += total_packets; 9020 rx_ring->rx_stats.bytes += total_bytes; 9021 u64_stats_update_end(&rx_ring->rx_syncp); 9022 q_vector->rx.total_packets += total_packets; 9023 q_vector->rx.total_bytes += total_bytes; 9024 9025 if (cleaned_count) 9026 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9027 9028 return total_packets; 9029 } 9030 9031 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9032 struct igb_rx_buffer *bi) 9033 { 9034 struct page *page = bi->page; 9035 dma_addr_t dma; 9036 9037 /* since we are recycling buffers we should seldom need to alloc */ 9038 if (likely(page)) 9039 return true; 9040 9041 /* alloc new page for storage */ 9042 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9043 if (unlikely(!page)) { 9044 rx_ring->rx_stats.alloc_failed++; 9045 return false; 9046 } 9047 9048 /* map page for use */ 9049 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9050 igb_rx_pg_size(rx_ring), 9051 DMA_FROM_DEVICE, 9052 IGB_RX_DMA_ATTR); 9053 9054 /* if mapping failed free memory back to system since 9055 * there isn't much point in holding memory we can't use 9056 */ 9057 if (dma_mapping_error(rx_ring->dev, dma)) { 9058 __free_pages(page, igb_rx_pg_order(rx_ring)); 9059 9060 rx_ring->rx_stats.alloc_failed++; 9061 return false; 9062 } 9063 9064 bi->dma = dma; 9065 bi->page = page; 9066 bi->page_offset = igb_rx_offset(rx_ring); 9067 page_ref_add(page, USHRT_MAX - 1); 9068 bi->pagecnt_bias = USHRT_MAX; 9069 9070 return true; 9071 } 9072 9073 /** 9074 * igb_alloc_rx_buffers - Replace used receive buffers 9075 * @rx_ring: rx descriptor ring to allocate new receive buffers 9076 * @cleaned_count: count of buffers to allocate 9077 **/ 9078 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9079 { 9080 union e1000_adv_rx_desc *rx_desc; 9081 struct igb_rx_buffer *bi; 9082 u16 i = rx_ring->next_to_use; 9083 u16 bufsz; 9084 9085 /* nothing to do */ 9086 if (!cleaned_count) 9087 return; 9088 9089 rx_desc = IGB_RX_DESC(rx_ring, i); 9090 bi = &rx_ring->rx_buffer_info[i]; 9091 i -= rx_ring->count; 9092 9093 bufsz = igb_rx_bufsz(rx_ring); 9094 9095 do { 9096 if (!igb_alloc_mapped_page(rx_ring, bi)) 9097 break; 9098 9099 /* sync the buffer for use by the device */ 9100 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9101 bi->page_offset, bufsz, 9102 DMA_FROM_DEVICE); 9103 9104 /* Refresh the desc even if buffer_addrs didn't change 9105 * because each write-back erases this info. 9106 */ 9107 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9108 9109 rx_desc++; 9110 bi++; 9111 i++; 9112 if (unlikely(!i)) { 9113 rx_desc = IGB_RX_DESC(rx_ring, 0); 9114 bi = rx_ring->rx_buffer_info; 9115 i -= rx_ring->count; 9116 } 9117 9118 /* clear the length for the next_to_use descriptor */ 9119 rx_desc->wb.upper.length = 0; 9120 9121 cleaned_count--; 9122 } while (cleaned_count); 9123 9124 i += rx_ring->count; 9125 9126 if (rx_ring->next_to_use != i) { 9127 /* record the next descriptor to use */ 9128 rx_ring->next_to_use = i; 9129 9130 /* update next to alloc since we have filled the ring */ 9131 rx_ring->next_to_alloc = i; 9132 9133 /* Force memory writes to complete before letting h/w 9134 * know there are new descriptors to fetch. (Only 9135 * applicable for weak-ordered memory model archs, 9136 * such as IA-64). 9137 */ 9138 dma_wmb(); 9139 writel(i, rx_ring->tail); 9140 } 9141 } 9142 9143 /** 9144 * igb_mii_ioctl - 9145 * @netdev: pointer to netdev struct 9146 * @ifr: interface structure 9147 * @cmd: ioctl command to execute 9148 **/ 9149 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9150 { 9151 struct igb_adapter *adapter = netdev_priv(netdev); 9152 struct mii_ioctl_data *data = if_mii(ifr); 9153 9154 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9155 return -EOPNOTSUPP; 9156 9157 switch (cmd) { 9158 case SIOCGMIIPHY: 9159 data->phy_id = adapter->hw.phy.addr; 9160 break; 9161 case SIOCGMIIREG: 9162 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9163 &data->val_out)) 9164 return -EIO; 9165 break; 9166 case SIOCSMIIREG: 9167 default: 9168 return -EOPNOTSUPP; 9169 } 9170 return 0; 9171 } 9172 9173 /** 9174 * igb_ioctl - 9175 * @netdev: pointer to netdev struct 9176 * @ifr: interface structure 9177 * @cmd: ioctl command to execute 9178 **/ 9179 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9180 { 9181 switch (cmd) { 9182 case SIOCGMIIPHY: 9183 case SIOCGMIIREG: 9184 case SIOCSMIIREG: 9185 return igb_mii_ioctl(netdev, ifr, cmd); 9186 case SIOCGHWTSTAMP: 9187 return igb_ptp_get_ts_config(netdev, ifr); 9188 case SIOCSHWTSTAMP: 9189 return igb_ptp_set_ts_config(netdev, ifr); 9190 default: 9191 return -EOPNOTSUPP; 9192 } 9193 } 9194 9195 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9196 { 9197 struct igb_adapter *adapter = hw->back; 9198 9199 pci_read_config_word(adapter->pdev, reg, value); 9200 } 9201 9202 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9203 { 9204 struct igb_adapter *adapter = hw->back; 9205 9206 pci_write_config_word(adapter->pdev, reg, *value); 9207 } 9208 9209 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9210 { 9211 struct igb_adapter *adapter = hw->back; 9212 9213 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9214 return -E1000_ERR_CONFIG; 9215 9216 return 0; 9217 } 9218 9219 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9220 { 9221 struct igb_adapter *adapter = hw->back; 9222 9223 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9224 return -E1000_ERR_CONFIG; 9225 9226 return 0; 9227 } 9228 9229 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9230 { 9231 struct igb_adapter *adapter = netdev_priv(netdev); 9232 struct e1000_hw *hw = &adapter->hw; 9233 u32 ctrl, rctl; 9234 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9235 9236 if (enable) { 9237 /* enable VLAN tag insert/strip */ 9238 ctrl = rd32(E1000_CTRL); 9239 ctrl |= E1000_CTRL_VME; 9240 wr32(E1000_CTRL, ctrl); 9241 9242 /* Disable CFI check */ 9243 rctl = rd32(E1000_RCTL); 9244 rctl &= ~E1000_RCTL_CFIEN; 9245 wr32(E1000_RCTL, rctl); 9246 } else { 9247 /* disable VLAN tag insert/strip */ 9248 ctrl = rd32(E1000_CTRL); 9249 ctrl &= ~E1000_CTRL_VME; 9250 wr32(E1000_CTRL, ctrl); 9251 } 9252 9253 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9254 } 9255 9256 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9257 __be16 proto, u16 vid) 9258 { 9259 struct igb_adapter *adapter = netdev_priv(netdev); 9260 struct e1000_hw *hw = &adapter->hw; 9261 int pf_id = adapter->vfs_allocated_count; 9262 9263 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9264 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9265 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9266 9267 set_bit(vid, adapter->active_vlans); 9268 9269 return 0; 9270 } 9271 9272 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9273 __be16 proto, u16 vid) 9274 { 9275 struct igb_adapter *adapter = netdev_priv(netdev); 9276 int pf_id = adapter->vfs_allocated_count; 9277 struct e1000_hw *hw = &adapter->hw; 9278 9279 /* remove VID from filter table */ 9280 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9281 igb_vfta_set(hw, vid, pf_id, false, true); 9282 9283 clear_bit(vid, adapter->active_vlans); 9284 9285 return 0; 9286 } 9287 9288 static void igb_restore_vlan(struct igb_adapter *adapter) 9289 { 9290 u16 vid = 1; 9291 9292 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9293 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9294 9295 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9296 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9297 } 9298 9299 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9300 { 9301 struct pci_dev *pdev = adapter->pdev; 9302 struct e1000_mac_info *mac = &adapter->hw.mac; 9303 9304 mac->autoneg = 0; 9305 9306 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9307 * for the switch() below to work 9308 */ 9309 if ((spd & 1) || (dplx & ~1)) 9310 goto err_inval; 9311 9312 /* Fiber NIC's only allow 1000 gbps Full duplex 9313 * and 100Mbps Full duplex for 100baseFx sfp 9314 */ 9315 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9316 switch (spd + dplx) { 9317 case SPEED_10 + DUPLEX_HALF: 9318 case SPEED_10 + DUPLEX_FULL: 9319 case SPEED_100 + DUPLEX_HALF: 9320 goto err_inval; 9321 default: 9322 break; 9323 } 9324 } 9325 9326 switch (spd + dplx) { 9327 case SPEED_10 + DUPLEX_HALF: 9328 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9329 break; 9330 case SPEED_10 + DUPLEX_FULL: 9331 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9332 break; 9333 case SPEED_100 + DUPLEX_HALF: 9334 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9335 break; 9336 case SPEED_100 + DUPLEX_FULL: 9337 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9338 break; 9339 case SPEED_1000 + DUPLEX_FULL: 9340 mac->autoneg = 1; 9341 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9342 break; 9343 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9344 default: 9345 goto err_inval; 9346 } 9347 9348 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9349 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9350 9351 return 0; 9352 9353 err_inval: 9354 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9355 return -EINVAL; 9356 } 9357 9358 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9359 bool runtime) 9360 { 9361 struct net_device *netdev = pci_get_drvdata(pdev); 9362 struct igb_adapter *adapter = netdev_priv(netdev); 9363 struct e1000_hw *hw = &adapter->hw; 9364 u32 ctrl, rctl, status; 9365 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9366 bool wake; 9367 9368 rtnl_lock(); 9369 netif_device_detach(netdev); 9370 9371 if (netif_running(netdev)) 9372 __igb_close(netdev, true); 9373 9374 igb_ptp_suspend(adapter); 9375 9376 igb_clear_interrupt_scheme(adapter); 9377 rtnl_unlock(); 9378 9379 status = rd32(E1000_STATUS); 9380 if (status & E1000_STATUS_LU) 9381 wufc &= ~E1000_WUFC_LNKC; 9382 9383 if (wufc) { 9384 igb_setup_rctl(adapter); 9385 igb_set_rx_mode(netdev); 9386 9387 /* turn on all-multi mode if wake on multicast is enabled */ 9388 if (wufc & E1000_WUFC_MC) { 9389 rctl = rd32(E1000_RCTL); 9390 rctl |= E1000_RCTL_MPE; 9391 wr32(E1000_RCTL, rctl); 9392 } 9393 9394 ctrl = rd32(E1000_CTRL); 9395 ctrl |= E1000_CTRL_ADVD3WUC; 9396 wr32(E1000_CTRL, ctrl); 9397 9398 /* Allow time for pending master requests to run */ 9399 igb_disable_pcie_master(hw); 9400 9401 wr32(E1000_WUC, E1000_WUC_PME_EN); 9402 wr32(E1000_WUFC, wufc); 9403 } else { 9404 wr32(E1000_WUC, 0); 9405 wr32(E1000_WUFC, 0); 9406 } 9407 9408 wake = wufc || adapter->en_mng_pt; 9409 if (!wake) 9410 igb_power_down_link(adapter); 9411 else 9412 igb_power_up_link(adapter); 9413 9414 if (enable_wake) 9415 *enable_wake = wake; 9416 9417 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9418 * would have already happened in close and is redundant. 9419 */ 9420 igb_release_hw_control(adapter); 9421 9422 pci_disable_device(pdev); 9423 9424 return 0; 9425 } 9426 9427 static void igb_deliver_wake_packet(struct net_device *netdev) 9428 { 9429 struct igb_adapter *adapter = netdev_priv(netdev); 9430 struct e1000_hw *hw = &adapter->hw; 9431 struct sk_buff *skb; 9432 u32 wupl; 9433 9434 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9435 9436 /* WUPM stores only the first 128 bytes of the wake packet. 9437 * Read the packet only if we have the whole thing. 9438 */ 9439 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9440 return; 9441 9442 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9443 if (!skb) 9444 return; 9445 9446 skb_put(skb, wupl); 9447 9448 /* Ensure reads are 32-bit aligned */ 9449 wupl = roundup(wupl, 4); 9450 9451 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9452 9453 skb->protocol = eth_type_trans(skb, netdev); 9454 netif_rx(skb); 9455 } 9456 9457 static int __maybe_unused igb_suspend(struct device *dev) 9458 { 9459 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9460 } 9461 9462 static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9463 { 9464 struct pci_dev *pdev = to_pci_dev(dev); 9465 struct net_device *netdev = pci_get_drvdata(pdev); 9466 struct igb_adapter *adapter = netdev_priv(netdev); 9467 struct e1000_hw *hw = &adapter->hw; 9468 u32 err, val; 9469 9470 pci_set_power_state(pdev, PCI_D0); 9471 pci_restore_state(pdev); 9472 pci_save_state(pdev); 9473 9474 if (!pci_device_is_present(pdev)) 9475 return -ENODEV; 9476 err = pci_enable_device_mem(pdev); 9477 if (err) { 9478 dev_err(&pdev->dev, 9479 "igb: Cannot enable PCI device from suspend\n"); 9480 return err; 9481 } 9482 pci_set_master(pdev); 9483 9484 pci_enable_wake(pdev, PCI_D3hot, 0); 9485 pci_enable_wake(pdev, PCI_D3cold, 0); 9486 9487 if (igb_init_interrupt_scheme(adapter, true)) { 9488 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9489 return -ENOMEM; 9490 } 9491 9492 igb_reset(adapter); 9493 9494 /* let the f/w know that the h/w is now under the control of the 9495 * driver. 9496 */ 9497 igb_get_hw_control(adapter); 9498 9499 val = rd32(E1000_WUS); 9500 if (val & WAKE_PKT_WUS) 9501 igb_deliver_wake_packet(netdev); 9502 9503 wr32(E1000_WUS, ~0); 9504 9505 if (!rpm) 9506 rtnl_lock(); 9507 if (!err && netif_running(netdev)) 9508 err = __igb_open(netdev, true); 9509 9510 if (!err) 9511 netif_device_attach(netdev); 9512 if (!rpm) 9513 rtnl_unlock(); 9514 9515 return err; 9516 } 9517 9518 static int __maybe_unused igb_resume(struct device *dev) 9519 { 9520 return __igb_resume(dev, false); 9521 } 9522 9523 static int __maybe_unused igb_runtime_idle(struct device *dev) 9524 { 9525 struct net_device *netdev = dev_get_drvdata(dev); 9526 struct igb_adapter *adapter = netdev_priv(netdev); 9527 9528 if (!igb_has_link(adapter)) 9529 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9530 9531 return -EBUSY; 9532 } 9533 9534 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9535 { 9536 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9537 } 9538 9539 static int __maybe_unused igb_runtime_resume(struct device *dev) 9540 { 9541 return __igb_resume(dev, true); 9542 } 9543 9544 static void igb_shutdown(struct pci_dev *pdev) 9545 { 9546 bool wake; 9547 9548 __igb_shutdown(pdev, &wake, 0); 9549 9550 if (system_state == SYSTEM_POWER_OFF) { 9551 pci_wake_from_d3(pdev, wake); 9552 pci_set_power_state(pdev, PCI_D3hot); 9553 } 9554 } 9555 9556 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9557 { 9558 #ifdef CONFIG_PCI_IOV 9559 int err; 9560 9561 if (num_vfs == 0) { 9562 return igb_disable_sriov(dev, true); 9563 } else { 9564 err = igb_enable_sriov(dev, num_vfs, true); 9565 return err ? err : num_vfs; 9566 } 9567 #endif 9568 return 0; 9569 } 9570 9571 /** 9572 * igb_io_error_detected - called when PCI error is detected 9573 * @pdev: Pointer to PCI device 9574 * @state: The current pci connection state 9575 * 9576 * This function is called after a PCI bus error affecting 9577 * this device has been detected. 9578 **/ 9579 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9580 pci_channel_state_t state) 9581 { 9582 struct net_device *netdev = pci_get_drvdata(pdev); 9583 struct igb_adapter *adapter = netdev_priv(netdev); 9584 9585 netif_device_detach(netdev); 9586 9587 if (state == pci_channel_io_perm_failure) 9588 return PCI_ERS_RESULT_DISCONNECT; 9589 9590 if (netif_running(netdev)) 9591 igb_down(adapter); 9592 pci_disable_device(pdev); 9593 9594 /* Request a slot reset. */ 9595 return PCI_ERS_RESULT_NEED_RESET; 9596 } 9597 9598 /** 9599 * igb_io_slot_reset - called after the pci bus has been reset. 9600 * @pdev: Pointer to PCI device 9601 * 9602 * Restart the card from scratch, as if from a cold-boot. Implementation 9603 * resembles the first-half of the __igb_resume routine. 9604 **/ 9605 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9606 { 9607 struct net_device *netdev = pci_get_drvdata(pdev); 9608 struct igb_adapter *adapter = netdev_priv(netdev); 9609 struct e1000_hw *hw = &adapter->hw; 9610 pci_ers_result_t result; 9611 9612 if (pci_enable_device_mem(pdev)) { 9613 dev_err(&pdev->dev, 9614 "Cannot re-enable PCI device after reset.\n"); 9615 result = PCI_ERS_RESULT_DISCONNECT; 9616 } else { 9617 pci_set_master(pdev); 9618 pci_restore_state(pdev); 9619 pci_save_state(pdev); 9620 9621 pci_enable_wake(pdev, PCI_D3hot, 0); 9622 pci_enable_wake(pdev, PCI_D3cold, 0); 9623 9624 /* In case of PCI error, adapter lose its HW address 9625 * so we should re-assign it here. 9626 */ 9627 hw->hw_addr = adapter->io_addr; 9628 9629 igb_reset(adapter); 9630 wr32(E1000_WUS, ~0); 9631 result = PCI_ERS_RESULT_RECOVERED; 9632 } 9633 9634 return result; 9635 } 9636 9637 /** 9638 * igb_io_resume - called when traffic can start flowing again. 9639 * @pdev: Pointer to PCI device 9640 * 9641 * This callback is called when the error recovery driver tells us that 9642 * its OK to resume normal operation. Implementation resembles the 9643 * second-half of the __igb_resume routine. 9644 */ 9645 static void igb_io_resume(struct pci_dev *pdev) 9646 { 9647 struct net_device *netdev = pci_get_drvdata(pdev); 9648 struct igb_adapter *adapter = netdev_priv(netdev); 9649 9650 if (netif_running(netdev)) { 9651 if (igb_up(adapter)) { 9652 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9653 return; 9654 } 9655 } 9656 9657 netif_device_attach(netdev); 9658 9659 /* let the f/w know that the h/w is now under the control of the 9660 * driver. 9661 */ 9662 igb_get_hw_control(adapter); 9663 } 9664 9665 /** 9666 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9667 * @adapter: Pointer to adapter structure 9668 * @index: Index of the RAR entry which need to be synced with MAC table 9669 **/ 9670 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9671 { 9672 struct e1000_hw *hw = &adapter->hw; 9673 u32 rar_low, rar_high; 9674 u8 *addr = adapter->mac_table[index].addr; 9675 9676 /* HW expects these to be in network order when they are plugged 9677 * into the registers which are little endian. In order to guarantee 9678 * that ordering we need to do an leXX_to_cpup here in order to be 9679 * ready for the byteswap that occurs with writel 9680 */ 9681 rar_low = le32_to_cpup((__le32 *)(addr)); 9682 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9683 9684 /* Indicate to hardware the Address is Valid. */ 9685 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9686 if (is_valid_ether_addr(addr)) 9687 rar_high |= E1000_RAH_AV; 9688 9689 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9690 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9691 9692 switch (hw->mac.type) { 9693 case e1000_82575: 9694 case e1000_i210: 9695 if (adapter->mac_table[index].state & 9696 IGB_MAC_STATE_QUEUE_STEERING) 9697 rar_high |= E1000_RAH_QSEL_ENABLE; 9698 9699 rar_high |= E1000_RAH_POOL_1 * 9700 adapter->mac_table[index].queue; 9701 break; 9702 default: 9703 rar_high |= E1000_RAH_POOL_1 << 9704 adapter->mac_table[index].queue; 9705 break; 9706 } 9707 } 9708 9709 wr32(E1000_RAL(index), rar_low); 9710 wrfl(); 9711 wr32(E1000_RAH(index), rar_high); 9712 wrfl(); 9713 } 9714 9715 static int igb_set_vf_mac(struct igb_adapter *adapter, 9716 int vf, unsigned char *mac_addr) 9717 { 9718 struct e1000_hw *hw = &adapter->hw; 9719 /* VF MAC addresses start at end of receive addresses and moves 9720 * towards the first, as a result a collision should not be possible 9721 */ 9722 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9723 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9724 9725 ether_addr_copy(vf_mac_addr, mac_addr); 9726 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9727 adapter->mac_table[rar_entry].queue = vf; 9728 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9729 igb_rar_set_index(adapter, rar_entry); 9730 9731 return 0; 9732 } 9733 9734 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9735 { 9736 struct igb_adapter *adapter = netdev_priv(netdev); 9737 9738 if (vf >= adapter->vfs_allocated_count) 9739 return -EINVAL; 9740 9741 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9742 * flag and allows to overwrite the MAC via VF netdev. This 9743 * is necessary to allow libvirt a way to restore the original 9744 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9745 * down a VM. 9746 */ 9747 if (is_zero_ether_addr(mac)) { 9748 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9749 dev_info(&adapter->pdev->dev, 9750 "remove administratively set MAC on VF %d\n", 9751 vf); 9752 } else if (is_valid_ether_addr(mac)) { 9753 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9754 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9755 mac, vf); 9756 dev_info(&adapter->pdev->dev, 9757 "Reload the VF driver to make this change effective."); 9758 /* Generate additional warning if PF is down */ 9759 if (test_bit(__IGB_DOWN, &adapter->state)) { 9760 dev_warn(&adapter->pdev->dev, 9761 "The VF MAC address has been set, but the PF device is not up.\n"); 9762 dev_warn(&adapter->pdev->dev, 9763 "Bring the PF device up before attempting to use the VF device.\n"); 9764 } 9765 } else { 9766 return -EINVAL; 9767 } 9768 return igb_set_vf_mac(adapter, vf, mac); 9769 } 9770 9771 static int igb_link_mbps(int internal_link_speed) 9772 { 9773 switch (internal_link_speed) { 9774 case SPEED_100: 9775 return 100; 9776 case SPEED_1000: 9777 return 1000; 9778 default: 9779 return 0; 9780 } 9781 } 9782 9783 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9784 int link_speed) 9785 { 9786 int rf_dec, rf_int; 9787 u32 bcnrc_val; 9788 9789 if (tx_rate != 0) { 9790 /* Calculate the rate factor values to set */ 9791 rf_int = link_speed / tx_rate; 9792 rf_dec = (link_speed - (rf_int * tx_rate)); 9793 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9794 tx_rate; 9795 9796 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9797 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9798 E1000_RTTBCNRC_RF_INT_MASK); 9799 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9800 } else { 9801 bcnrc_val = 0; 9802 } 9803 9804 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9805 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9806 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9807 */ 9808 wr32(E1000_RTTBCNRM, 0x14); 9809 wr32(E1000_RTTBCNRC, bcnrc_val); 9810 } 9811 9812 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9813 { 9814 int actual_link_speed, i; 9815 bool reset_rate = false; 9816 9817 /* VF TX rate limit was not set or not supported */ 9818 if ((adapter->vf_rate_link_speed == 0) || 9819 (adapter->hw.mac.type != e1000_82576)) 9820 return; 9821 9822 actual_link_speed = igb_link_mbps(adapter->link_speed); 9823 if (actual_link_speed != adapter->vf_rate_link_speed) { 9824 reset_rate = true; 9825 adapter->vf_rate_link_speed = 0; 9826 dev_info(&adapter->pdev->dev, 9827 "Link speed has been changed. VF Transmit rate is disabled\n"); 9828 } 9829 9830 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9831 if (reset_rate) 9832 adapter->vf_data[i].tx_rate = 0; 9833 9834 igb_set_vf_rate_limit(&adapter->hw, i, 9835 adapter->vf_data[i].tx_rate, 9836 actual_link_speed); 9837 } 9838 } 9839 9840 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9841 int min_tx_rate, int max_tx_rate) 9842 { 9843 struct igb_adapter *adapter = netdev_priv(netdev); 9844 struct e1000_hw *hw = &adapter->hw; 9845 int actual_link_speed; 9846 9847 if (hw->mac.type != e1000_82576) 9848 return -EOPNOTSUPP; 9849 9850 if (min_tx_rate) 9851 return -EINVAL; 9852 9853 actual_link_speed = igb_link_mbps(adapter->link_speed); 9854 if ((vf >= adapter->vfs_allocated_count) || 9855 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9856 (max_tx_rate < 0) || 9857 (max_tx_rate > actual_link_speed)) 9858 return -EINVAL; 9859 9860 adapter->vf_rate_link_speed = actual_link_speed; 9861 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9862 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9863 9864 return 0; 9865 } 9866 9867 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9868 bool setting) 9869 { 9870 struct igb_adapter *adapter = netdev_priv(netdev); 9871 struct e1000_hw *hw = &adapter->hw; 9872 u32 reg_val, reg_offset; 9873 9874 if (!adapter->vfs_allocated_count) 9875 return -EOPNOTSUPP; 9876 9877 if (vf >= adapter->vfs_allocated_count) 9878 return -EINVAL; 9879 9880 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9881 reg_val = rd32(reg_offset); 9882 if (setting) 9883 reg_val |= (BIT(vf) | 9884 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9885 else 9886 reg_val &= ~(BIT(vf) | 9887 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9888 wr32(reg_offset, reg_val); 9889 9890 adapter->vf_data[vf].spoofchk_enabled = setting; 9891 return 0; 9892 } 9893 9894 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9895 { 9896 struct igb_adapter *adapter = netdev_priv(netdev); 9897 9898 if (vf >= adapter->vfs_allocated_count) 9899 return -EINVAL; 9900 if (adapter->vf_data[vf].trusted == setting) 9901 return 0; 9902 9903 adapter->vf_data[vf].trusted = setting; 9904 9905 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9906 vf, setting ? "" : "not "); 9907 return 0; 9908 } 9909 9910 static int igb_ndo_get_vf_config(struct net_device *netdev, 9911 int vf, struct ifla_vf_info *ivi) 9912 { 9913 struct igb_adapter *adapter = netdev_priv(netdev); 9914 if (vf >= adapter->vfs_allocated_count) 9915 return -EINVAL; 9916 ivi->vf = vf; 9917 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9918 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9919 ivi->min_tx_rate = 0; 9920 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9921 ivi->qos = adapter->vf_data[vf].pf_qos; 9922 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9923 ivi->trusted = adapter->vf_data[vf].trusted; 9924 return 0; 9925 } 9926 9927 static void igb_vmm_control(struct igb_adapter *adapter) 9928 { 9929 struct e1000_hw *hw = &adapter->hw; 9930 u32 reg; 9931 9932 switch (hw->mac.type) { 9933 case e1000_82575: 9934 case e1000_i210: 9935 case e1000_i211: 9936 case e1000_i354: 9937 default: 9938 /* replication is not supported for 82575 */ 9939 return; 9940 case e1000_82576: 9941 /* notify HW that the MAC is adding vlan tags */ 9942 reg = rd32(E1000_DTXCTL); 9943 reg |= E1000_DTXCTL_VLAN_ADDED; 9944 wr32(E1000_DTXCTL, reg); 9945 fallthrough; 9946 case e1000_82580: 9947 /* enable replication vlan tag stripping */ 9948 reg = rd32(E1000_RPLOLR); 9949 reg |= E1000_RPLOLR_STRVLAN; 9950 wr32(E1000_RPLOLR, reg); 9951 fallthrough; 9952 case e1000_i350: 9953 /* none of the above registers are supported by i350 */ 9954 break; 9955 } 9956 9957 if (adapter->vfs_allocated_count) { 9958 igb_vmdq_set_loopback_pf(hw, true); 9959 igb_vmdq_set_replication_pf(hw, true); 9960 igb_vmdq_set_anti_spoofing_pf(hw, true, 9961 adapter->vfs_allocated_count); 9962 } else { 9963 igb_vmdq_set_loopback_pf(hw, false); 9964 igb_vmdq_set_replication_pf(hw, false); 9965 } 9966 } 9967 9968 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9969 { 9970 struct e1000_hw *hw = &adapter->hw; 9971 u32 dmac_thr; 9972 u16 hwm; 9973 u32 reg; 9974 9975 if (hw->mac.type > e1000_82580) { 9976 if (adapter->flags & IGB_FLAG_DMAC) { 9977 /* force threshold to 0. */ 9978 wr32(E1000_DMCTXTH, 0); 9979 9980 /* DMA Coalescing high water mark needs to be greater 9981 * than the Rx threshold. Set hwm to PBA - max frame 9982 * size in 16B units, capping it at PBA - 6KB. 9983 */ 9984 hwm = 64 * (pba - 6); 9985 reg = rd32(E1000_FCRTC); 9986 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9987 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9988 & E1000_FCRTC_RTH_COAL_MASK); 9989 wr32(E1000_FCRTC, reg); 9990 9991 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9992 * frame size, capping it at PBA - 10KB. 9993 */ 9994 dmac_thr = pba - 10; 9995 reg = rd32(E1000_DMACR); 9996 reg &= ~E1000_DMACR_DMACTHR_MASK; 9997 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9998 & E1000_DMACR_DMACTHR_MASK); 9999 10000 /* transition to L0x or L1 if available..*/ 10001 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10002 10003 /* watchdog timer= +-1000 usec in 32usec intervals */ 10004 reg |= (1000 >> 5); 10005 10006 /* Disable BMC-to-OS Watchdog Enable */ 10007 if (hw->mac.type != e1000_i354) 10008 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10009 wr32(E1000_DMACR, reg); 10010 10011 /* no lower threshold to disable 10012 * coalescing(smart fifb)-UTRESH=0 10013 */ 10014 wr32(E1000_DMCRTRH, 0); 10015 10016 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10017 10018 wr32(E1000_DMCTLX, reg); 10019 10020 /* free space in tx packet buffer to wake from 10021 * DMA coal 10022 */ 10023 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10024 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10025 } 10026 10027 if (hw->mac.type >= e1000_i210 || 10028 (adapter->flags & IGB_FLAG_DMAC)) { 10029 reg = rd32(E1000_PCIEMISC); 10030 reg |= E1000_PCIEMISC_LX_DECISION; 10031 wr32(E1000_PCIEMISC, reg); 10032 } /* endif adapter->dmac is not disabled */ 10033 } else if (hw->mac.type == e1000_82580) { 10034 u32 reg = rd32(E1000_PCIEMISC); 10035 10036 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10037 wr32(E1000_DMACR, 0); 10038 } 10039 } 10040 10041 /** 10042 * igb_read_i2c_byte - Reads 8 bit word over I2C 10043 * @hw: pointer to hardware structure 10044 * @byte_offset: byte offset to read 10045 * @dev_addr: device address 10046 * @data: value read 10047 * 10048 * Performs byte read operation over I2C interface at 10049 * a specified device address. 10050 **/ 10051 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10052 u8 dev_addr, u8 *data) 10053 { 10054 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10055 struct i2c_client *this_client = adapter->i2c_client; 10056 s32 status; 10057 u16 swfw_mask = 0; 10058 10059 if (!this_client) 10060 return E1000_ERR_I2C; 10061 10062 swfw_mask = E1000_SWFW_PHY0_SM; 10063 10064 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10065 return E1000_ERR_SWFW_SYNC; 10066 10067 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10068 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10069 10070 if (status < 0) 10071 return E1000_ERR_I2C; 10072 else { 10073 *data = status; 10074 return 0; 10075 } 10076 } 10077 10078 /** 10079 * igb_write_i2c_byte - Writes 8 bit word over I2C 10080 * @hw: pointer to hardware structure 10081 * @byte_offset: byte offset to write 10082 * @dev_addr: device address 10083 * @data: value to write 10084 * 10085 * Performs byte write operation over I2C interface at 10086 * a specified device address. 10087 **/ 10088 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10089 u8 dev_addr, u8 data) 10090 { 10091 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10092 struct i2c_client *this_client = adapter->i2c_client; 10093 s32 status; 10094 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10095 10096 if (!this_client) 10097 return E1000_ERR_I2C; 10098 10099 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10100 return E1000_ERR_SWFW_SYNC; 10101 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10102 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10103 10104 if (status) 10105 return E1000_ERR_I2C; 10106 else 10107 return 0; 10108 10109 } 10110 10111 int igb_reinit_queues(struct igb_adapter *adapter) 10112 { 10113 struct net_device *netdev = adapter->netdev; 10114 struct pci_dev *pdev = adapter->pdev; 10115 int err = 0; 10116 10117 if (netif_running(netdev)) 10118 igb_close(netdev); 10119 10120 igb_reset_interrupt_capability(adapter); 10121 10122 if (igb_init_interrupt_scheme(adapter, true)) { 10123 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10124 return -ENOMEM; 10125 } 10126 10127 if (netif_running(netdev)) 10128 err = igb_open(netdev); 10129 10130 return err; 10131 } 10132 10133 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10134 { 10135 struct igb_nfc_filter *rule; 10136 10137 spin_lock(&adapter->nfc_lock); 10138 10139 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10140 igb_erase_filter(adapter, rule); 10141 10142 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10143 igb_erase_filter(adapter, rule); 10144 10145 spin_unlock(&adapter->nfc_lock); 10146 } 10147 10148 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10149 { 10150 struct igb_nfc_filter *rule; 10151 10152 spin_lock(&adapter->nfc_lock); 10153 10154 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10155 igb_add_filter(adapter, rule); 10156 10157 spin_unlock(&adapter->nfc_lock); 10158 } 10159 /* igb_main.c */ 10160