1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #ifdef CONFIG_IGB_DCA 54 #include <linux/dca.h> 55 #endif 56 #include <linux/i2c.h> 57 #include "igb.h" 58 59 #define MAJ 5 60 #define MIN 2 61 #define BUILD 15 62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 63 __stringify(BUILD) "-k" 64 char igb_driver_name[] = "igb"; 65 char igb_driver_version[] = DRV_VERSION; 66 static const char igb_driver_string[] = 67 "Intel(R) Gigabit Ethernet Network Driver"; 68 static const char igb_copyright[] = 69 "Copyright (c) 2007-2014 Intel Corporation."; 70 71 static const struct e1000_info *igb_info_tbl[] = { 72 [board_82575] = &e1000_82575_info, 73 }; 74 75 static const struct pci_device_id igb_pci_tbl[] = { 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 111 /* required last entry */ 112 {0, } 113 }; 114 115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 116 117 static int igb_setup_all_tx_resources(struct igb_adapter *); 118 static int igb_setup_all_rx_resources(struct igb_adapter *); 119 static void igb_free_all_tx_resources(struct igb_adapter *); 120 static void igb_free_all_rx_resources(struct igb_adapter *); 121 static void igb_setup_mrqc(struct igb_adapter *); 122 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 123 static void igb_remove(struct pci_dev *pdev); 124 static int igb_sw_init(struct igb_adapter *); 125 static int igb_open(struct net_device *); 126 static int igb_close(struct net_device *); 127 static void igb_configure(struct igb_adapter *); 128 static void igb_configure_tx(struct igb_adapter *); 129 static void igb_configure_rx(struct igb_adapter *); 130 static void igb_clean_all_tx_rings(struct igb_adapter *); 131 static void igb_clean_all_rx_rings(struct igb_adapter *); 132 static void igb_clean_tx_ring(struct igb_ring *); 133 static void igb_clean_rx_ring(struct igb_ring *); 134 static void igb_set_rx_mode(struct net_device *); 135 static void igb_update_phy_info(unsigned long); 136 static void igb_watchdog(unsigned long); 137 static void igb_watchdog_task(struct work_struct *); 138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 140 struct rtnl_link_stats64 *stats); 141 static int igb_change_mtu(struct net_device *, int); 142 static int igb_set_mac(struct net_device *, void *); 143 static void igb_set_uta(struct igb_adapter *adapter); 144 static irqreturn_t igb_intr(int irq, void *); 145 static irqreturn_t igb_intr_msi(int irq, void *); 146 static irqreturn_t igb_msix_other(int irq, void *); 147 static irqreturn_t igb_msix_ring(int irq, void *); 148 #ifdef CONFIG_IGB_DCA 149 static void igb_update_dca(struct igb_q_vector *); 150 static void igb_setup_dca(struct igb_adapter *); 151 #endif /* CONFIG_IGB_DCA */ 152 static int igb_poll(struct napi_struct *, int); 153 static bool igb_clean_tx_irq(struct igb_q_vector *); 154 static bool igb_clean_rx_irq(struct igb_q_vector *, int); 155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 156 static void igb_tx_timeout(struct net_device *); 157 static void igb_reset_task(struct work_struct *); 158 static void igb_vlan_mode(struct net_device *netdev, 159 netdev_features_t features); 160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 162 static void igb_restore_vlan(struct igb_adapter *); 163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 164 static void igb_ping_all_vfs(struct igb_adapter *); 165 static void igb_msg_task(struct igb_adapter *); 166 static void igb_vmm_control(struct igb_adapter *); 167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 170 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 171 int vf, u16 vlan, u8 qos); 172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 174 bool setting); 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177 static void igb_check_vf_rate_limit(struct igb_adapter *); 178 179 #ifdef CONFIG_PCI_IOV 180 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 182 #endif 183 184 #ifdef CONFIG_PM 185 #ifdef CONFIG_PM_SLEEP 186 static int igb_suspend(struct device *); 187 #endif 188 static int igb_resume(struct device *); 189 static int igb_runtime_suspend(struct device *dev); 190 static int igb_runtime_resume(struct device *dev); 191 static int igb_runtime_idle(struct device *dev); 192 static const struct dev_pm_ops igb_pm_ops = { 193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 195 igb_runtime_idle) 196 }; 197 #endif 198 static void igb_shutdown(struct pci_dev *); 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 200 #ifdef CONFIG_IGB_DCA 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 202 static struct notifier_block dca_notifier = { 203 .notifier_call = igb_notify_dca, 204 .next = NULL, 205 .priority = 0 206 }; 207 #endif 208 #ifdef CONFIG_NET_POLL_CONTROLLER 209 /* for netdump / net console */ 210 static void igb_netpoll(struct net_device *); 211 #endif 212 #ifdef CONFIG_PCI_IOV 213 static unsigned int max_vfs; 214 module_param(max_vfs, uint, 0); 215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 216 #endif /* CONFIG_PCI_IOV */ 217 218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 219 pci_channel_state_t); 220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 221 static void igb_io_resume(struct pci_dev *); 222 223 static const struct pci_error_handlers igb_err_handler = { 224 .error_detected = igb_io_error_detected, 225 .slot_reset = igb_io_slot_reset, 226 .resume = igb_io_resume, 227 }; 228 229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 230 231 static struct pci_driver igb_driver = { 232 .name = igb_driver_name, 233 .id_table = igb_pci_tbl, 234 .probe = igb_probe, 235 .remove = igb_remove, 236 #ifdef CONFIG_PM 237 .driver.pm = &igb_pm_ops, 238 #endif 239 .shutdown = igb_shutdown, 240 .sriov_configure = igb_pci_sriov_configure, 241 .err_handler = &igb_err_handler 242 }; 243 244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 246 MODULE_LICENSE("GPL"); 247 MODULE_VERSION(DRV_VERSION); 248 249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 250 static int debug = -1; 251 module_param(debug, int, 0); 252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 253 254 struct igb_reg_info { 255 u32 ofs; 256 char *name; 257 }; 258 259 static const struct igb_reg_info igb_reg_info_tbl[] = { 260 261 /* General Registers */ 262 {E1000_CTRL, "CTRL"}, 263 {E1000_STATUS, "STATUS"}, 264 {E1000_CTRL_EXT, "CTRL_EXT"}, 265 266 /* Interrupt Registers */ 267 {E1000_ICR, "ICR"}, 268 269 /* RX Registers */ 270 {E1000_RCTL, "RCTL"}, 271 {E1000_RDLEN(0), "RDLEN"}, 272 {E1000_RDH(0), "RDH"}, 273 {E1000_RDT(0), "RDT"}, 274 {E1000_RXDCTL(0), "RXDCTL"}, 275 {E1000_RDBAL(0), "RDBAL"}, 276 {E1000_RDBAH(0), "RDBAH"}, 277 278 /* TX Registers */ 279 {E1000_TCTL, "TCTL"}, 280 {E1000_TDBAL(0), "TDBAL"}, 281 {E1000_TDBAH(0), "TDBAH"}, 282 {E1000_TDLEN(0), "TDLEN"}, 283 {E1000_TDH(0), "TDH"}, 284 {E1000_TDT(0), "TDT"}, 285 {E1000_TXDCTL(0), "TXDCTL"}, 286 {E1000_TDFH, "TDFH"}, 287 {E1000_TDFT, "TDFT"}, 288 {E1000_TDFHS, "TDFHS"}, 289 {E1000_TDFPC, "TDFPC"}, 290 291 /* List Terminator */ 292 {} 293 }; 294 295 /* igb_regdump - register printout routine */ 296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 297 { 298 int n = 0; 299 char rname[16]; 300 u32 regs[8]; 301 302 switch (reginfo->ofs) { 303 case E1000_RDLEN(0): 304 for (n = 0; n < 4; n++) 305 regs[n] = rd32(E1000_RDLEN(n)); 306 break; 307 case E1000_RDH(0): 308 for (n = 0; n < 4; n++) 309 regs[n] = rd32(E1000_RDH(n)); 310 break; 311 case E1000_RDT(0): 312 for (n = 0; n < 4; n++) 313 regs[n] = rd32(E1000_RDT(n)); 314 break; 315 case E1000_RXDCTL(0): 316 for (n = 0; n < 4; n++) 317 regs[n] = rd32(E1000_RXDCTL(n)); 318 break; 319 case E1000_RDBAL(0): 320 for (n = 0; n < 4; n++) 321 regs[n] = rd32(E1000_RDBAL(n)); 322 break; 323 case E1000_RDBAH(0): 324 for (n = 0; n < 4; n++) 325 regs[n] = rd32(E1000_RDBAH(n)); 326 break; 327 case E1000_TDBAL(0): 328 for (n = 0; n < 4; n++) 329 regs[n] = rd32(E1000_RDBAL(n)); 330 break; 331 case E1000_TDBAH(0): 332 for (n = 0; n < 4; n++) 333 regs[n] = rd32(E1000_TDBAH(n)); 334 break; 335 case E1000_TDLEN(0): 336 for (n = 0; n < 4; n++) 337 regs[n] = rd32(E1000_TDLEN(n)); 338 break; 339 case E1000_TDH(0): 340 for (n = 0; n < 4; n++) 341 regs[n] = rd32(E1000_TDH(n)); 342 break; 343 case E1000_TDT(0): 344 for (n = 0; n < 4; n++) 345 regs[n] = rd32(E1000_TDT(n)); 346 break; 347 case E1000_TXDCTL(0): 348 for (n = 0; n < 4; n++) 349 regs[n] = rd32(E1000_TXDCTL(n)); 350 break; 351 default: 352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 353 return; 354 } 355 356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 358 regs[2], regs[3]); 359 } 360 361 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 362 static void igb_dump(struct igb_adapter *adapter) 363 { 364 struct net_device *netdev = adapter->netdev; 365 struct e1000_hw *hw = &adapter->hw; 366 struct igb_reg_info *reginfo; 367 struct igb_ring *tx_ring; 368 union e1000_adv_tx_desc *tx_desc; 369 struct my_u0 { u64 a; u64 b; } *u0; 370 struct igb_ring *rx_ring; 371 union e1000_adv_rx_desc *rx_desc; 372 u32 staterr; 373 u16 i, n; 374 375 if (!netif_msg_hw(adapter)) 376 return; 377 378 /* Print netdevice Info */ 379 if (netdev) { 380 dev_info(&adapter->pdev->dev, "Net device Info\n"); 381 pr_info("Device Name state trans_start last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)dma_unmap_addr(buffer_info, dma), 407 dma_unmap_len(buffer_info, len), 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 435 436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 437 const char *next_desc; 438 struct igb_tx_buffer *buffer_info; 439 tx_desc = IGB_TX_DESC(tx_ring, i); 440 buffer_info = &tx_ring->tx_buffer_info[i]; 441 u0 = (struct my_u0 *)tx_desc; 442 if (i == tx_ring->next_to_use && 443 i == tx_ring->next_to_clean) 444 next_desc = " NTC/U"; 445 else if (i == tx_ring->next_to_use) 446 next_desc = " NTU"; 447 else if (i == tx_ring->next_to_clean) 448 next_desc = " NTC"; 449 else 450 next_desc = ""; 451 452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 453 i, le64_to_cpu(u0->a), 454 le64_to_cpu(u0->b), 455 (u64)dma_unmap_addr(buffer_info, dma), 456 dma_unmap_len(buffer_info, len), 457 buffer_info->next_to_watch, 458 (u64)buffer_info->time_stamp, 459 buffer_info->skb, next_desc); 460 461 if (netif_msg_pktdata(adapter) && buffer_info->skb) 462 print_hex_dump(KERN_INFO, "", 463 DUMP_PREFIX_ADDRESS, 464 16, 1, buffer_info->skb->data, 465 dma_unmap_len(buffer_info, len), 466 true); 467 } 468 } 469 470 /* Print RX Rings Summary */ 471 rx_ring_summary: 472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 473 pr_info("Queue [NTU] [NTC]\n"); 474 for (n = 0; n < adapter->num_rx_queues; n++) { 475 rx_ring = adapter->rx_ring[n]; 476 pr_info(" %5d %5X %5X\n", 477 n, rx_ring->next_to_use, rx_ring->next_to_clean); 478 } 479 480 /* Print RX Rings */ 481 if (!netif_msg_rx_status(adapter)) 482 goto exit; 483 484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 485 486 /* Advanced Receive Descriptor (Read) Format 487 * 63 1 0 488 * +-----------------------------------------------------+ 489 * 0 | Packet Buffer Address [63:1] |A0/NSE| 490 * +----------------------------------------------+------+ 491 * 8 | Header Buffer Address [63:1] | DD | 492 * +-----------------------------------------------------+ 493 * 494 * 495 * Advanced Receive Descriptor (Write-Back) Format 496 * 497 * 63 48 47 32 31 30 21 20 17 16 4 3 0 498 * +------------------------------------------------------+ 499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 500 * | Checksum Ident | | | | Type | Type | 501 * +------------------------------------------------------+ 502 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 503 * +------------------------------------------------------+ 504 * 63 48 47 32 31 20 19 0 505 */ 506 507 for (n = 0; n < adapter->num_rx_queues; n++) { 508 rx_ring = adapter->rx_ring[n]; 509 pr_info("------------------------------------\n"); 510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 511 pr_info("------------------------------------\n"); 512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 514 515 for (i = 0; i < rx_ring->count; i++) { 516 const char *next_desc; 517 struct igb_rx_buffer *buffer_info; 518 buffer_info = &rx_ring->rx_buffer_info[i]; 519 rx_desc = IGB_RX_DESC(rx_ring, i); 520 u0 = (struct my_u0 *)rx_desc; 521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 522 523 if (i == rx_ring->next_to_use) 524 next_desc = " NTU"; 525 else if (i == rx_ring->next_to_clean) 526 next_desc = " NTC"; 527 else 528 next_desc = ""; 529 530 if (staterr & E1000_RXD_STAT_DD) { 531 /* Descriptor Done */ 532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 533 "RWB", i, 534 le64_to_cpu(u0->a), 535 le64_to_cpu(u0->b), 536 next_desc); 537 } else { 538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 539 "R ", i, 540 le64_to_cpu(u0->a), 541 le64_to_cpu(u0->b), 542 (u64)buffer_info->dma, 543 next_desc); 544 545 if (netif_msg_pktdata(adapter) && 546 buffer_info->dma && buffer_info->page) { 547 print_hex_dump(KERN_INFO, "", 548 DUMP_PREFIX_ADDRESS, 549 16, 1, 550 page_address(buffer_info->page) + 551 buffer_info->page_offset, 552 IGB_RX_BUFSZ, true); 553 } 554 } 555 } 556 } 557 558 exit: 559 return; 560 } 561 562 /** 563 * igb_get_i2c_data - Reads the I2C SDA data bit 564 * @hw: pointer to hardware structure 565 * @i2cctl: Current value of I2CCTL register 566 * 567 * Returns the I2C data bit value 568 **/ 569 static int igb_get_i2c_data(void *data) 570 { 571 struct igb_adapter *adapter = (struct igb_adapter *)data; 572 struct e1000_hw *hw = &adapter->hw; 573 s32 i2cctl = rd32(E1000_I2CPARAMS); 574 575 return !!(i2cctl & E1000_I2C_DATA_IN); 576 } 577 578 /** 579 * igb_set_i2c_data - Sets the I2C data bit 580 * @data: pointer to hardware structure 581 * @state: I2C data value (0 or 1) to set 582 * 583 * Sets the I2C data bit 584 **/ 585 static void igb_set_i2c_data(void *data, int state) 586 { 587 struct igb_adapter *adapter = (struct igb_adapter *)data; 588 struct e1000_hw *hw = &adapter->hw; 589 s32 i2cctl = rd32(E1000_I2CPARAMS); 590 591 if (state) 592 i2cctl |= E1000_I2C_DATA_OUT; 593 else 594 i2cctl &= ~E1000_I2C_DATA_OUT; 595 596 i2cctl &= ~E1000_I2C_DATA_OE_N; 597 i2cctl |= E1000_I2C_CLK_OE_N; 598 wr32(E1000_I2CPARAMS, i2cctl); 599 wrfl(); 600 601 } 602 603 /** 604 * igb_set_i2c_clk - Sets the I2C SCL clock 605 * @data: pointer to hardware structure 606 * @state: state to set clock 607 * 608 * Sets the I2C clock line to state 609 **/ 610 static void igb_set_i2c_clk(void *data, int state) 611 { 612 struct igb_adapter *adapter = (struct igb_adapter *)data; 613 struct e1000_hw *hw = &adapter->hw; 614 s32 i2cctl = rd32(E1000_I2CPARAMS); 615 616 if (state) { 617 i2cctl |= E1000_I2C_CLK_OUT; 618 i2cctl &= ~E1000_I2C_CLK_OE_N; 619 } else { 620 i2cctl &= ~E1000_I2C_CLK_OUT; 621 i2cctl &= ~E1000_I2C_CLK_OE_N; 622 } 623 wr32(E1000_I2CPARAMS, i2cctl); 624 wrfl(); 625 } 626 627 /** 628 * igb_get_i2c_clk - Gets the I2C SCL clock state 629 * @data: pointer to hardware structure 630 * 631 * Gets the I2C clock state 632 **/ 633 static int igb_get_i2c_clk(void *data) 634 { 635 struct igb_adapter *adapter = (struct igb_adapter *)data; 636 struct e1000_hw *hw = &adapter->hw; 637 s32 i2cctl = rd32(E1000_I2CPARAMS); 638 639 return !!(i2cctl & E1000_I2C_CLK_IN); 640 } 641 642 static const struct i2c_algo_bit_data igb_i2c_algo = { 643 .setsda = igb_set_i2c_data, 644 .setscl = igb_set_i2c_clk, 645 .getsda = igb_get_i2c_data, 646 .getscl = igb_get_i2c_clk, 647 .udelay = 5, 648 .timeout = 20, 649 }; 650 651 /** 652 * igb_get_hw_dev - return device 653 * @hw: pointer to hardware structure 654 * 655 * used by hardware layer to print debugging information 656 **/ 657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 658 { 659 struct igb_adapter *adapter = hw->back; 660 return adapter->netdev; 661 } 662 663 /** 664 * igb_init_module - Driver Registration Routine 665 * 666 * igb_init_module is the first routine called when the driver is 667 * loaded. All it does is register with the PCI subsystem. 668 **/ 669 static int __init igb_init_module(void) 670 { 671 int ret; 672 673 pr_info("%s - version %s\n", 674 igb_driver_string, igb_driver_version); 675 pr_info("%s\n", igb_copyright); 676 677 #ifdef CONFIG_IGB_DCA 678 dca_register_notify(&dca_notifier); 679 #endif 680 ret = pci_register_driver(&igb_driver); 681 return ret; 682 } 683 684 module_init(igb_init_module); 685 686 /** 687 * igb_exit_module - Driver Exit Cleanup Routine 688 * 689 * igb_exit_module is called just before the driver is removed 690 * from memory. 691 **/ 692 static void __exit igb_exit_module(void) 693 { 694 #ifdef CONFIG_IGB_DCA 695 dca_unregister_notify(&dca_notifier); 696 #endif 697 pci_unregister_driver(&igb_driver); 698 } 699 700 module_exit(igb_exit_module); 701 702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 703 /** 704 * igb_cache_ring_register - Descriptor ring to register mapping 705 * @adapter: board private structure to initialize 706 * 707 * Once we know the feature-set enabled for the device, we'll cache 708 * the register offset the descriptor ring is assigned to. 709 **/ 710 static void igb_cache_ring_register(struct igb_adapter *adapter) 711 { 712 int i = 0, j = 0; 713 u32 rbase_offset = adapter->vfs_allocated_count; 714 715 switch (adapter->hw.mac.type) { 716 case e1000_82576: 717 /* The queues are allocated for virtualization such that VF 0 718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 719 * In order to avoid collision we start at the first free queue 720 * and continue consuming queues in the same sequence 721 */ 722 if (adapter->vfs_allocated_count) { 723 for (; i < adapter->rss_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + 725 Q_IDX_82576(i); 726 } 727 /* Fall through */ 728 case e1000_82575: 729 case e1000_82580: 730 case e1000_i350: 731 case e1000_i354: 732 case e1000_i210: 733 case e1000_i211: 734 /* Fall through */ 735 default: 736 for (; i < adapter->num_rx_queues; i++) 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 738 for (; j < adapter->num_tx_queues; j++) 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 740 break; 741 } 742 } 743 744 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 745 { 746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 748 u32 value = 0; 749 750 if (E1000_REMOVED(hw_addr)) 751 return ~value; 752 753 value = readl(&hw_addr[reg]); 754 755 /* reads should not return all F's */ 756 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 757 struct net_device *netdev = igb->netdev; 758 hw->hw_addr = NULL; 759 netif_device_detach(netdev); 760 netdev_err(netdev, "PCIe link lost, device now detached\n"); 761 } 762 763 return value; 764 } 765 766 /** 767 * igb_write_ivar - configure ivar for given MSI-X vector 768 * @hw: pointer to the HW structure 769 * @msix_vector: vector number we are allocating to a given ring 770 * @index: row index of IVAR register to write within IVAR table 771 * @offset: column offset of in IVAR, should be multiple of 8 772 * 773 * This function is intended to handle the writing of the IVAR register 774 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 775 * each containing an cause allocation for an Rx and Tx ring, and a 776 * variable number of rows depending on the number of queues supported. 777 **/ 778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 779 int index, int offset) 780 { 781 u32 ivar = array_rd32(E1000_IVAR0, index); 782 783 /* clear any bits that are currently set */ 784 ivar &= ~((u32)0xFF << offset); 785 786 /* write vector and valid bit */ 787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 788 789 array_wr32(E1000_IVAR0, index, ivar); 790 } 791 792 #define IGB_N0_QUEUE -1 793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 794 { 795 struct igb_adapter *adapter = q_vector->adapter; 796 struct e1000_hw *hw = &adapter->hw; 797 int rx_queue = IGB_N0_QUEUE; 798 int tx_queue = IGB_N0_QUEUE; 799 u32 msixbm = 0; 800 801 if (q_vector->rx.ring) 802 rx_queue = q_vector->rx.ring->reg_idx; 803 if (q_vector->tx.ring) 804 tx_queue = q_vector->tx.ring->reg_idx; 805 806 switch (hw->mac.type) { 807 case e1000_82575: 808 /* The 82575 assigns vectors using a bitmask, which matches the 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one 810 * or more queues to a vector, we write the appropriate bits 811 * into the MSIXBM register for that vector. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 815 if (tx_queue > IGB_N0_QUEUE) 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 818 msixbm |= E1000_EIMS_OTHER; 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 820 q_vector->eims_value = msixbm; 821 break; 822 case e1000_82576: 823 /* 82576 uses a table that essentially consists of 2 columns 824 * with 8 rows. The ordering is column-major so we use the 825 * lower 3 bits as the row index, and the 4th bit as the 826 * column offset. 827 */ 828 if (rx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 rx_queue & 0x7, 831 (rx_queue & 0x8) << 1); 832 if (tx_queue > IGB_N0_QUEUE) 833 igb_write_ivar(hw, msix_vector, 834 tx_queue & 0x7, 835 ((tx_queue & 0x8) << 1) + 8); 836 q_vector->eims_value = 1 << msix_vector; 837 break; 838 case e1000_82580: 839 case e1000_i350: 840 case e1000_i354: 841 case e1000_i210: 842 case e1000_i211: 843 /* On 82580 and newer adapters the scheme is similar to 82576 844 * however instead of ordering column-major we have things 845 * ordered row-major. So we traverse the table by using 846 * bit 0 as the column offset, and the remaining bits as the 847 * row index. 848 */ 849 if (rx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 rx_queue >> 1, 852 (rx_queue & 0x1) << 4); 853 if (tx_queue > IGB_N0_QUEUE) 854 igb_write_ivar(hw, msix_vector, 855 tx_queue >> 1, 856 ((tx_queue & 0x1) << 4) + 8); 857 q_vector->eims_value = 1 << msix_vector; 858 break; 859 default: 860 BUG(); 861 break; 862 } 863 864 /* add q_vector eims value to global eims_enable_mask */ 865 adapter->eims_enable_mask |= q_vector->eims_value; 866 867 /* configure q_vector to set itr on first interrupt */ 868 q_vector->set_itr = 1; 869 } 870 871 /** 872 * igb_configure_msix - Configure MSI-X hardware 873 * @adapter: board private structure to initialize 874 * 875 * igb_configure_msix sets up the hardware to properly 876 * generate MSI-X interrupts. 877 **/ 878 static void igb_configure_msix(struct igb_adapter *adapter) 879 { 880 u32 tmp; 881 int i, vector = 0; 882 struct e1000_hw *hw = &adapter->hw; 883 884 adapter->eims_enable_mask = 0; 885 886 /* set vector for other causes, i.e. link changes */ 887 switch (hw->mac.type) { 888 case e1000_82575: 889 tmp = rd32(E1000_CTRL_EXT); 890 /* enable MSI-X PBA support*/ 891 tmp |= E1000_CTRL_EXT_PBA_CLR; 892 893 /* Auto-Mask interrupts upon ICR read. */ 894 tmp |= E1000_CTRL_EXT_EIAME; 895 tmp |= E1000_CTRL_EXT_IRCA; 896 897 wr32(E1000_CTRL_EXT, tmp); 898 899 /* enable msix_other interrupt */ 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 901 adapter->eims_other = E1000_EIMS_OTHER; 902 903 break; 904 905 case e1000_82576: 906 case e1000_82580: 907 case e1000_i350: 908 case e1000_i354: 909 case e1000_i210: 910 case e1000_i211: 911 /* Turn on MSI-X capability first, or our settings 912 * won't stick. And it will take days to debug. 913 */ 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 915 E1000_GPIE_PBA | E1000_GPIE_EIAME | 916 E1000_GPIE_NSICR); 917 918 /* enable msix_other interrupt */ 919 adapter->eims_other = 1 << vector; 920 tmp = (vector++ | E1000_IVAR_VALID) << 8; 921 922 wr32(E1000_IVAR_MISC, tmp); 923 break; 924 default: 925 /* do nothing, since nothing else supports MSI-X */ 926 break; 927 } /* switch (hw->mac.type) */ 928 929 adapter->eims_enable_mask |= adapter->eims_other; 930 931 for (i = 0; i < adapter->num_q_vectors; i++) 932 igb_assign_vector(adapter->q_vector[i], vector++); 933 934 wrfl(); 935 } 936 937 /** 938 * igb_request_msix - Initialize MSI-X interrupts 939 * @adapter: board private structure to initialize 940 * 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 942 * kernel. 943 **/ 944 static int igb_request_msix(struct igb_adapter *adapter) 945 { 946 struct net_device *netdev = adapter->netdev; 947 struct e1000_hw *hw = &adapter->hw; 948 int i, err = 0, vector = 0, free_vector = 0; 949 950 err = request_irq(adapter->msix_entries[vector].vector, 951 igb_msix_other, 0, netdev->name, adapter); 952 if (err) 953 goto err_out; 954 955 for (i = 0; i < adapter->num_q_vectors; i++) { 956 struct igb_q_vector *q_vector = adapter->q_vector[i]; 957 958 vector++; 959 960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 961 962 if (q_vector->rx.ring && q_vector->tx.ring) 963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 964 q_vector->rx.ring->queue_index); 965 else if (q_vector->tx.ring) 966 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 967 q_vector->tx.ring->queue_index); 968 else if (q_vector->rx.ring) 969 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 970 q_vector->rx.ring->queue_index); 971 else 972 sprintf(q_vector->name, "%s-unused", netdev->name); 973 974 err = request_irq(adapter->msix_entries[vector].vector, 975 igb_msix_ring, 0, q_vector->name, 976 q_vector); 977 if (err) 978 goto err_free; 979 } 980 981 igb_configure_msix(adapter); 982 return 0; 983 984 err_free: 985 /* free already assigned IRQs */ 986 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 987 988 vector--; 989 for (i = 0; i < vector; i++) { 990 free_irq(adapter->msix_entries[free_vector++].vector, 991 adapter->q_vector[i]); 992 } 993 err_out: 994 return err; 995 } 996 997 /** 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector 999 * @adapter: board private structure to initialize 1000 * @v_idx: Index of vector to be freed 1001 * 1002 * This function frees the memory allocated to the q_vector. 1003 **/ 1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1005 { 1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1007 1008 adapter->q_vector[v_idx] = NULL; 1009 1010 /* igb_get_stats64() might access the rings on this vector, 1011 * we must wait a grace period before freeing it. 1012 */ 1013 if (q_vector) 1014 kfree_rcu(q_vector, rcu); 1015 } 1016 1017 /** 1018 * igb_reset_q_vector - Reset config for interrupt vector 1019 * @adapter: board private structure to initialize 1020 * @v_idx: Index of vector to be reset 1021 * 1022 * If NAPI is enabled it will delete any references to the 1023 * NAPI struct. This is preparation for igb_free_q_vector. 1024 **/ 1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1026 { 1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1028 1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1030 * allocated. So, q_vector is NULL so we should stop here. 1031 */ 1032 if (!q_vector) 1033 return; 1034 1035 if (q_vector->tx.ring) 1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1037 1038 if (q_vector->rx.ring) 1039 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1040 1041 netif_napi_del(&q_vector->napi); 1042 1043 } 1044 1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1046 { 1047 int v_idx = adapter->num_q_vectors; 1048 1049 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1050 pci_disable_msix(adapter->pdev); 1051 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1052 pci_disable_msi(adapter->pdev); 1053 1054 while (v_idx--) 1055 igb_reset_q_vector(adapter, v_idx); 1056 } 1057 1058 /** 1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1060 * @adapter: board private structure to initialize 1061 * 1062 * This function frees the memory allocated to the q_vectors. In addition if 1063 * NAPI is enabled it will delete any references to the NAPI struct prior 1064 * to freeing the q_vector. 1065 **/ 1066 static void igb_free_q_vectors(struct igb_adapter *adapter) 1067 { 1068 int v_idx = adapter->num_q_vectors; 1069 1070 adapter->num_tx_queues = 0; 1071 adapter->num_rx_queues = 0; 1072 adapter->num_q_vectors = 0; 1073 1074 while (v_idx--) { 1075 igb_reset_q_vector(adapter, v_idx); 1076 igb_free_q_vector(adapter, v_idx); 1077 } 1078 } 1079 1080 /** 1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1082 * @adapter: board private structure to initialize 1083 * 1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1085 * MSI-X interrupts allocated. 1086 */ 1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1088 { 1089 igb_free_q_vectors(adapter); 1090 igb_reset_interrupt_capability(adapter); 1091 } 1092 1093 /** 1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1095 * @adapter: board private structure to initialize 1096 * @msix: boolean value of MSIX capability 1097 * 1098 * Attempt to configure interrupts using the best available 1099 * capabilities of the hardware and kernel. 1100 **/ 1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1102 { 1103 int err; 1104 int numvecs, i; 1105 1106 if (!msix) 1107 goto msi_only; 1108 adapter->flags |= IGB_FLAG_HAS_MSIX; 1109 1110 /* Number of supported queues. */ 1111 adapter->num_rx_queues = adapter->rss_queues; 1112 if (adapter->vfs_allocated_count) 1113 adapter->num_tx_queues = 1; 1114 else 1115 adapter->num_tx_queues = adapter->rss_queues; 1116 1117 /* start with one vector for every Rx queue */ 1118 numvecs = adapter->num_rx_queues; 1119 1120 /* if Tx handler is separate add 1 for every Tx queue */ 1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1122 numvecs += adapter->num_tx_queues; 1123 1124 /* store the number of vectors reserved for queues */ 1125 adapter->num_q_vectors = numvecs; 1126 1127 /* add 1 vector for link status interrupts */ 1128 numvecs++; 1129 for (i = 0; i < numvecs; i++) 1130 adapter->msix_entries[i].entry = i; 1131 1132 err = pci_enable_msix_range(adapter->pdev, 1133 adapter->msix_entries, 1134 numvecs, 1135 numvecs); 1136 if (err > 0) 1137 return; 1138 1139 igb_reset_interrupt_capability(adapter); 1140 1141 /* If we can't do MSI-X, try MSI */ 1142 msi_only: 1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1144 #ifdef CONFIG_PCI_IOV 1145 /* disable SR-IOV for non MSI-X configurations */ 1146 if (adapter->vf_data) { 1147 struct e1000_hw *hw = &adapter->hw; 1148 /* disable iov and allow time for transactions to clear */ 1149 pci_disable_sriov(adapter->pdev); 1150 msleep(500); 1151 1152 kfree(adapter->vf_data); 1153 adapter->vf_data = NULL; 1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1155 wrfl(); 1156 msleep(100); 1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1158 } 1159 #endif 1160 adapter->vfs_allocated_count = 0; 1161 adapter->rss_queues = 1; 1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1163 adapter->num_rx_queues = 1; 1164 adapter->num_tx_queues = 1; 1165 adapter->num_q_vectors = 1; 1166 if (!pci_enable_msi(adapter->pdev)) 1167 adapter->flags |= IGB_FLAG_HAS_MSI; 1168 } 1169 1170 static void igb_add_ring(struct igb_ring *ring, 1171 struct igb_ring_container *head) 1172 { 1173 head->ring = ring; 1174 head->count++; 1175 } 1176 1177 /** 1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1179 * @adapter: board private structure to initialize 1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1181 * @v_idx: index of vector in adapter struct 1182 * @txr_count: total number of Tx rings to allocate 1183 * @txr_idx: index of first Tx ring to allocate 1184 * @rxr_count: total number of Rx rings to allocate 1185 * @rxr_idx: index of first Rx ring to allocate 1186 * 1187 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1188 **/ 1189 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1190 int v_count, int v_idx, 1191 int txr_count, int txr_idx, 1192 int rxr_count, int rxr_idx) 1193 { 1194 struct igb_q_vector *q_vector; 1195 struct igb_ring *ring; 1196 int ring_count, size; 1197 1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1199 if (txr_count > 1 || rxr_count > 1) 1200 return -ENOMEM; 1201 1202 ring_count = txr_count + rxr_count; 1203 size = sizeof(struct igb_q_vector) + 1204 (sizeof(struct igb_ring) * ring_count); 1205 1206 /* allocate q_vector and rings */ 1207 q_vector = adapter->q_vector[v_idx]; 1208 if (!q_vector) 1209 q_vector = kzalloc(size, GFP_KERNEL); 1210 if (!q_vector) 1211 return -ENOMEM; 1212 1213 /* initialize NAPI */ 1214 netif_napi_add(adapter->netdev, &q_vector->napi, 1215 igb_poll, 64); 1216 1217 /* tie q_vector and adapter together */ 1218 adapter->q_vector[v_idx] = q_vector; 1219 q_vector->adapter = adapter; 1220 1221 /* initialize work limits */ 1222 q_vector->tx.work_limit = adapter->tx_work_limit; 1223 1224 /* initialize ITR configuration */ 1225 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1226 q_vector->itr_val = IGB_START_ITR; 1227 1228 /* initialize pointer to rings */ 1229 ring = q_vector->ring; 1230 1231 /* intialize ITR */ 1232 if (rxr_count) { 1233 /* rx or rx/tx vector */ 1234 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1235 q_vector->itr_val = adapter->rx_itr_setting; 1236 } else { 1237 /* tx only vector */ 1238 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1239 q_vector->itr_val = adapter->tx_itr_setting; 1240 } 1241 1242 if (txr_count) { 1243 /* assign generic ring traits */ 1244 ring->dev = &adapter->pdev->dev; 1245 ring->netdev = adapter->netdev; 1246 1247 /* configure backlink on ring */ 1248 ring->q_vector = q_vector; 1249 1250 /* update q_vector Tx values */ 1251 igb_add_ring(ring, &q_vector->tx); 1252 1253 /* For 82575, context index must be unique per ring. */ 1254 if (adapter->hw.mac.type == e1000_82575) 1255 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1256 1257 /* apply Tx specific ring traits */ 1258 ring->count = adapter->tx_ring_count; 1259 ring->queue_index = txr_idx; 1260 1261 u64_stats_init(&ring->tx_syncp); 1262 u64_stats_init(&ring->tx_syncp2); 1263 1264 /* assign ring to adapter */ 1265 adapter->tx_ring[txr_idx] = ring; 1266 1267 /* push pointer to next ring */ 1268 ring++; 1269 } 1270 1271 if (rxr_count) { 1272 /* assign generic ring traits */ 1273 ring->dev = &adapter->pdev->dev; 1274 ring->netdev = adapter->netdev; 1275 1276 /* configure backlink on ring */ 1277 ring->q_vector = q_vector; 1278 1279 /* update q_vector Rx values */ 1280 igb_add_ring(ring, &q_vector->rx); 1281 1282 /* set flag indicating ring supports SCTP checksum offload */ 1283 if (adapter->hw.mac.type >= e1000_82576) 1284 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1285 1286 /* On i350, i354, i210, and i211, loopback VLAN packets 1287 * have the tag byte-swapped. 1288 */ 1289 if (adapter->hw.mac.type >= e1000_i350) 1290 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1291 1292 /* apply Rx specific ring traits */ 1293 ring->count = adapter->rx_ring_count; 1294 ring->queue_index = rxr_idx; 1295 1296 u64_stats_init(&ring->rx_syncp); 1297 1298 /* assign ring to adapter */ 1299 adapter->rx_ring[rxr_idx] = ring; 1300 } 1301 1302 return 0; 1303 } 1304 1305 1306 /** 1307 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1308 * @adapter: board private structure to initialize 1309 * 1310 * We allocate one q_vector per queue interrupt. If allocation fails we 1311 * return -ENOMEM. 1312 **/ 1313 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1314 { 1315 int q_vectors = adapter->num_q_vectors; 1316 int rxr_remaining = adapter->num_rx_queues; 1317 int txr_remaining = adapter->num_tx_queues; 1318 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1319 int err; 1320 1321 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1322 for (; rxr_remaining; v_idx++) { 1323 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1324 0, 0, 1, rxr_idx); 1325 1326 if (err) 1327 goto err_out; 1328 1329 /* update counts and index */ 1330 rxr_remaining--; 1331 rxr_idx++; 1332 } 1333 } 1334 1335 for (; v_idx < q_vectors; v_idx++) { 1336 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1337 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1338 1339 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1340 tqpv, txr_idx, rqpv, rxr_idx); 1341 1342 if (err) 1343 goto err_out; 1344 1345 /* update counts and index */ 1346 rxr_remaining -= rqpv; 1347 txr_remaining -= tqpv; 1348 rxr_idx++; 1349 txr_idx++; 1350 } 1351 1352 return 0; 1353 1354 err_out: 1355 adapter->num_tx_queues = 0; 1356 adapter->num_rx_queues = 0; 1357 adapter->num_q_vectors = 0; 1358 1359 while (v_idx--) 1360 igb_free_q_vector(adapter, v_idx); 1361 1362 return -ENOMEM; 1363 } 1364 1365 /** 1366 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1367 * @adapter: board private structure to initialize 1368 * @msix: boolean value of MSIX capability 1369 * 1370 * This function initializes the interrupts and allocates all of the queues. 1371 **/ 1372 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1373 { 1374 struct pci_dev *pdev = adapter->pdev; 1375 int err; 1376 1377 igb_set_interrupt_capability(adapter, msix); 1378 1379 err = igb_alloc_q_vectors(adapter); 1380 if (err) { 1381 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1382 goto err_alloc_q_vectors; 1383 } 1384 1385 igb_cache_ring_register(adapter); 1386 1387 return 0; 1388 1389 err_alloc_q_vectors: 1390 igb_reset_interrupt_capability(adapter); 1391 return err; 1392 } 1393 1394 /** 1395 * igb_request_irq - initialize interrupts 1396 * @adapter: board private structure to initialize 1397 * 1398 * Attempts to configure interrupts using the best available 1399 * capabilities of the hardware and kernel. 1400 **/ 1401 static int igb_request_irq(struct igb_adapter *adapter) 1402 { 1403 struct net_device *netdev = adapter->netdev; 1404 struct pci_dev *pdev = adapter->pdev; 1405 int err = 0; 1406 1407 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1408 err = igb_request_msix(adapter); 1409 if (!err) 1410 goto request_done; 1411 /* fall back to MSI */ 1412 igb_free_all_tx_resources(adapter); 1413 igb_free_all_rx_resources(adapter); 1414 1415 igb_clear_interrupt_scheme(adapter); 1416 err = igb_init_interrupt_scheme(adapter, false); 1417 if (err) 1418 goto request_done; 1419 1420 igb_setup_all_tx_resources(adapter); 1421 igb_setup_all_rx_resources(adapter); 1422 igb_configure(adapter); 1423 } 1424 1425 igb_assign_vector(adapter->q_vector[0], 0); 1426 1427 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1428 err = request_irq(pdev->irq, igb_intr_msi, 0, 1429 netdev->name, adapter); 1430 if (!err) 1431 goto request_done; 1432 1433 /* fall back to legacy interrupts */ 1434 igb_reset_interrupt_capability(adapter); 1435 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1436 } 1437 1438 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1439 netdev->name, adapter); 1440 1441 if (err) 1442 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1443 err); 1444 1445 request_done: 1446 return err; 1447 } 1448 1449 static void igb_free_irq(struct igb_adapter *adapter) 1450 { 1451 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1452 int vector = 0, i; 1453 1454 free_irq(adapter->msix_entries[vector++].vector, adapter); 1455 1456 for (i = 0; i < adapter->num_q_vectors; i++) 1457 free_irq(adapter->msix_entries[vector++].vector, 1458 adapter->q_vector[i]); 1459 } else { 1460 free_irq(adapter->pdev->irq, adapter); 1461 } 1462 } 1463 1464 /** 1465 * igb_irq_disable - Mask off interrupt generation on the NIC 1466 * @adapter: board private structure 1467 **/ 1468 static void igb_irq_disable(struct igb_adapter *adapter) 1469 { 1470 struct e1000_hw *hw = &adapter->hw; 1471 1472 /* we need to be careful when disabling interrupts. The VFs are also 1473 * mapped into these registers and so clearing the bits can cause 1474 * issues on the VF drivers so we only need to clear what we set 1475 */ 1476 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1477 u32 regval = rd32(E1000_EIAM); 1478 1479 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1480 wr32(E1000_EIMC, adapter->eims_enable_mask); 1481 regval = rd32(E1000_EIAC); 1482 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1483 } 1484 1485 wr32(E1000_IAM, 0); 1486 wr32(E1000_IMC, ~0); 1487 wrfl(); 1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1489 int i; 1490 1491 for (i = 0; i < adapter->num_q_vectors; i++) 1492 synchronize_irq(adapter->msix_entries[i].vector); 1493 } else { 1494 synchronize_irq(adapter->pdev->irq); 1495 } 1496 } 1497 1498 /** 1499 * igb_irq_enable - Enable default interrupt generation settings 1500 * @adapter: board private structure 1501 **/ 1502 static void igb_irq_enable(struct igb_adapter *adapter) 1503 { 1504 struct e1000_hw *hw = &adapter->hw; 1505 1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1508 u32 regval = rd32(E1000_EIAC); 1509 1510 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1511 regval = rd32(E1000_EIAM); 1512 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1513 wr32(E1000_EIMS, adapter->eims_enable_mask); 1514 if (adapter->vfs_allocated_count) { 1515 wr32(E1000_MBVFIMR, 0xFF); 1516 ims |= E1000_IMS_VMMB; 1517 } 1518 wr32(E1000_IMS, ims); 1519 } else { 1520 wr32(E1000_IMS, IMS_ENABLE_MASK | 1521 E1000_IMS_DRSTA); 1522 wr32(E1000_IAM, IMS_ENABLE_MASK | 1523 E1000_IMS_DRSTA); 1524 } 1525 } 1526 1527 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1528 { 1529 struct e1000_hw *hw = &adapter->hw; 1530 u16 vid = adapter->hw.mng_cookie.vlan_id; 1531 u16 old_vid = adapter->mng_vlan_id; 1532 1533 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1534 /* add VID to filter table */ 1535 igb_vfta_set(hw, vid, true); 1536 adapter->mng_vlan_id = vid; 1537 } else { 1538 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1539 } 1540 1541 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1542 (vid != old_vid) && 1543 !test_bit(old_vid, adapter->active_vlans)) { 1544 /* remove VID from filter table */ 1545 igb_vfta_set(hw, old_vid, false); 1546 } 1547 } 1548 1549 /** 1550 * igb_release_hw_control - release control of the h/w to f/w 1551 * @adapter: address of board private structure 1552 * 1553 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1554 * For ASF and Pass Through versions of f/w this means that the 1555 * driver is no longer loaded. 1556 **/ 1557 static void igb_release_hw_control(struct igb_adapter *adapter) 1558 { 1559 struct e1000_hw *hw = &adapter->hw; 1560 u32 ctrl_ext; 1561 1562 /* Let firmware take over control of h/w */ 1563 ctrl_ext = rd32(E1000_CTRL_EXT); 1564 wr32(E1000_CTRL_EXT, 1565 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1566 } 1567 1568 /** 1569 * igb_get_hw_control - get control of the h/w from f/w 1570 * @adapter: address of board private structure 1571 * 1572 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1573 * For ASF and Pass Through versions of f/w this means that 1574 * the driver is loaded. 1575 **/ 1576 static void igb_get_hw_control(struct igb_adapter *adapter) 1577 { 1578 struct e1000_hw *hw = &adapter->hw; 1579 u32 ctrl_ext; 1580 1581 /* Let firmware know the driver has taken over */ 1582 ctrl_ext = rd32(E1000_CTRL_EXT); 1583 wr32(E1000_CTRL_EXT, 1584 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1585 } 1586 1587 /** 1588 * igb_configure - configure the hardware for RX and TX 1589 * @adapter: private board structure 1590 **/ 1591 static void igb_configure(struct igb_adapter *adapter) 1592 { 1593 struct net_device *netdev = adapter->netdev; 1594 int i; 1595 1596 igb_get_hw_control(adapter); 1597 igb_set_rx_mode(netdev); 1598 1599 igb_restore_vlan(adapter); 1600 1601 igb_setup_tctl(adapter); 1602 igb_setup_mrqc(adapter); 1603 igb_setup_rctl(adapter); 1604 1605 igb_configure_tx(adapter); 1606 igb_configure_rx(adapter); 1607 1608 igb_rx_fifo_flush_82575(&adapter->hw); 1609 1610 /* call igb_desc_unused which always leaves 1611 * at least 1 descriptor unused to make sure 1612 * next_to_use != next_to_clean 1613 */ 1614 for (i = 0; i < adapter->num_rx_queues; i++) { 1615 struct igb_ring *ring = adapter->rx_ring[i]; 1616 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1617 } 1618 } 1619 1620 /** 1621 * igb_power_up_link - Power up the phy/serdes link 1622 * @adapter: address of board private structure 1623 **/ 1624 void igb_power_up_link(struct igb_adapter *adapter) 1625 { 1626 igb_reset_phy(&adapter->hw); 1627 1628 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1629 igb_power_up_phy_copper(&adapter->hw); 1630 else 1631 igb_power_up_serdes_link_82575(&adapter->hw); 1632 1633 igb_setup_link(&adapter->hw); 1634 } 1635 1636 /** 1637 * igb_power_down_link - Power down the phy/serdes link 1638 * @adapter: address of board private structure 1639 */ 1640 static void igb_power_down_link(struct igb_adapter *adapter) 1641 { 1642 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1643 igb_power_down_phy_copper_82575(&adapter->hw); 1644 else 1645 igb_shutdown_serdes_link_82575(&adapter->hw); 1646 } 1647 1648 /** 1649 * Detect and switch function for Media Auto Sense 1650 * @adapter: address of the board private structure 1651 **/ 1652 static void igb_check_swap_media(struct igb_adapter *adapter) 1653 { 1654 struct e1000_hw *hw = &adapter->hw; 1655 u32 ctrl_ext, connsw; 1656 bool swap_now = false; 1657 1658 ctrl_ext = rd32(E1000_CTRL_EXT); 1659 connsw = rd32(E1000_CONNSW); 1660 1661 /* need to live swap if current media is copper and we have fiber/serdes 1662 * to go to. 1663 */ 1664 1665 if ((hw->phy.media_type == e1000_media_type_copper) && 1666 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1667 swap_now = true; 1668 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1669 /* copper signal takes time to appear */ 1670 if (adapter->copper_tries < 4) { 1671 adapter->copper_tries++; 1672 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1673 wr32(E1000_CONNSW, connsw); 1674 return; 1675 } else { 1676 adapter->copper_tries = 0; 1677 if ((connsw & E1000_CONNSW_PHYSD) && 1678 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1679 swap_now = true; 1680 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1681 wr32(E1000_CONNSW, connsw); 1682 } 1683 } 1684 } 1685 1686 if (!swap_now) 1687 return; 1688 1689 switch (hw->phy.media_type) { 1690 case e1000_media_type_copper: 1691 netdev_info(adapter->netdev, 1692 "MAS: changing media to fiber/serdes\n"); 1693 ctrl_ext |= 1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1695 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1696 adapter->copper_tries = 0; 1697 break; 1698 case e1000_media_type_internal_serdes: 1699 case e1000_media_type_fiber: 1700 netdev_info(adapter->netdev, 1701 "MAS: changing media to copper\n"); 1702 ctrl_ext &= 1703 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1704 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1705 break; 1706 default: 1707 /* shouldn't get here during regular operation */ 1708 netdev_err(adapter->netdev, 1709 "AMS: Invalid media type found, returning\n"); 1710 break; 1711 } 1712 wr32(E1000_CTRL_EXT, ctrl_ext); 1713 } 1714 1715 /** 1716 * igb_up - Open the interface and prepare it to handle traffic 1717 * @adapter: board private structure 1718 **/ 1719 int igb_up(struct igb_adapter *adapter) 1720 { 1721 struct e1000_hw *hw = &adapter->hw; 1722 int i; 1723 1724 /* hardware has been reset, we need to reload some things */ 1725 igb_configure(adapter); 1726 1727 clear_bit(__IGB_DOWN, &adapter->state); 1728 1729 for (i = 0; i < adapter->num_q_vectors; i++) 1730 napi_enable(&(adapter->q_vector[i]->napi)); 1731 1732 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1733 igb_configure_msix(adapter); 1734 else 1735 igb_assign_vector(adapter->q_vector[0], 0); 1736 1737 /* Clear any pending interrupts. */ 1738 rd32(E1000_ICR); 1739 igb_irq_enable(adapter); 1740 1741 /* notify VFs that reset has been completed */ 1742 if (adapter->vfs_allocated_count) { 1743 u32 reg_data = rd32(E1000_CTRL_EXT); 1744 1745 reg_data |= E1000_CTRL_EXT_PFRSTD; 1746 wr32(E1000_CTRL_EXT, reg_data); 1747 } 1748 1749 netif_tx_start_all_queues(adapter->netdev); 1750 1751 /* start the watchdog. */ 1752 hw->mac.get_link_status = 1; 1753 schedule_work(&adapter->watchdog_task); 1754 1755 if ((adapter->flags & IGB_FLAG_EEE) && 1756 (!hw->dev_spec._82575.eee_disable)) 1757 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1758 1759 return 0; 1760 } 1761 1762 void igb_down(struct igb_adapter *adapter) 1763 { 1764 struct net_device *netdev = adapter->netdev; 1765 struct e1000_hw *hw = &adapter->hw; 1766 u32 tctl, rctl; 1767 int i; 1768 1769 /* signal that we're down so the interrupt handler does not 1770 * reschedule our watchdog timer 1771 */ 1772 set_bit(__IGB_DOWN, &adapter->state); 1773 1774 /* disable receives in the hardware */ 1775 rctl = rd32(E1000_RCTL); 1776 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1777 /* flush and sleep below */ 1778 1779 netif_carrier_off(netdev); 1780 netif_tx_stop_all_queues(netdev); 1781 1782 /* disable transmits in the hardware */ 1783 tctl = rd32(E1000_TCTL); 1784 tctl &= ~E1000_TCTL_EN; 1785 wr32(E1000_TCTL, tctl); 1786 /* flush both disables and wait for them to finish */ 1787 wrfl(); 1788 usleep_range(10000, 11000); 1789 1790 igb_irq_disable(adapter); 1791 1792 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1793 1794 for (i = 0; i < adapter->num_q_vectors; i++) { 1795 if (adapter->q_vector[i]) { 1796 napi_synchronize(&adapter->q_vector[i]->napi); 1797 napi_disable(&adapter->q_vector[i]->napi); 1798 } 1799 } 1800 1801 del_timer_sync(&adapter->watchdog_timer); 1802 del_timer_sync(&adapter->phy_info_timer); 1803 1804 /* record the stats before reset*/ 1805 spin_lock(&adapter->stats64_lock); 1806 igb_update_stats(adapter, &adapter->stats64); 1807 spin_unlock(&adapter->stats64_lock); 1808 1809 adapter->link_speed = 0; 1810 adapter->link_duplex = 0; 1811 1812 if (!pci_channel_offline(adapter->pdev)) 1813 igb_reset(adapter); 1814 igb_clean_all_tx_rings(adapter); 1815 igb_clean_all_rx_rings(adapter); 1816 #ifdef CONFIG_IGB_DCA 1817 1818 /* since we reset the hardware DCA settings were cleared */ 1819 igb_setup_dca(adapter); 1820 #endif 1821 } 1822 1823 void igb_reinit_locked(struct igb_adapter *adapter) 1824 { 1825 WARN_ON(in_interrupt()); 1826 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1827 usleep_range(1000, 2000); 1828 igb_down(adapter); 1829 igb_up(adapter); 1830 clear_bit(__IGB_RESETTING, &adapter->state); 1831 } 1832 1833 /** igb_enable_mas - Media Autosense re-enable after swap 1834 * 1835 * @adapter: adapter struct 1836 **/ 1837 static s32 igb_enable_mas(struct igb_adapter *adapter) 1838 { 1839 struct e1000_hw *hw = &adapter->hw; 1840 u32 connsw; 1841 s32 ret_val = 0; 1842 1843 connsw = rd32(E1000_CONNSW); 1844 if (!(hw->phy.media_type == e1000_media_type_copper)) 1845 return ret_val; 1846 1847 /* configure for SerDes media detect */ 1848 if (!(connsw & E1000_CONNSW_SERDESD)) { 1849 connsw |= E1000_CONNSW_ENRGSRC; 1850 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1851 wr32(E1000_CONNSW, connsw); 1852 wrfl(); 1853 } else if (connsw & E1000_CONNSW_SERDESD) { 1854 /* already SerDes, no need to enable anything */ 1855 return ret_val; 1856 } else { 1857 netdev_info(adapter->netdev, 1858 "MAS: Unable to configure feature, disabling..\n"); 1859 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1860 } 1861 return ret_val; 1862 } 1863 1864 void igb_reset(struct igb_adapter *adapter) 1865 { 1866 struct pci_dev *pdev = adapter->pdev; 1867 struct e1000_hw *hw = &adapter->hw; 1868 struct e1000_mac_info *mac = &hw->mac; 1869 struct e1000_fc_info *fc = &hw->fc; 1870 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1871 1872 /* Repartition Pba for greater than 9k mtu 1873 * To take effect CTRL.RST is required. 1874 */ 1875 switch (mac->type) { 1876 case e1000_i350: 1877 case e1000_i354: 1878 case e1000_82580: 1879 pba = rd32(E1000_RXPBS); 1880 pba = igb_rxpbs_adjust_82580(pba); 1881 break; 1882 case e1000_82576: 1883 pba = rd32(E1000_RXPBS); 1884 pba &= E1000_RXPBS_SIZE_MASK_82576; 1885 break; 1886 case e1000_82575: 1887 case e1000_i210: 1888 case e1000_i211: 1889 default: 1890 pba = E1000_PBA_34K; 1891 break; 1892 } 1893 1894 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1895 (mac->type < e1000_82576)) { 1896 /* adjust PBA for jumbo frames */ 1897 wr32(E1000_PBA, pba); 1898 1899 /* To maintain wire speed transmits, the Tx FIFO should be 1900 * large enough to accommodate two full transmit packets, 1901 * rounded up to the next 1KB and expressed in KB. Likewise, 1902 * the Rx FIFO should be large enough to accommodate at least 1903 * one full receive packet and is similarly rounded up and 1904 * expressed in KB. 1905 */ 1906 pba = rd32(E1000_PBA); 1907 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1908 tx_space = pba >> 16; 1909 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1910 pba &= 0xffff; 1911 /* the Tx fifo also stores 16 bytes of information about the Tx 1912 * but don't include ethernet FCS because hardware appends it 1913 */ 1914 min_tx_space = (adapter->max_frame_size + 1915 sizeof(union e1000_adv_tx_desc) - 1916 ETH_FCS_LEN) * 2; 1917 min_tx_space = ALIGN(min_tx_space, 1024); 1918 min_tx_space >>= 10; 1919 /* software strips receive CRC, so leave room for it */ 1920 min_rx_space = adapter->max_frame_size; 1921 min_rx_space = ALIGN(min_rx_space, 1024); 1922 min_rx_space >>= 10; 1923 1924 /* If current Tx allocation is less than the min Tx FIFO size, 1925 * and the min Tx FIFO size is less than the current Rx FIFO 1926 * allocation, take space away from current Rx allocation 1927 */ 1928 if (tx_space < min_tx_space && 1929 ((min_tx_space - tx_space) < pba)) { 1930 pba = pba - (min_tx_space - tx_space); 1931 1932 /* if short on Rx space, Rx wins and must trump Tx 1933 * adjustment 1934 */ 1935 if (pba < min_rx_space) 1936 pba = min_rx_space; 1937 } 1938 wr32(E1000_PBA, pba); 1939 } 1940 1941 /* flow control settings */ 1942 /* The high water mark must be low enough to fit one full frame 1943 * (or the size used for early receive) above it in the Rx FIFO. 1944 * Set it to the lower of: 1945 * - 90% of the Rx FIFO size, or 1946 * - the full Rx FIFO size minus one full frame 1947 */ 1948 hwm = min(((pba << 10) * 9 / 10), 1949 ((pba << 10) - 2 * adapter->max_frame_size)); 1950 1951 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1952 fc->low_water = fc->high_water - 16; 1953 fc->pause_time = 0xFFFF; 1954 fc->send_xon = 1; 1955 fc->current_mode = fc->requested_mode; 1956 1957 /* disable receive for all VFs and wait one second */ 1958 if (adapter->vfs_allocated_count) { 1959 int i; 1960 1961 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1962 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1963 1964 /* ping all the active vfs to let them know we are going down */ 1965 igb_ping_all_vfs(adapter); 1966 1967 /* disable transmits and receives */ 1968 wr32(E1000_VFRE, 0); 1969 wr32(E1000_VFTE, 0); 1970 } 1971 1972 /* Allow time for pending master requests to run */ 1973 hw->mac.ops.reset_hw(hw); 1974 wr32(E1000_WUC, 0); 1975 1976 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1977 /* need to resetup here after media swap */ 1978 adapter->ei.get_invariants(hw); 1979 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1980 } 1981 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1982 if (igb_enable_mas(adapter)) 1983 dev_err(&pdev->dev, 1984 "Error enabling Media Auto Sense\n"); 1985 } 1986 if (hw->mac.ops.init_hw(hw)) 1987 dev_err(&pdev->dev, "Hardware Error\n"); 1988 1989 /* Flow control settings reset on hardware reset, so guarantee flow 1990 * control is off when forcing speed. 1991 */ 1992 if (!hw->mac.autoneg) 1993 igb_force_mac_fc(hw); 1994 1995 igb_init_dmac(adapter, pba); 1996 #ifdef CONFIG_IGB_HWMON 1997 /* Re-initialize the thermal sensor on i350 devices. */ 1998 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1999 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2000 /* If present, re-initialize the external thermal sensor 2001 * interface. 2002 */ 2003 if (adapter->ets) 2004 mac->ops.init_thermal_sensor_thresh(hw); 2005 } 2006 } 2007 #endif 2008 /* Re-establish EEE setting */ 2009 if (hw->phy.media_type == e1000_media_type_copper) { 2010 switch (mac->type) { 2011 case e1000_i350: 2012 case e1000_i210: 2013 case e1000_i211: 2014 igb_set_eee_i350(hw, true, true); 2015 break; 2016 case e1000_i354: 2017 igb_set_eee_i354(hw, true, true); 2018 break; 2019 default: 2020 break; 2021 } 2022 } 2023 if (!netif_running(adapter->netdev)) 2024 igb_power_down_link(adapter); 2025 2026 igb_update_mng_vlan(adapter); 2027 2028 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2029 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2030 2031 /* Re-enable PTP, where applicable. */ 2032 igb_ptp_reset(adapter); 2033 2034 igb_get_phy_info(hw); 2035 } 2036 2037 static netdev_features_t igb_fix_features(struct net_device *netdev, 2038 netdev_features_t features) 2039 { 2040 /* Since there is no support for separate Rx/Tx vlan accel 2041 * enable/disable make sure Tx flag is always in same state as Rx. 2042 */ 2043 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2044 features |= NETIF_F_HW_VLAN_CTAG_TX; 2045 else 2046 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2047 2048 return features; 2049 } 2050 2051 static int igb_set_features(struct net_device *netdev, 2052 netdev_features_t features) 2053 { 2054 netdev_features_t changed = netdev->features ^ features; 2055 struct igb_adapter *adapter = netdev_priv(netdev); 2056 2057 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2058 igb_vlan_mode(netdev, features); 2059 2060 if (!(changed & NETIF_F_RXALL)) 2061 return 0; 2062 2063 netdev->features = features; 2064 2065 if (netif_running(netdev)) 2066 igb_reinit_locked(adapter); 2067 else 2068 igb_reset(adapter); 2069 2070 return 0; 2071 } 2072 2073 static const struct net_device_ops igb_netdev_ops = { 2074 .ndo_open = igb_open, 2075 .ndo_stop = igb_close, 2076 .ndo_start_xmit = igb_xmit_frame, 2077 .ndo_get_stats64 = igb_get_stats64, 2078 .ndo_set_rx_mode = igb_set_rx_mode, 2079 .ndo_set_mac_address = igb_set_mac, 2080 .ndo_change_mtu = igb_change_mtu, 2081 .ndo_do_ioctl = igb_ioctl, 2082 .ndo_tx_timeout = igb_tx_timeout, 2083 .ndo_validate_addr = eth_validate_addr, 2084 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2085 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2086 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2087 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2088 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2089 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2090 .ndo_get_vf_config = igb_ndo_get_vf_config, 2091 #ifdef CONFIG_NET_POLL_CONTROLLER 2092 .ndo_poll_controller = igb_netpoll, 2093 #endif 2094 .ndo_fix_features = igb_fix_features, 2095 .ndo_set_features = igb_set_features, 2096 .ndo_features_check = passthru_features_check, 2097 }; 2098 2099 /** 2100 * igb_set_fw_version - Configure version string for ethtool 2101 * @adapter: adapter struct 2102 **/ 2103 void igb_set_fw_version(struct igb_adapter *adapter) 2104 { 2105 struct e1000_hw *hw = &adapter->hw; 2106 struct e1000_fw_version fw; 2107 2108 igb_get_fw_version(hw, &fw); 2109 2110 switch (hw->mac.type) { 2111 case e1000_i210: 2112 case e1000_i211: 2113 if (!(igb_get_flash_presence_i210(hw))) { 2114 snprintf(adapter->fw_version, 2115 sizeof(adapter->fw_version), 2116 "%2d.%2d-%d", 2117 fw.invm_major, fw.invm_minor, 2118 fw.invm_img_type); 2119 break; 2120 } 2121 /* fall through */ 2122 default: 2123 /* if option is rom valid, display its version too */ 2124 if (fw.or_valid) { 2125 snprintf(adapter->fw_version, 2126 sizeof(adapter->fw_version), 2127 "%d.%d, 0x%08x, %d.%d.%d", 2128 fw.eep_major, fw.eep_minor, fw.etrack_id, 2129 fw.or_major, fw.or_build, fw.or_patch); 2130 /* no option rom */ 2131 } else if (fw.etrack_id != 0X0000) { 2132 snprintf(adapter->fw_version, 2133 sizeof(adapter->fw_version), 2134 "%d.%d, 0x%08x", 2135 fw.eep_major, fw.eep_minor, fw.etrack_id); 2136 } else { 2137 snprintf(adapter->fw_version, 2138 sizeof(adapter->fw_version), 2139 "%d.%d.%d", 2140 fw.eep_major, fw.eep_minor, fw.eep_build); 2141 } 2142 break; 2143 } 2144 } 2145 2146 /** 2147 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2148 * 2149 * @adapter: adapter struct 2150 **/ 2151 static void igb_init_mas(struct igb_adapter *adapter) 2152 { 2153 struct e1000_hw *hw = &adapter->hw; 2154 u16 eeprom_data; 2155 2156 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2157 switch (hw->bus.func) { 2158 case E1000_FUNC_0: 2159 if (eeprom_data & IGB_MAS_ENABLE_0) { 2160 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2161 netdev_info(adapter->netdev, 2162 "MAS: Enabling Media Autosense for port %d\n", 2163 hw->bus.func); 2164 } 2165 break; 2166 case E1000_FUNC_1: 2167 if (eeprom_data & IGB_MAS_ENABLE_1) { 2168 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2169 netdev_info(adapter->netdev, 2170 "MAS: Enabling Media Autosense for port %d\n", 2171 hw->bus.func); 2172 } 2173 break; 2174 case E1000_FUNC_2: 2175 if (eeprom_data & IGB_MAS_ENABLE_2) { 2176 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2177 netdev_info(adapter->netdev, 2178 "MAS: Enabling Media Autosense for port %d\n", 2179 hw->bus.func); 2180 } 2181 break; 2182 case E1000_FUNC_3: 2183 if (eeprom_data & IGB_MAS_ENABLE_3) { 2184 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2185 netdev_info(adapter->netdev, 2186 "MAS: Enabling Media Autosense for port %d\n", 2187 hw->bus.func); 2188 } 2189 break; 2190 default: 2191 /* Shouldn't get here */ 2192 netdev_err(adapter->netdev, 2193 "MAS: Invalid port configuration, returning\n"); 2194 break; 2195 } 2196 } 2197 2198 /** 2199 * igb_init_i2c - Init I2C interface 2200 * @adapter: pointer to adapter structure 2201 **/ 2202 static s32 igb_init_i2c(struct igb_adapter *adapter) 2203 { 2204 s32 status = 0; 2205 2206 /* I2C interface supported on i350 devices */ 2207 if (adapter->hw.mac.type != e1000_i350) 2208 return 0; 2209 2210 /* Initialize the i2c bus which is controlled by the registers. 2211 * This bus will use the i2c_algo_bit structue that implements 2212 * the protocol through toggling of the 4 bits in the register. 2213 */ 2214 adapter->i2c_adap.owner = THIS_MODULE; 2215 adapter->i2c_algo = igb_i2c_algo; 2216 adapter->i2c_algo.data = adapter; 2217 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2218 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2219 strlcpy(adapter->i2c_adap.name, "igb BB", 2220 sizeof(adapter->i2c_adap.name)); 2221 status = i2c_bit_add_bus(&adapter->i2c_adap); 2222 return status; 2223 } 2224 2225 /** 2226 * igb_probe - Device Initialization Routine 2227 * @pdev: PCI device information struct 2228 * @ent: entry in igb_pci_tbl 2229 * 2230 * Returns 0 on success, negative on failure 2231 * 2232 * igb_probe initializes an adapter identified by a pci_dev structure. 2233 * The OS initialization, configuring of the adapter private structure, 2234 * and a hardware reset occur. 2235 **/ 2236 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2237 { 2238 struct net_device *netdev; 2239 struct igb_adapter *adapter; 2240 struct e1000_hw *hw; 2241 u16 eeprom_data = 0; 2242 s32 ret_val; 2243 static int global_quad_port_a; /* global quad port a indication */ 2244 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2245 int err, pci_using_dac; 2246 u8 part_str[E1000_PBANUM_LENGTH]; 2247 2248 /* Catch broken hardware that put the wrong VF device ID in 2249 * the PCIe SR-IOV capability. 2250 */ 2251 if (pdev->is_virtfn) { 2252 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2253 pci_name(pdev), pdev->vendor, pdev->device); 2254 return -EINVAL; 2255 } 2256 2257 err = pci_enable_device_mem(pdev); 2258 if (err) 2259 return err; 2260 2261 pci_using_dac = 0; 2262 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2263 if (!err) { 2264 pci_using_dac = 1; 2265 } else { 2266 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2267 if (err) { 2268 dev_err(&pdev->dev, 2269 "No usable DMA configuration, aborting\n"); 2270 goto err_dma; 2271 } 2272 } 2273 2274 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2275 IORESOURCE_MEM), 2276 igb_driver_name); 2277 if (err) 2278 goto err_pci_reg; 2279 2280 pci_enable_pcie_error_reporting(pdev); 2281 2282 pci_set_master(pdev); 2283 pci_save_state(pdev); 2284 2285 err = -ENOMEM; 2286 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2287 IGB_MAX_TX_QUEUES); 2288 if (!netdev) 2289 goto err_alloc_etherdev; 2290 2291 SET_NETDEV_DEV(netdev, &pdev->dev); 2292 2293 pci_set_drvdata(pdev, netdev); 2294 adapter = netdev_priv(netdev); 2295 adapter->netdev = netdev; 2296 adapter->pdev = pdev; 2297 hw = &adapter->hw; 2298 hw->back = adapter; 2299 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2300 2301 err = -EIO; 2302 hw->hw_addr = pci_iomap(pdev, 0, 0); 2303 if (!hw->hw_addr) 2304 goto err_ioremap; 2305 2306 netdev->netdev_ops = &igb_netdev_ops; 2307 igb_set_ethtool_ops(netdev); 2308 netdev->watchdog_timeo = 5 * HZ; 2309 2310 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2311 2312 netdev->mem_start = pci_resource_start(pdev, 0); 2313 netdev->mem_end = pci_resource_end(pdev, 0); 2314 2315 /* PCI config space info */ 2316 hw->vendor_id = pdev->vendor; 2317 hw->device_id = pdev->device; 2318 hw->revision_id = pdev->revision; 2319 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2320 hw->subsystem_device_id = pdev->subsystem_device; 2321 2322 /* Copy the default MAC, PHY and NVM function pointers */ 2323 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2324 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2325 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2326 /* Initialize skew-specific constants */ 2327 err = ei->get_invariants(hw); 2328 if (err) 2329 goto err_sw_init; 2330 2331 /* setup the private structure */ 2332 err = igb_sw_init(adapter); 2333 if (err) 2334 goto err_sw_init; 2335 2336 igb_get_bus_info_pcie(hw); 2337 2338 hw->phy.autoneg_wait_to_complete = false; 2339 2340 /* Copper options */ 2341 if (hw->phy.media_type == e1000_media_type_copper) { 2342 hw->phy.mdix = AUTO_ALL_MODES; 2343 hw->phy.disable_polarity_correction = false; 2344 hw->phy.ms_type = e1000_ms_hw_default; 2345 } 2346 2347 if (igb_check_reset_block(hw)) 2348 dev_info(&pdev->dev, 2349 "PHY reset is blocked due to SOL/IDER session.\n"); 2350 2351 /* features is initialized to 0 in allocation, it might have bits 2352 * set by igb_sw_init so we should use an or instead of an 2353 * assignment. 2354 */ 2355 netdev->features |= NETIF_F_SG | 2356 NETIF_F_IP_CSUM | 2357 NETIF_F_IPV6_CSUM | 2358 NETIF_F_TSO | 2359 NETIF_F_TSO6 | 2360 NETIF_F_RXHASH | 2361 NETIF_F_RXCSUM | 2362 NETIF_F_HW_VLAN_CTAG_RX | 2363 NETIF_F_HW_VLAN_CTAG_TX; 2364 2365 /* copy netdev features into list of user selectable features */ 2366 netdev->hw_features |= netdev->features; 2367 netdev->hw_features |= NETIF_F_RXALL; 2368 2369 /* set this bit last since it cannot be part of hw_features */ 2370 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2371 2372 netdev->vlan_features |= NETIF_F_TSO | 2373 NETIF_F_TSO6 | 2374 NETIF_F_IP_CSUM | 2375 NETIF_F_IPV6_CSUM | 2376 NETIF_F_SG; 2377 2378 netdev->priv_flags |= IFF_SUPP_NOFCS; 2379 2380 if (pci_using_dac) { 2381 netdev->features |= NETIF_F_HIGHDMA; 2382 netdev->vlan_features |= NETIF_F_HIGHDMA; 2383 } 2384 2385 if (hw->mac.type >= e1000_82576) { 2386 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2387 netdev->features |= NETIF_F_SCTP_CSUM; 2388 } 2389 2390 netdev->priv_flags |= IFF_UNICAST_FLT; 2391 2392 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2393 2394 /* before reading the NVM, reset the controller to put the device in a 2395 * known good starting state 2396 */ 2397 hw->mac.ops.reset_hw(hw); 2398 2399 /* make sure the NVM is good , i211/i210 parts can have special NVM 2400 * that doesn't contain a checksum 2401 */ 2402 switch (hw->mac.type) { 2403 case e1000_i210: 2404 case e1000_i211: 2405 if (igb_get_flash_presence_i210(hw)) { 2406 if (hw->nvm.ops.validate(hw) < 0) { 2407 dev_err(&pdev->dev, 2408 "The NVM Checksum Is Not Valid\n"); 2409 err = -EIO; 2410 goto err_eeprom; 2411 } 2412 } 2413 break; 2414 default: 2415 if (hw->nvm.ops.validate(hw) < 0) { 2416 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2417 err = -EIO; 2418 goto err_eeprom; 2419 } 2420 break; 2421 } 2422 2423 /* copy the MAC address out of the NVM */ 2424 if (hw->mac.ops.read_mac_addr(hw)) 2425 dev_err(&pdev->dev, "NVM Read Error\n"); 2426 2427 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2428 2429 if (!is_valid_ether_addr(netdev->dev_addr)) { 2430 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2431 err = -EIO; 2432 goto err_eeprom; 2433 } 2434 2435 /* get firmware version for ethtool -i */ 2436 igb_set_fw_version(adapter); 2437 2438 /* configure RXPBSIZE and TXPBSIZE */ 2439 if (hw->mac.type == e1000_i210) { 2440 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2441 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2442 } 2443 2444 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2445 (unsigned long) adapter); 2446 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2447 (unsigned long) adapter); 2448 2449 INIT_WORK(&adapter->reset_task, igb_reset_task); 2450 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2451 2452 /* Initialize link properties that are user-changeable */ 2453 adapter->fc_autoneg = true; 2454 hw->mac.autoneg = true; 2455 hw->phy.autoneg_advertised = 0x2f; 2456 2457 hw->fc.requested_mode = e1000_fc_default; 2458 hw->fc.current_mode = e1000_fc_default; 2459 2460 igb_validate_mdi_setting(hw); 2461 2462 /* By default, support wake on port A */ 2463 if (hw->bus.func == 0) 2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2465 2466 /* Check the NVM for wake support on non-port A ports */ 2467 if (hw->mac.type >= e1000_82580) 2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2469 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2470 &eeprom_data); 2471 else if (hw->bus.func == 1) 2472 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2473 2474 if (eeprom_data & IGB_EEPROM_APME) 2475 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2476 2477 /* now that we have the eeprom settings, apply the special cases where 2478 * the eeprom may be wrong or the board simply won't support wake on 2479 * lan on a particular port 2480 */ 2481 switch (pdev->device) { 2482 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2483 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2484 break; 2485 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2486 case E1000_DEV_ID_82576_FIBER: 2487 case E1000_DEV_ID_82576_SERDES: 2488 /* Wake events only supported on port A for dual fiber 2489 * regardless of eeprom setting 2490 */ 2491 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2492 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2493 break; 2494 case E1000_DEV_ID_82576_QUAD_COPPER: 2495 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2496 /* if quad port adapter, disable WoL on all but port A */ 2497 if (global_quad_port_a != 0) 2498 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2499 else 2500 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2501 /* Reset for multiple quad port adapters */ 2502 if (++global_quad_port_a == 4) 2503 global_quad_port_a = 0; 2504 break; 2505 default: 2506 /* If the device can't wake, don't set software support */ 2507 if (!device_can_wakeup(&adapter->pdev->dev)) 2508 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2509 } 2510 2511 /* initialize the wol settings based on the eeprom settings */ 2512 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2513 adapter->wol |= E1000_WUFC_MAG; 2514 2515 /* Some vendors want WoL disabled by default, but still supported */ 2516 if ((hw->mac.type == e1000_i350) && 2517 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2518 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2519 adapter->wol = 0; 2520 } 2521 2522 device_set_wakeup_enable(&adapter->pdev->dev, 2523 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2524 2525 /* reset the hardware with the new settings */ 2526 igb_reset(adapter); 2527 2528 /* Init the I2C interface */ 2529 err = igb_init_i2c(adapter); 2530 if (err) { 2531 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2532 goto err_eeprom; 2533 } 2534 2535 /* let the f/w know that the h/w is now under the control of the 2536 * driver. 2537 */ 2538 igb_get_hw_control(adapter); 2539 2540 strcpy(netdev->name, "eth%d"); 2541 err = register_netdev(netdev); 2542 if (err) 2543 goto err_register; 2544 2545 /* carrier off reporting is important to ethtool even BEFORE open */ 2546 netif_carrier_off(netdev); 2547 2548 #ifdef CONFIG_IGB_DCA 2549 if (dca_add_requester(&pdev->dev) == 0) { 2550 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2551 dev_info(&pdev->dev, "DCA enabled\n"); 2552 igb_setup_dca(adapter); 2553 } 2554 2555 #endif 2556 #ifdef CONFIG_IGB_HWMON 2557 /* Initialize the thermal sensor on i350 devices. */ 2558 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2559 u16 ets_word; 2560 2561 /* Read the NVM to determine if this i350 device supports an 2562 * external thermal sensor. 2563 */ 2564 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2565 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2566 adapter->ets = true; 2567 else 2568 adapter->ets = false; 2569 if (igb_sysfs_init(adapter)) 2570 dev_err(&pdev->dev, 2571 "failed to allocate sysfs resources\n"); 2572 } else { 2573 adapter->ets = false; 2574 } 2575 #endif 2576 /* Check if Media Autosense is enabled */ 2577 adapter->ei = *ei; 2578 if (hw->dev_spec._82575.mas_capable) 2579 igb_init_mas(adapter); 2580 2581 /* do hw tstamp init after resetting */ 2582 igb_ptp_init(adapter); 2583 2584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2585 /* print bus type/speed/width info, not applicable to i354 */ 2586 if (hw->mac.type != e1000_i354) { 2587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2588 netdev->name, 2589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2591 "unknown"), 2592 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2593 "Width x4" : 2594 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2595 "Width x2" : 2596 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2597 "Width x1" : "unknown"), netdev->dev_addr); 2598 } 2599 2600 if ((hw->mac.type >= e1000_i210 || 2601 igb_get_flash_presence_i210(hw))) { 2602 ret_val = igb_read_part_string(hw, part_str, 2603 E1000_PBANUM_LENGTH); 2604 } else { 2605 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2606 } 2607 2608 if (ret_val) 2609 strcpy(part_str, "Unknown"); 2610 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2611 dev_info(&pdev->dev, 2612 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2613 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2614 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2615 adapter->num_rx_queues, adapter->num_tx_queues); 2616 if (hw->phy.media_type == e1000_media_type_copper) { 2617 switch (hw->mac.type) { 2618 case e1000_i350: 2619 case e1000_i210: 2620 case e1000_i211: 2621 /* Enable EEE for internal copper PHY devices */ 2622 err = igb_set_eee_i350(hw, true, true); 2623 if ((!err) && 2624 (!hw->dev_spec._82575.eee_disable)) { 2625 adapter->eee_advert = 2626 MDIO_EEE_100TX | MDIO_EEE_1000T; 2627 adapter->flags |= IGB_FLAG_EEE; 2628 } 2629 break; 2630 case e1000_i354: 2631 if ((rd32(E1000_CTRL_EXT) & 2632 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2633 err = igb_set_eee_i354(hw, true, true); 2634 if ((!err) && 2635 (!hw->dev_spec._82575.eee_disable)) { 2636 adapter->eee_advert = 2637 MDIO_EEE_100TX | MDIO_EEE_1000T; 2638 adapter->flags |= IGB_FLAG_EEE; 2639 } 2640 } 2641 break; 2642 default: 2643 break; 2644 } 2645 } 2646 pm_runtime_put_noidle(&pdev->dev); 2647 return 0; 2648 2649 err_register: 2650 igb_release_hw_control(adapter); 2651 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2652 err_eeprom: 2653 if (!igb_check_reset_block(hw)) 2654 igb_reset_phy(hw); 2655 2656 if (hw->flash_address) 2657 iounmap(hw->flash_address); 2658 err_sw_init: 2659 igb_clear_interrupt_scheme(adapter); 2660 pci_iounmap(pdev, hw->hw_addr); 2661 err_ioremap: 2662 free_netdev(netdev); 2663 err_alloc_etherdev: 2664 pci_release_selected_regions(pdev, 2665 pci_select_bars(pdev, IORESOURCE_MEM)); 2666 err_pci_reg: 2667 err_dma: 2668 pci_disable_device(pdev); 2669 return err; 2670 } 2671 2672 #ifdef CONFIG_PCI_IOV 2673 static int igb_disable_sriov(struct pci_dev *pdev) 2674 { 2675 struct net_device *netdev = pci_get_drvdata(pdev); 2676 struct igb_adapter *adapter = netdev_priv(netdev); 2677 struct e1000_hw *hw = &adapter->hw; 2678 2679 /* reclaim resources allocated to VFs */ 2680 if (adapter->vf_data) { 2681 /* disable iov and allow time for transactions to clear */ 2682 if (pci_vfs_assigned(pdev)) { 2683 dev_warn(&pdev->dev, 2684 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2685 return -EPERM; 2686 } else { 2687 pci_disable_sriov(pdev); 2688 msleep(500); 2689 } 2690 2691 kfree(adapter->vf_data); 2692 adapter->vf_data = NULL; 2693 adapter->vfs_allocated_count = 0; 2694 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2695 wrfl(); 2696 msleep(100); 2697 dev_info(&pdev->dev, "IOV Disabled\n"); 2698 2699 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2700 adapter->flags |= IGB_FLAG_DMAC; 2701 } 2702 2703 return 0; 2704 } 2705 2706 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2707 { 2708 struct net_device *netdev = pci_get_drvdata(pdev); 2709 struct igb_adapter *adapter = netdev_priv(netdev); 2710 int old_vfs = pci_num_vf(pdev); 2711 int err = 0; 2712 int i; 2713 2714 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2715 err = -EPERM; 2716 goto out; 2717 } 2718 if (!num_vfs) 2719 goto out; 2720 2721 if (old_vfs) { 2722 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2723 old_vfs, max_vfs); 2724 adapter->vfs_allocated_count = old_vfs; 2725 } else 2726 adapter->vfs_allocated_count = num_vfs; 2727 2728 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2729 sizeof(struct vf_data_storage), GFP_KERNEL); 2730 2731 /* if allocation failed then we do not support SR-IOV */ 2732 if (!adapter->vf_data) { 2733 adapter->vfs_allocated_count = 0; 2734 dev_err(&pdev->dev, 2735 "Unable to allocate memory for VF Data Storage\n"); 2736 err = -ENOMEM; 2737 goto out; 2738 } 2739 2740 /* only call pci_enable_sriov() if no VFs are allocated already */ 2741 if (!old_vfs) { 2742 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2743 if (err) 2744 goto err_out; 2745 } 2746 dev_info(&pdev->dev, "%d VFs allocated\n", 2747 adapter->vfs_allocated_count); 2748 for (i = 0; i < adapter->vfs_allocated_count; i++) 2749 igb_vf_configure(adapter, i); 2750 2751 /* DMA Coalescing is not supported in IOV mode. */ 2752 adapter->flags &= ~IGB_FLAG_DMAC; 2753 goto out; 2754 2755 err_out: 2756 kfree(adapter->vf_data); 2757 adapter->vf_data = NULL; 2758 adapter->vfs_allocated_count = 0; 2759 out: 2760 return err; 2761 } 2762 2763 #endif 2764 /** 2765 * igb_remove_i2c - Cleanup I2C interface 2766 * @adapter: pointer to adapter structure 2767 **/ 2768 static void igb_remove_i2c(struct igb_adapter *adapter) 2769 { 2770 /* free the adapter bus structure */ 2771 i2c_del_adapter(&adapter->i2c_adap); 2772 } 2773 2774 /** 2775 * igb_remove - Device Removal Routine 2776 * @pdev: PCI device information struct 2777 * 2778 * igb_remove is called by the PCI subsystem to alert the driver 2779 * that it should release a PCI device. The could be caused by a 2780 * Hot-Plug event, or because the driver is going to be removed from 2781 * memory. 2782 **/ 2783 static void igb_remove(struct pci_dev *pdev) 2784 { 2785 struct net_device *netdev = pci_get_drvdata(pdev); 2786 struct igb_adapter *adapter = netdev_priv(netdev); 2787 struct e1000_hw *hw = &adapter->hw; 2788 2789 pm_runtime_get_noresume(&pdev->dev); 2790 #ifdef CONFIG_IGB_HWMON 2791 igb_sysfs_exit(adapter); 2792 #endif 2793 igb_remove_i2c(adapter); 2794 igb_ptp_stop(adapter); 2795 /* The watchdog timer may be rescheduled, so explicitly 2796 * disable watchdog from being rescheduled. 2797 */ 2798 set_bit(__IGB_DOWN, &adapter->state); 2799 del_timer_sync(&adapter->watchdog_timer); 2800 del_timer_sync(&adapter->phy_info_timer); 2801 2802 cancel_work_sync(&adapter->reset_task); 2803 cancel_work_sync(&adapter->watchdog_task); 2804 2805 #ifdef CONFIG_IGB_DCA 2806 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2807 dev_info(&pdev->dev, "DCA disabled\n"); 2808 dca_remove_requester(&pdev->dev); 2809 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2811 } 2812 #endif 2813 2814 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2815 * would have already happened in close and is redundant. 2816 */ 2817 igb_release_hw_control(adapter); 2818 2819 unregister_netdev(netdev); 2820 2821 igb_clear_interrupt_scheme(adapter); 2822 2823 #ifdef CONFIG_PCI_IOV 2824 igb_disable_sriov(pdev); 2825 #endif 2826 2827 pci_iounmap(pdev, hw->hw_addr); 2828 if (hw->flash_address) 2829 iounmap(hw->flash_address); 2830 pci_release_selected_regions(pdev, 2831 pci_select_bars(pdev, IORESOURCE_MEM)); 2832 2833 kfree(adapter->shadow_vfta); 2834 free_netdev(netdev); 2835 2836 pci_disable_pcie_error_reporting(pdev); 2837 2838 pci_disable_device(pdev); 2839 } 2840 2841 /** 2842 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2843 * @adapter: board private structure to initialize 2844 * 2845 * This function initializes the vf specific data storage and then attempts to 2846 * allocate the VFs. The reason for ordering it this way is because it is much 2847 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2848 * the memory for the VFs. 2849 **/ 2850 static void igb_probe_vfs(struct igb_adapter *adapter) 2851 { 2852 #ifdef CONFIG_PCI_IOV 2853 struct pci_dev *pdev = adapter->pdev; 2854 struct e1000_hw *hw = &adapter->hw; 2855 2856 /* Virtualization features not supported on i210 family. */ 2857 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2858 return; 2859 2860 pci_sriov_set_totalvfs(pdev, 7); 2861 igb_pci_enable_sriov(pdev, max_vfs); 2862 2863 #endif /* CONFIG_PCI_IOV */ 2864 } 2865 2866 static void igb_init_queue_configuration(struct igb_adapter *adapter) 2867 { 2868 struct e1000_hw *hw = &adapter->hw; 2869 u32 max_rss_queues; 2870 2871 /* Determine the maximum number of RSS queues supported. */ 2872 switch (hw->mac.type) { 2873 case e1000_i211: 2874 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2875 break; 2876 case e1000_82575: 2877 case e1000_i210: 2878 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2879 break; 2880 case e1000_i350: 2881 /* I350 cannot do RSS and SR-IOV at the same time */ 2882 if (!!adapter->vfs_allocated_count) { 2883 max_rss_queues = 1; 2884 break; 2885 } 2886 /* fall through */ 2887 case e1000_82576: 2888 if (!!adapter->vfs_allocated_count) { 2889 max_rss_queues = 2; 2890 break; 2891 } 2892 /* fall through */ 2893 case e1000_82580: 2894 case e1000_i354: 2895 default: 2896 max_rss_queues = IGB_MAX_RX_QUEUES; 2897 break; 2898 } 2899 2900 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2901 2902 /* Determine if we need to pair queues. */ 2903 switch (hw->mac.type) { 2904 case e1000_82575: 2905 case e1000_i211: 2906 /* Device supports enough interrupts without queue pairing. */ 2907 break; 2908 case e1000_82576: 2909 /* If VFs are going to be allocated with RSS queues then we 2910 * should pair the queues in order to conserve interrupts due 2911 * to limited supply. 2912 */ 2913 if ((adapter->rss_queues > 1) && 2914 (adapter->vfs_allocated_count > 6)) 2915 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2916 /* fall through */ 2917 case e1000_82580: 2918 case e1000_i350: 2919 case e1000_i354: 2920 case e1000_i210: 2921 default: 2922 /* If rss_queues > half of max_rss_queues, pair the queues in 2923 * order to conserve interrupts due to limited supply. 2924 */ 2925 if (adapter->rss_queues > (max_rss_queues / 2)) 2926 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2927 break; 2928 } 2929 } 2930 2931 /** 2932 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2933 * @adapter: board private structure to initialize 2934 * 2935 * igb_sw_init initializes the Adapter private data structure. 2936 * Fields are initialized based on PCI device information and 2937 * OS network device settings (MTU size). 2938 **/ 2939 static int igb_sw_init(struct igb_adapter *adapter) 2940 { 2941 struct e1000_hw *hw = &adapter->hw; 2942 struct net_device *netdev = adapter->netdev; 2943 struct pci_dev *pdev = adapter->pdev; 2944 2945 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2946 2947 /* set default ring sizes */ 2948 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2949 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2950 2951 /* set default ITR values */ 2952 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2953 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2954 2955 /* set default work limits */ 2956 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2957 2958 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2959 VLAN_HLEN; 2960 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2961 2962 spin_lock_init(&adapter->stats64_lock); 2963 #ifdef CONFIG_PCI_IOV 2964 switch (hw->mac.type) { 2965 case e1000_82576: 2966 case e1000_i350: 2967 if (max_vfs > 7) { 2968 dev_warn(&pdev->dev, 2969 "Maximum of 7 VFs per PF, using max\n"); 2970 max_vfs = adapter->vfs_allocated_count = 7; 2971 } else 2972 adapter->vfs_allocated_count = max_vfs; 2973 if (adapter->vfs_allocated_count) 2974 dev_warn(&pdev->dev, 2975 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2976 break; 2977 default: 2978 break; 2979 } 2980 #endif /* CONFIG_PCI_IOV */ 2981 2982 igb_init_queue_configuration(adapter); 2983 2984 /* Setup and initialize a copy of the hw vlan table array */ 2985 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2986 GFP_ATOMIC); 2987 2988 /* This call may decrease the number of queues */ 2989 if (igb_init_interrupt_scheme(adapter, true)) { 2990 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2991 return -ENOMEM; 2992 } 2993 2994 igb_probe_vfs(adapter); 2995 2996 /* Explicitly disable IRQ since the NIC can be in any state. */ 2997 igb_irq_disable(adapter); 2998 2999 if (hw->mac.type >= e1000_i350) 3000 adapter->flags &= ~IGB_FLAG_DMAC; 3001 3002 set_bit(__IGB_DOWN, &adapter->state); 3003 return 0; 3004 } 3005 3006 /** 3007 * igb_open - Called when a network interface is made active 3008 * @netdev: network interface device structure 3009 * 3010 * Returns 0 on success, negative value on failure 3011 * 3012 * The open entry point is called when a network interface is made 3013 * active by the system (IFF_UP). At this point all resources needed 3014 * for transmit and receive operations are allocated, the interrupt 3015 * handler is registered with the OS, the watchdog timer is started, 3016 * and the stack is notified that the interface is ready. 3017 **/ 3018 static int __igb_open(struct net_device *netdev, bool resuming) 3019 { 3020 struct igb_adapter *adapter = netdev_priv(netdev); 3021 struct e1000_hw *hw = &adapter->hw; 3022 struct pci_dev *pdev = adapter->pdev; 3023 int err; 3024 int i; 3025 3026 /* disallow open during test */ 3027 if (test_bit(__IGB_TESTING, &adapter->state)) { 3028 WARN_ON(resuming); 3029 return -EBUSY; 3030 } 3031 3032 if (!resuming) 3033 pm_runtime_get_sync(&pdev->dev); 3034 3035 netif_carrier_off(netdev); 3036 3037 /* allocate transmit descriptors */ 3038 err = igb_setup_all_tx_resources(adapter); 3039 if (err) 3040 goto err_setup_tx; 3041 3042 /* allocate receive descriptors */ 3043 err = igb_setup_all_rx_resources(adapter); 3044 if (err) 3045 goto err_setup_rx; 3046 3047 igb_power_up_link(adapter); 3048 3049 /* before we allocate an interrupt, we must be ready to handle it. 3050 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3051 * as soon as we call pci_request_irq, so we have to setup our 3052 * clean_rx handler before we do so. 3053 */ 3054 igb_configure(adapter); 3055 3056 err = igb_request_irq(adapter); 3057 if (err) 3058 goto err_req_irq; 3059 3060 /* Notify the stack of the actual queue counts. */ 3061 err = netif_set_real_num_tx_queues(adapter->netdev, 3062 adapter->num_tx_queues); 3063 if (err) 3064 goto err_set_queues; 3065 3066 err = netif_set_real_num_rx_queues(adapter->netdev, 3067 adapter->num_rx_queues); 3068 if (err) 3069 goto err_set_queues; 3070 3071 /* From here on the code is the same as igb_up() */ 3072 clear_bit(__IGB_DOWN, &adapter->state); 3073 3074 for (i = 0; i < adapter->num_q_vectors; i++) 3075 napi_enable(&(adapter->q_vector[i]->napi)); 3076 3077 /* Clear any pending interrupts. */ 3078 rd32(E1000_ICR); 3079 3080 igb_irq_enable(adapter); 3081 3082 /* notify VFs that reset has been completed */ 3083 if (adapter->vfs_allocated_count) { 3084 u32 reg_data = rd32(E1000_CTRL_EXT); 3085 3086 reg_data |= E1000_CTRL_EXT_PFRSTD; 3087 wr32(E1000_CTRL_EXT, reg_data); 3088 } 3089 3090 netif_tx_start_all_queues(netdev); 3091 3092 if (!resuming) 3093 pm_runtime_put(&pdev->dev); 3094 3095 /* start the watchdog. */ 3096 hw->mac.get_link_status = 1; 3097 schedule_work(&adapter->watchdog_task); 3098 3099 return 0; 3100 3101 err_set_queues: 3102 igb_free_irq(adapter); 3103 err_req_irq: 3104 igb_release_hw_control(adapter); 3105 igb_power_down_link(adapter); 3106 igb_free_all_rx_resources(adapter); 3107 err_setup_rx: 3108 igb_free_all_tx_resources(adapter); 3109 err_setup_tx: 3110 igb_reset(adapter); 3111 if (!resuming) 3112 pm_runtime_put(&pdev->dev); 3113 3114 return err; 3115 } 3116 3117 static int igb_open(struct net_device *netdev) 3118 { 3119 return __igb_open(netdev, false); 3120 } 3121 3122 /** 3123 * igb_close - Disables a network interface 3124 * @netdev: network interface device structure 3125 * 3126 * Returns 0, this is not allowed to fail 3127 * 3128 * The close entry point is called when an interface is de-activated 3129 * by the OS. The hardware is still under the driver's control, but 3130 * needs to be disabled. A global MAC reset is issued to stop the 3131 * hardware, and all transmit and receive resources are freed. 3132 **/ 3133 static int __igb_close(struct net_device *netdev, bool suspending) 3134 { 3135 struct igb_adapter *adapter = netdev_priv(netdev); 3136 struct pci_dev *pdev = adapter->pdev; 3137 3138 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3139 3140 if (!suspending) 3141 pm_runtime_get_sync(&pdev->dev); 3142 3143 igb_down(adapter); 3144 igb_free_irq(adapter); 3145 3146 igb_free_all_tx_resources(adapter); 3147 igb_free_all_rx_resources(adapter); 3148 3149 if (!suspending) 3150 pm_runtime_put_sync(&pdev->dev); 3151 return 0; 3152 } 3153 3154 static int igb_close(struct net_device *netdev) 3155 { 3156 return __igb_close(netdev, false); 3157 } 3158 3159 /** 3160 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3161 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3162 * 3163 * Return 0 on success, negative on failure 3164 **/ 3165 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3166 { 3167 struct device *dev = tx_ring->dev; 3168 int size; 3169 3170 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3171 3172 tx_ring->tx_buffer_info = vzalloc(size); 3173 if (!tx_ring->tx_buffer_info) 3174 goto err; 3175 3176 /* round up to nearest 4K */ 3177 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3178 tx_ring->size = ALIGN(tx_ring->size, 4096); 3179 3180 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3181 &tx_ring->dma, GFP_KERNEL); 3182 if (!tx_ring->desc) 3183 goto err; 3184 3185 tx_ring->next_to_use = 0; 3186 tx_ring->next_to_clean = 0; 3187 3188 return 0; 3189 3190 err: 3191 vfree(tx_ring->tx_buffer_info); 3192 tx_ring->tx_buffer_info = NULL; 3193 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3194 return -ENOMEM; 3195 } 3196 3197 /** 3198 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3199 * (Descriptors) for all queues 3200 * @adapter: board private structure 3201 * 3202 * Return 0 on success, negative on failure 3203 **/ 3204 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3205 { 3206 struct pci_dev *pdev = adapter->pdev; 3207 int i, err = 0; 3208 3209 for (i = 0; i < adapter->num_tx_queues; i++) { 3210 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3211 if (err) { 3212 dev_err(&pdev->dev, 3213 "Allocation for Tx Queue %u failed\n", i); 3214 for (i--; i >= 0; i--) 3215 igb_free_tx_resources(adapter->tx_ring[i]); 3216 break; 3217 } 3218 } 3219 3220 return err; 3221 } 3222 3223 /** 3224 * igb_setup_tctl - configure the transmit control registers 3225 * @adapter: Board private structure 3226 **/ 3227 void igb_setup_tctl(struct igb_adapter *adapter) 3228 { 3229 struct e1000_hw *hw = &adapter->hw; 3230 u32 tctl; 3231 3232 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3233 wr32(E1000_TXDCTL(0), 0); 3234 3235 /* Program the Transmit Control Register */ 3236 tctl = rd32(E1000_TCTL); 3237 tctl &= ~E1000_TCTL_CT; 3238 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3239 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3240 3241 igb_config_collision_dist(hw); 3242 3243 /* Enable transmits */ 3244 tctl |= E1000_TCTL_EN; 3245 3246 wr32(E1000_TCTL, tctl); 3247 } 3248 3249 /** 3250 * igb_configure_tx_ring - Configure transmit ring after Reset 3251 * @adapter: board private structure 3252 * @ring: tx ring to configure 3253 * 3254 * Configure a transmit ring after a reset. 3255 **/ 3256 void igb_configure_tx_ring(struct igb_adapter *adapter, 3257 struct igb_ring *ring) 3258 { 3259 struct e1000_hw *hw = &adapter->hw; 3260 u32 txdctl = 0; 3261 u64 tdba = ring->dma; 3262 int reg_idx = ring->reg_idx; 3263 3264 /* disable the queue */ 3265 wr32(E1000_TXDCTL(reg_idx), 0); 3266 wrfl(); 3267 mdelay(10); 3268 3269 wr32(E1000_TDLEN(reg_idx), 3270 ring->count * sizeof(union e1000_adv_tx_desc)); 3271 wr32(E1000_TDBAL(reg_idx), 3272 tdba & 0x00000000ffffffffULL); 3273 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3274 3275 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3276 wr32(E1000_TDH(reg_idx), 0); 3277 writel(0, ring->tail); 3278 3279 txdctl |= IGB_TX_PTHRESH; 3280 txdctl |= IGB_TX_HTHRESH << 8; 3281 txdctl |= IGB_TX_WTHRESH << 16; 3282 3283 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3284 wr32(E1000_TXDCTL(reg_idx), txdctl); 3285 } 3286 3287 /** 3288 * igb_configure_tx - Configure transmit Unit after Reset 3289 * @adapter: board private structure 3290 * 3291 * Configure the Tx unit of the MAC after a reset. 3292 **/ 3293 static void igb_configure_tx(struct igb_adapter *adapter) 3294 { 3295 int i; 3296 3297 for (i = 0; i < adapter->num_tx_queues; i++) 3298 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3299 } 3300 3301 /** 3302 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3303 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3304 * 3305 * Returns 0 on success, negative on failure 3306 **/ 3307 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3308 { 3309 struct device *dev = rx_ring->dev; 3310 int size; 3311 3312 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3313 3314 rx_ring->rx_buffer_info = vzalloc(size); 3315 if (!rx_ring->rx_buffer_info) 3316 goto err; 3317 3318 /* Round up to nearest 4K */ 3319 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3320 rx_ring->size = ALIGN(rx_ring->size, 4096); 3321 3322 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3323 &rx_ring->dma, GFP_KERNEL); 3324 if (!rx_ring->desc) 3325 goto err; 3326 3327 rx_ring->next_to_alloc = 0; 3328 rx_ring->next_to_clean = 0; 3329 rx_ring->next_to_use = 0; 3330 3331 return 0; 3332 3333 err: 3334 vfree(rx_ring->rx_buffer_info); 3335 rx_ring->rx_buffer_info = NULL; 3336 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3337 return -ENOMEM; 3338 } 3339 3340 /** 3341 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3342 * (Descriptors) for all queues 3343 * @adapter: board private structure 3344 * 3345 * Return 0 on success, negative on failure 3346 **/ 3347 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3348 { 3349 struct pci_dev *pdev = adapter->pdev; 3350 int i, err = 0; 3351 3352 for (i = 0; i < adapter->num_rx_queues; i++) { 3353 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3354 if (err) { 3355 dev_err(&pdev->dev, 3356 "Allocation for Rx Queue %u failed\n", i); 3357 for (i--; i >= 0; i--) 3358 igb_free_rx_resources(adapter->rx_ring[i]); 3359 break; 3360 } 3361 } 3362 3363 return err; 3364 } 3365 3366 /** 3367 * igb_setup_mrqc - configure the multiple receive queue control registers 3368 * @adapter: Board private structure 3369 **/ 3370 static void igb_setup_mrqc(struct igb_adapter *adapter) 3371 { 3372 struct e1000_hw *hw = &adapter->hw; 3373 u32 mrqc, rxcsum; 3374 u32 j, num_rx_queues; 3375 u32 rss_key[10]; 3376 3377 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3378 for (j = 0; j < 10; j++) 3379 wr32(E1000_RSSRK(j), rss_key[j]); 3380 3381 num_rx_queues = adapter->rss_queues; 3382 3383 switch (hw->mac.type) { 3384 case e1000_82576: 3385 /* 82576 supports 2 RSS queues for SR-IOV */ 3386 if (adapter->vfs_allocated_count) 3387 num_rx_queues = 2; 3388 break; 3389 default: 3390 break; 3391 } 3392 3393 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3394 for (j = 0; j < IGB_RETA_SIZE; j++) 3395 adapter->rss_indir_tbl[j] = 3396 (j * num_rx_queues) / IGB_RETA_SIZE; 3397 adapter->rss_indir_tbl_init = num_rx_queues; 3398 } 3399 igb_write_rss_indir_tbl(adapter); 3400 3401 /* Disable raw packet checksumming so that RSS hash is placed in 3402 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3403 * offloads as they are enabled by default 3404 */ 3405 rxcsum = rd32(E1000_RXCSUM); 3406 rxcsum |= E1000_RXCSUM_PCSD; 3407 3408 if (adapter->hw.mac.type >= e1000_82576) 3409 /* Enable Receive Checksum Offload for SCTP */ 3410 rxcsum |= E1000_RXCSUM_CRCOFL; 3411 3412 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3413 wr32(E1000_RXCSUM, rxcsum); 3414 3415 /* Generate RSS hash based on packet types, TCP/UDP 3416 * port numbers and/or IPv4/v6 src and dst addresses 3417 */ 3418 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3419 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3420 E1000_MRQC_RSS_FIELD_IPV6 | 3421 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3422 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3423 3424 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3425 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3426 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3427 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3428 3429 /* If VMDq is enabled then we set the appropriate mode for that, else 3430 * we default to RSS so that an RSS hash is calculated per packet even 3431 * if we are only using one queue 3432 */ 3433 if (adapter->vfs_allocated_count) { 3434 if (hw->mac.type > e1000_82575) { 3435 /* Set the default pool for the PF's first queue */ 3436 u32 vtctl = rd32(E1000_VT_CTL); 3437 3438 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3439 E1000_VT_CTL_DISABLE_DEF_POOL); 3440 vtctl |= adapter->vfs_allocated_count << 3441 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3442 wr32(E1000_VT_CTL, vtctl); 3443 } 3444 if (adapter->rss_queues > 1) 3445 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3446 else 3447 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3448 } else { 3449 if (hw->mac.type != e1000_i211) 3450 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3451 } 3452 igb_vmm_control(adapter); 3453 3454 wr32(E1000_MRQC, mrqc); 3455 } 3456 3457 /** 3458 * igb_setup_rctl - configure the receive control registers 3459 * @adapter: Board private structure 3460 **/ 3461 void igb_setup_rctl(struct igb_adapter *adapter) 3462 { 3463 struct e1000_hw *hw = &adapter->hw; 3464 u32 rctl; 3465 3466 rctl = rd32(E1000_RCTL); 3467 3468 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3469 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3470 3471 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3472 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3473 3474 /* enable stripping of CRC. It's unlikely this will break BMC 3475 * redirection as it did with e1000. Newer features require 3476 * that the HW strips the CRC. 3477 */ 3478 rctl |= E1000_RCTL_SECRC; 3479 3480 /* disable store bad packets and clear size bits. */ 3481 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3482 3483 /* enable LPE to prevent packets larger than max_frame_size */ 3484 rctl |= E1000_RCTL_LPE; 3485 3486 /* disable queue 0 to prevent tail write w/o re-config */ 3487 wr32(E1000_RXDCTL(0), 0); 3488 3489 /* Attention!!! For SR-IOV PF driver operations you must enable 3490 * queue drop for all VF and PF queues to prevent head of line blocking 3491 * if an un-trusted VF does not provide descriptors to hardware. 3492 */ 3493 if (adapter->vfs_allocated_count) { 3494 /* set all queue drop enable bits */ 3495 wr32(E1000_QDE, ALL_QUEUES); 3496 } 3497 3498 /* This is useful for sniffing bad packets. */ 3499 if (adapter->netdev->features & NETIF_F_RXALL) { 3500 /* UPE and MPE will be handled by normal PROMISC logic 3501 * in e1000e_set_rx_mode 3502 */ 3503 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3504 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3505 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3506 3507 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3508 E1000_RCTL_DPF | /* Allow filtered pause */ 3509 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3510 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3511 * and that breaks VLANs. 3512 */ 3513 } 3514 3515 wr32(E1000_RCTL, rctl); 3516 } 3517 3518 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3519 int vfn) 3520 { 3521 struct e1000_hw *hw = &adapter->hw; 3522 u32 vmolr; 3523 3524 /* if it isn't the PF check to see if VFs are enabled and 3525 * increase the size to support vlan tags 3526 */ 3527 if (vfn < adapter->vfs_allocated_count && 3528 adapter->vf_data[vfn].vlans_enabled) 3529 size += VLAN_TAG_SIZE; 3530 3531 vmolr = rd32(E1000_VMOLR(vfn)); 3532 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3533 vmolr |= size | E1000_VMOLR_LPE; 3534 wr32(E1000_VMOLR(vfn), vmolr); 3535 3536 return 0; 3537 } 3538 3539 /** 3540 * igb_rlpml_set - set maximum receive packet size 3541 * @adapter: board private structure 3542 * 3543 * Configure maximum receivable packet size. 3544 **/ 3545 static void igb_rlpml_set(struct igb_adapter *adapter) 3546 { 3547 u32 max_frame_size = adapter->max_frame_size; 3548 struct e1000_hw *hw = &adapter->hw; 3549 u16 pf_id = adapter->vfs_allocated_count; 3550 3551 if (pf_id) { 3552 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3553 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3554 * to our max jumbo frame size, in case we need to enable 3555 * jumbo frames on one of the rings later. 3556 * This will not pass over-length frames into the default 3557 * queue because it's gated by the VMOLR.RLPML. 3558 */ 3559 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3560 } 3561 3562 wr32(E1000_RLPML, max_frame_size); 3563 } 3564 3565 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3566 int vfn, bool aupe) 3567 { 3568 struct e1000_hw *hw = &adapter->hw; 3569 u32 vmolr; 3570 3571 /* This register exists only on 82576 and newer so if we are older then 3572 * we should exit and do nothing 3573 */ 3574 if (hw->mac.type < e1000_82576) 3575 return; 3576 3577 vmolr = rd32(E1000_VMOLR(vfn)); 3578 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3579 if (hw->mac.type == e1000_i350) { 3580 u32 dvmolr; 3581 3582 dvmolr = rd32(E1000_DVMOLR(vfn)); 3583 dvmolr |= E1000_DVMOLR_STRVLAN; 3584 wr32(E1000_DVMOLR(vfn), dvmolr); 3585 } 3586 if (aupe) 3587 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3588 else 3589 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3590 3591 /* clear all bits that might not be set */ 3592 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3593 3594 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3595 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3596 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3597 * multicast packets 3598 */ 3599 if (vfn <= adapter->vfs_allocated_count) 3600 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3601 3602 wr32(E1000_VMOLR(vfn), vmolr); 3603 } 3604 3605 /** 3606 * igb_configure_rx_ring - Configure a receive ring after Reset 3607 * @adapter: board private structure 3608 * @ring: receive ring to be configured 3609 * 3610 * Configure the Rx unit of the MAC after a reset. 3611 **/ 3612 void igb_configure_rx_ring(struct igb_adapter *adapter, 3613 struct igb_ring *ring) 3614 { 3615 struct e1000_hw *hw = &adapter->hw; 3616 u64 rdba = ring->dma; 3617 int reg_idx = ring->reg_idx; 3618 u32 srrctl = 0, rxdctl = 0; 3619 3620 /* disable the queue */ 3621 wr32(E1000_RXDCTL(reg_idx), 0); 3622 3623 /* Set DMA base address registers */ 3624 wr32(E1000_RDBAL(reg_idx), 3625 rdba & 0x00000000ffffffffULL); 3626 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3627 wr32(E1000_RDLEN(reg_idx), 3628 ring->count * sizeof(union e1000_adv_rx_desc)); 3629 3630 /* initialize head and tail */ 3631 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3632 wr32(E1000_RDH(reg_idx), 0); 3633 writel(0, ring->tail); 3634 3635 /* set descriptor configuration */ 3636 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3637 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3638 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3639 if (hw->mac.type >= e1000_82580) 3640 srrctl |= E1000_SRRCTL_TIMESTAMP; 3641 /* Only set Drop Enable if we are supporting multiple queues */ 3642 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3643 srrctl |= E1000_SRRCTL_DROP_EN; 3644 3645 wr32(E1000_SRRCTL(reg_idx), srrctl); 3646 3647 /* set filtering for VMDQ pools */ 3648 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3649 3650 rxdctl |= IGB_RX_PTHRESH; 3651 rxdctl |= IGB_RX_HTHRESH << 8; 3652 rxdctl |= IGB_RX_WTHRESH << 16; 3653 3654 /* enable receive descriptor fetching */ 3655 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3656 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3657 } 3658 3659 /** 3660 * igb_configure_rx - Configure receive Unit after Reset 3661 * @adapter: board private structure 3662 * 3663 * Configure the Rx unit of the MAC after a reset. 3664 **/ 3665 static void igb_configure_rx(struct igb_adapter *adapter) 3666 { 3667 int i; 3668 3669 /* set UTA to appropriate mode */ 3670 igb_set_uta(adapter); 3671 3672 /* set the correct pool for the PF default MAC address in entry 0 */ 3673 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3674 adapter->vfs_allocated_count); 3675 3676 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3677 * the Base and Length of the Rx Descriptor Ring 3678 */ 3679 for (i = 0; i < adapter->num_rx_queues; i++) 3680 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3681 } 3682 3683 /** 3684 * igb_free_tx_resources - Free Tx Resources per Queue 3685 * @tx_ring: Tx descriptor ring for a specific queue 3686 * 3687 * Free all transmit software resources 3688 **/ 3689 void igb_free_tx_resources(struct igb_ring *tx_ring) 3690 { 3691 igb_clean_tx_ring(tx_ring); 3692 3693 vfree(tx_ring->tx_buffer_info); 3694 tx_ring->tx_buffer_info = NULL; 3695 3696 /* if not set, then don't free */ 3697 if (!tx_ring->desc) 3698 return; 3699 3700 dma_free_coherent(tx_ring->dev, tx_ring->size, 3701 tx_ring->desc, tx_ring->dma); 3702 3703 tx_ring->desc = NULL; 3704 } 3705 3706 /** 3707 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3708 * @adapter: board private structure 3709 * 3710 * Free all transmit software resources 3711 **/ 3712 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3713 { 3714 int i; 3715 3716 for (i = 0; i < adapter->num_tx_queues; i++) 3717 if (adapter->tx_ring[i]) 3718 igb_free_tx_resources(adapter->tx_ring[i]); 3719 } 3720 3721 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3722 struct igb_tx_buffer *tx_buffer) 3723 { 3724 if (tx_buffer->skb) { 3725 dev_kfree_skb_any(tx_buffer->skb); 3726 if (dma_unmap_len(tx_buffer, len)) 3727 dma_unmap_single(ring->dev, 3728 dma_unmap_addr(tx_buffer, dma), 3729 dma_unmap_len(tx_buffer, len), 3730 DMA_TO_DEVICE); 3731 } else if (dma_unmap_len(tx_buffer, len)) { 3732 dma_unmap_page(ring->dev, 3733 dma_unmap_addr(tx_buffer, dma), 3734 dma_unmap_len(tx_buffer, len), 3735 DMA_TO_DEVICE); 3736 } 3737 tx_buffer->next_to_watch = NULL; 3738 tx_buffer->skb = NULL; 3739 dma_unmap_len_set(tx_buffer, len, 0); 3740 /* buffer_info must be completely set up in the transmit path */ 3741 } 3742 3743 /** 3744 * igb_clean_tx_ring - Free Tx Buffers 3745 * @tx_ring: ring to be cleaned 3746 **/ 3747 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3748 { 3749 struct igb_tx_buffer *buffer_info; 3750 unsigned long size; 3751 u16 i; 3752 3753 if (!tx_ring->tx_buffer_info) 3754 return; 3755 /* Free all the Tx ring sk_buffs */ 3756 3757 for (i = 0; i < tx_ring->count; i++) { 3758 buffer_info = &tx_ring->tx_buffer_info[i]; 3759 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3760 } 3761 3762 netdev_tx_reset_queue(txring_txq(tx_ring)); 3763 3764 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3765 memset(tx_ring->tx_buffer_info, 0, size); 3766 3767 /* Zero out the descriptor ring */ 3768 memset(tx_ring->desc, 0, tx_ring->size); 3769 3770 tx_ring->next_to_use = 0; 3771 tx_ring->next_to_clean = 0; 3772 } 3773 3774 /** 3775 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3776 * @adapter: board private structure 3777 **/ 3778 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3779 { 3780 int i; 3781 3782 for (i = 0; i < adapter->num_tx_queues; i++) 3783 if (adapter->tx_ring[i]) 3784 igb_clean_tx_ring(adapter->tx_ring[i]); 3785 } 3786 3787 /** 3788 * igb_free_rx_resources - Free Rx Resources 3789 * @rx_ring: ring to clean the resources from 3790 * 3791 * Free all receive software resources 3792 **/ 3793 void igb_free_rx_resources(struct igb_ring *rx_ring) 3794 { 3795 igb_clean_rx_ring(rx_ring); 3796 3797 vfree(rx_ring->rx_buffer_info); 3798 rx_ring->rx_buffer_info = NULL; 3799 3800 /* if not set, then don't free */ 3801 if (!rx_ring->desc) 3802 return; 3803 3804 dma_free_coherent(rx_ring->dev, rx_ring->size, 3805 rx_ring->desc, rx_ring->dma); 3806 3807 rx_ring->desc = NULL; 3808 } 3809 3810 /** 3811 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3812 * @adapter: board private structure 3813 * 3814 * Free all receive software resources 3815 **/ 3816 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3817 { 3818 int i; 3819 3820 for (i = 0; i < adapter->num_rx_queues; i++) 3821 if (adapter->rx_ring[i]) 3822 igb_free_rx_resources(adapter->rx_ring[i]); 3823 } 3824 3825 /** 3826 * igb_clean_rx_ring - Free Rx Buffers per Queue 3827 * @rx_ring: ring to free buffers from 3828 **/ 3829 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3830 { 3831 unsigned long size; 3832 u16 i; 3833 3834 if (rx_ring->skb) 3835 dev_kfree_skb(rx_ring->skb); 3836 rx_ring->skb = NULL; 3837 3838 if (!rx_ring->rx_buffer_info) 3839 return; 3840 3841 /* Free all the Rx ring sk_buffs */ 3842 for (i = 0; i < rx_ring->count; i++) { 3843 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3844 3845 if (!buffer_info->page) 3846 continue; 3847 3848 dma_unmap_page(rx_ring->dev, 3849 buffer_info->dma, 3850 PAGE_SIZE, 3851 DMA_FROM_DEVICE); 3852 __free_page(buffer_info->page); 3853 3854 buffer_info->page = NULL; 3855 } 3856 3857 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3858 memset(rx_ring->rx_buffer_info, 0, size); 3859 3860 /* Zero out the descriptor ring */ 3861 memset(rx_ring->desc, 0, rx_ring->size); 3862 3863 rx_ring->next_to_alloc = 0; 3864 rx_ring->next_to_clean = 0; 3865 rx_ring->next_to_use = 0; 3866 } 3867 3868 /** 3869 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3870 * @adapter: board private structure 3871 **/ 3872 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3873 { 3874 int i; 3875 3876 for (i = 0; i < adapter->num_rx_queues; i++) 3877 if (adapter->rx_ring[i]) 3878 igb_clean_rx_ring(adapter->rx_ring[i]); 3879 } 3880 3881 /** 3882 * igb_set_mac - Change the Ethernet Address of the NIC 3883 * @netdev: network interface device structure 3884 * @p: pointer to an address structure 3885 * 3886 * Returns 0 on success, negative on failure 3887 **/ 3888 static int igb_set_mac(struct net_device *netdev, void *p) 3889 { 3890 struct igb_adapter *adapter = netdev_priv(netdev); 3891 struct e1000_hw *hw = &adapter->hw; 3892 struct sockaddr *addr = p; 3893 3894 if (!is_valid_ether_addr(addr->sa_data)) 3895 return -EADDRNOTAVAIL; 3896 3897 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3898 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3899 3900 /* set the correct pool for the new PF MAC address in entry 0 */ 3901 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3902 adapter->vfs_allocated_count); 3903 3904 return 0; 3905 } 3906 3907 /** 3908 * igb_write_mc_addr_list - write multicast addresses to MTA 3909 * @netdev: network interface device structure 3910 * 3911 * Writes multicast address list to the MTA hash table. 3912 * Returns: -ENOMEM on failure 3913 * 0 on no addresses written 3914 * X on writing X addresses to MTA 3915 **/ 3916 static int igb_write_mc_addr_list(struct net_device *netdev) 3917 { 3918 struct igb_adapter *adapter = netdev_priv(netdev); 3919 struct e1000_hw *hw = &adapter->hw; 3920 struct netdev_hw_addr *ha; 3921 u8 *mta_list; 3922 int i; 3923 3924 if (netdev_mc_empty(netdev)) { 3925 /* nothing to program, so clear mc list */ 3926 igb_update_mc_addr_list(hw, NULL, 0); 3927 igb_restore_vf_multicasts(adapter); 3928 return 0; 3929 } 3930 3931 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3932 if (!mta_list) 3933 return -ENOMEM; 3934 3935 /* The shared function expects a packed array of only addresses. */ 3936 i = 0; 3937 netdev_for_each_mc_addr(ha, netdev) 3938 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3939 3940 igb_update_mc_addr_list(hw, mta_list, i); 3941 kfree(mta_list); 3942 3943 return netdev_mc_count(netdev); 3944 } 3945 3946 /** 3947 * igb_write_uc_addr_list - write unicast addresses to RAR table 3948 * @netdev: network interface device structure 3949 * 3950 * Writes unicast address list to the RAR table. 3951 * Returns: -ENOMEM on failure/insufficient address space 3952 * 0 on no addresses written 3953 * X on writing X addresses to the RAR table 3954 **/ 3955 static int igb_write_uc_addr_list(struct net_device *netdev) 3956 { 3957 struct igb_adapter *adapter = netdev_priv(netdev); 3958 struct e1000_hw *hw = &adapter->hw; 3959 unsigned int vfn = adapter->vfs_allocated_count; 3960 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3961 int count = 0; 3962 3963 /* return ENOMEM indicating insufficient memory for addresses */ 3964 if (netdev_uc_count(netdev) > rar_entries) 3965 return -ENOMEM; 3966 3967 if (!netdev_uc_empty(netdev) && rar_entries) { 3968 struct netdev_hw_addr *ha; 3969 3970 netdev_for_each_uc_addr(ha, netdev) { 3971 if (!rar_entries) 3972 break; 3973 igb_rar_set_qsel(adapter, ha->addr, 3974 rar_entries--, 3975 vfn); 3976 count++; 3977 } 3978 } 3979 /* write the addresses in reverse order to avoid write combining */ 3980 for (; rar_entries > 0 ; rar_entries--) { 3981 wr32(E1000_RAH(rar_entries), 0); 3982 wr32(E1000_RAL(rar_entries), 0); 3983 } 3984 wrfl(); 3985 3986 return count; 3987 } 3988 3989 /** 3990 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3991 * @netdev: network interface device structure 3992 * 3993 * The set_rx_mode entry point is called whenever the unicast or multicast 3994 * address lists or the network interface flags are updated. This routine is 3995 * responsible for configuring the hardware for proper unicast, multicast, 3996 * promiscuous mode, and all-multi behavior. 3997 **/ 3998 static void igb_set_rx_mode(struct net_device *netdev) 3999 { 4000 struct igb_adapter *adapter = netdev_priv(netdev); 4001 struct e1000_hw *hw = &adapter->hw; 4002 unsigned int vfn = adapter->vfs_allocated_count; 4003 u32 rctl, vmolr = 0; 4004 int count; 4005 4006 /* Check for Promiscuous and All Multicast modes */ 4007 rctl = rd32(E1000_RCTL); 4008 4009 /* clear the effected bits */ 4010 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4011 4012 if (netdev->flags & IFF_PROMISC) { 4013 /* retain VLAN HW filtering if in VT mode */ 4014 if (adapter->vfs_allocated_count) 4015 rctl |= E1000_RCTL_VFE; 4016 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4017 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4018 } else { 4019 if (netdev->flags & IFF_ALLMULTI) { 4020 rctl |= E1000_RCTL_MPE; 4021 vmolr |= E1000_VMOLR_MPME; 4022 } else { 4023 /* Write addresses to the MTA, if the attempt fails 4024 * then we should just turn on promiscuous mode so 4025 * that we can at least receive multicast traffic 4026 */ 4027 count = igb_write_mc_addr_list(netdev); 4028 if (count < 0) { 4029 rctl |= E1000_RCTL_MPE; 4030 vmolr |= E1000_VMOLR_MPME; 4031 } else if (count) { 4032 vmolr |= E1000_VMOLR_ROMPE; 4033 } 4034 } 4035 /* Write addresses to available RAR registers, if there is not 4036 * sufficient space to store all the addresses then enable 4037 * unicast promiscuous mode 4038 */ 4039 count = igb_write_uc_addr_list(netdev); 4040 if (count < 0) { 4041 rctl |= E1000_RCTL_UPE; 4042 vmolr |= E1000_VMOLR_ROPE; 4043 } 4044 rctl |= E1000_RCTL_VFE; 4045 } 4046 wr32(E1000_RCTL, rctl); 4047 4048 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4049 * the VMOLR to enable the appropriate modes. Without this workaround 4050 * we will have issues with VLAN tag stripping not being done for frames 4051 * that are only arriving because we are the default pool 4052 */ 4053 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4054 return; 4055 4056 vmolr |= rd32(E1000_VMOLR(vfn)) & 4057 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4058 wr32(E1000_VMOLR(vfn), vmolr); 4059 igb_restore_vf_multicasts(adapter); 4060 } 4061 4062 static void igb_check_wvbr(struct igb_adapter *adapter) 4063 { 4064 struct e1000_hw *hw = &adapter->hw; 4065 u32 wvbr = 0; 4066 4067 switch (hw->mac.type) { 4068 case e1000_82576: 4069 case e1000_i350: 4070 wvbr = rd32(E1000_WVBR); 4071 if (!wvbr) 4072 return; 4073 break; 4074 default: 4075 break; 4076 } 4077 4078 adapter->wvbr |= wvbr; 4079 } 4080 4081 #define IGB_STAGGERED_QUEUE_OFFSET 8 4082 4083 static void igb_spoof_check(struct igb_adapter *adapter) 4084 { 4085 int j; 4086 4087 if (!adapter->wvbr) 4088 return; 4089 4090 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4091 if (adapter->wvbr & (1 << j) || 4092 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4093 dev_warn(&adapter->pdev->dev, 4094 "Spoof event(s) detected on VF %d\n", j); 4095 adapter->wvbr &= 4096 ~((1 << j) | 4097 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4098 } 4099 } 4100 } 4101 4102 /* Need to wait a few seconds after link up to get diagnostic information from 4103 * the phy 4104 */ 4105 static void igb_update_phy_info(unsigned long data) 4106 { 4107 struct igb_adapter *adapter = (struct igb_adapter *) data; 4108 igb_get_phy_info(&adapter->hw); 4109 } 4110 4111 /** 4112 * igb_has_link - check shared code for link and determine up/down 4113 * @adapter: pointer to driver private info 4114 **/ 4115 bool igb_has_link(struct igb_adapter *adapter) 4116 { 4117 struct e1000_hw *hw = &adapter->hw; 4118 bool link_active = false; 4119 4120 /* get_link_status is set on LSC (link status) interrupt or 4121 * rx sequence error interrupt. get_link_status will stay 4122 * false until the e1000_check_for_link establishes link 4123 * for copper adapters ONLY 4124 */ 4125 switch (hw->phy.media_type) { 4126 case e1000_media_type_copper: 4127 if (!hw->mac.get_link_status) 4128 return true; 4129 case e1000_media_type_internal_serdes: 4130 hw->mac.ops.check_for_link(hw); 4131 link_active = !hw->mac.get_link_status; 4132 break; 4133 default: 4134 case e1000_media_type_unknown: 4135 break; 4136 } 4137 4138 if (((hw->mac.type == e1000_i210) || 4139 (hw->mac.type == e1000_i211)) && 4140 (hw->phy.id == I210_I_PHY_ID)) { 4141 if (!netif_carrier_ok(adapter->netdev)) { 4142 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4143 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4144 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4145 adapter->link_check_timeout = jiffies; 4146 } 4147 } 4148 4149 return link_active; 4150 } 4151 4152 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4153 { 4154 bool ret = false; 4155 u32 ctrl_ext, thstat; 4156 4157 /* check for thermal sensor event on i350 copper only */ 4158 if (hw->mac.type == e1000_i350) { 4159 thstat = rd32(E1000_THSTAT); 4160 ctrl_ext = rd32(E1000_CTRL_EXT); 4161 4162 if ((hw->phy.media_type == e1000_media_type_copper) && 4163 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4164 ret = !!(thstat & event); 4165 } 4166 4167 return ret; 4168 } 4169 4170 /** 4171 * igb_check_lvmmc - check for malformed packets received 4172 * and indicated in LVMMC register 4173 * @adapter: pointer to adapter 4174 **/ 4175 static void igb_check_lvmmc(struct igb_adapter *adapter) 4176 { 4177 struct e1000_hw *hw = &adapter->hw; 4178 u32 lvmmc; 4179 4180 lvmmc = rd32(E1000_LVMMC); 4181 if (lvmmc) { 4182 if (unlikely(net_ratelimit())) { 4183 netdev_warn(adapter->netdev, 4184 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4185 lvmmc); 4186 } 4187 } 4188 } 4189 4190 /** 4191 * igb_watchdog - Timer Call-back 4192 * @data: pointer to adapter cast into an unsigned long 4193 **/ 4194 static void igb_watchdog(unsigned long data) 4195 { 4196 struct igb_adapter *adapter = (struct igb_adapter *)data; 4197 /* Do the rest outside of interrupt context */ 4198 schedule_work(&adapter->watchdog_task); 4199 } 4200 4201 static void igb_watchdog_task(struct work_struct *work) 4202 { 4203 struct igb_adapter *adapter = container_of(work, 4204 struct igb_adapter, 4205 watchdog_task); 4206 struct e1000_hw *hw = &adapter->hw; 4207 struct e1000_phy_info *phy = &hw->phy; 4208 struct net_device *netdev = adapter->netdev; 4209 u32 link; 4210 int i; 4211 u32 connsw; 4212 4213 link = igb_has_link(adapter); 4214 4215 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4216 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4217 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4218 else 4219 link = false; 4220 } 4221 4222 /* Force link down if we have fiber to swap to */ 4223 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4224 if (hw->phy.media_type == e1000_media_type_copper) { 4225 connsw = rd32(E1000_CONNSW); 4226 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4227 link = 0; 4228 } 4229 } 4230 if (link) { 4231 /* Perform a reset if the media type changed. */ 4232 if (hw->dev_spec._82575.media_changed) { 4233 hw->dev_spec._82575.media_changed = false; 4234 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4235 igb_reset(adapter); 4236 } 4237 /* Cancel scheduled suspend requests. */ 4238 pm_runtime_resume(netdev->dev.parent); 4239 4240 if (!netif_carrier_ok(netdev)) { 4241 u32 ctrl; 4242 4243 hw->mac.ops.get_speed_and_duplex(hw, 4244 &adapter->link_speed, 4245 &adapter->link_duplex); 4246 4247 ctrl = rd32(E1000_CTRL); 4248 /* Links status message must follow this format */ 4249 netdev_info(netdev, 4250 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4251 netdev->name, 4252 adapter->link_speed, 4253 adapter->link_duplex == FULL_DUPLEX ? 4254 "Full" : "Half", 4255 (ctrl & E1000_CTRL_TFCE) && 4256 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4257 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4258 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4259 4260 /* disable EEE if enabled */ 4261 if ((adapter->flags & IGB_FLAG_EEE) && 4262 (adapter->link_duplex == HALF_DUPLEX)) { 4263 dev_info(&adapter->pdev->dev, 4264 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4265 adapter->hw.dev_spec._82575.eee_disable = true; 4266 adapter->flags &= ~IGB_FLAG_EEE; 4267 } 4268 4269 /* check if SmartSpeed worked */ 4270 igb_check_downshift(hw); 4271 if (phy->speed_downgraded) 4272 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4273 4274 /* check for thermal sensor event */ 4275 if (igb_thermal_sensor_event(hw, 4276 E1000_THSTAT_LINK_THROTTLE)) 4277 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4278 4279 /* adjust timeout factor according to speed/duplex */ 4280 adapter->tx_timeout_factor = 1; 4281 switch (adapter->link_speed) { 4282 case SPEED_10: 4283 adapter->tx_timeout_factor = 14; 4284 break; 4285 case SPEED_100: 4286 /* maybe add some timeout factor ? */ 4287 break; 4288 } 4289 4290 netif_carrier_on(netdev); 4291 4292 igb_ping_all_vfs(adapter); 4293 igb_check_vf_rate_limit(adapter); 4294 4295 /* link state has changed, schedule phy info update */ 4296 if (!test_bit(__IGB_DOWN, &adapter->state)) 4297 mod_timer(&adapter->phy_info_timer, 4298 round_jiffies(jiffies + 2 * HZ)); 4299 } 4300 } else { 4301 if (netif_carrier_ok(netdev)) { 4302 adapter->link_speed = 0; 4303 adapter->link_duplex = 0; 4304 4305 /* check for thermal sensor event */ 4306 if (igb_thermal_sensor_event(hw, 4307 E1000_THSTAT_PWR_DOWN)) { 4308 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4309 } 4310 4311 /* Links status message must follow this format */ 4312 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4313 netdev->name); 4314 netif_carrier_off(netdev); 4315 4316 igb_ping_all_vfs(adapter); 4317 4318 /* link state has changed, schedule phy info update */ 4319 if (!test_bit(__IGB_DOWN, &adapter->state)) 4320 mod_timer(&adapter->phy_info_timer, 4321 round_jiffies(jiffies + 2 * HZ)); 4322 4323 /* link is down, time to check for alternate media */ 4324 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4325 igb_check_swap_media(adapter); 4326 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4327 schedule_work(&adapter->reset_task); 4328 /* return immediately */ 4329 return; 4330 } 4331 } 4332 pm_schedule_suspend(netdev->dev.parent, 4333 MSEC_PER_SEC * 5); 4334 4335 /* also check for alternate media here */ 4336 } else if (!netif_carrier_ok(netdev) && 4337 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4338 igb_check_swap_media(adapter); 4339 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4340 schedule_work(&adapter->reset_task); 4341 /* return immediately */ 4342 return; 4343 } 4344 } 4345 } 4346 4347 spin_lock(&adapter->stats64_lock); 4348 igb_update_stats(adapter, &adapter->stats64); 4349 spin_unlock(&adapter->stats64_lock); 4350 4351 for (i = 0; i < adapter->num_tx_queues; i++) { 4352 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4353 if (!netif_carrier_ok(netdev)) { 4354 /* We've lost link, so the controller stops DMA, 4355 * but we've got queued Tx work that's never going 4356 * to get done, so reset controller to flush Tx. 4357 * (Do the reset outside of interrupt context). 4358 */ 4359 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4360 adapter->tx_timeout_count++; 4361 schedule_work(&adapter->reset_task); 4362 /* return immediately since reset is imminent */ 4363 return; 4364 } 4365 } 4366 4367 /* Force detection of hung controller every watchdog period */ 4368 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4369 } 4370 4371 /* Cause software interrupt to ensure Rx ring is cleaned */ 4372 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4373 u32 eics = 0; 4374 4375 for (i = 0; i < adapter->num_q_vectors; i++) 4376 eics |= adapter->q_vector[i]->eims_value; 4377 wr32(E1000_EICS, eics); 4378 } else { 4379 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4380 } 4381 4382 igb_spoof_check(adapter); 4383 igb_ptp_rx_hang(adapter); 4384 4385 /* Check LVMMC register on i350/i354 only */ 4386 if ((adapter->hw.mac.type == e1000_i350) || 4387 (adapter->hw.mac.type == e1000_i354)) 4388 igb_check_lvmmc(adapter); 4389 4390 /* Reset the timer */ 4391 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4392 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4393 mod_timer(&adapter->watchdog_timer, 4394 round_jiffies(jiffies + HZ)); 4395 else 4396 mod_timer(&adapter->watchdog_timer, 4397 round_jiffies(jiffies + 2 * HZ)); 4398 } 4399 } 4400 4401 enum latency_range { 4402 lowest_latency = 0, 4403 low_latency = 1, 4404 bulk_latency = 2, 4405 latency_invalid = 255 4406 }; 4407 4408 /** 4409 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4410 * @q_vector: pointer to q_vector 4411 * 4412 * Stores a new ITR value based on strictly on packet size. This 4413 * algorithm is less sophisticated than that used in igb_update_itr, 4414 * due to the difficulty of synchronizing statistics across multiple 4415 * receive rings. The divisors and thresholds used by this function 4416 * were determined based on theoretical maximum wire speed and testing 4417 * data, in order to minimize response time while increasing bulk 4418 * throughput. 4419 * This functionality is controlled by ethtool's coalescing settings. 4420 * NOTE: This function is called only when operating in a multiqueue 4421 * receive environment. 4422 **/ 4423 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4424 { 4425 int new_val = q_vector->itr_val; 4426 int avg_wire_size = 0; 4427 struct igb_adapter *adapter = q_vector->adapter; 4428 unsigned int packets; 4429 4430 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4431 * ints/sec - ITR timer value of 120 ticks. 4432 */ 4433 if (adapter->link_speed != SPEED_1000) { 4434 new_val = IGB_4K_ITR; 4435 goto set_itr_val; 4436 } 4437 4438 packets = q_vector->rx.total_packets; 4439 if (packets) 4440 avg_wire_size = q_vector->rx.total_bytes / packets; 4441 4442 packets = q_vector->tx.total_packets; 4443 if (packets) 4444 avg_wire_size = max_t(u32, avg_wire_size, 4445 q_vector->tx.total_bytes / packets); 4446 4447 /* if avg_wire_size isn't set no work was done */ 4448 if (!avg_wire_size) 4449 goto clear_counts; 4450 4451 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4452 avg_wire_size += 24; 4453 4454 /* Don't starve jumbo frames */ 4455 avg_wire_size = min(avg_wire_size, 3000); 4456 4457 /* Give a little boost to mid-size frames */ 4458 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4459 new_val = avg_wire_size / 3; 4460 else 4461 new_val = avg_wire_size / 2; 4462 4463 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4464 if (new_val < IGB_20K_ITR && 4465 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4466 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4467 new_val = IGB_20K_ITR; 4468 4469 set_itr_val: 4470 if (new_val != q_vector->itr_val) { 4471 q_vector->itr_val = new_val; 4472 q_vector->set_itr = 1; 4473 } 4474 clear_counts: 4475 q_vector->rx.total_bytes = 0; 4476 q_vector->rx.total_packets = 0; 4477 q_vector->tx.total_bytes = 0; 4478 q_vector->tx.total_packets = 0; 4479 } 4480 4481 /** 4482 * igb_update_itr - update the dynamic ITR value based on statistics 4483 * @q_vector: pointer to q_vector 4484 * @ring_container: ring info to update the itr for 4485 * 4486 * Stores a new ITR value based on packets and byte 4487 * counts during the last interrupt. The advantage of per interrupt 4488 * computation is faster updates and more accurate ITR for the current 4489 * traffic pattern. Constants in this function were computed 4490 * based on theoretical maximum wire speed and thresholds were set based 4491 * on testing data as well as attempting to minimize response time 4492 * while increasing bulk throughput. 4493 * This functionality is controlled by ethtool's coalescing settings. 4494 * NOTE: These calculations are only valid when operating in a single- 4495 * queue environment. 4496 **/ 4497 static void igb_update_itr(struct igb_q_vector *q_vector, 4498 struct igb_ring_container *ring_container) 4499 { 4500 unsigned int packets = ring_container->total_packets; 4501 unsigned int bytes = ring_container->total_bytes; 4502 u8 itrval = ring_container->itr; 4503 4504 /* no packets, exit with status unchanged */ 4505 if (packets == 0) 4506 return; 4507 4508 switch (itrval) { 4509 case lowest_latency: 4510 /* handle TSO and jumbo frames */ 4511 if (bytes/packets > 8000) 4512 itrval = bulk_latency; 4513 else if ((packets < 5) && (bytes > 512)) 4514 itrval = low_latency; 4515 break; 4516 case low_latency: /* 50 usec aka 20000 ints/s */ 4517 if (bytes > 10000) { 4518 /* this if handles the TSO accounting */ 4519 if (bytes/packets > 8000) 4520 itrval = bulk_latency; 4521 else if ((packets < 10) || ((bytes/packets) > 1200)) 4522 itrval = bulk_latency; 4523 else if ((packets > 35)) 4524 itrval = lowest_latency; 4525 } else if (bytes/packets > 2000) { 4526 itrval = bulk_latency; 4527 } else if (packets <= 2 && bytes < 512) { 4528 itrval = lowest_latency; 4529 } 4530 break; 4531 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4532 if (bytes > 25000) { 4533 if (packets > 35) 4534 itrval = low_latency; 4535 } else if (bytes < 1500) { 4536 itrval = low_latency; 4537 } 4538 break; 4539 } 4540 4541 /* clear work counters since we have the values we need */ 4542 ring_container->total_bytes = 0; 4543 ring_container->total_packets = 0; 4544 4545 /* write updated itr to ring container */ 4546 ring_container->itr = itrval; 4547 } 4548 4549 static void igb_set_itr(struct igb_q_vector *q_vector) 4550 { 4551 struct igb_adapter *adapter = q_vector->adapter; 4552 u32 new_itr = q_vector->itr_val; 4553 u8 current_itr = 0; 4554 4555 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4556 if (adapter->link_speed != SPEED_1000) { 4557 current_itr = 0; 4558 new_itr = IGB_4K_ITR; 4559 goto set_itr_now; 4560 } 4561 4562 igb_update_itr(q_vector, &q_vector->tx); 4563 igb_update_itr(q_vector, &q_vector->rx); 4564 4565 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4566 4567 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4568 if (current_itr == lowest_latency && 4569 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4570 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4571 current_itr = low_latency; 4572 4573 switch (current_itr) { 4574 /* counts and packets in update_itr are dependent on these numbers */ 4575 case lowest_latency: 4576 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4577 break; 4578 case low_latency: 4579 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4580 break; 4581 case bulk_latency: 4582 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4583 break; 4584 default: 4585 break; 4586 } 4587 4588 set_itr_now: 4589 if (new_itr != q_vector->itr_val) { 4590 /* this attempts to bias the interrupt rate towards Bulk 4591 * by adding intermediate steps when interrupt rate is 4592 * increasing 4593 */ 4594 new_itr = new_itr > q_vector->itr_val ? 4595 max((new_itr * q_vector->itr_val) / 4596 (new_itr + (q_vector->itr_val >> 2)), 4597 new_itr) : new_itr; 4598 /* Don't write the value here; it resets the adapter's 4599 * internal timer, and causes us to delay far longer than 4600 * we should between interrupts. Instead, we write the ITR 4601 * value at the beginning of the next interrupt so the timing 4602 * ends up being correct. 4603 */ 4604 q_vector->itr_val = new_itr; 4605 q_vector->set_itr = 1; 4606 } 4607 } 4608 4609 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4610 u32 type_tucmd, u32 mss_l4len_idx) 4611 { 4612 struct e1000_adv_tx_context_desc *context_desc; 4613 u16 i = tx_ring->next_to_use; 4614 4615 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4616 4617 i++; 4618 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4619 4620 /* set bits to identify this as an advanced context descriptor */ 4621 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4622 4623 /* For 82575, context index must be unique per ring. */ 4624 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4625 mss_l4len_idx |= tx_ring->reg_idx << 4; 4626 4627 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4628 context_desc->seqnum_seed = 0; 4629 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4630 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4631 } 4632 4633 static int igb_tso(struct igb_ring *tx_ring, 4634 struct igb_tx_buffer *first, 4635 u8 *hdr_len) 4636 { 4637 struct sk_buff *skb = first->skb; 4638 u32 vlan_macip_lens, type_tucmd; 4639 u32 mss_l4len_idx, l4len; 4640 int err; 4641 4642 if (skb->ip_summed != CHECKSUM_PARTIAL) 4643 return 0; 4644 4645 if (!skb_is_gso(skb)) 4646 return 0; 4647 4648 err = skb_cow_head(skb, 0); 4649 if (err < 0) 4650 return err; 4651 4652 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4653 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4654 4655 if (first->protocol == htons(ETH_P_IP)) { 4656 struct iphdr *iph = ip_hdr(skb); 4657 iph->tot_len = 0; 4658 iph->check = 0; 4659 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4660 iph->daddr, 0, 4661 IPPROTO_TCP, 4662 0); 4663 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4664 first->tx_flags |= IGB_TX_FLAGS_TSO | 4665 IGB_TX_FLAGS_CSUM | 4666 IGB_TX_FLAGS_IPV4; 4667 } else if (skb_is_gso_v6(skb)) { 4668 ipv6_hdr(skb)->payload_len = 0; 4669 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4670 &ipv6_hdr(skb)->daddr, 4671 0, IPPROTO_TCP, 0); 4672 first->tx_flags |= IGB_TX_FLAGS_TSO | 4673 IGB_TX_FLAGS_CSUM; 4674 } 4675 4676 /* compute header lengths */ 4677 l4len = tcp_hdrlen(skb); 4678 *hdr_len = skb_transport_offset(skb) + l4len; 4679 4680 /* update gso size and bytecount with header size */ 4681 first->gso_segs = skb_shinfo(skb)->gso_segs; 4682 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4683 4684 /* MSS L4LEN IDX */ 4685 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4686 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4687 4688 /* VLAN MACLEN IPLEN */ 4689 vlan_macip_lens = skb_network_header_len(skb); 4690 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4691 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4692 4693 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4694 4695 return 1; 4696 } 4697 4698 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4699 { 4700 struct sk_buff *skb = first->skb; 4701 u32 vlan_macip_lens = 0; 4702 u32 mss_l4len_idx = 0; 4703 u32 type_tucmd = 0; 4704 4705 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4706 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4707 return; 4708 } else { 4709 u8 l4_hdr = 0; 4710 4711 switch (first->protocol) { 4712 case htons(ETH_P_IP): 4713 vlan_macip_lens |= skb_network_header_len(skb); 4714 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4715 l4_hdr = ip_hdr(skb)->protocol; 4716 break; 4717 case htons(ETH_P_IPV6): 4718 vlan_macip_lens |= skb_network_header_len(skb); 4719 l4_hdr = ipv6_hdr(skb)->nexthdr; 4720 break; 4721 default: 4722 if (unlikely(net_ratelimit())) { 4723 dev_warn(tx_ring->dev, 4724 "partial checksum but proto=%x!\n", 4725 first->protocol); 4726 } 4727 break; 4728 } 4729 4730 switch (l4_hdr) { 4731 case IPPROTO_TCP: 4732 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4733 mss_l4len_idx = tcp_hdrlen(skb) << 4734 E1000_ADVTXD_L4LEN_SHIFT; 4735 break; 4736 case IPPROTO_SCTP: 4737 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4738 mss_l4len_idx = sizeof(struct sctphdr) << 4739 E1000_ADVTXD_L4LEN_SHIFT; 4740 break; 4741 case IPPROTO_UDP: 4742 mss_l4len_idx = sizeof(struct udphdr) << 4743 E1000_ADVTXD_L4LEN_SHIFT; 4744 break; 4745 default: 4746 if (unlikely(net_ratelimit())) { 4747 dev_warn(tx_ring->dev, 4748 "partial checksum but l4 proto=%x!\n", 4749 l4_hdr); 4750 } 4751 break; 4752 } 4753 4754 /* update TX checksum flag */ 4755 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4756 } 4757 4758 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4759 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4760 4761 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4762 } 4763 4764 #define IGB_SET_FLAG(_input, _flag, _result) \ 4765 ((_flag <= _result) ? \ 4766 ((u32)(_input & _flag) * (_result / _flag)) : \ 4767 ((u32)(_input & _flag) / (_flag / _result))) 4768 4769 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4770 { 4771 /* set type for advanced descriptor with frame checksum insertion */ 4772 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4773 E1000_ADVTXD_DCMD_DEXT | 4774 E1000_ADVTXD_DCMD_IFCS; 4775 4776 /* set HW vlan bit if vlan is present */ 4777 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4778 (E1000_ADVTXD_DCMD_VLE)); 4779 4780 /* set segmentation bits for TSO */ 4781 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4782 (E1000_ADVTXD_DCMD_TSE)); 4783 4784 /* set timestamp bit if present */ 4785 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4786 (E1000_ADVTXD_MAC_TSTAMP)); 4787 4788 /* insert frame checksum */ 4789 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4790 4791 return cmd_type; 4792 } 4793 4794 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4795 union e1000_adv_tx_desc *tx_desc, 4796 u32 tx_flags, unsigned int paylen) 4797 { 4798 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4799 4800 /* 82575 requires a unique index per ring */ 4801 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4802 olinfo_status |= tx_ring->reg_idx << 4; 4803 4804 /* insert L4 checksum */ 4805 olinfo_status |= IGB_SET_FLAG(tx_flags, 4806 IGB_TX_FLAGS_CSUM, 4807 (E1000_TXD_POPTS_TXSM << 8)); 4808 4809 /* insert IPv4 checksum */ 4810 olinfo_status |= IGB_SET_FLAG(tx_flags, 4811 IGB_TX_FLAGS_IPV4, 4812 (E1000_TXD_POPTS_IXSM << 8)); 4813 4814 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4815 } 4816 4817 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4818 { 4819 struct net_device *netdev = tx_ring->netdev; 4820 4821 netif_stop_subqueue(netdev, tx_ring->queue_index); 4822 4823 /* Herbert's original patch had: 4824 * smp_mb__after_netif_stop_queue(); 4825 * but since that doesn't exist yet, just open code it. 4826 */ 4827 smp_mb(); 4828 4829 /* We need to check again in a case another CPU has just 4830 * made room available. 4831 */ 4832 if (igb_desc_unused(tx_ring) < size) 4833 return -EBUSY; 4834 4835 /* A reprieve! */ 4836 netif_wake_subqueue(netdev, tx_ring->queue_index); 4837 4838 u64_stats_update_begin(&tx_ring->tx_syncp2); 4839 tx_ring->tx_stats.restart_queue2++; 4840 u64_stats_update_end(&tx_ring->tx_syncp2); 4841 4842 return 0; 4843 } 4844 4845 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4846 { 4847 if (igb_desc_unused(tx_ring) >= size) 4848 return 0; 4849 return __igb_maybe_stop_tx(tx_ring, size); 4850 } 4851 4852 static void igb_tx_map(struct igb_ring *tx_ring, 4853 struct igb_tx_buffer *first, 4854 const u8 hdr_len) 4855 { 4856 struct sk_buff *skb = first->skb; 4857 struct igb_tx_buffer *tx_buffer; 4858 union e1000_adv_tx_desc *tx_desc; 4859 struct skb_frag_struct *frag; 4860 dma_addr_t dma; 4861 unsigned int data_len, size; 4862 u32 tx_flags = first->tx_flags; 4863 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4864 u16 i = tx_ring->next_to_use; 4865 4866 tx_desc = IGB_TX_DESC(tx_ring, i); 4867 4868 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4869 4870 size = skb_headlen(skb); 4871 data_len = skb->data_len; 4872 4873 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4874 4875 tx_buffer = first; 4876 4877 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4878 if (dma_mapping_error(tx_ring->dev, dma)) 4879 goto dma_error; 4880 4881 /* record length, and DMA address */ 4882 dma_unmap_len_set(tx_buffer, len, size); 4883 dma_unmap_addr_set(tx_buffer, dma, dma); 4884 4885 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4886 4887 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4888 tx_desc->read.cmd_type_len = 4889 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4890 4891 i++; 4892 tx_desc++; 4893 if (i == tx_ring->count) { 4894 tx_desc = IGB_TX_DESC(tx_ring, 0); 4895 i = 0; 4896 } 4897 tx_desc->read.olinfo_status = 0; 4898 4899 dma += IGB_MAX_DATA_PER_TXD; 4900 size -= IGB_MAX_DATA_PER_TXD; 4901 4902 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4903 } 4904 4905 if (likely(!data_len)) 4906 break; 4907 4908 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4909 4910 i++; 4911 tx_desc++; 4912 if (i == tx_ring->count) { 4913 tx_desc = IGB_TX_DESC(tx_ring, 0); 4914 i = 0; 4915 } 4916 tx_desc->read.olinfo_status = 0; 4917 4918 size = skb_frag_size(frag); 4919 data_len -= size; 4920 4921 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4922 size, DMA_TO_DEVICE); 4923 4924 tx_buffer = &tx_ring->tx_buffer_info[i]; 4925 } 4926 4927 /* write last descriptor with RS and EOP bits */ 4928 cmd_type |= size | IGB_TXD_DCMD; 4929 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4930 4931 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4932 4933 /* set the timestamp */ 4934 first->time_stamp = jiffies; 4935 4936 /* Force memory writes to complete before letting h/w know there 4937 * are new descriptors to fetch. (Only applicable for weak-ordered 4938 * memory model archs, such as IA-64). 4939 * 4940 * We also need this memory barrier to make certain all of the 4941 * status bits have been updated before next_to_watch is written. 4942 */ 4943 wmb(); 4944 4945 /* set next_to_watch value indicating a packet is present */ 4946 first->next_to_watch = tx_desc; 4947 4948 i++; 4949 if (i == tx_ring->count) 4950 i = 0; 4951 4952 tx_ring->next_to_use = i; 4953 4954 /* Make sure there is space in the ring for the next send. */ 4955 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4956 4957 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 4958 writel(i, tx_ring->tail); 4959 4960 /* we need this if more than one processor can write to our tail 4961 * at a time, it synchronizes IO on IA64/Altix systems 4962 */ 4963 mmiowb(); 4964 } 4965 return; 4966 4967 dma_error: 4968 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4969 4970 /* clear dma mappings for failed tx_buffer_info map */ 4971 for (;;) { 4972 tx_buffer = &tx_ring->tx_buffer_info[i]; 4973 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4974 if (tx_buffer == first) 4975 break; 4976 if (i == 0) 4977 i = tx_ring->count; 4978 i--; 4979 } 4980 4981 tx_ring->next_to_use = i; 4982 } 4983 4984 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4985 struct igb_ring *tx_ring) 4986 { 4987 struct igb_tx_buffer *first; 4988 int tso; 4989 u32 tx_flags = 0; 4990 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4991 __be16 protocol = vlan_get_protocol(skb); 4992 u8 hdr_len = 0; 4993 4994 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4995 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4996 * + 2 desc gap to keep tail from touching head, 4997 * + 1 desc for context descriptor, 4998 * otherwise try next time 4999 */ 5000 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 5001 unsigned short f; 5002 5003 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5004 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5005 } else { 5006 count += skb_shinfo(skb)->nr_frags; 5007 } 5008 5009 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5010 /* this is a hard error */ 5011 return NETDEV_TX_BUSY; 5012 } 5013 5014 /* record the location of the first descriptor for this packet */ 5015 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5016 first->skb = skb; 5017 first->bytecount = skb->len; 5018 first->gso_segs = 1; 5019 5020 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5021 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5022 5023 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5024 &adapter->state)) { 5025 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5026 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5027 5028 adapter->ptp_tx_skb = skb_get(skb); 5029 adapter->ptp_tx_start = jiffies; 5030 if (adapter->hw.mac.type == e1000_82576) 5031 schedule_work(&adapter->ptp_tx_work); 5032 } 5033 } 5034 5035 skb_tx_timestamp(skb); 5036 5037 if (skb_vlan_tag_present(skb)) { 5038 tx_flags |= IGB_TX_FLAGS_VLAN; 5039 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5040 } 5041 5042 /* record initial flags and protocol */ 5043 first->tx_flags = tx_flags; 5044 first->protocol = protocol; 5045 5046 tso = igb_tso(tx_ring, first, &hdr_len); 5047 if (tso < 0) 5048 goto out_drop; 5049 else if (!tso) 5050 igb_tx_csum(tx_ring, first); 5051 5052 igb_tx_map(tx_ring, first, hdr_len); 5053 5054 return NETDEV_TX_OK; 5055 5056 out_drop: 5057 igb_unmap_and_free_tx_resource(tx_ring, first); 5058 5059 return NETDEV_TX_OK; 5060 } 5061 5062 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5063 struct sk_buff *skb) 5064 { 5065 unsigned int r_idx = skb->queue_mapping; 5066 5067 if (r_idx >= adapter->num_tx_queues) 5068 r_idx = r_idx % adapter->num_tx_queues; 5069 5070 return adapter->tx_ring[r_idx]; 5071 } 5072 5073 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5074 struct net_device *netdev) 5075 { 5076 struct igb_adapter *adapter = netdev_priv(netdev); 5077 5078 if (test_bit(__IGB_DOWN, &adapter->state)) { 5079 dev_kfree_skb_any(skb); 5080 return NETDEV_TX_OK; 5081 } 5082 5083 if (skb->len <= 0) { 5084 dev_kfree_skb_any(skb); 5085 return NETDEV_TX_OK; 5086 } 5087 5088 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5089 * in order to meet this minimum size requirement. 5090 */ 5091 if (skb_put_padto(skb, 17)) 5092 return NETDEV_TX_OK; 5093 5094 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5095 } 5096 5097 /** 5098 * igb_tx_timeout - Respond to a Tx Hang 5099 * @netdev: network interface device structure 5100 **/ 5101 static void igb_tx_timeout(struct net_device *netdev) 5102 { 5103 struct igb_adapter *adapter = netdev_priv(netdev); 5104 struct e1000_hw *hw = &adapter->hw; 5105 5106 /* Do the reset outside of interrupt context */ 5107 adapter->tx_timeout_count++; 5108 5109 if (hw->mac.type >= e1000_82580) 5110 hw->dev_spec._82575.global_device_reset = true; 5111 5112 schedule_work(&adapter->reset_task); 5113 wr32(E1000_EICS, 5114 (adapter->eims_enable_mask & ~adapter->eims_other)); 5115 } 5116 5117 static void igb_reset_task(struct work_struct *work) 5118 { 5119 struct igb_adapter *adapter; 5120 adapter = container_of(work, struct igb_adapter, reset_task); 5121 5122 igb_dump(adapter); 5123 netdev_err(adapter->netdev, "Reset adapter\n"); 5124 igb_reinit_locked(adapter); 5125 } 5126 5127 /** 5128 * igb_get_stats64 - Get System Network Statistics 5129 * @netdev: network interface device structure 5130 * @stats: rtnl_link_stats64 pointer 5131 **/ 5132 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5133 struct rtnl_link_stats64 *stats) 5134 { 5135 struct igb_adapter *adapter = netdev_priv(netdev); 5136 5137 spin_lock(&adapter->stats64_lock); 5138 igb_update_stats(adapter, &adapter->stats64); 5139 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5140 spin_unlock(&adapter->stats64_lock); 5141 5142 return stats; 5143 } 5144 5145 /** 5146 * igb_change_mtu - Change the Maximum Transfer Unit 5147 * @netdev: network interface device structure 5148 * @new_mtu: new value for maximum frame size 5149 * 5150 * Returns 0 on success, negative on failure 5151 **/ 5152 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5153 { 5154 struct igb_adapter *adapter = netdev_priv(netdev); 5155 struct pci_dev *pdev = adapter->pdev; 5156 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5157 5158 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5159 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5160 return -EINVAL; 5161 } 5162 5163 #define MAX_STD_JUMBO_FRAME_SIZE 9238 5164 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5165 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5166 return -EINVAL; 5167 } 5168 5169 /* adjust max frame to be at least the size of a standard frame */ 5170 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5171 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5172 5173 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5174 usleep_range(1000, 2000); 5175 5176 /* igb_down has a dependency on max_frame_size */ 5177 adapter->max_frame_size = max_frame; 5178 5179 if (netif_running(netdev)) 5180 igb_down(adapter); 5181 5182 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5183 netdev->mtu, new_mtu); 5184 netdev->mtu = new_mtu; 5185 5186 if (netif_running(netdev)) 5187 igb_up(adapter); 5188 else 5189 igb_reset(adapter); 5190 5191 clear_bit(__IGB_RESETTING, &adapter->state); 5192 5193 return 0; 5194 } 5195 5196 /** 5197 * igb_update_stats - Update the board statistics counters 5198 * @adapter: board private structure 5199 **/ 5200 void igb_update_stats(struct igb_adapter *adapter, 5201 struct rtnl_link_stats64 *net_stats) 5202 { 5203 struct e1000_hw *hw = &adapter->hw; 5204 struct pci_dev *pdev = adapter->pdev; 5205 u32 reg, mpc; 5206 int i; 5207 u64 bytes, packets; 5208 unsigned int start; 5209 u64 _bytes, _packets; 5210 5211 /* Prevent stats update while adapter is being reset, or if the pci 5212 * connection is down. 5213 */ 5214 if (adapter->link_speed == 0) 5215 return; 5216 if (pci_channel_offline(pdev)) 5217 return; 5218 5219 bytes = 0; 5220 packets = 0; 5221 5222 rcu_read_lock(); 5223 for (i = 0; i < adapter->num_rx_queues; i++) { 5224 struct igb_ring *ring = adapter->rx_ring[i]; 5225 u32 rqdpc = rd32(E1000_RQDPC(i)); 5226 if (hw->mac.type >= e1000_i210) 5227 wr32(E1000_RQDPC(i), 0); 5228 5229 if (rqdpc) { 5230 ring->rx_stats.drops += rqdpc; 5231 net_stats->rx_fifo_errors += rqdpc; 5232 } 5233 5234 do { 5235 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5236 _bytes = ring->rx_stats.bytes; 5237 _packets = ring->rx_stats.packets; 5238 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5239 bytes += _bytes; 5240 packets += _packets; 5241 } 5242 5243 net_stats->rx_bytes = bytes; 5244 net_stats->rx_packets = packets; 5245 5246 bytes = 0; 5247 packets = 0; 5248 for (i = 0; i < adapter->num_tx_queues; i++) { 5249 struct igb_ring *ring = adapter->tx_ring[i]; 5250 do { 5251 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5252 _bytes = ring->tx_stats.bytes; 5253 _packets = ring->tx_stats.packets; 5254 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5255 bytes += _bytes; 5256 packets += _packets; 5257 } 5258 net_stats->tx_bytes = bytes; 5259 net_stats->tx_packets = packets; 5260 rcu_read_unlock(); 5261 5262 /* read stats registers */ 5263 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5264 adapter->stats.gprc += rd32(E1000_GPRC); 5265 adapter->stats.gorc += rd32(E1000_GORCL); 5266 rd32(E1000_GORCH); /* clear GORCL */ 5267 adapter->stats.bprc += rd32(E1000_BPRC); 5268 adapter->stats.mprc += rd32(E1000_MPRC); 5269 adapter->stats.roc += rd32(E1000_ROC); 5270 5271 adapter->stats.prc64 += rd32(E1000_PRC64); 5272 adapter->stats.prc127 += rd32(E1000_PRC127); 5273 adapter->stats.prc255 += rd32(E1000_PRC255); 5274 adapter->stats.prc511 += rd32(E1000_PRC511); 5275 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5276 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5277 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5278 adapter->stats.sec += rd32(E1000_SEC); 5279 5280 mpc = rd32(E1000_MPC); 5281 adapter->stats.mpc += mpc; 5282 net_stats->rx_fifo_errors += mpc; 5283 adapter->stats.scc += rd32(E1000_SCC); 5284 adapter->stats.ecol += rd32(E1000_ECOL); 5285 adapter->stats.mcc += rd32(E1000_MCC); 5286 adapter->stats.latecol += rd32(E1000_LATECOL); 5287 adapter->stats.dc += rd32(E1000_DC); 5288 adapter->stats.rlec += rd32(E1000_RLEC); 5289 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5290 adapter->stats.xontxc += rd32(E1000_XONTXC); 5291 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5292 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5293 adapter->stats.fcruc += rd32(E1000_FCRUC); 5294 adapter->stats.gptc += rd32(E1000_GPTC); 5295 adapter->stats.gotc += rd32(E1000_GOTCL); 5296 rd32(E1000_GOTCH); /* clear GOTCL */ 5297 adapter->stats.rnbc += rd32(E1000_RNBC); 5298 adapter->stats.ruc += rd32(E1000_RUC); 5299 adapter->stats.rfc += rd32(E1000_RFC); 5300 adapter->stats.rjc += rd32(E1000_RJC); 5301 adapter->stats.tor += rd32(E1000_TORH); 5302 adapter->stats.tot += rd32(E1000_TOTH); 5303 adapter->stats.tpr += rd32(E1000_TPR); 5304 5305 adapter->stats.ptc64 += rd32(E1000_PTC64); 5306 adapter->stats.ptc127 += rd32(E1000_PTC127); 5307 adapter->stats.ptc255 += rd32(E1000_PTC255); 5308 adapter->stats.ptc511 += rd32(E1000_PTC511); 5309 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5310 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5311 5312 adapter->stats.mptc += rd32(E1000_MPTC); 5313 adapter->stats.bptc += rd32(E1000_BPTC); 5314 5315 adapter->stats.tpt += rd32(E1000_TPT); 5316 adapter->stats.colc += rd32(E1000_COLC); 5317 5318 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5319 /* read internal phy specific stats */ 5320 reg = rd32(E1000_CTRL_EXT); 5321 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5322 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5323 5324 /* this stat has invalid values on i210/i211 */ 5325 if ((hw->mac.type != e1000_i210) && 5326 (hw->mac.type != e1000_i211)) 5327 adapter->stats.tncrs += rd32(E1000_TNCRS); 5328 } 5329 5330 adapter->stats.tsctc += rd32(E1000_TSCTC); 5331 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5332 5333 adapter->stats.iac += rd32(E1000_IAC); 5334 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5335 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5336 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5337 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5338 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5339 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5340 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5341 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5342 5343 /* Fill out the OS statistics structure */ 5344 net_stats->multicast = adapter->stats.mprc; 5345 net_stats->collisions = adapter->stats.colc; 5346 5347 /* Rx Errors */ 5348 5349 /* RLEC on some newer hardware can be incorrect so build 5350 * our own version based on RUC and ROC 5351 */ 5352 net_stats->rx_errors = adapter->stats.rxerrc + 5353 adapter->stats.crcerrs + adapter->stats.algnerrc + 5354 adapter->stats.ruc + adapter->stats.roc + 5355 adapter->stats.cexterr; 5356 net_stats->rx_length_errors = adapter->stats.ruc + 5357 adapter->stats.roc; 5358 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5359 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5360 net_stats->rx_missed_errors = adapter->stats.mpc; 5361 5362 /* Tx Errors */ 5363 net_stats->tx_errors = adapter->stats.ecol + 5364 adapter->stats.latecol; 5365 net_stats->tx_aborted_errors = adapter->stats.ecol; 5366 net_stats->tx_window_errors = adapter->stats.latecol; 5367 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5368 5369 /* Tx Dropped needs to be maintained elsewhere */ 5370 5371 /* Management Stats */ 5372 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5373 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5374 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5375 5376 /* OS2BMC Stats */ 5377 reg = rd32(E1000_MANC); 5378 if (reg & E1000_MANC_EN_BMC2OS) { 5379 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5380 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5381 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5382 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5383 } 5384 } 5385 5386 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5387 { 5388 struct e1000_hw *hw = &adapter->hw; 5389 struct ptp_clock_event event; 5390 struct timespec ts; 5391 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5392 5393 if (tsicr & TSINTR_SYS_WRAP) { 5394 event.type = PTP_CLOCK_PPS; 5395 if (adapter->ptp_caps.pps) 5396 ptp_clock_event(adapter->ptp_clock, &event); 5397 else 5398 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5399 ack |= TSINTR_SYS_WRAP; 5400 } 5401 5402 if (tsicr & E1000_TSICR_TXTS) { 5403 /* retrieve hardware timestamp */ 5404 schedule_work(&adapter->ptp_tx_work); 5405 ack |= E1000_TSICR_TXTS; 5406 } 5407 5408 if (tsicr & TSINTR_TT0) { 5409 spin_lock(&adapter->tmreg_lock); 5410 ts = timespec_add(adapter->perout[0].start, 5411 adapter->perout[0].period); 5412 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5413 wr32(E1000_TRGTTIMH0, ts.tv_sec); 5414 tsauxc = rd32(E1000_TSAUXC); 5415 tsauxc |= TSAUXC_EN_TT0; 5416 wr32(E1000_TSAUXC, tsauxc); 5417 adapter->perout[0].start = ts; 5418 spin_unlock(&adapter->tmreg_lock); 5419 ack |= TSINTR_TT0; 5420 } 5421 5422 if (tsicr & TSINTR_TT1) { 5423 spin_lock(&adapter->tmreg_lock); 5424 ts = timespec_add(adapter->perout[1].start, 5425 adapter->perout[1].period); 5426 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5427 wr32(E1000_TRGTTIMH1, ts.tv_sec); 5428 tsauxc = rd32(E1000_TSAUXC); 5429 tsauxc |= TSAUXC_EN_TT1; 5430 wr32(E1000_TSAUXC, tsauxc); 5431 adapter->perout[1].start = ts; 5432 spin_unlock(&adapter->tmreg_lock); 5433 ack |= TSINTR_TT1; 5434 } 5435 5436 if (tsicr & TSINTR_AUTT0) { 5437 nsec = rd32(E1000_AUXSTMPL0); 5438 sec = rd32(E1000_AUXSTMPH0); 5439 event.type = PTP_CLOCK_EXTTS; 5440 event.index = 0; 5441 event.timestamp = sec * 1000000000ULL + nsec; 5442 ptp_clock_event(adapter->ptp_clock, &event); 5443 ack |= TSINTR_AUTT0; 5444 } 5445 5446 if (tsicr & TSINTR_AUTT1) { 5447 nsec = rd32(E1000_AUXSTMPL1); 5448 sec = rd32(E1000_AUXSTMPH1); 5449 event.type = PTP_CLOCK_EXTTS; 5450 event.index = 1; 5451 event.timestamp = sec * 1000000000ULL + nsec; 5452 ptp_clock_event(adapter->ptp_clock, &event); 5453 ack |= TSINTR_AUTT1; 5454 } 5455 5456 /* acknowledge the interrupts */ 5457 wr32(E1000_TSICR, ack); 5458 } 5459 5460 static irqreturn_t igb_msix_other(int irq, void *data) 5461 { 5462 struct igb_adapter *adapter = data; 5463 struct e1000_hw *hw = &adapter->hw; 5464 u32 icr = rd32(E1000_ICR); 5465 /* reading ICR causes bit 31 of EICR to be cleared */ 5466 5467 if (icr & E1000_ICR_DRSTA) 5468 schedule_work(&adapter->reset_task); 5469 5470 if (icr & E1000_ICR_DOUTSYNC) { 5471 /* HW is reporting DMA is out of sync */ 5472 adapter->stats.doosync++; 5473 /* The DMA Out of Sync is also indication of a spoof event 5474 * in IOV mode. Check the Wrong VM Behavior register to 5475 * see if it is really a spoof event. 5476 */ 5477 igb_check_wvbr(adapter); 5478 } 5479 5480 /* Check for a mailbox event */ 5481 if (icr & E1000_ICR_VMMB) 5482 igb_msg_task(adapter); 5483 5484 if (icr & E1000_ICR_LSC) { 5485 hw->mac.get_link_status = 1; 5486 /* guard against interrupt when we're going down */ 5487 if (!test_bit(__IGB_DOWN, &adapter->state)) 5488 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5489 } 5490 5491 if (icr & E1000_ICR_TS) 5492 igb_tsync_interrupt(adapter); 5493 5494 wr32(E1000_EIMS, adapter->eims_other); 5495 5496 return IRQ_HANDLED; 5497 } 5498 5499 static void igb_write_itr(struct igb_q_vector *q_vector) 5500 { 5501 struct igb_adapter *adapter = q_vector->adapter; 5502 u32 itr_val = q_vector->itr_val & 0x7FFC; 5503 5504 if (!q_vector->set_itr) 5505 return; 5506 5507 if (!itr_val) 5508 itr_val = 0x4; 5509 5510 if (adapter->hw.mac.type == e1000_82575) 5511 itr_val |= itr_val << 16; 5512 else 5513 itr_val |= E1000_EITR_CNT_IGNR; 5514 5515 writel(itr_val, q_vector->itr_register); 5516 q_vector->set_itr = 0; 5517 } 5518 5519 static irqreturn_t igb_msix_ring(int irq, void *data) 5520 { 5521 struct igb_q_vector *q_vector = data; 5522 5523 /* Write the ITR value calculated from the previous interrupt. */ 5524 igb_write_itr(q_vector); 5525 5526 napi_schedule(&q_vector->napi); 5527 5528 return IRQ_HANDLED; 5529 } 5530 5531 #ifdef CONFIG_IGB_DCA 5532 static void igb_update_tx_dca(struct igb_adapter *adapter, 5533 struct igb_ring *tx_ring, 5534 int cpu) 5535 { 5536 struct e1000_hw *hw = &adapter->hw; 5537 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5538 5539 if (hw->mac.type != e1000_82575) 5540 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5541 5542 /* We can enable relaxed ordering for reads, but not writes when 5543 * DCA is enabled. This is due to a known issue in some chipsets 5544 * which will cause the DCA tag to be cleared. 5545 */ 5546 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5547 E1000_DCA_TXCTRL_DATA_RRO_EN | 5548 E1000_DCA_TXCTRL_DESC_DCA_EN; 5549 5550 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5551 } 5552 5553 static void igb_update_rx_dca(struct igb_adapter *adapter, 5554 struct igb_ring *rx_ring, 5555 int cpu) 5556 { 5557 struct e1000_hw *hw = &adapter->hw; 5558 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5559 5560 if (hw->mac.type != e1000_82575) 5561 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5562 5563 /* We can enable relaxed ordering for reads, but not writes when 5564 * DCA is enabled. This is due to a known issue in some chipsets 5565 * which will cause the DCA tag to be cleared. 5566 */ 5567 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5568 E1000_DCA_RXCTRL_DESC_DCA_EN; 5569 5570 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5571 } 5572 5573 static void igb_update_dca(struct igb_q_vector *q_vector) 5574 { 5575 struct igb_adapter *adapter = q_vector->adapter; 5576 int cpu = get_cpu(); 5577 5578 if (q_vector->cpu == cpu) 5579 goto out_no_update; 5580 5581 if (q_vector->tx.ring) 5582 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5583 5584 if (q_vector->rx.ring) 5585 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5586 5587 q_vector->cpu = cpu; 5588 out_no_update: 5589 put_cpu(); 5590 } 5591 5592 static void igb_setup_dca(struct igb_adapter *adapter) 5593 { 5594 struct e1000_hw *hw = &adapter->hw; 5595 int i; 5596 5597 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5598 return; 5599 5600 /* Always use CB2 mode, difference is masked in the CB driver. */ 5601 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5602 5603 for (i = 0; i < adapter->num_q_vectors; i++) { 5604 adapter->q_vector[i]->cpu = -1; 5605 igb_update_dca(adapter->q_vector[i]); 5606 } 5607 } 5608 5609 static int __igb_notify_dca(struct device *dev, void *data) 5610 { 5611 struct net_device *netdev = dev_get_drvdata(dev); 5612 struct igb_adapter *adapter = netdev_priv(netdev); 5613 struct pci_dev *pdev = adapter->pdev; 5614 struct e1000_hw *hw = &adapter->hw; 5615 unsigned long event = *(unsigned long *)data; 5616 5617 switch (event) { 5618 case DCA_PROVIDER_ADD: 5619 /* if already enabled, don't do it again */ 5620 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5621 break; 5622 if (dca_add_requester(dev) == 0) { 5623 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5624 dev_info(&pdev->dev, "DCA enabled\n"); 5625 igb_setup_dca(adapter); 5626 break; 5627 } 5628 /* Fall Through since DCA is disabled. */ 5629 case DCA_PROVIDER_REMOVE: 5630 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5631 /* without this a class_device is left 5632 * hanging around in the sysfs model 5633 */ 5634 dca_remove_requester(dev); 5635 dev_info(&pdev->dev, "DCA disabled\n"); 5636 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5637 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5638 } 5639 break; 5640 } 5641 5642 return 0; 5643 } 5644 5645 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5646 void *p) 5647 { 5648 int ret_val; 5649 5650 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5651 __igb_notify_dca); 5652 5653 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5654 } 5655 #endif /* CONFIG_IGB_DCA */ 5656 5657 #ifdef CONFIG_PCI_IOV 5658 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5659 { 5660 unsigned char mac_addr[ETH_ALEN]; 5661 5662 eth_zero_addr(mac_addr); 5663 igb_set_vf_mac(adapter, vf, mac_addr); 5664 5665 /* By default spoof check is enabled for all VFs */ 5666 adapter->vf_data[vf].spoofchk_enabled = true; 5667 5668 return 0; 5669 } 5670 5671 #endif 5672 static void igb_ping_all_vfs(struct igb_adapter *adapter) 5673 { 5674 struct e1000_hw *hw = &adapter->hw; 5675 u32 ping; 5676 int i; 5677 5678 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5679 ping = E1000_PF_CONTROL_MSG; 5680 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5681 ping |= E1000_VT_MSGTYPE_CTS; 5682 igb_write_mbx(hw, &ping, 1, i); 5683 } 5684 } 5685 5686 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5687 { 5688 struct e1000_hw *hw = &adapter->hw; 5689 u32 vmolr = rd32(E1000_VMOLR(vf)); 5690 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5691 5692 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5693 IGB_VF_FLAG_MULTI_PROMISC); 5694 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5695 5696 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5697 vmolr |= E1000_VMOLR_MPME; 5698 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5699 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5700 } else { 5701 /* if we have hashes and we are clearing a multicast promisc 5702 * flag we need to write the hashes to the MTA as this step 5703 * was previously skipped 5704 */ 5705 if (vf_data->num_vf_mc_hashes > 30) { 5706 vmolr |= E1000_VMOLR_MPME; 5707 } else if (vf_data->num_vf_mc_hashes) { 5708 int j; 5709 5710 vmolr |= E1000_VMOLR_ROMPE; 5711 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5712 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5713 } 5714 } 5715 5716 wr32(E1000_VMOLR(vf), vmolr); 5717 5718 /* there are flags left unprocessed, likely not supported */ 5719 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5720 return -EINVAL; 5721 5722 return 0; 5723 } 5724 5725 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5726 u32 *msgbuf, u32 vf) 5727 { 5728 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5729 u16 *hash_list = (u16 *)&msgbuf[1]; 5730 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5731 int i; 5732 5733 /* salt away the number of multicast addresses assigned 5734 * to this VF for later use to restore when the PF multi cast 5735 * list changes 5736 */ 5737 vf_data->num_vf_mc_hashes = n; 5738 5739 /* only up to 30 hash values supported */ 5740 if (n > 30) 5741 n = 30; 5742 5743 /* store the hashes for later use */ 5744 for (i = 0; i < n; i++) 5745 vf_data->vf_mc_hashes[i] = hash_list[i]; 5746 5747 /* Flush and reset the mta with the new values */ 5748 igb_set_rx_mode(adapter->netdev); 5749 5750 return 0; 5751 } 5752 5753 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5754 { 5755 struct e1000_hw *hw = &adapter->hw; 5756 struct vf_data_storage *vf_data; 5757 int i, j; 5758 5759 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5760 u32 vmolr = rd32(E1000_VMOLR(i)); 5761 5762 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5763 5764 vf_data = &adapter->vf_data[i]; 5765 5766 if ((vf_data->num_vf_mc_hashes > 30) || 5767 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5768 vmolr |= E1000_VMOLR_MPME; 5769 } else if (vf_data->num_vf_mc_hashes) { 5770 vmolr |= E1000_VMOLR_ROMPE; 5771 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5772 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5773 } 5774 wr32(E1000_VMOLR(i), vmolr); 5775 } 5776 } 5777 5778 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5779 { 5780 struct e1000_hw *hw = &adapter->hw; 5781 u32 pool_mask, reg, vid; 5782 int i; 5783 5784 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5785 5786 /* Find the vlan filter for this id */ 5787 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5788 reg = rd32(E1000_VLVF(i)); 5789 5790 /* remove the vf from the pool */ 5791 reg &= ~pool_mask; 5792 5793 /* if pool is empty then remove entry from vfta */ 5794 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5795 (reg & E1000_VLVF_VLANID_ENABLE)) { 5796 reg = 0; 5797 vid = reg & E1000_VLVF_VLANID_MASK; 5798 igb_vfta_set(hw, vid, false); 5799 } 5800 5801 wr32(E1000_VLVF(i), reg); 5802 } 5803 5804 adapter->vf_data[vf].vlans_enabled = 0; 5805 } 5806 5807 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5808 { 5809 struct e1000_hw *hw = &adapter->hw; 5810 u32 reg, i; 5811 5812 /* The vlvf table only exists on 82576 hardware and newer */ 5813 if (hw->mac.type < e1000_82576) 5814 return -1; 5815 5816 /* we only need to do this if VMDq is enabled */ 5817 if (!adapter->vfs_allocated_count) 5818 return -1; 5819 5820 /* Find the vlan filter for this id */ 5821 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5822 reg = rd32(E1000_VLVF(i)); 5823 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5824 vid == (reg & E1000_VLVF_VLANID_MASK)) 5825 break; 5826 } 5827 5828 if (add) { 5829 if (i == E1000_VLVF_ARRAY_SIZE) { 5830 /* Did not find a matching VLAN ID entry that was 5831 * enabled. Search for a free filter entry, i.e. 5832 * one without the enable bit set 5833 */ 5834 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5835 reg = rd32(E1000_VLVF(i)); 5836 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5837 break; 5838 } 5839 } 5840 if (i < E1000_VLVF_ARRAY_SIZE) { 5841 /* Found an enabled/available entry */ 5842 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5843 5844 /* if !enabled we need to set this up in vfta */ 5845 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5846 /* add VID to filter table */ 5847 igb_vfta_set(hw, vid, true); 5848 reg |= E1000_VLVF_VLANID_ENABLE; 5849 } 5850 reg &= ~E1000_VLVF_VLANID_MASK; 5851 reg |= vid; 5852 wr32(E1000_VLVF(i), reg); 5853 5854 /* do not modify RLPML for PF devices */ 5855 if (vf >= adapter->vfs_allocated_count) 5856 return 0; 5857 5858 if (!adapter->vf_data[vf].vlans_enabled) { 5859 u32 size; 5860 5861 reg = rd32(E1000_VMOLR(vf)); 5862 size = reg & E1000_VMOLR_RLPML_MASK; 5863 size += 4; 5864 reg &= ~E1000_VMOLR_RLPML_MASK; 5865 reg |= size; 5866 wr32(E1000_VMOLR(vf), reg); 5867 } 5868 5869 adapter->vf_data[vf].vlans_enabled++; 5870 } 5871 } else { 5872 if (i < E1000_VLVF_ARRAY_SIZE) { 5873 /* remove vf from the pool */ 5874 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5875 /* if pool is empty then remove entry from vfta */ 5876 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5877 reg = 0; 5878 igb_vfta_set(hw, vid, false); 5879 } 5880 wr32(E1000_VLVF(i), reg); 5881 5882 /* do not modify RLPML for PF devices */ 5883 if (vf >= adapter->vfs_allocated_count) 5884 return 0; 5885 5886 adapter->vf_data[vf].vlans_enabled--; 5887 if (!adapter->vf_data[vf].vlans_enabled) { 5888 u32 size; 5889 5890 reg = rd32(E1000_VMOLR(vf)); 5891 size = reg & E1000_VMOLR_RLPML_MASK; 5892 size -= 4; 5893 reg &= ~E1000_VMOLR_RLPML_MASK; 5894 reg |= size; 5895 wr32(E1000_VMOLR(vf), reg); 5896 } 5897 } 5898 } 5899 return 0; 5900 } 5901 5902 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5903 { 5904 struct e1000_hw *hw = &adapter->hw; 5905 5906 if (vid) 5907 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5908 else 5909 wr32(E1000_VMVIR(vf), 0); 5910 } 5911 5912 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5913 int vf, u16 vlan, u8 qos) 5914 { 5915 int err = 0; 5916 struct igb_adapter *adapter = netdev_priv(netdev); 5917 5918 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5919 return -EINVAL; 5920 if (vlan || qos) { 5921 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5922 if (err) 5923 goto out; 5924 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5925 igb_set_vmolr(adapter, vf, !vlan); 5926 adapter->vf_data[vf].pf_vlan = vlan; 5927 adapter->vf_data[vf].pf_qos = qos; 5928 dev_info(&adapter->pdev->dev, 5929 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5930 if (test_bit(__IGB_DOWN, &adapter->state)) { 5931 dev_warn(&adapter->pdev->dev, 5932 "The VF VLAN has been set, but the PF device is not up.\n"); 5933 dev_warn(&adapter->pdev->dev, 5934 "Bring the PF device up before attempting to use the VF device.\n"); 5935 } 5936 } else { 5937 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5938 false, vf); 5939 igb_set_vmvir(adapter, vlan, vf); 5940 igb_set_vmolr(adapter, vf, true); 5941 adapter->vf_data[vf].pf_vlan = 0; 5942 adapter->vf_data[vf].pf_qos = 0; 5943 } 5944 out: 5945 return err; 5946 } 5947 5948 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5949 { 5950 struct e1000_hw *hw = &adapter->hw; 5951 int i; 5952 u32 reg; 5953 5954 /* Find the vlan filter for this id */ 5955 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5956 reg = rd32(E1000_VLVF(i)); 5957 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5958 vid == (reg & E1000_VLVF_VLANID_MASK)) 5959 break; 5960 } 5961 5962 if (i >= E1000_VLVF_ARRAY_SIZE) 5963 i = -1; 5964 5965 return i; 5966 } 5967 5968 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5969 { 5970 struct e1000_hw *hw = &adapter->hw; 5971 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5972 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5973 int err = 0; 5974 5975 /* If in promiscuous mode we need to make sure the PF also has 5976 * the VLAN filter set. 5977 */ 5978 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5979 err = igb_vlvf_set(adapter, vid, add, 5980 adapter->vfs_allocated_count); 5981 if (err) 5982 goto out; 5983 5984 err = igb_vlvf_set(adapter, vid, add, vf); 5985 5986 if (err) 5987 goto out; 5988 5989 /* Go through all the checks to see if the VLAN filter should 5990 * be wiped completely. 5991 */ 5992 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5993 u32 vlvf, bits; 5994 int regndx = igb_find_vlvf_entry(adapter, vid); 5995 5996 if (regndx < 0) 5997 goto out; 5998 /* See if any other pools are set for this VLAN filter 5999 * entry other than the PF. 6000 */ 6001 vlvf = bits = rd32(E1000_VLVF(regndx)); 6002 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 6003 adapter->vfs_allocated_count); 6004 /* If the filter was removed then ensure PF pool bit 6005 * is cleared if the PF only added itself to the pool 6006 * because the PF is in promiscuous mode. 6007 */ 6008 if ((vlvf & VLAN_VID_MASK) == vid && 6009 !test_bit(vid, adapter->active_vlans) && 6010 !bits) 6011 igb_vlvf_set(adapter, vid, add, 6012 adapter->vfs_allocated_count); 6013 } 6014 6015 out: 6016 return err; 6017 } 6018 6019 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6020 { 6021 /* clear flags - except flag that indicates PF has set the MAC */ 6022 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 6023 adapter->vf_data[vf].last_nack = jiffies; 6024 6025 /* reset offloads to defaults */ 6026 igb_set_vmolr(adapter, vf, true); 6027 6028 /* reset vlans for device */ 6029 igb_clear_vf_vfta(adapter, vf); 6030 if (adapter->vf_data[vf].pf_vlan) 6031 igb_ndo_set_vf_vlan(adapter->netdev, vf, 6032 adapter->vf_data[vf].pf_vlan, 6033 adapter->vf_data[vf].pf_qos); 6034 else 6035 igb_clear_vf_vfta(adapter, vf); 6036 6037 /* reset multicast table array for vf */ 6038 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6039 6040 /* Flush and reset the mta with the new values */ 6041 igb_set_rx_mode(adapter->netdev); 6042 } 6043 6044 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6045 { 6046 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6047 6048 /* clear mac address as we were hotplug removed/added */ 6049 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6050 eth_zero_addr(vf_mac); 6051 6052 /* process remaining reset events */ 6053 igb_vf_reset(adapter, vf); 6054 } 6055 6056 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6057 { 6058 struct e1000_hw *hw = &adapter->hw; 6059 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6060 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6061 u32 reg, msgbuf[3]; 6062 u8 *addr = (u8 *)(&msgbuf[1]); 6063 6064 /* process all the same items cleared in a function level reset */ 6065 igb_vf_reset(adapter, vf); 6066 6067 /* set vf mac address */ 6068 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 6069 6070 /* enable transmit and receive for vf */ 6071 reg = rd32(E1000_VFTE); 6072 wr32(E1000_VFTE, reg | (1 << vf)); 6073 reg = rd32(E1000_VFRE); 6074 wr32(E1000_VFRE, reg | (1 << vf)); 6075 6076 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6077 6078 /* reply to reset with ack and vf mac address */ 6079 if (!is_zero_ether_addr(vf_mac)) { 6080 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6081 memcpy(addr, vf_mac, ETH_ALEN); 6082 } else { 6083 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6084 } 6085 igb_write_mbx(hw, msgbuf, 3, vf); 6086 } 6087 6088 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6089 { 6090 /* The VF MAC Address is stored in a packed array of bytes 6091 * starting at the second 32 bit word of the msg array 6092 */ 6093 unsigned char *addr = (char *)&msg[1]; 6094 int err = -1; 6095 6096 if (is_valid_ether_addr(addr)) 6097 err = igb_set_vf_mac(adapter, vf, addr); 6098 6099 return err; 6100 } 6101 6102 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6103 { 6104 struct e1000_hw *hw = &adapter->hw; 6105 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6106 u32 msg = E1000_VT_MSGTYPE_NACK; 6107 6108 /* if device isn't clear to send it shouldn't be reading either */ 6109 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6110 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6111 igb_write_mbx(hw, &msg, 1, vf); 6112 vf_data->last_nack = jiffies; 6113 } 6114 } 6115 6116 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6117 { 6118 struct pci_dev *pdev = adapter->pdev; 6119 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6120 struct e1000_hw *hw = &adapter->hw; 6121 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6122 s32 retval; 6123 6124 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6125 6126 if (retval) { 6127 /* if receive failed revoke VF CTS stats and restart init */ 6128 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6129 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6130 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6131 return; 6132 goto out; 6133 } 6134 6135 /* this is a message we already processed, do nothing */ 6136 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6137 return; 6138 6139 /* until the vf completes a reset it should not be 6140 * allowed to start any configuration. 6141 */ 6142 if (msgbuf[0] == E1000_VF_RESET) { 6143 igb_vf_reset_msg(adapter, vf); 6144 return; 6145 } 6146 6147 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6148 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6149 return; 6150 retval = -1; 6151 goto out; 6152 } 6153 6154 switch ((msgbuf[0] & 0xFFFF)) { 6155 case E1000_VF_SET_MAC_ADDR: 6156 retval = -EINVAL; 6157 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6158 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6159 else 6160 dev_warn(&pdev->dev, 6161 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6162 vf); 6163 break; 6164 case E1000_VF_SET_PROMISC: 6165 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6166 break; 6167 case E1000_VF_SET_MULTICAST: 6168 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6169 break; 6170 case E1000_VF_SET_LPE: 6171 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6172 break; 6173 case E1000_VF_SET_VLAN: 6174 retval = -1; 6175 if (vf_data->pf_vlan) 6176 dev_warn(&pdev->dev, 6177 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6178 vf); 6179 else 6180 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6181 break; 6182 default: 6183 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6184 retval = -1; 6185 break; 6186 } 6187 6188 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6189 out: 6190 /* notify the VF of the results of what it sent us */ 6191 if (retval) 6192 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6193 else 6194 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6195 6196 igb_write_mbx(hw, msgbuf, 1, vf); 6197 } 6198 6199 static void igb_msg_task(struct igb_adapter *adapter) 6200 { 6201 struct e1000_hw *hw = &adapter->hw; 6202 u32 vf; 6203 6204 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6205 /* process any reset requests */ 6206 if (!igb_check_for_rst(hw, vf)) 6207 igb_vf_reset_event(adapter, vf); 6208 6209 /* process any messages pending */ 6210 if (!igb_check_for_msg(hw, vf)) 6211 igb_rcv_msg_from_vf(adapter, vf); 6212 6213 /* process any acks */ 6214 if (!igb_check_for_ack(hw, vf)) 6215 igb_rcv_ack_from_vf(adapter, vf); 6216 } 6217 } 6218 6219 /** 6220 * igb_set_uta - Set unicast filter table address 6221 * @adapter: board private structure 6222 * 6223 * The unicast table address is a register array of 32-bit registers. 6224 * The table is meant to be used in a way similar to how the MTA is used 6225 * however due to certain limitations in the hardware it is necessary to 6226 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6227 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6228 **/ 6229 static void igb_set_uta(struct igb_adapter *adapter) 6230 { 6231 struct e1000_hw *hw = &adapter->hw; 6232 int i; 6233 6234 /* The UTA table only exists on 82576 hardware and newer */ 6235 if (hw->mac.type < e1000_82576) 6236 return; 6237 6238 /* we only need to do this if VMDq is enabled */ 6239 if (!adapter->vfs_allocated_count) 6240 return; 6241 6242 for (i = 0; i < hw->mac.uta_reg_count; i++) 6243 array_wr32(E1000_UTA, i, ~0); 6244 } 6245 6246 /** 6247 * igb_intr_msi - Interrupt Handler 6248 * @irq: interrupt number 6249 * @data: pointer to a network interface device structure 6250 **/ 6251 static irqreturn_t igb_intr_msi(int irq, void *data) 6252 { 6253 struct igb_adapter *adapter = data; 6254 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6255 struct e1000_hw *hw = &adapter->hw; 6256 /* read ICR disables interrupts using IAM */ 6257 u32 icr = rd32(E1000_ICR); 6258 6259 igb_write_itr(q_vector); 6260 6261 if (icr & E1000_ICR_DRSTA) 6262 schedule_work(&adapter->reset_task); 6263 6264 if (icr & E1000_ICR_DOUTSYNC) { 6265 /* HW is reporting DMA is out of sync */ 6266 adapter->stats.doosync++; 6267 } 6268 6269 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6270 hw->mac.get_link_status = 1; 6271 if (!test_bit(__IGB_DOWN, &adapter->state)) 6272 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6273 } 6274 6275 if (icr & E1000_ICR_TS) 6276 igb_tsync_interrupt(adapter); 6277 6278 napi_schedule(&q_vector->napi); 6279 6280 return IRQ_HANDLED; 6281 } 6282 6283 /** 6284 * igb_intr - Legacy Interrupt Handler 6285 * @irq: interrupt number 6286 * @data: pointer to a network interface device structure 6287 **/ 6288 static irqreturn_t igb_intr(int irq, void *data) 6289 { 6290 struct igb_adapter *adapter = data; 6291 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6292 struct e1000_hw *hw = &adapter->hw; 6293 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6294 * need for the IMC write 6295 */ 6296 u32 icr = rd32(E1000_ICR); 6297 6298 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6299 * not set, then the adapter didn't send an interrupt 6300 */ 6301 if (!(icr & E1000_ICR_INT_ASSERTED)) 6302 return IRQ_NONE; 6303 6304 igb_write_itr(q_vector); 6305 6306 if (icr & E1000_ICR_DRSTA) 6307 schedule_work(&adapter->reset_task); 6308 6309 if (icr & E1000_ICR_DOUTSYNC) { 6310 /* HW is reporting DMA is out of sync */ 6311 adapter->stats.doosync++; 6312 } 6313 6314 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6315 hw->mac.get_link_status = 1; 6316 /* guard against interrupt when we're going down */ 6317 if (!test_bit(__IGB_DOWN, &adapter->state)) 6318 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6319 } 6320 6321 if (icr & E1000_ICR_TS) 6322 igb_tsync_interrupt(adapter); 6323 6324 napi_schedule(&q_vector->napi); 6325 6326 return IRQ_HANDLED; 6327 } 6328 6329 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6330 { 6331 struct igb_adapter *adapter = q_vector->adapter; 6332 struct e1000_hw *hw = &adapter->hw; 6333 6334 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6335 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6336 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6337 igb_set_itr(q_vector); 6338 else 6339 igb_update_ring_itr(q_vector); 6340 } 6341 6342 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6343 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6344 wr32(E1000_EIMS, q_vector->eims_value); 6345 else 6346 igb_irq_enable(adapter); 6347 } 6348 } 6349 6350 /** 6351 * igb_poll - NAPI Rx polling callback 6352 * @napi: napi polling structure 6353 * @budget: count of how many packets we should handle 6354 **/ 6355 static int igb_poll(struct napi_struct *napi, int budget) 6356 { 6357 struct igb_q_vector *q_vector = container_of(napi, 6358 struct igb_q_vector, 6359 napi); 6360 bool clean_complete = true; 6361 6362 #ifdef CONFIG_IGB_DCA 6363 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6364 igb_update_dca(q_vector); 6365 #endif 6366 if (q_vector->tx.ring) 6367 clean_complete = igb_clean_tx_irq(q_vector); 6368 6369 if (q_vector->rx.ring) 6370 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6371 6372 /* If all work not completed, return budget and keep polling */ 6373 if (!clean_complete) 6374 return budget; 6375 6376 /* If not enough Rx work done, exit the polling mode */ 6377 napi_complete(napi); 6378 igb_ring_irq_enable(q_vector); 6379 6380 return 0; 6381 } 6382 6383 /** 6384 * igb_clean_tx_irq - Reclaim resources after transmit completes 6385 * @q_vector: pointer to q_vector containing needed info 6386 * 6387 * returns true if ring is completely cleaned 6388 **/ 6389 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6390 { 6391 struct igb_adapter *adapter = q_vector->adapter; 6392 struct igb_ring *tx_ring = q_vector->tx.ring; 6393 struct igb_tx_buffer *tx_buffer; 6394 union e1000_adv_tx_desc *tx_desc; 6395 unsigned int total_bytes = 0, total_packets = 0; 6396 unsigned int budget = q_vector->tx.work_limit; 6397 unsigned int i = tx_ring->next_to_clean; 6398 6399 if (test_bit(__IGB_DOWN, &adapter->state)) 6400 return true; 6401 6402 tx_buffer = &tx_ring->tx_buffer_info[i]; 6403 tx_desc = IGB_TX_DESC(tx_ring, i); 6404 i -= tx_ring->count; 6405 6406 do { 6407 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6408 6409 /* if next_to_watch is not set then there is no work pending */ 6410 if (!eop_desc) 6411 break; 6412 6413 /* prevent any other reads prior to eop_desc */ 6414 read_barrier_depends(); 6415 6416 /* if DD is not set pending work has not been completed */ 6417 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6418 break; 6419 6420 /* clear next_to_watch to prevent false hangs */ 6421 tx_buffer->next_to_watch = NULL; 6422 6423 /* update the statistics for this packet */ 6424 total_bytes += tx_buffer->bytecount; 6425 total_packets += tx_buffer->gso_segs; 6426 6427 /* free the skb */ 6428 dev_consume_skb_any(tx_buffer->skb); 6429 6430 /* unmap skb header data */ 6431 dma_unmap_single(tx_ring->dev, 6432 dma_unmap_addr(tx_buffer, dma), 6433 dma_unmap_len(tx_buffer, len), 6434 DMA_TO_DEVICE); 6435 6436 /* clear tx_buffer data */ 6437 tx_buffer->skb = NULL; 6438 dma_unmap_len_set(tx_buffer, len, 0); 6439 6440 /* clear last DMA location and unmap remaining buffers */ 6441 while (tx_desc != eop_desc) { 6442 tx_buffer++; 6443 tx_desc++; 6444 i++; 6445 if (unlikely(!i)) { 6446 i -= tx_ring->count; 6447 tx_buffer = tx_ring->tx_buffer_info; 6448 tx_desc = IGB_TX_DESC(tx_ring, 0); 6449 } 6450 6451 /* unmap any remaining paged data */ 6452 if (dma_unmap_len(tx_buffer, len)) { 6453 dma_unmap_page(tx_ring->dev, 6454 dma_unmap_addr(tx_buffer, dma), 6455 dma_unmap_len(tx_buffer, len), 6456 DMA_TO_DEVICE); 6457 dma_unmap_len_set(tx_buffer, len, 0); 6458 } 6459 } 6460 6461 /* move us one more past the eop_desc for start of next pkt */ 6462 tx_buffer++; 6463 tx_desc++; 6464 i++; 6465 if (unlikely(!i)) { 6466 i -= tx_ring->count; 6467 tx_buffer = tx_ring->tx_buffer_info; 6468 tx_desc = IGB_TX_DESC(tx_ring, 0); 6469 } 6470 6471 /* issue prefetch for next Tx descriptor */ 6472 prefetch(tx_desc); 6473 6474 /* update budget accounting */ 6475 budget--; 6476 } while (likely(budget)); 6477 6478 netdev_tx_completed_queue(txring_txq(tx_ring), 6479 total_packets, total_bytes); 6480 i += tx_ring->count; 6481 tx_ring->next_to_clean = i; 6482 u64_stats_update_begin(&tx_ring->tx_syncp); 6483 tx_ring->tx_stats.bytes += total_bytes; 6484 tx_ring->tx_stats.packets += total_packets; 6485 u64_stats_update_end(&tx_ring->tx_syncp); 6486 q_vector->tx.total_bytes += total_bytes; 6487 q_vector->tx.total_packets += total_packets; 6488 6489 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6490 struct e1000_hw *hw = &adapter->hw; 6491 6492 /* Detect a transmit hang in hardware, this serializes the 6493 * check with the clearing of time_stamp and movement of i 6494 */ 6495 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6496 if (tx_buffer->next_to_watch && 6497 time_after(jiffies, tx_buffer->time_stamp + 6498 (adapter->tx_timeout_factor * HZ)) && 6499 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6500 6501 /* detected Tx unit hang */ 6502 dev_err(tx_ring->dev, 6503 "Detected Tx Unit Hang\n" 6504 " Tx Queue <%d>\n" 6505 " TDH <%x>\n" 6506 " TDT <%x>\n" 6507 " next_to_use <%x>\n" 6508 " next_to_clean <%x>\n" 6509 "buffer_info[next_to_clean]\n" 6510 " time_stamp <%lx>\n" 6511 " next_to_watch <%p>\n" 6512 " jiffies <%lx>\n" 6513 " desc.status <%x>\n", 6514 tx_ring->queue_index, 6515 rd32(E1000_TDH(tx_ring->reg_idx)), 6516 readl(tx_ring->tail), 6517 tx_ring->next_to_use, 6518 tx_ring->next_to_clean, 6519 tx_buffer->time_stamp, 6520 tx_buffer->next_to_watch, 6521 jiffies, 6522 tx_buffer->next_to_watch->wb.status); 6523 netif_stop_subqueue(tx_ring->netdev, 6524 tx_ring->queue_index); 6525 6526 /* we are about to reset, no point in enabling stuff */ 6527 return true; 6528 } 6529 } 6530 6531 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6532 if (unlikely(total_packets && 6533 netif_carrier_ok(tx_ring->netdev) && 6534 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6535 /* Make sure that anybody stopping the queue after this 6536 * sees the new next_to_clean. 6537 */ 6538 smp_mb(); 6539 if (__netif_subqueue_stopped(tx_ring->netdev, 6540 tx_ring->queue_index) && 6541 !(test_bit(__IGB_DOWN, &adapter->state))) { 6542 netif_wake_subqueue(tx_ring->netdev, 6543 tx_ring->queue_index); 6544 6545 u64_stats_update_begin(&tx_ring->tx_syncp); 6546 tx_ring->tx_stats.restart_queue++; 6547 u64_stats_update_end(&tx_ring->tx_syncp); 6548 } 6549 } 6550 6551 return !!budget; 6552 } 6553 6554 /** 6555 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6556 * @rx_ring: rx descriptor ring to store buffers on 6557 * @old_buff: donor buffer to have page reused 6558 * 6559 * Synchronizes page for reuse by the adapter 6560 **/ 6561 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6562 struct igb_rx_buffer *old_buff) 6563 { 6564 struct igb_rx_buffer *new_buff; 6565 u16 nta = rx_ring->next_to_alloc; 6566 6567 new_buff = &rx_ring->rx_buffer_info[nta]; 6568 6569 /* update, and store next to alloc */ 6570 nta++; 6571 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6572 6573 /* transfer page from old buffer to new buffer */ 6574 *new_buff = *old_buff; 6575 6576 /* sync the buffer for use by the device */ 6577 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6578 old_buff->page_offset, 6579 IGB_RX_BUFSZ, 6580 DMA_FROM_DEVICE); 6581 } 6582 6583 static inline bool igb_page_is_reserved(struct page *page) 6584 { 6585 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 6586 } 6587 6588 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6589 struct page *page, 6590 unsigned int truesize) 6591 { 6592 /* avoid re-using remote pages */ 6593 if (unlikely(igb_page_is_reserved(page))) 6594 return false; 6595 6596 #if (PAGE_SIZE < 8192) 6597 /* if we are only owner of page we can reuse it */ 6598 if (unlikely(page_count(page) != 1)) 6599 return false; 6600 6601 /* flip page offset to other buffer */ 6602 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6603 #else 6604 /* move offset up to the next cache line */ 6605 rx_buffer->page_offset += truesize; 6606 6607 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6608 return false; 6609 #endif 6610 6611 /* Even if we own the page, we are not allowed to use atomic_set() 6612 * This would break get_page_unless_zero() users. 6613 */ 6614 atomic_inc(&page->_count); 6615 6616 return true; 6617 } 6618 6619 /** 6620 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6621 * @rx_ring: rx descriptor ring to transact packets on 6622 * @rx_buffer: buffer containing page to add 6623 * @rx_desc: descriptor containing length of buffer written by hardware 6624 * @skb: sk_buff to place the data into 6625 * 6626 * This function will add the data contained in rx_buffer->page to the skb. 6627 * This is done either through a direct copy if the data in the buffer is 6628 * less than the skb header size, otherwise it will just attach the page as 6629 * a frag to the skb. 6630 * 6631 * The function will then update the page offset if necessary and return 6632 * true if the buffer can be reused by the adapter. 6633 **/ 6634 static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6635 struct igb_rx_buffer *rx_buffer, 6636 union e1000_adv_rx_desc *rx_desc, 6637 struct sk_buff *skb) 6638 { 6639 struct page *page = rx_buffer->page; 6640 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6641 #if (PAGE_SIZE < 8192) 6642 unsigned int truesize = IGB_RX_BUFSZ; 6643 #else 6644 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6645 #endif 6646 6647 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6648 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6649 6650 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6651 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6652 va += IGB_TS_HDR_LEN; 6653 size -= IGB_TS_HDR_LEN; 6654 } 6655 6656 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6657 6658 /* page is not reserved, we can reuse buffer as-is */ 6659 if (likely(!igb_page_is_reserved(page))) 6660 return true; 6661 6662 /* this page cannot be reused so discard it */ 6663 __free_page(page); 6664 return false; 6665 } 6666 6667 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6668 rx_buffer->page_offset, size, truesize); 6669 6670 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6671 } 6672 6673 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6674 union e1000_adv_rx_desc *rx_desc, 6675 struct sk_buff *skb) 6676 { 6677 struct igb_rx_buffer *rx_buffer; 6678 struct page *page; 6679 6680 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6681 page = rx_buffer->page; 6682 prefetchw(page); 6683 6684 if (likely(!skb)) { 6685 void *page_addr = page_address(page) + 6686 rx_buffer->page_offset; 6687 6688 /* prefetch first cache line of first page */ 6689 prefetch(page_addr); 6690 #if L1_CACHE_BYTES < 128 6691 prefetch(page_addr + L1_CACHE_BYTES); 6692 #endif 6693 6694 /* allocate a skb to store the frags */ 6695 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 6696 if (unlikely(!skb)) { 6697 rx_ring->rx_stats.alloc_failed++; 6698 return NULL; 6699 } 6700 6701 /* we will be copying header into skb->data in 6702 * pskb_may_pull so it is in our interest to prefetch 6703 * it now to avoid a possible cache miss 6704 */ 6705 prefetchw(skb->data); 6706 } 6707 6708 /* we are reusing so sync this buffer for CPU use */ 6709 dma_sync_single_range_for_cpu(rx_ring->dev, 6710 rx_buffer->dma, 6711 rx_buffer->page_offset, 6712 IGB_RX_BUFSZ, 6713 DMA_FROM_DEVICE); 6714 6715 /* pull page into skb */ 6716 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6717 /* hand second half of page back to the ring */ 6718 igb_reuse_rx_page(rx_ring, rx_buffer); 6719 } else { 6720 /* we are not reusing the buffer so unmap it */ 6721 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6722 PAGE_SIZE, DMA_FROM_DEVICE); 6723 } 6724 6725 /* clear contents of rx_buffer */ 6726 rx_buffer->page = NULL; 6727 6728 return skb; 6729 } 6730 6731 static inline void igb_rx_checksum(struct igb_ring *ring, 6732 union e1000_adv_rx_desc *rx_desc, 6733 struct sk_buff *skb) 6734 { 6735 skb_checksum_none_assert(skb); 6736 6737 /* Ignore Checksum bit is set */ 6738 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6739 return; 6740 6741 /* Rx checksum disabled via ethtool */ 6742 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6743 return; 6744 6745 /* TCP/UDP checksum error bit is set */ 6746 if (igb_test_staterr(rx_desc, 6747 E1000_RXDEXT_STATERR_TCPE | 6748 E1000_RXDEXT_STATERR_IPE)) { 6749 /* work around errata with sctp packets where the TCPE aka 6750 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6751 * packets, (aka let the stack check the crc32c) 6752 */ 6753 if (!((skb->len == 60) && 6754 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6755 u64_stats_update_begin(&ring->rx_syncp); 6756 ring->rx_stats.csum_err++; 6757 u64_stats_update_end(&ring->rx_syncp); 6758 } 6759 /* let the stack verify checksum errors */ 6760 return; 6761 } 6762 /* It must be a TCP or UDP packet with a valid checksum */ 6763 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6764 E1000_RXD_STAT_UDPCS)) 6765 skb->ip_summed = CHECKSUM_UNNECESSARY; 6766 6767 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6768 le32_to_cpu(rx_desc->wb.upper.status_error)); 6769 } 6770 6771 static inline void igb_rx_hash(struct igb_ring *ring, 6772 union e1000_adv_rx_desc *rx_desc, 6773 struct sk_buff *skb) 6774 { 6775 if (ring->netdev->features & NETIF_F_RXHASH) 6776 skb_set_hash(skb, 6777 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6778 PKT_HASH_TYPE_L3); 6779 } 6780 6781 /** 6782 * igb_is_non_eop - process handling of non-EOP buffers 6783 * @rx_ring: Rx ring being processed 6784 * @rx_desc: Rx descriptor for current buffer 6785 * @skb: current socket buffer containing buffer in progress 6786 * 6787 * This function updates next to clean. If the buffer is an EOP buffer 6788 * this function exits returning false, otherwise it will place the 6789 * sk_buff in the next buffer to be chained and return true indicating 6790 * that this is in fact a non-EOP buffer. 6791 **/ 6792 static bool igb_is_non_eop(struct igb_ring *rx_ring, 6793 union e1000_adv_rx_desc *rx_desc) 6794 { 6795 u32 ntc = rx_ring->next_to_clean + 1; 6796 6797 /* fetch, update, and store next to clean */ 6798 ntc = (ntc < rx_ring->count) ? ntc : 0; 6799 rx_ring->next_to_clean = ntc; 6800 6801 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6802 6803 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6804 return false; 6805 6806 return true; 6807 } 6808 6809 /** 6810 * igb_pull_tail - igb specific version of skb_pull_tail 6811 * @rx_ring: rx descriptor ring packet is being transacted on 6812 * @rx_desc: pointer to the EOP Rx descriptor 6813 * @skb: pointer to current skb being adjusted 6814 * 6815 * This function is an igb specific version of __pskb_pull_tail. The 6816 * main difference between this version and the original function is that 6817 * this function can make several assumptions about the state of things 6818 * that allow for significant optimizations versus the standard function. 6819 * As a result we can do things like drop a frag and maintain an accurate 6820 * truesize for the skb. 6821 */ 6822 static void igb_pull_tail(struct igb_ring *rx_ring, 6823 union e1000_adv_rx_desc *rx_desc, 6824 struct sk_buff *skb) 6825 { 6826 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6827 unsigned char *va; 6828 unsigned int pull_len; 6829 6830 /* it is valid to use page_address instead of kmap since we are 6831 * working with pages allocated out of the lomem pool per 6832 * alloc_page(GFP_ATOMIC) 6833 */ 6834 va = skb_frag_address(frag); 6835 6836 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6837 /* retrieve timestamp from buffer */ 6838 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6839 6840 /* update pointers to remove timestamp header */ 6841 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6842 frag->page_offset += IGB_TS_HDR_LEN; 6843 skb->data_len -= IGB_TS_HDR_LEN; 6844 skb->len -= IGB_TS_HDR_LEN; 6845 6846 /* move va to start of packet data */ 6847 va += IGB_TS_HDR_LEN; 6848 } 6849 6850 /* we need the header to contain the greater of either ETH_HLEN or 6851 * 60 bytes if the skb->len is less than 60 for skb_pad. 6852 */ 6853 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); 6854 6855 /* align pull length to size of long to optimize memcpy performance */ 6856 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6857 6858 /* update all of the pointers */ 6859 skb_frag_size_sub(frag, pull_len); 6860 frag->page_offset += pull_len; 6861 skb->data_len -= pull_len; 6862 skb->tail += pull_len; 6863 } 6864 6865 /** 6866 * igb_cleanup_headers - Correct corrupted or empty headers 6867 * @rx_ring: rx descriptor ring packet is being transacted on 6868 * @rx_desc: pointer to the EOP Rx descriptor 6869 * @skb: pointer to current skb being fixed 6870 * 6871 * Address the case where we are pulling data in on pages only 6872 * and as such no data is present in the skb header. 6873 * 6874 * In addition if skb is not at least 60 bytes we need to pad it so that 6875 * it is large enough to qualify as a valid Ethernet frame. 6876 * 6877 * Returns true if an error was encountered and skb was freed. 6878 **/ 6879 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6880 union e1000_adv_rx_desc *rx_desc, 6881 struct sk_buff *skb) 6882 { 6883 if (unlikely((igb_test_staterr(rx_desc, 6884 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6885 struct net_device *netdev = rx_ring->netdev; 6886 if (!(netdev->features & NETIF_F_RXALL)) { 6887 dev_kfree_skb_any(skb); 6888 return true; 6889 } 6890 } 6891 6892 /* place header in linear portion of buffer */ 6893 if (skb_is_nonlinear(skb)) 6894 igb_pull_tail(rx_ring, rx_desc, skb); 6895 6896 /* if eth_skb_pad returns an error the skb was freed */ 6897 if (eth_skb_pad(skb)) 6898 return true; 6899 6900 return false; 6901 } 6902 6903 /** 6904 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6905 * @rx_ring: rx descriptor ring packet is being transacted on 6906 * @rx_desc: pointer to the EOP Rx descriptor 6907 * @skb: pointer to current skb being populated 6908 * 6909 * This function checks the ring, descriptor, and packet information in 6910 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6911 * other fields within the skb. 6912 **/ 6913 static void igb_process_skb_fields(struct igb_ring *rx_ring, 6914 union e1000_adv_rx_desc *rx_desc, 6915 struct sk_buff *skb) 6916 { 6917 struct net_device *dev = rx_ring->netdev; 6918 6919 igb_rx_hash(rx_ring, rx_desc, skb); 6920 6921 igb_rx_checksum(rx_ring, rx_desc, skb); 6922 6923 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6924 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6925 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6926 6927 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6928 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6929 u16 vid; 6930 6931 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6932 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6933 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6934 else 6935 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6936 6937 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6938 } 6939 6940 skb_record_rx_queue(skb, rx_ring->queue_index); 6941 6942 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6943 } 6944 6945 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6946 { 6947 struct igb_ring *rx_ring = q_vector->rx.ring; 6948 struct sk_buff *skb = rx_ring->skb; 6949 unsigned int total_bytes = 0, total_packets = 0; 6950 u16 cleaned_count = igb_desc_unused(rx_ring); 6951 6952 while (likely(total_packets < budget)) { 6953 union e1000_adv_rx_desc *rx_desc; 6954 6955 /* return some buffers to hardware, one at a time is too slow */ 6956 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6957 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6958 cleaned_count = 0; 6959 } 6960 6961 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6962 6963 if (!rx_desc->wb.upper.status_error) 6964 break; 6965 6966 /* This memory barrier is needed to keep us from reading 6967 * any other fields out of the rx_desc until we know the 6968 * descriptor has been written back 6969 */ 6970 dma_rmb(); 6971 6972 /* retrieve a buffer from the ring */ 6973 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6974 6975 /* exit if we failed to retrieve a buffer */ 6976 if (!skb) 6977 break; 6978 6979 cleaned_count++; 6980 6981 /* fetch next buffer in frame if non-eop */ 6982 if (igb_is_non_eop(rx_ring, rx_desc)) 6983 continue; 6984 6985 /* verify the packet layout is correct */ 6986 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6987 skb = NULL; 6988 continue; 6989 } 6990 6991 /* probably a little skewed due to removing CRC */ 6992 total_bytes += skb->len; 6993 6994 /* populate checksum, timestamp, VLAN, and protocol */ 6995 igb_process_skb_fields(rx_ring, rx_desc, skb); 6996 6997 napi_gro_receive(&q_vector->napi, skb); 6998 6999 /* reset skb pointer */ 7000 skb = NULL; 7001 7002 /* update budget accounting */ 7003 total_packets++; 7004 } 7005 7006 /* place incomplete frames back on ring for completion */ 7007 rx_ring->skb = skb; 7008 7009 u64_stats_update_begin(&rx_ring->rx_syncp); 7010 rx_ring->rx_stats.packets += total_packets; 7011 rx_ring->rx_stats.bytes += total_bytes; 7012 u64_stats_update_end(&rx_ring->rx_syncp); 7013 q_vector->rx.total_packets += total_packets; 7014 q_vector->rx.total_bytes += total_bytes; 7015 7016 if (cleaned_count) 7017 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7018 7019 return total_packets < budget; 7020 } 7021 7022 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7023 struct igb_rx_buffer *bi) 7024 { 7025 struct page *page = bi->page; 7026 dma_addr_t dma; 7027 7028 /* since we are recycling buffers we should seldom need to alloc */ 7029 if (likely(page)) 7030 return true; 7031 7032 /* alloc new page for storage */ 7033 page = dev_alloc_page(); 7034 if (unlikely(!page)) { 7035 rx_ring->rx_stats.alloc_failed++; 7036 return false; 7037 } 7038 7039 /* map page for use */ 7040 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7041 7042 /* if mapping failed free memory back to system since 7043 * there isn't much point in holding memory we can't use 7044 */ 7045 if (dma_mapping_error(rx_ring->dev, dma)) { 7046 __free_page(page); 7047 7048 rx_ring->rx_stats.alloc_failed++; 7049 return false; 7050 } 7051 7052 bi->dma = dma; 7053 bi->page = page; 7054 bi->page_offset = 0; 7055 7056 return true; 7057 } 7058 7059 /** 7060 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7061 * @adapter: address of board private structure 7062 **/ 7063 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7064 { 7065 union e1000_adv_rx_desc *rx_desc; 7066 struct igb_rx_buffer *bi; 7067 u16 i = rx_ring->next_to_use; 7068 7069 /* nothing to do */ 7070 if (!cleaned_count) 7071 return; 7072 7073 rx_desc = IGB_RX_DESC(rx_ring, i); 7074 bi = &rx_ring->rx_buffer_info[i]; 7075 i -= rx_ring->count; 7076 7077 do { 7078 if (!igb_alloc_mapped_page(rx_ring, bi)) 7079 break; 7080 7081 /* Refresh the desc even if buffer_addrs didn't change 7082 * because each write-back erases this info. 7083 */ 7084 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7085 7086 rx_desc++; 7087 bi++; 7088 i++; 7089 if (unlikely(!i)) { 7090 rx_desc = IGB_RX_DESC(rx_ring, 0); 7091 bi = rx_ring->rx_buffer_info; 7092 i -= rx_ring->count; 7093 } 7094 7095 /* clear the status bits for the next_to_use descriptor */ 7096 rx_desc->wb.upper.status_error = 0; 7097 7098 cleaned_count--; 7099 } while (cleaned_count); 7100 7101 i += rx_ring->count; 7102 7103 if (rx_ring->next_to_use != i) { 7104 /* record the next descriptor to use */ 7105 rx_ring->next_to_use = i; 7106 7107 /* update next to alloc since we have filled the ring */ 7108 rx_ring->next_to_alloc = i; 7109 7110 /* Force memory writes to complete before letting h/w 7111 * know there are new descriptors to fetch. (Only 7112 * applicable for weak-ordered memory model archs, 7113 * such as IA-64). 7114 */ 7115 wmb(); 7116 writel(i, rx_ring->tail); 7117 } 7118 } 7119 7120 /** 7121 * igb_mii_ioctl - 7122 * @netdev: 7123 * @ifreq: 7124 * @cmd: 7125 **/ 7126 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7127 { 7128 struct igb_adapter *adapter = netdev_priv(netdev); 7129 struct mii_ioctl_data *data = if_mii(ifr); 7130 7131 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7132 return -EOPNOTSUPP; 7133 7134 switch (cmd) { 7135 case SIOCGMIIPHY: 7136 data->phy_id = adapter->hw.phy.addr; 7137 break; 7138 case SIOCGMIIREG: 7139 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7140 &data->val_out)) 7141 return -EIO; 7142 break; 7143 case SIOCSMIIREG: 7144 default: 7145 return -EOPNOTSUPP; 7146 } 7147 return 0; 7148 } 7149 7150 /** 7151 * igb_ioctl - 7152 * @netdev: 7153 * @ifreq: 7154 * @cmd: 7155 **/ 7156 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7157 { 7158 switch (cmd) { 7159 case SIOCGMIIPHY: 7160 case SIOCGMIIREG: 7161 case SIOCSMIIREG: 7162 return igb_mii_ioctl(netdev, ifr, cmd); 7163 case SIOCGHWTSTAMP: 7164 return igb_ptp_get_ts_config(netdev, ifr); 7165 case SIOCSHWTSTAMP: 7166 return igb_ptp_set_ts_config(netdev, ifr); 7167 default: 7168 return -EOPNOTSUPP; 7169 } 7170 } 7171 7172 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7173 { 7174 struct igb_adapter *adapter = hw->back; 7175 7176 pci_read_config_word(adapter->pdev, reg, value); 7177 } 7178 7179 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7180 { 7181 struct igb_adapter *adapter = hw->back; 7182 7183 pci_write_config_word(adapter->pdev, reg, *value); 7184 } 7185 7186 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7187 { 7188 struct igb_adapter *adapter = hw->back; 7189 7190 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7191 return -E1000_ERR_CONFIG; 7192 7193 return 0; 7194 } 7195 7196 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7197 { 7198 struct igb_adapter *adapter = hw->back; 7199 7200 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7201 return -E1000_ERR_CONFIG; 7202 7203 return 0; 7204 } 7205 7206 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7207 { 7208 struct igb_adapter *adapter = netdev_priv(netdev); 7209 struct e1000_hw *hw = &adapter->hw; 7210 u32 ctrl, rctl; 7211 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7212 7213 if (enable) { 7214 /* enable VLAN tag insert/strip */ 7215 ctrl = rd32(E1000_CTRL); 7216 ctrl |= E1000_CTRL_VME; 7217 wr32(E1000_CTRL, ctrl); 7218 7219 /* Disable CFI check */ 7220 rctl = rd32(E1000_RCTL); 7221 rctl &= ~E1000_RCTL_CFIEN; 7222 wr32(E1000_RCTL, rctl); 7223 } else { 7224 /* disable VLAN tag insert/strip */ 7225 ctrl = rd32(E1000_CTRL); 7226 ctrl &= ~E1000_CTRL_VME; 7227 wr32(E1000_CTRL, ctrl); 7228 } 7229 7230 igb_rlpml_set(adapter); 7231 } 7232 7233 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7234 __be16 proto, u16 vid) 7235 { 7236 struct igb_adapter *adapter = netdev_priv(netdev); 7237 struct e1000_hw *hw = &adapter->hw; 7238 int pf_id = adapter->vfs_allocated_count; 7239 7240 /* attempt to add filter to vlvf array */ 7241 igb_vlvf_set(adapter, vid, true, pf_id); 7242 7243 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7244 igb_vfta_set(hw, vid, true); 7245 7246 set_bit(vid, adapter->active_vlans); 7247 7248 return 0; 7249 } 7250 7251 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7252 __be16 proto, u16 vid) 7253 { 7254 struct igb_adapter *adapter = netdev_priv(netdev); 7255 struct e1000_hw *hw = &adapter->hw; 7256 int pf_id = adapter->vfs_allocated_count; 7257 s32 err; 7258 7259 /* remove vlan from VLVF table array */ 7260 err = igb_vlvf_set(adapter, vid, false, pf_id); 7261 7262 /* if vid was not present in VLVF just remove it from table */ 7263 if (err) 7264 igb_vfta_set(hw, vid, false); 7265 7266 clear_bit(vid, adapter->active_vlans); 7267 7268 return 0; 7269 } 7270 7271 static void igb_restore_vlan(struct igb_adapter *adapter) 7272 { 7273 u16 vid; 7274 7275 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7276 7277 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7278 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7279 } 7280 7281 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7282 { 7283 struct pci_dev *pdev = adapter->pdev; 7284 struct e1000_mac_info *mac = &adapter->hw.mac; 7285 7286 mac->autoneg = 0; 7287 7288 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7289 * for the switch() below to work 7290 */ 7291 if ((spd & 1) || (dplx & ~1)) 7292 goto err_inval; 7293 7294 /* Fiber NIC's only allow 1000 gbps Full duplex 7295 * and 100Mbps Full duplex for 100baseFx sfp 7296 */ 7297 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7298 switch (spd + dplx) { 7299 case SPEED_10 + DUPLEX_HALF: 7300 case SPEED_10 + DUPLEX_FULL: 7301 case SPEED_100 + DUPLEX_HALF: 7302 goto err_inval; 7303 default: 7304 break; 7305 } 7306 } 7307 7308 switch (spd + dplx) { 7309 case SPEED_10 + DUPLEX_HALF: 7310 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7311 break; 7312 case SPEED_10 + DUPLEX_FULL: 7313 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7314 break; 7315 case SPEED_100 + DUPLEX_HALF: 7316 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7317 break; 7318 case SPEED_100 + DUPLEX_FULL: 7319 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7320 break; 7321 case SPEED_1000 + DUPLEX_FULL: 7322 mac->autoneg = 1; 7323 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7324 break; 7325 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7326 default: 7327 goto err_inval; 7328 } 7329 7330 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7331 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7332 7333 return 0; 7334 7335 err_inval: 7336 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7337 return -EINVAL; 7338 } 7339 7340 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7341 bool runtime) 7342 { 7343 struct net_device *netdev = pci_get_drvdata(pdev); 7344 struct igb_adapter *adapter = netdev_priv(netdev); 7345 struct e1000_hw *hw = &adapter->hw; 7346 u32 ctrl, rctl, status; 7347 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7348 #ifdef CONFIG_PM 7349 int retval = 0; 7350 #endif 7351 7352 netif_device_detach(netdev); 7353 7354 if (netif_running(netdev)) 7355 __igb_close(netdev, true); 7356 7357 igb_clear_interrupt_scheme(adapter); 7358 7359 #ifdef CONFIG_PM 7360 retval = pci_save_state(pdev); 7361 if (retval) 7362 return retval; 7363 #endif 7364 7365 status = rd32(E1000_STATUS); 7366 if (status & E1000_STATUS_LU) 7367 wufc &= ~E1000_WUFC_LNKC; 7368 7369 if (wufc) { 7370 igb_setup_rctl(adapter); 7371 igb_set_rx_mode(netdev); 7372 7373 /* turn on all-multi mode if wake on multicast is enabled */ 7374 if (wufc & E1000_WUFC_MC) { 7375 rctl = rd32(E1000_RCTL); 7376 rctl |= E1000_RCTL_MPE; 7377 wr32(E1000_RCTL, rctl); 7378 } 7379 7380 ctrl = rd32(E1000_CTRL); 7381 /* advertise wake from D3Cold */ 7382 #define E1000_CTRL_ADVD3WUC 0x00100000 7383 /* phy power management enable */ 7384 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7385 ctrl |= E1000_CTRL_ADVD3WUC; 7386 wr32(E1000_CTRL, ctrl); 7387 7388 /* Allow time for pending master requests to run */ 7389 igb_disable_pcie_master(hw); 7390 7391 wr32(E1000_WUC, E1000_WUC_PME_EN); 7392 wr32(E1000_WUFC, wufc); 7393 } else { 7394 wr32(E1000_WUC, 0); 7395 wr32(E1000_WUFC, 0); 7396 } 7397 7398 *enable_wake = wufc || adapter->en_mng_pt; 7399 if (!*enable_wake) 7400 igb_power_down_link(adapter); 7401 else 7402 igb_power_up_link(adapter); 7403 7404 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7405 * would have already happened in close and is redundant. 7406 */ 7407 igb_release_hw_control(adapter); 7408 7409 pci_disable_device(pdev); 7410 7411 return 0; 7412 } 7413 7414 #ifdef CONFIG_PM 7415 #ifdef CONFIG_PM_SLEEP 7416 static int igb_suspend(struct device *dev) 7417 { 7418 int retval; 7419 bool wake; 7420 struct pci_dev *pdev = to_pci_dev(dev); 7421 7422 retval = __igb_shutdown(pdev, &wake, 0); 7423 if (retval) 7424 return retval; 7425 7426 if (wake) { 7427 pci_prepare_to_sleep(pdev); 7428 } else { 7429 pci_wake_from_d3(pdev, false); 7430 pci_set_power_state(pdev, PCI_D3hot); 7431 } 7432 7433 return 0; 7434 } 7435 #endif /* CONFIG_PM_SLEEP */ 7436 7437 static int igb_resume(struct device *dev) 7438 { 7439 struct pci_dev *pdev = to_pci_dev(dev); 7440 struct net_device *netdev = pci_get_drvdata(pdev); 7441 struct igb_adapter *adapter = netdev_priv(netdev); 7442 struct e1000_hw *hw = &adapter->hw; 7443 u32 err; 7444 7445 pci_set_power_state(pdev, PCI_D0); 7446 pci_restore_state(pdev); 7447 pci_save_state(pdev); 7448 7449 if (!pci_device_is_present(pdev)) 7450 return -ENODEV; 7451 err = pci_enable_device_mem(pdev); 7452 if (err) { 7453 dev_err(&pdev->dev, 7454 "igb: Cannot enable PCI device from suspend\n"); 7455 return err; 7456 } 7457 pci_set_master(pdev); 7458 7459 pci_enable_wake(pdev, PCI_D3hot, 0); 7460 pci_enable_wake(pdev, PCI_D3cold, 0); 7461 7462 if (igb_init_interrupt_scheme(adapter, true)) { 7463 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7464 return -ENOMEM; 7465 } 7466 7467 igb_reset(adapter); 7468 7469 /* let the f/w know that the h/w is now under the control of the 7470 * driver. 7471 */ 7472 igb_get_hw_control(adapter); 7473 7474 wr32(E1000_WUS, ~0); 7475 7476 if (netdev->flags & IFF_UP) { 7477 rtnl_lock(); 7478 err = __igb_open(netdev, true); 7479 rtnl_unlock(); 7480 if (err) 7481 return err; 7482 } 7483 7484 netif_device_attach(netdev); 7485 return 0; 7486 } 7487 7488 static int igb_runtime_idle(struct device *dev) 7489 { 7490 struct pci_dev *pdev = to_pci_dev(dev); 7491 struct net_device *netdev = pci_get_drvdata(pdev); 7492 struct igb_adapter *adapter = netdev_priv(netdev); 7493 7494 if (!igb_has_link(adapter)) 7495 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7496 7497 return -EBUSY; 7498 } 7499 7500 static int igb_runtime_suspend(struct device *dev) 7501 { 7502 struct pci_dev *pdev = to_pci_dev(dev); 7503 int retval; 7504 bool wake; 7505 7506 retval = __igb_shutdown(pdev, &wake, 1); 7507 if (retval) 7508 return retval; 7509 7510 if (wake) { 7511 pci_prepare_to_sleep(pdev); 7512 } else { 7513 pci_wake_from_d3(pdev, false); 7514 pci_set_power_state(pdev, PCI_D3hot); 7515 } 7516 7517 return 0; 7518 } 7519 7520 static int igb_runtime_resume(struct device *dev) 7521 { 7522 return igb_resume(dev); 7523 } 7524 #endif /* CONFIG_PM */ 7525 7526 static void igb_shutdown(struct pci_dev *pdev) 7527 { 7528 bool wake; 7529 7530 __igb_shutdown(pdev, &wake, 0); 7531 7532 if (system_state == SYSTEM_POWER_OFF) { 7533 pci_wake_from_d3(pdev, wake); 7534 pci_set_power_state(pdev, PCI_D3hot); 7535 } 7536 } 7537 7538 #ifdef CONFIG_PCI_IOV 7539 static int igb_sriov_reinit(struct pci_dev *dev) 7540 { 7541 struct net_device *netdev = pci_get_drvdata(dev); 7542 struct igb_adapter *adapter = netdev_priv(netdev); 7543 struct pci_dev *pdev = adapter->pdev; 7544 7545 rtnl_lock(); 7546 7547 if (netif_running(netdev)) 7548 igb_close(netdev); 7549 else 7550 igb_reset(adapter); 7551 7552 igb_clear_interrupt_scheme(adapter); 7553 7554 igb_init_queue_configuration(adapter); 7555 7556 if (igb_init_interrupt_scheme(adapter, true)) { 7557 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7558 return -ENOMEM; 7559 } 7560 7561 if (netif_running(netdev)) 7562 igb_open(netdev); 7563 7564 rtnl_unlock(); 7565 7566 return 0; 7567 } 7568 7569 static int igb_pci_disable_sriov(struct pci_dev *dev) 7570 { 7571 int err = igb_disable_sriov(dev); 7572 7573 if (!err) 7574 err = igb_sriov_reinit(dev); 7575 7576 return err; 7577 } 7578 7579 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7580 { 7581 int err = igb_enable_sriov(dev, num_vfs); 7582 7583 if (err) 7584 goto out; 7585 7586 err = igb_sriov_reinit(dev); 7587 if (!err) 7588 return num_vfs; 7589 7590 out: 7591 return err; 7592 } 7593 7594 #endif 7595 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7596 { 7597 #ifdef CONFIG_PCI_IOV 7598 if (num_vfs == 0) 7599 return igb_pci_disable_sriov(dev); 7600 else 7601 return igb_pci_enable_sriov(dev, num_vfs); 7602 #endif 7603 return 0; 7604 } 7605 7606 #ifdef CONFIG_NET_POLL_CONTROLLER 7607 /* Polling 'interrupt' - used by things like netconsole to send skbs 7608 * without having to re-enable interrupts. It's not called while 7609 * the interrupt routine is executing. 7610 */ 7611 static void igb_netpoll(struct net_device *netdev) 7612 { 7613 struct igb_adapter *adapter = netdev_priv(netdev); 7614 struct e1000_hw *hw = &adapter->hw; 7615 struct igb_q_vector *q_vector; 7616 int i; 7617 7618 for (i = 0; i < adapter->num_q_vectors; i++) { 7619 q_vector = adapter->q_vector[i]; 7620 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7621 wr32(E1000_EIMC, q_vector->eims_value); 7622 else 7623 igb_irq_disable(adapter); 7624 napi_schedule(&q_vector->napi); 7625 } 7626 } 7627 #endif /* CONFIG_NET_POLL_CONTROLLER */ 7628 7629 /** 7630 * igb_io_error_detected - called when PCI error is detected 7631 * @pdev: Pointer to PCI device 7632 * @state: The current pci connection state 7633 * 7634 * This function is called after a PCI bus error affecting 7635 * this device has been detected. 7636 **/ 7637 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7638 pci_channel_state_t state) 7639 { 7640 struct net_device *netdev = pci_get_drvdata(pdev); 7641 struct igb_adapter *adapter = netdev_priv(netdev); 7642 7643 netif_device_detach(netdev); 7644 7645 if (state == pci_channel_io_perm_failure) 7646 return PCI_ERS_RESULT_DISCONNECT; 7647 7648 if (netif_running(netdev)) 7649 igb_down(adapter); 7650 pci_disable_device(pdev); 7651 7652 /* Request a slot slot reset. */ 7653 return PCI_ERS_RESULT_NEED_RESET; 7654 } 7655 7656 /** 7657 * igb_io_slot_reset - called after the pci bus has been reset. 7658 * @pdev: Pointer to PCI device 7659 * 7660 * Restart the card from scratch, as if from a cold-boot. Implementation 7661 * resembles the first-half of the igb_resume routine. 7662 **/ 7663 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7664 { 7665 struct net_device *netdev = pci_get_drvdata(pdev); 7666 struct igb_adapter *adapter = netdev_priv(netdev); 7667 struct e1000_hw *hw = &adapter->hw; 7668 pci_ers_result_t result; 7669 int err; 7670 7671 if (pci_enable_device_mem(pdev)) { 7672 dev_err(&pdev->dev, 7673 "Cannot re-enable PCI device after reset.\n"); 7674 result = PCI_ERS_RESULT_DISCONNECT; 7675 } else { 7676 pci_set_master(pdev); 7677 pci_restore_state(pdev); 7678 pci_save_state(pdev); 7679 7680 pci_enable_wake(pdev, PCI_D3hot, 0); 7681 pci_enable_wake(pdev, PCI_D3cold, 0); 7682 7683 igb_reset(adapter); 7684 wr32(E1000_WUS, ~0); 7685 result = PCI_ERS_RESULT_RECOVERED; 7686 } 7687 7688 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7689 if (err) { 7690 dev_err(&pdev->dev, 7691 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7692 err); 7693 /* non-fatal, continue */ 7694 } 7695 7696 return result; 7697 } 7698 7699 /** 7700 * igb_io_resume - called when traffic can start flowing again. 7701 * @pdev: Pointer to PCI device 7702 * 7703 * This callback is called when the error recovery driver tells us that 7704 * its OK to resume normal operation. Implementation resembles the 7705 * second-half of the igb_resume routine. 7706 */ 7707 static void igb_io_resume(struct pci_dev *pdev) 7708 { 7709 struct net_device *netdev = pci_get_drvdata(pdev); 7710 struct igb_adapter *adapter = netdev_priv(netdev); 7711 7712 if (netif_running(netdev)) { 7713 if (igb_up(adapter)) { 7714 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7715 return; 7716 } 7717 } 7718 7719 netif_device_attach(netdev); 7720 7721 /* let the f/w know that the h/w is now under the control of the 7722 * driver. 7723 */ 7724 igb_get_hw_control(adapter); 7725 } 7726 7727 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7728 u8 qsel) 7729 { 7730 u32 rar_low, rar_high; 7731 struct e1000_hw *hw = &adapter->hw; 7732 7733 /* HW expects these in little endian so we reverse the byte order 7734 * from network order (big endian) to little endian 7735 */ 7736 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7737 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7738 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7739 7740 /* Indicate to hardware the Address is Valid. */ 7741 rar_high |= E1000_RAH_AV; 7742 7743 if (hw->mac.type == e1000_82575) 7744 rar_high |= E1000_RAH_POOL_1 * qsel; 7745 else 7746 rar_high |= E1000_RAH_POOL_1 << qsel; 7747 7748 wr32(E1000_RAL(index), rar_low); 7749 wrfl(); 7750 wr32(E1000_RAH(index), rar_high); 7751 wrfl(); 7752 } 7753 7754 static int igb_set_vf_mac(struct igb_adapter *adapter, 7755 int vf, unsigned char *mac_addr) 7756 { 7757 struct e1000_hw *hw = &adapter->hw; 7758 /* VF MAC addresses start at end of receive addresses and moves 7759 * towards the first, as a result a collision should not be possible 7760 */ 7761 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7762 7763 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7764 7765 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7766 7767 return 0; 7768 } 7769 7770 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7771 { 7772 struct igb_adapter *adapter = netdev_priv(netdev); 7773 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7774 return -EINVAL; 7775 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7776 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7777 dev_info(&adapter->pdev->dev, 7778 "Reload the VF driver to make this change effective."); 7779 if (test_bit(__IGB_DOWN, &adapter->state)) { 7780 dev_warn(&adapter->pdev->dev, 7781 "The VF MAC address has been set, but the PF device is not up.\n"); 7782 dev_warn(&adapter->pdev->dev, 7783 "Bring the PF device up before attempting to use the VF device.\n"); 7784 } 7785 return igb_set_vf_mac(adapter, vf, mac); 7786 } 7787 7788 static int igb_link_mbps(int internal_link_speed) 7789 { 7790 switch (internal_link_speed) { 7791 case SPEED_100: 7792 return 100; 7793 case SPEED_1000: 7794 return 1000; 7795 default: 7796 return 0; 7797 } 7798 } 7799 7800 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7801 int link_speed) 7802 { 7803 int rf_dec, rf_int; 7804 u32 bcnrc_val; 7805 7806 if (tx_rate != 0) { 7807 /* Calculate the rate factor values to set */ 7808 rf_int = link_speed / tx_rate; 7809 rf_dec = (link_speed - (rf_int * tx_rate)); 7810 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7811 tx_rate; 7812 7813 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7814 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7815 E1000_RTTBCNRC_RF_INT_MASK); 7816 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7817 } else { 7818 bcnrc_val = 0; 7819 } 7820 7821 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7822 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7823 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7824 */ 7825 wr32(E1000_RTTBCNRM, 0x14); 7826 wr32(E1000_RTTBCNRC, bcnrc_val); 7827 } 7828 7829 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7830 { 7831 int actual_link_speed, i; 7832 bool reset_rate = false; 7833 7834 /* VF TX rate limit was not set or not supported */ 7835 if ((adapter->vf_rate_link_speed == 0) || 7836 (adapter->hw.mac.type != e1000_82576)) 7837 return; 7838 7839 actual_link_speed = igb_link_mbps(adapter->link_speed); 7840 if (actual_link_speed != adapter->vf_rate_link_speed) { 7841 reset_rate = true; 7842 adapter->vf_rate_link_speed = 0; 7843 dev_info(&adapter->pdev->dev, 7844 "Link speed has been changed. VF Transmit rate is disabled\n"); 7845 } 7846 7847 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7848 if (reset_rate) 7849 adapter->vf_data[i].tx_rate = 0; 7850 7851 igb_set_vf_rate_limit(&adapter->hw, i, 7852 adapter->vf_data[i].tx_rate, 7853 actual_link_speed); 7854 } 7855 } 7856 7857 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 7858 int min_tx_rate, int max_tx_rate) 7859 { 7860 struct igb_adapter *adapter = netdev_priv(netdev); 7861 struct e1000_hw *hw = &adapter->hw; 7862 int actual_link_speed; 7863 7864 if (hw->mac.type != e1000_82576) 7865 return -EOPNOTSUPP; 7866 7867 if (min_tx_rate) 7868 return -EINVAL; 7869 7870 actual_link_speed = igb_link_mbps(adapter->link_speed); 7871 if ((vf >= adapter->vfs_allocated_count) || 7872 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7873 (max_tx_rate < 0) || 7874 (max_tx_rate > actual_link_speed)) 7875 return -EINVAL; 7876 7877 adapter->vf_rate_link_speed = actual_link_speed; 7878 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 7879 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 7880 7881 return 0; 7882 } 7883 7884 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7885 bool setting) 7886 { 7887 struct igb_adapter *adapter = netdev_priv(netdev); 7888 struct e1000_hw *hw = &adapter->hw; 7889 u32 reg_val, reg_offset; 7890 7891 if (!adapter->vfs_allocated_count) 7892 return -EOPNOTSUPP; 7893 7894 if (vf >= adapter->vfs_allocated_count) 7895 return -EINVAL; 7896 7897 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7898 reg_val = rd32(reg_offset); 7899 if (setting) 7900 reg_val |= ((1 << vf) | 7901 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7902 else 7903 reg_val &= ~((1 << vf) | 7904 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7905 wr32(reg_offset, reg_val); 7906 7907 adapter->vf_data[vf].spoofchk_enabled = setting; 7908 return 0; 7909 } 7910 7911 static int igb_ndo_get_vf_config(struct net_device *netdev, 7912 int vf, struct ifla_vf_info *ivi) 7913 { 7914 struct igb_adapter *adapter = netdev_priv(netdev); 7915 if (vf >= adapter->vfs_allocated_count) 7916 return -EINVAL; 7917 ivi->vf = vf; 7918 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7919 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 7920 ivi->min_tx_rate = 0; 7921 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7922 ivi->qos = adapter->vf_data[vf].pf_qos; 7923 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7924 return 0; 7925 } 7926 7927 static void igb_vmm_control(struct igb_adapter *adapter) 7928 { 7929 struct e1000_hw *hw = &adapter->hw; 7930 u32 reg; 7931 7932 switch (hw->mac.type) { 7933 case e1000_82575: 7934 case e1000_i210: 7935 case e1000_i211: 7936 case e1000_i354: 7937 default: 7938 /* replication is not supported for 82575 */ 7939 return; 7940 case e1000_82576: 7941 /* notify HW that the MAC is adding vlan tags */ 7942 reg = rd32(E1000_DTXCTL); 7943 reg |= E1000_DTXCTL_VLAN_ADDED; 7944 wr32(E1000_DTXCTL, reg); 7945 /* Fall through */ 7946 case e1000_82580: 7947 /* enable replication vlan tag stripping */ 7948 reg = rd32(E1000_RPLOLR); 7949 reg |= E1000_RPLOLR_STRVLAN; 7950 wr32(E1000_RPLOLR, reg); 7951 /* Fall through */ 7952 case e1000_i350: 7953 /* none of the above registers are supported by i350 */ 7954 break; 7955 } 7956 7957 if (adapter->vfs_allocated_count) { 7958 igb_vmdq_set_loopback_pf(hw, true); 7959 igb_vmdq_set_replication_pf(hw, true); 7960 igb_vmdq_set_anti_spoofing_pf(hw, true, 7961 adapter->vfs_allocated_count); 7962 } else { 7963 igb_vmdq_set_loopback_pf(hw, false); 7964 igb_vmdq_set_replication_pf(hw, false); 7965 } 7966 } 7967 7968 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7969 { 7970 struct e1000_hw *hw = &adapter->hw; 7971 u32 dmac_thr; 7972 u16 hwm; 7973 7974 if (hw->mac.type > e1000_82580) { 7975 if (adapter->flags & IGB_FLAG_DMAC) { 7976 u32 reg; 7977 7978 /* force threshold to 0. */ 7979 wr32(E1000_DMCTXTH, 0); 7980 7981 /* DMA Coalescing high water mark needs to be greater 7982 * than the Rx threshold. Set hwm to PBA - max frame 7983 * size in 16B units, capping it at PBA - 6KB. 7984 */ 7985 hwm = 64 * pba - adapter->max_frame_size / 16; 7986 if (hwm < 64 * (pba - 6)) 7987 hwm = 64 * (pba - 6); 7988 reg = rd32(E1000_FCRTC); 7989 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7990 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7991 & E1000_FCRTC_RTH_COAL_MASK); 7992 wr32(E1000_FCRTC, reg); 7993 7994 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7995 * frame size, capping it at PBA - 10KB. 7996 */ 7997 dmac_thr = pba - adapter->max_frame_size / 512; 7998 if (dmac_thr < pba - 10) 7999 dmac_thr = pba - 10; 8000 reg = rd32(E1000_DMACR); 8001 reg &= ~E1000_DMACR_DMACTHR_MASK; 8002 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8003 & E1000_DMACR_DMACTHR_MASK); 8004 8005 /* transition to L0x or L1 if available..*/ 8006 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8007 8008 /* watchdog timer= +-1000 usec in 32usec intervals */ 8009 reg |= (1000 >> 5); 8010 8011 /* Disable BMC-to-OS Watchdog Enable */ 8012 if (hw->mac.type != e1000_i354) 8013 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8014 8015 wr32(E1000_DMACR, reg); 8016 8017 /* no lower threshold to disable 8018 * coalescing(smart fifb)-UTRESH=0 8019 */ 8020 wr32(E1000_DMCRTRH, 0); 8021 8022 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8023 8024 wr32(E1000_DMCTLX, reg); 8025 8026 /* free space in tx packet buffer to wake from 8027 * DMA coal 8028 */ 8029 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8030 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8031 8032 /* make low power state decision controlled 8033 * by DMA coal 8034 */ 8035 reg = rd32(E1000_PCIEMISC); 8036 reg &= ~E1000_PCIEMISC_LX_DECISION; 8037 wr32(E1000_PCIEMISC, reg); 8038 } /* endif adapter->dmac is not disabled */ 8039 } else if (hw->mac.type == e1000_82580) { 8040 u32 reg = rd32(E1000_PCIEMISC); 8041 8042 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8043 wr32(E1000_DMACR, 0); 8044 } 8045 } 8046 8047 /** 8048 * igb_read_i2c_byte - Reads 8 bit word over I2C 8049 * @hw: pointer to hardware structure 8050 * @byte_offset: byte offset to read 8051 * @dev_addr: device address 8052 * @data: value read 8053 * 8054 * Performs byte read operation over I2C interface at 8055 * a specified device address. 8056 **/ 8057 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8058 u8 dev_addr, u8 *data) 8059 { 8060 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8061 struct i2c_client *this_client = adapter->i2c_client; 8062 s32 status; 8063 u16 swfw_mask = 0; 8064 8065 if (!this_client) 8066 return E1000_ERR_I2C; 8067 8068 swfw_mask = E1000_SWFW_PHY0_SM; 8069 8070 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8071 return E1000_ERR_SWFW_SYNC; 8072 8073 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8074 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8075 8076 if (status < 0) 8077 return E1000_ERR_I2C; 8078 else { 8079 *data = status; 8080 return 0; 8081 } 8082 } 8083 8084 /** 8085 * igb_write_i2c_byte - Writes 8 bit word over I2C 8086 * @hw: pointer to hardware structure 8087 * @byte_offset: byte offset to write 8088 * @dev_addr: device address 8089 * @data: value to write 8090 * 8091 * Performs byte write operation over I2C interface at 8092 * a specified device address. 8093 **/ 8094 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8095 u8 dev_addr, u8 data) 8096 { 8097 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8098 struct i2c_client *this_client = adapter->i2c_client; 8099 s32 status; 8100 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8101 8102 if (!this_client) 8103 return E1000_ERR_I2C; 8104 8105 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8106 return E1000_ERR_SWFW_SYNC; 8107 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8108 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8109 8110 if (status) 8111 return E1000_ERR_I2C; 8112 else 8113 return 0; 8114 8115 } 8116 8117 int igb_reinit_queues(struct igb_adapter *adapter) 8118 { 8119 struct net_device *netdev = adapter->netdev; 8120 struct pci_dev *pdev = adapter->pdev; 8121 int err = 0; 8122 8123 if (netif_running(netdev)) 8124 igb_close(netdev); 8125 8126 igb_reset_interrupt_capability(adapter); 8127 8128 if (igb_init_interrupt_scheme(adapter, true)) { 8129 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8130 return -ENOMEM; 8131 } 8132 8133 if (netif_running(netdev)) 8134 err = igb_open(netdev); 8135 8136 return err; 8137 } 8138 /* igb_main.c */ 8139