1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3 
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5 
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/prefetch.h>
32 #include <linux/bpf.h>
33 #include <linux/bpf_trace.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/etherdevice.h>
36 #ifdef CONFIG_IGB_DCA
37 #include <linux/dca.h>
38 #endif
39 #include <linux/i2c.h>
40 #include "igb.h"
41 
42 enum queue_mode {
43 	QUEUE_MODE_STRICT_PRIORITY,
44 	QUEUE_MODE_STREAM_RESERVATION,
45 };
46 
47 enum tx_queue_prio {
48 	TX_QUEUE_PRIO_HIGH,
49 	TX_QUEUE_PRIO_LOW,
50 };
51 
52 char igb_driver_name[] = "igb";
53 static const char igb_driver_string[] =
54 				"Intel(R) Gigabit Ethernet Network Driver";
55 static const char igb_copyright[] =
56 				"Copyright (c) 2007-2014 Intel Corporation.";
57 
58 static const struct e1000_info *igb_info_tbl[] = {
59 	[board_82575] = &e1000_82575_info,
60 };
61 
62 static const struct pci_device_id igb_pci_tbl[] = {
63 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
64 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
65 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
66 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
67 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
68 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
69 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
70 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
71 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
72 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
73 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
74 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
75 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
76 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
77 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
78 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
79 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
80 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
81 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
82 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
83 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
84 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
85 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
86 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
87 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
88 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
89 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
90 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
91 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
92 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
93 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
94 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
95 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
96 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
97 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
98 	/* required last entry */
99 	{0, }
100 };
101 
102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
103 
104 static int igb_setup_all_tx_resources(struct igb_adapter *);
105 static int igb_setup_all_rx_resources(struct igb_adapter *);
106 static void igb_free_all_tx_resources(struct igb_adapter *);
107 static void igb_free_all_rx_resources(struct igb_adapter *);
108 static void igb_setup_mrqc(struct igb_adapter *);
109 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
110 static void igb_remove(struct pci_dev *pdev);
111 static void igb_init_queue_configuration(struct igb_adapter *adapter);
112 static int igb_sw_init(struct igb_adapter *);
113 int igb_open(struct net_device *);
114 int igb_close(struct net_device *);
115 static void igb_configure(struct igb_adapter *);
116 static void igb_configure_tx(struct igb_adapter *);
117 static void igb_configure_rx(struct igb_adapter *);
118 static void igb_clean_all_tx_rings(struct igb_adapter *);
119 static void igb_clean_all_rx_rings(struct igb_adapter *);
120 static void igb_clean_tx_ring(struct igb_ring *);
121 static void igb_clean_rx_ring(struct igb_ring *);
122 static void igb_set_rx_mode(struct net_device *);
123 static void igb_update_phy_info(struct timer_list *);
124 static void igb_watchdog(struct timer_list *);
125 static void igb_watchdog_task(struct work_struct *);
126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127 static void igb_get_stats64(struct net_device *dev,
128 			    struct rtnl_link_stats64 *stats);
129 static int igb_change_mtu(struct net_device *, int);
130 static int igb_set_mac(struct net_device *, void *);
131 static void igb_set_uta(struct igb_adapter *adapter, bool set);
132 static irqreturn_t igb_intr(int irq, void *);
133 static irqreturn_t igb_intr_msi(int irq, void *);
134 static irqreturn_t igb_msix_other(int irq, void *);
135 static irqreturn_t igb_msix_ring(int irq, void *);
136 #ifdef CONFIG_IGB_DCA
137 static void igb_update_dca(struct igb_q_vector *);
138 static void igb_setup_dca(struct igb_adapter *);
139 #endif /* CONFIG_IGB_DCA */
140 static int igb_poll(struct napi_struct *, int);
141 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142 static int igb_clean_rx_irq(struct igb_q_vector *, int);
143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145 static void igb_reset_task(struct work_struct *);
146 static void igb_vlan_mode(struct net_device *netdev,
147 			  netdev_features_t features);
148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150 static void igb_restore_vlan(struct igb_adapter *);
151 static void igb_rar_set_index(struct igb_adapter *, u32);
152 static void igb_ping_all_vfs(struct igb_adapter *);
153 static void igb_msg_task(struct igb_adapter *);
154 static void igb_vmm_control(struct igb_adapter *);
155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156 static void igb_flush_mac_table(struct igb_adapter *);
157 static int igb_available_rars(struct igb_adapter *, u8);
158 static void igb_set_default_mac_filter(struct igb_adapter *);
159 static int igb_uc_sync(struct net_device *, const unsigned char *);
160 static int igb_uc_unsync(struct net_device *, const unsigned char *);
161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 			       int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 				   bool setting);
168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 				bool setting);
170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 				 struct ifla_vf_info *ivi);
172 static void igb_check_vf_rate_limit(struct igb_adapter *);
173 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175 
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static int igb_disable_sriov(struct pci_dev *dev, bool reinit);
179 #endif
180 
181 static int igb_suspend(struct device *);
182 static int igb_resume(struct device *);
183 static int igb_runtime_suspend(struct device *dev);
184 static int igb_runtime_resume(struct device *dev);
185 static int igb_runtime_idle(struct device *dev);
186 #ifdef CONFIG_PM
187 static const struct dev_pm_ops igb_pm_ops = {
188 	SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
189 	SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
190 			igb_runtime_idle)
191 };
192 #endif
193 static void igb_shutdown(struct pci_dev *);
194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 	.notifier_call	= igb_notify_dca,
199 	.next		= NULL,
200 	.priority	= 0
201 };
202 #endif
203 #ifdef CONFIG_PCI_IOV
204 static unsigned int max_vfs;
205 module_param(max_vfs, uint, 0);
206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207 #endif /* CONFIG_PCI_IOV */
208 
209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 		     pci_channel_state_t);
211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212 static void igb_io_resume(struct pci_dev *);
213 
214 static const struct pci_error_handlers igb_err_handler = {
215 	.error_detected = igb_io_error_detected,
216 	.slot_reset = igb_io_slot_reset,
217 	.resume = igb_io_resume,
218 };
219 
220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221 
222 static struct pci_driver igb_driver = {
223 	.name     = igb_driver_name,
224 	.id_table = igb_pci_tbl,
225 	.probe    = igb_probe,
226 	.remove   = igb_remove,
227 #ifdef CONFIG_PM
228 	.driver.pm = &igb_pm_ops,
229 #endif
230 	.shutdown = igb_shutdown,
231 	.sriov_configure = igb_pci_sriov_configure,
232 	.err_handler = &igb_err_handler
233 };
234 
235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237 MODULE_LICENSE("GPL v2");
238 
239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240 static int debug = -1;
241 module_param(debug, int, 0);
242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243 
244 struct igb_reg_info {
245 	u32 ofs;
246 	char *name;
247 };
248 
249 static const struct igb_reg_info igb_reg_info_tbl[] = {
250 
251 	/* General Registers */
252 	{E1000_CTRL, "CTRL"},
253 	{E1000_STATUS, "STATUS"},
254 	{E1000_CTRL_EXT, "CTRL_EXT"},
255 
256 	/* Interrupt Registers */
257 	{E1000_ICR, "ICR"},
258 
259 	/* RX Registers */
260 	{E1000_RCTL, "RCTL"},
261 	{E1000_RDLEN(0), "RDLEN"},
262 	{E1000_RDH(0), "RDH"},
263 	{E1000_RDT(0), "RDT"},
264 	{E1000_RXDCTL(0), "RXDCTL"},
265 	{E1000_RDBAL(0), "RDBAL"},
266 	{E1000_RDBAH(0), "RDBAH"},
267 
268 	/* TX Registers */
269 	{E1000_TCTL, "TCTL"},
270 	{E1000_TDBAL(0), "TDBAL"},
271 	{E1000_TDBAH(0), "TDBAH"},
272 	{E1000_TDLEN(0), "TDLEN"},
273 	{E1000_TDH(0), "TDH"},
274 	{E1000_TDT(0), "TDT"},
275 	{E1000_TXDCTL(0), "TXDCTL"},
276 	{E1000_TDFH, "TDFH"},
277 	{E1000_TDFT, "TDFT"},
278 	{E1000_TDFHS, "TDFHS"},
279 	{E1000_TDFPC, "TDFPC"},
280 
281 	/* List Terminator */
282 	{}
283 };
284 
285 /* igb_regdump - register printout routine */
286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287 {
288 	int n = 0;
289 	char rname[16];
290 	u32 regs[8];
291 
292 	switch (reginfo->ofs) {
293 	case E1000_RDLEN(0):
294 		for (n = 0; n < 4; n++)
295 			regs[n] = rd32(E1000_RDLEN(n));
296 		break;
297 	case E1000_RDH(0):
298 		for (n = 0; n < 4; n++)
299 			regs[n] = rd32(E1000_RDH(n));
300 		break;
301 	case E1000_RDT(0):
302 		for (n = 0; n < 4; n++)
303 			regs[n] = rd32(E1000_RDT(n));
304 		break;
305 	case E1000_RXDCTL(0):
306 		for (n = 0; n < 4; n++)
307 			regs[n] = rd32(E1000_RXDCTL(n));
308 		break;
309 	case E1000_RDBAL(0):
310 		for (n = 0; n < 4; n++)
311 			regs[n] = rd32(E1000_RDBAL(n));
312 		break;
313 	case E1000_RDBAH(0):
314 		for (n = 0; n < 4; n++)
315 			regs[n] = rd32(E1000_RDBAH(n));
316 		break;
317 	case E1000_TDBAL(0):
318 		for (n = 0; n < 4; n++)
319 			regs[n] = rd32(E1000_TDBAL(n));
320 		break;
321 	case E1000_TDBAH(0):
322 		for (n = 0; n < 4; n++)
323 			regs[n] = rd32(E1000_TDBAH(n));
324 		break;
325 	case E1000_TDLEN(0):
326 		for (n = 0; n < 4; n++)
327 			regs[n] = rd32(E1000_TDLEN(n));
328 		break;
329 	case E1000_TDH(0):
330 		for (n = 0; n < 4; n++)
331 			regs[n] = rd32(E1000_TDH(n));
332 		break;
333 	case E1000_TDT(0):
334 		for (n = 0; n < 4; n++)
335 			regs[n] = rd32(E1000_TDT(n));
336 		break;
337 	case E1000_TXDCTL(0):
338 		for (n = 0; n < 4; n++)
339 			regs[n] = rd32(E1000_TXDCTL(n));
340 		break;
341 	default:
342 		pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 		return;
344 	}
345 
346 	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 	pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 		regs[2], regs[3]);
349 }
350 
351 /* igb_dump - Print registers, Tx-rings and Rx-rings */
352 static void igb_dump(struct igb_adapter *adapter)
353 {
354 	struct net_device *netdev = adapter->netdev;
355 	struct e1000_hw *hw = &adapter->hw;
356 	struct igb_reg_info *reginfo;
357 	struct igb_ring *tx_ring;
358 	union e1000_adv_tx_desc *tx_desc;
359 	struct my_u0 { __le64 a; __le64 b; } *u0;
360 	struct igb_ring *rx_ring;
361 	union e1000_adv_rx_desc *rx_desc;
362 	u32 staterr;
363 	u16 i, n;
364 
365 	if (!netif_msg_hw(adapter))
366 		return;
367 
368 	/* Print netdevice Info */
369 	if (netdev) {
370 		dev_info(&adapter->pdev->dev, "Net device Info\n");
371 		pr_info("Device Name     state            trans_start\n");
372 		pr_info("%-15s %016lX %016lX\n", netdev->name,
373 			netdev->state, dev_trans_start(netdev));
374 	}
375 
376 	/* Print Registers */
377 	dev_info(&adapter->pdev->dev, "Register Dump\n");
378 	pr_info(" Register Name   Value\n");
379 	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 	     reginfo->name; reginfo++) {
381 		igb_regdump(hw, reginfo);
382 	}
383 
384 	/* Print TX Ring Summary */
385 	if (!netdev || !netif_running(netdev))
386 		goto exit;
387 
388 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 	pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
390 	for (n = 0; n < adapter->num_tx_queues; n++) {
391 		struct igb_tx_buffer *buffer_info;
392 		tx_ring = adapter->tx_ring[n];
393 		buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 		pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 			n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 			(u64)dma_unmap_addr(buffer_info, dma),
397 			dma_unmap_len(buffer_info, len),
398 			buffer_info->next_to_watch,
399 			(u64)buffer_info->time_stamp);
400 	}
401 
402 	/* Print TX Rings */
403 	if (!netif_msg_tx_done(adapter))
404 		goto rx_ring_summary;
405 
406 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407 
408 	/* Transmit Descriptor Formats
409 	 *
410 	 * Advanced Transmit Descriptor
411 	 *   +--------------------------------------------------------------+
412 	 * 0 |         Buffer Address [63:0]                                |
413 	 *   +--------------------------------------------------------------+
414 	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
415 	 *   +--------------------------------------------------------------+
416 	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
417 	 */
418 
419 	for (n = 0; n < adapter->num_tx_queues; n++) {
420 		tx_ring = adapter->tx_ring[n];
421 		pr_info("------------------------------------\n");
422 		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 		pr_info("------------------------------------\n");
424 		pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
425 
426 		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 			const char *next_desc;
428 			struct igb_tx_buffer *buffer_info;
429 			tx_desc = IGB_TX_DESC(tx_ring, i);
430 			buffer_info = &tx_ring->tx_buffer_info[i];
431 			u0 = (struct my_u0 *)tx_desc;
432 			if (i == tx_ring->next_to_use &&
433 			    i == tx_ring->next_to_clean)
434 				next_desc = " NTC/U";
435 			else if (i == tx_ring->next_to_use)
436 				next_desc = " NTU";
437 			else if (i == tx_ring->next_to_clean)
438 				next_desc = " NTC";
439 			else
440 				next_desc = "";
441 
442 			pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
443 				i, le64_to_cpu(u0->a),
444 				le64_to_cpu(u0->b),
445 				(u64)dma_unmap_addr(buffer_info, dma),
446 				dma_unmap_len(buffer_info, len),
447 				buffer_info->next_to_watch,
448 				(u64)buffer_info->time_stamp,
449 				buffer_info->skb, next_desc);
450 
451 			if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 				print_hex_dump(KERN_INFO, "",
453 					DUMP_PREFIX_ADDRESS,
454 					16, 1, buffer_info->skb->data,
455 					dma_unmap_len(buffer_info, len),
456 					true);
457 		}
458 	}
459 
460 	/* Print RX Rings Summary */
461 rx_ring_summary:
462 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 	pr_info("Queue [NTU] [NTC]\n");
464 	for (n = 0; n < adapter->num_rx_queues; n++) {
465 		rx_ring = adapter->rx_ring[n];
466 		pr_info(" %5d %5X %5X\n",
467 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 	}
469 
470 	/* Print RX Rings */
471 	if (!netif_msg_rx_status(adapter))
472 		goto exit;
473 
474 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475 
476 	/* Advanced Receive Descriptor (Read) Format
477 	 *    63                                           1        0
478 	 *    +-----------------------------------------------------+
479 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
480 	 *    +----------------------------------------------+------+
481 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
482 	 *    +-----------------------------------------------------+
483 	 *
484 	 *
485 	 * Advanced Receive Descriptor (Write-Back) Format
486 	 *
487 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
488 	 *   +------------------------------------------------------+
489 	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
490 	 *   | Checksum   Ident  |   |           |    | Type | Type |
491 	 *   +------------------------------------------------------+
492 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 	 *   +------------------------------------------------------+
494 	 *   63       48 47    32 31            20 19               0
495 	 */
496 
497 	for (n = 0; n < adapter->num_rx_queues; n++) {
498 		rx_ring = adapter->rx_ring[n];
499 		pr_info("------------------------------------\n");
500 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 		pr_info("------------------------------------\n");
502 		pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
503 		pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504 
505 		for (i = 0; i < rx_ring->count; i++) {
506 			const char *next_desc;
507 			struct igb_rx_buffer *buffer_info;
508 			buffer_info = &rx_ring->rx_buffer_info[i];
509 			rx_desc = IGB_RX_DESC(rx_ring, i);
510 			u0 = (struct my_u0 *)rx_desc;
511 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 
513 			if (i == rx_ring->next_to_use)
514 				next_desc = " NTU";
515 			else if (i == rx_ring->next_to_clean)
516 				next_desc = " NTC";
517 			else
518 				next_desc = "";
519 
520 			if (staterr & E1000_RXD_STAT_DD) {
521 				/* Descriptor Done */
522 				pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
523 					"RWB", i,
524 					le64_to_cpu(u0->a),
525 					le64_to_cpu(u0->b),
526 					next_desc);
527 			} else {
528 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
529 					"R  ", i,
530 					le64_to_cpu(u0->a),
531 					le64_to_cpu(u0->b),
532 					(u64)buffer_info->dma,
533 					next_desc);
534 
535 				if (netif_msg_pktdata(adapter) &&
536 				    buffer_info->dma && buffer_info->page) {
537 					print_hex_dump(KERN_INFO, "",
538 					  DUMP_PREFIX_ADDRESS,
539 					  16, 1,
540 					  page_address(buffer_info->page) +
541 						      buffer_info->page_offset,
542 					  igb_rx_bufsz(rx_ring), true);
543 				}
544 			}
545 		}
546 	}
547 
548 exit:
549 	return;
550 }
551 
552 /**
553  *  igb_get_i2c_data - Reads the I2C SDA data bit
554  *  @data: opaque pointer to adapter struct
555  *
556  *  Returns the I2C data bit value
557  **/
558 static int igb_get_i2c_data(void *data)
559 {
560 	struct igb_adapter *adapter = (struct igb_adapter *)data;
561 	struct e1000_hw *hw = &adapter->hw;
562 	s32 i2cctl = rd32(E1000_I2CPARAMS);
563 
564 	return !!(i2cctl & E1000_I2C_DATA_IN);
565 }
566 
567 /**
568  *  igb_set_i2c_data - Sets the I2C data bit
569  *  @data: pointer to hardware structure
570  *  @state: I2C data value (0 or 1) to set
571  *
572  *  Sets the I2C data bit
573  **/
574 static void igb_set_i2c_data(void *data, int state)
575 {
576 	struct igb_adapter *adapter = (struct igb_adapter *)data;
577 	struct e1000_hw *hw = &adapter->hw;
578 	s32 i2cctl = rd32(E1000_I2CPARAMS);
579 
580 	if (state) {
581 		i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
582 	} else {
583 		i2cctl &= ~E1000_I2C_DATA_OE_N;
584 		i2cctl &= ~E1000_I2C_DATA_OUT;
585 	}
586 
587 	wr32(E1000_I2CPARAMS, i2cctl);
588 	wrfl();
589 }
590 
591 /**
592  *  igb_set_i2c_clk - Sets the I2C SCL clock
593  *  @data: pointer to hardware structure
594  *  @state: state to set clock
595  *
596  *  Sets the I2C clock line to state
597  **/
598 static void igb_set_i2c_clk(void *data, int state)
599 {
600 	struct igb_adapter *adapter = (struct igb_adapter *)data;
601 	struct e1000_hw *hw = &adapter->hw;
602 	s32 i2cctl = rd32(E1000_I2CPARAMS);
603 
604 	if (state) {
605 		i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N;
606 	} else {
607 		i2cctl &= ~E1000_I2C_CLK_OUT;
608 		i2cctl &= ~E1000_I2C_CLK_OE_N;
609 	}
610 	wr32(E1000_I2CPARAMS, i2cctl);
611 	wrfl();
612 }
613 
614 /**
615  *  igb_get_i2c_clk - Gets the I2C SCL clock state
616  *  @data: pointer to hardware structure
617  *
618  *  Gets the I2C clock state
619  **/
620 static int igb_get_i2c_clk(void *data)
621 {
622 	struct igb_adapter *adapter = (struct igb_adapter *)data;
623 	struct e1000_hw *hw = &adapter->hw;
624 	s32 i2cctl = rd32(E1000_I2CPARAMS);
625 
626 	return !!(i2cctl & E1000_I2C_CLK_IN);
627 }
628 
629 static const struct i2c_algo_bit_data igb_i2c_algo = {
630 	.setsda		= igb_set_i2c_data,
631 	.setscl		= igb_set_i2c_clk,
632 	.getsda		= igb_get_i2c_data,
633 	.getscl		= igb_get_i2c_clk,
634 	.udelay		= 5,
635 	.timeout	= 20,
636 };
637 
638 /**
639  *  igb_get_hw_dev - return device
640  *  @hw: pointer to hardware structure
641  *
642  *  used by hardware layer to print debugging information
643  **/
644 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
645 {
646 	struct igb_adapter *adapter = hw->back;
647 	return adapter->netdev;
648 }
649 
650 /**
651  *  igb_init_module - Driver Registration Routine
652  *
653  *  igb_init_module is the first routine called when the driver is
654  *  loaded. All it does is register with the PCI subsystem.
655  **/
656 static int __init igb_init_module(void)
657 {
658 	int ret;
659 
660 	pr_info("%s\n", igb_driver_string);
661 	pr_info("%s\n", igb_copyright);
662 
663 #ifdef CONFIG_IGB_DCA
664 	dca_register_notify(&dca_notifier);
665 #endif
666 	ret = pci_register_driver(&igb_driver);
667 	return ret;
668 }
669 
670 module_init(igb_init_module);
671 
672 /**
673  *  igb_exit_module - Driver Exit Cleanup Routine
674  *
675  *  igb_exit_module is called just before the driver is removed
676  *  from memory.
677  **/
678 static void __exit igb_exit_module(void)
679 {
680 #ifdef CONFIG_IGB_DCA
681 	dca_unregister_notify(&dca_notifier);
682 #endif
683 	pci_unregister_driver(&igb_driver);
684 }
685 
686 module_exit(igb_exit_module);
687 
688 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
689 /**
690  *  igb_cache_ring_register - Descriptor ring to register mapping
691  *  @adapter: board private structure to initialize
692  *
693  *  Once we know the feature-set enabled for the device, we'll cache
694  *  the register offset the descriptor ring is assigned to.
695  **/
696 static void igb_cache_ring_register(struct igb_adapter *adapter)
697 {
698 	int i = 0, j = 0;
699 	u32 rbase_offset = adapter->vfs_allocated_count;
700 
701 	switch (adapter->hw.mac.type) {
702 	case e1000_82576:
703 		/* The queues are allocated for virtualization such that VF 0
704 		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
705 		 * In order to avoid collision we start at the first free queue
706 		 * and continue consuming queues in the same sequence
707 		 */
708 		if (adapter->vfs_allocated_count) {
709 			for (; i < adapter->rss_queues; i++)
710 				adapter->rx_ring[i]->reg_idx = rbase_offset +
711 							       Q_IDX_82576(i);
712 		}
713 		fallthrough;
714 	case e1000_82575:
715 	case e1000_82580:
716 	case e1000_i350:
717 	case e1000_i354:
718 	case e1000_i210:
719 	case e1000_i211:
720 	default:
721 		for (; i < adapter->num_rx_queues; i++)
722 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
723 		for (; j < adapter->num_tx_queues; j++)
724 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
725 		break;
726 	}
727 }
728 
729 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
730 {
731 	struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
732 	u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
733 	u32 value = 0;
734 
735 	if (E1000_REMOVED(hw_addr))
736 		return ~value;
737 
738 	value = readl(&hw_addr[reg]);
739 
740 	/* reads should not return all F's */
741 	if (!(~value) && (!reg || !(~readl(hw_addr)))) {
742 		struct net_device *netdev = igb->netdev;
743 		hw->hw_addr = NULL;
744 		netdev_err(netdev, "PCIe link lost\n");
745 		WARN(pci_device_is_present(igb->pdev),
746 		     "igb: Failed to read reg 0x%x!\n", reg);
747 	}
748 
749 	return value;
750 }
751 
752 /**
753  *  igb_write_ivar - configure ivar for given MSI-X vector
754  *  @hw: pointer to the HW structure
755  *  @msix_vector: vector number we are allocating to a given ring
756  *  @index: row index of IVAR register to write within IVAR table
757  *  @offset: column offset of in IVAR, should be multiple of 8
758  *
759  *  This function is intended to handle the writing of the IVAR register
760  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
761  *  each containing an cause allocation for an Rx and Tx ring, and a
762  *  variable number of rows depending on the number of queues supported.
763  **/
764 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 			   int index, int offset)
766 {
767 	u32 ivar = array_rd32(E1000_IVAR0, index);
768 
769 	/* clear any bits that are currently set */
770 	ivar &= ~((u32)0xFF << offset);
771 
772 	/* write vector and valid bit */
773 	ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774 
775 	array_wr32(E1000_IVAR0, index, ivar);
776 }
777 
778 #define IGB_N0_QUEUE -1
779 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
780 {
781 	struct igb_adapter *adapter = q_vector->adapter;
782 	struct e1000_hw *hw = &adapter->hw;
783 	int rx_queue = IGB_N0_QUEUE;
784 	int tx_queue = IGB_N0_QUEUE;
785 	u32 msixbm = 0;
786 
787 	if (q_vector->rx.ring)
788 		rx_queue = q_vector->rx.ring->reg_idx;
789 	if (q_vector->tx.ring)
790 		tx_queue = q_vector->tx.ring->reg_idx;
791 
792 	switch (hw->mac.type) {
793 	case e1000_82575:
794 		/* The 82575 assigns vectors using a bitmask, which matches the
795 		 * bitmask for the EICR/EIMS/EIMC registers.  To assign one
796 		 * or more queues to a vector, we write the appropriate bits
797 		 * into the MSIXBM register for that vector.
798 		 */
799 		if (rx_queue > IGB_N0_QUEUE)
800 			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
801 		if (tx_queue > IGB_N0_QUEUE)
802 			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
803 		if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
804 			msixbm |= E1000_EIMS_OTHER;
805 		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
806 		q_vector->eims_value = msixbm;
807 		break;
808 	case e1000_82576:
809 		/* 82576 uses a table that essentially consists of 2 columns
810 		 * with 8 rows.  The ordering is column-major so we use the
811 		 * lower 3 bits as the row index, and the 4th bit as the
812 		 * column offset.
813 		 */
814 		if (rx_queue > IGB_N0_QUEUE)
815 			igb_write_ivar(hw, msix_vector,
816 				       rx_queue & 0x7,
817 				       (rx_queue & 0x8) << 1);
818 		if (tx_queue > IGB_N0_QUEUE)
819 			igb_write_ivar(hw, msix_vector,
820 				       tx_queue & 0x7,
821 				       ((tx_queue & 0x8) << 1) + 8);
822 		q_vector->eims_value = BIT(msix_vector);
823 		break;
824 	case e1000_82580:
825 	case e1000_i350:
826 	case e1000_i354:
827 	case e1000_i210:
828 	case e1000_i211:
829 		/* On 82580 and newer adapters the scheme is similar to 82576
830 		 * however instead of ordering column-major we have things
831 		 * ordered row-major.  So we traverse the table by using
832 		 * bit 0 as the column offset, and the remaining bits as the
833 		 * row index.
834 		 */
835 		if (rx_queue > IGB_N0_QUEUE)
836 			igb_write_ivar(hw, msix_vector,
837 				       rx_queue >> 1,
838 				       (rx_queue & 0x1) << 4);
839 		if (tx_queue > IGB_N0_QUEUE)
840 			igb_write_ivar(hw, msix_vector,
841 				       tx_queue >> 1,
842 				       ((tx_queue & 0x1) << 4) + 8);
843 		q_vector->eims_value = BIT(msix_vector);
844 		break;
845 	default:
846 		BUG();
847 		break;
848 	}
849 
850 	/* add q_vector eims value to global eims_enable_mask */
851 	adapter->eims_enable_mask |= q_vector->eims_value;
852 
853 	/* configure q_vector to set itr on first interrupt */
854 	q_vector->set_itr = 1;
855 }
856 
857 /**
858  *  igb_configure_msix - Configure MSI-X hardware
859  *  @adapter: board private structure to initialize
860  *
861  *  igb_configure_msix sets up the hardware to properly
862  *  generate MSI-X interrupts.
863  **/
864 static void igb_configure_msix(struct igb_adapter *adapter)
865 {
866 	u32 tmp;
867 	int i, vector = 0;
868 	struct e1000_hw *hw = &adapter->hw;
869 
870 	adapter->eims_enable_mask = 0;
871 
872 	/* set vector for other causes, i.e. link changes */
873 	switch (hw->mac.type) {
874 	case e1000_82575:
875 		tmp = rd32(E1000_CTRL_EXT);
876 		/* enable MSI-X PBA support*/
877 		tmp |= E1000_CTRL_EXT_PBA_CLR;
878 
879 		/* Auto-Mask interrupts upon ICR read. */
880 		tmp |= E1000_CTRL_EXT_EIAME;
881 		tmp |= E1000_CTRL_EXT_IRCA;
882 
883 		wr32(E1000_CTRL_EXT, tmp);
884 
885 		/* enable msix_other interrupt */
886 		array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
887 		adapter->eims_other = E1000_EIMS_OTHER;
888 
889 		break;
890 
891 	case e1000_82576:
892 	case e1000_82580:
893 	case e1000_i350:
894 	case e1000_i354:
895 	case e1000_i210:
896 	case e1000_i211:
897 		/* Turn on MSI-X capability first, or our settings
898 		 * won't stick.  And it will take days to debug.
899 		 */
900 		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
901 		     E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 		     E1000_GPIE_NSICR);
903 
904 		/* enable msix_other interrupt */
905 		adapter->eims_other = BIT(vector);
906 		tmp = (vector++ | E1000_IVAR_VALID) << 8;
907 
908 		wr32(E1000_IVAR_MISC, tmp);
909 		break;
910 	default:
911 		/* do nothing, since nothing else supports MSI-X */
912 		break;
913 	} /* switch (hw->mac.type) */
914 
915 	adapter->eims_enable_mask |= adapter->eims_other;
916 
917 	for (i = 0; i < adapter->num_q_vectors; i++)
918 		igb_assign_vector(adapter->q_vector[i], vector++);
919 
920 	wrfl();
921 }
922 
923 /**
924  *  igb_request_msix - Initialize MSI-X interrupts
925  *  @adapter: board private structure to initialize
926  *
927  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
928  *  kernel.
929  **/
930 static int igb_request_msix(struct igb_adapter *adapter)
931 {
932 	unsigned int num_q_vectors = adapter->num_q_vectors;
933 	struct net_device *netdev = adapter->netdev;
934 	int i, err = 0, vector = 0, free_vector = 0;
935 
936 	err = request_irq(adapter->msix_entries[vector].vector,
937 			  igb_msix_other, 0, netdev->name, adapter);
938 	if (err)
939 		goto err_out;
940 
941 	if (num_q_vectors > MAX_Q_VECTORS) {
942 		num_q_vectors = MAX_Q_VECTORS;
943 		dev_warn(&adapter->pdev->dev,
944 			 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
945 			 adapter->num_q_vectors, MAX_Q_VECTORS);
946 	}
947 	for (i = 0; i < num_q_vectors; i++) {
948 		struct igb_q_vector *q_vector = adapter->q_vector[i];
949 
950 		vector++;
951 
952 		q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
953 
954 		if (q_vector->rx.ring && q_vector->tx.ring)
955 			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
956 				q_vector->rx.ring->queue_index);
957 		else if (q_vector->tx.ring)
958 			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
959 				q_vector->tx.ring->queue_index);
960 		else if (q_vector->rx.ring)
961 			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
962 				q_vector->rx.ring->queue_index);
963 		else
964 			sprintf(q_vector->name, "%s-unused", netdev->name);
965 
966 		err = request_irq(adapter->msix_entries[vector].vector,
967 				  igb_msix_ring, 0, q_vector->name,
968 				  q_vector);
969 		if (err)
970 			goto err_free;
971 	}
972 
973 	igb_configure_msix(adapter);
974 	return 0;
975 
976 err_free:
977 	/* free already assigned IRQs */
978 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
979 
980 	vector--;
981 	for (i = 0; i < vector; i++) {
982 		free_irq(adapter->msix_entries[free_vector++].vector,
983 			 adapter->q_vector[i]);
984 	}
985 err_out:
986 	return err;
987 }
988 
989 /**
990  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
991  *  @adapter: board private structure to initialize
992  *  @v_idx: Index of vector to be freed
993  *
994  *  This function frees the memory allocated to the q_vector.
995  **/
996 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
997 {
998 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
999 
1000 	adapter->q_vector[v_idx] = NULL;
1001 
1002 	/* igb_get_stats64() might access the rings on this vector,
1003 	 * we must wait a grace period before freeing it.
1004 	 */
1005 	if (q_vector)
1006 		kfree_rcu(q_vector, rcu);
1007 }
1008 
1009 /**
1010  *  igb_reset_q_vector - Reset config for interrupt vector
1011  *  @adapter: board private structure to initialize
1012  *  @v_idx: Index of vector to be reset
1013  *
1014  *  If NAPI is enabled it will delete any references to the
1015  *  NAPI struct. This is preparation for igb_free_q_vector.
1016  **/
1017 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1018 {
1019 	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1020 
1021 	/* Coming from igb_set_interrupt_capability, the vectors are not yet
1022 	 * allocated. So, q_vector is NULL so we should stop here.
1023 	 */
1024 	if (!q_vector)
1025 		return;
1026 
1027 	if (q_vector->tx.ring)
1028 		adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1029 
1030 	if (q_vector->rx.ring)
1031 		adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1032 
1033 	netif_napi_del(&q_vector->napi);
1034 
1035 }
1036 
1037 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1038 {
1039 	int v_idx = adapter->num_q_vectors;
1040 
1041 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
1042 		pci_disable_msix(adapter->pdev);
1043 	else if (adapter->flags & IGB_FLAG_HAS_MSI)
1044 		pci_disable_msi(adapter->pdev);
1045 
1046 	while (v_idx--)
1047 		igb_reset_q_vector(adapter, v_idx);
1048 }
1049 
1050 /**
1051  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1052  *  @adapter: board private structure to initialize
1053  *
1054  *  This function frees the memory allocated to the q_vectors.  In addition if
1055  *  NAPI is enabled it will delete any references to the NAPI struct prior
1056  *  to freeing the q_vector.
1057  **/
1058 static void igb_free_q_vectors(struct igb_adapter *adapter)
1059 {
1060 	int v_idx = adapter->num_q_vectors;
1061 
1062 	adapter->num_tx_queues = 0;
1063 	adapter->num_rx_queues = 0;
1064 	adapter->num_q_vectors = 0;
1065 
1066 	while (v_idx--) {
1067 		igb_reset_q_vector(adapter, v_idx);
1068 		igb_free_q_vector(adapter, v_idx);
1069 	}
1070 }
1071 
1072 /**
1073  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1074  *  @adapter: board private structure to initialize
1075  *
1076  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1077  *  MSI-X interrupts allocated.
1078  */
1079 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1080 {
1081 	igb_free_q_vectors(adapter);
1082 	igb_reset_interrupt_capability(adapter);
1083 }
1084 
1085 /**
1086  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1087  *  @adapter: board private structure to initialize
1088  *  @msix: boolean value of MSIX capability
1089  *
1090  *  Attempt to configure interrupts using the best available
1091  *  capabilities of the hardware and kernel.
1092  **/
1093 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1094 {
1095 	int err;
1096 	int numvecs, i;
1097 
1098 	if (!msix)
1099 		goto msi_only;
1100 	adapter->flags |= IGB_FLAG_HAS_MSIX;
1101 
1102 	/* Number of supported queues. */
1103 	adapter->num_rx_queues = adapter->rss_queues;
1104 	if (adapter->vfs_allocated_count)
1105 		adapter->num_tx_queues = 1;
1106 	else
1107 		adapter->num_tx_queues = adapter->rss_queues;
1108 
1109 	/* start with one vector for every Rx queue */
1110 	numvecs = adapter->num_rx_queues;
1111 
1112 	/* if Tx handler is separate add 1 for every Tx queue */
1113 	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1114 		numvecs += adapter->num_tx_queues;
1115 
1116 	/* store the number of vectors reserved for queues */
1117 	adapter->num_q_vectors = numvecs;
1118 
1119 	/* add 1 vector for link status interrupts */
1120 	numvecs++;
1121 	for (i = 0; i < numvecs; i++)
1122 		adapter->msix_entries[i].entry = i;
1123 
1124 	err = pci_enable_msix_range(adapter->pdev,
1125 				    adapter->msix_entries,
1126 				    numvecs,
1127 				    numvecs);
1128 	if (err > 0)
1129 		return;
1130 
1131 	igb_reset_interrupt_capability(adapter);
1132 
1133 	/* If we can't do MSI-X, try MSI */
1134 msi_only:
1135 	adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1136 #ifdef CONFIG_PCI_IOV
1137 	/* disable SR-IOV for non MSI-X configurations */
1138 	if (adapter->vf_data) {
1139 		struct e1000_hw *hw = &adapter->hw;
1140 		/* disable iov and allow time for transactions to clear */
1141 		pci_disable_sriov(adapter->pdev);
1142 		msleep(500);
1143 
1144 		kfree(adapter->vf_mac_list);
1145 		adapter->vf_mac_list = NULL;
1146 		kfree(adapter->vf_data);
1147 		adapter->vf_data = NULL;
1148 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1149 		wrfl();
1150 		msleep(100);
1151 		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1152 	}
1153 #endif
1154 	adapter->vfs_allocated_count = 0;
1155 	adapter->rss_queues = 1;
1156 	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1157 	adapter->num_rx_queues = 1;
1158 	adapter->num_tx_queues = 1;
1159 	adapter->num_q_vectors = 1;
1160 	if (!pci_enable_msi(adapter->pdev))
1161 		adapter->flags |= IGB_FLAG_HAS_MSI;
1162 }
1163 
1164 static void igb_add_ring(struct igb_ring *ring,
1165 			 struct igb_ring_container *head)
1166 {
1167 	head->ring = ring;
1168 	head->count++;
1169 }
1170 
1171 /**
1172  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1173  *  @adapter: board private structure to initialize
1174  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1175  *  @v_idx: index of vector in adapter struct
1176  *  @txr_count: total number of Tx rings to allocate
1177  *  @txr_idx: index of first Tx ring to allocate
1178  *  @rxr_count: total number of Rx rings to allocate
1179  *  @rxr_idx: index of first Rx ring to allocate
1180  *
1181  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1182  **/
1183 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1184 			      int v_count, int v_idx,
1185 			      int txr_count, int txr_idx,
1186 			      int rxr_count, int rxr_idx)
1187 {
1188 	struct igb_q_vector *q_vector;
1189 	struct igb_ring *ring;
1190 	int ring_count;
1191 	size_t size;
1192 
1193 	/* igb only supports 1 Tx and/or 1 Rx queue per vector */
1194 	if (txr_count > 1 || rxr_count > 1)
1195 		return -ENOMEM;
1196 
1197 	ring_count = txr_count + rxr_count;
1198 	size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count));
1199 
1200 	/* allocate q_vector and rings */
1201 	q_vector = adapter->q_vector[v_idx];
1202 	if (!q_vector) {
1203 		q_vector = kzalloc(size, GFP_KERNEL);
1204 	} else if (size > ksize(q_vector)) {
1205 		struct igb_q_vector *new_q_vector;
1206 
1207 		new_q_vector = kzalloc(size, GFP_KERNEL);
1208 		if (new_q_vector)
1209 			kfree_rcu(q_vector, rcu);
1210 		q_vector = new_q_vector;
1211 	} else {
1212 		memset(q_vector, 0, size);
1213 	}
1214 	if (!q_vector)
1215 		return -ENOMEM;
1216 
1217 	/* initialize NAPI */
1218 	netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll);
1219 
1220 	/* tie q_vector and adapter together */
1221 	adapter->q_vector[v_idx] = q_vector;
1222 	q_vector->adapter = adapter;
1223 
1224 	/* initialize work limits */
1225 	q_vector->tx.work_limit = adapter->tx_work_limit;
1226 
1227 	/* initialize ITR configuration */
1228 	q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1229 	q_vector->itr_val = IGB_START_ITR;
1230 
1231 	/* initialize pointer to rings */
1232 	ring = q_vector->ring;
1233 
1234 	/* intialize ITR */
1235 	if (rxr_count) {
1236 		/* rx or rx/tx vector */
1237 		if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1238 			q_vector->itr_val = adapter->rx_itr_setting;
1239 	} else {
1240 		/* tx only vector */
1241 		if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1242 			q_vector->itr_val = adapter->tx_itr_setting;
1243 	}
1244 
1245 	if (txr_count) {
1246 		/* assign generic ring traits */
1247 		ring->dev = &adapter->pdev->dev;
1248 		ring->netdev = adapter->netdev;
1249 
1250 		/* configure backlink on ring */
1251 		ring->q_vector = q_vector;
1252 
1253 		/* update q_vector Tx values */
1254 		igb_add_ring(ring, &q_vector->tx);
1255 
1256 		/* For 82575, context index must be unique per ring. */
1257 		if (adapter->hw.mac.type == e1000_82575)
1258 			set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1259 
1260 		/* apply Tx specific ring traits */
1261 		ring->count = adapter->tx_ring_count;
1262 		ring->queue_index = txr_idx;
1263 
1264 		ring->cbs_enable = false;
1265 		ring->idleslope = 0;
1266 		ring->sendslope = 0;
1267 		ring->hicredit = 0;
1268 		ring->locredit = 0;
1269 
1270 		u64_stats_init(&ring->tx_syncp);
1271 		u64_stats_init(&ring->tx_syncp2);
1272 
1273 		/* assign ring to adapter */
1274 		adapter->tx_ring[txr_idx] = ring;
1275 
1276 		/* push pointer to next ring */
1277 		ring++;
1278 	}
1279 
1280 	if (rxr_count) {
1281 		/* assign generic ring traits */
1282 		ring->dev = &adapter->pdev->dev;
1283 		ring->netdev = adapter->netdev;
1284 
1285 		/* configure backlink on ring */
1286 		ring->q_vector = q_vector;
1287 
1288 		/* update q_vector Rx values */
1289 		igb_add_ring(ring, &q_vector->rx);
1290 
1291 		/* set flag indicating ring supports SCTP checksum offload */
1292 		if (adapter->hw.mac.type >= e1000_82576)
1293 			set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1294 
1295 		/* On i350, i354, i210, and i211, loopback VLAN packets
1296 		 * have the tag byte-swapped.
1297 		 */
1298 		if (adapter->hw.mac.type >= e1000_i350)
1299 			set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1300 
1301 		/* apply Rx specific ring traits */
1302 		ring->count = adapter->rx_ring_count;
1303 		ring->queue_index = rxr_idx;
1304 
1305 		u64_stats_init(&ring->rx_syncp);
1306 
1307 		/* assign ring to adapter */
1308 		adapter->rx_ring[rxr_idx] = ring;
1309 	}
1310 
1311 	return 0;
1312 }
1313 
1314 
1315 /**
1316  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1317  *  @adapter: board private structure to initialize
1318  *
1319  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1320  *  return -ENOMEM.
1321  **/
1322 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1323 {
1324 	int q_vectors = adapter->num_q_vectors;
1325 	int rxr_remaining = adapter->num_rx_queues;
1326 	int txr_remaining = adapter->num_tx_queues;
1327 	int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1328 	int err;
1329 
1330 	if (q_vectors >= (rxr_remaining + txr_remaining)) {
1331 		for (; rxr_remaining; v_idx++) {
1332 			err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1333 						 0, 0, 1, rxr_idx);
1334 
1335 			if (err)
1336 				goto err_out;
1337 
1338 			/* update counts and index */
1339 			rxr_remaining--;
1340 			rxr_idx++;
1341 		}
1342 	}
1343 
1344 	for (; v_idx < q_vectors; v_idx++) {
1345 		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1346 		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347 
1348 		err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1349 					 tqpv, txr_idx, rqpv, rxr_idx);
1350 
1351 		if (err)
1352 			goto err_out;
1353 
1354 		/* update counts and index */
1355 		rxr_remaining -= rqpv;
1356 		txr_remaining -= tqpv;
1357 		rxr_idx++;
1358 		txr_idx++;
1359 	}
1360 
1361 	return 0;
1362 
1363 err_out:
1364 	adapter->num_tx_queues = 0;
1365 	adapter->num_rx_queues = 0;
1366 	adapter->num_q_vectors = 0;
1367 
1368 	while (v_idx--)
1369 		igb_free_q_vector(adapter, v_idx);
1370 
1371 	return -ENOMEM;
1372 }
1373 
1374 /**
1375  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1376  *  @adapter: board private structure to initialize
1377  *  @msix: boolean value of MSIX capability
1378  *
1379  *  This function initializes the interrupts and allocates all of the queues.
1380  **/
1381 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1382 {
1383 	struct pci_dev *pdev = adapter->pdev;
1384 	int err;
1385 
1386 	igb_set_interrupt_capability(adapter, msix);
1387 
1388 	err = igb_alloc_q_vectors(adapter);
1389 	if (err) {
1390 		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1391 		goto err_alloc_q_vectors;
1392 	}
1393 
1394 	igb_cache_ring_register(adapter);
1395 
1396 	return 0;
1397 
1398 err_alloc_q_vectors:
1399 	igb_reset_interrupt_capability(adapter);
1400 	return err;
1401 }
1402 
1403 /**
1404  *  igb_request_irq - initialize interrupts
1405  *  @adapter: board private structure to initialize
1406  *
1407  *  Attempts to configure interrupts using the best available
1408  *  capabilities of the hardware and kernel.
1409  **/
1410 static int igb_request_irq(struct igb_adapter *adapter)
1411 {
1412 	struct net_device *netdev = adapter->netdev;
1413 	struct pci_dev *pdev = adapter->pdev;
1414 	int err = 0;
1415 
1416 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1417 		err = igb_request_msix(adapter);
1418 		if (!err)
1419 			goto request_done;
1420 		/* fall back to MSI */
1421 		igb_free_all_tx_resources(adapter);
1422 		igb_free_all_rx_resources(adapter);
1423 
1424 		igb_clear_interrupt_scheme(adapter);
1425 		err = igb_init_interrupt_scheme(adapter, false);
1426 		if (err)
1427 			goto request_done;
1428 
1429 		igb_setup_all_tx_resources(adapter);
1430 		igb_setup_all_rx_resources(adapter);
1431 		igb_configure(adapter);
1432 	}
1433 
1434 	igb_assign_vector(adapter->q_vector[0], 0);
1435 
1436 	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1437 		err = request_irq(pdev->irq, igb_intr_msi, 0,
1438 				  netdev->name, adapter);
1439 		if (!err)
1440 			goto request_done;
1441 
1442 		/* fall back to legacy interrupts */
1443 		igb_reset_interrupt_capability(adapter);
1444 		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1445 	}
1446 
1447 	err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1448 			  netdev->name, adapter);
1449 
1450 	if (err)
1451 		dev_err(&pdev->dev, "Error %d getting interrupt\n",
1452 			err);
1453 
1454 request_done:
1455 	return err;
1456 }
1457 
1458 static void igb_free_irq(struct igb_adapter *adapter)
1459 {
1460 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1461 		int vector = 0, i;
1462 
1463 		free_irq(adapter->msix_entries[vector++].vector, adapter);
1464 
1465 		for (i = 0; i < adapter->num_q_vectors; i++)
1466 			free_irq(adapter->msix_entries[vector++].vector,
1467 				 adapter->q_vector[i]);
1468 	} else {
1469 		free_irq(adapter->pdev->irq, adapter);
1470 	}
1471 }
1472 
1473 /**
1474  *  igb_irq_disable - Mask off interrupt generation on the NIC
1475  *  @adapter: board private structure
1476  **/
1477 static void igb_irq_disable(struct igb_adapter *adapter)
1478 {
1479 	struct e1000_hw *hw = &adapter->hw;
1480 
1481 	/* we need to be careful when disabling interrupts.  The VFs are also
1482 	 * mapped into these registers and so clearing the bits can cause
1483 	 * issues on the VF drivers so we only need to clear what we set
1484 	 */
1485 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1486 		u32 regval = rd32(E1000_EIAM);
1487 
1488 		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1489 		wr32(E1000_EIMC, adapter->eims_enable_mask);
1490 		regval = rd32(E1000_EIAC);
1491 		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1492 	}
1493 
1494 	wr32(E1000_IAM, 0);
1495 	wr32(E1000_IMC, ~0);
1496 	wrfl();
1497 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1498 		int i;
1499 
1500 		for (i = 0; i < adapter->num_q_vectors; i++)
1501 			synchronize_irq(adapter->msix_entries[i].vector);
1502 	} else {
1503 		synchronize_irq(adapter->pdev->irq);
1504 	}
1505 }
1506 
1507 /**
1508  *  igb_irq_enable - Enable default interrupt generation settings
1509  *  @adapter: board private structure
1510  **/
1511 static void igb_irq_enable(struct igb_adapter *adapter)
1512 {
1513 	struct e1000_hw *hw = &adapter->hw;
1514 
1515 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1516 		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1517 		u32 regval = rd32(E1000_EIAC);
1518 
1519 		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1520 		regval = rd32(E1000_EIAM);
1521 		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1522 		wr32(E1000_EIMS, adapter->eims_enable_mask);
1523 		if (adapter->vfs_allocated_count) {
1524 			wr32(E1000_MBVFIMR, 0xFF);
1525 			ims |= E1000_IMS_VMMB;
1526 		}
1527 		wr32(E1000_IMS, ims);
1528 	} else {
1529 		wr32(E1000_IMS, IMS_ENABLE_MASK |
1530 				E1000_IMS_DRSTA);
1531 		wr32(E1000_IAM, IMS_ENABLE_MASK |
1532 				E1000_IMS_DRSTA);
1533 	}
1534 }
1535 
1536 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1537 {
1538 	struct e1000_hw *hw = &adapter->hw;
1539 	u16 pf_id = adapter->vfs_allocated_count;
1540 	u16 vid = adapter->hw.mng_cookie.vlan_id;
1541 	u16 old_vid = adapter->mng_vlan_id;
1542 
1543 	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1544 		/* add VID to filter table */
1545 		igb_vfta_set(hw, vid, pf_id, true, true);
1546 		adapter->mng_vlan_id = vid;
1547 	} else {
1548 		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1549 	}
1550 
1551 	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1552 	    (vid != old_vid) &&
1553 	    !test_bit(old_vid, adapter->active_vlans)) {
1554 		/* remove VID from filter table */
1555 		igb_vfta_set(hw, vid, pf_id, false, true);
1556 	}
1557 }
1558 
1559 /**
1560  *  igb_release_hw_control - release control of the h/w to f/w
1561  *  @adapter: address of board private structure
1562  *
1563  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1564  *  For ASF and Pass Through versions of f/w this means that the
1565  *  driver is no longer loaded.
1566  **/
1567 static void igb_release_hw_control(struct igb_adapter *adapter)
1568 {
1569 	struct e1000_hw *hw = &adapter->hw;
1570 	u32 ctrl_ext;
1571 
1572 	/* Let firmware take over control of h/w */
1573 	ctrl_ext = rd32(E1000_CTRL_EXT);
1574 	wr32(E1000_CTRL_EXT,
1575 			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1576 }
1577 
1578 /**
1579  *  igb_get_hw_control - get control of the h/w from f/w
1580  *  @adapter: address of board private structure
1581  *
1582  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1583  *  For ASF and Pass Through versions of f/w this means that
1584  *  the driver is loaded.
1585  **/
1586 static void igb_get_hw_control(struct igb_adapter *adapter)
1587 {
1588 	struct e1000_hw *hw = &adapter->hw;
1589 	u32 ctrl_ext;
1590 
1591 	/* Let firmware know the driver has taken over */
1592 	ctrl_ext = rd32(E1000_CTRL_EXT);
1593 	wr32(E1000_CTRL_EXT,
1594 			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1595 }
1596 
1597 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1598 {
1599 	struct net_device *netdev = adapter->netdev;
1600 	struct e1000_hw *hw = &adapter->hw;
1601 
1602 	WARN_ON(hw->mac.type != e1000_i210);
1603 
1604 	if (enable)
1605 		adapter->flags |= IGB_FLAG_FQTSS;
1606 	else
1607 		adapter->flags &= ~IGB_FLAG_FQTSS;
1608 
1609 	if (netif_running(netdev))
1610 		schedule_work(&adapter->reset_task);
1611 }
1612 
1613 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1614 {
1615 	return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1616 }
1617 
1618 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1619 				   enum tx_queue_prio prio)
1620 {
1621 	u32 val;
1622 
1623 	WARN_ON(hw->mac.type != e1000_i210);
1624 	WARN_ON(queue < 0 || queue > 4);
1625 
1626 	val = rd32(E1000_I210_TXDCTL(queue));
1627 
1628 	if (prio == TX_QUEUE_PRIO_HIGH)
1629 		val |= E1000_TXDCTL_PRIORITY;
1630 	else
1631 		val &= ~E1000_TXDCTL_PRIORITY;
1632 
1633 	wr32(E1000_I210_TXDCTL(queue), val);
1634 }
1635 
1636 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1637 {
1638 	u32 val;
1639 
1640 	WARN_ON(hw->mac.type != e1000_i210);
1641 	WARN_ON(queue < 0 || queue > 1);
1642 
1643 	val = rd32(E1000_I210_TQAVCC(queue));
1644 
1645 	if (mode == QUEUE_MODE_STREAM_RESERVATION)
1646 		val |= E1000_TQAVCC_QUEUEMODE;
1647 	else
1648 		val &= ~E1000_TQAVCC_QUEUEMODE;
1649 
1650 	wr32(E1000_I210_TQAVCC(queue), val);
1651 }
1652 
1653 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1654 {
1655 	int i;
1656 
1657 	for (i = 0; i < adapter->num_tx_queues; i++) {
1658 		if (adapter->tx_ring[i]->cbs_enable)
1659 			return true;
1660 	}
1661 
1662 	return false;
1663 }
1664 
1665 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1666 {
1667 	int i;
1668 
1669 	for (i = 0; i < adapter->num_tx_queues; i++) {
1670 		if (adapter->tx_ring[i]->launchtime_enable)
1671 			return true;
1672 	}
1673 
1674 	return false;
1675 }
1676 
1677 /**
1678  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1679  *  @adapter: pointer to adapter struct
1680  *  @queue: queue number
1681  *
1682  *  Configure CBS and Launchtime for a given hardware queue.
1683  *  Parameters are retrieved from the correct Tx ring, so
1684  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1685  *  for setting those correctly prior to this function being called.
1686  **/
1687 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1688 {
1689 	struct net_device *netdev = adapter->netdev;
1690 	struct e1000_hw *hw = &adapter->hw;
1691 	struct igb_ring *ring;
1692 	u32 tqavcc, tqavctrl;
1693 	u16 value;
1694 
1695 	WARN_ON(hw->mac.type != e1000_i210);
1696 	WARN_ON(queue < 0 || queue > 1);
1697 	ring = adapter->tx_ring[queue];
1698 
1699 	/* If any of the Qav features is enabled, configure queues as SR and
1700 	 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1701 	 * as SP.
1702 	 */
1703 	if (ring->cbs_enable || ring->launchtime_enable) {
1704 		set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1705 		set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1706 	} else {
1707 		set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1708 		set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1709 	}
1710 
1711 	/* If CBS is enabled, set DataTranARB and config its parameters. */
1712 	if (ring->cbs_enable || queue == 0) {
1713 		/* i210 does not allow the queue 0 to be in the Strict
1714 		 * Priority mode while the Qav mode is enabled, so,
1715 		 * instead of disabling strict priority mode, we give
1716 		 * queue 0 the maximum of credits possible.
1717 		 *
1718 		 * See section 8.12.19 of the i210 datasheet, "Note:
1719 		 * Queue0 QueueMode must be set to 1b when
1720 		 * TransmitMode is set to Qav."
1721 		 */
1722 		if (queue == 0 && !ring->cbs_enable) {
1723 			/* max "linkspeed" idleslope in kbps */
1724 			ring->idleslope = 1000000;
1725 			ring->hicredit = ETH_FRAME_LEN;
1726 		}
1727 
1728 		/* Always set data transfer arbitration to credit-based
1729 		 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1730 		 * the queues.
1731 		 */
1732 		tqavctrl = rd32(E1000_I210_TQAVCTRL);
1733 		tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1734 		wr32(E1000_I210_TQAVCTRL, tqavctrl);
1735 
1736 		/* According to i210 datasheet section 7.2.7.7, we should set
1737 		 * the 'idleSlope' field from TQAVCC register following the
1738 		 * equation:
1739 		 *
1740 		 * For 100 Mbps link speed:
1741 		 *
1742 		 *     value = BW * 0x7735 * 0.2                          (E1)
1743 		 *
1744 		 * For 1000Mbps link speed:
1745 		 *
1746 		 *     value = BW * 0x7735 * 2                            (E2)
1747 		 *
1748 		 * E1 and E2 can be merged into one equation as shown below.
1749 		 * Note that 'link-speed' is in Mbps.
1750 		 *
1751 		 *     value = BW * 0x7735 * 2 * link-speed
1752 		 *                           --------------               (E3)
1753 		 *                                1000
1754 		 *
1755 		 * 'BW' is the percentage bandwidth out of full link speed
1756 		 * which can be found with the following equation. Note that
1757 		 * idleSlope here is the parameter from this function which
1758 		 * is in kbps.
1759 		 *
1760 		 *     BW =     idleSlope
1761 		 *          -----------------                             (E4)
1762 		 *          link-speed * 1000
1763 		 *
1764 		 * That said, we can come up with a generic equation to
1765 		 * calculate the value we should set it TQAVCC register by
1766 		 * replacing 'BW' in E3 by E4. The resulting equation is:
1767 		 *
1768 		 * value =     idleSlope     * 0x7735 * 2 * link-speed
1769 		 *         -----------------            --------------    (E5)
1770 		 *         link-speed * 1000                 1000
1771 		 *
1772 		 * 'link-speed' is present in both sides of the fraction so
1773 		 * it is canceled out. The final equation is the following:
1774 		 *
1775 		 *     value = idleSlope * 61034
1776 		 *             -----------------                          (E6)
1777 		 *                  1000000
1778 		 *
1779 		 * NOTE: For i210, given the above, we can see that idleslope
1780 		 *       is represented in 16.38431 kbps units by the value at
1781 		 *       the TQAVCC register (1Gbps / 61034), which reduces
1782 		 *       the granularity for idleslope increments.
1783 		 *       For instance, if you want to configure a 2576kbps
1784 		 *       idleslope, the value to be written on the register
1785 		 *       would have to be 157.23. If rounded down, you end
1786 		 *       up with less bandwidth available than originally
1787 		 *       required (~2572 kbps). If rounded up, you end up
1788 		 *       with a higher bandwidth (~2589 kbps). Below the
1789 		 *       approach we take is to always round up the
1790 		 *       calculated value, so the resulting bandwidth might
1791 		 *       be slightly higher for some configurations.
1792 		 */
1793 		value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1794 
1795 		tqavcc = rd32(E1000_I210_TQAVCC(queue));
1796 		tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1797 		tqavcc |= value;
1798 		wr32(E1000_I210_TQAVCC(queue), tqavcc);
1799 
1800 		wr32(E1000_I210_TQAVHC(queue),
1801 		     0x80000000 + ring->hicredit * 0x7735);
1802 	} else {
1803 
1804 		/* Set idleSlope to zero. */
1805 		tqavcc = rd32(E1000_I210_TQAVCC(queue));
1806 		tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1807 		wr32(E1000_I210_TQAVCC(queue), tqavcc);
1808 
1809 		/* Set hiCredit to zero. */
1810 		wr32(E1000_I210_TQAVHC(queue), 0);
1811 
1812 		/* If CBS is not enabled for any queues anymore, then return to
1813 		 * the default state of Data Transmission Arbitration on
1814 		 * TQAVCTRL.
1815 		 */
1816 		if (!is_any_cbs_enabled(adapter)) {
1817 			tqavctrl = rd32(E1000_I210_TQAVCTRL);
1818 			tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1819 			wr32(E1000_I210_TQAVCTRL, tqavctrl);
1820 		}
1821 	}
1822 
1823 	/* If LaunchTime is enabled, set DataTranTIM. */
1824 	if (ring->launchtime_enable) {
1825 		/* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1826 		 * for any of the SR queues, and configure fetchtime delta.
1827 		 * XXX NOTE:
1828 		 *     - LaunchTime will be enabled for all SR queues.
1829 		 *     - A fixed offset can be added relative to the launch
1830 		 *       time of all packets if configured at reg LAUNCH_OS0.
1831 		 *       We are keeping it as 0 for now (default value).
1832 		 */
1833 		tqavctrl = rd32(E1000_I210_TQAVCTRL);
1834 		tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1835 		       E1000_TQAVCTRL_FETCHTIME_DELTA;
1836 		wr32(E1000_I210_TQAVCTRL, tqavctrl);
1837 	} else {
1838 		/* If Launchtime is not enabled for any SR queues anymore,
1839 		 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1840 		 * effectively disabling Launchtime.
1841 		 */
1842 		if (!is_any_txtime_enabled(adapter)) {
1843 			tqavctrl = rd32(E1000_I210_TQAVCTRL);
1844 			tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1845 			tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1846 			wr32(E1000_I210_TQAVCTRL, tqavctrl);
1847 		}
1848 	}
1849 
1850 	/* XXX: In i210 controller the sendSlope and loCredit parameters from
1851 	 * CBS are not configurable by software so we don't do any 'controller
1852 	 * configuration' in respect to these parameters.
1853 	 */
1854 
1855 	netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1856 		   ring->cbs_enable ? "enabled" : "disabled",
1857 		   ring->launchtime_enable ? "enabled" : "disabled",
1858 		   queue,
1859 		   ring->idleslope, ring->sendslope,
1860 		   ring->hicredit, ring->locredit);
1861 }
1862 
1863 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1864 				  bool enable)
1865 {
1866 	struct igb_ring *ring;
1867 
1868 	if (queue < 0 || queue > adapter->num_tx_queues)
1869 		return -EINVAL;
1870 
1871 	ring = adapter->tx_ring[queue];
1872 	ring->launchtime_enable = enable;
1873 
1874 	return 0;
1875 }
1876 
1877 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1878 			       bool enable, int idleslope, int sendslope,
1879 			       int hicredit, int locredit)
1880 {
1881 	struct igb_ring *ring;
1882 
1883 	if (queue < 0 || queue > adapter->num_tx_queues)
1884 		return -EINVAL;
1885 
1886 	ring = adapter->tx_ring[queue];
1887 
1888 	ring->cbs_enable = enable;
1889 	ring->idleslope = idleslope;
1890 	ring->sendslope = sendslope;
1891 	ring->hicredit = hicredit;
1892 	ring->locredit = locredit;
1893 
1894 	return 0;
1895 }
1896 
1897 /**
1898  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1899  *  @adapter: pointer to adapter struct
1900  *
1901  *  Configure TQAVCTRL register switching the controller's Tx mode
1902  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1903  *  a call to igb_config_tx_modes() per queue so any previously saved
1904  *  Tx parameters are applied.
1905  **/
1906 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1907 {
1908 	struct net_device *netdev = adapter->netdev;
1909 	struct e1000_hw *hw = &adapter->hw;
1910 	u32 val;
1911 
1912 	/* Only i210 controller supports changing the transmission mode. */
1913 	if (hw->mac.type != e1000_i210)
1914 		return;
1915 
1916 	if (is_fqtss_enabled(adapter)) {
1917 		int i, max_queue;
1918 
1919 		/* Configure TQAVCTRL register: set transmit mode to 'Qav',
1920 		 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1921 		 * so SP queues wait for SR ones.
1922 		 */
1923 		val = rd32(E1000_I210_TQAVCTRL);
1924 		val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1925 		val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1926 		wr32(E1000_I210_TQAVCTRL, val);
1927 
1928 		/* Configure Tx and Rx packet buffers sizes as described in
1929 		 * i210 datasheet section 7.2.7.7.
1930 		 */
1931 		val = rd32(E1000_TXPBS);
1932 		val &= ~I210_TXPBSIZE_MASK;
1933 		val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1934 			I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1935 		wr32(E1000_TXPBS, val);
1936 
1937 		val = rd32(E1000_RXPBS);
1938 		val &= ~I210_RXPBSIZE_MASK;
1939 		val |= I210_RXPBSIZE_PB_30KB;
1940 		wr32(E1000_RXPBS, val);
1941 
1942 		/* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1943 		 * register should not exceed the buffer size programmed in
1944 		 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1945 		 * so according to the datasheet we should set MAX_TPKT_SIZE to
1946 		 * 4kB / 64.
1947 		 *
1948 		 * However, when we do so, no frame from queue 2 and 3 are
1949 		 * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1950 		 * or _equal_ to the buffer size programmed in TXPBS. For this
1951 		 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1952 		 */
1953 		val = (4096 - 1) / 64;
1954 		wr32(E1000_I210_DTXMXPKTSZ, val);
1955 
1956 		/* Since FQTSS mode is enabled, apply any CBS configuration
1957 		 * previously set. If no previous CBS configuration has been
1958 		 * done, then the initial configuration is applied, which means
1959 		 * CBS is disabled.
1960 		 */
1961 		max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1962 			    adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1963 
1964 		for (i = 0; i < max_queue; i++) {
1965 			igb_config_tx_modes(adapter, i);
1966 		}
1967 	} else {
1968 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1969 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1970 		wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1971 
1972 		val = rd32(E1000_I210_TQAVCTRL);
1973 		/* According to Section 8.12.21, the other flags we've set when
1974 		 * enabling FQTSS are not relevant when disabling FQTSS so we
1975 		 * don't set they here.
1976 		 */
1977 		val &= ~E1000_TQAVCTRL_XMIT_MODE;
1978 		wr32(E1000_I210_TQAVCTRL, val);
1979 	}
1980 
1981 	netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1982 		   "enabled" : "disabled");
1983 }
1984 
1985 /**
1986  *  igb_configure - configure the hardware for RX and TX
1987  *  @adapter: private board structure
1988  **/
1989 static void igb_configure(struct igb_adapter *adapter)
1990 {
1991 	struct net_device *netdev = adapter->netdev;
1992 	int i;
1993 
1994 	igb_get_hw_control(adapter);
1995 	igb_set_rx_mode(netdev);
1996 	igb_setup_tx_mode(adapter);
1997 
1998 	igb_restore_vlan(adapter);
1999 
2000 	igb_setup_tctl(adapter);
2001 	igb_setup_mrqc(adapter);
2002 	igb_setup_rctl(adapter);
2003 
2004 	igb_nfc_filter_restore(adapter);
2005 	igb_configure_tx(adapter);
2006 	igb_configure_rx(adapter);
2007 
2008 	igb_rx_fifo_flush_82575(&adapter->hw);
2009 
2010 	/* call igb_desc_unused which always leaves
2011 	 * at least 1 descriptor unused to make sure
2012 	 * next_to_use != next_to_clean
2013 	 */
2014 	for (i = 0; i < adapter->num_rx_queues; i++) {
2015 		struct igb_ring *ring = adapter->rx_ring[i];
2016 		igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2017 	}
2018 }
2019 
2020 /**
2021  *  igb_power_up_link - Power up the phy/serdes link
2022  *  @adapter: address of board private structure
2023  **/
2024 void igb_power_up_link(struct igb_adapter *adapter)
2025 {
2026 	igb_reset_phy(&adapter->hw);
2027 
2028 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
2029 		igb_power_up_phy_copper(&adapter->hw);
2030 	else
2031 		igb_power_up_serdes_link_82575(&adapter->hw);
2032 
2033 	igb_setup_link(&adapter->hw);
2034 }
2035 
2036 /**
2037  *  igb_power_down_link - Power down the phy/serdes link
2038  *  @adapter: address of board private structure
2039  */
2040 static void igb_power_down_link(struct igb_adapter *adapter)
2041 {
2042 	if (adapter->hw.phy.media_type == e1000_media_type_copper)
2043 		igb_power_down_phy_copper_82575(&adapter->hw);
2044 	else
2045 		igb_shutdown_serdes_link_82575(&adapter->hw);
2046 }
2047 
2048 /**
2049  * igb_check_swap_media -  Detect and switch function for Media Auto Sense
2050  * @adapter: address of the board private structure
2051  **/
2052 static void igb_check_swap_media(struct igb_adapter *adapter)
2053 {
2054 	struct e1000_hw *hw = &adapter->hw;
2055 	u32 ctrl_ext, connsw;
2056 	bool swap_now = false;
2057 
2058 	ctrl_ext = rd32(E1000_CTRL_EXT);
2059 	connsw = rd32(E1000_CONNSW);
2060 
2061 	/* need to live swap if current media is copper and we have fiber/serdes
2062 	 * to go to.
2063 	 */
2064 
2065 	if ((hw->phy.media_type == e1000_media_type_copper) &&
2066 	    (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2067 		swap_now = true;
2068 	} else if ((hw->phy.media_type != e1000_media_type_copper) &&
2069 		   !(connsw & E1000_CONNSW_SERDESD)) {
2070 		/* copper signal takes time to appear */
2071 		if (adapter->copper_tries < 4) {
2072 			adapter->copper_tries++;
2073 			connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2074 			wr32(E1000_CONNSW, connsw);
2075 			return;
2076 		} else {
2077 			adapter->copper_tries = 0;
2078 			if ((connsw & E1000_CONNSW_PHYSD) &&
2079 			    (!(connsw & E1000_CONNSW_PHY_PDN))) {
2080 				swap_now = true;
2081 				connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2082 				wr32(E1000_CONNSW, connsw);
2083 			}
2084 		}
2085 	}
2086 
2087 	if (!swap_now)
2088 		return;
2089 
2090 	switch (hw->phy.media_type) {
2091 	case e1000_media_type_copper:
2092 		netdev_info(adapter->netdev,
2093 			"MAS: changing media to fiber/serdes\n");
2094 		ctrl_ext |=
2095 			E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2096 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
2097 		adapter->copper_tries = 0;
2098 		break;
2099 	case e1000_media_type_internal_serdes:
2100 	case e1000_media_type_fiber:
2101 		netdev_info(adapter->netdev,
2102 			"MAS: changing media to copper\n");
2103 		ctrl_ext &=
2104 			~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2105 		adapter->flags |= IGB_FLAG_MEDIA_RESET;
2106 		break;
2107 	default:
2108 		/* shouldn't get here during regular operation */
2109 		netdev_err(adapter->netdev,
2110 			"AMS: Invalid media type found, returning\n");
2111 		break;
2112 	}
2113 	wr32(E1000_CTRL_EXT, ctrl_ext);
2114 }
2115 
2116 /**
2117  *  igb_up - Open the interface and prepare it to handle traffic
2118  *  @adapter: board private structure
2119  **/
2120 int igb_up(struct igb_adapter *adapter)
2121 {
2122 	struct e1000_hw *hw = &adapter->hw;
2123 	int i;
2124 
2125 	/* hardware has been reset, we need to reload some things */
2126 	igb_configure(adapter);
2127 
2128 	clear_bit(__IGB_DOWN, &adapter->state);
2129 
2130 	for (i = 0; i < adapter->num_q_vectors; i++)
2131 		napi_enable(&(adapter->q_vector[i]->napi));
2132 
2133 	if (adapter->flags & IGB_FLAG_HAS_MSIX)
2134 		igb_configure_msix(adapter);
2135 	else
2136 		igb_assign_vector(adapter->q_vector[0], 0);
2137 
2138 	/* Clear any pending interrupts. */
2139 	rd32(E1000_TSICR);
2140 	rd32(E1000_ICR);
2141 	igb_irq_enable(adapter);
2142 
2143 	/* notify VFs that reset has been completed */
2144 	if (adapter->vfs_allocated_count) {
2145 		u32 reg_data = rd32(E1000_CTRL_EXT);
2146 
2147 		reg_data |= E1000_CTRL_EXT_PFRSTD;
2148 		wr32(E1000_CTRL_EXT, reg_data);
2149 	}
2150 
2151 	netif_tx_start_all_queues(adapter->netdev);
2152 
2153 	/* start the watchdog. */
2154 	hw->mac.get_link_status = 1;
2155 	schedule_work(&adapter->watchdog_task);
2156 
2157 	if ((adapter->flags & IGB_FLAG_EEE) &&
2158 	    (!hw->dev_spec._82575.eee_disable))
2159 		adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2160 
2161 	return 0;
2162 }
2163 
2164 void igb_down(struct igb_adapter *adapter)
2165 {
2166 	struct net_device *netdev = adapter->netdev;
2167 	struct e1000_hw *hw = &adapter->hw;
2168 	u32 tctl, rctl;
2169 	int i;
2170 
2171 	/* signal that we're down so the interrupt handler does not
2172 	 * reschedule our watchdog timer
2173 	 */
2174 	set_bit(__IGB_DOWN, &adapter->state);
2175 
2176 	/* disable receives in the hardware */
2177 	rctl = rd32(E1000_RCTL);
2178 	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2179 	/* flush and sleep below */
2180 
2181 	igb_nfc_filter_exit(adapter);
2182 
2183 	netif_carrier_off(netdev);
2184 	netif_tx_stop_all_queues(netdev);
2185 
2186 	/* disable transmits in the hardware */
2187 	tctl = rd32(E1000_TCTL);
2188 	tctl &= ~E1000_TCTL_EN;
2189 	wr32(E1000_TCTL, tctl);
2190 	/* flush both disables and wait for them to finish */
2191 	wrfl();
2192 	usleep_range(10000, 11000);
2193 
2194 	igb_irq_disable(adapter);
2195 
2196 	adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2197 
2198 	for (i = 0; i < adapter->num_q_vectors; i++) {
2199 		if (adapter->q_vector[i]) {
2200 			napi_synchronize(&adapter->q_vector[i]->napi);
2201 			napi_disable(&adapter->q_vector[i]->napi);
2202 		}
2203 	}
2204 
2205 	del_timer_sync(&adapter->watchdog_timer);
2206 	del_timer_sync(&adapter->phy_info_timer);
2207 
2208 	/* record the stats before reset*/
2209 	spin_lock(&adapter->stats64_lock);
2210 	igb_update_stats(adapter);
2211 	spin_unlock(&adapter->stats64_lock);
2212 
2213 	adapter->link_speed = 0;
2214 	adapter->link_duplex = 0;
2215 
2216 	if (!pci_channel_offline(adapter->pdev))
2217 		igb_reset(adapter);
2218 
2219 	/* clear VLAN promisc flag so VFTA will be updated if necessary */
2220 	adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2221 
2222 	igb_clean_all_tx_rings(adapter);
2223 	igb_clean_all_rx_rings(adapter);
2224 #ifdef CONFIG_IGB_DCA
2225 
2226 	/* since we reset the hardware DCA settings were cleared */
2227 	igb_setup_dca(adapter);
2228 #endif
2229 }
2230 
2231 void igb_reinit_locked(struct igb_adapter *adapter)
2232 {
2233 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2234 		usleep_range(1000, 2000);
2235 	igb_down(adapter);
2236 	igb_up(adapter);
2237 	clear_bit(__IGB_RESETTING, &adapter->state);
2238 }
2239 
2240 /** igb_enable_mas - Media Autosense re-enable after swap
2241  *
2242  * @adapter: adapter struct
2243  **/
2244 static void igb_enable_mas(struct igb_adapter *adapter)
2245 {
2246 	struct e1000_hw *hw = &adapter->hw;
2247 	u32 connsw = rd32(E1000_CONNSW);
2248 
2249 	/* configure for SerDes media detect */
2250 	if ((hw->phy.media_type == e1000_media_type_copper) &&
2251 	    (!(connsw & E1000_CONNSW_SERDESD))) {
2252 		connsw |= E1000_CONNSW_ENRGSRC;
2253 		connsw |= E1000_CONNSW_AUTOSENSE_EN;
2254 		wr32(E1000_CONNSW, connsw);
2255 		wrfl();
2256 	}
2257 }
2258 
2259 #ifdef CONFIG_IGB_HWMON
2260 /**
2261  *  igb_set_i2c_bb - Init I2C interface
2262  *  @hw: pointer to hardware structure
2263  **/
2264 static void igb_set_i2c_bb(struct e1000_hw *hw)
2265 {
2266 	u32 ctrl_ext;
2267 	s32 i2cctl;
2268 
2269 	ctrl_ext = rd32(E1000_CTRL_EXT);
2270 	ctrl_ext |= E1000_CTRL_I2C_ENA;
2271 	wr32(E1000_CTRL_EXT, ctrl_ext);
2272 	wrfl();
2273 
2274 	i2cctl = rd32(E1000_I2CPARAMS);
2275 	i2cctl |= E1000_I2CBB_EN
2276 		| E1000_I2C_CLK_OE_N
2277 		| E1000_I2C_DATA_OE_N;
2278 	wr32(E1000_I2CPARAMS, i2cctl);
2279 	wrfl();
2280 }
2281 #endif
2282 
2283 void igb_reset(struct igb_adapter *adapter)
2284 {
2285 	struct pci_dev *pdev = adapter->pdev;
2286 	struct e1000_hw *hw = &adapter->hw;
2287 	struct e1000_mac_info *mac = &hw->mac;
2288 	struct e1000_fc_info *fc = &hw->fc;
2289 	u32 pba, hwm;
2290 
2291 	/* Repartition Pba for greater than 9k mtu
2292 	 * To take effect CTRL.RST is required.
2293 	 */
2294 	switch (mac->type) {
2295 	case e1000_i350:
2296 	case e1000_i354:
2297 	case e1000_82580:
2298 		pba = rd32(E1000_RXPBS);
2299 		pba = igb_rxpbs_adjust_82580(pba);
2300 		break;
2301 	case e1000_82576:
2302 		pba = rd32(E1000_RXPBS);
2303 		pba &= E1000_RXPBS_SIZE_MASK_82576;
2304 		break;
2305 	case e1000_82575:
2306 	case e1000_i210:
2307 	case e1000_i211:
2308 	default:
2309 		pba = E1000_PBA_34K;
2310 		break;
2311 	}
2312 
2313 	if (mac->type == e1000_82575) {
2314 		u32 min_rx_space, min_tx_space, needed_tx_space;
2315 
2316 		/* write Rx PBA so that hardware can report correct Tx PBA */
2317 		wr32(E1000_PBA, pba);
2318 
2319 		/* To maintain wire speed transmits, the Tx FIFO should be
2320 		 * large enough to accommodate two full transmit packets,
2321 		 * rounded up to the next 1KB and expressed in KB.  Likewise,
2322 		 * the Rx FIFO should be large enough to accommodate at least
2323 		 * one full receive packet and is similarly rounded up and
2324 		 * expressed in KB.
2325 		 */
2326 		min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2327 
2328 		/* The Tx FIFO also stores 16 bytes of information about the Tx
2329 		 * but don't include Ethernet FCS because hardware appends it.
2330 		 * We only need to round down to the nearest 512 byte block
2331 		 * count since the value we care about is 2 frames, not 1.
2332 		 */
2333 		min_tx_space = adapter->max_frame_size;
2334 		min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2335 		min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2336 
2337 		/* upper 16 bits has Tx packet buffer allocation size in KB */
2338 		needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2339 
2340 		/* If current Tx allocation is less than the min Tx FIFO size,
2341 		 * and the min Tx FIFO size is less than the current Rx FIFO
2342 		 * allocation, take space away from current Rx allocation.
2343 		 */
2344 		if (needed_tx_space < pba) {
2345 			pba -= needed_tx_space;
2346 
2347 			/* if short on Rx space, Rx wins and must trump Tx
2348 			 * adjustment
2349 			 */
2350 			if (pba < min_rx_space)
2351 				pba = min_rx_space;
2352 		}
2353 
2354 		/* adjust PBA for jumbo frames */
2355 		wr32(E1000_PBA, pba);
2356 	}
2357 
2358 	/* flow control settings
2359 	 * The high water mark must be low enough to fit one full frame
2360 	 * after transmitting the pause frame.  As such we must have enough
2361 	 * space to allow for us to complete our current transmit and then
2362 	 * receive the frame that is in progress from the link partner.
2363 	 * Set it to:
2364 	 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2365 	 */
2366 	hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2367 
2368 	fc->high_water = hwm & 0xFFFFFFF0;	/* 16-byte granularity */
2369 	fc->low_water = fc->high_water - 16;
2370 	fc->pause_time = 0xFFFF;
2371 	fc->send_xon = 1;
2372 	fc->current_mode = fc->requested_mode;
2373 
2374 	/* disable receive for all VFs and wait one second */
2375 	if (adapter->vfs_allocated_count) {
2376 		int i;
2377 
2378 		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2379 			adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2380 
2381 		/* ping all the active vfs to let them know we are going down */
2382 		igb_ping_all_vfs(adapter);
2383 
2384 		/* disable transmits and receives */
2385 		wr32(E1000_VFRE, 0);
2386 		wr32(E1000_VFTE, 0);
2387 	}
2388 
2389 	/* Allow time for pending master requests to run */
2390 	hw->mac.ops.reset_hw(hw);
2391 	wr32(E1000_WUC, 0);
2392 
2393 	if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2394 		/* need to resetup here after media swap */
2395 		adapter->ei.get_invariants(hw);
2396 		adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2397 	}
2398 	if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2399 	    (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2400 		igb_enable_mas(adapter);
2401 	}
2402 	if (hw->mac.ops.init_hw(hw))
2403 		dev_err(&pdev->dev, "Hardware Error\n");
2404 
2405 	/* RAR registers were cleared during init_hw, clear mac table */
2406 	igb_flush_mac_table(adapter);
2407 	__dev_uc_unsync(adapter->netdev, NULL);
2408 
2409 	/* Recover default RAR entry */
2410 	igb_set_default_mac_filter(adapter);
2411 
2412 	/* Flow control settings reset on hardware reset, so guarantee flow
2413 	 * control is off when forcing speed.
2414 	 */
2415 	if (!hw->mac.autoneg)
2416 		igb_force_mac_fc(hw);
2417 
2418 	igb_init_dmac(adapter, pba);
2419 #ifdef CONFIG_IGB_HWMON
2420 	/* Re-initialize the thermal sensor on i350 devices. */
2421 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
2422 		if (mac->type == e1000_i350 && hw->bus.func == 0) {
2423 			/* If present, re-initialize the external thermal sensor
2424 			 * interface.
2425 			 */
2426 			if (adapter->ets)
2427 				igb_set_i2c_bb(hw);
2428 			mac->ops.init_thermal_sensor_thresh(hw);
2429 		}
2430 	}
2431 #endif
2432 	/* Re-establish EEE setting */
2433 	if (hw->phy.media_type == e1000_media_type_copper) {
2434 		switch (mac->type) {
2435 		case e1000_i350:
2436 		case e1000_i210:
2437 		case e1000_i211:
2438 			igb_set_eee_i350(hw, true, true);
2439 			break;
2440 		case e1000_i354:
2441 			igb_set_eee_i354(hw, true, true);
2442 			break;
2443 		default:
2444 			break;
2445 		}
2446 	}
2447 	if (!netif_running(adapter->netdev))
2448 		igb_power_down_link(adapter);
2449 
2450 	igb_update_mng_vlan(adapter);
2451 
2452 	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2453 	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2454 
2455 	/* Re-enable PTP, where applicable. */
2456 	if (adapter->ptp_flags & IGB_PTP_ENABLED)
2457 		igb_ptp_reset(adapter);
2458 
2459 	igb_get_phy_info(hw);
2460 }
2461 
2462 static netdev_features_t igb_fix_features(struct net_device *netdev,
2463 	netdev_features_t features)
2464 {
2465 	/* Since there is no support for separate Rx/Tx vlan accel
2466 	 * enable/disable make sure Tx flag is always in same state as Rx.
2467 	 */
2468 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
2469 		features |= NETIF_F_HW_VLAN_CTAG_TX;
2470 	else
2471 		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2472 
2473 	return features;
2474 }
2475 
2476 static int igb_set_features(struct net_device *netdev,
2477 	netdev_features_t features)
2478 {
2479 	netdev_features_t changed = netdev->features ^ features;
2480 	struct igb_adapter *adapter = netdev_priv(netdev);
2481 
2482 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2483 		igb_vlan_mode(netdev, features);
2484 
2485 	if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2486 		return 0;
2487 
2488 	if (!(features & NETIF_F_NTUPLE)) {
2489 		struct hlist_node *node2;
2490 		struct igb_nfc_filter *rule;
2491 
2492 		spin_lock(&adapter->nfc_lock);
2493 		hlist_for_each_entry_safe(rule, node2,
2494 					  &adapter->nfc_filter_list, nfc_node) {
2495 			igb_erase_filter(adapter, rule);
2496 			hlist_del(&rule->nfc_node);
2497 			kfree(rule);
2498 		}
2499 		spin_unlock(&adapter->nfc_lock);
2500 		adapter->nfc_filter_count = 0;
2501 	}
2502 
2503 	netdev->features = features;
2504 
2505 	if (netif_running(netdev))
2506 		igb_reinit_locked(adapter);
2507 	else
2508 		igb_reset(adapter);
2509 
2510 	return 1;
2511 }
2512 
2513 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2514 			   struct net_device *dev,
2515 			   const unsigned char *addr, u16 vid,
2516 			   u16 flags,
2517 			   struct netlink_ext_ack *extack)
2518 {
2519 	/* guarantee we can provide a unique filter for the unicast address */
2520 	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2521 		struct igb_adapter *adapter = netdev_priv(dev);
2522 		int vfn = adapter->vfs_allocated_count;
2523 
2524 		if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2525 			return -ENOMEM;
2526 	}
2527 
2528 	return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2529 }
2530 
2531 #define IGB_MAX_MAC_HDR_LEN	127
2532 #define IGB_MAX_NETWORK_HDR_LEN	511
2533 
2534 static netdev_features_t
2535 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2536 		   netdev_features_t features)
2537 {
2538 	unsigned int network_hdr_len, mac_hdr_len;
2539 
2540 	/* Make certain the headers can be described by a context descriptor */
2541 	mac_hdr_len = skb_network_header(skb) - skb->data;
2542 	if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2543 		return features & ~(NETIF_F_HW_CSUM |
2544 				    NETIF_F_SCTP_CRC |
2545 				    NETIF_F_GSO_UDP_L4 |
2546 				    NETIF_F_HW_VLAN_CTAG_TX |
2547 				    NETIF_F_TSO |
2548 				    NETIF_F_TSO6);
2549 
2550 	network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2551 	if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2552 		return features & ~(NETIF_F_HW_CSUM |
2553 				    NETIF_F_SCTP_CRC |
2554 				    NETIF_F_GSO_UDP_L4 |
2555 				    NETIF_F_TSO |
2556 				    NETIF_F_TSO6);
2557 
2558 	/* We can only support IPV4 TSO in tunnels if we can mangle the
2559 	 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2560 	 */
2561 	if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2562 		features &= ~NETIF_F_TSO;
2563 
2564 	return features;
2565 }
2566 
2567 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2568 {
2569 	if (!is_fqtss_enabled(adapter)) {
2570 		enable_fqtss(adapter, true);
2571 		return;
2572 	}
2573 
2574 	igb_config_tx_modes(adapter, queue);
2575 
2576 	if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2577 		enable_fqtss(adapter, false);
2578 }
2579 
2580 static int igb_offload_cbs(struct igb_adapter *adapter,
2581 			   struct tc_cbs_qopt_offload *qopt)
2582 {
2583 	struct e1000_hw *hw = &adapter->hw;
2584 	int err;
2585 
2586 	/* CBS offloading is only supported by i210 controller. */
2587 	if (hw->mac.type != e1000_i210)
2588 		return -EOPNOTSUPP;
2589 
2590 	/* CBS offloading is only supported by queue 0 and queue 1. */
2591 	if (qopt->queue < 0 || qopt->queue > 1)
2592 		return -EINVAL;
2593 
2594 	err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2595 				  qopt->idleslope, qopt->sendslope,
2596 				  qopt->hicredit, qopt->locredit);
2597 	if (err)
2598 		return err;
2599 
2600 	igb_offload_apply(adapter, qopt->queue);
2601 
2602 	return 0;
2603 }
2604 
2605 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2606 #define VLAN_PRIO_FULL_MASK (0x07)
2607 
2608 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2609 				struct flow_cls_offload *f,
2610 				int traffic_class,
2611 				struct igb_nfc_filter *input)
2612 {
2613 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2614 	struct flow_dissector *dissector = rule->match.dissector;
2615 	struct netlink_ext_ack *extack = f->common.extack;
2616 
2617 	if (dissector->used_keys &
2618 	    ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2619 	      BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2620 	      BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2621 	      BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
2622 		NL_SET_ERR_MSG_MOD(extack,
2623 				   "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2624 		return -EOPNOTSUPP;
2625 	}
2626 
2627 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2628 		struct flow_match_eth_addrs match;
2629 
2630 		flow_rule_match_eth_addrs(rule, &match);
2631 		if (!is_zero_ether_addr(match.mask->dst)) {
2632 			if (!is_broadcast_ether_addr(match.mask->dst)) {
2633 				NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2634 				return -EINVAL;
2635 			}
2636 
2637 			input->filter.match_flags |=
2638 				IGB_FILTER_FLAG_DST_MAC_ADDR;
2639 			ether_addr_copy(input->filter.dst_addr, match.key->dst);
2640 		}
2641 
2642 		if (!is_zero_ether_addr(match.mask->src)) {
2643 			if (!is_broadcast_ether_addr(match.mask->src)) {
2644 				NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2645 				return -EINVAL;
2646 			}
2647 
2648 			input->filter.match_flags |=
2649 				IGB_FILTER_FLAG_SRC_MAC_ADDR;
2650 			ether_addr_copy(input->filter.src_addr, match.key->src);
2651 		}
2652 	}
2653 
2654 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2655 		struct flow_match_basic match;
2656 
2657 		flow_rule_match_basic(rule, &match);
2658 		if (match.mask->n_proto) {
2659 			if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2660 				NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2661 				return -EINVAL;
2662 			}
2663 
2664 			input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2665 			input->filter.etype = match.key->n_proto;
2666 		}
2667 	}
2668 
2669 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2670 		struct flow_match_vlan match;
2671 
2672 		flow_rule_match_vlan(rule, &match);
2673 		if (match.mask->vlan_priority) {
2674 			if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2675 				NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2676 				return -EINVAL;
2677 			}
2678 
2679 			input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2680 			input->filter.vlan_tci =
2681 				(__force __be16)match.key->vlan_priority;
2682 		}
2683 	}
2684 
2685 	input->action = traffic_class;
2686 	input->cookie = f->cookie;
2687 
2688 	return 0;
2689 }
2690 
2691 static int igb_configure_clsflower(struct igb_adapter *adapter,
2692 				   struct flow_cls_offload *cls_flower)
2693 {
2694 	struct netlink_ext_ack *extack = cls_flower->common.extack;
2695 	struct igb_nfc_filter *filter, *f;
2696 	int err, tc;
2697 
2698 	tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2699 	if (tc < 0) {
2700 		NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2701 		return -EINVAL;
2702 	}
2703 
2704 	filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2705 	if (!filter)
2706 		return -ENOMEM;
2707 
2708 	err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2709 	if (err < 0)
2710 		goto err_parse;
2711 
2712 	spin_lock(&adapter->nfc_lock);
2713 
2714 	hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2715 		if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2716 			err = -EEXIST;
2717 			NL_SET_ERR_MSG_MOD(extack,
2718 					   "This filter is already set in ethtool");
2719 			goto err_locked;
2720 		}
2721 	}
2722 
2723 	hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2724 		if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2725 			err = -EEXIST;
2726 			NL_SET_ERR_MSG_MOD(extack,
2727 					   "This filter is already set in cls_flower");
2728 			goto err_locked;
2729 		}
2730 	}
2731 
2732 	err = igb_add_filter(adapter, filter);
2733 	if (err < 0) {
2734 		NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2735 		goto err_locked;
2736 	}
2737 
2738 	hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2739 
2740 	spin_unlock(&adapter->nfc_lock);
2741 
2742 	return 0;
2743 
2744 err_locked:
2745 	spin_unlock(&adapter->nfc_lock);
2746 
2747 err_parse:
2748 	kfree(filter);
2749 
2750 	return err;
2751 }
2752 
2753 static int igb_delete_clsflower(struct igb_adapter *adapter,
2754 				struct flow_cls_offload *cls_flower)
2755 {
2756 	struct igb_nfc_filter *filter;
2757 	int err;
2758 
2759 	spin_lock(&adapter->nfc_lock);
2760 
2761 	hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2762 		if (filter->cookie == cls_flower->cookie)
2763 			break;
2764 
2765 	if (!filter) {
2766 		err = -ENOENT;
2767 		goto out;
2768 	}
2769 
2770 	err = igb_erase_filter(adapter, filter);
2771 	if (err < 0)
2772 		goto out;
2773 
2774 	hlist_del(&filter->nfc_node);
2775 	kfree(filter);
2776 
2777 out:
2778 	spin_unlock(&adapter->nfc_lock);
2779 
2780 	return err;
2781 }
2782 
2783 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2784 				   struct flow_cls_offload *cls_flower)
2785 {
2786 	switch (cls_flower->command) {
2787 	case FLOW_CLS_REPLACE:
2788 		return igb_configure_clsflower(adapter, cls_flower);
2789 	case FLOW_CLS_DESTROY:
2790 		return igb_delete_clsflower(adapter, cls_flower);
2791 	case FLOW_CLS_STATS:
2792 		return -EOPNOTSUPP;
2793 	default:
2794 		return -EOPNOTSUPP;
2795 	}
2796 }
2797 
2798 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2799 				 void *cb_priv)
2800 {
2801 	struct igb_adapter *adapter = cb_priv;
2802 
2803 	if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2804 		return -EOPNOTSUPP;
2805 
2806 	switch (type) {
2807 	case TC_SETUP_CLSFLOWER:
2808 		return igb_setup_tc_cls_flower(adapter, type_data);
2809 
2810 	default:
2811 		return -EOPNOTSUPP;
2812 	}
2813 }
2814 
2815 static int igb_offload_txtime(struct igb_adapter *adapter,
2816 			      struct tc_etf_qopt_offload *qopt)
2817 {
2818 	struct e1000_hw *hw = &adapter->hw;
2819 	int err;
2820 
2821 	/* Launchtime offloading is only supported by i210 controller. */
2822 	if (hw->mac.type != e1000_i210)
2823 		return -EOPNOTSUPP;
2824 
2825 	/* Launchtime offloading is only supported by queues 0 and 1. */
2826 	if (qopt->queue < 0 || qopt->queue > 1)
2827 		return -EINVAL;
2828 
2829 	err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2830 	if (err)
2831 		return err;
2832 
2833 	igb_offload_apply(adapter, qopt->queue);
2834 
2835 	return 0;
2836 }
2837 
2838 static int igb_tc_query_caps(struct igb_adapter *adapter,
2839 			     struct tc_query_caps_base *base)
2840 {
2841 	switch (base->type) {
2842 	case TC_SETUP_QDISC_TAPRIO: {
2843 		struct tc_taprio_caps *caps = base->caps;
2844 
2845 		caps->broken_mqprio = true;
2846 
2847 		return 0;
2848 	}
2849 	default:
2850 		return -EOPNOTSUPP;
2851 	}
2852 }
2853 
2854 static LIST_HEAD(igb_block_cb_list);
2855 
2856 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2857 			void *type_data)
2858 {
2859 	struct igb_adapter *adapter = netdev_priv(dev);
2860 
2861 	switch (type) {
2862 	case TC_QUERY_CAPS:
2863 		return igb_tc_query_caps(adapter, type_data);
2864 	case TC_SETUP_QDISC_CBS:
2865 		return igb_offload_cbs(adapter, type_data);
2866 	case TC_SETUP_BLOCK:
2867 		return flow_block_cb_setup_simple(type_data,
2868 						  &igb_block_cb_list,
2869 						  igb_setup_tc_block_cb,
2870 						  adapter, adapter, true);
2871 
2872 	case TC_SETUP_QDISC_ETF:
2873 		return igb_offload_txtime(adapter, type_data);
2874 
2875 	default:
2876 		return -EOPNOTSUPP;
2877 	}
2878 }
2879 
2880 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2881 {
2882 	int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2883 	struct igb_adapter *adapter = netdev_priv(dev);
2884 	struct bpf_prog *prog = bpf->prog, *old_prog;
2885 	bool running = netif_running(dev);
2886 	bool need_reset;
2887 
2888 	/* verify igb ring attributes are sufficient for XDP */
2889 	for (i = 0; i < adapter->num_rx_queues; i++) {
2890 		struct igb_ring *ring = adapter->rx_ring[i];
2891 
2892 		if (frame_size > igb_rx_bufsz(ring)) {
2893 			NL_SET_ERR_MSG_MOD(bpf->extack,
2894 					   "The RX buffer size is too small for the frame size");
2895 			netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2896 				    igb_rx_bufsz(ring), frame_size);
2897 			return -EINVAL;
2898 		}
2899 	}
2900 
2901 	old_prog = xchg(&adapter->xdp_prog, prog);
2902 	need_reset = (!!prog != !!old_prog);
2903 
2904 	/* device is up and bpf is added/removed, must setup the RX queues */
2905 	if (need_reset && running) {
2906 		igb_close(dev);
2907 	} else {
2908 		for (i = 0; i < adapter->num_rx_queues; i++)
2909 			(void)xchg(&adapter->rx_ring[i]->xdp_prog,
2910 			    adapter->xdp_prog);
2911 	}
2912 
2913 	if (old_prog)
2914 		bpf_prog_put(old_prog);
2915 
2916 	/* bpf is just replaced, RXQ and MTU are already setup */
2917 	if (!need_reset) {
2918 		return 0;
2919 	} else {
2920 		if (prog)
2921 			xdp_features_set_redirect_target(dev, true);
2922 		else
2923 			xdp_features_clear_redirect_target(dev);
2924 	}
2925 
2926 	if (running)
2927 		igb_open(dev);
2928 
2929 	return 0;
2930 }
2931 
2932 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2933 {
2934 	switch (xdp->command) {
2935 	case XDP_SETUP_PROG:
2936 		return igb_xdp_setup(dev, xdp);
2937 	default:
2938 		return -EINVAL;
2939 	}
2940 }
2941 
2942 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2943 {
2944 	/* Force memory writes to complete before letting h/w know there
2945 	 * are new descriptors to fetch.
2946 	 */
2947 	wmb();
2948 	writel(ring->next_to_use, ring->tail);
2949 }
2950 
2951 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2952 {
2953 	unsigned int r_idx = smp_processor_id();
2954 
2955 	if (r_idx >= adapter->num_tx_queues)
2956 		r_idx = r_idx % adapter->num_tx_queues;
2957 
2958 	return adapter->tx_ring[r_idx];
2959 }
2960 
2961 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2962 {
2963 	struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2964 	int cpu = smp_processor_id();
2965 	struct igb_ring *tx_ring;
2966 	struct netdev_queue *nq;
2967 	u32 ret;
2968 
2969 	if (unlikely(!xdpf))
2970 		return IGB_XDP_CONSUMED;
2971 
2972 	/* During program transitions its possible adapter->xdp_prog is assigned
2973 	 * but ring has not been configured yet. In this case simply abort xmit.
2974 	 */
2975 	tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2976 	if (unlikely(!tx_ring))
2977 		return IGB_XDP_CONSUMED;
2978 
2979 	nq = txring_txq(tx_ring);
2980 	__netif_tx_lock(nq, cpu);
2981 	/* Avoid transmit queue timeout since we share it with the slow path */
2982 	txq_trans_cond_update(nq);
2983 	ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2984 	__netif_tx_unlock(nq);
2985 
2986 	return ret;
2987 }
2988 
2989 static int igb_xdp_xmit(struct net_device *dev, int n,
2990 			struct xdp_frame **frames, u32 flags)
2991 {
2992 	struct igb_adapter *adapter = netdev_priv(dev);
2993 	int cpu = smp_processor_id();
2994 	struct igb_ring *tx_ring;
2995 	struct netdev_queue *nq;
2996 	int nxmit = 0;
2997 	int i;
2998 
2999 	if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
3000 		return -ENETDOWN;
3001 
3002 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3003 		return -EINVAL;
3004 
3005 	/* During program transitions its possible adapter->xdp_prog is assigned
3006 	 * but ring has not been configured yet. In this case simply abort xmit.
3007 	 */
3008 	tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
3009 	if (unlikely(!tx_ring))
3010 		return -ENXIO;
3011 
3012 	nq = txring_txq(tx_ring);
3013 	__netif_tx_lock(nq, cpu);
3014 
3015 	/* Avoid transmit queue timeout since we share it with the slow path */
3016 	txq_trans_cond_update(nq);
3017 
3018 	for (i = 0; i < n; i++) {
3019 		struct xdp_frame *xdpf = frames[i];
3020 		int err;
3021 
3022 		err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
3023 		if (err != IGB_XDP_TX)
3024 			break;
3025 		nxmit++;
3026 	}
3027 
3028 	__netif_tx_unlock(nq);
3029 
3030 	if (unlikely(flags & XDP_XMIT_FLUSH))
3031 		igb_xdp_ring_update_tail(tx_ring);
3032 
3033 	return nxmit;
3034 }
3035 
3036 static const struct net_device_ops igb_netdev_ops = {
3037 	.ndo_open		= igb_open,
3038 	.ndo_stop		= igb_close,
3039 	.ndo_start_xmit		= igb_xmit_frame,
3040 	.ndo_get_stats64	= igb_get_stats64,
3041 	.ndo_set_rx_mode	= igb_set_rx_mode,
3042 	.ndo_set_mac_address	= igb_set_mac,
3043 	.ndo_change_mtu		= igb_change_mtu,
3044 	.ndo_eth_ioctl		= igb_ioctl,
3045 	.ndo_tx_timeout		= igb_tx_timeout,
3046 	.ndo_validate_addr	= eth_validate_addr,
3047 	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
3048 	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
3049 	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
3050 	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
3051 	.ndo_set_vf_rate	= igb_ndo_set_vf_bw,
3052 	.ndo_set_vf_spoofchk	= igb_ndo_set_vf_spoofchk,
3053 	.ndo_set_vf_trust	= igb_ndo_set_vf_trust,
3054 	.ndo_get_vf_config	= igb_ndo_get_vf_config,
3055 	.ndo_fix_features	= igb_fix_features,
3056 	.ndo_set_features	= igb_set_features,
3057 	.ndo_fdb_add		= igb_ndo_fdb_add,
3058 	.ndo_features_check	= igb_features_check,
3059 	.ndo_setup_tc		= igb_setup_tc,
3060 	.ndo_bpf		= igb_xdp,
3061 	.ndo_xdp_xmit		= igb_xdp_xmit,
3062 };
3063 
3064 /**
3065  * igb_set_fw_version - Configure version string for ethtool
3066  * @adapter: adapter struct
3067  **/
3068 void igb_set_fw_version(struct igb_adapter *adapter)
3069 {
3070 	struct e1000_hw *hw = &adapter->hw;
3071 	struct e1000_fw_version fw;
3072 
3073 	igb_get_fw_version(hw, &fw);
3074 
3075 	switch (hw->mac.type) {
3076 	case e1000_i210:
3077 	case e1000_i211:
3078 		if (!(igb_get_flash_presence_i210(hw))) {
3079 			snprintf(adapter->fw_version,
3080 				 sizeof(adapter->fw_version),
3081 				 "%2d.%2d-%d",
3082 				 fw.invm_major, fw.invm_minor,
3083 				 fw.invm_img_type);
3084 			break;
3085 		}
3086 		fallthrough;
3087 	default:
3088 		/* if option is rom valid, display its version too */
3089 		if (fw.or_valid) {
3090 			snprintf(adapter->fw_version,
3091 				 sizeof(adapter->fw_version),
3092 				 "%d.%d, 0x%08x, %d.%d.%d",
3093 				 fw.eep_major, fw.eep_minor, fw.etrack_id,
3094 				 fw.or_major, fw.or_build, fw.or_patch);
3095 		/* no option rom */
3096 		} else if (fw.etrack_id != 0X0000) {
3097 			snprintf(adapter->fw_version,
3098 			    sizeof(adapter->fw_version),
3099 			    "%d.%d, 0x%08x",
3100 			    fw.eep_major, fw.eep_minor, fw.etrack_id);
3101 		} else {
3102 		snprintf(adapter->fw_version,
3103 		    sizeof(adapter->fw_version),
3104 		    "%d.%d.%d",
3105 		    fw.eep_major, fw.eep_minor, fw.eep_build);
3106 		}
3107 		break;
3108 	}
3109 }
3110 
3111 /**
3112  * igb_init_mas - init Media Autosense feature if enabled in the NVM
3113  *
3114  * @adapter: adapter struct
3115  **/
3116 static void igb_init_mas(struct igb_adapter *adapter)
3117 {
3118 	struct e1000_hw *hw = &adapter->hw;
3119 	u16 eeprom_data;
3120 
3121 	hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3122 	switch (hw->bus.func) {
3123 	case E1000_FUNC_0:
3124 		if (eeprom_data & IGB_MAS_ENABLE_0) {
3125 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3126 			netdev_info(adapter->netdev,
3127 				"MAS: Enabling Media Autosense for port %d\n",
3128 				hw->bus.func);
3129 		}
3130 		break;
3131 	case E1000_FUNC_1:
3132 		if (eeprom_data & IGB_MAS_ENABLE_1) {
3133 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3134 			netdev_info(adapter->netdev,
3135 				"MAS: Enabling Media Autosense for port %d\n",
3136 				hw->bus.func);
3137 		}
3138 		break;
3139 	case E1000_FUNC_2:
3140 		if (eeprom_data & IGB_MAS_ENABLE_2) {
3141 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3142 			netdev_info(adapter->netdev,
3143 				"MAS: Enabling Media Autosense for port %d\n",
3144 				hw->bus.func);
3145 		}
3146 		break;
3147 	case E1000_FUNC_3:
3148 		if (eeprom_data & IGB_MAS_ENABLE_3) {
3149 			adapter->flags |= IGB_FLAG_MAS_ENABLE;
3150 			netdev_info(adapter->netdev,
3151 				"MAS: Enabling Media Autosense for port %d\n",
3152 				hw->bus.func);
3153 		}
3154 		break;
3155 	default:
3156 		/* Shouldn't get here */
3157 		netdev_err(adapter->netdev,
3158 			"MAS: Invalid port configuration, returning\n");
3159 		break;
3160 	}
3161 }
3162 
3163 /**
3164  *  igb_init_i2c - Init I2C interface
3165  *  @adapter: pointer to adapter structure
3166  **/
3167 static s32 igb_init_i2c(struct igb_adapter *adapter)
3168 {
3169 	s32 status = 0;
3170 
3171 	/* I2C interface supported on i350 devices */
3172 	if (adapter->hw.mac.type != e1000_i350)
3173 		return 0;
3174 
3175 	/* Initialize the i2c bus which is controlled by the registers.
3176 	 * This bus will use the i2c_algo_bit structure that implements
3177 	 * the protocol through toggling of the 4 bits in the register.
3178 	 */
3179 	adapter->i2c_adap.owner = THIS_MODULE;
3180 	adapter->i2c_algo = igb_i2c_algo;
3181 	adapter->i2c_algo.data = adapter;
3182 	adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3183 	adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3184 	strscpy(adapter->i2c_adap.name, "igb BB",
3185 		sizeof(adapter->i2c_adap.name));
3186 	status = i2c_bit_add_bus(&adapter->i2c_adap);
3187 	return status;
3188 }
3189 
3190 /**
3191  *  igb_probe - Device Initialization Routine
3192  *  @pdev: PCI device information struct
3193  *  @ent: entry in igb_pci_tbl
3194  *
3195  *  Returns 0 on success, negative on failure
3196  *
3197  *  igb_probe initializes an adapter identified by a pci_dev structure.
3198  *  The OS initialization, configuring of the adapter private structure,
3199  *  and a hardware reset occur.
3200  **/
3201 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3202 {
3203 	struct net_device *netdev;
3204 	struct igb_adapter *adapter;
3205 	struct e1000_hw *hw;
3206 	u16 eeprom_data = 0;
3207 	s32 ret_val;
3208 	static int global_quad_port_a; /* global quad port a indication */
3209 	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3210 	u8 part_str[E1000_PBANUM_LENGTH];
3211 	int err;
3212 
3213 	/* Catch broken hardware that put the wrong VF device ID in
3214 	 * the PCIe SR-IOV capability.
3215 	 */
3216 	if (pdev->is_virtfn) {
3217 		WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3218 			pci_name(pdev), pdev->vendor, pdev->device);
3219 		return -EINVAL;
3220 	}
3221 
3222 	err = pci_enable_device_mem(pdev);
3223 	if (err)
3224 		return err;
3225 
3226 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3227 	if (err) {
3228 		dev_err(&pdev->dev,
3229 			"No usable DMA configuration, aborting\n");
3230 		goto err_dma;
3231 	}
3232 
3233 	err = pci_request_mem_regions(pdev, igb_driver_name);
3234 	if (err)
3235 		goto err_pci_reg;
3236 
3237 	pci_set_master(pdev);
3238 	pci_save_state(pdev);
3239 
3240 	err = -ENOMEM;
3241 	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3242 				   IGB_MAX_TX_QUEUES);
3243 	if (!netdev)
3244 		goto err_alloc_etherdev;
3245 
3246 	SET_NETDEV_DEV(netdev, &pdev->dev);
3247 
3248 	pci_set_drvdata(pdev, netdev);
3249 	adapter = netdev_priv(netdev);
3250 	adapter->netdev = netdev;
3251 	adapter->pdev = pdev;
3252 	hw = &adapter->hw;
3253 	hw->back = adapter;
3254 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3255 
3256 	err = -EIO;
3257 	adapter->io_addr = pci_iomap(pdev, 0, 0);
3258 	if (!adapter->io_addr)
3259 		goto err_ioremap;
3260 	/* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3261 	hw->hw_addr = adapter->io_addr;
3262 
3263 	netdev->netdev_ops = &igb_netdev_ops;
3264 	igb_set_ethtool_ops(netdev);
3265 	netdev->watchdog_timeo = 5 * HZ;
3266 
3267 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3268 
3269 	netdev->mem_start = pci_resource_start(pdev, 0);
3270 	netdev->mem_end = pci_resource_end(pdev, 0);
3271 
3272 	/* PCI config space info */
3273 	hw->vendor_id = pdev->vendor;
3274 	hw->device_id = pdev->device;
3275 	hw->revision_id = pdev->revision;
3276 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
3277 	hw->subsystem_device_id = pdev->subsystem_device;
3278 
3279 	/* Copy the default MAC, PHY and NVM function pointers */
3280 	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3281 	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3282 	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3283 	/* Initialize skew-specific constants */
3284 	err = ei->get_invariants(hw);
3285 	if (err)
3286 		goto err_sw_init;
3287 
3288 	/* setup the private structure */
3289 	err = igb_sw_init(adapter);
3290 	if (err)
3291 		goto err_sw_init;
3292 
3293 	igb_get_bus_info_pcie(hw);
3294 
3295 	hw->phy.autoneg_wait_to_complete = false;
3296 
3297 	/* Copper options */
3298 	if (hw->phy.media_type == e1000_media_type_copper) {
3299 		hw->phy.mdix = AUTO_ALL_MODES;
3300 		hw->phy.disable_polarity_correction = false;
3301 		hw->phy.ms_type = e1000_ms_hw_default;
3302 	}
3303 
3304 	if (igb_check_reset_block(hw))
3305 		dev_info(&pdev->dev,
3306 			"PHY reset is blocked due to SOL/IDER session.\n");
3307 
3308 	/* features is initialized to 0 in allocation, it might have bits
3309 	 * set by igb_sw_init so we should use an or instead of an
3310 	 * assignment.
3311 	 */
3312 	netdev->features |= NETIF_F_SG |
3313 			    NETIF_F_TSO |
3314 			    NETIF_F_TSO6 |
3315 			    NETIF_F_RXHASH |
3316 			    NETIF_F_RXCSUM |
3317 			    NETIF_F_HW_CSUM;
3318 
3319 	if (hw->mac.type >= e1000_82576)
3320 		netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3321 
3322 	if (hw->mac.type >= e1000_i350)
3323 		netdev->features |= NETIF_F_HW_TC;
3324 
3325 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3326 				  NETIF_F_GSO_GRE_CSUM | \
3327 				  NETIF_F_GSO_IPXIP4 | \
3328 				  NETIF_F_GSO_IPXIP6 | \
3329 				  NETIF_F_GSO_UDP_TUNNEL | \
3330 				  NETIF_F_GSO_UDP_TUNNEL_CSUM)
3331 
3332 	netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3333 	netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3334 
3335 	/* copy netdev features into list of user selectable features */
3336 	netdev->hw_features |= netdev->features |
3337 			       NETIF_F_HW_VLAN_CTAG_RX |
3338 			       NETIF_F_HW_VLAN_CTAG_TX |
3339 			       NETIF_F_RXALL;
3340 
3341 	if (hw->mac.type >= e1000_i350)
3342 		netdev->hw_features |= NETIF_F_NTUPLE;
3343 
3344 	netdev->features |= NETIF_F_HIGHDMA;
3345 
3346 	netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3347 	netdev->mpls_features |= NETIF_F_HW_CSUM;
3348 	netdev->hw_enc_features |= netdev->vlan_features;
3349 
3350 	/* set this bit last since it cannot be part of vlan_features */
3351 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3352 			    NETIF_F_HW_VLAN_CTAG_RX |
3353 			    NETIF_F_HW_VLAN_CTAG_TX;
3354 
3355 	netdev->priv_flags |= IFF_SUPP_NOFCS;
3356 
3357 	netdev->priv_flags |= IFF_UNICAST_FLT;
3358 	netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT;
3359 
3360 	/* MTU range: 68 - 9216 */
3361 	netdev->min_mtu = ETH_MIN_MTU;
3362 	netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3363 
3364 	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3365 
3366 	/* before reading the NVM, reset the controller to put the device in a
3367 	 * known good starting state
3368 	 */
3369 	hw->mac.ops.reset_hw(hw);
3370 
3371 	/* make sure the NVM is good , i211/i210 parts can have special NVM
3372 	 * that doesn't contain a checksum
3373 	 */
3374 	switch (hw->mac.type) {
3375 	case e1000_i210:
3376 	case e1000_i211:
3377 		if (igb_get_flash_presence_i210(hw)) {
3378 			if (hw->nvm.ops.validate(hw) < 0) {
3379 				dev_err(&pdev->dev,
3380 					"The NVM Checksum Is Not Valid\n");
3381 				err = -EIO;
3382 				goto err_eeprom;
3383 			}
3384 		}
3385 		break;
3386 	default:
3387 		if (hw->nvm.ops.validate(hw) < 0) {
3388 			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3389 			err = -EIO;
3390 			goto err_eeprom;
3391 		}
3392 		break;
3393 	}
3394 
3395 	if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3396 		/* copy the MAC address out of the NVM */
3397 		if (hw->mac.ops.read_mac_addr(hw))
3398 			dev_err(&pdev->dev, "NVM Read Error\n");
3399 	}
3400 
3401 	eth_hw_addr_set(netdev, hw->mac.addr);
3402 
3403 	if (!is_valid_ether_addr(netdev->dev_addr)) {
3404 		dev_err(&pdev->dev, "Invalid MAC Address\n");
3405 		err = -EIO;
3406 		goto err_eeprom;
3407 	}
3408 
3409 	igb_set_default_mac_filter(adapter);
3410 
3411 	/* get firmware version for ethtool -i */
3412 	igb_set_fw_version(adapter);
3413 
3414 	/* configure RXPBSIZE and TXPBSIZE */
3415 	if (hw->mac.type == e1000_i210) {
3416 		wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3417 		wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3418 	}
3419 
3420 	timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3421 	timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3422 
3423 	INIT_WORK(&adapter->reset_task, igb_reset_task);
3424 	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3425 
3426 	/* Initialize link properties that are user-changeable */
3427 	adapter->fc_autoneg = true;
3428 	hw->mac.autoneg = true;
3429 	hw->phy.autoneg_advertised = 0x2f;
3430 
3431 	hw->fc.requested_mode = e1000_fc_default;
3432 	hw->fc.current_mode = e1000_fc_default;
3433 
3434 	igb_validate_mdi_setting(hw);
3435 
3436 	/* By default, support wake on port A */
3437 	if (hw->bus.func == 0)
3438 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3439 
3440 	/* Check the NVM for wake support on non-port A ports */
3441 	if (hw->mac.type >= e1000_82580)
3442 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3443 				 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3444 				 &eeprom_data);
3445 	else if (hw->bus.func == 1)
3446 		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3447 
3448 	if (eeprom_data & IGB_EEPROM_APME)
3449 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3450 
3451 	/* now that we have the eeprom settings, apply the special cases where
3452 	 * the eeprom may be wrong or the board simply won't support wake on
3453 	 * lan on a particular port
3454 	 */
3455 	switch (pdev->device) {
3456 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
3457 		adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3458 		break;
3459 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
3460 	case E1000_DEV_ID_82576_FIBER:
3461 	case E1000_DEV_ID_82576_SERDES:
3462 		/* Wake events only supported on port A for dual fiber
3463 		 * regardless of eeprom setting
3464 		 */
3465 		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3466 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3467 		break;
3468 	case E1000_DEV_ID_82576_QUAD_COPPER:
3469 	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3470 		/* if quad port adapter, disable WoL on all but port A */
3471 		if (global_quad_port_a != 0)
3472 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3473 		else
3474 			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3475 		/* Reset for multiple quad port adapters */
3476 		if (++global_quad_port_a == 4)
3477 			global_quad_port_a = 0;
3478 		break;
3479 	default:
3480 		/* If the device can't wake, don't set software support */
3481 		if (!device_can_wakeup(&adapter->pdev->dev))
3482 			adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3483 	}
3484 
3485 	/* initialize the wol settings based on the eeprom settings */
3486 	if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3487 		adapter->wol |= E1000_WUFC_MAG;
3488 
3489 	/* Some vendors want WoL disabled by default, but still supported */
3490 	if ((hw->mac.type == e1000_i350) &&
3491 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3492 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3493 		adapter->wol = 0;
3494 	}
3495 
3496 	/* Some vendors want the ability to Use the EEPROM setting as
3497 	 * enable/disable only, and not for capability
3498 	 */
3499 	if (((hw->mac.type == e1000_i350) ||
3500 	     (hw->mac.type == e1000_i354)) &&
3501 	    (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3502 		adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3503 		adapter->wol = 0;
3504 	}
3505 	if (hw->mac.type == e1000_i350) {
3506 		if (((pdev->subsystem_device == 0x5001) ||
3507 		     (pdev->subsystem_device == 0x5002)) &&
3508 				(hw->bus.func == 0)) {
3509 			adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3510 			adapter->wol = 0;
3511 		}
3512 		if (pdev->subsystem_device == 0x1F52)
3513 			adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3514 	}
3515 
3516 	device_set_wakeup_enable(&adapter->pdev->dev,
3517 				 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3518 
3519 	/* reset the hardware with the new settings */
3520 	igb_reset(adapter);
3521 
3522 	/* Init the I2C interface */
3523 	err = igb_init_i2c(adapter);
3524 	if (err) {
3525 		dev_err(&pdev->dev, "failed to init i2c interface\n");
3526 		goto err_eeprom;
3527 	}
3528 
3529 	/* let the f/w know that the h/w is now under the control of the
3530 	 * driver.
3531 	 */
3532 	igb_get_hw_control(adapter);
3533 
3534 	strcpy(netdev->name, "eth%d");
3535 	err = register_netdev(netdev);
3536 	if (err)
3537 		goto err_register;
3538 
3539 	/* carrier off reporting is important to ethtool even BEFORE open */
3540 	netif_carrier_off(netdev);
3541 
3542 #ifdef CONFIG_IGB_DCA
3543 	if (dca_add_requester(&pdev->dev) == 0) {
3544 		adapter->flags |= IGB_FLAG_DCA_ENABLED;
3545 		dev_info(&pdev->dev, "DCA enabled\n");
3546 		igb_setup_dca(adapter);
3547 	}
3548 
3549 #endif
3550 #ifdef CONFIG_IGB_HWMON
3551 	/* Initialize the thermal sensor on i350 devices. */
3552 	if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3553 		u16 ets_word;
3554 
3555 		/* Read the NVM to determine if this i350 device supports an
3556 		 * external thermal sensor.
3557 		 */
3558 		hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3559 		if (ets_word != 0x0000 && ets_word != 0xFFFF)
3560 			adapter->ets = true;
3561 		else
3562 			adapter->ets = false;
3563 		/* Only enable I2C bit banging if an external thermal
3564 		 * sensor is supported.
3565 		 */
3566 		if (adapter->ets)
3567 			igb_set_i2c_bb(hw);
3568 		hw->mac.ops.init_thermal_sensor_thresh(hw);
3569 		if (igb_sysfs_init(adapter))
3570 			dev_err(&pdev->dev,
3571 				"failed to allocate sysfs resources\n");
3572 	} else {
3573 		adapter->ets = false;
3574 	}
3575 #endif
3576 	/* Check if Media Autosense is enabled */
3577 	adapter->ei = *ei;
3578 	if (hw->dev_spec._82575.mas_capable)
3579 		igb_init_mas(adapter);
3580 
3581 	/* do hw tstamp init after resetting */
3582 	igb_ptp_init(adapter);
3583 
3584 	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3585 	/* print bus type/speed/width info, not applicable to i354 */
3586 	if (hw->mac.type != e1000_i354) {
3587 		dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3588 			 netdev->name,
3589 			 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3590 			  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3591 			   "unknown"),
3592 			 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3593 			  "Width x4" :
3594 			  (hw->bus.width == e1000_bus_width_pcie_x2) ?
3595 			  "Width x2" :
3596 			  (hw->bus.width == e1000_bus_width_pcie_x1) ?
3597 			  "Width x1" : "unknown"), netdev->dev_addr);
3598 	}
3599 
3600 	if ((hw->mac.type == e1000_82576 &&
3601 	     rd32(E1000_EECD) & E1000_EECD_PRES) ||
3602 	    (hw->mac.type >= e1000_i210 ||
3603 	     igb_get_flash_presence_i210(hw))) {
3604 		ret_val = igb_read_part_string(hw, part_str,
3605 					       E1000_PBANUM_LENGTH);
3606 	} else {
3607 		ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3608 	}
3609 
3610 	if (ret_val)
3611 		strcpy(part_str, "Unknown");
3612 	dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3613 	dev_info(&pdev->dev,
3614 		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3615 		(adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3616 		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3617 		adapter->num_rx_queues, adapter->num_tx_queues);
3618 	if (hw->phy.media_type == e1000_media_type_copper) {
3619 		switch (hw->mac.type) {
3620 		case e1000_i350:
3621 		case e1000_i210:
3622 		case e1000_i211:
3623 			/* Enable EEE for internal copper PHY devices */
3624 			err = igb_set_eee_i350(hw, true, true);
3625 			if ((!err) &&
3626 			    (!hw->dev_spec._82575.eee_disable)) {
3627 				adapter->eee_advert =
3628 					MDIO_EEE_100TX | MDIO_EEE_1000T;
3629 				adapter->flags |= IGB_FLAG_EEE;
3630 			}
3631 			break;
3632 		case e1000_i354:
3633 			if ((rd32(E1000_CTRL_EXT) &
3634 			    E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3635 				err = igb_set_eee_i354(hw, true, true);
3636 				if ((!err) &&
3637 					(!hw->dev_spec._82575.eee_disable)) {
3638 					adapter->eee_advert =
3639 					   MDIO_EEE_100TX | MDIO_EEE_1000T;
3640 					adapter->flags |= IGB_FLAG_EEE;
3641 				}
3642 			}
3643 			break;
3644 		default:
3645 			break;
3646 		}
3647 	}
3648 
3649 	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3650 
3651 	pm_runtime_put_noidle(&pdev->dev);
3652 	return 0;
3653 
3654 err_register:
3655 	igb_release_hw_control(adapter);
3656 	memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3657 err_eeprom:
3658 	if (!igb_check_reset_block(hw))
3659 		igb_reset_phy(hw);
3660 
3661 	if (hw->flash_address)
3662 		iounmap(hw->flash_address);
3663 err_sw_init:
3664 	kfree(adapter->mac_table);
3665 	kfree(adapter->shadow_vfta);
3666 	igb_clear_interrupt_scheme(adapter);
3667 #ifdef CONFIG_PCI_IOV
3668 	igb_disable_sriov(pdev, false);
3669 #endif
3670 	pci_iounmap(pdev, adapter->io_addr);
3671 err_ioremap:
3672 	free_netdev(netdev);
3673 err_alloc_etherdev:
3674 	pci_release_mem_regions(pdev);
3675 err_pci_reg:
3676 err_dma:
3677 	pci_disable_device(pdev);
3678 	return err;
3679 }
3680 
3681 #ifdef CONFIG_PCI_IOV
3682 static int igb_sriov_reinit(struct pci_dev *dev)
3683 {
3684 	struct net_device *netdev = pci_get_drvdata(dev);
3685 	struct igb_adapter *adapter = netdev_priv(netdev);
3686 	struct pci_dev *pdev = adapter->pdev;
3687 
3688 	rtnl_lock();
3689 
3690 	if (netif_running(netdev))
3691 		igb_close(netdev);
3692 	else
3693 		igb_reset(adapter);
3694 
3695 	igb_clear_interrupt_scheme(adapter);
3696 
3697 	igb_init_queue_configuration(adapter);
3698 
3699 	if (igb_init_interrupt_scheme(adapter, true)) {
3700 		rtnl_unlock();
3701 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3702 		return -ENOMEM;
3703 	}
3704 
3705 	if (netif_running(netdev))
3706 		igb_open(netdev);
3707 
3708 	rtnl_unlock();
3709 
3710 	return 0;
3711 }
3712 
3713 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit)
3714 {
3715 	struct net_device *netdev = pci_get_drvdata(pdev);
3716 	struct igb_adapter *adapter = netdev_priv(netdev);
3717 	struct e1000_hw *hw = &adapter->hw;
3718 	unsigned long flags;
3719 
3720 	/* reclaim resources allocated to VFs */
3721 	if (adapter->vf_data) {
3722 		/* disable iov and allow time for transactions to clear */
3723 		if (pci_vfs_assigned(pdev)) {
3724 			dev_warn(&pdev->dev,
3725 				 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3726 			return -EPERM;
3727 		} else {
3728 			pci_disable_sriov(pdev);
3729 			msleep(500);
3730 		}
3731 		spin_lock_irqsave(&adapter->vfs_lock, flags);
3732 		kfree(adapter->vf_mac_list);
3733 		adapter->vf_mac_list = NULL;
3734 		kfree(adapter->vf_data);
3735 		adapter->vf_data = NULL;
3736 		adapter->vfs_allocated_count = 0;
3737 		spin_unlock_irqrestore(&adapter->vfs_lock, flags);
3738 		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3739 		wrfl();
3740 		msleep(100);
3741 		dev_info(&pdev->dev, "IOV Disabled\n");
3742 
3743 		/* Re-enable DMA Coalescing flag since IOV is turned off */
3744 		adapter->flags |= IGB_FLAG_DMAC;
3745 	}
3746 
3747 	return reinit ? igb_sriov_reinit(pdev) : 0;
3748 }
3749 
3750 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit)
3751 {
3752 	struct net_device *netdev = pci_get_drvdata(pdev);
3753 	struct igb_adapter *adapter = netdev_priv(netdev);
3754 	int old_vfs = pci_num_vf(pdev);
3755 	struct vf_mac_filter *mac_list;
3756 	int err = 0;
3757 	int num_vf_mac_filters, i;
3758 
3759 	if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3760 		err = -EPERM;
3761 		goto out;
3762 	}
3763 	if (!num_vfs)
3764 		goto out;
3765 
3766 	if (old_vfs) {
3767 		dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3768 			 old_vfs, max_vfs);
3769 		adapter->vfs_allocated_count = old_vfs;
3770 	} else
3771 		adapter->vfs_allocated_count = num_vfs;
3772 
3773 	adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3774 				sizeof(struct vf_data_storage), GFP_KERNEL);
3775 
3776 	/* if allocation failed then we do not support SR-IOV */
3777 	if (!adapter->vf_data) {
3778 		adapter->vfs_allocated_count = 0;
3779 		err = -ENOMEM;
3780 		goto out;
3781 	}
3782 
3783 	/* Due to the limited number of RAR entries calculate potential
3784 	 * number of MAC filters available for the VFs. Reserve entries
3785 	 * for PF default MAC, PF MAC filters and at least one RAR entry
3786 	 * for each VF for VF MAC.
3787 	 */
3788 	num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3789 			     (1 + IGB_PF_MAC_FILTERS_RESERVED +
3790 			      adapter->vfs_allocated_count);
3791 
3792 	adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3793 				       sizeof(struct vf_mac_filter),
3794 				       GFP_KERNEL);
3795 
3796 	mac_list = adapter->vf_mac_list;
3797 	INIT_LIST_HEAD(&adapter->vf_macs.l);
3798 
3799 	if (adapter->vf_mac_list) {
3800 		/* Initialize list of VF MAC filters */
3801 		for (i = 0; i < num_vf_mac_filters; i++) {
3802 			mac_list->vf = -1;
3803 			mac_list->free = true;
3804 			list_add(&mac_list->l, &adapter->vf_macs.l);
3805 			mac_list++;
3806 		}
3807 	} else {
3808 		/* If we could not allocate memory for the VF MAC filters
3809 		 * we can continue without this feature but warn user.
3810 		 */
3811 		dev_err(&pdev->dev,
3812 			"Unable to allocate memory for VF MAC filter list\n");
3813 	}
3814 
3815 	dev_info(&pdev->dev, "%d VFs allocated\n",
3816 		 adapter->vfs_allocated_count);
3817 	for (i = 0; i < adapter->vfs_allocated_count; i++)
3818 		igb_vf_configure(adapter, i);
3819 
3820 	/* DMA Coalescing is not supported in IOV mode. */
3821 	adapter->flags &= ~IGB_FLAG_DMAC;
3822 
3823 	if (reinit) {
3824 		err = igb_sriov_reinit(pdev);
3825 		if (err)
3826 			goto err_out;
3827 	}
3828 
3829 	/* only call pci_enable_sriov() if no VFs are allocated already */
3830 	if (!old_vfs) {
3831 		err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3832 		if (err)
3833 			goto err_out;
3834 	}
3835 
3836 	goto out;
3837 
3838 err_out:
3839 	kfree(adapter->vf_mac_list);
3840 	adapter->vf_mac_list = NULL;
3841 	kfree(adapter->vf_data);
3842 	adapter->vf_data = NULL;
3843 	adapter->vfs_allocated_count = 0;
3844 out:
3845 	return err;
3846 }
3847 
3848 #endif
3849 /**
3850  *  igb_remove_i2c - Cleanup  I2C interface
3851  *  @adapter: pointer to adapter structure
3852  **/
3853 static void igb_remove_i2c(struct igb_adapter *adapter)
3854 {
3855 	/* free the adapter bus structure */
3856 	i2c_del_adapter(&adapter->i2c_adap);
3857 }
3858 
3859 /**
3860  *  igb_remove - Device Removal Routine
3861  *  @pdev: PCI device information struct
3862  *
3863  *  igb_remove is called by the PCI subsystem to alert the driver
3864  *  that it should release a PCI device.  The could be caused by a
3865  *  Hot-Plug event, or because the driver is going to be removed from
3866  *  memory.
3867  **/
3868 static void igb_remove(struct pci_dev *pdev)
3869 {
3870 	struct net_device *netdev = pci_get_drvdata(pdev);
3871 	struct igb_adapter *adapter = netdev_priv(netdev);
3872 	struct e1000_hw *hw = &adapter->hw;
3873 
3874 	pm_runtime_get_noresume(&pdev->dev);
3875 #ifdef CONFIG_IGB_HWMON
3876 	igb_sysfs_exit(adapter);
3877 #endif
3878 	igb_remove_i2c(adapter);
3879 	igb_ptp_stop(adapter);
3880 	/* The watchdog timer may be rescheduled, so explicitly
3881 	 * disable watchdog from being rescheduled.
3882 	 */
3883 	set_bit(__IGB_DOWN, &adapter->state);
3884 	del_timer_sync(&adapter->watchdog_timer);
3885 	del_timer_sync(&adapter->phy_info_timer);
3886 
3887 	cancel_work_sync(&adapter->reset_task);
3888 	cancel_work_sync(&adapter->watchdog_task);
3889 
3890 #ifdef CONFIG_IGB_DCA
3891 	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3892 		dev_info(&pdev->dev, "DCA disabled\n");
3893 		dca_remove_requester(&pdev->dev);
3894 		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3895 		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3896 	}
3897 #endif
3898 
3899 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
3900 	 * would have already happened in close and is redundant.
3901 	 */
3902 	igb_release_hw_control(adapter);
3903 
3904 #ifdef CONFIG_PCI_IOV
3905 	igb_disable_sriov(pdev, false);
3906 #endif
3907 
3908 	unregister_netdev(netdev);
3909 
3910 	igb_clear_interrupt_scheme(adapter);
3911 
3912 	pci_iounmap(pdev, adapter->io_addr);
3913 	if (hw->flash_address)
3914 		iounmap(hw->flash_address);
3915 	pci_release_mem_regions(pdev);
3916 
3917 	kfree(adapter->mac_table);
3918 	kfree(adapter->shadow_vfta);
3919 	free_netdev(netdev);
3920 
3921 	pci_disable_device(pdev);
3922 }
3923 
3924 /**
3925  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3926  *  @adapter: board private structure to initialize
3927  *
3928  *  This function initializes the vf specific data storage and then attempts to
3929  *  allocate the VFs.  The reason for ordering it this way is because it is much
3930  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
3931  *  the memory for the VFs.
3932  **/
3933 static void igb_probe_vfs(struct igb_adapter *adapter)
3934 {
3935 #ifdef CONFIG_PCI_IOV
3936 	struct pci_dev *pdev = adapter->pdev;
3937 	struct e1000_hw *hw = &adapter->hw;
3938 
3939 	/* Virtualization features not supported on i210 and 82580 family. */
3940 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) ||
3941 	    (hw->mac.type == e1000_82580))
3942 		return;
3943 
3944 	/* Of the below we really only want the effect of getting
3945 	 * IGB_FLAG_HAS_MSIX set (if available), without which
3946 	 * igb_enable_sriov() has no effect.
3947 	 */
3948 	igb_set_interrupt_capability(adapter, true);
3949 	igb_reset_interrupt_capability(adapter);
3950 
3951 	pci_sriov_set_totalvfs(pdev, 7);
3952 	igb_enable_sriov(pdev, max_vfs, false);
3953 
3954 #endif /* CONFIG_PCI_IOV */
3955 }
3956 
3957 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3958 {
3959 	struct e1000_hw *hw = &adapter->hw;
3960 	unsigned int max_rss_queues;
3961 
3962 	/* Determine the maximum number of RSS queues supported. */
3963 	switch (hw->mac.type) {
3964 	case e1000_i211:
3965 		max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3966 		break;
3967 	case e1000_82575:
3968 	case e1000_i210:
3969 		max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3970 		break;
3971 	case e1000_i350:
3972 		/* I350 cannot do RSS and SR-IOV at the same time */
3973 		if (!!adapter->vfs_allocated_count) {
3974 			max_rss_queues = 1;
3975 			break;
3976 		}
3977 		fallthrough;
3978 	case e1000_82576:
3979 		if (!!adapter->vfs_allocated_count) {
3980 			max_rss_queues = 2;
3981 			break;
3982 		}
3983 		fallthrough;
3984 	case e1000_82580:
3985 	case e1000_i354:
3986 	default:
3987 		max_rss_queues = IGB_MAX_RX_QUEUES;
3988 		break;
3989 	}
3990 
3991 	return max_rss_queues;
3992 }
3993 
3994 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3995 {
3996 	u32 max_rss_queues;
3997 
3998 	max_rss_queues = igb_get_max_rss_queues(adapter);
3999 	adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
4000 
4001 	igb_set_flag_queue_pairs(adapter, max_rss_queues);
4002 }
4003 
4004 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
4005 			      const u32 max_rss_queues)
4006 {
4007 	struct e1000_hw *hw = &adapter->hw;
4008 
4009 	/* Determine if we need to pair queues. */
4010 	switch (hw->mac.type) {
4011 	case e1000_82575:
4012 	case e1000_i211:
4013 		/* Device supports enough interrupts without queue pairing. */
4014 		break;
4015 	case e1000_82576:
4016 	case e1000_82580:
4017 	case e1000_i350:
4018 	case e1000_i354:
4019 	case e1000_i210:
4020 	default:
4021 		/* If rss_queues > half of max_rss_queues, pair the queues in
4022 		 * order to conserve interrupts due to limited supply.
4023 		 */
4024 		if (adapter->rss_queues > (max_rss_queues / 2))
4025 			adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
4026 		else
4027 			adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
4028 		break;
4029 	}
4030 }
4031 
4032 /**
4033  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
4034  *  @adapter: board private structure to initialize
4035  *
4036  *  igb_sw_init initializes the Adapter private data structure.
4037  *  Fields are initialized based on PCI device information and
4038  *  OS network device settings (MTU size).
4039  **/
4040 static int igb_sw_init(struct igb_adapter *adapter)
4041 {
4042 	struct e1000_hw *hw = &adapter->hw;
4043 	struct net_device *netdev = adapter->netdev;
4044 	struct pci_dev *pdev = adapter->pdev;
4045 
4046 	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
4047 
4048 	/* set default ring sizes */
4049 	adapter->tx_ring_count = IGB_DEFAULT_TXD;
4050 	adapter->rx_ring_count = IGB_DEFAULT_RXD;
4051 
4052 	/* set default ITR values */
4053 	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
4054 	adapter->tx_itr_setting = IGB_DEFAULT_ITR;
4055 
4056 	/* set default work limits */
4057 	adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
4058 
4059 	adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
4060 	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4061 
4062 	spin_lock_init(&adapter->nfc_lock);
4063 	spin_lock_init(&adapter->stats64_lock);
4064 
4065 	/* init spinlock to avoid concurrency of VF resources */
4066 	spin_lock_init(&adapter->vfs_lock);
4067 #ifdef CONFIG_PCI_IOV
4068 	switch (hw->mac.type) {
4069 	case e1000_82576:
4070 	case e1000_i350:
4071 		if (max_vfs > 7) {
4072 			dev_warn(&pdev->dev,
4073 				 "Maximum of 7 VFs per PF, using max\n");
4074 			max_vfs = adapter->vfs_allocated_count = 7;
4075 		} else
4076 			adapter->vfs_allocated_count = max_vfs;
4077 		if (adapter->vfs_allocated_count)
4078 			dev_warn(&pdev->dev,
4079 				 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
4080 		break;
4081 	default:
4082 		break;
4083 	}
4084 #endif /* CONFIG_PCI_IOV */
4085 
4086 	/* Assume MSI-X interrupts, will be checked during IRQ allocation */
4087 	adapter->flags |= IGB_FLAG_HAS_MSIX;
4088 
4089 	adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4090 				     sizeof(struct igb_mac_addr),
4091 				     GFP_KERNEL);
4092 	if (!adapter->mac_table)
4093 		return -ENOMEM;
4094 
4095 	igb_probe_vfs(adapter);
4096 
4097 	igb_init_queue_configuration(adapter);
4098 
4099 	/* Setup and initialize a copy of the hw vlan table array */
4100 	adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4101 				       GFP_KERNEL);
4102 	if (!adapter->shadow_vfta)
4103 		return -ENOMEM;
4104 
4105 	/* This call may decrease the number of queues */
4106 	if (igb_init_interrupt_scheme(adapter, true)) {
4107 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4108 		return -ENOMEM;
4109 	}
4110 
4111 	/* Explicitly disable IRQ since the NIC can be in any state. */
4112 	igb_irq_disable(adapter);
4113 
4114 	if (hw->mac.type >= e1000_i350)
4115 		adapter->flags &= ~IGB_FLAG_DMAC;
4116 
4117 	set_bit(__IGB_DOWN, &adapter->state);
4118 	return 0;
4119 }
4120 
4121 /**
4122  *  __igb_open - Called when a network interface is made active
4123  *  @netdev: network interface device structure
4124  *  @resuming: indicates whether we are in a resume call
4125  *
4126  *  Returns 0 on success, negative value on failure
4127  *
4128  *  The open entry point is called when a network interface is made
4129  *  active by the system (IFF_UP).  At this point all resources needed
4130  *  for transmit and receive operations are allocated, the interrupt
4131  *  handler is registered with the OS, the watchdog timer is started,
4132  *  and the stack is notified that the interface is ready.
4133  **/
4134 static int __igb_open(struct net_device *netdev, bool resuming)
4135 {
4136 	struct igb_adapter *adapter = netdev_priv(netdev);
4137 	struct e1000_hw *hw = &adapter->hw;
4138 	struct pci_dev *pdev = adapter->pdev;
4139 	int err;
4140 	int i;
4141 
4142 	/* disallow open during test */
4143 	if (test_bit(__IGB_TESTING, &adapter->state)) {
4144 		WARN_ON(resuming);
4145 		return -EBUSY;
4146 	}
4147 
4148 	if (!resuming)
4149 		pm_runtime_get_sync(&pdev->dev);
4150 
4151 	netif_carrier_off(netdev);
4152 
4153 	/* allocate transmit descriptors */
4154 	err = igb_setup_all_tx_resources(adapter);
4155 	if (err)
4156 		goto err_setup_tx;
4157 
4158 	/* allocate receive descriptors */
4159 	err = igb_setup_all_rx_resources(adapter);
4160 	if (err)
4161 		goto err_setup_rx;
4162 
4163 	igb_power_up_link(adapter);
4164 
4165 	/* before we allocate an interrupt, we must be ready to handle it.
4166 	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4167 	 * as soon as we call pci_request_irq, so we have to setup our
4168 	 * clean_rx handler before we do so.
4169 	 */
4170 	igb_configure(adapter);
4171 
4172 	err = igb_request_irq(adapter);
4173 	if (err)
4174 		goto err_req_irq;
4175 
4176 	/* Notify the stack of the actual queue counts. */
4177 	err = netif_set_real_num_tx_queues(adapter->netdev,
4178 					   adapter->num_tx_queues);
4179 	if (err)
4180 		goto err_set_queues;
4181 
4182 	err = netif_set_real_num_rx_queues(adapter->netdev,
4183 					   adapter->num_rx_queues);
4184 	if (err)
4185 		goto err_set_queues;
4186 
4187 	/* From here on the code is the same as igb_up() */
4188 	clear_bit(__IGB_DOWN, &adapter->state);
4189 
4190 	for (i = 0; i < adapter->num_q_vectors; i++)
4191 		napi_enable(&(adapter->q_vector[i]->napi));
4192 
4193 	/* Clear any pending interrupts. */
4194 	rd32(E1000_TSICR);
4195 	rd32(E1000_ICR);
4196 
4197 	igb_irq_enable(adapter);
4198 
4199 	/* notify VFs that reset has been completed */
4200 	if (adapter->vfs_allocated_count) {
4201 		u32 reg_data = rd32(E1000_CTRL_EXT);
4202 
4203 		reg_data |= E1000_CTRL_EXT_PFRSTD;
4204 		wr32(E1000_CTRL_EXT, reg_data);
4205 	}
4206 
4207 	netif_tx_start_all_queues(netdev);
4208 
4209 	if (!resuming)
4210 		pm_runtime_put(&pdev->dev);
4211 
4212 	/* start the watchdog. */
4213 	hw->mac.get_link_status = 1;
4214 	schedule_work(&adapter->watchdog_task);
4215 
4216 	return 0;
4217 
4218 err_set_queues:
4219 	igb_free_irq(adapter);
4220 err_req_irq:
4221 	igb_release_hw_control(adapter);
4222 	igb_power_down_link(adapter);
4223 	igb_free_all_rx_resources(adapter);
4224 err_setup_rx:
4225 	igb_free_all_tx_resources(adapter);
4226 err_setup_tx:
4227 	igb_reset(adapter);
4228 	if (!resuming)
4229 		pm_runtime_put(&pdev->dev);
4230 
4231 	return err;
4232 }
4233 
4234 int igb_open(struct net_device *netdev)
4235 {
4236 	return __igb_open(netdev, false);
4237 }
4238 
4239 /**
4240  *  __igb_close - Disables a network interface
4241  *  @netdev: network interface device structure
4242  *  @suspending: indicates we are in a suspend call
4243  *
4244  *  Returns 0, this is not allowed to fail
4245  *
4246  *  The close entry point is called when an interface is de-activated
4247  *  by the OS.  The hardware is still under the driver's control, but
4248  *  needs to be disabled.  A global MAC reset is issued to stop the
4249  *  hardware, and all transmit and receive resources are freed.
4250  **/
4251 static int __igb_close(struct net_device *netdev, bool suspending)
4252 {
4253 	struct igb_adapter *adapter = netdev_priv(netdev);
4254 	struct pci_dev *pdev = adapter->pdev;
4255 
4256 	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4257 
4258 	if (!suspending)
4259 		pm_runtime_get_sync(&pdev->dev);
4260 
4261 	igb_down(adapter);
4262 	igb_free_irq(adapter);
4263 
4264 	igb_free_all_tx_resources(adapter);
4265 	igb_free_all_rx_resources(adapter);
4266 
4267 	if (!suspending)
4268 		pm_runtime_put_sync(&pdev->dev);
4269 	return 0;
4270 }
4271 
4272 int igb_close(struct net_device *netdev)
4273 {
4274 	if (netif_device_present(netdev) || netdev->dismantle)
4275 		return __igb_close(netdev, false);
4276 	return 0;
4277 }
4278 
4279 /**
4280  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
4281  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
4282  *
4283  *  Return 0 on success, negative on failure
4284  **/
4285 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4286 {
4287 	struct device *dev = tx_ring->dev;
4288 	int size;
4289 
4290 	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4291 
4292 	tx_ring->tx_buffer_info = vmalloc(size);
4293 	if (!tx_ring->tx_buffer_info)
4294 		goto err;
4295 
4296 	/* round up to nearest 4K */
4297 	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4298 	tx_ring->size = ALIGN(tx_ring->size, 4096);
4299 
4300 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4301 					   &tx_ring->dma, GFP_KERNEL);
4302 	if (!tx_ring->desc)
4303 		goto err;
4304 
4305 	tx_ring->next_to_use = 0;
4306 	tx_ring->next_to_clean = 0;
4307 
4308 	return 0;
4309 
4310 err:
4311 	vfree(tx_ring->tx_buffer_info);
4312 	tx_ring->tx_buffer_info = NULL;
4313 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4314 	return -ENOMEM;
4315 }
4316 
4317 /**
4318  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
4319  *				 (Descriptors) for all queues
4320  *  @adapter: board private structure
4321  *
4322  *  Return 0 on success, negative on failure
4323  **/
4324 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4325 {
4326 	struct pci_dev *pdev = adapter->pdev;
4327 	int i, err = 0;
4328 
4329 	for (i = 0; i < adapter->num_tx_queues; i++) {
4330 		err = igb_setup_tx_resources(adapter->tx_ring[i]);
4331 		if (err) {
4332 			dev_err(&pdev->dev,
4333 				"Allocation for Tx Queue %u failed\n", i);
4334 			for (i--; i >= 0; i--)
4335 				igb_free_tx_resources(adapter->tx_ring[i]);
4336 			break;
4337 		}
4338 	}
4339 
4340 	return err;
4341 }
4342 
4343 /**
4344  *  igb_setup_tctl - configure the transmit control registers
4345  *  @adapter: Board private structure
4346  **/
4347 void igb_setup_tctl(struct igb_adapter *adapter)
4348 {
4349 	struct e1000_hw *hw = &adapter->hw;
4350 	u32 tctl;
4351 
4352 	/* disable queue 0 which is enabled by default on 82575 and 82576 */
4353 	wr32(E1000_TXDCTL(0), 0);
4354 
4355 	/* Program the Transmit Control Register */
4356 	tctl = rd32(E1000_TCTL);
4357 	tctl &= ~E1000_TCTL_CT;
4358 	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4359 		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4360 
4361 	igb_config_collision_dist(hw);
4362 
4363 	/* Enable transmits */
4364 	tctl |= E1000_TCTL_EN;
4365 
4366 	wr32(E1000_TCTL, tctl);
4367 }
4368 
4369 /**
4370  *  igb_configure_tx_ring - Configure transmit ring after Reset
4371  *  @adapter: board private structure
4372  *  @ring: tx ring to configure
4373  *
4374  *  Configure a transmit ring after a reset.
4375  **/
4376 void igb_configure_tx_ring(struct igb_adapter *adapter,
4377 			   struct igb_ring *ring)
4378 {
4379 	struct e1000_hw *hw = &adapter->hw;
4380 	u32 txdctl = 0;
4381 	u64 tdba = ring->dma;
4382 	int reg_idx = ring->reg_idx;
4383 
4384 	wr32(E1000_TDLEN(reg_idx),
4385 	     ring->count * sizeof(union e1000_adv_tx_desc));
4386 	wr32(E1000_TDBAL(reg_idx),
4387 	     tdba & 0x00000000ffffffffULL);
4388 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4389 
4390 	ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4391 	wr32(E1000_TDH(reg_idx), 0);
4392 	writel(0, ring->tail);
4393 
4394 	txdctl |= IGB_TX_PTHRESH;
4395 	txdctl |= IGB_TX_HTHRESH << 8;
4396 	txdctl |= IGB_TX_WTHRESH << 16;
4397 
4398 	/* reinitialize tx_buffer_info */
4399 	memset(ring->tx_buffer_info, 0,
4400 	       sizeof(struct igb_tx_buffer) * ring->count);
4401 
4402 	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4403 	wr32(E1000_TXDCTL(reg_idx), txdctl);
4404 }
4405 
4406 /**
4407  *  igb_configure_tx - Configure transmit Unit after Reset
4408  *  @adapter: board private structure
4409  *
4410  *  Configure the Tx unit of the MAC after a reset.
4411  **/
4412 static void igb_configure_tx(struct igb_adapter *adapter)
4413 {
4414 	struct e1000_hw *hw = &adapter->hw;
4415 	int i;
4416 
4417 	/* disable the queues */
4418 	for (i = 0; i < adapter->num_tx_queues; i++)
4419 		wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4420 
4421 	wrfl();
4422 	usleep_range(10000, 20000);
4423 
4424 	for (i = 0; i < adapter->num_tx_queues; i++)
4425 		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4426 }
4427 
4428 /**
4429  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
4430  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
4431  *
4432  *  Returns 0 on success, negative on failure
4433  **/
4434 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4435 {
4436 	struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4437 	struct device *dev = rx_ring->dev;
4438 	int size, res;
4439 
4440 	/* XDP RX-queue info */
4441 	if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
4442 		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4443 	res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4444 			       rx_ring->queue_index, 0);
4445 	if (res < 0) {
4446 		dev_err(dev, "Failed to register xdp_rxq index %u\n",
4447 			rx_ring->queue_index);
4448 		return res;
4449 	}
4450 
4451 	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4452 
4453 	rx_ring->rx_buffer_info = vmalloc(size);
4454 	if (!rx_ring->rx_buffer_info)
4455 		goto err;
4456 
4457 	/* Round up to nearest 4K */
4458 	rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4459 	rx_ring->size = ALIGN(rx_ring->size, 4096);
4460 
4461 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4462 					   &rx_ring->dma, GFP_KERNEL);
4463 	if (!rx_ring->desc)
4464 		goto err;
4465 
4466 	rx_ring->next_to_alloc = 0;
4467 	rx_ring->next_to_clean = 0;
4468 	rx_ring->next_to_use = 0;
4469 
4470 	rx_ring->xdp_prog = adapter->xdp_prog;
4471 
4472 	return 0;
4473 
4474 err:
4475 	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4476 	vfree(rx_ring->rx_buffer_info);
4477 	rx_ring->rx_buffer_info = NULL;
4478 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4479 	return -ENOMEM;
4480 }
4481 
4482 /**
4483  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
4484  *				 (Descriptors) for all queues
4485  *  @adapter: board private structure
4486  *
4487  *  Return 0 on success, negative on failure
4488  **/
4489 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4490 {
4491 	struct pci_dev *pdev = adapter->pdev;
4492 	int i, err = 0;
4493 
4494 	for (i = 0; i < adapter->num_rx_queues; i++) {
4495 		err = igb_setup_rx_resources(adapter->rx_ring[i]);
4496 		if (err) {
4497 			dev_err(&pdev->dev,
4498 				"Allocation for Rx Queue %u failed\n", i);
4499 			for (i--; i >= 0; i--)
4500 				igb_free_rx_resources(adapter->rx_ring[i]);
4501 			break;
4502 		}
4503 	}
4504 
4505 	return err;
4506 }
4507 
4508 /**
4509  *  igb_setup_mrqc - configure the multiple receive queue control registers
4510  *  @adapter: Board private structure
4511  **/
4512 static void igb_setup_mrqc(struct igb_adapter *adapter)
4513 {
4514 	struct e1000_hw *hw = &adapter->hw;
4515 	u32 mrqc, rxcsum;
4516 	u32 j, num_rx_queues;
4517 	u32 rss_key[10];
4518 
4519 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
4520 	for (j = 0; j < 10; j++)
4521 		wr32(E1000_RSSRK(j), rss_key[j]);
4522 
4523 	num_rx_queues = adapter->rss_queues;
4524 
4525 	switch (hw->mac.type) {
4526 	case e1000_82576:
4527 		/* 82576 supports 2 RSS queues for SR-IOV */
4528 		if (adapter->vfs_allocated_count)
4529 			num_rx_queues = 2;
4530 		break;
4531 	default:
4532 		break;
4533 	}
4534 
4535 	if (adapter->rss_indir_tbl_init != num_rx_queues) {
4536 		for (j = 0; j < IGB_RETA_SIZE; j++)
4537 			adapter->rss_indir_tbl[j] =
4538 			(j * num_rx_queues) / IGB_RETA_SIZE;
4539 		adapter->rss_indir_tbl_init = num_rx_queues;
4540 	}
4541 	igb_write_rss_indir_tbl(adapter);
4542 
4543 	/* Disable raw packet checksumming so that RSS hash is placed in
4544 	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
4545 	 * offloads as they are enabled by default
4546 	 */
4547 	rxcsum = rd32(E1000_RXCSUM);
4548 	rxcsum |= E1000_RXCSUM_PCSD;
4549 
4550 	if (adapter->hw.mac.type >= e1000_82576)
4551 		/* Enable Receive Checksum Offload for SCTP */
4552 		rxcsum |= E1000_RXCSUM_CRCOFL;
4553 
4554 	/* Don't need to set TUOFL or IPOFL, they default to 1 */
4555 	wr32(E1000_RXCSUM, rxcsum);
4556 
4557 	/* Generate RSS hash based on packet types, TCP/UDP
4558 	 * port numbers and/or IPv4/v6 src and dst addresses
4559 	 */
4560 	mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4561 	       E1000_MRQC_RSS_FIELD_IPV4_TCP |
4562 	       E1000_MRQC_RSS_FIELD_IPV6 |
4563 	       E1000_MRQC_RSS_FIELD_IPV6_TCP |
4564 	       E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4565 
4566 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4567 		mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4568 	if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4569 		mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4570 
4571 	/* If VMDq is enabled then we set the appropriate mode for that, else
4572 	 * we default to RSS so that an RSS hash is calculated per packet even
4573 	 * if we are only using one queue
4574 	 */
4575 	if (adapter->vfs_allocated_count) {
4576 		if (hw->mac.type > e1000_82575) {
4577 			/* Set the default pool for the PF's first queue */
4578 			u32 vtctl = rd32(E1000_VT_CTL);
4579 
4580 			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4581 				   E1000_VT_CTL_DISABLE_DEF_POOL);
4582 			vtctl |= adapter->vfs_allocated_count <<
4583 				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4584 			wr32(E1000_VT_CTL, vtctl);
4585 		}
4586 		if (adapter->rss_queues > 1)
4587 			mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4588 		else
4589 			mrqc |= E1000_MRQC_ENABLE_VMDQ;
4590 	} else {
4591 		mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4592 	}
4593 	igb_vmm_control(adapter);
4594 
4595 	wr32(E1000_MRQC, mrqc);
4596 }
4597 
4598 /**
4599  *  igb_setup_rctl - configure the receive control registers
4600  *  @adapter: Board private structure
4601  **/
4602 void igb_setup_rctl(struct igb_adapter *adapter)
4603 {
4604 	struct e1000_hw *hw = &adapter->hw;
4605 	u32 rctl;
4606 
4607 	rctl = rd32(E1000_RCTL);
4608 
4609 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4610 	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4611 
4612 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4613 		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4614 
4615 	/* enable stripping of CRC. It's unlikely this will break BMC
4616 	 * redirection as it did with e1000. Newer features require
4617 	 * that the HW strips the CRC.
4618 	 */
4619 	rctl |= E1000_RCTL_SECRC;
4620 
4621 	/* disable store bad packets and clear size bits. */
4622 	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4623 
4624 	/* enable LPE to allow for reception of jumbo frames */
4625 	rctl |= E1000_RCTL_LPE;
4626 
4627 	/* disable queue 0 to prevent tail write w/o re-config */
4628 	wr32(E1000_RXDCTL(0), 0);
4629 
4630 	/* Attention!!!  For SR-IOV PF driver operations you must enable
4631 	 * queue drop for all VF and PF queues to prevent head of line blocking
4632 	 * if an un-trusted VF does not provide descriptors to hardware.
4633 	 */
4634 	if (adapter->vfs_allocated_count) {
4635 		/* set all queue drop enable bits */
4636 		wr32(E1000_QDE, ALL_QUEUES);
4637 	}
4638 
4639 	/* This is useful for sniffing bad packets. */
4640 	if (adapter->netdev->features & NETIF_F_RXALL) {
4641 		/* UPE and MPE will be handled by normal PROMISC logic
4642 		 * in e1000e_set_rx_mode
4643 		 */
4644 		rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4645 			 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4646 			 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4647 
4648 		rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4649 			  E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4650 		/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4651 		 * and that breaks VLANs.
4652 		 */
4653 	}
4654 
4655 	wr32(E1000_RCTL, rctl);
4656 }
4657 
4658 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4659 				   int vfn)
4660 {
4661 	struct e1000_hw *hw = &adapter->hw;
4662 	u32 vmolr;
4663 
4664 	if (size > MAX_JUMBO_FRAME_SIZE)
4665 		size = MAX_JUMBO_FRAME_SIZE;
4666 
4667 	vmolr = rd32(E1000_VMOLR(vfn));
4668 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
4669 	vmolr |= size | E1000_VMOLR_LPE;
4670 	wr32(E1000_VMOLR(vfn), vmolr);
4671 
4672 	return 0;
4673 }
4674 
4675 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4676 					 int vfn, bool enable)
4677 {
4678 	struct e1000_hw *hw = &adapter->hw;
4679 	u32 val, reg;
4680 
4681 	if (hw->mac.type < e1000_82576)
4682 		return;
4683 
4684 	if (hw->mac.type == e1000_i350)
4685 		reg = E1000_DVMOLR(vfn);
4686 	else
4687 		reg = E1000_VMOLR(vfn);
4688 
4689 	val = rd32(reg);
4690 	if (enable)
4691 		val |= E1000_VMOLR_STRVLAN;
4692 	else
4693 		val &= ~(E1000_VMOLR_STRVLAN);
4694 	wr32(reg, val);
4695 }
4696 
4697 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4698 				 int vfn, bool aupe)
4699 {
4700 	struct e1000_hw *hw = &adapter->hw;
4701 	u32 vmolr;
4702 
4703 	/* This register exists only on 82576 and newer so if we are older then
4704 	 * we should exit and do nothing
4705 	 */
4706 	if (hw->mac.type < e1000_82576)
4707 		return;
4708 
4709 	vmolr = rd32(E1000_VMOLR(vfn));
4710 	if (aupe)
4711 		vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4712 	else
4713 		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4714 
4715 	/* clear all bits that might not be set */
4716 	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4717 
4718 	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4719 		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4720 	/* for VMDq only allow the VFs and pool 0 to accept broadcast and
4721 	 * multicast packets
4722 	 */
4723 	if (vfn <= adapter->vfs_allocated_count)
4724 		vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4725 
4726 	wr32(E1000_VMOLR(vfn), vmolr);
4727 }
4728 
4729 /**
4730  *  igb_setup_srrctl - configure the split and replication receive control
4731  *                     registers
4732  *  @adapter: Board private structure
4733  *  @ring: receive ring to be configured
4734  **/
4735 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4736 {
4737 	struct e1000_hw *hw = &adapter->hw;
4738 	int reg_idx = ring->reg_idx;
4739 	u32 srrctl = 0;
4740 
4741 	srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4742 	if (ring_uses_large_buffer(ring))
4743 		srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4744 	else
4745 		srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4746 	srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4747 	if (hw->mac.type >= e1000_82580)
4748 		srrctl |= E1000_SRRCTL_TIMESTAMP;
4749 	/* Only set Drop Enable if VFs allocated, or we are supporting multiple
4750 	 * queues and rx flow control is disabled
4751 	 */
4752 	if (adapter->vfs_allocated_count ||
4753 	    (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4754 	     adapter->num_rx_queues > 1))
4755 		srrctl |= E1000_SRRCTL_DROP_EN;
4756 
4757 	wr32(E1000_SRRCTL(reg_idx), srrctl);
4758 }
4759 
4760 /**
4761  *  igb_configure_rx_ring - Configure a receive ring after Reset
4762  *  @adapter: board private structure
4763  *  @ring: receive ring to be configured
4764  *
4765  *  Configure the Rx unit of the MAC after a reset.
4766  **/
4767 void igb_configure_rx_ring(struct igb_adapter *adapter,
4768 			   struct igb_ring *ring)
4769 {
4770 	struct e1000_hw *hw = &adapter->hw;
4771 	union e1000_adv_rx_desc *rx_desc;
4772 	u64 rdba = ring->dma;
4773 	int reg_idx = ring->reg_idx;
4774 	u32 rxdctl = 0;
4775 
4776 	xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4777 	WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4778 					   MEM_TYPE_PAGE_SHARED, NULL));
4779 
4780 	/* disable the queue */
4781 	wr32(E1000_RXDCTL(reg_idx), 0);
4782 
4783 	/* Set DMA base address registers */
4784 	wr32(E1000_RDBAL(reg_idx),
4785 	     rdba & 0x00000000ffffffffULL);
4786 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4787 	wr32(E1000_RDLEN(reg_idx),
4788 	     ring->count * sizeof(union e1000_adv_rx_desc));
4789 
4790 	/* initialize head and tail */
4791 	ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4792 	wr32(E1000_RDH(reg_idx), 0);
4793 	writel(0, ring->tail);
4794 
4795 	/* set descriptor configuration */
4796 	igb_setup_srrctl(adapter, ring);
4797 
4798 	/* set filtering for VMDQ pools */
4799 	igb_set_vmolr(adapter, reg_idx & 0x7, true);
4800 
4801 	rxdctl |= IGB_RX_PTHRESH;
4802 	rxdctl |= IGB_RX_HTHRESH << 8;
4803 	rxdctl |= IGB_RX_WTHRESH << 16;
4804 
4805 	/* initialize rx_buffer_info */
4806 	memset(ring->rx_buffer_info, 0,
4807 	       sizeof(struct igb_rx_buffer) * ring->count);
4808 
4809 	/* initialize Rx descriptor 0 */
4810 	rx_desc = IGB_RX_DESC(ring, 0);
4811 	rx_desc->wb.upper.length = 0;
4812 
4813 	/* enable receive descriptor fetching */
4814 	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4815 	wr32(E1000_RXDCTL(reg_idx), rxdctl);
4816 }
4817 
4818 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4819 				  struct igb_ring *rx_ring)
4820 {
4821 #if (PAGE_SIZE < 8192)
4822 	struct e1000_hw *hw = &adapter->hw;
4823 #endif
4824 
4825 	/* set build_skb and buffer size flags */
4826 	clear_ring_build_skb_enabled(rx_ring);
4827 	clear_ring_uses_large_buffer(rx_ring);
4828 
4829 	if (adapter->flags & IGB_FLAG_RX_LEGACY)
4830 		return;
4831 
4832 	set_ring_build_skb_enabled(rx_ring);
4833 
4834 #if (PAGE_SIZE < 8192)
4835 	if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB ||
4836 	    rd32(E1000_RCTL) & E1000_RCTL_SBP)
4837 		set_ring_uses_large_buffer(rx_ring);
4838 #endif
4839 }
4840 
4841 /**
4842  *  igb_configure_rx - Configure receive Unit after Reset
4843  *  @adapter: board private structure
4844  *
4845  *  Configure the Rx unit of the MAC after a reset.
4846  **/
4847 static void igb_configure_rx(struct igb_adapter *adapter)
4848 {
4849 	int i;
4850 
4851 	/* set the correct pool for the PF default MAC address in entry 0 */
4852 	igb_set_default_mac_filter(adapter);
4853 
4854 	/* Setup the HW Rx Head and Tail Descriptor Pointers and
4855 	 * the Base and Length of the Rx Descriptor Ring
4856 	 */
4857 	for (i = 0; i < adapter->num_rx_queues; i++) {
4858 		struct igb_ring *rx_ring = adapter->rx_ring[i];
4859 
4860 		igb_set_rx_buffer_len(adapter, rx_ring);
4861 		igb_configure_rx_ring(adapter, rx_ring);
4862 	}
4863 }
4864 
4865 /**
4866  *  igb_free_tx_resources - Free Tx Resources per Queue
4867  *  @tx_ring: Tx descriptor ring for a specific queue
4868  *
4869  *  Free all transmit software resources
4870  **/
4871 void igb_free_tx_resources(struct igb_ring *tx_ring)
4872 {
4873 	igb_clean_tx_ring(tx_ring);
4874 
4875 	vfree(tx_ring->tx_buffer_info);
4876 	tx_ring->tx_buffer_info = NULL;
4877 
4878 	/* if not set, then don't free */
4879 	if (!tx_ring->desc)
4880 		return;
4881 
4882 	dma_free_coherent(tx_ring->dev, tx_ring->size,
4883 			  tx_ring->desc, tx_ring->dma);
4884 
4885 	tx_ring->desc = NULL;
4886 }
4887 
4888 /**
4889  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4890  *  @adapter: board private structure
4891  *
4892  *  Free all transmit software resources
4893  **/
4894 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4895 {
4896 	int i;
4897 
4898 	for (i = 0; i < adapter->num_tx_queues; i++)
4899 		if (adapter->tx_ring[i])
4900 			igb_free_tx_resources(adapter->tx_ring[i]);
4901 }
4902 
4903 /**
4904  *  igb_clean_tx_ring - Free Tx Buffers
4905  *  @tx_ring: ring to be cleaned
4906  **/
4907 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4908 {
4909 	u16 i = tx_ring->next_to_clean;
4910 	struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4911 
4912 	while (i != tx_ring->next_to_use) {
4913 		union e1000_adv_tx_desc *eop_desc, *tx_desc;
4914 
4915 		/* Free all the Tx ring sk_buffs or xdp frames */
4916 		if (tx_buffer->type == IGB_TYPE_SKB)
4917 			dev_kfree_skb_any(tx_buffer->skb);
4918 		else
4919 			xdp_return_frame(tx_buffer->xdpf);
4920 
4921 		/* unmap skb header data */
4922 		dma_unmap_single(tx_ring->dev,
4923 				 dma_unmap_addr(tx_buffer, dma),
4924 				 dma_unmap_len(tx_buffer, len),
4925 				 DMA_TO_DEVICE);
4926 
4927 		/* check for eop_desc to determine the end of the packet */
4928 		eop_desc = tx_buffer->next_to_watch;
4929 		tx_desc = IGB_TX_DESC(tx_ring, i);
4930 
4931 		/* unmap remaining buffers */
4932 		while (tx_desc != eop_desc) {
4933 			tx_buffer++;
4934 			tx_desc++;
4935 			i++;
4936 			if (unlikely(i == tx_ring->count)) {
4937 				i = 0;
4938 				tx_buffer = tx_ring->tx_buffer_info;
4939 				tx_desc = IGB_TX_DESC(tx_ring, 0);
4940 			}
4941 
4942 			/* unmap any remaining paged data */
4943 			if (dma_unmap_len(tx_buffer, len))
4944 				dma_unmap_page(tx_ring->dev,
4945 					       dma_unmap_addr(tx_buffer, dma),
4946 					       dma_unmap_len(tx_buffer, len),
4947 					       DMA_TO_DEVICE);
4948 		}
4949 
4950 		tx_buffer->next_to_watch = NULL;
4951 
4952 		/* move us one more past the eop_desc for start of next pkt */
4953 		tx_buffer++;
4954 		i++;
4955 		if (unlikely(i == tx_ring->count)) {
4956 			i = 0;
4957 			tx_buffer = tx_ring->tx_buffer_info;
4958 		}
4959 	}
4960 
4961 	/* reset BQL for queue */
4962 	netdev_tx_reset_queue(txring_txq(tx_ring));
4963 
4964 	/* reset next_to_use and next_to_clean */
4965 	tx_ring->next_to_use = 0;
4966 	tx_ring->next_to_clean = 0;
4967 }
4968 
4969 /**
4970  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4971  *  @adapter: board private structure
4972  **/
4973 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4974 {
4975 	int i;
4976 
4977 	for (i = 0; i < adapter->num_tx_queues; i++)
4978 		if (adapter->tx_ring[i])
4979 			igb_clean_tx_ring(adapter->tx_ring[i]);
4980 }
4981 
4982 /**
4983  *  igb_free_rx_resources - Free Rx Resources
4984  *  @rx_ring: ring to clean the resources from
4985  *
4986  *  Free all receive software resources
4987  **/
4988 void igb_free_rx_resources(struct igb_ring *rx_ring)
4989 {
4990 	igb_clean_rx_ring(rx_ring);
4991 
4992 	rx_ring->xdp_prog = NULL;
4993 	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4994 	vfree(rx_ring->rx_buffer_info);
4995 	rx_ring->rx_buffer_info = NULL;
4996 
4997 	/* if not set, then don't free */
4998 	if (!rx_ring->desc)
4999 		return;
5000 
5001 	dma_free_coherent(rx_ring->dev, rx_ring->size,
5002 			  rx_ring->desc, rx_ring->dma);
5003 
5004 	rx_ring->desc = NULL;
5005 }
5006 
5007 /**
5008  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
5009  *  @adapter: board private structure
5010  *
5011  *  Free all receive software resources
5012  **/
5013 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
5014 {
5015 	int i;
5016 
5017 	for (i = 0; i < adapter->num_rx_queues; i++)
5018 		if (adapter->rx_ring[i])
5019 			igb_free_rx_resources(adapter->rx_ring[i]);
5020 }
5021 
5022 /**
5023  *  igb_clean_rx_ring - Free Rx Buffers per Queue
5024  *  @rx_ring: ring to free buffers from
5025  **/
5026 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
5027 {
5028 	u16 i = rx_ring->next_to_clean;
5029 
5030 	dev_kfree_skb(rx_ring->skb);
5031 	rx_ring->skb = NULL;
5032 
5033 	/* Free all the Rx ring sk_buffs */
5034 	while (i != rx_ring->next_to_alloc) {
5035 		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5036 
5037 		/* Invalidate cache lines that may have been written to by
5038 		 * device so that we avoid corrupting memory.
5039 		 */
5040 		dma_sync_single_range_for_cpu(rx_ring->dev,
5041 					      buffer_info->dma,
5042 					      buffer_info->page_offset,
5043 					      igb_rx_bufsz(rx_ring),
5044 					      DMA_FROM_DEVICE);
5045 
5046 		/* free resources associated with mapping */
5047 		dma_unmap_page_attrs(rx_ring->dev,
5048 				     buffer_info->dma,
5049 				     igb_rx_pg_size(rx_ring),
5050 				     DMA_FROM_DEVICE,
5051 				     IGB_RX_DMA_ATTR);
5052 		__page_frag_cache_drain(buffer_info->page,
5053 					buffer_info->pagecnt_bias);
5054 
5055 		i++;
5056 		if (i == rx_ring->count)
5057 			i = 0;
5058 	}
5059 
5060 	rx_ring->next_to_alloc = 0;
5061 	rx_ring->next_to_clean = 0;
5062 	rx_ring->next_to_use = 0;
5063 }
5064 
5065 /**
5066  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
5067  *  @adapter: board private structure
5068  **/
5069 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
5070 {
5071 	int i;
5072 
5073 	for (i = 0; i < adapter->num_rx_queues; i++)
5074 		if (adapter->rx_ring[i])
5075 			igb_clean_rx_ring(adapter->rx_ring[i]);
5076 }
5077 
5078 /**
5079  *  igb_set_mac - Change the Ethernet Address of the NIC
5080  *  @netdev: network interface device structure
5081  *  @p: pointer to an address structure
5082  *
5083  *  Returns 0 on success, negative on failure
5084  **/
5085 static int igb_set_mac(struct net_device *netdev, void *p)
5086 {
5087 	struct igb_adapter *adapter = netdev_priv(netdev);
5088 	struct e1000_hw *hw = &adapter->hw;
5089 	struct sockaddr *addr = p;
5090 
5091 	if (!is_valid_ether_addr(addr->sa_data))
5092 		return -EADDRNOTAVAIL;
5093 
5094 	eth_hw_addr_set(netdev, addr->sa_data);
5095 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5096 
5097 	/* set the correct pool for the new PF MAC address in entry 0 */
5098 	igb_set_default_mac_filter(adapter);
5099 
5100 	return 0;
5101 }
5102 
5103 /**
5104  *  igb_write_mc_addr_list - write multicast addresses to MTA
5105  *  @netdev: network interface device structure
5106  *
5107  *  Writes multicast address list to the MTA hash table.
5108  *  Returns: -ENOMEM on failure
5109  *           0 on no addresses written
5110  *           X on writing X addresses to MTA
5111  **/
5112 static int igb_write_mc_addr_list(struct net_device *netdev)
5113 {
5114 	struct igb_adapter *adapter = netdev_priv(netdev);
5115 	struct e1000_hw *hw = &adapter->hw;
5116 	struct netdev_hw_addr *ha;
5117 	u8  *mta_list;
5118 	int i;
5119 
5120 	if (netdev_mc_empty(netdev)) {
5121 		/* nothing to program, so clear mc list */
5122 		igb_update_mc_addr_list(hw, NULL, 0);
5123 		igb_restore_vf_multicasts(adapter);
5124 		return 0;
5125 	}
5126 
5127 	mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5128 	if (!mta_list)
5129 		return -ENOMEM;
5130 
5131 	/* The shared function expects a packed array of only addresses. */
5132 	i = 0;
5133 	netdev_for_each_mc_addr(ha, netdev)
5134 		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5135 
5136 	igb_update_mc_addr_list(hw, mta_list, i);
5137 	kfree(mta_list);
5138 
5139 	return netdev_mc_count(netdev);
5140 }
5141 
5142 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5143 {
5144 	struct e1000_hw *hw = &adapter->hw;
5145 	u32 i, pf_id;
5146 
5147 	switch (hw->mac.type) {
5148 	case e1000_i210:
5149 	case e1000_i211:
5150 	case e1000_i350:
5151 		/* VLAN filtering needed for VLAN prio filter */
5152 		if (adapter->netdev->features & NETIF_F_NTUPLE)
5153 			break;
5154 		fallthrough;
5155 	case e1000_82576:
5156 	case e1000_82580:
5157 	case e1000_i354:
5158 		/* VLAN filtering needed for pool filtering */
5159 		if (adapter->vfs_allocated_count)
5160 			break;
5161 		fallthrough;
5162 	default:
5163 		return 1;
5164 	}
5165 
5166 	/* We are already in VLAN promisc, nothing to do */
5167 	if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5168 		return 0;
5169 
5170 	if (!adapter->vfs_allocated_count)
5171 		goto set_vfta;
5172 
5173 	/* Add PF to all active pools */
5174 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5175 
5176 	for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5177 		u32 vlvf = rd32(E1000_VLVF(i));
5178 
5179 		vlvf |= BIT(pf_id);
5180 		wr32(E1000_VLVF(i), vlvf);
5181 	}
5182 
5183 set_vfta:
5184 	/* Set all bits in the VLAN filter table array */
5185 	for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5186 		hw->mac.ops.write_vfta(hw, i, ~0U);
5187 
5188 	/* Set flag so we don't redo unnecessary work */
5189 	adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5190 
5191 	return 0;
5192 }
5193 
5194 #define VFTA_BLOCK_SIZE 8
5195 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5196 {
5197 	struct e1000_hw *hw = &adapter->hw;
5198 	u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5199 	u32 vid_start = vfta_offset * 32;
5200 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5201 	u32 i, vid, word, bits, pf_id;
5202 
5203 	/* guarantee that we don't scrub out management VLAN */
5204 	vid = adapter->mng_vlan_id;
5205 	if (vid >= vid_start && vid < vid_end)
5206 		vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5207 
5208 	if (!adapter->vfs_allocated_count)
5209 		goto set_vfta;
5210 
5211 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5212 
5213 	for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5214 		u32 vlvf = rd32(E1000_VLVF(i));
5215 
5216 		/* pull VLAN ID from VLVF */
5217 		vid = vlvf & VLAN_VID_MASK;
5218 
5219 		/* only concern ourselves with a certain range */
5220 		if (vid < vid_start || vid >= vid_end)
5221 			continue;
5222 
5223 		if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5224 			/* record VLAN ID in VFTA */
5225 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5226 
5227 			/* if PF is part of this then continue */
5228 			if (test_bit(vid, adapter->active_vlans))
5229 				continue;
5230 		}
5231 
5232 		/* remove PF from the pool */
5233 		bits = ~BIT(pf_id);
5234 		bits &= rd32(E1000_VLVF(i));
5235 		wr32(E1000_VLVF(i), bits);
5236 	}
5237 
5238 set_vfta:
5239 	/* extract values from active_vlans and write back to VFTA */
5240 	for (i = VFTA_BLOCK_SIZE; i--;) {
5241 		vid = (vfta_offset + i) * 32;
5242 		word = vid / BITS_PER_LONG;
5243 		bits = vid % BITS_PER_LONG;
5244 
5245 		vfta[i] |= adapter->active_vlans[word] >> bits;
5246 
5247 		hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5248 	}
5249 }
5250 
5251 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5252 {
5253 	u32 i;
5254 
5255 	/* We are not in VLAN promisc, nothing to do */
5256 	if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5257 		return;
5258 
5259 	/* Set flag so we don't redo unnecessary work */
5260 	adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5261 
5262 	for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5263 		igb_scrub_vfta(adapter, i);
5264 }
5265 
5266 /**
5267  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5268  *  @netdev: network interface device structure
5269  *
5270  *  The set_rx_mode entry point is called whenever the unicast or multicast
5271  *  address lists or the network interface flags are updated.  This routine is
5272  *  responsible for configuring the hardware for proper unicast, multicast,
5273  *  promiscuous mode, and all-multi behavior.
5274  **/
5275 static void igb_set_rx_mode(struct net_device *netdev)
5276 {
5277 	struct igb_adapter *adapter = netdev_priv(netdev);
5278 	struct e1000_hw *hw = &adapter->hw;
5279 	unsigned int vfn = adapter->vfs_allocated_count;
5280 	u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5281 	int count;
5282 
5283 	/* Check for Promiscuous and All Multicast modes */
5284 	if (netdev->flags & IFF_PROMISC) {
5285 		rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5286 		vmolr |= E1000_VMOLR_MPME;
5287 
5288 		/* enable use of UTA filter to force packets to default pool */
5289 		if (hw->mac.type == e1000_82576)
5290 			vmolr |= E1000_VMOLR_ROPE;
5291 	} else {
5292 		if (netdev->flags & IFF_ALLMULTI) {
5293 			rctl |= E1000_RCTL_MPE;
5294 			vmolr |= E1000_VMOLR_MPME;
5295 		} else {
5296 			/* Write addresses to the MTA, if the attempt fails
5297 			 * then we should just turn on promiscuous mode so
5298 			 * that we can at least receive multicast traffic
5299 			 */
5300 			count = igb_write_mc_addr_list(netdev);
5301 			if (count < 0) {
5302 				rctl |= E1000_RCTL_MPE;
5303 				vmolr |= E1000_VMOLR_MPME;
5304 			} else if (count) {
5305 				vmolr |= E1000_VMOLR_ROMPE;
5306 			}
5307 		}
5308 	}
5309 
5310 	/* Write addresses to available RAR registers, if there is not
5311 	 * sufficient space to store all the addresses then enable
5312 	 * unicast promiscuous mode
5313 	 */
5314 	if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5315 		rctl |= E1000_RCTL_UPE;
5316 		vmolr |= E1000_VMOLR_ROPE;
5317 	}
5318 
5319 	/* enable VLAN filtering by default */
5320 	rctl |= E1000_RCTL_VFE;
5321 
5322 	/* disable VLAN filtering for modes that require it */
5323 	if ((netdev->flags & IFF_PROMISC) ||
5324 	    (netdev->features & NETIF_F_RXALL)) {
5325 		/* if we fail to set all rules then just clear VFE */
5326 		if (igb_vlan_promisc_enable(adapter))
5327 			rctl &= ~E1000_RCTL_VFE;
5328 	} else {
5329 		igb_vlan_promisc_disable(adapter);
5330 	}
5331 
5332 	/* update state of unicast, multicast, and VLAN filtering modes */
5333 	rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5334 				     E1000_RCTL_VFE);
5335 	wr32(E1000_RCTL, rctl);
5336 
5337 #if (PAGE_SIZE < 8192)
5338 	if (!adapter->vfs_allocated_count) {
5339 		if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5340 			rlpml = IGB_MAX_FRAME_BUILD_SKB;
5341 	}
5342 #endif
5343 	wr32(E1000_RLPML, rlpml);
5344 
5345 	/* In order to support SR-IOV and eventually VMDq it is necessary to set
5346 	 * the VMOLR to enable the appropriate modes.  Without this workaround
5347 	 * we will have issues with VLAN tag stripping not being done for frames
5348 	 * that are only arriving because we are the default pool
5349 	 */
5350 	if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5351 		return;
5352 
5353 	/* set UTA to appropriate mode */
5354 	igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5355 
5356 	vmolr |= rd32(E1000_VMOLR(vfn)) &
5357 		 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5358 
5359 	/* enable Rx jumbo frames, restrict as needed to support build_skb */
5360 	vmolr &= ~E1000_VMOLR_RLPML_MASK;
5361 #if (PAGE_SIZE < 8192)
5362 	if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5363 		vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5364 	else
5365 #endif
5366 		vmolr |= MAX_JUMBO_FRAME_SIZE;
5367 	vmolr |= E1000_VMOLR_LPE;
5368 
5369 	wr32(E1000_VMOLR(vfn), vmolr);
5370 
5371 	igb_restore_vf_multicasts(adapter);
5372 }
5373 
5374 static void igb_check_wvbr(struct igb_adapter *adapter)
5375 {
5376 	struct e1000_hw *hw = &adapter->hw;
5377 	u32 wvbr = 0;
5378 
5379 	switch (hw->mac.type) {
5380 	case e1000_82576:
5381 	case e1000_i350:
5382 		wvbr = rd32(E1000_WVBR);
5383 		if (!wvbr)
5384 			return;
5385 		break;
5386 	default:
5387 		break;
5388 	}
5389 
5390 	adapter->wvbr |= wvbr;
5391 }
5392 
5393 #define IGB_STAGGERED_QUEUE_OFFSET 8
5394 
5395 static void igb_spoof_check(struct igb_adapter *adapter)
5396 {
5397 	int j;
5398 
5399 	if (!adapter->wvbr)
5400 		return;
5401 
5402 	for (j = 0; j < adapter->vfs_allocated_count; j++) {
5403 		if (adapter->wvbr & BIT(j) ||
5404 		    adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5405 			dev_warn(&adapter->pdev->dev,
5406 				"Spoof event(s) detected on VF %d\n", j);
5407 			adapter->wvbr &=
5408 				~(BIT(j) |
5409 				  BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5410 		}
5411 	}
5412 }
5413 
5414 /* Need to wait a few seconds after link up to get diagnostic information from
5415  * the phy
5416  */
5417 static void igb_update_phy_info(struct timer_list *t)
5418 {
5419 	struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5420 	igb_get_phy_info(&adapter->hw);
5421 }
5422 
5423 /**
5424  *  igb_has_link - check shared code for link and determine up/down
5425  *  @adapter: pointer to driver private info
5426  **/
5427 bool igb_has_link(struct igb_adapter *adapter)
5428 {
5429 	struct e1000_hw *hw = &adapter->hw;
5430 	bool link_active = false;
5431 
5432 	/* get_link_status is set on LSC (link status) interrupt or
5433 	 * rx sequence error interrupt.  get_link_status will stay
5434 	 * false until the e1000_check_for_link establishes link
5435 	 * for copper adapters ONLY
5436 	 */
5437 	switch (hw->phy.media_type) {
5438 	case e1000_media_type_copper:
5439 		if (!hw->mac.get_link_status)
5440 			return true;
5441 		fallthrough;
5442 	case e1000_media_type_internal_serdes:
5443 		hw->mac.ops.check_for_link(hw);
5444 		link_active = !hw->mac.get_link_status;
5445 		break;
5446 	default:
5447 	case e1000_media_type_unknown:
5448 		break;
5449 	}
5450 
5451 	if (((hw->mac.type == e1000_i210) ||
5452 	     (hw->mac.type == e1000_i211)) &&
5453 	     (hw->phy.id == I210_I_PHY_ID)) {
5454 		if (!netif_carrier_ok(adapter->netdev)) {
5455 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5456 		} else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5457 			adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5458 			adapter->link_check_timeout = jiffies;
5459 		}
5460 	}
5461 
5462 	return link_active;
5463 }
5464 
5465 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5466 {
5467 	bool ret = false;
5468 	u32 ctrl_ext, thstat;
5469 
5470 	/* check for thermal sensor event on i350 copper only */
5471 	if (hw->mac.type == e1000_i350) {
5472 		thstat = rd32(E1000_THSTAT);
5473 		ctrl_ext = rd32(E1000_CTRL_EXT);
5474 
5475 		if ((hw->phy.media_type == e1000_media_type_copper) &&
5476 		    !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5477 			ret = !!(thstat & event);
5478 	}
5479 
5480 	return ret;
5481 }
5482 
5483 /**
5484  *  igb_check_lvmmc - check for malformed packets received
5485  *  and indicated in LVMMC register
5486  *  @adapter: pointer to adapter
5487  **/
5488 static void igb_check_lvmmc(struct igb_adapter *adapter)
5489 {
5490 	struct e1000_hw *hw = &adapter->hw;
5491 	u32 lvmmc;
5492 
5493 	lvmmc = rd32(E1000_LVMMC);
5494 	if (lvmmc) {
5495 		if (unlikely(net_ratelimit())) {
5496 			netdev_warn(adapter->netdev,
5497 				    "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5498 				    lvmmc);
5499 		}
5500 	}
5501 }
5502 
5503 /**
5504  *  igb_watchdog - Timer Call-back
5505  *  @t: pointer to timer_list containing our private info pointer
5506  **/
5507 static void igb_watchdog(struct timer_list *t)
5508 {
5509 	struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5510 	/* Do the rest outside of interrupt context */
5511 	schedule_work(&adapter->watchdog_task);
5512 }
5513 
5514 static void igb_watchdog_task(struct work_struct *work)
5515 {
5516 	struct igb_adapter *adapter = container_of(work,
5517 						   struct igb_adapter,
5518 						   watchdog_task);
5519 	struct e1000_hw *hw = &adapter->hw;
5520 	struct e1000_phy_info *phy = &hw->phy;
5521 	struct net_device *netdev = adapter->netdev;
5522 	u32 link;
5523 	int i;
5524 	u32 connsw;
5525 	u16 phy_data, retry_count = 20;
5526 
5527 	link = igb_has_link(adapter);
5528 
5529 	if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5530 		if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5531 			adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5532 		else
5533 			link = false;
5534 	}
5535 
5536 	/* Force link down if we have fiber to swap to */
5537 	if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5538 		if (hw->phy.media_type == e1000_media_type_copper) {
5539 			connsw = rd32(E1000_CONNSW);
5540 			if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5541 				link = 0;
5542 		}
5543 	}
5544 	if (link) {
5545 		/* Perform a reset if the media type changed. */
5546 		if (hw->dev_spec._82575.media_changed) {
5547 			hw->dev_spec._82575.media_changed = false;
5548 			adapter->flags |= IGB_FLAG_MEDIA_RESET;
5549 			igb_reset(adapter);
5550 		}
5551 		/* Cancel scheduled suspend requests. */
5552 		pm_runtime_resume(netdev->dev.parent);
5553 
5554 		if (!netif_carrier_ok(netdev)) {
5555 			u32 ctrl;
5556 
5557 			hw->mac.ops.get_speed_and_duplex(hw,
5558 							 &adapter->link_speed,
5559 							 &adapter->link_duplex);
5560 
5561 			ctrl = rd32(E1000_CTRL);
5562 			/* Links status message must follow this format */
5563 			netdev_info(netdev,
5564 			       "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5565 			       netdev->name,
5566 			       adapter->link_speed,
5567 			       adapter->link_duplex == FULL_DUPLEX ?
5568 			       "Full" : "Half",
5569 			       (ctrl & E1000_CTRL_TFCE) &&
5570 			       (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5571 			       (ctrl & E1000_CTRL_RFCE) ?  "RX" :
5572 			       (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
5573 
5574 			/* disable EEE if enabled */
5575 			if ((adapter->flags & IGB_FLAG_EEE) &&
5576 				(adapter->link_duplex == HALF_DUPLEX)) {
5577 				dev_info(&adapter->pdev->dev,
5578 				"EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5579 				adapter->hw.dev_spec._82575.eee_disable = true;
5580 				adapter->flags &= ~IGB_FLAG_EEE;
5581 			}
5582 
5583 			/* check if SmartSpeed worked */
5584 			igb_check_downshift(hw);
5585 			if (phy->speed_downgraded)
5586 				netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5587 
5588 			/* check for thermal sensor event */
5589 			if (igb_thermal_sensor_event(hw,
5590 			    E1000_THSTAT_LINK_THROTTLE))
5591 				netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5592 
5593 			/* adjust timeout factor according to speed/duplex */
5594 			adapter->tx_timeout_factor = 1;
5595 			switch (adapter->link_speed) {
5596 			case SPEED_10:
5597 				adapter->tx_timeout_factor = 14;
5598 				break;
5599 			case SPEED_100:
5600 				/* maybe add some timeout factor ? */
5601 				break;
5602 			}
5603 
5604 			if (adapter->link_speed != SPEED_1000 ||
5605 			    !hw->phy.ops.read_reg)
5606 				goto no_wait;
5607 
5608 			/* wait for Remote receiver status OK */
5609 retry_read_status:
5610 			if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5611 					      &phy_data)) {
5612 				if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5613 				    retry_count) {
5614 					msleep(100);
5615 					retry_count--;
5616 					goto retry_read_status;
5617 				} else if (!retry_count) {
5618 					dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5619 				}
5620 			} else {
5621 				dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5622 			}
5623 no_wait:
5624 			netif_carrier_on(netdev);
5625 
5626 			igb_ping_all_vfs(adapter);
5627 			igb_check_vf_rate_limit(adapter);
5628 
5629 			/* link state has changed, schedule phy info update */
5630 			if (!test_bit(__IGB_DOWN, &adapter->state))
5631 				mod_timer(&adapter->phy_info_timer,
5632 					  round_jiffies(jiffies + 2 * HZ));
5633 		}
5634 	} else {
5635 		if (netif_carrier_ok(netdev)) {
5636 			adapter->link_speed = 0;
5637 			adapter->link_duplex = 0;
5638 
5639 			/* check for thermal sensor event */
5640 			if (igb_thermal_sensor_event(hw,
5641 			    E1000_THSTAT_PWR_DOWN)) {
5642 				netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5643 			}
5644 
5645 			/* Links status message must follow this format */
5646 			netdev_info(netdev, "igb: %s NIC Link is Down\n",
5647 			       netdev->name);
5648 			netif_carrier_off(netdev);
5649 
5650 			igb_ping_all_vfs(adapter);
5651 
5652 			/* link state has changed, schedule phy info update */
5653 			if (!test_bit(__IGB_DOWN, &adapter->state))
5654 				mod_timer(&adapter->phy_info_timer,
5655 					  round_jiffies(jiffies + 2 * HZ));
5656 
5657 			/* link is down, time to check for alternate media */
5658 			if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5659 				igb_check_swap_media(adapter);
5660 				if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5661 					schedule_work(&adapter->reset_task);
5662 					/* return immediately */
5663 					return;
5664 				}
5665 			}
5666 			pm_schedule_suspend(netdev->dev.parent,
5667 					    MSEC_PER_SEC * 5);
5668 
5669 		/* also check for alternate media here */
5670 		} else if (!netif_carrier_ok(netdev) &&
5671 			   (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5672 			igb_check_swap_media(adapter);
5673 			if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5674 				schedule_work(&adapter->reset_task);
5675 				/* return immediately */
5676 				return;
5677 			}
5678 		}
5679 	}
5680 
5681 	spin_lock(&adapter->stats64_lock);
5682 	igb_update_stats(adapter);
5683 	spin_unlock(&adapter->stats64_lock);
5684 
5685 	for (i = 0; i < adapter->num_tx_queues; i++) {
5686 		struct igb_ring *tx_ring = adapter->tx_ring[i];
5687 		if (!netif_carrier_ok(netdev)) {
5688 			/* We've lost link, so the controller stops DMA,
5689 			 * but we've got queued Tx work that's never going
5690 			 * to get done, so reset controller to flush Tx.
5691 			 * (Do the reset outside of interrupt context).
5692 			 */
5693 			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5694 				adapter->tx_timeout_count++;
5695 				schedule_work(&adapter->reset_task);
5696 				/* return immediately since reset is imminent */
5697 				return;
5698 			}
5699 		}
5700 
5701 		/* Force detection of hung controller every watchdog period */
5702 		set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5703 	}
5704 
5705 	/* Cause software interrupt to ensure Rx ring is cleaned */
5706 	if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5707 		u32 eics = 0;
5708 
5709 		for (i = 0; i < adapter->num_q_vectors; i++)
5710 			eics |= adapter->q_vector[i]->eims_value;
5711 		wr32(E1000_EICS, eics);
5712 	} else {
5713 		wr32(E1000_ICS, E1000_ICS_RXDMT0);
5714 	}
5715 
5716 	igb_spoof_check(adapter);
5717 	igb_ptp_rx_hang(adapter);
5718 	igb_ptp_tx_hang(adapter);
5719 
5720 	/* Check LVMMC register on i350/i354 only */
5721 	if ((adapter->hw.mac.type == e1000_i350) ||
5722 	    (adapter->hw.mac.type == e1000_i354))
5723 		igb_check_lvmmc(adapter);
5724 
5725 	/* Reset the timer */
5726 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
5727 		if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5728 			mod_timer(&adapter->watchdog_timer,
5729 				  round_jiffies(jiffies +  HZ));
5730 		else
5731 			mod_timer(&adapter->watchdog_timer,
5732 				  round_jiffies(jiffies + 2 * HZ));
5733 	}
5734 }
5735 
5736 enum latency_range {
5737 	lowest_latency = 0,
5738 	low_latency = 1,
5739 	bulk_latency = 2,
5740 	latency_invalid = 255
5741 };
5742 
5743 /**
5744  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5745  *  @q_vector: pointer to q_vector
5746  *
5747  *  Stores a new ITR value based on strictly on packet size.  This
5748  *  algorithm is less sophisticated than that used in igb_update_itr,
5749  *  due to the difficulty of synchronizing statistics across multiple
5750  *  receive rings.  The divisors and thresholds used by this function
5751  *  were determined based on theoretical maximum wire speed and testing
5752  *  data, in order to minimize response time while increasing bulk
5753  *  throughput.
5754  *  This functionality is controlled by ethtool's coalescing settings.
5755  *  NOTE:  This function is called only when operating in a multiqueue
5756  *         receive environment.
5757  **/
5758 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5759 {
5760 	int new_val = q_vector->itr_val;
5761 	int avg_wire_size = 0;
5762 	struct igb_adapter *adapter = q_vector->adapter;
5763 	unsigned int packets;
5764 
5765 	/* For non-gigabit speeds, just fix the interrupt rate at 4000
5766 	 * ints/sec - ITR timer value of 120 ticks.
5767 	 */
5768 	if (adapter->link_speed != SPEED_1000) {
5769 		new_val = IGB_4K_ITR;
5770 		goto set_itr_val;
5771 	}
5772 
5773 	packets = q_vector->rx.total_packets;
5774 	if (packets)
5775 		avg_wire_size = q_vector->rx.total_bytes / packets;
5776 
5777 	packets = q_vector->tx.total_packets;
5778 	if (packets)
5779 		avg_wire_size = max_t(u32, avg_wire_size,
5780 				      q_vector->tx.total_bytes / packets);
5781 
5782 	/* if avg_wire_size isn't set no work was done */
5783 	if (!avg_wire_size)
5784 		goto clear_counts;
5785 
5786 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
5787 	avg_wire_size += 24;
5788 
5789 	/* Don't starve jumbo frames */
5790 	avg_wire_size = min(avg_wire_size, 3000);
5791 
5792 	/* Give a little boost to mid-size frames */
5793 	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5794 		new_val = avg_wire_size / 3;
5795 	else
5796 		new_val = avg_wire_size / 2;
5797 
5798 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
5799 	if (new_val < IGB_20K_ITR &&
5800 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5801 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5802 		new_val = IGB_20K_ITR;
5803 
5804 set_itr_val:
5805 	if (new_val != q_vector->itr_val) {
5806 		q_vector->itr_val = new_val;
5807 		q_vector->set_itr = 1;
5808 	}
5809 clear_counts:
5810 	q_vector->rx.total_bytes = 0;
5811 	q_vector->rx.total_packets = 0;
5812 	q_vector->tx.total_bytes = 0;
5813 	q_vector->tx.total_packets = 0;
5814 }
5815 
5816 /**
5817  *  igb_update_itr - update the dynamic ITR value based on statistics
5818  *  @q_vector: pointer to q_vector
5819  *  @ring_container: ring info to update the itr for
5820  *
5821  *  Stores a new ITR value based on packets and byte
5822  *  counts during the last interrupt.  The advantage of per interrupt
5823  *  computation is faster updates and more accurate ITR for the current
5824  *  traffic pattern.  Constants in this function were computed
5825  *  based on theoretical maximum wire speed and thresholds were set based
5826  *  on testing data as well as attempting to minimize response time
5827  *  while increasing bulk throughput.
5828  *  This functionality is controlled by ethtool's coalescing settings.
5829  *  NOTE:  These calculations are only valid when operating in a single-
5830  *         queue environment.
5831  **/
5832 static void igb_update_itr(struct igb_q_vector *q_vector,
5833 			   struct igb_ring_container *ring_container)
5834 {
5835 	unsigned int packets = ring_container->total_packets;
5836 	unsigned int bytes = ring_container->total_bytes;
5837 	u8 itrval = ring_container->itr;
5838 
5839 	/* no packets, exit with status unchanged */
5840 	if (packets == 0)
5841 		return;
5842 
5843 	switch (itrval) {
5844 	case lowest_latency:
5845 		/* handle TSO and jumbo frames */
5846 		if (bytes/packets > 8000)
5847 			itrval = bulk_latency;
5848 		else if ((packets < 5) && (bytes > 512))
5849 			itrval = low_latency;
5850 		break;
5851 	case low_latency:  /* 50 usec aka 20000 ints/s */
5852 		if (bytes > 10000) {
5853 			/* this if handles the TSO accounting */
5854 			if (bytes/packets > 8000)
5855 				itrval = bulk_latency;
5856 			else if ((packets < 10) || ((bytes/packets) > 1200))
5857 				itrval = bulk_latency;
5858 			else if ((packets > 35))
5859 				itrval = lowest_latency;
5860 		} else if (bytes/packets > 2000) {
5861 			itrval = bulk_latency;
5862 		} else if (packets <= 2 && bytes < 512) {
5863 			itrval = lowest_latency;
5864 		}
5865 		break;
5866 	case bulk_latency: /* 250 usec aka 4000 ints/s */
5867 		if (bytes > 25000) {
5868 			if (packets > 35)
5869 				itrval = low_latency;
5870 		} else if (bytes < 1500) {
5871 			itrval = low_latency;
5872 		}
5873 		break;
5874 	}
5875 
5876 	/* clear work counters since we have the values we need */
5877 	ring_container->total_bytes = 0;
5878 	ring_container->total_packets = 0;
5879 
5880 	/* write updated itr to ring container */
5881 	ring_container->itr = itrval;
5882 }
5883 
5884 static void igb_set_itr(struct igb_q_vector *q_vector)
5885 {
5886 	struct igb_adapter *adapter = q_vector->adapter;
5887 	u32 new_itr = q_vector->itr_val;
5888 	u8 current_itr = 0;
5889 
5890 	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5891 	if (adapter->link_speed != SPEED_1000) {
5892 		current_itr = 0;
5893 		new_itr = IGB_4K_ITR;
5894 		goto set_itr_now;
5895 	}
5896 
5897 	igb_update_itr(q_vector, &q_vector->tx);
5898 	igb_update_itr(q_vector, &q_vector->rx);
5899 
5900 	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5901 
5902 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
5903 	if (current_itr == lowest_latency &&
5904 	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5905 	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5906 		current_itr = low_latency;
5907 
5908 	switch (current_itr) {
5909 	/* counts and packets in update_itr are dependent on these numbers */
5910 	case lowest_latency:
5911 		new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5912 		break;
5913 	case low_latency:
5914 		new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5915 		break;
5916 	case bulk_latency:
5917 		new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5918 		break;
5919 	default:
5920 		break;
5921 	}
5922 
5923 set_itr_now:
5924 	if (new_itr != q_vector->itr_val) {
5925 		/* this attempts to bias the interrupt rate towards Bulk
5926 		 * by adding intermediate steps when interrupt rate is
5927 		 * increasing
5928 		 */
5929 		new_itr = new_itr > q_vector->itr_val ?
5930 			  max((new_itr * q_vector->itr_val) /
5931 			  (new_itr + (q_vector->itr_val >> 2)),
5932 			  new_itr) : new_itr;
5933 		/* Don't write the value here; it resets the adapter's
5934 		 * internal timer, and causes us to delay far longer than
5935 		 * we should between interrupts.  Instead, we write the ITR
5936 		 * value at the beginning of the next interrupt so the timing
5937 		 * ends up being correct.
5938 		 */
5939 		q_vector->itr_val = new_itr;
5940 		q_vector->set_itr = 1;
5941 	}
5942 }
5943 
5944 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5945 			    struct igb_tx_buffer *first,
5946 			    u32 vlan_macip_lens, u32 type_tucmd,
5947 			    u32 mss_l4len_idx)
5948 {
5949 	struct e1000_adv_tx_context_desc *context_desc;
5950 	u16 i = tx_ring->next_to_use;
5951 	struct timespec64 ts;
5952 
5953 	context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5954 
5955 	i++;
5956 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5957 
5958 	/* set bits to identify this as an advanced context descriptor */
5959 	type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5960 
5961 	/* For 82575, context index must be unique per ring. */
5962 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5963 		mss_l4len_idx |= tx_ring->reg_idx << 4;
5964 
5965 	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
5966 	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
5967 	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);
5968 
5969 	/* We assume there is always a valid tx time available. Invalid times
5970 	 * should have been handled by the upper layers.
5971 	 */
5972 	if (tx_ring->launchtime_enable) {
5973 		ts = ktime_to_timespec64(first->skb->tstamp);
5974 		skb_txtime_consumed(first->skb);
5975 		context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5976 	} else {
5977 		context_desc->seqnum_seed = 0;
5978 	}
5979 }
5980 
5981 static int igb_tso(struct igb_ring *tx_ring,
5982 		   struct igb_tx_buffer *first,
5983 		   u8 *hdr_len)
5984 {
5985 	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5986 	struct sk_buff *skb = first->skb;
5987 	union {
5988 		struct iphdr *v4;
5989 		struct ipv6hdr *v6;
5990 		unsigned char *hdr;
5991 	} ip;
5992 	union {
5993 		struct tcphdr *tcp;
5994 		struct udphdr *udp;
5995 		unsigned char *hdr;
5996 	} l4;
5997 	u32 paylen, l4_offset;
5998 	int err;
5999 
6000 	if (skb->ip_summed != CHECKSUM_PARTIAL)
6001 		return 0;
6002 
6003 	if (!skb_is_gso(skb))
6004 		return 0;
6005 
6006 	err = skb_cow_head(skb, 0);
6007 	if (err < 0)
6008 		return err;
6009 
6010 	ip.hdr = skb_network_header(skb);
6011 	l4.hdr = skb_checksum_start(skb);
6012 
6013 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6014 	type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
6015 		      E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
6016 
6017 	/* initialize outer IP header fields */
6018 	if (ip.v4->version == 4) {
6019 		unsigned char *csum_start = skb_checksum_start(skb);
6020 		unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
6021 
6022 		/* IP header will have to cancel out any data that
6023 		 * is not a part of the outer IP header
6024 		 */
6025 		ip.v4->check = csum_fold(csum_partial(trans_start,
6026 						      csum_start - trans_start,
6027 						      0));
6028 		type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
6029 
6030 		ip.v4->tot_len = 0;
6031 		first->tx_flags |= IGB_TX_FLAGS_TSO |
6032 				   IGB_TX_FLAGS_CSUM |
6033 				   IGB_TX_FLAGS_IPV4;
6034 	} else {
6035 		ip.v6->payload_len = 0;
6036 		first->tx_flags |= IGB_TX_FLAGS_TSO |
6037 				   IGB_TX_FLAGS_CSUM;
6038 	}
6039 
6040 	/* determine offset of inner transport header */
6041 	l4_offset = l4.hdr - skb->data;
6042 
6043 	/* remove payload length from inner checksum */
6044 	paylen = skb->len - l4_offset;
6045 	if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
6046 		/* compute length of segmentation header */
6047 		*hdr_len = (l4.tcp->doff * 4) + l4_offset;
6048 		csum_replace_by_diff(&l4.tcp->check,
6049 			(__force __wsum)htonl(paylen));
6050 	} else {
6051 		/* compute length of segmentation header */
6052 		*hdr_len = sizeof(*l4.udp) + l4_offset;
6053 		csum_replace_by_diff(&l4.udp->check,
6054 				     (__force __wsum)htonl(paylen));
6055 	}
6056 
6057 	/* update gso size and bytecount with header size */
6058 	first->gso_segs = skb_shinfo(skb)->gso_segs;
6059 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
6060 
6061 	/* MSS L4LEN IDX */
6062 	mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
6063 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
6064 
6065 	/* VLAN MACLEN IPLEN */
6066 	vlan_macip_lens = l4.hdr - ip.hdr;
6067 	vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
6068 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6069 
6070 	igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
6071 			type_tucmd, mss_l4len_idx);
6072 
6073 	return 1;
6074 }
6075 
6076 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
6077 {
6078 	struct sk_buff *skb = first->skb;
6079 	u32 vlan_macip_lens = 0;
6080 	u32 type_tucmd = 0;
6081 
6082 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
6083 csum_failed:
6084 		if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
6085 		    !tx_ring->launchtime_enable)
6086 			return;
6087 		goto no_csum;
6088 	}
6089 
6090 	switch (skb->csum_offset) {
6091 	case offsetof(struct tcphdr, check):
6092 		type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
6093 		fallthrough;
6094 	case offsetof(struct udphdr, check):
6095 		break;
6096 	case offsetof(struct sctphdr, checksum):
6097 		/* validate that this is actually an SCTP request */
6098 		if (skb_csum_is_sctp(skb)) {
6099 			type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6100 			break;
6101 		}
6102 		fallthrough;
6103 	default:
6104 		skb_checksum_help(skb);
6105 		goto csum_failed;
6106 	}
6107 
6108 	/* update TX checksum flag */
6109 	first->tx_flags |= IGB_TX_FLAGS_CSUM;
6110 	vlan_macip_lens = skb_checksum_start_offset(skb) -
6111 			  skb_network_offset(skb);
6112 no_csum:
6113 	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6114 	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6115 
6116 	igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6117 }
6118 
6119 #define IGB_SET_FLAG(_input, _flag, _result) \
6120 	((_flag <= _result) ? \
6121 	 ((u32)(_input & _flag) * (_result / _flag)) : \
6122 	 ((u32)(_input & _flag) / (_flag / _result)))
6123 
6124 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6125 {
6126 	/* set type for advanced descriptor with frame checksum insertion */
6127 	u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6128 		       E1000_ADVTXD_DCMD_DEXT |
6129 		       E1000_ADVTXD_DCMD_IFCS;
6130 
6131 	/* set HW vlan bit if vlan is present */
6132 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6133 				 (E1000_ADVTXD_DCMD_VLE));
6134 
6135 	/* set segmentation bits for TSO */
6136 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6137 				 (E1000_ADVTXD_DCMD_TSE));
6138 
6139 	/* set timestamp bit if present */
6140 	cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6141 				 (E1000_ADVTXD_MAC_TSTAMP));
6142 
6143 	/* insert frame checksum */
6144 	cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6145 
6146 	return cmd_type;
6147 }
6148 
6149 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6150 				 union e1000_adv_tx_desc *tx_desc,
6151 				 u32 tx_flags, unsigned int paylen)
6152 {
6153 	u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6154 
6155 	/* 82575 requires a unique index per ring */
6156 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6157 		olinfo_status |= tx_ring->reg_idx << 4;
6158 
6159 	/* insert L4 checksum */
6160 	olinfo_status |= IGB_SET_FLAG(tx_flags,
6161 				      IGB_TX_FLAGS_CSUM,
6162 				      (E1000_TXD_POPTS_TXSM << 8));
6163 
6164 	/* insert IPv4 checksum */
6165 	olinfo_status |= IGB_SET_FLAG(tx_flags,
6166 				      IGB_TX_FLAGS_IPV4,
6167 				      (E1000_TXD_POPTS_IXSM << 8));
6168 
6169 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6170 }
6171 
6172 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6173 {
6174 	struct net_device *netdev = tx_ring->netdev;
6175 
6176 	netif_stop_subqueue(netdev, tx_ring->queue_index);
6177 
6178 	/* Herbert's original patch had:
6179 	 *  smp_mb__after_netif_stop_queue();
6180 	 * but since that doesn't exist yet, just open code it.
6181 	 */
6182 	smp_mb();
6183 
6184 	/* We need to check again in a case another CPU has just
6185 	 * made room available.
6186 	 */
6187 	if (igb_desc_unused(tx_ring) < size)
6188 		return -EBUSY;
6189 
6190 	/* A reprieve! */
6191 	netif_wake_subqueue(netdev, tx_ring->queue_index);
6192 
6193 	u64_stats_update_begin(&tx_ring->tx_syncp2);
6194 	tx_ring->tx_stats.restart_queue2++;
6195 	u64_stats_update_end(&tx_ring->tx_syncp2);
6196 
6197 	return 0;
6198 }
6199 
6200 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6201 {
6202 	if (igb_desc_unused(tx_ring) >= size)
6203 		return 0;
6204 	return __igb_maybe_stop_tx(tx_ring, size);
6205 }
6206 
6207 static int igb_tx_map(struct igb_ring *tx_ring,
6208 		      struct igb_tx_buffer *first,
6209 		      const u8 hdr_len)
6210 {
6211 	struct sk_buff *skb = first->skb;
6212 	struct igb_tx_buffer *tx_buffer;
6213 	union e1000_adv_tx_desc *tx_desc;
6214 	skb_frag_t *frag;
6215 	dma_addr_t dma;
6216 	unsigned int data_len, size;
6217 	u32 tx_flags = first->tx_flags;
6218 	u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6219 	u16 i = tx_ring->next_to_use;
6220 
6221 	tx_desc = IGB_TX_DESC(tx_ring, i);
6222 
6223 	igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6224 
6225 	size = skb_headlen(skb);
6226 	data_len = skb->data_len;
6227 
6228 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6229 
6230 	tx_buffer = first;
6231 
6232 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6233 		if (dma_mapping_error(tx_ring->dev, dma))
6234 			goto dma_error;
6235 
6236 		/* record length, and DMA address */
6237 		dma_unmap_len_set(tx_buffer, len, size);
6238 		dma_unmap_addr_set(tx_buffer, dma, dma);
6239 
6240 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
6241 
6242 		while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6243 			tx_desc->read.cmd_type_len =
6244 				cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6245 
6246 			i++;
6247 			tx_desc++;
6248 			if (i == tx_ring->count) {
6249 				tx_desc = IGB_TX_DESC(tx_ring, 0);
6250 				i = 0;
6251 			}
6252 			tx_desc->read.olinfo_status = 0;
6253 
6254 			dma += IGB_MAX_DATA_PER_TXD;
6255 			size -= IGB_MAX_DATA_PER_TXD;
6256 
6257 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
6258 		}
6259 
6260 		if (likely(!data_len))
6261 			break;
6262 
6263 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6264 
6265 		i++;
6266 		tx_desc++;
6267 		if (i == tx_ring->count) {
6268 			tx_desc = IGB_TX_DESC(tx_ring, 0);
6269 			i = 0;
6270 		}
6271 		tx_desc->read.olinfo_status = 0;
6272 
6273 		size = skb_frag_size(frag);
6274 		data_len -= size;
6275 
6276 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6277 				       size, DMA_TO_DEVICE);
6278 
6279 		tx_buffer = &tx_ring->tx_buffer_info[i];
6280 	}
6281 
6282 	/* write last descriptor with RS and EOP bits */
6283 	cmd_type |= size | IGB_TXD_DCMD;
6284 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6285 
6286 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6287 
6288 	/* set the timestamp */
6289 	first->time_stamp = jiffies;
6290 
6291 	skb_tx_timestamp(skb);
6292 
6293 	/* Force memory writes to complete before letting h/w know there
6294 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
6295 	 * memory model archs, such as IA-64).
6296 	 *
6297 	 * We also need this memory barrier to make certain all of the
6298 	 * status bits have been updated before next_to_watch is written.
6299 	 */
6300 	dma_wmb();
6301 
6302 	/* set next_to_watch value indicating a packet is present */
6303 	first->next_to_watch = tx_desc;
6304 
6305 	i++;
6306 	if (i == tx_ring->count)
6307 		i = 0;
6308 
6309 	tx_ring->next_to_use = i;
6310 
6311 	/* Make sure there is space in the ring for the next send. */
6312 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6313 
6314 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6315 		writel(i, tx_ring->tail);
6316 	}
6317 	return 0;
6318 
6319 dma_error:
6320 	dev_err(tx_ring->dev, "TX DMA map failed\n");
6321 	tx_buffer = &tx_ring->tx_buffer_info[i];
6322 
6323 	/* clear dma mappings for failed tx_buffer_info map */
6324 	while (tx_buffer != first) {
6325 		if (dma_unmap_len(tx_buffer, len))
6326 			dma_unmap_page(tx_ring->dev,
6327 				       dma_unmap_addr(tx_buffer, dma),
6328 				       dma_unmap_len(tx_buffer, len),
6329 				       DMA_TO_DEVICE);
6330 		dma_unmap_len_set(tx_buffer, len, 0);
6331 
6332 		if (i-- == 0)
6333 			i += tx_ring->count;
6334 		tx_buffer = &tx_ring->tx_buffer_info[i];
6335 	}
6336 
6337 	if (dma_unmap_len(tx_buffer, len))
6338 		dma_unmap_single(tx_ring->dev,
6339 				 dma_unmap_addr(tx_buffer, dma),
6340 				 dma_unmap_len(tx_buffer, len),
6341 				 DMA_TO_DEVICE);
6342 	dma_unmap_len_set(tx_buffer, len, 0);
6343 
6344 	dev_kfree_skb_any(tx_buffer->skb);
6345 	tx_buffer->skb = NULL;
6346 
6347 	tx_ring->next_to_use = i;
6348 
6349 	return -1;
6350 }
6351 
6352 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6353 		      struct igb_ring *tx_ring,
6354 		      struct xdp_frame *xdpf)
6355 {
6356 	struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
6357 	u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
6358 	u16 count, i, index = tx_ring->next_to_use;
6359 	struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index];
6360 	struct igb_tx_buffer *tx_buffer = tx_head;
6361 	union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index);
6362 	u32 len = xdpf->len, cmd_type, olinfo_status;
6363 	void *data = xdpf->data;
6364 
6365 	count = TXD_USE_COUNT(len);
6366 	for (i = 0; i < nr_frags; i++)
6367 		count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
6368 
6369 	if (igb_maybe_stop_tx(tx_ring, count + 3))
6370 		return IGB_XDP_CONSUMED;
6371 
6372 	i = 0;
6373 	/* record the location of the first descriptor for this packet */
6374 	tx_head->bytecount = xdp_get_frame_len(xdpf);
6375 	tx_head->type = IGB_TYPE_XDP;
6376 	tx_head->gso_segs = 1;
6377 	tx_head->xdpf = xdpf;
6378 
6379 	olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT;
6380 	/* 82575 requires a unique index per ring */
6381 	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6382 		olinfo_status |= tx_ring->reg_idx << 4;
6383 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6384 
6385 	for (;;) {
6386 		dma_addr_t dma;
6387 
6388 		dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
6389 		if (dma_mapping_error(tx_ring->dev, dma))
6390 			goto unmap;
6391 
6392 		/* record length, and DMA address */
6393 		dma_unmap_len_set(tx_buffer, len, len);
6394 		dma_unmap_addr_set(tx_buffer, dma, dma);
6395 
6396 		/* put descriptor type bits */
6397 		cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT |
6398 			   E1000_ADVTXD_DCMD_IFCS | len;
6399 
6400 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6401 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
6402 
6403 		tx_buffer->protocol = 0;
6404 
6405 		if (++index == tx_ring->count)
6406 			index = 0;
6407 
6408 		if (i == nr_frags)
6409 			break;
6410 
6411 		tx_buffer = &tx_ring->tx_buffer_info[index];
6412 		tx_desc = IGB_TX_DESC(tx_ring, index);
6413 		tx_desc->read.olinfo_status = 0;
6414 
6415 		data = skb_frag_address(&sinfo->frags[i]);
6416 		len = skb_frag_size(&sinfo->frags[i]);
6417 		i++;
6418 	}
6419 	tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
6420 
6421 	netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount);
6422 	/* set the timestamp */
6423 	tx_head->time_stamp = jiffies;
6424 
6425 	/* Avoid any potential race with xdp_xmit and cleanup */
6426 	smp_wmb();
6427 
6428 	/* set next_to_watch value indicating a packet is present */
6429 	tx_head->next_to_watch = tx_desc;
6430 	tx_ring->next_to_use = index;
6431 
6432 	/* Make sure there is space in the ring for the next send. */
6433 	igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6434 
6435 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6436 		writel(index, tx_ring->tail);
6437 
6438 	return IGB_XDP_TX;
6439 
6440 unmap:
6441 	for (;;) {
6442 		tx_buffer = &tx_ring->tx_buffer_info[index];
6443 		if (dma_unmap_len(tx_buffer, len))
6444 			dma_unmap_page(tx_ring->dev,
6445 				       dma_unmap_addr(tx_buffer, dma),
6446 				       dma_unmap_len(tx_buffer, len),
6447 				       DMA_TO_DEVICE);
6448 		dma_unmap_len_set(tx_buffer, len, 0);
6449 		if (tx_buffer == tx_head)
6450 			break;
6451 
6452 		if (!index)
6453 			index += tx_ring->count;
6454 		index--;
6455 	}
6456 
6457 	return IGB_XDP_CONSUMED;
6458 }
6459 
6460 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6461 				struct igb_ring *tx_ring)
6462 {
6463 	struct igb_tx_buffer *first;
6464 	int tso;
6465 	u32 tx_flags = 0;
6466 	unsigned short f;
6467 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
6468 	__be16 protocol = vlan_get_protocol(skb);
6469 	u8 hdr_len = 0;
6470 
6471 	/* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6472 	 *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6473 	 *       + 2 desc gap to keep tail from touching head,
6474 	 *       + 1 desc for context descriptor,
6475 	 * otherwise try next time
6476 	 */
6477 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6478 		count += TXD_USE_COUNT(skb_frag_size(
6479 						&skb_shinfo(skb)->frags[f]));
6480 
6481 	if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6482 		/* this is a hard error */
6483 		return NETDEV_TX_BUSY;
6484 	}
6485 
6486 	/* record the location of the first descriptor for this packet */
6487 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6488 	first->type = IGB_TYPE_SKB;
6489 	first->skb = skb;
6490 	first->bytecount = skb->len;
6491 	first->gso_segs = 1;
6492 
6493 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6494 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6495 
6496 		if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6497 		    !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6498 					   &adapter->state)) {
6499 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6500 			tx_flags |= IGB_TX_FLAGS_TSTAMP;
6501 
6502 			adapter->ptp_tx_skb = skb_get(skb);
6503 			adapter->ptp_tx_start = jiffies;
6504 			if (adapter->hw.mac.type == e1000_82576)
6505 				schedule_work(&adapter->ptp_tx_work);
6506 		} else {
6507 			adapter->tx_hwtstamp_skipped++;
6508 		}
6509 	}
6510 
6511 	if (skb_vlan_tag_present(skb)) {
6512 		tx_flags |= IGB_TX_FLAGS_VLAN;
6513 		tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6514 	}
6515 
6516 	/* record initial flags and protocol */
6517 	first->tx_flags = tx_flags;
6518 	first->protocol = protocol;
6519 
6520 	tso = igb_tso(tx_ring, first, &hdr_len);
6521 	if (tso < 0)
6522 		goto out_drop;
6523 	else if (!tso)
6524 		igb_tx_csum(tx_ring, first);
6525 
6526 	if (igb_tx_map(tx_ring, first, hdr_len))
6527 		goto cleanup_tx_tstamp;
6528 
6529 	return NETDEV_TX_OK;
6530 
6531 out_drop:
6532 	dev_kfree_skb_any(first->skb);
6533 	first->skb = NULL;
6534 cleanup_tx_tstamp:
6535 	if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6536 		struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6537 
6538 		dev_kfree_skb_any(adapter->ptp_tx_skb);
6539 		adapter->ptp_tx_skb = NULL;
6540 		if (adapter->hw.mac.type == e1000_82576)
6541 			cancel_work_sync(&adapter->ptp_tx_work);
6542 		clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6543 	}
6544 
6545 	return NETDEV_TX_OK;
6546 }
6547 
6548 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6549 						    struct sk_buff *skb)
6550 {
6551 	unsigned int r_idx = skb->queue_mapping;
6552 
6553 	if (r_idx >= adapter->num_tx_queues)
6554 		r_idx = r_idx % adapter->num_tx_queues;
6555 
6556 	return adapter->tx_ring[r_idx];
6557 }
6558 
6559 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6560 				  struct net_device *netdev)
6561 {
6562 	struct igb_adapter *adapter = netdev_priv(netdev);
6563 
6564 	/* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6565 	 * in order to meet this minimum size requirement.
6566 	 */
6567 	if (skb_put_padto(skb, 17))
6568 		return NETDEV_TX_OK;
6569 
6570 	return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6571 }
6572 
6573 /**
6574  *  igb_tx_timeout - Respond to a Tx Hang
6575  *  @netdev: network interface device structure
6576  *  @txqueue: number of the Tx queue that hung (unused)
6577  **/
6578 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6579 {
6580 	struct igb_adapter *adapter = netdev_priv(netdev);
6581 	struct e1000_hw *hw = &adapter->hw;
6582 
6583 	/* Do the reset outside of interrupt context */
6584 	adapter->tx_timeout_count++;
6585 
6586 	if (hw->mac.type >= e1000_82580)
6587 		hw->dev_spec._82575.global_device_reset = true;
6588 
6589 	schedule_work(&adapter->reset_task);
6590 	wr32(E1000_EICS,
6591 	     (adapter->eims_enable_mask & ~adapter->eims_other));
6592 }
6593 
6594 static void igb_reset_task(struct work_struct *work)
6595 {
6596 	struct igb_adapter *adapter;
6597 	adapter = container_of(work, struct igb_adapter, reset_task);
6598 
6599 	rtnl_lock();
6600 	/* If we're already down or resetting, just bail */
6601 	if (test_bit(__IGB_DOWN, &adapter->state) ||
6602 	    test_bit(__IGB_RESETTING, &adapter->state)) {
6603 		rtnl_unlock();
6604 		return;
6605 	}
6606 
6607 	igb_dump(adapter);
6608 	netdev_err(adapter->netdev, "Reset adapter\n");
6609 	igb_reinit_locked(adapter);
6610 	rtnl_unlock();
6611 }
6612 
6613 /**
6614  *  igb_get_stats64 - Get System Network Statistics
6615  *  @netdev: network interface device structure
6616  *  @stats: rtnl_link_stats64 pointer
6617  **/
6618 static void igb_get_stats64(struct net_device *netdev,
6619 			    struct rtnl_link_stats64 *stats)
6620 {
6621 	struct igb_adapter *adapter = netdev_priv(netdev);
6622 
6623 	spin_lock(&adapter->stats64_lock);
6624 	igb_update_stats(adapter);
6625 	memcpy(stats, &adapter->stats64, sizeof(*stats));
6626 	spin_unlock(&adapter->stats64_lock);
6627 }
6628 
6629 /**
6630  *  igb_change_mtu - Change the Maximum Transfer Unit
6631  *  @netdev: network interface device structure
6632  *  @new_mtu: new value for maximum frame size
6633  *
6634  *  Returns 0 on success, negative on failure
6635  **/
6636 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6637 {
6638 	struct igb_adapter *adapter = netdev_priv(netdev);
6639 	int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6640 
6641 	if (adapter->xdp_prog) {
6642 		int i;
6643 
6644 		for (i = 0; i < adapter->num_rx_queues; i++) {
6645 			struct igb_ring *ring = adapter->rx_ring[i];
6646 
6647 			if (max_frame > igb_rx_bufsz(ring)) {
6648 				netdev_warn(adapter->netdev,
6649 					    "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6650 					    max_frame);
6651 				return -EINVAL;
6652 			}
6653 		}
6654 	}
6655 
6656 	/* adjust max frame to be at least the size of a standard frame */
6657 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6658 		max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6659 
6660 	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6661 		usleep_range(1000, 2000);
6662 
6663 	/* igb_down has a dependency on max_frame_size */
6664 	adapter->max_frame_size = max_frame;
6665 
6666 	if (netif_running(netdev))
6667 		igb_down(adapter);
6668 
6669 	netdev_dbg(netdev, "changing MTU from %d to %d\n",
6670 		   netdev->mtu, new_mtu);
6671 	netdev->mtu = new_mtu;
6672 
6673 	if (netif_running(netdev))
6674 		igb_up(adapter);
6675 	else
6676 		igb_reset(adapter);
6677 
6678 	clear_bit(__IGB_RESETTING, &adapter->state);
6679 
6680 	return 0;
6681 }
6682 
6683 /**
6684  *  igb_update_stats - Update the board statistics counters
6685  *  @adapter: board private structure
6686  **/
6687 void igb_update_stats(struct igb_adapter *adapter)
6688 {
6689 	struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6690 	struct e1000_hw *hw = &adapter->hw;
6691 	struct pci_dev *pdev = adapter->pdev;
6692 	u32 reg, mpc;
6693 	int i;
6694 	u64 bytes, packets;
6695 	unsigned int start;
6696 	u64 _bytes, _packets;
6697 
6698 	/* Prevent stats update while adapter is being reset, or if the pci
6699 	 * connection is down.
6700 	 */
6701 	if (adapter->link_speed == 0)
6702 		return;
6703 	if (pci_channel_offline(pdev))
6704 		return;
6705 
6706 	bytes = 0;
6707 	packets = 0;
6708 
6709 	rcu_read_lock();
6710 	for (i = 0; i < adapter->num_rx_queues; i++) {
6711 		struct igb_ring *ring = adapter->rx_ring[i];
6712 		u32 rqdpc = rd32(E1000_RQDPC(i));
6713 		if (hw->mac.type >= e1000_i210)
6714 			wr32(E1000_RQDPC(i), 0);
6715 
6716 		if (rqdpc) {
6717 			ring->rx_stats.drops += rqdpc;
6718 			net_stats->rx_fifo_errors += rqdpc;
6719 		}
6720 
6721 		do {
6722 			start = u64_stats_fetch_begin(&ring->rx_syncp);
6723 			_bytes = ring->rx_stats.bytes;
6724 			_packets = ring->rx_stats.packets;
6725 		} while (u64_stats_fetch_retry(&ring->rx_syncp, start));
6726 		bytes += _bytes;
6727 		packets += _packets;
6728 	}
6729 
6730 	net_stats->rx_bytes = bytes;
6731 	net_stats->rx_packets = packets;
6732 
6733 	bytes = 0;
6734 	packets = 0;
6735 	for (i = 0; i < adapter->num_tx_queues; i++) {
6736 		struct igb_ring *ring = adapter->tx_ring[i];
6737 		do {
6738 			start = u64_stats_fetch_begin(&ring->tx_syncp);
6739 			_bytes = ring->tx_stats.bytes;
6740 			_packets = ring->tx_stats.packets;
6741 		} while (u64_stats_fetch_retry(&ring->tx_syncp, start));
6742 		bytes += _bytes;
6743 		packets += _packets;
6744 	}
6745 	net_stats->tx_bytes = bytes;
6746 	net_stats->tx_packets = packets;
6747 	rcu_read_unlock();
6748 
6749 	/* read stats registers */
6750 	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6751 	adapter->stats.gprc += rd32(E1000_GPRC);
6752 	adapter->stats.gorc += rd32(E1000_GORCL);
6753 	rd32(E1000_GORCH); /* clear GORCL */
6754 	adapter->stats.bprc += rd32(E1000_BPRC);
6755 	adapter->stats.mprc += rd32(E1000_MPRC);
6756 	adapter->stats.roc += rd32(E1000_ROC);
6757 
6758 	adapter->stats.prc64 += rd32(E1000_PRC64);
6759 	adapter->stats.prc127 += rd32(E1000_PRC127);
6760 	adapter->stats.prc255 += rd32(E1000_PRC255);
6761 	adapter->stats.prc511 += rd32(E1000_PRC511);
6762 	adapter->stats.prc1023 += rd32(E1000_PRC1023);
6763 	adapter->stats.prc1522 += rd32(E1000_PRC1522);
6764 	adapter->stats.symerrs += rd32(E1000_SYMERRS);
6765 	adapter->stats.sec += rd32(E1000_SEC);
6766 
6767 	mpc = rd32(E1000_MPC);
6768 	adapter->stats.mpc += mpc;
6769 	net_stats->rx_fifo_errors += mpc;
6770 	adapter->stats.scc += rd32(E1000_SCC);
6771 	adapter->stats.ecol += rd32(E1000_ECOL);
6772 	adapter->stats.mcc += rd32(E1000_MCC);
6773 	adapter->stats.latecol += rd32(E1000_LATECOL);
6774 	adapter->stats.dc += rd32(E1000_DC);
6775 	adapter->stats.rlec += rd32(E1000_RLEC);
6776 	adapter->stats.xonrxc += rd32(E1000_XONRXC);
6777 	adapter->stats.xontxc += rd32(E1000_XONTXC);
6778 	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6779 	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6780 	adapter->stats.fcruc += rd32(E1000_FCRUC);
6781 	adapter->stats.gptc += rd32(E1000_GPTC);
6782 	adapter->stats.gotc += rd32(E1000_GOTCL);
6783 	rd32(E1000_GOTCH); /* clear GOTCL */
6784 	adapter->stats.rnbc += rd32(E1000_RNBC);
6785 	adapter->stats.ruc += rd32(E1000_RUC);
6786 	adapter->stats.rfc += rd32(E1000_RFC);
6787 	adapter->stats.rjc += rd32(E1000_RJC);
6788 	adapter->stats.tor += rd32(E1000_TORH);
6789 	adapter->stats.tot += rd32(E1000_TOTH);
6790 	adapter->stats.tpr += rd32(E1000_TPR);
6791 
6792 	adapter->stats.ptc64 += rd32(E1000_PTC64);
6793 	adapter->stats.ptc127 += rd32(E1000_PTC127);
6794 	adapter->stats.ptc255 += rd32(E1000_PTC255);
6795 	adapter->stats.ptc511 += rd32(E1000_PTC511);
6796 	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6797 	adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6798 
6799 	adapter->stats.mptc += rd32(E1000_MPTC);
6800 	adapter->stats.bptc += rd32(E1000_BPTC);
6801 
6802 	adapter->stats.tpt += rd32(E1000_TPT);
6803 	adapter->stats.colc += rd32(E1000_COLC);
6804 
6805 	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6806 	/* read internal phy specific stats */
6807 	reg = rd32(E1000_CTRL_EXT);
6808 	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6809 		adapter->stats.rxerrc += rd32(E1000_RXERRC);
6810 
6811 		/* this stat has invalid values on i210/i211 */
6812 		if ((hw->mac.type != e1000_i210) &&
6813 		    (hw->mac.type != e1000_i211))
6814 			adapter->stats.tncrs += rd32(E1000_TNCRS);
6815 	}
6816 
6817 	adapter->stats.tsctc += rd32(E1000_TSCTC);
6818 	adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6819 
6820 	adapter->stats.iac += rd32(E1000_IAC);
6821 	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6822 	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6823 	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6824 	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6825 	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6826 	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6827 	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6828 	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6829 
6830 	/* Fill out the OS statistics structure */
6831 	net_stats->multicast = adapter->stats.mprc;
6832 	net_stats->collisions = adapter->stats.colc;
6833 
6834 	/* Rx Errors */
6835 
6836 	/* RLEC on some newer hardware can be incorrect so build
6837 	 * our own version based on RUC and ROC
6838 	 */
6839 	net_stats->rx_errors = adapter->stats.rxerrc +
6840 		adapter->stats.crcerrs + adapter->stats.algnerrc +
6841 		adapter->stats.ruc + adapter->stats.roc +
6842 		adapter->stats.cexterr;
6843 	net_stats->rx_length_errors = adapter->stats.ruc +
6844 				      adapter->stats.roc;
6845 	net_stats->rx_crc_errors = adapter->stats.crcerrs;
6846 	net_stats->rx_frame_errors = adapter->stats.algnerrc;
6847 	net_stats->rx_missed_errors = adapter->stats.mpc;
6848 
6849 	/* Tx Errors */
6850 	net_stats->tx_errors = adapter->stats.ecol +
6851 			       adapter->stats.latecol;
6852 	net_stats->tx_aborted_errors = adapter->stats.ecol;
6853 	net_stats->tx_window_errors = adapter->stats.latecol;
6854 	net_stats->tx_carrier_errors = adapter->stats.tncrs;
6855 
6856 	/* Tx Dropped needs to be maintained elsewhere */
6857 
6858 	/* Management Stats */
6859 	adapter->stats.mgptc += rd32(E1000_MGTPTC);
6860 	adapter->stats.mgprc += rd32(E1000_MGTPRC);
6861 	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6862 
6863 	/* OS2BMC Stats */
6864 	reg = rd32(E1000_MANC);
6865 	if (reg & E1000_MANC_EN_BMC2OS) {
6866 		adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6867 		adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6868 		adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6869 		adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6870 	}
6871 }
6872 
6873 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt)
6874 {
6875 	int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt);
6876 	struct e1000_hw *hw = &adapter->hw;
6877 	struct timespec64 ts;
6878 	u32 tsauxc;
6879 
6880 	if (pin < 0 || pin >= IGB_N_SDP)
6881 		return;
6882 
6883 	spin_lock(&adapter->tmreg_lock);
6884 
6885 	if (hw->mac.type == e1000_82580 ||
6886 	    hw->mac.type == e1000_i354 ||
6887 	    hw->mac.type == e1000_i350) {
6888 		s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period);
6889 		u32 systiml, systimh, level_mask, level, rem;
6890 		u64 systim, now;
6891 
6892 		/* read systim registers in sequence */
6893 		rd32(E1000_SYSTIMR);
6894 		systiml = rd32(E1000_SYSTIML);
6895 		systimh = rd32(E1000_SYSTIMH);
6896 		systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
6897 		now = timecounter_cyc2time(&adapter->tc, systim);
6898 
6899 		if (pin < 2) {
6900 			level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000;
6901 			level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
6902 		} else {
6903 			level_mask = (tsintr_tt == 1) ? 0x80 : 0x40;
6904 			level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
6905 		}
6906 
6907 		div_u64_rem(now, ns, &rem);
6908 		systim = systim + (ns - rem);
6909 
6910 		/* synchronize pin level with rising/falling edges */
6911 		div_u64_rem(now, ns << 1, &rem);
6912 		if (rem < ns) {
6913 			/* first half of period */
6914 			if (level == 0) {
6915 				/* output is already low, skip this period */
6916 				systim += ns;
6917 				pr_notice("igb: periodic output on %s missed falling edge\n",
6918 					  adapter->sdp_config[pin].name);
6919 			}
6920 		} else {
6921 			/* second half of period */
6922 			if (level == 1) {
6923 				/* output is already high, skip this period */
6924 				systim += ns;
6925 				pr_notice("igb: periodic output on %s missed rising edge\n",
6926 					  adapter->sdp_config[pin].name);
6927 			}
6928 		}
6929 
6930 		/* for this chip family tv_sec is the upper part of the binary value,
6931 		 * so not seconds
6932 		 */
6933 		ts.tv_nsec = (u32)systim;
6934 		ts.tv_sec  = ((u32)(systim >> 32)) & 0xFF;
6935 	} else {
6936 		ts = timespec64_add(adapter->perout[tsintr_tt].start,
6937 				    adapter->perout[tsintr_tt].period);
6938 	}
6939 
6940 	/* u32 conversion of tv_sec is safe until y2106 */
6941 	wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
6942 	wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec);
6943 	tsauxc = rd32(E1000_TSAUXC);
6944 	tsauxc |= TSAUXC_EN_TT0;
6945 	wr32(E1000_TSAUXC, tsauxc);
6946 	adapter->perout[tsintr_tt].start = ts;
6947 
6948 	spin_unlock(&adapter->tmreg_lock);
6949 }
6950 
6951 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt)
6952 {
6953 	int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt);
6954 	int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0;
6955 	int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0;
6956 	struct e1000_hw *hw = &adapter->hw;
6957 	struct ptp_clock_event event;
6958 	struct timespec64 ts;
6959 	unsigned long flags;
6960 
6961 	if (pin < 0 || pin >= IGB_N_SDP)
6962 		return;
6963 
6964 	if (hw->mac.type == e1000_82580 ||
6965 	    hw->mac.type == e1000_i354 ||
6966 	    hw->mac.type == e1000_i350) {
6967 		u64 ns = rd32(auxstmpl);
6968 
6969 		ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32;
6970 		spin_lock_irqsave(&adapter->tmreg_lock, flags);
6971 		ns = timecounter_cyc2time(&adapter->tc, ns);
6972 		spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
6973 		ts = ns_to_timespec64(ns);
6974 	} else {
6975 		ts.tv_nsec = rd32(auxstmpl);
6976 		ts.tv_sec  = rd32(auxstmph);
6977 	}
6978 
6979 	event.type = PTP_CLOCK_EXTTS;
6980 	event.index = tsintr_tt;
6981 	event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec;
6982 	ptp_clock_event(adapter->ptp_clock, &event);
6983 }
6984 
6985 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6986 {
6987 	struct e1000_hw *hw = &adapter->hw;
6988 	u32 tsicr = rd32(E1000_TSICR);
6989 	struct ptp_clock_event event;
6990 
6991 	if (tsicr & TSINTR_SYS_WRAP) {
6992 		event.type = PTP_CLOCK_PPS;
6993 		if (adapter->ptp_caps.pps)
6994 			ptp_clock_event(adapter->ptp_clock, &event);
6995 	}
6996 
6997 	if (tsicr & E1000_TSICR_TXTS) {
6998 		/* retrieve hardware timestamp */
6999 		schedule_work(&adapter->ptp_tx_work);
7000 	}
7001 
7002 	if (tsicr & TSINTR_TT0)
7003 		igb_perout(adapter, 0);
7004 
7005 	if (tsicr & TSINTR_TT1)
7006 		igb_perout(adapter, 1);
7007 
7008 	if (tsicr & TSINTR_AUTT0)
7009 		igb_extts(adapter, 0);
7010 
7011 	if (tsicr & TSINTR_AUTT1)
7012 		igb_extts(adapter, 1);
7013 }
7014 
7015 static irqreturn_t igb_msix_other(int irq, void *data)
7016 {
7017 	struct igb_adapter *adapter = data;
7018 	struct e1000_hw *hw = &adapter->hw;
7019 	u32 icr = rd32(E1000_ICR);
7020 	/* reading ICR causes bit 31 of EICR to be cleared */
7021 
7022 	if (icr & E1000_ICR_DRSTA)
7023 		schedule_work(&adapter->reset_task);
7024 
7025 	if (icr & E1000_ICR_DOUTSYNC) {
7026 		/* HW is reporting DMA is out of sync */
7027 		adapter->stats.doosync++;
7028 		/* The DMA Out of Sync is also indication of a spoof event
7029 		 * in IOV mode. Check the Wrong VM Behavior register to
7030 		 * see if it is really a spoof event.
7031 		 */
7032 		igb_check_wvbr(adapter);
7033 	}
7034 
7035 	/* Check for a mailbox event */
7036 	if (icr & E1000_ICR_VMMB)
7037 		igb_msg_task(adapter);
7038 
7039 	if (icr & E1000_ICR_LSC) {
7040 		hw->mac.get_link_status = 1;
7041 		/* guard against interrupt when we're going down */
7042 		if (!test_bit(__IGB_DOWN, &adapter->state))
7043 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
7044 	}
7045 
7046 	if (icr & E1000_ICR_TS)
7047 		igb_tsync_interrupt(adapter);
7048 
7049 	wr32(E1000_EIMS, adapter->eims_other);
7050 
7051 	return IRQ_HANDLED;
7052 }
7053 
7054 static void igb_write_itr(struct igb_q_vector *q_vector)
7055 {
7056 	struct igb_adapter *adapter = q_vector->adapter;
7057 	u32 itr_val = q_vector->itr_val & 0x7FFC;
7058 
7059 	if (!q_vector->set_itr)
7060 		return;
7061 
7062 	if (!itr_val)
7063 		itr_val = 0x4;
7064 
7065 	if (adapter->hw.mac.type == e1000_82575)
7066 		itr_val |= itr_val << 16;
7067 	else
7068 		itr_val |= E1000_EITR_CNT_IGNR;
7069 
7070 	writel(itr_val, q_vector->itr_register);
7071 	q_vector->set_itr = 0;
7072 }
7073 
7074 static irqreturn_t igb_msix_ring(int irq, void *data)
7075 {
7076 	struct igb_q_vector *q_vector = data;
7077 
7078 	/* Write the ITR value calculated from the previous interrupt. */
7079 	igb_write_itr(q_vector);
7080 
7081 	napi_schedule(&q_vector->napi);
7082 
7083 	return IRQ_HANDLED;
7084 }
7085 
7086 #ifdef CONFIG_IGB_DCA
7087 static void igb_update_tx_dca(struct igb_adapter *adapter,
7088 			      struct igb_ring *tx_ring,
7089 			      int cpu)
7090 {
7091 	struct e1000_hw *hw = &adapter->hw;
7092 	u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
7093 
7094 	if (hw->mac.type != e1000_82575)
7095 		txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
7096 
7097 	/* We can enable relaxed ordering for reads, but not writes when
7098 	 * DCA is enabled.  This is due to a known issue in some chipsets
7099 	 * which will cause the DCA tag to be cleared.
7100 	 */
7101 	txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
7102 		  E1000_DCA_TXCTRL_DATA_RRO_EN |
7103 		  E1000_DCA_TXCTRL_DESC_DCA_EN;
7104 
7105 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
7106 }
7107 
7108 static void igb_update_rx_dca(struct igb_adapter *adapter,
7109 			      struct igb_ring *rx_ring,
7110 			      int cpu)
7111 {
7112 	struct e1000_hw *hw = &adapter->hw;
7113 	u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
7114 
7115 	if (hw->mac.type != e1000_82575)
7116 		rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
7117 
7118 	/* We can enable relaxed ordering for reads, but not writes when
7119 	 * DCA is enabled.  This is due to a known issue in some chipsets
7120 	 * which will cause the DCA tag to be cleared.
7121 	 */
7122 	rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
7123 		  E1000_DCA_RXCTRL_DESC_DCA_EN;
7124 
7125 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
7126 }
7127 
7128 static void igb_update_dca(struct igb_q_vector *q_vector)
7129 {
7130 	struct igb_adapter *adapter = q_vector->adapter;
7131 	int cpu = get_cpu();
7132 
7133 	if (q_vector->cpu == cpu)
7134 		goto out_no_update;
7135 
7136 	if (q_vector->tx.ring)
7137 		igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
7138 
7139 	if (q_vector->rx.ring)
7140 		igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
7141 
7142 	q_vector->cpu = cpu;
7143 out_no_update:
7144 	put_cpu();
7145 }
7146 
7147 static void igb_setup_dca(struct igb_adapter *adapter)
7148 {
7149 	struct e1000_hw *hw = &adapter->hw;
7150 	int i;
7151 
7152 	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
7153 		return;
7154 
7155 	/* Always use CB2 mode, difference is masked in the CB driver. */
7156 	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
7157 
7158 	for (i = 0; i < adapter->num_q_vectors; i++) {
7159 		adapter->q_vector[i]->cpu = -1;
7160 		igb_update_dca(adapter->q_vector[i]);
7161 	}
7162 }
7163 
7164 static int __igb_notify_dca(struct device *dev, void *data)
7165 {
7166 	struct net_device *netdev = dev_get_drvdata(dev);
7167 	struct igb_adapter *adapter = netdev_priv(netdev);
7168 	struct pci_dev *pdev = adapter->pdev;
7169 	struct e1000_hw *hw = &adapter->hw;
7170 	unsigned long event = *(unsigned long *)data;
7171 
7172 	switch (event) {
7173 	case DCA_PROVIDER_ADD:
7174 		/* if already enabled, don't do it again */
7175 		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
7176 			break;
7177 		if (dca_add_requester(dev) == 0) {
7178 			adapter->flags |= IGB_FLAG_DCA_ENABLED;
7179 			dev_info(&pdev->dev, "DCA enabled\n");
7180 			igb_setup_dca(adapter);
7181 			break;
7182 		}
7183 		fallthrough; /* since DCA is disabled. */
7184 	case DCA_PROVIDER_REMOVE:
7185 		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
7186 			/* without this a class_device is left
7187 			 * hanging around in the sysfs model
7188 			 */
7189 			dca_remove_requester(dev);
7190 			dev_info(&pdev->dev, "DCA disabled\n");
7191 			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
7192 			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
7193 		}
7194 		break;
7195 	}
7196 
7197 	return 0;
7198 }
7199 
7200 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
7201 			  void *p)
7202 {
7203 	int ret_val;
7204 
7205 	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7206 					 __igb_notify_dca);
7207 
7208 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7209 }
7210 #endif /* CONFIG_IGB_DCA */
7211 
7212 #ifdef CONFIG_PCI_IOV
7213 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7214 {
7215 	unsigned char mac_addr[ETH_ALEN];
7216 
7217 	eth_zero_addr(mac_addr);
7218 	igb_set_vf_mac(adapter, vf, mac_addr);
7219 
7220 	/* By default spoof check is enabled for all VFs */
7221 	adapter->vf_data[vf].spoofchk_enabled = true;
7222 
7223 	/* By default VFs are not trusted */
7224 	adapter->vf_data[vf].trusted = false;
7225 
7226 	return 0;
7227 }
7228 
7229 #endif
7230 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7231 {
7232 	struct e1000_hw *hw = &adapter->hw;
7233 	u32 ping;
7234 	int i;
7235 
7236 	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7237 		ping = E1000_PF_CONTROL_MSG;
7238 		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7239 			ping |= E1000_VT_MSGTYPE_CTS;
7240 		igb_write_mbx(hw, &ping, 1, i);
7241 	}
7242 }
7243 
7244 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7245 {
7246 	struct e1000_hw *hw = &adapter->hw;
7247 	u32 vmolr = rd32(E1000_VMOLR(vf));
7248 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7249 
7250 	vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7251 			    IGB_VF_FLAG_MULTI_PROMISC);
7252 	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7253 
7254 	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7255 		vmolr |= E1000_VMOLR_MPME;
7256 		vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7257 		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7258 	} else {
7259 		/* if we have hashes and we are clearing a multicast promisc
7260 		 * flag we need to write the hashes to the MTA as this step
7261 		 * was previously skipped
7262 		 */
7263 		if (vf_data->num_vf_mc_hashes > 30) {
7264 			vmolr |= E1000_VMOLR_MPME;
7265 		} else if (vf_data->num_vf_mc_hashes) {
7266 			int j;
7267 
7268 			vmolr |= E1000_VMOLR_ROMPE;
7269 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7270 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7271 		}
7272 	}
7273 
7274 	wr32(E1000_VMOLR(vf), vmolr);
7275 
7276 	/* there are flags left unprocessed, likely not supported */
7277 	if (*msgbuf & E1000_VT_MSGINFO_MASK)
7278 		return -EINVAL;
7279 
7280 	return 0;
7281 }
7282 
7283 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7284 				  u32 *msgbuf, u32 vf)
7285 {
7286 	int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7287 	u16 *hash_list = (u16 *)&msgbuf[1];
7288 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7289 	int i;
7290 
7291 	/* salt away the number of multicast addresses assigned
7292 	 * to this VF for later use to restore when the PF multi cast
7293 	 * list changes
7294 	 */
7295 	vf_data->num_vf_mc_hashes = n;
7296 
7297 	/* only up to 30 hash values supported */
7298 	if (n > 30)
7299 		n = 30;
7300 
7301 	/* store the hashes for later use */
7302 	for (i = 0; i < n; i++)
7303 		vf_data->vf_mc_hashes[i] = hash_list[i];
7304 
7305 	/* Flush and reset the mta with the new values */
7306 	igb_set_rx_mode(adapter->netdev);
7307 
7308 	return 0;
7309 }
7310 
7311 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7312 {
7313 	struct e1000_hw *hw = &adapter->hw;
7314 	struct vf_data_storage *vf_data;
7315 	int i, j;
7316 
7317 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
7318 		u32 vmolr = rd32(E1000_VMOLR(i));
7319 
7320 		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7321 
7322 		vf_data = &adapter->vf_data[i];
7323 
7324 		if ((vf_data->num_vf_mc_hashes > 30) ||
7325 		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7326 			vmolr |= E1000_VMOLR_MPME;
7327 		} else if (vf_data->num_vf_mc_hashes) {
7328 			vmolr |= E1000_VMOLR_ROMPE;
7329 			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7330 				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7331 		}
7332 		wr32(E1000_VMOLR(i), vmolr);
7333 	}
7334 }
7335 
7336 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7337 {
7338 	struct e1000_hw *hw = &adapter->hw;
7339 	u32 pool_mask, vlvf_mask, i;
7340 
7341 	/* create mask for VF and other pools */
7342 	pool_mask = E1000_VLVF_POOLSEL_MASK;
7343 	vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7344 
7345 	/* drop PF from pool bits */
7346 	pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7347 			     adapter->vfs_allocated_count);
7348 
7349 	/* Find the vlan filter for this id */
7350 	for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7351 		u32 vlvf = rd32(E1000_VLVF(i));
7352 		u32 vfta_mask, vid, vfta;
7353 
7354 		/* remove the vf from the pool */
7355 		if (!(vlvf & vlvf_mask))
7356 			continue;
7357 
7358 		/* clear out bit from VLVF */
7359 		vlvf ^= vlvf_mask;
7360 
7361 		/* if other pools are present, just remove ourselves */
7362 		if (vlvf & pool_mask)
7363 			goto update_vlvfb;
7364 
7365 		/* if PF is present, leave VFTA */
7366 		if (vlvf & E1000_VLVF_POOLSEL_MASK)
7367 			goto update_vlvf;
7368 
7369 		vid = vlvf & E1000_VLVF_VLANID_MASK;
7370 		vfta_mask = BIT(vid % 32);
7371 
7372 		/* clear bit from VFTA */
7373 		vfta = adapter->shadow_vfta[vid / 32];
7374 		if (vfta & vfta_mask)
7375 			hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7376 update_vlvf:
7377 		/* clear pool selection enable */
7378 		if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7379 			vlvf &= E1000_VLVF_POOLSEL_MASK;
7380 		else
7381 			vlvf = 0;
7382 update_vlvfb:
7383 		/* clear pool bits */
7384 		wr32(E1000_VLVF(i), vlvf);
7385 	}
7386 }
7387 
7388 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7389 {
7390 	u32 vlvf;
7391 	int idx;
7392 
7393 	/* short cut the special case */
7394 	if (vlan == 0)
7395 		return 0;
7396 
7397 	/* Search for the VLAN id in the VLVF entries */
7398 	for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7399 		vlvf = rd32(E1000_VLVF(idx));
7400 		if ((vlvf & VLAN_VID_MASK) == vlan)
7401 			break;
7402 	}
7403 
7404 	return idx;
7405 }
7406 
7407 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7408 {
7409 	struct e1000_hw *hw = &adapter->hw;
7410 	u32 bits, pf_id;
7411 	int idx;
7412 
7413 	idx = igb_find_vlvf_entry(hw, vid);
7414 	if (!idx)
7415 		return;
7416 
7417 	/* See if any other pools are set for this VLAN filter
7418 	 * entry other than the PF.
7419 	 */
7420 	pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7421 	bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7422 	bits &= rd32(E1000_VLVF(idx));
7423 
7424 	/* Disable the filter so this falls into the default pool. */
7425 	if (!bits) {
7426 		if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7427 			wr32(E1000_VLVF(idx), BIT(pf_id));
7428 		else
7429 			wr32(E1000_VLVF(idx), 0);
7430 	}
7431 }
7432 
7433 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7434 			   bool add, u32 vf)
7435 {
7436 	int pf_id = adapter->vfs_allocated_count;
7437 	struct e1000_hw *hw = &adapter->hw;
7438 	int err;
7439 
7440 	/* If VLAN overlaps with one the PF is currently monitoring make
7441 	 * sure that we are able to allocate a VLVF entry.  This may be
7442 	 * redundant but it guarantees PF will maintain visibility to
7443 	 * the VLAN.
7444 	 */
7445 	if (add && test_bit(vid, adapter->active_vlans)) {
7446 		err = igb_vfta_set(hw, vid, pf_id, true, false);
7447 		if (err)
7448 			return err;
7449 	}
7450 
7451 	err = igb_vfta_set(hw, vid, vf, add, false);
7452 
7453 	if (add && !err)
7454 		return err;
7455 
7456 	/* If we failed to add the VF VLAN or we are removing the VF VLAN
7457 	 * we may need to drop the PF pool bit in order to allow us to free
7458 	 * up the VLVF resources.
7459 	 */
7460 	if (test_bit(vid, adapter->active_vlans) ||
7461 	    (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7462 		igb_update_pf_vlvf(adapter, vid);
7463 
7464 	return err;
7465 }
7466 
7467 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7468 {
7469 	struct e1000_hw *hw = &adapter->hw;
7470 
7471 	if (vid)
7472 		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7473 	else
7474 		wr32(E1000_VMVIR(vf), 0);
7475 }
7476 
7477 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7478 				u16 vlan, u8 qos)
7479 {
7480 	int err;
7481 
7482 	err = igb_set_vf_vlan(adapter, vlan, true, vf);
7483 	if (err)
7484 		return err;
7485 
7486 	igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7487 	igb_set_vmolr(adapter, vf, !vlan);
7488 
7489 	/* revoke access to previous VLAN */
7490 	if (vlan != adapter->vf_data[vf].pf_vlan)
7491 		igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7492 				false, vf);
7493 
7494 	adapter->vf_data[vf].pf_vlan = vlan;
7495 	adapter->vf_data[vf].pf_qos = qos;
7496 	igb_set_vf_vlan_strip(adapter, vf, true);
7497 	dev_info(&adapter->pdev->dev,
7498 		 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7499 	if (test_bit(__IGB_DOWN, &adapter->state)) {
7500 		dev_warn(&adapter->pdev->dev,
7501 			 "The VF VLAN has been set, but the PF device is not up.\n");
7502 		dev_warn(&adapter->pdev->dev,
7503 			 "Bring the PF device up before attempting to use the VF device.\n");
7504 	}
7505 
7506 	return err;
7507 }
7508 
7509 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7510 {
7511 	/* Restore tagless access via VLAN 0 */
7512 	igb_set_vf_vlan(adapter, 0, true, vf);
7513 
7514 	igb_set_vmvir(adapter, 0, vf);
7515 	igb_set_vmolr(adapter, vf, true);
7516 
7517 	/* Remove any PF assigned VLAN */
7518 	if (adapter->vf_data[vf].pf_vlan)
7519 		igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7520 				false, vf);
7521 
7522 	adapter->vf_data[vf].pf_vlan = 0;
7523 	adapter->vf_data[vf].pf_qos = 0;
7524 	igb_set_vf_vlan_strip(adapter, vf, false);
7525 
7526 	return 0;
7527 }
7528 
7529 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7530 			       u16 vlan, u8 qos, __be16 vlan_proto)
7531 {
7532 	struct igb_adapter *adapter = netdev_priv(netdev);
7533 
7534 	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7535 		return -EINVAL;
7536 
7537 	if (vlan_proto != htons(ETH_P_8021Q))
7538 		return -EPROTONOSUPPORT;
7539 
7540 	return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7541 			       igb_disable_port_vlan(adapter, vf);
7542 }
7543 
7544 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7545 {
7546 	int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
7547 	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7548 	int ret;
7549 
7550 	if (adapter->vf_data[vf].pf_vlan)
7551 		return -1;
7552 
7553 	/* VLAN 0 is a special case, don't allow it to be removed */
7554 	if (!vid && !add)
7555 		return 0;
7556 
7557 	ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7558 	if (!ret)
7559 		igb_set_vf_vlan_strip(adapter, vf, !!vid);
7560 	return ret;
7561 }
7562 
7563 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7564 {
7565 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7566 
7567 	/* clear flags - except flag that indicates PF has set the MAC */
7568 	vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7569 	vf_data->last_nack = jiffies;
7570 
7571 	/* reset vlans for device */
7572 	igb_clear_vf_vfta(adapter, vf);
7573 	igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7574 	igb_set_vmvir(adapter, vf_data->pf_vlan |
7575 			       (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7576 	igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7577 	igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7578 
7579 	/* reset multicast table array for vf */
7580 	adapter->vf_data[vf].num_vf_mc_hashes = 0;
7581 
7582 	/* Flush and reset the mta with the new values */
7583 	igb_set_rx_mode(adapter->netdev);
7584 }
7585 
7586 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7587 {
7588 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7589 
7590 	/* clear mac address as we were hotplug removed/added */
7591 	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7592 		eth_zero_addr(vf_mac);
7593 
7594 	/* process remaining reset events */
7595 	igb_vf_reset(adapter, vf);
7596 }
7597 
7598 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7599 {
7600 	struct e1000_hw *hw = &adapter->hw;
7601 	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7602 	u32 reg, msgbuf[3] = {};
7603 	u8 *addr = (u8 *)(&msgbuf[1]);
7604 
7605 	/* process all the same items cleared in a function level reset */
7606 	igb_vf_reset(adapter, vf);
7607 
7608 	/* set vf mac address */
7609 	igb_set_vf_mac(adapter, vf, vf_mac);
7610 
7611 	/* enable transmit and receive for vf */
7612 	reg = rd32(E1000_VFTE);
7613 	wr32(E1000_VFTE, reg | BIT(vf));
7614 	reg = rd32(E1000_VFRE);
7615 	wr32(E1000_VFRE, reg | BIT(vf));
7616 
7617 	adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7618 
7619 	/* reply to reset with ack and vf mac address */
7620 	if (!is_zero_ether_addr(vf_mac)) {
7621 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7622 		memcpy(addr, vf_mac, ETH_ALEN);
7623 	} else {
7624 		msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7625 	}
7626 	igb_write_mbx(hw, msgbuf, 3, vf);
7627 }
7628 
7629 static void igb_flush_mac_table(struct igb_adapter *adapter)
7630 {
7631 	struct e1000_hw *hw = &adapter->hw;
7632 	int i;
7633 
7634 	for (i = 0; i < hw->mac.rar_entry_count; i++) {
7635 		adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7636 		eth_zero_addr(adapter->mac_table[i].addr);
7637 		adapter->mac_table[i].queue = 0;
7638 		igb_rar_set_index(adapter, i);
7639 	}
7640 }
7641 
7642 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7643 {
7644 	struct e1000_hw *hw = &adapter->hw;
7645 	/* do not count rar entries reserved for VFs MAC addresses */
7646 	int rar_entries = hw->mac.rar_entry_count -
7647 			  adapter->vfs_allocated_count;
7648 	int i, count = 0;
7649 
7650 	for (i = 0; i < rar_entries; i++) {
7651 		/* do not count default entries */
7652 		if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7653 			continue;
7654 
7655 		/* do not count "in use" entries for different queues */
7656 		if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7657 		    (adapter->mac_table[i].queue != queue))
7658 			continue;
7659 
7660 		count++;
7661 	}
7662 
7663 	return count;
7664 }
7665 
7666 /* Set default MAC address for the PF in the first RAR entry */
7667 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7668 {
7669 	struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7670 
7671 	ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7672 	mac_table->queue = adapter->vfs_allocated_count;
7673 	mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7674 
7675 	igb_rar_set_index(adapter, 0);
7676 }
7677 
7678 /* If the filter to be added and an already existing filter express
7679  * the same address and address type, it should be possible to only
7680  * override the other configurations, for example the queue to steer
7681  * traffic.
7682  */
7683 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7684 				      const u8 *addr, const u8 flags)
7685 {
7686 	if (!(entry->state & IGB_MAC_STATE_IN_USE))
7687 		return true;
7688 
7689 	if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7690 	    (flags & IGB_MAC_STATE_SRC_ADDR))
7691 		return false;
7692 
7693 	if (!ether_addr_equal(addr, entry->addr))
7694 		return false;
7695 
7696 	return true;
7697 }
7698 
7699 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7700  * 'flags' is used to indicate what kind of match is made, match is by
7701  * default for the destination address, if matching by source address
7702  * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7703  */
7704 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7705 				    const u8 *addr, const u8 queue,
7706 				    const u8 flags)
7707 {
7708 	struct e1000_hw *hw = &adapter->hw;
7709 	int rar_entries = hw->mac.rar_entry_count -
7710 			  adapter->vfs_allocated_count;
7711 	int i;
7712 
7713 	if (is_zero_ether_addr(addr))
7714 		return -EINVAL;
7715 
7716 	/* Search for the first empty entry in the MAC table.
7717 	 * Do not touch entries at the end of the table reserved for the VF MAC
7718 	 * addresses.
7719 	 */
7720 	for (i = 0; i < rar_entries; i++) {
7721 		if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7722 					       addr, flags))
7723 			continue;
7724 
7725 		ether_addr_copy(adapter->mac_table[i].addr, addr);
7726 		adapter->mac_table[i].queue = queue;
7727 		adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7728 
7729 		igb_rar_set_index(adapter, i);
7730 		return i;
7731 	}
7732 
7733 	return -ENOSPC;
7734 }
7735 
7736 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7737 			      const u8 queue)
7738 {
7739 	return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7740 }
7741 
7742 /* Remove a MAC filter for 'addr' directing matching traffic to
7743  * 'queue', 'flags' is used to indicate what kind of match need to be
7744  * removed, match is by default for the destination address, if
7745  * matching by source address is to be removed the flag
7746  * IGB_MAC_STATE_SRC_ADDR can be used.
7747  */
7748 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7749 				    const u8 *addr, const u8 queue,
7750 				    const u8 flags)
7751 {
7752 	struct e1000_hw *hw = &adapter->hw;
7753 	int rar_entries = hw->mac.rar_entry_count -
7754 			  adapter->vfs_allocated_count;
7755 	int i;
7756 
7757 	if (is_zero_ether_addr(addr))
7758 		return -EINVAL;
7759 
7760 	/* Search for matching entry in the MAC table based on given address
7761 	 * and queue. Do not touch entries at the end of the table reserved
7762 	 * for the VF MAC addresses.
7763 	 */
7764 	for (i = 0; i < rar_entries; i++) {
7765 		if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7766 			continue;
7767 		if ((adapter->mac_table[i].state & flags) != flags)
7768 			continue;
7769 		if (adapter->mac_table[i].queue != queue)
7770 			continue;
7771 		if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7772 			continue;
7773 
7774 		/* When a filter for the default address is "deleted",
7775 		 * we return it to its initial configuration
7776 		 */
7777 		if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7778 			adapter->mac_table[i].state =
7779 				IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7780 			adapter->mac_table[i].queue =
7781 				adapter->vfs_allocated_count;
7782 		} else {
7783 			adapter->mac_table[i].state = 0;
7784 			adapter->mac_table[i].queue = 0;
7785 			eth_zero_addr(adapter->mac_table[i].addr);
7786 		}
7787 
7788 		igb_rar_set_index(adapter, i);
7789 		return 0;
7790 	}
7791 
7792 	return -ENOENT;
7793 }
7794 
7795 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7796 			      const u8 queue)
7797 {
7798 	return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7799 }
7800 
7801 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7802 				const u8 *addr, u8 queue, u8 flags)
7803 {
7804 	struct e1000_hw *hw = &adapter->hw;
7805 
7806 	/* In theory, this should be supported on 82575 as well, but
7807 	 * that part wasn't easily accessible during development.
7808 	 */
7809 	if (hw->mac.type != e1000_i210)
7810 		return -EOPNOTSUPP;
7811 
7812 	return igb_add_mac_filter_flags(adapter, addr, queue,
7813 					IGB_MAC_STATE_QUEUE_STEERING | flags);
7814 }
7815 
7816 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7817 				const u8 *addr, u8 queue, u8 flags)
7818 {
7819 	return igb_del_mac_filter_flags(adapter, addr, queue,
7820 					IGB_MAC_STATE_QUEUE_STEERING | flags);
7821 }
7822 
7823 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7824 {
7825 	struct igb_adapter *adapter = netdev_priv(netdev);
7826 	int ret;
7827 
7828 	ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7829 
7830 	return min_t(int, ret, 0);
7831 }
7832 
7833 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7834 {
7835 	struct igb_adapter *adapter = netdev_priv(netdev);
7836 
7837 	igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7838 
7839 	return 0;
7840 }
7841 
7842 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7843 				 const u32 info, const u8 *addr)
7844 {
7845 	struct pci_dev *pdev = adapter->pdev;
7846 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7847 	struct list_head *pos;
7848 	struct vf_mac_filter *entry = NULL;
7849 	int ret = 0;
7850 
7851 	if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7852 	    !vf_data->trusted) {
7853 		dev_warn(&pdev->dev,
7854 			 "VF %d requested MAC filter but is administratively denied\n",
7855 			  vf);
7856 		return -EINVAL;
7857 	}
7858 	if (!is_valid_ether_addr(addr)) {
7859 		dev_warn(&pdev->dev,
7860 			 "VF %d attempted to set invalid MAC filter\n",
7861 			  vf);
7862 		return -EINVAL;
7863 	}
7864 
7865 	switch (info) {
7866 	case E1000_VF_MAC_FILTER_CLR:
7867 		/* remove all unicast MAC filters related to the current VF */
7868 		list_for_each(pos, &adapter->vf_macs.l) {
7869 			entry = list_entry(pos, struct vf_mac_filter, l);
7870 			if (entry->vf == vf) {
7871 				entry->vf = -1;
7872 				entry->free = true;
7873 				igb_del_mac_filter(adapter, entry->vf_mac, vf);
7874 			}
7875 		}
7876 		break;
7877 	case E1000_VF_MAC_FILTER_ADD:
7878 		/* try to find empty slot in the list */
7879 		list_for_each(pos, &adapter->vf_macs.l) {
7880 			entry = list_entry(pos, struct vf_mac_filter, l);
7881 			if (entry->free)
7882 				break;
7883 		}
7884 
7885 		if (entry && entry->free) {
7886 			entry->free = false;
7887 			entry->vf = vf;
7888 			ether_addr_copy(entry->vf_mac, addr);
7889 
7890 			ret = igb_add_mac_filter(adapter, addr, vf);
7891 			ret = min_t(int, ret, 0);
7892 		} else {
7893 			ret = -ENOSPC;
7894 		}
7895 
7896 		if (ret == -ENOSPC)
7897 			dev_warn(&pdev->dev,
7898 				 "VF %d has requested MAC filter but there is no space for it\n",
7899 				 vf);
7900 		break;
7901 	default:
7902 		ret = -EINVAL;
7903 		break;
7904 	}
7905 
7906 	return ret;
7907 }
7908 
7909 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7910 {
7911 	struct pci_dev *pdev = adapter->pdev;
7912 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7913 	u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7914 
7915 	/* The VF MAC Address is stored in a packed array of bytes
7916 	 * starting at the second 32 bit word of the msg array
7917 	 */
7918 	unsigned char *addr = (unsigned char *)&msg[1];
7919 	int ret = 0;
7920 
7921 	if (!info) {
7922 		if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7923 		    !vf_data->trusted) {
7924 			dev_warn(&pdev->dev,
7925 				 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7926 				 vf);
7927 			return -EINVAL;
7928 		}
7929 
7930 		if (!is_valid_ether_addr(addr)) {
7931 			dev_warn(&pdev->dev,
7932 				 "VF %d attempted to set invalid MAC\n",
7933 				 vf);
7934 			return -EINVAL;
7935 		}
7936 
7937 		ret = igb_set_vf_mac(adapter, vf, addr);
7938 	} else {
7939 		ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7940 	}
7941 
7942 	return ret;
7943 }
7944 
7945 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7946 {
7947 	struct e1000_hw *hw = &adapter->hw;
7948 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7949 	u32 msg = E1000_VT_MSGTYPE_NACK;
7950 
7951 	/* if device isn't clear to send it shouldn't be reading either */
7952 	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7953 	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7954 		igb_write_mbx(hw, &msg, 1, vf);
7955 		vf_data->last_nack = jiffies;
7956 	}
7957 }
7958 
7959 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7960 {
7961 	struct pci_dev *pdev = adapter->pdev;
7962 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
7963 	struct e1000_hw *hw = &adapter->hw;
7964 	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7965 	s32 retval;
7966 
7967 	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7968 
7969 	if (retval) {
7970 		/* if receive failed revoke VF CTS stats and restart init */
7971 		dev_err(&pdev->dev, "Error receiving message from VF\n");
7972 		vf_data->flags &= ~IGB_VF_FLAG_CTS;
7973 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7974 			goto unlock;
7975 		goto out;
7976 	}
7977 
7978 	/* this is a message we already processed, do nothing */
7979 	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7980 		goto unlock;
7981 
7982 	/* until the vf completes a reset it should not be
7983 	 * allowed to start any configuration.
7984 	 */
7985 	if (msgbuf[0] == E1000_VF_RESET) {
7986 		/* unlocks mailbox */
7987 		igb_vf_reset_msg(adapter, vf);
7988 		return;
7989 	}
7990 
7991 	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7992 		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7993 			goto unlock;
7994 		retval = -1;
7995 		goto out;
7996 	}
7997 
7998 	switch ((msgbuf[0] & 0xFFFF)) {
7999 	case E1000_VF_SET_MAC_ADDR:
8000 		retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
8001 		break;
8002 	case E1000_VF_SET_PROMISC:
8003 		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
8004 		break;
8005 	case E1000_VF_SET_MULTICAST:
8006 		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
8007 		break;
8008 	case E1000_VF_SET_LPE:
8009 		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
8010 		break;
8011 	case E1000_VF_SET_VLAN:
8012 		retval = -1;
8013 		if (vf_data->pf_vlan)
8014 			dev_warn(&pdev->dev,
8015 				 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
8016 				 vf);
8017 		else
8018 			retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
8019 		break;
8020 	default:
8021 		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
8022 		retval = -1;
8023 		break;
8024 	}
8025 
8026 	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
8027 out:
8028 	/* notify the VF of the results of what it sent us */
8029 	if (retval)
8030 		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
8031 	else
8032 		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
8033 
8034 	/* unlocks mailbox */
8035 	igb_write_mbx(hw, msgbuf, 1, vf);
8036 	return;
8037 
8038 unlock:
8039 	igb_unlock_mbx(hw, vf);
8040 }
8041 
8042 static void igb_msg_task(struct igb_adapter *adapter)
8043 {
8044 	struct e1000_hw *hw = &adapter->hw;
8045 	unsigned long flags;
8046 	u32 vf;
8047 
8048 	spin_lock_irqsave(&adapter->vfs_lock, flags);
8049 	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
8050 		/* process any reset requests */
8051 		if (!igb_check_for_rst(hw, vf))
8052 			igb_vf_reset_event(adapter, vf);
8053 
8054 		/* process any messages pending */
8055 		if (!igb_check_for_msg(hw, vf))
8056 			igb_rcv_msg_from_vf(adapter, vf);
8057 
8058 		/* process any acks */
8059 		if (!igb_check_for_ack(hw, vf))
8060 			igb_rcv_ack_from_vf(adapter, vf);
8061 	}
8062 	spin_unlock_irqrestore(&adapter->vfs_lock, flags);
8063 }
8064 
8065 /**
8066  *  igb_set_uta - Set unicast filter table address
8067  *  @adapter: board private structure
8068  *  @set: boolean indicating if we are setting or clearing bits
8069  *
8070  *  The unicast table address is a register array of 32-bit registers.
8071  *  The table is meant to be used in a way similar to how the MTA is used
8072  *  however due to certain limitations in the hardware it is necessary to
8073  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
8074  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
8075  **/
8076 static void igb_set_uta(struct igb_adapter *adapter, bool set)
8077 {
8078 	struct e1000_hw *hw = &adapter->hw;
8079 	u32 uta = set ? ~0 : 0;
8080 	int i;
8081 
8082 	/* we only need to do this if VMDq is enabled */
8083 	if (!adapter->vfs_allocated_count)
8084 		return;
8085 
8086 	for (i = hw->mac.uta_reg_count; i--;)
8087 		array_wr32(E1000_UTA, i, uta);
8088 }
8089 
8090 /**
8091  *  igb_intr_msi - Interrupt Handler
8092  *  @irq: interrupt number
8093  *  @data: pointer to a network interface device structure
8094  **/
8095 static irqreturn_t igb_intr_msi(int irq, void *data)
8096 {
8097 	struct igb_adapter *adapter = data;
8098 	struct igb_q_vector *q_vector = adapter->q_vector[0];
8099 	struct e1000_hw *hw = &adapter->hw;
8100 	/* read ICR disables interrupts using IAM */
8101 	u32 icr = rd32(E1000_ICR);
8102 
8103 	igb_write_itr(q_vector);
8104 
8105 	if (icr & E1000_ICR_DRSTA)
8106 		schedule_work(&adapter->reset_task);
8107 
8108 	if (icr & E1000_ICR_DOUTSYNC) {
8109 		/* HW is reporting DMA is out of sync */
8110 		adapter->stats.doosync++;
8111 	}
8112 
8113 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8114 		hw->mac.get_link_status = 1;
8115 		if (!test_bit(__IGB_DOWN, &adapter->state))
8116 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
8117 	}
8118 
8119 	if (icr & E1000_ICR_TS)
8120 		igb_tsync_interrupt(adapter);
8121 
8122 	napi_schedule(&q_vector->napi);
8123 
8124 	return IRQ_HANDLED;
8125 }
8126 
8127 /**
8128  *  igb_intr - Legacy Interrupt Handler
8129  *  @irq: interrupt number
8130  *  @data: pointer to a network interface device structure
8131  **/
8132 static irqreturn_t igb_intr(int irq, void *data)
8133 {
8134 	struct igb_adapter *adapter = data;
8135 	struct igb_q_vector *q_vector = adapter->q_vector[0];
8136 	struct e1000_hw *hw = &adapter->hw;
8137 	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
8138 	 * need for the IMC write
8139 	 */
8140 	u32 icr = rd32(E1000_ICR);
8141 
8142 	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
8143 	 * not set, then the adapter didn't send an interrupt
8144 	 */
8145 	if (!(icr & E1000_ICR_INT_ASSERTED))
8146 		return IRQ_NONE;
8147 
8148 	igb_write_itr(q_vector);
8149 
8150 	if (icr & E1000_ICR_DRSTA)
8151 		schedule_work(&adapter->reset_task);
8152 
8153 	if (icr & E1000_ICR_DOUTSYNC) {
8154 		/* HW is reporting DMA is out of sync */
8155 		adapter->stats.doosync++;
8156 	}
8157 
8158 	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8159 		hw->mac.get_link_status = 1;
8160 		/* guard against interrupt when we're going down */
8161 		if (!test_bit(__IGB_DOWN, &adapter->state))
8162 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
8163 	}
8164 
8165 	if (icr & E1000_ICR_TS)
8166 		igb_tsync_interrupt(adapter);
8167 
8168 	napi_schedule(&q_vector->napi);
8169 
8170 	return IRQ_HANDLED;
8171 }
8172 
8173 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
8174 {
8175 	struct igb_adapter *adapter = q_vector->adapter;
8176 	struct e1000_hw *hw = &adapter->hw;
8177 
8178 	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
8179 	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
8180 		if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
8181 			igb_set_itr(q_vector);
8182 		else
8183 			igb_update_ring_itr(q_vector);
8184 	}
8185 
8186 	if (!test_bit(__IGB_DOWN, &adapter->state)) {
8187 		if (adapter->flags & IGB_FLAG_HAS_MSIX)
8188 			wr32(E1000_EIMS, q_vector->eims_value);
8189 		else
8190 			igb_irq_enable(adapter);
8191 	}
8192 }
8193 
8194 /**
8195  *  igb_poll - NAPI Rx polling callback
8196  *  @napi: napi polling structure
8197  *  @budget: count of how many packets we should handle
8198  **/
8199 static int igb_poll(struct napi_struct *napi, int budget)
8200 {
8201 	struct igb_q_vector *q_vector = container_of(napi,
8202 						     struct igb_q_vector,
8203 						     napi);
8204 	bool clean_complete = true;
8205 	int work_done = 0;
8206 
8207 #ifdef CONFIG_IGB_DCA
8208 	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
8209 		igb_update_dca(q_vector);
8210 #endif
8211 	if (q_vector->tx.ring)
8212 		clean_complete = igb_clean_tx_irq(q_vector, budget);
8213 
8214 	if (q_vector->rx.ring) {
8215 		int cleaned = igb_clean_rx_irq(q_vector, budget);
8216 
8217 		work_done += cleaned;
8218 		if (cleaned >= budget)
8219 			clean_complete = false;
8220 	}
8221 
8222 	/* If all work not completed, return budget and keep polling */
8223 	if (!clean_complete)
8224 		return budget;
8225 
8226 	/* Exit the polling mode, but don't re-enable interrupts if stack might
8227 	 * poll us due to busy-polling
8228 	 */
8229 	if (likely(napi_complete_done(napi, work_done)))
8230 		igb_ring_irq_enable(q_vector);
8231 
8232 	return work_done;
8233 }
8234 
8235 /**
8236  *  igb_clean_tx_irq - Reclaim resources after transmit completes
8237  *  @q_vector: pointer to q_vector containing needed info
8238  *  @napi_budget: Used to determine if we are in netpoll
8239  *
8240  *  returns true if ring is completely cleaned
8241  **/
8242 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8243 {
8244 	struct igb_adapter *adapter = q_vector->adapter;
8245 	struct igb_ring *tx_ring = q_vector->tx.ring;
8246 	struct igb_tx_buffer *tx_buffer;
8247 	union e1000_adv_tx_desc *tx_desc;
8248 	unsigned int total_bytes = 0, total_packets = 0;
8249 	unsigned int budget = q_vector->tx.work_limit;
8250 	unsigned int i = tx_ring->next_to_clean;
8251 
8252 	if (test_bit(__IGB_DOWN, &adapter->state))
8253 		return true;
8254 
8255 	tx_buffer = &tx_ring->tx_buffer_info[i];
8256 	tx_desc = IGB_TX_DESC(tx_ring, i);
8257 	i -= tx_ring->count;
8258 
8259 	do {
8260 		union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8261 
8262 		/* if next_to_watch is not set then there is no work pending */
8263 		if (!eop_desc)
8264 			break;
8265 
8266 		/* prevent any other reads prior to eop_desc */
8267 		smp_rmb();
8268 
8269 		/* if DD is not set pending work has not been completed */
8270 		if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8271 			break;
8272 
8273 		/* clear next_to_watch to prevent false hangs */
8274 		tx_buffer->next_to_watch = NULL;
8275 
8276 		/* update the statistics for this packet */
8277 		total_bytes += tx_buffer->bytecount;
8278 		total_packets += tx_buffer->gso_segs;
8279 
8280 		/* free the skb */
8281 		if (tx_buffer->type == IGB_TYPE_SKB)
8282 			napi_consume_skb(tx_buffer->skb, napi_budget);
8283 		else
8284 			xdp_return_frame(tx_buffer->xdpf);
8285 
8286 		/* unmap skb header data */
8287 		dma_unmap_single(tx_ring->dev,
8288 				 dma_unmap_addr(tx_buffer, dma),
8289 				 dma_unmap_len(tx_buffer, len),
8290 				 DMA_TO_DEVICE);
8291 
8292 		/* clear tx_buffer data */
8293 		dma_unmap_len_set(tx_buffer, len, 0);
8294 
8295 		/* clear last DMA location and unmap remaining buffers */
8296 		while (tx_desc != eop_desc) {
8297 			tx_buffer++;
8298 			tx_desc++;
8299 			i++;
8300 			if (unlikely(!i)) {
8301 				i -= tx_ring->count;
8302 				tx_buffer = tx_ring->tx_buffer_info;
8303 				tx_desc = IGB_TX_DESC(tx_ring, 0);
8304 			}
8305 
8306 			/* unmap any remaining paged data */
8307 			if (dma_unmap_len(tx_buffer, len)) {
8308 				dma_unmap_page(tx_ring->dev,
8309 					       dma_unmap_addr(tx_buffer, dma),
8310 					       dma_unmap_len(tx_buffer, len),
8311 					       DMA_TO_DEVICE);
8312 				dma_unmap_len_set(tx_buffer, len, 0);
8313 			}
8314 		}
8315 
8316 		/* move us one more past the eop_desc for start of next pkt */
8317 		tx_buffer++;
8318 		tx_desc++;
8319 		i++;
8320 		if (unlikely(!i)) {
8321 			i -= tx_ring->count;
8322 			tx_buffer = tx_ring->tx_buffer_info;
8323 			tx_desc = IGB_TX_DESC(tx_ring, 0);
8324 		}
8325 
8326 		/* issue prefetch for next Tx descriptor */
8327 		prefetch(tx_desc);
8328 
8329 		/* update budget accounting */
8330 		budget--;
8331 	} while (likely(budget));
8332 
8333 	netdev_tx_completed_queue(txring_txq(tx_ring),
8334 				  total_packets, total_bytes);
8335 	i += tx_ring->count;
8336 	tx_ring->next_to_clean = i;
8337 	u64_stats_update_begin(&tx_ring->tx_syncp);
8338 	tx_ring->tx_stats.bytes += total_bytes;
8339 	tx_ring->tx_stats.packets += total_packets;
8340 	u64_stats_update_end(&tx_ring->tx_syncp);
8341 	q_vector->tx.total_bytes += total_bytes;
8342 	q_vector->tx.total_packets += total_packets;
8343 
8344 	if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8345 		struct e1000_hw *hw = &adapter->hw;
8346 
8347 		/* Detect a transmit hang in hardware, this serializes the
8348 		 * check with the clearing of time_stamp and movement of i
8349 		 */
8350 		clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8351 		if (tx_buffer->next_to_watch &&
8352 		    time_after(jiffies, tx_buffer->time_stamp +
8353 			       (adapter->tx_timeout_factor * HZ)) &&
8354 		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8355 
8356 			/* detected Tx unit hang */
8357 			dev_err(tx_ring->dev,
8358 				"Detected Tx Unit Hang\n"
8359 				"  Tx Queue             <%d>\n"
8360 				"  TDH                  <%x>\n"
8361 				"  TDT                  <%x>\n"
8362 				"  next_to_use          <%x>\n"
8363 				"  next_to_clean        <%x>\n"
8364 				"buffer_info[next_to_clean]\n"
8365 				"  time_stamp           <%lx>\n"
8366 				"  next_to_watch        <%p>\n"
8367 				"  jiffies              <%lx>\n"
8368 				"  desc.status          <%x>\n",
8369 				tx_ring->queue_index,
8370 				rd32(E1000_TDH(tx_ring->reg_idx)),
8371 				readl(tx_ring->tail),
8372 				tx_ring->next_to_use,
8373 				tx_ring->next_to_clean,
8374 				tx_buffer->time_stamp,
8375 				tx_buffer->next_to_watch,
8376 				jiffies,
8377 				tx_buffer->next_to_watch->wb.status);
8378 			netif_stop_subqueue(tx_ring->netdev,
8379 					    tx_ring->queue_index);
8380 
8381 			/* we are about to reset, no point in enabling stuff */
8382 			return true;
8383 		}
8384 	}
8385 
8386 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8387 	if (unlikely(total_packets &&
8388 	    netif_carrier_ok(tx_ring->netdev) &&
8389 	    igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8390 		/* Make sure that anybody stopping the queue after this
8391 		 * sees the new next_to_clean.
8392 		 */
8393 		smp_mb();
8394 		if (__netif_subqueue_stopped(tx_ring->netdev,
8395 					     tx_ring->queue_index) &&
8396 		    !(test_bit(__IGB_DOWN, &adapter->state))) {
8397 			netif_wake_subqueue(tx_ring->netdev,
8398 					    tx_ring->queue_index);
8399 
8400 			u64_stats_update_begin(&tx_ring->tx_syncp);
8401 			tx_ring->tx_stats.restart_queue++;
8402 			u64_stats_update_end(&tx_ring->tx_syncp);
8403 		}
8404 	}
8405 
8406 	return !!budget;
8407 }
8408 
8409 /**
8410  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
8411  *  @rx_ring: rx descriptor ring to store buffers on
8412  *  @old_buff: donor buffer to have page reused
8413  *
8414  *  Synchronizes page for reuse by the adapter
8415  **/
8416 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8417 			      struct igb_rx_buffer *old_buff)
8418 {
8419 	struct igb_rx_buffer *new_buff;
8420 	u16 nta = rx_ring->next_to_alloc;
8421 
8422 	new_buff = &rx_ring->rx_buffer_info[nta];
8423 
8424 	/* update, and store next to alloc */
8425 	nta++;
8426 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8427 
8428 	/* Transfer page from old buffer to new buffer.
8429 	 * Move each member individually to avoid possible store
8430 	 * forwarding stalls.
8431 	 */
8432 	new_buff->dma		= old_buff->dma;
8433 	new_buff->page		= old_buff->page;
8434 	new_buff->page_offset	= old_buff->page_offset;
8435 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
8436 }
8437 
8438 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8439 				  int rx_buf_pgcnt)
8440 {
8441 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8442 	struct page *page = rx_buffer->page;
8443 
8444 	/* avoid re-using remote and pfmemalloc pages */
8445 	if (!dev_page_is_reusable(page))
8446 		return false;
8447 
8448 #if (PAGE_SIZE < 8192)
8449 	/* if we are only owner of page we can reuse it */
8450 	if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8451 		return false;
8452 #else
8453 #define IGB_LAST_OFFSET \
8454 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8455 
8456 	if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8457 		return false;
8458 #endif
8459 
8460 	/* If we have drained the page fragment pool we need to update
8461 	 * the pagecnt_bias and page count so that we fully restock the
8462 	 * number of references the driver holds.
8463 	 */
8464 	if (unlikely(pagecnt_bias == 1)) {
8465 		page_ref_add(page, USHRT_MAX - 1);
8466 		rx_buffer->pagecnt_bias = USHRT_MAX;
8467 	}
8468 
8469 	return true;
8470 }
8471 
8472 /**
8473  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8474  *  @rx_ring: rx descriptor ring to transact packets on
8475  *  @rx_buffer: buffer containing page to add
8476  *  @skb: sk_buff to place the data into
8477  *  @size: size of buffer to be added
8478  *
8479  *  This function will add the data contained in rx_buffer->page to the skb.
8480  **/
8481 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8482 			    struct igb_rx_buffer *rx_buffer,
8483 			    struct sk_buff *skb,
8484 			    unsigned int size)
8485 {
8486 #if (PAGE_SIZE < 8192)
8487 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8488 #else
8489 	unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8490 				SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8491 				SKB_DATA_ALIGN(size);
8492 #endif
8493 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8494 			rx_buffer->page_offset, size, truesize);
8495 #if (PAGE_SIZE < 8192)
8496 	rx_buffer->page_offset ^= truesize;
8497 #else
8498 	rx_buffer->page_offset += truesize;
8499 #endif
8500 }
8501 
8502 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8503 					 struct igb_rx_buffer *rx_buffer,
8504 					 struct xdp_buff *xdp,
8505 					 ktime_t timestamp)
8506 {
8507 #if (PAGE_SIZE < 8192)
8508 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8509 #else
8510 	unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8511 					       xdp->data_hard_start);
8512 #endif
8513 	unsigned int size = xdp->data_end - xdp->data;
8514 	unsigned int headlen;
8515 	struct sk_buff *skb;
8516 
8517 	/* prefetch first cache line of first page */
8518 	net_prefetch(xdp->data);
8519 
8520 	/* allocate a skb to store the frags */
8521 	skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8522 	if (unlikely(!skb))
8523 		return NULL;
8524 
8525 	if (timestamp)
8526 		skb_hwtstamps(skb)->hwtstamp = timestamp;
8527 
8528 	/* Determine available headroom for copy */
8529 	headlen = size;
8530 	if (headlen > IGB_RX_HDR_LEN)
8531 		headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8532 
8533 	/* align pull length to size of long to optimize memcpy performance */
8534 	memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8535 
8536 	/* update all of the pointers */
8537 	size -= headlen;
8538 	if (size) {
8539 		skb_add_rx_frag(skb, 0, rx_buffer->page,
8540 				(xdp->data + headlen) - page_address(rx_buffer->page),
8541 				size, truesize);
8542 #if (PAGE_SIZE < 8192)
8543 		rx_buffer->page_offset ^= truesize;
8544 #else
8545 		rx_buffer->page_offset += truesize;
8546 #endif
8547 	} else {
8548 		rx_buffer->pagecnt_bias++;
8549 	}
8550 
8551 	return skb;
8552 }
8553 
8554 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8555 				     struct igb_rx_buffer *rx_buffer,
8556 				     struct xdp_buff *xdp,
8557 				     ktime_t timestamp)
8558 {
8559 #if (PAGE_SIZE < 8192)
8560 	unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8561 #else
8562 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8563 				SKB_DATA_ALIGN(xdp->data_end -
8564 					       xdp->data_hard_start);
8565 #endif
8566 	unsigned int metasize = xdp->data - xdp->data_meta;
8567 	struct sk_buff *skb;
8568 
8569 	/* prefetch first cache line of first page */
8570 	net_prefetch(xdp->data_meta);
8571 
8572 	/* build an skb around the page buffer */
8573 	skb = napi_build_skb(xdp->data_hard_start, truesize);
8574 	if (unlikely(!skb))
8575 		return NULL;
8576 
8577 	/* update pointers within the skb to store the data */
8578 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
8579 	__skb_put(skb, xdp->data_end - xdp->data);
8580 
8581 	if (metasize)
8582 		skb_metadata_set(skb, metasize);
8583 
8584 	if (timestamp)
8585 		skb_hwtstamps(skb)->hwtstamp = timestamp;
8586 
8587 	/* update buffer offset */
8588 #if (PAGE_SIZE < 8192)
8589 	rx_buffer->page_offset ^= truesize;
8590 #else
8591 	rx_buffer->page_offset += truesize;
8592 #endif
8593 
8594 	return skb;
8595 }
8596 
8597 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8598 				   struct igb_ring *rx_ring,
8599 				   struct xdp_buff *xdp)
8600 {
8601 	int err, result = IGB_XDP_PASS;
8602 	struct bpf_prog *xdp_prog;
8603 	u32 act;
8604 
8605 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8606 
8607 	if (!xdp_prog)
8608 		goto xdp_out;
8609 
8610 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
8611 
8612 	act = bpf_prog_run_xdp(xdp_prog, xdp);
8613 	switch (act) {
8614 	case XDP_PASS:
8615 		break;
8616 	case XDP_TX:
8617 		result = igb_xdp_xmit_back(adapter, xdp);
8618 		if (result == IGB_XDP_CONSUMED)
8619 			goto out_failure;
8620 		break;
8621 	case XDP_REDIRECT:
8622 		err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8623 		if (err)
8624 			goto out_failure;
8625 		result = IGB_XDP_REDIR;
8626 		break;
8627 	default:
8628 		bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act);
8629 		fallthrough;
8630 	case XDP_ABORTED:
8631 out_failure:
8632 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8633 		fallthrough;
8634 	case XDP_DROP:
8635 		result = IGB_XDP_CONSUMED;
8636 		break;
8637 	}
8638 xdp_out:
8639 	return ERR_PTR(-result);
8640 }
8641 
8642 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8643 					  unsigned int size)
8644 {
8645 	unsigned int truesize;
8646 
8647 #if (PAGE_SIZE < 8192)
8648 	truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8649 #else
8650 	truesize = ring_uses_build_skb(rx_ring) ?
8651 		SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8652 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8653 		SKB_DATA_ALIGN(size);
8654 #endif
8655 	return truesize;
8656 }
8657 
8658 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8659 			       struct igb_rx_buffer *rx_buffer,
8660 			       unsigned int size)
8661 {
8662 	unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8663 #if (PAGE_SIZE < 8192)
8664 	rx_buffer->page_offset ^= truesize;
8665 #else
8666 	rx_buffer->page_offset += truesize;
8667 #endif
8668 }
8669 
8670 static inline void igb_rx_checksum(struct igb_ring *ring,
8671 				   union e1000_adv_rx_desc *rx_desc,
8672 				   struct sk_buff *skb)
8673 {
8674 	skb_checksum_none_assert(skb);
8675 
8676 	/* Ignore Checksum bit is set */
8677 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8678 		return;
8679 
8680 	/* Rx checksum disabled via ethtool */
8681 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
8682 		return;
8683 
8684 	/* TCP/UDP checksum error bit is set */
8685 	if (igb_test_staterr(rx_desc,
8686 			     E1000_RXDEXT_STATERR_TCPE |
8687 			     E1000_RXDEXT_STATERR_IPE)) {
8688 		/* work around errata with sctp packets where the TCPE aka
8689 		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8690 		 * packets, (aka let the stack check the crc32c)
8691 		 */
8692 		if (!((skb->len == 60) &&
8693 		      test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8694 			u64_stats_update_begin(&ring->rx_syncp);
8695 			ring->rx_stats.csum_err++;
8696 			u64_stats_update_end(&ring->rx_syncp);
8697 		}
8698 		/* let the stack verify checksum errors */
8699 		return;
8700 	}
8701 	/* It must be a TCP or UDP packet with a valid checksum */
8702 	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8703 				      E1000_RXD_STAT_UDPCS))
8704 		skb->ip_summed = CHECKSUM_UNNECESSARY;
8705 
8706 	dev_dbg(ring->dev, "cksum success: bits %08X\n",
8707 		le32_to_cpu(rx_desc->wb.upper.status_error));
8708 }
8709 
8710 static inline void igb_rx_hash(struct igb_ring *ring,
8711 			       union e1000_adv_rx_desc *rx_desc,
8712 			       struct sk_buff *skb)
8713 {
8714 	if (ring->netdev->features & NETIF_F_RXHASH)
8715 		skb_set_hash(skb,
8716 			     le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8717 			     PKT_HASH_TYPE_L3);
8718 }
8719 
8720 /**
8721  *  igb_is_non_eop - process handling of non-EOP buffers
8722  *  @rx_ring: Rx ring being processed
8723  *  @rx_desc: Rx descriptor for current buffer
8724  *
8725  *  This function updates next to clean.  If the buffer is an EOP buffer
8726  *  this function exits returning false, otherwise it will place the
8727  *  sk_buff in the next buffer to be chained and return true indicating
8728  *  that this is in fact a non-EOP buffer.
8729  **/
8730 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8731 			   union e1000_adv_rx_desc *rx_desc)
8732 {
8733 	u32 ntc = rx_ring->next_to_clean + 1;
8734 
8735 	/* fetch, update, and store next to clean */
8736 	ntc = (ntc < rx_ring->count) ? ntc : 0;
8737 	rx_ring->next_to_clean = ntc;
8738 
8739 	prefetch(IGB_RX_DESC(rx_ring, ntc));
8740 
8741 	if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8742 		return false;
8743 
8744 	return true;
8745 }
8746 
8747 /**
8748  *  igb_cleanup_headers - Correct corrupted or empty headers
8749  *  @rx_ring: rx descriptor ring packet is being transacted on
8750  *  @rx_desc: pointer to the EOP Rx descriptor
8751  *  @skb: pointer to current skb being fixed
8752  *
8753  *  Address the case where we are pulling data in on pages only
8754  *  and as such no data is present in the skb header.
8755  *
8756  *  In addition if skb is not at least 60 bytes we need to pad it so that
8757  *  it is large enough to qualify as a valid Ethernet frame.
8758  *
8759  *  Returns true if an error was encountered and skb was freed.
8760  **/
8761 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8762 				union e1000_adv_rx_desc *rx_desc,
8763 				struct sk_buff *skb)
8764 {
8765 	/* XDP packets use error pointer so abort at this point */
8766 	if (IS_ERR(skb))
8767 		return true;
8768 
8769 	if (unlikely((igb_test_staterr(rx_desc,
8770 				       E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8771 		struct net_device *netdev = rx_ring->netdev;
8772 		if (!(netdev->features & NETIF_F_RXALL)) {
8773 			dev_kfree_skb_any(skb);
8774 			return true;
8775 		}
8776 	}
8777 
8778 	/* if eth_skb_pad returns an error the skb was freed */
8779 	if (eth_skb_pad(skb))
8780 		return true;
8781 
8782 	return false;
8783 }
8784 
8785 /**
8786  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
8787  *  @rx_ring: rx descriptor ring packet is being transacted on
8788  *  @rx_desc: pointer to the EOP Rx descriptor
8789  *  @skb: pointer to current skb being populated
8790  *
8791  *  This function checks the ring, descriptor, and packet information in
8792  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
8793  *  other fields within the skb.
8794  **/
8795 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8796 				   union e1000_adv_rx_desc *rx_desc,
8797 				   struct sk_buff *skb)
8798 {
8799 	struct net_device *dev = rx_ring->netdev;
8800 
8801 	igb_rx_hash(rx_ring, rx_desc, skb);
8802 
8803 	igb_rx_checksum(rx_ring, rx_desc, skb);
8804 
8805 	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8806 	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8807 		igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8808 
8809 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8810 	    igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8811 		u16 vid;
8812 
8813 		if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8814 		    test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8815 			vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8816 		else
8817 			vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8818 
8819 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8820 	}
8821 
8822 	skb_record_rx_queue(skb, rx_ring->queue_index);
8823 
8824 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8825 }
8826 
8827 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8828 {
8829 	return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8830 }
8831 
8832 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8833 					       const unsigned int size, int *rx_buf_pgcnt)
8834 {
8835 	struct igb_rx_buffer *rx_buffer;
8836 
8837 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8838 	*rx_buf_pgcnt =
8839 #if (PAGE_SIZE < 8192)
8840 		page_count(rx_buffer->page);
8841 #else
8842 		0;
8843 #endif
8844 	prefetchw(rx_buffer->page);
8845 
8846 	/* we are reusing so sync this buffer for CPU use */
8847 	dma_sync_single_range_for_cpu(rx_ring->dev,
8848 				      rx_buffer->dma,
8849 				      rx_buffer->page_offset,
8850 				      size,
8851 				      DMA_FROM_DEVICE);
8852 
8853 	rx_buffer->pagecnt_bias--;
8854 
8855 	return rx_buffer;
8856 }
8857 
8858 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8859 			      struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8860 {
8861 	if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8862 		/* hand second half of page back to the ring */
8863 		igb_reuse_rx_page(rx_ring, rx_buffer);
8864 	} else {
8865 		/* We are not reusing the buffer so unmap it and free
8866 		 * any references we are holding to it
8867 		 */
8868 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8869 				     igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8870 				     IGB_RX_DMA_ATTR);
8871 		__page_frag_cache_drain(rx_buffer->page,
8872 					rx_buffer->pagecnt_bias);
8873 	}
8874 
8875 	/* clear contents of rx_buffer */
8876 	rx_buffer->page = NULL;
8877 }
8878 
8879 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8880 {
8881 	struct igb_adapter *adapter = q_vector->adapter;
8882 	struct igb_ring *rx_ring = q_vector->rx.ring;
8883 	struct sk_buff *skb = rx_ring->skb;
8884 	unsigned int total_bytes = 0, total_packets = 0;
8885 	u16 cleaned_count = igb_desc_unused(rx_ring);
8886 	unsigned int xdp_xmit = 0;
8887 	struct xdp_buff xdp;
8888 	u32 frame_sz = 0;
8889 	int rx_buf_pgcnt;
8890 
8891 	/* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8892 #if (PAGE_SIZE < 8192)
8893 	frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8894 #endif
8895 	xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8896 
8897 	while (likely(total_packets < budget)) {
8898 		union e1000_adv_rx_desc *rx_desc;
8899 		struct igb_rx_buffer *rx_buffer;
8900 		ktime_t timestamp = 0;
8901 		int pkt_offset = 0;
8902 		unsigned int size;
8903 		void *pktbuf;
8904 
8905 		/* return some buffers to hardware, one at a time is too slow */
8906 		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8907 			igb_alloc_rx_buffers(rx_ring, cleaned_count);
8908 			cleaned_count = 0;
8909 		}
8910 
8911 		rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8912 		size = le16_to_cpu(rx_desc->wb.upper.length);
8913 		if (!size)
8914 			break;
8915 
8916 		/* This memory barrier is needed to keep us from reading
8917 		 * any other fields out of the rx_desc until we know the
8918 		 * descriptor has been written back
8919 		 */
8920 		dma_rmb();
8921 
8922 		rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8923 		pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8924 
8925 		/* pull rx packet timestamp if available and valid */
8926 		if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8927 			int ts_hdr_len;
8928 
8929 			ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8930 							 pktbuf, &timestamp);
8931 
8932 			pkt_offset += ts_hdr_len;
8933 			size -= ts_hdr_len;
8934 		}
8935 
8936 		/* retrieve a buffer from the ring */
8937 		if (!skb) {
8938 			unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8939 			unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8940 
8941 			xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8942 			xdp_buff_clear_frags_flag(&xdp);
8943 #if (PAGE_SIZE > 4096)
8944 			/* At larger PAGE_SIZE, frame_sz depend on len size */
8945 			xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8946 #endif
8947 			skb = igb_run_xdp(adapter, rx_ring, &xdp);
8948 		}
8949 
8950 		if (IS_ERR(skb)) {
8951 			unsigned int xdp_res = -PTR_ERR(skb);
8952 
8953 			if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8954 				xdp_xmit |= xdp_res;
8955 				igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8956 			} else {
8957 				rx_buffer->pagecnt_bias++;
8958 			}
8959 			total_packets++;
8960 			total_bytes += size;
8961 		} else if (skb)
8962 			igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8963 		else if (ring_uses_build_skb(rx_ring))
8964 			skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8965 					    timestamp);
8966 		else
8967 			skb = igb_construct_skb(rx_ring, rx_buffer,
8968 						&xdp, timestamp);
8969 
8970 		/* exit if we failed to retrieve a buffer */
8971 		if (!skb) {
8972 			rx_ring->rx_stats.alloc_failed++;
8973 			rx_buffer->pagecnt_bias++;
8974 			break;
8975 		}
8976 
8977 		igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8978 		cleaned_count++;
8979 
8980 		/* fetch next buffer in frame if non-eop */
8981 		if (igb_is_non_eop(rx_ring, rx_desc))
8982 			continue;
8983 
8984 		/* verify the packet layout is correct */
8985 		if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8986 			skb = NULL;
8987 			continue;
8988 		}
8989 
8990 		/* probably a little skewed due to removing CRC */
8991 		total_bytes += skb->len;
8992 
8993 		/* populate checksum, timestamp, VLAN, and protocol */
8994 		igb_process_skb_fields(rx_ring, rx_desc, skb);
8995 
8996 		napi_gro_receive(&q_vector->napi, skb);
8997 
8998 		/* reset skb pointer */
8999 		skb = NULL;
9000 
9001 		/* update budget accounting */
9002 		total_packets++;
9003 	}
9004 
9005 	/* place incomplete frames back on ring for completion */
9006 	rx_ring->skb = skb;
9007 
9008 	if (xdp_xmit & IGB_XDP_REDIR)
9009 		xdp_do_flush();
9010 
9011 	if (xdp_xmit & IGB_XDP_TX) {
9012 		struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
9013 
9014 		igb_xdp_ring_update_tail(tx_ring);
9015 	}
9016 
9017 	u64_stats_update_begin(&rx_ring->rx_syncp);
9018 	rx_ring->rx_stats.packets += total_packets;
9019 	rx_ring->rx_stats.bytes += total_bytes;
9020 	u64_stats_update_end(&rx_ring->rx_syncp);
9021 	q_vector->rx.total_packets += total_packets;
9022 	q_vector->rx.total_bytes += total_bytes;
9023 
9024 	if (cleaned_count)
9025 		igb_alloc_rx_buffers(rx_ring, cleaned_count);
9026 
9027 	return total_packets;
9028 }
9029 
9030 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
9031 				  struct igb_rx_buffer *bi)
9032 {
9033 	struct page *page = bi->page;
9034 	dma_addr_t dma;
9035 
9036 	/* since we are recycling buffers we should seldom need to alloc */
9037 	if (likely(page))
9038 		return true;
9039 
9040 	/* alloc new page for storage */
9041 	page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
9042 	if (unlikely(!page)) {
9043 		rx_ring->rx_stats.alloc_failed++;
9044 		return false;
9045 	}
9046 
9047 	/* map page for use */
9048 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
9049 				 igb_rx_pg_size(rx_ring),
9050 				 DMA_FROM_DEVICE,
9051 				 IGB_RX_DMA_ATTR);
9052 
9053 	/* if mapping failed free memory back to system since
9054 	 * there isn't much point in holding memory we can't use
9055 	 */
9056 	if (dma_mapping_error(rx_ring->dev, dma)) {
9057 		__free_pages(page, igb_rx_pg_order(rx_ring));
9058 
9059 		rx_ring->rx_stats.alloc_failed++;
9060 		return false;
9061 	}
9062 
9063 	bi->dma = dma;
9064 	bi->page = page;
9065 	bi->page_offset = igb_rx_offset(rx_ring);
9066 	page_ref_add(page, USHRT_MAX - 1);
9067 	bi->pagecnt_bias = USHRT_MAX;
9068 
9069 	return true;
9070 }
9071 
9072 /**
9073  *  igb_alloc_rx_buffers - Replace used receive buffers
9074  *  @rx_ring: rx descriptor ring to allocate new receive buffers
9075  *  @cleaned_count: count of buffers to allocate
9076  **/
9077 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9078 {
9079 	union e1000_adv_rx_desc *rx_desc;
9080 	struct igb_rx_buffer *bi;
9081 	u16 i = rx_ring->next_to_use;
9082 	u16 bufsz;
9083 
9084 	/* nothing to do */
9085 	if (!cleaned_count)
9086 		return;
9087 
9088 	rx_desc = IGB_RX_DESC(rx_ring, i);
9089 	bi = &rx_ring->rx_buffer_info[i];
9090 	i -= rx_ring->count;
9091 
9092 	bufsz = igb_rx_bufsz(rx_ring);
9093 
9094 	do {
9095 		if (!igb_alloc_mapped_page(rx_ring, bi))
9096 			break;
9097 
9098 		/* sync the buffer for use by the device */
9099 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
9100 						 bi->page_offset, bufsz,
9101 						 DMA_FROM_DEVICE);
9102 
9103 		/* Refresh the desc even if buffer_addrs didn't change
9104 		 * because each write-back erases this info.
9105 		 */
9106 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9107 
9108 		rx_desc++;
9109 		bi++;
9110 		i++;
9111 		if (unlikely(!i)) {
9112 			rx_desc = IGB_RX_DESC(rx_ring, 0);
9113 			bi = rx_ring->rx_buffer_info;
9114 			i -= rx_ring->count;
9115 		}
9116 
9117 		/* clear the length for the next_to_use descriptor */
9118 		rx_desc->wb.upper.length = 0;
9119 
9120 		cleaned_count--;
9121 	} while (cleaned_count);
9122 
9123 	i += rx_ring->count;
9124 
9125 	if (rx_ring->next_to_use != i) {
9126 		/* record the next descriptor to use */
9127 		rx_ring->next_to_use = i;
9128 
9129 		/* update next to alloc since we have filled the ring */
9130 		rx_ring->next_to_alloc = i;
9131 
9132 		/* Force memory writes to complete before letting h/w
9133 		 * know there are new descriptors to fetch.  (Only
9134 		 * applicable for weak-ordered memory model archs,
9135 		 * such as IA-64).
9136 		 */
9137 		dma_wmb();
9138 		writel(i, rx_ring->tail);
9139 	}
9140 }
9141 
9142 /**
9143  * igb_mii_ioctl -
9144  * @netdev: pointer to netdev struct
9145  * @ifr: interface structure
9146  * @cmd: ioctl command to execute
9147  **/
9148 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9149 {
9150 	struct igb_adapter *adapter = netdev_priv(netdev);
9151 	struct mii_ioctl_data *data = if_mii(ifr);
9152 
9153 	if (adapter->hw.phy.media_type != e1000_media_type_copper)
9154 		return -EOPNOTSUPP;
9155 
9156 	switch (cmd) {
9157 	case SIOCGMIIPHY:
9158 		data->phy_id = adapter->hw.phy.addr;
9159 		break;
9160 	case SIOCGMIIREG:
9161 		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9162 				     &data->val_out))
9163 			return -EIO;
9164 		break;
9165 	case SIOCSMIIREG:
9166 	default:
9167 		return -EOPNOTSUPP;
9168 	}
9169 	return 0;
9170 }
9171 
9172 /**
9173  * igb_ioctl -
9174  * @netdev: pointer to netdev struct
9175  * @ifr: interface structure
9176  * @cmd: ioctl command to execute
9177  **/
9178 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9179 {
9180 	switch (cmd) {
9181 	case SIOCGMIIPHY:
9182 	case SIOCGMIIREG:
9183 	case SIOCSMIIREG:
9184 		return igb_mii_ioctl(netdev, ifr, cmd);
9185 	case SIOCGHWTSTAMP:
9186 		return igb_ptp_get_ts_config(netdev, ifr);
9187 	case SIOCSHWTSTAMP:
9188 		return igb_ptp_set_ts_config(netdev, ifr);
9189 	default:
9190 		return -EOPNOTSUPP;
9191 	}
9192 }
9193 
9194 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9195 {
9196 	struct igb_adapter *adapter = hw->back;
9197 
9198 	pci_read_config_word(adapter->pdev, reg, value);
9199 }
9200 
9201 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9202 {
9203 	struct igb_adapter *adapter = hw->back;
9204 
9205 	pci_write_config_word(adapter->pdev, reg, *value);
9206 }
9207 
9208 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9209 {
9210 	struct igb_adapter *adapter = hw->back;
9211 
9212 	if (pcie_capability_read_word(adapter->pdev, reg, value))
9213 		return -E1000_ERR_CONFIG;
9214 
9215 	return 0;
9216 }
9217 
9218 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9219 {
9220 	struct igb_adapter *adapter = hw->back;
9221 
9222 	if (pcie_capability_write_word(adapter->pdev, reg, *value))
9223 		return -E1000_ERR_CONFIG;
9224 
9225 	return 0;
9226 }
9227 
9228 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9229 {
9230 	struct igb_adapter *adapter = netdev_priv(netdev);
9231 	struct e1000_hw *hw = &adapter->hw;
9232 	u32 ctrl, rctl;
9233 	bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9234 
9235 	if (enable) {
9236 		/* enable VLAN tag insert/strip */
9237 		ctrl = rd32(E1000_CTRL);
9238 		ctrl |= E1000_CTRL_VME;
9239 		wr32(E1000_CTRL, ctrl);
9240 
9241 		/* Disable CFI check */
9242 		rctl = rd32(E1000_RCTL);
9243 		rctl &= ~E1000_RCTL_CFIEN;
9244 		wr32(E1000_RCTL, rctl);
9245 	} else {
9246 		/* disable VLAN tag insert/strip */
9247 		ctrl = rd32(E1000_CTRL);
9248 		ctrl &= ~E1000_CTRL_VME;
9249 		wr32(E1000_CTRL, ctrl);
9250 	}
9251 
9252 	igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9253 }
9254 
9255 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9256 			       __be16 proto, u16 vid)
9257 {
9258 	struct igb_adapter *adapter = netdev_priv(netdev);
9259 	struct e1000_hw *hw = &adapter->hw;
9260 	int pf_id = adapter->vfs_allocated_count;
9261 
9262 	/* add the filter since PF can receive vlans w/o entry in vlvf */
9263 	if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9264 		igb_vfta_set(hw, vid, pf_id, true, !!vid);
9265 
9266 	set_bit(vid, adapter->active_vlans);
9267 
9268 	return 0;
9269 }
9270 
9271 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9272 				__be16 proto, u16 vid)
9273 {
9274 	struct igb_adapter *adapter = netdev_priv(netdev);
9275 	int pf_id = adapter->vfs_allocated_count;
9276 	struct e1000_hw *hw = &adapter->hw;
9277 
9278 	/* remove VID from filter table */
9279 	if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9280 		igb_vfta_set(hw, vid, pf_id, false, true);
9281 
9282 	clear_bit(vid, adapter->active_vlans);
9283 
9284 	return 0;
9285 }
9286 
9287 static void igb_restore_vlan(struct igb_adapter *adapter)
9288 {
9289 	u16 vid = 1;
9290 
9291 	igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9292 	igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9293 
9294 	for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9295 		igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9296 }
9297 
9298 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9299 {
9300 	struct pci_dev *pdev = adapter->pdev;
9301 	struct e1000_mac_info *mac = &adapter->hw.mac;
9302 
9303 	mac->autoneg = 0;
9304 
9305 	/* Make sure dplx is at most 1 bit and lsb of speed is not set
9306 	 * for the switch() below to work
9307 	 */
9308 	if ((spd & 1) || (dplx & ~1))
9309 		goto err_inval;
9310 
9311 	/* Fiber NIC's only allow 1000 gbps Full duplex
9312 	 * and 100Mbps Full duplex for 100baseFx sfp
9313 	 */
9314 	if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9315 		switch (spd + dplx) {
9316 		case SPEED_10 + DUPLEX_HALF:
9317 		case SPEED_10 + DUPLEX_FULL:
9318 		case SPEED_100 + DUPLEX_HALF:
9319 			goto err_inval;
9320 		default:
9321 			break;
9322 		}
9323 	}
9324 
9325 	switch (spd + dplx) {
9326 	case SPEED_10 + DUPLEX_HALF:
9327 		mac->forced_speed_duplex = ADVERTISE_10_HALF;
9328 		break;
9329 	case SPEED_10 + DUPLEX_FULL:
9330 		mac->forced_speed_duplex = ADVERTISE_10_FULL;
9331 		break;
9332 	case SPEED_100 + DUPLEX_HALF:
9333 		mac->forced_speed_duplex = ADVERTISE_100_HALF;
9334 		break;
9335 	case SPEED_100 + DUPLEX_FULL:
9336 		mac->forced_speed_duplex = ADVERTISE_100_FULL;
9337 		break;
9338 	case SPEED_1000 + DUPLEX_FULL:
9339 		mac->autoneg = 1;
9340 		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9341 		break;
9342 	case SPEED_1000 + DUPLEX_HALF: /* not supported */
9343 	default:
9344 		goto err_inval;
9345 	}
9346 
9347 	/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9348 	adapter->hw.phy.mdix = AUTO_ALL_MODES;
9349 
9350 	return 0;
9351 
9352 err_inval:
9353 	dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9354 	return -EINVAL;
9355 }
9356 
9357 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9358 			  bool runtime)
9359 {
9360 	struct net_device *netdev = pci_get_drvdata(pdev);
9361 	struct igb_adapter *adapter = netdev_priv(netdev);
9362 	struct e1000_hw *hw = &adapter->hw;
9363 	u32 ctrl, rctl, status;
9364 	u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9365 	bool wake;
9366 
9367 	rtnl_lock();
9368 	netif_device_detach(netdev);
9369 
9370 	if (netif_running(netdev))
9371 		__igb_close(netdev, true);
9372 
9373 	igb_ptp_suspend(adapter);
9374 
9375 	igb_clear_interrupt_scheme(adapter);
9376 	rtnl_unlock();
9377 
9378 	status = rd32(E1000_STATUS);
9379 	if (status & E1000_STATUS_LU)
9380 		wufc &= ~E1000_WUFC_LNKC;
9381 
9382 	if (wufc) {
9383 		igb_setup_rctl(adapter);
9384 		igb_set_rx_mode(netdev);
9385 
9386 		/* turn on all-multi mode if wake on multicast is enabled */
9387 		if (wufc & E1000_WUFC_MC) {
9388 			rctl = rd32(E1000_RCTL);
9389 			rctl |= E1000_RCTL_MPE;
9390 			wr32(E1000_RCTL, rctl);
9391 		}
9392 
9393 		ctrl = rd32(E1000_CTRL);
9394 		ctrl |= E1000_CTRL_ADVD3WUC;
9395 		wr32(E1000_CTRL, ctrl);
9396 
9397 		/* Allow time for pending master requests to run */
9398 		igb_disable_pcie_master(hw);
9399 
9400 		wr32(E1000_WUC, E1000_WUC_PME_EN);
9401 		wr32(E1000_WUFC, wufc);
9402 	} else {
9403 		wr32(E1000_WUC, 0);
9404 		wr32(E1000_WUFC, 0);
9405 	}
9406 
9407 	wake = wufc || adapter->en_mng_pt;
9408 	if (!wake)
9409 		igb_power_down_link(adapter);
9410 	else
9411 		igb_power_up_link(adapter);
9412 
9413 	if (enable_wake)
9414 		*enable_wake = wake;
9415 
9416 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
9417 	 * would have already happened in close and is redundant.
9418 	 */
9419 	igb_release_hw_control(adapter);
9420 
9421 	pci_disable_device(pdev);
9422 
9423 	return 0;
9424 }
9425 
9426 static void igb_deliver_wake_packet(struct net_device *netdev)
9427 {
9428 	struct igb_adapter *adapter = netdev_priv(netdev);
9429 	struct e1000_hw *hw = &adapter->hw;
9430 	struct sk_buff *skb;
9431 	u32 wupl;
9432 
9433 	wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9434 
9435 	/* WUPM stores only the first 128 bytes of the wake packet.
9436 	 * Read the packet only if we have the whole thing.
9437 	 */
9438 	if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9439 		return;
9440 
9441 	skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9442 	if (!skb)
9443 		return;
9444 
9445 	skb_put(skb, wupl);
9446 
9447 	/* Ensure reads are 32-bit aligned */
9448 	wupl = roundup(wupl, 4);
9449 
9450 	memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9451 
9452 	skb->protocol = eth_type_trans(skb, netdev);
9453 	netif_rx(skb);
9454 }
9455 
9456 static int __maybe_unused igb_suspend(struct device *dev)
9457 {
9458 	return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9459 }
9460 
9461 static int __maybe_unused __igb_resume(struct device *dev, bool rpm)
9462 {
9463 	struct pci_dev *pdev = to_pci_dev(dev);
9464 	struct net_device *netdev = pci_get_drvdata(pdev);
9465 	struct igb_adapter *adapter = netdev_priv(netdev);
9466 	struct e1000_hw *hw = &adapter->hw;
9467 	u32 err, val;
9468 
9469 	pci_set_power_state(pdev, PCI_D0);
9470 	pci_restore_state(pdev);
9471 	pci_save_state(pdev);
9472 
9473 	if (!pci_device_is_present(pdev))
9474 		return -ENODEV;
9475 	err = pci_enable_device_mem(pdev);
9476 	if (err) {
9477 		dev_err(&pdev->dev,
9478 			"igb: Cannot enable PCI device from suspend\n");
9479 		return err;
9480 	}
9481 	pci_set_master(pdev);
9482 
9483 	pci_enable_wake(pdev, PCI_D3hot, 0);
9484 	pci_enable_wake(pdev, PCI_D3cold, 0);
9485 
9486 	if (igb_init_interrupt_scheme(adapter, true)) {
9487 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9488 		return -ENOMEM;
9489 	}
9490 
9491 	igb_reset(adapter);
9492 
9493 	/* let the f/w know that the h/w is now under the control of the
9494 	 * driver.
9495 	 */
9496 	igb_get_hw_control(adapter);
9497 
9498 	val = rd32(E1000_WUS);
9499 	if (val & WAKE_PKT_WUS)
9500 		igb_deliver_wake_packet(netdev);
9501 
9502 	wr32(E1000_WUS, ~0);
9503 
9504 	if (!rpm)
9505 		rtnl_lock();
9506 	if (!err && netif_running(netdev))
9507 		err = __igb_open(netdev, true);
9508 
9509 	if (!err)
9510 		netif_device_attach(netdev);
9511 	if (!rpm)
9512 		rtnl_unlock();
9513 
9514 	return err;
9515 }
9516 
9517 static int __maybe_unused igb_resume(struct device *dev)
9518 {
9519 	return __igb_resume(dev, false);
9520 }
9521 
9522 static int __maybe_unused igb_runtime_idle(struct device *dev)
9523 {
9524 	struct net_device *netdev = dev_get_drvdata(dev);
9525 	struct igb_adapter *adapter = netdev_priv(netdev);
9526 
9527 	if (!igb_has_link(adapter))
9528 		pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9529 
9530 	return -EBUSY;
9531 }
9532 
9533 static int __maybe_unused igb_runtime_suspend(struct device *dev)
9534 {
9535 	return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9536 }
9537 
9538 static int __maybe_unused igb_runtime_resume(struct device *dev)
9539 {
9540 	return __igb_resume(dev, true);
9541 }
9542 
9543 static void igb_shutdown(struct pci_dev *pdev)
9544 {
9545 	bool wake;
9546 
9547 	__igb_shutdown(pdev, &wake, 0);
9548 
9549 	if (system_state == SYSTEM_POWER_OFF) {
9550 		pci_wake_from_d3(pdev, wake);
9551 		pci_set_power_state(pdev, PCI_D3hot);
9552 	}
9553 }
9554 
9555 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9556 {
9557 #ifdef CONFIG_PCI_IOV
9558 	int err;
9559 
9560 	if (num_vfs == 0) {
9561 		return igb_disable_sriov(dev, true);
9562 	} else {
9563 		err = igb_enable_sriov(dev, num_vfs, true);
9564 		return err ? err : num_vfs;
9565 	}
9566 #endif
9567 	return 0;
9568 }
9569 
9570 /**
9571  *  igb_io_error_detected - called when PCI error is detected
9572  *  @pdev: Pointer to PCI device
9573  *  @state: The current pci connection state
9574  *
9575  *  This function is called after a PCI bus error affecting
9576  *  this device has been detected.
9577  **/
9578 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9579 					      pci_channel_state_t state)
9580 {
9581 	struct net_device *netdev = pci_get_drvdata(pdev);
9582 	struct igb_adapter *adapter = netdev_priv(netdev);
9583 
9584 	if (state == pci_channel_io_normal) {
9585 		dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n");
9586 		return PCI_ERS_RESULT_CAN_RECOVER;
9587 	}
9588 
9589 	netif_device_detach(netdev);
9590 
9591 	if (state == pci_channel_io_perm_failure)
9592 		return PCI_ERS_RESULT_DISCONNECT;
9593 
9594 	if (netif_running(netdev))
9595 		igb_down(adapter);
9596 	pci_disable_device(pdev);
9597 
9598 	/* Request a slot reset. */
9599 	return PCI_ERS_RESULT_NEED_RESET;
9600 }
9601 
9602 /**
9603  *  igb_io_slot_reset - called after the pci bus has been reset.
9604  *  @pdev: Pointer to PCI device
9605  *
9606  *  Restart the card from scratch, as if from a cold-boot. Implementation
9607  *  resembles the first-half of the __igb_resume routine.
9608  **/
9609 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9610 {
9611 	struct net_device *netdev = pci_get_drvdata(pdev);
9612 	struct igb_adapter *adapter = netdev_priv(netdev);
9613 	struct e1000_hw *hw = &adapter->hw;
9614 	pci_ers_result_t result;
9615 
9616 	if (pci_enable_device_mem(pdev)) {
9617 		dev_err(&pdev->dev,
9618 			"Cannot re-enable PCI device after reset.\n");
9619 		result = PCI_ERS_RESULT_DISCONNECT;
9620 	} else {
9621 		pci_set_master(pdev);
9622 		pci_restore_state(pdev);
9623 		pci_save_state(pdev);
9624 
9625 		pci_enable_wake(pdev, PCI_D3hot, 0);
9626 		pci_enable_wake(pdev, PCI_D3cold, 0);
9627 
9628 		/* In case of PCI error, adapter lose its HW address
9629 		 * so we should re-assign it here.
9630 		 */
9631 		hw->hw_addr = adapter->io_addr;
9632 
9633 		igb_reset(adapter);
9634 		wr32(E1000_WUS, ~0);
9635 		result = PCI_ERS_RESULT_RECOVERED;
9636 	}
9637 
9638 	return result;
9639 }
9640 
9641 /**
9642  *  igb_io_resume - called when traffic can start flowing again.
9643  *  @pdev: Pointer to PCI device
9644  *
9645  *  This callback is called when the error recovery driver tells us that
9646  *  its OK to resume normal operation. Implementation resembles the
9647  *  second-half of the __igb_resume routine.
9648  */
9649 static void igb_io_resume(struct pci_dev *pdev)
9650 {
9651 	struct net_device *netdev = pci_get_drvdata(pdev);
9652 	struct igb_adapter *adapter = netdev_priv(netdev);
9653 
9654 	if (netif_running(netdev)) {
9655 		if (igb_up(adapter)) {
9656 			dev_err(&pdev->dev, "igb_up failed after reset\n");
9657 			return;
9658 		}
9659 	}
9660 
9661 	netif_device_attach(netdev);
9662 
9663 	/* let the f/w know that the h/w is now under the control of the
9664 	 * driver.
9665 	 */
9666 	igb_get_hw_control(adapter);
9667 }
9668 
9669 /**
9670  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9671  *  @adapter: Pointer to adapter structure
9672  *  @index: Index of the RAR entry which need to be synced with MAC table
9673  **/
9674 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9675 {
9676 	struct e1000_hw *hw = &adapter->hw;
9677 	u32 rar_low, rar_high;
9678 	u8 *addr = adapter->mac_table[index].addr;
9679 
9680 	/* HW expects these to be in network order when they are plugged
9681 	 * into the registers which are little endian.  In order to guarantee
9682 	 * that ordering we need to do an leXX_to_cpup here in order to be
9683 	 * ready for the byteswap that occurs with writel
9684 	 */
9685 	rar_low = le32_to_cpup((__le32 *)(addr));
9686 	rar_high = le16_to_cpup((__le16 *)(addr + 4));
9687 
9688 	/* Indicate to hardware the Address is Valid. */
9689 	if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9690 		if (is_valid_ether_addr(addr))
9691 			rar_high |= E1000_RAH_AV;
9692 
9693 		if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9694 			rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9695 
9696 		switch (hw->mac.type) {
9697 		case e1000_82575:
9698 		case e1000_i210:
9699 			if (adapter->mac_table[index].state &
9700 			    IGB_MAC_STATE_QUEUE_STEERING)
9701 				rar_high |= E1000_RAH_QSEL_ENABLE;
9702 
9703 			rar_high |= E1000_RAH_POOL_1 *
9704 				    adapter->mac_table[index].queue;
9705 			break;
9706 		default:
9707 			rar_high |= E1000_RAH_POOL_1 <<
9708 				    adapter->mac_table[index].queue;
9709 			break;
9710 		}
9711 	}
9712 
9713 	wr32(E1000_RAL(index), rar_low);
9714 	wrfl();
9715 	wr32(E1000_RAH(index), rar_high);
9716 	wrfl();
9717 }
9718 
9719 static int igb_set_vf_mac(struct igb_adapter *adapter,
9720 			  int vf, unsigned char *mac_addr)
9721 {
9722 	struct e1000_hw *hw = &adapter->hw;
9723 	/* VF MAC addresses start at end of receive addresses and moves
9724 	 * towards the first, as a result a collision should not be possible
9725 	 */
9726 	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9727 	unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9728 
9729 	ether_addr_copy(vf_mac_addr, mac_addr);
9730 	ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9731 	adapter->mac_table[rar_entry].queue = vf;
9732 	adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9733 	igb_rar_set_index(adapter, rar_entry);
9734 
9735 	return 0;
9736 }
9737 
9738 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9739 {
9740 	struct igb_adapter *adapter = netdev_priv(netdev);
9741 
9742 	if (vf >= adapter->vfs_allocated_count)
9743 		return -EINVAL;
9744 
9745 	/* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9746 	 * flag and allows to overwrite the MAC via VF netdev.  This
9747 	 * is necessary to allow libvirt a way to restore the original
9748 	 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9749 	 * down a VM.
9750 	 */
9751 	if (is_zero_ether_addr(mac)) {
9752 		adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9753 		dev_info(&adapter->pdev->dev,
9754 			 "remove administratively set MAC on VF %d\n",
9755 			 vf);
9756 	} else if (is_valid_ether_addr(mac)) {
9757 		adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9758 		dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9759 			 mac, vf);
9760 		dev_info(&adapter->pdev->dev,
9761 			 "Reload the VF driver to make this change effective.");
9762 		/* Generate additional warning if PF is down */
9763 		if (test_bit(__IGB_DOWN, &adapter->state)) {
9764 			dev_warn(&adapter->pdev->dev,
9765 				 "The VF MAC address has been set, but the PF device is not up.\n");
9766 			dev_warn(&adapter->pdev->dev,
9767 				 "Bring the PF device up before attempting to use the VF device.\n");
9768 		}
9769 	} else {
9770 		return -EINVAL;
9771 	}
9772 	return igb_set_vf_mac(adapter, vf, mac);
9773 }
9774 
9775 static int igb_link_mbps(int internal_link_speed)
9776 {
9777 	switch (internal_link_speed) {
9778 	case SPEED_100:
9779 		return 100;
9780 	case SPEED_1000:
9781 		return 1000;
9782 	default:
9783 		return 0;
9784 	}
9785 }
9786 
9787 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9788 				  int link_speed)
9789 {
9790 	int rf_dec, rf_int;
9791 	u32 bcnrc_val;
9792 
9793 	if (tx_rate != 0) {
9794 		/* Calculate the rate factor values to set */
9795 		rf_int = link_speed / tx_rate;
9796 		rf_dec = (link_speed - (rf_int * tx_rate));
9797 		rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9798 			 tx_rate;
9799 
9800 		bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9801 		bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9802 			      E1000_RTTBCNRC_RF_INT_MASK);
9803 		bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9804 	} else {
9805 		bcnrc_val = 0;
9806 	}
9807 
9808 	wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9809 	/* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9810 	 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9811 	 */
9812 	wr32(E1000_RTTBCNRM, 0x14);
9813 	wr32(E1000_RTTBCNRC, bcnrc_val);
9814 }
9815 
9816 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9817 {
9818 	int actual_link_speed, i;
9819 	bool reset_rate = false;
9820 
9821 	/* VF TX rate limit was not set or not supported */
9822 	if ((adapter->vf_rate_link_speed == 0) ||
9823 	    (adapter->hw.mac.type != e1000_82576))
9824 		return;
9825 
9826 	actual_link_speed = igb_link_mbps(adapter->link_speed);
9827 	if (actual_link_speed != adapter->vf_rate_link_speed) {
9828 		reset_rate = true;
9829 		adapter->vf_rate_link_speed = 0;
9830 		dev_info(&adapter->pdev->dev,
9831 			 "Link speed has been changed. VF Transmit rate is disabled\n");
9832 	}
9833 
9834 	for (i = 0; i < adapter->vfs_allocated_count; i++) {
9835 		if (reset_rate)
9836 			adapter->vf_data[i].tx_rate = 0;
9837 
9838 		igb_set_vf_rate_limit(&adapter->hw, i,
9839 				      adapter->vf_data[i].tx_rate,
9840 				      actual_link_speed);
9841 	}
9842 }
9843 
9844 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9845 			     int min_tx_rate, int max_tx_rate)
9846 {
9847 	struct igb_adapter *adapter = netdev_priv(netdev);
9848 	struct e1000_hw *hw = &adapter->hw;
9849 	int actual_link_speed;
9850 
9851 	if (hw->mac.type != e1000_82576)
9852 		return -EOPNOTSUPP;
9853 
9854 	if (min_tx_rate)
9855 		return -EINVAL;
9856 
9857 	actual_link_speed = igb_link_mbps(adapter->link_speed);
9858 	if ((vf >= adapter->vfs_allocated_count) ||
9859 	    (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9860 	    (max_tx_rate < 0) ||
9861 	    (max_tx_rate > actual_link_speed))
9862 		return -EINVAL;
9863 
9864 	adapter->vf_rate_link_speed = actual_link_speed;
9865 	adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9866 	igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9867 
9868 	return 0;
9869 }
9870 
9871 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9872 				   bool setting)
9873 {
9874 	struct igb_adapter *adapter = netdev_priv(netdev);
9875 	struct e1000_hw *hw = &adapter->hw;
9876 	u32 reg_val, reg_offset;
9877 
9878 	if (!adapter->vfs_allocated_count)
9879 		return -EOPNOTSUPP;
9880 
9881 	if (vf >= adapter->vfs_allocated_count)
9882 		return -EINVAL;
9883 
9884 	reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9885 	reg_val = rd32(reg_offset);
9886 	if (setting)
9887 		reg_val |= (BIT(vf) |
9888 			    BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9889 	else
9890 		reg_val &= ~(BIT(vf) |
9891 			     BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9892 	wr32(reg_offset, reg_val);
9893 
9894 	adapter->vf_data[vf].spoofchk_enabled = setting;
9895 	return 0;
9896 }
9897 
9898 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9899 {
9900 	struct igb_adapter *adapter = netdev_priv(netdev);
9901 
9902 	if (vf >= adapter->vfs_allocated_count)
9903 		return -EINVAL;
9904 	if (adapter->vf_data[vf].trusted == setting)
9905 		return 0;
9906 
9907 	adapter->vf_data[vf].trusted = setting;
9908 
9909 	dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9910 		 vf, setting ? "" : "not ");
9911 	return 0;
9912 }
9913 
9914 static int igb_ndo_get_vf_config(struct net_device *netdev,
9915 				 int vf, struct ifla_vf_info *ivi)
9916 {
9917 	struct igb_adapter *adapter = netdev_priv(netdev);
9918 	if (vf >= adapter->vfs_allocated_count)
9919 		return -EINVAL;
9920 	ivi->vf = vf;
9921 	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9922 	ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9923 	ivi->min_tx_rate = 0;
9924 	ivi->vlan = adapter->vf_data[vf].pf_vlan;
9925 	ivi->qos = adapter->vf_data[vf].pf_qos;
9926 	ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9927 	ivi->trusted = adapter->vf_data[vf].trusted;
9928 	return 0;
9929 }
9930 
9931 static void igb_vmm_control(struct igb_adapter *adapter)
9932 {
9933 	struct e1000_hw *hw = &adapter->hw;
9934 	u32 reg;
9935 
9936 	switch (hw->mac.type) {
9937 	case e1000_82575:
9938 	case e1000_i210:
9939 	case e1000_i211:
9940 	case e1000_i354:
9941 	default:
9942 		/* replication is not supported for 82575 */
9943 		return;
9944 	case e1000_82576:
9945 		/* notify HW that the MAC is adding vlan tags */
9946 		reg = rd32(E1000_DTXCTL);
9947 		reg |= E1000_DTXCTL_VLAN_ADDED;
9948 		wr32(E1000_DTXCTL, reg);
9949 		fallthrough;
9950 	case e1000_82580:
9951 		/* enable replication vlan tag stripping */
9952 		reg = rd32(E1000_RPLOLR);
9953 		reg |= E1000_RPLOLR_STRVLAN;
9954 		wr32(E1000_RPLOLR, reg);
9955 		fallthrough;
9956 	case e1000_i350:
9957 		/* none of the above registers are supported by i350 */
9958 		break;
9959 	}
9960 
9961 	if (adapter->vfs_allocated_count) {
9962 		igb_vmdq_set_loopback_pf(hw, true);
9963 		igb_vmdq_set_replication_pf(hw, true);
9964 		igb_vmdq_set_anti_spoofing_pf(hw, true,
9965 					      adapter->vfs_allocated_count);
9966 	} else {
9967 		igb_vmdq_set_loopback_pf(hw, false);
9968 		igb_vmdq_set_replication_pf(hw, false);
9969 	}
9970 }
9971 
9972 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9973 {
9974 	struct e1000_hw *hw = &adapter->hw;
9975 	u32 dmac_thr;
9976 	u16 hwm;
9977 	u32 reg;
9978 
9979 	if (hw->mac.type > e1000_82580) {
9980 		if (adapter->flags & IGB_FLAG_DMAC) {
9981 			/* force threshold to 0. */
9982 			wr32(E1000_DMCTXTH, 0);
9983 
9984 			/* DMA Coalescing high water mark needs to be greater
9985 			 * than the Rx threshold. Set hwm to PBA - max frame
9986 			 * size in 16B units, capping it at PBA - 6KB.
9987 			 */
9988 			hwm = 64 * (pba - 6);
9989 			reg = rd32(E1000_FCRTC);
9990 			reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9991 			reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9992 				& E1000_FCRTC_RTH_COAL_MASK);
9993 			wr32(E1000_FCRTC, reg);
9994 
9995 			/* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9996 			 * frame size, capping it at PBA - 10KB.
9997 			 */
9998 			dmac_thr = pba - 10;
9999 			reg = rd32(E1000_DMACR);
10000 			reg &= ~E1000_DMACR_DMACTHR_MASK;
10001 			reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
10002 				& E1000_DMACR_DMACTHR_MASK);
10003 
10004 			/* transition to L0x or L1 if available..*/
10005 			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
10006 
10007 			/* watchdog timer= +-1000 usec in 32usec intervals */
10008 			reg |= (1000 >> 5);
10009 
10010 			/* Disable BMC-to-OS Watchdog Enable */
10011 			if (hw->mac.type != e1000_i354)
10012 				reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
10013 			wr32(E1000_DMACR, reg);
10014 
10015 			/* no lower threshold to disable
10016 			 * coalescing(smart fifb)-UTRESH=0
10017 			 */
10018 			wr32(E1000_DMCRTRH, 0);
10019 
10020 			reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
10021 
10022 			wr32(E1000_DMCTLX, reg);
10023 
10024 			/* free space in tx packet buffer to wake from
10025 			 * DMA coal
10026 			 */
10027 			wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
10028 			     (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
10029 		}
10030 
10031 		if (hw->mac.type >= e1000_i210 ||
10032 		    (adapter->flags & IGB_FLAG_DMAC)) {
10033 			reg = rd32(E1000_PCIEMISC);
10034 			reg |= E1000_PCIEMISC_LX_DECISION;
10035 			wr32(E1000_PCIEMISC, reg);
10036 		} /* endif adapter->dmac is not disabled */
10037 	} else if (hw->mac.type == e1000_82580) {
10038 		u32 reg = rd32(E1000_PCIEMISC);
10039 
10040 		wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
10041 		wr32(E1000_DMACR, 0);
10042 	}
10043 }
10044 
10045 /**
10046  *  igb_read_i2c_byte - Reads 8 bit word over I2C
10047  *  @hw: pointer to hardware structure
10048  *  @byte_offset: byte offset to read
10049  *  @dev_addr: device address
10050  *  @data: value read
10051  *
10052  *  Performs byte read operation over I2C interface at
10053  *  a specified device address.
10054  **/
10055 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10056 		      u8 dev_addr, u8 *data)
10057 {
10058 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10059 	struct i2c_client *this_client = adapter->i2c_client;
10060 	s32 status;
10061 	u16 swfw_mask = 0;
10062 
10063 	if (!this_client)
10064 		return E1000_ERR_I2C;
10065 
10066 	swfw_mask = E1000_SWFW_PHY0_SM;
10067 
10068 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10069 		return E1000_ERR_SWFW_SYNC;
10070 
10071 	status = i2c_smbus_read_byte_data(this_client, byte_offset);
10072 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10073 
10074 	if (status < 0)
10075 		return E1000_ERR_I2C;
10076 	else {
10077 		*data = status;
10078 		return 0;
10079 	}
10080 }
10081 
10082 /**
10083  *  igb_write_i2c_byte - Writes 8 bit word over I2C
10084  *  @hw: pointer to hardware structure
10085  *  @byte_offset: byte offset to write
10086  *  @dev_addr: device address
10087  *  @data: value to write
10088  *
10089  *  Performs byte write operation over I2C interface at
10090  *  a specified device address.
10091  **/
10092 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10093 		       u8 dev_addr, u8 data)
10094 {
10095 	struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10096 	struct i2c_client *this_client = adapter->i2c_client;
10097 	s32 status;
10098 	u16 swfw_mask = E1000_SWFW_PHY0_SM;
10099 
10100 	if (!this_client)
10101 		return E1000_ERR_I2C;
10102 
10103 	if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10104 		return E1000_ERR_SWFW_SYNC;
10105 	status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
10106 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10107 
10108 	if (status)
10109 		return E1000_ERR_I2C;
10110 	else
10111 		return 0;
10112 
10113 }
10114 
10115 int igb_reinit_queues(struct igb_adapter *adapter)
10116 {
10117 	struct net_device *netdev = adapter->netdev;
10118 	struct pci_dev *pdev = adapter->pdev;
10119 	int err = 0;
10120 
10121 	if (netif_running(netdev))
10122 		igb_close(netdev);
10123 
10124 	igb_reset_interrupt_capability(adapter);
10125 
10126 	if (igb_init_interrupt_scheme(adapter, true)) {
10127 		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
10128 		return -ENOMEM;
10129 	}
10130 
10131 	if (netif_running(netdev))
10132 		err = igb_open(netdev);
10133 
10134 	return err;
10135 }
10136 
10137 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
10138 {
10139 	struct igb_nfc_filter *rule;
10140 
10141 	spin_lock(&adapter->nfc_lock);
10142 
10143 	hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10144 		igb_erase_filter(adapter, rule);
10145 
10146 	hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
10147 		igb_erase_filter(adapter, rule);
10148 
10149 	spin_unlock(&adapter->nfc_lock);
10150 }
10151 
10152 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
10153 {
10154 	struct igb_nfc_filter *rule;
10155 
10156 	spin_lock(&adapter->nfc_lock);
10157 
10158 	hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10159 		igb_add_filter(adapter, rule);
10160 
10161 	spin_unlock(&adapter->nfc_lock);
10162 }
10163 /* igb_main.c */
10164