1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #include <linux/module.h> 27 #include <linux/types.h> 28 #include <linux/init.h> 29 #include <linux/bitops.h> 30 #include <linux/vmalloc.h> 31 #include <linux/pagemap.h> 32 #include <linux/netdevice.h> 33 #include <linux/ipv6.h> 34 #include <linux/slab.h> 35 #include <net/checksum.h> 36 #include <net/ip6_checksum.h> 37 #include <linux/net_tstamp.h> 38 #include <linux/mii.h> 39 #include <linux/ethtool.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/pci.h> 43 #include <linux/pci-aspm.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/ip.h> 47 #include <linux/tcp.h> 48 #include <linux/sctp.h> 49 #include <linux/if_ether.h> 50 #include <linux/aer.h> 51 #include <linux/prefetch.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/etherdevice.h> 54 #ifdef CONFIG_IGB_DCA 55 #include <linux/dca.h> 56 #endif 57 #include <linux/i2c.h> 58 #include "igb.h" 59 60 #define MAJ 5 61 #define MIN 4 62 #define BUILD 0 63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 64 __stringify(BUILD) "-k" 65 char igb_driver_name[] = "igb"; 66 char igb_driver_version[] = DRV_VERSION; 67 static const char igb_driver_string[] = 68 "Intel(R) Gigabit Ethernet Network Driver"; 69 static const char igb_copyright[] = 70 "Copyright (c) 2007-2014 Intel Corporation."; 71 72 static const struct e1000_info *igb_info_tbl[] = { 73 [board_82575] = &e1000_82575_info, 74 }; 75 76 static const struct pci_device_id igb_pci_tbl[] = { 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 112 /* required last entry */ 113 {0, } 114 }; 115 116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 117 118 static int igb_setup_all_tx_resources(struct igb_adapter *); 119 static int igb_setup_all_rx_resources(struct igb_adapter *); 120 static void igb_free_all_tx_resources(struct igb_adapter *); 121 static void igb_free_all_rx_resources(struct igb_adapter *); 122 static void igb_setup_mrqc(struct igb_adapter *); 123 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124 static void igb_remove(struct pci_dev *pdev); 125 static int igb_sw_init(struct igb_adapter *); 126 int igb_open(struct net_device *); 127 int igb_close(struct net_device *); 128 static void igb_configure(struct igb_adapter *); 129 static void igb_configure_tx(struct igb_adapter *); 130 static void igb_configure_rx(struct igb_adapter *); 131 static void igb_clean_all_tx_rings(struct igb_adapter *); 132 static void igb_clean_all_rx_rings(struct igb_adapter *); 133 static void igb_clean_tx_ring(struct igb_ring *); 134 static void igb_clean_rx_ring(struct igb_ring *); 135 static void igb_set_rx_mode(struct net_device *); 136 static void igb_update_phy_info(unsigned long); 137 static void igb_watchdog(unsigned long); 138 static void igb_watchdog_task(struct work_struct *); 139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140 static void igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142 static int igb_change_mtu(struct net_device *, int); 143 static int igb_set_mac(struct net_device *, void *); 144 static void igb_set_uta(struct igb_adapter *adapter, bool set); 145 static irqreturn_t igb_intr(int irq, void *); 146 static irqreturn_t igb_intr_msi(int irq, void *); 147 static irqreturn_t igb_msix_other(int irq, void *); 148 static irqreturn_t igb_msix_ring(int irq, void *); 149 #ifdef CONFIG_IGB_DCA 150 static void igb_update_dca(struct igb_q_vector *); 151 static void igb_setup_dca(struct igb_adapter *); 152 #endif /* CONFIG_IGB_DCA */ 153 static int igb_poll(struct napi_struct *, int); 154 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 155 static int igb_clean_rx_irq(struct igb_q_vector *, int); 156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157 static void igb_tx_timeout(struct net_device *); 158 static void igb_reset_task(struct work_struct *); 159 static void igb_vlan_mode(struct net_device *netdev, 160 netdev_features_t features); 161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 163 static void igb_restore_vlan(struct igb_adapter *); 164 static void igb_rar_set_index(struct igb_adapter *, u32); 165 static void igb_ping_all_vfs(struct igb_adapter *); 166 static void igb_msg_task(struct igb_adapter *); 167 static void igb_vmm_control(struct igb_adapter *); 168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 169 static void igb_flush_mac_table(struct igb_adapter *); 170 static int igb_available_rars(struct igb_adapter *, u8); 171 static void igb_set_default_mac_filter(struct igb_adapter *); 172 static int igb_uc_sync(struct net_device *, const unsigned char *); 173 static int igb_uc_unsync(struct net_device *, const unsigned char *); 174 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 175 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 176 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 177 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 178 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 179 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 180 bool setting); 181 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 182 struct ifla_vf_info *ivi); 183 static void igb_check_vf_rate_limit(struct igb_adapter *); 184 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 185 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 186 187 #ifdef CONFIG_PCI_IOV 188 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 189 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 190 static int igb_disable_sriov(struct pci_dev *dev); 191 static int igb_pci_disable_sriov(struct pci_dev *dev); 192 #endif 193 194 #ifdef CONFIG_PM 195 #ifdef CONFIG_PM_SLEEP 196 static int igb_suspend(struct device *); 197 #endif 198 static int igb_resume(struct device *); 199 static int igb_runtime_suspend(struct device *dev); 200 static int igb_runtime_resume(struct device *dev); 201 static int igb_runtime_idle(struct device *dev); 202 static const struct dev_pm_ops igb_pm_ops = { 203 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 204 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 205 igb_runtime_idle) 206 }; 207 #endif 208 static void igb_shutdown(struct pci_dev *); 209 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 210 #ifdef CONFIG_IGB_DCA 211 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 212 static struct notifier_block dca_notifier = { 213 .notifier_call = igb_notify_dca, 214 .next = NULL, 215 .priority = 0 216 }; 217 #endif 218 #ifdef CONFIG_NET_POLL_CONTROLLER 219 /* for netdump / net console */ 220 static void igb_netpoll(struct net_device *); 221 #endif 222 #ifdef CONFIG_PCI_IOV 223 static unsigned int max_vfs; 224 module_param(max_vfs, uint, 0); 225 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 226 #endif /* CONFIG_PCI_IOV */ 227 228 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 229 pci_channel_state_t); 230 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 231 static void igb_io_resume(struct pci_dev *); 232 233 static const struct pci_error_handlers igb_err_handler = { 234 .error_detected = igb_io_error_detected, 235 .slot_reset = igb_io_slot_reset, 236 .resume = igb_io_resume, 237 }; 238 239 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 240 241 static struct pci_driver igb_driver = { 242 .name = igb_driver_name, 243 .id_table = igb_pci_tbl, 244 .probe = igb_probe, 245 .remove = igb_remove, 246 #ifdef CONFIG_PM 247 .driver.pm = &igb_pm_ops, 248 #endif 249 .shutdown = igb_shutdown, 250 .sriov_configure = igb_pci_sriov_configure, 251 .err_handler = &igb_err_handler 252 }; 253 254 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 255 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 256 MODULE_LICENSE("GPL"); 257 MODULE_VERSION(DRV_VERSION); 258 259 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 260 static int debug = -1; 261 module_param(debug, int, 0); 262 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 263 264 struct igb_reg_info { 265 u32 ofs; 266 char *name; 267 }; 268 269 static const struct igb_reg_info igb_reg_info_tbl[] = { 270 271 /* General Registers */ 272 {E1000_CTRL, "CTRL"}, 273 {E1000_STATUS, "STATUS"}, 274 {E1000_CTRL_EXT, "CTRL_EXT"}, 275 276 /* Interrupt Registers */ 277 {E1000_ICR, "ICR"}, 278 279 /* RX Registers */ 280 {E1000_RCTL, "RCTL"}, 281 {E1000_RDLEN(0), "RDLEN"}, 282 {E1000_RDH(0), "RDH"}, 283 {E1000_RDT(0), "RDT"}, 284 {E1000_RXDCTL(0), "RXDCTL"}, 285 {E1000_RDBAL(0), "RDBAL"}, 286 {E1000_RDBAH(0), "RDBAH"}, 287 288 /* TX Registers */ 289 {E1000_TCTL, "TCTL"}, 290 {E1000_TDBAL(0), "TDBAL"}, 291 {E1000_TDBAH(0), "TDBAH"}, 292 {E1000_TDLEN(0), "TDLEN"}, 293 {E1000_TDH(0), "TDH"}, 294 {E1000_TDT(0), "TDT"}, 295 {E1000_TXDCTL(0), "TXDCTL"}, 296 {E1000_TDFH, "TDFH"}, 297 {E1000_TDFT, "TDFT"}, 298 {E1000_TDFHS, "TDFHS"}, 299 {E1000_TDFPC, "TDFPC"}, 300 301 /* List Terminator */ 302 {} 303 }; 304 305 /* igb_regdump - register printout routine */ 306 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 307 { 308 int n = 0; 309 char rname[16]; 310 u32 regs[8]; 311 312 switch (reginfo->ofs) { 313 case E1000_RDLEN(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDLEN(n)); 316 break; 317 case E1000_RDH(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDH(n)); 320 break; 321 case E1000_RDT(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RDT(n)); 324 break; 325 case E1000_RXDCTL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RXDCTL(n)); 328 break; 329 case E1000_RDBAL(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAL(n)); 332 break; 333 case E1000_RDBAH(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAH(n)); 336 break; 337 case E1000_TDBAL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_RDBAL(n)); 340 break; 341 case E1000_TDBAH(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDBAH(n)); 344 break; 345 case E1000_TDLEN(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDLEN(n)); 348 break; 349 case E1000_TDH(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDH(n)); 352 break; 353 case E1000_TDT(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TDT(n)); 356 break; 357 case E1000_TXDCTL(0): 358 for (n = 0; n < 4; n++) 359 regs[n] = rd32(E1000_TXDCTL(n)); 360 break; 361 default: 362 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 363 return; 364 } 365 366 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 367 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 368 regs[2], regs[3]); 369 } 370 371 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 372 static void igb_dump(struct igb_adapter *adapter) 373 { 374 struct net_device *netdev = adapter->netdev; 375 struct e1000_hw *hw = &adapter->hw; 376 struct igb_reg_info *reginfo; 377 struct igb_ring *tx_ring; 378 union e1000_adv_tx_desc *tx_desc; 379 struct my_u0 { u64 a; u64 b; } *u0; 380 struct igb_ring *rx_ring; 381 union e1000_adv_rx_desc *rx_desc; 382 u32 staterr; 383 u16 i, n; 384 385 if (!netif_msg_hw(adapter)) 386 return; 387 388 /* Print netdevice Info */ 389 if (netdev) { 390 dev_info(&adapter->pdev->dev, "Net device Info\n"); 391 pr_info("Device Name state trans_start\n"); 392 pr_info("%-15s %016lX %016lX\n", netdev->name, 393 netdev->state, dev_trans_start(netdev)); 394 } 395 396 /* Print Registers */ 397 dev_info(&adapter->pdev->dev, "Register Dump\n"); 398 pr_info(" Register Name Value\n"); 399 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 400 reginfo->name; reginfo++) { 401 igb_regdump(hw, reginfo); 402 } 403 404 /* Print TX Ring Summary */ 405 if (!netdev || !netif_running(netdev)) 406 goto exit; 407 408 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 409 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 410 for (n = 0; n < adapter->num_tx_queues; n++) { 411 struct igb_tx_buffer *buffer_info; 412 tx_ring = adapter->tx_ring[n]; 413 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 414 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 415 n, tx_ring->next_to_use, tx_ring->next_to_clean, 416 (u64)dma_unmap_addr(buffer_info, dma), 417 dma_unmap_len(buffer_info, len), 418 buffer_info->next_to_watch, 419 (u64)buffer_info->time_stamp); 420 } 421 422 /* Print TX Rings */ 423 if (!netif_msg_tx_done(adapter)) 424 goto rx_ring_summary; 425 426 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 427 428 /* Transmit Descriptor Formats 429 * 430 * Advanced Transmit Descriptor 431 * +--------------------------------------------------------------+ 432 * 0 | Buffer Address [63:0] | 433 * +--------------------------------------------------------------+ 434 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 435 * +--------------------------------------------------------------+ 436 * 63 46 45 40 39 38 36 35 32 31 24 15 0 437 */ 438 439 for (n = 0; n < adapter->num_tx_queues; n++) { 440 tx_ring = adapter->tx_ring[n]; 441 pr_info("------------------------------------\n"); 442 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 443 pr_info("------------------------------------\n"); 444 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 445 446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 447 const char *next_desc; 448 struct igb_tx_buffer *buffer_info; 449 tx_desc = IGB_TX_DESC(tx_ring, i); 450 buffer_info = &tx_ring->tx_buffer_info[i]; 451 u0 = (struct my_u0 *)tx_desc; 452 if (i == tx_ring->next_to_use && 453 i == tx_ring->next_to_clean) 454 next_desc = " NTC/U"; 455 else if (i == tx_ring->next_to_use) 456 next_desc = " NTU"; 457 else if (i == tx_ring->next_to_clean) 458 next_desc = " NTC"; 459 else 460 next_desc = ""; 461 462 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 463 i, le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481 rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 523 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 524 525 for (i = 0; i < rx_ring->count; i++) { 526 const char *next_desc; 527 struct igb_rx_buffer *buffer_info; 528 buffer_info = &rx_ring->rx_buffer_info[i]; 529 rx_desc = IGB_RX_DESC(rx_ring, i); 530 u0 = (struct my_u0 *)rx_desc; 531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 532 533 if (i == rx_ring->next_to_use) 534 next_desc = " NTU"; 535 else if (i == rx_ring->next_to_clean) 536 next_desc = " NTC"; 537 else 538 next_desc = ""; 539 540 if (staterr & E1000_RXD_STAT_DD) { 541 /* Descriptor Done */ 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 543 "RWB", i, 544 le64_to_cpu(u0->a), 545 le64_to_cpu(u0->b), 546 next_desc); 547 } else { 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 549 "R ", i, 550 le64_to_cpu(u0->a), 551 le64_to_cpu(u0->b), 552 (u64)buffer_info->dma, 553 next_desc); 554 555 if (netif_msg_pktdata(adapter) && 556 buffer_info->dma && buffer_info->page) { 557 print_hex_dump(KERN_INFO, "", 558 DUMP_PREFIX_ADDRESS, 559 16, 1, 560 page_address(buffer_info->page) + 561 buffer_info->page_offset, 562 igb_rx_bufsz(rx_ring), true); 563 } 564 } 565 } 566 } 567 568 exit: 569 return; 570 } 571 572 /** 573 * igb_get_i2c_data - Reads the I2C SDA data bit 574 * @hw: pointer to hardware structure 575 * @i2cctl: Current value of I2CCTL register 576 * 577 * Returns the I2C data bit value 578 **/ 579 static int igb_get_i2c_data(void *data) 580 { 581 struct igb_adapter *adapter = (struct igb_adapter *)data; 582 struct e1000_hw *hw = &adapter->hw; 583 s32 i2cctl = rd32(E1000_I2CPARAMS); 584 585 return !!(i2cctl & E1000_I2C_DATA_IN); 586 } 587 588 /** 589 * igb_set_i2c_data - Sets the I2C data bit 590 * @data: pointer to hardware structure 591 * @state: I2C data value (0 or 1) to set 592 * 593 * Sets the I2C data bit 594 **/ 595 static void igb_set_i2c_data(void *data, int state) 596 { 597 struct igb_adapter *adapter = (struct igb_adapter *)data; 598 struct e1000_hw *hw = &adapter->hw; 599 s32 i2cctl = rd32(E1000_I2CPARAMS); 600 601 if (state) 602 i2cctl |= E1000_I2C_DATA_OUT; 603 else 604 i2cctl &= ~E1000_I2C_DATA_OUT; 605 606 i2cctl &= ~E1000_I2C_DATA_OE_N; 607 i2cctl |= E1000_I2C_CLK_OE_N; 608 wr32(E1000_I2CPARAMS, i2cctl); 609 wrfl(); 610 611 } 612 613 /** 614 * igb_set_i2c_clk - Sets the I2C SCL clock 615 * @data: pointer to hardware structure 616 * @state: state to set clock 617 * 618 * Sets the I2C clock line to state 619 **/ 620 static void igb_set_i2c_clk(void *data, int state) 621 { 622 struct igb_adapter *adapter = (struct igb_adapter *)data; 623 struct e1000_hw *hw = &adapter->hw; 624 s32 i2cctl = rd32(E1000_I2CPARAMS); 625 626 if (state) { 627 i2cctl |= E1000_I2C_CLK_OUT; 628 i2cctl &= ~E1000_I2C_CLK_OE_N; 629 } else { 630 i2cctl &= ~E1000_I2C_CLK_OUT; 631 i2cctl &= ~E1000_I2C_CLK_OE_N; 632 } 633 wr32(E1000_I2CPARAMS, i2cctl); 634 wrfl(); 635 } 636 637 /** 638 * igb_get_i2c_clk - Gets the I2C SCL clock state 639 * @data: pointer to hardware structure 640 * 641 * Gets the I2C clock state 642 **/ 643 static int igb_get_i2c_clk(void *data) 644 { 645 struct igb_adapter *adapter = (struct igb_adapter *)data; 646 struct e1000_hw *hw = &adapter->hw; 647 s32 i2cctl = rd32(E1000_I2CPARAMS); 648 649 return !!(i2cctl & E1000_I2C_CLK_IN); 650 } 651 652 static const struct i2c_algo_bit_data igb_i2c_algo = { 653 .setsda = igb_set_i2c_data, 654 .setscl = igb_set_i2c_clk, 655 .getsda = igb_get_i2c_data, 656 .getscl = igb_get_i2c_clk, 657 .udelay = 5, 658 .timeout = 20, 659 }; 660 661 /** 662 * igb_get_hw_dev - return device 663 * @hw: pointer to hardware structure 664 * 665 * used by hardware layer to print debugging information 666 **/ 667 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 668 { 669 struct igb_adapter *adapter = hw->back; 670 return adapter->netdev; 671 } 672 673 /** 674 * igb_init_module - Driver Registration Routine 675 * 676 * igb_init_module is the first routine called when the driver is 677 * loaded. All it does is register with the PCI subsystem. 678 **/ 679 static int __init igb_init_module(void) 680 { 681 int ret; 682 683 pr_info("%s - version %s\n", 684 igb_driver_string, igb_driver_version); 685 pr_info("%s\n", igb_copyright); 686 687 #ifdef CONFIG_IGB_DCA 688 dca_register_notify(&dca_notifier); 689 #endif 690 ret = pci_register_driver(&igb_driver); 691 return ret; 692 } 693 694 module_init(igb_init_module); 695 696 /** 697 * igb_exit_module - Driver Exit Cleanup Routine 698 * 699 * igb_exit_module is called just before the driver is removed 700 * from memory. 701 **/ 702 static void __exit igb_exit_module(void) 703 { 704 #ifdef CONFIG_IGB_DCA 705 dca_unregister_notify(&dca_notifier); 706 #endif 707 pci_unregister_driver(&igb_driver); 708 } 709 710 module_exit(igb_exit_module); 711 712 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 713 /** 714 * igb_cache_ring_register - Descriptor ring to register mapping 715 * @adapter: board private structure to initialize 716 * 717 * Once we know the feature-set enabled for the device, we'll cache 718 * the register offset the descriptor ring is assigned to. 719 **/ 720 static void igb_cache_ring_register(struct igb_adapter *adapter) 721 { 722 int i = 0, j = 0; 723 u32 rbase_offset = adapter->vfs_allocated_count; 724 725 switch (adapter->hw.mac.type) { 726 case e1000_82576: 727 /* The queues are allocated for virtualization such that VF 0 728 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 729 * In order to avoid collision we start at the first free queue 730 * and continue consuming queues in the same sequence 731 */ 732 if (adapter->vfs_allocated_count) { 733 for (; i < adapter->rss_queues; i++) 734 adapter->rx_ring[i]->reg_idx = rbase_offset + 735 Q_IDX_82576(i); 736 } 737 /* Fall through */ 738 case e1000_82575: 739 case e1000_82580: 740 case e1000_i350: 741 case e1000_i354: 742 case e1000_i210: 743 case e1000_i211: 744 /* Fall through */ 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752 } 753 754 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 755 { 756 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 757 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 758 u32 value = 0; 759 760 if (E1000_REMOVED(hw_addr)) 761 return ~value; 762 763 value = readl(&hw_addr[reg]); 764 765 /* reads should not return all F's */ 766 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 767 struct net_device *netdev = igb->netdev; 768 hw->hw_addr = NULL; 769 netif_device_detach(netdev); 770 netdev_err(netdev, "PCIe link lost, device now detached\n"); 771 } 772 773 return value; 774 } 775 776 /** 777 * igb_write_ivar - configure ivar for given MSI-X vector 778 * @hw: pointer to the HW structure 779 * @msix_vector: vector number we are allocating to a given ring 780 * @index: row index of IVAR register to write within IVAR table 781 * @offset: column offset of in IVAR, should be multiple of 8 782 * 783 * This function is intended to handle the writing of the IVAR register 784 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 785 * each containing an cause allocation for an Rx and Tx ring, and a 786 * variable number of rows depending on the number of queues supported. 787 **/ 788 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 789 int index, int offset) 790 { 791 u32 ivar = array_rd32(E1000_IVAR0, index); 792 793 /* clear any bits that are currently set */ 794 ivar &= ~((u32)0xFF << offset); 795 796 /* write vector and valid bit */ 797 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 798 799 array_wr32(E1000_IVAR0, index, ivar); 800 } 801 802 #define IGB_N0_QUEUE -1 803 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 804 { 805 struct igb_adapter *adapter = q_vector->adapter; 806 struct e1000_hw *hw = &adapter->hw; 807 int rx_queue = IGB_N0_QUEUE; 808 int tx_queue = IGB_N0_QUEUE; 809 u32 msixbm = 0; 810 811 if (q_vector->rx.ring) 812 rx_queue = q_vector->rx.ring->reg_idx; 813 if (q_vector->tx.ring) 814 tx_queue = q_vector->tx.ring->reg_idx; 815 816 switch (hw->mac.type) { 817 case e1000_82575: 818 /* The 82575 assigns vectors using a bitmask, which matches the 819 * bitmask for the EICR/EIMS/EIMC registers. To assign one 820 * or more queues to a vector, we write the appropriate bits 821 * into the MSIXBM register for that vector. 822 */ 823 if (rx_queue > IGB_N0_QUEUE) 824 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 825 if (tx_queue > IGB_N0_QUEUE) 826 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 827 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 828 msixbm |= E1000_EIMS_OTHER; 829 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 830 q_vector->eims_value = msixbm; 831 break; 832 case e1000_82576: 833 /* 82576 uses a table that essentially consists of 2 columns 834 * with 8 rows. The ordering is column-major so we use the 835 * lower 3 bits as the row index, and the 4th bit as the 836 * column offset. 837 */ 838 if (rx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 rx_queue & 0x7, 841 (rx_queue & 0x8) << 1); 842 if (tx_queue > IGB_N0_QUEUE) 843 igb_write_ivar(hw, msix_vector, 844 tx_queue & 0x7, 845 ((tx_queue & 0x8) << 1) + 8); 846 q_vector->eims_value = BIT(msix_vector); 847 break; 848 case e1000_82580: 849 case e1000_i350: 850 case e1000_i354: 851 case e1000_i210: 852 case e1000_i211: 853 /* On 82580 and newer adapters the scheme is similar to 82576 854 * however instead of ordering column-major we have things 855 * ordered row-major. So we traverse the table by using 856 * bit 0 as the column offset, and the remaining bits as the 857 * row index. 858 */ 859 if (rx_queue > IGB_N0_QUEUE) 860 igb_write_ivar(hw, msix_vector, 861 rx_queue >> 1, 862 (rx_queue & 0x1) << 4); 863 if (tx_queue > IGB_N0_QUEUE) 864 igb_write_ivar(hw, msix_vector, 865 tx_queue >> 1, 866 ((tx_queue & 0x1) << 4) + 8); 867 q_vector->eims_value = BIT(msix_vector); 868 break; 869 default: 870 BUG(); 871 break; 872 } 873 874 /* add q_vector eims value to global eims_enable_mask */ 875 adapter->eims_enable_mask |= q_vector->eims_value; 876 877 /* configure q_vector to set itr on first interrupt */ 878 q_vector->set_itr = 1; 879 } 880 881 /** 882 * igb_configure_msix - Configure MSI-X hardware 883 * @adapter: board private structure to initialize 884 * 885 * igb_configure_msix sets up the hardware to properly 886 * generate MSI-X interrupts. 887 **/ 888 static void igb_configure_msix(struct igb_adapter *adapter) 889 { 890 u32 tmp; 891 int i, vector = 0; 892 struct e1000_hw *hw = &adapter->hw; 893 894 adapter->eims_enable_mask = 0; 895 896 /* set vector for other causes, i.e. link changes */ 897 switch (hw->mac.type) { 898 case e1000_82575: 899 tmp = rd32(E1000_CTRL_EXT); 900 /* enable MSI-X PBA support*/ 901 tmp |= E1000_CTRL_EXT_PBA_CLR; 902 903 /* Auto-Mask interrupts upon ICR read. */ 904 tmp |= E1000_CTRL_EXT_EIAME; 905 tmp |= E1000_CTRL_EXT_IRCA; 906 907 wr32(E1000_CTRL_EXT, tmp); 908 909 /* enable msix_other interrupt */ 910 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 911 adapter->eims_other = E1000_EIMS_OTHER; 912 913 break; 914 915 case e1000_82576: 916 case e1000_82580: 917 case e1000_i350: 918 case e1000_i354: 919 case e1000_i210: 920 case e1000_i211: 921 /* Turn on MSI-X capability first, or our settings 922 * won't stick. And it will take days to debug. 923 */ 924 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 925 E1000_GPIE_PBA | E1000_GPIE_EIAME | 926 E1000_GPIE_NSICR); 927 928 /* enable msix_other interrupt */ 929 adapter->eims_other = BIT(vector); 930 tmp = (vector++ | E1000_IVAR_VALID) << 8; 931 932 wr32(E1000_IVAR_MISC, tmp); 933 break; 934 default: 935 /* do nothing, since nothing else supports MSI-X */ 936 break; 937 } /* switch (hw->mac.type) */ 938 939 adapter->eims_enable_mask |= adapter->eims_other; 940 941 for (i = 0; i < adapter->num_q_vectors; i++) 942 igb_assign_vector(adapter->q_vector[i], vector++); 943 944 wrfl(); 945 } 946 947 /** 948 * igb_request_msix - Initialize MSI-X interrupts 949 * @adapter: board private structure to initialize 950 * 951 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 952 * kernel. 953 **/ 954 static int igb_request_msix(struct igb_adapter *adapter) 955 { 956 struct net_device *netdev = adapter->netdev; 957 int i, err = 0, vector = 0, free_vector = 0; 958 959 err = request_irq(adapter->msix_entries[vector].vector, 960 igb_msix_other, 0, netdev->name, adapter); 961 if (err) 962 goto err_out; 963 964 for (i = 0; i < adapter->num_q_vectors; i++) { 965 struct igb_q_vector *q_vector = adapter->q_vector[i]; 966 967 vector++; 968 969 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 970 971 if (q_vector->rx.ring && q_vector->tx.ring) 972 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 973 q_vector->rx.ring->queue_index); 974 else if (q_vector->tx.ring) 975 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 976 q_vector->tx.ring->queue_index); 977 else if (q_vector->rx.ring) 978 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 979 q_vector->rx.ring->queue_index); 980 else 981 sprintf(q_vector->name, "%s-unused", netdev->name); 982 983 err = request_irq(adapter->msix_entries[vector].vector, 984 igb_msix_ring, 0, q_vector->name, 985 q_vector); 986 if (err) 987 goto err_free; 988 } 989 990 igb_configure_msix(adapter); 991 return 0; 992 993 err_free: 994 /* free already assigned IRQs */ 995 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 996 997 vector--; 998 for (i = 0; i < vector; i++) { 999 free_irq(adapter->msix_entries[free_vector++].vector, 1000 adapter->q_vector[i]); 1001 } 1002 err_out: 1003 return err; 1004 } 1005 1006 /** 1007 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1008 * @adapter: board private structure to initialize 1009 * @v_idx: Index of vector to be freed 1010 * 1011 * This function frees the memory allocated to the q_vector. 1012 **/ 1013 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1014 { 1015 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1016 1017 adapter->q_vector[v_idx] = NULL; 1018 1019 /* igb_get_stats64() might access the rings on this vector, 1020 * we must wait a grace period before freeing it. 1021 */ 1022 if (q_vector) 1023 kfree_rcu(q_vector, rcu); 1024 } 1025 1026 /** 1027 * igb_reset_q_vector - Reset config for interrupt vector 1028 * @adapter: board private structure to initialize 1029 * @v_idx: Index of vector to be reset 1030 * 1031 * If NAPI is enabled it will delete any references to the 1032 * NAPI struct. This is preparation for igb_free_q_vector. 1033 **/ 1034 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1035 { 1036 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1037 1038 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1039 * allocated. So, q_vector is NULL so we should stop here. 1040 */ 1041 if (!q_vector) 1042 return; 1043 1044 if (q_vector->tx.ring) 1045 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1046 1047 if (q_vector->rx.ring) 1048 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1049 1050 netif_napi_del(&q_vector->napi); 1051 1052 } 1053 1054 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1055 { 1056 int v_idx = adapter->num_q_vectors; 1057 1058 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1059 pci_disable_msix(adapter->pdev); 1060 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1061 pci_disable_msi(adapter->pdev); 1062 1063 while (v_idx--) 1064 igb_reset_q_vector(adapter, v_idx); 1065 } 1066 1067 /** 1068 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function frees the memory allocated to the q_vectors. In addition if 1072 * NAPI is enabled it will delete any references to the NAPI struct prior 1073 * to freeing the q_vector. 1074 **/ 1075 static void igb_free_q_vectors(struct igb_adapter *adapter) 1076 { 1077 int v_idx = adapter->num_q_vectors; 1078 1079 adapter->num_tx_queues = 0; 1080 adapter->num_rx_queues = 0; 1081 adapter->num_q_vectors = 0; 1082 1083 while (v_idx--) { 1084 igb_reset_q_vector(adapter, v_idx); 1085 igb_free_q_vector(adapter, v_idx); 1086 } 1087 } 1088 1089 /** 1090 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1091 * @adapter: board private structure to initialize 1092 * 1093 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1094 * MSI-X interrupts allocated. 1095 */ 1096 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1097 { 1098 igb_free_q_vectors(adapter); 1099 igb_reset_interrupt_capability(adapter); 1100 } 1101 1102 /** 1103 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1104 * @adapter: board private structure to initialize 1105 * @msix: boolean value of MSIX capability 1106 * 1107 * Attempt to configure interrupts using the best available 1108 * capabilities of the hardware and kernel. 1109 **/ 1110 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1111 { 1112 int err; 1113 int numvecs, i; 1114 1115 if (!msix) 1116 goto msi_only; 1117 adapter->flags |= IGB_FLAG_HAS_MSIX; 1118 1119 /* Number of supported queues. */ 1120 adapter->num_rx_queues = adapter->rss_queues; 1121 if (adapter->vfs_allocated_count) 1122 adapter->num_tx_queues = 1; 1123 else 1124 adapter->num_tx_queues = adapter->rss_queues; 1125 1126 /* start with one vector for every Rx queue */ 1127 numvecs = adapter->num_rx_queues; 1128 1129 /* if Tx handler is separate add 1 for every Tx queue */ 1130 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1131 numvecs += adapter->num_tx_queues; 1132 1133 /* store the number of vectors reserved for queues */ 1134 adapter->num_q_vectors = numvecs; 1135 1136 /* add 1 vector for link status interrupts */ 1137 numvecs++; 1138 for (i = 0; i < numvecs; i++) 1139 adapter->msix_entries[i].entry = i; 1140 1141 err = pci_enable_msix_range(adapter->pdev, 1142 adapter->msix_entries, 1143 numvecs, 1144 numvecs); 1145 if (err > 0) 1146 return; 1147 1148 igb_reset_interrupt_capability(adapter); 1149 1150 /* If we can't do MSI-X, try MSI */ 1151 msi_only: 1152 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1153 #ifdef CONFIG_PCI_IOV 1154 /* disable SR-IOV for non MSI-X configurations */ 1155 if (adapter->vf_data) { 1156 struct e1000_hw *hw = &adapter->hw; 1157 /* disable iov and allow time for transactions to clear */ 1158 pci_disable_sriov(adapter->pdev); 1159 msleep(500); 1160 1161 kfree(adapter->vf_mac_list); 1162 adapter->vf_mac_list = NULL; 1163 kfree(adapter->vf_data); 1164 adapter->vf_data = NULL; 1165 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1166 wrfl(); 1167 msleep(100); 1168 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1169 } 1170 #endif 1171 adapter->vfs_allocated_count = 0; 1172 adapter->rss_queues = 1; 1173 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1174 adapter->num_rx_queues = 1; 1175 adapter->num_tx_queues = 1; 1176 adapter->num_q_vectors = 1; 1177 if (!pci_enable_msi(adapter->pdev)) 1178 adapter->flags |= IGB_FLAG_HAS_MSI; 1179 } 1180 1181 static void igb_add_ring(struct igb_ring *ring, 1182 struct igb_ring_container *head) 1183 { 1184 head->ring = ring; 1185 head->count++; 1186 } 1187 1188 /** 1189 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1190 * @adapter: board private structure to initialize 1191 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1192 * @v_idx: index of vector in adapter struct 1193 * @txr_count: total number of Tx rings to allocate 1194 * @txr_idx: index of first Tx ring to allocate 1195 * @rxr_count: total number of Rx rings to allocate 1196 * @rxr_idx: index of first Rx ring to allocate 1197 * 1198 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1199 **/ 1200 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1201 int v_count, int v_idx, 1202 int txr_count, int txr_idx, 1203 int rxr_count, int rxr_idx) 1204 { 1205 struct igb_q_vector *q_vector; 1206 struct igb_ring *ring; 1207 int ring_count, size; 1208 1209 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1210 if (txr_count > 1 || rxr_count > 1) 1211 return -ENOMEM; 1212 1213 ring_count = txr_count + rxr_count; 1214 size = sizeof(struct igb_q_vector) + 1215 (sizeof(struct igb_ring) * ring_count); 1216 1217 /* allocate q_vector and rings */ 1218 q_vector = adapter->q_vector[v_idx]; 1219 if (!q_vector) { 1220 q_vector = kzalloc(size, GFP_KERNEL); 1221 } else if (size > ksize(q_vector)) { 1222 kfree_rcu(q_vector, rcu); 1223 q_vector = kzalloc(size, GFP_KERNEL); 1224 } else { 1225 memset(q_vector, 0, size); 1226 } 1227 if (!q_vector) 1228 return -ENOMEM; 1229 1230 /* initialize NAPI */ 1231 netif_napi_add(adapter->netdev, &q_vector->napi, 1232 igb_poll, 64); 1233 1234 /* tie q_vector and adapter together */ 1235 adapter->q_vector[v_idx] = q_vector; 1236 q_vector->adapter = adapter; 1237 1238 /* initialize work limits */ 1239 q_vector->tx.work_limit = adapter->tx_work_limit; 1240 1241 /* initialize ITR configuration */ 1242 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1243 q_vector->itr_val = IGB_START_ITR; 1244 1245 /* initialize pointer to rings */ 1246 ring = q_vector->ring; 1247 1248 /* intialize ITR */ 1249 if (rxr_count) { 1250 /* rx or rx/tx vector */ 1251 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1252 q_vector->itr_val = adapter->rx_itr_setting; 1253 } else { 1254 /* tx only vector */ 1255 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1256 q_vector->itr_val = adapter->tx_itr_setting; 1257 } 1258 1259 if (txr_count) { 1260 /* assign generic ring traits */ 1261 ring->dev = &adapter->pdev->dev; 1262 ring->netdev = adapter->netdev; 1263 1264 /* configure backlink on ring */ 1265 ring->q_vector = q_vector; 1266 1267 /* update q_vector Tx values */ 1268 igb_add_ring(ring, &q_vector->tx); 1269 1270 /* For 82575, context index must be unique per ring. */ 1271 if (adapter->hw.mac.type == e1000_82575) 1272 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1273 1274 /* apply Tx specific ring traits */ 1275 ring->count = adapter->tx_ring_count; 1276 ring->queue_index = txr_idx; 1277 1278 u64_stats_init(&ring->tx_syncp); 1279 u64_stats_init(&ring->tx_syncp2); 1280 1281 /* assign ring to adapter */ 1282 adapter->tx_ring[txr_idx] = ring; 1283 1284 /* push pointer to next ring */ 1285 ring++; 1286 } 1287 1288 if (rxr_count) { 1289 /* assign generic ring traits */ 1290 ring->dev = &adapter->pdev->dev; 1291 ring->netdev = adapter->netdev; 1292 1293 /* configure backlink on ring */ 1294 ring->q_vector = q_vector; 1295 1296 /* update q_vector Rx values */ 1297 igb_add_ring(ring, &q_vector->rx); 1298 1299 /* set flag indicating ring supports SCTP checksum offload */ 1300 if (adapter->hw.mac.type >= e1000_82576) 1301 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1302 1303 /* On i350, i354, i210, and i211, loopback VLAN packets 1304 * have the tag byte-swapped. 1305 */ 1306 if (adapter->hw.mac.type >= e1000_i350) 1307 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1308 1309 /* apply Rx specific ring traits */ 1310 ring->count = adapter->rx_ring_count; 1311 ring->queue_index = rxr_idx; 1312 1313 u64_stats_init(&ring->rx_syncp); 1314 1315 /* assign ring to adapter */ 1316 adapter->rx_ring[rxr_idx] = ring; 1317 } 1318 1319 return 0; 1320 } 1321 1322 1323 /** 1324 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1325 * @adapter: board private structure to initialize 1326 * 1327 * We allocate one q_vector per queue interrupt. If allocation fails we 1328 * return -ENOMEM. 1329 **/ 1330 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1331 { 1332 int q_vectors = adapter->num_q_vectors; 1333 int rxr_remaining = adapter->num_rx_queues; 1334 int txr_remaining = adapter->num_tx_queues; 1335 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1336 int err; 1337 1338 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1339 for (; rxr_remaining; v_idx++) { 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1341 0, 0, 1, rxr_idx); 1342 1343 if (err) 1344 goto err_out; 1345 1346 /* update counts and index */ 1347 rxr_remaining--; 1348 rxr_idx++; 1349 } 1350 } 1351 1352 for (; v_idx < q_vectors; v_idx++) { 1353 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1354 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1355 1356 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1357 tqpv, txr_idx, rqpv, rxr_idx); 1358 1359 if (err) 1360 goto err_out; 1361 1362 /* update counts and index */ 1363 rxr_remaining -= rqpv; 1364 txr_remaining -= tqpv; 1365 rxr_idx++; 1366 txr_idx++; 1367 } 1368 1369 return 0; 1370 1371 err_out: 1372 adapter->num_tx_queues = 0; 1373 adapter->num_rx_queues = 0; 1374 adapter->num_q_vectors = 0; 1375 1376 while (v_idx--) 1377 igb_free_q_vector(adapter, v_idx); 1378 1379 return -ENOMEM; 1380 } 1381 1382 /** 1383 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1384 * @adapter: board private structure to initialize 1385 * @msix: boolean value of MSIX capability 1386 * 1387 * This function initializes the interrupts and allocates all of the queues. 1388 **/ 1389 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1390 { 1391 struct pci_dev *pdev = adapter->pdev; 1392 int err; 1393 1394 igb_set_interrupt_capability(adapter, msix); 1395 1396 err = igb_alloc_q_vectors(adapter); 1397 if (err) { 1398 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1399 goto err_alloc_q_vectors; 1400 } 1401 1402 igb_cache_ring_register(adapter); 1403 1404 return 0; 1405 1406 err_alloc_q_vectors: 1407 igb_reset_interrupt_capability(adapter); 1408 return err; 1409 } 1410 1411 /** 1412 * igb_request_irq - initialize interrupts 1413 * @adapter: board private structure to initialize 1414 * 1415 * Attempts to configure interrupts using the best available 1416 * capabilities of the hardware and kernel. 1417 **/ 1418 static int igb_request_irq(struct igb_adapter *adapter) 1419 { 1420 struct net_device *netdev = adapter->netdev; 1421 struct pci_dev *pdev = adapter->pdev; 1422 int err = 0; 1423 1424 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1425 err = igb_request_msix(adapter); 1426 if (!err) 1427 goto request_done; 1428 /* fall back to MSI */ 1429 igb_free_all_tx_resources(adapter); 1430 igb_free_all_rx_resources(adapter); 1431 1432 igb_clear_interrupt_scheme(adapter); 1433 err = igb_init_interrupt_scheme(adapter, false); 1434 if (err) 1435 goto request_done; 1436 1437 igb_setup_all_tx_resources(adapter); 1438 igb_setup_all_rx_resources(adapter); 1439 igb_configure(adapter); 1440 } 1441 1442 igb_assign_vector(adapter->q_vector[0], 0); 1443 1444 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1445 err = request_irq(pdev->irq, igb_intr_msi, 0, 1446 netdev->name, adapter); 1447 if (!err) 1448 goto request_done; 1449 1450 /* fall back to legacy interrupts */ 1451 igb_reset_interrupt_capability(adapter); 1452 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1453 } 1454 1455 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1456 netdev->name, adapter); 1457 1458 if (err) 1459 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1460 err); 1461 1462 request_done: 1463 return err; 1464 } 1465 1466 static void igb_free_irq(struct igb_adapter *adapter) 1467 { 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 int vector = 0, i; 1470 1471 free_irq(adapter->msix_entries[vector++].vector, adapter); 1472 1473 for (i = 0; i < adapter->num_q_vectors; i++) 1474 free_irq(adapter->msix_entries[vector++].vector, 1475 adapter->q_vector[i]); 1476 } else { 1477 free_irq(adapter->pdev->irq, adapter); 1478 } 1479 } 1480 1481 /** 1482 * igb_irq_disable - Mask off interrupt generation on the NIC 1483 * @adapter: board private structure 1484 **/ 1485 static void igb_irq_disable(struct igb_adapter *adapter) 1486 { 1487 struct e1000_hw *hw = &adapter->hw; 1488 1489 /* we need to be careful when disabling interrupts. The VFs are also 1490 * mapped into these registers and so clearing the bits can cause 1491 * issues on the VF drivers so we only need to clear what we set 1492 */ 1493 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1494 u32 regval = rd32(E1000_EIAM); 1495 1496 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1497 wr32(E1000_EIMC, adapter->eims_enable_mask); 1498 regval = rd32(E1000_EIAC); 1499 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1500 } 1501 1502 wr32(E1000_IAM, 0); 1503 wr32(E1000_IMC, ~0); 1504 wrfl(); 1505 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1506 int i; 1507 1508 for (i = 0; i < adapter->num_q_vectors; i++) 1509 synchronize_irq(adapter->msix_entries[i].vector); 1510 } else { 1511 synchronize_irq(adapter->pdev->irq); 1512 } 1513 } 1514 1515 /** 1516 * igb_irq_enable - Enable default interrupt generation settings 1517 * @adapter: board private structure 1518 **/ 1519 static void igb_irq_enable(struct igb_adapter *adapter) 1520 { 1521 struct e1000_hw *hw = &adapter->hw; 1522 1523 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1524 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1525 u32 regval = rd32(E1000_EIAC); 1526 1527 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1528 regval = rd32(E1000_EIAM); 1529 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1530 wr32(E1000_EIMS, adapter->eims_enable_mask); 1531 if (adapter->vfs_allocated_count) { 1532 wr32(E1000_MBVFIMR, 0xFF); 1533 ims |= E1000_IMS_VMMB; 1534 } 1535 wr32(E1000_IMS, ims); 1536 } else { 1537 wr32(E1000_IMS, IMS_ENABLE_MASK | 1538 E1000_IMS_DRSTA); 1539 wr32(E1000_IAM, IMS_ENABLE_MASK | 1540 E1000_IMS_DRSTA); 1541 } 1542 } 1543 1544 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1545 { 1546 struct e1000_hw *hw = &adapter->hw; 1547 u16 pf_id = adapter->vfs_allocated_count; 1548 u16 vid = adapter->hw.mng_cookie.vlan_id; 1549 u16 old_vid = adapter->mng_vlan_id; 1550 1551 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1552 /* add VID to filter table */ 1553 igb_vfta_set(hw, vid, pf_id, true, true); 1554 adapter->mng_vlan_id = vid; 1555 } else { 1556 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1557 } 1558 1559 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1560 (vid != old_vid) && 1561 !test_bit(old_vid, adapter->active_vlans)) { 1562 /* remove VID from filter table */ 1563 igb_vfta_set(hw, vid, pf_id, false, true); 1564 } 1565 } 1566 1567 /** 1568 * igb_release_hw_control - release control of the h/w to f/w 1569 * @adapter: address of board private structure 1570 * 1571 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1572 * For ASF and Pass Through versions of f/w this means that the 1573 * driver is no longer loaded. 1574 **/ 1575 static void igb_release_hw_control(struct igb_adapter *adapter) 1576 { 1577 struct e1000_hw *hw = &adapter->hw; 1578 u32 ctrl_ext; 1579 1580 /* Let firmware take over control of h/w */ 1581 ctrl_ext = rd32(E1000_CTRL_EXT); 1582 wr32(E1000_CTRL_EXT, 1583 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1584 } 1585 1586 /** 1587 * igb_get_hw_control - get control of the h/w from f/w 1588 * @adapter: address of board private structure 1589 * 1590 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1591 * For ASF and Pass Through versions of f/w this means that 1592 * the driver is loaded. 1593 **/ 1594 static void igb_get_hw_control(struct igb_adapter *adapter) 1595 { 1596 struct e1000_hw *hw = &adapter->hw; 1597 u32 ctrl_ext; 1598 1599 /* Let firmware know the driver has taken over */ 1600 ctrl_ext = rd32(E1000_CTRL_EXT); 1601 wr32(E1000_CTRL_EXT, 1602 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1603 } 1604 1605 /** 1606 * igb_configure - configure the hardware for RX and TX 1607 * @adapter: private board structure 1608 **/ 1609 static void igb_configure(struct igb_adapter *adapter) 1610 { 1611 struct net_device *netdev = adapter->netdev; 1612 int i; 1613 1614 igb_get_hw_control(adapter); 1615 igb_set_rx_mode(netdev); 1616 1617 igb_restore_vlan(adapter); 1618 1619 igb_setup_tctl(adapter); 1620 igb_setup_mrqc(adapter); 1621 igb_setup_rctl(adapter); 1622 1623 igb_nfc_filter_restore(adapter); 1624 igb_configure_tx(adapter); 1625 igb_configure_rx(adapter); 1626 1627 igb_rx_fifo_flush_82575(&adapter->hw); 1628 1629 /* call igb_desc_unused which always leaves 1630 * at least 1 descriptor unused to make sure 1631 * next_to_use != next_to_clean 1632 */ 1633 for (i = 0; i < adapter->num_rx_queues; i++) { 1634 struct igb_ring *ring = adapter->rx_ring[i]; 1635 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1636 } 1637 } 1638 1639 /** 1640 * igb_power_up_link - Power up the phy/serdes link 1641 * @adapter: address of board private structure 1642 **/ 1643 void igb_power_up_link(struct igb_adapter *adapter) 1644 { 1645 igb_reset_phy(&adapter->hw); 1646 1647 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1648 igb_power_up_phy_copper(&adapter->hw); 1649 else 1650 igb_power_up_serdes_link_82575(&adapter->hw); 1651 1652 igb_setup_link(&adapter->hw); 1653 } 1654 1655 /** 1656 * igb_power_down_link - Power down the phy/serdes link 1657 * @adapter: address of board private structure 1658 */ 1659 static void igb_power_down_link(struct igb_adapter *adapter) 1660 { 1661 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1662 igb_power_down_phy_copper_82575(&adapter->hw); 1663 else 1664 igb_shutdown_serdes_link_82575(&adapter->hw); 1665 } 1666 1667 /** 1668 * Detect and switch function for Media Auto Sense 1669 * @adapter: address of the board private structure 1670 **/ 1671 static void igb_check_swap_media(struct igb_adapter *adapter) 1672 { 1673 struct e1000_hw *hw = &adapter->hw; 1674 u32 ctrl_ext, connsw; 1675 bool swap_now = false; 1676 1677 ctrl_ext = rd32(E1000_CTRL_EXT); 1678 connsw = rd32(E1000_CONNSW); 1679 1680 /* need to live swap if current media is copper and we have fiber/serdes 1681 * to go to. 1682 */ 1683 1684 if ((hw->phy.media_type == e1000_media_type_copper) && 1685 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1686 swap_now = true; 1687 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1688 /* copper signal takes time to appear */ 1689 if (adapter->copper_tries < 4) { 1690 adapter->copper_tries++; 1691 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1692 wr32(E1000_CONNSW, connsw); 1693 return; 1694 } else { 1695 adapter->copper_tries = 0; 1696 if ((connsw & E1000_CONNSW_PHYSD) && 1697 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1698 swap_now = true; 1699 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1700 wr32(E1000_CONNSW, connsw); 1701 } 1702 } 1703 } 1704 1705 if (!swap_now) 1706 return; 1707 1708 switch (hw->phy.media_type) { 1709 case e1000_media_type_copper: 1710 netdev_info(adapter->netdev, 1711 "MAS: changing media to fiber/serdes\n"); 1712 ctrl_ext |= 1713 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1714 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1715 adapter->copper_tries = 0; 1716 break; 1717 case e1000_media_type_internal_serdes: 1718 case e1000_media_type_fiber: 1719 netdev_info(adapter->netdev, 1720 "MAS: changing media to copper\n"); 1721 ctrl_ext &= 1722 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1723 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1724 break; 1725 default: 1726 /* shouldn't get here during regular operation */ 1727 netdev_err(adapter->netdev, 1728 "AMS: Invalid media type found, returning\n"); 1729 break; 1730 } 1731 wr32(E1000_CTRL_EXT, ctrl_ext); 1732 } 1733 1734 /** 1735 * igb_up - Open the interface and prepare it to handle traffic 1736 * @adapter: board private structure 1737 **/ 1738 int igb_up(struct igb_adapter *adapter) 1739 { 1740 struct e1000_hw *hw = &adapter->hw; 1741 int i; 1742 1743 /* hardware has been reset, we need to reload some things */ 1744 igb_configure(adapter); 1745 1746 clear_bit(__IGB_DOWN, &adapter->state); 1747 1748 for (i = 0; i < adapter->num_q_vectors; i++) 1749 napi_enable(&(adapter->q_vector[i]->napi)); 1750 1751 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1752 igb_configure_msix(adapter); 1753 else 1754 igb_assign_vector(adapter->q_vector[0], 0); 1755 1756 /* Clear any pending interrupts. */ 1757 rd32(E1000_ICR); 1758 igb_irq_enable(adapter); 1759 1760 /* notify VFs that reset has been completed */ 1761 if (adapter->vfs_allocated_count) { 1762 u32 reg_data = rd32(E1000_CTRL_EXT); 1763 1764 reg_data |= E1000_CTRL_EXT_PFRSTD; 1765 wr32(E1000_CTRL_EXT, reg_data); 1766 } 1767 1768 netif_tx_start_all_queues(adapter->netdev); 1769 1770 /* start the watchdog. */ 1771 hw->mac.get_link_status = 1; 1772 schedule_work(&adapter->watchdog_task); 1773 1774 if ((adapter->flags & IGB_FLAG_EEE) && 1775 (!hw->dev_spec._82575.eee_disable)) 1776 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1777 1778 return 0; 1779 } 1780 1781 void igb_down(struct igb_adapter *adapter) 1782 { 1783 struct net_device *netdev = adapter->netdev; 1784 struct e1000_hw *hw = &adapter->hw; 1785 u32 tctl, rctl; 1786 int i; 1787 1788 /* signal that we're down so the interrupt handler does not 1789 * reschedule our watchdog timer 1790 */ 1791 set_bit(__IGB_DOWN, &adapter->state); 1792 1793 /* disable receives in the hardware */ 1794 rctl = rd32(E1000_RCTL); 1795 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1796 /* flush and sleep below */ 1797 1798 netif_carrier_off(netdev); 1799 netif_tx_stop_all_queues(netdev); 1800 1801 /* disable transmits in the hardware */ 1802 tctl = rd32(E1000_TCTL); 1803 tctl &= ~E1000_TCTL_EN; 1804 wr32(E1000_TCTL, tctl); 1805 /* flush both disables and wait for them to finish */ 1806 wrfl(); 1807 usleep_range(10000, 11000); 1808 1809 igb_irq_disable(adapter); 1810 1811 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1812 1813 for (i = 0; i < adapter->num_q_vectors; i++) { 1814 if (adapter->q_vector[i]) { 1815 napi_synchronize(&adapter->q_vector[i]->napi); 1816 napi_disable(&adapter->q_vector[i]->napi); 1817 } 1818 } 1819 1820 del_timer_sync(&adapter->watchdog_timer); 1821 del_timer_sync(&adapter->phy_info_timer); 1822 1823 /* record the stats before reset*/ 1824 spin_lock(&adapter->stats64_lock); 1825 igb_update_stats(adapter, &adapter->stats64); 1826 spin_unlock(&adapter->stats64_lock); 1827 1828 adapter->link_speed = 0; 1829 adapter->link_duplex = 0; 1830 1831 if (!pci_channel_offline(adapter->pdev)) 1832 igb_reset(adapter); 1833 1834 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1835 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 1836 1837 igb_clean_all_tx_rings(adapter); 1838 igb_clean_all_rx_rings(adapter); 1839 #ifdef CONFIG_IGB_DCA 1840 1841 /* since we reset the hardware DCA settings were cleared */ 1842 igb_setup_dca(adapter); 1843 #endif 1844 } 1845 1846 void igb_reinit_locked(struct igb_adapter *adapter) 1847 { 1848 WARN_ON(in_interrupt()); 1849 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1850 usleep_range(1000, 2000); 1851 igb_down(adapter); 1852 igb_up(adapter); 1853 clear_bit(__IGB_RESETTING, &adapter->state); 1854 } 1855 1856 /** igb_enable_mas - Media Autosense re-enable after swap 1857 * 1858 * @adapter: adapter struct 1859 **/ 1860 static void igb_enable_mas(struct igb_adapter *adapter) 1861 { 1862 struct e1000_hw *hw = &adapter->hw; 1863 u32 connsw = rd32(E1000_CONNSW); 1864 1865 /* configure for SerDes media detect */ 1866 if ((hw->phy.media_type == e1000_media_type_copper) && 1867 (!(connsw & E1000_CONNSW_SERDESD))) { 1868 connsw |= E1000_CONNSW_ENRGSRC; 1869 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1870 wr32(E1000_CONNSW, connsw); 1871 wrfl(); 1872 } 1873 } 1874 1875 void igb_reset(struct igb_adapter *adapter) 1876 { 1877 struct pci_dev *pdev = adapter->pdev; 1878 struct e1000_hw *hw = &adapter->hw; 1879 struct e1000_mac_info *mac = &hw->mac; 1880 struct e1000_fc_info *fc = &hw->fc; 1881 u32 pba, hwm; 1882 1883 /* Repartition Pba for greater than 9k mtu 1884 * To take effect CTRL.RST is required. 1885 */ 1886 switch (mac->type) { 1887 case e1000_i350: 1888 case e1000_i354: 1889 case e1000_82580: 1890 pba = rd32(E1000_RXPBS); 1891 pba = igb_rxpbs_adjust_82580(pba); 1892 break; 1893 case e1000_82576: 1894 pba = rd32(E1000_RXPBS); 1895 pba &= E1000_RXPBS_SIZE_MASK_82576; 1896 break; 1897 case e1000_82575: 1898 case e1000_i210: 1899 case e1000_i211: 1900 default: 1901 pba = E1000_PBA_34K; 1902 break; 1903 } 1904 1905 if (mac->type == e1000_82575) { 1906 u32 min_rx_space, min_tx_space, needed_tx_space; 1907 1908 /* write Rx PBA so that hardware can report correct Tx PBA */ 1909 wr32(E1000_PBA, pba); 1910 1911 /* To maintain wire speed transmits, the Tx FIFO should be 1912 * large enough to accommodate two full transmit packets, 1913 * rounded up to the next 1KB and expressed in KB. Likewise, 1914 * the Rx FIFO should be large enough to accommodate at least 1915 * one full receive packet and is similarly rounded up and 1916 * expressed in KB. 1917 */ 1918 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 1919 1920 /* The Tx FIFO also stores 16 bytes of information about the Tx 1921 * but don't include Ethernet FCS because hardware appends it. 1922 * We only need to round down to the nearest 512 byte block 1923 * count since the value we care about is 2 frames, not 1. 1924 */ 1925 min_tx_space = adapter->max_frame_size; 1926 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 1927 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 1928 1929 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1930 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 1931 1932 /* If current Tx allocation is less than the min Tx FIFO size, 1933 * and the min Tx FIFO size is less than the current Rx FIFO 1934 * allocation, take space away from current Rx allocation. 1935 */ 1936 if (needed_tx_space < pba) { 1937 pba -= needed_tx_space; 1938 1939 /* if short on Rx space, Rx wins and must trump Tx 1940 * adjustment 1941 */ 1942 if (pba < min_rx_space) 1943 pba = min_rx_space; 1944 } 1945 1946 /* adjust PBA for jumbo frames */ 1947 wr32(E1000_PBA, pba); 1948 } 1949 1950 /* flow control settings 1951 * The high water mark must be low enough to fit one full frame 1952 * after transmitting the pause frame. As such we must have enough 1953 * space to allow for us to complete our current transmit and then 1954 * receive the frame that is in progress from the link partner. 1955 * Set it to: 1956 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 1957 */ 1958 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 1959 1960 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1961 fc->low_water = fc->high_water - 16; 1962 fc->pause_time = 0xFFFF; 1963 fc->send_xon = 1; 1964 fc->current_mode = fc->requested_mode; 1965 1966 /* disable receive for all VFs and wait one second */ 1967 if (adapter->vfs_allocated_count) { 1968 int i; 1969 1970 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1971 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1972 1973 /* ping all the active vfs to let them know we are going down */ 1974 igb_ping_all_vfs(adapter); 1975 1976 /* disable transmits and receives */ 1977 wr32(E1000_VFRE, 0); 1978 wr32(E1000_VFTE, 0); 1979 } 1980 1981 /* Allow time for pending master requests to run */ 1982 hw->mac.ops.reset_hw(hw); 1983 wr32(E1000_WUC, 0); 1984 1985 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1986 /* need to resetup here after media swap */ 1987 adapter->ei.get_invariants(hw); 1988 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1989 } 1990 if ((mac->type == e1000_82575) && 1991 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 1992 igb_enable_mas(adapter); 1993 } 1994 if (hw->mac.ops.init_hw(hw)) 1995 dev_err(&pdev->dev, "Hardware Error\n"); 1996 1997 /* RAR registers were cleared during init_hw, clear mac table */ 1998 igb_flush_mac_table(adapter); 1999 __dev_uc_unsync(adapter->netdev, NULL); 2000 2001 /* Recover default RAR entry */ 2002 igb_set_default_mac_filter(adapter); 2003 2004 /* Flow control settings reset on hardware reset, so guarantee flow 2005 * control is off when forcing speed. 2006 */ 2007 if (!hw->mac.autoneg) 2008 igb_force_mac_fc(hw); 2009 2010 igb_init_dmac(adapter, pba); 2011 #ifdef CONFIG_IGB_HWMON 2012 /* Re-initialize the thermal sensor on i350 devices. */ 2013 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2014 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2015 /* If present, re-initialize the external thermal sensor 2016 * interface. 2017 */ 2018 if (adapter->ets) 2019 mac->ops.init_thermal_sensor_thresh(hw); 2020 } 2021 } 2022 #endif 2023 /* Re-establish EEE setting */ 2024 if (hw->phy.media_type == e1000_media_type_copper) { 2025 switch (mac->type) { 2026 case e1000_i350: 2027 case e1000_i210: 2028 case e1000_i211: 2029 igb_set_eee_i350(hw, true, true); 2030 break; 2031 case e1000_i354: 2032 igb_set_eee_i354(hw, true, true); 2033 break; 2034 default: 2035 break; 2036 } 2037 } 2038 if (!netif_running(adapter->netdev)) 2039 igb_power_down_link(adapter); 2040 2041 igb_update_mng_vlan(adapter); 2042 2043 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2044 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2045 2046 /* Re-enable PTP, where applicable. */ 2047 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2048 igb_ptp_reset(adapter); 2049 2050 igb_get_phy_info(hw); 2051 } 2052 2053 static netdev_features_t igb_fix_features(struct net_device *netdev, 2054 netdev_features_t features) 2055 { 2056 /* Since there is no support for separate Rx/Tx vlan accel 2057 * enable/disable make sure Tx flag is always in same state as Rx. 2058 */ 2059 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2060 features |= NETIF_F_HW_VLAN_CTAG_TX; 2061 else 2062 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2063 2064 return features; 2065 } 2066 2067 static int igb_set_features(struct net_device *netdev, 2068 netdev_features_t features) 2069 { 2070 netdev_features_t changed = netdev->features ^ features; 2071 struct igb_adapter *adapter = netdev_priv(netdev); 2072 2073 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2074 igb_vlan_mode(netdev, features); 2075 2076 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2077 return 0; 2078 2079 if (!(features & NETIF_F_NTUPLE)) { 2080 struct hlist_node *node2; 2081 struct igb_nfc_filter *rule; 2082 2083 spin_lock(&adapter->nfc_lock); 2084 hlist_for_each_entry_safe(rule, node2, 2085 &adapter->nfc_filter_list, nfc_node) { 2086 igb_erase_filter(adapter, rule); 2087 hlist_del(&rule->nfc_node); 2088 kfree(rule); 2089 } 2090 spin_unlock(&adapter->nfc_lock); 2091 adapter->nfc_filter_count = 0; 2092 } 2093 2094 netdev->features = features; 2095 2096 if (netif_running(netdev)) 2097 igb_reinit_locked(adapter); 2098 else 2099 igb_reset(adapter); 2100 2101 return 0; 2102 } 2103 2104 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2105 struct net_device *dev, 2106 const unsigned char *addr, u16 vid, 2107 u16 flags) 2108 { 2109 /* guarantee we can provide a unique filter for the unicast address */ 2110 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2111 struct igb_adapter *adapter = netdev_priv(dev); 2112 int vfn = adapter->vfs_allocated_count; 2113 2114 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2115 return -ENOMEM; 2116 } 2117 2118 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2119 } 2120 2121 #define IGB_MAX_MAC_HDR_LEN 127 2122 #define IGB_MAX_NETWORK_HDR_LEN 511 2123 2124 static netdev_features_t 2125 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2126 netdev_features_t features) 2127 { 2128 unsigned int network_hdr_len, mac_hdr_len; 2129 2130 /* Make certain the headers can be described by a context descriptor */ 2131 mac_hdr_len = skb_network_header(skb) - skb->data; 2132 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2133 return features & ~(NETIF_F_HW_CSUM | 2134 NETIF_F_SCTP_CRC | 2135 NETIF_F_HW_VLAN_CTAG_TX | 2136 NETIF_F_TSO | 2137 NETIF_F_TSO6); 2138 2139 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2140 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2141 return features & ~(NETIF_F_HW_CSUM | 2142 NETIF_F_SCTP_CRC | 2143 NETIF_F_TSO | 2144 NETIF_F_TSO6); 2145 2146 /* We can only support IPV4 TSO in tunnels if we can mangle the 2147 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2148 */ 2149 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2150 features &= ~NETIF_F_TSO; 2151 2152 return features; 2153 } 2154 2155 static const struct net_device_ops igb_netdev_ops = { 2156 .ndo_open = igb_open, 2157 .ndo_stop = igb_close, 2158 .ndo_start_xmit = igb_xmit_frame, 2159 .ndo_get_stats64 = igb_get_stats64, 2160 .ndo_set_rx_mode = igb_set_rx_mode, 2161 .ndo_set_mac_address = igb_set_mac, 2162 .ndo_change_mtu = igb_change_mtu, 2163 .ndo_do_ioctl = igb_ioctl, 2164 .ndo_tx_timeout = igb_tx_timeout, 2165 .ndo_validate_addr = eth_validate_addr, 2166 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2167 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2168 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2169 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2170 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2171 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2172 .ndo_get_vf_config = igb_ndo_get_vf_config, 2173 #ifdef CONFIG_NET_POLL_CONTROLLER 2174 .ndo_poll_controller = igb_netpoll, 2175 #endif 2176 .ndo_fix_features = igb_fix_features, 2177 .ndo_set_features = igb_set_features, 2178 .ndo_fdb_add = igb_ndo_fdb_add, 2179 .ndo_features_check = igb_features_check, 2180 }; 2181 2182 /** 2183 * igb_set_fw_version - Configure version string for ethtool 2184 * @adapter: adapter struct 2185 **/ 2186 void igb_set_fw_version(struct igb_adapter *adapter) 2187 { 2188 struct e1000_hw *hw = &adapter->hw; 2189 struct e1000_fw_version fw; 2190 2191 igb_get_fw_version(hw, &fw); 2192 2193 switch (hw->mac.type) { 2194 case e1000_i210: 2195 case e1000_i211: 2196 if (!(igb_get_flash_presence_i210(hw))) { 2197 snprintf(adapter->fw_version, 2198 sizeof(adapter->fw_version), 2199 "%2d.%2d-%d", 2200 fw.invm_major, fw.invm_minor, 2201 fw.invm_img_type); 2202 break; 2203 } 2204 /* fall through */ 2205 default: 2206 /* if option is rom valid, display its version too */ 2207 if (fw.or_valid) { 2208 snprintf(adapter->fw_version, 2209 sizeof(adapter->fw_version), 2210 "%d.%d, 0x%08x, %d.%d.%d", 2211 fw.eep_major, fw.eep_minor, fw.etrack_id, 2212 fw.or_major, fw.or_build, fw.or_patch); 2213 /* no option rom */ 2214 } else if (fw.etrack_id != 0X0000) { 2215 snprintf(adapter->fw_version, 2216 sizeof(adapter->fw_version), 2217 "%d.%d, 0x%08x", 2218 fw.eep_major, fw.eep_minor, fw.etrack_id); 2219 } else { 2220 snprintf(adapter->fw_version, 2221 sizeof(adapter->fw_version), 2222 "%d.%d.%d", 2223 fw.eep_major, fw.eep_minor, fw.eep_build); 2224 } 2225 break; 2226 } 2227 } 2228 2229 /** 2230 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2231 * 2232 * @adapter: adapter struct 2233 **/ 2234 static void igb_init_mas(struct igb_adapter *adapter) 2235 { 2236 struct e1000_hw *hw = &adapter->hw; 2237 u16 eeprom_data; 2238 2239 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2240 switch (hw->bus.func) { 2241 case E1000_FUNC_0: 2242 if (eeprom_data & IGB_MAS_ENABLE_0) { 2243 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2244 netdev_info(adapter->netdev, 2245 "MAS: Enabling Media Autosense for port %d\n", 2246 hw->bus.func); 2247 } 2248 break; 2249 case E1000_FUNC_1: 2250 if (eeprom_data & IGB_MAS_ENABLE_1) { 2251 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2252 netdev_info(adapter->netdev, 2253 "MAS: Enabling Media Autosense for port %d\n", 2254 hw->bus.func); 2255 } 2256 break; 2257 case E1000_FUNC_2: 2258 if (eeprom_data & IGB_MAS_ENABLE_2) { 2259 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2260 netdev_info(adapter->netdev, 2261 "MAS: Enabling Media Autosense for port %d\n", 2262 hw->bus.func); 2263 } 2264 break; 2265 case E1000_FUNC_3: 2266 if (eeprom_data & IGB_MAS_ENABLE_3) { 2267 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2268 netdev_info(adapter->netdev, 2269 "MAS: Enabling Media Autosense for port %d\n", 2270 hw->bus.func); 2271 } 2272 break; 2273 default: 2274 /* Shouldn't get here */ 2275 netdev_err(adapter->netdev, 2276 "MAS: Invalid port configuration, returning\n"); 2277 break; 2278 } 2279 } 2280 2281 /** 2282 * igb_init_i2c - Init I2C interface 2283 * @adapter: pointer to adapter structure 2284 **/ 2285 static s32 igb_init_i2c(struct igb_adapter *adapter) 2286 { 2287 s32 status = 0; 2288 2289 /* I2C interface supported on i350 devices */ 2290 if (adapter->hw.mac.type != e1000_i350) 2291 return 0; 2292 2293 /* Initialize the i2c bus which is controlled by the registers. 2294 * This bus will use the i2c_algo_bit structue that implements 2295 * the protocol through toggling of the 4 bits in the register. 2296 */ 2297 adapter->i2c_adap.owner = THIS_MODULE; 2298 adapter->i2c_algo = igb_i2c_algo; 2299 adapter->i2c_algo.data = adapter; 2300 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2301 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2302 strlcpy(adapter->i2c_adap.name, "igb BB", 2303 sizeof(adapter->i2c_adap.name)); 2304 status = i2c_bit_add_bus(&adapter->i2c_adap); 2305 return status; 2306 } 2307 2308 /** 2309 * igb_probe - Device Initialization Routine 2310 * @pdev: PCI device information struct 2311 * @ent: entry in igb_pci_tbl 2312 * 2313 * Returns 0 on success, negative on failure 2314 * 2315 * igb_probe initializes an adapter identified by a pci_dev structure. 2316 * The OS initialization, configuring of the adapter private structure, 2317 * and a hardware reset occur. 2318 **/ 2319 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2320 { 2321 struct net_device *netdev; 2322 struct igb_adapter *adapter; 2323 struct e1000_hw *hw; 2324 u16 eeprom_data = 0; 2325 s32 ret_val; 2326 static int global_quad_port_a; /* global quad port a indication */ 2327 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2328 int err, pci_using_dac; 2329 u8 part_str[E1000_PBANUM_LENGTH]; 2330 2331 /* Catch broken hardware that put the wrong VF device ID in 2332 * the PCIe SR-IOV capability. 2333 */ 2334 if (pdev->is_virtfn) { 2335 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2336 pci_name(pdev), pdev->vendor, pdev->device); 2337 return -EINVAL; 2338 } 2339 2340 err = pci_enable_device_mem(pdev); 2341 if (err) 2342 return err; 2343 2344 pci_using_dac = 0; 2345 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2346 if (!err) { 2347 pci_using_dac = 1; 2348 } else { 2349 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2350 if (err) { 2351 dev_err(&pdev->dev, 2352 "No usable DMA configuration, aborting\n"); 2353 goto err_dma; 2354 } 2355 } 2356 2357 err = pci_request_mem_regions(pdev, igb_driver_name); 2358 if (err) 2359 goto err_pci_reg; 2360 2361 pci_enable_pcie_error_reporting(pdev); 2362 2363 pci_set_master(pdev); 2364 pci_save_state(pdev); 2365 2366 err = -ENOMEM; 2367 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2368 IGB_MAX_TX_QUEUES); 2369 if (!netdev) 2370 goto err_alloc_etherdev; 2371 2372 SET_NETDEV_DEV(netdev, &pdev->dev); 2373 2374 pci_set_drvdata(pdev, netdev); 2375 adapter = netdev_priv(netdev); 2376 adapter->netdev = netdev; 2377 adapter->pdev = pdev; 2378 hw = &adapter->hw; 2379 hw->back = adapter; 2380 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2381 2382 err = -EIO; 2383 adapter->io_addr = pci_iomap(pdev, 0, 0); 2384 if (!adapter->io_addr) 2385 goto err_ioremap; 2386 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 2387 hw->hw_addr = adapter->io_addr; 2388 2389 netdev->netdev_ops = &igb_netdev_ops; 2390 igb_set_ethtool_ops(netdev); 2391 netdev->watchdog_timeo = 5 * HZ; 2392 2393 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2394 2395 netdev->mem_start = pci_resource_start(pdev, 0); 2396 netdev->mem_end = pci_resource_end(pdev, 0); 2397 2398 /* PCI config space info */ 2399 hw->vendor_id = pdev->vendor; 2400 hw->device_id = pdev->device; 2401 hw->revision_id = pdev->revision; 2402 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2403 hw->subsystem_device_id = pdev->subsystem_device; 2404 2405 /* Copy the default MAC, PHY and NVM function pointers */ 2406 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2407 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2408 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2409 /* Initialize skew-specific constants */ 2410 err = ei->get_invariants(hw); 2411 if (err) 2412 goto err_sw_init; 2413 2414 /* setup the private structure */ 2415 err = igb_sw_init(adapter); 2416 if (err) 2417 goto err_sw_init; 2418 2419 igb_get_bus_info_pcie(hw); 2420 2421 hw->phy.autoneg_wait_to_complete = false; 2422 2423 /* Copper options */ 2424 if (hw->phy.media_type == e1000_media_type_copper) { 2425 hw->phy.mdix = AUTO_ALL_MODES; 2426 hw->phy.disable_polarity_correction = false; 2427 hw->phy.ms_type = e1000_ms_hw_default; 2428 } 2429 2430 if (igb_check_reset_block(hw)) 2431 dev_info(&pdev->dev, 2432 "PHY reset is blocked due to SOL/IDER session.\n"); 2433 2434 /* features is initialized to 0 in allocation, it might have bits 2435 * set by igb_sw_init so we should use an or instead of an 2436 * assignment. 2437 */ 2438 netdev->features |= NETIF_F_SG | 2439 NETIF_F_TSO | 2440 NETIF_F_TSO6 | 2441 NETIF_F_RXHASH | 2442 NETIF_F_RXCSUM | 2443 NETIF_F_HW_CSUM; 2444 2445 if (hw->mac.type >= e1000_82576) 2446 netdev->features |= NETIF_F_SCTP_CRC; 2447 2448 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 2449 NETIF_F_GSO_GRE_CSUM | \ 2450 NETIF_F_GSO_IPXIP4 | \ 2451 NETIF_F_GSO_IPXIP6 | \ 2452 NETIF_F_GSO_UDP_TUNNEL | \ 2453 NETIF_F_GSO_UDP_TUNNEL_CSUM) 2454 2455 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 2456 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 2457 2458 /* copy netdev features into list of user selectable features */ 2459 netdev->hw_features |= netdev->features | 2460 NETIF_F_HW_VLAN_CTAG_RX | 2461 NETIF_F_HW_VLAN_CTAG_TX | 2462 NETIF_F_RXALL; 2463 2464 if (hw->mac.type >= e1000_i350) 2465 netdev->hw_features |= NETIF_F_NTUPLE; 2466 2467 if (pci_using_dac) 2468 netdev->features |= NETIF_F_HIGHDMA; 2469 2470 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 2471 netdev->mpls_features |= NETIF_F_HW_CSUM; 2472 netdev->hw_enc_features |= netdev->vlan_features; 2473 2474 /* set this bit last since it cannot be part of vlan_features */ 2475 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2476 NETIF_F_HW_VLAN_CTAG_RX | 2477 NETIF_F_HW_VLAN_CTAG_TX; 2478 2479 netdev->priv_flags |= IFF_SUPP_NOFCS; 2480 2481 netdev->priv_flags |= IFF_UNICAST_FLT; 2482 2483 /* MTU range: 68 - 9216 */ 2484 netdev->min_mtu = ETH_MIN_MTU; 2485 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 2486 2487 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2488 2489 /* before reading the NVM, reset the controller to put the device in a 2490 * known good starting state 2491 */ 2492 hw->mac.ops.reset_hw(hw); 2493 2494 /* make sure the NVM is good , i211/i210 parts can have special NVM 2495 * that doesn't contain a checksum 2496 */ 2497 switch (hw->mac.type) { 2498 case e1000_i210: 2499 case e1000_i211: 2500 if (igb_get_flash_presence_i210(hw)) { 2501 if (hw->nvm.ops.validate(hw) < 0) { 2502 dev_err(&pdev->dev, 2503 "The NVM Checksum Is Not Valid\n"); 2504 err = -EIO; 2505 goto err_eeprom; 2506 } 2507 } 2508 break; 2509 default: 2510 if (hw->nvm.ops.validate(hw) < 0) { 2511 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2512 err = -EIO; 2513 goto err_eeprom; 2514 } 2515 break; 2516 } 2517 2518 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 2519 /* copy the MAC address out of the NVM */ 2520 if (hw->mac.ops.read_mac_addr(hw)) 2521 dev_err(&pdev->dev, "NVM Read Error\n"); 2522 } 2523 2524 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2525 2526 if (!is_valid_ether_addr(netdev->dev_addr)) { 2527 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2528 err = -EIO; 2529 goto err_eeprom; 2530 } 2531 2532 igb_set_default_mac_filter(adapter); 2533 2534 /* get firmware version for ethtool -i */ 2535 igb_set_fw_version(adapter); 2536 2537 /* configure RXPBSIZE and TXPBSIZE */ 2538 if (hw->mac.type == e1000_i210) { 2539 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 2540 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 2541 } 2542 2543 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2544 (unsigned long) adapter); 2545 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2546 (unsigned long) adapter); 2547 2548 INIT_WORK(&adapter->reset_task, igb_reset_task); 2549 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2550 2551 /* Initialize link properties that are user-changeable */ 2552 adapter->fc_autoneg = true; 2553 hw->mac.autoneg = true; 2554 hw->phy.autoneg_advertised = 0x2f; 2555 2556 hw->fc.requested_mode = e1000_fc_default; 2557 hw->fc.current_mode = e1000_fc_default; 2558 2559 igb_validate_mdi_setting(hw); 2560 2561 /* By default, support wake on port A */ 2562 if (hw->bus.func == 0) 2563 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2564 2565 /* Check the NVM for wake support on non-port A ports */ 2566 if (hw->mac.type >= e1000_82580) 2567 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2568 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2569 &eeprom_data); 2570 else if (hw->bus.func == 1) 2571 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2572 2573 if (eeprom_data & IGB_EEPROM_APME) 2574 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2575 2576 /* now that we have the eeprom settings, apply the special cases where 2577 * the eeprom may be wrong or the board simply won't support wake on 2578 * lan on a particular port 2579 */ 2580 switch (pdev->device) { 2581 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2582 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2583 break; 2584 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2585 case E1000_DEV_ID_82576_FIBER: 2586 case E1000_DEV_ID_82576_SERDES: 2587 /* Wake events only supported on port A for dual fiber 2588 * regardless of eeprom setting 2589 */ 2590 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2591 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2592 break; 2593 case E1000_DEV_ID_82576_QUAD_COPPER: 2594 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2595 /* if quad port adapter, disable WoL on all but port A */ 2596 if (global_quad_port_a != 0) 2597 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2598 else 2599 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2600 /* Reset for multiple quad port adapters */ 2601 if (++global_quad_port_a == 4) 2602 global_quad_port_a = 0; 2603 break; 2604 default: 2605 /* If the device can't wake, don't set software support */ 2606 if (!device_can_wakeup(&adapter->pdev->dev)) 2607 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2608 } 2609 2610 /* initialize the wol settings based on the eeprom settings */ 2611 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2612 adapter->wol |= E1000_WUFC_MAG; 2613 2614 /* Some vendors want WoL disabled by default, but still supported */ 2615 if ((hw->mac.type == e1000_i350) && 2616 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2617 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2618 adapter->wol = 0; 2619 } 2620 2621 /* Some vendors want the ability to Use the EEPROM setting as 2622 * enable/disable only, and not for capability 2623 */ 2624 if (((hw->mac.type == e1000_i350) || 2625 (hw->mac.type == e1000_i354)) && 2626 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 2627 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2628 adapter->wol = 0; 2629 } 2630 if (hw->mac.type == e1000_i350) { 2631 if (((pdev->subsystem_device == 0x5001) || 2632 (pdev->subsystem_device == 0x5002)) && 2633 (hw->bus.func == 0)) { 2634 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2635 adapter->wol = 0; 2636 } 2637 if (pdev->subsystem_device == 0x1F52) 2638 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2639 } 2640 2641 device_set_wakeup_enable(&adapter->pdev->dev, 2642 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2643 2644 /* reset the hardware with the new settings */ 2645 igb_reset(adapter); 2646 2647 /* Init the I2C interface */ 2648 err = igb_init_i2c(adapter); 2649 if (err) { 2650 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2651 goto err_eeprom; 2652 } 2653 2654 /* let the f/w know that the h/w is now under the control of the 2655 * driver. 2656 */ 2657 igb_get_hw_control(adapter); 2658 2659 strcpy(netdev->name, "eth%d"); 2660 err = register_netdev(netdev); 2661 if (err) 2662 goto err_register; 2663 2664 /* carrier off reporting is important to ethtool even BEFORE open */ 2665 netif_carrier_off(netdev); 2666 2667 #ifdef CONFIG_IGB_DCA 2668 if (dca_add_requester(&pdev->dev) == 0) { 2669 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2670 dev_info(&pdev->dev, "DCA enabled\n"); 2671 igb_setup_dca(adapter); 2672 } 2673 2674 #endif 2675 #ifdef CONFIG_IGB_HWMON 2676 /* Initialize the thermal sensor on i350 devices. */ 2677 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2678 u16 ets_word; 2679 2680 /* Read the NVM to determine if this i350 device supports an 2681 * external thermal sensor. 2682 */ 2683 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2684 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2685 adapter->ets = true; 2686 else 2687 adapter->ets = false; 2688 if (igb_sysfs_init(adapter)) 2689 dev_err(&pdev->dev, 2690 "failed to allocate sysfs resources\n"); 2691 } else { 2692 adapter->ets = false; 2693 } 2694 #endif 2695 /* Check if Media Autosense is enabled */ 2696 adapter->ei = *ei; 2697 if (hw->dev_spec._82575.mas_capable) 2698 igb_init_mas(adapter); 2699 2700 /* do hw tstamp init after resetting */ 2701 igb_ptp_init(adapter); 2702 2703 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2704 /* print bus type/speed/width info, not applicable to i354 */ 2705 if (hw->mac.type != e1000_i354) { 2706 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2707 netdev->name, 2708 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2709 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2710 "unknown"), 2711 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2712 "Width x4" : 2713 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2714 "Width x2" : 2715 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2716 "Width x1" : "unknown"), netdev->dev_addr); 2717 } 2718 2719 if ((hw->mac.type >= e1000_i210 || 2720 igb_get_flash_presence_i210(hw))) { 2721 ret_val = igb_read_part_string(hw, part_str, 2722 E1000_PBANUM_LENGTH); 2723 } else { 2724 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2725 } 2726 2727 if (ret_val) 2728 strcpy(part_str, "Unknown"); 2729 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2730 dev_info(&pdev->dev, 2731 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2732 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2733 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2734 adapter->num_rx_queues, adapter->num_tx_queues); 2735 if (hw->phy.media_type == e1000_media_type_copper) { 2736 switch (hw->mac.type) { 2737 case e1000_i350: 2738 case e1000_i210: 2739 case e1000_i211: 2740 /* Enable EEE for internal copper PHY devices */ 2741 err = igb_set_eee_i350(hw, true, true); 2742 if ((!err) && 2743 (!hw->dev_spec._82575.eee_disable)) { 2744 adapter->eee_advert = 2745 MDIO_EEE_100TX | MDIO_EEE_1000T; 2746 adapter->flags |= IGB_FLAG_EEE; 2747 } 2748 break; 2749 case e1000_i354: 2750 if ((rd32(E1000_CTRL_EXT) & 2751 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2752 err = igb_set_eee_i354(hw, true, true); 2753 if ((!err) && 2754 (!hw->dev_spec._82575.eee_disable)) { 2755 adapter->eee_advert = 2756 MDIO_EEE_100TX | MDIO_EEE_1000T; 2757 adapter->flags |= IGB_FLAG_EEE; 2758 } 2759 } 2760 break; 2761 default: 2762 break; 2763 } 2764 } 2765 pm_runtime_put_noidle(&pdev->dev); 2766 return 0; 2767 2768 err_register: 2769 igb_release_hw_control(adapter); 2770 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2771 err_eeprom: 2772 if (!igb_check_reset_block(hw)) 2773 igb_reset_phy(hw); 2774 2775 if (hw->flash_address) 2776 iounmap(hw->flash_address); 2777 err_sw_init: 2778 kfree(adapter->mac_table); 2779 kfree(adapter->shadow_vfta); 2780 igb_clear_interrupt_scheme(adapter); 2781 #ifdef CONFIG_PCI_IOV 2782 igb_disable_sriov(pdev); 2783 #endif 2784 pci_iounmap(pdev, adapter->io_addr); 2785 err_ioremap: 2786 free_netdev(netdev); 2787 err_alloc_etherdev: 2788 pci_release_mem_regions(pdev); 2789 err_pci_reg: 2790 err_dma: 2791 pci_disable_device(pdev); 2792 return err; 2793 } 2794 2795 #ifdef CONFIG_PCI_IOV 2796 static int igb_disable_sriov(struct pci_dev *pdev) 2797 { 2798 struct net_device *netdev = pci_get_drvdata(pdev); 2799 struct igb_adapter *adapter = netdev_priv(netdev); 2800 struct e1000_hw *hw = &adapter->hw; 2801 2802 /* reclaim resources allocated to VFs */ 2803 if (adapter->vf_data) { 2804 /* disable iov and allow time for transactions to clear */ 2805 if (pci_vfs_assigned(pdev)) { 2806 dev_warn(&pdev->dev, 2807 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2808 return -EPERM; 2809 } else { 2810 pci_disable_sriov(pdev); 2811 msleep(500); 2812 } 2813 2814 kfree(adapter->vf_mac_list); 2815 adapter->vf_mac_list = NULL; 2816 kfree(adapter->vf_data); 2817 adapter->vf_data = NULL; 2818 adapter->vfs_allocated_count = 0; 2819 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2820 wrfl(); 2821 msleep(100); 2822 dev_info(&pdev->dev, "IOV Disabled\n"); 2823 2824 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2825 adapter->flags |= IGB_FLAG_DMAC; 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2832 { 2833 struct net_device *netdev = pci_get_drvdata(pdev); 2834 struct igb_adapter *adapter = netdev_priv(netdev); 2835 int old_vfs = pci_num_vf(pdev); 2836 struct vf_mac_filter *mac_list; 2837 int err = 0; 2838 int num_vf_mac_filters, i; 2839 2840 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2841 err = -EPERM; 2842 goto out; 2843 } 2844 if (!num_vfs) 2845 goto out; 2846 2847 if (old_vfs) { 2848 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2849 old_vfs, max_vfs); 2850 adapter->vfs_allocated_count = old_vfs; 2851 } else 2852 adapter->vfs_allocated_count = num_vfs; 2853 2854 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2855 sizeof(struct vf_data_storage), GFP_KERNEL); 2856 2857 /* if allocation failed then we do not support SR-IOV */ 2858 if (!adapter->vf_data) { 2859 adapter->vfs_allocated_count = 0; 2860 dev_err(&pdev->dev, 2861 "Unable to allocate memory for VF Data Storage\n"); 2862 err = -ENOMEM; 2863 goto out; 2864 } 2865 2866 /* Due to the limited number of RAR entries calculate potential 2867 * number of MAC filters available for the VFs. Reserve entries 2868 * for PF default MAC, PF MAC filters and at least one RAR entry 2869 * for each VF for VF MAC. 2870 */ 2871 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 2872 (1 + IGB_PF_MAC_FILTERS_RESERVED + 2873 adapter->vfs_allocated_count); 2874 2875 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 2876 sizeof(struct vf_mac_filter), 2877 GFP_KERNEL); 2878 2879 mac_list = adapter->vf_mac_list; 2880 INIT_LIST_HEAD(&adapter->vf_macs.l); 2881 2882 if (adapter->vf_mac_list) { 2883 /* Initialize list of VF MAC filters */ 2884 for (i = 0; i < num_vf_mac_filters; i++) { 2885 mac_list->vf = -1; 2886 mac_list->free = true; 2887 list_add(&mac_list->l, &adapter->vf_macs.l); 2888 mac_list++; 2889 } 2890 } else { 2891 /* If we could not allocate memory for the VF MAC filters 2892 * we can continue without this feature but warn user. 2893 */ 2894 dev_err(&pdev->dev, 2895 "Unable to allocate memory for VF MAC filter list\n"); 2896 } 2897 2898 /* only call pci_enable_sriov() if no VFs are allocated already */ 2899 if (!old_vfs) { 2900 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2901 if (err) 2902 goto err_out; 2903 } 2904 dev_info(&pdev->dev, "%d VFs allocated\n", 2905 adapter->vfs_allocated_count); 2906 for (i = 0; i < adapter->vfs_allocated_count; i++) 2907 igb_vf_configure(adapter, i); 2908 2909 /* DMA Coalescing is not supported in IOV mode. */ 2910 adapter->flags &= ~IGB_FLAG_DMAC; 2911 goto out; 2912 2913 err_out: 2914 kfree(adapter->vf_mac_list); 2915 adapter->vf_mac_list = NULL; 2916 kfree(adapter->vf_data); 2917 adapter->vf_data = NULL; 2918 adapter->vfs_allocated_count = 0; 2919 out: 2920 return err; 2921 } 2922 2923 #endif 2924 /** 2925 * igb_remove_i2c - Cleanup I2C interface 2926 * @adapter: pointer to adapter structure 2927 **/ 2928 static void igb_remove_i2c(struct igb_adapter *adapter) 2929 { 2930 /* free the adapter bus structure */ 2931 i2c_del_adapter(&adapter->i2c_adap); 2932 } 2933 2934 /** 2935 * igb_remove - Device Removal Routine 2936 * @pdev: PCI device information struct 2937 * 2938 * igb_remove is called by the PCI subsystem to alert the driver 2939 * that it should release a PCI device. The could be caused by a 2940 * Hot-Plug event, or because the driver is going to be removed from 2941 * memory. 2942 **/ 2943 static void igb_remove(struct pci_dev *pdev) 2944 { 2945 struct net_device *netdev = pci_get_drvdata(pdev); 2946 struct igb_adapter *adapter = netdev_priv(netdev); 2947 struct e1000_hw *hw = &adapter->hw; 2948 2949 pm_runtime_get_noresume(&pdev->dev); 2950 #ifdef CONFIG_IGB_HWMON 2951 igb_sysfs_exit(adapter); 2952 #endif 2953 igb_remove_i2c(adapter); 2954 igb_ptp_stop(adapter); 2955 /* The watchdog timer may be rescheduled, so explicitly 2956 * disable watchdog from being rescheduled. 2957 */ 2958 set_bit(__IGB_DOWN, &adapter->state); 2959 del_timer_sync(&adapter->watchdog_timer); 2960 del_timer_sync(&adapter->phy_info_timer); 2961 2962 cancel_work_sync(&adapter->reset_task); 2963 cancel_work_sync(&adapter->watchdog_task); 2964 2965 #ifdef CONFIG_IGB_DCA 2966 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2967 dev_info(&pdev->dev, "DCA disabled\n"); 2968 dca_remove_requester(&pdev->dev); 2969 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2970 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2971 } 2972 #endif 2973 2974 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2975 * would have already happened in close and is redundant. 2976 */ 2977 igb_release_hw_control(adapter); 2978 2979 #ifdef CONFIG_PCI_IOV 2980 igb_disable_sriov(pdev); 2981 #endif 2982 2983 unregister_netdev(netdev); 2984 2985 igb_clear_interrupt_scheme(adapter); 2986 2987 pci_iounmap(pdev, adapter->io_addr); 2988 if (hw->flash_address) 2989 iounmap(hw->flash_address); 2990 pci_release_mem_regions(pdev); 2991 2992 kfree(adapter->mac_table); 2993 kfree(adapter->shadow_vfta); 2994 free_netdev(netdev); 2995 2996 pci_disable_pcie_error_reporting(pdev); 2997 2998 pci_disable_device(pdev); 2999 } 3000 3001 /** 3002 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3003 * @adapter: board private structure to initialize 3004 * 3005 * This function initializes the vf specific data storage and then attempts to 3006 * allocate the VFs. The reason for ordering it this way is because it is much 3007 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3008 * the memory for the VFs. 3009 **/ 3010 static void igb_probe_vfs(struct igb_adapter *adapter) 3011 { 3012 #ifdef CONFIG_PCI_IOV 3013 struct pci_dev *pdev = adapter->pdev; 3014 struct e1000_hw *hw = &adapter->hw; 3015 3016 /* Virtualization features not supported on i210 family. */ 3017 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3018 return; 3019 3020 /* Of the below we really only want the effect of getting 3021 * IGB_FLAG_HAS_MSIX set (if available), without which 3022 * igb_enable_sriov() has no effect. 3023 */ 3024 igb_set_interrupt_capability(adapter, true); 3025 igb_reset_interrupt_capability(adapter); 3026 3027 pci_sriov_set_totalvfs(pdev, 7); 3028 igb_enable_sriov(pdev, max_vfs); 3029 3030 #endif /* CONFIG_PCI_IOV */ 3031 } 3032 3033 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3034 { 3035 struct e1000_hw *hw = &adapter->hw; 3036 u32 max_rss_queues; 3037 3038 /* Determine the maximum number of RSS queues supported. */ 3039 switch (hw->mac.type) { 3040 case e1000_i211: 3041 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3042 break; 3043 case e1000_82575: 3044 case e1000_i210: 3045 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3046 break; 3047 case e1000_i350: 3048 /* I350 cannot do RSS and SR-IOV at the same time */ 3049 if (!!adapter->vfs_allocated_count) { 3050 max_rss_queues = 1; 3051 break; 3052 } 3053 /* fall through */ 3054 case e1000_82576: 3055 if (!!adapter->vfs_allocated_count) { 3056 max_rss_queues = 2; 3057 break; 3058 } 3059 /* fall through */ 3060 case e1000_82580: 3061 case e1000_i354: 3062 default: 3063 max_rss_queues = IGB_MAX_RX_QUEUES; 3064 break; 3065 } 3066 3067 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3068 3069 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3070 } 3071 3072 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3073 const u32 max_rss_queues) 3074 { 3075 struct e1000_hw *hw = &adapter->hw; 3076 3077 /* Determine if we need to pair queues. */ 3078 switch (hw->mac.type) { 3079 case e1000_82575: 3080 case e1000_i211: 3081 /* Device supports enough interrupts without queue pairing. */ 3082 break; 3083 case e1000_82576: 3084 case e1000_82580: 3085 case e1000_i350: 3086 case e1000_i354: 3087 case e1000_i210: 3088 default: 3089 /* If rss_queues > half of max_rss_queues, pair the queues in 3090 * order to conserve interrupts due to limited supply. 3091 */ 3092 if (adapter->rss_queues > (max_rss_queues / 2)) 3093 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3094 else 3095 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3096 break; 3097 } 3098 } 3099 3100 /** 3101 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3102 * @adapter: board private structure to initialize 3103 * 3104 * igb_sw_init initializes the Adapter private data structure. 3105 * Fields are initialized based on PCI device information and 3106 * OS network device settings (MTU size). 3107 **/ 3108 static int igb_sw_init(struct igb_adapter *adapter) 3109 { 3110 struct e1000_hw *hw = &adapter->hw; 3111 struct net_device *netdev = adapter->netdev; 3112 struct pci_dev *pdev = adapter->pdev; 3113 3114 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3115 3116 /* set default ring sizes */ 3117 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3118 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3119 3120 /* set default ITR values */ 3121 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3122 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3123 3124 /* set default work limits */ 3125 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3126 3127 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3128 VLAN_HLEN; 3129 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3130 3131 spin_lock_init(&adapter->nfc_lock); 3132 spin_lock_init(&adapter->stats64_lock); 3133 #ifdef CONFIG_PCI_IOV 3134 switch (hw->mac.type) { 3135 case e1000_82576: 3136 case e1000_i350: 3137 if (max_vfs > 7) { 3138 dev_warn(&pdev->dev, 3139 "Maximum of 7 VFs per PF, using max\n"); 3140 max_vfs = adapter->vfs_allocated_count = 7; 3141 } else 3142 adapter->vfs_allocated_count = max_vfs; 3143 if (adapter->vfs_allocated_count) 3144 dev_warn(&pdev->dev, 3145 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3146 break; 3147 default: 3148 break; 3149 } 3150 #endif /* CONFIG_PCI_IOV */ 3151 3152 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3153 adapter->flags |= IGB_FLAG_HAS_MSIX; 3154 3155 adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) * 3156 hw->mac.rar_entry_count, GFP_ATOMIC); 3157 if (!adapter->mac_table) 3158 return -ENOMEM; 3159 3160 igb_probe_vfs(adapter); 3161 3162 igb_init_queue_configuration(adapter); 3163 3164 /* Setup and initialize a copy of the hw vlan table array */ 3165 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 3166 GFP_ATOMIC); 3167 3168 /* This call may decrease the number of queues */ 3169 if (igb_init_interrupt_scheme(adapter, true)) { 3170 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3171 return -ENOMEM; 3172 } 3173 3174 /* Explicitly disable IRQ since the NIC can be in any state. */ 3175 igb_irq_disable(adapter); 3176 3177 if (hw->mac.type >= e1000_i350) 3178 adapter->flags &= ~IGB_FLAG_DMAC; 3179 3180 set_bit(__IGB_DOWN, &adapter->state); 3181 return 0; 3182 } 3183 3184 /** 3185 * igb_open - Called when a network interface is made active 3186 * @netdev: network interface device structure 3187 * 3188 * Returns 0 on success, negative value on failure 3189 * 3190 * The open entry point is called when a network interface is made 3191 * active by the system (IFF_UP). At this point all resources needed 3192 * for transmit and receive operations are allocated, the interrupt 3193 * handler is registered with the OS, the watchdog timer is started, 3194 * and the stack is notified that the interface is ready. 3195 **/ 3196 static int __igb_open(struct net_device *netdev, bool resuming) 3197 { 3198 struct igb_adapter *adapter = netdev_priv(netdev); 3199 struct e1000_hw *hw = &adapter->hw; 3200 struct pci_dev *pdev = adapter->pdev; 3201 int err; 3202 int i; 3203 3204 /* disallow open during test */ 3205 if (test_bit(__IGB_TESTING, &adapter->state)) { 3206 WARN_ON(resuming); 3207 return -EBUSY; 3208 } 3209 3210 if (!resuming) 3211 pm_runtime_get_sync(&pdev->dev); 3212 3213 netif_carrier_off(netdev); 3214 3215 /* allocate transmit descriptors */ 3216 err = igb_setup_all_tx_resources(adapter); 3217 if (err) 3218 goto err_setup_tx; 3219 3220 /* allocate receive descriptors */ 3221 err = igb_setup_all_rx_resources(adapter); 3222 if (err) 3223 goto err_setup_rx; 3224 3225 igb_power_up_link(adapter); 3226 3227 /* before we allocate an interrupt, we must be ready to handle it. 3228 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3229 * as soon as we call pci_request_irq, so we have to setup our 3230 * clean_rx handler before we do so. 3231 */ 3232 igb_configure(adapter); 3233 3234 err = igb_request_irq(adapter); 3235 if (err) 3236 goto err_req_irq; 3237 3238 /* Notify the stack of the actual queue counts. */ 3239 err = netif_set_real_num_tx_queues(adapter->netdev, 3240 adapter->num_tx_queues); 3241 if (err) 3242 goto err_set_queues; 3243 3244 err = netif_set_real_num_rx_queues(adapter->netdev, 3245 adapter->num_rx_queues); 3246 if (err) 3247 goto err_set_queues; 3248 3249 /* From here on the code is the same as igb_up() */ 3250 clear_bit(__IGB_DOWN, &adapter->state); 3251 3252 for (i = 0; i < adapter->num_q_vectors; i++) 3253 napi_enable(&(adapter->q_vector[i]->napi)); 3254 3255 /* Clear any pending interrupts. */ 3256 rd32(E1000_ICR); 3257 3258 igb_irq_enable(adapter); 3259 3260 /* notify VFs that reset has been completed */ 3261 if (adapter->vfs_allocated_count) { 3262 u32 reg_data = rd32(E1000_CTRL_EXT); 3263 3264 reg_data |= E1000_CTRL_EXT_PFRSTD; 3265 wr32(E1000_CTRL_EXT, reg_data); 3266 } 3267 3268 netif_tx_start_all_queues(netdev); 3269 3270 if (!resuming) 3271 pm_runtime_put(&pdev->dev); 3272 3273 /* start the watchdog. */ 3274 hw->mac.get_link_status = 1; 3275 schedule_work(&adapter->watchdog_task); 3276 3277 return 0; 3278 3279 err_set_queues: 3280 igb_free_irq(adapter); 3281 err_req_irq: 3282 igb_release_hw_control(adapter); 3283 igb_power_down_link(adapter); 3284 igb_free_all_rx_resources(adapter); 3285 err_setup_rx: 3286 igb_free_all_tx_resources(adapter); 3287 err_setup_tx: 3288 igb_reset(adapter); 3289 if (!resuming) 3290 pm_runtime_put(&pdev->dev); 3291 3292 return err; 3293 } 3294 3295 int igb_open(struct net_device *netdev) 3296 { 3297 return __igb_open(netdev, false); 3298 } 3299 3300 /** 3301 * igb_close - Disables a network interface 3302 * @netdev: network interface device structure 3303 * 3304 * Returns 0, this is not allowed to fail 3305 * 3306 * The close entry point is called when an interface is de-activated 3307 * by the OS. The hardware is still under the driver's control, but 3308 * needs to be disabled. A global MAC reset is issued to stop the 3309 * hardware, and all transmit and receive resources are freed. 3310 **/ 3311 static int __igb_close(struct net_device *netdev, bool suspending) 3312 { 3313 struct igb_adapter *adapter = netdev_priv(netdev); 3314 struct pci_dev *pdev = adapter->pdev; 3315 3316 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3317 3318 if (!suspending) 3319 pm_runtime_get_sync(&pdev->dev); 3320 3321 igb_down(adapter); 3322 igb_free_irq(adapter); 3323 3324 igb_nfc_filter_exit(adapter); 3325 3326 igb_free_all_tx_resources(adapter); 3327 igb_free_all_rx_resources(adapter); 3328 3329 if (!suspending) 3330 pm_runtime_put_sync(&pdev->dev); 3331 return 0; 3332 } 3333 3334 int igb_close(struct net_device *netdev) 3335 { 3336 if (netif_device_present(netdev)) 3337 return __igb_close(netdev, false); 3338 return 0; 3339 } 3340 3341 /** 3342 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3343 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3344 * 3345 * Return 0 on success, negative on failure 3346 **/ 3347 int igb_setup_tx_resources(struct igb_ring *tx_ring) 3348 { 3349 struct device *dev = tx_ring->dev; 3350 int size; 3351 3352 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3353 3354 tx_ring->tx_buffer_info = vmalloc(size); 3355 if (!tx_ring->tx_buffer_info) 3356 goto err; 3357 3358 /* round up to nearest 4K */ 3359 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3360 tx_ring->size = ALIGN(tx_ring->size, 4096); 3361 3362 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3363 &tx_ring->dma, GFP_KERNEL); 3364 if (!tx_ring->desc) 3365 goto err; 3366 3367 tx_ring->next_to_use = 0; 3368 tx_ring->next_to_clean = 0; 3369 3370 return 0; 3371 3372 err: 3373 vfree(tx_ring->tx_buffer_info); 3374 tx_ring->tx_buffer_info = NULL; 3375 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3376 return -ENOMEM; 3377 } 3378 3379 /** 3380 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3381 * (Descriptors) for all queues 3382 * @adapter: board private structure 3383 * 3384 * Return 0 on success, negative on failure 3385 **/ 3386 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3387 { 3388 struct pci_dev *pdev = adapter->pdev; 3389 int i, err = 0; 3390 3391 for (i = 0; i < adapter->num_tx_queues; i++) { 3392 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3393 if (err) { 3394 dev_err(&pdev->dev, 3395 "Allocation for Tx Queue %u failed\n", i); 3396 for (i--; i >= 0; i--) 3397 igb_free_tx_resources(adapter->tx_ring[i]); 3398 break; 3399 } 3400 } 3401 3402 return err; 3403 } 3404 3405 /** 3406 * igb_setup_tctl - configure the transmit control registers 3407 * @adapter: Board private structure 3408 **/ 3409 void igb_setup_tctl(struct igb_adapter *adapter) 3410 { 3411 struct e1000_hw *hw = &adapter->hw; 3412 u32 tctl; 3413 3414 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3415 wr32(E1000_TXDCTL(0), 0); 3416 3417 /* Program the Transmit Control Register */ 3418 tctl = rd32(E1000_TCTL); 3419 tctl &= ~E1000_TCTL_CT; 3420 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3421 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3422 3423 igb_config_collision_dist(hw); 3424 3425 /* Enable transmits */ 3426 tctl |= E1000_TCTL_EN; 3427 3428 wr32(E1000_TCTL, tctl); 3429 } 3430 3431 /** 3432 * igb_configure_tx_ring - Configure transmit ring after Reset 3433 * @adapter: board private structure 3434 * @ring: tx ring to configure 3435 * 3436 * Configure a transmit ring after a reset. 3437 **/ 3438 void igb_configure_tx_ring(struct igb_adapter *adapter, 3439 struct igb_ring *ring) 3440 { 3441 struct e1000_hw *hw = &adapter->hw; 3442 u32 txdctl = 0; 3443 u64 tdba = ring->dma; 3444 int reg_idx = ring->reg_idx; 3445 3446 /* disable the queue */ 3447 wr32(E1000_TXDCTL(reg_idx), 0); 3448 wrfl(); 3449 mdelay(10); 3450 3451 wr32(E1000_TDLEN(reg_idx), 3452 ring->count * sizeof(union e1000_adv_tx_desc)); 3453 wr32(E1000_TDBAL(reg_idx), 3454 tdba & 0x00000000ffffffffULL); 3455 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3456 3457 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 3458 wr32(E1000_TDH(reg_idx), 0); 3459 writel(0, ring->tail); 3460 3461 txdctl |= IGB_TX_PTHRESH; 3462 txdctl |= IGB_TX_HTHRESH << 8; 3463 txdctl |= IGB_TX_WTHRESH << 16; 3464 3465 /* reinitialize tx_buffer_info */ 3466 memset(ring->tx_buffer_info, 0, 3467 sizeof(struct igb_tx_buffer) * ring->count); 3468 3469 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3470 wr32(E1000_TXDCTL(reg_idx), txdctl); 3471 } 3472 3473 /** 3474 * igb_configure_tx - Configure transmit Unit after Reset 3475 * @adapter: board private structure 3476 * 3477 * Configure the Tx unit of the MAC after a reset. 3478 **/ 3479 static void igb_configure_tx(struct igb_adapter *adapter) 3480 { 3481 int i; 3482 3483 for (i = 0; i < adapter->num_tx_queues; i++) 3484 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3485 } 3486 3487 /** 3488 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3489 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3490 * 3491 * Returns 0 on success, negative on failure 3492 **/ 3493 int igb_setup_rx_resources(struct igb_ring *rx_ring) 3494 { 3495 struct device *dev = rx_ring->dev; 3496 int size; 3497 3498 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3499 3500 rx_ring->rx_buffer_info = vmalloc(size); 3501 if (!rx_ring->rx_buffer_info) 3502 goto err; 3503 3504 /* Round up to nearest 4K */ 3505 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3506 rx_ring->size = ALIGN(rx_ring->size, 4096); 3507 3508 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3509 &rx_ring->dma, GFP_KERNEL); 3510 if (!rx_ring->desc) 3511 goto err; 3512 3513 rx_ring->next_to_alloc = 0; 3514 rx_ring->next_to_clean = 0; 3515 rx_ring->next_to_use = 0; 3516 3517 return 0; 3518 3519 err: 3520 vfree(rx_ring->rx_buffer_info); 3521 rx_ring->rx_buffer_info = NULL; 3522 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3523 return -ENOMEM; 3524 } 3525 3526 /** 3527 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3528 * (Descriptors) for all queues 3529 * @adapter: board private structure 3530 * 3531 * Return 0 on success, negative on failure 3532 **/ 3533 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3534 { 3535 struct pci_dev *pdev = adapter->pdev; 3536 int i, err = 0; 3537 3538 for (i = 0; i < adapter->num_rx_queues; i++) { 3539 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3540 if (err) { 3541 dev_err(&pdev->dev, 3542 "Allocation for Rx Queue %u failed\n", i); 3543 for (i--; i >= 0; i--) 3544 igb_free_rx_resources(adapter->rx_ring[i]); 3545 break; 3546 } 3547 } 3548 3549 return err; 3550 } 3551 3552 /** 3553 * igb_setup_mrqc - configure the multiple receive queue control registers 3554 * @adapter: Board private structure 3555 **/ 3556 static void igb_setup_mrqc(struct igb_adapter *adapter) 3557 { 3558 struct e1000_hw *hw = &adapter->hw; 3559 u32 mrqc, rxcsum; 3560 u32 j, num_rx_queues; 3561 u32 rss_key[10]; 3562 3563 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3564 for (j = 0; j < 10; j++) 3565 wr32(E1000_RSSRK(j), rss_key[j]); 3566 3567 num_rx_queues = adapter->rss_queues; 3568 3569 switch (hw->mac.type) { 3570 case e1000_82576: 3571 /* 82576 supports 2 RSS queues for SR-IOV */ 3572 if (adapter->vfs_allocated_count) 3573 num_rx_queues = 2; 3574 break; 3575 default: 3576 break; 3577 } 3578 3579 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3580 for (j = 0; j < IGB_RETA_SIZE; j++) 3581 adapter->rss_indir_tbl[j] = 3582 (j * num_rx_queues) / IGB_RETA_SIZE; 3583 adapter->rss_indir_tbl_init = num_rx_queues; 3584 } 3585 igb_write_rss_indir_tbl(adapter); 3586 3587 /* Disable raw packet checksumming so that RSS hash is placed in 3588 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3589 * offloads as they are enabled by default 3590 */ 3591 rxcsum = rd32(E1000_RXCSUM); 3592 rxcsum |= E1000_RXCSUM_PCSD; 3593 3594 if (adapter->hw.mac.type >= e1000_82576) 3595 /* Enable Receive Checksum Offload for SCTP */ 3596 rxcsum |= E1000_RXCSUM_CRCOFL; 3597 3598 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3599 wr32(E1000_RXCSUM, rxcsum); 3600 3601 /* Generate RSS hash based on packet types, TCP/UDP 3602 * port numbers and/or IPv4/v6 src and dst addresses 3603 */ 3604 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3605 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3606 E1000_MRQC_RSS_FIELD_IPV6 | 3607 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3608 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3609 3610 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3611 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3612 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3613 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3614 3615 /* If VMDq is enabled then we set the appropriate mode for that, else 3616 * we default to RSS so that an RSS hash is calculated per packet even 3617 * if we are only using one queue 3618 */ 3619 if (adapter->vfs_allocated_count) { 3620 if (hw->mac.type > e1000_82575) { 3621 /* Set the default pool for the PF's first queue */ 3622 u32 vtctl = rd32(E1000_VT_CTL); 3623 3624 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3625 E1000_VT_CTL_DISABLE_DEF_POOL); 3626 vtctl |= adapter->vfs_allocated_count << 3627 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3628 wr32(E1000_VT_CTL, vtctl); 3629 } 3630 if (adapter->rss_queues > 1) 3631 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 3632 else 3633 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3634 } else { 3635 if (hw->mac.type != e1000_i211) 3636 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 3637 } 3638 igb_vmm_control(adapter); 3639 3640 wr32(E1000_MRQC, mrqc); 3641 } 3642 3643 /** 3644 * igb_setup_rctl - configure the receive control registers 3645 * @adapter: Board private structure 3646 **/ 3647 void igb_setup_rctl(struct igb_adapter *adapter) 3648 { 3649 struct e1000_hw *hw = &adapter->hw; 3650 u32 rctl; 3651 3652 rctl = rd32(E1000_RCTL); 3653 3654 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3655 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3656 3657 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3658 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3659 3660 /* enable stripping of CRC. It's unlikely this will break BMC 3661 * redirection as it did with e1000. Newer features require 3662 * that the HW strips the CRC. 3663 */ 3664 rctl |= E1000_RCTL_SECRC; 3665 3666 /* disable store bad packets and clear size bits. */ 3667 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3668 3669 /* enable LPE to allow for reception of jumbo frames */ 3670 rctl |= E1000_RCTL_LPE; 3671 3672 /* disable queue 0 to prevent tail write w/o re-config */ 3673 wr32(E1000_RXDCTL(0), 0); 3674 3675 /* Attention!!! For SR-IOV PF driver operations you must enable 3676 * queue drop for all VF and PF queues to prevent head of line blocking 3677 * if an un-trusted VF does not provide descriptors to hardware. 3678 */ 3679 if (adapter->vfs_allocated_count) { 3680 /* set all queue drop enable bits */ 3681 wr32(E1000_QDE, ALL_QUEUES); 3682 } 3683 3684 /* This is useful for sniffing bad packets. */ 3685 if (adapter->netdev->features & NETIF_F_RXALL) { 3686 /* UPE and MPE will be handled by normal PROMISC logic 3687 * in e1000e_set_rx_mode 3688 */ 3689 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3690 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3691 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3692 3693 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 3694 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3695 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3696 * and that breaks VLANs. 3697 */ 3698 } 3699 3700 wr32(E1000_RCTL, rctl); 3701 } 3702 3703 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3704 int vfn) 3705 { 3706 struct e1000_hw *hw = &adapter->hw; 3707 u32 vmolr; 3708 3709 if (size > MAX_JUMBO_FRAME_SIZE) 3710 size = MAX_JUMBO_FRAME_SIZE; 3711 3712 vmolr = rd32(E1000_VMOLR(vfn)); 3713 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3714 vmolr |= size | E1000_VMOLR_LPE; 3715 wr32(E1000_VMOLR(vfn), vmolr); 3716 3717 return 0; 3718 } 3719 3720 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 3721 int vfn, bool enable) 3722 { 3723 struct e1000_hw *hw = &adapter->hw; 3724 u32 val, reg; 3725 3726 if (hw->mac.type < e1000_82576) 3727 return; 3728 3729 if (hw->mac.type == e1000_i350) 3730 reg = E1000_DVMOLR(vfn); 3731 else 3732 reg = E1000_VMOLR(vfn); 3733 3734 val = rd32(reg); 3735 if (enable) 3736 val |= E1000_VMOLR_STRVLAN; 3737 else 3738 val &= ~(E1000_VMOLR_STRVLAN); 3739 wr32(reg, val); 3740 } 3741 3742 static inline void igb_set_vmolr(struct igb_adapter *adapter, 3743 int vfn, bool aupe) 3744 { 3745 struct e1000_hw *hw = &adapter->hw; 3746 u32 vmolr; 3747 3748 /* This register exists only on 82576 and newer so if we are older then 3749 * we should exit and do nothing 3750 */ 3751 if (hw->mac.type < e1000_82576) 3752 return; 3753 3754 vmolr = rd32(E1000_VMOLR(vfn)); 3755 if (aupe) 3756 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3757 else 3758 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3759 3760 /* clear all bits that might not be set */ 3761 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3762 3763 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3764 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3765 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3766 * multicast packets 3767 */ 3768 if (vfn <= adapter->vfs_allocated_count) 3769 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3770 3771 wr32(E1000_VMOLR(vfn), vmolr); 3772 } 3773 3774 /** 3775 * igb_configure_rx_ring - Configure a receive ring after Reset 3776 * @adapter: board private structure 3777 * @ring: receive ring to be configured 3778 * 3779 * Configure the Rx unit of the MAC after a reset. 3780 **/ 3781 void igb_configure_rx_ring(struct igb_adapter *adapter, 3782 struct igb_ring *ring) 3783 { 3784 struct e1000_hw *hw = &adapter->hw; 3785 union e1000_adv_rx_desc *rx_desc; 3786 u64 rdba = ring->dma; 3787 int reg_idx = ring->reg_idx; 3788 u32 srrctl = 0, rxdctl = 0; 3789 3790 /* disable the queue */ 3791 wr32(E1000_RXDCTL(reg_idx), 0); 3792 3793 /* Set DMA base address registers */ 3794 wr32(E1000_RDBAL(reg_idx), 3795 rdba & 0x00000000ffffffffULL); 3796 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3797 wr32(E1000_RDLEN(reg_idx), 3798 ring->count * sizeof(union e1000_adv_rx_desc)); 3799 3800 /* initialize head and tail */ 3801 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 3802 wr32(E1000_RDH(reg_idx), 0); 3803 writel(0, ring->tail); 3804 3805 /* set descriptor configuration */ 3806 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3807 if (ring_uses_large_buffer(ring)) 3808 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3809 else 3810 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3811 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3812 if (hw->mac.type >= e1000_82580) 3813 srrctl |= E1000_SRRCTL_TIMESTAMP; 3814 /* Only set Drop Enable if we are supporting multiple queues */ 3815 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3816 srrctl |= E1000_SRRCTL_DROP_EN; 3817 3818 wr32(E1000_SRRCTL(reg_idx), srrctl); 3819 3820 /* set filtering for VMDQ pools */ 3821 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3822 3823 rxdctl |= IGB_RX_PTHRESH; 3824 rxdctl |= IGB_RX_HTHRESH << 8; 3825 rxdctl |= IGB_RX_WTHRESH << 16; 3826 3827 /* initialize rx_buffer_info */ 3828 memset(ring->rx_buffer_info, 0, 3829 sizeof(struct igb_rx_buffer) * ring->count); 3830 3831 /* initialize Rx descriptor 0 */ 3832 rx_desc = IGB_RX_DESC(ring, 0); 3833 rx_desc->wb.upper.length = 0; 3834 3835 /* enable receive descriptor fetching */ 3836 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3837 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3838 } 3839 3840 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 3841 struct igb_ring *rx_ring) 3842 { 3843 /* set build_skb and buffer size flags */ 3844 clear_ring_build_skb_enabled(rx_ring); 3845 clear_ring_uses_large_buffer(rx_ring); 3846 3847 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3848 return; 3849 3850 set_ring_build_skb_enabled(rx_ring); 3851 3852 #if (PAGE_SIZE < 8192) 3853 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 3854 return; 3855 3856 set_ring_uses_large_buffer(rx_ring); 3857 #endif 3858 } 3859 3860 /** 3861 * igb_configure_rx - Configure receive Unit after Reset 3862 * @adapter: board private structure 3863 * 3864 * Configure the Rx unit of the MAC after a reset. 3865 **/ 3866 static void igb_configure_rx(struct igb_adapter *adapter) 3867 { 3868 int i; 3869 3870 /* set the correct pool for the PF default MAC address in entry 0 */ 3871 igb_set_default_mac_filter(adapter); 3872 3873 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3874 * the Base and Length of the Rx Descriptor Ring 3875 */ 3876 for (i = 0; i < adapter->num_rx_queues; i++) { 3877 struct igb_ring *rx_ring = adapter->rx_ring[i]; 3878 3879 igb_set_rx_buffer_len(adapter, rx_ring); 3880 igb_configure_rx_ring(adapter, rx_ring); 3881 } 3882 } 3883 3884 /** 3885 * igb_free_tx_resources - Free Tx Resources per Queue 3886 * @tx_ring: Tx descriptor ring for a specific queue 3887 * 3888 * Free all transmit software resources 3889 **/ 3890 void igb_free_tx_resources(struct igb_ring *tx_ring) 3891 { 3892 igb_clean_tx_ring(tx_ring); 3893 3894 vfree(tx_ring->tx_buffer_info); 3895 tx_ring->tx_buffer_info = NULL; 3896 3897 /* if not set, then don't free */ 3898 if (!tx_ring->desc) 3899 return; 3900 3901 dma_free_coherent(tx_ring->dev, tx_ring->size, 3902 tx_ring->desc, tx_ring->dma); 3903 3904 tx_ring->desc = NULL; 3905 } 3906 3907 /** 3908 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3909 * @adapter: board private structure 3910 * 3911 * Free all transmit software resources 3912 **/ 3913 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3914 { 3915 int i; 3916 3917 for (i = 0; i < adapter->num_tx_queues; i++) 3918 if (adapter->tx_ring[i]) 3919 igb_free_tx_resources(adapter->tx_ring[i]); 3920 } 3921 3922 /** 3923 * igb_clean_tx_ring - Free Tx Buffers 3924 * @tx_ring: ring to be cleaned 3925 **/ 3926 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3927 { 3928 u16 i = tx_ring->next_to_clean; 3929 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 3930 3931 while (i != tx_ring->next_to_use) { 3932 union e1000_adv_tx_desc *eop_desc, *tx_desc; 3933 3934 /* Free all the Tx ring sk_buffs */ 3935 dev_kfree_skb_any(tx_buffer->skb); 3936 3937 /* unmap skb header data */ 3938 dma_unmap_single(tx_ring->dev, 3939 dma_unmap_addr(tx_buffer, dma), 3940 dma_unmap_len(tx_buffer, len), 3941 DMA_TO_DEVICE); 3942 3943 /* check for eop_desc to determine the end of the packet */ 3944 eop_desc = tx_buffer->next_to_watch; 3945 tx_desc = IGB_TX_DESC(tx_ring, i); 3946 3947 /* unmap remaining buffers */ 3948 while (tx_desc != eop_desc) { 3949 tx_buffer++; 3950 tx_desc++; 3951 i++; 3952 if (unlikely(i == tx_ring->count)) { 3953 i = 0; 3954 tx_buffer = tx_ring->tx_buffer_info; 3955 tx_desc = IGB_TX_DESC(tx_ring, 0); 3956 } 3957 3958 /* unmap any remaining paged data */ 3959 if (dma_unmap_len(tx_buffer, len)) 3960 dma_unmap_page(tx_ring->dev, 3961 dma_unmap_addr(tx_buffer, dma), 3962 dma_unmap_len(tx_buffer, len), 3963 DMA_TO_DEVICE); 3964 } 3965 3966 /* move us one more past the eop_desc for start of next pkt */ 3967 tx_buffer++; 3968 i++; 3969 if (unlikely(i == tx_ring->count)) { 3970 i = 0; 3971 tx_buffer = tx_ring->tx_buffer_info; 3972 } 3973 } 3974 3975 /* reset BQL for queue */ 3976 netdev_tx_reset_queue(txring_txq(tx_ring)); 3977 3978 /* reset next_to_use and next_to_clean */ 3979 tx_ring->next_to_use = 0; 3980 tx_ring->next_to_clean = 0; 3981 } 3982 3983 /** 3984 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3985 * @adapter: board private structure 3986 **/ 3987 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3988 { 3989 int i; 3990 3991 for (i = 0; i < adapter->num_tx_queues; i++) 3992 if (adapter->tx_ring[i]) 3993 igb_clean_tx_ring(adapter->tx_ring[i]); 3994 } 3995 3996 /** 3997 * igb_free_rx_resources - Free Rx Resources 3998 * @rx_ring: ring to clean the resources from 3999 * 4000 * Free all receive software resources 4001 **/ 4002 void igb_free_rx_resources(struct igb_ring *rx_ring) 4003 { 4004 igb_clean_rx_ring(rx_ring); 4005 4006 vfree(rx_ring->rx_buffer_info); 4007 rx_ring->rx_buffer_info = NULL; 4008 4009 /* if not set, then don't free */ 4010 if (!rx_ring->desc) 4011 return; 4012 4013 dma_free_coherent(rx_ring->dev, rx_ring->size, 4014 rx_ring->desc, rx_ring->dma); 4015 4016 rx_ring->desc = NULL; 4017 } 4018 4019 /** 4020 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4021 * @adapter: board private structure 4022 * 4023 * Free all receive software resources 4024 **/ 4025 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4026 { 4027 int i; 4028 4029 for (i = 0; i < adapter->num_rx_queues; i++) 4030 if (adapter->rx_ring[i]) 4031 igb_free_rx_resources(adapter->rx_ring[i]); 4032 } 4033 4034 /** 4035 * igb_clean_rx_ring - Free Rx Buffers per Queue 4036 * @rx_ring: ring to free buffers from 4037 **/ 4038 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4039 { 4040 u16 i = rx_ring->next_to_clean; 4041 4042 if (rx_ring->skb) 4043 dev_kfree_skb(rx_ring->skb); 4044 rx_ring->skb = NULL; 4045 4046 /* Free all the Rx ring sk_buffs */ 4047 while (i != rx_ring->next_to_alloc) { 4048 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4049 4050 /* Invalidate cache lines that may have been written to by 4051 * device so that we avoid corrupting memory. 4052 */ 4053 dma_sync_single_range_for_cpu(rx_ring->dev, 4054 buffer_info->dma, 4055 buffer_info->page_offset, 4056 igb_rx_bufsz(rx_ring), 4057 DMA_FROM_DEVICE); 4058 4059 /* free resources associated with mapping */ 4060 dma_unmap_page_attrs(rx_ring->dev, 4061 buffer_info->dma, 4062 igb_rx_pg_size(rx_ring), 4063 DMA_FROM_DEVICE, 4064 IGB_RX_DMA_ATTR); 4065 __page_frag_cache_drain(buffer_info->page, 4066 buffer_info->pagecnt_bias); 4067 4068 i++; 4069 if (i == rx_ring->count) 4070 i = 0; 4071 } 4072 4073 rx_ring->next_to_alloc = 0; 4074 rx_ring->next_to_clean = 0; 4075 rx_ring->next_to_use = 0; 4076 } 4077 4078 /** 4079 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4080 * @adapter: board private structure 4081 **/ 4082 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4083 { 4084 int i; 4085 4086 for (i = 0; i < adapter->num_rx_queues; i++) 4087 if (adapter->rx_ring[i]) 4088 igb_clean_rx_ring(adapter->rx_ring[i]); 4089 } 4090 4091 /** 4092 * igb_set_mac - Change the Ethernet Address of the NIC 4093 * @netdev: network interface device structure 4094 * @p: pointer to an address structure 4095 * 4096 * Returns 0 on success, negative on failure 4097 **/ 4098 static int igb_set_mac(struct net_device *netdev, void *p) 4099 { 4100 struct igb_adapter *adapter = netdev_priv(netdev); 4101 struct e1000_hw *hw = &adapter->hw; 4102 struct sockaddr *addr = p; 4103 4104 if (!is_valid_ether_addr(addr->sa_data)) 4105 return -EADDRNOTAVAIL; 4106 4107 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4108 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4109 4110 /* set the correct pool for the new PF MAC address in entry 0 */ 4111 igb_set_default_mac_filter(adapter); 4112 4113 return 0; 4114 } 4115 4116 /** 4117 * igb_write_mc_addr_list - write multicast addresses to MTA 4118 * @netdev: network interface device structure 4119 * 4120 * Writes multicast address list to the MTA hash table. 4121 * Returns: -ENOMEM on failure 4122 * 0 on no addresses written 4123 * X on writing X addresses to MTA 4124 **/ 4125 static int igb_write_mc_addr_list(struct net_device *netdev) 4126 { 4127 struct igb_adapter *adapter = netdev_priv(netdev); 4128 struct e1000_hw *hw = &adapter->hw; 4129 struct netdev_hw_addr *ha; 4130 u8 *mta_list; 4131 int i; 4132 4133 if (netdev_mc_empty(netdev)) { 4134 /* nothing to program, so clear mc list */ 4135 igb_update_mc_addr_list(hw, NULL, 0); 4136 igb_restore_vf_multicasts(adapter); 4137 return 0; 4138 } 4139 4140 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 4141 if (!mta_list) 4142 return -ENOMEM; 4143 4144 /* The shared function expects a packed array of only addresses. */ 4145 i = 0; 4146 netdev_for_each_mc_addr(ha, netdev) 4147 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 4148 4149 igb_update_mc_addr_list(hw, mta_list, i); 4150 kfree(mta_list); 4151 4152 return netdev_mc_count(netdev); 4153 } 4154 4155 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 4156 { 4157 struct e1000_hw *hw = &adapter->hw; 4158 u32 i, pf_id; 4159 4160 switch (hw->mac.type) { 4161 case e1000_i210: 4162 case e1000_i211: 4163 case e1000_i350: 4164 /* VLAN filtering needed for VLAN prio filter */ 4165 if (adapter->netdev->features & NETIF_F_NTUPLE) 4166 break; 4167 /* fall through */ 4168 case e1000_82576: 4169 case e1000_82580: 4170 case e1000_i354: 4171 /* VLAN filtering needed for pool filtering */ 4172 if (adapter->vfs_allocated_count) 4173 break; 4174 /* fall through */ 4175 default: 4176 return 1; 4177 } 4178 4179 /* We are already in VLAN promisc, nothing to do */ 4180 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 4181 return 0; 4182 4183 if (!adapter->vfs_allocated_count) 4184 goto set_vfta; 4185 4186 /* Add PF to all active pools */ 4187 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4188 4189 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4190 u32 vlvf = rd32(E1000_VLVF(i)); 4191 4192 vlvf |= BIT(pf_id); 4193 wr32(E1000_VLVF(i), vlvf); 4194 } 4195 4196 set_vfta: 4197 /* Set all bits in the VLAN filter table array */ 4198 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 4199 hw->mac.ops.write_vfta(hw, i, ~0U); 4200 4201 /* Set flag so we don't redo unnecessary work */ 4202 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 4203 4204 return 0; 4205 } 4206 4207 #define VFTA_BLOCK_SIZE 8 4208 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 4209 { 4210 struct e1000_hw *hw = &adapter->hw; 4211 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4212 u32 vid_start = vfta_offset * 32; 4213 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4214 u32 i, vid, word, bits, pf_id; 4215 4216 /* guarantee that we don't scrub out management VLAN */ 4217 vid = adapter->mng_vlan_id; 4218 if (vid >= vid_start && vid < vid_end) 4219 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4220 4221 if (!adapter->vfs_allocated_count) 4222 goto set_vfta; 4223 4224 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 4225 4226 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 4227 u32 vlvf = rd32(E1000_VLVF(i)); 4228 4229 /* pull VLAN ID from VLVF */ 4230 vid = vlvf & VLAN_VID_MASK; 4231 4232 /* only concern ourselves with a certain range */ 4233 if (vid < vid_start || vid >= vid_end) 4234 continue; 4235 4236 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 4237 /* record VLAN ID in VFTA */ 4238 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4239 4240 /* if PF is part of this then continue */ 4241 if (test_bit(vid, adapter->active_vlans)) 4242 continue; 4243 } 4244 4245 /* remove PF from the pool */ 4246 bits = ~BIT(pf_id); 4247 bits &= rd32(E1000_VLVF(i)); 4248 wr32(E1000_VLVF(i), bits); 4249 } 4250 4251 set_vfta: 4252 /* extract values from active_vlans and write back to VFTA */ 4253 for (i = VFTA_BLOCK_SIZE; i--;) { 4254 vid = (vfta_offset + i) * 32; 4255 word = vid / BITS_PER_LONG; 4256 bits = vid % BITS_PER_LONG; 4257 4258 vfta[i] |= adapter->active_vlans[word] >> bits; 4259 4260 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 4261 } 4262 } 4263 4264 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 4265 { 4266 u32 i; 4267 4268 /* We are not in VLAN promisc, nothing to do */ 4269 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 4270 return; 4271 4272 /* Set flag so we don't redo unnecessary work */ 4273 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 4274 4275 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 4276 igb_scrub_vfta(adapter, i); 4277 } 4278 4279 /** 4280 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 4281 * @netdev: network interface device structure 4282 * 4283 * The set_rx_mode entry point is called whenever the unicast or multicast 4284 * address lists or the network interface flags are updated. This routine is 4285 * responsible for configuring the hardware for proper unicast, multicast, 4286 * promiscuous mode, and all-multi behavior. 4287 **/ 4288 static void igb_set_rx_mode(struct net_device *netdev) 4289 { 4290 struct igb_adapter *adapter = netdev_priv(netdev); 4291 struct e1000_hw *hw = &adapter->hw; 4292 unsigned int vfn = adapter->vfs_allocated_count; 4293 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 4294 int count; 4295 4296 /* Check for Promiscuous and All Multicast modes */ 4297 if (netdev->flags & IFF_PROMISC) { 4298 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 4299 vmolr |= E1000_VMOLR_MPME; 4300 4301 /* enable use of UTA filter to force packets to default pool */ 4302 if (hw->mac.type == e1000_82576) 4303 vmolr |= E1000_VMOLR_ROPE; 4304 } else { 4305 if (netdev->flags & IFF_ALLMULTI) { 4306 rctl |= E1000_RCTL_MPE; 4307 vmolr |= E1000_VMOLR_MPME; 4308 } else { 4309 /* Write addresses to the MTA, if the attempt fails 4310 * then we should just turn on promiscuous mode so 4311 * that we can at least receive multicast traffic 4312 */ 4313 count = igb_write_mc_addr_list(netdev); 4314 if (count < 0) { 4315 rctl |= E1000_RCTL_MPE; 4316 vmolr |= E1000_VMOLR_MPME; 4317 } else if (count) { 4318 vmolr |= E1000_VMOLR_ROMPE; 4319 } 4320 } 4321 } 4322 4323 /* Write addresses to available RAR registers, if there is not 4324 * sufficient space to store all the addresses then enable 4325 * unicast promiscuous mode 4326 */ 4327 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 4328 rctl |= E1000_RCTL_UPE; 4329 vmolr |= E1000_VMOLR_ROPE; 4330 } 4331 4332 /* enable VLAN filtering by default */ 4333 rctl |= E1000_RCTL_VFE; 4334 4335 /* disable VLAN filtering for modes that require it */ 4336 if ((netdev->flags & IFF_PROMISC) || 4337 (netdev->features & NETIF_F_RXALL)) { 4338 /* if we fail to set all rules then just clear VFE */ 4339 if (igb_vlan_promisc_enable(adapter)) 4340 rctl &= ~E1000_RCTL_VFE; 4341 } else { 4342 igb_vlan_promisc_disable(adapter); 4343 } 4344 4345 /* update state of unicast, multicast, and VLAN filtering modes */ 4346 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 4347 E1000_RCTL_VFE); 4348 wr32(E1000_RCTL, rctl); 4349 4350 #if (PAGE_SIZE < 8192) 4351 if (!adapter->vfs_allocated_count) { 4352 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4353 rlpml = IGB_MAX_FRAME_BUILD_SKB; 4354 } 4355 #endif 4356 wr32(E1000_RLPML, rlpml); 4357 4358 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4359 * the VMOLR to enable the appropriate modes. Without this workaround 4360 * we will have issues with VLAN tag stripping not being done for frames 4361 * that are only arriving because we are the default pool 4362 */ 4363 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4364 return; 4365 4366 /* set UTA to appropriate mode */ 4367 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 4368 4369 vmolr |= rd32(E1000_VMOLR(vfn)) & 4370 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4371 4372 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 4373 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4374 #if (PAGE_SIZE < 8192) 4375 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4376 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 4377 else 4378 #endif 4379 vmolr |= MAX_JUMBO_FRAME_SIZE; 4380 vmolr |= E1000_VMOLR_LPE; 4381 4382 wr32(E1000_VMOLR(vfn), vmolr); 4383 4384 igb_restore_vf_multicasts(adapter); 4385 } 4386 4387 static void igb_check_wvbr(struct igb_adapter *adapter) 4388 { 4389 struct e1000_hw *hw = &adapter->hw; 4390 u32 wvbr = 0; 4391 4392 switch (hw->mac.type) { 4393 case e1000_82576: 4394 case e1000_i350: 4395 wvbr = rd32(E1000_WVBR); 4396 if (!wvbr) 4397 return; 4398 break; 4399 default: 4400 break; 4401 } 4402 4403 adapter->wvbr |= wvbr; 4404 } 4405 4406 #define IGB_STAGGERED_QUEUE_OFFSET 8 4407 4408 static void igb_spoof_check(struct igb_adapter *adapter) 4409 { 4410 int j; 4411 4412 if (!adapter->wvbr) 4413 return; 4414 4415 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4416 if (adapter->wvbr & BIT(j) || 4417 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 4418 dev_warn(&adapter->pdev->dev, 4419 "Spoof event(s) detected on VF %d\n", j); 4420 adapter->wvbr &= 4421 ~(BIT(j) | 4422 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 4423 } 4424 } 4425 } 4426 4427 /* Need to wait a few seconds after link up to get diagnostic information from 4428 * the phy 4429 */ 4430 static void igb_update_phy_info(unsigned long data) 4431 { 4432 struct igb_adapter *adapter = (struct igb_adapter *) data; 4433 igb_get_phy_info(&adapter->hw); 4434 } 4435 4436 /** 4437 * igb_has_link - check shared code for link and determine up/down 4438 * @adapter: pointer to driver private info 4439 **/ 4440 bool igb_has_link(struct igb_adapter *adapter) 4441 { 4442 struct e1000_hw *hw = &adapter->hw; 4443 bool link_active = false; 4444 4445 /* get_link_status is set on LSC (link status) interrupt or 4446 * rx sequence error interrupt. get_link_status will stay 4447 * false until the e1000_check_for_link establishes link 4448 * for copper adapters ONLY 4449 */ 4450 switch (hw->phy.media_type) { 4451 case e1000_media_type_copper: 4452 if (!hw->mac.get_link_status) 4453 return true; 4454 case e1000_media_type_internal_serdes: 4455 hw->mac.ops.check_for_link(hw); 4456 link_active = !hw->mac.get_link_status; 4457 break; 4458 default: 4459 case e1000_media_type_unknown: 4460 break; 4461 } 4462 4463 if (((hw->mac.type == e1000_i210) || 4464 (hw->mac.type == e1000_i211)) && 4465 (hw->phy.id == I210_I_PHY_ID)) { 4466 if (!netif_carrier_ok(adapter->netdev)) { 4467 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4468 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4469 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4470 adapter->link_check_timeout = jiffies; 4471 } 4472 } 4473 4474 return link_active; 4475 } 4476 4477 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4478 { 4479 bool ret = false; 4480 u32 ctrl_ext, thstat; 4481 4482 /* check for thermal sensor event on i350 copper only */ 4483 if (hw->mac.type == e1000_i350) { 4484 thstat = rd32(E1000_THSTAT); 4485 ctrl_ext = rd32(E1000_CTRL_EXT); 4486 4487 if ((hw->phy.media_type == e1000_media_type_copper) && 4488 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4489 ret = !!(thstat & event); 4490 } 4491 4492 return ret; 4493 } 4494 4495 /** 4496 * igb_check_lvmmc - check for malformed packets received 4497 * and indicated in LVMMC register 4498 * @adapter: pointer to adapter 4499 **/ 4500 static void igb_check_lvmmc(struct igb_adapter *adapter) 4501 { 4502 struct e1000_hw *hw = &adapter->hw; 4503 u32 lvmmc; 4504 4505 lvmmc = rd32(E1000_LVMMC); 4506 if (lvmmc) { 4507 if (unlikely(net_ratelimit())) { 4508 netdev_warn(adapter->netdev, 4509 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 4510 lvmmc); 4511 } 4512 } 4513 } 4514 4515 /** 4516 * igb_watchdog - Timer Call-back 4517 * @data: pointer to adapter cast into an unsigned long 4518 **/ 4519 static void igb_watchdog(unsigned long data) 4520 { 4521 struct igb_adapter *adapter = (struct igb_adapter *)data; 4522 /* Do the rest outside of interrupt context */ 4523 schedule_work(&adapter->watchdog_task); 4524 } 4525 4526 static void igb_watchdog_task(struct work_struct *work) 4527 { 4528 struct igb_adapter *adapter = container_of(work, 4529 struct igb_adapter, 4530 watchdog_task); 4531 struct e1000_hw *hw = &adapter->hw; 4532 struct e1000_phy_info *phy = &hw->phy; 4533 struct net_device *netdev = adapter->netdev; 4534 u32 link; 4535 int i; 4536 u32 connsw; 4537 u16 phy_data, retry_count = 20; 4538 4539 link = igb_has_link(adapter); 4540 4541 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4542 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4543 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4544 else 4545 link = false; 4546 } 4547 4548 /* Force link down if we have fiber to swap to */ 4549 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4550 if (hw->phy.media_type == e1000_media_type_copper) { 4551 connsw = rd32(E1000_CONNSW); 4552 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4553 link = 0; 4554 } 4555 } 4556 if (link) { 4557 /* Perform a reset if the media type changed. */ 4558 if (hw->dev_spec._82575.media_changed) { 4559 hw->dev_spec._82575.media_changed = false; 4560 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4561 igb_reset(adapter); 4562 } 4563 /* Cancel scheduled suspend requests. */ 4564 pm_runtime_resume(netdev->dev.parent); 4565 4566 if (!netif_carrier_ok(netdev)) { 4567 u32 ctrl; 4568 4569 hw->mac.ops.get_speed_and_duplex(hw, 4570 &adapter->link_speed, 4571 &adapter->link_duplex); 4572 4573 ctrl = rd32(E1000_CTRL); 4574 /* Links status message must follow this format */ 4575 netdev_info(netdev, 4576 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4577 netdev->name, 4578 adapter->link_speed, 4579 adapter->link_duplex == FULL_DUPLEX ? 4580 "Full" : "Half", 4581 (ctrl & E1000_CTRL_TFCE) && 4582 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4583 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4584 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4585 4586 /* disable EEE if enabled */ 4587 if ((adapter->flags & IGB_FLAG_EEE) && 4588 (adapter->link_duplex == HALF_DUPLEX)) { 4589 dev_info(&adapter->pdev->dev, 4590 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4591 adapter->hw.dev_spec._82575.eee_disable = true; 4592 adapter->flags &= ~IGB_FLAG_EEE; 4593 } 4594 4595 /* check if SmartSpeed worked */ 4596 igb_check_downshift(hw); 4597 if (phy->speed_downgraded) 4598 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4599 4600 /* check for thermal sensor event */ 4601 if (igb_thermal_sensor_event(hw, 4602 E1000_THSTAT_LINK_THROTTLE)) 4603 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4604 4605 /* adjust timeout factor according to speed/duplex */ 4606 adapter->tx_timeout_factor = 1; 4607 switch (adapter->link_speed) { 4608 case SPEED_10: 4609 adapter->tx_timeout_factor = 14; 4610 break; 4611 case SPEED_100: 4612 /* maybe add some timeout factor ? */ 4613 break; 4614 } 4615 4616 if (adapter->link_speed != SPEED_1000) 4617 goto no_wait; 4618 4619 /* wait for Remote receiver status OK */ 4620 retry_read_status: 4621 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 4622 &phy_data)) { 4623 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 4624 retry_count) { 4625 msleep(100); 4626 retry_count--; 4627 goto retry_read_status; 4628 } else if (!retry_count) { 4629 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 4630 } 4631 } else { 4632 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 4633 } 4634 no_wait: 4635 netif_carrier_on(netdev); 4636 4637 igb_ping_all_vfs(adapter); 4638 igb_check_vf_rate_limit(adapter); 4639 4640 /* link state has changed, schedule phy info update */ 4641 if (!test_bit(__IGB_DOWN, &adapter->state)) 4642 mod_timer(&adapter->phy_info_timer, 4643 round_jiffies(jiffies + 2 * HZ)); 4644 } 4645 } else { 4646 if (netif_carrier_ok(netdev)) { 4647 adapter->link_speed = 0; 4648 adapter->link_duplex = 0; 4649 4650 /* check for thermal sensor event */ 4651 if (igb_thermal_sensor_event(hw, 4652 E1000_THSTAT_PWR_DOWN)) { 4653 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4654 } 4655 4656 /* Links status message must follow this format */ 4657 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4658 netdev->name); 4659 netif_carrier_off(netdev); 4660 4661 igb_ping_all_vfs(adapter); 4662 4663 /* link state has changed, schedule phy info update */ 4664 if (!test_bit(__IGB_DOWN, &adapter->state)) 4665 mod_timer(&adapter->phy_info_timer, 4666 round_jiffies(jiffies + 2 * HZ)); 4667 4668 /* link is down, time to check for alternate media */ 4669 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4670 igb_check_swap_media(adapter); 4671 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4672 schedule_work(&adapter->reset_task); 4673 /* return immediately */ 4674 return; 4675 } 4676 } 4677 pm_schedule_suspend(netdev->dev.parent, 4678 MSEC_PER_SEC * 5); 4679 4680 /* also check for alternate media here */ 4681 } else if (!netif_carrier_ok(netdev) && 4682 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4683 igb_check_swap_media(adapter); 4684 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4685 schedule_work(&adapter->reset_task); 4686 /* return immediately */ 4687 return; 4688 } 4689 } 4690 } 4691 4692 spin_lock(&adapter->stats64_lock); 4693 igb_update_stats(adapter, &adapter->stats64); 4694 spin_unlock(&adapter->stats64_lock); 4695 4696 for (i = 0; i < adapter->num_tx_queues; i++) { 4697 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4698 if (!netif_carrier_ok(netdev)) { 4699 /* We've lost link, so the controller stops DMA, 4700 * but we've got queued Tx work that's never going 4701 * to get done, so reset controller to flush Tx. 4702 * (Do the reset outside of interrupt context). 4703 */ 4704 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4705 adapter->tx_timeout_count++; 4706 schedule_work(&adapter->reset_task); 4707 /* return immediately since reset is imminent */ 4708 return; 4709 } 4710 } 4711 4712 /* Force detection of hung controller every watchdog period */ 4713 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4714 } 4715 4716 /* Cause software interrupt to ensure Rx ring is cleaned */ 4717 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4718 u32 eics = 0; 4719 4720 for (i = 0; i < adapter->num_q_vectors; i++) 4721 eics |= adapter->q_vector[i]->eims_value; 4722 wr32(E1000_EICS, eics); 4723 } else { 4724 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4725 } 4726 4727 igb_spoof_check(adapter); 4728 igb_ptp_rx_hang(adapter); 4729 4730 /* Check LVMMC register on i350/i354 only */ 4731 if ((adapter->hw.mac.type == e1000_i350) || 4732 (adapter->hw.mac.type == e1000_i354)) 4733 igb_check_lvmmc(adapter); 4734 4735 /* Reset the timer */ 4736 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4737 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4738 mod_timer(&adapter->watchdog_timer, 4739 round_jiffies(jiffies + HZ)); 4740 else 4741 mod_timer(&adapter->watchdog_timer, 4742 round_jiffies(jiffies + 2 * HZ)); 4743 } 4744 } 4745 4746 enum latency_range { 4747 lowest_latency = 0, 4748 low_latency = 1, 4749 bulk_latency = 2, 4750 latency_invalid = 255 4751 }; 4752 4753 /** 4754 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4755 * @q_vector: pointer to q_vector 4756 * 4757 * Stores a new ITR value based on strictly on packet size. This 4758 * algorithm is less sophisticated than that used in igb_update_itr, 4759 * due to the difficulty of synchronizing statistics across multiple 4760 * receive rings. The divisors and thresholds used by this function 4761 * were determined based on theoretical maximum wire speed and testing 4762 * data, in order to minimize response time while increasing bulk 4763 * throughput. 4764 * This functionality is controlled by ethtool's coalescing settings. 4765 * NOTE: This function is called only when operating in a multiqueue 4766 * receive environment. 4767 **/ 4768 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4769 { 4770 int new_val = q_vector->itr_val; 4771 int avg_wire_size = 0; 4772 struct igb_adapter *adapter = q_vector->adapter; 4773 unsigned int packets; 4774 4775 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4776 * ints/sec - ITR timer value of 120 ticks. 4777 */ 4778 if (adapter->link_speed != SPEED_1000) { 4779 new_val = IGB_4K_ITR; 4780 goto set_itr_val; 4781 } 4782 4783 packets = q_vector->rx.total_packets; 4784 if (packets) 4785 avg_wire_size = q_vector->rx.total_bytes / packets; 4786 4787 packets = q_vector->tx.total_packets; 4788 if (packets) 4789 avg_wire_size = max_t(u32, avg_wire_size, 4790 q_vector->tx.total_bytes / packets); 4791 4792 /* if avg_wire_size isn't set no work was done */ 4793 if (!avg_wire_size) 4794 goto clear_counts; 4795 4796 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4797 avg_wire_size += 24; 4798 4799 /* Don't starve jumbo frames */ 4800 avg_wire_size = min(avg_wire_size, 3000); 4801 4802 /* Give a little boost to mid-size frames */ 4803 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4804 new_val = avg_wire_size / 3; 4805 else 4806 new_val = avg_wire_size / 2; 4807 4808 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4809 if (new_val < IGB_20K_ITR && 4810 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4811 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4812 new_val = IGB_20K_ITR; 4813 4814 set_itr_val: 4815 if (new_val != q_vector->itr_val) { 4816 q_vector->itr_val = new_val; 4817 q_vector->set_itr = 1; 4818 } 4819 clear_counts: 4820 q_vector->rx.total_bytes = 0; 4821 q_vector->rx.total_packets = 0; 4822 q_vector->tx.total_bytes = 0; 4823 q_vector->tx.total_packets = 0; 4824 } 4825 4826 /** 4827 * igb_update_itr - update the dynamic ITR value based on statistics 4828 * @q_vector: pointer to q_vector 4829 * @ring_container: ring info to update the itr for 4830 * 4831 * Stores a new ITR value based on packets and byte 4832 * counts during the last interrupt. The advantage of per interrupt 4833 * computation is faster updates and more accurate ITR for the current 4834 * traffic pattern. Constants in this function were computed 4835 * based on theoretical maximum wire speed and thresholds were set based 4836 * on testing data as well as attempting to minimize response time 4837 * while increasing bulk throughput. 4838 * This functionality is controlled by ethtool's coalescing settings. 4839 * NOTE: These calculations are only valid when operating in a single- 4840 * queue environment. 4841 **/ 4842 static void igb_update_itr(struct igb_q_vector *q_vector, 4843 struct igb_ring_container *ring_container) 4844 { 4845 unsigned int packets = ring_container->total_packets; 4846 unsigned int bytes = ring_container->total_bytes; 4847 u8 itrval = ring_container->itr; 4848 4849 /* no packets, exit with status unchanged */ 4850 if (packets == 0) 4851 return; 4852 4853 switch (itrval) { 4854 case lowest_latency: 4855 /* handle TSO and jumbo frames */ 4856 if (bytes/packets > 8000) 4857 itrval = bulk_latency; 4858 else if ((packets < 5) && (bytes > 512)) 4859 itrval = low_latency; 4860 break; 4861 case low_latency: /* 50 usec aka 20000 ints/s */ 4862 if (bytes > 10000) { 4863 /* this if handles the TSO accounting */ 4864 if (bytes/packets > 8000) 4865 itrval = bulk_latency; 4866 else if ((packets < 10) || ((bytes/packets) > 1200)) 4867 itrval = bulk_latency; 4868 else if ((packets > 35)) 4869 itrval = lowest_latency; 4870 } else if (bytes/packets > 2000) { 4871 itrval = bulk_latency; 4872 } else if (packets <= 2 && bytes < 512) { 4873 itrval = lowest_latency; 4874 } 4875 break; 4876 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4877 if (bytes > 25000) { 4878 if (packets > 35) 4879 itrval = low_latency; 4880 } else if (bytes < 1500) { 4881 itrval = low_latency; 4882 } 4883 break; 4884 } 4885 4886 /* clear work counters since we have the values we need */ 4887 ring_container->total_bytes = 0; 4888 ring_container->total_packets = 0; 4889 4890 /* write updated itr to ring container */ 4891 ring_container->itr = itrval; 4892 } 4893 4894 static void igb_set_itr(struct igb_q_vector *q_vector) 4895 { 4896 struct igb_adapter *adapter = q_vector->adapter; 4897 u32 new_itr = q_vector->itr_val; 4898 u8 current_itr = 0; 4899 4900 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4901 if (adapter->link_speed != SPEED_1000) { 4902 current_itr = 0; 4903 new_itr = IGB_4K_ITR; 4904 goto set_itr_now; 4905 } 4906 4907 igb_update_itr(q_vector, &q_vector->tx); 4908 igb_update_itr(q_vector, &q_vector->rx); 4909 4910 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4911 4912 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4913 if (current_itr == lowest_latency && 4914 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4915 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4916 current_itr = low_latency; 4917 4918 switch (current_itr) { 4919 /* counts and packets in update_itr are dependent on these numbers */ 4920 case lowest_latency: 4921 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4922 break; 4923 case low_latency: 4924 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4925 break; 4926 case bulk_latency: 4927 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4928 break; 4929 default: 4930 break; 4931 } 4932 4933 set_itr_now: 4934 if (new_itr != q_vector->itr_val) { 4935 /* this attempts to bias the interrupt rate towards Bulk 4936 * by adding intermediate steps when interrupt rate is 4937 * increasing 4938 */ 4939 new_itr = new_itr > q_vector->itr_val ? 4940 max((new_itr * q_vector->itr_val) / 4941 (new_itr + (q_vector->itr_val >> 2)), 4942 new_itr) : new_itr; 4943 /* Don't write the value here; it resets the adapter's 4944 * internal timer, and causes us to delay far longer than 4945 * we should between interrupts. Instead, we write the ITR 4946 * value at the beginning of the next interrupt so the timing 4947 * ends up being correct. 4948 */ 4949 q_vector->itr_val = new_itr; 4950 q_vector->set_itr = 1; 4951 } 4952 } 4953 4954 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4955 u32 type_tucmd, u32 mss_l4len_idx) 4956 { 4957 struct e1000_adv_tx_context_desc *context_desc; 4958 u16 i = tx_ring->next_to_use; 4959 4960 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4961 4962 i++; 4963 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4964 4965 /* set bits to identify this as an advanced context descriptor */ 4966 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4967 4968 /* For 82575, context index must be unique per ring. */ 4969 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4970 mss_l4len_idx |= tx_ring->reg_idx << 4; 4971 4972 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4973 context_desc->seqnum_seed = 0; 4974 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4975 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4976 } 4977 4978 static int igb_tso(struct igb_ring *tx_ring, 4979 struct igb_tx_buffer *first, 4980 u8 *hdr_len) 4981 { 4982 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 4983 struct sk_buff *skb = first->skb; 4984 union { 4985 struct iphdr *v4; 4986 struct ipv6hdr *v6; 4987 unsigned char *hdr; 4988 } ip; 4989 union { 4990 struct tcphdr *tcp; 4991 unsigned char *hdr; 4992 } l4; 4993 u32 paylen, l4_offset; 4994 int err; 4995 4996 if (skb->ip_summed != CHECKSUM_PARTIAL) 4997 return 0; 4998 4999 if (!skb_is_gso(skb)) 5000 return 0; 5001 5002 err = skb_cow_head(skb, 0); 5003 if (err < 0) 5004 return err; 5005 5006 ip.hdr = skb_network_header(skb); 5007 l4.hdr = skb_checksum_start(skb); 5008 5009 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5010 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5011 5012 /* initialize outer IP header fields */ 5013 if (ip.v4->version == 4) { 5014 unsigned char *csum_start = skb_checksum_start(skb); 5015 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5016 5017 /* IP header will have to cancel out any data that 5018 * is not a part of the outer IP header 5019 */ 5020 ip.v4->check = csum_fold(csum_partial(trans_start, 5021 csum_start - trans_start, 5022 0)); 5023 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5024 5025 ip.v4->tot_len = 0; 5026 first->tx_flags |= IGB_TX_FLAGS_TSO | 5027 IGB_TX_FLAGS_CSUM | 5028 IGB_TX_FLAGS_IPV4; 5029 } else { 5030 ip.v6->payload_len = 0; 5031 first->tx_flags |= IGB_TX_FLAGS_TSO | 5032 IGB_TX_FLAGS_CSUM; 5033 } 5034 5035 /* determine offset of inner transport header */ 5036 l4_offset = l4.hdr - skb->data; 5037 5038 /* compute length of segmentation header */ 5039 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5040 5041 /* remove payload length from inner checksum */ 5042 paylen = skb->len - l4_offset; 5043 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 5044 5045 /* update gso size and bytecount with header size */ 5046 first->gso_segs = skb_shinfo(skb)->gso_segs; 5047 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5048 5049 /* MSS L4LEN IDX */ 5050 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5051 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5052 5053 /* VLAN MACLEN IPLEN */ 5054 vlan_macip_lens = l4.hdr - ip.hdr; 5055 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5056 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5057 5058 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5059 5060 return 1; 5061 } 5062 5063 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5064 { 5065 unsigned int offset = 0; 5066 5067 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5068 5069 return offset == skb_checksum_start_offset(skb); 5070 } 5071 5072 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5073 { 5074 struct sk_buff *skb = first->skb; 5075 u32 vlan_macip_lens = 0; 5076 u32 type_tucmd = 0; 5077 5078 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5079 csum_failed: 5080 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 5081 return; 5082 goto no_csum; 5083 } 5084 5085 switch (skb->csum_offset) { 5086 case offsetof(struct tcphdr, check): 5087 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5088 /* fall through */ 5089 case offsetof(struct udphdr, check): 5090 break; 5091 case offsetof(struct sctphdr, checksum): 5092 /* validate that this is actually an SCTP request */ 5093 if (((first->protocol == htons(ETH_P_IP)) && 5094 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5095 ((first->protocol == htons(ETH_P_IPV6)) && 5096 igb_ipv6_csum_is_sctp(skb))) { 5097 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5098 break; 5099 } 5100 default: 5101 skb_checksum_help(skb); 5102 goto csum_failed; 5103 } 5104 5105 /* update TX checksum flag */ 5106 first->tx_flags |= IGB_TX_FLAGS_CSUM; 5107 vlan_macip_lens = skb_checksum_start_offset(skb) - 5108 skb_network_offset(skb); 5109 no_csum: 5110 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5111 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5112 5113 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5114 } 5115 5116 #define IGB_SET_FLAG(_input, _flag, _result) \ 5117 ((_flag <= _result) ? \ 5118 ((u32)(_input & _flag) * (_result / _flag)) : \ 5119 ((u32)(_input & _flag) / (_flag / _result))) 5120 5121 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 5122 { 5123 /* set type for advanced descriptor with frame checksum insertion */ 5124 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 5125 E1000_ADVTXD_DCMD_DEXT | 5126 E1000_ADVTXD_DCMD_IFCS; 5127 5128 /* set HW vlan bit if vlan is present */ 5129 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 5130 (E1000_ADVTXD_DCMD_VLE)); 5131 5132 /* set segmentation bits for TSO */ 5133 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 5134 (E1000_ADVTXD_DCMD_TSE)); 5135 5136 /* set timestamp bit if present */ 5137 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 5138 (E1000_ADVTXD_MAC_TSTAMP)); 5139 5140 /* insert frame checksum */ 5141 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 5142 5143 return cmd_type; 5144 } 5145 5146 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 5147 union e1000_adv_tx_desc *tx_desc, 5148 u32 tx_flags, unsigned int paylen) 5149 { 5150 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 5151 5152 /* 82575 requires a unique index per ring */ 5153 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5154 olinfo_status |= tx_ring->reg_idx << 4; 5155 5156 /* insert L4 checksum */ 5157 olinfo_status |= IGB_SET_FLAG(tx_flags, 5158 IGB_TX_FLAGS_CSUM, 5159 (E1000_TXD_POPTS_TXSM << 8)); 5160 5161 /* insert IPv4 checksum */ 5162 olinfo_status |= IGB_SET_FLAG(tx_flags, 5163 IGB_TX_FLAGS_IPV4, 5164 (E1000_TXD_POPTS_IXSM << 8)); 5165 5166 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 5167 } 5168 5169 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5170 { 5171 struct net_device *netdev = tx_ring->netdev; 5172 5173 netif_stop_subqueue(netdev, tx_ring->queue_index); 5174 5175 /* Herbert's original patch had: 5176 * smp_mb__after_netif_stop_queue(); 5177 * but since that doesn't exist yet, just open code it. 5178 */ 5179 smp_mb(); 5180 5181 /* We need to check again in a case another CPU has just 5182 * made room available. 5183 */ 5184 if (igb_desc_unused(tx_ring) < size) 5185 return -EBUSY; 5186 5187 /* A reprieve! */ 5188 netif_wake_subqueue(netdev, tx_ring->queue_index); 5189 5190 u64_stats_update_begin(&tx_ring->tx_syncp2); 5191 tx_ring->tx_stats.restart_queue2++; 5192 u64_stats_update_end(&tx_ring->tx_syncp2); 5193 5194 return 0; 5195 } 5196 5197 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 5198 { 5199 if (igb_desc_unused(tx_ring) >= size) 5200 return 0; 5201 return __igb_maybe_stop_tx(tx_ring, size); 5202 } 5203 5204 static void igb_tx_map(struct igb_ring *tx_ring, 5205 struct igb_tx_buffer *first, 5206 const u8 hdr_len) 5207 { 5208 struct sk_buff *skb = first->skb; 5209 struct igb_tx_buffer *tx_buffer; 5210 union e1000_adv_tx_desc *tx_desc; 5211 struct skb_frag_struct *frag; 5212 dma_addr_t dma; 5213 unsigned int data_len, size; 5214 u32 tx_flags = first->tx_flags; 5215 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 5216 u16 i = tx_ring->next_to_use; 5217 5218 tx_desc = IGB_TX_DESC(tx_ring, i); 5219 5220 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 5221 5222 size = skb_headlen(skb); 5223 data_len = skb->data_len; 5224 5225 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 5226 5227 tx_buffer = first; 5228 5229 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 5230 if (dma_mapping_error(tx_ring->dev, dma)) 5231 goto dma_error; 5232 5233 /* record length, and DMA address */ 5234 dma_unmap_len_set(tx_buffer, len, size); 5235 dma_unmap_addr_set(tx_buffer, dma, dma); 5236 5237 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5238 5239 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 5240 tx_desc->read.cmd_type_len = 5241 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 5242 5243 i++; 5244 tx_desc++; 5245 if (i == tx_ring->count) { 5246 tx_desc = IGB_TX_DESC(tx_ring, 0); 5247 i = 0; 5248 } 5249 tx_desc->read.olinfo_status = 0; 5250 5251 dma += IGB_MAX_DATA_PER_TXD; 5252 size -= IGB_MAX_DATA_PER_TXD; 5253 5254 tx_desc->read.buffer_addr = cpu_to_le64(dma); 5255 } 5256 5257 if (likely(!data_len)) 5258 break; 5259 5260 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 5261 5262 i++; 5263 tx_desc++; 5264 if (i == tx_ring->count) { 5265 tx_desc = IGB_TX_DESC(tx_ring, 0); 5266 i = 0; 5267 } 5268 tx_desc->read.olinfo_status = 0; 5269 5270 size = skb_frag_size(frag); 5271 data_len -= size; 5272 5273 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 5274 size, DMA_TO_DEVICE); 5275 5276 tx_buffer = &tx_ring->tx_buffer_info[i]; 5277 } 5278 5279 /* write last descriptor with RS and EOP bits */ 5280 cmd_type |= size | IGB_TXD_DCMD; 5281 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 5282 5283 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 5284 5285 /* set the timestamp */ 5286 first->time_stamp = jiffies; 5287 5288 /* Force memory writes to complete before letting h/w know there 5289 * are new descriptors to fetch. (Only applicable for weak-ordered 5290 * memory model archs, such as IA-64). 5291 * 5292 * We also need this memory barrier to make certain all of the 5293 * status bits have been updated before next_to_watch is written. 5294 */ 5295 wmb(); 5296 5297 /* set next_to_watch value indicating a packet is present */ 5298 first->next_to_watch = tx_desc; 5299 5300 i++; 5301 if (i == tx_ring->count) 5302 i = 0; 5303 5304 tx_ring->next_to_use = i; 5305 5306 /* Make sure there is space in the ring for the next send. */ 5307 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5308 5309 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 5310 writel(i, tx_ring->tail); 5311 5312 /* we need this if more than one processor can write to our tail 5313 * at a time, it synchronizes IO on IA64/Altix systems 5314 */ 5315 mmiowb(); 5316 } 5317 return; 5318 5319 dma_error: 5320 dev_err(tx_ring->dev, "TX DMA map failed\n"); 5321 tx_buffer = &tx_ring->tx_buffer_info[i]; 5322 5323 /* clear dma mappings for failed tx_buffer_info map */ 5324 while (tx_buffer != first) { 5325 if (dma_unmap_len(tx_buffer, len)) 5326 dma_unmap_page(tx_ring->dev, 5327 dma_unmap_addr(tx_buffer, dma), 5328 dma_unmap_len(tx_buffer, len), 5329 DMA_TO_DEVICE); 5330 dma_unmap_len_set(tx_buffer, len, 0); 5331 5332 if (i--) 5333 i += tx_ring->count; 5334 tx_buffer = &tx_ring->tx_buffer_info[i]; 5335 } 5336 5337 if (dma_unmap_len(tx_buffer, len)) 5338 dma_unmap_single(tx_ring->dev, 5339 dma_unmap_addr(tx_buffer, dma), 5340 dma_unmap_len(tx_buffer, len), 5341 DMA_TO_DEVICE); 5342 dma_unmap_len_set(tx_buffer, len, 0); 5343 5344 dev_kfree_skb_any(tx_buffer->skb); 5345 tx_buffer->skb = NULL; 5346 5347 tx_ring->next_to_use = i; 5348 } 5349 5350 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 5351 struct igb_ring *tx_ring) 5352 { 5353 struct igb_tx_buffer *first; 5354 int tso; 5355 u32 tx_flags = 0; 5356 unsigned short f; 5357 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 5358 __be16 protocol = vlan_get_protocol(skb); 5359 u8 hdr_len = 0; 5360 5361 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 5362 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 5363 * + 2 desc gap to keep tail from touching head, 5364 * + 1 desc for context descriptor, 5365 * otherwise try next time 5366 */ 5367 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 5368 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 5369 5370 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 5371 /* this is a hard error */ 5372 return NETDEV_TX_BUSY; 5373 } 5374 5375 /* record the location of the first descriptor for this packet */ 5376 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 5377 first->skb = skb; 5378 first->bytecount = skb->len; 5379 first->gso_segs = 1; 5380 5381 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5382 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 5383 5384 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 5385 &adapter->state)) { 5386 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5387 tx_flags |= IGB_TX_FLAGS_TSTAMP; 5388 5389 adapter->ptp_tx_skb = skb_get(skb); 5390 adapter->ptp_tx_start = jiffies; 5391 if (adapter->hw.mac.type == e1000_82576) 5392 schedule_work(&adapter->ptp_tx_work); 5393 } 5394 } 5395 5396 skb_tx_timestamp(skb); 5397 5398 if (skb_vlan_tag_present(skb)) { 5399 tx_flags |= IGB_TX_FLAGS_VLAN; 5400 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5401 } 5402 5403 /* record initial flags and protocol */ 5404 first->tx_flags = tx_flags; 5405 first->protocol = protocol; 5406 5407 tso = igb_tso(tx_ring, first, &hdr_len); 5408 if (tso < 0) 5409 goto out_drop; 5410 else if (!tso) 5411 igb_tx_csum(tx_ring, first); 5412 5413 igb_tx_map(tx_ring, first, hdr_len); 5414 5415 return NETDEV_TX_OK; 5416 5417 out_drop: 5418 dev_kfree_skb_any(first->skb); 5419 first->skb = NULL; 5420 5421 return NETDEV_TX_OK; 5422 } 5423 5424 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5425 struct sk_buff *skb) 5426 { 5427 unsigned int r_idx = skb->queue_mapping; 5428 5429 if (r_idx >= adapter->num_tx_queues) 5430 r_idx = r_idx % adapter->num_tx_queues; 5431 5432 return adapter->tx_ring[r_idx]; 5433 } 5434 5435 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5436 struct net_device *netdev) 5437 { 5438 struct igb_adapter *adapter = netdev_priv(netdev); 5439 5440 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5441 * in order to meet this minimum size requirement. 5442 */ 5443 if (skb_put_padto(skb, 17)) 5444 return NETDEV_TX_OK; 5445 5446 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5447 } 5448 5449 /** 5450 * igb_tx_timeout - Respond to a Tx Hang 5451 * @netdev: network interface device structure 5452 **/ 5453 static void igb_tx_timeout(struct net_device *netdev) 5454 { 5455 struct igb_adapter *adapter = netdev_priv(netdev); 5456 struct e1000_hw *hw = &adapter->hw; 5457 5458 /* Do the reset outside of interrupt context */ 5459 adapter->tx_timeout_count++; 5460 5461 if (hw->mac.type >= e1000_82580) 5462 hw->dev_spec._82575.global_device_reset = true; 5463 5464 schedule_work(&adapter->reset_task); 5465 wr32(E1000_EICS, 5466 (adapter->eims_enable_mask & ~adapter->eims_other)); 5467 } 5468 5469 static void igb_reset_task(struct work_struct *work) 5470 { 5471 struct igb_adapter *adapter; 5472 adapter = container_of(work, struct igb_adapter, reset_task); 5473 5474 igb_dump(adapter); 5475 netdev_err(adapter->netdev, "Reset adapter\n"); 5476 igb_reinit_locked(adapter); 5477 } 5478 5479 /** 5480 * igb_get_stats64 - Get System Network Statistics 5481 * @netdev: network interface device structure 5482 * @stats: rtnl_link_stats64 pointer 5483 **/ 5484 static void igb_get_stats64(struct net_device *netdev, 5485 struct rtnl_link_stats64 *stats) 5486 { 5487 struct igb_adapter *adapter = netdev_priv(netdev); 5488 5489 spin_lock(&adapter->stats64_lock); 5490 igb_update_stats(adapter, &adapter->stats64); 5491 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5492 spin_unlock(&adapter->stats64_lock); 5493 } 5494 5495 /** 5496 * igb_change_mtu - Change the Maximum Transfer Unit 5497 * @netdev: network interface device structure 5498 * @new_mtu: new value for maximum frame size 5499 * 5500 * Returns 0 on success, negative on failure 5501 **/ 5502 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5503 { 5504 struct igb_adapter *adapter = netdev_priv(netdev); 5505 struct pci_dev *pdev = adapter->pdev; 5506 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5507 5508 /* adjust max frame to be at least the size of a standard frame */ 5509 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5510 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5511 5512 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5513 usleep_range(1000, 2000); 5514 5515 /* igb_down has a dependency on max_frame_size */ 5516 adapter->max_frame_size = max_frame; 5517 5518 if (netif_running(netdev)) 5519 igb_down(adapter); 5520 5521 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5522 netdev->mtu, new_mtu); 5523 netdev->mtu = new_mtu; 5524 5525 if (netif_running(netdev)) 5526 igb_up(adapter); 5527 else 5528 igb_reset(adapter); 5529 5530 clear_bit(__IGB_RESETTING, &adapter->state); 5531 5532 return 0; 5533 } 5534 5535 /** 5536 * igb_update_stats - Update the board statistics counters 5537 * @adapter: board private structure 5538 **/ 5539 void igb_update_stats(struct igb_adapter *adapter, 5540 struct rtnl_link_stats64 *net_stats) 5541 { 5542 struct e1000_hw *hw = &adapter->hw; 5543 struct pci_dev *pdev = adapter->pdev; 5544 u32 reg, mpc; 5545 int i; 5546 u64 bytes, packets; 5547 unsigned int start; 5548 u64 _bytes, _packets; 5549 5550 /* Prevent stats update while adapter is being reset, or if the pci 5551 * connection is down. 5552 */ 5553 if (adapter->link_speed == 0) 5554 return; 5555 if (pci_channel_offline(pdev)) 5556 return; 5557 5558 bytes = 0; 5559 packets = 0; 5560 5561 rcu_read_lock(); 5562 for (i = 0; i < adapter->num_rx_queues; i++) { 5563 struct igb_ring *ring = adapter->rx_ring[i]; 5564 u32 rqdpc = rd32(E1000_RQDPC(i)); 5565 if (hw->mac.type >= e1000_i210) 5566 wr32(E1000_RQDPC(i), 0); 5567 5568 if (rqdpc) { 5569 ring->rx_stats.drops += rqdpc; 5570 net_stats->rx_fifo_errors += rqdpc; 5571 } 5572 5573 do { 5574 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5575 _bytes = ring->rx_stats.bytes; 5576 _packets = ring->rx_stats.packets; 5577 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5578 bytes += _bytes; 5579 packets += _packets; 5580 } 5581 5582 net_stats->rx_bytes = bytes; 5583 net_stats->rx_packets = packets; 5584 5585 bytes = 0; 5586 packets = 0; 5587 for (i = 0; i < adapter->num_tx_queues; i++) { 5588 struct igb_ring *ring = adapter->tx_ring[i]; 5589 do { 5590 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5591 _bytes = ring->tx_stats.bytes; 5592 _packets = ring->tx_stats.packets; 5593 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5594 bytes += _bytes; 5595 packets += _packets; 5596 } 5597 net_stats->tx_bytes = bytes; 5598 net_stats->tx_packets = packets; 5599 rcu_read_unlock(); 5600 5601 /* read stats registers */ 5602 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5603 adapter->stats.gprc += rd32(E1000_GPRC); 5604 adapter->stats.gorc += rd32(E1000_GORCL); 5605 rd32(E1000_GORCH); /* clear GORCL */ 5606 adapter->stats.bprc += rd32(E1000_BPRC); 5607 adapter->stats.mprc += rd32(E1000_MPRC); 5608 adapter->stats.roc += rd32(E1000_ROC); 5609 5610 adapter->stats.prc64 += rd32(E1000_PRC64); 5611 adapter->stats.prc127 += rd32(E1000_PRC127); 5612 adapter->stats.prc255 += rd32(E1000_PRC255); 5613 adapter->stats.prc511 += rd32(E1000_PRC511); 5614 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5615 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5616 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5617 adapter->stats.sec += rd32(E1000_SEC); 5618 5619 mpc = rd32(E1000_MPC); 5620 adapter->stats.mpc += mpc; 5621 net_stats->rx_fifo_errors += mpc; 5622 adapter->stats.scc += rd32(E1000_SCC); 5623 adapter->stats.ecol += rd32(E1000_ECOL); 5624 adapter->stats.mcc += rd32(E1000_MCC); 5625 adapter->stats.latecol += rd32(E1000_LATECOL); 5626 adapter->stats.dc += rd32(E1000_DC); 5627 adapter->stats.rlec += rd32(E1000_RLEC); 5628 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5629 adapter->stats.xontxc += rd32(E1000_XONTXC); 5630 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5631 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5632 adapter->stats.fcruc += rd32(E1000_FCRUC); 5633 adapter->stats.gptc += rd32(E1000_GPTC); 5634 adapter->stats.gotc += rd32(E1000_GOTCL); 5635 rd32(E1000_GOTCH); /* clear GOTCL */ 5636 adapter->stats.rnbc += rd32(E1000_RNBC); 5637 adapter->stats.ruc += rd32(E1000_RUC); 5638 adapter->stats.rfc += rd32(E1000_RFC); 5639 adapter->stats.rjc += rd32(E1000_RJC); 5640 adapter->stats.tor += rd32(E1000_TORH); 5641 adapter->stats.tot += rd32(E1000_TOTH); 5642 adapter->stats.tpr += rd32(E1000_TPR); 5643 5644 adapter->stats.ptc64 += rd32(E1000_PTC64); 5645 adapter->stats.ptc127 += rd32(E1000_PTC127); 5646 adapter->stats.ptc255 += rd32(E1000_PTC255); 5647 adapter->stats.ptc511 += rd32(E1000_PTC511); 5648 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5649 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5650 5651 adapter->stats.mptc += rd32(E1000_MPTC); 5652 adapter->stats.bptc += rd32(E1000_BPTC); 5653 5654 adapter->stats.tpt += rd32(E1000_TPT); 5655 adapter->stats.colc += rd32(E1000_COLC); 5656 5657 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5658 /* read internal phy specific stats */ 5659 reg = rd32(E1000_CTRL_EXT); 5660 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5661 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5662 5663 /* this stat has invalid values on i210/i211 */ 5664 if ((hw->mac.type != e1000_i210) && 5665 (hw->mac.type != e1000_i211)) 5666 adapter->stats.tncrs += rd32(E1000_TNCRS); 5667 } 5668 5669 adapter->stats.tsctc += rd32(E1000_TSCTC); 5670 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5671 5672 adapter->stats.iac += rd32(E1000_IAC); 5673 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5674 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5675 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5676 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5677 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5678 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5679 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5680 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5681 5682 /* Fill out the OS statistics structure */ 5683 net_stats->multicast = adapter->stats.mprc; 5684 net_stats->collisions = adapter->stats.colc; 5685 5686 /* Rx Errors */ 5687 5688 /* RLEC on some newer hardware can be incorrect so build 5689 * our own version based on RUC and ROC 5690 */ 5691 net_stats->rx_errors = adapter->stats.rxerrc + 5692 adapter->stats.crcerrs + adapter->stats.algnerrc + 5693 adapter->stats.ruc + adapter->stats.roc + 5694 adapter->stats.cexterr; 5695 net_stats->rx_length_errors = adapter->stats.ruc + 5696 adapter->stats.roc; 5697 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5698 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5699 net_stats->rx_missed_errors = adapter->stats.mpc; 5700 5701 /* Tx Errors */ 5702 net_stats->tx_errors = adapter->stats.ecol + 5703 adapter->stats.latecol; 5704 net_stats->tx_aborted_errors = adapter->stats.ecol; 5705 net_stats->tx_window_errors = adapter->stats.latecol; 5706 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5707 5708 /* Tx Dropped needs to be maintained elsewhere */ 5709 5710 /* Management Stats */ 5711 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5712 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5713 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5714 5715 /* OS2BMC Stats */ 5716 reg = rd32(E1000_MANC); 5717 if (reg & E1000_MANC_EN_BMC2OS) { 5718 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5719 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5720 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5721 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5722 } 5723 } 5724 5725 static void igb_tsync_interrupt(struct igb_adapter *adapter) 5726 { 5727 struct e1000_hw *hw = &adapter->hw; 5728 struct ptp_clock_event event; 5729 struct timespec64 ts; 5730 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 5731 5732 if (tsicr & TSINTR_SYS_WRAP) { 5733 event.type = PTP_CLOCK_PPS; 5734 if (adapter->ptp_caps.pps) 5735 ptp_clock_event(adapter->ptp_clock, &event); 5736 else 5737 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP"); 5738 ack |= TSINTR_SYS_WRAP; 5739 } 5740 5741 if (tsicr & E1000_TSICR_TXTS) { 5742 /* retrieve hardware timestamp */ 5743 schedule_work(&adapter->ptp_tx_work); 5744 ack |= E1000_TSICR_TXTS; 5745 } 5746 5747 if (tsicr & TSINTR_TT0) { 5748 spin_lock(&adapter->tmreg_lock); 5749 ts = timespec64_add(adapter->perout[0].start, 5750 adapter->perout[0].period); 5751 /* u32 conversion of tv_sec is safe until y2106 */ 5752 wr32(E1000_TRGTTIML0, ts.tv_nsec); 5753 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 5754 tsauxc = rd32(E1000_TSAUXC); 5755 tsauxc |= TSAUXC_EN_TT0; 5756 wr32(E1000_TSAUXC, tsauxc); 5757 adapter->perout[0].start = ts; 5758 spin_unlock(&adapter->tmreg_lock); 5759 ack |= TSINTR_TT0; 5760 } 5761 5762 if (tsicr & TSINTR_TT1) { 5763 spin_lock(&adapter->tmreg_lock); 5764 ts = timespec64_add(adapter->perout[1].start, 5765 adapter->perout[1].period); 5766 wr32(E1000_TRGTTIML1, ts.tv_nsec); 5767 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 5768 tsauxc = rd32(E1000_TSAUXC); 5769 tsauxc |= TSAUXC_EN_TT1; 5770 wr32(E1000_TSAUXC, tsauxc); 5771 adapter->perout[1].start = ts; 5772 spin_unlock(&adapter->tmreg_lock); 5773 ack |= TSINTR_TT1; 5774 } 5775 5776 if (tsicr & TSINTR_AUTT0) { 5777 nsec = rd32(E1000_AUXSTMPL0); 5778 sec = rd32(E1000_AUXSTMPH0); 5779 event.type = PTP_CLOCK_EXTTS; 5780 event.index = 0; 5781 event.timestamp = sec * 1000000000ULL + nsec; 5782 ptp_clock_event(adapter->ptp_clock, &event); 5783 ack |= TSINTR_AUTT0; 5784 } 5785 5786 if (tsicr & TSINTR_AUTT1) { 5787 nsec = rd32(E1000_AUXSTMPL1); 5788 sec = rd32(E1000_AUXSTMPH1); 5789 event.type = PTP_CLOCK_EXTTS; 5790 event.index = 1; 5791 event.timestamp = sec * 1000000000ULL + nsec; 5792 ptp_clock_event(adapter->ptp_clock, &event); 5793 ack |= TSINTR_AUTT1; 5794 } 5795 5796 /* acknowledge the interrupts */ 5797 wr32(E1000_TSICR, ack); 5798 } 5799 5800 static irqreturn_t igb_msix_other(int irq, void *data) 5801 { 5802 struct igb_adapter *adapter = data; 5803 struct e1000_hw *hw = &adapter->hw; 5804 u32 icr = rd32(E1000_ICR); 5805 /* reading ICR causes bit 31 of EICR to be cleared */ 5806 5807 if (icr & E1000_ICR_DRSTA) 5808 schedule_work(&adapter->reset_task); 5809 5810 if (icr & E1000_ICR_DOUTSYNC) { 5811 /* HW is reporting DMA is out of sync */ 5812 adapter->stats.doosync++; 5813 /* The DMA Out of Sync is also indication of a spoof event 5814 * in IOV mode. Check the Wrong VM Behavior register to 5815 * see if it is really a spoof event. 5816 */ 5817 igb_check_wvbr(adapter); 5818 } 5819 5820 /* Check for a mailbox event */ 5821 if (icr & E1000_ICR_VMMB) 5822 igb_msg_task(adapter); 5823 5824 if (icr & E1000_ICR_LSC) { 5825 hw->mac.get_link_status = 1; 5826 /* guard against interrupt when we're going down */ 5827 if (!test_bit(__IGB_DOWN, &adapter->state)) 5828 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5829 } 5830 5831 if (icr & E1000_ICR_TS) 5832 igb_tsync_interrupt(adapter); 5833 5834 wr32(E1000_EIMS, adapter->eims_other); 5835 5836 return IRQ_HANDLED; 5837 } 5838 5839 static void igb_write_itr(struct igb_q_vector *q_vector) 5840 { 5841 struct igb_adapter *adapter = q_vector->adapter; 5842 u32 itr_val = q_vector->itr_val & 0x7FFC; 5843 5844 if (!q_vector->set_itr) 5845 return; 5846 5847 if (!itr_val) 5848 itr_val = 0x4; 5849 5850 if (adapter->hw.mac.type == e1000_82575) 5851 itr_val |= itr_val << 16; 5852 else 5853 itr_val |= E1000_EITR_CNT_IGNR; 5854 5855 writel(itr_val, q_vector->itr_register); 5856 q_vector->set_itr = 0; 5857 } 5858 5859 static irqreturn_t igb_msix_ring(int irq, void *data) 5860 { 5861 struct igb_q_vector *q_vector = data; 5862 5863 /* Write the ITR value calculated from the previous interrupt. */ 5864 igb_write_itr(q_vector); 5865 5866 napi_schedule(&q_vector->napi); 5867 5868 return IRQ_HANDLED; 5869 } 5870 5871 #ifdef CONFIG_IGB_DCA 5872 static void igb_update_tx_dca(struct igb_adapter *adapter, 5873 struct igb_ring *tx_ring, 5874 int cpu) 5875 { 5876 struct e1000_hw *hw = &adapter->hw; 5877 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5878 5879 if (hw->mac.type != e1000_82575) 5880 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5881 5882 /* We can enable relaxed ordering for reads, but not writes when 5883 * DCA is enabled. This is due to a known issue in some chipsets 5884 * which will cause the DCA tag to be cleared. 5885 */ 5886 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5887 E1000_DCA_TXCTRL_DATA_RRO_EN | 5888 E1000_DCA_TXCTRL_DESC_DCA_EN; 5889 5890 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5891 } 5892 5893 static void igb_update_rx_dca(struct igb_adapter *adapter, 5894 struct igb_ring *rx_ring, 5895 int cpu) 5896 { 5897 struct e1000_hw *hw = &adapter->hw; 5898 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5899 5900 if (hw->mac.type != e1000_82575) 5901 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5902 5903 /* We can enable relaxed ordering for reads, but not writes when 5904 * DCA is enabled. This is due to a known issue in some chipsets 5905 * which will cause the DCA tag to be cleared. 5906 */ 5907 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5908 E1000_DCA_RXCTRL_DESC_DCA_EN; 5909 5910 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5911 } 5912 5913 static void igb_update_dca(struct igb_q_vector *q_vector) 5914 { 5915 struct igb_adapter *adapter = q_vector->adapter; 5916 int cpu = get_cpu(); 5917 5918 if (q_vector->cpu == cpu) 5919 goto out_no_update; 5920 5921 if (q_vector->tx.ring) 5922 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5923 5924 if (q_vector->rx.ring) 5925 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5926 5927 q_vector->cpu = cpu; 5928 out_no_update: 5929 put_cpu(); 5930 } 5931 5932 static void igb_setup_dca(struct igb_adapter *adapter) 5933 { 5934 struct e1000_hw *hw = &adapter->hw; 5935 int i; 5936 5937 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5938 return; 5939 5940 /* Always use CB2 mode, difference is masked in the CB driver. */ 5941 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5942 5943 for (i = 0; i < adapter->num_q_vectors; i++) { 5944 adapter->q_vector[i]->cpu = -1; 5945 igb_update_dca(adapter->q_vector[i]); 5946 } 5947 } 5948 5949 static int __igb_notify_dca(struct device *dev, void *data) 5950 { 5951 struct net_device *netdev = dev_get_drvdata(dev); 5952 struct igb_adapter *adapter = netdev_priv(netdev); 5953 struct pci_dev *pdev = adapter->pdev; 5954 struct e1000_hw *hw = &adapter->hw; 5955 unsigned long event = *(unsigned long *)data; 5956 5957 switch (event) { 5958 case DCA_PROVIDER_ADD: 5959 /* if already enabled, don't do it again */ 5960 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5961 break; 5962 if (dca_add_requester(dev) == 0) { 5963 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5964 dev_info(&pdev->dev, "DCA enabled\n"); 5965 igb_setup_dca(adapter); 5966 break; 5967 } 5968 /* Fall Through since DCA is disabled. */ 5969 case DCA_PROVIDER_REMOVE: 5970 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5971 /* without this a class_device is left 5972 * hanging around in the sysfs model 5973 */ 5974 dca_remove_requester(dev); 5975 dev_info(&pdev->dev, "DCA disabled\n"); 5976 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5977 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5978 } 5979 break; 5980 } 5981 5982 return 0; 5983 } 5984 5985 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5986 void *p) 5987 { 5988 int ret_val; 5989 5990 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5991 __igb_notify_dca); 5992 5993 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5994 } 5995 #endif /* CONFIG_IGB_DCA */ 5996 5997 #ifdef CONFIG_PCI_IOV 5998 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5999 { 6000 unsigned char mac_addr[ETH_ALEN]; 6001 6002 eth_zero_addr(mac_addr); 6003 igb_set_vf_mac(adapter, vf, mac_addr); 6004 6005 /* By default spoof check is enabled for all VFs */ 6006 adapter->vf_data[vf].spoofchk_enabled = true; 6007 6008 return 0; 6009 } 6010 6011 #endif 6012 static void igb_ping_all_vfs(struct igb_adapter *adapter) 6013 { 6014 struct e1000_hw *hw = &adapter->hw; 6015 u32 ping; 6016 int i; 6017 6018 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 6019 ping = E1000_PF_CONTROL_MSG; 6020 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 6021 ping |= E1000_VT_MSGTYPE_CTS; 6022 igb_write_mbx(hw, &ping, 1, i); 6023 } 6024 } 6025 6026 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6027 { 6028 struct e1000_hw *hw = &adapter->hw; 6029 u32 vmolr = rd32(E1000_VMOLR(vf)); 6030 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6031 6032 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 6033 IGB_VF_FLAG_MULTI_PROMISC); 6034 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6035 6036 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 6037 vmolr |= E1000_VMOLR_MPME; 6038 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 6039 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 6040 } else { 6041 /* if we have hashes and we are clearing a multicast promisc 6042 * flag we need to write the hashes to the MTA as this step 6043 * was previously skipped 6044 */ 6045 if (vf_data->num_vf_mc_hashes > 30) { 6046 vmolr |= E1000_VMOLR_MPME; 6047 } else if (vf_data->num_vf_mc_hashes) { 6048 int j; 6049 6050 vmolr |= E1000_VMOLR_ROMPE; 6051 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6052 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6053 } 6054 } 6055 6056 wr32(E1000_VMOLR(vf), vmolr); 6057 6058 /* there are flags left unprocessed, likely not supported */ 6059 if (*msgbuf & E1000_VT_MSGINFO_MASK) 6060 return -EINVAL; 6061 6062 return 0; 6063 } 6064 6065 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 6066 u32 *msgbuf, u32 vf) 6067 { 6068 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6069 u16 *hash_list = (u16 *)&msgbuf[1]; 6070 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6071 int i; 6072 6073 /* salt away the number of multicast addresses assigned 6074 * to this VF for later use to restore when the PF multi cast 6075 * list changes 6076 */ 6077 vf_data->num_vf_mc_hashes = n; 6078 6079 /* only up to 30 hash values supported */ 6080 if (n > 30) 6081 n = 30; 6082 6083 /* store the hashes for later use */ 6084 for (i = 0; i < n; i++) 6085 vf_data->vf_mc_hashes[i] = hash_list[i]; 6086 6087 /* Flush and reset the mta with the new values */ 6088 igb_set_rx_mode(adapter->netdev); 6089 6090 return 0; 6091 } 6092 6093 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 6094 { 6095 struct e1000_hw *hw = &adapter->hw; 6096 struct vf_data_storage *vf_data; 6097 int i, j; 6098 6099 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6100 u32 vmolr = rd32(E1000_VMOLR(i)); 6101 6102 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 6103 6104 vf_data = &adapter->vf_data[i]; 6105 6106 if ((vf_data->num_vf_mc_hashes > 30) || 6107 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 6108 vmolr |= E1000_VMOLR_MPME; 6109 } else if (vf_data->num_vf_mc_hashes) { 6110 vmolr |= E1000_VMOLR_ROMPE; 6111 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 6112 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 6113 } 6114 wr32(E1000_VMOLR(i), vmolr); 6115 } 6116 } 6117 6118 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 6119 { 6120 struct e1000_hw *hw = &adapter->hw; 6121 u32 pool_mask, vlvf_mask, i; 6122 6123 /* create mask for VF and other pools */ 6124 pool_mask = E1000_VLVF_POOLSEL_MASK; 6125 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 6126 6127 /* drop PF from pool bits */ 6128 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 6129 adapter->vfs_allocated_count); 6130 6131 /* Find the vlan filter for this id */ 6132 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 6133 u32 vlvf = rd32(E1000_VLVF(i)); 6134 u32 vfta_mask, vid, vfta; 6135 6136 /* remove the vf from the pool */ 6137 if (!(vlvf & vlvf_mask)) 6138 continue; 6139 6140 /* clear out bit from VLVF */ 6141 vlvf ^= vlvf_mask; 6142 6143 /* if other pools are present, just remove ourselves */ 6144 if (vlvf & pool_mask) 6145 goto update_vlvfb; 6146 6147 /* if PF is present, leave VFTA */ 6148 if (vlvf & E1000_VLVF_POOLSEL_MASK) 6149 goto update_vlvf; 6150 6151 vid = vlvf & E1000_VLVF_VLANID_MASK; 6152 vfta_mask = BIT(vid % 32); 6153 6154 /* clear bit from VFTA */ 6155 vfta = adapter->shadow_vfta[vid / 32]; 6156 if (vfta & vfta_mask) 6157 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 6158 update_vlvf: 6159 /* clear pool selection enable */ 6160 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6161 vlvf &= E1000_VLVF_POOLSEL_MASK; 6162 else 6163 vlvf = 0; 6164 update_vlvfb: 6165 /* clear pool bits */ 6166 wr32(E1000_VLVF(i), vlvf); 6167 } 6168 } 6169 6170 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 6171 { 6172 u32 vlvf; 6173 int idx; 6174 6175 /* short cut the special case */ 6176 if (vlan == 0) 6177 return 0; 6178 6179 /* Search for the VLAN id in the VLVF entries */ 6180 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 6181 vlvf = rd32(E1000_VLVF(idx)); 6182 if ((vlvf & VLAN_VID_MASK) == vlan) 6183 break; 6184 } 6185 6186 return idx; 6187 } 6188 6189 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 6190 { 6191 struct e1000_hw *hw = &adapter->hw; 6192 u32 bits, pf_id; 6193 int idx; 6194 6195 idx = igb_find_vlvf_entry(hw, vid); 6196 if (!idx) 6197 return; 6198 6199 /* See if any other pools are set for this VLAN filter 6200 * entry other than the PF. 6201 */ 6202 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 6203 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 6204 bits &= rd32(E1000_VLVF(idx)); 6205 6206 /* Disable the filter so this falls into the default pool. */ 6207 if (!bits) { 6208 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 6209 wr32(E1000_VLVF(idx), BIT(pf_id)); 6210 else 6211 wr32(E1000_VLVF(idx), 0); 6212 } 6213 } 6214 6215 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 6216 bool add, u32 vf) 6217 { 6218 int pf_id = adapter->vfs_allocated_count; 6219 struct e1000_hw *hw = &adapter->hw; 6220 int err; 6221 6222 /* If VLAN overlaps with one the PF is currently monitoring make 6223 * sure that we are able to allocate a VLVF entry. This may be 6224 * redundant but it guarantees PF will maintain visibility to 6225 * the VLAN. 6226 */ 6227 if (add && test_bit(vid, adapter->active_vlans)) { 6228 err = igb_vfta_set(hw, vid, pf_id, true, false); 6229 if (err) 6230 return err; 6231 } 6232 6233 err = igb_vfta_set(hw, vid, vf, add, false); 6234 6235 if (add && !err) 6236 return err; 6237 6238 /* If we failed to add the VF VLAN or we are removing the VF VLAN 6239 * we may need to drop the PF pool bit in order to allow us to free 6240 * up the VLVF resources. 6241 */ 6242 if (test_bit(vid, adapter->active_vlans) || 6243 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 6244 igb_update_pf_vlvf(adapter, vid); 6245 6246 return err; 6247 } 6248 6249 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 6250 { 6251 struct e1000_hw *hw = &adapter->hw; 6252 6253 if (vid) 6254 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 6255 else 6256 wr32(E1000_VMVIR(vf), 0); 6257 } 6258 6259 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 6260 u16 vlan, u8 qos) 6261 { 6262 int err; 6263 6264 err = igb_set_vf_vlan(adapter, vlan, true, vf); 6265 if (err) 6266 return err; 6267 6268 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 6269 igb_set_vmolr(adapter, vf, !vlan); 6270 6271 /* revoke access to previous VLAN */ 6272 if (vlan != adapter->vf_data[vf].pf_vlan) 6273 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6274 false, vf); 6275 6276 adapter->vf_data[vf].pf_vlan = vlan; 6277 adapter->vf_data[vf].pf_qos = qos; 6278 igb_set_vf_vlan_strip(adapter, vf, true); 6279 dev_info(&adapter->pdev->dev, 6280 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 6281 if (test_bit(__IGB_DOWN, &adapter->state)) { 6282 dev_warn(&adapter->pdev->dev, 6283 "The VF VLAN has been set, but the PF device is not up.\n"); 6284 dev_warn(&adapter->pdev->dev, 6285 "Bring the PF device up before attempting to use the VF device.\n"); 6286 } 6287 6288 return err; 6289 } 6290 6291 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 6292 { 6293 /* Restore tagless access via VLAN 0 */ 6294 igb_set_vf_vlan(adapter, 0, true, vf); 6295 6296 igb_set_vmvir(adapter, 0, vf); 6297 igb_set_vmolr(adapter, vf, true); 6298 6299 /* Remove any PF assigned VLAN */ 6300 if (adapter->vf_data[vf].pf_vlan) 6301 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 6302 false, vf); 6303 6304 adapter->vf_data[vf].pf_vlan = 0; 6305 adapter->vf_data[vf].pf_qos = 0; 6306 igb_set_vf_vlan_strip(adapter, vf, false); 6307 6308 return 0; 6309 } 6310 6311 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 6312 u16 vlan, u8 qos, __be16 vlan_proto) 6313 { 6314 struct igb_adapter *adapter = netdev_priv(netdev); 6315 6316 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 6317 return -EINVAL; 6318 6319 if (vlan_proto != htons(ETH_P_8021Q)) 6320 return -EPROTONOSUPPORT; 6321 6322 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 6323 igb_disable_port_vlan(adapter, vf); 6324 } 6325 6326 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 6327 { 6328 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 6329 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 6330 int ret; 6331 6332 if (adapter->vf_data[vf].pf_vlan) 6333 return -1; 6334 6335 /* VLAN 0 is a special case, don't allow it to be removed */ 6336 if (!vid && !add) 6337 return 0; 6338 6339 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 6340 if (!ret) 6341 igb_set_vf_vlan_strip(adapter, vf, !!vid); 6342 return ret; 6343 } 6344 6345 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 6346 { 6347 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6348 6349 /* clear flags - except flag that indicates PF has set the MAC */ 6350 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 6351 vf_data->last_nack = jiffies; 6352 6353 /* reset vlans for device */ 6354 igb_clear_vf_vfta(adapter, vf); 6355 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 6356 igb_set_vmvir(adapter, vf_data->pf_vlan | 6357 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 6358 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 6359 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 6360 6361 /* reset multicast table array for vf */ 6362 adapter->vf_data[vf].num_vf_mc_hashes = 0; 6363 6364 /* Flush and reset the mta with the new values */ 6365 igb_set_rx_mode(adapter->netdev); 6366 } 6367 6368 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 6369 { 6370 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6371 6372 /* clear mac address as we were hotplug removed/added */ 6373 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 6374 eth_zero_addr(vf_mac); 6375 6376 /* process remaining reset events */ 6377 igb_vf_reset(adapter, vf); 6378 } 6379 6380 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 6381 { 6382 struct e1000_hw *hw = &adapter->hw; 6383 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 6384 u32 reg, msgbuf[3]; 6385 u8 *addr = (u8 *)(&msgbuf[1]); 6386 6387 /* process all the same items cleared in a function level reset */ 6388 igb_vf_reset(adapter, vf); 6389 6390 /* set vf mac address */ 6391 igb_set_vf_mac(adapter, vf, vf_mac); 6392 6393 /* enable transmit and receive for vf */ 6394 reg = rd32(E1000_VFTE); 6395 wr32(E1000_VFTE, reg | BIT(vf)); 6396 reg = rd32(E1000_VFRE); 6397 wr32(E1000_VFRE, reg | BIT(vf)); 6398 6399 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 6400 6401 /* reply to reset with ack and vf mac address */ 6402 if (!is_zero_ether_addr(vf_mac)) { 6403 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 6404 memcpy(addr, vf_mac, ETH_ALEN); 6405 } else { 6406 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 6407 } 6408 igb_write_mbx(hw, msgbuf, 3, vf); 6409 } 6410 6411 static void igb_flush_mac_table(struct igb_adapter *adapter) 6412 { 6413 struct e1000_hw *hw = &adapter->hw; 6414 int i; 6415 6416 for (i = 0; i < hw->mac.rar_entry_count; i++) { 6417 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6418 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6419 adapter->mac_table[i].queue = 0; 6420 igb_rar_set_index(adapter, i); 6421 } 6422 } 6423 6424 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 6425 { 6426 struct e1000_hw *hw = &adapter->hw; 6427 /* do not count rar entries reserved for VFs MAC addresses */ 6428 int rar_entries = hw->mac.rar_entry_count - 6429 adapter->vfs_allocated_count; 6430 int i, count = 0; 6431 6432 for (i = 0; i < rar_entries; i++) { 6433 /* do not count default entries */ 6434 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 6435 continue; 6436 6437 /* do not count "in use" entries for different queues */ 6438 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 6439 (adapter->mac_table[i].queue != queue)) 6440 continue; 6441 6442 count++; 6443 } 6444 6445 return count; 6446 } 6447 6448 /* Set default MAC address for the PF in the first RAR entry */ 6449 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 6450 { 6451 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 6452 6453 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 6454 mac_table->queue = adapter->vfs_allocated_count; 6455 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 6456 6457 igb_rar_set_index(adapter, 0); 6458 } 6459 6460 int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6461 const u8 queue) 6462 { 6463 struct e1000_hw *hw = &adapter->hw; 6464 int rar_entries = hw->mac.rar_entry_count - 6465 adapter->vfs_allocated_count; 6466 int i; 6467 6468 if (is_zero_ether_addr(addr)) 6469 return -EINVAL; 6470 6471 /* Search for the first empty entry in the MAC table. 6472 * Do not touch entries at the end of the table reserved for the VF MAC 6473 * addresses. 6474 */ 6475 for (i = 0; i < rar_entries; i++) { 6476 if (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) 6477 continue; 6478 6479 ether_addr_copy(adapter->mac_table[i].addr, addr); 6480 adapter->mac_table[i].queue = queue; 6481 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE; 6482 6483 igb_rar_set_index(adapter, i); 6484 return i; 6485 } 6486 6487 return -ENOSPC; 6488 } 6489 6490 int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 6491 const u8 queue) 6492 { 6493 struct e1000_hw *hw = &adapter->hw; 6494 int rar_entries = hw->mac.rar_entry_count - 6495 adapter->vfs_allocated_count; 6496 int i; 6497 6498 if (is_zero_ether_addr(addr)) 6499 return -EINVAL; 6500 6501 /* Search for matching entry in the MAC table based on given address 6502 * and queue. Do not touch entries at the end of the table reserved 6503 * for the VF MAC addresses. 6504 */ 6505 for (i = 0; i < rar_entries; i++) { 6506 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 6507 continue; 6508 if (adapter->mac_table[i].queue != queue) 6509 continue; 6510 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 6511 continue; 6512 6513 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 6514 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 6515 adapter->mac_table[i].queue = 0; 6516 6517 igb_rar_set_index(adapter, i); 6518 return 0; 6519 } 6520 6521 return -ENOENT; 6522 } 6523 6524 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 6525 { 6526 struct igb_adapter *adapter = netdev_priv(netdev); 6527 int ret; 6528 6529 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6530 6531 return min_t(int, ret, 0); 6532 } 6533 6534 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 6535 { 6536 struct igb_adapter *adapter = netdev_priv(netdev); 6537 6538 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 6539 6540 return 0; 6541 } 6542 6543 int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 6544 const u32 info, const u8 *addr) 6545 { 6546 struct pci_dev *pdev = adapter->pdev; 6547 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6548 struct list_head *pos; 6549 struct vf_mac_filter *entry = NULL; 6550 int ret = 0; 6551 6552 switch (info) { 6553 case E1000_VF_MAC_FILTER_CLR: 6554 /* remove all unicast MAC filters related to the current VF */ 6555 list_for_each(pos, &adapter->vf_macs.l) { 6556 entry = list_entry(pos, struct vf_mac_filter, l); 6557 if (entry->vf == vf) { 6558 entry->vf = -1; 6559 entry->free = true; 6560 igb_del_mac_filter(adapter, entry->vf_mac, vf); 6561 } 6562 } 6563 break; 6564 case E1000_VF_MAC_FILTER_ADD: 6565 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6566 dev_warn(&pdev->dev, 6567 "VF %d requested MAC filter but is administratively denied\n", 6568 vf); 6569 return -EINVAL; 6570 } 6571 6572 if (!is_valid_ether_addr(addr)) { 6573 dev_warn(&pdev->dev, 6574 "VF %d attempted to set invalid MAC filter\n", 6575 vf); 6576 return -EINVAL; 6577 } 6578 6579 /* try to find empty slot in the list */ 6580 list_for_each(pos, &adapter->vf_macs.l) { 6581 entry = list_entry(pos, struct vf_mac_filter, l); 6582 if (entry->free) 6583 break; 6584 } 6585 6586 if (entry && entry->free) { 6587 entry->free = false; 6588 entry->vf = vf; 6589 ether_addr_copy(entry->vf_mac, addr); 6590 6591 ret = igb_add_mac_filter(adapter, addr, vf); 6592 ret = min_t(int, ret, 0); 6593 } else { 6594 ret = -ENOSPC; 6595 } 6596 6597 if (ret == -ENOSPC) 6598 dev_warn(&pdev->dev, 6599 "VF %d has requested MAC filter but there is no space for it\n", 6600 vf); 6601 break; 6602 default: 6603 ret = -EINVAL; 6604 break; 6605 } 6606 6607 return ret; 6608 } 6609 6610 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 6611 { 6612 struct pci_dev *pdev = adapter->pdev; 6613 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6614 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 6615 6616 /* The VF MAC Address is stored in a packed array of bytes 6617 * starting at the second 32 bit word of the msg array 6618 */ 6619 unsigned char *addr = (unsigned char *)&msg[1]; 6620 int ret = 0; 6621 6622 if (!info) { 6623 if (vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) { 6624 dev_warn(&pdev->dev, 6625 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6626 vf); 6627 return -EINVAL; 6628 } 6629 6630 if (!is_valid_ether_addr(addr)) { 6631 dev_warn(&pdev->dev, 6632 "VF %d attempted to set invalid MAC\n", 6633 vf); 6634 return -EINVAL; 6635 } 6636 6637 ret = igb_set_vf_mac(adapter, vf, addr); 6638 } else { 6639 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 6640 } 6641 6642 return ret; 6643 } 6644 6645 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6646 { 6647 struct e1000_hw *hw = &adapter->hw; 6648 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6649 u32 msg = E1000_VT_MSGTYPE_NACK; 6650 6651 /* if device isn't clear to send it shouldn't be reading either */ 6652 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6653 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6654 igb_write_mbx(hw, &msg, 1, vf); 6655 vf_data->last_nack = jiffies; 6656 } 6657 } 6658 6659 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6660 { 6661 struct pci_dev *pdev = adapter->pdev; 6662 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6663 struct e1000_hw *hw = &adapter->hw; 6664 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6665 s32 retval; 6666 6667 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6668 6669 if (retval) { 6670 /* if receive failed revoke VF CTS stats and restart init */ 6671 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6672 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6673 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6674 return; 6675 goto out; 6676 } 6677 6678 /* this is a message we already processed, do nothing */ 6679 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6680 return; 6681 6682 /* until the vf completes a reset it should not be 6683 * allowed to start any configuration. 6684 */ 6685 if (msgbuf[0] == E1000_VF_RESET) { 6686 igb_vf_reset_msg(adapter, vf); 6687 return; 6688 } 6689 6690 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6691 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6692 return; 6693 retval = -1; 6694 goto out; 6695 } 6696 6697 switch ((msgbuf[0] & 0xFFFF)) { 6698 case E1000_VF_SET_MAC_ADDR: 6699 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6700 break; 6701 case E1000_VF_SET_PROMISC: 6702 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6703 break; 6704 case E1000_VF_SET_MULTICAST: 6705 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6706 break; 6707 case E1000_VF_SET_LPE: 6708 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6709 break; 6710 case E1000_VF_SET_VLAN: 6711 retval = -1; 6712 if (vf_data->pf_vlan) 6713 dev_warn(&pdev->dev, 6714 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6715 vf); 6716 else 6717 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 6718 break; 6719 default: 6720 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6721 retval = -1; 6722 break; 6723 } 6724 6725 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6726 out: 6727 /* notify the VF of the results of what it sent us */ 6728 if (retval) 6729 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6730 else 6731 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6732 6733 igb_write_mbx(hw, msgbuf, 1, vf); 6734 } 6735 6736 static void igb_msg_task(struct igb_adapter *adapter) 6737 { 6738 struct e1000_hw *hw = &adapter->hw; 6739 u32 vf; 6740 6741 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6742 /* process any reset requests */ 6743 if (!igb_check_for_rst(hw, vf)) 6744 igb_vf_reset_event(adapter, vf); 6745 6746 /* process any messages pending */ 6747 if (!igb_check_for_msg(hw, vf)) 6748 igb_rcv_msg_from_vf(adapter, vf); 6749 6750 /* process any acks */ 6751 if (!igb_check_for_ack(hw, vf)) 6752 igb_rcv_ack_from_vf(adapter, vf); 6753 } 6754 } 6755 6756 /** 6757 * igb_set_uta - Set unicast filter table address 6758 * @adapter: board private structure 6759 * @set: boolean indicating if we are setting or clearing bits 6760 * 6761 * The unicast table address is a register array of 32-bit registers. 6762 * The table is meant to be used in a way similar to how the MTA is used 6763 * however due to certain limitations in the hardware it is necessary to 6764 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6765 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6766 **/ 6767 static void igb_set_uta(struct igb_adapter *adapter, bool set) 6768 { 6769 struct e1000_hw *hw = &adapter->hw; 6770 u32 uta = set ? ~0 : 0; 6771 int i; 6772 6773 /* we only need to do this if VMDq is enabled */ 6774 if (!adapter->vfs_allocated_count) 6775 return; 6776 6777 for (i = hw->mac.uta_reg_count; i--;) 6778 array_wr32(E1000_UTA, i, uta); 6779 } 6780 6781 /** 6782 * igb_intr_msi - Interrupt Handler 6783 * @irq: interrupt number 6784 * @data: pointer to a network interface device structure 6785 **/ 6786 static irqreturn_t igb_intr_msi(int irq, void *data) 6787 { 6788 struct igb_adapter *adapter = data; 6789 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6790 struct e1000_hw *hw = &adapter->hw; 6791 /* read ICR disables interrupts using IAM */ 6792 u32 icr = rd32(E1000_ICR); 6793 6794 igb_write_itr(q_vector); 6795 6796 if (icr & E1000_ICR_DRSTA) 6797 schedule_work(&adapter->reset_task); 6798 6799 if (icr & E1000_ICR_DOUTSYNC) { 6800 /* HW is reporting DMA is out of sync */ 6801 adapter->stats.doosync++; 6802 } 6803 6804 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6805 hw->mac.get_link_status = 1; 6806 if (!test_bit(__IGB_DOWN, &adapter->state)) 6807 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6808 } 6809 6810 if (icr & E1000_ICR_TS) 6811 igb_tsync_interrupt(adapter); 6812 6813 napi_schedule(&q_vector->napi); 6814 6815 return IRQ_HANDLED; 6816 } 6817 6818 /** 6819 * igb_intr - Legacy Interrupt Handler 6820 * @irq: interrupt number 6821 * @data: pointer to a network interface device structure 6822 **/ 6823 static irqreturn_t igb_intr(int irq, void *data) 6824 { 6825 struct igb_adapter *adapter = data; 6826 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6827 struct e1000_hw *hw = &adapter->hw; 6828 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6829 * need for the IMC write 6830 */ 6831 u32 icr = rd32(E1000_ICR); 6832 6833 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6834 * not set, then the adapter didn't send an interrupt 6835 */ 6836 if (!(icr & E1000_ICR_INT_ASSERTED)) 6837 return IRQ_NONE; 6838 6839 igb_write_itr(q_vector); 6840 6841 if (icr & E1000_ICR_DRSTA) 6842 schedule_work(&adapter->reset_task); 6843 6844 if (icr & E1000_ICR_DOUTSYNC) { 6845 /* HW is reporting DMA is out of sync */ 6846 adapter->stats.doosync++; 6847 } 6848 6849 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6850 hw->mac.get_link_status = 1; 6851 /* guard against interrupt when we're going down */ 6852 if (!test_bit(__IGB_DOWN, &adapter->state)) 6853 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6854 } 6855 6856 if (icr & E1000_ICR_TS) 6857 igb_tsync_interrupt(adapter); 6858 6859 napi_schedule(&q_vector->napi); 6860 6861 return IRQ_HANDLED; 6862 } 6863 6864 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6865 { 6866 struct igb_adapter *adapter = q_vector->adapter; 6867 struct e1000_hw *hw = &adapter->hw; 6868 6869 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6870 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6871 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6872 igb_set_itr(q_vector); 6873 else 6874 igb_update_ring_itr(q_vector); 6875 } 6876 6877 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6878 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6879 wr32(E1000_EIMS, q_vector->eims_value); 6880 else 6881 igb_irq_enable(adapter); 6882 } 6883 } 6884 6885 /** 6886 * igb_poll - NAPI Rx polling callback 6887 * @napi: napi polling structure 6888 * @budget: count of how many packets we should handle 6889 **/ 6890 static int igb_poll(struct napi_struct *napi, int budget) 6891 { 6892 struct igb_q_vector *q_vector = container_of(napi, 6893 struct igb_q_vector, 6894 napi); 6895 bool clean_complete = true; 6896 int work_done = 0; 6897 6898 #ifdef CONFIG_IGB_DCA 6899 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6900 igb_update_dca(q_vector); 6901 #endif 6902 if (q_vector->tx.ring) 6903 clean_complete = igb_clean_tx_irq(q_vector, budget); 6904 6905 if (q_vector->rx.ring) { 6906 int cleaned = igb_clean_rx_irq(q_vector, budget); 6907 6908 work_done += cleaned; 6909 if (cleaned >= budget) 6910 clean_complete = false; 6911 } 6912 6913 /* If all work not completed, return budget and keep polling */ 6914 if (!clean_complete) 6915 return budget; 6916 6917 /* If not enough Rx work done, exit the polling mode */ 6918 napi_complete_done(napi, work_done); 6919 igb_ring_irq_enable(q_vector); 6920 6921 return 0; 6922 } 6923 6924 /** 6925 * igb_clean_tx_irq - Reclaim resources after transmit completes 6926 * @q_vector: pointer to q_vector containing needed info 6927 * @napi_budget: Used to determine if we are in netpoll 6928 * 6929 * returns true if ring is completely cleaned 6930 **/ 6931 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 6932 { 6933 struct igb_adapter *adapter = q_vector->adapter; 6934 struct igb_ring *tx_ring = q_vector->tx.ring; 6935 struct igb_tx_buffer *tx_buffer; 6936 union e1000_adv_tx_desc *tx_desc; 6937 unsigned int total_bytes = 0, total_packets = 0; 6938 unsigned int budget = q_vector->tx.work_limit; 6939 unsigned int i = tx_ring->next_to_clean; 6940 6941 if (test_bit(__IGB_DOWN, &adapter->state)) 6942 return true; 6943 6944 tx_buffer = &tx_ring->tx_buffer_info[i]; 6945 tx_desc = IGB_TX_DESC(tx_ring, i); 6946 i -= tx_ring->count; 6947 6948 do { 6949 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6950 6951 /* if next_to_watch is not set then there is no work pending */ 6952 if (!eop_desc) 6953 break; 6954 6955 /* prevent any other reads prior to eop_desc */ 6956 read_barrier_depends(); 6957 6958 /* if DD is not set pending work has not been completed */ 6959 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6960 break; 6961 6962 /* clear next_to_watch to prevent false hangs */ 6963 tx_buffer->next_to_watch = NULL; 6964 6965 /* update the statistics for this packet */ 6966 total_bytes += tx_buffer->bytecount; 6967 total_packets += tx_buffer->gso_segs; 6968 6969 /* free the skb */ 6970 napi_consume_skb(tx_buffer->skb, napi_budget); 6971 6972 /* unmap skb header data */ 6973 dma_unmap_single(tx_ring->dev, 6974 dma_unmap_addr(tx_buffer, dma), 6975 dma_unmap_len(tx_buffer, len), 6976 DMA_TO_DEVICE); 6977 6978 /* clear tx_buffer data */ 6979 dma_unmap_len_set(tx_buffer, len, 0); 6980 6981 /* clear last DMA location and unmap remaining buffers */ 6982 while (tx_desc != eop_desc) { 6983 tx_buffer++; 6984 tx_desc++; 6985 i++; 6986 if (unlikely(!i)) { 6987 i -= tx_ring->count; 6988 tx_buffer = tx_ring->tx_buffer_info; 6989 tx_desc = IGB_TX_DESC(tx_ring, 0); 6990 } 6991 6992 /* unmap any remaining paged data */ 6993 if (dma_unmap_len(tx_buffer, len)) { 6994 dma_unmap_page(tx_ring->dev, 6995 dma_unmap_addr(tx_buffer, dma), 6996 dma_unmap_len(tx_buffer, len), 6997 DMA_TO_DEVICE); 6998 dma_unmap_len_set(tx_buffer, len, 0); 6999 } 7000 } 7001 7002 /* move us one more past the eop_desc for start of next pkt */ 7003 tx_buffer++; 7004 tx_desc++; 7005 i++; 7006 if (unlikely(!i)) { 7007 i -= tx_ring->count; 7008 tx_buffer = tx_ring->tx_buffer_info; 7009 tx_desc = IGB_TX_DESC(tx_ring, 0); 7010 } 7011 7012 /* issue prefetch for next Tx descriptor */ 7013 prefetch(tx_desc); 7014 7015 /* update budget accounting */ 7016 budget--; 7017 } while (likely(budget)); 7018 7019 netdev_tx_completed_queue(txring_txq(tx_ring), 7020 total_packets, total_bytes); 7021 i += tx_ring->count; 7022 tx_ring->next_to_clean = i; 7023 u64_stats_update_begin(&tx_ring->tx_syncp); 7024 tx_ring->tx_stats.bytes += total_bytes; 7025 tx_ring->tx_stats.packets += total_packets; 7026 u64_stats_update_end(&tx_ring->tx_syncp); 7027 q_vector->tx.total_bytes += total_bytes; 7028 q_vector->tx.total_packets += total_packets; 7029 7030 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 7031 struct e1000_hw *hw = &adapter->hw; 7032 7033 /* Detect a transmit hang in hardware, this serializes the 7034 * check with the clearing of time_stamp and movement of i 7035 */ 7036 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 7037 if (tx_buffer->next_to_watch && 7038 time_after(jiffies, tx_buffer->time_stamp + 7039 (adapter->tx_timeout_factor * HZ)) && 7040 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 7041 7042 /* detected Tx unit hang */ 7043 dev_err(tx_ring->dev, 7044 "Detected Tx Unit Hang\n" 7045 " Tx Queue <%d>\n" 7046 " TDH <%x>\n" 7047 " TDT <%x>\n" 7048 " next_to_use <%x>\n" 7049 " next_to_clean <%x>\n" 7050 "buffer_info[next_to_clean]\n" 7051 " time_stamp <%lx>\n" 7052 " next_to_watch <%p>\n" 7053 " jiffies <%lx>\n" 7054 " desc.status <%x>\n", 7055 tx_ring->queue_index, 7056 rd32(E1000_TDH(tx_ring->reg_idx)), 7057 readl(tx_ring->tail), 7058 tx_ring->next_to_use, 7059 tx_ring->next_to_clean, 7060 tx_buffer->time_stamp, 7061 tx_buffer->next_to_watch, 7062 jiffies, 7063 tx_buffer->next_to_watch->wb.status); 7064 netif_stop_subqueue(tx_ring->netdev, 7065 tx_ring->queue_index); 7066 7067 /* we are about to reset, no point in enabling stuff */ 7068 return true; 7069 } 7070 } 7071 7072 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 7073 if (unlikely(total_packets && 7074 netif_carrier_ok(tx_ring->netdev) && 7075 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 7076 /* Make sure that anybody stopping the queue after this 7077 * sees the new next_to_clean. 7078 */ 7079 smp_mb(); 7080 if (__netif_subqueue_stopped(tx_ring->netdev, 7081 tx_ring->queue_index) && 7082 !(test_bit(__IGB_DOWN, &adapter->state))) { 7083 netif_wake_subqueue(tx_ring->netdev, 7084 tx_ring->queue_index); 7085 7086 u64_stats_update_begin(&tx_ring->tx_syncp); 7087 tx_ring->tx_stats.restart_queue++; 7088 u64_stats_update_end(&tx_ring->tx_syncp); 7089 } 7090 } 7091 7092 return !!budget; 7093 } 7094 7095 /** 7096 * igb_reuse_rx_page - page flip buffer and store it back on the ring 7097 * @rx_ring: rx descriptor ring to store buffers on 7098 * @old_buff: donor buffer to have page reused 7099 * 7100 * Synchronizes page for reuse by the adapter 7101 **/ 7102 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 7103 struct igb_rx_buffer *old_buff) 7104 { 7105 struct igb_rx_buffer *new_buff; 7106 u16 nta = rx_ring->next_to_alloc; 7107 7108 new_buff = &rx_ring->rx_buffer_info[nta]; 7109 7110 /* update, and store next to alloc */ 7111 nta++; 7112 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 7113 7114 /* Transfer page from old buffer to new buffer. 7115 * Move each member individually to avoid possible store 7116 * forwarding stalls. 7117 */ 7118 new_buff->dma = old_buff->dma; 7119 new_buff->page = old_buff->page; 7120 new_buff->page_offset = old_buff->page_offset; 7121 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 7122 } 7123 7124 static inline bool igb_page_is_reserved(struct page *page) 7125 { 7126 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 7127 } 7128 7129 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 7130 { 7131 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 7132 struct page *page = rx_buffer->page; 7133 7134 /* avoid re-using remote pages */ 7135 if (unlikely(igb_page_is_reserved(page))) 7136 return false; 7137 7138 #if (PAGE_SIZE < 8192) 7139 /* if we are only owner of page we can reuse it */ 7140 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 7141 return false; 7142 #else 7143 #define IGB_LAST_OFFSET \ 7144 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 7145 7146 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 7147 return false; 7148 #endif 7149 7150 /* If we have drained the page fragment pool we need to update 7151 * the pagecnt_bias and page count so that we fully restock the 7152 * number of references the driver holds. 7153 */ 7154 if (unlikely(!pagecnt_bias)) { 7155 page_ref_add(page, USHRT_MAX); 7156 rx_buffer->pagecnt_bias = USHRT_MAX; 7157 } 7158 7159 return true; 7160 } 7161 7162 /** 7163 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 7164 * @rx_ring: rx descriptor ring to transact packets on 7165 * @rx_buffer: buffer containing page to add 7166 * @skb: sk_buff to place the data into 7167 * @size: size of buffer to be added 7168 * 7169 * This function will add the data contained in rx_buffer->page to the skb. 7170 **/ 7171 static void igb_add_rx_frag(struct igb_ring *rx_ring, 7172 struct igb_rx_buffer *rx_buffer, 7173 struct sk_buff *skb, 7174 unsigned int size) 7175 { 7176 #if (PAGE_SIZE < 8192) 7177 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7178 #else 7179 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 7180 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 7181 SKB_DATA_ALIGN(size); 7182 #endif 7183 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 7184 rx_buffer->page_offset, size, truesize); 7185 #if (PAGE_SIZE < 8192) 7186 rx_buffer->page_offset ^= truesize; 7187 #else 7188 rx_buffer->page_offset += truesize; 7189 #endif 7190 } 7191 7192 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 7193 struct igb_rx_buffer *rx_buffer, 7194 union e1000_adv_rx_desc *rx_desc, 7195 unsigned int size) 7196 { 7197 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7198 #if (PAGE_SIZE < 8192) 7199 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7200 #else 7201 unsigned int truesize = SKB_DATA_ALIGN(size); 7202 #endif 7203 unsigned int headlen; 7204 struct sk_buff *skb; 7205 7206 /* prefetch first cache line of first page */ 7207 prefetch(va); 7208 #if L1_CACHE_BYTES < 128 7209 prefetch(va + L1_CACHE_BYTES); 7210 #endif 7211 7212 /* allocate a skb to store the frags */ 7213 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 7214 if (unlikely(!skb)) 7215 return NULL; 7216 7217 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 7218 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 7219 va += IGB_TS_HDR_LEN; 7220 size -= IGB_TS_HDR_LEN; 7221 } 7222 7223 /* Determine available headroom for copy */ 7224 headlen = size; 7225 if (headlen > IGB_RX_HDR_LEN) 7226 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN); 7227 7228 /* align pull length to size of long to optimize memcpy performance */ 7229 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 7230 7231 /* update all of the pointers */ 7232 size -= headlen; 7233 if (size) { 7234 skb_add_rx_frag(skb, 0, rx_buffer->page, 7235 (va + headlen) - page_address(rx_buffer->page), 7236 size, truesize); 7237 #if (PAGE_SIZE < 8192) 7238 rx_buffer->page_offset ^= truesize; 7239 #else 7240 rx_buffer->page_offset += truesize; 7241 #endif 7242 } else { 7243 rx_buffer->pagecnt_bias++; 7244 } 7245 7246 return skb; 7247 } 7248 7249 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 7250 struct igb_rx_buffer *rx_buffer, 7251 union e1000_adv_rx_desc *rx_desc, 7252 unsigned int size) 7253 { 7254 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 7255 #if (PAGE_SIZE < 8192) 7256 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 7257 #else 7258 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 7259 SKB_DATA_ALIGN(IGB_SKB_PAD + size); 7260 #endif 7261 struct sk_buff *skb; 7262 7263 /* prefetch first cache line of first page */ 7264 prefetch(va); 7265 #if L1_CACHE_BYTES < 128 7266 prefetch(va + L1_CACHE_BYTES); 7267 #endif 7268 7269 /* build an skb around the page buffer */ 7270 skb = build_skb(va - IGB_SKB_PAD, truesize); 7271 if (unlikely(!skb)) 7272 return NULL; 7273 7274 /* update pointers within the skb to store the data */ 7275 skb_reserve(skb, IGB_SKB_PAD); 7276 __skb_put(skb, size); 7277 7278 /* pull timestamp out of packet data */ 7279 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 7280 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 7281 __skb_pull(skb, IGB_TS_HDR_LEN); 7282 } 7283 7284 /* update buffer offset */ 7285 #if (PAGE_SIZE < 8192) 7286 rx_buffer->page_offset ^= truesize; 7287 #else 7288 rx_buffer->page_offset += truesize; 7289 #endif 7290 7291 return skb; 7292 } 7293 7294 static inline void igb_rx_checksum(struct igb_ring *ring, 7295 union e1000_adv_rx_desc *rx_desc, 7296 struct sk_buff *skb) 7297 { 7298 skb_checksum_none_assert(skb); 7299 7300 /* Ignore Checksum bit is set */ 7301 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 7302 return; 7303 7304 /* Rx checksum disabled via ethtool */ 7305 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 7306 return; 7307 7308 /* TCP/UDP checksum error bit is set */ 7309 if (igb_test_staterr(rx_desc, 7310 E1000_RXDEXT_STATERR_TCPE | 7311 E1000_RXDEXT_STATERR_IPE)) { 7312 /* work around errata with sctp packets where the TCPE aka 7313 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 7314 * packets, (aka let the stack check the crc32c) 7315 */ 7316 if (!((skb->len == 60) && 7317 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 7318 u64_stats_update_begin(&ring->rx_syncp); 7319 ring->rx_stats.csum_err++; 7320 u64_stats_update_end(&ring->rx_syncp); 7321 } 7322 /* let the stack verify checksum errors */ 7323 return; 7324 } 7325 /* It must be a TCP or UDP packet with a valid checksum */ 7326 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 7327 E1000_RXD_STAT_UDPCS)) 7328 skb->ip_summed = CHECKSUM_UNNECESSARY; 7329 7330 dev_dbg(ring->dev, "cksum success: bits %08X\n", 7331 le32_to_cpu(rx_desc->wb.upper.status_error)); 7332 } 7333 7334 static inline void igb_rx_hash(struct igb_ring *ring, 7335 union e1000_adv_rx_desc *rx_desc, 7336 struct sk_buff *skb) 7337 { 7338 if (ring->netdev->features & NETIF_F_RXHASH) 7339 skb_set_hash(skb, 7340 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 7341 PKT_HASH_TYPE_L3); 7342 } 7343 7344 /** 7345 * igb_is_non_eop - process handling of non-EOP buffers 7346 * @rx_ring: Rx ring being processed 7347 * @rx_desc: Rx descriptor for current buffer 7348 * @skb: current socket buffer containing buffer in progress 7349 * 7350 * This function updates next to clean. If the buffer is an EOP buffer 7351 * this function exits returning false, otherwise it will place the 7352 * sk_buff in the next buffer to be chained and return true indicating 7353 * that this is in fact a non-EOP buffer. 7354 **/ 7355 static bool igb_is_non_eop(struct igb_ring *rx_ring, 7356 union e1000_adv_rx_desc *rx_desc) 7357 { 7358 u32 ntc = rx_ring->next_to_clean + 1; 7359 7360 /* fetch, update, and store next to clean */ 7361 ntc = (ntc < rx_ring->count) ? ntc : 0; 7362 rx_ring->next_to_clean = ntc; 7363 7364 prefetch(IGB_RX_DESC(rx_ring, ntc)); 7365 7366 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 7367 return false; 7368 7369 return true; 7370 } 7371 7372 /** 7373 * igb_cleanup_headers - Correct corrupted or empty headers 7374 * @rx_ring: rx descriptor ring packet is being transacted on 7375 * @rx_desc: pointer to the EOP Rx descriptor 7376 * @skb: pointer to current skb being fixed 7377 * 7378 * Address the case where we are pulling data in on pages only 7379 * and as such no data is present in the skb header. 7380 * 7381 * In addition if skb is not at least 60 bytes we need to pad it so that 7382 * it is large enough to qualify as a valid Ethernet frame. 7383 * 7384 * Returns true if an error was encountered and skb was freed. 7385 **/ 7386 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 7387 union e1000_adv_rx_desc *rx_desc, 7388 struct sk_buff *skb) 7389 { 7390 if (unlikely((igb_test_staterr(rx_desc, 7391 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 7392 struct net_device *netdev = rx_ring->netdev; 7393 if (!(netdev->features & NETIF_F_RXALL)) { 7394 dev_kfree_skb_any(skb); 7395 return true; 7396 } 7397 } 7398 7399 /* if eth_skb_pad returns an error the skb was freed */ 7400 if (eth_skb_pad(skb)) 7401 return true; 7402 7403 return false; 7404 } 7405 7406 /** 7407 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 7408 * @rx_ring: rx descriptor ring packet is being transacted on 7409 * @rx_desc: pointer to the EOP Rx descriptor 7410 * @skb: pointer to current skb being populated 7411 * 7412 * This function checks the ring, descriptor, and packet information in 7413 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 7414 * other fields within the skb. 7415 **/ 7416 static void igb_process_skb_fields(struct igb_ring *rx_ring, 7417 union e1000_adv_rx_desc *rx_desc, 7418 struct sk_buff *skb) 7419 { 7420 struct net_device *dev = rx_ring->netdev; 7421 7422 igb_rx_hash(rx_ring, rx_desc, skb); 7423 7424 igb_rx_checksum(rx_ring, rx_desc, skb); 7425 7426 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 7427 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 7428 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 7429 7430 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 7431 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 7432 u16 vid; 7433 7434 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 7435 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 7436 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 7437 else 7438 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 7439 7440 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 7441 } 7442 7443 skb_record_rx_queue(skb, rx_ring->queue_index); 7444 7445 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 7446 } 7447 7448 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 7449 const unsigned int size) 7450 { 7451 struct igb_rx_buffer *rx_buffer; 7452 7453 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 7454 prefetchw(rx_buffer->page); 7455 7456 /* we are reusing so sync this buffer for CPU use */ 7457 dma_sync_single_range_for_cpu(rx_ring->dev, 7458 rx_buffer->dma, 7459 rx_buffer->page_offset, 7460 size, 7461 DMA_FROM_DEVICE); 7462 7463 rx_buffer->pagecnt_bias--; 7464 7465 return rx_buffer; 7466 } 7467 7468 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 7469 struct igb_rx_buffer *rx_buffer) 7470 { 7471 if (igb_can_reuse_rx_page(rx_buffer)) { 7472 /* hand second half of page back to the ring */ 7473 igb_reuse_rx_page(rx_ring, rx_buffer); 7474 } else { 7475 /* We are not reusing the buffer so unmap it and free 7476 * any references we are holding to it 7477 */ 7478 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 7479 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 7480 IGB_RX_DMA_ATTR); 7481 __page_frag_cache_drain(rx_buffer->page, 7482 rx_buffer->pagecnt_bias); 7483 } 7484 7485 /* clear contents of rx_buffer */ 7486 rx_buffer->page = NULL; 7487 } 7488 7489 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 7490 { 7491 struct igb_ring *rx_ring = q_vector->rx.ring; 7492 struct sk_buff *skb = rx_ring->skb; 7493 unsigned int total_bytes = 0, total_packets = 0; 7494 u16 cleaned_count = igb_desc_unused(rx_ring); 7495 7496 while (likely(total_packets < budget)) { 7497 union e1000_adv_rx_desc *rx_desc; 7498 struct igb_rx_buffer *rx_buffer; 7499 unsigned int size; 7500 7501 /* return some buffers to hardware, one at a time is too slow */ 7502 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 7503 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7504 cleaned_count = 0; 7505 } 7506 7507 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7508 size = le16_to_cpu(rx_desc->wb.upper.length); 7509 if (!size) 7510 break; 7511 7512 /* This memory barrier is needed to keep us from reading 7513 * any other fields out of the rx_desc until we know the 7514 * descriptor has been written back 7515 */ 7516 dma_rmb(); 7517 7518 rx_buffer = igb_get_rx_buffer(rx_ring, size); 7519 7520 /* retrieve a buffer from the ring */ 7521 if (skb) 7522 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 7523 else if (ring_uses_build_skb(rx_ring)) 7524 skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size); 7525 else 7526 skb = igb_construct_skb(rx_ring, rx_buffer, 7527 rx_desc, size); 7528 7529 /* exit if we failed to retrieve a buffer */ 7530 if (!skb) { 7531 rx_ring->rx_stats.alloc_failed++; 7532 rx_buffer->pagecnt_bias++; 7533 break; 7534 } 7535 7536 igb_put_rx_buffer(rx_ring, rx_buffer); 7537 cleaned_count++; 7538 7539 /* fetch next buffer in frame if non-eop */ 7540 if (igb_is_non_eop(rx_ring, rx_desc)) 7541 continue; 7542 7543 /* verify the packet layout is correct */ 7544 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7545 skb = NULL; 7546 continue; 7547 } 7548 7549 /* probably a little skewed due to removing CRC */ 7550 total_bytes += skb->len; 7551 7552 /* populate checksum, timestamp, VLAN, and protocol */ 7553 igb_process_skb_fields(rx_ring, rx_desc, skb); 7554 7555 napi_gro_receive(&q_vector->napi, skb); 7556 7557 /* reset skb pointer */ 7558 skb = NULL; 7559 7560 /* update budget accounting */ 7561 total_packets++; 7562 } 7563 7564 /* place incomplete frames back on ring for completion */ 7565 rx_ring->skb = skb; 7566 7567 u64_stats_update_begin(&rx_ring->rx_syncp); 7568 rx_ring->rx_stats.packets += total_packets; 7569 rx_ring->rx_stats.bytes += total_bytes; 7570 u64_stats_update_end(&rx_ring->rx_syncp); 7571 q_vector->rx.total_packets += total_packets; 7572 q_vector->rx.total_bytes += total_bytes; 7573 7574 if (cleaned_count) 7575 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7576 7577 return total_packets; 7578 } 7579 7580 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring) 7581 { 7582 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 7583 } 7584 7585 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7586 struct igb_rx_buffer *bi) 7587 { 7588 struct page *page = bi->page; 7589 dma_addr_t dma; 7590 7591 /* since we are recycling buffers we should seldom need to alloc */ 7592 if (likely(page)) 7593 return true; 7594 7595 /* alloc new page for storage */ 7596 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 7597 if (unlikely(!page)) { 7598 rx_ring->rx_stats.alloc_failed++; 7599 return false; 7600 } 7601 7602 /* map page for use */ 7603 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 7604 igb_rx_pg_size(rx_ring), 7605 DMA_FROM_DEVICE, 7606 IGB_RX_DMA_ATTR); 7607 7608 /* if mapping failed free memory back to system since 7609 * there isn't much point in holding memory we can't use 7610 */ 7611 if (dma_mapping_error(rx_ring->dev, dma)) { 7612 __free_pages(page, igb_rx_pg_order(rx_ring)); 7613 7614 rx_ring->rx_stats.alloc_failed++; 7615 return false; 7616 } 7617 7618 bi->dma = dma; 7619 bi->page = page; 7620 bi->page_offset = igb_rx_offset(rx_ring); 7621 bi->pagecnt_bias = 1; 7622 7623 return true; 7624 } 7625 7626 /** 7627 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7628 * @adapter: address of board private structure 7629 **/ 7630 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7631 { 7632 union e1000_adv_rx_desc *rx_desc; 7633 struct igb_rx_buffer *bi; 7634 u16 i = rx_ring->next_to_use; 7635 u16 bufsz; 7636 7637 /* nothing to do */ 7638 if (!cleaned_count) 7639 return; 7640 7641 rx_desc = IGB_RX_DESC(rx_ring, i); 7642 bi = &rx_ring->rx_buffer_info[i]; 7643 i -= rx_ring->count; 7644 7645 bufsz = igb_rx_bufsz(rx_ring); 7646 7647 do { 7648 if (!igb_alloc_mapped_page(rx_ring, bi)) 7649 break; 7650 7651 /* sync the buffer for use by the device */ 7652 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 7653 bi->page_offset, bufsz, 7654 DMA_FROM_DEVICE); 7655 7656 /* Refresh the desc even if buffer_addrs didn't change 7657 * because each write-back erases this info. 7658 */ 7659 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7660 7661 rx_desc++; 7662 bi++; 7663 i++; 7664 if (unlikely(!i)) { 7665 rx_desc = IGB_RX_DESC(rx_ring, 0); 7666 bi = rx_ring->rx_buffer_info; 7667 i -= rx_ring->count; 7668 } 7669 7670 /* clear the length for the next_to_use descriptor */ 7671 rx_desc->wb.upper.length = 0; 7672 7673 cleaned_count--; 7674 } while (cleaned_count); 7675 7676 i += rx_ring->count; 7677 7678 if (rx_ring->next_to_use != i) { 7679 /* record the next descriptor to use */ 7680 rx_ring->next_to_use = i; 7681 7682 /* update next to alloc since we have filled the ring */ 7683 rx_ring->next_to_alloc = i; 7684 7685 /* Force memory writes to complete before letting h/w 7686 * know there are new descriptors to fetch. (Only 7687 * applicable for weak-ordered memory model archs, 7688 * such as IA-64). 7689 */ 7690 wmb(); 7691 writel(i, rx_ring->tail); 7692 } 7693 } 7694 7695 /** 7696 * igb_mii_ioctl - 7697 * @netdev: 7698 * @ifreq: 7699 * @cmd: 7700 **/ 7701 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7702 { 7703 struct igb_adapter *adapter = netdev_priv(netdev); 7704 struct mii_ioctl_data *data = if_mii(ifr); 7705 7706 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7707 return -EOPNOTSUPP; 7708 7709 switch (cmd) { 7710 case SIOCGMIIPHY: 7711 data->phy_id = adapter->hw.phy.addr; 7712 break; 7713 case SIOCGMIIREG: 7714 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7715 &data->val_out)) 7716 return -EIO; 7717 break; 7718 case SIOCSMIIREG: 7719 default: 7720 return -EOPNOTSUPP; 7721 } 7722 return 0; 7723 } 7724 7725 /** 7726 * igb_ioctl - 7727 * @netdev: 7728 * @ifreq: 7729 * @cmd: 7730 **/ 7731 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7732 { 7733 switch (cmd) { 7734 case SIOCGMIIPHY: 7735 case SIOCGMIIREG: 7736 case SIOCSMIIREG: 7737 return igb_mii_ioctl(netdev, ifr, cmd); 7738 case SIOCGHWTSTAMP: 7739 return igb_ptp_get_ts_config(netdev, ifr); 7740 case SIOCSHWTSTAMP: 7741 return igb_ptp_set_ts_config(netdev, ifr); 7742 default: 7743 return -EOPNOTSUPP; 7744 } 7745 } 7746 7747 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7748 { 7749 struct igb_adapter *adapter = hw->back; 7750 7751 pci_read_config_word(adapter->pdev, reg, value); 7752 } 7753 7754 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 7755 { 7756 struct igb_adapter *adapter = hw->back; 7757 7758 pci_write_config_word(adapter->pdev, reg, *value); 7759 } 7760 7761 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7762 { 7763 struct igb_adapter *adapter = hw->back; 7764 7765 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7766 return -E1000_ERR_CONFIG; 7767 7768 return 0; 7769 } 7770 7771 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7772 { 7773 struct igb_adapter *adapter = hw->back; 7774 7775 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7776 return -E1000_ERR_CONFIG; 7777 7778 return 0; 7779 } 7780 7781 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7782 { 7783 struct igb_adapter *adapter = netdev_priv(netdev); 7784 struct e1000_hw *hw = &adapter->hw; 7785 u32 ctrl, rctl; 7786 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7787 7788 if (enable) { 7789 /* enable VLAN tag insert/strip */ 7790 ctrl = rd32(E1000_CTRL); 7791 ctrl |= E1000_CTRL_VME; 7792 wr32(E1000_CTRL, ctrl); 7793 7794 /* Disable CFI check */ 7795 rctl = rd32(E1000_RCTL); 7796 rctl &= ~E1000_RCTL_CFIEN; 7797 wr32(E1000_RCTL, rctl); 7798 } else { 7799 /* disable VLAN tag insert/strip */ 7800 ctrl = rd32(E1000_CTRL); 7801 ctrl &= ~E1000_CTRL_VME; 7802 wr32(E1000_CTRL, ctrl); 7803 } 7804 7805 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 7806 } 7807 7808 static int igb_vlan_rx_add_vid(struct net_device *netdev, 7809 __be16 proto, u16 vid) 7810 { 7811 struct igb_adapter *adapter = netdev_priv(netdev); 7812 struct e1000_hw *hw = &adapter->hw; 7813 int pf_id = adapter->vfs_allocated_count; 7814 7815 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7816 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7817 igb_vfta_set(hw, vid, pf_id, true, !!vid); 7818 7819 set_bit(vid, adapter->active_vlans); 7820 7821 return 0; 7822 } 7823 7824 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7825 __be16 proto, u16 vid) 7826 { 7827 struct igb_adapter *adapter = netdev_priv(netdev); 7828 int pf_id = adapter->vfs_allocated_count; 7829 struct e1000_hw *hw = &adapter->hw; 7830 7831 /* remove VID from filter table */ 7832 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7833 igb_vfta_set(hw, vid, pf_id, false, true); 7834 7835 clear_bit(vid, adapter->active_vlans); 7836 7837 return 0; 7838 } 7839 7840 static void igb_restore_vlan(struct igb_adapter *adapter) 7841 { 7842 u16 vid = 1; 7843 7844 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7845 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 7846 7847 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 7848 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7849 } 7850 7851 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7852 { 7853 struct pci_dev *pdev = adapter->pdev; 7854 struct e1000_mac_info *mac = &adapter->hw.mac; 7855 7856 mac->autoneg = 0; 7857 7858 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7859 * for the switch() below to work 7860 */ 7861 if ((spd & 1) || (dplx & ~1)) 7862 goto err_inval; 7863 7864 /* Fiber NIC's only allow 1000 gbps Full duplex 7865 * and 100Mbps Full duplex for 100baseFx sfp 7866 */ 7867 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7868 switch (spd + dplx) { 7869 case SPEED_10 + DUPLEX_HALF: 7870 case SPEED_10 + DUPLEX_FULL: 7871 case SPEED_100 + DUPLEX_HALF: 7872 goto err_inval; 7873 default: 7874 break; 7875 } 7876 } 7877 7878 switch (spd + dplx) { 7879 case SPEED_10 + DUPLEX_HALF: 7880 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7881 break; 7882 case SPEED_10 + DUPLEX_FULL: 7883 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7884 break; 7885 case SPEED_100 + DUPLEX_HALF: 7886 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7887 break; 7888 case SPEED_100 + DUPLEX_FULL: 7889 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7890 break; 7891 case SPEED_1000 + DUPLEX_FULL: 7892 mac->autoneg = 1; 7893 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7894 break; 7895 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7896 default: 7897 goto err_inval; 7898 } 7899 7900 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7901 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7902 7903 return 0; 7904 7905 err_inval: 7906 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7907 return -EINVAL; 7908 } 7909 7910 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7911 bool runtime) 7912 { 7913 struct net_device *netdev = pci_get_drvdata(pdev); 7914 struct igb_adapter *adapter = netdev_priv(netdev); 7915 struct e1000_hw *hw = &adapter->hw; 7916 u32 ctrl, rctl, status; 7917 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7918 #ifdef CONFIG_PM 7919 int retval = 0; 7920 #endif 7921 7922 rtnl_lock(); 7923 netif_device_detach(netdev); 7924 7925 if (netif_running(netdev)) 7926 __igb_close(netdev, true); 7927 7928 igb_ptp_suspend(adapter); 7929 7930 igb_clear_interrupt_scheme(adapter); 7931 rtnl_unlock(); 7932 7933 #ifdef CONFIG_PM 7934 retval = pci_save_state(pdev); 7935 if (retval) 7936 return retval; 7937 #endif 7938 7939 status = rd32(E1000_STATUS); 7940 if (status & E1000_STATUS_LU) 7941 wufc &= ~E1000_WUFC_LNKC; 7942 7943 if (wufc) { 7944 igb_setup_rctl(adapter); 7945 igb_set_rx_mode(netdev); 7946 7947 /* turn on all-multi mode if wake on multicast is enabled */ 7948 if (wufc & E1000_WUFC_MC) { 7949 rctl = rd32(E1000_RCTL); 7950 rctl |= E1000_RCTL_MPE; 7951 wr32(E1000_RCTL, rctl); 7952 } 7953 7954 ctrl = rd32(E1000_CTRL); 7955 /* advertise wake from D3Cold */ 7956 #define E1000_CTRL_ADVD3WUC 0x00100000 7957 /* phy power management enable */ 7958 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7959 ctrl |= E1000_CTRL_ADVD3WUC; 7960 wr32(E1000_CTRL, ctrl); 7961 7962 /* Allow time for pending master requests to run */ 7963 igb_disable_pcie_master(hw); 7964 7965 wr32(E1000_WUC, E1000_WUC_PME_EN); 7966 wr32(E1000_WUFC, wufc); 7967 } else { 7968 wr32(E1000_WUC, 0); 7969 wr32(E1000_WUFC, 0); 7970 } 7971 7972 *enable_wake = wufc || adapter->en_mng_pt; 7973 if (!*enable_wake) 7974 igb_power_down_link(adapter); 7975 else 7976 igb_power_up_link(adapter); 7977 7978 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7979 * would have already happened in close and is redundant. 7980 */ 7981 igb_release_hw_control(adapter); 7982 7983 pci_disable_device(pdev); 7984 7985 return 0; 7986 } 7987 7988 static void igb_deliver_wake_packet(struct net_device *netdev) 7989 { 7990 struct igb_adapter *adapter = netdev_priv(netdev); 7991 struct e1000_hw *hw = &adapter->hw; 7992 struct sk_buff *skb; 7993 u32 wupl; 7994 7995 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 7996 7997 /* WUPM stores only the first 128 bytes of the wake packet. 7998 * Read the packet only if we have the whole thing. 7999 */ 8000 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 8001 return; 8002 8003 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 8004 if (!skb) 8005 return; 8006 8007 skb_put(skb, wupl); 8008 8009 /* Ensure reads are 32-bit aligned */ 8010 wupl = roundup(wupl, 4); 8011 8012 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 8013 8014 skb->protocol = eth_type_trans(skb, netdev); 8015 netif_rx(skb); 8016 } 8017 8018 #ifdef CONFIG_PM 8019 #ifdef CONFIG_PM_SLEEP 8020 static int igb_suspend(struct device *dev) 8021 { 8022 int retval; 8023 bool wake; 8024 struct pci_dev *pdev = to_pci_dev(dev); 8025 8026 retval = __igb_shutdown(pdev, &wake, 0); 8027 if (retval) 8028 return retval; 8029 8030 if (wake) { 8031 pci_prepare_to_sleep(pdev); 8032 } else { 8033 pci_wake_from_d3(pdev, false); 8034 pci_set_power_state(pdev, PCI_D3hot); 8035 } 8036 8037 return 0; 8038 } 8039 #endif /* CONFIG_PM_SLEEP */ 8040 8041 static int igb_resume(struct device *dev) 8042 { 8043 struct pci_dev *pdev = to_pci_dev(dev); 8044 struct net_device *netdev = pci_get_drvdata(pdev); 8045 struct igb_adapter *adapter = netdev_priv(netdev); 8046 struct e1000_hw *hw = &adapter->hw; 8047 u32 err, val; 8048 8049 pci_set_power_state(pdev, PCI_D0); 8050 pci_restore_state(pdev); 8051 pci_save_state(pdev); 8052 8053 if (!pci_device_is_present(pdev)) 8054 return -ENODEV; 8055 err = pci_enable_device_mem(pdev); 8056 if (err) { 8057 dev_err(&pdev->dev, 8058 "igb: Cannot enable PCI device from suspend\n"); 8059 return err; 8060 } 8061 pci_set_master(pdev); 8062 8063 pci_enable_wake(pdev, PCI_D3hot, 0); 8064 pci_enable_wake(pdev, PCI_D3cold, 0); 8065 8066 if (igb_init_interrupt_scheme(adapter, true)) { 8067 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8068 return -ENOMEM; 8069 } 8070 8071 igb_reset(adapter); 8072 8073 /* let the f/w know that the h/w is now under the control of the 8074 * driver. 8075 */ 8076 igb_get_hw_control(adapter); 8077 8078 val = rd32(E1000_WUS); 8079 if (val & WAKE_PKT_WUS) 8080 igb_deliver_wake_packet(netdev); 8081 8082 wr32(E1000_WUS, ~0); 8083 8084 rtnl_lock(); 8085 if (!err && netif_running(netdev)) 8086 err = __igb_open(netdev, true); 8087 8088 if (!err) 8089 netif_device_attach(netdev); 8090 rtnl_unlock(); 8091 8092 return err; 8093 } 8094 8095 static int igb_runtime_idle(struct device *dev) 8096 { 8097 struct pci_dev *pdev = to_pci_dev(dev); 8098 struct net_device *netdev = pci_get_drvdata(pdev); 8099 struct igb_adapter *adapter = netdev_priv(netdev); 8100 8101 if (!igb_has_link(adapter)) 8102 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 8103 8104 return -EBUSY; 8105 } 8106 8107 static int igb_runtime_suspend(struct device *dev) 8108 { 8109 struct pci_dev *pdev = to_pci_dev(dev); 8110 int retval; 8111 bool wake; 8112 8113 retval = __igb_shutdown(pdev, &wake, 1); 8114 if (retval) 8115 return retval; 8116 8117 if (wake) { 8118 pci_prepare_to_sleep(pdev); 8119 } else { 8120 pci_wake_from_d3(pdev, false); 8121 pci_set_power_state(pdev, PCI_D3hot); 8122 } 8123 8124 return 0; 8125 } 8126 8127 static int igb_runtime_resume(struct device *dev) 8128 { 8129 return igb_resume(dev); 8130 } 8131 #endif /* CONFIG_PM */ 8132 8133 static void igb_shutdown(struct pci_dev *pdev) 8134 { 8135 bool wake; 8136 8137 __igb_shutdown(pdev, &wake, 0); 8138 8139 if (system_state == SYSTEM_POWER_OFF) { 8140 pci_wake_from_d3(pdev, wake); 8141 pci_set_power_state(pdev, PCI_D3hot); 8142 } 8143 } 8144 8145 #ifdef CONFIG_PCI_IOV 8146 static int igb_sriov_reinit(struct pci_dev *dev) 8147 { 8148 struct net_device *netdev = pci_get_drvdata(dev); 8149 struct igb_adapter *adapter = netdev_priv(netdev); 8150 struct pci_dev *pdev = adapter->pdev; 8151 8152 rtnl_lock(); 8153 8154 if (netif_running(netdev)) 8155 igb_close(netdev); 8156 else 8157 igb_reset(adapter); 8158 8159 igb_clear_interrupt_scheme(adapter); 8160 8161 igb_init_queue_configuration(adapter); 8162 8163 if (igb_init_interrupt_scheme(adapter, true)) { 8164 rtnl_unlock(); 8165 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8166 return -ENOMEM; 8167 } 8168 8169 if (netif_running(netdev)) 8170 igb_open(netdev); 8171 8172 rtnl_unlock(); 8173 8174 return 0; 8175 } 8176 8177 static int igb_pci_disable_sriov(struct pci_dev *dev) 8178 { 8179 int err = igb_disable_sriov(dev); 8180 8181 if (!err) 8182 err = igb_sriov_reinit(dev); 8183 8184 return err; 8185 } 8186 8187 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 8188 { 8189 int err = igb_enable_sriov(dev, num_vfs); 8190 8191 if (err) 8192 goto out; 8193 8194 err = igb_sriov_reinit(dev); 8195 if (!err) 8196 return num_vfs; 8197 8198 out: 8199 return err; 8200 } 8201 8202 #endif 8203 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 8204 { 8205 #ifdef CONFIG_PCI_IOV 8206 if (num_vfs == 0) 8207 return igb_pci_disable_sriov(dev); 8208 else 8209 return igb_pci_enable_sriov(dev, num_vfs); 8210 #endif 8211 return 0; 8212 } 8213 8214 #ifdef CONFIG_NET_POLL_CONTROLLER 8215 /* Polling 'interrupt' - used by things like netconsole to send skbs 8216 * without having to re-enable interrupts. It's not called while 8217 * the interrupt routine is executing. 8218 */ 8219 static void igb_netpoll(struct net_device *netdev) 8220 { 8221 struct igb_adapter *adapter = netdev_priv(netdev); 8222 struct e1000_hw *hw = &adapter->hw; 8223 struct igb_q_vector *q_vector; 8224 int i; 8225 8226 for (i = 0; i < adapter->num_q_vectors; i++) { 8227 q_vector = adapter->q_vector[i]; 8228 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8229 wr32(E1000_EIMC, q_vector->eims_value); 8230 else 8231 igb_irq_disable(adapter); 8232 napi_schedule(&q_vector->napi); 8233 } 8234 } 8235 #endif /* CONFIG_NET_POLL_CONTROLLER */ 8236 8237 /** 8238 * igb_io_error_detected - called when PCI error is detected 8239 * @pdev: Pointer to PCI device 8240 * @state: The current pci connection state 8241 * 8242 * This function is called after a PCI bus error affecting 8243 * this device has been detected. 8244 **/ 8245 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 8246 pci_channel_state_t state) 8247 { 8248 struct net_device *netdev = pci_get_drvdata(pdev); 8249 struct igb_adapter *adapter = netdev_priv(netdev); 8250 8251 netif_device_detach(netdev); 8252 8253 if (state == pci_channel_io_perm_failure) 8254 return PCI_ERS_RESULT_DISCONNECT; 8255 8256 if (netif_running(netdev)) 8257 igb_down(adapter); 8258 pci_disable_device(pdev); 8259 8260 /* Request a slot slot reset. */ 8261 return PCI_ERS_RESULT_NEED_RESET; 8262 } 8263 8264 /** 8265 * igb_io_slot_reset - called after the pci bus has been reset. 8266 * @pdev: Pointer to PCI device 8267 * 8268 * Restart the card from scratch, as if from a cold-boot. Implementation 8269 * resembles the first-half of the igb_resume routine. 8270 **/ 8271 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 8272 { 8273 struct net_device *netdev = pci_get_drvdata(pdev); 8274 struct igb_adapter *adapter = netdev_priv(netdev); 8275 struct e1000_hw *hw = &adapter->hw; 8276 pci_ers_result_t result; 8277 int err; 8278 8279 if (pci_enable_device_mem(pdev)) { 8280 dev_err(&pdev->dev, 8281 "Cannot re-enable PCI device after reset.\n"); 8282 result = PCI_ERS_RESULT_DISCONNECT; 8283 } else { 8284 pci_set_master(pdev); 8285 pci_restore_state(pdev); 8286 pci_save_state(pdev); 8287 8288 pci_enable_wake(pdev, PCI_D3hot, 0); 8289 pci_enable_wake(pdev, PCI_D3cold, 0); 8290 8291 /* In case of PCI error, adapter lose its HW address 8292 * so we should re-assign it here. 8293 */ 8294 hw->hw_addr = adapter->io_addr; 8295 8296 igb_reset(adapter); 8297 wr32(E1000_WUS, ~0); 8298 result = PCI_ERS_RESULT_RECOVERED; 8299 } 8300 8301 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8302 if (err) { 8303 dev_err(&pdev->dev, 8304 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8305 err); 8306 /* non-fatal, continue */ 8307 } 8308 8309 return result; 8310 } 8311 8312 /** 8313 * igb_io_resume - called when traffic can start flowing again. 8314 * @pdev: Pointer to PCI device 8315 * 8316 * This callback is called when the error recovery driver tells us that 8317 * its OK to resume normal operation. Implementation resembles the 8318 * second-half of the igb_resume routine. 8319 */ 8320 static void igb_io_resume(struct pci_dev *pdev) 8321 { 8322 struct net_device *netdev = pci_get_drvdata(pdev); 8323 struct igb_adapter *adapter = netdev_priv(netdev); 8324 8325 if (netif_running(netdev)) { 8326 if (igb_up(adapter)) { 8327 dev_err(&pdev->dev, "igb_up failed after reset\n"); 8328 return; 8329 } 8330 } 8331 8332 netif_device_attach(netdev); 8333 8334 /* let the f/w know that the h/w is now under the control of the 8335 * driver. 8336 */ 8337 igb_get_hw_control(adapter); 8338 } 8339 8340 /** 8341 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 8342 * @adapter: Pointer to adapter structure 8343 * @index: Index of the RAR entry which need to be synced with MAC table 8344 **/ 8345 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 8346 { 8347 struct e1000_hw *hw = &adapter->hw; 8348 u32 rar_low, rar_high; 8349 u8 *addr = adapter->mac_table[index].addr; 8350 8351 /* HW expects these to be in network order when they are plugged 8352 * into the registers which are little endian. In order to guarantee 8353 * that ordering we need to do an leXX_to_cpup here in order to be 8354 * ready for the byteswap that occurs with writel 8355 */ 8356 rar_low = le32_to_cpup((__le32 *)(addr)); 8357 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 8358 8359 /* Indicate to hardware the Address is Valid. */ 8360 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 8361 rar_high |= E1000_RAH_AV; 8362 8363 if (hw->mac.type == e1000_82575) 8364 rar_high |= E1000_RAH_POOL_1 * 8365 adapter->mac_table[index].queue; 8366 else 8367 rar_high |= E1000_RAH_POOL_1 << 8368 adapter->mac_table[index].queue; 8369 } 8370 8371 wr32(E1000_RAL(index), rar_low); 8372 wrfl(); 8373 wr32(E1000_RAH(index), rar_high); 8374 wrfl(); 8375 } 8376 8377 static int igb_set_vf_mac(struct igb_adapter *adapter, 8378 int vf, unsigned char *mac_addr) 8379 { 8380 struct e1000_hw *hw = &adapter->hw; 8381 /* VF MAC addresses start at end of receive addresses and moves 8382 * towards the first, as a result a collision should not be possible 8383 */ 8384 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 8385 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 8386 8387 ether_addr_copy(vf_mac_addr, mac_addr); 8388 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 8389 adapter->mac_table[rar_entry].queue = vf; 8390 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 8391 igb_rar_set_index(adapter, rar_entry); 8392 8393 return 0; 8394 } 8395 8396 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 8397 { 8398 struct igb_adapter *adapter = netdev_priv(netdev); 8399 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 8400 return -EINVAL; 8401 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 8402 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 8403 dev_info(&adapter->pdev->dev, 8404 "Reload the VF driver to make this change effective."); 8405 if (test_bit(__IGB_DOWN, &adapter->state)) { 8406 dev_warn(&adapter->pdev->dev, 8407 "The VF MAC address has been set, but the PF device is not up.\n"); 8408 dev_warn(&adapter->pdev->dev, 8409 "Bring the PF device up before attempting to use the VF device.\n"); 8410 } 8411 return igb_set_vf_mac(adapter, vf, mac); 8412 } 8413 8414 static int igb_link_mbps(int internal_link_speed) 8415 { 8416 switch (internal_link_speed) { 8417 case SPEED_100: 8418 return 100; 8419 case SPEED_1000: 8420 return 1000; 8421 default: 8422 return 0; 8423 } 8424 } 8425 8426 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 8427 int link_speed) 8428 { 8429 int rf_dec, rf_int; 8430 u32 bcnrc_val; 8431 8432 if (tx_rate != 0) { 8433 /* Calculate the rate factor values to set */ 8434 rf_int = link_speed / tx_rate; 8435 rf_dec = (link_speed - (rf_int * tx_rate)); 8436 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 8437 tx_rate; 8438 8439 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 8440 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 8441 E1000_RTTBCNRC_RF_INT_MASK); 8442 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 8443 } else { 8444 bcnrc_val = 0; 8445 } 8446 8447 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 8448 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 8449 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 8450 */ 8451 wr32(E1000_RTTBCNRM, 0x14); 8452 wr32(E1000_RTTBCNRC, bcnrc_val); 8453 } 8454 8455 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 8456 { 8457 int actual_link_speed, i; 8458 bool reset_rate = false; 8459 8460 /* VF TX rate limit was not set or not supported */ 8461 if ((adapter->vf_rate_link_speed == 0) || 8462 (adapter->hw.mac.type != e1000_82576)) 8463 return; 8464 8465 actual_link_speed = igb_link_mbps(adapter->link_speed); 8466 if (actual_link_speed != adapter->vf_rate_link_speed) { 8467 reset_rate = true; 8468 adapter->vf_rate_link_speed = 0; 8469 dev_info(&adapter->pdev->dev, 8470 "Link speed has been changed. VF Transmit rate is disabled\n"); 8471 } 8472 8473 for (i = 0; i < adapter->vfs_allocated_count; i++) { 8474 if (reset_rate) 8475 adapter->vf_data[i].tx_rate = 0; 8476 8477 igb_set_vf_rate_limit(&adapter->hw, i, 8478 adapter->vf_data[i].tx_rate, 8479 actual_link_speed); 8480 } 8481 } 8482 8483 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 8484 int min_tx_rate, int max_tx_rate) 8485 { 8486 struct igb_adapter *adapter = netdev_priv(netdev); 8487 struct e1000_hw *hw = &adapter->hw; 8488 int actual_link_speed; 8489 8490 if (hw->mac.type != e1000_82576) 8491 return -EOPNOTSUPP; 8492 8493 if (min_tx_rate) 8494 return -EINVAL; 8495 8496 actual_link_speed = igb_link_mbps(adapter->link_speed); 8497 if ((vf >= adapter->vfs_allocated_count) || 8498 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 8499 (max_tx_rate < 0) || 8500 (max_tx_rate > actual_link_speed)) 8501 return -EINVAL; 8502 8503 adapter->vf_rate_link_speed = actual_link_speed; 8504 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 8505 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 8506 8507 return 0; 8508 } 8509 8510 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 8511 bool setting) 8512 { 8513 struct igb_adapter *adapter = netdev_priv(netdev); 8514 struct e1000_hw *hw = &adapter->hw; 8515 u32 reg_val, reg_offset; 8516 8517 if (!adapter->vfs_allocated_count) 8518 return -EOPNOTSUPP; 8519 8520 if (vf >= adapter->vfs_allocated_count) 8521 return -EINVAL; 8522 8523 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 8524 reg_val = rd32(reg_offset); 8525 if (setting) 8526 reg_val |= (BIT(vf) | 8527 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8528 else 8529 reg_val &= ~(BIT(vf) | 8530 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 8531 wr32(reg_offset, reg_val); 8532 8533 adapter->vf_data[vf].spoofchk_enabled = setting; 8534 return 0; 8535 } 8536 8537 static int igb_ndo_get_vf_config(struct net_device *netdev, 8538 int vf, struct ifla_vf_info *ivi) 8539 { 8540 struct igb_adapter *adapter = netdev_priv(netdev); 8541 if (vf >= adapter->vfs_allocated_count) 8542 return -EINVAL; 8543 ivi->vf = vf; 8544 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 8545 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 8546 ivi->min_tx_rate = 0; 8547 ivi->vlan = adapter->vf_data[vf].pf_vlan; 8548 ivi->qos = adapter->vf_data[vf].pf_qos; 8549 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 8550 return 0; 8551 } 8552 8553 static void igb_vmm_control(struct igb_adapter *adapter) 8554 { 8555 struct e1000_hw *hw = &adapter->hw; 8556 u32 reg; 8557 8558 switch (hw->mac.type) { 8559 case e1000_82575: 8560 case e1000_i210: 8561 case e1000_i211: 8562 case e1000_i354: 8563 default: 8564 /* replication is not supported for 82575 */ 8565 return; 8566 case e1000_82576: 8567 /* notify HW that the MAC is adding vlan tags */ 8568 reg = rd32(E1000_DTXCTL); 8569 reg |= E1000_DTXCTL_VLAN_ADDED; 8570 wr32(E1000_DTXCTL, reg); 8571 /* Fall through */ 8572 case e1000_82580: 8573 /* enable replication vlan tag stripping */ 8574 reg = rd32(E1000_RPLOLR); 8575 reg |= E1000_RPLOLR_STRVLAN; 8576 wr32(E1000_RPLOLR, reg); 8577 /* Fall through */ 8578 case e1000_i350: 8579 /* none of the above registers are supported by i350 */ 8580 break; 8581 } 8582 8583 if (adapter->vfs_allocated_count) { 8584 igb_vmdq_set_loopback_pf(hw, true); 8585 igb_vmdq_set_replication_pf(hw, true); 8586 igb_vmdq_set_anti_spoofing_pf(hw, true, 8587 adapter->vfs_allocated_count); 8588 } else { 8589 igb_vmdq_set_loopback_pf(hw, false); 8590 igb_vmdq_set_replication_pf(hw, false); 8591 } 8592 } 8593 8594 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 8595 { 8596 struct e1000_hw *hw = &adapter->hw; 8597 u32 dmac_thr; 8598 u16 hwm; 8599 8600 if (hw->mac.type > e1000_82580) { 8601 if (adapter->flags & IGB_FLAG_DMAC) { 8602 u32 reg; 8603 8604 /* force threshold to 0. */ 8605 wr32(E1000_DMCTXTH, 0); 8606 8607 /* DMA Coalescing high water mark needs to be greater 8608 * than the Rx threshold. Set hwm to PBA - max frame 8609 * size in 16B units, capping it at PBA - 6KB. 8610 */ 8611 hwm = 64 * (pba - 6); 8612 reg = rd32(E1000_FCRTC); 8613 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8614 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8615 & E1000_FCRTC_RTH_COAL_MASK); 8616 wr32(E1000_FCRTC, reg); 8617 8618 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8619 * frame size, capping it at PBA - 10KB. 8620 */ 8621 dmac_thr = pba - 10; 8622 reg = rd32(E1000_DMACR); 8623 reg &= ~E1000_DMACR_DMACTHR_MASK; 8624 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8625 & E1000_DMACR_DMACTHR_MASK); 8626 8627 /* transition to L0x or L1 if available..*/ 8628 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8629 8630 /* watchdog timer= +-1000 usec in 32usec intervals */ 8631 reg |= (1000 >> 5); 8632 8633 /* Disable BMC-to-OS Watchdog Enable */ 8634 if (hw->mac.type != e1000_i354) 8635 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8636 8637 wr32(E1000_DMACR, reg); 8638 8639 /* no lower threshold to disable 8640 * coalescing(smart fifb)-UTRESH=0 8641 */ 8642 wr32(E1000_DMCRTRH, 0); 8643 8644 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8645 8646 wr32(E1000_DMCTLX, reg); 8647 8648 /* free space in tx packet buffer to wake from 8649 * DMA coal 8650 */ 8651 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8652 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8653 8654 /* make low power state decision controlled 8655 * by DMA coal 8656 */ 8657 reg = rd32(E1000_PCIEMISC); 8658 reg &= ~E1000_PCIEMISC_LX_DECISION; 8659 wr32(E1000_PCIEMISC, reg); 8660 } /* endif adapter->dmac is not disabled */ 8661 } else if (hw->mac.type == e1000_82580) { 8662 u32 reg = rd32(E1000_PCIEMISC); 8663 8664 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8665 wr32(E1000_DMACR, 0); 8666 } 8667 } 8668 8669 /** 8670 * igb_read_i2c_byte - Reads 8 bit word over I2C 8671 * @hw: pointer to hardware structure 8672 * @byte_offset: byte offset to read 8673 * @dev_addr: device address 8674 * @data: value read 8675 * 8676 * Performs byte read operation over I2C interface at 8677 * a specified device address. 8678 **/ 8679 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8680 u8 dev_addr, u8 *data) 8681 { 8682 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8683 struct i2c_client *this_client = adapter->i2c_client; 8684 s32 status; 8685 u16 swfw_mask = 0; 8686 8687 if (!this_client) 8688 return E1000_ERR_I2C; 8689 8690 swfw_mask = E1000_SWFW_PHY0_SM; 8691 8692 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8693 return E1000_ERR_SWFW_SYNC; 8694 8695 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8696 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8697 8698 if (status < 0) 8699 return E1000_ERR_I2C; 8700 else { 8701 *data = status; 8702 return 0; 8703 } 8704 } 8705 8706 /** 8707 * igb_write_i2c_byte - Writes 8 bit word over I2C 8708 * @hw: pointer to hardware structure 8709 * @byte_offset: byte offset to write 8710 * @dev_addr: device address 8711 * @data: value to write 8712 * 8713 * Performs byte write operation over I2C interface at 8714 * a specified device address. 8715 **/ 8716 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8717 u8 dev_addr, u8 data) 8718 { 8719 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8720 struct i2c_client *this_client = adapter->i2c_client; 8721 s32 status; 8722 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8723 8724 if (!this_client) 8725 return E1000_ERR_I2C; 8726 8727 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 8728 return E1000_ERR_SWFW_SYNC; 8729 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8730 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8731 8732 if (status) 8733 return E1000_ERR_I2C; 8734 else 8735 return 0; 8736 8737 } 8738 8739 int igb_reinit_queues(struct igb_adapter *adapter) 8740 { 8741 struct net_device *netdev = adapter->netdev; 8742 struct pci_dev *pdev = adapter->pdev; 8743 int err = 0; 8744 8745 if (netif_running(netdev)) 8746 igb_close(netdev); 8747 8748 igb_reset_interrupt_capability(adapter); 8749 8750 if (igb_init_interrupt_scheme(adapter, true)) { 8751 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8752 return -ENOMEM; 8753 } 8754 8755 if (netif_running(netdev)) 8756 err = igb_open(netdev); 8757 8758 return err; 8759 } 8760 8761 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 8762 { 8763 struct igb_nfc_filter *rule; 8764 8765 spin_lock(&adapter->nfc_lock); 8766 8767 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8768 igb_erase_filter(adapter, rule); 8769 8770 spin_unlock(&adapter->nfc_lock); 8771 } 8772 8773 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 8774 { 8775 struct igb_nfc_filter *rule; 8776 8777 spin_lock(&adapter->nfc_lock); 8778 8779 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 8780 igb_add_filter(adapter, rule); 8781 8782 spin_unlock(&adapter->nfc_lock); 8783 } 8784 /* igb_main.c */ 8785