1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/aer.h> 32 #include <linux/prefetch.h> 33 #include <linux/bpf.h> 34 #include <linux/bpf_trace.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/etherdevice.h> 37 #ifdef CONFIG_IGB_DCA 38 #include <linux/dca.h> 39 #endif 40 #include <linux/i2c.h> 41 #include "igb.h" 42 43 enum queue_mode { 44 QUEUE_MODE_STRICT_PRIORITY, 45 QUEUE_MODE_STREAM_RESERVATION, 46 }; 47 48 enum tx_queue_prio { 49 TX_QUEUE_PRIO_HIGH, 50 TX_QUEUE_PRIO_LOW, 51 }; 52 53 char igb_driver_name[] = "igb"; 54 static const char igb_driver_string[] = 55 "Intel(R) Gigabit Ethernet Network Driver"; 56 static const char igb_copyright[] = 57 "Copyright (c) 2007-2014 Intel Corporation."; 58 59 static const struct e1000_info *igb_info_tbl[] = { 60 [board_82575] = &e1000_82575_info, 61 }; 62 63 static const struct pci_device_id igb_pci_tbl[] = { 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 99 /* required last entry */ 100 {0, } 101 }; 102 103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 104 105 static int igb_setup_all_tx_resources(struct igb_adapter *); 106 static int igb_setup_all_rx_resources(struct igb_adapter *); 107 static void igb_free_all_tx_resources(struct igb_adapter *); 108 static void igb_free_all_rx_resources(struct igb_adapter *); 109 static void igb_setup_mrqc(struct igb_adapter *); 110 static int igb_probe(struct pci_dev *, const struct pci_device_id *); 111 static void igb_remove(struct pci_dev *pdev); 112 static int igb_sw_init(struct igb_adapter *); 113 int igb_open(struct net_device *); 114 int igb_close(struct net_device *); 115 static void igb_configure(struct igb_adapter *); 116 static void igb_configure_tx(struct igb_adapter *); 117 static void igb_configure_rx(struct igb_adapter *); 118 static void igb_clean_all_tx_rings(struct igb_adapter *); 119 static void igb_clean_all_rx_rings(struct igb_adapter *); 120 static void igb_clean_tx_ring(struct igb_ring *); 121 static void igb_clean_rx_ring(struct igb_ring *); 122 static void igb_set_rx_mode(struct net_device *); 123 static void igb_update_phy_info(struct timer_list *); 124 static void igb_watchdog(struct timer_list *); 125 static void igb_watchdog_task(struct work_struct *); 126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 127 static void igb_get_stats64(struct net_device *dev, 128 struct rtnl_link_stats64 *stats); 129 static int igb_change_mtu(struct net_device *, int); 130 static int igb_set_mac(struct net_device *, void *); 131 static void igb_set_uta(struct igb_adapter *adapter, bool set); 132 static irqreturn_t igb_intr(int irq, void *); 133 static irqreturn_t igb_intr_msi(int irq, void *); 134 static irqreturn_t igb_msix_other(int irq, void *); 135 static irqreturn_t igb_msix_ring(int irq, void *); 136 #ifdef CONFIG_IGB_DCA 137 static void igb_update_dca(struct igb_q_vector *); 138 static void igb_setup_dca(struct igb_adapter *); 139 #endif /* CONFIG_IGB_DCA */ 140 static int igb_poll(struct napi_struct *, int); 141 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 142 static int igb_clean_rx_irq(struct igb_q_vector *, int); 143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 145 static void igb_reset_task(struct work_struct *); 146 static void igb_vlan_mode(struct net_device *netdev, 147 netdev_features_t features); 148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 150 static void igb_restore_vlan(struct igb_adapter *); 151 static void igb_rar_set_index(struct igb_adapter *, u32); 152 static void igb_ping_all_vfs(struct igb_adapter *); 153 static void igb_msg_task(struct igb_adapter *); 154 static void igb_vmm_control(struct igb_adapter *); 155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 156 static void igb_flush_mac_table(struct igb_adapter *); 157 static int igb_available_rars(struct igb_adapter *, u8); 158 static void igb_set_default_mac_filter(struct igb_adapter *); 159 static int igb_uc_sync(struct net_device *, const unsigned char *); 160 static int igb_uc_unsync(struct net_device *, const unsigned char *); 161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 163 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 164 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 167 bool setting); 168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 169 bool setting); 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 171 struct ifla_vf_info *ivi); 172 static void igb_check_vf_rate_limit(struct igb_adapter *); 173 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 174 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 175 176 #ifdef CONFIG_PCI_IOV 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 179 static int igb_disable_sriov(struct pci_dev *dev); 180 static int igb_pci_disable_sriov(struct pci_dev *dev); 181 #endif 182 183 static int igb_suspend(struct device *); 184 static int igb_resume(struct device *); 185 static int igb_runtime_suspend(struct device *dev); 186 static int igb_runtime_resume(struct device *dev); 187 static int igb_runtime_idle(struct device *dev); 188 static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192 }; 193 static void igb_shutdown(struct pci_dev *); 194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 195 #ifdef CONFIG_IGB_DCA 196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197 static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201 }; 202 #endif 203 #ifdef CONFIG_PCI_IOV 204 static unsigned int max_vfs; 205 module_param(max_vfs, uint, 0); 206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 207 #endif /* CONFIG_PCI_IOV */ 208 209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 210 pci_channel_state_t); 211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 212 static void igb_io_resume(struct pci_dev *); 213 214 static const struct pci_error_handlers igb_err_handler = { 215 .error_detected = igb_io_error_detected, 216 .slot_reset = igb_io_slot_reset, 217 .resume = igb_io_resume, 218 }; 219 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 221 222 static struct pci_driver igb_driver = { 223 .name = igb_driver_name, 224 .id_table = igb_pci_tbl, 225 .probe = igb_probe, 226 .remove = igb_remove, 227 #ifdef CONFIG_PM 228 .driver.pm = &igb_pm_ops, 229 #endif 230 .shutdown = igb_shutdown, 231 .sriov_configure = igb_pci_sriov_configure, 232 .err_handler = &igb_err_handler 233 }; 234 235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 237 MODULE_LICENSE("GPL v2"); 238 239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 240 static int debug = -1; 241 module_param(debug, int, 0); 242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 243 244 struct igb_reg_info { 245 u32 ofs; 246 char *name; 247 }; 248 249 static const struct igb_reg_info igb_reg_info_tbl[] = { 250 251 /* General Registers */ 252 {E1000_CTRL, "CTRL"}, 253 {E1000_STATUS, "STATUS"}, 254 {E1000_CTRL_EXT, "CTRL_EXT"}, 255 256 /* Interrupt Registers */ 257 {E1000_ICR, "ICR"}, 258 259 /* RX Registers */ 260 {E1000_RCTL, "RCTL"}, 261 {E1000_RDLEN(0), "RDLEN"}, 262 {E1000_RDH(0), "RDH"}, 263 {E1000_RDT(0), "RDT"}, 264 {E1000_RXDCTL(0), "RXDCTL"}, 265 {E1000_RDBAL(0), "RDBAL"}, 266 {E1000_RDBAH(0), "RDBAH"}, 267 268 /* TX Registers */ 269 {E1000_TCTL, "TCTL"}, 270 {E1000_TDBAL(0), "TDBAL"}, 271 {E1000_TDBAH(0), "TDBAH"}, 272 {E1000_TDLEN(0), "TDLEN"}, 273 {E1000_TDH(0), "TDH"}, 274 {E1000_TDT(0), "TDT"}, 275 {E1000_TXDCTL(0), "TXDCTL"}, 276 {E1000_TDFH, "TDFH"}, 277 {E1000_TDFT, "TDFT"}, 278 {E1000_TDFHS, "TDFHS"}, 279 {E1000_TDFPC, "TDFPC"}, 280 281 /* List Terminator */ 282 {} 283 }; 284 285 /* igb_regdump - register printout routine */ 286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 287 { 288 int n = 0; 289 char rname[16]; 290 u32 regs[8]; 291 292 switch (reginfo->ofs) { 293 case E1000_RDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_RDLEN(n)); 296 break; 297 case E1000_RDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_RDH(n)); 300 break; 301 case E1000_RDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_RDT(n)); 304 break; 305 case E1000_RXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RXDCTL(n)); 308 break; 309 case E1000_RDBAL(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDBAL(n)); 312 break; 313 case E1000_RDBAH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDBAH(n)); 316 break; 317 case E1000_TDBAL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDBAL(n)); 320 break; 321 case E1000_TDBAH(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_TDBAH(n)); 324 break; 325 case E1000_TDLEN(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_TDLEN(n)); 328 break; 329 case E1000_TDH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_TDH(n)); 332 break; 333 case E1000_TDT(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDT(n)); 336 break; 337 case E1000_TXDCTL(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TXDCTL(n)); 340 break; 341 default: 342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 343 return; 344 } 345 346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 348 regs[2], regs[3]); 349 } 350 351 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 352 static void igb_dump(struct igb_adapter *adapter) 353 { 354 struct net_device *netdev = adapter->netdev; 355 struct e1000_hw *hw = &adapter->hw; 356 struct igb_reg_info *reginfo; 357 struct igb_ring *tx_ring; 358 union e1000_adv_tx_desc *tx_desc; 359 struct my_u0 { u64 a; u64 b; } *u0; 360 struct igb_ring *rx_ring; 361 union e1000_adv_rx_desc *rx_desc; 362 u32 staterr; 363 u16 i, n; 364 365 if (!netif_msg_hw(adapter)) 366 return; 367 368 /* Print netdevice Info */ 369 if (netdev) { 370 dev_info(&adapter->pdev->dev, "Net device Info\n"); 371 pr_info("Device Name state trans_start\n"); 372 pr_info("%-15s %016lX %016lX\n", netdev->name, 373 netdev->state, dev_trans_start(netdev)); 374 } 375 376 /* Print Registers */ 377 dev_info(&adapter->pdev->dev, "Register Dump\n"); 378 pr_info(" Register Name Value\n"); 379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 380 reginfo->name; reginfo++) { 381 igb_regdump(hw, reginfo); 382 } 383 384 /* Print TX Ring Summary */ 385 if (!netdev || !netif_running(netdev)) 386 goto exit; 387 388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 390 for (n = 0; n < adapter->num_tx_queues; n++) { 391 struct igb_tx_buffer *buffer_info; 392 tx_ring = adapter->tx_ring[n]; 393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 395 n, tx_ring->next_to_use, tx_ring->next_to_clean, 396 (u64)dma_unmap_addr(buffer_info, dma), 397 dma_unmap_len(buffer_info, len), 398 buffer_info->next_to_watch, 399 (u64)buffer_info->time_stamp); 400 } 401 402 /* Print TX Rings */ 403 if (!netif_msg_tx_done(adapter)) 404 goto rx_ring_summary; 405 406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 407 408 /* Transmit Descriptor Formats 409 * 410 * Advanced Transmit Descriptor 411 * +--------------------------------------------------------------+ 412 * 0 | Buffer Address [63:0] | 413 * +--------------------------------------------------------------+ 414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 415 * +--------------------------------------------------------------+ 416 * 63 46 45 40 39 38 36 35 32 31 24 15 0 417 */ 418 419 for (n = 0; n < adapter->num_tx_queues; n++) { 420 tx_ring = adapter->tx_ring[n]; 421 pr_info("------------------------------------\n"); 422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 423 pr_info("------------------------------------\n"); 424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 425 426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 427 const char *next_desc; 428 struct igb_tx_buffer *buffer_info; 429 tx_desc = IGB_TX_DESC(tx_ring, i); 430 buffer_info = &tx_ring->tx_buffer_info[i]; 431 u0 = (struct my_u0 *)tx_desc; 432 if (i == tx_ring->next_to_use && 433 i == tx_ring->next_to_clean) 434 next_desc = " NTC/U"; 435 else if (i == tx_ring->next_to_use) 436 next_desc = " NTU"; 437 else if (i == tx_ring->next_to_clean) 438 next_desc = " NTC"; 439 else 440 next_desc = ""; 441 442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 443 i, le64_to_cpu(u0->a), 444 le64_to_cpu(u0->b), 445 (u64)dma_unmap_addr(buffer_info, dma), 446 dma_unmap_len(buffer_info, len), 447 buffer_info->next_to_watch, 448 (u64)buffer_info->time_stamp, 449 buffer_info->skb, next_desc); 450 451 if (netif_msg_pktdata(adapter) && buffer_info->skb) 452 print_hex_dump(KERN_INFO, "", 453 DUMP_PREFIX_ADDRESS, 454 16, 1, buffer_info->skb->data, 455 dma_unmap_len(buffer_info, len), 456 true); 457 } 458 } 459 460 /* Print RX Rings Summary */ 461 rx_ring_summary: 462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 463 pr_info("Queue [NTU] [NTC]\n"); 464 for (n = 0; n < adapter->num_rx_queues; n++) { 465 rx_ring = adapter->rx_ring[n]; 466 pr_info(" %5d %5X %5X\n", 467 n, rx_ring->next_to_use, rx_ring->next_to_clean); 468 } 469 470 /* Print RX Rings */ 471 if (!netif_msg_rx_status(adapter)) 472 goto exit; 473 474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 475 476 /* Advanced Receive Descriptor (Read) Format 477 * 63 1 0 478 * +-----------------------------------------------------+ 479 * 0 | Packet Buffer Address [63:1] |A0/NSE| 480 * +----------------------------------------------+------+ 481 * 8 | Header Buffer Address [63:1] | DD | 482 * +-----------------------------------------------------+ 483 * 484 * 485 * Advanced Receive Descriptor (Write-Back) Format 486 * 487 * 63 48 47 32 31 30 21 20 17 16 4 3 0 488 * +------------------------------------------------------+ 489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 490 * | Checksum Ident | | | | Type | Type | 491 * +------------------------------------------------------+ 492 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 493 * +------------------------------------------------------+ 494 * 63 48 47 32 31 20 19 0 495 */ 496 497 for (n = 0; n < adapter->num_rx_queues; n++) { 498 rx_ring = adapter->rx_ring[n]; 499 pr_info("------------------------------------\n"); 500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 501 pr_info("------------------------------------\n"); 502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 504 505 for (i = 0; i < rx_ring->count; i++) { 506 const char *next_desc; 507 struct igb_rx_buffer *buffer_info; 508 buffer_info = &rx_ring->rx_buffer_info[i]; 509 rx_desc = IGB_RX_DESC(rx_ring, i); 510 u0 = (struct my_u0 *)rx_desc; 511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 512 513 if (i == rx_ring->next_to_use) 514 next_desc = " NTU"; 515 else if (i == rx_ring->next_to_clean) 516 next_desc = " NTC"; 517 else 518 next_desc = ""; 519 520 if (staterr & E1000_RXD_STAT_DD) { 521 /* Descriptor Done */ 522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 523 "RWB", i, 524 le64_to_cpu(u0->a), 525 le64_to_cpu(u0->b), 526 next_desc); 527 } else { 528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 529 "R ", i, 530 le64_to_cpu(u0->a), 531 le64_to_cpu(u0->b), 532 (u64)buffer_info->dma, 533 next_desc); 534 535 if (netif_msg_pktdata(adapter) && 536 buffer_info->dma && buffer_info->page) { 537 print_hex_dump(KERN_INFO, "", 538 DUMP_PREFIX_ADDRESS, 539 16, 1, 540 page_address(buffer_info->page) + 541 buffer_info->page_offset, 542 igb_rx_bufsz(rx_ring), true); 543 } 544 } 545 } 546 } 547 548 exit: 549 return; 550 } 551 552 /** 553 * igb_get_i2c_data - Reads the I2C SDA data bit 554 * @data: opaque pointer to adapter struct 555 * 556 * Returns the I2C data bit value 557 **/ 558 static int igb_get_i2c_data(void *data) 559 { 560 struct igb_adapter *adapter = (struct igb_adapter *)data; 561 struct e1000_hw *hw = &adapter->hw; 562 s32 i2cctl = rd32(E1000_I2CPARAMS); 563 564 return !!(i2cctl & E1000_I2C_DATA_IN); 565 } 566 567 /** 568 * igb_set_i2c_data - Sets the I2C data bit 569 * @data: pointer to hardware structure 570 * @state: I2C data value (0 or 1) to set 571 * 572 * Sets the I2C data bit 573 **/ 574 static void igb_set_i2c_data(void *data, int state) 575 { 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 if (state) 581 i2cctl |= E1000_I2C_DATA_OUT; 582 else 583 i2cctl &= ~E1000_I2C_DATA_OUT; 584 585 i2cctl &= ~E1000_I2C_DATA_OE_N; 586 i2cctl |= E1000_I2C_CLK_OE_N; 587 wr32(E1000_I2CPARAMS, i2cctl); 588 wrfl(); 589 590 } 591 592 /** 593 * igb_set_i2c_clk - Sets the I2C SCL clock 594 * @data: pointer to hardware structure 595 * @state: state to set clock 596 * 597 * Sets the I2C clock line to state 598 **/ 599 static void igb_set_i2c_clk(void *data, int state) 600 { 601 struct igb_adapter *adapter = (struct igb_adapter *)data; 602 struct e1000_hw *hw = &adapter->hw; 603 s32 i2cctl = rd32(E1000_I2CPARAMS); 604 605 if (state) { 606 i2cctl |= E1000_I2C_CLK_OUT; 607 i2cctl &= ~E1000_I2C_CLK_OE_N; 608 } else { 609 i2cctl &= ~E1000_I2C_CLK_OUT; 610 i2cctl &= ~E1000_I2C_CLK_OE_N; 611 } 612 wr32(E1000_I2CPARAMS, i2cctl); 613 wrfl(); 614 } 615 616 /** 617 * igb_get_i2c_clk - Gets the I2C SCL clock state 618 * @data: pointer to hardware structure 619 * 620 * Gets the I2C clock state 621 **/ 622 static int igb_get_i2c_clk(void *data) 623 { 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 return !!(i2cctl & E1000_I2C_CLK_IN); 629 } 630 631 static const struct i2c_algo_bit_data igb_i2c_algo = { 632 .setsda = igb_set_i2c_data, 633 .setscl = igb_set_i2c_clk, 634 .getsda = igb_get_i2c_data, 635 .getscl = igb_get_i2c_clk, 636 .udelay = 5, 637 .timeout = 20, 638 }; 639 640 /** 641 * igb_get_hw_dev - return device 642 * @hw: pointer to hardware structure 643 * 644 * used by hardware layer to print debugging information 645 **/ 646 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 647 { 648 struct igb_adapter *adapter = hw->back; 649 return adapter->netdev; 650 } 651 652 /** 653 * igb_init_module - Driver Registration Routine 654 * 655 * igb_init_module is the first routine called when the driver is 656 * loaded. All it does is register with the PCI subsystem. 657 **/ 658 static int __init igb_init_module(void) 659 { 660 int ret; 661 662 pr_info("%s\n", igb_driver_string); 663 pr_info("%s\n", igb_copyright); 664 665 #ifdef CONFIG_IGB_DCA 666 dca_register_notify(&dca_notifier); 667 #endif 668 ret = pci_register_driver(&igb_driver); 669 return ret; 670 } 671 672 module_init(igb_init_module); 673 674 /** 675 * igb_exit_module - Driver Exit Cleanup Routine 676 * 677 * igb_exit_module is called just before the driver is removed 678 * from memory. 679 **/ 680 static void __exit igb_exit_module(void) 681 { 682 #ifdef CONFIG_IGB_DCA 683 dca_unregister_notify(&dca_notifier); 684 #endif 685 pci_unregister_driver(&igb_driver); 686 } 687 688 module_exit(igb_exit_module); 689 690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 691 /** 692 * igb_cache_ring_register - Descriptor ring to register mapping 693 * @adapter: board private structure to initialize 694 * 695 * Once we know the feature-set enabled for the device, we'll cache 696 * the register offset the descriptor ring is assigned to. 697 **/ 698 static void igb_cache_ring_register(struct igb_adapter *adapter) 699 { 700 int i = 0, j = 0; 701 u32 rbase_offset = adapter->vfs_allocated_count; 702 703 switch (adapter->hw.mac.type) { 704 case e1000_82576: 705 /* The queues are allocated for virtualization such that VF 0 706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 707 * In order to avoid collision we start at the first free queue 708 * and continue consuming queues in the same sequence 709 */ 710 if (adapter->vfs_allocated_count) { 711 for (; i < adapter->rss_queues; i++) 712 adapter->rx_ring[i]->reg_idx = rbase_offset + 713 Q_IDX_82576(i); 714 } 715 fallthrough; 716 case e1000_82575: 717 case e1000_82580: 718 case e1000_i350: 719 case e1000_i354: 720 case e1000_i210: 721 case e1000_i211: 722 default: 723 for (; i < adapter->num_rx_queues; i++) 724 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 725 for (; j < adapter->num_tx_queues; j++) 726 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 727 break; 728 } 729 } 730 731 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 732 { 733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 735 u32 value = 0; 736 737 if (E1000_REMOVED(hw_addr)) 738 return ~value; 739 740 value = readl(&hw_addr[reg]); 741 742 /* reads should not return all F's */ 743 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 744 struct net_device *netdev = igb->netdev; 745 hw->hw_addr = NULL; 746 netdev_err(netdev, "PCIe link lost\n"); 747 WARN(pci_device_is_present(igb->pdev), 748 "igb: Failed to read reg 0x%x!\n", reg); 749 } 750 751 return value; 752 } 753 754 /** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768 { 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778 } 779 780 #define IGB_N0_QUEUE -1 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782 { 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = BIT(msix_vector); 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = BIT(msix_vector); 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857 } 858 859 /** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866 static void igb_configure_msix(struct igb_adapter *adapter) 867 { 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = BIT(vector); 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923 } 924 925 /** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932 static int igb_request_msix(struct igb_adapter *adapter) 933 { 934 struct net_device *netdev = adapter->netdev; 935 int i, err = 0, vector = 0, free_vector = 0; 936 937 err = request_irq(adapter->msix_entries[vector].vector, 938 igb_msix_other, 0, netdev->name, adapter); 939 if (err) 940 goto err_out; 941 942 for (i = 0; i < adapter->num_q_vectors; i++) { 943 struct igb_q_vector *q_vector = adapter->q_vector[i]; 944 945 vector++; 946 947 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 948 949 if (q_vector->rx.ring && q_vector->tx.ring) 950 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 951 q_vector->rx.ring->queue_index); 952 else if (q_vector->tx.ring) 953 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 954 q_vector->tx.ring->queue_index); 955 else if (q_vector->rx.ring) 956 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 957 q_vector->rx.ring->queue_index); 958 else 959 sprintf(q_vector->name, "%s-unused", netdev->name); 960 961 err = request_irq(adapter->msix_entries[vector].vector, 962 igb_msix_ring, 0, q_vector->name, 963 q_vector); 964 if (err) 965 goto err_free; 966 } 967 968 igb_configure_msix(adapter); 969 return 0; 970 971 err_free: 972 /* free already assigned IRQs */ 973 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 974 975 vector--; 976 for (i = 0; i < vector; i++) { 977 free_irq(adapter->msix_entries[free_vector++].vector, 978 adapter->q_vector[i]); 979 } 980 err_out: 981 return err; 982 } 983 984 /** 985 * igb_free_q_vector - Free memory allocated for specific interrupt vector 986 * @adapter: board private structure to initialize 987 * @v_idx: Index of vector to be freed 988 * 989 * This function frees the memory allocated to the q_vector. 990 **/ 991 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 992 { 993 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 994 995 adapter->q_vector[v_idx] = NULL; 996 997 /* igb_get_stats64() might access the rings on this vector, 998 * we must wait a grace period before freeing it. 999 */ 1000 if (q_vector) 1001 kfree_rcu(q_vector, rcu); 1002 } 1003 1004 /** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013 { 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1017 * allocated. So, q_vector is NULL so we should stop here. 1018 */ 1019 if (!q_vector) 1020 return; 1021 1022 if (q_vector->tx.ring) 1023 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1024 1025 if (q_vector->rx.ring) 1026 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1027 1028 netif_napi_del(&q_vector->napi); 1029 1030 } 1031 1032 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1033 { 1034 int v_idx = adapter->num_q_vectors; 1035 1036 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1037 pci_disable_msix(adapter->pdev); 1038 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1039 pci_disable_msi(adapter->pdev); 1040 1041 while (v_idx--) 1042 igb_reset_q_vector(adapter, v_idx); 1043 } 1044 1045 /** 1046 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1047 * @adapter: board private structure to initialize 1048 * 1049 * This function frees the memory allocated to the q_vectors. In addition if 1050 * NAPI is enabled it will delete any references to the NAPI struct prior 1051 * to freeing the q_vector. 1052 **/ 1053 static void igb_free_q_vectors(struct igb_adapter *adapter) 1054 { 1055 int v_idx = adapter->num_q_vectors; 1056 1057 adapter->num_tx_queues = 0; 1058 adapter->num_rx_queues = 0; 1059 adapter->num_q_vectors = 0; 1060 1061 while (v_idx--) { 1062 igb_reset_q_vector(adapter, v_idx); 1063 igb_free_q_vector(adapter, v_idx); 1064 } 1065 } 1066 1067 /** 1068 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1072 * MSI-X interrupts allocated. 1073 */ 1074 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1075 { 1076 igb_free_q_vectors(adapter); 1077 igb_reset_interrupt_capability(adapter); 1078 } 1079 1080 /** 1081 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1082 * @adapter: board private structure to initialize 1083 * @msix: boolean value of MSIX capability 1084 * 1085 * Attempt to configure interrupts using the best available 1086 * capabilities of the hardware and kernel. 1087 **/ 1088 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1089 { 1090 int err; 1091 int numvecs, i; 1092 1093 if (!msix) 1094 goto msi_only; 1095 adapter->flags |= IGB_FLAG_HAS_MSIX; 1096 1097 /* Number of supported queues. */ 1098 adapter->num_rx_queues = adapter->rss_queues; 1099 if (adapter->vfs_allocated_count) 1100 adapter->num_tx_queues = 1; 1101 else 1102 adapter->num_tx_queues = adapter->rss_queues; 1103 1104 /* start with one vector for every Rx queue */ 1105 numvecs = adapter->num_rx_queues; 1106 1107 /* if Tx handler is separate add 1 for every Tx queue */ 1108 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1109 numvecs += adapter->num_tx_queues; 1110 1111 /* store the number of vectors reserved for queues */ 1112 adapter->num_q_vectors = numvecs; 1113 1114 /* add 1 vector for link status interrupts */ 1115 numvecs++; 1116 for (i = 0; i < numvecs; i++) 1117 adapter->msix_entries[i].entry = i; 1118 1119 err = pci_enable_msix_range(adapter->pdev, 1120 adapter->msix_entries, 1121 numvecs, 1122 numvecs); 1123 if (err > 0) 1124 return; 1125 1126 igb_reset_interrupt_capability(adapter); 1127 1128 /* If we can't do MSI-X, try MSI */ 1129 msi_only: 1130 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1131 #ifdef CONFIG_PCI_IOV 1132 /* disable SR-IOV for non MSI-X configurations */ 1133 if (adapter->vf_data) { 1134 struct e1000_hw *hw = &adapter->hw; 1135 /* disable iov and allow time for transactions to clear */ 1136 pci_disable_sriov(adapter->pdev); 1137 msleep(500); 1138 1139 kfree(adapter->vf_mac_list); 1140 adapter->vf_mac_list = NULL; 1141 kfree(adapter->vf_data); 1142 adapter->vf_data = NULL; 1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1144 wrfl(); 1145 msleep(100); 1146 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1147 } 1148 #endif 1149 adapter->vfs_allocated_count = 0; 1150 adapter->rss_queues = 1; 1151 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1152 adapter->num_rx_queues = 1; 1153 adapter->num_tx_queues = 1; 1154 adapter->num_q_vectors = 1; 1155 if (!pci_enable_msi(adapter->pdev)) 1156 adapter->flags |= IGB_FLAG_HAS_MSI; 1157 } 1158 1159 static void igb_add_ring(struct igb_ring *ring, 1160 struct igb_ring_container *head) 1161 { 1162 head->ring = ring; 1163 head->count++; 1164 } 1165 1166 /** 1167 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1168 * @adapter: board private structure to initialize 1169 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1170 * @v_idx: index of vector in adapter struct 1171 * @txr_count: total number of Tx rings to allocate 1172 * @txr_idx: index of first Tx ring to allocate 1173 * @rxr_count: total number of Rx rings to allocate 1174 * @rxr_idx: index of first Rx ring to allocate 1175 * 1176 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1177 **/ 1178 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1179 int v_count, int v_idx, 1180 int txr_count, int txr_idx, 1181 int rxr_count, int rxr_idx) 1182 { 1183 struct igb_q_vector *q_vector; 1184 struct igb_ring *ring; 1185 int ring_count; 1186 size_t size; 1187 1188 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1189 if (txr_count > 1 || rxr_count > 1) 1190 return -ENOMEM; 1191 1192 ring_count = txr_count + rxr_count; 1193 size = struct_size(q_vector, ring, ring_count); 1194 1195 /* allocate q_vector and rings */ 1196 q_vector = adapter->q_vector[v_idx]; 1197 if (!q_vector) { 1198 q_vector = kzalloc(size, GFP_KERNEL); 1199 } else if (size > ksize(q_vector)) { 1200 kfree_rcu(q_vector, rcu); 1201 q_vector = kzalloc(size, GFP_KERNEL); 1202 } else { 1203 memset(q_vector, 0, size); 1204 } 1205 if (!q_vector) 1206 return -ENOMEM; 1207 1208 /* initialize NAPI */ 1209 netif_napi_add(adapter->netdev, &q_vector->napi, 1210 igb_poll, 64); 1211 1212 /* tie q_vector and adapter together */ 1213 adapter->q_vector[v_idx] = q_vector; 1214 q_vector->adapter = adapter; 1215 1216 /* initialize work limits */ 1217 q_vector->tx.work_limit = adapter->tx_work_limit; 1218 1219 /* initialize ITR configuration */ 1220 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1221 q_vector->itr_val = IGB_START_ITR; 1222 1223 /* initialize pointer to rings */ 1224 ring = q_vector->ring; 1225 1226 /* intialize ITR */ 1227 if (rxr_count) { 1228 /* rx or rx/tx vector */ 1229 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1230 q_vector->itr_val = adapter->rx_itr_setting; 1231 } else { 1232 /* tx only vector */ 1233 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1234 q_vector->itr_val = adapter->tx_itr_setting; 1235 } 1236 1237 if (txr_count) { 1238 /* assign generic ring traits */ 1239 ring->dev = &adapter->pdev->dev; 1240 ring->netdev = adapter->netdev; 1241 1242 /* configure backlink on ring */ 1243 ring->q_vector = q_vector; 1244 1245 /* update q_vector Tx values */ 1246 igb_add_ring(ring, &q_vector->tx); 1247 1248 /* For 82575, context index must be unique per ring. */ 1249 if (adapter->hw.mac.type == e1000_82575) 1250 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1251 1252 /* apply Tx specific ring traits */ 1253 ring->count = adapter->tx_ring_count; 1254 ring->queue_index = txr_idx; 1255 1256 ring->cbs_enable = false; 1257 ring->idleslope = 0; 1258 ring->sendslope = 0; 1259 ring->hicredit = 0; 1260 ring->locredit = 0; 1261 1262 u64_stats_init(&ring->tx_syncp); 1263 u64_stats_init(&ring->tx_syncp2); 1264 1265 /* assign ring to adapter */ 1266 adapter->tx_ring[txr_idx] = ring; 1267 1268 /* push pointer to next ring */ 1269 ring++; 1270 } 1271 1272 if (rxr_count) { 1273 /* assign generic ring traits */ 1274 ring->dev = &adapter->pdev->dev; 1275 ring->netdev = adapter->netdev; 1276 1277 /* configure backlink on ring */ 1278 ring->q_vector = q_vector; 1279 1280 /* update q_vector Rx values */ 1281 igb_add_ring(ring, &q_vector->rx); 1282 1283 /* set flag indicating ring supports SCTP checksum offload */ 1284 if (adapter->hw.mac.type >= e1000_82576) 1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1286 1287 /* On i350, i354, i210, and i211, loopback VLAN packets 1288 * have the tag byte-swapped. 1289 */ 1290 if (adapter->hw.mac.type >= e1000_i350) 1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1292 1293 /* apply Rx specific ring traits */ 1294 ring->count = adapter->rx_ring_count; 1295 ring->queue_index = rxr_idx; 1296 1297 u64_stats_init(&ring->rx_syncp); 1298 1299 /* assign ring to adapter */ 1300 adapter->rx_ring[rxr_idx] = ring; 1301 } 1302 1303 return 0; 1304 } 1305 1306 1307 /** 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1309 * @adapter: board private structure to initialize 1310 * 1311 * We allocate one q_vector per queue interrupt. If allocation fails we 1312 * return -ENOMEM. 1313 **/ 1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1315 { 1316 int q_vectors = adapter->num_q_vectors; 1317 int rxr_remaining = adapter->num_rx_queues; 1318 int txr_remaining = adapter->num_tx_queues; 1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1320 int err; 1321 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1323 for (; rxr_remaining; v_idx++) { 1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1325 0, 0, 1, rxr_idx); 1326 1327 if (err) 1328 goto err_out; 1329 1330 /* update counts and index */ 1331 rxr_remaining--; 1332 rxr_idx++; 1333 } 1334 } 1335 1336 for (; v_idx < q_vectors; v_idx++) { 1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1339 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1341 tqpv, txr_idx, rqpv, rxr_idx); 1342 1343 if (err) 1344 goto err_out; 1345 1346 /* update counts and index */ 1347 rxr_remaining -= rqpv; 1348 txr_remaining -= tqpv; 1349 rxr_idx++; 1350 txr_idx++; 1351 } 1352 1353 return 0; 1354 1355 err_out: 1356 adapter->num_tx_queues = 0; 1357 adapter->num_rx_queues = 0; 1358 adapter->num_q_vectors = 0; 1359 1360 while (v_idx--) 1361 igb_free_q_vector(adapter, v_idx); 1362 1363 return -ENOMEM; 1364 } 1365 1366 /** 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1368 * @adapter: board private structure to initialize 1369 * @msix: boolean value of MSIX capability 1370 * 1371 * This function initializes the interrupts and allocates all of the queues. 1372 **/ 1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1374 { 1375 struct pci_dev *pdev = adapter->pdev; 1376 int err; 1377 1378 igb_set_interrupt_capability(adapter, msix); 1379 1380 err = igb_alloc_q_vectors(adapter); 1381 if (err) { 1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1383 goto err_alloc_q_vectors; 1384 } 1385 1386 igb_cache_ring_register(adapter); 1387 1388 return 0; 1389 1390 err_alloc_q_vectors: 1391 igb_reset_interrupt_capability(adapter); 1392 return err; 1393 } 1394 1395 /** 1396 * igb_request_irq - initialize interrupts 1397 * @adapter: board private structure to initialize 1398 * 1399 * Attempts to configure interrupts using the best available 1400 * capabilities of the hardware and kernel. 1401 **/ 1402 static int igb_request_irq(struct igb_adapter *adapter) 1403 { 1404 struct net_device *netdev = adapter->netdev; 1405 struct pci_dev *pdev = adapter->pdev; 1406 int err = 0; 1407 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1409 err = igb_request_msix(adapter); 1410 if (!err) 1411 goto request_done; 1412 /* fall back to MSI */ 1413 igb_free_all_tx_resources(adapter); 1414 igb_free_all_rx_resources(adapter); 1415 1416 igb_clear_interrupt_scheme(adapter); 1417 err = igb_init_interrupt_scheme(adapter, false); 1418 if (err) 1419 goto request_done; 1420 1421 igb_setup_all_tx_resources(adapter); 1422 igb_setup_all_rx_resources(adapter); 1423 igb_configure(adapter); 1424 } 1425 1426 igb_assign_vector(adapter->q_vector[0], 0); 1427 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1429 err = request_irq(pdev->irq, igb_intr_msi, 0, 1430 netdev->name, adapter); 1431 if (!err) 1432 goto request_done; 1433 1434 /* fall back to legacy interrupts */ 1435 igb_reset_interrupt_capability(adapter); 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1437 } 1438 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1440 netdev->name, adapter); 1441 1442 if (err) 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1444 err); 1445 1446 request_done: 1447 return err; 1448 } 1449 1450 static void igb_free_irq(struct igb_adapter *adapter) 1451 { 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1453 int vector = 0, i; 1454 1455 free_irq(adapter->msix_entries[vector++].vector, adapter); 1456 1457 for (i = 0; i < adapter->num_q_vectors; i++) 1458 free_irq(adapter->msix_entries[vector++].vector, 1459 adapter->q_vector[i]); 1460 } else { 1461 free_irq(adapter->pdev->irq, adapter); 1462 } 1463 } 1464 1465 /** 1466 * igb_irq_disable - Mask off interrupt generation on the NIC 1467 * @adapter: board private structure 1468 **/ 1469 static void igb_irq_disable(struct igb_adapter *adapter) 1470 { 1471 struct e1000_hw *hw = &adapter->hw; 1472 1473 /* we need to be careful when disabling interrupts. The VFs are also 1474 * mapped into these registers and so clearing the bits can cause 1475 * issues on the VF drivers so we only need to clear what we set 1476 */ 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1478 u32 regval = rd32(E1000_EIAM); 1479 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 1492 for (i = 0; i < adapter->num_q_vectors; i++) 1493 synchronize_irq(adapter->msix_entries[i].vector); 1494 } else { 1495 synchronize_irq(adapter->pdev->irq); 1496 } 1497 } 1498 1499 /** 1500 * igb_irq_enable - Enable default interrupt generation settings 1501 * @adapter: board private structure 1502 **/ 1503 static void igb_irq_enable(struct igb_adapter *adapter) 1504 { 1505 struct e1000_hw *hw = &adapter->hw; 1506 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1509 u32 regval = rd32(E1000_EIAC); 1510 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1512 regval = rd32(E1000_EIAM); 1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1514 wr32(E1000_EIMS, adapter->eims_enable_mask); 1515 if (adapter->vfs_allocated_count) { 1516 wr32(E1000_MBVFIMR, 0xFF); 1517 ims |= E1000_IMS_VMMB; 1518 } 1519 wr32(E1000_IMS, ims); 1520 } else { 1521 wr32(E1000_IMS, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 wr32(E1000_IAM, IMS_ENABLE_MASK | 1524 E1000_IMS_DRSTA); 1525 } 1526 } 1527 1528 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1529 { 1530 struct e1000_hw *hw = &adapter->hw; 1531 u16 pf_id = adapter->vfs_allocated_count; 1532 u16 vid = adapter->hw.mng_cookie.vlan_id; 1533 u16 old_vid = adapter->mng_vlan_id; 1534 1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1536 /* add VID to filter table */ 1537 igb_vfta_set(hw, vid, pf_id, true, true); 1538 adapter->mng_vlan_id = vid; 1539 } else { 1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1541 } 1542 1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1544 (vid != old_vid) && 1545 !test_bit(old_vid, adapter->active_vlans)) { 1546 /* remove VID from filter table */ 1547 igb_vfta_set(hw, vid, pf_id, false, true); 1548 } 1549 } 1550 1551 /** 1552 * igb_release_hw_control - release control of the h/w to f/w 1553 * @adapter: address of board private structure 1554 * 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1556 * For ASF and Pass Through versions of f/w this means that the 1557 * driver is no longer loaded. 1558 **/ 1559 static void igb_release_hw_control(struct igb_adapter *adapter) 1560 { 1561 struct e1000_hw *hw = &adapter->hw; 1562 u32 ctrl_ext; 1563 1564 /* Let firmware take over control of h/w */ 1565 ctrl_ext = rd32(E1000_CTRL_EXT); 1566 wr32(E1000_CTRL_EXT, 1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1568 } 1569 1570 /** 1571 * igb_get_hw_control - get control of the h/w from f/w 1572 * @adapter: address of board private structure 1573 * 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1575 * For ASF and Pass Through versions of f/w this means that 1576 * the driver is loaded. 1577 **/ 1578 static void igb_get_hw_control(struct igb_adapter *adapter) 1579 { 1580 struct e1000_hw *hw = &adapter->hw; 1581 u32 ctrl_ext; 1582 1583 /* Let firmware know the driver has taken over */ 1584 ctrl_ext = rd32(E1000_CTRL_EXT); 1585 wr32(E1000_CTRL_EXT, 1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1587 } 1588 1589 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1590 { 1591 struct net_device *netdev = adapter->netdev; 1592 struct e1000_hw *hw = &adapter->hw; 1593 1594 WARN_ON(hw->mac.type != e1000_i210); 1595 1596 if (enable) 1597 adapter->flags |= IGB_FLAG_FQTSS; 1598 else 1599 adapter->flags &= ~IGB_FLAG_FQTSS; 1600 1601 if (netif_running(netdev)) 1602 schedule_work(&adapter->reset_task); 1603 } 1604 1605 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1606 { 1607 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1608 } 1609 1610 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1611 enum tx_queue_prio prio) 1612 { 1613 u32 val; 1614 1615 WARN_ON(hw->mac.type != e1000_i210); 1616 WARN_ON(queue < 0 || queue > 4); 1617 1618 val = rd32(E1000_I210_TXDCTL(queue)); 1619 1620 if (prio == TX_QUEUE_PRIO_HIGH) 1621 val |= E1000_TXDCTL_PRIORITY; 1622 else 1623 val &= ~E1000_TXDCTL_PRIORITY; 1624 1625 wr32(E1000_I210_TXDCTL(queue), val); 1626 } 1627 1628 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1629 { 1630 u32 val; 1631 1632 WARN_ON(hw->mac.type != e1000_i210); 1633 WARN_ON(queue < 0 || queue > 1); 1634 1635 val = rd32(E1000_I210_TQAVCC(queue)); 1636 1637 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1638 val |= E1000_TQAVCC_QUEUEMODE; 1639 else 1640 val &= ~E1000_TQAVCC_QUEUEMODE; 1641 1642 wr32(E1000_I210_TQAVCC(queue), val); 1643 } 1644 1645 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1646 { 1647 int i; 1648 1649 for (i = 0; i < adapter->num_tx_queues; i++) { 1650 if (adapter->tx_ring[i]->cbs_enable) 1651 return true; 1652 } 1653 1654 return false; 1655 } 1656 1657 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1658 { 1659 int i; 1660 1661 for (i = 0; i < adapter->num_tx_queues; i++) { 1662 if (adapter->tx_ring[i]->launchtime_enable) 1663 return true; 1664 } 1665 1666 return false; 1667 } 1668 1669 /** 1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1671 * @adapter: pointer to adapter struct 1672 * @queue: queue number 1673 * 1674 * Configure CBS and Launchtime for a given hardware queue. 1675 * Parameters are retrieved from the correct Tx ring, so 1676 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1677 * for setting those correctly prior to this function being called. 1678 **/ 1679 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1680 { 1681 struct igb_ring *ring = adapter->tx_ring[queue]; 1682 struct net_device *netdev = adapter->netdev; 1683 struct e1000_hw *hw = &adapter->hw; 1684 u32 tqavcc, tqavctrl; 1685 u16 value; 1686 1687 WARN_ON(hw->mac.type != e1000_i210); 1688 WARN_ON(queue < 0 || queue > 1); 1689 1690 /* If any of the Qav features is enabled, configure queues as SR and 1691 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1692 * as SP. 1693 */ 1694 if (ring->cbs_enable || ring->launchtime_enable) { 1695 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1696 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1697 } else { 1698 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1699 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1700 } 1701 1702 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1703 if (ring->cbs_enable || queue == 0) { 1704 /* i210 does not allow the queue 0 to be in the Strict 1705 * Priority mode while the Qav mode is enabled, so, 1706 * instead of disabling strict priority mode, we give 1707 * queue 0 the maximum of credits possible. 1708 * 1709 * See section 8.12.19 of the i210 datasheet, "Note: 1710 * Queue0 QueueMode must be set to 1b when 1711 * TransmitMode is set to Qav." 1712 */ 1713 if (queue == 0 && !ring->cbs_enable) { 1714 /* max "linkspeed" idleslope in kbps */ 1715 ring->idleslope = 1000000; 1716 ring->hicredit = ETH_FRAME_LEN; 1717 } 1718 1719 /* Always set data transfer arbitration to credit-based 1720 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1721 * the queues. 1722 */ 1723 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1724 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1725 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1726 1727 /* According to i210 datasheet section 7.2.7.7, we should set 1728 * the 'idleSlope' field from TQAVCC register following the 1729 * equation: 1730 * 1731 * For 100 Mbps link speed: 1732 * 1733 * value = BW * 0x7735 * 0.2 (E1) 1734 * 1735 * For 1000Mbps link speed: 1736 * 1737 * value = BW * 0x7735 * 2 (E2) 1738 * 1739 * E1 and E2 can be merged into one equation as shown below. 1740 * Note that 'link-speed' is in Mbps. 1741 * 1742 * value = BW * 0x7735 * 2 * link-speed 1743 * -------------- (E3) 1744 * 1000 1745 * 1746 * 'BW' is the percentage bandwidth out of full link speed 1747 * which can be found with the following equation. Note that 1748 * idleSlope here is the parameter from this function which 1749 * is in kbps. 1750 * 1751 * BW = idleSlope 1752 * ----------------- (E4) 1753 * link-speed * 1000 1754 * 1755 * That said, we can come up with a generic equation to 1756 * calculate the value we should set it TQAVCC register by 1757 * replacing 'BW' in E3 by E4. The resulting equation is: 1758 * 1759 * value = idleSlope * 0x7735 * 2 * link-speed 1760 * ----------------- -------------- (E5) 1761 * link-speed * 1000 1000 1762 * 1763 * 'link-speed' is present in both sides of the fraction so 1764 * it is canceled out. The final equation is the following: 1765 * 1766 * value = idleSlope * 61034 1767 * ----------------- (E6) 1768 * 1000000 1769 * 1770 * NOTE: For i210, given the above, we can see that idleslope 1771 * is represented in 16.38431 kbps units by the value at 1772 * the TQAVCC register (1Gbps / 61034), which reduces 1773 * the granularity for idleslope increments. 1774 * For instance, if you want to configure a 2576kbps 1775 * idleslope, the value to be written on the register 1776 * would have to be 157.23. If rounded down, you end 1777 * up with less bandwidth available than originally 1778 * required (~2572 kbps). If rounded up, you end up 1779 * with a higher bandwidth (~2589 kbps). Below the 1780 * approach we take is to always round up the 1781 * calculated value, so the resulting bandwidth might 1782 * be slightly higher for some configurations. 1783 */ 1784 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1785 1786 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1787 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1788 tqavcc |= value; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 wr32(E1000_I210_TQAVHC(queue), 1792 0x80000000 + ring->hicredit * 0x7735); 1793 } else { 1794 1795 /* Set idleSlope to zero. */ 1796 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1797 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1799 1800 /* Set hiCredit to zero. */ 1801 wr32(E1000_I210_TQAVHC(queue), 0); 1802 1803 /* If CBS is not enabled for any queues anymore, then return to 1804 * the default state of Data Transmission Arbitration on 1805 * TQAVCTRL. 1806 */ 1807 if (!is_any_cbs_enabled(adapter)) { 1808 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1809 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1810 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1811 } 1812 } 1813 1814 /* If LaunchTime is enabled, set DataTranTIM. */ 1815 if (ring->launchtime_enable) { 1816 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1817 * for any of the SR queues, and configure fetchtime delta. 1818 * XXX NOTE: 1819 * - LaunchTime will be enabled for all SR queues. 1820 * - A fixed offset can be added relative to the launch 1821 * time of all packets if configured at reg LAUNCH_OS0. 1822 * We are keeping it as 0 for now (default value). 1823 */ 1824 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1825 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1826 E1000_TQAVCTRL_FETCHTIME_DELTA; 1827 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1828 } else { 1829 /* If Launchtime is not enabled for any SR queues anymore, 1830 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1831 * effectively disabling Launchtime. 1832 */ 1833 if (!is_any_txtime_enabled(adapter)) { 1834 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1835 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1836 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1837 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1838 } 1839 } 1840 1841 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1842 * CBS are not configurable by software so we don't do any 'controller 1843 * configuration' in respect to these parameters. 1844 */ 1845 1846 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1847 ring->cbs_enable ? "enabled" : "disabled", 1848 ring->launchtime_enable ? "enabled" : "disabled", 1849 queue, 1850 ring->idleslope, ring->sendslope, 1851 ring->hicredit, ring->locredit); 1852 } 1853 1854 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1855 bool enable) 1856 { 1857 struct igb_ring *ring; 1858 1859 if (queue < 0 || queue > adapter->num_tx_queues) 1860 return -EINVAL; 1861 1862 ring = adapter->tx_ring[queue]; 1863 ring->launchtime_enable = enable; 1864 1865 return 0; 1866 } 1867 1868 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1869 bool enable, int idleslope, int sendslope, 1870 int hicredit, int locredit) 1871 { 1872 struct igb_ring *ring; 1873 1874 if (queue < 0 || queue > adapter->num_tx_queues) 1875 return -EINVAL; 1876 1877 ring = adapter->tx_ring[queue]; 1878 1879 ring->cbs_enable = enable; 1880 ring->idleslope = idleslope; 1881 ring->sendslope = sendslope; 1882 ring->hicredit = hicredit; 1883 ring->locredit = locredit; 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1890 * @adapter: pointer to adapter struct 1891 * 1892 * Configure TQAVCTRL register switching the controller's Tx mode 1893 * if FQTSS mode is enabled or disabled. Additionally, will issue 1894 * a call to igb_config_tx_modes() per queue so any previously saved 1895 * Tx parameters are applied. 1896 **/ 1897 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1898 { 1899 struct net_device *netdev = adapter->netdev; 1900 struct e1000_hw *hw = &adapter->hw; 1901 u32 val; 1902 1903 /* Only i210 controller supports changing the transmission mode. */ 1904 if (hw->mac.type != e1000_i210) 1905 return; 1906 1907 if (is_fqtss_enabled(adapter)) { 1908 int i, max_queue; 1909 1910 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1911 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1912 * so SP queues wait for SR ones. 1913 */ 1914 val = rd32(E1000_I210_TQAVCTRL); 1915 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1916 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1917 wr32(E1000_I210_TQAVCTRL, val); 1918 1919 /* Configure Tx and Rx packet buffers sizes as described in 1920 * i210 datasheet section 7.2.7.7. 1921 */ 1922 val = rd32(E1000_TXPBS); 1923 val &= ~I210_TXPBSIZE_MASK; 1924 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB | 1925 I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB; 1926 wr32(E1000_TXPBS, val); 1927 1928 val = rd32(E1000_RXPBS); 1929 val &= ~I210_RXPBSIZE_MASK; 1930 val |= I210_RXPBSIZE_PB_30KB; 1931 wr32(E1000_RXPBS, val); 1932 1933 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1934 * register should not exceed the buffer size programmed in 1935 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1936 * so according to the datasheet we should set MAX_TPKT_SIZE to 1937 * 4kB / 64. 1938 * 1939 * However, when we do so, no frame from queue 2 and 3 are 1940 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1941 * or _equal_ to the buffer size programmed in TXPBS. For this 1942 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1943 */ 1944 val = (4096 - 1) / 64; 1945 wr32(E1000_I210_DTXMXPKTSZ, val); 1946 1947 /* Since FQTSS mode is enabled, apply any CBS configuration 1948 * previously set. If no previous CBS configuration has been 1949 * done, then the initial configuration is applied, which means 1950 * CBS is disabled. 1951 */ 1952 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1953 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1954 1955 for (i = 0; i < max_queue; i++) { 1956 igb_config_tx_modes(adapter, i); 1957 } 1958 } else { 1959 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1960 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1961 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1962 1963 val = rd32(E1000_I210_TQAVCTRL); 1964 /* According to Section 8.12.21, the other flags we've set when 1965 * enabling FQTSS are not relevant when disabling FQTSS so we 1966 * don't set they here. 1967 */ 1968 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1969 wr32(E1000_I210_TQAVCTRL, val); 1970 } 1971 1972 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1973 "enabled" : "disabled"); 1974 } 1975 1976 /** 1977 * igb_configure - configure the hardware for RX and TX 1978 * @adapter: private board structure 1979 **/ 1980 static void igb_configure(struct igb_adapter *adapter) 1981 { 1982 struct net_device *netdev = adapter->netdev; 1983 int i; 1984 1985 igb_get_hw_control(adapter); 1986 igb_set_rx_mode(netdev); 1987 igb_setup_tx_mode(adapter); 1988 1989 igb_restore_vlan(adapter); 1990 1991 igb_setup_tctl(adapter); 1992 igb_setup_mrqc(adapter); 1993 igb_setup_rctl(adapter); 1994 1995 igb_nfc_filter_restore(adapter); 1996 igb_configure_tx(adapter); 1997 igb_configure_rx(adapter); 1998 1999 igb_rx_fifo_flush_82575(&adapter->hw); 2000 2001 /* call igb_desc_unused which always leaves 2002 * at least 1 descriptor unused to make sure 2003 * next_to_use != next_to_clean 2004 */ 2005 for (i = 0; i < adapter->num_rx_queues; i++) { 2006 struct igb_ring *ring = adapter->rx_ring[i]; 2007 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2008 } 2009 } 2010 2011 /** 2012 * igb_power_up_link - Power up the phy/serdes link 2013 * @adapter: address of board private structure 2014 **/ 2015 void igb_power_up_link(struct igb_adapter *adapter) 2016 { 2017 igb_reset_phy(&adapter->hw); 2018 2019 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2020 igb_power_up_phy_copper(&adapter->hw); 2021 else 2022 igb_power_up_serdes_link_82575(&adapter->hw); 2023 2024 igb_setup_link(&adapter->hw); 2025 } 2026 2027 /** 2028 * igb_power_down_link - Power down the phy/serdes link 2029 * @adapter: address of board private structure 2030 */ 2031 static void igb_power_down_link(struct igb_adapter *adapter) 2032 { 2033 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2034 igb_power_down_phy_copper_82575(&adapter->hw); 2035 else 2036 igb_shutdown_serdes_link_82575(&adapter->hw); 2037 } 2038 2039 /** 2040 * Detect and switch function for Media Auto Sense 2041 * @adapter: address of the board private structure 2042 **/ 2043 static void igb_check_swap_media(struct igb_adapter *adapter) 2044 { 2045 struct e1000_hw *hw = &adapter->hw; 2046 u32 ctrl_ext, connsw; 2047 bool swap_now = false; 2048 2049 ctrl_ext = rd32(E1000_CTRL_EXT); 2050 connsw = rd32(E1000_CONNSW); 2051 2052 /* need to live swap if current media is copper and we have fiber/serdes 2053 * to go to. 2054 */ 2055 2056 if ((hw->phy.media_type == e1000_media_type_copper) && 2057 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2058 swap_now = true; 2059 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2060 !(connsw & E1000_CONNSW_SERDESD)) { 2061 /* copper signal takes time to appear */ 2062 if (adapter->copper_tries < 4) { 2063 adapter->copper_tries++; 2064 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2065 wr32(E1000_CONNSW, connsw); 2066 return; 2067 } else { 2068 adapter->copper_tries = 0; 2069 if ((connsw & E1000_CONNSW_PHYSD) && 2070 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2071 swap_now = true; 2072 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2073 wr32(E1000_CONNSW, connsw); 2074 } 2075 } 2076 } 2077 2078 if (!swap_now) 2079 return; 2080 2081 switch (hw->phy.media_type) { 2082 case e1000_media_type_copper: 2083 netdev_info(adapter->netdev, 2084 "MAS: changing media to fiber/serdes\n"); 2085 ctrl_ext |= 2086 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2087 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2088 adapter->copper_tries = 0; 2089 break; 2090 case e1000_media_type_internal_serdes: 2091 case e1000_media_type_fiber: 2092 netdev_info(adapter->netdev, 2093 "MAS: changing media to copper\n"); 2094 ctrl_ext &= 2095 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2096 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2097 break; 2098 default: 2099 /* shouldn't get here during regular operation */ 2100 netdev_err(adapter->netdev, 2101 "AMS: Invalid media type found, returning\n"); 2102 break; 2103 } 2104 wr32(E1000_CTRL_EXT, ctrl_ext); 2105 } 2106 2107 /** 2108 * igb_up - Open the interface and prepare it to handle traffic 2109 * @adapter: board private structure 2110 **/ 2111 int igb_up(struct igb_adapter *adapter) 2112 { 2113 struct e1000_hw *hw = &adapter->hw; 2114 int i; 2115 2116 /* hardware has been reset, we need to reload some things */ 2117 igb_configure(adapter); 2118 2119 clear_bit(__IGB_DOWN, &adapter->state); 2120 2121 for (i = 0; i < adapter->num_q_vectors; i++) 2122 napi_enable(&(adapter->q_vector[i]->napi)); 2123 2124 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2125 igb_configure_msix(adapter); 2126 else 2127 igb_assign_vector(adapter->q_vector[0], 0); 2128 2129 /* Clear any pending interrupts. */ 2130 rd32(E1000_TSICR); 2131 rd32(E1000_ICR); 2132 igb_irq_enable(adapter); 2133 2134 /* notify VFs that reset has been completed */ 2135 if (adapter->vfs_allocated_count) { 2136 u32 reg_data = rd32(E1000_CTRL_EXT); 2137 2138 reg_data |= E1000_CTRL_EXT_PFRSTD; 2139 wr32(E1000_CTRL_EXT, reg_data); 2140 } 2141 2142 netif_tx_start_all_queues(adapter->netdev); 2143 2144 /* start the watchdog. */ 2145 hw->mac.get_link_status = 1; 2146 schedule_work(&adapter->watchdog_task); 2147 2148 if ((adapter->flags & IGB_FLAG_EEE) && 2149 (!hw->dev_spec._82575.eee_disable)) 2150 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2151 2152 return 0; 2153 } 2154 2155 void igb_down(struct igb_adapter *adapter) 2156 { 2157 struct net_device *netdev = adapter->netdev; 2158 struct e1000_hw *hw = &adapter->hw; 2159 u32 tctl, rctl; 2160 int i; 2161 2162 /* signal that we're down so the interrupt handler does not 2163 * reschedule our watchdog timer 2164 */ 2165 set_bit(__IGB_DOWN, &adapter->state); 2166 2167 /* disable receives in the hardware */ 2168 rctl = rd32(E1000_RCTL); 2169 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2170 /* flush and sleep below */ 2171 2172 igb_nfc_filter_exit(adapter); 2173 2174 netif_carrier_off(netdev); 2175 netif_tx_stop_all_queues(netdev); 2176 2177 /* disable transmits in the hardware */ 2178 tctl = rd32(E1000_TCTL); 2179 tctl &= ~E1000_TCTL_EN; 2180 wr32(E1000_TCTL, tctl); 2181 /* flush both disables and wait for them to finish */ 2182 wrfl(); 2183 usleep_range(10000, 11000); 2184 2185 igb_irq_disable(adapter); 2186 2187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2188 2189 for (i = 0; i < adapter->num_q_vectors; i++) { 2190 if (adapter->q_vector[i]) { 2191 napi_synchronize(&adapter->q_vector[i]->napi); 2192 napi_disable(&adapter->q_vector[i]->napi); 2193 } 2194 } 2195 2196 del_timer_sync(&adapter->watchdog_timer); 2197 del_timer_sync(&adapter->phy_info_timer); 2198 2199 /* record the stats before reset*/ 2200 spin_lock(&adapter->stats64_lock); 2201 igb_update_stats(adapter); 2202 spin_unlock(&adapter->stats64_lock); 2203 2204 adapter->link_speed = 0; 2205 adapter->link_duplex = 0; 2206 2207 if (!pci_channel_offline(adapter->pdev)) 2208 igb_reset(adapter); 2209 2210 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2211 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2212 2213 igb_clean_all_tx_rings(adapter); 2214 igb_clean_all_rx_rings(adapter); 2215 #ifdef CONFIG_IGB_DCA 2216 2217 /* since we reset the hardware DCA settings were cleared */ 2218 igb_setup_dca(adapter); 2219 #endif 2220 } 2221 2222 void igb_reinit_locked(struct igb_adapter *adapter) 2223 { 2224 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2225 usleep_range(1000, 2000); 2226 igb_down(adapter); 2227 igb_up(adapter); 2228 clear_bit(__IGB_RESETTING, &adapter->state); 2229 } 2230 2231 /** igb_enable_mas - Media Autosense re-enable after swap 2232 * 2233 * @adapter: adapter struct 2234 **/ 2235 static void igb_enable_mas(struct igb_adapter *adapter) 2236 { 2237 struct e1000_hw *hw = &adapter->hw; 2238 u32 connsw = rd32(E1000_CONNSW); 2239 2240 /* configure for SerDes media detect */ 2241 if ((hw->phy.media_type == e1000_media_type_copper) && 2242 (!(connsw & E1000_CONNSW_SERDESD))) { 2243 connsw |= E1000_CONNSW_ENRGSRC; 2244 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2245 wr32(E1000_CONNSW, connsw); 2246 wrfl(); 2247 } 2248 } 2249 2250 void igb_reset(struct igb_adapter *adapter) 2251 { 2252 struct pci_dev *pdev = adapter->pdev; 2253 struct e1000_hw *hw = &adapter->hw; 2254 struct e1000_mac_info *mac = &hw->mac; 2255 struct e1000_fc_info *fc = &hw->fc; 2256 u32 pba, hwm; 2257 2258 /* Repartition Pba for greater than 9k mtu 2259 * To take effect CTRL.RST is required. 2260 */ 2261 switch (mac->type) { 2262 case e1000_i350: 2263 case e1000_i354: 2264 case e1000_82580: 2265 pba = rd32(E1000_RXPBS); 2266 pba = igb_rxpbs_adjust_82580(pba); 2267 break; 2268 case e1000_82576: 2269 pba = rd32(E1000_RXPBS); 2270 pba &= E1000_RXPBS_SIZE_MASK_82576; 2271 break; 2272 case e1000_82575: 2273 case e1000_i210: 2274 case e1000_i211: 2275 default: 2276 pba = E1000_PBA_34K; 2277 break; 2278 } 2279 2280 if (mac->type == e1000_82575) { 2281 u32 min_rx_space, min_tx_space, needed_tx_space; 2282 2283 /* write Rx PBA so that hardware can report correct Tx PBA */ 2284 wr32(E1000_PBA, pba); 2285 2286 /* To maintain wire speed transmits, the Tx FIFO should be 2287 * large enough to accommodate two full transmit packets, 2288 * rounded up to the next 1KB and expressed in KB. Likewise, 2289 * the Rx FIFO should be large enough to accommodate at least 2290 * one full receive packet and is similarly rounded up and 2291 * expressed in KB. 2292 */ 2293 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2294 2295 /* The Tx FIFO also stores 16 bytes of information about the Tx 2296 * but don't include Ethernet FCS because hardware appends it. 2297 * We only need to round down to the nearest 512 byte block 2298 * count since the value we care about is 2 frames, not 1. 2299 */ 2300 min_tx_space = adapter->max_frame_size; 2301 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2302 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2303 2304 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2305 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2306 2307 /* If current Tx allocation is less than the min Tx FIFO size, 2308 * and the min Tx FIFO size is less than the current Rx FIFO 2309 * allocation, take space away from current Rx allocation. 2310 */ 2311 if (needed_tx_space < pba) { 2312 pba -= needed_tx_space; 2313 2314 /* if short on Rx space, Rx wins and must trump Tx 2315 * adjustment 2316 */ 2317 if (pba < min_rx_space) 2318 pba = min_rx_space; 2319 } 2320 2321 /* adjust PBA for jumbo frames */ 2322 wr32(E1000_PBA, pba); 2323 } 2324 2325 /* flow control settings 2326 * The high water mark must be low enough to fit one full frame 2327 * after transmitting the pause frame. As such we must have enough 2328 * space to allow for us to complete our current transmit and then 2329 * receive the frame that is in progress from the link partner. 2330 * Set it to: 2331 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2332 */ 2333 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2334 2335 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2336 fc->low_water = fc->high_water - 16; 2337 fc->pause_time = 0xFFFF; 2338 fc->send_xon = 1; 2339 fc->current_mode = fc->requested_mode; 2340 2341 /* disable receive for all VFs and wait one second */ 2342 if (adapter->vfs_allocated_count) { 2343 int i; 2344 2345 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2346 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2347 2348 /* ping all the active vfs to let them know we are going down */ 2349 igb_ping_all_vfs(adapter); 2350 2351 /* disable transmits and receives */ 2352 wr32(E1000_VFRE, 0); 2353 wr32(E1000_VFTE, 0); 2354 } 2355 2356 /* Allow time for pending master requests to run */ 2357 hw->mac.ops.reset_hw(hw); 2358 wr32(E1000_WUC, 0); 2359 2360 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2361 /* need to resetup here after media swap */ 2362 adapter->ei.get_invariants(hw); 2363 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2364 } 2365 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2366 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2367 igb_enable_mas(adapter); 2368 } 2369 if (hw->mac.ops.init_hw(hw)) 2370 dev_err(&pdev->dev, "Hardware Error\n"); 2371 2372 /* RAR registers were cleared during init_hw, clear mac table */ 2373 igb_flush_mac_table(adapter); 2374 __dev_uc_unsync(adapter->netdev, NULL); 2375 2376 /* Recover default RAR entry */ 2377 igb_set_default_mac_filter(adapter); 2378 2379 /* Flow control settings reset on hardware reset, so guarantee flow 2380 * control is off when forcing speed. 2381 */ 2382 if (!hw->mac.autoneg) 2383 igb_force_mac_fc(hw); 2384 2385 igb_init_dmac(adapter, pba); 2386 #ifdef CONFIG_IGB_HWMON 2387 /* Re-initialize the thermal sensor on i350 devices. */ 2388 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2389 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2390 /* If present, re-initialize the external thermal sensor 2391 * interface. 2392 */ 2393 if (adapter->ets) 2394 mac->ops.init_thermal_sensor_thresh(hw); 2395 } 2396 } 2397 #endif 2398 /* Re-establish EEE setting */ 2399 if (hw->phy.media_type == e1000_media_type_copper) { 2400 switch (mac->type) { 2401 case e1000_i350: 2402 case e1000_i210: 2403 case e1000_i211: 2404 igb_set_eee_i350(hw, true, true); 2405 break; 2406 case e1000_i354: 2407 igb_set_eee_i354(hw, true, true); 2408 break; 2409 default: 2410 break; 2411 } 2412 } 2413 if (!netif_running(adapter->netdev)) 2414 igb_power_down_link(adapter); 2415 2416 igb_update_mng_vlan(adapter); 2417 2418 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2419 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2420 2421 /* Re-enable PTP, where applicable. */ 2422 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2423 igb_ptp_reset(adapter); 2424 2425 igb_get_phy_info(hw); 2426 } 2427 2428 static netdev_features_t igb_fix_features(struct net_device *netdev, 2429 netdev_features_t features) 2430 { 2431 /* Since there is no support for separate Rx/Tx vlan accel 2432 * enable/disable make sure Tx flag is always in same state as Rx. 2433 */ 2434 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2435 features |= NETIF_F_HW_VLAN_CTAG_TX; 2436 else 2437 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2438 2439 return features; 2440 } 2441 2442 static int igb_set_features(struct net_device *netdev, 2443 netdev_features_t features) 2444 { 2445 netdev_features_t changed = netdev->features ^ features; 2446 struct igb_adapter *adapter = netdev_priv(netdev); 2447 2448 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2449 igb_vlan_mode(netdev, features); 2450 2451 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2452 return 0; 2453 2454 if (!(features & NETIF_F_NTUPLE)) { 2455 struct hlist_node *node2; 2456 struct igb_nfc_filter *rule; 2457 2458 spin_lock(&adapter->nfc_lock); 2459 hlist_for_each_entry_safe(rule, node2, 2460 &adapter->nfc_filter_list, nfc_node) { 2461 igb_erase_filter(adapter, rule); 2462 hlist_del(&rule->nfc_node); 2463 kfree(rule); 2464 } 2465 spin_unlock(&adapter->nfc_lock); 2466 adapter->nfc_filter_count = 0; 2467 } 2468 2469 netdev->features = features; 2470 2471 if (netif_running(netdev)) 2472 igb_reinit_locked(adapter); 2473 else 2474 igb_reset(adapter); 2475 2476 return 1; 2477 } 2478 2479 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2480 struct net_device *dev, 2481 const unsigned char *addr, u16 vid, 2482 u16 flags, 2483 struct netlink_ext_ack *extack) 2484 { 2485 /* guarantee we can provide a unique filter for the unicast address */ 2486 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2487 struct igb_adapter *adapter = netdev_priv(dev); 2488 int vfn = adapter->vfs_allocated_count; 2489 2490 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2491 return -ENOMEM; 2492 } 2493 2494 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2495 } 2496 2497 #define IGB_MAX_MAC_HDR_LEN 127 2498 #define IGB_MAX_NETWORK_HDR_LEN 511 2499 2500 static netdev_features_t 2501 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2502 netdev_features_t features) 2503 { 2504 unsigned int network_hdr_len, mac_hdr_len; 2505 2506 /* Make certain the headers can be described by a context descriptor */ 2507 mac_hdr_len = skb_network_header(skb) - skb->data; 2508 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2509 return features & ~(NETIF_F_HW_CSUM | 2510 NETIF_F_SCTP_CRC | 2511 NETIF_F_GSO_UDP_L4 | 2512 NETIF_F_HW_VLAN_CTAG_TX | 2513 NETIF_F_TSO | 2514 NETIF_F_TSO6); 2515 2516 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2517 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2518 return features & ~(NETIF_F_HW_CSUM | 2519 NETIF_F_SCTP_CRC | 2520 NETIF_F_GSO_UDP_L4 | 2521 NETIF_F_TSO | 2522 NETIF_F_TSO6); 2523 2524 /* We can only support IPV4 TSO in tunnels if we can mangle the 2525 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2526 */ 2527 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2528 features &= ~NETIF_F_TSO; 2529 2530 return features; 2531 } 2532 2533 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2534 { 2535 if (!is_fqtss_enabled(adapter)) { 2536 enable_fqtss(adapter, true); 2537 return; 2538 } 2539 2540 igb_config_tx_modes(adapter, queue); 2541 2542 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2543 enable_fqtss(adapter, false); 2544 } 2545 2546 static int igb_offload_cbs(struct igb_adapter *adapter, 2547 struct tc_cbs_qopt_offload *qopt) 2548 { 2549 struct e1000_hw *hw = &adapter->hw; 2550 int err; 2551 2552 /* CBS offloading is only supported by i210 controller. */ 2553 if (hw->mac.type != e1000_i210) 2554 return -EOPNOTSUPP; 2555 2556 /* CBS offloading is only supported by queue 0 and queue 1. */ 2557 if (qopt->queue < 0 || qopt->queue > 1) 2558 return -EINVAL; 2559 2560 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2561 qopt->idleslope, qopt->sendslope, 2562 qopt->hicredit, qopt->locredit); 2563 if (err) 2564 return err; 2565 2566 igb_offload_apply(adapter, qopt->queue); 2567 2568 return 0; 2569 } 2570 2571 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2572 #define VLAN_PRIO_FULL_MASK (0x07) 2573 2574 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2575 struct flow_cls_offload *f, 2576 int traffic_class, 2577 struct igb_nfc_filter *input) 2578 { 2579 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2580 struct flow_dissector *dissector = rule->match.dissector; 2581 struct netlink_ext_ack *extack = f->common.extack; 2582 2583 if (dissector->used_keys & 2584 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) | 2585 BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2586 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2587 BIT(FLOW_DISSECTOR_KEY_VLAN))) { 2588 NL_SET_ERR_MSG_MOD(extack, 2589 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2590 return -EOPNOTSUPP; 2591 } 2592 2593 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2594 struct flow_match_eth_addrs match; 2595 2596 flow_rule_match_eth_addrs(rule, &match); 2597 if (!is_zero_ether_addr(match.mask->dst)) { 2598 if (!is_broadcast_ether_addr(match.mask->dst)) { 2599 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2600 return -EINVAL; 2601 } 2602 2603 input->filter.match_flags |= 2604 IGB_FILTER_FLAG_DST_MAC_ADDR; 2605 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2606 } 2607 2608 if (!is_zero_ether_addr(match.mask->src)) { 2609 if (!is_broadcast_ether_addr(match.mask->src)) { 2610 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2611 return -EINVAL; 2612 } 2613 2614 input->filter.match_flags |= 2615 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2616 ether_addr_copy(input->filter.src_addr, match.key->src); 2617 } 2618 } 2619 2620 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2621 struct flow_match_basic match; 2622 2623 flow_rule_match_basic(rule, &match); 2624 if (match.mask->n_proto) { 2625 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2626 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2627 return -EINVAL; 2628 } 2629 2630 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2631 input->filter.etype = match.key->n_proto; 2632 } 2633 } 2634 2635 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2636 struct flow_match_vlan match; 2637 2638 flow_rule_match_vlan(rule, &match); 2639 if (match.mask->vlan_priority) { 2640 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2641 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2642 return -EINVAL; 2643 } 2644 2645 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2646 input->filter.vlan_tci = match.key->vlan_priority; 2647 } 2648 } 2649 2650 input->action = traffic_class; 2651 input->cookie = f->cookie; 2652 2653 return 0; 2654 } 2655 2656 static int igb_configure_clsflower(struct igb_adapter *adapter, 2657 struct flow_cls_offload *cls_flower) 2658 { 2659 struct netlink_ext_ack *extack = cls_flower->common.extack; 2660 struct igb_nfc_filter *filter, *f; 2661 int err, tc; 2662 2663 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2664 if (tc < 0) { 2665 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2666 return -EINVAL; 2667 } 2668 2669 filter = kzalloc(sizeof(*filter), GFP_KERNEL); 2670 if (!filter) 2671 return -ENOMEM; 2672 2673 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2674 if (err < 0) 2675 goto err_parse; 2676 2677 spin_lock(&adapter->nfc_lock); 2678 2679 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2680 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2681 err = -EEXIST; 2682 NL_SET_ERR_MSG_MOD(extack, 2683 "This filter is already set in ethtool"); 2684 goto err_locked; 2685 } 2686 } 2687 2688 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2690 err = -EEXIST; 2691 NL_SET_ERR_MSG_MOD(extack, 2692 "This filter is already set in cls_flower"); 2693 goto err_locked; 2694 } 2695 } 2696 2697 err = igb_add_filter(adapter, filter); 2698 if (err < 0) { 2699 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2700 goto err_locked; 2701 } 2702 2703 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2704 2705 spin_unlock(&adapter->nfc_lock); 2706 2707 return 0; 2708 2709 err_locked: 2710 spin_unlock(&adapter->nfc_lock); 2711 2712 err_parse: 2713 kfree(filter); 2714 2715 return err; 2716 } 2717 2718 static int igb_delete_clsflower(struct igb_adapter *adapter, 2719 struct flow_cls_offload *cls_flower) 2720 { 2721 struct igb_nfc_filter *filter; 2722 int err; 2723 2724 spin_lock(&adapter->nfc_lock); 2725 2726 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2727 if (filter->cookie == cls_flower->cookie) 2728 break; 2729 2730 if (!filter) { 2731 err = -ENOENT; 2732 goto out; 2733 } 2734 2735 err = igb_erase_filter(adapter, filter); 2736 if (err < 0) 2737 goto out; 2738 2739 hlist_del(&filter->nfc_node); 2740 kfree(filter); 2741 2742 out: 2743 spin_unlock(&adapter->nfc_lock); 2744 2745 return err; 2746 } 2747 2748 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2749 struct flow_cls_offload *cls_flower) 2750 { 2751 switch (cls_flower->command) { 2752 case FLOW_CLS_REPLACE: 2753 return igb_configure_clsflower(adapter, cls_flower); 2754 case FLOW_CLS_DESTROY: 2755 return igb_delete_clsflower(adapter, cls_flower); 2756 case FLOW_CLS_STATS: 2757 return -EOPNOTSUPP; 2758 default: 2759 return -EOPNOTSUPP; 2760 } 2761 } 2762 2763 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2764 void *cb_priv) 2765 { 2766 struct igb_adapter *adapter = cb_priv; 2767 2768 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2769 return -EOPNOTSUPP; 2770 2771 switch (type) { 2772 case TC_SETUP_CLSFLOWER: 2773 return igb_setup_tc_cls_flower(adapter, type_data); 2774 2775 default: 2776 return -EOPNOTSUPP; 2777 } 2778 } 2779 2780 static int igb_offload_txtime(struct igb_adapter *adapter, 2781 struct tc_etf_qopt_offload *qopt) 2782 { 2783 struct e1000_hw *hw = &adapter->hw; 2784 int err; 2785 2786 /* Launchtime offloading is only supported by i210 controller. */ 2787 if (hw->mac.type != e1000_i210) 2788 return -EOPNOTSUPP; 2789 2790 /* Launchtime offloading is only supported by queues 0 and 1. */ 2791 if (qopt->queue < 0 || qopt->queue > 1) 2792 return -EINVAL; 2793 2794 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2795 if (err) 2796 return err; 2797 2798 igb_offload_apply(adapter, qopt->queue); 2799 2800 return 0; 2801 } 2802 2803 static LIST_HEAD(igb_block_cb_list); 2804 2805 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2806 void *type_data) 2807 { 2808 struct igb_adapter *adapter = netdev_priv(dev); 2809 2810 switch (type) { 2811 case TC_SETUP_QDISC_CBS: 2812 return igb_offload_cbs(adapter, type_data); 2813 case TC_SETUP_BLOCK: 2814 return flow_block_cb_setup_simple(type_data, 2815 &igb_block_cb_list, 2816 igb_setup_tc_block_cb, 2817 adapter, adapter, true); 2818 2819 case TC_SETUP_QDISC_ETF: 2820 return igb_offload_txtime(adapter, type_data); 2821 2822 default: 2823 return -EOPNOTSUPP; 2824 } 2825 } 2826 2827 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2828 { 2829 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2830 struct igb_adapter *adapter = netdev_priv(dev); 2831 struct bpf_prog *prog = bpf->prog, *old_prog; 2832 bool running = netif_running(dev); 2833 bool need_reset; 2834 2835 /* verify igb ring attributes are sufficient for XDP */ 2836 for (i = 0; i < adapter->num_rx_queues; i++) { 2837 struct igb_ring *ring = adapter->rx_ring[i]; 2838 2839 if (frame_size > igb_rx_bufsz(ring)) { 2840 NL_SET_ERR_MSG_MOD(bpf->extack, 2841 "The RX buffer size is too small for the frame size"); 2842 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2843 igb_rx_bufsz(ring), frame_size); 2844 return -EINVAL; 2845 } 2846 } 2847 2848 old_prog = xchg(&adapter->xdp_prog, prog); 2849 need_reset = (!!prog != !!old_prog); 2850 2851 /* device is up and bpf is added/removed, must setup the RX queues */ 2852 if (need_reset && running) { 2853 igb_close(dev); 2854 } else { 2855 for (i = 0; i < adapter->num_rx_queues; i++) 2856 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2857 adapter->xdp_prog); 2858 } 2859 2860 if (old_prog) 2861 bpf_prog_put(old_prog); 2862 2863 /* bpf is just replaced, RXQ and MTU are already setup */ 2864 if (!need_reset) 2865 return 0; 2866 2867 if (running) 2868 igb_open(dev); 2869 2870 return 0; 2871 } 2872 2873 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2874 { 2875 switch (xdp->command) { 2876 case XDP_SETUP_PROG: 2877 return igb_xdp_setup(dev, xdp); 2878 default: 2879 return -EINVAL; 2880 } 2881 } 2882 2883 static void igb_xdp_ring_update_tail(struct igb_ring *ring) 2884 { 2885 /* Force memory writes to complete before letting h/w know there 2886 * are new descriptors to fetch. 2887 */ 2888 wmb(); 2889 writel(ring->next_to_use, ring->tail); 2890 } 2891 2892 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter) 2893 { 2894 unsigned int r_idx = smp_processor_id(); 2895 2896 if (r_idx >= adapter->num_tx_queues) 2897 r_idx = r_idx % adapter->num_tx_queues; 2898 2899 return adapter->tx_ring[r_idx]; 2900 } 2901 2902 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2903 { 2904 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2905 int cpu = smp_processor_id(); 2906 struct igb_ring *tx_ring; 2907 struct netdev_queue *nq; 2908 u32 ret; 2909 2910 if (unlikely(!xdpf)) 2911 return IGB_XDP_CONSUMED; 2912 2913 /* During program transitions its possible adapter->xdp_prog is assigned 2914 * but ring has not been configured yet. In this case simply abort xmit. 2915 */ 2916 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2917 if (unlikely(!tx_ring)) 2918 return IGB_XDP_CONSUMED; 2919 2920 nq = txring_txq(tx_ring); 2921 __netif_tx_lock(nq, cpu); 2922 /* Avoid transmit queue timeout since we share it with the slow path */ 2923 nq->trans_start = jiffies; 2924 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2925 __netif_tx_unlock(nq); 2926 2927 return ret; 2928 } 2929 2930 static int igb_xdp_xmit(struct net_device *dev, int n, 2931 struct xdp_frame **frames, u32 flags) 2932 { 2933 struct igb_adapter *adapter = netdev_priv(dev); 2934 int cpu = smp_processor_id(); 2935 struct igb_ring *tx_ring; 2936 struct netdev_queue *nq; 2937 int drops = 0; 2938 int i; 2939 2940 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2941 return -ENETDOWN; 2942 2943 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2944 return -EINVAL; 2945 2946 /* During program transitions its possible adapter->xdp_prog is assigned 2947 * but ring has not been configured yet. In this case simply abort xmit. 2948 */ 2949 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL; 2950 if (unlikely(!tx_ring)) 2951 return -ENXIO; 2952 2953 nq = txring_txq(tx_ring); 2954 __netif_tx_lock(nq, cpu); 2955 2956 /* Avoid transmit queue timeout since we share it with the slow path */ 2957 nq->trans_start = jiffies; 2958 2959 for (i = 0; i < n; i++) { 2960 struct xdp_frame *xdpf = frames[i]; 2961 int err; 2962 2963 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2964 if (err != IGB_XDP_TX) { 2965 xdp_return_frame_rx_napi(xdpf); 2966 drops++; 2967 } 2968 } 2969 2970 __netif_tx_unlock(nq); 2971 2972 if (unlikely(flags & XDP_XMIT_FLUSH)) 2973 igb_xdp_ring_update_tail(tx_ring); 2974 2975 return n - drops; 2976 } 2977 2978 static const struct net_device_ops igb_netdev_ops = { 2979 .ndo_open = igb_open, 2980 .ndo_stop = igb_close, 2981 .ndo_start_xmit = igb_xmit_frame, 2982 .ndo_get_stats64 = igb_get_stats64, 2983 .ndo_set_rx_mode = igb_set_rx_mode, 2984 .ndo_set_mac_address = igb_set_mac, 2985 .ndo_change_mtu = igb_change_mtu, 2986 .ndo_do_ioctl = igb_ioctl, 2987 .ndo_tx_timeout = igb_tx_timeout, 2988 .ndo_validate_addr = eth_validate_addr, 2989 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2990 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2991 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2992 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2993 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 2994 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2995 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 2996 .ndo_get_vf_config = igb_ndo_get_vf_config, 2997 .ndo_fix_features = igb_fix_features, 2998 .ndo_set_features = igb_set_features, 2999 .ndo_fdb_add = igb_ndo_fdb_add, 3000 .ndo_features_check = igb_features_check, 3001 .ndo_setup_tc = igb_setup_tc, 3002 .ndo_bpf = igb_xdp, 3003 .ndo_xdp_xmit = igb_xdp_xmit, 3004 }; 3005 3006 /** 3007 * igb_set_fw_version - Configure version string for ethtool 3008 * @adapter: adapter struct 3009 **/ 3010 void igb_set_fw_version(struct igb_adapter *adapter) 3011 { 3012 struct e1000_hw *hw = &adapter->hw; 3013 struct e1000_fw_version fw; 3014 3015 igb_get_fw_version(hw, &fw); 3016 3017 switch (hw->mac.type) { 3018 case e1000_i210: 3019 case e1000_i211: 3020 if (!(igb_get_flash_presence_i210(hw))) { 3021 snprintf(adapter->fw_version, 3022 sizeof(adapter->fw_version), 3023 "%2d.%2d-%d", 3024 fw.invm_major, fw.invm_minor, 3025 fw.invm_img_type); 3026 break; 3027 } 3028 fallthrough; 3029 default: 3030 /* if option is rom valid, display its version too */ 3031 if (fw.or_valid) { 3032 snprintf(adapter->fw_version, 3033 sizeof(adapter->fw_version), 3034 "%d.%d, 0x%08x, %d.%d.%d", 3035 fw.eep_major, fw.eep_minor, fw.etrack_id, 3036 fw.or_major, fw.or_build, fw.or_patch); 3037 /* no option rom */ 3038 } else if (fw.etrack_id != 0X0000) { 3039 snprintf(adapter->fw_version, 3040 sizeof(adapter->fw_version), 3041 "%d.%d, 0x%08x", 3042 fw.eep_major, fw.eep_minor, fw.etrack_id); 3043 } else { 3044 snprintf(adapter->fw_version, 3045 sizeof(adapter->fw_version), 3046 "%d.%d.%d", 3047 fw.eep_major, fw.eep_minor, fw.eep_build); 3048 } 3049 break; 3050 } 3051 } 3052 3053 /** 3054 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3055 * 3056 * @adapter: adapter struct 3057 **/ 3058 static void igb_init_mas(struct igb_adapter *adapter) 3059 { 3060 struct e1000_hw *hw = &adapter->hw; 3061 u16 eeprom_data; 3062 3063 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3064 switch (hw->bus.func) { 3065 case E1000_FUNC_0: 3066 if (eeprom_data & IGB_MAS_ENABLE_0) { 3067 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3068 netdev_info(adapter->netdev, 3069 "MAS: Enabling Media Autosense for port %d\n", 3070 hw->bus.func); 3071 } 3072 break; 3073 case E1000_FUNC_1: 3074 if (eeprom_data & IGB_MAS_ENABLE_1) { 3075 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3076 netdev_info(adapter->netdev, 3077 "MAS: Enabling Media Autosense for port %d\n", 3078 hw->bus.func); 3079 } 3080 break; 3081 case E1000_FUNC_2: 3082 if (eeprom_data & IGB_MAS_ENABLE_2) { 3083 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3084 netdev_info(adapter->netdev, 3085 "MAS: Enabling Media Autosense for port %d\n", 3086 hw->bus.func); 3087 } 3088 break; 3089 case E1000_FUNC_3: 3090 if (eeprom_data & IGB_MAS_ENABLE_3) { 3091 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3092 netdev_info(adapter->netdev, 3093 "MAS: Enabling Media Autosense for port %d\n", 3094 hw->bus.func); 3095 } 3096 break; 3097 default: 3098 /* Shouldn't get here */ 3099 netdev_err(adapter->netdev, 3100 "MAS: Invalid port configuration, returning\n"); 3101 break; 3102 } 3103 } 3104 3105 /** 3106 * igb_init_i2c - Init I2C interface 3107 * @adapter: pointer to adapter structure 3108 **/ 3109 static s32 igb_init_i2c(struct igb_adapter *adapter) 3110 { 3111 s32 status = 0; 3112 3113 /* I2C interface supported on i350 devices */ 3114 if (adapter->hw.mac.type != e1000_i350) 3115 return 0; 3116 3117 /* Initialize the i2c bus which is controlled by the registers. 3118 * This bus will use the i2c_algo_bit structue that implements 3119 * the protocol through toggling of the 4 bits in the register. 3120 */ 3121 adapter->i2c_adap.owner = THIS_MODULE; 3122 adapter->i2c_algo = igb_i2c_algo; 3123 adapter->i2c_algo.data = adapter; 3124 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3125 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3126 strlcpy(adapter->i2c_adap.name, "igb BB", 3127 sizeof(adapter->i2c_adap.name)); 3128 status = i2c_bit_add_bus(&adapter->i2c_adap); 3129 return status; 3130 } 3131 3132 /** 3133 * igb_probe - Device Initialization Routine 3134 * @pdev: PCI device information struct 3135 * @ent: entry in igb_pci_tbl 3136 * 3137 * Returns 0 on success, negative on failure 3138 * 3139 * igb_probe initializes an adapter identified by a pci_dev structure. 3140 * The OS initialization, configuring of the adapter private structure, 3141 * and a hardware reset occur. 3142 **/ 3143 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3144 { 3145 struct net_device *netdev; 3146 struct igb_adapter *adapter; 3147 struct e1000_hw *hw; 3148 u16 eeprom_data = 0; 3149 s32 ret_val; 3150 static int global_quad_port_a; /* global quad port a indication */ 3151 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3152 int err, pci_using_dac; 3153 u8 part_str[E1000_PBANUM_LENGTH]; 3154 3155 /* Catch broken hardware that put the wrong VF device ID in 3156 * the PCIe SR-IOV capability. 3157 */ 3158 if (pdev->is_virtfn) { 3159 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 3160 pci_name(pdev), pdev->vendor, pdev->device); 3161 return -EINVAL; 3162 } 3163 3164 err = pci_enable_device_mem(pdev); 3165 if (err) 3166 return err; 3167 3168 pci_using_dac = 0; 3169 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3170 if (!err) { 3171 pci_using_dac = 1; 3172 } else { 3173 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3174 if (err) { 3175 dev_err(&pdev->dev, 3176 "No usable DMA configuration, aborting\n"); 3177 goto err_dma; 3178 } 3179 } 3180 3181 err = pci_request_mem_regions(pdev, igb_driver_name); 3182 if (err) 3183 goto err_pci_reg; 3184 3185 pci_enable_pcie_error_reporting(pdev); 3186 3187 pci_set_master(pdev); 3188 pci_save_state(pdev); 3189 3190 err = -ENOMEM; 3191 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3192 IGB_MAX_TX_QUEUES); 3193 if (!netdev) 3194 goto err_alloc_etherdev; 3195 3196 SET_NETDEV_DEV(netdev, &pdev->dev); 3197 3198 pci_set_drvdata(pdev, netdev); 3199 adapter = netdev_priv(netdev); 3200 adapter->netdev = netdev; 3201 adapter->pdev = pdev; 3202 hw = &adapter->hw; 3203 hw->back = adapter; 3204 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3205 3206 err = -EIO; 3207 adapter->io_addr = pci_iomap(pdev, 0, 0); 3208 if (!adapter->io_addr) 3209 goto err_ioremap; 3210 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3211 hw->hw_addr = adapter->io_addr; 3212 3213 netdev->netdev_ops = &igb_netdev_ops; 3214 igb_set_ethtool_ops(netdev); 3215 netdev->watchdog_timeo = 5 * HZ; 3216 3217 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 3218 3219 netdev->mem_start = pci_resource_start(pdev, 0); 3220 netdev->mem_end = pci_resource_end(pdev, 0); 3221 3222 /* PCI config space info */ 3223 hw->vendor_id = pdev->vendor; 3224 hw->device_id = pdev->device; 3225 hw->revision_id = pdev->revision; 3226 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3227 hw->subsystem_device_id = pdev->subsystem_device; 3228 3229 /* Copy the default MAC, PHY and NVM function pointers */ 3230 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3231 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3232 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3233 /* Initialize skew-specific constants */ 3234 err = ei->get_invariants(hw); 3235 if (err) 3236 goto err_sw_init; 3237 3238 /* setup the private structure */ 3239 err = igb_sw_init(adapter); 3240 if (err) 3241 goto err_sw_init; 3242 3243 igb_get_bus_info_pcie(hw); 3244 3245 hw->phy.autoneg_wait_to_complete = false; 3246 3247 /* Copper options */ 3248 if (hw->phy.media_type == e1000_media_type_copper) { 3249 hw->phy.mdix = AUTO_ALL_MODES; 3250 hw->phy.disable_polarity_correction = false; 3251 hw->phy.ms_type = e1000_ms_hw_default; 3252 } 3253 3254 if (igb_check_reset_block(hw)) 3255 dev_info(&pdev->dev, 3256 "PHY reset is blocked due to SOL/IDER session.\n"); 3257 3258 /* features is initialized to 0 in allocation, it might have bits 3259 * set by igb_sw_init so we should use an or instead of an 3260 * assignment. 3261 */ 3262 netdev->features |= NETIF_F_SG | 3263 NETIF_F_TSO | 3264 NETIF_F_TSO6 | 3265 NETIF_F_RXHASH | 3266 NETIF_F_RXCSUM | 3267 NETIF_F_HW_CSUM; 3268 3269 if (hw->mac.type >= e1000_82576) 3270 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3271 3272 if (hw->mac.type >= e1000_i350) 3273 netdev->features |= NETIF_F_HW_TC; 3274 3275 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3276 NETIF_F_GSO_GRE_CSUM | \ 3277 NETIF_F_GSO_IPXIP4 | \ 3278 NETIF_F_GSO_IPXIP6 | \ 3279 NETIF_F_GSO_UDP_TUNNEL | \ 3280 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3281 3282 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3283 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3284 3285 /* copy netdev features into list of user selectable features */ 3286 netdev->hw_features |= netdev->features | 3287 NETIF_F_HW_VLAN_CTAG_RX | 3288 NETIF_F_HW_VLAN_CTAG_TX | 3289 NETIF_F_RXALL; 3290 3291 if (hw->mac.type >= e1000_i350) 3292 netdev->hw_features |= NETIF_F_NTUPLE; 3293 3294 if (pci_using_dac) 3295 netdev->features |= NETIF_F_HIGHDMA; 3296 3297 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3298 netdev->mpls_features |= NETIF_F_HW_CSUM; 3299 netdev->hw_enc_features |= netdev->vlan_features; 3300 3301 /* set this bit last since it cannot be part of vlan_features */ 3302 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3303 NETIF_F_HW_VLAN_CTAG_RX | 3304 NETIF_F_HW_VLAN_CTAG_TX; 3305 3306 netdev->priv_flags |= IFF_SUPP_NOFCS; 3307 3308 netdev->priv_flags |= IFF_UNICAST_FLT; 3309 3310 /* MTU range: 68 - 9216 */ 3311 netdev->min_mtu = ETH_MIN_MTU; 3312 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3313 3314 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3315 3316 /* before reading the NVM, reset the controller to put the device in a 3317 * known good starting state 3318 */ 3319 hw->mac.ops.reset_hw(hw); 3320 3321 /* make sure the NVM is good , i211/i210 parts can have special NVM 3322 * that doesn't contain a checksum 3323 */ 3324 switch (hw->mac.type) { 3325 case e1000_i210: 3326 case e1000_i211: 3327 if (igb_get_flash_presence_i210(hw)) { 3328 if (hw->nvm.ops.validate(hw) < 0) { 3329 dev_err(&pdev->dev, 3330 "The NVM Checksum Is Not Valid\n"); 3331 err = -EIO; 3332 goto err_eeprom; 3333 } 3334 } 3335 break; 3336 default: 3337 if (hw->nvm.ops.validate(hw) < 0) { 3338 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3339 err = -EIO; 3340 goto err_eeprom; 3341 } 3342 break; 3343 } 3344 3345 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3346 /* copy the MAC address out of the NVM */ 3347 if (hw->mac.ops.read_mac_addr(hw)) 3348 dev_err(&pdev->dev, "NVM Read Error\n"); 3349 } 3350 3351 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3352 3353 if (!is_valid_ether_addr(netdev->dev_addr)) { 3354 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3355 err = -EIO; 3356 goto err_eeprom; 3357 } 3358 3359 igb_set_default_mac_filter(adapter); 3360 3361 /* get firmware version for ethtool -i */ 3362 igb_set_fw_version(adapter); 3363 3364 /* configure RXPBSIZE and TXPBSIZE */ 3365 if (hw->mac.type == e1000_i210) { 3366 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3367 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3368 } 3369 3370 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3371 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3372 3373 INIT_WORK(&adapter->reset_task, igb_reset_task); 3374 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3375 3376 /* Initialize link properties that are user-changeable */ 3377 adapter->fc_autoneg = true; 3378 hw->mac.autoneg = true; 3379 hw->phy.autoneg_advertised = 0x2f; 3380 3381 hw->fc.requested_mode = e1000_fc_default; 3382 hw->fc.current_mode = e1000_fc_default; 3383 3384 igb_validate_mdi_setting(hw); 3385 3386 /* By default, support wake on port A */ 3387 if (hw->bus.func == 0) 3388 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3389 3390 /* Check the NVM for wake support on non-port A ports */ 3391 if (hw->mac.type >= e1000_82580) 3392 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3393 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3394 &eeprom_data); 3395 else if (hw->bus.func == 1) 3396 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3397 3398 if (eeprom_data & IGB_EEPROM_APME) 3399 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3400 3401 /* now that we have the eeprom settings, apply the special cases where 3402 * the eeprom may be wrong or the board simply won't support wake on 3403 * lan on a particular port 3404 */ 3405 switch (pdev->device) { 3406 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3407 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3408 break; 3409 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3410 case E1000_DEV_ID_82576_FIBER: 3411 case E1000_DEV_ID_82576_SERDES: 3412 /* Wake events only supported on port A for dual fiber 3413 * regardless of eeprom setting 3414 */ 3415 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3416 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3417 break; 3418 case E1000_DEV_ID_82576_QUAD_COPPER: 3419 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3420 /* if quad port adapter, disable WoL on all but port A */ 3421 if (global_quad_port_a != 0) 3422 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3423 else 3424 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3425 /* Reset for multiple quad port adapters */ 3426 if (++global_quad_port_a == 4) 3427 global_quad_port_a = 0; 3428 break; 3429 default: 3430 /* If the device can't wake, don't set software support */ 3431 if (!device_can_wakeup(&adapter->pdev->dev)) 3432 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3433 } 3434 3435 /* initialize the wol settings based on the eeprom settings */ 3436 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3437 adapter->wol |= E1000_WUFC_MAG; 3438 3439 /* Some vendors want WoL disabled by default, but still supported */ 3440 if ((hw->mac.type == e1000_i350) && 3441 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3443 adapter->wol = 0; 3444 } 3445 3446 /* Some vendors want the ability to Use the EEPROM setting as 3447 * enable/disable only, and not for capability 3448 */ 3449 if (((hw->mac.type == e1000_i350) || 3450 (hw->mac.type == e1000_i354)) && 3451 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3452 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3453 adapter->wol = 0; 3454 } 3455 if (hw->mac.type == e1000_i350) { 3456 if (((pdev->subsystem_device == 0x5001) || 3457 (pdev->subsystem_device == 0x5002)) && 3458 (hw->bus.func == 0)) { 3459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3460 adapter->wol = 0; 3461 } 3462 if (pdev->subsystem_device == 0x1F52) 3463 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3464 } 3465 3466 device_set_wakeup_enable(&adapter->pdev->dev, 3467 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3468 3469 /* reset the hardware with the new settings */ 3470 igb_reset(adapter); 3471 3472 /* Init the I2C interface */ 3473 err = igb_init_i2c(adapter); 3474 if (err) { 3475 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3476 goto err_eeprom; 3477 } 3478 3479 /* let the f/w know that the h/w is now under the control of the 3480 * driver. 3481 */ 3482 igb_get_hw_control(adapter); 3483 3484 strcpy(netdev->name, "eth%d"); 3485 err = register_netdev(netdev); 3486 if (err) 3487 goto err_register; 3488 3489 /* carrier off reporting is important to ethtool even BEFORE open */ 3490 netif_carrier_off(netdev); 3491 3492 #ifdef CONFIG_IGB_DCA 3493 if (dca_add_requester(&pdev->dev) == 0) { 3494 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3495 dev_info(&pdev->dev, "DCA enabled\n"); 3496 igb_setup_dca(adapter); 3497 } 3498 3499 #endif 3500 #ifdef CONFIG_IGB_HWMON 3501 /* Initialize the thermal sensor on i350 devices. */ 3502 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3503 u16 ets_word; 3504 3505 /* Read the NVM to determine if this i350 device supports an 3506 * external thermal sensor. 3507 */ 3508 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3509 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3510 adapter->ets = true; 3511 else 3512 adapter->ets = false; 3513 if (igb_sysfs_init(adapter)) 3514 dev_err(&pdev->dev, 3515 "failed to allocate sysfs resources\n"); 3516 } else { 3517 adapter->ets = false; 3518 } 3519 #endif 3520 /* Check if Media Autosense is enabled */ 3521 adapter->ei = *ei; 3522 if (hw->dev_spec._82575.mas_capable) 3523 igb_init_mas(adapter); 3524 3525 /* do hw tstamp init after resetting */ 3526 igb_ptp_init(adapter); 3527 3528 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3529 /* print bus type/speed/width info, not applicable to i354 */ 3530 if (hw->mac.type != e1000_i354) { 3531 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3532 netdev->name, 3533 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3534 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3535 "unknown"), 3536 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3537 "Width x4" : 3538 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3539 "Width x2" : 3540 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3541 "Width x1" : "unknown"), netdev->dev_addr); 3542 } 3543 3544 if ((hw->mac.type == e1000_82576 && 3545 rd32(E1000_EECD) & E1000_EECD_PRES) || 3546 (hw->mac.type >= e1000_i210 || 3547 igb_get_flash_presence_i210(hw))) { 3548 ret_val = igb_read_part_string(hw, part_str, 3549 E1000_PBANUM_LENGTH); 3550 } else { 3551 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3552 } 3553 3554 if (ret_val) 3555 strcpy(part_str, "Unknown"); 3556 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3557 dev_info(&pdev->dev, 3558 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3559 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3560 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3561 adapter->num_rx_queues, adapter->num_tx_queues); 3562 if (hw->phy.media_type == e1000_media_type_copper) { 3563 switch (hw->mac.type) { 3564 case e1000_i350: 3565 case e1000_i210: 3566 case e1000_i211: 3567 /* Enable EEE for internal copper PHY devices */ 3568 err = igb_set_eee_i350(hw, true, true); 3569 if ((!err) && 3570 (!hw->dev_spec._82575.eee_disable)) { 3571 adapter->eee_advert = 3572 MDIO_EEE_100TX | MDIO_EEE_1000T; 3573 adapter->flags |= IGB_FLAG_EEE; 3574 } 3575 break; 3576 case e1000_i354: 3577 if ((rd32(E1000_CTRL_EXT) & 3578 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3579 err = igb_set_eee_i354(hw, true, true); 3580 if ((!err) && 3581 (!hw->dev_spec._82575.eee_disable)) { 3582 adapter->eee_advert = 3583 MDIO_EEE_100TX | MDIO_EEE_1000T; 3584 adapter->flags |= IGB_FLAG_EEE; 3585 } 3586 } 3587 break; 3588 default: 3589 break; 3590 } 3591 } 3592 3593 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3594 3595 pm_runtime_put_noidle(&pdev->dev); 3596 return 0; 3597 3598 err_register: 3599 igb_release_hw_control(adapter); 3600 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3601 err_eeprom: 3602 if (!igb_check_reset_block(hw)) 3603 igb_reset_phy(hw); 3604 3605 if (hw->flash_address) 3606 iounmap(hw->flash_address); 3607 err_sw_init: 3608 kfree(adapter->mac_table); 3609 kfree(adapter->shadow_vfta); 3610 igb_clear_interrupt_scheme(adapter); 3611 #ifdef CONFIG_PCI_IOV 3612 igb_disable_sriov(pdev); 3613 #endif 3614 pci_iounmap(pdev, adapter->io_addr); 3615 err_ioremap: 3616 free_netdev(netdev); 3617 err_alloc_etherdev: 3618 pci_release_mem_regions(pdev); 3619 err_pci_reg: 3620 err_dma: 3621 pci_disable_device(pdev); 3622 return err; 3623 } 3624 3625 #ifdef CONFIG_PCI_IOV 3626 static int igb_disable_sriov(struct pci_dev *pdev) 3627 { 3628 struct net_device *netdev = pci_get_drvdata(pdev); 3629 struct igb_adapter *adapter = netdev_priv(netdev); 3630 struct e1000_hw *hw = &adapter->hw; 3631 3632 /* reclaim resources allocated to VFs */ 3633 if (adapter->vf_data) { 3634 /* disable iov and allow time for transactions to clear */ 3635 if (pci_vfs_assigned(pdev)) { 3636 dev_warn(&pdev->dev, 3637 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3638 return -EPERM; 3639 } else { 3640 pci_disable_sriov(pdev); 3641 msleep(500); 3642 } 3643 3644 kfree(adapter->vf_mac_list); 3645 adapter->vf_mac_list = NULL; 3646 kfree(adapter->vf_data); 3647 adapter->vf_data = NULL; 3648 adapter->vfs_allocated_count = 0; 3649 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3650 wrfl(); 3651 msleep(100); 3652 dev_info(&pdev->dev, "IOV Disabled\n"); 3653 3654 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3655 adapter->flags |= IGB_FLAG_DMAC; 3656 } 3657 3658 return 0; 3659 } 3660 3661 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 3662 { 3663 struct net_device *netdev = pci_get_drvdata(pdev); 3664 struct igb_adapter *adapter = netdev_priv(netdev); 3665 int old_vfs = pci_num_vf(pdev); 3666 struct vf_mac_filter *mac_list; 3667 int err = 0; 3668 int num_vf_mac_filters, i; 3669 3670 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3671 err = -EPERM; 3672 goto out; 3673 } 3674 if (!num_vfs) 3675 goto out; 3676 3677 if (old_vfs) { 3678 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3679 old_vfs, max_vfs); 3680 adapter->vfs_allocated_count = old_vfs; 3681 } else 3682 adapter->vfs_allocated_count = num_vfs; 3683 3684 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 3685 sizeof(struct vf_data_storage), GFP_KERNEL); 3686 3687 /* if allocation failed then we do not support SR-IOV */ 3688 if (!adapter->vf_data) { 3689 adapter->vfs_allocated_count = 0; 3690 err = -ENOMEM; 3691 goto out; 3692 } 3693 3694 /* Due to the limited number of RAR entries calculate potential 3695 * number of MAC filters available for the VFs. Reserve entries 3696 * for PF default MAC, PF MAC filters and at least one RAR entry 3697 * for each VF for VF MAC. 3698 */ 3699 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3700 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3701 adapter->vfs_allocated_count); 3702 3703 adapter->vf_mac_list = kcalloc(num_vf_mac_filters, 3704 sizeof(struct vf_mac_filter), 3705 GFP_KERNEL); 3706 3707 mac_list = adapter->vf_mac_list; 3708 INIT_LIST_HEAD(&adapter->vf_macs.l); 3709 3710 if (adapter->vf_mac_list) { 3711 /* Initialize list of VF MAC filters */ 3712 for (i = 0; i < num_vf_mac_filters; i++) { 3713 mac_list->vf = -1; 3714 mac_list->free = true; 3715 list_add(&mac_list->l, &adapter->vf_macs.l); 3716 mac_list++; 3717 } 3718 } else { 3719 /* If we could not allocate memory for the VF MAC filters 3720 * we can continue without this feature but warn user. 3721 */ 3722 dev_err(&pdev->dev, 3723 "Unable to allocate memory for VF MAC filter list\n"); 3724 } 3725 3726 /* only call pci_enable_sriov() if no VFs are allocated already */ 3727 if (!old_vfs) { 3728 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3729 if (err) 3730 goto err_out; 3731 } 3732 dev_info(&pdev->dev, "%d VFs allocated\n", 3733 adapter->vfs_allocated_count); 3734 for (i = 0; i < adapter->vfs_allocated_count; i++) 3735 igb_vf_configure(adapter, i); 3736 3737 /* DMA Coalescing is not supported in IOV mode. */ 3738 adapter->flags &= ~IGB_FLAG_DMAC; 3739 goto out; 3740 3741 err_out: 3742 kfree(adapter->vf_mac_list); 3743 adapter->vf_mac_list = NULL; 3744 kfree(adapter->vf_data); 3745 adapter->vf_data = NULL; 3746 adapter->vfs_allocated_count = 0; 3747 out: 3748 return err; 3749 } 3750 3751 #endif 3752 /** 3753 * igb_remove_i2c - Cleanup I2C interface 3754 * @adapter: pointer to adapter structure 3755 **/ 3756 static void igb_remove_i2c(struct igb_adapter *adapter) 3757 { 3758 /* free the adapter bus structure */ 3759 i2c_del_adapter(&adapter->i2c_adap); 3760 } 3761 3762 /** 3763 * igb_remove - Device Removal Routine 3764 * @pdev: PCI device information struct 3765 * 3766 * igb_remove is called by the PCI subsystem to alert the driver 3767 * that it should release a PCI device. The could be caused by a 3768 * Hot-Plug event, or because the driver is going to be removed from 3769 * memory. 3770 **/ 3771 static void igb_remove(struct pci_dev *pdev) 3772 { 3773 struct net_device *netdev = pci_get_drvdata(pdev); 3774 struct igb_adapter *adapter = netdev_priv(netdev); 3775 struct e1000_hw *hw = &adapter->hw; 3776 3777 pm_runtime_get_noresume(&pdev->dev); 3778 #ifdef CONFIG_IGB_HWMON 3779 igb_sysfs_exit(adapter); 3780 #endif 3781 igb_remove_i2c(adapter); 3782 igb_ptp_stop(adapter); 3783 /* The watchdog timer may be rescheduled, so explicitly 3784 * disable watchdog from being rescheduled. 3785 */ 3786 set_bit(__IGB_DOWN, &adapter->state); 3787 del_timer_sync(&adapter->watchdog_timer); 3788 del_timer_sync(&adapter->phy_info_timer); 3789 3790 cancel_work_sync(&adapter->reset_task); 3791 cancel_work_sync(&adapter->watchdog_task); 3792 3793 #ifdef CONFIG_IGB_DCA 3794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3795 dev_info(&pdev->dev, "DCA disabled\n"); 3796 dca_remove_requester(&pdev->dev); 3797 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3798 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3799 } 3800 #endif 3801 3802 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3803 * would have already happened in close and is redundant. 3804 */ 3805 igb_release_hw_control(adapter); 3806 3807 #ifdef CONFIG_PCI_IOV 3808 igb_disable_sriov(pdev); 3809 #endif 3810 3811 unregister_netdev(netdev); 3812 3813 igb_clear_interrupt_scheme(adapter); 3814 3815 pci_iounmap(pdev, adapter->io_addr); 3816 if (hw->flash_address) 3817 iounmap(hw->flash_address); 3818 pci_release_mem_regions(pdev); 3819 3820 kfree(adapter->mac_table); 3821 kfree(adapter->shadow_vfta); 3822 free_netdev(netdev); 3823 3824 pci_disable_pcie_error_reporting(pdev); 3825 3826 pci_disable_device(pdev); 3827 } 3828 3829 /** 3830 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3831 * @adapter: board private structure to initialize 3832 * 3833 * This function initializes the vf specific data storage and then attempts to 3834 * allocate the VFs. The reason for ordering it this way is because it is much 3835 * mor expensive time wise to disable SR-IOV than it is to allocate and free 3836 * the memory for the VFs. 3837 **/ 3838 static void igb_probe_vfs(struct igb_adapter *adapter) 3839 { 3840 #ifdef CONFIG_PCI_IOV 3841 struct pci_dev *pdev = adapter->pdev; 3842 struct e1000_hw *hw = &adapter->hw; 3843 3844 /* Virtualization features not supported on i210 family. */ 3845 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 3846 return; 3847 3848 /* Of the below we really only want the effect of getting 3849 * IGB_FLAG_HAS_MSIX set (if available), without which 3850 * igb_enable_sriov() has no effect. 3851 */ 3852 igb_set_interrupt_capability(adapter, true); 3853 igb_reset_interrupt_capability(adapter); 3854 3855 pci_sriov_set_totalvfs(pdev, 7); 3856 igb_enable_sriov(pdev, max_vfs); 3857 3858 #endif /* CONFIG_PCI_IOV */ 3859 } 3860 3861 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3862 { 3863 struct e1000_hw *hw = &adapter->hw; 3864 unsigned int max_rss_queues; 3865 3866 /* Determine the maximum number of RSS queues supported. */ 3867 switch (hw->mac.type) { 3868 case e1000_i211: 3869 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3870 break; 3871 case e1000_82575: 3872 case e1000_i210: 3873 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3874 break; 3875 case e1000_i350: 3876 /* I350 cannot do RSS and SR-IOV at the same time */ 3877 if (!!adapter->vfs_allocated_count) { 3878 max_rss_queues = 1; 3879 break; 3880 } 3881 fallthrough; 3882 case e1000_82576: 3883 if (!!adapter->vfs_allocated_count) { 3884 max_rss_queues = 2; 3885 break; 3886 } 3887 fallthrough; 3888 case e1000_82580: 3889 case e1000_i354: 3890 default: 3891 max_rss_queues = IGB_MAX_RX_QUEUES; 3892 break; 3893 } 3894 3895 return max_rss_queues; 3896 } 3897 3898 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3899 { 3900 u32 max_rss_queues; 3901 3902 max_rss_queues = igb_get_max_rss_queues(adapter); 3903 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3904 3905 igb_set_flag_queue_pairs(adapter, max_rss_queues); 3906 } 3907 3908 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 3909 const u32 max_rss_queues) 3910 { 3911 struct e1000_hw *hw = &adapter->hw; 3912 3913 /* Determine if we need to pair queues. */ 3914 switch (hw->mac.type) { 3915 case e1000_82575: 3916 case e1000_i211: 3917 /* Device supports enough interrupts without queue pairing. */ 3918 break; 3919 case e1000_82576: 3920 case e1000_82580: 3921 case e1000_i350: 3922 case e1000_i354: 3923 case e1000_i210: 3924 default: 3925 /* If rss_queues > half of max_rss_queues, pair the queues in 3926 * order to conserve interrupts due to limited supply. 3927 */ 3928 if (adapter->rss_queues > (max_rss_queues / 2)) 3929 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 3930 else 3931 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 3932 break; 3933 } 3934 } 3935 3936 /** 3937 * igb_sw_init - Initialize general software structures (struct igb_adapter) 3938 * @adapter: board private structure to initialize 3939 * 3940 * igb_sw_init initializes the Adapter private data structure. 3941 * Fields are initialized based on PCI device information and 3942 * OS network device settings (MTU size). 3943 **/ 3944 static int igb_sw_init(struct igb_adapter *adapter) 3945 { 3946 struct e1000_hw *hw = &adapter->hw; 3947 struct net_device *netdev = adapter->netdev; 3948 struct pci_dev *pdev = adapter->pdev; 3949 3950 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3951 3952 /* set default ring sizes */ 3953 adapter->tx_ring_count = IGB_DEFAULT_TXD; 3954 adapter->rx_ring_count = IGB_DEFAULT_RXD; 3955 3956 /* set default ITR values */ 3957 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 3958 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 3959 3960 /* set default work limits */ 3961 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 3962 3963 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 3964 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3965 3966 spin_lock_init(&adapter->nfc_lock); 3967 spin_lock_init(&adapter->stats64_lock); 3968 #ifdef CONFIG_PCI_IOV 3969 switch (hw->mac.type) { 3970 case e1000_82576: 3971 case e1000_i350: 3972 if (max_vfs > 7) { 3973 dev_warn(&pdev->dev, 3974 "Maximum of 7 VFs per PF, using max\n"); 3975 max_vfs = adapter->vfs_allocated_count = 7; 3976 } else 3977 adapter->vfs_allocated_count = max_vfs; 3978 if (adapter->vfs_allocated_count) 3979 dev_warn(&pdev->dev, 3980 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 3981 break; 3982 default: 3983 break; 3984 } 3985 #endif /* CONFIG_PCI_IOV */ 3986 3987 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3988 adapter->flags |= IGB_FLAG_HAS_MSIX; 3989 3990 adapter->mac_table = kcalloc(hw->mac.rar_entry_count, 3991 sizeof(struct igb_mac_addr), 3992 GFP_KERNEL); 3993 if (!adapter->mac_table) 3994 return -ENOMEM; 3995 3996 igb_probe_vfs(adapter); 3997 3998 igb_init_queue_configuration(adapter); 3999 4000 /* Setup and initialize a copy of the hw vlan table array */ 4001 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4002 GFP_KERNEL); 4003 if (!adapter->shadow_vfta) 4004 return -ENOMEM; 4005 4006 /* This call may decrease the number of queues */ 4007 if (igb_init_interrupt_scheme(adapter, true)) { 4008 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4009 return -ENOMEM; 4010 } 4011 4012 /* Explicitly disable IRQ since the NIC can be in any state. */ 4013 igb_irq_disable(adapter); 4014 4015 if (hw->mac.type >= e1000_i350) 4016 adapter->flags &= ~IGB_FLAG_DMAC; 4017 4018 set_bit(__IGB_DOWN, &adapter->state); 4019 return 0; 4020 } 4021 4022 /** 4023 * igb_open - Called when a network interface is made active 4024 * @netdev: network interface device structure 4025 * @resuming: indicates whether we are in a resume call 4026 * 4027 * Returns 0 on success, negative value on failure 4028 * 4029 * The open entry point is called when a network interface is made 4030 * active by the system (IFF_UP). At this point all resources needed 4031 * for transmit and receive operations are allocated, the interrupt 4032 * handler is registered with the OS, the watchdog timer is started, 4033 * and the stack is notified that the interface is ready. 4034 **/ 4035 static int __igb_open(struct net_device *netdev, bool resuming) 4036 { 4037 struct igb_adapter *adapter = netdev_priv(netdev); 4038 struct e1000_hw *hw = &adapter->hw; 4039 struct pci_dev *pdev = adapter->pdev; 4040 int err; 4041 int i; 4042 4043 /* disallow open during test */ 4044 if (test_bit(__IGB_TESTING, &adapter->state)) { 4045 WARN_ON(resuming); 4046 return -EBUSY; 4047 } 4048 4049 if (!resuming) 4050 pm_runtime_get_sync(&pdev->dev); 4051 4052 netif_carrier_off(netdev); 4053 4054 /* allocate transmit descriptors */ 4055 err = igb_setup_all_tx_resources(adapter); 4056 if (err) 4057 goto err_setup_tx; 4058 4059 /* allocate receive descriptors */ 4060 err = igb_setup_all_rx_resources(adapter); 4061 if (err) 4062 goto err_setup_rx; 4063 4064 igb_power_up_link(adapter); 4065 4066 /* before we allocate an interrupt, we must be ready to handle it. 4067 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4068 * as soon as we call pci_request_irq, so we have to setup our 4069 * clean_rx handler before we do so. 4070 */ 4071 igb_configure(adapter); 4072 4073 err = igb_request_irq(adapter); 4074 if (err) 4075 goto err_req_irq; 4076 4077 /* Notify the stack of the actual queue counts. */ 4078 err = netif_set_real_num_tx_queues(adapter->netdev, 4079 adapter->num_tx_queues); 4080 if (err) 4081 goto err_set_queues; 4082 4083 err = netif_set_real_num_rx_queues(adapter->netdev, 4084 adapter->num_rx_queues); 4085 if (err) 4086 goto err_set_queues; 4087 4088 /* From here on the code is the same as igb_up() */ 4089 clear_bit(__IGB_DOWN, &adapter->state); 4090 4091 for (i = 0; i < adapter->num_q_vectors; i++) 4092 napi_enable(&(adapter->q_vector[i]->napi)); 4093 4094 /* Clear any pending interrupts. */ 4095 rd32(E1000_TSICR); 4096 rd32(E1000_ICR); 4097 4098 igb_irq_enable(adapter); 4099 4100 /* notify VFs that reset has been completed */ 4101 if (adapter->vfs_allocated_count) { 4102 u32 reg_data = rd32(E1000_CTRL_EXT); 4103 4104 reg_data |= E1000_CTRL_EXT_PFRSTD; 4105 wr32(E1000_CTRL_EXT, reg_data); 4106 } 4107 4108 netif_tx_start_all_queues(netdev); 4109 4110 if (!resuming) 4111 pm_runtime_put(&pdev->dev); 4112 4113 /* start the watchdog. */ 4114 hw->mac.get_link_status = 1; 4115 schedule_work(&adapter->watchdog_task); 4116 4117 return 0; 4118 4119 err_set_queues: 4120 igb_free_irq(adapter); 4121 err_req_irq: 4122 igb_release_hw_control(adapter); 4123 igb_power_down_link(adapter); 4124 igb_free_all_rx_resources(adapter); 4125 err_setup_rx: 4126 igb_free_all_tx_resources(adapter); 4127 err_setup_tx: 4128 igb_reset(adapter); 4129 if (!resuming) 4130 pm_runtime_put(&pdev->dev); 4131 4132 return err; 4133 } 4134 4135 int igb_open(struct net_device *netdev) 4136 { 4137 return __igb_open(netdev, false); 4138 } 4139 4140 /** 4141 * igb_close - Disables a network interface 4142 * @netdev: network interface device structure 4143 * @suspending: indicates we are in a suspend call 4144 * 4145 * Returns 0, this is not allowed to fail 4146 * 4147 * The close entry point is called when an interface is de-activated 4148 * by the OS. The hardware is still under the driver's control, but 4149 * needs to be disabled. A global MAC reset is issued to stop the 4150 * hardware, and all transmit and receive resources are freed. 4151 **/ 4152 static int __igb_close(struct net_device *netdev, bool suspending) 4153 { 4154 struct igb_adapter *adapter = netdev_priv(netdev); 4155 struct pci_dev *pdev = adapter->pdev; 4156 4157 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4158 4159 if (!suspending) 4160 pm_runtime_get_sync(&pdev->dev); 4161 4162 igb_down(adapter); 4163 igb_free_irq(adapter); 4164 4165 igb_free_all_tx_resources(adapter); 4166 igb_free_all_rx_resources(adapter); 4167 4168 if (!suspending) 4169 pm_runtime_put_sync(&pdev->dev); 4170 return 0; 4171 } 4172 4173 int igb_close(struct net_device *netdev) 4174 { 4175 if (netif_device_present(netdev) || netdev->dismantle) 4176 return __igb_close(netdev, false); 4177 return 0; 4178 } 4179 4180 /** 4181 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4182 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4183 * 4184 * Return 0 on success, negative on failure 4185 **/ 4186 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4187 { 4188 struct device *dev = tx_ring->dev; 4189 int size; 4190 4191 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4192 4193 tx_ring->tx_buffer_info = vmalloc(size); 4194 if (!tx_ring->tx_buffer_info) 4195 goto err; 4196 4197 /* round up to nearest 4K */ 4198 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4199 tx_ring->size = ALIGN(tx_ring->size, 4096); 4200 4201 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4202 &tx_ring->dma, GFP_KERNEL); 4203 if (!tx_ring->desc) 4204 goto err; 4205 4206 tx_ring->next_to_use = 0; 4207 tx_ring->next_to_clean = 0; 4208 4209 return 0; 4210 4211 err: 4212 vfree(tx_ring->tx_buffer_info); 4213 tx_ring->tx_buffer_info = NULL; 4214 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4215 return -ENOMEM; 4216 } 4217 4218 /** 4219 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4220 * (Descriptors) for all queues 4221 * @adapter: board private structure 4222 * 4223 * Return 0 on success, negative on failure 4224 **/ 4225 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4226 { 4227 struct pci_dev *pdev = adapter->pdev; 4228 int i, err = 0; 4229 4230 for (i = 0; i < adapter->num_tx_queues; i++) { 4231 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4232 if (err) { 4233 dev_err(&pdev->dev, 4234 "Allocation for Tx Queue %u failed\n", i); 4235 for (i--; i >= 0; i--) 4236 igb_free_tx_resources(adapter->tx_ring[i]); 4237 break; 4238 } 4239 } 4240 4241 return err; 4242 } 4243 4244 /** 4245 * igb_setup_tctl - configure the transmit control registers 4246 * @adapter: Board private structure 4247 **/ 4248 void igb_setup_tctl(struct igb_adapter *adapter) 4249 { 4250 struct e1000_hw *hw = &adapter->hw; 4251 u32 tctl; 4252 4253 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4254 wr32(E1000_TXDCTL(0), 0); 4255 4256 /* Program the Transmit Control Register */ 4257 tctl = rd32(E1000_TCTL); 4258 tctl &= ~E1000_TCTL_CT; 4259 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4260 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4261 4262 igb_config_collision_dist(hw); 4263 4264 /* Enable transmits */ 4265 tctl |= E1000_TCTL_EN; 4266 4267 wr32(E1000_TCTL, tctl); 4268 } 4269 4270 /** 4271 * igb_configure_tx_ring - Configure transmit ring after Reset 4272 * @adapter: board private structure 4273 * @ring: tx ring to configure 4274 * 4275 * Configure a transmit ring after a reset. 4276 **/ 4277 void igb_configure_tx_ring(struct igb_adapter *adapter, 4278 struct igb_ring *ring) 4279 { 4280 struct e1000_hw *hw = &adapter->hw; 4281 u32 txdctl = 0; 4282 u64 tdba = ring->dma; 4283 int reg_idx = ring->reg_idx; 4284 4285 wr32(E1000_TDLEN(reg_idx), 4286 ring->count * sizeof(union e1000_adv_tx_desc)); 4287 wr32(E1000_TDBAL(reg_idx), 4288 tdba & 0x00000000ffffffffULL); 4289 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4290 4291 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4292 wr32(E1000_TDH(reg_idx), 0); 4293 writel(0, ring->tail); 4294 4295 txdctl |= IGB_TX_PTHRESH; 4296 txdctl |= IGB_TX_HTHRESH << 8; 4297 txdctl |= IGB_TX_WTHRESH << 16; 4298 4299 /* reinitialize tx_buffer_info */ 4300 memset(ring->tx_buffer_info, 0, 4301 sizeof(struct igb_tx_buffer) * ring->count); 4302 4303 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4304 wr32(E1000_TXDCTL(reg_idx), txdctl); 4305 } 4306 4307 /** 4308 * igb_configure_tx - Configure transmit Unit after Reset 4309 * @adapter: board private structure 4310 * 4311 * Configure the Tx unit of the MAC after a reset. 4312 **/ 4313 static void igb_configure_tx(struct igb_adapter *adapter) 4314 { 4315 struct e1000_hw *hw = &adapter->hw; 4316 int i; 4317 4318 /* disable the queues */ 4319 for (i = 0; i < adapter->num_tx_queues; i++) 4320 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4321 4322 wrfl(); 4323 usleep_range(10000, 20000); 4324 4325 for (i = 0; i < adapter->num_tx_queues; i++) 4326 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4327 } 4328 4329 /** 4330 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4331 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4332 * 4333 * Returns 0 on success, negative on failure 4334 **/ 4335 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4336 { 4337 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4338 struct device *dev = rx_ring->dev; 4339 int size; 4340 4341 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4342 4343 rx_ring->rx_buffer_info = vmalloc(size); 4344 if (!rx_ring->rx_buffer_info) 4345 goto err; 4346 4347 /* Round up to nearest 4K */ 4348 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4349 rx_ring->size = ALIGN(rx_ring->size, 4096); 4350 4351 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4352 &rx_ring->dma, GFP_KERNEL); 4353 if (!rx_ring->desc) 4354 goto err; 4355 4356 rx_ring->next_to_alloc = 0; 4357 rx_ring->next_to_clean = 0; 4358 rx_ring->next_to_use = 0; 4359 4360 rx_ring->xdp_prog = adapter->xdp_prog; 4361 4362 /* XDP RX-queue info */ 4363 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4364 rx_ring->queue_index, 0) < 0) 4365 goto err; 4366 4367 return 0; 4368 4369 err: 4370 vfree(rx_ring->rx_buffer_info); 4371 rx_ring->rx_buffer_info = NULL; 4372 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4373 return -ENOMEM; 4374 } 4375 4376 /** 4377 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4378 * (Descriptors) for all queues 4379 * @adapter: board private structure 4380 * 4381 * Return 0 on success, negative on failure 4382 **/ 4383 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4384 { 4385 struct pci_dev *pdev = adapter->pdev; 4386 int i, err = 0; 4387 4388 for (i = 0; i < adapter->num_rx_queues; i++) { 4389 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4390 if (err) { 4391 dev_err(&pdev->dev, 4392 "Allocation for Rx Queue %u failed\n", i); 4393 for (i--; i >= 0; i--) 4394 igb_free_rx_resources(adapter->rx_ring[i]); 4395 break; 4396 } 4397 } 4398 4399 return err; 4400 } 4401 4402 /** 4403 * igb_setup_mrqc - configure the multiple receive queue control registers 4404 * @adapter: Board private structure 4405 **/ 4406 static void igb_setup_mrqc(struct igb_adapter *adapter) 4407 { 4408 struct e1000_hw *hw = &adapter->hw; 4409 u32 mrqc, rxcsum; 4410 u32 j, num_rx_queues; 4411 u32 rss_key[10]; 4412 4413 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4414 for (j = 0; j < 10; j++) 4415 wr32(E1000_RSSRK(j), rss_key[j]); 4416 4417 num_rx_queues = adapter->rss_queues; 4418 4419 switch (hw->mac.type) { 4420 case e1000_82576: 4421 /* 82576 supports 2 RSS queues for SR-IOV */ 4422 if (adapter->vfs_allocated_count) 4423 num_rx_queues = 2; 4424 break; 4425 default: 4426 break; 4427 } 4428 4429 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4430 for (j = 0; j < IGB_RETA_SIZE; j++) 4431 adapter->rss_indir_tbl[j] = 4432 (j * num_rx_queues) / IGB_RETA_SIZE; 4433 adapter->rss_indir_tbl_init = num_rx_queues; 4434 } 4435 igb_write_rss_indir_tbl(adapter); 4436 4437 /* Disable raw packet checksumming so that RSS hash is placed in 4438 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4439 * offloads as they are enabled by default 4440 */ 4441 rxcsum = rd32(E1000_RXCSUM); 4442 rxcsum |= E1000_RXCSUM_PCSD; 4443 4444 if (adapter->hw.mac.type >= e1000_82576) 4445 /* Enable Receive Checksum Offload for SCTP */ 4446 rxcsum |= E1000_RXCSUM_CRCOFL; 4447 4448 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4449 wr32(E1000_RXCSUM, rxcsum); 4450 4451 /* Generate RSS hash based on packet types, TCP/UDP 4452 * port numbers and/or IPv4/v6 src and dst addresses 4453 */ 4454 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4455 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4456 E1000_MRQC_RSS_FIELD_IPV6 | 4457 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4458 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4459 4460 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4461 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4462 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4463 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4464 4465 /* If VMDq is enabled then we set the appropriate mode for that, else 4466 * we default to RSS so that an RSS hash is calculated per packet even 4467 * if we are only using one queue 4468 */ 4469 if (adapter->vfs_allocated_count) { 4470 if (hw->mac.type > e1000_82575) { 4471 /* Set the default pool for the PF's first queue */ 4472 u32 vtctl = rd32(E1000_VT_CTL); 4473 4474 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4475 E1000_VT_CTL_DISABLE_DEF_POOL); 4476 vtctl |= adapter->vfs_allocated_count << 4477 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4478 wr32(E1000_VT_CTL, vtctl); 4479 } 4480 if (adapter->rss_queues > 1) 4481 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4482 else 4483 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4484 } else { 4485 if (hw->mac.type != e1000_i211) 4486 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4487 } 4488 igb_vmm_control(adapter); 4489 4490 wr32(E1000_MRQC, mrqc); 4491 } 4492 4493 /** 4494 * igb_setup_rctl - configure the receive control registers 4495 * @adapter: Board private structure 4496 **/ 4497 void igb_setup_rctl(struct igb_adapter *adapter) 4498 { 4499 struct e1000_hw *hw = &adapter->hw; 4500 u32 rctl; 4501 4502 rctl = rd32(E1000_RCTL); 4503 4504 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4505 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4506 4507 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4508 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4509 4510 /* enable stripping of CRC. It's unlikely this will break BMC 4511 * redirection as it did with e1000. Newer features require 4512 * that the HW strips the CRC. 4513 */ 4514 rctl |= E1000_RCTL_SECRC; 4515 4516 /* disable store bad packets and clear size bits. */ 4517 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4518 4519 /* enable LPE to allow for reception of jumbo frames */ 4520 rctl |= E1000_RCTL_LPE; 4521 4522 /* disable queue 0 to prevent tail write w/o re-config */ 4523 wr32(E1000_RXDCTL(0), 0); 4524 4525 /* Attention!!! For SR-IOV PF driver operations you must enable 4526 * queue drop for all VF and PF queues to prevent head of line blocking 4527 * if an un-trusted VF does not provide descriptors to hardware. 4528 */ 4529 if (adapter->vfs_allocated_count) { 4530 /* set all queue drop enable bits */ 4531 wr32(E1000_QDE, ALL_QUEUES); 4532 } 4533 4534 /* This is useful for sniffing bad packets. */ 4535 if (adapter->netdev->features & NETIF_F_RXALL) { 4536 /* UPE and MPE will be handled by normal PROMISC logic 4537 * in e1000e_set_rx_mode 4538 */ 4539 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4540 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4541 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4542 4543 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4544 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4545 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4546 * and that breaks VLANs. 4547 */ 4548 } 4549 4550 wr32(E1000_RCTL, rctl); 4551 } 4552 4553 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4554 int vfn) 4555 { 4556 struct e1000_hw *hw = &adapter->hw; 4557 u32 vmolr; 4558 4559 if (size > MAX_JUMBO_FRAME_SIZE) 4560 size = MAX_JUMBO_FRAME_SIZE; 4561 4562 vmolr = rd32(E1000_VMOLR(vfn)); 4563 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4564 vmolr |= size | E1000_VMOLR_LPE; 4565 wr32(E1000_VMOLR(vfn), vmolr); 4566 4567 return 0; 4568 } 4569 4570 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4571 int vfn, bool enable) 4572 { 4573 struct e1000_hw *hw = &adapter->hw; 4574 u32 val, reg; 4575 4576 if (hw->mac.type < e1000_82576) 4577 return; 4578 4579 if (hw->mac.type == e1000_i350) 4580 reg = E1000_DVMOLR(vfn); 4581 else 4582 reg = E1000_VMOLR(vfn); 4583 4584 val = rd32(reg); 4585 if (enable) 4586 val |= E1000_VMOLR_STRVLAN; 4587 else 4588 val &= ~(E1000_VMOLR_STRVLAN); 4589 wr32(reg, val); 4590 } 4591 4592 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4593 int vfn, bool aupe) 4594 { 4595 struct e1000_hw *hw = &adapter->hw; 4596 u32 vmolr; 4597 4598 /* This register exists only on 82576 and newer so if we are older then 4599 * we should exit and do nothing 4600 */ 4601 if (hw->mac.type < e1000_82576) 4602 return; 4603 4604 vmolr = rd32(E1000_VMOLR(vfn)); 4605 if (aupe) 4606 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4607 else 4608 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4609 4610 /* clear all bits that might not be set */ 4611 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4612 4613 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4614 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4615 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4616 * multicast packets 4617 */ 4618 if (vfn <= adapter->vfs_allocated_count) 4619 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4620 4621 wr32(E1000_VMOLR(vfn), vmolr); 4622 } 4623 4624 /** 4625 * igb_setup_srrctl - configure the split and replication receive control 4626 * registers 4627 * @adapter: Board private structure 4628 * @ring: receive ring to be configured 4629 **/ 4630 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4631 { 4632 struct e1000_hw *hw = &adapter->hw; 4633 int reg_idx = ring->reg_idx; 4634 u32 srrctl = 0; 4635 4636 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4637 if (ring_uses_large_buffer(ring)) 4638 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4639 else 4640 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4641 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4642 if (hw->mac.type >= e1000_82580) 4643 srrctl |= E1000_SRRCTL_TIMESTAMP; 4644 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4645 * queues and rx flow control is disabled 4646 */ 4647 if (adapter->vfs_allocated_count || 4648 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4649 adapter->num_rx_queues > 1)) 4650 srrctl |= E1000_SRRCTL_DROP_EN; 4651 4652 wr32(E1000_SRRCTL(reg_idx), srrctl); 4653 } 4654 4655 /** 4656 * igb_configure_rx_ring - Configure a receive ring after Reset 4657 * @adapter: board private structure 4658 * @ring: receive ring to be configured 4659 * 4660 * Configure the Rx unit of the MAC after a reset. 4661 **/ 4662 void igb_configure_rx_ring(struct igb_adapter *adapter, 4663 struct igb_ring *ring) 4664 { 4665 struct e1000_hw *hw = &adapter->hw; 4666 union e1000_adv_rx_desc *rx_desc; 4667 u64 rdba = ring->dma; 4668 int reg_idx = ring->reg_idx; 4669 u32 rxdctl = 0; 4670 4671 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4672 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4673 MEM_TYPE_PAGE_SHARED, NULL)); 4674 4675 /* disable the queue */ 4676 wr32(E1000_RXDCTL(reg_idx), 0); 4677 4678 /* Set DMA base address registers */ 4679 wr32(E1000_RDBAL(reg_idx), 4680 rdba & 0x00000000ffffffffULL); 4681 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4682 wr32(E1000_RDLEN(reg_idx), 4683 ring->count * sizeof(union e1000_adv_rx_desc)); 4684 4685 /* initialize head and tail */ 4686 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4687 wr32(E1000_RDH(reg_idx), 0); 4688 writel(0, ring->tail); 4689 4690 /* set descriptor configuration */ 4691 igb_setup_srrctl(adapter, ring); 4692 4693 /* set filtering for VMDQ pools */ 4694 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4695 4696 rxdctl |= IGB_RX_PTHRESH; 4697 rxdctl |= IGB_RX_HTHRESH << 8; 4698 rxdctl |= IGB_RX_WTHRESH << 16; 4699 4700 /* initialize rx_buffer_info */ 4701 memset(ring->rx_buffer_info, 0, 4702 sizeof(struct igb_rx_buffer) * ring->count); 4703 4704 /* initialize Rx descriptor 0 */ 4705 rx_desc = IGB_RX_DESC(ring, 0); 4706 rx_desc->wb.upper.length = 0; 4707 4708 /* enable receive descriptor fetching */ 4709 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4710 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4711 } 4712 4713 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4714 struct igb_ring *rx_ring) 4715 { 4716 /* set build_skb and buffer size flags */ 4717 clear_ring_build_skb_enabled(rx_ring); 4718 clear_ring_uses_large_buffer(rx_ring); 4719 4720 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4721 return; 4722 4723 set_ring_build_skb_enabled(rx_ring); 4724 4725 #if (PAGE_SIZE < 8192) 4726 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 4727 return; 4728 4729 set_ring_uses_large_buffer(rx_ring); 4730 #endif 4731 } 4732 4733 /** 4734 * igb_configure_rx - Configure receive Unit after Reset 4735 * @adapter: board private structure 4736 * 4737 * Configure the Rx unit of the MAC after a reset. 4738 **/ 4739 static void igb_configure_rx(struct igb_adapter *adapter) 4740 { 4741 int i; 4742 4743 /* set the correct pool for the PF default MAC address in entry 0 */ 4744 igb_set_default_mac_filter(adapter); 4745 4746 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4747 * the Base and Length of the Rx Descriptor Ring 4748 */ 4749 for (i = 0; i < adapter->num_rx_queues; i++) { 4750 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4751 4752 igb_set_rx_buffer_len(adapter, rx_ring); 4753 igb_configure_rx_ring(adapter, rx_ring); 4754 } 4755 } 4756 4757 /** 4758 * igb_free_tx_resources - Free Tx Resources per Queue 4759 * @tx_ring: Tx descriptor ring for a specific queue 4760 * 4761 * Free all transmit software resources 4762 **/ 4763 void igb_free_tx_resources(struct igb_ring *tx_ring) 4764 { 4765 igb_clean_tx_ring(tx_ring); 4766 4767 vfree(tx_ring->tx_buffer_info); 4768 tx_ring->tx_buffer_info = NULL; 4769 4770 /* if not set, then don't free */ 4771 if (!tx_ring->desc) 4772 return; 4773 4774 dma_free_coherent(tx_ring->dev, tx_ring->size, 4775 tx_ring->desc, tx_ring->dma); 4776 4777 tx_ring->desc = NULL; 4778 } 4779 4780 /** 4781 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4782 * @adapter: board private structure 4783 * 4784 * Free all transmit software resources 4785 **/ 4786 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4787 { 4788 int i; 4789 4790 for (i = 0; i < adapter->num_tx_queues; i++) 4791 if (adapter->tx_ring[i]) 4792 igb_free_tx_resources(adapter->tx_ring[i]); 4793 } 4794 4795 /** 4796 * igb_clean_tx_ring - Free Tx Buffers 4797 * @tx_ring: ring to be cleaned 4798 **/ 4799 static void igb_clean_tx_ring(struct igb_ring *tx_ring) 4800 { 4801 u16 i = tx_ring->next_to_clean; 4802 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4803 4804 while (i != tx_ring->next_to_use) { 4805 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4806 4807 /* Free all the Tx ring sk_buffs */ 4808 dev_kfree_skb_any(tx_buffer->skb); 4809 4810 /* unmap skb header data */ 4811 dma_unmap_single(tx_ring->dev, 4812 dma_unmap_addr(tx_buffer, dma), 4813 dma_unmap_len(tx_buffer, len), 4814 DMA_TO_DEVICE); 4815 4816 /* check for eop_desc to determine the end of the packet */ 4817 eop_desc = tx_buffer->next_to_watch; 4818 tx_desc = IGB_TX_DESC(tx_ring, i); 4819 4820 /* unmap remaining buffers */ 4821 while (tx_desc != eop_desc) { 4822 tx_buffer++; 4823 tx_desc++; 4824 i++; 4825 if (unlikely(i == tx_ring->count)) { 4826 i = 0; 4827 tx_buffer = tx_ring->tx_buffer_info; 4828 tx_desc = IGB_TX_DESC(tx_ring, 0); 4829 } 4830 4831 /* unmap any remaining paged data */ 4832 if (dma_unmap_len(tx_buffer, len)) 4833 dma_unmap_page(tx_ring->dev, 4834 dma_unmap_addr(tx_buffer, dma), 4835 dma_unmap_len(tx_buffer, len), 4836 DMA_TO_DEVICE); 4837 } 4838 4839 /* move us one more past the eop_desc for start of next pkt */ 4840 tx_buffer++; 4841 i++; 4842 if (unlikely(i == tx_ring->count)) { 4843 i = 0; 4844 tx_buffer = tx_ring->tx_buffer_info; 4845 } 4846 } 4847 4848 /* reset BQL for queue */ 4849 netdev_tx_reset_queue(txring_txq(tx_ring)); 4850 4851 /* reset next_to_use and next_to_clean */ 4852 tx_ring->next_to_use = 0; 4853 tx_ring->next_to_clean = 0; 4854 } 4855 4856 /** 4857 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 4858 * @adapter: board private structure 4859 **/ 4860 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 4861 { 4862 int i; 4863 4864 for (i = 0; i < adapter->num_tx_queues; i++) 4865 if (adapter->tx_ring[i]) 4866 igb_clean_tx_ring(adapter->tx_ring[i]); 4867 } 4868 4869 /** 4870 * igb_free_rx_resources - Free Rx Resources 4871 * @rx_ring: ring to clean the resources from 4872 * 4873 * Free all receive software resources 4874 **/ 4875 void igb_free_rx_resources(struct igb_ring *rx_ring) 4876 { 4877 igb_clean_rx_ring(rx_ring); 4878 4879 rx_ring->xdp_prog = NULL; 4880 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4881 vfree(rx_ring->rx_buffer_info); 4882 rx_ring->rx_buffer_info = NULL; 4883 4884 /* if not set, then don't free */ 4885 if (!rx_ring->desc) 4886 return; 4887 4888 dma_free_coherent(rx_ring->dev, rx_ring->size, 4889 rx_ring->desc, rx_ring->dma); 4890 4891 rx_ring->desc = NULL; 4892 } 4893 4894 /** 4895 * igb_free_all_rx_resources - Free Rx Resources for All Queues 4896 * @adapter: board private structure 4897 * 4898 * Free all receive software resources 4899 **/ 4900 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 4901 { 4902 int i; 4903 4904 for (i = 0; i < adapter->num_rx_queues; i++) 4905 if (adapter->rx_ring[i]) 4906 igb_free_rx_resources(adapter->rx_ring[i]); 4907 } 4908 4909 /** 4910 * igb_clean_rx_ring - Free Rx Buffers per Queue 4911 * @rx_ring: ring to free buffers from 4912 **/ 4913 static void igb_clean_rx_ring(struct igb_ring *rx_ring) 4914 { 4915 u16 i = rx_ring->next_to_clean; 4916 4917 dev_kfree_skb(rx_ring->skb); 4918 rx_ring->skb = NULL; 4919 4920 /* Free all the Rx ring sk_buffs */ 4921 while (i != rx_ring->next_to_alloc) { 4922 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 4923 4924 /* Invalidate cache lines that may have been written to by 4925 * device so that we avoid corrupting memory. 4926 */ 4927 dma_sync_single_range_for_cpu(rx_ring->dev, 4928 buffer_info->dma, 4929 buffer_info->page_offset, 4930 igb_rx_bufsz(rx_ring), 4931 DMA_FROM_DEVICE); 4932 4933 /* free resources associated with mapping */ 4934 dma_unmap_page_attrs(rx_ring->dev, 4935 buffer_info->dma, 4936 igb_rx_pg_size(rx_ring), 4937 DMA_FROM_DEVICE, 4938 IGB_RX_DMA_ATTR); 4939 __page_frag_cache_drain(buffer_info->page, 4940 buffer_info->pagecnt_bias); 4941 4942 i++; 4943 if (i == rx_ring->count) 4944 i = 0; 4945 } 4946 4947 rx_ring->next_to_alloc = 0; 4948 rx_ring->next_to_clean = 0; 4949 rx_ring->next_to_use = 0; 4950 } 4951 4952 /** 4953 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 4954 * @adapter: board private structure 4955 **/ 4956 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 4957 { 4958 int i; 4959 4960 for (i = 0; i < adapter->num_rx_queues; i++) 4961 if (adapter->rx_ring[i]) 4962 igb_clean_rx_ring(adapter->rx_ring[i]); 4963 } 4964 4965 /** 4966 * igb_set_mac - Change the Ethernet Address of the NIC 4967 * @netdev: network interface device structure 4968 * @p: pointer to an address structure 4969 * 4970 * Returns 0 on success, negative on failure 4971 **/ 4972 static int igb_set_mac(struct net_device *netdev, void *p) 4973 { 4974 struct igb_adapter *adapter = netdev_priv(netdev); 4975 struct e1000_hw *hw = &adapter->hw; 4976 struct sockaddr *addr = p; 4977 4978 if (!is_valid_ether_addr(addr->sa_data)) 4979 return -EADDRNOTAVAIL; 4980 4981 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4982 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 4983 4984 /* set the correct pool for the new PF MAC address in entry 0 */ 4985 igb_set_default_mac_filter(adapter); 4986 4987 return 0; 4988 } 4989 4990 /** 4991 * igb_write_mc_addr_list - write multicast addresses to MTA 4992 * @netdev: network interface device structure 4993 * 4994 * Writes multicast address list to the MTA hash table. 4995 * Returns: -ENOMEM on failure 4996 * 0 on no addresses written 4997 * X on writing X addresses to MTA 4998 **/ 4999 static int igb_write_mc_addr_list(struct net_device *netdev) 5000 { 5001 struct igb_adapter *adapter = netdev_priv(netdev); 5002 struct e1000_hw *hw = &adapter->hw; 5003 struct netdev_hw_addr *ha; 5004 u8 *mta_list; 5005 int i; 5006 5007 if (netdev_mc_empty(netdev)) { 5008 /* nothing to program, so clear mc list */ 5009 igb_update_mc_addr_list(hw, NULL, 0); 5010 igb_restore_vf_multicasts(adapter); 5011 return 0; 5012 } 5013 5014 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5015 if (!mta_list) 5016 return -ENOMEM; 5017 5018 /* The shared function expects a packed array of only addresses. */ 5019 i = 0; 5020 netdev_for_each_mc_addr(ha, netdev) 5021 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5022 5023 igb_update_mc_addr_list(hw, mta_list, i); 5024 kfree(mta_list); 5025 5026 return netdev_mc_count(netdev); 5027 } 5028 5029 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5030 { 5031 struct e1000_hw *hw = &adapter->hw; 5032 u32 i, pf_id; 5033 5034 switch (hw->mac.type) { 5035 case e1000_i210: 5036 case e1000_i211: 5037 case e1000_i350: 5038 /* VLAN filtering needed for VLAN prio filter */ 5039 if (adapter->netdev->features & NETIF_F_NTUPLE) 5040 break; 5041 fallthrough; 5042 case e1000_82576: 5043 case e1000_82580: 5044 case e1000_i354: 5045 /* VLAN filtering needed for pool filtering */ 5046 if (adapter->vfs_allocated_count) 5047 break; 5048 fallthrough; 5049 default: 5050 return 1; 5051 } 5052 5053 /* We are already in VLAN promisc, nothing to do */ 5054 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5055 return 0; 5056 5057 if (!adapter->vfs_allocated_count) 5058 goto set_vfta; 5059 5060 /* Add PF to all active pools */ 5061 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5062 5063 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5064 u32 vlvf = rd32(E1000_VLVF(i)); 5065 5066 vlvf |= BIT(pf_id); 5067 wr32(E1000_VLVF(i), vlvf); 5068 } 5069 5070 set_vfta: 5071 /* Set all bits in the VLAN filter table array */ 5072 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5073 hw->mac.ops.write_vfta(hw, i, ~0U); 5074 5075 /* Set flag so we don't redo unnecessary work */ 5076 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5077 5078 return 0; 5079 } 5080 5081 #define VFTA_BLOCK_SIZE 8 5082 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5083 { 5084 struct e1000_hw *hw = &adapter->hw; 5085 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5086 u32 vid_start = vfta_offset * 32; 5087 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5088 u32 i, vid, word, bits, pf_id; 5089 5090 /* guarantee that we don't scrub out management VLAN */ 5091 vid = adapter->mng_vlan_id; 5092 if (vid >= vid_start && vid < vid_end) 5093 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5094 5095 if (!adapter->vfs_allocated_count) 5096 goto set_vfta; 5097 5098 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5099 5100 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5101 u32 vlvf = rd32(E1000_VLVF(i)); 5102 5103 /* pull VLAN ID from VLVF */ 5104 vid = vlvf & VLAN_VID_MASK; 5105 5106 /* only concern ourselves with a certain range */ 5107 if (vid < vid_start || vid >= vid_end) 5108 continue; 5109 5110 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5111 /* record VLAN ID in VFTA */ 5112 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5113 5114 /* if PF is part of this then continue */ 5115 if (test_bit(vid, adapter->active_vlans)) 5116 continue; 5117 } 5118 5119 /* remove PF from the pool */ 5120 bits = ~BIT(pf_id); 5121 bits &= rd32(E1000_VLVF(i)); 5122 wr32(E1000_VLVF(i), bits); 5123 } 5124 5125 set_vfta: 5126 /* extract values from active_vlans and write back to VFTA */ 5127 for (i = VFTA_BLOCK_SIZE; i--;) { 5128 vid = (vfta_offset + i) * 32; 5129 word = vid / BITS_PER_LONG; 5130 bits = vid % BITS_PER_LONG; 5131 5132 vfta[i] |= adapter->active_vlans[word] >> bits; 5133 5134 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5135 } 5136 } 5137 5138 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5139 { 5140 u32 i; 5141 5142 /* We are not in VLAN promisc, nothing to do */ 5143 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5144 return; 5145 5146 /* Set flag so we don't redo unnecessary work */ 5147 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5148 5149 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5150 igb_scrub_vfta(adapter, i); 5151 } 5152 5153 /** 5154 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5155 * @netdev: network interface device structure 5156 * 5157 * The set_rx_mode entry point is called whenever the unicast or multicast 5158 * address lists or the network interface flags are updated. This routine is 5159 * responsible for configuring the hardware for proper unicast, multicast, 5160 * promiscuous mode, and all-multi behavior. 5161 **/ 5162 static void igb_set_rx_mode(struct net_device *netdev) 5163 { 5164 struct igb_adapter *adapter = netdev_priv(netdev); 5165 struct e1000_hw *hw = &adapter->hw; 5166 unsigned int vfn = adapter->vfs_allocated_count; 5167 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5168 int count; 5169 5170 /* Check for Promiscuous and All Multicast modes */ 5171 if (netdev->flags & IFF_PROMISC) { 5172 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5173 vmolr |= E1000_VMOLR_MPME; 5174 5175 /* enable use of UTA filter to force packets to default pool */ 5176 if (hw->mac.type == e1000_82576) 5177 vmolr |= E1000_VMOLR_ROPE; 5178 } else { 5179 if (netdev->flags & IFF_ALLMULTI) { 5180 rctl |= E1000_RCTL_MPE; 5181 vmolr |= E1000_VMOLR_MPME; 5182 } else { 5183 /* Write addresses to the MTA, if the attempt fails 5184 * then we should just turn on promiscuous mode so 5185 * that we can at least receive multicast traffic 5186 */ 5187 count = igb_write_mc_addr_list(netdev); 5188 if (count < 0) { 5189 rctl |= E1000_RCTL_MPE; 5190 vmolr |= E1000_VMOLR_MPME; 5191 } else if (count) { 5192 vmolr |= E1000_VMOLR_ROMPE; 5193 } 5194 } 5195 } 5196 5197 /* Write addresses to available RAR registers, if there is not 5198 * sufficient space to store all the addresses then enable 5199 * unicast promiscuous mode 5200 */ 5201 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5202 rctl |= E1000_RCTL_UPE; 5203 vmolr |= E1000_VMOLR_ROPE; 5204 } 5205 5206 /* enable VLAN filtering by default */ 5207 rctl |= E1000_RCTL_VFE; 5208 5209 /* disable VLAN filtering for modes that require it */ 5210 if ((netdev->flags & IFF_PROMISC) || 5211 (netdev->features & NETIF_F_RXALL)) { 5212 /* if we fail to set all rules then just clear VFE */ 5213 if (igb_vlan_promisc_enable(adapter)) 5214 rctl &= ~E1000_RCTL_VFE; 5215 } else { 5216 igb_vlan_promisc_disable(adapter); 5217 } 5218 5219 /* update state of unicast, multicast, and VLAN filtering modes */ 5220 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5221 E1000_RCTL_VFE); 5222 wr32(E1000_RCTL, rctl); 5223 5224 #if (PAGE_SIZE < 8192) 5225 if (!adapter->vfs_allocated_count) { 5226 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5227 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5228 } 5229 #endif 5230 wr32(E1000_RLPML, rlpml); 5231 5232 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5233 * the VMOLR to enable the appropriate modes. Without this workaround 5234 * we will have issues with VLAN tag stripping not being done for frames 5235 * that are only arriving because we are the default pool 5236 */ 5237 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5238 return; 5239 5240 /* set UTA to appropriate mode */ 5241 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5242 5243 vmolr |= rd32(E1000_VMOLR(vfn)) & 5244 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5245 5246 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5247 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5248 #if (PAGE_SIZE < 8192) 5249 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5250 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5251 else 5252 #endif 5253 vmolr |= MAX_JUMBO_FRAME_SIZE; 5254 vmolr |= E1000_VMOLR_LPE; 5255 5256 wr32(E1000_VMOLR(vfn), vmolr); 5257 5258 igb_restore_vf_multicasts(adapter); 5259 } 5260 5261 static void igb_check_wvbr(struct igb_adapter *adapter) 5262 { 5263 struct e1000_hw *hw = &adapter->hw; 5264 u32 wvbr = 0; 5265 5266 switch (hw->mac.type) { 5267 case e1000_82576: 5268 case e1000_i350: 5269 wvbr = rd32(E1000_WVBR); 5270 if (!wvbr) 5271 return; 5272 break; 5273 default: 5274 break; 5275 } 5276 5277 adapter->wvbr |= wvbr; 5278 } 5279 5280 #define IGB_STAGGERED_QUEUE_OFFSET 8 5281 5282 static void igb_spoof_check(struct igb_adapter *adapter) 5283 { 5284 int j; 5285 5286 if (!adapter->wvbr) 5287 return; 5288 5289 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5290 if (adapter->wvbr & BIT(j) || 5291 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5292 dev_warn(&adapter->pdev->dev, 5293 "Spoof event(s) detected on VF %d\n", j); 5294 adapter->wvbr &= 5295 ~(BIT(j) | 5296 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5297 } 5298 } 5299 } 5300 5301 /* Need to wait a few seconds after link up to get diagnostic information from 5302 * the phy 5303 */ 5304 static void igb_update_phy_info(struct timer_list *t) 5305 { 5306 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5307 igb_get_phy_info(&adapter->hw); 5308 } 5309 5310 /** 5311 * igb_has_link - check shared code for link and determine up/down 5312 * @adapter: pointer to driver private info 5313 **/ 5314 bool igb_has_link(struct igb_adapter *adapter) 5315 { 5316 struct e1000_hw *hw = &adapter->hw; 5317 bool link_active = false; 5318 5319 /* get_link_status is set on LSC (link status) interrupt or 5320 * rx sequence error interrupt. get_link_status will stay 5321 * false until the e1000_check_for_link establishes link 5322 * for copper adapters ONLY 5323 */ 5324 switch (hw->phy.media_type) { 5325 case e1000_media_type_copper: 5326 if (!hw->mac.get_link_status) 5327 return true; 5328 fallthrough; 5329 case e1000_media_type_internal_serdes: 5330 hw->mac.ops.check_for_link(hw); 5331 link_active = !hw->mac.get_link_status; 5332 break; 5333 default: 5334 case e1000_media_type_unknown: 5335 break; 5336 } 5337 5338 if (((hw->mac.type == e1000_i210) || 5339 (hw->mac.type == e1000_i211)) && 5340 (hw->phy.id == I210_I_PHY_ID)) { 5341 if (!netif_carrier_ok(adapter->netdev)) { 5342 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5343 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5344 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5345 adapter->link_check_timeout = jiffies; 5346 } 5347 } 5348 5349 return link_active; 5350 } 5351 5352 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5353 { 5354 bool ret = false; 5355 u32 ctrl_ext, thstat; 5356 5357 /* check for thermal sensor event on i350 copper only */ 5358 if (hw->mac.type == e1000_i350) { 5359 thstat = rd32(E1000_THSTAT); 5360 ctrl_ext = rd32(E1000_CTRL_EXT); 5361 5362 if ((hw->phy.media_type == e1000_media_type_copper) && 5363 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5364 ret = !!(thstat & event); 5365 } 5366 5367 return ret; 5368 } 5369 5370 /** 5371 * igb_check_lvmmc - check for malformed packets received 5372 * and indicated in LVMMC register 5373 * @adapter: pointer to adapter 5374 **/ 5375 static void igb_check_lvmmc(struct igb_adapter *adapter) 5376 { 5377 struct e1000_hw *hw = &adapter->hw; 5378 u32 lvmmc; 5379 5380 lvmmc = rd32(E1000_LVMMC); 5381 if (lvmmc) { 5382 if (unlikely(net_ratelimit())) { 5383 netdev_warn(adapter->netdev, 5384 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5385 lvmmc); 5386 } 5387 } 5388 } 5389 5390 /** 5391 * igb_watchdog - Timer Call-back 5392 * @t: pointer to timer_list containing our private info pointer 5393 **/ 5394 static void igb_watchdog(struct timer_list *t) 5395 { 5396 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5397 /* Do the rest outside of interrupt context */ 5398 schedule_work(&adapter->watchdog_task); 5399 } 5400 5401 static void igb_watchdog_task(struct work_struct *work) 5402 { 5403 struct igb_adapter *adapter = container_of(work, 5404 struct igb_adapter, 5405 watchdog_task); 5406 struct e1000_hw *hw = &adapter->hw; 5407 struct e1000_phy_info *phy = &hw->phy; 5408 struct net_device *netdev = adapter->netdev; 5409 u32 link; 5410 int i; 5411 u32 connsw; 5412 u16 phy_data, retry_count = 20; 5413 5414 link = igb_has_link(adapter); 5415 5416 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5417 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5418 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5419 else 5420 link = false; 5421 } 5422 5423 /* Force link down if we have fiber to swap to */ 5424 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5425 if (hw->phy.media_type == e1000_media_type_copper) { 5426 connsw = rd32(E1000_CONNSW); 5427 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5428 link = 0; 5429 } 5430 } 5431 if (link) { 5432 /* Perform a reset if the media type changed. */ 5433 if (hw->dev_spec._82575.media_changed) { 5434 hw->dev_spec._82575.media_changed = false; 5435 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5436 igb_reset(adapter); 5437 } 5438 /* Cancel scheduled suspend requests. */ 5439 pm_runtime_resume(netdev->dev.parent); 5440 5441 if (!netif_carrier_ok(netdev)) { 5442 u32 ctrl; 5443 5444 hw->mac.ops.get_speed_and_duplex(hw, 5445 &adapter->link_speed, 5446 &adapter->link_duplex); 5447 5448 ctrl = rd32(E1000_CTRL); 5449 /* Links status message must follow this format */ 5450 netdev_info(netdev, 5451 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5452 netdev->name, 5453 adapter->link_speed, 5454 adapter->link_duplex == FULL_DUPLEX ? 5455 "Full" : "Half", 5456 (ctrl & E1000_CTRL_TFCE) && 5457 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5458 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5459 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5460 5461 /* disable EEE if enabled */ 5462 if ((adapter->flags & IGB_FLAG_EEE) && 5463 (adapter->link_duplex == HALF_DUPLEX)) { 5464 dev_info(&adapter->pdev->dev, 5465 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5466 adapter->hw.dev_spec._82575.eee_disable = true; 5467 adapter->flags &= ~IGB_FLAG_EEE; 5468 } 5469 5470 /* check if SmartSpeed worked */ 5471 igb_check_downshift(hw); 5472 if (phy->speed_downgraded) 5473 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5474 5475 /* check for thermal sensor event */ 5476 if (igb_thermal_sensor_event(hw, 5477 E1000_THSTAT_LINK_THROTTLE)) 5478 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5479 5480 /* adjust timeout factor according to speed/duplex */ 5481 adapter->tx_timeout_factor = 1; 5482 switch (adapter->link_speed) { 5483 case SPEED_10: 5484 adapter->tx_timeout_factor = 14; 5485 break; 5486 case SPEED_100: 5487 /* maybe add some timeout factor ? */ 5488 break; 5489 } 5490 5491 if (adapter->link_speed != SPEED_1000) 5492 goto no_wait; 5493 5494 /* wait for Remote receiver status OK */ 5495 retry_read_status: 5496 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5497 &phy_data)) { 5498 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5499 retry_count) { 5500 msleep(100); 5501 retry_count--; 5502 goto retry_read_status; 5503 } else if (!retry_count) { 5504 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5505 } 5506 } else { 5507 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5508 } 5509 no_wait: 5510 netif_carrier_on(netdev); 5511 5512 igb_ping_all_vfs(adapter); 5513 igb_check_vf_rate_limit(adapter); 5514 5515 /* link state has changed, schedule phy info update */ 5516 if (!test_bit(__IGB_DOWN, &adapter->state)) 5517 mod_timer(&adapter->phy_info_timer, 5518 round_jiffies(jiffies + 2 * HZ)); 5519 } 5520 } else { 5521 if (netif_carrier_ok(netdev)) { 5522 adapter->link_speed = 0; 5523 adapter->link_duplex = 0; 5524 5525 /* check for thermal sensor event */ 5526 if (igb_thermal_sensor_event(hw, 5527 E1000_THSTAT_PWR_DOWN)) { 5528 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5529 } 5530 5531 /* Links status message must follow this format */ 5532 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5533 netdev->name); 5534 netif_carrier_off(netdev); 5535 5536 igb_ping_all_vfs(adapter); 5537 5538 /* link state has changed, schedule phy info update */ 5539 if (!test_bit(__IGB_DOWN, &adapter->state)) 5540 mod_timer(&adapter->phy_info_timer, 5541 round_jiffies(jiffies + 2 * HZ)); 5542 5543 /* link is down, time to check for alternate media */ 5544 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5545 igb_check_swap_media(adapter); 5546 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5547 schedule_work(&adapter->reset_task); 5548 /* return immediately */ 5549 return; 5550 } 5551 } 5552 pm_schedule_suspend(netdev->dev.parent, 5553 MSEC_PER_SEC * 5); 5554 5555 /* also check for alternate media here */ 5556 } else if (!netif_carrier_ok(netdev) && 5557 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5558 igb_check_swap_media(adapter); 5559 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5560 schedule_work(&adapter->reset_task); 5561 /* return immediately */ 5562 return; 5563 } 5564 } 5565 } 5566 5567 spin_lock(&adapter->stats64_lock); 5568 igb_update_stats(adapter); 5569 spin_unlock(&adapter->stats64_lock); 5570 5571 for (i = 0; i < adapter->num_tx_queues; i++) { 5572 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5573 if (!netif_carrier_ok(netdev)) { 5574 /* We've lost link, so the controller stops DMA, 5575 * but we've got queued Tx work that's never going 5576 * to get done, so reset controller to flush Tx. 5577 * (Do the reset outside of interrupt context). 5578 */ 5579 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5580 adapter->tx_timeout_count++; 5581 schedule_work(&adapter->reset_task); 5582 /* return immediately since reset is imminent */ 5583 return; 5584 } 5585 } 5586 5587 /* Force detection of hung controller every watchdog period */ 5588 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5589 } 5590 5591 /* Cause software interrupt to ensure Rx ring is cleaned */ 5592 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5593 u32 eics = 0; 5594 5595 for (i = 0; i < adapter->num_q_vectors; i++) 5596 eics |= adapter->q_vector[i]->eims_value; 5597 wr32(E1000_EICS, eics); 5598 } else { 5599 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5600 } 5601 5602 igb_spoof_check(adapter); 5603 igb_ptp_rx_hang(adapter); 5604 igb_ptp_tx_hang(adapter); 5605 5606 /* Check LVMMC register on i350/i354 only */ 5607 if ((adapter->hw.mac.type == e1000_i350) || 5608 (adapter->hw.mac.type == e1000_i354)) 5609 igb_check_lvmmc(adapter); 5610 5611 /* Reset the timer */ 5612 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5613 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5614 mod_timer(&adapter->watchdog_timer, 5615 round_jiffies(jiffies + HZ)); 5616 else 5617 mod_timer(&adapter->watchdog_timer, 5618 round_jiffies(jiffies + 2 * HZ)); 5619 } 5620 } 5621 5622 enum latency_range { 5623 lowest_latency = 0, 5624 low_latency = 1, 5625 bulk_latency = 2, 5626 latency_invalid = 255 5627 }; 5628 5629 /** 5630 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5631 * @q_vector: pointer to q_vector 5632 * 5633 * Stores a new ITR value based on strictly on packet size. This 5634 * algorithm is less sophisticated than that used in igb_update_itr, 5635 * due to the difficulty of synchronizing statistics across multiple 5636 * receive rings. The divisors and thresholds used by this function 5637 * were determined based on theoretical maximum wire speed and testing 5638 * data, in order to minimize response time while increasing bulk 5639 * throughput. 5640 * This functionality is controlled by ethtool's coalescing settings. 5641 * NOTE: This function is called only when operating in a multiqueue 5642 * receive environment. 5643 **/ 5644 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5645 { 5646 int new_val = q_vector->itr_val; 5647 int avg_wire_size = 0; 5648 struct igb_adapter *adapter = q_vector->adapter; 5649 unsigned int packets; 5650 5651 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5652 * ints/sec - ITR timer value of 120 ticks. 5653 */ 5654 if (adapter->link_speed != SPEED_1000) { 5655 new_val = IGB_4K_ITR; 5656 goto set_itr_val; 5657 } 5658 5659 packets = q_vector->rx.total_packets; 5660 if (packets) 5661 avg_wire_size = q_vector->rx.total_bytes / packets; 5662 5663 packets = q_vector->tx.total_packets; 5664 if (packets) 5665 avg_wire_size = max_t(u32, avg_wire_size, 5666 q_vector->tx.total_bytes / packets); 5667 5668 /* if avg_wire_size isn't set no work was done */ 5669 if (!avg_wire_size) 5670 goto clear_counts; 5671 5672 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5673 avg_wire_size += 24; 5674 5675 /* Don't starve jumbo frames */ 5676 avg_wire_size = min(avg_wire_size, 3000); 5677 5678 /* Give a little boost to mid-size frames */ 5679 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5680 new_val = avg_wire_size / 3; 5681 else 5682 new_val = avg_wire_size / 2; 5683 5684 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5685 if (new_val < IGB_20K_ITR && 5686 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5687 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5688 new_val = IGB_20K_ITR; 5689 5690 set_itr_val: 5691 if (new_val != q_vector->itr_val) { 5692 q_vector->itr_val = new_val; 5693 q_vector->set_itr = 1; 5694 } 5695 clear_counts: 5696 q_vector->rx.total_bytes = 0; 5697 q_vector->rx.total_packets = 0; 5698 q_vector->tx.total_bytes = 0; 5699 q_vector->tx.total_packets = 0; 5700 } 5701 5702 /** 5703 * igb_update_itr - update the dynamic ITR value based on statistics 5704 * @q_vector: pointer to q_vector 5705 * @ring_container: ring info to update the itr for 5706 * 5707 * Stores a new ITR value based on packets and byte 5708 * counts during the last interrupt. The advantage of per interrupt 5709 * computation is faster updates and more accurate ITR for the current 5710 * traffic pattern. Constants in this function were computed 5711 * based on theoretical maximum wire speed and thresholds were set based 5712 * on testing data as well as attempting to minimize response time 5713 * while increasing bulk throughput. 5714 * This functionality is controlled by ethtool's coalescing settings. 5715 * NOTE: These calculations are only valid when operating in a single- 5716 * queue environment. 5717 **/ 5718 static void igb_update_itr(struct igb_q_vector *q_vector, 5719 struct igb_ring_container *ring_container) 5720 { 5721 unsigned int packets = ring_container->total_packets; 5722 unsigned int bytes = ring_container->total_bytes; 5723 u8 itrval = ring_container->itr; 5724 5725 /* no packets, exit with status unchanged */ 5726 if (packets == 0) 5727 return; 5728 5729 switch (itrval) { 5730 case lowest_latency: 5731 /* handle TSO and jumbo frames */ 5732 if (bytes/packets > 8000) 5733 itrval = bulk_latency; 5734 else if ((packets < 5) && (bytes > 512)) 5735 itrval = low_latency; 5736 break; 5737 case low_latency: /* 50 usec aka 20000 ints/s */ 5738 if (bytes > 10000) { 5739 /* this if handles the TSO accounting */ 5740 if (bytes/packets > 8000) 5741 itrval = bulk_latency; 5742 else if ((packets < 10) || ((bytes/packets) > 1200)) 5743 itrval = bulk_latency; 5744 else if ((packets > 35)) 5745 itrval = lowest_latency; 5746 } else if (bytes/packets > 2000) { 5747 itrval = bulk_latency; 5748 } else if (packets <= 2 && bytes < 512) { 5749 itrval = lowest_latency; 5750 } 5751 break; 5752 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5753 if (bytes > 25000) { 5754 if (packets > 35) 5755 itrval = low_latency; 5756 } else if (bytes < 1500) { 5757 itrval = low_latency; 5758 } 5759 break; 5760 } 5761 5762 /* clear work counters since we have the values we need */ 5763 ring_container->total_bytes = 0; 5764 ring_container->total_packets = 0; 5765 5766 /* write updated itr to ring container */ 5767 ring_container->itr = itrval; 5768 } 5769 5770 static void igb_set_itr(struct igb_q_vector *q_vector) 5771 { 5772 struct igb_adapter *adapter = q_vector->adapter; 5773 u32 new_itr = q_vector->itr_val; 5774 u8 current_itr = 0; 5775 5776 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5777 if (adapter->link_speed != SPEED_1000) { 5778 current_itr = 0; 5779 new_itr = IGB_4K_ITR; 5780 goto set_itr_now; 5781 } 5782 5783 igb_update_itr(q_vector, &q_vector->tx); 5784 igb_update_itr(q_vector, &q_vector->rx); 5785 5786 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5787 5788 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5789 if (current_itr == lowest_latency && 5790 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5791 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5792 current_itr = low_latency; 5793 5794 switch (current_itr) { 5795 /* counts and packets in update_itr are dependent on these numbers */ 5796 case lowest_latency: 5797 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5798 break; 5799 case low_latency: 5800 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5801 break; 5802 case bulk_latency: 5803 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5804 break; 5805 default: 5806 break; 5807 } 5808 5809 set_itr_now: 5810 if (new_itr != q_vector->itr_val) { 5811 /* this attempts to bias the interrupt rate towards Bulk 5812 * by adding intermediate steps when interrupt rate is 5813 * increasing 5814 */ 5815 new_itr = new_itr > q_vector->itr_val ? 5816 max((new_itr * q_vector->itr_val) / 5817 (new_itr + (q_vector->itr_val >> 2)), 5818 new_itr) : new_itr; 5819 /* Don't write the value here; it resets the adapter's 5820 * internal timer, and causes us to delay far longer than 5821 * we should between interrupts. Instead, we write the ITR 5822 * value at the beginning of the next interrupt so the timing 5823 * ends up being correct. 5824 */ 5825 q_vector->itr_val = new_itr; 5826 q_vector->set_itr = 1; 5827 } 5828 } 5829 5830 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 5831 struct igb_tx_buffer *first, 5832 u32 vlan_macip_lens, u32 type_tucmd, 5833 u32 mss_l4len_idx) 5834 { 5835 struct e1000_adv_tx_context_desc *context_desc; 5836 u16 i = tx_ring->next_to_use; 5837 struct timespec64 ts; 5838 5839 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5840 5841 i++; 5842 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 5843 5844 /* set bits to identify this as an advanced context descriptor */ 5845 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 5846 5847 /* For 82575, context index must be unique per ring. */ 5848 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 5849 mss_l4len_idx |= tx_ring->reg_idx << 4; 5850 5851 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5852 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5853 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5854 5855 /* We assume there is always a valid tx time available. Invalid times 5856 * should have been handled by the upper layers. 5857 */ 5858 if (tx_ring->launchtime_enable) { 5859 ts = ktime_to_timespec64(first->skb->tstamp); 5860 first->skb->tstamp = ktime_set(0, 0); 5861 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 5862 } else { 5863 context_desc->seqnum_seed = 0; 5864 } 5865 } 5866 5867 static int igb_tso(struct igb_ring *tx_ring, 5868 struct igb_tx_buffer *first, 5869 u8 *hdr_len) 5870 { 5871 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 5872 struct sk_buff *skb = first->skb; 5873 union { 5874 struct iphdr *v4; 5875 struct ipv6hdr *v6; 5876 unsigned char *hdr; 5877 } ip; 5878 union { 5879 struct tcphdr *tcp; 5880 struct udphdr *udp; 5881 unsigned char *hdr; 5882 } l4; 5883 u32 paylen, l4_offset; 5884 int err; 5885 5886 if (skb->ip_summed != CHECKSUM_PARTIAL) 5887 return 0; 5888 5889 if (!skb_is_gso(skb)) 5890 return 0; 5891 5892 err = skb_cow_head(skb, 0); 5893 if (err < 0) 5894 return err; 5895 5896 ip.hdr = skb_network_header(skb); 5897 l4.hdr = skb_checksum_start(skb); 5898 5899 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 5900 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 5901 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 5902 5903 /* initialize outer IP header fields */ 5904 if (ip.v4->version == 4) { 5905 unsigned char *csum_start = skb_checksum_start(skb); 5906 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 5907 5908 /* IP header will have to cancel out any data that 5909 * is not a part of the outer IP header 5910 */ 5911 ip.v4->check = csum_fold(csum_partial(trans_start, 5912 csum_start - trans_start, 5913 0)); 5914 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 5915 5916 ip.v4->tot_len = 0; 5917 first->tx_flags |= IGB_TX_FLAGS_TSO | 5918 IGB_TX_FLAGS_CSUM | 5919 IGB_TX_FLAGS_IPV4; 5920 } else { 5921 ip.v6->payload_len = 0; 5922 first->tx_flags |= IGB_TX_FLAGS_TSO | 5923 IGB_TX_FLAGS_CSUM; 5924 } 5925 5926 /* determine offset of inner transport header */ 5927 l4_offset = l4.hdr - skb->data; 5928 5929 /* remove payload length from inner checksum */ 5930 paylen = skb->len - l4_offset; 5931 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 5932 /* compute length of segmentation header */ 5933 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 5934 csum_replace_by_diff(&l4.tcp->check, 5935 (__force __wsum)htonl(paylen)); 5936 } else { 5937 /* compute length of segmentation header */ 5938 *hdr_len = sizeof(*l4.udp) + l4_offset; 5939 csum_replace_by_diff(&l4.udp->check, 5940 (__force __wsum)htonl(paylen)); 5941 } 5942 5943 /* update gso size and bytecount with header size */ 5944 first->gso_segs = skb_shinfo(skb)->gso_segs; 5945 first->bytecount += (first->gso_segs - 1) * *hdr_len; 5946 5947 /* MSS L4LEN IDX */ 5948 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 5949 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 5950 5951 /* VLAN MACLEN IPLEN */ 5952 vlan_macip_lens = l4.hdr - ip.hdr; 5953 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5954 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5955 5956 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 5957 type_tucmd, mss_l4len_idx); 5958 5959 return 1; 5960 } 5961 5962 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb) 5963 { 5964 unsigned int offset = 0; 5965 5966 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 5967 5968 return offset == skb_checksum_start_offset(skb); 5969 } 5970 5971 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 5972 { 5973 struct sk_buff *skb = first->skb; 5974 u32 vlan_macip_lens = 0; 5975 u32 type_tucmd = 0; 5976 5977 if (skb->ip_summed != CHECKSUM_PARTIAL) { 5978 csum_failed: 5979 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 5980 !tx_ring->launchtime_enable) 5981 return; 5982 goto no_csum; 5983 } 5984 5985 switch (skb->csum_offset) { 5986 case offsetof(struct tcphdr, check): 5987 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 5988 fallthrough; 5989 case offsetof(struct udphdr, check): 5990 break; 5991 case offsetof(struct sctphdr, checksum): 5992 /* validate that this is actually an SCTP request */ 5993 if (((first->protocol == htons(ETH_P_IP)) && 5994 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 5995 ((first->protocol == htons(ETH_P_IPV6)) && 5996 igb_ipv6_csum_is_sctp(skb))) { 5997 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 5998 break; 5999 } 6000 fallthrough; 6001 default: 6002 skb_checksum_help(skb); 6003 goto csum_failed; 6004 } 6005 6006 /* update TX checksum flag */ 6007 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6008 vlan_macip_lens = skb_checksum_start_offset(skb) - 6009 skb_network_offset(skb); 6010 no_csum: 6011 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6012 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6013 6014 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6015 } 6016 6017 #define IGB_SET_FLAG(_input, _flag, _result) \ 6018 ((_flag <= _result) ? \ 6019 ((u32)(_input & _flag) * (_result / _flag)) : \ 6020 ((u32)(_input & _flag) / (_flag / _result))) 6021 6022 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6023 { 6024 /* set type for advanced descriptor with frame checksum insertion */ 6025 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6026 E1000_ADVTXD_DCMD_DEXT | 6027 E1000_ADVTXD_DCMD_IFCS; 6028 6029 /* set HW vlan bit if vlan is present */ 6030 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6031 (E1000_ADVTXD_DCMD_VLE)); 6032 6033 /* set segmentation bits for TSO */ 6034 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6035 (E1000_ADVTXD_DCMD_TSE)); 6036 6037 /* set timestamp bit if present */ 6038 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6039 (E1000_ADVTXD_MAC_TSTAMP)); 6040 6041 /* insert frame checksum */ 6042 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6043 6044 return cmd_type; 6045 } 6046 6047 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6048 union e1000_adv_tx_desc *tx_desc, 6049 u32 tx_flags, unsigned int paylen) 6050 { 6051 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6052 6053 /* 82575 requires a unique index per ring */ 6054 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6055 olinfo_status |= tx_ring->reg_idx << 4; 6056 6057 /* insert L4 checksum */ 6058 olinfo_status |= IGB_SET_FLAG(tx_flags, 6059 IGB_TX_FLAGS_CSUM, 6060 (E1000_TXD_POPTS_TXSM << 8)); 6061 6062 /* insert IPv4 checksum */ 6063 olinfo_status |= IGB_SET_FLAG(tx_flags, 6064 IGB_TX_FLAGS_IPV4, 6065 (E1000_TXD_POPTS_IXSM << 8)); 6066 6067 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6068 } 6069 6070 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6071 { 6072 struct net_device *netdev = tx_ring->netdev; 6073 6074 netif_stop_subqueue(netdev, tx_ring->queue_index); 6075 6076 /* Herbert's original patch had: 6077 * smp_mb__after_netif_stop_queue(); 6078 * but since that doesn't exist yet, just open code it. 6079 */ 6080 smp_mb(); 6081 6082 /* We need to check again in a case another CPU has just 6083 * made room available. 6084 */ 6085 if (igb_desc_unused(tx_ring) < size) 6086 return -EBUSY; 6087 6088 /* A reprieve! */ 6089 netif_wake_subqueue(netdev, tx_ring->queue_index); 6090 6091 u64_stats_update_begin(&tx_ring->tx_syncp2); 6092 tx_ring->tx_stats.restart_queue2++; 6093 u64_stats_update_end(&tx_ring->tx_syncp2); 6094 6095 return 0; 6096 } 6097 6098 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6099 { 6100 if (igb_desc_unused(tx_ring) >= size) 6101 return 0; 6102 return __igb_maybe_stop_tx(tx_ring, size); 6103 } 6104 6105 static int igb_tx_map(struct igb_ring *tx_ring, 6106 struct igb_tx_buffer *first, 6107 const u8 hdr_len) 6108 { 6109 struct sk_buff *skb = first->skb; 6110 struct igb_tx_buffer *tx_buffer; 6111 union e1000_adv_tx_desc *tx_desc; 6112 skb_frag_t *frag; 6113 dma_addr_t dma; 6114 unsigned int data_len, size; 6115 u32 tx_flags = first->tx_flags; 6116 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6117 u16 i = tx_ring->next_to_use; 6118 6119 tx_desc = IGB_TX_DESC(tx_ring, i); 6120 6121 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6122 6123 size = skb_headlen(skb); 6124 data_len = skb->data_len; 6125 6126 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6127 6128 tx_buffer = first; 6129 6130 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6131 if (dma_mapping_error(tx_ring->dev, dma)) 6132 goto dma_error; 6133 6134 /* record length, and DMA address */ 6135 dma_unmap_len_set(tx_buffer, len, size); 6136 dma_unmap_addr_set(tx_buffer, dma, dma); 6137 6138 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6139 6140 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6141 tx_desc->read.cmd_type_len = 6142 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6143 6144 i++; 6145 tx_desc++; 6146 if (i == tx_ring->count) { 6147 tx_desc = IGB_TX_DESC(tx_ring, 0); 6148 i = 0; 6149 } 6150 tx_desc->read.olinfo_status = 0; 6151 6152 dma += IGB_MAX_DATA_PER_TXD; 6153 size -= IGB_MAX_DATA_PER_TXD; 6154 6155 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6156 } 6157 6158 if (likely(!data_len)) 6159 break; 6160 6161 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6162 6163 i++; 6164 tx_desc++; 6165 if (i == tx_ring->count) { 6166 tx_desc = IGB_TX_DESC(tx_ring, 0); 6167 i = 0; 6168 } 6169 tx_desc->read.olinfo_status = 0; 6170 6171 size = skb_frag_size(frag); 6172 data_len -= size; 6173 6174 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6175 size, DMA_TO_DEVICE); 6176 6177 tx_buffer = &tx_ring->tx_buffer_info[i]; 6178 } 6179 6180 /* write last descriptor with RS and EOP bits */ 6181 cmd_type |= size | IGB_TXD_DCMD; 6182 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6183 6184 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6185 6186 /* set the timestamp */ 6187 first->time_stamp = jiffies; 6188 6189 skb_tx_timestamp(skb); 6190 6191 /* Force memory writes to complete before letting h/w know there 6192 * are new descriptors to fetch. (Only applicable for weak-ordered 6193 * memory model archs, such as IA-64). 6194 * 6195 * We also need this memory barrier to make certain all of the 6196 * status bits have been updated before next_to_watch is written. 6197 */ 6198 dma_wmb(); 6199 6200 /* set next_to_watch value indicating a packet is present */ 6201 first->next_to_watch = tx_desc; 6202 6203 i++; 6204 if (i == tx_ring->count) 6205 i = 0; 6206 6207 tx_ring->next_to_use = i; 6208 6209 /* Make sure there is space in the ring for the next send. */ 6210 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6211 6212 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6213 writel(i, tx_ring->tail); 6214 } 6215 return 0; 6216 6217 dma_error: 6218 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6219 tx_buffer = &tx_ring->tx_buffer_info[i]; 6220 6221 /* clear dma mappings for failed tx_buffer_info map */ 6222 while (tx_buffer != first) { 6223 if (dma_unmap_len(tx_buffer, len)) 6224 dma_unmap_page(tx_ring->dev, 6225 dma_unmap_addr(tx_buffer, dma), 6226 dma_unmap_len(tx_buffer, len), 6227 DMA_TO_DEVICE); 6228 dma_unmap_len_set(tx_buffer, len, 0); 6229 6230 if (i-- == 0) 6231 i += tx_ring->count; 6232 tx_buffer = &tx_ring->tx_buffer_info[i]; 6233 } 6234 6235 if (dma_unmap_len(tx_buffer, len)) 6236 dma_unmap_single(tx_ring->dev, 6237 dma_unmap_addr(tx_buffer, dma), 6238 dma_unmap_len(tx_buffer, len), 6239 DMA_TO_DEVICE); 6240 dma_unmap_len_set(tx_buffer, len, 0); 6241 6242 dev_kfree_skb_any(tx_buffer->skb); 6243 tx_buffer->skb = NULL; 6244 6245 tx_ring->next_to_use = i; 6246 6247 return -1; 6248 } 6249 6250 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6251 struct igb_ring *tx_ring, 6252 struct xdp_frame *xdpf) 6253 { 6254 union e1000_adv_tx_desc *tx_desc; 6255 u32 len, cmd_type, olinfo_status; 6256 struct igb_tx_buffer *tx_buffer; 6257 dma_addr_t dma; 6258 u16 i; 6259 6260 len = xdpf->len; 6261 6262 if (unlikely(!igb_desc_unused(tx_ring))) 6263 return IGB_XDP_CONSUMED; 6264 6265 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE); 6266 if (dma_mapping_error(tx_ring->dev, dma)) 6267 return IGB_XDP_CONSUMED; 6268 6269 /* record the location of the first descriptor for this packet */ 6270 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6271 tx_buffer->bytecount = len; 6272 tx_buffer->gso_segs = 1; 6273 tx_buffer->protocol = 0; 6274 6275 i = tx_ring->next_to_use; 6276 tx_desc = IGB_TX_DESC(tx_ring, i); 6277 6278 dma_unmap_len_set(tx_buffer, len, len); 6279 dma_unmap_addr_set(tx_buffer, dma, dma); 6280 tx_buffer->type = IGB_TYPE_XDP; 6281 tx_buffer->xdpf = xdpf; 6282 6283 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6284 6285 /* put descriptor type bits */ 6286 cmd_type = E1000_ADVTXD_DTYP_DATA | 6287 E1000_ADVTXD_DCMD_DEXT | 6288 E1000_ADVTXD_DCMD_IFCS; 6289 cmd_type |= len | IGB_TXD_DCMD; 6290 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6291 6292 olinfo_status = cpu_to_le32(len << E1000_ADVTXD_PAYLEN_SHIFT); 6293 /* 82575 requires a unique index per ring */ 6294 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6295 olinfo_status |= tx_ring->reg_idx << 4; 6296 6297 tx_desc->read.olinfo_status = olinfo_status; 6298 6299 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount); 6300 6301 /* set the timestamp */ 6302 tx_buffer->time_stamp = jiffies; 6303 6304 /* Avoid any potential race with xdp_xmit and cleanup */ 6305 smp_wmb(); 6306 6307 /* set next_to_watch value indicating a packet is present */ 6308 i++; 6309 if (i == tx_ring->count) 6310 i = 0; 6311 6312 tx_buffer->next_to_watch = tx_desc; 6313 tx_ring->next_to_use = i; 6314 6315 /* Make sure there is space in the ring for the next send. */ 6316 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6317 6318 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6319 writel(i, tx_ring->tail); 6320 6321 return IGB_XDP_TX; 6322 } 6323 6324 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6325 struct igb_ring *tx_ring) 6326 { 6327 struct igb_tx_buffer *first; 6328 int tso; 6329 u32 tx_flags = 0; 6330 unsigned short f; 6331 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6332 __be16 protocol = vlan_get_protocol(skb); 6333 u8 hdr_len = 0; 6334 6335 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6336 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6337 * + 2 desc gap to keep tail from touching head, 6338 * + 1 desc for context descriptor, 6339 * otherwise try next time 6340 */ 6341 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6342 count += TXD_USE_COUNT(skb_frag_size( 6343 &skb_shinfo(skb)->frags[f])); 6344 6345 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6346 /* this is a hard error */ 6347 return NETDEV_TX_BUSY; 6348 } 6349 6350 /* record the location of the first descriptor for this packet */ 6351 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6352 first->type = IGB_TYPE_SKB; 6353 first->skb = skb; 6354 first->bytecount = skb->len; 6355 first->gso_segs = 1; 6356 6357 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6358 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6359 6360 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6361 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6362 &adapter->state)) { 6363 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6364 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6365 6366 adapter->ptp_tx_skb = skb_get(skb); 6367 adapter->ptp_tx_start = jiffies; 6368 if (adapter->hw.mac.type == e1000_82576) 6369 schedule_work(&adapter->ptp_tx_work); 6370 } else { 6371 adapter->tx_hwtstamp_skipped++; 6372 } 6373 } 6374 6375 if (skb_vlan_tag_present(skb)) { 6376 tx_flags |= IGB_TX_FLAGS_VLAN; 6377 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6378 } 6379 6380 /* record initial flags and protocol */ 6381 first->tx_flags = tx_flags; 6382 first->protocol = protocol; 6383 6384 tso = igb_tso(tx_ring, first, &hdr_len); 6385 if (tso < 0) 6386 goto out_drop; 6387 else if (!tso) 6388 igb_tx_csum(tx_ring, first); 6389 6390 if (igb_tx_map(tx_ring, first, hdr_len)) 6391 goto cleanup_tx_tstamp; 6392 6393 return NETDEV_TX_OK; 6394 6395 out_drop: 6396 dev_kfree_skb_any(first->skb); 6397 first->skb = NULL; 6398 cleanup_tx_tstamp: 6399 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6400 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6401 6402 dev_kfree_skb_any(adapter->ptp_tx_skb); 6403 adapter->ptp_tx_skb = NULL; 6404 if (adapter->hw.mac.type == e1000_82576) 6405 cancel_work_sync(&adapter->ptp_tx_work); 6406 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6407 } 6408 6409 return NETDEV_TX_OK; 6410 } 6411 6412 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6413 struct sk_buff *skb) 6414 { 6415 unsigned int r_idx = skb->queue_mapping; 6416 6417 if (r_idx >= adapter->num_tx_queues) 6418 r_idx = r_idx % adapter->num_tx_queues; 6419 6420 return adapter->tx_ring[r_idx]; 6421 } 6422 6423 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6424 struct net_device *netdev) 6425 { 6426 struct igb_adapter *adapter = netdev_priv(netdev); 6427 6428 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6429 * in order to meet this minimum size requirement. 6430 */ 6431 if (skb_put_padto(skb, 17)) 6432 return NETDEV_TX_OK; 6433 6434 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6435 } 6436 6437 /** 6438 * igb_tx_timeout - Respond to a Tx Hang 6439 * @netdev: network interface device structure 6440 * @txqueue: number of the Tx queue that hung (unused) 6441 **/ 6442 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6443 { 6444 struct igb_adapter *adapter = netdev_priv(netdev); 6445 struct e1000_hw *hw = &adapter->hw; 6446 6447 /* Do the reset outside of interrupt context */ 6448 adapter->tx_timeout_count++; 6449 6450 if (hw->mac.type >= e1000_82580) 6451 hw->dev_spec._82575.global_device_reset = true; 6452 6453 schedule_work(&adapter->reset_task); 6454 wr32(E1000_EICS, 6455 (adapter->eims_enable_mask & ~adapter->eims_other)); 6456 } 6457 6458 static void igb_reset_task(struct work_struct *work) 6459 { 6460 struct igb_adapter *adapter; 6461 adapter = container_of(work, struct igb_adapter, reset_task); 6462 6463 rtnl_lock(); 6464 /* If we're already down or resetting, just bail */ 6465 if (test_bit(__IGB_DOWN, &adapter->state) || 6466 test_bit(__IGB_RESETTING, &adapter->state)) { 6467 rtnl_unlock(); 6468 return; 6469 } 6470 6471 igb_dump(adapter); 6472 netdev_err(adapter->netdev, "Reset adapter\n"); 6473 igb_reinit_locked(adapter); 6474 rtnl_unlock(); 6475 } 6476 6477 /** 6478 * igb_get_stats64 - Get System Network Statistics 6479 * @netdev: network interface device structure 6480 * @stats: rtnl_link_stats64 pointer 6481 **/ 6482 static void igb_get_stats64(struct net_device *netdev, 6483 struct rtnl_link_stats64 *stats) 6484 { 6485 struct igb_adapter *adapter = netdev_priv(netdev); 6486 6487 spin_lock(&adapter->stats64_lock); 6488 igb_update_stats(adapter); 6489 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6490 spin_unlock(&adapter->stats64_lock); 6491 } 6492 6493 /** 6494 * igb_change_mtu - Change the Maximum Transfer Unit 6495 * @netdev: network interface device structure 6496 * @new_mtu: new value for maximum frame size 6497 * 6498 * Returns 0 on success, negative on failure 6499 **/ 6500 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6501 { 6502 struct igb_adapter *adapter = netdev_priv(netdev); 6503 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6504 6505 if (adapter->xdp_prog) { 6506 int i; 6507 6508 for (i = 0; i < adapter->num_rx_queues; i++) { 6509 struct igb_ring *ring = adapter->rx_ring[i]; 6510 6511 if (max_frame > igb_rx_bufsz(ring)) { 6512 netdev_warn(adapter->netdev, 6513 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6514 max_frame); 6515 return -EINVAL; 6516 } 6517 } 6518 } 6519 6520 /* adjust max frame to be at least the size of a standard frame */ 6521 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6522 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6523 6524 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6525 usleep_range(1000, 2000); 6526 6527 /* igb_down has a dependency on max_frame_size */ 6528 adapter->max_frame_size = max_frame; 6529 6530 if (netif_running(netdev)) 6531 igb_down(adapter); 6532 6533 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6534 netdev->mtu, new_mtu); 6535 netdev->mtu = new_mtu; 6536 6537 if (netif_running(netdev)) 6538 igb_up(adapter); 6539 else 6540 igb_reset(adapter); 6541 6542 clear_bit(__IGB_RESETTING, &adapter->state); 6543 6544 return 0; 6545 } 6546 6547 /** 6548 * igb_update_stats - Update the board statistics counters 6549 * @adapter: board private structure 6550 **/ 6551 void igb_update_stats(struct igb_adapter *adapter) 6552 { 6553 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6554 struct e1000_hw *hw = &adapter->hw; 6555 struct pci_dev *pdev = adapter->pdev; 6556 u32 reg, mpc; 6557 int i; 6558 u64 bytes, packets; 6559 unsigned int start; 6560 u64 _bytes, _packets; 6561 6562 /* Prevent stats update while adapter is being reset, or if the pci 6563 * connection is down. 6564 */ 6565 if (adapter->link_speed == 0) 6566 return; 6567 if (pci_channel_offline(pdev)) 6568 return; 6569 6570 bytes = 0; 6571 packets = 0; 6572 6573 rcu_read_lock(); 6574 for (i = 0; i < adapter->num_rx_queues; i++) { 6575 struct igb_ring *ring = adapter->rx_ring[i]; 6576 u32 rqdpc = rd32(E1000_RQDPC(i)); 6577 if (hw->mac.type >= e1000_i210) 6578 wr32(E1000_RQDPC(i), 0); 6579 6580 if (rqdpc) { 6581 ring->rx_stats.drops += rqdpc; 6582 net_stats->rx_fifo_errors += rqdpc; 6583 } 6584 6585 do { 6586 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 6587 _bytes = ring->rx_stats.bytes; 6588 _packets = ring->rx_stats.packets; 6589 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 6590 bytes += _bytes; 6591 packets += _packets; 6592 } 6593 6594 net_stats->rx_bytes = bytes; 6595 net_stats->rx_packets = packets; 6596 6597 bytes = 0; 6598 packets = 0; 6599 for (i = 0; i < adapter->num_tx_queues; i++) { 6600 struct igb_ring *ring = adapter->tx_ring[i]; 6601 do { 6602 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 6603 _bytes = ring->tx_stats.bytes; 6604 _packets = ring->tx_stats.packets; 6605 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 6606 bytes += _bytes; 6607 packets += _packets; 6608 } 6609 net_stats->tx_bytes = bytes; 6610 net_stats->tx_packets = packets; 6611 rcu_read_unlock(); 6612 6613 /* read stats registers */ 6614 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6615 adapter->stats.gprc += rd32(E1000_GPRC); 6616 adapter->stats.gorc += rd32(E1000_GORCL); 6617 rd32(E1000_GORCH); /* clear GORCL */ 6618 adapter->stats.bprc += rd32(E1000_BPRC); 6619 adapter->stats.mprc += rd32(E1000_MPRC); 6620 adapter->stats.roc += rd32(E1000_ROC); 6621 6622 adapter->stats.prc64 += rd32(E1000_PRC64); 6623 adapter->stats.prc127 += rd32(E1000_PRC127); 6624 adapter->stats.prc255 += rd32(E1000_PRC255); 6625 adapter->stats.prc511 += rd32(E1000_PRC511); 6626 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6627 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6628 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6629 adapter->stats.sec += rd32(E1000_SEC); 6630 6631 mpc = rd32(E1000_MPC); 6632 adapter->stats.mpc += mpc; 6633 net_stats->rx_fifo_errors += mpc; 6634 adapter->stats.scc += rd32(E1000_SCC); 6635 adapter->stats.ecol += rd32(E1000_ECOL); 6636 adapter->stats.mcc += rd32(E1000_MCC); 6637 adapter->stats.latecol += rd32(E1000_LATECOL); 6638 adapter->stats.dc += rd32(E1000_DC); 6639 adapter->stats.rlec += rd32(E1000_RLEC); 6640 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6641 adapter->stats.xontxc += rd32(E1000_XONTXC); 6642 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6643 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6644 adapter->stats.fcruc += rd32(E1000_FCRUC); 6645 adapter->stats.gptc += rd32(E1000_GPTC); 6646 adapter->stats.gotc += rd32(E1000_GOTCL); 6647 rd32(E1000_GOTCH); /* clear GOTCL */ 6648 adapter->stats.rnbc += rd32(E1000_RNBC); 6649 adapter->stats.ruc += rd32(E1000_RUC); 6650 adapter->stats.rfc += rd32(E1000_RFC); 6651 adapter->stats.rjc += rd32(E1000_RJC); 6652 adapter->stats.tor += rd32(E1000_TORH); 6653 adapter->stats.tot += rd32(E1000_TOTH); 6654 adapter->stats.tpr += rd32(E1000_TPR); 6655 6656 adapter->stats.ptc64 += rd32(E1000_PTC64); 6657 adapter->stats.ptc127 += rd32(E1000_PTC127); 6658 adapter->stats.ptc255 += rd32(E1000_PTC255); 6659 adapter->stats.ptc511 += rd32(E1000_PTC511); 6660 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6661 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6662 6663 adapter->stats.mptc += rd32(E1000_MPTC); 6664 adapter->stats.bptc += rd32(E1000_BPTC); 6665 6666 adapter->stats.tpt += rd32(E1000_TPT); 6667 adapter->stats.colc += rd32(E1000_COLC); 6668 6669 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6670 /* read internal phy specific stats */ 6671 reg = rd32(E1000_CTRL_EXT); 6672 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6673 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6674 6675 /* this stat has invalid values on i210/i211 */ 6676 if ((hw->mac.type != e1000_i210) && 6677 (hw->mac.type != e1000_i211)) 6678 adapter->stats.tncrs += rd32(E1000_TNCRS); 6679 } 6680 6681 adapter->stats.tsctc += rd32(E1000_TSCTC); 6682 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6683 6684 adapter->stats.iac += rd32(E1000_IAC); 6685 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6686 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6687 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6688 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6689 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6690 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6691 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6692 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6693 6694 /* Fill out the OS statistics structure */ 6695 net_stats->multicast = adapter->stats.mprc; 6696 net_stats->collisions = adapter->stats.colc; 6697 6698 /* Rx Errors */ 6699 6700 /* RLEC on some newer hardware can be incorrect so build 6701 * our own version based on RUC and ROC 6702 */ 6703 net_stats->rx_errors = adapter->stats.rxerrc + 6704 adapter->stats.crcerrs + adapter->stats.algnerrc + 6705 adapter->stats.ruc + adapter->stats.roc + 6706 adapter->stats.cexterr; 6707 net_stats->rx_length_errors = adapter->stats.ruc + 6708 adapter->stats.roc; 6709 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6710 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6711 net_stats->rx_missed_errors = adapter->stats.mpc; 6712 6713 /* Tx Errors */ 6714 net_stats->tx_errors = adapter->stats.ecol + 6715 adapter->stats.latecol; 6716 net_stats->tx_aborted_errors = adapter->stats.ecol; 6717 net_stats->tx_window_errors = adapter->stats.latecol; 6718 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6719 6720 /* Tx Dropped needs to be maintained elsewhere */ 6721 6722 /* Management Stats */ 6723 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6724 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6725 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6726 6727 /* OS2BMC Stats */ 6728 reg = rd32(E1000_MANC); 6729 if (reg & E1000_MANC_EN_BMC2OS) { 6730 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6731 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6732 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6733 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6734 } 6735 } 6736 6737 static void igb_tsync_interrupt(struct igb_adapter *adapter) 6738 { 6739 struct e1000_hw *hw = &adapter->hw; 6740 struct ptp_clock_event event; 6741 struct timespec64 ts; 6742 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR); 6743 6744 if (tsicr & TSINTR_SYS_WRAP) { 6745 event.type = PTP_CLOCK_PPS; 6746 if (adapter->ptp_caps.pps) 6747 ptp_clock_event(adapter->ptp_clock, &event); 6748 ack |= TSINTR_SYS_WRAP; 6749 } 6750 6751 if (tsicr & E1000_TSICR_TXTS) { 6752 /* retrieve hardware timestamp */ 6753 schedule_work(&adapter->ptp_tx_work); 6754 ack |= E1000_TSICR_TXTS; 6755 } 6756 6757 if (tsicr & TSINTR_TT0) { 6758 spin_lock(&adapter->tmreg_lock); 6759 ts = timespec64_add(adapter->perout[0].start, 6760 adapter->perout[0].period); 6761 /* u32 conversion of tv_sec is safe until y2106 */ 6762 wr32(E1000_TRGTTIML0, ts.tv_nsec); 6763 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec); 6764 tsauxc = rd32(E1000_TSAUXC); 6765 tsauxc |= TSAUXC_EN_TT0; 6766 wr32(E1000_TSAUXC, tsauxc); 6767 adapter->perout[0].start = ts; 6768 spin_unlock(&adapter->tmreg_lock); 6769 ack |= TSINTR_TT0; 6770 } 6771 6772 if (tsicr & TSINTR_TT1) { 6773 spin_lock(&adapter->tmreg_lock); 6774 ts = timespec64_add(adapter->perout[1].start, 6775 adapter->perout[1].period); 6776 wr32(E1000_TRGTTIML1, ts.tv_nsec); 6777 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec); 6778 tsauxc = rd32(E1000_TSAUXC); 6779 tsauxc |= TSAUXC_EN_TT1; 6780 wr32(E1000_TSAUXC, tsauxc); 6781 adapter->perout[1].start = ts; 6782 spin_unlock(&adapter->tmreg_lock); 6783 ack |= TSINTR_TT1; 6784 } 6785 6786 if (tsicr & TSINTR_AUTT0) { 6787 nsec = rd32(E1000_AUXSTMPL0); 6788 sec = rd32(E1000_AUXSTMPH0); 6789 event.type = PTP_CLOCK_EXTTS; 6790 event.index = 0; 6791 event.timestamp = sec * 1000000000ULL + nsec; 6792 ptp_clock_event(adapter->ptp_clock, &event); 6793 ack |= TSINTR_AUTT0; 6794 } 6795 6796 if (tsicr & TSINTR_AUTT1) { 6797 nsec = rd32(E1000_AUXSTMPL1); 6798 sec = rd32(E1000_AUXSTMPH1); 6799 event.type = PTP_CLOCK_EXTTS; 6800 event.index = 1; 6801 event.timestamp = sec * 1000000000ULL + nsec; 6802 ptp_clock_event(adapter->ptp_clock, &event); 6803 ack |= TSINTR_AUTT1; 6804 } 6805 6806 /* acknowledge the interrupts */ 6807 wr32(E1000_TSICR, ack); 6808 } 6809 6810 static irqreturn_t igb_msix_other(int irq, void *data) 6811 { 6812 struct igb_adapter *adapter = data; 6813 struct e1000_hw *hw = &adapter->hw; 6814 u32 icr = rd32(E1000_ICR); 6815 /* reading ICR causes bit 31 of EICR to be cleared */ 6816 6817 if (icr & E1000_ICR_DRSTA) 6818 schedule_work(&adapter->reset_task); 6819 6820 if (icr & E1000_ICR_DOUTSYNC) { 6821 /* HW is reporting DMA is out of sync */ 6822 adapter->stats.doosync++; 6823 /* The DMA Out of Sync is also indication of a spoof event 6824 * in IOV mode. Check the Wrong VM Behavior register to 6825 * see if it is really a spoof event. 6826 */ 6827 igb_check_wvbr(adapter); 6828 } 6829 6830 /* Check for a mailbox event */ 6831 if (icr & E1000_ICR_VMMB) 6832 igb_msg_task(adapter); 6833 6834 if (icr & E1000_ICR_LSC) { 6835 hw->mac.get_link_status = 1; 6836 /* guard against interrupt when we're going down */ 6837 if (!test_bit(__IGB_DOWN, &adapter->state)) 6838 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6839 } 6840 6841 if (icr & E1000_ICR_TS) 6842 igb_tsync_interrupt(adapter); 6843 6844 wr32(E1000_EIMS, adapter->eims_other); 6845 6846 return IRQ_HANDLED; 6847 } 6848 6849 static void igb_write_itr(struct igb_q_vector *q_vector) 6850 { 6851 struct igb_adapter *adapter = q_vector->adapter; 6852 u32 itr_val = q_vector->itr_val & 0x7FFC; 6853 6854 if (!q_vector->set_itr) 6855 return; 6856 6857 if (!itr_val) 6858 itr_val = 0x4; 6859 6860 if (adapter->hw.mac.type == e1000_82575) 6861 itr_val |= itr_val << 16; 6862 else 6863 itr_val |= E1000_EITR_CNT_IGNR; 6864 6865 writel(itr_val, q_vector->itr_register); 6866 q_vector->set_itr = 0; 6867 } 6868 6869 static irqreturn_t igb_msix_ring(int irq, void *data) 6870 { 6871 struct igb_q_vector *q_vector = data; 6872 6873 /* Write the ITR value calculated from the previous interrupt. */ 6874 igb_write_itr(q_vector); 6875 6876 napi_schedule(&q_vector->napi); 6877 6878 return IRQ_HANDLED; 6879 } 6880 6881 #ifdef CONFIG_IGB_DCA 6882 static void igb_update_tx_dca(struct igb_adapter *adapter, 6883 struct igb_ring *tx_ring, 6884 int cpu) 6885 { 6886 struct e1000_hw *hw = &adapter->hw; 6887 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 6888 6889 if (hw->mac.type != e1000_82575) 6890 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 6891 6892 /* We can enable relaxed ordering for reads, but not writes when 6893 * DCA is enabled. This is due to a known issue in some chipsets 6894 * which will cause the DCA tag to be cleared. 6895 */ 6896 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 6897 E1000_DCA_TXCTRL_DATA_RRO_EN | 6898 E1000_DCA_TXCTRL_DESC_DCA_EN; 6899 6900 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 6901 } 6902 6903 static void igb_update_rx_dca(struct igb_adapter *adapter, 6904 struct igb_ring *rx_ring, 6905 int cpu) 6906 { 6907 struct e1000_hw *hw = &adapter->hw; 6908 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 6909 6910 if (hw->mac.type != e1000_82575) 6911 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 6912 6913 /* We can enable relaxed ordering for reads, but not writes when 6914 * DCA is enabled. This is due to a known issue in some chipsets 6915 * which will cause the DCA tag to be cleared. 6916 */ 6917 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 6918 E1000_DCA_RXCTRL_DESC_DCA_EN; 6919 6920 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 6921 } 6922 6923 static void igb_update_dca(struct igb_q_vector *q_vector) 6924 { 6925 struct igb_adapter *adapter = q_vector->adapter; 6926 int cpu = get_cpu(); 6927 6928 if (q_vector->cpu == cpu) 6929 goto out_no_update; 6930 6931 if (q_vector->tx.ring) 6932 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 6933 6934 if (q_vector->rx.ring) 6935 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 6936 6937 q_vector->cpu = cpu; 6938 out_no_update: 6939 put_cpu(); 6940 } 6941 6942 static void igb_setup_dca(struct igb_adapter *adapter) 6943 { 6944 struct e1000_hw *hw = &adapter->hw; 6945 int i; 6946 6947 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 6948 return; 6949 6950 /* Always use CB2 mode, difference is masked in the CB driver. */ 6951 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 6952 6953 for (i = 0; i < adapter->num_q_vectors; i++) { 6954 adapter->q_vector[i]->cpu = -1; 6955 igb_update_dca(adapter->q_vector[i]); 6956 } 6957 } 6958 6959 static int __igb_notify_dca(struct device *dev, void *data) 6960 { 6961 struct net_device *netdev = dev_get_drvdata(dev); 6962 struct igb_adapter *adapter = netdev_priv(netdev); 6963 struct pci_dev *pdev = adapter->pdev; 6964 struct e1000_hw *hw = &adapter->hw; 6965 unsigned long event = *(unsigned long *)data; 6966 6967 switch (event) { 6968 case DCA_PROVIDER_ADD: 6969 /* if already enabled, don't do it again */ 6970 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 6971 break; 6972 if (dca_add_requester(dev) == 0) { 6973 adapter->flags |= IGB_FLAG_DCA_ENABLED; 6974 dev_info(&pdev->dev, "DCA enabled\n"); 6975 igb_setup_dca(adapter); 6976 break; 6977 } 6978 fallthrough; /* since DCA is disabled. */ 6979 case DCA_PROVIDER_REMOVE: 6980 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 6981 /* without this a class_device is left 6982 * hanging around in the sysfs model 6983 */ 6984 dca_remove_requester(dev); 6985 dev_info(&pdev->dev, "DCA disabled\n"); 6986 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 6987 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 6988 } 6989 break; 6990 } 6991 6992 return 0; 6993 } 6994 6995 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 6996 void *p) 6997 { 6998 int ret_val; 6999 7000 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7001 __igb_notify_dca); 7002 7003 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7004 } 7005 #endif /* CONFIG_IGB_DCA */ 7006 7007 #ifdef CONFIG_PCI_IOV 7008 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7009 { 7010 unsigned char mac_addr[ETH_ALEN]; 7011 7012 eth_zero_addr(mac_addr); 7013 igb_set_vf_mac(adapter, vf, mac_addr); 7014 7015 /* By default spoof check is enabled for all VFs */ 7016 adapter->vf_data[vf].spoofchk_enabled = true; 7017 7018 /* By default VFs are not trusted */ 7019 adapter->vf_data[vf].trusted = false; 7020 7021 return 0; 7022 } 7023 7024 #endif 7025 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7026 { 7027 struct e1000_hw *hw = &adapter->hw; 7028 u32 ping; 7029 int i; 7030 7031 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7032 ping = E1000_PF_CONTROL_MSG; 7033 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7034 ping |= E1000_VT_MSGTYPE_CTS; 7035 igb_write_mbx(hw, &ping, 1, i); 7036 } 7037 } 7038 7039 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7040 { 7041 struct e1000_hw *hw = &adapter->hw; 7042 u32 vmolr = rd32(E1000_VMOLR(vf)); 7043 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7044 7045 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7046 IGB_VF_FLAG_MULTI_PROMISC); 7047 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7048 7049 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7050 vmolr |= E1000_VMOLR_MPME; 7051 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7052 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7053 } else { 7054 /* if we have hashes and we are clearing a multicast promisc 7055 * flag we need to write the hashes to the MTA as this step 7056 * was previously skipped 7057 */ 7058 if (vf_data->num_vf_mc_hashes > 30) { 7059 vmolr |= E1000_VMOLR_MPME; 7060 } else if (vf_data->num_vf_mc_hashes) { 7061 int j; 7062 7063 vmolr |= E1000_VMOLR_ROMPE; 7064 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7065 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7066 } 7067 } 7068 7069 wr32(E1000_VMOLR(vf), vmolr); 7070 7071 /* there are flags left unprocessed, likely not supported */ 7072 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7073 return -EINVAL; 7074 7075 return 0; 7076 } 7077 7078 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7079 u32 *msgbuf, u32 vf) 7080 { 7081 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7082 u16 *hash_list = (u16 *)&msgbuf[1]; 7083 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7084 int i; 7085 7086 /* salt away the number of multicast addresses assigned 7087 * to this VF for later use to restore when the PF multi cast 7088 * list changes 7089 */ 7090 vf_data->num_vf_mc_hashes = n; 7091 7092 /* only up to 30 hash values supported */ 7093 if (n > 30) 7094 n = 30; 7095 7096 /* store the hashes for later use */ 7097 for (i = 0; i < n; i++) 7098 vf_data->vf_mc_hashes[i] = hash_list[i]; 7099 7100 /* Flush and reset the mta with the new values */ 7101 igb_set_rx_mode(adapter->netdev); 7102 7103 return 0; 7104 } 7105 7106 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7107 { 7108 struct e1000_hw *hw = &adapter->hw; 7109 struct vf_data_storage *vf_data; 7110 int i, j; 7111 7112 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7113 u32 vmolr = rd32(E1000_VMOLR(i)); 7114 7115 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7116 7117 vf_data = &adapter->vf_data[i]; 7118 7119 if ((vf_data->num_vf_mc_hashes > 30) || 7120 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7121 vmolr |= E1000_VMOLR_MPME; 7122 } else if (vf_data->num_vf_mc_hashes) { 7123 vmolr |= E1000_VMOLR_ROMPE; 7124 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7125 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7126 } 7127 wr32(E1000_VMOLR(i), vmolr); 7128 } 7129 } 7130 7131 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7132 { 7133 struct e1000_hw *hw = &adapter->hw; 7134 u32 pool_mask, vlvf_mask, i; 7135 7136 /* create mask for VF and other pools */ 7137 pool_mask = E1000_VLVF_POOLSEL_MASK; 7138 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7139 7140 /* drop PF from pool bits */ 7141 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7142 adapter->vfs_allocated_count); 7143 7144 /* Find the vlan filter for this id */ 7145 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7146 u32 vlvf = rd32(E1000_VLVF(i)); 7147 u32 vfta_mask, vid, vfta; 7148 7149 /* remove the vf from the pool */ 7150 if (!(vlvf & vlvf_mask)) 7151 continue; 7152 7153 /* clear out bit from VLVF */ 7154 vlvf ^= vlvf_mask; 7155 7156 /* if other pools are present, just remove ourselves */ 7157 if (vlvf & pool_mask) 7158 goto update_vlvfb; 7159 7160 /* if PF is present, leave VFTA */ 7161 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7162 goto update_vlvf; 7163 7164 vid = vlvf & E1000_VLVF_VLANID_MASK; 7165 vfta_mask = BIT(vid % 32); 7166 7167 /* clear bit from VFTA */ 7168 vfta = adapter->shadow_vfta[vid / 32]; 7169 if (vfta & vfta_mask) 7170 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7171 update_vlvf: 7172 /* clear pool selection enable */ 7173 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7174 vlvf &= E1000_VLVF_POOLSEL_MASK; 7175 else 7176 vlvf = 0; 7177 update_vlvfb: 7178 /* clear pool bits */ 7179 wr32(E1000_VLVF(i), vlvf); 7180 } 7181 } 7182 7183 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7184 { 7185 u32 vlvf; 7186 int idx; 7187 7188 /* short cut the special case */ 7189 if (vlan == 0) 7190 return 0; 7191 7192 /* Search for the VLAN id in the VLVF entries */ 7193 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7194 vlvf = rd32(E1000_VLVF(idx)); 7195 if ((vlvf & VLAN_VID_MASK) == vlan) 7196 break; 7197 } 7198 7199 return idx; 7200 } 7201 7202 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7203 { 7204 struct e1000_hw *hw = &adapter->hw; 7205 u32 bits, pf_id; 7206 int idx; 7207 7208 idx = igb_find_vlvf_entry(hw, vid); 7209 if (!idx) 7210 return; 7211 7212 /* See if any other pools are set for this VLAN filter 7213 * entry other than the PF. 7214 */ 7215 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7216 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7217 bits &= rd32(E1000_VLVF(idx)); 7218 7219 /* Disable the filter so this falls into the default pool. */ 7220 if (!bits) { 7221 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7222 wr32(E1000_VLVF(idx), BIT(pf_id)); 7223 else 7224 wr32(E1000_VLVF(idx), 0); 7225 } 7226 } 7227 7228 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7229 bool add, u32 vf) 7230 { 7231 int pf_id = adapter->vfs_allocated_count; 7232 struct e1000_hw *hw = &adapter->hw; 7233 int err; 7234 7235 /* If VLAN overlaps with one the PF is currently monitoring make 7236 * sure that we are able to allocate a VLVF entry. This may be 7237 * redundant but it guarantees PF will maintain visibility to 7238 * the VLAN. 7239 */ 7240 if (add && test_bit(vid, adapter->active_vlans)) { 7241 err = igb_vfta_set(hw, vid, pf_id, true, false); 7242 if (err) 7243 return err; 7244 } 7245 7246 err = igb_vfta_set(hw, vid, vf, add, false); 7247 7248 if (add && !err) 7249 return err; 7250 7251 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7252 * we may need to drop the PF pool bit in order to allow us to free 7253 * up the VLVF resources. 7254 */ 7255 if (test_bit(vid, adapter->active_vlans) || 7256 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7257 igb_update_pf_vlvf(adapter, vid); 7258 7259 return err; 7260 } 7261 7262 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7263 { 7264 struct e1000_hw *hw = &adapter->hw; 7265 7266 if (vid) 7267 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7268 else 7269 wr32(E1000_VMVIR(vf), 0); 7270 } 7271 7272 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7273 u16 vlan, u8 qos) 7274 { 7275 int err; 7276 7277 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7278 if (err) 7279 return err; 7280 7281 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7282 igb_set_vmolr(adapter, vf, !vlan); 7283 7284 /* revoke access to previous VLAN */ 7285 if (vlan != adapter->vf_data[vf].pf_vlan) 7286 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7287 false, vf); 7288 7289 adapter->vf_data[vf].pf_vlan = vlan; 7290 adapter->vf_data[vf].pf_qos = qos; 7291 igb_set_vf_vlan_strip(adapter, vf, true); 7292 dev_info(&adapter->pdev->dev, 7293 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7294 if (test_bit(__IGB_DOWN, &adapter->state)) { 7295 dev_warn(&adapter->pdev->dev, 7296 "The VF VLAN has been set, but the PF device is not up.\n"); 7297 dev_warn(&adapter->pdev->dev, 7298 "Bring the PF device up before attempting to use the VF device.\n"); 7299 } 7300 7301 return err; 7302 } 7303 7304 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7305 { 7306 /* Restore tagless access via VLAN 0 */ 7307 igb_set_vf_vlan(adapter, 0, true, vf); 7308 7309 igb_set_vmvir(adapter, 0, vf); 7310 igb_set_vmolr(adapter, vf, true); 7311 7312 /* Remove any PF assigned VLAN */ 7313 if (adapter->vf_data[vf].pf_vlan) 7314 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7315 false, vf); 7316 7317 adapter->vf_data[vf].pf_vlan = 0; 7318 adapter->vf_data[vf].pf_qos = 0; 7319 igb_set_vf_vlan_strip(adapter, vf, false); 7320 7321 return 0; 7322 } 7323 7324 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7325 u16 vlan, u8 qos, __be16 vlan_proto) 7326 { 7327 struct igb_adapter *adapter = netdev_priv(netdev); 7328 7329 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7330 return -EINVAL; 7331 7332 if (vlan_proto != htons(ETH_P_8021Q)) 7333 return -EPROTONOSUPPORT; 7334 7335 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7336 igb_disable_port_vlan(adapter, vf); 7337 } 7338 7339 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7340 { 7341 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7342 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7343 int ret; 7344 7345 if (adapter->vf_data[vf].pf_vlan) 7346 return -1; 7347 7348 /* VLAN 0 is a special case, don't allow it to be removed */ 7349 if (!vid && !add) 7350 return 0; 7351 7352 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7353 if (!ret) 7354 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7355 return ret; 7356 } 7357 7358 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7359 { 7360 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7361 7362 /* clear flags - except flag that indicates PF has set the MAC */ 7363 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7364 vf_data->last_nack = jiffies; 7365 7366 /* reset vlans for device */ 7367 igb_clear_vf_vfta(adapter, vf); 7368 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7369 igb_set_vmvir(adapter, vf_data->pf_vlan | 7370 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7371 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7372 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7373 7374 /* reset multicast table array for vf */ 7375 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7376 7377 /* Flush and reset the mta with the new values */ 7378 igb_set_rx_mode(adapter->netdev); 7379 } 7380 7381 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7382 { 7383 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7384 7385 /* clear mac address as we were hotplug removed/added */ 7386 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7387 eth_zero_addr(vf_mac); 7388 7389 /* process remaining reset events */ 7390 igb_vf_reset(adapter, vf); 7391 } 7392 7393 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7394 { 7395 struct e1000_hw *hw = &adapter->hw; 7396 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7397 u32 reg, msgbuf[3]; 7398 u8 *addr = (u8 *)(&msgbuf[1]); 7399 7400 /* process all the same items cleared in a function level reset */ 7401 igb_vf_reset(adapter, vf); 7402 7403 /* set vf mac address */ 7404 igb_set_vf_mac(adapter, vf, vf_mac); 7405 7406 /* enable transmit and receive for vf */ 7407 reg = rd32(E1000_VFTE); 7408 wr32(E1000_VFTE, reg | BIT(vf)); 7409 reg = rd32(E1000_VFRE); 7410 wr32(E1000_VFRE, reg | BIT(vf)); 7411 7412 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7413 7414 /* reply to reset with ack and vf mac address */ 7415 if (!is_zero_ether_addr(vf_mac)) { 7416 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7417 memcpy(addr, vf_mac, ETH_ALEN); 7418 } else { 7419 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7420 } 7421 igb_write_mbx(hw, msgbuf, 3, vf); 7422 } 7423 7424 static void igb_flush_mac_table(struct igb_adapter *adapter) 7425 { 7426 struct e1000_hw *hw = &adapter->hw; 7427 int i; 7428 7429 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7430 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7431 eth_zero_addr(adapter->mac_table[i].addr); 7432 adapter->mac_table[i].queue = 0; 7433 igb_rar_set_index(adapter, i); 7434 } 7435 } 7436 7437 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7438 { 7439 struct e1000_hw *hw = &adapter->hw; 7440 /* do not count rar entries reserved for VFs MAC addresses */ 7441 int rar_entries = hw->mac.rar_entry_count - 7442 adapter->vfs_allocated_count; 7443 int i, count = 0; 7444 7445 for (i = 0; i < rar_entries; i++) { 7446 /* do not count default entries */ 7447 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7448 continue; 7449 7450 /* do not count "in use" entries for different queues */ 7451 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7452 (adapter->mac_table[i].queue != queue)) 7453 continue; 7454 7455 count++; 7456 } 7457 7458 return count; 7459 } 7460 7461 /* Set default MAC address for the PF in the first RAR entry */ 7462 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7463 { 7464 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7465 7466 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7467 mac_table->queue = adapter->vfs_allocated_count; 7468 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7469 7470 igb_rar_set_index(adapter, 0); 7471 } 7472 7473 /* If the filter to be added and an already existing filter express 7474 * the same address and address type, it should be possible to only 7475 * override the other configurations, for example the queue to steer 7476 * traffic. 7477 */ 7478 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7479 const u8 *addr, const u8 flags) 7480 { 7481 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7482 return true; 7483 7484 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7485 (flags & IGB_MAC_STATE_SRC_ADDR)) 7486 return false; 7487 7488 if (!ether_addr_equal(addr, entry->addr)) 7489 return false; 7490 7491 return true; 7492 } 7493 7494 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7495 * 'flags' is used to indicate what kind of match is made, match is by 7496 * default for the destination address, if matching by source address 7497 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7498 */ 7499 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7500 const u8 *addr, const u8 queue, 7501 const u8 flags) 7502 { 7503 struct e1000_hw *hw = &adapter->hw; 7504 int rar_entries = hw->mac.rar_entry_count - 7505 adapter->vfs_allocated_count; 7506 int i; 7507 7508 if (is_zero_ether_addr(addr)) 7509 return -EINVAL; 7510 7511 /* Search for the first empty entry in the MAC table. 7512 * Do not touch entries at the end of the table reserved for the VF MAC 7513 * addresses. 7514 */ 7515 for (i = 0; i < rar_entries; i++) { 7516 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7517 addr, flags)) 7518 continue; 7519 7520 ether_addr_copy(adapter->mac_table[i].addr, addr); 7521 adapter->mac_table[i].queue = queue; 7522 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7523 7524 igb_rar_set_index(adapter, i); 7525 return i; 7526 } 7527 7528 return -ENOSPC; 7529 } 7530 7531 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7532 const u8 queue) 7533 { 7534 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7535 } 7536 7537 /* Remove a MAC filter for 'addr' directing matching traffic to 7538 * 'queue', 'flags' is used to indicate what kind of match need to be 7539 * removed, match is by default for the destination address, if 7540 * matching by source address is to be removed the flag 7541 * IGB_MAC_STATE_SRC_ADDR can be used. 7542 */ 7543 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7544 const u8 *addr, const u8 queue, 7545 const u8 flags) 7546 { 7547 struct e1000_hw *hw = &adapter->hw; 7548 int rar_entries = hw->mac.rar_entry_count - 7549 adapter->vfs_allocated_count; 7550 int i; 7551 7552 if (is_zero_ether_addr(addr)) 7553 return -EINVAL; 7554 7555 /* Search for matching entry in the MAC table based on given address 7556 * and queue. Do not touch entries at the end of the table reserved 7557 * for the VF MAC addresses. 7558 */ 7559 for (i = 0; i < rar_entries; i++) { 7560 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7561 continue; 7562 if ((adapter->mac_table[i].state & flags) != flags) 7563 continue; 7564 if (adapter->mac_table[i].queue != queue) 7565 continue; 7566 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7567 continue; 7568 7569 /* When a filter for the default address is "deleted", 7570 * we return it to its initial configuration 7571 */ 7572 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7573 adapter->mac_table[i].state = 7574 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7575 adapter->mac_table[i].queue = 7576 adapter->vfs_allocated_count; 7577 } else { 7578 adapter->mac_table[i].state = 0; 7579 adapter->mac_table[i].queue = 0; 7580 eth_zero_addr(adapter->mac_table[i].addr); 7581 } 7582 7583 igb_rar_set_index(adapter, i); 7584 return 0; 7585 } 7586 7587 return -ENOENT; 7588 } 7589 7590 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7591 const u8 queue) 7592 { 7593 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7594 } 7595 7596 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7597 const u8 *addr, u8 queue, u8 flags) 7598 { 7599 struct e1000_hw *hw = &adapter->hw; 7600 7601 /* In theory, this should be supported on 82575 as well, but 7602 * that part wasn't easily accessible during development. 7603 */ 7604 if (hw->mac.type != e1000_i210) 7605 return -EOPNOTSUPP; 7606 7607 return igb_add_mac_filter_flags(adapter, addr, queue, 7608 IGB_MAC_STATE_QUEUE_STEERING | flags); 7609 } 7610 7611 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7612 const u8 *addr, u8 queue, u8 flags) 7613 { 7614 return igb_del_mac_filter_flags(adapter, addr, queue, 7615 IGB_MAC_STATE_QUEUE_STEERING | flags); 7616 } 7617 7618 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7619 { 7620 struct igb_adapter *adapter = netdev_priv(netdev); 7621 int ret; 7622 7623 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7624 7625 return min_t(int, ret, 0); 7626 } 7627 7628 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7629 { 7630 struct igb_adapter *adapter = netdev_priv(netdev); 7631 7632 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7633 7634 return 0; 7635 } 7636 7637 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7638 const u32 info, const u8 *addr) 7639 { 7640 struct pci_dev *pdev = adapter->pdev; 7641 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7642 struct list_head *pos; 7643 struct vf_mac_filter *entry = NULL; 7644 int ret = 0; 7645 7646 switch (info) { 7647 case E1000_VF_MAC_FILTER_CLR: 7648 /* remove all unicast MAC filters related to the current VF */ 7649 list_for_each(pos, &adapter->vf_macs.l) { 7650 entry = list_entry(pos, struct vf_mac_filter, l); 7651 if (entry->vf == vf) { 7652 entry->vf = -1; 7653 entry->free = true; 7654 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7655 } 7656 } 7657 break; 7658 case E1000_VF_MAC_FILTER_ADD: 7659 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7660 !vf_data->trusted) { 7661 dev_warn(&pdev->dev, 7662 "VF %d requested MAC filter but is administratively denied\n", 7663 vf); 7664 return -EINVAL; 7665 } 7666 if (!is_valid_ether_addr(addr)) { 7667 dev_warn(&pdev->dev, 7668 "VF %d attempted to set invalid MAC filter\n", 7669 vf); 7670 return -EINVAL; 7671 } 7672 7673 /* try to find empty slot in the list */ 7674 list_for_each(pos, &adapter->vf_macs.l) { 7675 entry = list_entry(pos, struct vf_mac_filter, l); 7676 if (entry->free) 7677 break; 7678 } 7679 7680 if (entry && entry->free) { 7681 entry->free = false; 7682 entry->vf = vf; 7683 ether_addr_copy(entry->vf_mac, addr); 7684 7685 ret = igb_add_mac_filter(adapter, addr, vf); 7686 ret = min_t(int, ret, 0); 7687 } else { 7688 ret = -ENOSPC; 7689 } 7690 7691 if (ret == -ENOSPC) 7692 dev_warn(&pdev->dev, 7693 "VF %d has requested MAC filter but there is no space for it\n", 7694 vf); 7695 break; 7696 default: 7697 ret = -EINVAL; 7698 break; 7699 } 7700 7701 return ret; 7702 } 7703 7704 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7705 { 7706 struct pci_dev *pdev = adapter->pdev; 7707 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7708 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7709 7710 /* The VF MAC Address is stored in a packed array of bytes 7711 * starting at the second 32 bit word of the msg array 7712 */ 7713 unsigned char *addr = (unsigned char *)&msg[1]; 7714 int ret = 0; 7715 7716 if (!info) { 7717 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7718 !vf_data->trusted) { 7719 dev_warn(&pdev->dev, 7720 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 7721 vf); 7722 return -EINVAL; 7723 } 7724 7725 if (!is_valid_ether_addr(addr)) { 7726 dev_warn(&pdev->dev, 7727 "VF %d attempted to set invalid MAC\n", 7728 vf); 7729 return -EINVAL; 7730 } 7731 7732 ret = igb_set_vf_mac(adapter, vf, addr); 7733 } else { 7734 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 7735 } 7736 7737 return ret; 7738 } 7739 7740 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 7741 { 7742 struct e1000_hw *hw = &adapter->hw; 7743 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7744 u32 msg = E1000_VT_MSGTYPE_NACK; 7745 7746 /* if device isn't clear to send it shouldn't be reading either */ 7747 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 7748 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 7749 igb_write_mbx(hw, &msg, 1, vf); 7750 vf_data->last_nack = jiffies; 7751 } 7752 } 7753 7754 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 7755 { 7756 struct pci_dev *pdev = adapter->pdev; 7757 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 7758 struct e1000_hw *hw = &adapter->hw; 7759 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7760 s32 retval; 7761 7762 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 7763 7764 if (retval) { 7765 /* if receive failed revoke VF CTS stats and restart init */ 7766 dev_err(&pdev->dev, "Error receiving message from VF\n"); 7767 vf_data->flags &= ~IGB_VF_FLAG_CTS; 7768 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7769 goto unlock; 7770 goto out; 7771 } 7772 7773 /* this is a message we already processed, do nothing */ 7774 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 7775 goto unlock; 7776 7777 /* until the vf completes a reset it should not be 7778 * allowed to start any configuration. 7779 */ 7780 if (msgbuf[0] == E1000_VF_RESET) { 7781 /* unlocks mailbox */ 7782 igb_vf_reset_msg(adapter, vf); 7783 return; 7784 } 7785 7786 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 7787 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 7788 goto unlock; 7789 retval = -1; 7790 goto out; 7791 } 7792 7793 switch ((msgbuf[0] & 0xFFFF)) { 7794 case E1000_VF_SET_MAC_ADDR: 7795 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 7796 break; 7797 case E1000_VF_SET_PROMISC: 7798 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 7799 break; 7800 case E1000_VF_SET_MULTICAST: 7801 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 7802 break; 7803 case E1000_VF_SET_LPE: 7804 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 7805 break; 7806 case E1000_VF_SET_VLAN: 7807 retval = -1; 7808 if (vf_data->pf_vlan) 7809 dev_warn(&pdev->dev, 7810 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 7811 vf); 7812 else 7813 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 7814 break; 7815 default: 7816 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 7817 retval = -1; 7818 break; 7819 } 7820 7821 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 7822 out: 7823 /* notify the VF of the results of what it sent us */ 7824 if (retval) 7825 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 7826 else 7827 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 7828 7829 /* unlocks mailbox */ 7830 igb_write_mbx(hw, msgbuf, 1, vf); 7831 return; 7832 7833 unlock: 7834 igb_unlock_mbx(hw, vf); 7835 } 7836 7837 static void igb_msg_task(struct igb_adapter *adapter) 7838 { 7839 struct e1000_hw *hw = &adapter->hw; 7840 u32 vf; 7841 7842 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 7843 /* process any reset requests */ 7844 if (!igb_check_for_rst(hw, vf)) 7845 igb_vf_reset_event(adapter, vf); 7846 7847 /* process any messages pending */ 7848 if (!igb_check_for_msg(hw, vf)) 7849 igb_rcv_msg_from_vf(adapter, vf); 7850 7851 /* process any acks */ 7852 if (!igb_check_for_ack(hw, vf)) 7853 igb_rcv_ack_from_vf(adapter, vf); 7854 } 7855 } 7856 7857 /** 7858 * igb_set_uta - Set unicast filter table address 7859 * @adapter: board private structure 7860 * @set: boolean indicating if we are setting or clearing bits 7861 * 7862 * The unicast table address is a register array of 32-bit registers. 7863 * The table is meant to be used in a way similar to how the MTA is used 7864 * however due to certain limitations in the hardware it is necessary to 7865 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 7866 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 7867 **/ 7868 static void igb_set_uta(struct igb_adapter *adapter, bool set) 7869 { 7870 struct e1000_hw *hw = &adapter->hw; 7871 u32 uta = set ? ~0 : 0; 7872 int i; 7873 7874 /* we only need to do this if VMDq is enabled */ 7875 if (!adapter->vfs_allocated_count) 7876 return; 7877 7878 for (i = hw->mac.uta_reg_count; i--;) 7879 array_wr32(E1000_UTA, i, uta); 7880 } 7881 7882 /** 7883 * igb_intr_msi - Interrupt Handler 7884 * @irq: interrupt number 7885 * @data: pointer to a network interface device structure 7886 **/ 7887 static irqreturn_t igb_intr_msi(int irq, void *data) 7888 { 7889 struct igb_adapter *adapter = data; 7890 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7891 struct e1000_hw *hw = &adapter->hw; 7892 /* read ICR disables interrupts using IAM */ 7893 u32 icr = rd32(E1000_ICR); 7894 7895 igb_write_itr(q_vector); 7896 7897 if (icr & E1000_ICR_DRSTA) 7898 schedule_work(&adapter->reset_task); 7899 7900 if (icr & E1000_ICR_DOUTSYNC) { 7901 /* HW is reporting DMA is out of sync */ 7902 adapter->stats.doosync++; 7903 } 7904 7905 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7906 hw->mac.get_link_status = 1; 7907 if (!test_bit(__IGB_DOWN, &adapter->state)) 7908 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7909 } 7910 7911 if (icr & E1000_ICR_TS) 7912 igb_tsync_interrupt(adapter); 7913 7914 napi_schedule(&q_vector->napi); 7915 7916 return IRQ_HANDLED; 7917 } 7918 7919 /** 7920 * igb_intr - Legacy Interrupt Handler 7921 * @irq: interrupt number 7922 * @data: pointer to a network interface device structure 7923 **/ 7924 static irqreturn_t igb_intr(int irq, void *data) 7925 { 7926 struct igb_adapter *adapter = data; 7927 struct igb_q_vector *q_vector = adapter->q_vector[0]; 7928 struct e1000_hw *hw = &adapter->hw; 7929 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 7930 * need for the IMC write 7931 */ 7932 u32 icr = rd32(E1000_ICR); 7933 7934 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 7935 * not set, then the adapter didn't send an interrupt 7936 */ 7937 if (!(icr & E1000_ICR_INT_ASSERTED)) 7938 return IRQ_NONE; 7939 7940 igb_write_itr(q_vector); 7941 7942 if (icr & E1000_ICR_DRSTA) 7943 schedule_work(&adapter->reset_task); 7944 7945 if (icr & E1000_ICR_DOUTSYNC) { 7946 /* HW is reporting DMA is out of sync */ 7947 adapter->stats.doosync++; 7948 } 7949 7950 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 7951 hw->mac.get_link_status = 1; 7952 /* guard against interrupt when we're going down */ 7953 if (!test_bit(__IGB_DOWN, &adapter->state)) 7954 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7955 } 7956 7957 if (icr & E1000_ICR_TS) 7958 igb_tsync_interrupt(adapter); 7959 7960 napi_schedule(&q_vector->napi); 7961 7962 return IRQ_HANDLED; 7963 } 7964 7965 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 7966 { 7967 struct igb_adapter *adapter = q_vector->adapter; 7968 struct e1000_hw *hw = &adapter->hw; 7969 7970 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 7971 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 7972 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 7973 igb_set_itr(q_vector); 7974 else 7975 igb_update_ring_itr(q_vector); 7976 } 7977 7978 if (!test_bit(__IGB_DOWN, &adapter->state)) { 7979 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7980 wr32(E1000_EIMS, q_vector->eims_value); 7981 else 7982 igb_irq_enable(adapter); 7983 } 7984 } 7985 7986 /** 7987 * igb_poll - NAPI Rx polling callback 7988 * @napi: napi polling structure 7989 * @budget: count of how many packets we should handle 7990 **/ 7991 static int igb_poll(struct napi_struct *napi, int budget) 7992 { 7993 struct igb_q_vector *q_vector = container_of(napi, 7994 struct igb_q_vector, 7995 napi); 7996 bool clean_complete = true; 7997 int work_done = 0; 7998 7999 #ifdef CONFIG_IGB_DCA 8000 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8001 igb_update_dca(q_vector); 8002 #endif 8003 if (q_vector->tx.ring) 8004 clean_complete = igb_clean_tx_irq(q_vector, budget); 8005 8006 if (q_vector->rx.ring) { 8007 int cleaned = igb_clean_rx_irq(q_vector, budget); 8008 8009 work_done += cleaned; 8010 if (cleaned >= budget) 8011 clean_complete = false; 8012 } 8013 8014 /* If all work not completed, return budget and keep polling */ 8015 if (!clean_complete) 8016 return budget; 8017 8018 /* Exit the polling mode, but don't re-enable interrupts if stack might 8019 * poll us due to busy-polling 8020 */ 8021 if (likely(napi_complete_done(napi, work_done))) 8022 igb_ring_irq_enable(q_vector); 8023 8024 return min(work_done, budget - 1); 8025 } 8026 8027 /** 8028 * igb_clean_tx_irq - Reclaim resources after transmit completes 8029 * @q_vector: pointer to q_vector containing needed info 8030 * @napi_budget: Used to determine if we are in netpoll 8031 * 8032 * returns true if ring is completely cleaned 8033 **/ 8034 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8035 { 8036 struct igb_adapter *adapter = q_vector->adapter; 8037 struct igb_ring *tx_ring = q_vector->tx.ring; 8038 struct igb_tx_buffer *tx_buffer; 8039 union e1000_adv_tx_desc *tx_desc; 8040 unsigned int total_bytes = 0, total_packets = 0; 8041 unsigned int budget = q_vector->tx.work_limit; 8042 unsigned int i = tx_ring->next_to_clean; 8043 8044 if (test_bit(__IGB_DOWN, &adapter->state)) 8045 return true; 8046 8047 tx_buffer = &tx_ring->tx_buffer_info[i]; 8048 tx_desc = IGB_TX_DESC(tx_ring, i); 8049 i -= tx_ring->count; 8050 8051 do { 8052 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8053 8054 /* if next_to_watch is not set then there is no work pending */ 8055 if (!eop_desc) 8056 break; 8057 8058 /* prevent any other reads prior to eop_desc */ 8059 smp_rmb(); 8060 8061 /* if DD is not set pending work has not been completed */ 8062 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8063 break; 8064 8065 /* clear next_to_watch to prevent false hangs */ 8066 tx_buffer->next_to_watch = NULL; 8067 8068 /* update the statistics for this packet */ 8069 total_bytes += tx_buffer->bytecount; 8070 total_packets += tx_buffer->gso_segs; 8071 8072 /* free the skb */ 8073 if (tx_buffer->type == IGB_TYPE_SKB) 8074 napi_consume_skb(tx_buffer->skb, napi_budget); 8075 else 8076 xdp_return_frame(tx_buffer->xdpf); 8077 8078 /* unmap skb header data */ 8079 dma_unmap_single(tx_ring->dev, 8080 dma_unmap_addr(tx_buffer, dma), 8081 dma_unmap_len(tx_buffer, len), 8082 DMA_TO_DEVICE); 8083 8084 /* clear tx_buffer data */ 8085 dma_unmap_len_set(tx_buffer, len, 0); 8086 8087 /* clear last DMA location and unmap remaining buffers */ 8088 while (tx_desc != eop_desc) { 8089 tx_buffer++; 8090 tx_desc++; 8091 i++; 8092 if (unlikely(!i)) { 8093 i -= tx_ring->count; 8094 tx_buffer = tx_ring->tx_buffer_info; 8095 tx_desc = IGB_TX_DESC(tx_ring, 0); 8096 } 8097 8098 /* unmap any remaining paged data */ 8099 if (dma_unmap_len(tx_buffer, len)) { 8100 dma_unmap_page(tx_ring->dev, 8101 dma_unmap_addr(tx_buffer, dma), 8102 dma_unmap_len(tx_buffer, len), 8103 DMA_TO_DEVICE); 8104 dma_unmap_len_set(tx_buffer, len, 0); 8105 } 8106 } 8107 8108 /* move us one more past the eop_desc for start of next pkt */ 8109 tx_buffer++; 8110 tx_desc++; 8111 i++; 8112 if (unlikely(!i)) { 8113 i -= tx_ring->count; 8114 tx_buffer = tx_ring->tx_buffer_info; 8115 tx_desc = IGB_TX_DESC(tx_ring, 0); 8116 } 8117 8118 /* issue prefetch for next Tx descriptor */ 8119 prefetch(tx_desc); 8120 8121 /* update budget accounting */ 8122 budget--; 8123 } while (likely(budget)); 8124 8125 netdev_tx_completed_queue(txring_txq(tx_ring), 8126 total_packets, total_bytes); 8127 i += tx_ring->count; 8128 tx_ring->next_to_clean = i; 8129 u64_stats_update_begin(&tx_ring->tx_syncp); 8130 tx_ring->tx_stats.bytes += total_bytes; 8131 tx_ring->tx_stats.packets += total_packets; 8132 u64_stats_update_end(&tx_ring->tx_syncp); 8133 q_vector->tx.total_bytes += total_bytes; 8134 q_vector->tx.total_packets += total_packets; 8135 8136 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8137 struct e1000_hw *hw = &adapter->hw; 8138 8139 /* Detect a transmit hang in hardware, this serializes the 8140 * check with the clearing of time_stamp and movement of i 8141 */ 8142 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8143 if (tx_buffer->next_to_watch && 8144 time_after(jiffies, tx_buffer->time_stamp + 8145 (adapter->tx_timeout_factor * HZ)) && 8146 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8147 8148 /* detected Tx unit hang */ 8149 dev_err(tx_ring->dev, 8150 "Detected Tx Unit Hang\n" 8151 " Tx Queue <%d>\n" 8152 " TDH <%x>\n" 8153 " TDT <%x>\n" 8154 " next_to_use <%x>\n" 8155 " next_to_clean <%x>\n" 8156 "buffer_info[next_to_clean]\n" 8157 " time_stamp <%lx>\n" 8158 " next_to_watch <%p>\n" 8159 " jiffies <%lx>\n" 8160 " desc.status <%x>\n", 8161 tx_ring->queue_index, 8162 rd32(E1000_TDH(tx_ring->reg_idx)), 8163 readl(tx_ring->tail), 8164 tx_ring->next_to_use, 8165 tx_ring->next_to_clean, 8166 tx_buffer->time_stamp, 8167 tx_buffer->next_to_watch, 8168 jiffies, 8169 tx_buffer->next_to_watch->wb.status); 8170 netif_stop_subqueue(tx_ring->netdev, 8171 tx_ring->queue_index); 8172 8173 /* we are about to reset, no point in enabling stuff */ 8174 return true; 8175 } 8176 } 8177 8178 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8179 if (unlikely(total_packets && 8180 netif_carrier_ok(tx_ring->netdev) && 8181 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8182 /* Make sure that anybody stopping the queue after this 8183 * sees the new next_to_clean. 8184 */ 8185 smp_mb(); 8186 if (__netif_subqueue_stopped(tx_ring->netdev, 8187 tx_ring->queue_index) && 8188 !(test_bit(__IGB_DOWN, &adapter->state))) { 8189 netif_wake_subqueue(tx_ring->netdev, 8190 tx_ring->queue_index); 8191 8192 u64_stats_update_begin(&tx_ring->tx_syncp); 8193 tx_ring->tx_stats.restart_queue++; 8194 u64_stats_update_end(&tx_ring->tx_syncp); 8195 } 8196 } 8197 8198 return !!budget; 8199 } 8200 8201 /** 8202 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8203 * @rx_ring: rx descriptor ring to store buffers on 8204 * @old_buff: donor buffer to have page reused 8205 * 8206 * Synchronizes page for reuse by the adapter 8207 **/ 8208 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8209 struct igb_rx_buffer *old_buff) 8210 { 8211 struct igb_rx_buffer *new_buff; 8212 u16 nta = rx_ring->next_to_alloc; 8213 8214 new_buff = &rx_ring->rx_buffer_info[nta]; 8215 8216 /* update, and store next to alloc */ 8217 nta++; 8218 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8219 8220 /* Transfer page from old buffer to new buffer. 8221 * Move each member individually to avoid possible store 8222 * forwarding stalls. 8223 */ 8224 new_buff->dma = old_buff->dma; 8225 new_buff->page = old_buff->page; 8226 new_buff->page_offset = old_buff->page_offset; 8227 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8228 } 8229 8230 static inline bool igb_page_is_reserved(struct page *page) 8231 { 8232 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 8233 } 8234 8235 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer) 8236 { 8237 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8238 struct page *page = rx_buffer->page; 8239 8240 /* avoid re-using remote pages */ 8241 if (unlikely(igb_page_is_reserved(page))) 8242 return false; 8243 8244 #if (PAGE_SIZE < 8192) 8245 /* if we are only owner of page we can reuse it */ 8246 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 8247 return false; 8248 #else 8249 #define IGB_LAST_OFFSET \ 8250 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8251 8252 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8253 return false; 8254 #endif 8255 8256 /* If we have drained the page fragment pool we need to update 8257 * the pagecnt_bias and page count so that we fully restock the 8258 * number of references the driver holds. 8259 */ 8260 if (unlikely(pagecnt_bias == 1)) { 8261 page_ref_add(page, USHRT_MAX - 1); 8262 rx_buffer->pagecnt_bias = USHRT_MAX; 8263 } 8264 8265 return true; 8266 } 8267 8268 /** 8269 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8270 * @rx_ring: rx descriptor ring to transact packets on 8271 * @rx_buffer: buffer containing page to add 8272 * @skb: sk_buff to place the data into 8273 * @size: size of buffer to be added 8274 * 8275 * This function will add the data contained in rx_buffer->page to the skb. 8276 **/ 8277 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8278 struct igb_rx_buffer *rx_buffer, 8279 struct sk_buff *skb, 8280 unsigned int size) 8281 { 8282 #if (PAGE_SIZE < 8192) 8283 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8284 #else 8285 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8286 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8287 SKB_DATA_ALIGN(size); 8288 #endif 8289 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8290 rx_buffer->page_offset, size, truesize); 8291 #if (PAGE_SIZE < 8192) 8292 rx_buffer->page_offset ^= truesize; 8293 #else 8294 rx_buffer->page_offset += truesize; 8295 #endif 8296 } 8297 8298 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8299 struct igb_rx_buffer *rx_buffer, 8300 struct xdp_buff *xdp, 8301 union e1000_adv_rx_desc *rx_desc) 8302 { 8303 #if (PAGE_SIZE < 8192) 8304 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8305 #else 8306 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8307 xdp->data_hard_start); 8308 #endif 8309 unsigned int size = xdp->data_end - xdp->data; 8310 unsigned int headlen; 8311 struct sk_buff *skb; 8312 8313 /* prefetch first cache line of first page */ 8314 net_prefetch(xdp->data); 8315 8316 /* allocate a skb to store the frags */ 8317 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8318 if (unlikely(!skb)) 8319 return NULL; 8320 8321 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) { 8322 igb_ptp_rx_pktstamp(rx_ring->q_vector, xdp->data, skb); 8323 xdp->data += IGB_TS_HDR_LEN; 8324 size -= IGB_TS_HDR_LEN; 8325 } 8326 8327 /* Determine available headroom for copy */ 8328 headlen = size; 8329 if (headlen > IGB_RX_HDR_LEN) 8330 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8331 8332 /* align pull length to size of long to optimize memcpy performance */ 8333 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8334 8335 /* update all of the pointers */ 8336 size -= headlen; 8337 if (size) { 8338 skb_add_rx_frag(skb, 0, rx_buffer->page, 8339 (xdp->data + headlen) - page_address(rx_buffer->page), 8340 size, truesize); 8341 #if (PAGE_SIZE < 8192) 8342 rx_buffer->page_offset ^= truesize; 8343 #else 8344 rx_buffer->page_offset += truesize; 8345 #endif 8346 } else { 8347 rx_buffer->pagecnt_bias++; 8348 } 8349 8350 return skb; 8351 } 8352 8353 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8354 struct igb_rx_buffer *rx_buffer, 8355 struct xdp_buff *xdp, 8356 union e1000_adv_rx_desc *rx_desc) 8357 { 8358 #if (PAGE_SIZE < 8192) 8359 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8360 #else 8361 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8362 SKB_DATA_ALIGN(xdp->data_end - 8363 xdp->data_hard_start); 8364 #endif 8365 unsigned int metasize = xdp->data - xdp->data_meta; 8366 struct sk_buff *skb; 8367 8368 /* prefetch first cache line of first page */ 8369 net_prefetch(xdp->data_meta); 8370 8371 /* build an skb around the page buffer */ 8372 skb = build_skb(xdp->data_hard_start, truesize); 8373 if (unlikely(!skb)) 8374 return NULL; 8375 8376 /* update pointers within the skb to store the data */ 8377 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8378 __skb_put(skb, xdp->data_end - xdp->data); 8379 8380 if (metasize) 8381 skb_metadata_set(skb, metasize); 8382 8383 /* pull timestamp out of packet data */ 8384 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 8385 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb); 8386 __skb_pull(skb, IGB_TS_HDR_LEN); 8387 } 8388 8389 /* update buffer offset */ 8390 #if (PAGE_SIZE < 8192) 8391 rx_buffer->page_offset ^= truesize; 8392 #else 8393 rx_buffer->page_offset += truesize; 8394 #endif 8395 8396 return skb; 8397 } 8398 8399 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter, 8400 struct igb_ring *rx_ring, 8401 struct xdp_buff *xdp) 8402 { 8403 int err, result = IGB_XDP_PASS; 8404 struct bpf_prog *xdp_prog; 8405 u32 act; 8406 8407 rcu_read_lock(); 8408 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8409 8410 if (!xdp_prog) 8411 goto xdp_out; 8412 8413 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8414 8415 act = bpf_prog_run_xdp(xdp_prog, xdp); 8416 switch (act) { 8417 case XDP_PASS: 8418 break; 8419 case XDP_TX: 8420 result = igb_xdp_xmit_back(adapter, xdp); 8421 break; 8422 case XDP_REDIRECT: 8423 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8424 if (!err) 8425 result = IGB_XDP_REDIR; 8426 else 8427 result = IGB_XDP_CONSUMED; 8428 break; 8429 default: 8430 bpf_warn_invalid_xdp_action(act); 8431 fallthrough; 8432 case XDP_ABORTED: 8433 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8434 fallthrough; 8435 case XDP_DROP: 8436 result = IGB_XDP_CONSUMED; 8437 break; 8438 } 8439 xdp_out: 8440 rcu_read_unlock(); 8441 return ERR_PTR(-result); 8442 } 8443 8444 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8445 unsigned int size) 8446 { 8447 unsigned int truesize; 8448 8449 #if (PAGE_SIZE < 8192) 8450 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8451 #else 8452 truesize = ring_uses_build_skb(rx_ring) ? 8453 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8454 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8455 SKB_DATA_ALIGN(size); 8456 #endif 8457 return truesize; 8458 } 8459 8460 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8461 struct igb_rx_buffer *rx_buffer, 8462 unsigned int size) 8463 { 8464 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8465 #if (PAGE_SIZE < 8192) 8466 rx_buffer->page_offset ^= truesize; 8467 #else 8468 rx_buffer->page_offset += truesize; 8469 #endif 8470 } 8471 8472 static inline void igb_rx_checksum(struct igb_ring *ring, 8473 union e1000_adv_rx_desc *rx_desc, 8474 struct sk_buff *skb) 8475 { 8476 skb_checksum_none_assert(skb); 8477 8478 /* Ignore Checksum bit is set */ 8479 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8480 return; 8481 8482 /* Rx checksum disabled via ethtool */ 8483 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8484 return; 8485 8486 /* TCP/UDP checksum error bit is set */ 8487 if (igb_test_staterr(rx_desc, 8488 E1000_RXDEXT_STATERR_TCPE | 8489 E1000_RXDEXT_STATERR_IPE)) { 8490 /* work around errata with sctp packets where the TCPE aka 8491 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8492 * packets, (aka let the stack check the crc32c) 8493 */ 8494 if (!((skb->len == 60) && 8495 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8496 u64_stats_update_begin(&ring->rx_syncp); 8497 ring->rx_stats.csum_err++; 8498 u64_stats_update_end(&ring->rx_syncp); 8499 } 8500 /* let the stack verify checksum errors */ 8501 return; 8502 } 8503 /* It must be a TCP or UDP packet with a valid checksum */ 8504 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8505 E1000_RXD_STAT_UDPCS)) 8506 skb->ip_summed = CHECKSUM_UNNECESSARY; 8507 8508 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8509 le32_to_cpu(rx_desc->wb.upper.status_error)); 8510 } 8511 8512 static inline void igb_rx_hash(struct igb_ring *ring, 8513 union e1000_adv_rx_desc *rx_desc, 8514 struct sk_buff *skb) 8515 { 8516 if (ring->netdev->features & NETIF_F_RXHASH) 8517 skb_set_hash(skb, 8518 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8519 PKT_HASH_TYPE_L3); 8520 } 8521 8522 /** 8523 * igb_is_non_eop - process handling of non-EOP buffers 8524 * @rx_ring: Rx ring being processed 8525 * @rx_desc: Rx descriptor for current buffer 8526 * 8527 * This function updates next to clean. If the buffer is an EOP buffer 8528 * this function exits returning false, otherwise it will place the 8529 * sk_buff in the next buffer to be chained and return true indicating 8530 * that this is in fact a non-EOP buffer. 8531 **/ 8532 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8533 union e1000_adv_rx_desc *rx_desc) 8534 { 8535 u32 ntc = rx_ring->next_to_clean + 1; 8536 8537 /* fetch, update, and store next to clean */ 8538 ntc = (ntc < rx_ring->count) ? ntc : 0; 8539 rx_ring->next_to_clean = ntc; 8540 8541 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8542 8543 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8544 return false; 8545 8546 return true; 8547 } 8548 8549 /** 8550 * igb_cleanup_headers - Correct corrupted or empty headers 8551 * @rx_ring: rx descriptor ring packet is being transacted on 8552 * @rx_desc: pointer to the EOP Rx descriptor 8553 * @skb: pointer to current skb being fixed 8554 * 8555 * Address the case where we are pulling data in on pages only 8556 * and as such no data is present in the skb header. 8557 * 8558 * In addition if skb is not at least 60 bytes we need to pad it so that 8559 * it is large enough to qualify as a valid Ethernet frame. 8560 * 8561 * Returns true if an error was encountered and skb was freed. 8562 **/ 8563 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8564 union e1000_adv_rx_desc *rx_desc, 8565 struct sk_buff *skb) 8566 { 8567 /* XDP packets use error pointer so abort at this point */ 8568 if (IS_ERR(skb)) 8569 return true; 8570 8571 if (unlikely((igb_test_staterr(rx_desc, 8572 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8573 struct net_device *netdev = rx_ring->netdev; 8574 if (!(netdev->features & NETIF_F_RXALL)) { 8575 dev_kfree_skb_any(skb); 8576 return true; 8577 } 8578 } 8579 8580 /* if eth_skb_pad returns an error the skb was freed */ 8581 if (eth_skb_pad(skb)) 8582 return true; 8583 8584 return false; 8585 } 8586 8587 /** 8588 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8589 * @rx_ring: rx descriptor ring packet is being transacted on 8590 * @rx_desc: pointer to the EOP Rx descriptor 8591 * @skb: pointer to current skb being populated 8592 * 8593 * This function checks the ring, descriptor, and packet information in 8594 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8595 * other fields within the skb. 8596 **/ 8597 static void igb_process_skb_fields(struct igb_ring *rx_ring, 8598 union e1000_adv_rx_desc *rx_desc, 8599 struct sk_buff *skb) 8600 { 8601 struct net_device *dev = rx_ring->netdev; 8602 8603 igb_rx_hash(rx_ring, rx_desc, skb); 8604 8605 igb_rx_checksum(rx_ring, rx_desc, skb); 8606 8607 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8608 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8609 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8610 8611 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8612 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8613 u16 vid; 8614 8615 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8616 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8617 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 8618 else 8619 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8620 8621 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8622 } 8623 8624 skb_record_rx_queue(skb, rx_ring->queue_index); 8625 8626 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8627 } 8628 8629 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8630 { 8631 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8632 } 8633 8634 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8635 const unsigned int size) 8636 { 8637 struct igb_rx_buffer *rx_buffer; 8638 8639 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8640 prefetchw(rx_buffer->page); 8641 8642 /* we are reusing so sync this buffer for CPU use */ 8643 dma_sync_single_range_for_cpu(rx_ring->dev, 8644 rx_buffer->dma, 8645 rx_buffer->page_offset, 8646 size, 8647 DMA_FROM_DEVICE); 8648 8649 rx_buffer->pagecnt_bias--; 8650 8651 return rx_buffer; 8652 } 8653 8654 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8655 struct igb_rx_buffer *rx_buffer) 8656 { 8657 if (igb_can_reuse_rx_page(rx_buffer)) { 8658 /* hand second half of page back to the ring */ 8659 igb_reuse_rx_page(rx_ring, rx_buffer); 8660 } else { 8661 /* We are not reusing the buffer so unmap it and free 8662 * any references we are holding to it 8663 */ 8664 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8665 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8666 IGB_RX_DMA_ATTR); 8667 __page_frag_cache_drain(rx_buffer->page, 8668 rx_buffer->pagecnt_bias); 8669 } 8670 8671 /* clear contents of rx_buffer */ 8672 rx_buffer->page = NULL; 8673 } 8674 8675 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 8676 { 8677 struct igb_adapter *adapter = q_vector->adapter; 8678 struct igb_ring *rx_ring = q_vector->rx.ring; 8679 struct sk_buff *skb = rx_ring->skb; 8680 unsigned int total_bytes = 0, total_packets = 0; 8681 u16 cleaned_count = igb_desc_unused(rx_ring); 8682 unsigned int xdp_xmit = 0; 8683 struct xdp_buff xdp; 8684 8685 xdp.rxq = &rx_ring->xdp_rxq; 8686 8687 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 8688 #if (PAGE_SIZE < 8192) 8689 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, 0); 8690 #endif 8691 8692 while (likely(total_packets < budget)) { 8693 union e1000_adv_rx_desc *rx_desc; 8694 struct igb_rx_buffer *rx_buffer; 8695 unsigned int size; 8696 8697 /* return some buffers to hardware, one at a time is too slow */ 8698 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 8699 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8700 cleaned_count = 0; 8701 } 8702 8703 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 8704 size = le16_to_cpu(rx_desc->wb.upper.length); 8705 if (!size) 8706 break; 8707 8708 /* This memory barrier is needed to keep us from reading 8709 * any other fields out of the rx_desc until we know the 8710 * descriptor has been written back 8711 */ 8712 dma_rmb(); 8713 8714 rx_buffer = igb_get_rx_buffer(rx_ring, size); 8715 8716 /* retrieve a buffer from the ring */ 8717 if (!skb) { 8718 xdp.data = page_address(rx_buffer->page) + 8719 rx_buffer->page_offset; 8720 xdp.data_meta = xdp.data; 8721 xdp.data_hard_start = xdp.data - 8722 igb_rx_offset(rx_ring); 8723 xdp.data_end = xdp.data + size; 8724 #if (PAGE_SIZE > 4096) 8725 /* At larger PAGE_SIZE, frame_sz depend on len size */ 8726 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 8727 #endif 8728 skb = igb_run_xdp(adapter, rx_ring, &xdp); 8729 } 8730 8731 if (IS_ERR(skb)) { 8732 unsigned int xdp_res = -PTR_ERR(skb); 8733 8734 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 8735 xdp_xmit |= xdp_res; 8736 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 8737 } else { 8738 rx_buffer->pagecnt_bias++; 8739 } 8740 total_packets++; 8741 total_bytes += size; 8742 } else if (skb) 8743 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 8744 else if (ring_uses_build_skb(rx_ring)) 8745 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, rx_desc); 8746 else 8747 skb = igb_construct_skb(rx_ring, rx_buffer, 8748 &xdp, rx_desc); 8749 8750 /* exit if we failed to retrieve a buffer */ 8751 if (!skb) { 8752 rx_ring->rx_stats.alloc_failed++; 8753 rx_buffer->pagecnt_bias++; 8754 break; 8755 } 8756 8757 igb_put_rx_buffer(rx_ring, rx_buffer); 8758 cleaned_count++; 8759 8760 /* fetch next buffer in frame if non-eop */ 8761 if (igb_is_non_eop(rx_ring, rx_desc)) 8762 continue; 8763 8764 /* verify the packet layout is correct */ 8765 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 8766 skb = NULL; 8767 continue; 8768 } 8769 8770 /* probably a little skewed due to removing CRC */ 8771 total_bytes += skb->len; 8772 8773 /* populate checksum, timestamp, VLAN, and protocol */ 8774 igb_process_skb_fields(rx_ring, rx_desc, skb); 8775 8776 napi_gro_receive(&q_vector->napi, skb); 8777 8778 /* reset skb pointer */ 8779 skb = NULL; 8780 8781 /* update budget accounting */ 8782 total_packets++; 8783 } 8784 8785 /* place incomplete frames back on ring for completion */ 8786 rx_ring->skb = skb; 8787 8788 if (xdp_xmit & IGB_XDP_REDIR) 8789 xdp_do_flush(); 8790 8791 if (xdp_xmit & IGB_XDP_TX) { 8792 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8793 8794 igb_xdp_ring_update_tail(tx_ring); 8795 } 8796 8797 u64_stats_update_begin(&rx_ring->rx_syncp); 8798 rx_ring->rx_stats.packets += total_packets; 8799 rx_ring->rx_stats.bytes += total_bytes; 8800 u64_stats_update_end(&rx_ring->rx_syncp); 8801 q_vector->rx.total_packets += total_packets; 8802 q_vector->rx.total_bytes += total_bytes; 8803 8804 if (cleaned_count) 8805 igb_alloc_rx_buffers(rx_ring, cleaned_count); 8806 8807 return total_packets; 8808 } 8809 8810 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 8811 struct igb_rx_buffer *bi) 8812 { 8813 struct page *page = bi->page; 8814 dma_addr_t dma; 8815 8816 /* since we are recycling buffers we should seldom need to alloc */ 8817 if (likely(page)) 8818 return true; 8819 8820 /* alloc new page for storage */ 8821 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 8822 if (unlikely(!page)) { 8823 rx_ring->rx_stats.alloc_failed++; 8824 return false; 8825 } 8826 8827 /* map page for use */ 8828 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 8829 igb_rx_pg_size(rx_ring), 8830 DMA_FROM_DEVICE, 8831 IGB_RX_DMA_ATTR); 8832 8833 /* if mapping failed free memory back to system since 8834 * there isn't much point in holding memory we can't use 8835 */ 8836 if (dma_mapping_error(rx_ring->dev, dma)) { 8837 __free_pages(page, igb_rx_pg_order(rx_ring)); 8838 8839 rx_ring->rx_stats.alloc_failed++; 8840 return false; 8841 } 8842 8843 bi->dma = dma; 8844 bi->page = page; 8845 bi->page_offset = igb_rx_offset(rx_ring); 8846 page_ref_add(page, USHRT_MAX - 1); 8847 bi->pagecnt_bias = USHRT_MAX; 8848 8849 return true; 8850 } 8851 8852 /** 8853 * igb_alloc_rx_buffers - Replace used receive buffers 8854 * @rx_ring: rx descriptor ring to allocate new receive buffers 8855 * @cleaned_count: count of buffers to allocate 8856 **/ 8857 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 8858 { 8859 union e1000_adv_rx_desc *rx_desc; 8860 struct igb_rx_buffer *bi; 8861 u16 i = rx_ring->next_to_use; 8862 u16 bufsz; 8863 8864 /* nothing to do */ 8865 if (!cleaned_count) 8866 return; 8867 8868 rx_desc = IGB_RX_DESC(rx_ring, i); 8869 bi = &rx_ring->rx_buffer_info[i]; 8870 i -= rx_ring->count; 8871 8872 bufsz = igb_rx_bufsz(rx_ring); 8873 8874 do { 8875 if (!igb_alloc_mapped_page(rx_ring, bi)) 8876 break; 8877 8878 /* sync the buffer for use by the device */ 8879 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 8880 bi->page_offset, bufsz, 8881 DMA_FROM_DEVICE); 8882 8883 /* Refresh the desc even if buffer_addrs didn't change 8884 * because each write-back erases this info. 8885 */ 8886 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 8887 8888 rx_desc++; 8889 bi++; 8890 i++; 8891 if (unlikely(!i)) { 8892 rx_desc = IGB_RX_DESC(rx_ring, 0); 8893 bi = rx_ring->rx_buffer_info; 8894 i -= rx_ring->count; 8895 } 8896 8897 /* clear the length for the next_to_use descriptor */ 8898 rx_desc->wb.upper.length = 0; 8899 8900 cleaned_count--; 8901 } while (cleaned_count); 8902 8903 i += rx_ring->count; 8904 8905 if (rx_ring->next_to_use != i) { 8906 /* record the next descriptor to use */ 8907 rx_ring->next_to_use = i; 8908 8909 /* update next to alloc since we have filled the ring */ 8910 rx_ring->next_to_alloc = i; 8911 8912 /* Force memory writes to complete before letting h/w 8913 * know there are new descriptors to fetch. (Only 8914 * applicable for weak-ordered memory model archs, 8915 * such as IA-64). 8916 */ 8917 dma_wmb(); 8918 writel(i, rx_ring->tail); 8919 } 8920 } 8921 8922 /** 8923 * igb_mii_ioctl - 8924 * @netdev: pointer to netdev struct 8925 * @ifr: interface structure 8926 * @cmd: ioctl command to execute 8927 **/ 8928 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8929 { 8930 struct igb_adapter *adapter = netdev_priv(netdev); 8931 struct mii_ioctl_data *data = if_mii(ifr); 8932 8933 if (adapter->hw.phy.media_type != e1000_media_type_copper) 8934 return -EOPNOTSUPP; 8935 8936 switch (cmd) { 8937 case SIOCGMIIPHY: 8938 data->phy_id = adapter->hw.phy.addr; 8939 break; 8940 case SIOCGMIIREG: 8941 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 8942 &data->val_out)) 8943 return -EIO; 8944 break; 8945 case SIOCSMIIREG: 8946 default: 8947 return -EOPNOTSUPP; 8948 } 8949 return 0; 8950 } 8951 8952 /** 8953 * igb_ioctl - 8954 * @netdev: pointer to netdev struct 8955 * @ifr: interface structure 8956 * @cmd: ioctl command to execute 8957 **/ 8958 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 8959 { 8960 switch (cmd) { 8961 case SIOCGMIIPHY: 8962 case SIOCGMIIREG: 8963 case SIOCSMIIREG: 8964 return igb_mii_ioctl(netdev, ifr, cmd); 8965 case SIOCGHWTSTAMP: 8966 return igb_ptp_get_ts_config(netdev, ifr); 8967 case SIOCSHWTSTAMP: 8968 return igb_ptp_set_ts_config(netdev, ifr); 8969 default: 8970 return -EOPNOTSUPP; 8971 } 8972 } 8973 8974 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8975 { 8976 struct igb_adapter *adapter = hw->back; 8977 8978 pci_read_config_word(adapter->pdev, reg, value); 8979 } 8980 8981 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 8982 { 8983 struct igb_adapter *adapter = hw->back; 8984 8985 pci_write_config_word(adapter->pdev, reg, *value); 8986 } 8987 8988 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8989 { 8990 struct igb_adapter *adapter = hw->back; 8991 8992 if (pcie_capability_read_word(adapter->pdev, reg, value)) 8993 return -E1000_ERR_CONFIG; 8994 8995 return 0; 8996 } 8997 8998 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 8999 { 9000 struct igb_adapter *adapter = hw->back; 9001 9002 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9003 return -E1000_ERR_CONFIG; 9004 9005 return 0; 9006 } 9007 9008 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9009 { 9010 struct igb_adapter *adapter = netdev_priv(netdev); 9011 struct e1000_hw *hw = &adapter->hw; 9012 u32 ctrl, rctl; 9013 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9014 9015 if (enable) { 9016 /* enable VLAN tag insert/strip */ 9017 ctrl = rd32(E1000_CTRL); 9018 ctrl |= E1000_CTRL_VME; 9019 wr32(E1000_CTRL, ctrl); 9020 9021 /* Disable CFI check */ 9022 rctl = rd32(E1000_RCTL); 9023 rctl &= ~E1000_RCTL_CFIEN; 9024 wr32(E1000_RCTL, rctl); 9025 } else { 9026 /* disable VLAN tag insert/strip */ 9027 ctrl = rd32(E1000_CTRL); 9028 ctrl &= ~E1000_CTRL_VME; 9029 wr32(E1000_CTRL, ctrl); 9030 } 9031 9032 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9033 } 9034 9035 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9036 __be16 proto, u16 vid) 9037 { 9038 struct igb_adapter *adapter = netdev_priv(netdev); 9039 struct e1000_hw *hw = &adapter->hw; 9040 int pf_id = adapter->vfs_allocated_count; 9041 9042 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9043 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9044 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9045 9046 set_bit(vid, adapter->active_vlans); 9047 9048 return 0; 9049 } 9050 9051 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9052 __be16 proto, u16 vid) 9053 { 9054 struct igb_adapter *adapter = netdev_priv(netdev); 9055 int pf_id = adapter->vfs_allocated_count; 9056 struct e1000_hw *hw = &adapter->hw; 9057 9058 /* remove VID from filter table */ 9059 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9060 igb_vfta_set(hw, vid, pf_id, false, true); 9061 9062 clear_bit(vid, adapter->active_vlans); 9063 9064 return 0; 9065 } 9066 9067 static void igb_restore_vlan(struct igb_adapter *adapter) 9068 { 9069 u16 vid = 1; 9070 9071 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9072 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9073 9074 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9075 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9076 } 9077 9078 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9079 { 9080 struct pci_dev *pdev = adapter->pdev; 9081 struct e1000_mac_info *mac = &adapter->hw.mac; 9082 9083 mac->autoneg = 0; 9084 9085 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9086 * for the switch() below to work 9087 */ 9088 if ((spd & 1) || (dplx & ~1)) 9089 goto err_inval; 9090 9091 /* Fiber NIC's only allow 1000 gbps Full duplex 9092 * and 100Mbps Full duplex for 100baseFx sfp 9093 */ 9094 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9095 switch (spd + dplx) { 9096 case SPEED_10 + DUPLEX_HALF: 9097 case SPEED_10 + DUPLEX_FULL: 9098 case SPEED_100 + DUPLEX_HALF: 9099 goto err_inval; 9100 default: 9101 break; 9102 } 9103 } 9104 9105 switch (spd + dplx) { 9106 case SPEED_10 + DUPLEX_HALF: 9107 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9108 break; 9109 case SPEED_10 + DUPLEX_FULL: 9110 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9111 break; 9112 case SPEED_100 + DUPLEX_HALF: 9113 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9114 break; 9115 case SPEED_100 + DUPLEX_FULL: 9116 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9117 break; 9118 case SPEED_1000 + DUPLEX_FULL: 9119 mac->autoneg = 1; 9120 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9121 break; 9122 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9123 default: 9124 goto err_inval; 9125 } 9126 9127 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9128 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9129 9130 return 0; 9131 9132 err_inval: 9133 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9134 return -EINVAL; 9135 } 9136 9137 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9138 bool runtime) 9139 { 9140 struct net_device *netdev = pci_get_drvdata(pdev); 9141 struct igb_adapter *adapter = netdev_priv(netdev); 9142 struct e1000_hw *hw = &adapter->hw; 9143 u32 ctrl, rctl, status; 9144 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9145 bool wake; 9146 9147 rtnl_lock(); 9148 netif_device_detach(netdev); 9149 9150 if (netif_running(netdev)) 9151 __igb_close(netdev, true); 9152 9153 igb_ptp_suspend(adapter); 9154 9155 igb_clear_interrupt_scheme(adapter); 9156 rtnl_unlock(); 9157 9158 status = rd32(E1000_STATUS); 9159 if (status & E1000_STATUS_LU) 9160 wufc &= ~E1000_WUFC_LNKC; 9161 9162 if (wufc) { 9163 igb_setup_rctl(adapter); 9164 igb_set_rx_mode(netdev); 9165 9166 /* turn on all-multi mode if wake on multicast is enabled */ 9167 if (wufc & E1000_WUFC_MC) { 9168 rctl = rd32(E1000_RCTL); 9169 rctl |= E1000_RCTL_MPE; 9170 wr32(E1000_RCTL, rctl); 9171 } 9172 9173 ctrl = rd32(E1000_CTRL); 9174 ctrl |= E1000_CTRL_ADVD3WUC; 9175 wr32(E1000_CTRL, ctrl); 9176 9177 /* Allow time for pending master requests to run */ 9178 igb_disable_pcie_master(hw); 9179 9180 wr32(E1000_WUC, E1000_WUC_PME_EN); 9181 wr32(E1000_WUFC, wufc); 9182 } else { 9183 wr32(E1000_WUC, 0); 9184 wr32(E1000_WUFC, 0); 9185 } 9186 9187 wake = wufc || adapter->en_mng_pt; 9188 if (!wake) 9189 igb_power_down_link(adapter); 9190 else 9191 igb_power_up_link(adapter); 9192 9193 if (enable_wake) 9194 *enable_wake = wake; 9195 9196 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9197 * would have already happened in close and is redundant. 9198 */ 9199 igb_release_hw_control(adapter); 9200 9201 pci_disable_device(pdev); 9202 9203 return 0; 9204 } 9205 9206 static void igb_deliver_wake_packet(struct net_device *netdev) 9207 { 9208 struct igb_adapter *adapter = netdev_priv(netdev); 9209 struct e1000_hw *hw = &adapter->hw; 9210 struct sk_buff *skb; 9211 u32 wupl; 9212 9213 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9214 9215 /* WUPM stores only the first 128 bytes of the wake packet. 9216 * Read the packet only if we have the whole thing. 9217 */ 9218 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9219 return; 9220 9221 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9222 if (!skb) 9223 return; 9224 9225 skb_put(skb, wupl); 9226 9227 /* Ensure reads are 32-bit aligned */ 9228 wupl = roundup(wupl, 4); 9229 9230 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9231 9232 skb->protocol = eth_type_trans(skb, netdev); 9233 netif_rx(skb); 9234 } 9235 9236 static int __maybe_unused igb_suspend(struct device *dev) 9237 { 9238 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9239 } 9240 9241 static int __maybe_unused igb_resume(struct device *dev) 9242 { 9243 struct pci_dev *pdev = to_pci_dev(dev); 9244 struct net_device *netdev = pci_get_drvdata(pdev); 9245 struct igb_adapter *adapter = netdev_priv(netdev); 9246 struct e1000_hw *hw = &adapter->hw; 9247 u32 err, val; 9248 9249 pci_set_power_state(pdev, PCI_D0); 9250 pci_restore_state(pdev); 9251 pci_save_state(pdev); 9252 9253 if (!pci_device_is_present(pdev)) 9254 return -ENODEV; 9255 err = pci_enable_device_mem(pdev); 9256 if (err) { 9257 dev_err(&pdev->dev, 9258 "igb: Cannot enable PCI device from suspend\n"); 9259 return err; 9260 } 9261 pci_set_master(pdev); 9262 9263 pci_enable_wake(pdev, PCI_D3hot, 0); 9264 pci_enable_wake(pdev, PCI_D3cold, 0); 9265 9266 if (igb_init_interrupt_scheme(adapter, true)) { 9267 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9268 return -ENOMEM; 9269 } 9270 9271 igb_reset(adapter); 9272 9273 /* let the f/w know that the h/w is now under the control of the 9274 * driver. 9275 */ 9276 igb_get_hw_control(adapter); 9277 9278 val = rd32(E1000_WUS); 9279 if (val & WAKE_PKT_WUS) 9280 igb_deliver_wake_packet(netdev); 9281 9282 wr32(E1000_WUS, ~0); 9283 9284 rtnl_lock(); 9285 if (!err && netif_running(netdev)) 9286 err = __igb_open(netdev, true); 9287 9288 if (!err) 9289 netif_device_attach(netdev); 9290 rtnl_unlock(); 9291 9292 return err; 9293 } 9294 9295 static int __maybe_unused igb_runtime_idle(struct device *dev) 9296 { 9297 struct net_device *netdev = dev_get_drvdata(dev); 9298 struct igb_adapter *adapter = netdev_priv(netdev); 9299 9300 if (!igb_has_link(adapter)) 9301 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9302 9303 return -EBUSY; 9304 } 9305 9306 static int __maybe_unused igb_runtime_suspend(struct device *dev) 9307 { 9308 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9309 } 9310 9311 static int __maybe_unused igb_runtime_resume(struct device *dev) 9312 { 9313 return igb_resume(dev); 9314 } 9315 9316 static void igb_shutdown(struct pci_dev *pdev) 9317 { 9318 bool wake; 9319 9320 __igb_shutdown(pdev, &wake, 0); 9321 9322 if (system_state == SYSTEM_POWER_OFF) { 9323 pci_wake_from_d3(pdev, wake); 9324 pci_set_power_state(pdev, PCI_D3hot); 9325 } 9326 } 9327 9328 #ifdef CONFIG_PCI_IOV 9329 static int igb_sriov_reinit(struct pci_dev *dev) 9330 { 9331 struct net_device *netdev = pci_get_drvdata(dev); 9332 struct igb_adapter *adapter = netdev_priv(netdev); 9333 struct pci_dev *pdev = adapter->pdev; 9334 9335 rtnl_lock(); 9336 9337 if (netif_running(netdev)) 9338 igb_close(netdev); 9339 else 9340 igb_reset(adapter); 9341 9342 igb_clear_interrupt_scheme(adapter); 9343 9344 igb_init_queue_configuration(adapter); 9345 9346 if (igb_init_interrupt_scheme(adapter, true)) { 9347 rtnl_unlock(); 9348 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9349 return -ENOMEM; 9350 } 9351 9352 if (netif_running(netdev)) 9353 igb_open(netdev); 9354 9355 rtnl_unlock(); 9356 9357 return 0; 9358 } 9359 9360 static int igb_pci_disable_sriov(struct pci_dev *dev) 9361 { 9362 int err = igb_disable_sriov(dev); 9363 9364 if (!err) 9365 err = igb_sriov_reinit(dev); 9366 9367 return err; 9368 } 9369 9370 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 9371 { 9372 int err = igb_enable_sriov(dev, num_vfs); 9373 9374 if (err) 9375 goto out; 9376 9377 err = igb_sriov_reinit(dev); 9378 if (!err) 9379 return num_vfs; 9380 9381 out: 9382 return err; 9383 } 9384 9385 #endif 9386 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9387 { 9388 #ifdef CONFIG_PCI_IOV 9389 if (num_vfs == 0) 9390 return igb_pci_disable_sriov(dev); 9391 else 9392 return igb_pci_enable_sriov(dev, num_vfs); 9393 #endif 9394 return 0; 9395 } 9396 9397 /** 9398 * igb_io_error_detected - called when PCI error is detected 9399 * @pdev: Pointer to PCI device 9400 * @state: The current pci connection state 9401 * 9402 * This function is called after a PCI bus error affecting 9403 * this device has been detected. 9404 **/ 9405 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9406 pci_channel_state_t state) 9407 { 9408 struct net_device *netdev = pci_get_drvdata(pdev); 9409 struct igb_adapter *adapter = netdev_priv(netdev); 9410 9411 netif_device_detach(netdev); 9412 9413 if (state == pci_channel_io_perm_failure) 9414 return PCI_ERS_RESULT_DISCONNECT; 9415 9416 if (netif_running(netdev)) 9417 igb_down(adapter); 9418 pci_disable_device(pdev); 9419 9420 /* Request a slot slot reset. */ 9421 return PCI_ERS_RESULT_NEED_RESET; 9422 } 9423 9424 /** 9425 * igb_io_slot_reset - called after the pci bus has been reset. 9426 * @pdev: Pointer to PCI device 9427 * 9428 * Restart the card from scratch, as if from a cold-boot. Implementation 9429 * resembles the first-half of the igb_resume routine. 9430 **/ 9431 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9432 { 9433 struct net_device *netdev = pci_get_drvdata(pdev); 9434 struct igb_adapter *adapter = netdev_priv(netdev); 9435 struct e1000_hw *hw = &adapter->hw; 9436 pci_ers_result_t result; 9437 9438 if (pci_enable_device_mem(pdev)) { 9439 dev_err(&pdev->dev, 9440 "Cannot re-enable PCI device after reset.\n"); 9441 result = PCI_ERS_RESULT_DISCONNECT; 9442 } else { 9443 pci_set_master(pdev); 9444 pci_restore_state(pdev); 9445 pci_save_state(pdev); 9446 9447 pci_enable_wake(pdev, PCI_D3hot, 0); 9448 pci_enable_wake(pdev, PCI_D3cold, 0); 9449 9450 /* In case of PCI error, adapter lose its HW address 9451 * so we should re-assign it here. 9452 */ 9453 hw->hw_addr = adapter->io_addr; 9454 9455 igb_reset(adapter); 9456 wr32(E1000_WUS, ~0); 9457 result = PCI_ERS_RESULT_RECOVERED; 9458 } 9459 9460 return result; 9461 } 9462 9463 /** 9464 * igb_io_resume - called when traffic can start flowing again. 9465 * @pdev: Pointer to PCI device 9466 * 9467 * This callback is called when the error recovery driver tells us that 9468 * its OK to resume normal operation. Implementation resembles the 9469 * second-half of the igb_resume routine. 9470 */ 9471 static void igb_io_resume(struct pci_dev *pdev) 9472 { 9473 struct net_device *netdev = pci_get_drvdata(pdev); 9474 struct igb_adapter *adapter = netdev_priv(netdev); 9475 9476 if (netif_running(netdev)) { 9477 if (igb_up(adapter)) { 9478 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9479 return; 9480 } 9481 } 9482 9483 netif_device_attach(netdev); 9484 9485 /* let the f/w know that the h/w is now under the control of the 9486 * driver. 9487 */ 9488 igb_get_hw_control(adapter); 9489 } 9490 9491 /** 9492 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9493 * @adapter: Pointer to adapter structure 9494 * @index: Index of the RAR entry which need to be synced with MAC table 9495 **/ 9496 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9497 { 9498 struct e1000_hw *hw = &adapter->hw; 9499 u32 rar_low, rar_high; 9500 u8 *addr = adapter->mac_table[index].addr; 9501 9502 /* HW expects these to be in network order when they are plugged 9503 * into the registers which are little endian. In order to guarantee 9504 * that ordering we need to do an leXX_to_cpup here in order to be 9505 * ready for the byteswap that occurs with writel 9506 */ 9507 rar_low = le32_to_cpup((__le32 *)(addr)); 9508 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9509 9510 /* Indicate to hardware the Address is Valid. */ 9511 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9512 if (is_valid_ether_addr(addr)) 9513 rar_high |= E1000_RAH_AV; 9514 9515 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9516 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9517 9518 switch (hw->mac.type) { 9519 case e1000_82575: 9520 case e1000_i210: 9521 if (adapter->mac_table[index].state & 9522 IGB_MAC_STATE_QUEUE_STEERING) 9523 rar_high |= E1000_RAH_QSEL_ENABLE; 9524 9525 rar_high |= E1000_RAH_POOL_1 * 9526 adapter->mac_table[index].queue; 9527 break; 9528 default: 9529 rar_high |= E1000_RAH_POOL_1 << 9530 adapter->mac_table[index].queue; 9531 break; 9532 } 9533 } 9534 9535 wr32(E1000_RAL(index), rar_low); 9536 wrfl(); 9537 wr32(E1000_RAH(index), rar_high); 9538 wrfl(); 9539 } 9540 9541 static int igb_set_vf_mac(struct igb_adapter *adapter, 9542 int vf, unsigned char *mac_addr) 9543 { 9544 struct e1000_hw *hw = &adapter->hw; 9545 /* VF MAC addresses start at end of receive addresses and moves 9546 * towards the first, as a result a collision should not be possible 9547 */ 9548 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9549 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9550 9551 ether_addr_copy(vf_mac_addr, mac_addr); 9552 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9553 adapter->mac_table[rar_entry].queue = vf; 9554 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9555 igb_rar_set_index(adapter, rar_entry); 9556 9557 return 0; 9558 } 9559 9560 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9561 { 9562 struct igb_adapter *adapter = netdev_priv(netdev); 9563 9564 if (vf >= adapter->vfs_allocated_count) 9565 return -EINVAL; 9566 9567 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9568 * flag and allows to overwrite the MAC via VF netdev. This 9569 * is necessary to allow libvirt a way to restore the original 9570 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9571 * down a VM. 9572 */ 9573 if (is_zero_ether_addr(mac)) { 9574 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9575 dev_info(&adapter->pdev->dev, 9576 "remove administratively set MAC on VF %d\n", 9577 vf); 9578 } else if (is_valid_ether_addr(mac)) { 9579 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9580 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9581 mac, vf); 9582 dev_info(&adapter->pdev->dev, 9583 "Reload the VF driver to make this change effective."); 9584 /* Generate additional warning if PF is down */ 9585 if (test_bit(__IGB_DOWN, &adapter->state)) { 9586 dev_warn(&adapter->pdev->dev, 9587 "The VF MAC address has been set, but the PF device is not up.\n"); 9588 dev_warn(&adapter->pdev->dev, 9589 "Bring the PF device up before attempting to use the VF device.\n"); 9590 } 9591 } else { 9592 return -EINVAL; 9593 } 9594 return igb_set_vf_mac(adapter, vf, mac); 9595 } 9596 9597 static int igb_link_mbps(int internal_link_speed) 9598 { 9599 switch (internal_link_speed) { 9600 case SPEED_100: 9601 return 100; 9602 case SPEED_1000: 9603 return 1000; 9604 default: 9605 return 0; 9606 } 9607 } 9608 9609 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9610 int link_speed) 9611 { 9612 int rf_dec, rf_int; 9613 u32 bcnrc_val; 9614 9615 if (tx_rate != 0) { 9616 /* Calculate the rate factor values to set */ 9617 rf_int = link_speed / tx_rate; 9618 rf_dec = (link_speed - (rf_int * tx_rate)); 9619 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9620 tx_rate; 9621 9622 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9623 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9624 E1000_RTTBCNRC_RF_INT_MASK); 9625 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9626 } else { 9627 bcnrc_val = 0; 9628 } 9629 9630 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9631 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9632 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9633 */ 9634 wr32(E1000_RTTBCNRM, 0x14); 9635 wr32(E1000_RTTBCNRC, bcnrc_val); 9636 } 9637 9638 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9639 { 9640 int actual_link_speed, i; 9641 bool reset_rate = false; 9642 9643 /* VF TX rate limit was not set or not supported */ 9644 if ((adapter->vf_rate_link_speed == 0) || 9645 (adapter->hw.mac.type != e1000_82576)) 9646 return; 9647 9648 actual_link_speed = igb_link_mbps(adapter->link_speed); 9649 if (actual_link_speed != adapter->vf_rate_link_speed) { 9650 reset_rate = true; 9651 adapter->vf_rate_link_speed = 0; 9652 dev_info(&adapter->pdev->dev, 9653 "Link speed has been changed. VF Transmit rate is disabled\n"); 9654 } 9655 9656 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9657 if (reset_rate) 9658 adapter->vf_data[i].tx_rate = 0; 9659 9660 igb_set_vf_rate_limit(&adapter->hw, i, 9661 adapter->vf_data[i].tx_rate, 9662 actual_link_speed); 9663 } 9664 } 9665 9666 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9667 int min_tx_rate, int max_tx_rate) 9668 { 9669 struct igb_adapter *adapter = netdev_priv(netdev); 9670 struct e1000_hw *hw = &adapter->hw; 9671 int actual_link_speed; 9672 9673 if (hw->mac.type != e1000_82576) 9674 return -EOPNOTSUPP; 9675 9676 if (min_tx_rate) 9677 return -EINVAL; 9678 9679 actual_link_speed = igb_link_mbps(adapter->link_speed); 9680 if ((vf >= adapter->vfs_allocated_count) || 9681 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9682 (max_tx_rate < 0) || 9683 (max_tx_rate > actual_link_speed)) 9684 return -EINVAL; 9685 9686 adapter->vf_rate_link_speed = actual_link_speed; 9687 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 9688 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 9689 9690 return 0; 9691 } 9692 9693 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 9694 bool setting) 9695 { 9696 struct igb_adapter *adapter = netdev_priv(netdev); 9697 struct e1000_hw *hw = &adapter->hw; 9698 u32 reg_val, reg_offset; 9699 9700 if (!adapter->vfs_allocated_count) 9701 return -EOPNOTSUPP; 9702 9703 if (vf >= adapter->vfs_allocated_count) 9704 return -EINVAL; 9705 9706 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 9707 reg_val = rd32(reg_offset); 9708 if (setting) 9709 reg_val |= (BIT(vf) | 9710 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9711 else 9712 reg_val &= ~(BIT(vf) | 9713 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 9714 wr32(reg_offset, reg_val); 9715 9716 adapter->vf_data[vf].spoofchk_enabled = setting; 9717 return 0; 9718 } 9719 9720 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 9721 { 9722 struct igb_adapter *adapter = netdev_priv(netdev); 9723 9724 if (vf >= adapter->vfs_allocated_count) 9725 return -EINVAL; 9726 if (adapter->vf_data[vf].trusted == setting) 9727 return 0; 9728 9729 adapter->vf_data[vf].trusted = setting; 9730 9731 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 9732 vf, setting ? "" : "not "); 9733 return 0; 9734 } 9735 9736 static int igb_ndo_get_vf_config(struct net_device *netdev, 9737 int vf, struct ifla_vf_info *ivi) 9738 { 9739 struct igb_adapter *adapter = netdev_priv(netdev); 9740 if (vf >= adapter->vfs_allocated_count) 9741 return -EINVAL; 9742 ivi->vf = vf; 9743 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 9744 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 9745 ivi->min_tx_rate = 0; 9746 ivi->vlan = adapter->vf_data[vf].pf_vlan; 9747 ivi->qos = adapter->vf_data[vf].pf_qos; 9748 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 9749 ivi->trusted = adapter->vf_data[vf].trusted; 9750 return 0; 9751 } 9752 9753 static void igb_vmm_control(struct igb_adapter *adapter) 9754 { 9755 struct e1000_hw *hw = &adapter->hw; 9756 u32 reg; 9757 9758 switch (hw->mac.type) { 9759 case e1000_82575: 9760 case e1000_i210: 9761 case e1000_i211: 9762 case e1000_i354: 9763 default: 9764 /* replication is not supported for 82575 */ 9765 return; 9766 case e1000_82576: 9767 /* notify HW that the MAC is adding vlan tags */ 9768 reg = rd32(E1000_DTXCTL); 9769 reg |= E1000_DTXCTL_VLAN_ADDED; 9770 wr32(E1000_DTXCTL, reg); 9771 fallthrough; 9772 case e1000_82580: 9773 /* enable replication vlan tag stripping */ 9774 reg = rd32(E1000_RPLOLR); 9775 reg |= E1000_RPLOLR_STRVLAN; 9776 wr32(E1000_RPLOLR, reg); 9777 fallthrough; 9778 case e1000_i350: 9779 /* none of the above registers are supported by i350 */ 9780 break; 9781 } 9782 9783 if (adapter->vfs_allocated_count) { 9784 igb_vmdq_set_loopback_pf(hw, true); 9785 igb_vmdq_set_replication_pf(hw, true); 9786 igb_vmdq_set_anti_spoofing_pf(hw, true, 9787 adapter->vfs_allocated_count); 9788 } else { 9789 igb_vmdq_set_loopback_pf(hw, false); 9790 igb_vmdq_set_replication_pf(hw, false); 9791 } 9792 } 9793 9794 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 9795 { 9796 struct e1000_hw *hw = &adapter->hw; 9797 u32 dmac_thr; 9798 u16 hwm; 9799 9800 if (hw->mac.type > e1000_82580) { 9801 if (adapter->flags & IGB_FLAG_DMAC) { 9802 u32 reg; 9803 9804 /* force threshold to 0. */ 9805 wr32(E1000_DMCTXTH, 0); 9806 9807 /* DMA Coalescing high water mark needs to be greater 9808 * than the Rx threshold. Set hwm to PBA - max frame 9809 * size in 16B units, capping it at PBA - 6KB. 9810 */ 9811 hwm = 64 * (pba - 6); 9812 reg = rd32(E1000_FCRTC); 9813 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 9814 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 9815 & E1000_FCRTC_RTH_COAL_MASK); 9816 wr32(E1000_FCRTC, reg); 9817 9818 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 9819 * frame size, capping it at PBA - 10KB. 9820 */ 9821 dmac_thr = pba - 10; 9822 reg = rd32(E1000_DMACR); 9823 reg &= ~E1000_DMACR_DMACTHR_MASK; 9824 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 9825 & E1000_DMACR_DMACTHR_MASK); 9826 9827 /* transition to L0x or L1 if available..*/ 9828 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 9829 9830 /* watchdog timer= +-1000 usec in 32usec intervals */ 9831 reg |= (1000 >> 5); 9832 9833 /* Disable BMC-to-OS Watchdog Enable */ 9834 if (hw->mac.type != e1000_i354) 9835 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 9836 9837 wr32(E1000_DMACR, reg); 9838 9839 /* no lower threshold to disable 9840 * coalescing(smart fifb)-UTRESH=0 9841 */ 9842 wr32(E1000_DMCRTRH, 0); 9843 9844 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 9845 9846 wr32(E1000_DMCTLX, reg); 9847 9848 /* free space in tx packet buffer to wake from 9849 * DMA coal 9850 */ 9851 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 9852 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 9853 9854 /* make low power state decision controlled 9855 * by DMA coal 9856 */ 9857 reg = rd32(E1000_PCIEMISC); 9858 reg &= ~E1000_PCIEMISC_LX_DECISION; 9859 wr32(E1000_PCIEMISC, reg); 9860 } /* endif adapter->dmac is not disabled */ 9861 } else if (hw->mac.type == e1000_82580) { 9862 u32 reg = rd32(E1000_PCIEMISC); 9863 9864 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 9865 wr32(E1000_DMACR, 0); 9866 } 9867 } 9868 9869 /** 9870 * igb_read_i2c_byte - Reads 8 bit word over I2C 9871 * @hw: pointer to hardware structure 9872 * @byte_offset: byte offset to read 9873 * @dev_addr: device address 9874 * @data: value read 9875 * 9876 * Performs byte read operation over I2C interface at 9877 * a specified device address. 9878 **/ 9879 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9880 u8 dev_addr, u8 *data) 9881 { 9882 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9883 struct i2c_client *this_client = adapter->i2c_client; 9884 s32 status; 9885 u16 swfw_mask = 0; 9886 9887 if (!this_client) 9888 return E1000_ERR_I2C; 9889 9890 swfw_mask = E1000_SWFW_PHY0_SM; 9891 9892 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9893 return E1000_ERR_SWFW_SYNC; 9894 9895 status = i2c_smbus_read_byte_data(this_client, byte_offset); 9896 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9897 9898 if (status < 0) 9899 return E1000_ERR_I2C; 9900 else { 9901 *data = status; 9902 return 0; 9903 } 9904 } 9905 9906 /** 9907 * igb_write_i2c_byte - Writes 8 bit word over I2C 9908 * @hw: pointer to hardware structure 9909 * @byte_offset: byte offset to write 9910 * @dev_addr: device address 9911 * @data: value to write 9912 * 9913 * Performs byte write operation over I2C interface at 9914 * a specified device address. 9915 **/ 9916 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 9917 u8 dev_addr, u8 data) 9918 { 9919 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 9920 struct i2c_client *this_client = adapter->i2c_client; 9921 s32 status; 9922 u16 swfw_mask = E1000_SWFW_PHY0_SM; 9923 9924 if (!this_client) 9925 return E1000_ERR_I2C; 9926 9927 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 9928 return E1000_ERR_SWFW_SYNC; 9929 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 9930 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 9931 9932 if (status) 9933 return E1000_ERR_I2C; 9934 else 9935 return 0; 9936 9937 } 9938 9939 int igb_reinit_queues(struct igb_adapter *adapter) 9940 { 9941 struct net_device *netdev = adapter->netdev; 9942 struct pci_dev *pdev = adapter->pdev; 9943 int err = 0; 9944 9945 if (netif_running(netdev)) 9946 igb_close(netdev); 9947 9948 igb_reset_interrupt_capability(adapter); 9949 9950 if (igb_init_interrupt_scheme(adapter, true)) { 9951 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9952 return -ENOMEM; 9953 } 9954 9955 if (netif_running(netdev)) 9956 err = igb_open(netdev); 9957 9958 return err; 9959 } 9960 9961 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 9962 { 9963 struct igb_nfc_filter *rule; 9964 9965 spin_lock(&adapter->nfc_lock); 9966 9967 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9968 igb_erase_filter(adapter, rule); 9969 9970 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 9971 igb_erase_filter(adapter, rule); 9972 9973 spin_unlock(&adapter->nfc_lock); 9974 } 9975 9976 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 9977 { 9978 struct igb_nfc_filter *rule; 9979 9980 spin_lock(&adapter->nfc_lock); 9981 9982 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 9983 igb_add_filter(adapter, rule); 9984 9985 spin_unlock(&adapter->nfc_lock); 9986 } 9987 /* igb_main.c */ 9988