1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* ethtool support for igb */ 25 26 #include <linux/vmalloc.h> 27 #include <linux/netdevice.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/interrupt.h> 31 #include <linux/if_ether.h> 32 #include <linux/ethtool.h> 33 #include <linux/sched.h> 34 #include <linux/slab.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/highmem.h> 37 #include <linux/mdio.h> 38 39 #include "igb.h" 40 41 struct igb_stats { 42 char stat_string[ETH_GSTRING_LEN]; 43 int sizeof_stat; 44 int stat_offset; 45 }; 46 47 #define IGB_STAT(_name, _stat) { \ 48 .stat_string = _name, \ 49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 50 .stat_offset = offsetof(struct igb_adapter, _stat) \ 51 } 52 static const struct igb_stats igb_gstrings_stats[] = { 53 IGB_STAT("rx_packets", stats.gprc), 54 IGB_STAT("tx_packets", stats.gptc), 55 IGB_STAT("rx_bytes", stats.gorc), 56 IGB_STAT("tx_bytes", stats.gotc), 57 IGB_STAT("rx_broadcast", stats.bprc), 58 IGB_STAT("tx_broadcast", stats.bptc), 59 IGB_STAT("rx_multicast", stats.mprc), 60 IGB_STAT("tx_multicast", stats.mptc), 61 IGB_STAT("multicast", stats.mprc), 62 IGB_STAT("collisions", stats.colc), 63 IGB_STAT("rx_crc_errors", stats.crcerrs), 64 IGB_STAT("rx_no_buffer_count", stats.rnbc), 65 IGB_STAT("rx_missed_errors", stats.mpc), 66 IGB_STAT("tx_aborted_errors", stats.ecol), 67 IGB_STAT("tx_carrier_errors", stats.tncrs), 68 IGB_STAT("tx_window_errors", stats.latecol), 69 IGB_STAT("tx_abort_late_coll", stats.latecol), 70 IGB_STAT("tx_deferred_ok", stats.dc), 71 IGB_STAT("tx_single_coll_ok", stats.scc), 72 IGB_STAT("tx_multi_coll_ok", stats.mcc), 73 IGB_STAT("tx_timeout_count", tx_timeout_count), 74 IGB_STAT("rx_long_length_errors", stats.roc), 75 IGB_STAT("rx_short_length_errors", stats.ruc), 76 IGB_STAT("rx_align_errors", stats.algnerrc), 77 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 79 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 81 IGB_STAT("tx_flow_control_xon", stats.xontxc), 82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 83 IGB_STAT("rx_long_byte_count", stats.gorc), 84 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 85 IGB_STAT("tx_smbus", stats.mgptc), 86 IGB_STAT("rx_smbus", stats.mgprc), 87 IGB_STAT("dropped_smbus", stats.mgpdc), 88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 94 }; 95 96 #define IGB_NETDEV_STAT(_net_stat) { \ 97 .stat_string = __stringify(_net_stat), \ 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 100 } 101 static const struct igb_stats igb_gstrings_net_stats[] = { 102 IGB_NETDEV_STAT(rx_errors), 103 IGB_NETDEV_STAT(tx_errors), 104 IGB_NETDEV_STAT(tx_dropped), 105 IGB_NETDEV_STAT(rx_length_errors), 106 IGB_NETDEV_STAT(rx_over_errors), 107 IGB_NETDEV_STAT(rx_frame_errors), 108 IGB_NETDEV_STAT(rx_fifo_errors), 109 IGB_NETDEV_STAT(tx_fifo_errors), 110 IGB_NETDEV_STAT(tx_heartbeat_errors) 111 }; 112 113 #define IGB_GLOBAL_STATS_LEN \ 114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 115 #define IGB_NETDEV_STATS_LEN \ 116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 117 #define IGB_RX_QUEUE_STATS_LEN \ 118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 119 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 121 122 #define IGB_QUEUE_STATS_LEN \ 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 124 IGB_RX_QUEUE_STATS_LEN) + \ 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 126 IGB_TX_QUEUE_STATS_LEN)) 127 #define IGB_STATS_LEN \ 128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 129 130 enum igb_diagnostics_results { 131 TEST_REG = 0, 132 TEST_EEP, 133 TEST_IRQ, 134 TEST_LOOP, 135 TEST_LINK 136 }; 137 138 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 139 [TEST_REG] = "Register test (offline)", 140 [TEST_EEP] = "Eeprom test (offline)", 141 [TEST_IRQ] = "Interrupt test (offline)", 142 [TEST_LOOP] = "Loopback test (offline)", 143 [TEST_LINK] = "Link test (on/offline)" 144 }; 145 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 146 147 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = { 148 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) 149 "legacy-rx", 150 }; 151 152 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings) 153 154 static int igb_get_link_ksettings(struct net_device *netdev, 155 struct ethtool_link_ksettings *cmd) 156 { 157 struct igb_adapter *adapter = netdev_priv(netdev); 158 struct e1000_hw *hw = &adapter->hw; 159 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 160 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 161 u32 status; 162 u32 speed; 163 u32 supported, advertising; 164 165 status = rd32(E1000_STATUS); 166 if (hw->phy.media_type == e1000_media_type_copper) { 167 168 supported = (SUPPORTED_10baseT_Half | 169 SUPPORTED_10baseT_Full | 170 SUPPORTED_100baseT_Half | 171 SUPPORTED_100baseT_Full | 172 SUPPORTED_1000baseT_Full| 173 SUPPORTED_Autoneg | 174 SUPPORTED_TP | 175 SUPPORTED_Pause); 176 advertising = ADVERTISED_TP; 177 178 if (hw->mac.autoneg == 1) { 179 advertising |= ADVERTISED_Autoneg; 180 /* the e1000 autoneg seems to match ethtool nicely */ 181 advertising |= hw->phy.autoneg_advertised; 182 } 183 184 cmd->base.port = PORT_TP; 185 cmd->base.phy_address = hw->phy.addr; 186 } else { 187 supported = (SUPPORTED_FIBRE | 188 SUPPORTED_1000baseKX_Full | 189 SUPPORTED_Autoneg | 190 SUPPORTED_Pause); 191 advertising = (ADVERTISED_FIBRE | 192 ADVERTISED_1000baseKX_Full); 193 if (hw->mac.type == e1000_i354) { 194 if ((hw->device_id == 195 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 196 !(status & E1000_STATUS_2P5_SKU_OVER)) { 197 supported |= SUPPORTED_2500baseX_Full; 198 supported &= ~SUPPORTED_1000baseKX_Full; 199 advertising |= ADVERTISED_2500baseX_Full; 200 advertising &= ~ADVERTISED_1000baseKX_Full; 201 } 202 } 203 if (eth_flags->e100_base_fx) { 204 supported |= SUPPORTED_100baseT_Full; 205 advertising |= ADVERTISED_100baseT_Full; 206 } 207 if (hw->mac.autoneg == 1) 208 advertising |= ADVERTISED_Autoneg; 209 210 cmd->base.port = PORT_FIBRE; 211 } 212 if (hw->mac.autoneg != 1) 213 advertising &= ~(ADVERTISED_Pause | 214 ADVERTISED_Asym_Pause); 215 216 switch (hw->fc.requested_mode) { 217 case e1000_fc_full: 218 advertising |= ADVERTISED_Pause; 219 break; 220 case e1000_fc_rx_pause: 221 advertising |= (ADVERTISED_Pause | 222 ADVERTISED_Asym_Pause); 223 break; 224 case e1000_fc_tx_pause: 225 advertising |= ADVERTISED_Asym_Pause; 226 break; 227 default: 228 advertising &= ~(ADVERTISED_Pause | 229 ADVERTISED_Asym_Pause); 230 } 231 if (status & E1000_STATUS_LU) { 232 if ((status & E1000_STATUS_2P5_SKU) && 233 !(status & E1000_STATUS_2P5_SKU_OVER)) { 234 speed = SPEED_2500; 235 } else if (status & E1000_STATUS_SPEED_1000) { 236 speed = SPEED_1000; 237 } else if (status & E1000_STATUS_SPEED_100) { 238 speed = SPEED_100; 239 } else { 240 speed = SPEED_10; 241 } 242 if ((status & E1000_STATUS_FD) || 243 hw->phy.media_type != e1000_media_type_copper) 244 cmd->base.duplex = DUPLEX_FULL; 245 else 246 cmd->base.duplex = DUPLEX_HALF; 247 } else { 248 speed = SPEED_UNKNOWN; 249 cmd->base.duplex = DUPLEX_UNKNOWN; 250 } 251 cmd->base.speed = speed; 252 if ((hw->phy.media_type == e1000_media_type_fiber) || 253 hw->mac.autoneg) 254 cmd->base.autoneg = AUTONEG_ENABLE; 255 else 256 cmd->base.autoneg = AUTONEG_DISABLE; 257 258 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 259 if (hw->phy.media_type == e1000_media_type_copper) 260 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 261 ETH_TP_MDI; 262 else 263 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 264 265 if (hw->phy.mdix == AUTO_ALL_MODES) 266 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 267 else 268 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; 269 270 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 271 supported); 272 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 273 advertising); 274 275 return 0; 276 } 277 278 static int igb_set_link_ksettings(struct net_device *netdev, 279 const struct ethtool_link_ksettings *cmd) 280 { 281 struct igb_adapter *adapter = netdev_priv(netdev); 282 struct e1000_hw *hw = &adapter->hw; 283 u32 advertising; 284 285 /* When SoL/IDER sessions are active, autoneg/speed/duplex 286 * cannot be changed 287 */ 288 if (igb_check_reset_block(hw)) { 289 dev_err(&adapter->pdev->dev, 290 "Cannot change link characteristics when SoL/IDER is active.\n"); 291 return -EINVAL; 292 } 293 294 /* MDI setting is only allowed when autoneg enabled because 295 * some hardware doesn't allow MDI setting when speed or 296 * duplex is forced. 297 */ 298 if (cmd->base.eth_tp_mdix_ctrl) { 299 if (hw->phy.media_type != e1000_media_type_copper) 300 return -EOPNOTSUPP; 301 302 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 303 (cmd->base.autoneg != AUTONEG_ENABLE)) { 304 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 305 return -EINVAL; 306 } 307 } 308 309 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 310 usleep_range(1000, 2000); 311 312 ethtool_convert_link_mode_to_legacy_u32(&advertising, 313 cmd->link_modes.advertising); 314 315 if (cmd->base.autoneg == AUTONEG_ENABLE) { 316 hw->mac.autoneg = 1; 317 if (hw->phy.media_type == e1000_media_type_fiber) { 318 hw->phy.autoneg_advertised = advertising | 319 ADVERTISED_FIBRE | 320 ADVERTISED_Autoneg; 321 switch (adapter->link_speed) { 322 case SPEED_2500: 323 hw->phy.autoneg_advertised = 324 ADVERTISED_2500baseX_Full; 325 break; 326 case SPEED_1000: 327 hw->phy.autoneg_advertised = 328 ADVERTISED_1000baseT_Full; 329 break; 330 case SPEED_100: 331 hw->phy.autoneg_advertised = 332 ADVERTISED_100baseT_Full; 333 break; 334 default: 335 break; 336 } 337 } else { 338 hw->phy.autoneg_advertised = advertising | 339 ADVERTISED_TP | 340 ADVERTISED_Autoneg; 341 } 342 advertising = hw->phy.autoneg_advertised; 343 if (adapter->fc_autoneg) 344 hw->fc.requested_mode = e1000_fc_default; 345 } else { 346 u32 speed = cmd->base.speed; 347 /* calling this overrides forced MDI setting */ 348 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { 349 clear_bit(__IGB_RESETTING, &adapter->state); 350 return -EINVAL; 351 } 352 } 353 354 /* MDI-X => 2; MDI => 1; Auto => 3 */ 355 if (cmd->base.eth_tp_mdix_ctrl) { 356 /* fix up the value for auto (3 => 0) as zero is mapped 357 * internally to auto 358 */ 359 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 360 hw->phy.mdix = AUTO_ALL_MODES; 361 else 362 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; 363 } 364 365 /* reset the link */ 366 if (netif_running(adapter->netdev)) { 367 igb_down(adapter); 368 igb_up(adapter); 369 } else 370 igb_reset(adapter); 371 372 clear_bit(__IGB_RESETTING, &adapter->state); 373 return 0; 374 } 375 376 static u32 igb_get_link(struct net_device *netdev) 377 { 378 struct igb_adapter *adapter = netdev_priv(netdev); 379 struct e1000_mac_info *mac = &adapter->hw.mac; 380 381 /* If the link is not reported up to netdev, interrupts are disabled, 382 * and so the physical link state may have changed since we last 383 * looked. Set get_link_status to make sure that the true link 384 * state is interrogated, rather than pulling a cached and possibly 385 * stale link state from the driver. 386 */ 387 if (!netif_carrier_ok(netdev)) 388 mac->get_link_status = 1; 389 390 return igb_has_link(adapter); 391 } 392 393 static void igb_get_pauseparam(struct net_device *netdev, 394 struct ethtool_pauseparam *pause) 395 { 396 struct igb_adapter *adapter = netdev_priv(netdev); 397 struct e1000_hw *hw = &adapter->hw; 398 399 pause->autoneg = 400 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 401 402 if (hw->fc.current_mode == e1000_fc_rx_pause) 403 pause->rx_pause = 1; 404 else if (hw->fc.current_mode == e1000_fc_tx_pause) 405 pause->tx_pause = 1; 406 else if (hw->fc.current_mode == e1000_fc_full) { 407 pause->rx_pause = 1; 408 pause->tx_pause = 1; 409 } 410 } 411 412 static int igb_set_pauseparam(struct net_device *netdev, 413 struct ethtool_pauseparam *pause) 414 { 415 struct igb_adapter *adapter = netdev_priv(netdev); 416 struct e1000_hw *hw = &adapter->hw; 417 int retval = 0; 418 419 /* 100basefx does not support setting link flow control */ 420 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 421 return -EINVAL; 422 423 adapter->fc_autoneg = pause->autoneg; 424 425 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 426 usleep_range(1000, 2000); 427 428 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 429 hw->fc.requested_mode = e1000_fc_default; 430 if (netif_running(adapter->netdev)) { 431 igb_down(adapter); 432 igb_up(adapter); 433 } else { 434 igb_reset(adapter); 435 } 436 } else { 437 if (pause->rx_pause && pause->tx_pause) 438 hw->fc.requested_mode = e1000_fc_full; 439 else if (pause->rx_pause && !pause->tx_pause) 440 hw->fc.requested_mode = e1000_fc_rx_pause; 441 else if (!pause->rx_pause && pause->tx_pause) 442 hw->fc.requested_mode = e1000_fc_tx_pause; 443 else if (!pause->rx_pause && !pause->tx_pause) 444 hw->fc.requested_mode = e1000_fc_none; 445 446 hw->fc.current_mode = hw->fc.requested_mode; 447 448 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 449 igb_force_mac_fc(hw) : igb_setup_link(hw)); 450 } 451 452 clear_bit(__IGB_RESETTING, &adapter->state); 453 return retval; 454 } 455 456 static u32 igb_get_msglevel(struct net_device *netdev) 457 { 458 struct igb_adapter *adapter = netdev_priv(netdev); 459 return adapter->msg_enable; 460 } 461 462 static void igb_set_msglevel(struct net_device *netdev, u32 data) 463 { 464 struct igb_adapter *adapter = netdev_priv(netdev); 465 adapter->msg_enable = data; 466 } 467 468 static int igb_get_regs_len(struct net_device *netdev) 469 { 470 #define IGB_REGS_LEN 739 471 return IGB_REGS_LEN * sizeof(u32); 472 } 473 474 static void igb_get_regs(struct net_device *netdev, 475 struct ethtool_regs *regs, void *p) 476 { 477 struct igb_adapter *adapter = netdev_priv(netdev); 478 struct e1000_hw *hw = &adapter->hw; 479 u32 *regs_buff = p; 480 u8 i; 481 482 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 483 484 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 485 486 /* General Registers */ 487 regs_buff[0] = rd32(E1000_CTRL); 488 regs_buff[1] = rd32(E1000_STATUS); 489 regs_buff[2] = rd32(E1000_CTRL_EXT); 490 regs_buff[3] = rd32(E1000_MDIC); 491 regs_buff[4] = rd32(E1000_SCTL); 492 regs_buff[5] = rd32(E1000_CONNSW); 493 regs_buff[6] = rd32(E1000_VET); 494 regs_buff[7] = rd32(E1000_LEDCTL); 495 regs_buff[8] = rd32(E1000_PBA); 496 regs_buff[9] = rd32(E1000_PBS); 497 regs_buff[10] = rd32(E1000_FRTIMER); 498 regs_buff[11] = rd32(E1000_TCPTIMER); 499 500 /* NVM Register */ 501 regs_buff[12] = rd32(E1000_EECD); 502 503 /* Interrupt */ 504 /* Reading EICS for EICR because they read the 505 * same but EICS does not clear on read 506 */ 507 regs_buff[13] = rd32(E1000_EICS); 508 regs_buff[14] = rd32(E1000_EICS); 509 regs_buff[15] = rd32(E1000_EIMS); 510 regs_buff[16] = rd32(E1000_EIMC); 511 regs_buff[17] = rd32(E1000_EIAC); 512 regs_buff[18] = rd32(E1000_EIAM); 513 /* Reading ICS for ICR because they read the 514 * same but ICS does not clear on read 515 */ 516 regs_buff[19] = rd32(E1000_ICS); 517 regs_buff[20] = rd32(E1000_ICS); 518 regs_buff[21] = rd32(E1000_IMS); 519 regs_buff[22] = rd32(E1000_IMC); 520 regs_buff[23] = rd32(E1000_IAC); 521 regs_buff[24] = rd32(E1000_IAM); 522 regs_buff[25] = rd32(E1000_IMIRVP); 523 524 /* Flow Control */ 525 regs_buff[26] = rd32(E1000_FCAL); 526 regs_buff[27] = rd32(E1000_FCAH); 527 regs_buff[28] = rd32(E1000_FCTTV); 528 regs_buff[29] = rd32(E1000_FCRTL); 529 regs_buff[30] = rd32(E1000_FCRTH); 530 regs_buff[31] = rd32(E1000_FCRTV); 531 532 /* Receive */ 533 regs_buff[32] = rd32(E1000_RCTL); 534 regs_buff[33] = rd32(E1000_RXCSUM); 535 regs_buff[34] = rd32(E1000_RLPML); 536 regs_buff[35] = rd32(E1000_RFCTL); 537 regs_buff[36] = rd32(E1000_MRQC); 538 regs_buff[37] = rd32(E1000_VT_CTL); 539 540 /* Transmit */ 541 regs_buff[38] = rd32(E1000_TCTL); 542 regs_buff[39] = rd32(E1000_TCTL_EXT); 543 regs_buff[40] = rd32(E1000_TIPG); 544 regs_buff[41] = rd32(E1000_DTXCTL); 545 546 /* Wake Up */ 547 regs_buff[42] = rd32(E1000_WUC); 548 regs_buff[43] = rd32(E1000_WUFC); 549 regs_buff[44] = rd32(E1000_WUS); 550 regs_buff[45] = rd32(E1000_IPAV); 551 regs_buff[46] = rd32(E1000_WUPL); 552 553 /* MAC */ 554 regs_buff[47] = rd32(E1000_PCS_CFG0); 555 regs_buff[48] = rd32(E1000_PCS_LCTL); 556 regs_buff[49] = rd32(E1000_PCS_LSTAT); 557 regs_buff[50] = rd32(E1000_PCS_ANADV); 558 regs_buff[51] = rd32(E1000_PCS_LPAB); 559 regs_buff[52] = rd32(E1000_PCS_NPTX); 560 regs_buff[53] = rd32(E1000_PCS_LPABNP); 561 562 /* Statistics */ 563 regs_buff[54] = adapter->stats.crcerrs; 564 regs_buff[55] = adapter->stats.algnerrc; 565 regs_buff[56] = adapter->stats.symerrs; 566 regs_buff[57] = adapter->stats.rxerrc; 567 regs_buff[58] = adapter->stats.mpc; 568 regs_buff[59] = adapter->stats.scc; 569 regs_buff[60] = adapter->stats.ecol; 570 regs_buff[61] = adapter->stats.mcc; 571 regs_buff[62] = adapter->stats.latecol; 572 regs_buff[63] = adapter->stats.colc; 573 regs_buff[64] = adapter->stats.dc; 574 regs_buff[65] = adapter->stats.tncrs; 575 regs_buff[66] = adapter->stats.sec; 576 regs_buff[67] = adapter->stats.htdpmc; 577 regs_buff[68] = adapter->stats.rlec; 578 regs_buff[69] = adapter->stats.xonrxc; 579 regs_buff[70] = adapter->stats.xontxc; 580 regs_buff[71] = adapter->stats.xoffrxc; 581 regs_buff[72] = adapter->stats.xofftxc; 582 regs_buff[73] = adapter->stats.fcruc; 583 regs_buff[74] = adapter->stats.prc64; 584 regs_buff[75] = adapter->stats.prc127; 585 regs_buff[76] = adapter->stats.prc255; 586 regs_buff[77] = adapter->stats.prc511; 587 regs_buff[78] = adapter->stats.prc1023; 588 regs_buff[79] = adapter->stats.prc1522; 589 regs_buff[80] = adapter->stats.gprc; 590 regs_buff[81] = adapter->stats.bprc; 591 regs_buff[82] = adapter->stats.mprc; 592 regs_buff[83] = adapter->stats.gptc; 593 regs_buff[84] = adapter->stats.gorc; 594 regs_buff[86] = adapter->stats.gotc; 595 regs_buff[88] = adapter->stats.rnbc; 596 regs_buff[89] = adapter->stats.ruc; 597 regs_buff[90] = adapter->stats.rfc; 598 regs_buff[91] = adapter->stats.roc; 599 regs_buff[92] = adapter->stats.rjc; 600 regs_buff[93] = adapter->stats.mgprc; 601 regs_buff[94] = adapter->stats.mgpdc; 602 regs_buff[95] = adapter->stats.mgptc; 603 regs_buff[96] = adapter->stats.tor; 604 regs_buff[98] = adapter->stats.tot; 605 regs_buff[100] = adapter->stats.tpr; 606 regs_buff[101] = adapter->stats.tpt; 607 regs_buff[102] = adapter->stats.ptc64; 608 regs_buff[103] = adapter->stats.ptc127; 609 regs_buff[104] = adapter->stats.ptc255; 610 regs_buff[105] = adapter->stats.ptc511; 611 regs_buff[106] = adapter->stats.ptc1023; 612 regs_buff[107] = adapter->stats.ptc1522; 613 regs_buff[108] = adapter->stats.mptc; 614 regs_buff[109] = adapter->stats.bptc; 615 regs_buff[110] = adapter->stats.tsctc; 616 regs_buff[111] = adapter->stats.iac; 617 regs_buff[112] = adapter->stats.rpthc; 618 regs_buff[113] = adapter->stats.hgptc; 619 regs_buff[114] = adapter->stats.hgorc; 620 regs_buff[116] = adapter->stats.hgotc; 621 regs_buff[118] = adapter->stats.lenerrs; 622 regs_buff[119] = adapter->stats.scvpc; 623 regs_buff[120] = adapter->stats.hrmpc; 624 625 for (i = 0; i < 4; i++) 626 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 627 for (i = 0; i < 4; i++) 628 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 629 for (i = 0; i < 4; i++) 630 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 631 for (i = 0; i < 4; i++) 632 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 633 for (i = 0; i < 4; i++) 634 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 635 for (i = 0; i < 4; i++) 636 regs_buff[141 + i] = rd32(E1000_RDH(i)); 637 for (i = 0; i < 4; i++) 638 regs_buff[145 + i] = rd32(E1000_RDT(i)); 639 for (i = 0; i < 4; i++) 640 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 641 642 for (i = 0; i < 10; i++) 643 regs_buff[153 + i] = rd32(E1000_EITR(i)); 644 for (i = 0; i < 8; i++) 645 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 646 for (i = 0; i < 8; i++) 647 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 648 for (i = 0; i < 16; i++) 649 regs_buff[179 + i] = rd32(E1000_RAL(i)); 650 for (i = 0; i < 16; i++) 651 regs_buff[195 + i] = rd32(E1000_RAH(i)); 652 653 for (i = 0; i < 4; i++) 654 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 655 for (i = 0; i < 4; i++) 656 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 657 for (i = 0; i < 4; i++) 658 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 659 for (i = 0; i < 4; i++) 660 regs_buff[223 + i] = rd32(E1000_TDH(i)); 661 for (i = 0; i < 4; i++) 662 regs_buff[227 + i] = rd32(E1000_TDT(i)); 663 for (i = 0; i < 4; i++) 664 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 665 for (i = 0; i < 4; i++) 666 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 667 for (i = 0; i < 4; i++) 668 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 669 for (i = 0; i < 4; i++) 670 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 671 672 for (i = 0; i < 4; i++) 673 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 674 for (i = 0; i < 4; i++) 675 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 676 for (i = 0; i < 32; i++) 677 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 678 for (i = 0; i < 128; i++) 679 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 680 for (i = 0; i < 128; i++) 681 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 682 for (i = 0; i < 4; i++) 683 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 684 685 regs_buff[547] = rd32(E1000_TDFH); 686 regs_buff[548] = rd32(E1000_TDFT); 687 regs_buff[549] = rd32(E1000_TDFHS); 688 regs_buff[550] = rd32(E1000_TDFPC); 689 690 if (hw->mac.type > e1000_82580) { 691 regs_buff[551] = adapter->stats.o2bgptc; 692 regs_buff[552] = adapter->stats.b2ospc; 693 regs_buff[553] = adapter->stats.o2bspc; 694 regs_buff[554] = adapter->stats.b2ogprc; 695 } 696 697 if (hw->mac.type != e1000_82576) 698 return; 699 for (i = 0; i < 12; i++) 700 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 701 for (i = 0; i < 4; i++) 702 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 703 for (i = 0; i < 12; i++) 704 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 705 for (i = 0; i < 12; i++) 706 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 713 for (i = 0; i < 12; i++) 714 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 715 716 for (i = 0; i < 12; i++) 717 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 718 for (i = 0; i < 12; i++) 719 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 720 for (i = 0; i < 12; i++) 721 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 722 for (i = 0; i < 12; i++) 723 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 724 for (i = 0; i < 12; i++) 725 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 726 for (i = 0; i < 12; i++) 727 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 728 for (i = 0; i < 12; i++) 729 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 730 for (i = 0; i < 12; i++) 731 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 732 } 733 734 static int igb_get_eeprom_len(struct net_device *netdev) 735 { 736 struct igb_adapter *adapter = netdev_priv(netdev); 737 return adapter->hw.nvm.word_size * 2; 738 } 739 740 static int igb_get_eeprom(struct net_device *netdev, 741 struct ethtool_eeprom *eeprom, u8 *bytes) 742 { 743 struct igb_adapter *adapter = netdev_priv(netdev); 744 struct e1000_hw *hw = &adapter->hw; 745 u16 *eeprom_buff; 746 int first_word, last_word; 747 int ret_val = 0; 748 u16 i; 749 750 if (eeprom->len == 0) 751 return -EINVAL; 752 753 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 754 755 first_word = eeprom->offset >> 1; 756 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 757 758 eeprom_buff = kmalloc(sizeof(u16) * 759 (last_word - first_word + 1), GFP_KERNEL); 760 if (!eeprom_buff) 761 return -ENOMEM; 762 763 if (hw->nvm.type == e1000_nvm_eeprom_spi) 764 ret_val = hw->nvm.ops.read(hw, first_word, 765 last_word - first_word + 1, 766 eeprom_buff); 767 else { 768 for (i = 0; i < last_word - first_word + 1; i++) { 769 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 770 &eeprom_buff[i]); 771 if (ret_val) 772 break; 773 } 774 } 775 776 /* Device's eeprom is always little-endian, word addressable */ 777 for (i = 0; i < last_word - first_word + 1; i++) 778 le16_to_cpus(&eeprom_buff[i]); 779 780 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 781 eeprom->len); 782 kfree(eeprom_buff); 783 784 return ret_val; 785 } 786 787 static int igb_set_eeprom(struct net_device *netdev, 788 struct ethtool_eeprom *eeprom, u8 *bytes) 789 { 790 struct igb_adapter *adapter = netdev_priv(netdev); 791 struct e1000_hw *hw = &adapter->hw; 792 u16 *eeprom_buff; 793 void *ptr; 794 int max_len, first_word, last_word, ret_val = 0; 795 u16 i; 796 797 if (eeprom->len == 0) 798 return -EOPNOTSUPP; 799 800 if ((hw->mac.type >= e1000_i210) && 801 !igb_get_flash_presence_i210(hw)) { 802 return -EOPNOTSUPP; 803 } 804 805 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 806 return -EFAULT; 807 808 max_len = hw->nvm.word_size * 2; 809 810 first_word = eeprom->offset >> 1; 811 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 812 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 813 if (!eeprom_buff) 814 return -ENOMEM; 815 816 ptr = (void *)eeprom_buff; 817 818 if (eeprom->offset & 1) { 819 /* need read/modify/write of first changed EEPROM word 820 * only the second byte of the word is being modified 821 */ 822 ret_val = hw->nvm.ops.read(hw, first_word, 1, 823 &eeprom_buff[0]); 824 ptr++; 825 } 826 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 827 /* need read/modify/write of last changed EEPROM word 828 * only the first byte of the word is being modified 829 */ 830 ret_val = hw->nvm.ops.read(hw, last_word, 1, 831 &eeprom_buff[last_word - first_word]); 832 } 833 834 /* Device's eeprom is always little-endian, word addressable */ 835 for (i = 0; i < last_word - first_word + 1; i++) 836 le16_to_cpus(&eeprom_buff[i]); 837 838 memcpy(ptr, bytes, eeprom->len); 839 840 for (i = 0; i < last_word - first_word + 1; i++) 841 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 842 843 ret_val = hw->nvm.ops.write(hw, first_word, 844 last_word - first_word + 1, eeprom_buff); 845 846 /* Update the checksum if nvm write succeeded */ 847 if (ret_val == 0) 848 hw->nvm.ops.update(hw); 849 850 igb_set_fw_version(adapter); 851 kfree(eeprom_buff); 852 return ret_val; 853 } 854 855 static void igb_get_drvinfo(struct net_device *netdev, 856 struct ethtool_drvinfo *drvinfo) 857 { 858 struct igb_adapter *adapter = netdev_priv(netdev); 859 860 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 861 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 862 863 /* EEPROM image version # is reported as firmware version # for 864 * 82575 controllers 865 */ 866 strlcpy(drvinfo->fw_version, adapter->fw_version, 867 sizeof(drvinfo->fw_version)); 868 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 869 sizeof(drvinfo->bus_info)); 870 871 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN; 872 } 873 874 static void igb_get_ringparam(struct net_device *netdev, 875 struct ethtool_ringparam *ring) 876 { 877 struct igb_adapter *adapter = netdev_priv(netdev); 878 879 ring->rx_max_pending = IGB_MAX_RXD; 880 ring->tx_max_pending = IGB_MAX_TXD; 881 ring->rx_pending = adapter->rx_ring_count; 882 ring->tx_pending = adapter->tx_ring_count; 883 } 884 885 static int igb_set_ringparam(struct net_device *netdev, 886 struct ethtool_ringparam *ring) 887 { 888 struct igb_adapter *adapter = netdev_priv(netdev); 889 struct igb_ring *temp_ring; 890 int i, err = 0; 891 u16 new_rx_count, new_tx_count; 892 893 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 894 return -EINVAL; 895 896 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 897 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 898 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 899 900 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 901 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 902 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 903 904 if ((new_tx_count == adapter->tx_ring_count) && 905 (new_rx_count == adapter->rx_ring_count)) { 906 /* nothing to do */ 907 return 0; 908 } 909 910 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 911 usleep_range(1000, 2000); 912 913 if (!netif_running(adapter->netdev)) { 914 for (i = 0; i < adapter->num_tx_queues; i++) 915 adapter->tx_ring[i]->count = new_tx_count; 916 for (i = 0; i < adapter->num_rx_queues; i++) 917 adapter->rx_ring[i]->count = new_rx_count; 918 adapter->tx_ring_count = new_tx_count; 919 adapter->rx_ring_count = new_rx_count; 920 goto clear_reset; 921 } 922 923 if (adapter->num_tx_queues > adapter->num_rx_queues) 924 temp_ring = vmalloc(adapter->num_tx_queues * 925 sizeof(struct igb_ring)); 926 else 927 temp_ring = vmalloc(adapter->num_rx_queues * 928 sizeof(struct igb_ring)); 929 930 if (!temp_ring) { 931 err = -ENOMEM; 932 goto clear_reset; 933 } 934 935 igb_down(adapter); 936 937 /* We can't just free everything and then setup again, 938 * because the ISRs in MSI-X mode get passed pointers 939 * to the Tx and Rx ring structs. 940 */ 941 if (new_tx_count != adapter->tx_ring_count) { 942 for (i = 0; i < adapter->num_tx_queues; i++) { 943 memcpy(&temp_ring[i], adapter->tx_ring[i], 944 sizeof(struct igb_ring)); 945 946 temp_ring[i].count = new_tx_count; 947 err = igb_setup_tx_resources(&temp_ring[i]); 948 if (err) { 949 while (i) { 950 i--; 951 igb_free_tx_resources(&temp_ring[i]); 952 } 953 goto err_setup; 954 } 955 } 956 957 for (i = 0; i < adapter->num_tx_queues; i++) { 958 igb_free_tx_resources(adapter->tx_ring[i]); 959 960 memcpy(adapter->tx_ring[i], &temp_ring[i], 961 sizeof(struct igb_ring)); 962 } 963 964 adapter->tx_ring_count = new_tx_count; 965 } 966 967 if (new_rx_count != adapter->rx_ring_count) { 968 for (i = 0; i < adapter->num_rx_queues; i++) { 969 memcpy(&temp_ring[i], adapter->rx_ring[i], 970 sizeof(struct igb_ring)); 971 972 temp_ring[i].count = new_rx_count; 973 err = igb_setup_rx_resources(&temp_ring[i]); 974 if (err) { 975 while (i) { 976 i--; 977 igb_free_rx_resources(&temp_ring[i]); 978 } 979 goto err_setup; 980 } 981 982 } 983 984 for (i = 0; i < adapter->num_rx_queues; i++) { 985 igb_free_rx_resources(adapter->rx_ring[i]); 986 987 memcpy(adapter->rx_ring[i], &temp_ring[i], 988 sizeof(struct igb_ring)); 989 } 990 991 adapter->rx_ring_count = new_rx_count; 992 } 993 err_setup: 994 igb_up(adapter); 995 vfree(temp_ring); 996 clear_reset: 997 clear_bit(__IGB_RESETTING, &adapter->state); 998 return err; 999 } 1000 1001 /* ethtool register test data */ 1002 struct igb_reg_test { 1003 u16 reg; 1004 u16 reg_offset; 1005 u16 array_len; 1006 u16 test_type; 1007 u32 mask; 1008 u32 write; 1009 }; 1010 1011 /* In the hardware, registers are laid out either singly, in arrays 1012 * spaced 0x100 bytes apart, or in contiguous tables. We assume 1013 * most tests take place on arrays or single registers (handled 1014 * as a single-element array) and special-case the tables. 1015 * Table tests are always pattern tests. 1016 * 1017 * We also make provision for some required setup steps by specifying 1018 * registers to be written without any read-back testing. 1019 */ 1020 1021 #define PATTERN_TEST 1 1022 #define SET_READ_TEST 2 1023 #define WRITE_NO_TEST 3 1024 #define TABLE32_TEST 4 1025 #define TABLE64_TEST_LO 5 1026 #define TABLE64_TEST_HI 6 1027 1028 /* i210 reg test */ 1029 static struct igb_reg_test reg_test_i210[] = { 1030 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1031 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1032 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1033 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1034 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1035 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1036 /* RDH is read-only for i210, only test RDT. */ 1037 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1038 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1039 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1040 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1041 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1042 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1043 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1044 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1045 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1046 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1047 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1048 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1049 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1050 0xFFFFFFFF, 0xFFFFFFFF }, 1051 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1052 0x900FFFFF, 0xFFFFFFFF }, 1053 { E1000_MTA, 0, 128, TABLE32_TEST, 1054 0xFFFFFFFF, 0xFFFFFFFF }, 1055 { 0, 0, 0, 0, 0 } 1056 }; 1057 1058 /* i350 reg test */ 1059 static struct igb_reg_test reg_test_i350[] = { 1060 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1061 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1062 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1063 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1064 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1065 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1066 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1067 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1068 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1069 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1070 /* RDH is read-only for i350, only test RDT. */ 1071 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1072 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1073 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1074 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1075 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1076 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1077 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1078 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1079 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1080 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1081 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1082 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1083 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1084 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1085 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1086 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1087 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1088 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1089 0xFFFFFFFF, 0xFFFFFFFF }, 1090 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1091 0xC3FFFFFF, 0xFFFFFFFF }, 1092 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1093 0xFFFFFFFF, 0xFFFFFFFF }, 1094 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1095 0xC3FFFFFF, 0xFFFFFFFF }, 1096 { E1000_MTA, 0, 128, TABLE32_TEST, 1097 0xFFFFFFFF, 0xFFFFFFFF }, 1098 { 0, 0, 0, 0 } 1099 }; 1100 1101 /* 82580 reg test */ 1102 static struct igb_reg_test reg_test_82580[] = { 1103 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1104 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1105 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1106 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1107 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1108 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1109 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1110 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1111 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1112 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1113 /* RDH is read-only for 82580, only test RDT. */ 1114 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1115 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1116 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1117 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1118 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1119 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1120 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1121 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1122 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1123 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1124 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1125 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1126 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1127 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1128 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1129 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1130 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1131 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1132 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1134 0x83FFFFFF, 0xFFFFFFFF }, 1135 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1136 0xFFFFFFFF, 0xFFFFFFFF }, 1137 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1138 0x83FFFFFF, 0xFFFFFFFF }, 1139 { E1000_MTA, 0, 128, TABLE32_TEST, 1140 0xFFFFFFFF, 0xFFFFFFFF }, 1141 { 0, 0, 0, 0 } 1142 }; 1143 1144 /* 82576 reg test */ 1145 static struct igb_reg_test reg_test_82576[] = { 1146 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1147 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1148 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1149 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1150 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1151 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1152 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1153 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1154 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1155 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1156 /* Enable all RX queues before testing. */ 1157 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1158 E1000_RXDCTL_QUEUE_ENABLE }, 1159 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1160 E1000_RXDCTL_QUEUE_ENABLE }, 1161 /* RDH is read-only for 82576, only test RDT. */ 1162 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1163 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1164 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1165 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1166 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1167 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1168 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1169 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1170 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1171 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1172 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1173 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1174 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1175 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1176 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1177 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1178 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1179 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1180 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1181 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1182 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1183 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1184 { 0, 0, 0, 0 } 1185 }; 1186 1187 /* 82575 register test */ 1188 static struct igb_reg_test reg_test_82575[] = { 1189 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1190 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1191 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1192 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1193 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1194 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1195 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1196 /* Enable all four RX queues before testing. */ 1197 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1198 E1000_RXDCTL_QUEUE_ENABLE }, 1199 /* RDH is read-only for 82575, only test RDT. */ 1200 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1201 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1202 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1203 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1204 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1205 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1206 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1207 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1208 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1209 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1210 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1211 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1212 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1213 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1214 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1215 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1216 { 0, 0, 0, 0 } 1217 }; 1218 1219 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1220 int reg, u32 mask, u32 write) 1221 { 1222 struct e1000_hw *hw = &adapter->hw; 1223 u32 pat, val; 1224 static const u32 _test[] = { 1225 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1226 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1227 wr32(reg, (_test[pat] & write)); 1228 val = rd32(reg) & mask; 1229 if (val != (_test[pat] & write & mask)) { 1230 dev_err(&adapter->pdev->dev, 1231 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1232 reg, val, (_test[pat] & write & mask)); 1233 *data = reg; 1234 return true; 1235 } 1236 } 1237 1238 return false; 1239 } 1240 1241 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1242 int reg, u32 mask, u32 write) 1243 { 1244 struct e1000_hw *hw = &adapter->hw; 1245 u32 val; 1246 1247 wr32(reg, write & mask); 1248 val = rd32(reg); 1249 if ((write & mask) != (val & mask)) { 1250 dev_err(&adapter->pdev->dev, 1251 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1252 reg, (val & mask), (write & mask)); 1253 *data = reg; 1254 return true; 1255 } 1256 1257 return false; 1258 } 1259 1260 #define REG_PATTERN_TEST(reg, mask, write) \ 1261 do { \ 1262 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1263 return 1; \ 1264 } while (0) 1265 1266 #define REG_SET_AND_CHECK(reg, mask, write) \ 1267 do { \ 1268 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1269 return 1; \ 1270 } while (0) 1271 1272 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1273 { 1274 struct e1000_hw *hw = &adapter->hw; 1275 struct igb_reg_test *test; 1276 u32 value, before, after; 1277 u32 i, toggle; 1278 1279 switch (adapter->hw.mac.type) { 1280 case e1000_i350: 1281 case e1000_i354: 1282 test = reg_test_i350; 1283 toggle = 0x7FEFF3FF; 1284 break; 1285 case e1000_i210: 1286 case e1000_i211: 1287 test = reg_test_i210; 1288 toggle = 0x7FEFF3FF; 1289 break; 1290 case e1000_82580: 1291 test = reg_test_82580; 1292 toggle = 0x7FEFF3FF; 1293 break; 1294 case e1000_82576: 1295 test = reg_test_82576; 1296 toggle = 0x7FFFF3FF; 1297 break; 1298 default: 1299 test = reg_test_82575; 1300 toggle = 0x7FFFF3FF; 1301 break; 1302 } 1303 1304 /* Because the status register is such a special case, 1305 * we handle it separately from the rest of the register 1306 * tests. Some bits are read-only, some toggle, and some 1307 * are writable on newer MACs. 1308 */ 1309 before = rd32(E1000_STATUS); 1310 value = (rd32(E1000_STATUS) & toggle); 1311 wr32(E1000_STATUS, toggle); 1312 after = rd32(E1000_STATUS) & toggle; 1313 if (value != after) { 1314 dev_err(&adapter->pdev->dev, 1315 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1316 after, value); 1317 *data = 1; 1318 return 1; 1319 } 1320 /* restore previous status */ 1321 wr32(E1000_STATUS, before); 1322 1323 /* Perform the remainder of the register test, looping through 1324 * the test table until we either fail or reach the null entry. 1325 */ 1326 while (test->reg) { 1327 for (i = 0; i < test->array_len; i++) { 1328 switch (test->test_type) { 1329 case PATTERN_TEST: 1330 REG_PATTERN_TEST(test->reg + 1331 (i * test->reg_offset), 1332 test->mask, 1333 test->write); 1334 break; 1335 case SET_READ_TEST: 1336 REG_SET_AND_CHECK(test->reg + 1337 (i * test->reg_offset), 1338 test->mask, 1339 test->write); 1340 break; 1341 case WRITE_NO_TEST: 1342 writel(test->write, 1343 (adapter->hw.hw_addr + test->reg) 1344 + (i * test->reg_offset)); 1345 break; 1346 case TABLE32_TEST: 1347 REG_PATTERN_TEST(test->reg + (i * 4), 1348 test->mask, 1349 test->write); 1350 break; 1351 case TABLE64_TEST_LO: 1352 REG_PATTERN_TEST(test->reg + (i * 8), 1353 test->mask, 1354 test->write); 1355 break; 1356 case TABLE64_TEST_HI: 1357 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1358 test->mask, 1359 test->write); 1360 break; 1361 } 1362 } 1363 test++; 1364 } 1365 1366 *data = 0; 1367 return 0; 1368 } 1369 1370 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1371 { 1372 struct e1000_hw *hw = &adapter->hw; 1373 1374 *data = 0; 1375 1376 /* Validate eeprom on all parts but flashless */ 1377 switch (hw->mac.type) { 1378 case e1000_i210: 1379 case e1000_i211: 1380 if (igb_get_flash_presence_i210(hw)) { 1381 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1382 *data = 2; 1383 } 1384 break; 1385 default: 1386 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1387 *data = 2; 1388 break; 1389 } 1390 1391 return *data; 1392 } 1393 1394 static irqreturn_t igb_test_intr(int irq, void *data) 1395 { 1396 struct igb_adapter *adapter = (struct igb_adapter *) data; 1397 struct e1000_hw *hw = &adapter->hw; 1398 1399 adapter->test_icr |= rd32(E1000_ICR); 1400 1401 return IRQ_HANDLED; 1402 } 1403 1404 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1405 { 1406 struct e1000_hw *hw = &adapter->hw; 1407 struct net_device *netdev = adapter->netdev; 1408 u32 mask, ics_mask, i = 0, shared_int = true; 1409 u32 irq = adapter->pdev->irq; 1410 1411 *data = 0; 1412 1413 /* Hook up test interrupt handler just for this test */ 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1415 if (request_irq(adapter->msix_entries[0].vector, 1416 igb_test_intr, 0, netdev->name, adapter)) { 1417 *data = 1; 1418 return -1; 1419 } 1420 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1421 shared_int = false; 1422 if (request_irq(irq, 1423 igb_test_intr, 0, netdev->name, adapter)) { 1424 *data = 1; 1425 return -1; 1426 } 1427 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1428 netdev->name, adapter)) { 1429 shared_int = false; 1430 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1431 netdev->name, adapter)) { 1432 *data = 1; 1433 return -1; 1434 } 1435 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1436 (shared_int ? "shared" : "unshared")); 1437 1438 /* Disable all the interrupts */ 1439 wr32(E1000_IMC, ~0); 1440 wrfl(); 1441 usleep_range(10000, 11000); 1442 1443 /* Define all writable bits for ICS */ 1444 switch (hw->mac.type) { 1445 case e1000_82575: 1446 ics_mask = 0x37F47EDD; 1447 break; 1448 case e1000_82576: 1449 ics_mask = 0x77D4FBFD; 1450 break; 1451 case e1000_82580: 1452 ics_mask = 0x77DCFED5; 1453 break; 1454 case e1000_i350: 1455 case e1000_i354: 1456 case e1000_i210: 1457 case e1000_i211: 1458 ics_mask = 0x77DCFED5; 1459 break; 1460 default: 1461 ics_mask = 0x7FFFFFFF; 1462 break; 1463 } 1464 1465 /* Test each interrupt */ 1466 for (; i < 31; i++) { 1467 /* Interrupt to test */ 1468 mask = BIT(i); 1469 1470 if (!(mask & ics_mask)) 1471 continue; 1472 1473 if (!shared_int) { 1474 /* Disable the interrupt to be reported in 1475 * the cause register and then force the same 1476 * interrupt and see if one gets posted. If 1477 * an interrupt was posted to the bus, the 1478 * test failed. 1479 */ 1480 adapter->test_icr = 0; 1481 1482 /* Flush any pending interrupts */ 1483 wr32(E1000_ICR, ~0); 1484 1485 wr32(E1000_IMC, mask); 1486 wr32(E1000_ICS, mask); 1487 wrfl(); 1488 usleep_range(10000, 11000); 1489 1490 if (adapter->test_icr & mask) { 1491 *data = 3; 1492 break; 1493 } 1494 } 1495 1496 /* Enable the interrupt to be reported in 1497 * the cause register and then force the same 1498 * interrupt and see if one gets posted. If 1499 * an interrupt was not posted to the bus, the 1500 * test failed. 1501 */ 1502 adapter->test_icr = 0; 1503 1504 /* Flush any pending interrupts */ 1505 wr32(E1000_ICR, ~0); 1506 1507 wr32(E1000_IMS, mask); 1508 wr32(E1000_ICS, mask); 1509 wrfl(); 1510 usleep_range(10000, 11000); 1511 1512 if (!(adapter->test_icr & mask)) { 1513 *data = 4; 1514 break; 1515 } 1516 1517 if (!shared_int) { 1518 /* Disable the other interrupts to be reported in 1519 * the cause register and then force the other 1520 * interrupts and see if any get posted. If 1521 * an interrupt was posted to the bus, the 1522 * test failed. 1523 */ 1524 adapter->test_icr = 0; 1525 1526 /* Flush any pending interrupts */ 1527 wr32(E1000_ICR, ~0); 1528 1529 wr32(E1000_IMC, ~mask); 1530 wr32(E1000_ICS, ~mask); 1531 wrfl(); 1532 usleep_range(10000, 11000); 1533 1534 if (adapter->test_icr & mask) { 1535 *data = 5; 1536 break; 1537 } 1538 } 1539 } 1540 1541 /* Disable all the interrupts */ 1542 wr32(E1000_IMC, ~0); 1543 wrfl(); 1544 usleep_range(10000, 11000); 1545 1546 /* Unhook test interrupt handler */ 1547 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1548 free_irq(adapter->msix_entries[0].vector, adapter); 1549 else 1550 free_irq(irq, adapter); 1551 1552 return *data; 1553 } 1554 1555 static void igb_free_desc_rings(struct igb_adapter *adapter) 1556 { 1557 igb_free_tx_resources(&adapter->test_tx_ring); 1558 igb_free_rx_resources(&adapter->test_rx_ring); 1559 } 1560 1561 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1562 { 1563 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1564 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1565 struct e1000_hw *hw = &adapter->hw; 1566 int ret_val; 1567 1568 /* Setup Tx descriptor ring and Tx buffers */ 1569 tx_ring->count = IGB_DEFAULT_TXD; 1570 tx_ring->dev = &adapter->pdev->dev; 1571 tx_ring->netdev = adapter->netdev; 1572 tx_ring->reg_idx = adapter->vfs_allocated_count; 1573 1574 if (igb_setup_tx_resources(tx_ring)) { 1575 ret_val = 1; 1576 goto err_nomem; 1577 } 1578 1579 igb_setup_tctl(adapter); 1580 igb_configure_tx_ring(adapter, tx_ring); 1581 1582 /* Setup Rx descriptor ring and Rx buffers */ 1583 rx_ring->count = IGB_DEFAULT_RXD; 1584 rx_ring->dev = &adapter->pdev->dev; 1585 rx_ring->netdev = adapter->netdev; 1586 rx_ring->reg_idx = adapter->vfs_allocated_count; 1587 1588 if (igb_setup_rx_resources(rx_ring)) { 1589 ret_val = 3; 1590 goto err_nomem; 1591 } 1592 1593 /* set the default queue to queue 0 of PF */ 1594 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1595 1596 /* enable receive ring */ 1597 igb_setup_rctl(adapter); 1598 igb_configure_rx_ring(adapter, rx_ring); 1599 1600 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1601 1602 return 0; 1603 1604 err_nomem: 1605 igb_free_desc_rings(adapter); 1606 return ret_val; 1607 } 1608 1609 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1610 { 1611 struct e1000_hw *hw = &adapter->hw; 1612 1613 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1614 igb_write_phy_reg(hw, 29, 0x001F); 1615 igb_write_phy_reg(hw, 30, 0x8FFC); 1616 igb_write_phy_reg(hw, 29, 0x001A); 1617 igb_write_phy_reg(hw, 30, 0x8FF0); 1618 } 1619 1620 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1621 { 1622 struct e1000_hw *hw = &adapter->hw; 1623 u32 ctrl_reg = 0; 1624 1625 hw->mac.autoneg = false; 1626 1627 if (hw->phy.type == e1000_phy_m88) { 1628 if (hw->phy.id != I210_I_PHY_ID) { 1629 /* Auto-MDI/MDIX Off */ 1630 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1631 /* reset to update Auto-MDI/MDIX */ 1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1633 /* autoneg off */ 1634 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1635 } else { 1636 /* force 1000, set loopback */ 1637 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1638 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1639 } 1640 } else if (hw->phy.type == e1000_phy_82580) { 1641 /* enable MII loopback */ 1642 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1643 } 1644 1645 /* add small delay to avoid loopback test failure */ 1646 msleep(50); 1647 1648 /* force 1000, set loopback */ 1649 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1650 1651 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1652 ctrl_reg = rd32(E1000_CTRL); 1653 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1654 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1655 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1656 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1657 E1000_CTRL_FD | /* Force Duplex to FULL */ 1658 E1000_CTRL_SLU); /* Set link up enable bit */ 1659 1660 if (hw->phy.type == e1000_phy_m88) 1661 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1662 1663 wr32(E1000_CTRL, ctrl_reg); 1664 1665 /* Disable the receiver on the PHY so when a cable is plugged in, the 1666 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1667 */ 1668 if (hw->phy.type == e1000_phy_m88) 1669 igb_phy_disable_receiver(adapter); 1670 1671 mdelay(500); 1672 return 0; 1673 } 1674 1675 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1676 { 1677 return igb_integrated_phy_loopback(adapter); 1678 } 1679 1680 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1681 { 1682 struct e1000_hw *hw = &adapter->hw; 1683 u32 reg; 1684 1685 reg = rd32(E1000_CTRL_EXT); 1686 1687 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1688 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1689 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1690 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1691 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1693 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1694 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1695 /* Enable DH89xxCC MPHY for near end loopback */ 1696 reg = rd32(E1000_MPHY_ADDR_CTL); 1697 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1698 E1000_MPHY_PCS_CLK_REG_OFFSET; 1699 wr32(E1000_MPHY_ADDR_CTL, reg); 1700 1701 reg = rd32(E1000_MPHY_DATA); 1702 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1703 wr32(E1000_MPHY_DATA, reg); 1704 } 1705 1706 reg = rd32(E1000_RCTL); 1707 reg |= E1000_RCTL_LBM_TCVR; 1708 wr32(E1000_RCTL, reg); 1709 1710 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1711 1712 reg = rd32(E1000_CTRL); 1713 reg &= ~(E1000_CTRL_RFCE | 1714 E1000_CTRL_TFCE | 1715 E1000_CTRL_LRST); 1716 reg |= E1000_CTRL_SLU | 1717 E1000_CTRL_FD; 1718 wr32(E1000_CTRL, reg); 1719 1720 /* Unset switch control to serdes energy detect */ 1721 reg = rd32(E1000_CONNSW); 1722 reg &= ~E1000_CONNSW_ENRGSRC; 1723 wr32(E1000_CONNSW, reg); 1724 1725 /* Unset sigdetect for SERDES loopback on 1726 * 82580 and newer devices. 1727 */ 1728 if (hw->mac.type >= e1000_82580) { 1729 reg = rd32(E1000_PCS_CFG0); 1730 reg |= E1000_PCS_CFG_IGN_SD; 1731 wr32(E1000_PCS_CFG0, reg); 1732 } 1733 1734 /* Set PCS register for forced speed */ 1735 reg = rd32(E1000_PCS_LCTL); 1736 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1737 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1738 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1739 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1740 E1000_PCS_LCTL_FSD | /* Force Speed */ 1741 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1742 wr32(E1000_PCS_LCTL, reg); 1743 1744 return 0; 1745 } 1746 1747 return igb_set_phy_loopback(adapter); 1748 } 1749 1750 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1751 { 1752 struct e1000_hw *hw = &adapter->hw; 1753 u32 rctl; 1754 u16 phy_reg; 1755 1756 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1757 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1758 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1759 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1760 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1761 u32 reg; 1762 1763 /* Disable near end loopback on DH89xxCC */ 1764 reg = rd32(E1000_MPHY_ADDR_CTL); 1765 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1766 E1000_MPHY_PCS_CLK_REG_OFFSET; 1767 wr32(E1000_MPHY_ADDR_CTL, reg); 1768 1769 reg = rd32(E1000_MPHY_DATA); 1770 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1771 wr32(E1000_MPHY_DATA, reg); 1772 } 1773 1774 rctl = rd32(E1000_RCTL); 1775 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1776 wr32(E1000_RCTL, rctl); 1777 1778 hw->mac.autoneg = true; 1779 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1780 if (phy_reg & MII_CR_LOOPBACK) { 1781 phy_reg &= ~MII_CR_LOOPBACK; 1782 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1783 igb_phy_sw_reset(hw); 1784 } 1785 } 1786 1787 static void igb_create_lbtest_frame(struct sk_buff *skb, 1788 unsigned int frame_size) 1789 { 1790 memset(skb->data, 0xFF, frame_size); 1791 frame_size /= 2; 1792 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1793 memset(&skb->data[frame_size + 10], 0xBE, 1); 1794 memset(&skb->data[frame_size + 12], 0xAF, 1); 1795 } 1796 1797 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1798 unsigned int frame_size) 1799 { 1800 unsigned char *data; 1801 bool match = true; 1802 1803 frame_size >>= 1; 1804 1805 data = kmap(rx_buffer->page); 1806 1807 if (data[3] != 0xFF || 1808 data[frame_size + 10] != 0xBE || 1809 data[frame_size + 12] != 0xAF) 1810 match = false; 1811 1812 kunmap(rx_buffer->page); 1813 1814 return match; 1815 } 1816 1817 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1818 struct igb_ring *tx_ring, 1819 unsigned int size) 1820 { 1821 union e1000_adv_rx_desc *rx_desc; 1822 struct igb_rx_buffer *rx_buffer_info; 1823 struct igb_tx_buffer *tx_buffer_info; 1824 u16 rx_ntc, tx_ntc, count = 0; 1825 1826 /* initialize next to clean and descriptor values */ 1827 rx_ntc = rx_ring->next_to_clean; 1828 tx_ntc = tx_ring->next_to_clean; 1829 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1830 1831 while (rx_desc->wb.upper.length) { 1832 /* check Rx buffer */ 1833 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1834 1835 /* sync Rx buffer for CPU read */ 1836 dma_sync_single_for_cpu(rx_ring->dev, 1837 rx_buffer_info->dma, 1838 size, 1839 DMA_FROM_DEVICE); 1840 1841 /* verify contents of skb */ 1842 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1843 count++; 1844 1845 /* sync Rx buffer for device write */ 1846 dma_sync_single_for_device(rx_ring->dev, 1847 rx_buffer_info->dma, 1848 size, 1849 DMA_FROM_DEVICE); 1850 1851 /* unmap buffer on Tx side */ 1852 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1853 1854 /* Free all the Tx ring sk_buffs */ 1855 dev_kfree_skb_any(tx_buffer_info->skb); 1856 1857 /* unmap skb header data */ 1858 dma_unmap_single(tx_ring->dev, 1859 dma_unmap_addr(tx_buffer_info, dma), 1860 dma_unmap_len(tx_buffer_info, len), 1861 DMA_TO_DEVICE); 1862 dma_unmap_len_set(tx_buffer_info, len, 0); 1863 1864 /* increment Rx/Tx next to clean counters */ 1865 rx_ntc++; 1866 if (rx_ntc == rx_ring->count) 1867 rx_ntc = 0; 1868 tx_ntc++; 1869 if (tx_ntc == tx_ring->count) 1870 tx_ntc = 0; 1871 1872 /* fetch next descriptor */ 1873 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1874 } 1875 1876 netdev_tx_reset_queue(txring_txq(tx_ring)); 1877 1878 /* re-map buffers to ring, store next to clean values */ 1879 igb_alloc_rx_buffers(rx_ring, count); 1880 rx_ring->next_to_clean = rx_ntc; 1881 tx_ring->next_to_clean = tx_ntc; 1882 1883 return count; 1884 } 1885 1886 static int igb_run_loopback_test(struct igb_adapter *adapter) 1887 { 1888 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1889 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1890 u16 i, j, lc, good_cnt; 1891 int ret_val = 0; 1892 unsigned int size = IGB_RX_HDR_LEN; 1893 netdev_tx_t tx_ret_val; 1894 struct sk_buff *skb; 1895 1896 /* allocate test skb */ 1897 skb = alloc_skb(size, GFP_KERNEL); 1898 if (!skb) 1899 return 11; 1900 1901 /* place data into test skb */ 1902 igb_create_lbtest_frame(skb, size); 1903 skb_put(skb, size); 1904 1905 /* Calculate the loop count based on the largest descriptor ring 1906 * The idea is to wrap the largest ring a number of times using 64 1907 * send/receive pairs during each loop 1908 */ 1909 1910 if (rx_ring->count <= tx_ring->count) 1911 lc = ((tx_ring->count / 64) * 2) + 1; 1912 else 1913 lc = ((rx_ring->count / 64) * 2) + 1; 1914 1915 for (j = 0; j <= lc; j++) { /* loop count loop */ 1916 /* reset count of good packets */ 1917 good_cnt = 0; 1918 1919 /* place 64 packets on the transmit queue*/ 1920 for (i = 0; i < 64; i++) { 1921 skb_get(skb); 1922 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1923 if (tx_ret_val == NETDEV_TX_OK) 1924 good_cnt++; 1925 } 1926 1927 if (good_cnt != 64) { 1928 ret_val = 12; 1929 break; 1930 } 1931 1932 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1933 msleep(200); 1934 1935 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1936 if (good_cnt != 64) { 1937 ret_val = 13; 1938 break; 1939 } 1940 } /* end loop count loop */ 1941 1942 /* free the original skb */ 1943 kfree_skb(skb); 1944 1945 return ret_val; 1946 } 1947 1948 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1949 { 1950 /* PHY loopback cannot be performed if SoL/IDER 1951 * sessions are active 1952 */ 1953 if (igb_check_reset_block(&adapter->hw)) { 1954 dev_err(&adapter->pdev->dev, 1955 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1956 *data = 0; 1957 goto out; 1958 } 1959 1960 if (adapter->hw.mac.type == e1000_i354) { 1961 dev_info(&adapter->pdev->dev, 1962 "Loopback test not supported on i354.\n"); 1963 *data = 0; 1964 goto out; 1965 } 1966 *data = igb_setup_desc_rings(adapter); 1967 if (*data) 1968 goto out; 1969 *data = igb_setup_loopback_test(adapter); 1970 if (*data) 1971 goto err_loopback; 1972 *data = igb_run_loopback_test(adapter); 1973 igb_loopback_cleanup(adapter); 1974 1975 err_loopback: 1976 igb_free_desc_rings(adapter); 1977 out: 1978 return *data; 1979 } 1980 1981 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1982 { 1983 struct e1000_hw *hw = &adapter->hw; 1984 *data = 0; 1985 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1986 int i = 0; 1987 1988 hw->mac.serdes_has_link = false; 1989 1990 /* On some blade server designs, link establishment 1991 * could take as long as 2-3 minutes 1992 */ 1993 do { 1994 hw->mac.ops.check_for_link(&adapter->hw); 1995 if (hw->mac.serdes_has_link) 1996 return *data; 1997 msleep(20); 1998 } while (i++ < 3750); 1999 2000 *data = 1; 2001 } else { 2002 hw->mac.ops.check_for_link(&adapter->hw); 2003 if (hw->mac.autoneg) 2004 msleep(5000); 2005 2006 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 2007 *data = 1; 2008 } 2009 return *data; 2010 } 2011 2012 static void igb_diag_test(struct net_device *netdev, 2013 struct ethtool_test *eth_test, u64 *data) 2014 { 2015 struct igb_adapter *adapter = netdev_priv(netdev); 2016 u16 autoneg_advertised; 2017 u8 forced_speed_duplex, autoneg; 2018 bool if_running = netif_running(netdev); 2019 2020 set_bit(__IGB_TESTING, &adapter->state); 2021 2022 /* can't do offline tests on media switching devices */ 2023 if (adapter->hw.dev_spec._82575.mas_capable) 2024 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 2025 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2026 /* Offline tests */ 2027 2028 /* save speed, duplex, autoneg settings */ 2029 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2030 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2031 autoneg = adapter->hw.mac.autoneg; 2032 2033 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2034 2035 /* power up link for link test */ 2036 igb_power_up_link(adapter); 2037 2038 /* Link test performed before hardware reset so autoneg doesn't 2039 * interfere with test result 2040 */ 2041 if (igb_link_test(adapter, &data[TEST_LINK])) 2042 eth_test->flags |= ETH_TEST_FL_FAILED; 2043 2044 if (if_running) 2045 /* indicate we're in test mode */ 2046 igb_close(netdev); 2047 else 2048 igb_reset(adapter); 2049 2050 if (igb_reg_test(adapter, &data[TEST_REG])) 2051 eth_test->flags |= ETH_TEST_FL_FAILED; 2052 2053 igb_reset(adapter); 2054 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2055 eth_test->flags |= ETH_TEST_FL_FAILED; 2056 2057 igb_reset(adapter); 2058 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2059 eth_test->flags |= ETH_TEST_FL_FAILED; 2060 2061 igb_reset(adapter); 2062 /* power up link for loopback test */ 2063 igb_power_up_link(adapter); 2064 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2065 eth_test->flags |= ETH_TEST_FL_FAILED; 2066 2067 /* restore speed, duplex, autoneg settings */ 2068 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2069 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2070 adapter->hw.mac.autoneg = autoneg; 2071 2072 /* force this routine to wait until autoneg complete/timeout */ 2073 adapter->hw.phy.autoneg_wait_to_complete = true; 2074 igb_reset(adapter); 2075 adapter->hw.phy.autoneg_wait_to_complete = false; 2076 2077 clear_bit(__IGB_TESTING, &adapter->state); 2078 if (if_running) 2079 igb_open(netdev); 2080 } else { 2081 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2082 2083 /* PHY is powered down when interface is down */ 2084 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2085 eth_test->flags |= ETH_TEST_FL_FAILED; 2086 else 2087 data[TEST_LINK] = 0; 2088 2089 /* Online tests aren't run; pass by default */ 2090 data[TEST_REG] = 0; 2091 data[TEST_EEP] = 0; 2092 data[TEST_IRQ] = 0; 2093 data[TEST_LOOP] = 0; 2094 2095 clear_bit(__IGB_TESTING, &adapter->state); 2096 } 2097 msleep_interruptible(4 * 1000); 2098 } 2099 2100 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2101 { 2102 struct igb_adapter *adapter = netdev_priv(netdev); 2103 2104 wol->wolopts = 0; 2105 2106 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2107 return; 2108 2109 wol->supported = WAKE_UCAST | WAKE_MCAST | 2110 WAKE_BCAST | WAKE_MAGIC | 2111 WAKE_PHY; 2112 2113 /* apply any specific unsupported masks here */ 2114 switch (adapter->hw.device_id) { 2115 default: 2116 break; 2117 } 2118 2119 if (adapter->wol & E1000_WUFC_EX) 2120 wol->wolopts |= WAKE_UCAST; 2121 if (adapter->wol & E1000_WUFC_MC) 2122 wol->wolopts |= WAKE_MCAST; 2123 if (adapter->wol & E1000_WUFC_BC) 2124 wol->wolopts |= WAKE_BCAST; 2125 if (adapter->wol & E1000_WUFC_MAG) 2126 wol->wolopts |= WAKE_MAGIC; 2127 if (adapter->wol & E1000_WUFC_LNKC) 2128 wol->wolopts |= WAKE_PHY; 2129 } 2130 2131 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2132 { 2133 struct igb_adapter *adapter = netdev_priv(netdev); 2134 2135 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2136 return -EOPNOTSUPP; 2137 2138 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2139 return wol->wolopts ? -EOPNOTSUPP : 0; 2140 2141 /* these settings will always override what we currently have */ 2142 adapter->wol = 0; 2143 2144 if (wol->wolopts & WAKE_UCAST) 2145 adapter->wol |= E1000_WUFC_EX; 2146 if (wol->wolopts & WAKE_MCAST) 2147 adapter->wol |= E1000_WUFC_MC; 2148 if (wol->wolopts & WAKE_BCAST) 2149 adapter->wol |= E1000_WUFC_BC; 2150 if (wol->wolopts & WAKE_MAGIC) 2151 adapter->wol |= E1000_WUFC_MAG; 2152 if (wol->wolopts & WAKE_PHY) 2153 adapter->wol |= E1000_WUFC_LNKC; 2154 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2155 2156 return 0; 2157 } 2158 2159 /* bit defines for adapter->led_status */ 2160 #define IGB_LED_ON 0 2161 2162 static int igb_set_phys_id(struct net_device *netdev, 2163 enum ethtool_phys_id_state state) 2164 { 2165 struct igb_adapter *adapter = netdev_priv(netdev); 2166 struct e1000_hw *hw = &adapter->hw; 2167 2168 switch (state) { 2169 case ETHTOOL_ID_ACTIVE: 2170 igb_blink_led(hw); 2171 return 2; 2172 case ETHTOOL_ID_ON: 2173 igb_blink_led(hw); 2174 break; 2175 case ETHTOOL_ID_OFF: 2176 igb_led_off(hw); 2177 break; 2178 case ETHTOOL_ID_INACTIVE: 2179 igb_led_off(hw); 2180 clear_bit(IGB_LED_ON, &adapter->led_status); 2181 igb_cleanup_led(hw); 2182 break; 2183 } 2184 2185 return 0; 2186 } 2187 2188 static int igb_set_coalesce(struct net_device *netdev, 2189 struct ethtool_coalesce *ec) 2190 { 2191 struct igb_adapter *adapter = netdev_priv(netdev); 2192 int i; 2193 2194 if (ec->rx_max_coalesced_frames || 2195 ec->rx_coalesce_usecs_irq || 2196 ec->rx_max_coalesced_frames_irq || 2197 ec->tx_max_coalesced_frames || 2198 ec->tx_coalesce_usecs_irq || 2199 ec->stats_block_coalesce_usecs || 2200 ec->use_adaptive_rx_coalesce || 2201 ec->use_adaptive_tx_coalesce || 2202 ec->pkt_rate_low || 2203 ec->rx_coalesce_usecs_low || 2204 ec->rx_max_coalesced_frames_low || 2205 ec->tx_coalesce_usecs_low || 2206 ec->tx_max_coalesced_frames_low || 2207 ec->pkt_rate_high || 2208 ec->rx_coalesce_usecs_high || 2209 ec->rx_max_coalesced_frames_high || 2210 ec->tx_coalesce_usecs_high || 2211 ec->tx_max_coalesced_frames_high || 2212 ec->rate_sample_interval) 2213 return -ENOTSUPP; 2214 2215 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2216 ((ec->rx_coalesce_usecs > 3) && 2217 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2218 (ec->rx_coalesce_usecs == 2)) 2219 return -EINVAL; 2220 2221 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2222 ((ec->tx_coalesce_usecs > 3) && 2223 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2224 (ec->tx_coalesce_usecs == 2)) 2225 return -EINVAL; 2226 2227 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2228 return -EINVAL; 2229 2230 /* If ITR is disabled, disable DMAC */ 2231 if (ec->rx_coalesce_usecs == 0) { 2232 if (adapter->flags & IGB_FLAG_DMAC) 2233 adapter->flags &= ~IGB_FLAG_DMAC; 2234 } 2235 2236 /* convert to rate of irq's per second */ 2237 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2238 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2239 else 2240 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2241 2242 /* convert to rate of irq's per second */ 2243 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2244 adapter->tx_itr_setting = adapter->rx_itr_setting; 2245 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2246 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2247 else 2248 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2249 2250 for (i = 0; i < adapter->num_q_vectors; i++) { 2251 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2252 q_vector->tx.work_limit = adapter->tx_work_limit; 2253 if (q_vector->rx.ring) 2254 q_vector->itr_val = adapter->rx_itr_setting; 2255 else 2256 q_vector->itr_val = adapter->tx_itr_setting; 2257 if (q_vector->itr_val && q_vector->itr_val <= 3) 2258 q_vector->itr_val = IGB_START_ITR; 2259 q_vector->set_itr = 1; 2260 } 2261 2262 return 0; 2263 } 2264 2265 static int igb_get_coalesce(struct net_device *netdev, 2266 struct ethtool_coalesce *ec) 2267 { 2268 struct igb_adapter *adapter = netdev_priv(netdev); 2269 2270 if (adapter->rx_itr_setting <= 3) 2271 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2272 else 2273 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2274 2275 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2276 if (adapter->tx_itr_setting <= 3) 2277 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2278 else 2279 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2280 } 2281 2282 return 0; 2283 } 2284 2285 static int igb_nway_reset(struct net_device *netdev) 2286 { 2287 struct igb_adapter *adapter = netdev_priv(netdev); 2288 if (netif_running(netdev)) 2289 igb_reinit_locked(adapter); 2290 return 0; 2291 } 2292 2293 static int igb_get_sset_count(struct net_device *netdev, int sset) 2294 { 2295 switch (sset) { 2296 case ETH_SS_STATS: 2297 return IGB_STATS_LEN; 2298 case ETH_SS_TEST: 2299 return IGB_TEST_LEN; 2300 case ETH_SS_PRIV_FLAGS: 2301 return IGB_PRIV_FLAGS_STR_LEN; 2302 default: 2303 return -ENOTSUPP; 2304 } 2305 } 2306 2307 static void igb_get_ethtool_stats(struct net_device *netdev, 2308 struct ethtool_stats *stats, u64 *data) 2309 { 2310 struct igb_adapter *adapter = netdev_priv(netdev); 2311 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2312 unsigned int start; 2313 struct igb_ring *ring; 2314 int i, j; 2315 char *p; 2316 2317 spin_lock(&adapter->stats64_lock); 2318 igb_update_stats(adapter, net_stats); 2319 2320 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2321 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2322 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2323 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2324 } 2325 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2326 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2327 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2328 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2329 } 2330 for (j = 0; j < adapter->num_tx_queues; j++) { 2331 u64 restart2; 2332 2333 ring = adapter->tx_ring[j]; 2334 do { 2335 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2336 data[i] = ring->tx_stats.packets; 2337 data[i+1] = ring->tx_stats.bytes; 2338 data[i+2] = ring->tx_stats.restart_queue; 2339 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2340 do { 2341 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2342 restart2 = ring->tx_stats.restart_queue2; 2343 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2344 data[i+2] += restart2; 2345 2346 i += IGB_TX_QUEUE_STATS_LEN; 2347 } 2348 for (j = 0; j < adapter->num_rx_queues; j++) { 2349 ring = adapter->rx_ring[j]; 2350 do { 2351 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2352 data[i] = ring->rx_stats.packets; 2353 data[i+1] = ring->rx_stats.bytes; 2354 data[i+2] = ring->rx_stats.drops; 2355 data[i+3] = ring->rx_stats.csum_err; 2356 data[i+4] = ring->rx_stats.alloc_failed; 2357 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2358 i += IGB_RX_QUEUE_STATS_LEN; 2359 } 2360 spin_unlock(&adapter->stats64_lock); 2361 } 2362 2363 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2364 { 2365 struct igb_adapter *adapter = netdev_priv(netdev); 2366 u8 *p = data; 2367 int i; 2368 2369 switch (stringset) { 2370 case ETH_SS_TEST: 2371 memcpy(data, *igb_gstrings_test, 2372 IGB_TEST_LEN*ETH_GSTRING_LEN); 2373 break; 2374 case ETH_SS_STATS: 2375 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2376 memcpy(p, igb_gstrings_stats[i].stat_string, 2377 ETH_GSTRING_LEN); 2378 p += ETH_GSTRING_LEN; 2379 } 2380 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2381 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2382 ETH_GSTRING_LEN); 2383 p += ETH_GSTRING_LEN; 2384 } 2385 for (i = 0; i < adapter->num_tx_queues; i++) { 2386 sprintf(p, "tx_queue_%u_packets", i); 2387 p += ETH_GSTRING_LEN; 2388 sprintf(p, "tx_queue_%u_bytes", i); 2389 p += ETH_GSTRING_LEN; 2390 sprintf(p, "tx_queue_%u_restart", i); 2391 p += ETH_GSTRING_LEN; 2392 } 2393 for (i = 0; i < adapter->num_rx_queues; i++) { 2394 sprintf(p, "rx_queue_%u_packets", i); 2395 p += ETH_GSTRING_LEN; 2396 sprintf(p, "rx_queue_%u_bytes", i); 2397 p += ETH_GSTRING_LEN; 2398 sprintf(p, "rx_queue_%u_drops", i); 2399 p += ETH_GSTRING_LEN; 2400 sprintf(p, "rx_queue_%u_csum_err", i); 2401 p += ETH_GSTRING_LEN; 2402 sprintf(p, "rx_queue_%u_alloc_failed", i); 2403 p += ETH_GSTRING_LEN; 2404 } 2405 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2406 break; 2407 case ETH_SS_PRIV_FLAGS: 2408 memcpy(data, igb_priv_flags_strings, 2409 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 2410 break; 2411 } 2412 } 2413 2414 static int igb_get_ts_info(struct net_device *dev, 2415 struct ethtool_ts_info *info) 2416 { 2417 struct igb_adapter *adapter = netdev_priv(dev); 2418 2419 if (adapter->ptp_clock) 2420 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2421 else 2422 info->phc_index = -1; 2423 2424 switch (adapter->hw.mac.type) { 2425 case e1000_82575: 2426 info->so_timestamping = 2427 SOF_TIMESTAMPING_TX_SOFTWARE | 2428 SOF_TIMESTAMPING_RX_SOFTWARE | 2429 SOF_TIMESTAMPING_SOFTWARE; 2430 return 0; 2431 case e1000_82576: 2432 case e1000_82580: 2433 case e1000_i350: 2434 case e1000_i354: 2435 case e1000_i210: 2436 case e1000_i211: 2437 info->so_timestamping = 2438 SOF_TIMESTAMPING_TX_SOFTWARE | 2439 SOF_TIMESTAMPING_RX_SOFTWARE | 2440 SOF_TIMESTAMPING_SOFTWARE | 2441 SOF_TIMESTAMPING_TX_HARDWARE | 2442 SOF_TIMESTAMPING_RX_HARDWARE | 2443 SOF_TIMESTAMPING_RAW_HARDWARE; 2444 2445 info->tx_types = 2446 BIT(HWTSTAMP_TX_OFF) | 2447 BIT(HWTSTAMP_TX_ON); 2448 2449 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2450 2451 /* 82576 does not support timestamping all packets. */ 2452 if (adapter->hw.mac.type >= e1000_82580) 2453 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2454 else 2455 info->rx_filters |= 2456 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2457 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2458 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2459 2460 return 0; 2461 default: 2462 return -EOPNOTSUPP; 2463 } 2464 } 2465 2466 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2467 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2468 struct ethtool_rxnfc *cmd) 2469 { 2470 struct ethtool_rx_flow_spec *fsp = &cmd->fs; 2471 struct igb_nfc_filter *rule = NULL; 2472 2473 /* report total rule count */ 2474 cmd->data = IGB_MAX_RXNFC_FILTERS; 2475 2476 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2477 if (fsp->location <= rule->sw_idx) 2478 break; 2479 } 2480 2481 if (!rule || fsp->location != rule->sw_idx) 2482 return -EINVAL; 2483 2484 if (rule->filter.match_flags) { 2485 fsp->flow_type = ETHER_FLOW; 2486 fsp->ring_cookie = rule->action; 2487 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2488 fsp->h_u.ether_spec.h_proto = rule->filter.etype; 2489 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; 2490 } 2491 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) { 2492 fsp->flow_type |= FLOW_EXT; 2493 fsp->h_ext.vlan_tci = rule->filter.vlan_tci; 2494 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK); 2495 } 2496 return 0; 2497 } 2498 return -EINVAL; 2499 } 2500 2501 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter, 2502 struct ethtool_rxnfc *cmd, 2503 u32 *rule_locs) 2504 { 2505 struct igb_nfc_filter *rule; 2506 int cnt = 0; 2507 2508 /* report total rule count */ 2509 cmd->data = IGB_MAX_RXNFC_FILTERS; 2510 2511 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2512 if (cnt == cmd->rule_cnt) 2513 return -EMSGSIZE; 2514 rule_locs[cnt] = rule->sw_idx; 2515 cnt++; 2516 } 2517 2518 cmd->rule_cnt = cnt; 2519 2520 return 0; 2521 } 2522 2523 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2524 struct ethtool_rxnfc *cmd) 2525 { 2526 cmd->data = 0; 2527 2528 /* Report default options for RSS on igb */ 2529 switch (cmd->flow_type) { 2530 case TCP_V4_FLOW: 2531 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2532 /* Fall through */ 2533 case UDP_V4_FLOW: 2534 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2535 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2536 /* Fall through */ 2537 case SCTP_V4_FLOW: 2538 case AH_ESP_V4_FLOW: 2539 case AH_V4_FLOW: 2540 case ESP_V4_FLOW: 2541 case IPV4_FLOW: 2542 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2543 break; 2544 case TCP_V6_FLOW: 2545 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2546 /* Fall through */ 2547 case UDP_V6_FLOW: 2548 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2549 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2550 /* Fall through */ 2551 case SCTP_V6_FLOW: 2552 case AH_ESP_V6_FLOW: 2553 case AH_V6_FLOW: 2554 case ESP_V6_FLOW: 2555 case IPV6_FLOW: 2556 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2557 break; 2558 default: 2559 return -EINVAL; 2560 } 2561 2562 return 0; 2563 } 2564 2565 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2566 u32 *rule_locs) 2567 { 2568 struct igb_adapter *adapter = netdev_priv(dev); 2569 int ret = -EOPNOTSUPP; 2570 2571 switch (cmd->cmd) { 2572 case ETHTOOL_GRXRINGS: 2573 cmd->data = adapter->num_rx_queues; 2574 ret = 0; 2575 break; 2576 case ETHTOOL_GRXCLSRLCNT: 2577 cmd->rule_cnt = adapter->nfc_filter_count; 2578 ret = 0; 2579 break; 2580 case ETHTOOL_GRXCLSRULE: 2581 ret = igb_get_ethtool_nfc_entry(adapter, cmd); 2582 break; 2583 case ETHTOOL_GRXCLSRLALL: 2584 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs); 2585 break; 2586 case ETHTOOL_GRXFH: 2587 ret = igb_get_rss_hash_opts(adapter, cmd); 2588 break; 2589 default: 2590 break; 2591 } 2592 2593 return ret; 2594 } 2595 2596 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2597 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2598 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2599 struct ethtool_rxnfc *nfc) 2600 { 2601 u32 flags = adapter->flags; 2602 2603 /* RSS does not support anything other than hashing 2604 * to queues on src and dst IPs and ports 2605 */ 2606 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2607 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2608 return -EINVAL; 2609 2610 switch (nfc->flow_type) { 2611 case TCP_V4_FLOW: 2612 case TCP_V6_FLOW: 2613 if (!(nfc->data & RXH_IP_SRC) || 2614 !(nfc->data & RXH_IP_DST) || 2615 !(nfc->data & RXH_L4_B_0_1) || 2616 !(nfc->data & RXH_L4_B_2_3)) 2617 return -EINVAL; 2618 break; 2619 case UDP_V4_FLOW: 2620 if (!(nfc->data & RXH_IP_SRC) || 2621 !(nfc->data & RXH_IP_DST)) 2622 return -EINVAL; 2623 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2624 case 0: 2625 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2626 break; 2627 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2628 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2629 break; 2630 default: 2631 return -EINVAL; 2632 } 2633 break; 2634 case UDP_V6_FLOW: 2635 if (!(nfc->data & RXH_IP_SRC) || 2636 !(nfc->data & RXH_IP_DST)) 2637 return -EINVAL; 2638 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2639 case 0: 2640 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2641 break; 2642 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2643 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2644 break; 2645 default: 2646 return -EINVAL; 2647 } 2648 break; 2649 case AH_ESP_V4_FLOW: 2650 case AH_V4_FLOW: 2651 case ESP_V4_FLOW: 2652 case SCTP_V4_FLOW: 2653 case AH_ESP_V6_FLOW: 2654 case AH_V6_FLOW: 2655 case ESP_V6_FLOW: 2656 case SCTP_V6_FLOW: 2657 if (!(nfc->data & RXH_IP_SRC) || 2658 !(nfc->data & RXH_IP_DST) || 2659 (nfc->data & RXH_L4_B_0_1) || 2660 (nfc->data & RXH_L4_B_2_3)) 2661 return -EINVAL; 2662 break; 2663 default: 2664 return -EINVAL; 2665 } 2666 2667 /* if we changed something we need to update flags */ 2668 if (flags != adapter->flags) { 2669 struct e1000_hw *hw = &adapter->hw; 2670 u32 mrqc = rd32(E1000_MRQC); 2671 2672 if ((flags & UDP_RSS_FLAGS) && 2673 !(adapter->flags & UDP_RSS_FLAGS)) 2674 dev_err(&adapter->pdev->dev, 2675 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2676 2677 adapter->flags = flags; 2678 2679 /* Perform hash on these packet types */ 2680 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2681 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2682 E1000_MRQC_RSS_FIELD_IPV6 | 2683 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2684 2685 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2686 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2687 2688 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2689 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2690 2691 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2692 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2693 2694 wr32(E1000_MRQC, mrqc); 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter, 2701 struct igb_nfc_filter *input) 2702 { 2703 struct e1000_hw *hw = &adapter->hw; 2704 u8 i; 2705 u32 etqf; 2706 u16 etype; 2707 2708 /* find an empty etype filter register */ 2709 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { 2710 if (!adapter->etype_bitmap[i]) 2711 break; 2712 } 2713 if (i == MAX_ETYPE_FILTER) { 2714 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n"); 2715 return -EINVAL; 2716 } 2717 2718 adapter->etype_bitmap[i] = true; 2719 2720 etqf = rd32(E1000_ETQF(i)); 2721 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK); 2722 2723 etqf |= E1000_ETQF_FILTER_ENABLE; 2724 etqf &= ~E1000_ETQF_ETYPE_MASK; 2725 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2726 2727 etqf &= ~E1000_ETQF_QUEUE_MASK; 2728 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2729 & E1000_ETQF_QUEUE_MASK); 2730 etqf |= E1000_ETQF_QUEUE_ENABLE; 2731 2732 wr32(E1000_ETQF(i), etqf); 2733 2734 input->etype_reg_index = i; 2735 2736 return 0; 2737 } 2738 2739 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter, 2740 struct igb_nfc_filter *input) 2741 { 2742 struct e1000_hw *hw = &adapter->hw; 2743 u8 vlan_priority; 2744 u16 queue_index; 2745 u32 vlapqf; 2746 2747 vlapqf = rd32(E1000_VLAPQF); 2748 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2749 >> VLAN_PRIO_SHIFT; 2750 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2751 2752 /* check whether this vlan prio is already set */ 2753 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) && 2754 (queue_index != input->action)) { 2755 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n"); 2756 return -EEXIST; 2757 } 2758 2759 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority); 2760 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action); 2761 2762 wr32(E1000_VLAPQF, vlapqf); 2763 2764 return 0; 2765 } 2766 2767 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2768 { 2769 int err = -EINVAL; 2770 2771 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2772 err = igb_rxnfc_write_etype_filter(adapter, input); 2773 if (err) 2774 return err; 2775 } 2776 2777 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2778 err = igb_rxnfc_write_vlan_prio_filter(adapter, input); 2779 2780 return err; 2781 } 2782 2783 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter, 2784 u16 reg_index) 2785 { 2786 struct e1000_hw *hw = &adapter->hw; 2787 u32 etqf = rd32(E1000_ETQF(reg_index)); 2788 2789 etqf &= ~E1000_ETQF_QUEUE_ENABLE; 2790 etqf &= ~E1000_ETQF_QUEUE_MASK; 2791 etqf &= ~E1000_ETQF_FILTER_ENABLE; 2792 2793 wr32(E1000_ETQF(reg_index), etqf); 2794 2795 adapter->etype_bitmap[reg_index] = false; 2796 } 2797 2798 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter, 2799 u16 vlan_tci) 2800 { 2801 struct e1000_hw *hw = &adapter->hw; 2802 u8 vlan_priority; 2803 u32 vlapqf; 2804 2805 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2806 2807 vlapqf = rd32(E1000_VLAPQF); 2808 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority); 2809 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority, 2810 E1000_VLAPQF_QUEUE_MASK); 2811 2812 wr32(E1000_VLAPQF, vlapqf); 2813 } 2814 2815 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2816 { 2817 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) 2818 igb_clear_etype_filter_regs(adapter, 2819 input->etype_reg_index); 2820 2821 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2822 igb_clear_vlan_prio_filter(adapter, 2823 ntohs(input->filter.vlan_tci)); 2824 2825 return 0; 2826 } 2827 2828 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter, 2829 struct igb_nfc_filter *input, 2830 u16 sw_idx) 2831 { 2832 struct igb_nfc_filter *rule, *parent; 2833 int err = -EINVAL; 2834 2835 parent = NULL; 2836 rule = NULL; 2837 2838 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2839 /* hash found, or no matching entry */ 2840 if (rule->sw_idx >= sw_idx) 2841 break; 2842 parent = rule; 2843 } 2844 2845 /* if there is an old rule occupying our place remove it */ 2846 if (rule && (rule->sw_idx == sw_idx)) { 2847 if (!input) 2848 err = igb_erase_filter(adapter, rule); 2849 2850 hlist_del(&rule->nfc_node); 2851 kfree(rule); 2852 adapter->nfc_filter_count--; 2853 } 2854 2855 /* If no input this was a delete, err should be 0 if a rule was 2856 * successfully found and removed from the list else -EINVAL 2857 */ 2858 if (!input) 2859 return err; 2860 2861 /* initialize node */ 2862 INIT_HLIST_NODE(&input->nfc_node); 2863 2864 /* add filter to the list */ 2865 if (parent) 2866 hlist_add_behind(&parent->nfc_node, &input->nfc_node); 2867 else 2868 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list); 2869 2870 /* update counts */ 2871 adapter->nfc_filter_count++; 2872 2873 return 0; 2874 } 2875 2876 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, 2877 struct ethtool_rxnfc *cmd) 2878 { 2879 struct net_device *netdev = adapter->netdev; 2880 struct ethtool_rx_flow_spec *fsp = 2881 (struct ethtool_rx_flow_spec *)&cmd->fs; 2882 struct igb_nfc_filter *input, *rule; 2883 int err = 0; 2884 2885 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 2886 return -EOPNOTSUPP; 2887 2888 /* Don't allow programming if the action is a queue greater than 2889 * the number of online Rx queues. 2890 */ 2891 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) || 2892 (fsp->ring_cookie >= adapter->num_rx_queues)) { 2893 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n"); 2894 return -EINVAL; 2895 } 2896 2897 /* Don't allow indexes to exist outside of available space */ 2898 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) { 2899 dev_err(&adapter->pdev->dev, "Location out of range\n"); 2900 return -EINVAL; 2901 } 2902 2903 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW) 2904 return -EINVAL; 2905 2906 if (fsp->m_u.ether_spec.h_proto != ETHER_TYPE_FULL_MASK && 2907 fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) 2908 return -EINVAL; 2909 2910 input = kzalloc(sizeof(*input), GFP_KERNEL); 2911 if (!input) 2912 return -ENOMEM; 2913 2914 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) { 2915 input->filter.etype = fsp->h_u.ether_spec.h_proto; 2916 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE; 2917 } 2918 2919 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) { 2920 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) { 2921 err = -EINVAL; 2922 goto err_out; 2923 } 2924 input->filter.vlan_tci = fsp->h_ext.vlan_tci; 2925 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2926 } 2927 2928 input->action = fsp->ring_cookie; 2929 input->sw_idx = fsp->location; 2930 2931 spin_lock(&adapter->nfc_lock); 2932 2933 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2934 if (!memcmp(&input->filter, &rule->filter, 2935 sizeof(input->filter))) { 2936 err = -EEXIST; 2937 dev_err(&adapter->pdev->dev, 2938 "ethtool: this filter is already set\n"); 2939 goto err_out_w_lock; 2940 } 2941 } 2942 2943 err = igb_add_filter(adapter, input); 2944 if (err) 2945 goto err_out_w_lock; 2946 2947 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); 2948 2949 spin_unlock(&adapter->nfc_lock); 2950 return 0; 2951 2952 err_out_w_lock: 2953 spin_unlock(&adapter->nfc_lock); 2954 err_out: 2955 kfree(input); 2956 return err; 2957 } 2958 2959 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter, 2960 struct ethtool_rxnfc *cmd) 2961 { 2962 struct ethtool_rx_flow_spec *fsp = 2963 (struct ethtool_rx_flow_spec *)&cmd->fs; 2964 int err; 2965 2966 spin_lock(&adapter->nfc_lock); 2967 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location); 2968 spin_unlock(&adapter->nfc_lock); 2969 2970 return err; 2971 } 2972 2973 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2974 { 2975 struct igb_adapter *adapter = netdev_priv(dev); 2976 int ret = -EOPNOTSUPP; 2977 2978 switch (cmd->cmd) { 2979 case ETHTOOL_SRXFH: 2980 ret = igb_set_rss_hash_opt(adapter, cmd); 2981 break; 2982 case ETHTOOL_SRXCLSRLINS: 2983 ret = igb_add_ethtool_nfc_entry(adapter, cmd); 2984 break; 2985 case ETHTOOL_SRXCLSRLDEL: 2986 ret = igb_del_ethtool_nfc_entry(adapter, cmd); 2987 default: 2988 break; 2989 } 2990 2991 return ret; 2992 } 2993 2994 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 2995 { 2996 struct igb_adapter *adapter = netdev_priv(netdev); 2997 struct e1000_hw *hw = &adapter->hw; 2998 u32 ret_val; 2999 u16 phy_data; 3000 3001 if ((hw->mac.type < e1000_i350) || 3002 (hw->phy.media_type != e1000_media_type_copper)) 3003 return -EOPNOTSUPP; 3004 3005 edata->supported = (SUPPORTED_1000baseT_Full | 3006 SUPPORTED_100baseT_Full); 3007 if (!hw->dev_spec._82575.eee_disable) 3008 edata->advertised = 3009 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 3010 3011 /* The IPCNFG and EEER registers are not supported on I354. */ 3012 if (hw->mac.type == e1000_i354) { 3013 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 3014 } else { 3015 u32 eeer; 3016 3017 eeer = rd32(E1000_EEER); 3018 3019 /* EEE status on negotiated link */ 3020 if (eeer & E1000_EEER_EEE_NEG) 3021 edata->eee_active = true; 3022 3023 if (eeer & E1000_EEER_TX_LPI_EN) 3024 edata->tx_lpi_enabled = true; 3025 } 3026 3027 /* EEE Link Partner Advertised */ 3028 switch (hw->mac.type) { 3029 case e1000_i350: 3030 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 3031 &phy_data); 3032 if (ret_val) 3033 return -ENODATA; 3034 3035 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3036 break; 3037 case e1000_i354: 3038 case e1000_i210: 3039 case e1000_i211: 3040 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 3041 E1000_EEE_LP_ADV_DEV_I210, 3042 &phy_data); 3043 if (ret_val) 3044 return -ENODATA; 3045 3046 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3047 3048 break; 3049 default: 3050 break; 3051 } 3052 3053 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 3054 3055 if ((hw->mac.type == e1000_i354) && 3056 (edata->eee_enabled)) 3057 edata->tx_lpi_enabled = true; 3058 3059 /* Report correct negotiated EEE status for devices that 3060 * wrongly report EEE at half-duplex 3061 */ 3062 if (adapter->link_duplex == HALF_DUPLEX) { 3063 edata->eee_enabled = false; 3064 edata->eee_active = false; 3065 edata->tx_lpi_enabled = false; 3066 edata->advertised &= ~edata->advertised; 3067 } 3068 3069 return 0; 3070 } 3071 3072 static int igb_set_eee(struct net_device *netdev, 3073 struct ethtool_eee *edata) 3074 { 3075 struct igb_adapter *adapter = netdev_priv(netdev); 3076 struct e1000_hw *hw = &adapter->hw; 3077 struct ethtool_eee eee_curr; 3078 bool adv1g_eee = true, adv100m_eee = true; 3079 s32 ret_val; 3080 3081 if ((hw->mac.type < e1000_i350) || 3082 (hw->phy.media_type != e1000_media_type_copper)) 3083 return -EOPNOTSUPP; 3084 3085 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 3086 3087 ret_val = igb_get_eee(netdev, &eee_curr); 3088 if (ret_val) 3089 return ret_val; 3090 3091 if (eee_curr.eee_enabled) { 3092 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 3093 dev_err(&adapter->pdev->dev, 3094 "Setting EEE tx-lpi is not supported\n"); 3095 return -EINVAL; 3096 } 3097 3098 /* Tx LPI timer is not implemented currently */ 3099 if (edata->tx_lpi_timer) { 3100 dev_err(&adapter->pdev->dev, 3101 "Setting EEE Tx LPI timer is not supported\n"); 3102 return -EINVAL; 3103 } 3104 3105 if (!edata->advertised || (edata->advertised & 3106 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 3107 dev_err(&adapter->pdev->dev, 3108 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 3109 return -EINVAL; 3110 } 3111 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 3112 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 3113 3114 } else if (!edata->eee_enabled) { 3115 dev_err(&adapter->pdev->dev, 3116 "Setting EEE options are not supported with EEE disabled\n"); 3117 return -EINVAL; 3118 } 3119 3120 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 3121 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 3122 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 3123 adapter->flags |= IGB_FLAG_EEE; 3124 3125 /* reset link */ 3126 if (netif_running(netdev)) 3127 igb_reinit_locked(adapter); 3128 else 3129 igb_reset(adapter); 3130 } 3131 3132 if (hw->mac.type == e1000_i354) 3133 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 3134 else 3135 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 3136 3137 if (ret_val) { 3138 dev_err(&adapter->pdev->dev, 3139 "Problem setting EEE advertisement options\n"); 3140 return -EINVAL; 3141 } 3142 3143 return 0; 3144 } 3145 3146 static int igb_get_module_info(struct net_device *netdev, 3147 struct ethtool_modinfo *modinfo) 3148 { 3149 struct igb_adapter *adapter = netdev_priv(netdev); 3150 struct e1000_hw *hw = &adapter->hw; 3151 u32 status = 0; 3152 u16 sff8472_rev, addr_mode; 3153 bool page_swap = false; 3154 3155 if ((hw->phy.media_type == e1000_media_type_copper) || 3156 (hw->phy.media_type == e1000_media_type_unknown)) 3157 return -EOPNOTSUPP; 3158 3159 /* Check whether we support SFF-8472 or not */ 3160 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 3161 if (status) 3162 return -EIO; 3163 3164 /* addressing mode is not supported */ 3165 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 3166 if (status) 3167 return -EIO; 3168 3169 /* addressing mode is not supported */ 3170 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 3171 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3172 page_swap = true; 3173 } 3174 3175 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 3176 /* We have an SFP, but it does not support SFF-8472 */ 3177 modinfo->type = ETH_MODULE_SFF_8079; 3178 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3179 } else { 3180 /* We have an SFP which supports a revision of SFF-8472 */ 3181 modinfo->type = ETH_MODULE_SFF_8472; 3182 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3183 } 3184 3185 return 0; 3186 } 3187 3188 static int igb_get_module_eeprom(struct net_device *netdev, 3189 struct ethtool_eeprom *ee, u8 *data) 3190 { 3191 struct igb_adapter *adapter = netdev_priv(netdev); 3192 struct e1000_hw *hw = &adapter->hw; 3193 u32 status = 0; 3194 u16 *dataword; 3195 u16 first_word, last_word; 3196 int i = 0; 3197 3198 if (ee->len == 0) 3199 return -EINVAL; 3200 3201 first_word = ee->offset >> 1; 3202 last_word = (ee->offset + ee->len - 1) >> 1; 3203 3204 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1), 3205 GFP_KERNEL); 3206 if (!dataword) 3207 return -ENOMEM; 3208 3209 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 3210 for (i = 0; i < last_word - first_word + 1; i++) { 3211 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 3212 &dataword[i]); 3213 if (status) { 3214 /* Error occurred while reading module */ 3215 kfree(dataword); 3216 return -EIO; 3217 } 3218 3219 be16_to_cpus(&dataword[i]); 3220 } 3221 3222 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 3223 kfree(dataword); 3224 3225 return 0; 3226 } 3227 3228 static int igb_ethtool_begin(struct net_device *netdev) 3229 { 3230 struct igb_adapter *adapter = netdev_priv(netdev); 3231 pm_runtime_get_sync(&adapter->pdev->dev); 3232 return 0; 3233 } 3234 3235 static void igb_ethtool_complete(struct net_device *netdev) 3236 { 3237 struct igb_adapter *adapter = netdev_priv(netdev); 3238 pm_runtime_put(&adapter->pdev->dev); 3239 } 3240 3241 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 3242 { 3243 return IGB_RETA_SIZE; 3244 } 3245 3246 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3247 u8 *hfunc) 3248 { 3249 struct igb_adapter *adapter = netdev_priv(netdev); 3250 int i; 3251 3252 if (hfunc) 3253 *hfunc = ETH_RSS_HASH_TOP; 3254 if (!indir) 3255 return 0; 3256 for (i = 0; i < IGB_RETA_SIZE; i++) 3257 indir[i] = adapter->rss_indir_tbl[i]; 3258 3259 return 0; 3260 } 3261 3262 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 3263 { 3264 struct e1000_hw *hw = &adapter->hw; 3265 u32 reg = E1000_RETA(0); 3266 u32 shift = 0; 3267 int i = 0; 3268 3269 switch (hw->mac.type) { 3270 case e1000_82575: 3271 shift = 6; 3272 break; 3273 case e1000_82576: 3274 /* 82576 supports 2 RSS queues for SR-IOV */ 3275 if (adapter->vfs_allocated_count) 3276 shift = 3; 3277 break; 3278 default: 3279 break; 3280 } 3281 3282 while (i < IGB_RETA_SIZE) { 3283 u32 val = 0; 3284 int j; 3285 3286 for (j = 3; j >= 0; j--) { 3287 val <<= 8; 3288 val |= adapter->rss_indir_tbl[i + j]; 3289 } 3290 3291 wr32(reg, val << shift); 3292 reg += 4; 3293 i += 4; 3294 } 3295 } 3296 3297 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 3298 const u8 *key, const u8 hfunc) 3299 { 3300 struct igb_adapter *adapter = netdev_priv(netdev); 3301 struct e1000_hw *hw = &adapter->hw; 3302 int i; 3303 u32 num_queues; 3304 3305 /* We do not allow change in unsupported parameters */ 3306 if (key || 3307 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3308 return -EOPNOTSUPP; 3309 if (!indir) 3310 return 0; 3311 3312 num_queues = adapter->rss_queues; 3313 3314 switch (hw->mac.type) { 3315 case e1000_82576: 3316 /* 82576 supports 2 RSS queues for SR-IOV */ 3317 if (adapter->vfs_allocated_count) 3318 num_queues = 2; 3319 break; 3320 default: 3321 break; 3322 } 3323 3324 /* Verify user input. */ 3325 for (i = 0; i < IGB_RETA_SIZE; i++) 3326 if (indir[i] >= num_queues) 3327 return -EINVAL; 3328 3329 3330 for (i = 0; i < IGB_RETA_SIZE; i++) 3331 adapter->rss_indir_tbl[i] = indir[i]; 3332 3333 igb_write_rss_indir_tbl(adapter); 3334 3335 return 0; 3336 } 3337 3338 static unsigned int igb_max_channels(struct igb_adapter *adapter) 3339 { 3340 struct e1000_hw *hw = &adapter->hw; 3341 unsigned int max_combined = 0; 3342 3343 switch (hw->mac.type) { 3344 case e1000_i211: 3345 max_combined = IGB_MAX_RX_QUEUES_I211; 3346 break; 3347 case e1000_82575: 3348 case e1000_i210: 3349 max_combined = IGB_MAX_RX_QUEUES_82575; 3350 break; 3351 case e1000_i350: 3352 if (!!adapter->vfs_allocated_count) { 3353 max_combined = 1; 3354 break; 3355 } 3356 /* fall through */ 3357 case e1000_82576: 3358 if (!!adapter->vfs_allocated_count) { 3359 max_combined = 2; 3360 break; 3361 } 3362 /* fall through */ 3363 case e1000_82580: 3364 case e1000_i354: 3365 default: 3366 max_combined = IGB_MAX_RX_QUEUES; 3367 break; 3368 } 3369 3370 return max_combined; 3371 } 3372 3373 static void igb_get_channels(struct net_device *netdev, 3374 struct ethtool_channels *ch) 3375 { 3376 struct igb_adapter *adapter = netdev_priv(netdev); 3377 3378 /* Report maximum channels */ 3379 ch->max_combined = igb_max_channels(adapter); 3380 3381 /* Report info for other vector */ 3382 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3383 ch->max_other = NON_Q_VECTORS; 3384 ch->other_count = NON_Q_VECTORS; 3385 } 3386 3387 ch->combined_count = adapter->rss_queues; 3388 } 3389 3390 static int igb_set_channels(struct net_device *netdev, 3391 struct ethtool_channels *ch) 3392 { 3393 struct igb_adapter *adapter = netdev_priv(netdev); 3394 unsigned int count = ch->combined_count; 3395 unsigned int max_combined = 0; 3396 3397 /* Verify they are not requesting separate vectors */ 3398 if (!count || ch->rx_count || ch->tx_count) 3399 return -EINVAL; 3400 3401 /* Verify other_count is valid and has not been changed */ 3402 if (ch->other_count != NON_Q_VECTORS) 3403 return -EINVAL; 3404 3405 /* Verify the number of channels doesn't exceed hw limits */ 3406 max_combined = igb_max_channels(adapter); 3407 if (count > max_combined) 3408 return -EINVAL; 3409 3410 if (count != adapter->rss_queues) { 3411 adapter->rss_queues = count; 3412 igb_set_flag_queue_pairs(adapter, max_combined); 3413 3414 /* Hardware has to reinitialize queues and interrupts to 3415 * match the new configuration. 3416 */ 3417 return igb_reinit_queues(adapter); 3418 } 3419 3420 return 0; 3421 } 3422 3423 static u32 igb_get_priv_flags(struct net_device *netdev) 3424 { 3425 struct igb_adapter *adapter = netdev_priv(netdev); 3426 u32 priv_flags = 0; 3427 3428 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3429 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX; 3430 3431 return priv_flags; 3432 } 3433 3434 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3435 { 3436 struct igb_adapter *adapter = netdev_priv(netdev); 3437 unsigned int flags = adapter->flags; 3438 3439 flags &= ~IGB_FLAG_RX_LEGACY; 3440 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX) 3441 flags |= IGB_FLAG_RX_LEGACY; 3442 3443 if (flags != adapter->flags) { 3444 adapter->flags = flags; 3445 3446 /* reset interface to repopulate queues */ 3447 if (netif_running(netdev)) 3448 igb_reinit_locked(adapter); 3449 } 3450 3451 return 0; 3452 } 3453 3454 static const struct ethtool_ops igb_ethtool_ops = { 3455 .get_drvinfo = igb_get_drvinfo, 3456 .get_regs_len = igb_get_regs_len, 3457 .get_regs = igb_get_regs, 3458 .get_wol = igb_get_wol, 3459 .set_wol = igb_set_wol, 3460 .get_msglevel = igb_get_msglevel, 3461 .set_msglevel = igb_set_msglevel, 3462 .nway_reset = igb_nway_reset, 3463 .get_link = igb_get_link, 3464 .get_eeprom_len = igb_get_eeprom_len, 3465 .get_eeprom = igb_get_eeprom, 3466 .set_eeprom = igb_set_eeprom, 3467 .get_ringparam = igb_get_ringparam, 3468 .set_ringparam = igb_set_ringparam, 3469 .get_pauseparam = igb_get_pauseparam, 3470 .set_pauseparam = igb_set_pauseparam, 3471 .self_test = igb_diag_test, 3472 .get_strings = igb_get_strings, 3473 .set_phys_id = igb_set_phys_id, 3474 .get_sset_count = igb_get_sset_count, 3475 .get_ethtool_stats = igb_get_ethtool_stats, 3476 .get_coalesce = igb_get_coalesce, 3477 .set_coalesce = igb_set_coalesce, 3478 .get_ts_info = igb_get_ts_info, 3479 .get_rxnfc = igb_get_rxnfc, 3480 .set_rxnfc = igb_set_rxnfc, 3481 .get_eee = igb_get_eee, 3482 .set_eee = igb_set_eee, 3483 .get_module_info = igb_get_module_info, 3484 .get_module_eeprom = igb_get_module_eeprom, 3485 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3486 .get_rxfh = igb_get_rxfh, 3487 .set_rxfh = igb_set_rxfh, 3488 .get_channels = igb_get_channels, 3489 .set_channels = igb_set_channels, 3490 .get_priv_flags = igb_get_priv_flags, 3491 .set_priv_flags = igb_set_priv_flags, 3492 .begin = igb_ethtool_begin, 3493 .complete = igb_ethtool_complete, 3494 .get_link_ksettings = igb_get_link_ksettings, 3495 .set_link_ksettings = igb_set_link_ksettings, 3496 }; 3497 3498 void igb_set_ethtool_ops(struct net_device *netdev) 3499 { 3500 netdev->ethtool_ops = &igb_ethtool_ops; 3501 } 3502