1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* ethtool support for igb */ 25 26 #include <linux/vmalloc.h> 27 #include <linux/netdevice.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/interrupt.h> 31 #include <linux/if_ether.h> 32 #include <linux/ethtool.h> 33 #include <linux/sched.h> 34 #include <linux/slab.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/highmem.h> 37 #include <linux/mdio.h> 38 39 #include "igb.h" 40 41 struct igb_stats { 42 char stat_string[ETH_GSTRING_LEN]; 43 int sizeof_stat; 44 int stat_offset; 45 }; 46 47 #define IGB_STAT(_name, _stat) { \ 48 .stat_string = _name, \ 49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 50 .stat_offset = offsetof(struct igb_adapter, _stat) \ 51 } 52 static const struct igb_stats igb_gstrings_stats[] = { 53 IGB_STAT("rx_packets", stats.gprc), 54 IGB_STAT("tx_packets", stats.gptc), 55 IGB_STAT("rx_bytes", stats.gorc), 56 IGB_STAT("tx_bytes", stats.gotc), 57 IGB_STAT("rx_broadcast", stats.bprc), 58 IGB_STAT("tx_broadcast", stats.bptc), 59 IGB_STAT("rx_multicast", stats.mprc), 60 IGB_STAT("tx_multicast", stats.mptc), 61 IGB_STAT("multicast", stats.mprc), 62 IGB_STAT("collisions", stats.colc), 63 IGB_STAT("rx_crc_errors", stats.crcerrs), 64 IGB_STAT("rx_no_buffer_count", stats.rnbc), 65 IGB_STAT("rx_missed_errors", stats.mpc), 66 IGB_STAT("tx_aborted_errors", stats.ecol), 67 IGB_STAT("tx_carrier_errors", stats.tncrs), 68 IGB_STAT("tx_window_errors", stats.latecol), 69 IGB_STAT("tx_abort_late_coll", stats.latecol), 70 IGB_STAT("tx_deferred_ok", stats.dc), 71 IGB_STAT("tx_single_coll_ok", stats.scc), 72 IGB_STAT("tx_multi_coll_ok", stats.mcc), 73 IGB_STAT("tx_timeout_count", tx_timeout_count), 74 IGB_STAT("rx_long_length_errors", stats.roc), 75 IGB_STAT("rx_short_length_errors", stats.ruc), 76 IGB_STAT("rx_align_errors", stats.algnerrc), 77 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 79 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 81 IGB_STAT("tx_flow_control_xon", stats.xontxc), 82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 83 IGB_STAT("rx_long_byte_count", stats.gorc), 84 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 85 IGB_STAT("tx_smbus", stats.mgptc), 86 IGB_STAT("rx_smbus", stats.mgprc), 87 IGB_STAT("dropped_smbus", stats.mgpdc), 88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 94 }; 95 96 #define IGB_NETDEV_STAT(_net_stat) { \ 97 .stat_string = __stringify(_net_stat), \ 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 100 } 101 static const struct igb_stats igb_gstrings_net_stats[] = { 102 IGB_NETDEV_STAT(rx_errors), 103 IGB_NETDEV_STAT(tx_errors), 104 IGB_NETDEV_STAT(tx_dropped), 105 IGB_NETDEV_STAT(rx_length_errors), 106 IGB_NETDEV_STAT(rx_over_errors), 107 IGB_NETDEV_STAT(rx_frame_errors), 108 IGB_NETDEV_STAT(rx_fifo_errors), 109 IGB_NETDEV_STAT(tx_fifo_errors), 110 IGB_NETDEV_STAT(tx_heartbeat_errors) 111 }; 112 113 #define IGB_GLOBAL_STATS_LEN \ 114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 115 #define IGB_NETDEV_STATS_LEN \ 116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 117 #define IGB_RX_QUEUE_STATS_LEN \ 118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 119 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 121 122 #define IGB_QUEUE_STATS_LEN \ 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 124 IGB_RX_QUEUE_STATS_LEN) + \ 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 126 IGB_TX_QUEUE_STATS_LEN)) 127 #define IGB_STATS_LEN \ 128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 129 130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 131 "Register test (offline)", "Eeprom test (offline)", 132 "Interrupt test (offline)", "Loopback test (offline)", 133 "Link test (on/offline)" 134 }; 135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 136 137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 138 { 139 struct igb_adapter *adapter = netdev_priv(netdev); 140 struct e1000_hw *hw = &adapter->hw; 141 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 142 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 143 u32 status; 144 u32 speed; 145 146 status = rd32(E1000_STATUS); 147 if (hw->phy.media_type == e1000_media_type_copper) { 148 149 ecmd->supported = (SUPPORTED_10baseT_Half | 150 SUPPORTED_10baseT_Full | 151 SUPPORTED_100baseT_Half | 152 SUPPORTED_100baseT_Full | 153 SUPPORTED_1000baseT_Full| 154 SUPPORTED_Autoneg | 155 SUPPORTED_TP | 156 SUPPORTED_Pause); 157 ecmd->advertising = ADVERTISED_TP; 158 159 if (hw->mac.autoneg == 1) { 160 ecmd->advertising |= ADVERTISED_Autoneg; 161 /* the e1000 autoneg seems to match ethtool nicely */ 162 ecmd->advertising |= hw->phy.autoneg_advertised; 163 } 164 165 ecmd->port = PORT_TP; 166 ecmd->phy_address = hw->phy.addr; 167 ecmd->transceiver = XCVR_INTERNAL; 168 } else { 169 ecmd->supported = (SUPPORTED_FIBRE | 170 SUPPORTED_1000baseKX_Full | 171 SUPPORTED_Autoneg | 172 SUPPORTED_Pause); 173 ecmd->advertising = (ADVERTISED_FIBRE | 174 ADVERTISED_1000baseKX_Full); 175 if (hw->mac.type == e1000_i354) { 176 if ((hw->device_id == 177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 178 !(status & E1000_STATUS_2P5_SKU_OVER)) { 179 ecmd->supported |= SUPPORTED_2500baseX_Full; 180 ecmd->supported &= 181 ~SUPPORTED_1000baseKX_Full; 182 ecmd->advertising |= ADVERTISED_2500baseX_Full; 183 ecmd->advertising &= 184 ~ADVERTISED_1000baseKX_Full; 185 } 186 } 187 if (eth_flags->e100_base_fx) { 188 ecmd->supported |= SUPPORTED_100baseT_Full; 189 ecmd->advertising |= ADVERTISED_100baseT_Full; 190 } 191 if (hw->mac.autoneg == 1) 192 ecmd->advertising |= ADVERTISED_Autoneg; 193 194 ecmd->port = PORT_FIBRE; 195 ecmd->transceiver = XCVR_EXTERNAL; 196 } 197 if (hw->mac.autoneg != 1) 198 ecmd->advertising &= ~(ADVERTISED_Pause | 199 ADVERTISED_Asym_Pause); 200 201 switch (hw->fc.requested_mode) { 202 case e1000_fc_full: 203 ecmd->advertising |= ADVERTISED_Pause; 204 break; 205 case e1000_fc_rx_pause: 206 ecmd->advertising |= (ADVERTISED_Pause | 207 ADVERTISED_Asym_Pause); 208 break; 209 case e1000_fc_tx_pause: 210 ecmd->advertising |= ADVERTISED_Asym_Pause; 211 break; 212 default: 213 ecmd->advertising &= ~(ADVERTISED_Pause | 214 ADVERTISED_Asym_Pause); 215 } 216 if (status & E1000_STATUS_LU) { 217 if ((status & E1000_STATUS_2P5_SKU) && 218 !(status & E1000_STATUS_2P5_SKU_OVER)) { 219 speed = SPEED_2500; 220 } else if (status & E1000_STATUS_SPEED_1000) { 221 speed = SPEED_1000; 222 } else if (status & E1000_STATUS_SPEED_100) { 223 speed = SPEED_100; 224 } else { 225 speed = SPEED_10; 226 } 227 if ((status & E1000_STATUS_FD) || 228 hw->phy.media_type != e1000_media_type_copper) 229 ecmd->duplex = DUPLEX_FULL; 230 else 231 ecmd->duplex = DUPLEX_HALF; 232 } else { 233 speed = SPEED_UNKNOWN; 234 ecmd->duplex = DUPLEX_UNKNOWN; 235 } 236 ethtool_cmd_speed_set(ecmd, speed); 237 if ((hw->phy.media_type == e1000_media_type_fiber) || 238 hw->mac.autoneg) 239 ecmd->autoneg = AUTONEG_ENABLE; 240 else 241 ecmd->autoneg = AUTONEG_DISABLE; 242 243 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 244 if (hw->phy.media_type == e1000_media_type_copper) 245 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 246 ETH_TP_MDI; 247 else 248 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 249 250 if (hw->phy.mdix == AUTO_ALL_MODES) 251 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 252 else 253 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; 254 255 return 0; 256 } 257 258 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 259 { 260 struct igb_adapter *adapter = netdev_priv(netdev); 261 struct e1000_hw *hw = &adapter->hw; 262 263 /* When SoL/IDER sessions are active, autoneg/speed/duplex 264 * cannot be changed 265 */ 266 if (igb_check_reset_block(hw)) { 267 dev_err(&adapter->pdev->dev, 268 "Cannot change link characteristics when SoL/IDER is active.\n"); 269 return -EINVAL; 270 } 271 272 /* MDI setting is only allowed when autoneg enabled because 273 * some hardware doesn't allow MDI setting when speed or 274 * duplex is forced. 275 */ 276 if (ecmd->eth_tp_mdix_ctrl) { 277 if (hw->phy.media_type != e1000_media_type_copper) 278 return -EOPNOTSUPP; 279 280 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 281 (ecmd->autoneg != AUTONEG_ENABLE)) { 282 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 283 return -EINVAL; 284 } 285 } 286 287 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 288 usleep_range(1000, 2000); 289 290 if (ecmd->autoneg == AUTONEG_ENABLE) { 291 hw->mac.autoneg = 1; 292 if (hw->phy.media_type == e1000_media_type_fiber) { 293 hw->phy.autoneg_advertised = ecmd->advertising | 294 ADVERTISED_FIBRE | 295 ADVERTISED_Autoneg; 296 switch (adapter->link_speed) { 297 case SPEED_2500: 298 hw->phy.autoneg_advertised = 299 ADVERTISED_2500baseX_Full; 300 break; 301 case SPEED_1000: 302 hw->phy.autoneg_advertised = 303 ADVERTISED_1000baseT_Full; 304 break; 305 case SPEED_100: 306 hw->phy.autoneg_advertised = 307 ADVERTISED_100baseT_Full; 308 break; 309 default: 310 break; 311 } 312 } else { 313 hw->phy.autoneg_advertised = ecmd->advertising | 314 ADVERTISED_TP | 315 ADVERTISED_Autoneg; 316 } 317 ecmd->advertising = hw->phy.autoneg_advertised; 318 if (adapter->fc_autoneg) 319 hw->fc.requested_mode = e1000_fc_default; 320 } else { 321 u32 speed = ethtool_cmd_speed(ecmd); 322 /* calling this overrides forced MDI setting */ 323 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 324 clear_bit(__IGB_RESETTING, &adapter->state); 325 return -EINVAL; 326 } 327 } 328 329 /* MDI-X => 2; MDI => 1; Auto => 3 */ 330 if (ecmd->eth_tp_mdix_ctrl) { 331 /* fix up the value for auto (3 => 0) as zero is mapped 332 * internally to auto 333 */ 334 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 335 hw->phy.mdix = AUTO_ALL_MODES; 336 else 337 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl; 338 } 339 340 /* reset the link */ 341 if (netif_running(adapter->netdev)) { 342 igb_down(adapter); 343 igb_up(adapter); 344 } else 345 igb_reset(adapter); 346 347 clear_bit(__IGB_RESETTING, &adapter->state); 348 return 0; 349 } 350 351 static u32 igb_get_link(struct net_device *netdev) 352 { 353 struct igb_adapter *adapter = netdev_priv(netdev); 354 struct e1000_mac_info *mac = &adapter->hw.mac; 355 356 /* If the link is not reported up to netdev, interrupts are disabled, 357 * and so the physical link state may have changed since we last 358 * looked. Set get_link_status to make sure that the true link 359 * state is interrogated, rather than pulling a cached and possibly 360 * stale link state from the driver. 361 */ 362 if (!netif_carrier_ok(netdev)) 363 mac->get_link_status = 1; 364 365 return igb_has_link(adapter); 366 } 367 368 static void igb_get_pauseparam(struct net_device *netdev, 369 struct ethtool_pauseparam *pause) 370 { 371 struct igb_adapter *adapter = netdev_priv(netdev); 372 struct e1000_hw *hw = &adapter->hw; 373 374 pause->autoneg = 375 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 376 377 if (hw->fc.current_mode == e1000_fc_rx_pause) 378 pause->rx_pause = 1; 379 else if (hw->fc.current_mode == e1000_fc_tx_pause) 380 pause->tx_pause = 1; 381 else if (hw->fc.current_mode == e1000_fc_full) { 382 pause->rx_pause = 1; 383 pause->tx_pause = 1; 384 } 385 } 386 387 static int igb_set_pauseparam(struct net_device *netdev, 388 struct ethtool_pauseparam *pause) 389 { 390 struct igb_adapter *adapter = netdev_priv(netdev); 391 struct e1000_hw *hw = &adapter->hw; 392 int retval = 0; 393 394 /* 100basefx does not support setting link flow control */ 395 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 396 return -EINVAL; 397 398 adapter->fc_autoneg = pause->autoneg; 399 400 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 401 usleep_range(1000, 2000); 402 403 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 404 hw->fc.requested_mode = e1000_fc_default; 405 if (netif_running(adapter->netdev)) { 406 igb_down(adapter); 407 igb_up(adapter); 408 } else { 409 igb_reset(adapter); 410 } 411 } else { 412 if (pause->rx_pause && pause->tx_pause) 413 hw->fc.requested_mode = e1000_fc_full; 414 else if (pause->rx_pause && !pause->tx_pause) 415 hw->fc.requested_mode = e1000_fc_rx_pause; 416 else if (!pause->rx_pause && pause->tx_pause) 417 hw->fc.requested_mode = e1000_fc_tx_pause; 418 else if (!pause->rx_pause && !pause->tx_pause) 419 hw->fc.requested_mode = e1000_fc_none; 420 421 hw->fc.current_mode = hw->fc.requested_mode; 422 423 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 424 igb_force_mac_fc(hw) : igb_setup_link(hw)); 425 } 426 427 clear_bit(__IGB_RESETTING, &adapter->state); 428 return retval; 429 } 430 431 static u32 igb_get_msglevel(struct net_device *netdev) 432 { 433 struct igb_adapter *adapter = netdev_priv(netdev); 434 return adapter->msg_enable; 435 } 436 437 static void igb_set_msglevel(struct net_device *netdev, u32 data) 438 { 439 struct igb_adapter *adapter = netdev_priv(netdev); 440 adapter->msg_enable = data; 441 } 442 443 static int igb_get_regs_len(struct net_device *netdev) 444 { 445 #define IGB_REGS_LEN 739 446 return IGB_REGS_LEN * sizeof(u32); 447 } 448 449 static void igb_get_regs(struct net_device *netdev, 450 struct ethtool_regs *regs, void *p) 451 { 452 struct igb_adapter *adapter = netdev_priv(netdev); 453 struct e1000_hw *hw = &adapter->hw; 454 u32 *regs_buff = p; 455 u8 i; 456 457 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 458 459 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 460 461 /* General Registers */ 462 regs_buff[0] = rd32(E1000_CTRL); 463 regs_buff[1] = rd32(E1000_STATUS); 464 regs_buff[2] = rd32(E1000_CTRL_EXT); 465 regs_buff[3] = rd32(E1000_MDIC); 466 regs_buff[4] = rd32(E1000_SCTL); 467 regs_buff[5] = rd32(E1000_CONNSW); 468 regs_buff[6] = rd32(E1000_VET); 469 regs_buff[7] = rd32(E1000_LEDCTL); 470 regs_buff[8] = rd32(E1000_PBA); 471 regs_buff[9] = rd32(E1000_PBS); 472 regs_buff[10] = rd32(E1000_FRTIMER); 473 regs_buff[11] = rd32(E1000_TCPTIMER); 474 475 /* NVM Register */ 476 regs_buff[12] = rd32(E1000_EECD); 477 478 /* Interrupt */ 479 /* Reading EICS for EICR because they read the 480 * same but EICS does not clear on read 481 */ 482 regs_buff[13] = rd32(E1000_EICS); 483 regs_buff[14] = rd32(E1000_EICS); 484 regs_buff[15] = rd32(E1000_EIMS); 485 regs_buff[16] = rd32(E1000_EIMC); 486 regs_buff[17] = rd32(E1000_EIAC); 487 regs_buff[18] = rd32(E1000_EIAM); 488 /* Reading ICS for ICR because they read the 489 * same but ICS does not clear on read 490 */ 491 regs_buff[19] = rd32(E1000_ICS); 492 regs_buff[20] = rd32(E1000_ICS); 493 regs_buff[21] = rd32(E1000_IMS); 494 regs_buff[22] = rd32(E1000_IMC); 495 regs_buff[23] = rd32(E1000_IAC); 496 regs_buff[24] = rd32(E1000_IAM); 497 regs_buff[25] = rd32(E1000_IMIRVP); 498 499 /* Flow Control */ 500 regs_buff[26] = rd32(E1000_FCAL); 501 regs_buff[27] = rd32(E1000_FCAH); 502 regs_buff[28] = rd32(E1000_FCTTV); 503 regs_buff[29] = rd32(E1000_FCRTL); 504 regs_buff[30] = rd32(E1000_FCRTH); 505 regs_buff[31] = rd32(E1000_FCRTV); 506 507 /* Receive */ 508 regs_buff[32] = rd32(E1000_RCTL); 509 regs_buff[33] = rd32(E1000_RXCSUM); 510 regs_buff[34] = rd32(E1000_RLPML); 511 regs_buff[35] = rd32(E1000_RFCTL); 512 regs_buff[36] = rd32(E1000_MRQC); 513 regs_buff[37] = rd32(E1000_VT_CTL); 514 515 /* Transmit */ 516 regs_buff[38] = rd32(E1000_TCTL); 517 regs_buff[39] = rd32(E1000_TCTL_EXT); 518 regs_buff[40] = rd32(E1000_TIPG); 519 regs_buff[41] = rd32(E1000_DTXCTL); 520 521 /* Wake Up */ 522 regs_buff[42] = rd32(E1000_WUC); 523 regs_buff[43] = rd32(E1000_WUFC); 524 regs_buff[44] = rd32(E1000_WUS); 525 regs_buff[45] = rd32(E1000_IPAV); 526 regs_buff[46] = rd32(E1000_WUPL); 527 528 /* MAC */ 529 regs_buff[47] = rd32(E1000_PCS_CFG0); 530 regs_buff[48] = rd32(E1000_PCS_LCTL); 531 regs_buff[49] = rd32(E1000_PCS_LSTAT); 532 regs_buff[50] = rd32(E1000_PCS_ANADV); 533 regs_buff[51] = rd32(E1000_PCS_LPAB); 534 regs_buff[52] = rd32(E1000_PCS_NPTX); 535 regs_buff[53] = rd32(E1000_PCS_LPABNP); 536 537 /* Statistics */ 538 regs_buff[54] = adapter->stats.crcerrs; 539 regs_buff[55] = adapter->stats.algnerrc; 540 regs_buff[56] = adapter->stats.symerrs; 541 regs_buff[57] = adapter->stats.rxerrc; 542 regs_buff[58] = adapter->stats.mpc; 543 regs_buff[59] = adapter->stats.scc; 544 regs_buff[60] = adapter->stats.ecol; 545 regs_buff[61] = adapter->stats.mcc; 546 regs_buff[62] = adapter->stats.latecol; 547 regs_buff[63] = adapter->stats.colc; 548 regs_buff[64] = adapter->stats.dc; 549 regs_buff[65] = adapter->stats.tncrs; 550 regs_buff[66] = adapter->stats.sec; 551 regs_buff[67] = adapter->stats.htdpmc; 552 regs_buff[68] = adapter->stats.rlec; 553 regs_buff[69] = adapter->stats.xonrxc; 554 regs_buff[70] = adapter->stats.xontxc; 555 regs_buff[71] = adapter->stats.xoffrxc; 556 regs_buff[72] = adapter->stats.xofftxc; 557 regs_buff[73] = adapter->stats.fcruc; 558 regs_buff[74] = adapter->stats.prc64; 559 regs_buff[75] = adapter->stats.prc127; 560 regs_buff[76] = adapter->stats.prc255; 561 regs_buff[77] = adapter->stats.prc511; 562 regs_buff[78] = adapter->stats.prc1023; 563 regs_buff[79] = adapter->stats.prc1522; 564 regs_buff[80] = adapter->stats.gprc; 565 regs_buff[81] = adapter->stats.bprc; 566 regs_buff[82] = adapter->stats.mprc; 567 regs_buff[83] = adapter->stats.gptc; 568 regs_buff[84] = adapter->stats.gorc; 569 regs_buff[86] = adapter->stats.gotc; 570 regs_buff[88] = adapter->stats.rnbc; 571 regs_buff[89] = adapter->stats.ruc; 572 regs_buff[90] = adapter->stats.rfc; 573 regs_buff[91] = adapter->stats.roc; 574 regs_buff[92] = adapter->stats.rjc; 575 regs_buff[93] = adapter->stats.mgprc; 576 regs_buff[94] = adapter->stats.mgpdc; 577 regs_buff[95] = adapter->stats.mgptc; 578 regs_buff[96] = adapter->stats.tor; 579 regs_buff[98] = adapter->stats.tot; 580 regs_buff[100] = adapter->stats.tpr; 581 regs_buff[101] = adapter->stats.tpt; 582 regs_buff[102] = adapter->stats.ptc64; 583 regs_buff[103] = adapter->stats.ptc127; 584 regs_buff[104] = adapter->stats.ptc255; 585 regs_buff[105] = adapter->stats.ptc511; 586 regs_buff[106] = adapter->stats.ptc1023; 587 regs_buff[107] = adapter->stats.ptc1522; 588 regs_buff[108] = adapter->stats.mptc; 589 regs_buff[109] = adapter->stats.bptc; 590 regs_buff[110] = adapter->stats.tsctc; 591 regs_buff[111] = adapter->stats.iac; 592 regs_buff[112] = adapter->stats.rpthc; 593 regs_buff[113] = adapter->stats.hgptc; 594 regs_buff[114] = adapter->stats.hgorc; 595 regs_buff[116] = adapter->stats.hgotc; 596 regs_buff[118] = adapter->stats.lenerrs; 597 regs_buff[119] = adapter->stats.scvpc; 598 regs_buff[120] = adapter->stats.hrmpc; 599 600 for (i = 0; i < 4; i++) 601 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 602 for (i = 0; i < 4; i++) 603 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 604 for (i = 0; i < 4; i++) 605 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 606 for (i = 0; i < 4; i++) 607 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 608 for (i = 0; i < 4; i++) 609 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 610 for (i = 0; i < 4; i++) 611 regs_buff[141 + i] = rd32(E1000_RDH(i)); 612 for (i = 0; i < 4; i++) 613 regs_buff[145 + i] = rd32(E1000_RDT(i)); 614 for (i = 0; i < 4; i++) 615 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 616 617 for (i = 0; i < 10; i++) 618 regs_buff[153 + i] = rd32(E1000_EITR(i)); 619 for (i = 0; i < 8; i++) 620 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 621 for (i = 0; i < 8; i++) 622 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 623 for (i = 0; i < 16; i++) 624 regs_buff[179 + i] = rd32(E1000_RAL(i)); 625 for (i = 0; i < 16; i++) 626 regs_buff[195 + i] = rd32(E1000_RAH(i)); 627 628 for (i = 0; i < 4; i++) 629 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 630 for (i = 0; i < 4; i++) 631 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 632 for (i = 0; i < 4; i++) 633 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 634 for (i = 0; i < 4; i++) 635 regs_buff[223 + i] = rd32(E1000_TDH(i)); 636 for (i = 0; i < 4; i++) 637 regs_buff[227 + i] = rd32(E1000_TDT(i)); 638 for (i = 0; i < 4; i++) 639 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 640 for (i = 0; i < 4; i++) 641 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 642 for (i = 0; i < 4; i++) 643 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 644 for (i = 0; i < 4; i++) 645 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 646 647 for (i = 0; i < 4; i++) 648 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 649 for (i = 0; i < 4; i++) 650 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 651 for (i = 0; i < 32; i++) 652 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 653 for (i = 0; i < 128; i++) 654 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 655 for (i = 0; i < 128; i++) 656 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 657 for (i = 0; i < 4; i++) 658 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 659 660 regs_buff[547] = rd32(E1000_TDFH); 661 regs_buff[548] = rd32(E1000_TDFT); 662 regs_buff[549] = rd32(E1000_TDFHS); 663 regs_buff[550] = rd32(E1000_TDFPC); 664 665 if (hw->mac.type > e1000_82580) { 666 regs_buff[551] = adapter->stats.o2bgptc; 667 regs_buff[552] = adapter->stats.b2ospc; 668 regs_buff[553] = adapter->stats.o2bspc; 669 regs_buff[554] = adapter->stats.b2ogprc; 670 } 671 672 if (hw->mac.type != e1000_82576) 673 return; 674 for (i = 0; i < 12; i++) 675 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 676 for (i = 0; i < 4; i++) 677 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 678 for (i = 0; i < 12; i++) 679 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 680 for (i = 0; i < 12; i++) 681 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 682 for (i = 0; i < 12; i++) 683 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 684 for (i = 0; i < 12; i++) 685 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 686 for (i = 0; i < 12; i++) 687 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 688 for (i = 0; i < 12; i++) 689 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 690 691 for (i = 0; i < 12; i++) 692 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 693 for (i = 0; i < 12; i++) 694 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 695 for (i = 0; i < 12; i++) 696 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 697 for (i = 0; i < 12; i++) 698 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 699 for (i = 0; i < 12; i++) 700 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 701 for (i = 0; i < 12; i++) 702 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 703 for (i = 0; i < 12; i++) 704 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 705 for (i = 0; i < 12; i++) 706 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 707 } 708 709 static int igb_get_eeprom_len(struct net_device *netdev) 710 { 711 struct igb_adapter *adapter = netdev_priv(netdev); 712 return adapter->hw.nvm.word_size * 2; 713 } 714 715 static int igb_get_eeprom(struct net_device *netdev, 716 struct ethtool_eeprom *eeprom, u8 *bytes) 717 { 718 struct igb_adapter *adapter = netdev_priv(netdev); 719 struct e1000_hw *hw = &adapter->hw; 720 u16 *eeprom_buff; 721 int first_word, last_word; 722 int ret_val = 0; 723 u16 i; 724 725 if (eeprom->len == 0) 726 return -EINVAL; 727 728 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 729 730 first_word = eeprom->offset >> 1; 731 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 732 733 eeprom_buff = kmalloc(sizeof(u16) * 734 (last_word - first_word + 1), GFP_KERNEL); 735 if (!eeprom_buff) 736 return -ENOMEM; 737 738 if (hw->nvm.type == e1000_nvm_eeprom_spi) 739 ret_val = hw->nvm.ops.read(hw, first_word, 740 last_word - first_word + 1, 741 eeprom_buff); 742 else { 743 for (i = 0; i < last_word - first_word + 1; i++) { 744 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 745 &eeprom_buff[i]); 746 if (ret_val) 747 break; 748 } 749 } 750 751 /* Device's eeprom is always little-endian, word addressable */ 752 for (i = 0; i < last_word - first_word + 1; i++) 753 le16_to_cpus(&eeprom_buff[i]); 754 755 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 756 eeprom->len); 757 kfree(eeprom_buff); 758 759 return ret_val; 760 } 761 762 static int igb_set_eeprom(struct net_device *netdev, 763 struct ethtool_eeprom *eeprom, u8 *bytes) 764 { 765 struct igb_adapter *adapter = netdev_priv(netdev); 766 struct e1000_hw *hw = &adapter->hw; 767 u16 *eeprom_buff; 768 void *ptr; 769 int max_len, first_word, last_word, ret_val = 0; 770 u16 i; 771 772 if (eeprom->len == 0) 773 return -EOPNOTSUPP; 774 775 if ((hw->mac.type >= e1000_i210) && 776 !igb_get_flash_presence_i210(hw)) { 777 return -EOPNOTSUPP; 778 } 779 780 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 781 return -EFAULT; 782 783 max_len = hw->nvm.word_size * 2; 784 785 first_word = eeprom->offset >> 1; 786 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 787 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 788 if (!eeprom_buff) 789 return -ENOMEM; 790 791 ptr = (void *)eeprom_buff; 792 793 if (eeprom->offset & 1) { 794 /* need read/modify/write of first changed EEPROM word 795 * only the second byte of the word is being modified 796 */ 797 ret_val = hw->nvm.ops.read(hw, first_word, 1, 798 &eeprom_buff[0]); 799 ptr++; 800 } 801 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 802 /* need read/modify/write of last changed EEPROM word 803 * only the first byte of the word is being modified 804 */ 805 ret_val = hw->nvm.ops.read(hw, last_word, 1, 806 &eeprom_buff[last_word - first_word]); 807 } 808 809 /* Device's eeprom is always little-endian, word addressable */ 810 for (i = 0; i < last_word - first_word + 1; i++) 811 le16_to_cpus(&eeprom_buff[i]); 812 813 memcpy(ptr, bytes, eeprom->len); 814 815 for (i = 0; i < last_word - first_word + 1; i++) 816 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 817 818 ret_val = hw->nvm.ops.write(hw, first_word, 819 last_word - first_word + 1, eeprom_buff); 820 821 /* Update the checksum if nvm write succeeded */ 822 if (ret_val == 0) 823 hw->nvm.ops.update(hw); 824 825 igb_set_fw_version(adapter); 826 kfree(eeprom_buff); 827 return ret_val; 828 } 829 830 static void igb_get_drvinfo(struct net_device *netdev, 831 struct ethtool_drvinfo *drvinfo) 832 { 833 struct igb_adapter *adapter = netdev_priv(netdev); 834 835 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 836 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 837 838 /* EEPROM image version # is reported as firmware version # for 839 * 82575 controllers 840 */ 841 strlcpy(drvinfo->fw_version, adapter->fw_version, 842 sizeof(drvinfo->fw_version)); 843 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 844 sizeof(drvinfo->bus_info)); 845 } 846 847 static void igb_get_ringparam(struct net_device *netdev, 848 struct ethtool_ringparam *ring) 849 { 850 struct igb_adapter *adapter = netdev_priv(netdev); 851 852 ring->rx_max_pending = IGB_MAX_RXD; 853 ring->tx_max_pending = IGB_MAX_TXD; 854 ring->rx_pending = adapter->rx_ring_count; 855 ring->tx_pending = adapter->tx_ring_count; 856 } 857 858 static int igb_set_ringparam(struct net_device *netdev, 859 struct ethtool_ringparam *ring) 860 { 861 struct igb_adapter *adapter = netdev_priv(netdev); 862 struct igb_ring *temp_ring; 863 int i, err = 0; 864 u16 new_rx_count, new_tx_count; 865 866 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 867 return -EINVAL; 868 869 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 870 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 871 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 872 873 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 874 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 875 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 876 877 if ((new_tx_count == adapter->tx_ring_count) && 878 (new_rx_count == adapter->rx_ring_count)) { 879 /* nothing to do */ 880 return 0; 881 } 882 883 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 884 usleep_range(1000, 2000); 885 886 if (!netif_running(adapter->netdev)) { 887 for (i = 0; i < adapter->num_tx_queues; i++) 888 adapter->tx_ring[i]->count = new_tx_count; 889 for (i = 0; i < adapter->num_rx_queues; i++) 890 adapter->rx_ring[i]->count = new_rx_count; 891 adapter->tx_ring_count = new_tx_count; 892 adapter->rx_ring_count = new_rx_count; 893 goto clear_reset; 894 } 895 896 if (adapter->num_tx_queues > adapter->num_rx_queues) 897 temp_ring = vmalloc(adapter->num_tx_queues * 898 sizeof(struct igb_ring)); 899 else 900 temp_ring = vmalloc(adapter->num_rx_queues * 901 sizeof(struct igb_ring)); 902 903 if (!temp_ring) { 904 err = -ENOMEM; 905 goto clear_reset; 906 } 907 908 igb_down(adapter); 909 910 /* We can't just free everything and then setup again, 911 * because the ISRs in MSI-X mode get passed pointers 912 * to the Tx and Rx ring structs. 913 */ 914 if (new_tx_count != adapter->tx_ring_count) { 915 for (i = 0; i < adapter->num_tx_queues; i++) { 916 memcpy(&temp_ring[i], adapter->tx_ring[i], 917 sizeof(struct igb_ring)); 918 919 temp_ring[i].count = new_tx_count; 920 err = igb_setup_tx_resources(&temp_ring[i]); 921 if (err) { 922 while (i) { 923 i--; 924 igb_free_tx_resources(&temp_ring[i]); 925 } 926 goto err_setup; 927 } 928 } 929 930 for (i = 0; i < adapter->num_tx_queues; i++) { 931 igb_free_tx_resources(adapter->tx_ring[i]); 932 933 memcpy(adapter->tx_ring[i], &temp_ring[i], 934 sizeof(struct igb_ring)); 935 } 936 937 adapter->tx_ring_count = new_tx_count; 938 } 939 940 if (new_rx_count != adapter->rx_ring_count) { 941 for (i = 0; i < adapter->num_rx_queues; i++) { 942 memcpy(&temp_ring[i], adapter->rx_ring[i], 943 sizeof(struct igb_ring)); 944 945 temp_ring[i].count = new_rx_count; 946 err = igb_setup_rx_resources(&temp_ring[i]); 947 if (err) { 948 while (i) { 949 i--; 950 igb_free_rx_resources(&temp_ring[i]); 951 } 952 goto err_setup; 953 } 954 955 } 956 957 for (i = 0; i < adapter->num_rx_queues; i++) { 958 igb_free_rx_resources(adapter->rx_ring[i]); 959 960 memcpy(adapter->rx_ring[i], &temp_ring[i], 961 sizeof(struct igb_ring)); 962 } 963 964 adapter->rx_ring_count = new_rx_count; 965 } 966 err_setup: 967 igb_up(adapter); 968 vfree(temp_ring); 969 clear_reset: 970 clear_bit(__IGB_RESETTING, &adapter->state); 971 return err; 972 } 973 974 /* ethtool register test data */ 975 struct igb_reg_test { 976 u16 reg; 977 u16 reg_offset; 978 u16 array_len; 979 u16 test_type; 980 u32 mask; 981 u32 write; 982 }; 983 984 /* In the hardware, registers are laid out either singly, in arrays 985 * spaced 0x100 bytes apart, or in contiguous tables. We assume 986 * most tests take place on arrays or single registers (handled 987 * as a single-element array) and special-case the tables. 988 * Table tests are always pattern tests. 989 * 990 * We also make provision for some required setup steps by specifying 991 * registers to be written without any read-back testing. 992 */ 993 994 #define PATTERN_TEST 1 995 #define SET_READ_TEST 2 996 #define WRITE_NO_TEST 3 997 #define TABLE32_TEST 4 998 #define TABLE64_TEST_LO 5 999 #define TABLE64_TEST_HI 6 1000 1001 /* i210 reg test */ 1002 static struct igb_reg_test reg_test_i210[] = { 1003 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1004 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1005 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1006 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1007 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1008 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1009 /* RDH is read-only for i210, only test RDT. */ 1010 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1011 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1012 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1013 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1014 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1015 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1016 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1017 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1018 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1019 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1020 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1021 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1022 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1023 0xFFFFFFFF, 0xFFFFFFFF }, 1024 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1025 0x900FFFFF, 0xFFFFFFFF }, 1026 { E1000_MTA, 0, 128, TABLE32_TEST, 1027 0xFFFFFFFF, 0xFFFFFFFF }, 1028 { 0, 0, 0, 0, 0 } 1029 }; 1030 1031 /* i350 reg test */ 1032 static struct igb_reg_test reg_test_i350[] = { 1033 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1034 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1035 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1036 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1037 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1038 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1039 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1040 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1041 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1042 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1043 /* RDH is read-only for i350, only test RDT. */ 1044 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1045 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1046 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1047 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1048 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1049 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1050 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1051 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1052 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1053 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1054 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1055 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1056 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1057 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1058 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1059 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1060 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1061 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1062 0xFFFFFFFF, 0xFFFFFFFF }, 1063 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1064 0xC3FFFFFF, 0xFFFFFFFF }, 1065 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1066 0xFFFFFFFF, 0xFFFFFFFF }, 1067 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1068 0xC3FFFFFF, 0xFFFFFFFF }, 1069 { E1000_MTA, 0, 128, TABLE32_TEST, 1070 0xFFFFFFFF, 0xFFFFFFFF }, 1071 { 0, 0, 0, 0 } 1072 }; 1073 1074 /* 82580 reg test */ 1075 static struct igb_reg_test reg_test_82580[] = { 1076 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1077 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1078 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1079 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1080 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1081 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1082 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1083 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1084 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1085 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1086 /* RDH is read-only for 82580, only test RDT. */ 1087 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1088 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1089 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1090 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1091 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1092 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1093 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1094 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1095 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1096 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1097 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1098 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1099 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1100 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1101 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1102 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1103 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1104 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1105 0xFFFFFFFF, 0xFFFFFFFF }, 1106 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1107 0x83FFFFFF, 0xFFFFFFFF }, 1108 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1109 0xFFFFFFFF, 0xFFFFFFFF }, 1110 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1111 0x83FFFFFF, 0xFFFFFFFF }, 1112 { E1000_MTA, 0, 128, TABLE32_TEST, 1113 0xFFFFFFFF, 0xFFFFFFFF }, 1114 { 0, 0, 0, 0 } 1115 }; 1116 1117 /* 82576 reg test */ 1118 static struct igb_reg_test reg_test_82576[] = { 1119 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1120 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1121 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1122 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1123 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1124 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1125 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1126 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1127 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1128 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1129 /* Enable all RX queues before testing. */ 1130 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1131 E1000_RXDCTL_QUEUE_ENABLE }, 1132 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1133 E1000_RXDCTL_QUEUE_ENABLE }, 1134 /* RDH is read-only for 82576, only test RDT. */ 1135 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1136 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1137 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1138 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1139 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1140 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1141 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1142 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1143 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1144 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1145 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1146 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1147 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1148 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1149 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1150 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1151 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1152 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1153 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1154 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1155 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1156 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1157 { 0, 0, 0, 0 } 1158 }; 1159 1160 /* 82575 register test */ 1161 static struct igb_reg_test reg_test_82575[] = { 1162 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1163 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1164 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1165 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1166 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1167 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1168 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1169 /* Enable all four RX queues before testing. */ 1170 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1171 E1000_RXDCTL_QUEUE_ENABLE }, 1172 /* RDH is read-only for 82575, only test RDT. */ 1173 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1174 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1175 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1176 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1177 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1178 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1179 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1180 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1181 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1182 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1183 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1184 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1185 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1186 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1187 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1188 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1189 { 0, 0, 0, 0 } 1190 }; 1191 1192 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1193 int reg, u32 mask, u32 write) 1194 { 1195 struct e1000_hw *hw = &adapter->hw; 1196 u32 pat, val; 1197 static const u32 _test[] = { 1198 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1199 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1200 wr32(reg, (_test[pat] & write)); 1201 val = rd32(reg) & mask; 1202 if (val != (_test[pat] & write & mask)) { 1203 dev_err(&adapter->pdev->dev, 1204 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1205 reg, val, (_test[pat] & write & mask)); 1206 *data = reg; 1207 return true; 1208 } 1209 } 1210 1211 return false; 1212 } 1213 1214 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1215 int reg, u32 mask, u32 write) 1216 { 1217 struct e1000_hw *hw = &adapter->hw; 1218 u32 val; 1219 1220 wr32(reg, write & mask); 1221 val = rd32(reg); 1222 if ((write & mask) != (val & mask)) { 1223 dev_err(&adapter->pdev->dev, 1224 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1225 reg, (val & mask), (write & mask)); 1226 *data = reg; 1227 return true; 1228 } 1229 1230 return false; 1231 } 1232 1233 #define REG_PATTERN_TEST(reg, mask, write) \ 1234 do { \ 1235 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1236 return 1; \ 1237 } while (0) 1238 1239 #define REG_SET_AND_CHECK(reg, mask, write) \ 1240 do { \ 1241 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1242 return 1; \ 1243 } while (0) 1244 1245 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1246 { 1247 struct e1000_hw *hw = &adapter->hw; 1248 struct igb_reg_test *test; 1249 u32 value, before, after; 1250 u32 i, toggle; 1251 1252 switch (adapter->hw.mac.type) { 1253 case e1000_i350: 1254 case e1000_i354: 1255 test = reg_test_i350; 1256 toggle = 0x7FEFF3FF; 1257 break; 1258 case e1000_i210: 1259 case e1000_i211: 1260 test = reg_test_i210; 1261 toggle = 0x7FEFF3FF; 1262 break; 1263 case e1000_82580: 1264 test = reg_test_82580; 1265 toggle = 0x7FEFF3FF; 1266 break; 1267 case e1000_82576: 1268 test = reg_test_82576; 1269 toggle = 0x7FFFF3FF; 1270 break; 1271 default: 1272 test = reg_test_82575; 1273 toggle = 0x7FFFF3FF; 1274 break; 1275 } 1276 1277 /* Because the status register is such a special case, 1278 * we handle it separately from the rest of the register 1279 * tests. Some bits are read-only, some toggle, and some 1280 * are writable on newer MACs. 1281 */ 1282 before = rd32(E1000_STATUS); 1283 value = (rd32(E1000_STATUS) & toggle); 1284 wr32(E1000_STATUS, toggle); 1285 after = rd32(E1000_STATUS) & toggle; 1286 if (value != after) { 1287 dev_err(&adapter->pdev->dev, 1288 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1289 after, value); 1290 *data = 1; 1291 return 1; 1292 } 1293 /* restore previous status */ 1294 wr32(E1000_STATUS, before); 1295 1296 /* Perform the remainder of the register test, looping through 1297 * the test table until we either fail or reach the null entry. 1298 */ 1299 while (test->reg) { 1300 for (i = 0; i < test->array_len; i++) { 1301 switch (test->test_type) { 1302 case PATTERN_TEST: 1303 REG_PATTERN_TEST(test->reg + 1304 (i * test->reg_offset), 1305 test->mask, 1306 test->write); 1307 break; 1308 case SET_READ_TEST: 1309 REG_SET_AND_CHECK(test->reg + 1310 (i * test->reg_offset), 1311 test->mask, 1312 test->write); 1313 break; 1314 case WRITE_NO_TEST: 1315 writel(test->write, 1316 (adapter->hw.hw_addr + test->reg) 1317 + (i * test->reg_offset)); 1318 break; 1319 case TABLE32_TEST: 1320 REG_PATTERN_TEST(test->reg + (i * 4), 1321 test->mask, 1322 test->write); 1323 break; 1324 case TABLE64_TEST_LO: 1325 REG_PATTERN_TEST(test->reg + (i * 8), 1326 test->mask, 1327 test->write); 1328 break; 1329 case TABLE64_TEST_HI: 1330 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1331 test->mask, 1332 test->write); 1333 break; 1334 } 1335 } 1336 test++; 1337 } 1338 1339 *data = 0; 1340 return 0; 1341 } 1342 1343 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1344 { 1345 struct e1000_hw *hw = &adapter->hw; 1346 1347 *data = 0; 1348 1349 /* Validate eeprom on all parts but flashless */ 1350 switch (hw->mac.type) { 1351 case e1000_i210: 1352 case e1000_i211: 1353 if (igb_get_flash_presence_i210(hw)) { 1354 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1355 *data = 2; 1356 } 1357 break; 1358 default: 1359 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1360 *data = 2; 1361 break; 1362 } 1363 1364 return *data; 1365 } 1366 1367 static irqreturn_t igb_test_intr(int irq, void *data) 1368 { 1369 struct igb_adapter *adapter = (struct igb_adapter *) data; 1370 struct e1000_hw *hw = &adapter->hw; 1371 1372 adapter->test_icr |= rd32(E1000_ICR); 1373 1374 return IRQ_HANDLED; 1375 } 1376 1377 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1378 { 1379 struct e1000_hw *hw = &adapter->hw; 1380 struct net_device *netdev = adapter->netdev; 1381 u32 mask, ics_mask, i = 0, shared_int = true; 1382 u32 irq = adapter->pdev->irq; 1383 1384 *data = 0; 1385 1386 /* Hook up test interrupt handler just for this test */ 1387 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1388 if (request_irq(adapter->msix_entries[0].vector, 1389 igb_test_intr, 0, netdev->name, adapter)) { 1390 *data = 1; 1391 return -1; 1392 } 1393 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1394 shared_int = false; 1395 if (request_irq(irq, 1396 igb_test_intr, 0, netdev->name, adapter)) { 1397 *data = 1; 1398 return -1; 1399 } 1400 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1401 netdev->name, adapter)) { 1402 shared_int = false; 1403 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1404 netdev->name, adapter)) { 1405 *data = 1; 1406 return -1; 1407 } 1408 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1409 (shared_int ? "shared" : "unshared")); 1410 1411 /* Disable all the interrupts */ 1412 wr32(E1000_IMC, ~0); 1413 wrfl(); 1414 usleep_range(10000, 11000); 1415 1416 /* Define all writable bits for ICS */ 1417 switch (hw->mac.type) { 1418 case e1000_82575: 1419 ics_mask = 0x37F47EDD; 1420 break; 1421 case e1000_82576: 1422 ics_mask = 0x77D4FBFD; 1423 break; 1424 case e1000_82580: 1425 ics_mask = 0x77DCFED5; 1426 break; 1427 case e1000_i350: 1428 case e1000_i354: 1429 case e1000_i210: 1430 case e1000_i211: 1431 ics_mask = 0x77DCFED5; 1432 break; 1433 default: 1434 ics_mask = 0x7FFFFFFF; 1435 break; 1436 } 1437 1438 /* Test each interrupt */ 1439 for (; i < 31; i++) { 1440 /* Interrupt to test */ 1441 mask = 1 << i; 1442 1443 if (!(mask & ics_mask)) 1444 continue; 1445 1446 if (!shared_int) { 1447 /* Disable the interrupt to be reported in 1448 * the cause register and then force the same 1449 * interrupt and see if one gets posted. If 1450 * an interrupt was posted to the bus, the 1451 * test failed. 1452 */ 1453 adapter->test_icr = 0; 1454 1455 /* Flush any pending interrupts */ 1456 wr32(E1000_ICR, ~0); 1457 1458 wr32(E1000_IMC, mask); 1459 wr32(E1000_ICS, mask); 1460 wrfl(); 1461 usleep_range(10000, 11000); 1462 1463 if (adapter->test_icr & mask) { 1464 *data = 3; 1465 break; 1466 } 1467 } 1468 1469 /* Enable the interrupt to be reported in 1470 * the cause register and then force the same 1471 * interrupt and see if one gets posted. If 1472 * an interrupt was not posted to the bus, the 1473 * test failed. 1474 */ 1475 adapter->test_icr = 0; 1476 1477 /* Flush any pending interrupts */ 1478 wr32(E1000_ICR, ~0); 1479 1480 wr32(E1000_IMS, mask); 1481 wr32(E1000_ICS, mask); 1482 wrfl(); 1483 usleep_range(10000, 11000); 1484 1485 if (!(adapter->test_icr & mask)) { 1486 *data = 4; 1487 break; 1488 } 1489 1490 if (!shared_int) { 1491 /* Disable the other interrupts to be reported in 1492 * the cause register and then force the other 1493 * interrupts and see if any get posted. If 1494 * an interrupt was posted to the bus, the 1495 * test failed. 1496 */ 1497 adapter->test_icr = 0; 1498 1499 /* Flush any pending interrupts */ 1500 wr32(E1000_ICR, ~0); 1501 1502 wr32(E1000_IMC, ~mask); 1503 wr32(E1000_ICS, ~mask); 1504 wrfl(); 1505 usleep_range(10000, 11000); 1506 1507 if (adapter->test_icr & mask) { 1508 *data = 5; 1509 break; 1510 } 1511 } 1512 } 1513 1514 /* Disable all the interrupts */ 1515 wr32(E1000_IMC, ~0); 1516 wrfl(); 1517 usleep_range(10000, 11000); 1518 1519 /* Unhook test interrupt handler */ 1520 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1521 free_irq(adapter->msix_entries[0].vector, adapter); 1522 else 1523 free_irq(irq, adapter); 1524 1525 return *data; 1526 } 1527 1528 static void igb_free_desc_rings(struct igb_adapter *adapter) 1529 { 1530 igb_free_tx_resources(&adapter->test_tx_ring); 1531 igb_free_rx_resources(&adapter->test_rx_ring); 1532 } 1533 1534 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1535 { 1536 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1537 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1538 struct e1000_hw *hw = &adapter->hw; 1539 int ret_val; 1540 1541 /* Setup Tx descriptor ring and Tx buffers */ 1542 tx_ring->count = IGB_DEFAULT_TXD; 1543 tx_ring->dev = &adapter->pdev->dev; 1544 tx_ring->netdev = adapter->netdev; 1545 tx_ring->reg_idx = adapter->vfs_allocated_count; 1546 1547 if (igb_setup_tx_resources(tx_ring)) { 1548 ret_val = 1; 1549 goto err_nomem; 1550 } 1551 1552 igb_setup_tctl(adapter); 1553 igb_configure_tx_ring(adapter, tx_ring); 1554 1555 /* Setup Rx descriptor ring and Rx buffers */ 1556 rx_ring->count = IGB_DEFAULT_RXD; 1557 rx_ring->dev = &adapter->pdev->dev; 1558 rx_ring->netdev = adapter->netdev; 1559 rx_ring->reg_idx = adapter->vfs_allocated_count; 1560 1561 if (igb_setup_rx_resources(rx_ring)) { 1562 ret_val = 3; 1563 goto err_nomem; 1564 } 1565 1566 /* set the default queue to queue 0 of PF */ 1567 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1568 1569 /* enable receive ring */ 1570 igb_setup_rctl(adapter); 1571 igb_configure_rx_ring(adapter, rx_ring); 1572 1573 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1574 1575 return 0; 1576 1577 err_nomem: 1578 igb_free_desc_rings(adapter); 1579 return ret_val; 1580 } 1581 1582 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1583 { 1584 struct e1000_hw *hw = &adapter->hw; 1585 1586 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1587 igb_write_phy_reg(hw, 29, 0x001F); 1588 igb_write_phy_reg(hw, 30, 0x8FFC); 1589 igb_write_phy_reg(hw, 29, 0x001A); 1590 igb_write_phy_reg(hw, 30, 0x8FF0); 1591 } 1592 1593 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1594 { 1595 struct e1000_hw *hw = &adapter->hw; 1596 u32 ctrl_reg = 0; 1597 1598 hw->mac.autoneg = false; 1599 1600 if (hw->phy.type == e1000_phy_m88) { 1601 if (hw->phy.id != I210_I_PHY_ID) { 1602 /* Auto-MDI/MDIX Off */ 1603 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1604 /* reset to update Auto-MDI/MDIX */ 1605 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1606 /* autoneg off */ 1607 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1608 } else { 1609 /* force 1000, set loopback */ 1610 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1611 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1612 } 1613 } else if (hw->phy.type == e1000_phy_82580) { 1614 /* enable MII loopback */ 1615 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1616 } 1617 1618 /* add small delay to avoid loopback test failure */ 1619 msleep(50); 1620 1621 /* force 1000, set loopback */ 1622 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1623 1624 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1625 ctrl_reg = rd32(E1000_CTRL); 1626 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1627 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1628 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1629 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1630 E1000_CTRL_FD | /* Force Duplex to FULL */ 1631 E1000_CTRL_SLU); /* Set link up enable bit */ 1632 1633 if (hw->phy.type == e1000_phy_m88) 1634 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1635 1636 wr32(E1000_CTRL, ctrl_reg); 1637 1638 /* Disable the receiver on the PHY so when a cable is plugged in, the 1639 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1640 */ 1641 if (hw->phy.type == e1000_phy_m88) 1642 igb_phy_disable_receiver(adapter); 1643 1644 mdelay(500); 1645 return 0; 1646 } 1647 1648 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1649 { 1650 return igb_integrated_phy_loopback(adapter); 1651 } 1652 1653 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1654 { 1655 struct e1000_hw *hw = &adapter->hw; 1656 u32 reg; 1657 1658 reg = rd32(E1000_CTRL_EXT); 1659 1660 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1661 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1662 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1663 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1664 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1665 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1666 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1667 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1668 /* Enable DH89xxCC MPHY for near end loopback */ 1669 reg = rd32(E1000_MPHY_ADDR_CTL); 1670 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1671 E1000_MPHY_PCS_CLK_REG_OFFSET; 1672 wr32(E1000_MPHY_ADDR_CTL, reg); 1673 1674 reg = rd32(E1000_MPHY_DATA); 1675 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1676 wr32(E1000_MPHY_DATA, reg); 1677 } 1678 1679 reg = rd32(E1000_RCTL); 1680 reg |= E1000_RCTL_LBM_TCVR; 1681 wr32(E1000_RCTL, reg); 1682 1683 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1684 1685 reg = rd32(E1000_CTRL); 1686 reg &= ~(E1000_CTRL_RFCE | 1687 E1000_CTRL_TFCE | 1688 E1000_CTRL_LRST); 1689 reg |= E1000_CTRL_SLU | 1690 E1000_CTRL_FD; 1691 wr32(E1000_CTRL, reg); 1692 1693 /* Unset switch control to serdes energy detect */ 1694 reg = rd32(E1000_CONNSW); 1695 reg &= ~E1000_CONNSW_ENRGSRC; 1696 wr32(E1000_CONNSW, reg); 1697 1698 /* Unset sigdetect for SERDES loopback on 1699 * 82580 and newer devices. 1700 */ 1701 if (hw->mac.type >= e1000_82580) { 1702 reg = rd32(E1000_PCS_CFG0); 1703 reg |= E1000_PCS_CFG_IGN_SD; 1704 wr32(E1000_PCS_CFG0, reg); 1705 } 1706 1707 /* Set PCS register for forced speed */ 1708 reg = rd32(E1000_PCS_LCTL); 1709 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1710 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1711 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1712 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1713 E1000_PCS_LCTL_FSD | /* Force Speed */ 1714 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1715 wr32(E1000_PCS_LCTL, reg); 1716 1717 return 0; 1718 } 1719 1720 return igb_set_phy_loopback(adapter); 1721 } 1722 1723 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1724 { 1725 struct e1000_hw *hw = &adapter->hw; 1726 u32 rctl; 1727 u16 phy_reg; 1728 1729 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1730 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1731 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1732 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1733 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1734 u32 reg; 1735 1736 /* Disable near end loopback on DH89xxCC */ 1737 reg = rd32(E1000_MPHY_ADDR_CTL); 1738 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1739 E1000_MPHY_PCS_CLK_REG_OFFSET; 1740 wr32(E1000_MPHY_ADDR_CTL, reg); 1741 1742 reg = rd32(E1000_MPHY_DATA); 1743 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1744 wr32(E1000_MPHY_DATA, reg); 1745 } 1746 1747 rctl = rd32(E1000_RCTL); 1748 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1749 wr32(E1000_RCTL, rctl); 1750 1751 hw->mac.autoneg = true; 1752 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1753 if (phy_reg & MII_CR_LOOPBACK) { 1754 phy_reg &= ~MII_CR_LOOPBACK; 1755 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1756 igb_phy_sw_reset(hw); 1757 } 1758 } 1759 1760 static void igb_create_lbtest_frame(struct sk_buff *skb, 1761 unsigned int frame_size) 1762 { 1763 memset(skb->data, 0xFF, frame_size); 1764 frame_size /= 2; 1765 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1766 memset(&skb->data[frame_size + 10], 0xBE, 1); 1767 memset(&skb->data[frame_size + 12], 0xAF, 1); 1768 } 1769 1770 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1771 unsigned int frame_size) 1772 { 1773 unsigned char *data; 1774 bool match = true; 1775 1776 frame_size >>= 1; 1777 1778 data = kmap(rx_buffer->page); 1779 1780 if (data[3] != 0xFF || 1781 data[frame_size + 10] != 0xBE || 1782 data[frame_size + 12] != 0xAF) 1783 match = false; 1784 1785 kunmap(rx_buffer->page); 1786 1787 return match; 1788 } 1789 1790 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1791 struct igb_ring *tx_ring, 1792 unsigned int size) 1793 { 1794 union e1000_adv_rx_desc *rx_desc; 1795 struct igb_rx_buffer *rx_buffer_info; 1796 struct igb_tx_buffer *tx_buffer_info; 1797 u16 rx_ntc, tx_ntc, count = 0; 1798 1799 /* initialize next to clean and descriptor values */ 1800 rx_ntc = rx_ring->next_to_clean; 1801 tx_ntc = tx_ring->next_to_clean; 1802 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1803 1804 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1805 /* check Rx buffer */ 1806 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1807 1808 /* sync Rx buffer for CPU read */ 1809 dma_sync_single_for_cpu(rx_ring->dev, 1810 rx_buffer_info->dma, 1811 IGB_RX_BUFSZ, 1812 DMA_FROM_DEVICE); 1813 1814 /* verify contents of skb */ 1815 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1816 count++; 1817 1818 /* sync Rx buffer for device write */ 1819 dma_sync_single_for_device(rx_ring->dev, 1820 rx_buffer_info->dma, 1821 IGB_RX_BUFSZ, 1822 DMA_FROM_DEVICE); 1823 1824 /* unmap buffer on Tx side */ 1825 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1826 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1827 1828 /* increment Rx/Tx next to clean counters */ 1829 rx_ntc++; 1830 if (rx_ntc == rx_ring->count) 1831 rx_ntc = 0; 1832 tx_ntc++; 1833 if (tx_ntc == tx_ring->count) 1834 tx_ntc = 0; 1835 1836 /* fetch next descriptor */ 1837 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1838 } 1839 1840 netdev_tx_reset_queue(txring_txq(tx_ring)); 1841 1842 /* re-map buffers to ring, store next to clean values */ 1843 igb_alloc_rx_buffers(rx_ring, count); 1844 rx_ring->next_to_clean = rx_ntc; 1845 tx_ring->next_to_clean = tx_ntc; 1846 1847 return count; 1848 } 1849 1850 static int igb_run_loopback_test(struct igb_adapter *adapter) 1851 { 1852 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1853 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1854 u16 i, j, lc, good_cnt; 1855 int ret_val = 0; 1856 unsigned int size = IGB_RX_HDR_LEN; 1857 netdev_tx_t tx_ret_val; 1858 struct sk_buff *skb; 1859 1860 /* allocate test skb */ 1861 skb = alloc_skb(size, GFP_KERNEL); 1862 if (!skb) 1863 return 11; 1864 1865 /* place data into test skb */ 1866 igb_create_lbtest_frame(skb, size); 1867 skb_put(skb, size); 1868 1869 /* Calculate the loop count based on the largest descriptor ring 1870 * The idea is to wrap the largest ring a number of times using 64 1871 * send/receive pairs during each loop 1872 */ 1873 1874 if (rx_ring->count <= tx_ring->count) 1875 lc = ((tx_ring->count / 64) * 2) + 1; 1876 else 1877 lc = ((rx_ring->count / 64) * 2) + 1; 1878 1879 for (j = 0; j <= lc; j++) { /* loop count loop */ 1880 /* reset count of good packets */ 1881 good_cnt = 0; 1882 1883 /* place 64 packets on the transmit queue*/ 1884 for (i = 0; i < 64; i++) { 1885 skb_get(skb); 1886 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1887 if (tx_ret_val == NETDEV_TX_OK) 1888 good_cnt++; 1889 } 1890 1891 if (good_cnt != 64) { 1892 ret_val = 12; 1893 break; 1894 } 1895 1896 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1897 msleep(200); 1898 1899 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1900 if (good_cnt != 64) { 1901 ret_val = 13; 1902 break; 1903 } 1904 } /* end loop count loop */ 1905 1906 /* free the original skb */ 1907 kfree_skb(skb); 1908 1909 return ret_val; 1910 } 1911 1912 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1913 { 1914 /* PHY loopback cannot be performed if SoL/IDER 1915 * sessions are active 1916 */ 1917 if (igb_check_reset_block(&adapter->hw)) { 1918 dev_err(&adapter->pdev->dev, 1919 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1920 *data = 0; 1921 goto out; 1922 } 1923 1924 if (adapter->hw.mac.type == e1000_i354) { 1925 dev_info(&adapter->pdev->dev, 1926 "Loopback test not supported on i354.\n"); 1927 *data = 0; 1928 goto out; 1929 } 1930 *data = igb_setup_desc_rings(adapter); 1931 if (*data) 1932 goto out; 1933 *data = igb_setup_loopback_test(adapter); 1934 if (*data) 1935 goto err_loopback; 1936 *data = igb_run_loopback_test(adapter); 1937 igb_loopback_cleanup(adapter); 1938 1939 err_loopback: 1940 igb_free_desc_rings(adapter); 1941 out: 1942 return *data; 1943 } 1944 1945 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1946 { 1947 struct e1000_hw *hw = &adapter->hw; 1948 *data = 0; 1949 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1950 int i = 0; 1951 1952 hw->mac.serdes_has_link = false; 1953 1954 /* On some blade server designs, link establishment 1955 * could take as long as 2-3 minutes 1956 */ 1957 do { 1958 hw->mac.ops.check_for_link(&adapter->hw); 1959 if (hw->mac.serdes_has_link) 1960 return *data; 1961 msleep(20); 1962 } while (i++ < 3750); 1963 1964 *data = 1; 1965 } else { 1966 hw->mac.ops.check_for_link(&adapter->hw); 1967 if (hw->mac.autoneg) 1968 msleep(5000); 1969 1970 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1971 *data = 1; 1972 } 1973 return *data; 1974 } 1975 1976 static void igb_diag_test(struct net_device *netdev, 1977 struct ethtool_test *eth_test, u64 *data) 1978 { 1979 struct igb_adapter *adapter = netdev_priv(netdev); 1980 u16 autoneg_advertised; 1981 u8 forced_speed_duplex, autoneg; 1982 bool if_running = netif_running(netdev); 1983 1984 set_bit(__IGB_TESTING, &adapter->state); 1985 1986 /* can't do offline tests on media switching devices */ 1987 if (adapter->hw.dev_spec._82575.mas_capable) 1988 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 1989 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1990 /* Offline tests */ 1991 1992 /* save speed, duplex, autoneg settings */ 1993 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 1994 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 1995 autoneg = adapter->hw.mac.autoneg; 1996 1997 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 1998 1999 /* power up link for link test */ 2000 igb_power_up_link(adapter); 2001 2002 /* Link test performed before hardware reset so autoneg doesn't 2003 * interfere with test result 2004 */ 2005 if (igb_link_test(adapter, &data[4])) 2006 eth_test->flags |= ETH_TEST_FL_FAILED; 2007 2008 if (if_running) 2009 /* indicate we're in test mode */ 2010 dev_close(netdev); 2011 else 2012 igb_reset(adapter); 2013 2014 if (igb_reg_test(adapter, &data[0])) 2015 eth_test->flags |= ETH_TEST_FL_FAILED; 2016 2017 igb_reset(adapter); 2018 if (igb_eeprom_test(adapter, &data[1])) 2019 eth_test->flags |= ETH_TEST_FL_FAILED; 2020 2021 igb_reset(adapter); 2022 if (igb_intr_test(adapter, &data[2])) 2023 eth_test->flags |= ETH_TEST_FL_FAILED; 2024 2025 igb_reset(adapter); 2026 /* power up link for loopback test */ 2027 igb_power_up_link(adapter); 2028 if (igb_loopback_test(adapter, &data[3])) 2029 eth_test->flags |= ETH_TEST_FL_FAILED; 2030 2031 /* restore speed, duplex, autoneg settings */ 2032 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2033 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2034 adapter->hw.mac.autoneg = autoneg; 2035 2036 /* force this routine to wait until autoneg complete/timeout */ 2037 adapter->hw.phy.autoneg_wait_to_complete = true; 2038 igb_reset(adapter); 2039 adapter->hw.phy.autoneg_wait_to_complete = false; 2040 2041 clear_bit(__IGB_TESTING, &adapter->state); 2042 if (if_running) 2043 dev_open(netdev); 2044 } else { 2045 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2046 2047 /* PHY is powered down when interface is down */ 2048 if (if_running && igb_link_test(adapter, &data[4])) 2049 eth_test->flags |= ETH_TEST_FL_FAILED; 2050 else 2051 data[4] = 0; 2052 2053 /* Online tests aren't run; pass by default */ 2054 data[0] = 0; 2055 data[1] = 0; 2056 data[2] = 0; 2057 data[3] = 0; 2058 2059 clear_bit(__IGB_TESTING, &adapter->state); 2060 } 2061 msleep_interruptible(4 * 1000); 2062 } 2063 2064 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2065 { 2066 struct igb_adapter *adapter = netdev_priv(netdev); 2067 2068 wol->wolopts = 0; 2069 2070 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2071 return; 2072 2073 wol->supported = WAKE_UCAST | WAKE_MCAST | 2074 WAKE_BCAST | WAKE_MAGIC | 2075 WAKE_PHY; 2076 2077 /* apply any specific unsupported masks here */ 2078 switch (adapter->hw.device_id) { 2079 default: 2080 break; 2081 } 2082 2083 if (adapter->wol & E1000_WUFC_EX) 2084 wol->wolopts |= WAKE_UCAST; 2085 if (adapter->wol & E1000_WUFC_MC) 2086 wol->wolopts |= WAKE_MCAST; 2087 if (adapter->wol & E1000_WUFC_BC) 2088 wol->wolopts |= WAKE_BCAST; 2089 if (adapter->wol & E1000_WUFC_MAG) 2090 wol->wolopts |= WAKE_MAGIC; 2091 if (adapter->wol & E1000_WUFC_LNKC) 2092 wol->wolopts |= WAKE_PHY; 2093 } 2094 2095 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2096 { 2097 struct igb_adapter *adapter = netdev_priv(netdev); 2098 2099 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2100 return -EOPNOTSUPP; 2101 2102 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2103 return wol->wolopts ? -EOPNOTSUPP : 0; 2104 2105 /* these settings will always override what we currently have */ 2106 adapter->wol = 0; 2107 2108 if (wol->wolopts & WAKE_UCAST) 2109 adapter->wol |= E1000_WUFC_EX; 2110 if (wol->wolopts & WAKE_MCAST) 2111 adapter->wol |= E1000_WUFC_MC; 2112 if (wol->wolopts & WAKE_BCAST) 2113 adapter->wol |= E1000_WUFC_BC; 2114 if (wol->wolopts & WAKE_MAGIC) 2115 adapter->wol |= E1000_WUFC_MAG; 2116 if (wol->wolopts & WAKE_PHY) 2117 adapter->wol |= E1000_WUFC_LNKC; 2118 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2119 2120 return 0; 2121 } 2122 2123 /* bit defines for adapter->led_status */ 2124 #define IGB_LED_ON 0 2125 2126 static int igb_set_phys_id(struct net_device *netdev, 2127 enum ethtool_phys_id_state state) 2128 { 2129 struct igb_adapter *adapter = netdev_priv(netdev); 2130 struct e1000_hw *hw = &adapter->hw; 2131 2132 switch (state) { 2133 case ETHTOOL_ID_ACTIVE: 2134 igb_blink_led(hw); 2135 return 2; 2136 case ETHTOOL_ID_ON: 2137 igb_blink_led(hw); 2138 break; 2139 case ETHTOOL_ID_OFF: 2140 igb_led_off(hw); 2141 break; 2142 case ETHTOOL_ID_INACTIVE: 2143 igb_led_off(hw); 2144 clear_bit(IGB_LED_ON, &adapter->led_status); 2145 igb_cleanup_led(hw); 2146 break; 2147 } 2148 2149 return 0; 2150 } 2151 2152 static int igb_set_coalesce(struct net_device *netdev, 2153 struct ethtool_coalesce *ec) 2154 { 2155 struct igb_adapter *adapter = netdev_priv(netdev); 2156 int i; 2157 2158 if (ec->rx_max_coalesced_frames || 2159 ec->rx_coalesce_usecs_irq || 2160 ec->rx_max_coalesced_frames_irq || 2161 ec->tx_max_coalesced_frames || 2162 ec->tx_coalesce_usecs_irq || 2163 ec->stats_block_coalesce_usecs || 2164 ec->use_adaptive_rx_coalesce || 2165 ec->use_adaptive_tx_coalesce || 2166 ec->pkt_rate_low || 2167 ec->rx_coalesce_usecs_low || 2168 ec->rx_max_coalesced_frames_low || 2169 ec->tx_coalesce_usecs_low || 2170 ec->tx_max_coalesced_frames_low || 2171 ec->pkt_rate_high || 2172 ec->rx_coalesce_usecs_high || 2173 ec->rx_max_coalesced_frames_high || 2174 ec->tx_coalesce_usecs_high || 2175 ec->tx_max_coalesced_frames_high || 2176 ec->rate_sample_interval) 2177 return -ENOTSUPP; 2178 2179 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2180 ((ec->rx_coalesce_usecs > 3) && 2181 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2182 (ec->rx_coalesce_usecs == 2)) 2183 return -EINVAL; 2184 2185 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2186 ((ec->tx_coalesce_usecs > 3) && 2187 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2188 (ec->tx_coalesce_usecs == 2)) 2189 return -EINVAL; 2190 2191 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2192 return -EINVAL; 2193 2194 /* If ITR is disabled, disable DMAC */ 2195 if (ec->rx_coalesce_usecs == 0) { 2196 if (adapter->flags & IGB_FLAG_DMAC) 2197 adapter->flags &= ~IGB_FLAG_DMAC; 2198 } 2199 2200 /* convert to rate of irq's per second */ 2201 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2202 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2203 else 2204 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2205 2206 /* convert to rate of irq's per second */ 2207 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2208 adapter->tx_itr_setting = adapter->rx_itr_setting; 2209 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2210 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2211 else 2212 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2213 2214 for (i = 0; i < adapter->num_q_vectors; i++) { 2215 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2216 q_vector->tx.work_limit = adapter->tx_work_limit; 2217 if (q_vector->rx.ring) 2218 q_vector->itr_val = adapter->rx_itr_setting; 2219 else 2220 q_vector->itr_val = adapter->tx_itr_setting; 2221 if (q_vector->itr_val && q_vector->itr_val <= 3) 2222 q_vector->itr_val = IGB_START_ITR; 2223 q_vector->set_itr = 1; 2224 } 2225 2226 return 0; 2227 } 2228 2229 static int igb_get_coalesce(struct net_device *netdev, 2230 struct ethtool_coalesce *ec) 2231 { 2232 struct igb_adapter *adapter = netdev_priv(netdev); 2233 2234 if (adapter->rx_itr_setting <= 3) 2235 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2236 else 2237 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2238 2239 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2240 if (adapter->tx_itr_setting <= 3) 2241 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2242 else 2243 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int igb_nway_reset(struct net_device *netdev) 2250 { 2251 struct igb_adapter *adapter = netdev_priv(netdev); 2252 if (netif_running(netdev)) 2253 igb_reinit_locked(adapter); 2254 return 0; 2255 } 2256 2257 static int igb_get_sset_count(struct net_device *netdev, int sset) 2258 { 2259 switch (sset) { 2260 case ETH_SS_STATS: 2261 return IGB_STATS_LEN; 2262 case ETH_SS_TEST: 2263 return IGB_TEST_LEN; 2264 default: 2265 return -ENOTSUPP; 2266 } 2267 } 2268 2269 static void igb_get_ethtool_stats(struct net_device *netdev, 2270 struct ethtool_stats *stats, u64 *data) 2271 { 2272 struct igb_adapter *adapter = netdev_priv(netdev); 2273 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2274 unsigned int start; 2275 struct igb_ring *ring; 2276 int i, j; 2277 char *p; 2278 2279 spin_lock(&adapter->stats64_lock); 2280 igb_update_stats(adapter, net_stats); 2281 2282 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2283 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2284 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2285 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2286 } 2287 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2288 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2289 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2290 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2291 } 2292 for (j = 0; j < adapter->num_tx_queues; j++) { 2293 u64 restart2; 2294 2295 ring = adapter->tx_ring[j]; 2296 do { 2297 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2298 data[i] = ring->tx_stats.packets; 2299 data[i+1] = ring->tx_stats.bytes; 2300 data[i+2] = ring->tx_stats.restart_queue; 2301 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2302 do { 2303 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2304 restart2 = ring->tx_stats.restart_queue2; 2305 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2306 data[i+2] += restart2; 2307 2308 i += IGB_TX_QUEUE_STATS_LEN; 2309 } 2310 for (j = 0; j < adapter->num_rx_queues; j++) { 2311 ring = adapter->rx_ring[j]; 2312 do { 2313 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2314 data[i] = ring->rx_stats.packets; 2315 data[i+1] = ring->rx_stats.bytes; 2316 data[i+2] = ring->rx_stats.drops; 2317 data[i+3] = ring->rx_stats.csum_err; 2318 data[i+4] = ring->rx_stats.alloc_failed; 2319 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2320 i += IGB_RX_QUEUE_STATS_LEN; 2321 } 2322 spin_unlock(&adapter->stats64_lock); 2323 } 2324 2325 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2326 { 2327 struct igb_adapter *adapter = netdev_priv(netdev); 2328 u8 *p = data; 2329 int i; 2330 2331 switch (stringset) { 2332 case ETH_SS_TEST: 2333 memcpy(data, *igb_gstrings_test, 2334 IGB_TEST_LEN*ETH_GSTRING_LEN); 2335 break; 2336 case ETH_SS_STATS: 2337 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2338 memcpy(p, igb_gstrings_stats[i].stat_string, 2339 ETH_GSTRING_LEN); 2340 p += ETH_GSTRING_LEN; 2341 } 2342 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2343 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2344 ETH_GSTRING_LEN); 2345 p += ETH_GSTRING_LEN; 2346 } 2347 for (i = 0; i < adapter->num_tx_queues; i++) { 2348 sprintf(p, "tx_queue_%u_packets", i); 2349 p += ETH_GSTRING_LEN; 2350 sprintf(p, "tx_queue_%u_bytes", i); 2351 p += ETH_GSTRING_LEN; 2352 sprintf(p, "tx_queue_%u_restart", i); 2353 p += ETH_GSTRING_LEN; 2354 } 2355 for (i = 0; i < adapter->num_rx_queues; i++) { 2356 sprintf(p, "rx_queue_%u_packets", i); 2357 p += ETH_GSTRING_LEN; 2358 sprintf(p, "rx_queue_%u_bytes", i); 2359 p += ETH_GSTRING_LEN; 2360 sprintf(p, "rx_queue_%u_drops", i); 2361 p += ETH_GSTRING_LEN; 2362 sprintf(p, "rx_queue_%u_csum_err", i); 2363 p += ETH_GSTRING_LEN; 2364 sprintf(p, "rx_queue_%u_alloc_failed", i); 2365 p += ETH_GSTRING_LEN; 2366 } 2367 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2368 break; 2369 } 2370 } 2371 2372 static int igb_get_ts_info(struct net_device *dev, 2373 struct ethtool_ts_info *info) 2374 { 2375 struct igb_adapter *adapter = netdev_priv(dev); 2376 2377 if (adapter->ptp_clock) 2378 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2379 else 2380 info->phc_index = -1; 2381 2382 switch (adapter->hw.mac.type) { 2383 case e1000_82575: 2384 info->so_timestamping = 2385 SOF_TIMESTAMPING_TX_SOFTWARE | 2386 SOF_TIMESTAMPING_RX_SOFTWARE | 2387 SOF_TIMESTAMPING_SOFTWARE; 2388 return 0; 2389 case e1000_82576: 2390 case e1000_82580: 2391 case e1000_i350: 2392 case e1000_i354: 2393 case e1000_i210: 2394 case e1000_i211: 2395 info->so_timestamping = 2396 SOF_TIMESTAMPING_TX_SOFTWARE | 2397 SOF_TIMESTAMPING_RX_SOFTWARE | 2398 SOF_TIMESTAMPING_SOFTWARE | 2399 SOF_TIMESTAMPING_TX_HARDWARE | 2400 SOF_TIMESTAMPING_RX_HARDWARE | 2401 SOF_TIMESTAMPING_RAW_HARDWARE; 2402 2403 info->tx_types = 2404 (1 << HWTSTAMP_TX_OFF) | 2405 (1 << HWTSTAMP_TX_ON); 2406 2407 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE; 2408 2409 /* 82576 does not support timestamping all packets. */ 2410 if (adapter->hw.mac.type >= e1000_82580) 2411 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL; 2412 else 2413 info->rx_filters |= 2414 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2415 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2416 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2417 2418 return 0; 2419 default: 2420 return -EOPNOTSUPP; 2421 } 2422 } 2423 2424 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2425 struct ethtool_rxnfc *cmd) 2426 { 2427 cmd->data = 0; 2428 2429 /* Report default options for RSS on igb */ 2430 switch (cmd->flow_type) { 2431 case TCP_V4_FLOW: 2432 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2433 /* Fall through */ 2434 case UDP_V4_FLOW: 2435 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2436 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2437 /* Fall through */ 2438 case SCTP_V4_FLOW: 2439 case AH_ESP_V4_FLOW: 2440 case AH_V4_FLOW: 2441 case ESP_V4_FLOW: 2442 case IPV4_FLOW: 2443 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2444 break; 2445 case TCP_V6_FLOW: 2446 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2447 /* Fall through */ 2448 case UDP_V6_FLOW: 2449 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2450 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2451 /* Fall through */ 2452 case SCTP_V6_FLOW: 2453 case AH_ESP_V6_FLOW: 2454 case AH_V6_FLOW: 2455 case ESP_V6_FLOW: 2456 case IPV6_FLOW: 2457 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2458 break; 2459 default: 2460 return -EINVAL; 2461 } 2462 2463 return 0; 2464 } 2465 2466 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2467 u32 *rule_locs) 2468 { 2469 struct igb_adapter *adapter = netdev_priv(dev); 2470 int ret = -EOPNOTSUPP; 2471 2472 switch (cmd->cmd) { 2473 case ETHTOOL_GRXRINGS: 2474 cmd->data = adapter->num_rx_queues; 2475 ret = 0; 2476 break; 2477 case ETHTOOL_GRXFH: 2478 ret = igb_get_rss_hash_opts(adapter, cmd); 2479 break; 2480 default: 2481 break; 2482 } 2483 2484 return ret; 2485 } 2486 2487 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2488 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2489 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2490 struct ethtool_rxnfc *nfc) 2491 { 2492 u32 flags = adapter->flags; 2493 2494 /* RSS does not support anything other than hashing 2495 * to queues on src and dst IPs and ports 2496 */ 2497 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2498 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2499 return -EINVAL; 2500 2501 switch (nfc->flow_type) { 2502 case TCP_V4_FLOW: 2503 case TCP_V6_FLOW: 2504 if (!(nfc->data & RXH_IP_SRC) || 2505 !(nfc->data & RXH_IP_DST) || 2506 !(nfc->data & RXH_L4_B_0_1) || 2507 !(nfc->data & RXH_L4_B_2_3)) 2508 return -EINVAL; 2509 break; 2510 case UDP_V4_FLOW: 2511 if (!(nfc->data & RXH_IP_SRC) || 2512 !(nfc->data & RXH_IP_DST)) 2513 return -EINVAL; 2514 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2515 case 0: 2516 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2517 break; 2518 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2519 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2520 break; 2521 default: 2522 return -EINVAL; 2523 } 2524 break; 2525 case UDP_V6_FLOW: 2526 if (!(nfc->data & RXH_IP_SRC) || 2527 !(nfc->data & RXH_IP_DST)) 2528 return -EINVAL; 2529 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2530 case 0: 2531 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2532 break; 2533 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2534 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2535 break; 2536 default: 2537 return -EINVAL; 2538 } 2539 break; 2540 case AH_ESP_V4_FLOW: 2541 case AH_V4_FLOW: 2542 case ESP_V4_FLOW: 2543 case SCTP_V4_FLOW: 2544 case AH_ESP_V6_FLOW: 2545 case AH_V6_FLOW: 2546 case ESP_V6_FLOW: 2547 case SCTP_V6_FLOW: 2548 if (!(nfc->data & RXH_IP_SRC) || 2549 !(nfc->data & RXH_IP_DST) || 2550 (nfc->data & RXH_L4_B_0_1) || 2551 (nfc->data & RXH_L4_B_2_3)) 2552 return -EINVAL; 2553 break; 2554 default: 2555 return -EINVAL; 2556 } 2557 2558 /* if we changed something we need to update flags */ 2559 if (flags != adapter->flags) { 2560 struct e1000_hw *hw = &adapter->hw; 2561 u32 mrqc = rd32(E1000_MRQC); 2562 2563 if ((flags & UDP_RSS_FLAGS) && 2564 !(adapter->flags & UDP_RSS_FLAGS)) 2565 dev_err(&adapter->pdev->dev, 2566 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2567 2568 adapter->flags = flags; 2569 2570 /* Perform hash on these packet types */ 2571 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2572 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2573 E1000_MRQC_RSS_FIELD_IPV6 | 2574 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2575 2576 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2577 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2578 2579 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2580 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2581 2582 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2583 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2584 2585 wr32(E1000_MRQC, mrqc); 2586 } 2587 2588 return 0; 2589 } 2590 2591 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2592 { 2593 struct igb_adapter *adapter = netdev_priv(dev); 2594 int ret = -EOPNOTSUPP; 2595 2596 switch (cmd->cmd) { 2597 case ETHTOOL_SRXFH: 2598 ret = igb_set_rss_hash_opt(adapter, cmd); 2599 break; 2600 default: 2601 break; 2602 } 2603 2604 return ret; 2605 } 2606 2607 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 2608 { 2609 struct igb_adapter *adapter = netdev_priv(netdev); 2610 struct e1000_hw *hw = &adapter->hw; 2611 u32 ret_val; 2612 u16 phy_data; 2613 2614 if ((hw->mac.type < e1000_i350) || 2615 (hw->phy.media_type != e1000_media_type_copper)) 2616 return -EOPNOTSUPP; 2617 2618 edata->supported = (SUPPORTED_1000baseT_Full | 2619 SUPPORTED_100baseT_Full); 2620 if (!hw->dev_spec._82575.eee_disable) 2621 edata->advertised = 2622 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 2623 2624 /* The IPCNFG and EEER registers are not supported on I354. */ 2625 if (hw->mac.type == e1000_i354) { 2626 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 2627 } else { 2628 u32 eeer; 2629 2630 eeer = rd32(E1000_EEER); 2631 2632 /* EEE status on negotiated link */ 2633 if (eeer & E1000_EEER_EEE_NEG) 2634 edata->eee_active = true; 2635 2636 if (eeer & E1000_EEER_TX_LPI_EN) 2637 edata->tx_lpi_enabled = true; 2638 } 2639 2640 /* EEE Link Partner Advertised */ 2641 switch (hw->mac.type) { 2642 case e1000_i350: 2643 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 2644 &phy_data); 2645 if (ret_val) 2646 return -ENODATA; 2647 2648 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2649 break; 2650 case e1000_i354: 2651 case e1000_i210: 2652 case e1000_i211: 2653 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 2654 E1000_EEE_LP_ADV_DEV_I210, 2655 &phy_data); 2656 if (ret_val) 2657 return -ENODATA; 2658 2659 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2660 2661 break; 2662 default: 2663 break; 2664 } 2665 2666 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 2667 2668 if ((hw->mac.type == e1000_i354) && 2669 (edata->eee_enabled)) 2670 edata->tx_lpi_enabled = true; 2671 2672 /* Report correct negotiated EEE status for devices that 2673 * wrongly report EEE at half-duplex 2674 */ 2675 if (adapter->link_duplex == HALF_DUPLEX) { 2676 edata->eee_enabled = false; 2677 edata->eee_active = false; 2678 edata->tx_lpi_enabled = false; 2679 edata->advertised &= ~edata->advertised; 2680 } 2681 2682 return 0; 2683 } 2684 2685 static int igb_set_eee(struct net_device *netdev, 2686 struct ethtool_eee *edata) 2687 { 2688 struct igb_adapter *adapter = netdev_priv(netdev); 2689 struct e1000_hw *hw = &adapter->hw; 2690 struct ethtool_eee eee_curr; 2691 bool adv1g_eee = true, adv100m_eee = true; 2692 s32 ret_val; 2693 2694 if ((hw->mac.type < e1000_i350) || 2695 (hw->phy.media_type != e1000_media_type_copper)) 2696 return -EOPNOTSUPP; 2697 2698 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 2699 2700 ret_val = igb_get_eee(netdev, &eee_curr); 2701 if (ret_val) 2702 return ret_val; 2703 2704 if (eee_curr.eee_enabled) { 2705 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 2706 dev_err(&adapter->pdev->dev, 2707 "Setting EEE tx-lpi is not supported\n"); 2708 return -EINVAL; 2709 } 2710 2711 /* Tx LPI timer is not implemented currently */ 2712 if (edata->tx_lpi_timer) { 2713 dev_err(&adapter->pdev->dev, 2714 "Setting EEE Tx LPI timer is not supported\n"); 2715 return -EINVAL; 2716 } 2717 2718 if (!edata->advertised || (edata->advertised & 2719 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 2720 dev_err(&adapter->pdev->dev, 2721 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 2722 return -EINVAL; 2723 } 2724 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 2725 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 2726 2727 } else if (!edata->eee_enabled) { 2728 dev_err(&adapter->pdev->dev, 2729 "Setting EEE options are not supported with EEE disabled\n"); 2730 return -EINVAL; 2731 } 2732 2733 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 2734 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 2735 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 2736 adapter->flags |= IGB_FLAG_EEE; 2737 2738 /* reset link */ 2739 if (netif_running(netdev)) 2740 igb_reinit_locked(adapter); 2741 else 2742 igb_reset(adapter); 2743 } 2744 2745 if (hw->mac.type == e1000_i354) 2746 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 2747 else 2748 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 2749 2750 if (ret_val) { 2751 dev_err(&adapter->pdev->dev, 2752 "Problem setting EEE advertisement options\n"); 2753 return -EINVAL; 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int igb_get_module_info(struct net_device *netdev, 2760 struct ethtool_modinfo *modinfo) 2761 { 2762 struct igb_adapter *adapter = netdev_priv(netdev); 2763 struct e1000_hw *hw = &adapter->hw; 2764 u32 status = 0; 2765 u16 sff8472_rev, addr_mode; 2766 bool page_swap = false; 2767 2768 if ((hw->phy.media_type == e1000_media_type_copper) || 2769 (hw->phy.media_type == e1000_media_type_unknown)) 2770 return -EOPNOTSUPP; 2771 2772 /* Check whether we support SFF-8472 or not */ 2773 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 2774 if (status) 2775 return -EIO; 2776 2777 /* addressing mode is not supported */ 2778 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 2779 if (status) 2780 return -EIO; 2781 2782 /* addressing mode is not supported */ 2783 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 2784 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 2785 page_swap = true; 2786 } 2787 2788 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 2789 /* We have an SFP, but it does not support SFF-8472 */ 2790 modinfo->type = ETH_MODULE_SFF_8079; 2791 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 2792 } else { 2793 /* We have an SFP which supports a revision of SFF-8472 */ 2794 modinfo->type = ETH_MODULE_SFF_8472; 2795 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2796 } 2797 2798 return 0; 2799 } 2800 2801 static int igb_get_module_eeprom(struct net_device *netdev, 2802 struct ethtool_eeprom *ee, u8 *data) 2803 { 2804 struct igb_adapter *adapter = netdev_priv(netdev); 2805 struct e1000_hw *hw = &adapter->hw; 2806 u32 status = 0; 2807 u16 *dataword; 2808 u16 first_word, last_word; 2809 int i = 0; 2810 2811 if (ee->len == 0) 2812 return -EINVAL; 2813 2814 first_word = ee->offset >> 1; 2815 last_word = (ee->offset + ee->len - 1) >> 1; 2816 2817 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1), 2818 GFP_KERNEL); 2819 if (!dataword) 2820 return -ENOMEM; 2821 2822 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 2823 for (i = 0; i < last_word - first_word + 1; i++) { 2824 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]); 2825 if (status) { 2826 /* Error occurred while reading module */ 2827 kfree(dataword); 2828 return -EIO; 2829 } 2830 2831 be16_to_cpus(&dataword[i]); 2832 } 2833 2834 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 2835 kfree(dataword); 2836 2837 return 0; 2838 } 2839 2840 static int igb_ethtool_begin(struct net_device *netdev) 2841 { 2842 struct igb_adapter *adapter = netdev_priv(netdev); 2843 pm_runtime_get_sync(&adapter->pdev->dev); 2844 return 0; 2845 } 2846 2847 static void igb_ethtool_complete(struct net_device *netdev) 2848 { 2849 struct igb_adapter *adapter = netdev_priv(netdev); 2850 pm_runtime_put(&adapter->pdev->dev); 2851 } 2852 2853 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 2854 { 2855 return IGB_RETA_SIZE; 2856 } 2857 2858 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2859 u8 *hfunc) 2860 { 2861 struct igb_adapter *adapter = netdev_priv(netdev); 2862 int i; 2863 2864 if (hfunc) 2865 *hfunc = ETH_RSS_HASH_TOP; 2866 if (!indir) 2867 return 0; 2868 for (i = 0; i < IGB_RETA_SIZE; i++) 2869 indir[i] = adapter->rss_indir_tbl[i]; 2870 2871 return 0; 2872 } 2873 2874 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 2875 { 2876 struct e1000_hw *hw = &adapter->hw; 2877 u32 reg = E1000_RETA(0); 2878 u32 shift = 0; 2879 int i = 0; 2880 2881 switch (hw->mac.type) { 2882 case e1000_82575: 2883 shift = 6; 2884 break; 2885 case e1000_82576: 2886 /* 82576 supports 2 RSS queues for SR-IOV */ 2887 if (adapter->vfs_allocated_count) 2888 shift = 3; 2889 break; 2890 default: 2891 break; 2892 } 2893 2894 while (i < IGB_RETA_SIZE) { 2895 u32 val = 0; 2896 int j; 2897 2898 for (j = 3; j >= 0; j--) { 2899 val <<= 8; 2900 val |= adapter->rss_indir_tbl[i + j]; 2901 } 2902 2903 wr32(reg, val << shift); 2904 reg += 4; 2905 i += 4; 2906 } 2907 } 2908 2909 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 2910 const u8 *key, const u8 hfunc) 2911 { 2912 struct igb_adapter *adapter = netdev_priv(netdev); 2913 struct e1000_hw *hw = &adapter->hw; 2914 int i; 2915 u32 num_queues; 2916 2917 /* We do not allow change in unsupported parameters */ 2918 if (key || 2919 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 2920 return -EOPNOTSUPP; 2921 if (!indir) 2922 return 0; 2923 2924 num_queues = adapter->rss_queues; 2925 2926 switch (hw->mac.type) { 2927 case e1000_82576: 2928 /* 82576 supports 2 RSS queues for SR-IOV */ 2929 if (adapter->vfs_allocated_count) 2930 num_queues = 2; 2931 break; 2932 default: 2933 break; 2934 } 2935 2936 /* Verify user input. */ 2937 for (i = 0; i < IGB_RETA_SIZE; i++) 2938 if (indir[i] >= num_queues) 2939 return -EINVAL; 2940 2941 2942 for (i = 0; i < IGB_RETA_SIZE; i++) 2943 adapter->rss_indir_tbl[i] = indir[i]; 2944 2945 igb_write_rss_indir_tbl(adapter); 2946 2947 return 0; 2948 } 2949 2950 static unsigned int igb_max_channels(struct igb_adapter *adapter) 2951 { 2952 struct e1000_hw *hw = &adapter->hw; 2953 unsigned int max_combined = 0; 2954 2955 switch (hw->mac.type) { 2956 case e1000_i211: 2957 max_combined = IGB_MAX_RX_QUEUES_I211; 2958 break; 2959 case e1000_82575: 2960 case e1000_i210: 2961 max_combined = IGB_MAX_RX_QUEUES_82575; 2962 break; 2963 case e1000_i350: 2964 if (!!adapter->vfs_allocated_count) { 2965 max_combined = 1; 2966 break; 2967 } 2968 /* fall through */ 2969 case e1000_82576: 2970 if (!!adapter->vfs_allocated_count) { 2971 max_combined = 2; 2972 break; 2973 } 2974 /* fall through */ 2975 case e1000_82580: 2976 case e1000_i354: 2977 default: 2978 max_combined = IGB_MAX_RX_QUEUES; 2979 break; 2980 } 2981 2982 return max_combined; 2983 } 2984 2985 static void igb_get_channels(struct net_device *netdev, 2986 struct ethtool_channels *ch) 2987 { 2988 struct igb_adapter *adapter = netdev_priv(netdev); 2989 2990 /* Report maximum channels */ 2991 ch->max_combined = igb_max_channels(adapter); 2992 2993 /* Report info for other vector */ 2994 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 2995 ch->max_other = NON_Q_VECTORS; 2996 ch->other_count = NON_Q_VECTORS; 2997 } 2998 2999 ch->combined_count = adapter->rss_queues; 3000 } 3001 3002 static int igb_set_channels(struct net_device *netdev, 3003 struct ethtool_channels *ch) 3004 { 3005 struct igb_adapter *adapter = netdev_priv(netdev); 3006 unsigned int count = ch->combined_count; 3007 unsigned int max_combined = 0; 3008 3009 /* Verify they are not requesting separate vectors */ 3010 if (!count || ch->rx_count || ch->tx_count) 3011 return -EINVAL; 3012 3013 /* Verify other_count is valid and has not been changed */ 3014 if (ch->other_count != NON_Q_VECTORS) 3015 return -EINVAL; 3016 3017 /* Verify the number of channels doesn't exceed hw limits */ 3018 max_combined = igb_max_channels(adapter); 3019 if (count > max_combined) 3020 return -EINVAL; 3021 3022 if (count != adapter->rss_queues) { 3023 adapter->rss_queues = count; 3024 igb_set_flag_queue_pairs(adapter, max_combined); 3025 3026 /* Hardware has to reinitialize queues and interrupts to 3027 * match the new configuration. 3028 */ 3029 return igb_reinit_queues(adapter); 3030 } 3031 3032 return 0; 3033 } 3034 3035 static const struct ethtool_ops igb_ethtool_ops = { 3036 .get_settings = igb_get_settings, 3037 .set_settings = igb_set_settings, 3038 .get_drvinfo = igb_get_drvinfo, 3039 .get_regs_len = igb_get_regs_len, 3040 .get_regs = igb_get_regs, 3041 .get_wol = igb_get_wol, 3042 .set_wol = igb_set_wol, 3043 .get_msglevel = igb_get_msglevel, 3044 .set_msglevel = igb_set_msglevel, 3045 .nway_reset = igb_nway_reset, 3046 .get_link = igb_get_link, 3047 .get_eeprom_len = igb_get_eeprom_len, 3048 .get_eeprom = igb_get_eeprom, 3049 .set_eeprom = igb_set_eeprom, 3050 .get_ringparam = igb_get_ringparam, 3051 .set_ringparam = igb_set_ringparam, 3052 .get_pauseparam = igb_get_pauseparam, 3053 .set_pauseparam = igb_set_pauseparam, 3054 .self_test = igb_diag_test, 3055 .get_strings = igb_get_strings, 3056 .set_phys_id = igb_set_phys_id, 3057 .get_sset_count = igb_get_sset_count, 3058 .get_ethtool_stats = igb_get_ethtool_stats, 3059 .get_coalesce = igb_get_coalesce, 3060 .set_coalesce = igb_set_coalesce, 3061 .get_ts_info = igb_get_ts_info, 3062 .get_rxnfc = igb_get_rxnfc, 3063 .set_rxnfc = igb_set_rxnfc, 3064 .get_eee = igb_get_eee, 3065 .set_eee = igb_set_eee, 3066 .get_module_info = igb_get_module_info, 3067 .get_module_eeprom = igb_get_module_eeprom, 3068 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3069 .get_rxfh = igb_get_rxfh, 3070 .set_rxfh = igb_set_rxfh, 3071 .get_channels = igb_get_channels, 3072 .set_channels = igb_set_channels, 3073 .begin = igb_ethtool_begin, 3074 .complete = igb_ethtool_complete, 3075 }; 3076 3077 void igb_set_ethtool_ops(struct net_device *netdev) 3078 { 3079 netdev->ethtool_ops = &igb_ethtool_ops; 3080 } 3081