1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* ethtool support for igb */ 5 6 #include <linux/vmalloc.h> 7 #include <linux/netdevice.h> 8 #include <linux/pci.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/if_ether.h> 12 #include <linux/ethtool.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/highmem.h> 17 #include <linux/mdio.h> 18 19 #include "igb.h" 20 21 struct igb_stats { 22 char stat_string[ETH_GSTRING_LEN]; 23 int sizeof_stat; 24 int stat_offset; 25 }; 26 27 #define IGB_STAT(_name, _stat) { \ 28 .stat_string = _name, \ 29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \ 30 .stat_offset = offsetof(struct igb_adapter, _stat) \ 31 } 32 static const struct igb_stats igb_gstrings_stats[] = { 33 IGB_STAT("rx_packets", stats.gprc), 34 IGB_STAT("tx_packets", stats.gptc), 35 IGB_STAT("rx_bytes", stats.gorc), 36 IGB_STAT("tx_bytes", stats.gotc), 37 IGB_STAT("rx_broadcast", stats.bprc), 38 IGB_STAT("tx_broadcast", stats.bptc), 39 IGB_STAT("rx_multicast", stats.mprc), 40 IGB_STAT("tx_multicast", stats.mptc), 41 IGB_STAT("multicast", stats.mprc), 42 IGB_STAT("collisions", stats.colc), 43 IGB_STAT("rx_crc_errors", stats.crcerrs), 44 IGB_STAT("rx_no_buffer_count", stats.rnbc), 45 IGB_STAT("rx_missed_errors", stats.mpc), 46 IGB_STAT("tx_aborted_errors", stats.ecol), 47 IGB_STAT("tx_carrier_errors", stats.tncrs), 48 IGB_STAT("tx_window_errors", stats.latecol), 49 IGB_STAT("tx_abort_late_coll", stats.latecol), 50 IGB_STAT("tx_deferred_ok", stats.dc), 51 IGB_STAT("tx_single_coll_ok", stats.scc), 52 IGB_STAT("tx_multi_coll_ok", stats.mcc), 53 IGB_STAT("tx_timeout_count", tx_timeout_count), 54 IGB_STAT("rx_long_length_errors", stats.roc), 55 IGB_STAT("rx_short_length_errors", stats.ruc), 56 IGB_STAT("rx_align_errors", stats.algnerrc), 57 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 59 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 61 IGB_STAT("tx_flow_control_xon", stats.xontxc), 62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 63 IGB_STAT("rx_long_byte_count", stats.gorc), 64 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 65 IGB_STAT("tx_smbus", stats.mgptc), 66 IGB_STAT("rx_smbus", stats.mgprc), 67 IGB_STAT("dropped_smbus", stats.mgpdc), 68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped), 74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 75 }; 76 77 #define IGB_NETDEV_STAT(_net_stat) { \ 78 .stat_string = __stringify(_net_stat), \ 79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \ 80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 81 } 82 static const struct igb_stats igb_gstrings_net_stats[] = { 83 IGB_NETDEV_STAT(rx_errors), 84 IGB_NETDEV_STAT(tx_errors), 85 IGB_NETDEV_STAT(tx_dropped), 86 IGB_NETDEV_STAT(rx_length_errors), 87 IGB_NETDEV_STAT(rx_over_errors), 88 IGB_NETDEV_STAT(rx_frame_errors), 89 IGB_NETDEV_STAT(rx_fifo_errors), 90 IGB_NETDEV_STAT(tx_fifo_errors), 91 IGB_NETDEV_STAT(tx_heartbeat_errors) 92 }; 93 94 #define IGB_GLOBAL_STATS_LEN \ 95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 96 #define IGB_NETDEV_STATS_LEN \ 97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 98 #define IGB_RX_QUEUE_STATS_LEN \ 99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 100 101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 102 103 #define IGB_QUEUE_STATS_LEN \ 104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 105 IGB_RX_QUEUE_STATS_LEN) + \ 106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 107 IGB_TX_QUEUE_STATS_LEN)) 108 #define IGB_STATS_LEN \ 109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 110 111 enum igb_diagnostics_results { 112 TEST_REG = 0, 113 TEST_EEP, 114 TEST_IRQ, 115 TEST_LOOP, 116 TEST_LINK 117 }; 118 119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 120 [TEST_REG] = "Register test (offline)", 121 [TEST_EEP] = "Eeprom test (offline)", 122 [TEST_IRQ] = "Interrupt test (offline)", 123 [TEST_LOOP] = "Loopback test (offline)", 124 [TEST_LINK] = "Link test (on/offline)" 125 }; 126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 127 128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = { 129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) 130 "legacy-rx", 131 }; 132 133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings) 134 135 static int igb_get_link_ksettings(struct net_device *netdev, 136 struct ethtool_link_ksettings *cmd) 137 { 138 struct igb_adapter *adapter = netdev_priv(netdev); 139 struct e1000_hw *hw = &adapter->hw; 140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 142 u32 status; 143 u32 speed; 144 u32 supported, advertising; 145 146 status = pm_runtime_suspended(&adapter->pdev->dev) ? 147 0 : rd32(E1000_STATUS); 148 if (hw->phy.media_type == e1000_media_type_copper) { 149 150 supported = (SUPPORTED_10baseT_Half | 151 SUPPORTED_10baseT_Full | 152 SUPPORTED_100baseT_Half | 153 SUPPORTED_100baseT_Full | 154 SUPPORTED_1000baseT_Full| 155 SUPPORTED_Autoneg | 156 SUPPORTED_TP | 157 SUPPORTED_Pause); 158 advertising = ADVERTISED_TP; 159 160 if (hw->mac.autoneg == 1) { 161 advertising |= ADVERTISED_Autoneg; 162 /* the e1000 autoneg seems to match ethtool nicely */ 163 advertising |= hw->phy.autoneg_advertised; 164 } 165 166 cmd->base.port = PORT_TP; 167 cmd->base.phy_address = hw->phy.addr; 168 } else { 169 supported = (SUPPORTED_FIBRE | 170 SUPPORTED_1000baseKX_Full | 171 SUPPORTED_Autoneg | 172 SUPPORTED_Pause); 173 advertising = (ADVERTISED_FIBRE | 174 ADVERTISED_1000baseKX_Full); 175 if (hw->mac.type == e1000_i354) { 176 if ((hw->device_id == 177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 178 !(status & E1000_STATUS_2P5_SKU_OVER)) { 179 supported |= SUPPORTED_2500baseX_Full; 180 supported &= ~SUPPORTED_1000baseKX_Full; 181 advertising |= ADVERTISED_2500baseX_Full; 182 advertising &= ~ADVERTISED_1000baseKX_Full; 183 } 184 } 185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { 186 supported |= SUPPORTED_100baseT_Full; 187 advertising |= ADVERTISED_100baseT_Full; 188 } 189 if (hw->mac.autoneg == 1) 190 advertising |= ADVERTISED_Autoneg; 191 192 cmd->base.port = PORT_FIBRE; 193 } 194 if (hw->mac.autoneg != 1) 195 advertising &= ~(ADVERTISED_Pause | 196 ADVERTISED_Asym_Pause); 197 198 switch (hw->fc.requested_mode) { 199 case e1000_fc_full: 200 advertising |= ADVERTISED_Pause; 201 break; 202 case e1000_fc_rx_pause: 203 advertising |= (ADVERTISED_Pause | 204 ADVERTISED_Asym_Pause); 205 break; 206 case e1000_fc_tx_pause: 207 advertising |= ADVERTISED_Asym_Pause; 208 break; 209 default: 210 advertising &= ~(ADVERTISED_Pause | 211 ADVERTISED_Asym_Pause); 212 } 213 if (status & E1000_STATUS_LU) { 214 if ((status & E1000_STATUS_2P5_SKU) && 215 !(status & E1000_STATUS_2P5_SKU_OVER)) { 216 speed = SPEED_2500; 217 } else if (status & E1000_STATUS_SPEED_1000) { 218 speed = SPEED_1000; 219 } else if (status & E1000_STATUS_SPEED_100) { 220 speed = SPEED_100; 221 } else { 222 speed = SPEED_10; 223 } 224 if ((status & E1000_STATUS_FD) || 225 hw->phy.media_type != e1000_media_type_copper) 226 cmd->base.duplex = DUPLEX_FULL; 227 else 228 cmd->base.duplex = DUPLEX_HALF; 229 } else { 230 speed = SPEED_UNKNOWN; 231 cmd->base.duplex = DUPLEX_UNKNOWN; 232 } 233 cmd->base.speed = speed; 234 if ((hw->phy.media_type == e1000_media_type_fiber) || 235 hw->mac.autoneg) 236 cmd->base.autoneg = AUTONEG_ENABLE; 237 else 238 cmd->base.autoneg = AUTONEG_DISABLE; 239 240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 241 if (hw->phy.media_type == e1000_media_type_copper) 242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 243 ETH_TP_MDI; 244 else 245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 246 247 if (hw->phy.mdix == AUTO_ALL_MODES) 248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 249 else 250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; 251 252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 253 supported); 254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 255 advertising); 256 257 return 0; 258 } 259 260 static int igb_set_link_ksettings(struct net_device *netdev, 261 const struct ethtool_link_ksettings *cmd) 262 { 263 struct igb_adapter *adapter = netdev_priv(netdev); 264 struct e1000_hw *hw = &adapter->hw; 265 u32 advertising; 266 267 /* When SoL/IDER sessions are active, autoneg/speed/duplex 268 * cannot be changed 269 */ 270 if (igb_check_reset_block(hw)) { 271 dev_err(&adapter->pdev->dev, 272 "Cannot change link characteristics when SoL/IDER is active.\n"); 273 return -EINVAL; 274 } 275 276 /* MDI setting is only allowed when autoneg enabled because 277 * some hardware doesn't allow MDI setting when speed or 278 * duplex is forced. 279 */ 280 if (cmd->base.eth_tp_mdix_ctrl) { 281 if (hw->phy.media_type != e1000_media_type_copper) 282 return -EOPNOTSUPP; 283 284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 285 (cmd->base.autoneg != AUTONEG_ENABLE)) { 286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 287 return -EINVAL; 288 } 289 } 290 291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 292 usleep_range(1000, 2000); 293 294 ethtool_convert_link_mode_to_legacy_u32(&advertising, 295 cmd->link_modes.advertising); 296 297 if (cmd->base.autoneg == AUTONEG_ENABLE) { 298 hw->mac.autoneg = 1; 299 if (hw->phy.media_type == e1000_media_type_fiber) { 300 hw->phy.autoneg_advertised = advertising | 301 ADVERTISED_FIBRE | 302 ADVERTISED_Autoneg; 303 switch (adapter->link_speed) { 304 case SPEED_2500: 305 hw->phy.autoneg_advertised = 306 ADVERTISED_2500baseX_Full; 307 break; 308 case SPEED_1000: 309 hw->phy.autoneg_advertised = 310 ADVERTISED_1000baseT_Full; 311 break; 312 case SPEED_100: 313 hw->phy.autoneg_advertised = 314 ADVERTISED_100baseT_Full; 315 break; 316 default: 317 break; 318 } 319 } else { 320 hw->phy.autoneg_advertised = advertising | 321 ADVERTISED_TP | 322 ADVERTISED_Autoneg; 323 } 324 advertising = hw->phy.autoneg_advertised; 325 if (adapter->fc_autoneg) 326 hw->fc.requested_mode = e1000_fc_default; 327 } else { 328 u32 speed = cmd->base.speed; 329 /* calling this overrides forced MDI setting */ 330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { 331 clear_bit(__IGB_RESETTING, &adapter->state); 332 return -EINVAL; 333 } 334 } 335 336 /* MDI-X => 2; MDI => 1; Auto => 3 */ 337 if (cmd->base.eth_tp_mdix_ctrl) { 338 /* fix up the value for auto (3 => 0) as zero is mapped 339 * internally to auto 340 */ 341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 342 hw->phy.mdix = AUTO_ALL_MODES; 343 else 344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; 345 } 346 347 /* reset the link */ 348 if (netif_running(adapter->netdev)) { 349 igb_down(adapter); 350 igb_up(adapter); 351 } else 352 igb_reset(adapter); 353 354 clear_bit(__IGB_RESETTING, &adapter->state); 355 return 0; 356 } 357 358 static u32 igb_get_link(struct net_device *netdev) 359 { 360 struct igb_adapter *adapter = netdev_priv(netdev); 361 struct e1000_mac_info *mac = &adapter->hw.mac; 362 363 /* If the link is not reported up to netdev, interrupts are disabled, 364 * and so the physical link state may have changed since we last 365 * looked. Set get_link_status to make sure that the true link 366 * state is interrogated, rather than pulling a cached and possibly 367 * stale link state from the driver. 368 */ 369 if (!netif_carrier_ok(netdev)) 370 mac->get_link_status = 1; 371 372 return igb_has_link(adapter); 373 } 374 375 static void igb_get_pauseparam(struct net_device *netdev, 376 struct ethtool_pauseparam *pause) 377 { 378 struct igb_adapter *adapter = netdev_priv(netdev); 379 struct e1000_hw *hw = &adapter->hw; 380 381 pause->autoneg = 382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 383 384 if (hw->fc.current_mode == e1000_fc_rx_pause) 385 pause->rx_pause = 1; 386 else if (hw->fc.current_mode == e1000_fc_tx_pause) 387 pause->tx_pause = 1; 388 else if (hw->fc.current_mode == e1000_fc_full) { 389 pause->rx_pause = 1; 390 pause->tx_pause = 1; 391 } 392 } 393 394 static int igb_set_pauseparam(struct net_device *netdev, 395 struct ethtool_pauseparam *pause) 396 { 397 struct igb_adapter *adapter = netdev_priv(netdev); 398 struct e1000_hw *hw = &adapter->hw; 399 int retval = 0; 400 int i; 401 402 /* 100basefx does not support setting link flow control */ 403 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 404 return -EINVAL; 405 406 adapter->fc_autoneg = pause->autoneg; 407 408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 409 usleep_range(1000, 2000); 410 411 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 412 hw->fc.requested_mode = e1000_fc_default; 413 if (netif_running(adapter->netdev)) { 414 igb_down(adapter); 415 igb_up(adapter); 416 } else { 417 igb_reset(adapter); 418 } 419 } else { 420 if (pause->rx_pause && pause->tx_pause) 421 hw->fc.requested_mode = e1000_fc_full; 422 else if (pause->rx_pause && !pause->tx_pause) 423 hw->fc.requested_mode = e1000_fc_rx_pause; 424 else if (!pause->rx_pause && pause->tx_pause) 425 hw->fc.requested_mode = e1000_fc_tx_pause; 426 else if (!pause->rx_pause && !pause->tx_pause) 427 hw->fc.requested_mode = e1000_fc_none; 428 429 hw->fc.current_mode = hw->fc.requested_mode; 430 431 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 432 igb_force_mac_fc(hw) : igb_setup_link(hw)); 433 434 /* Make sure SRRCTL considers new fc settings for each ring */ 435 for (i = 0; i < adapter->num_rx_queues; i++) { 436 struct igb_ring *ring = adapter->rx_ring[i]; 437 438 igb_setup_srrctl(adapter, ring); 439 } 440 } 441 442 clear_bit(__IGB_RESETTING, &adapter->state); 443 return retval; 444 } 445 446 static u32 igb_get_msglevel(struct net_device *netdev) 447 { 448 struct igb_adapter *adapter = netdev_priv(netdev); 449 return adapter->msg_enable; 450 } 451 452 static void igb_set_msglevel(struct net_device *netdev, u32 data) 453 { 454 struct igb_adapter *adapter = netdev_priv(netdev); 455 adapter->msg_enable = data; 456 } 457 458 static int igb_get_regs_len(struct net_device *netdev) 459 { 460 #define IGB_REGS_LEN 740 461 return IGB_REGS_LEN * sizeof(u32); 462 } 463 464 static void igb_get_regs(struct net_device *netdev, 465 struct ethtool_regs *regs, void *p) 466 { 467 struct igb_adapter *adapter = netdev_priv(netdev); 468 struct e1000_hw *hw = &adapter->hw; 469 u32 *regs_buff = p; 470 u8 i; 471 472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 473 474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 475 476 /* General Registers */ 477 regs_buff[0] = rd32(E1000_CTRL); 478 regs_buff[1] = rd32(E1000_STATUS); 479 regs_buff[2] = rd32(E1000_CTRL_EXT); 480 regs_buff[3] = rd32(E1000_MDIC); 481 regs_buff[4] = rd32(E1000_SCTL); 482 regs_buff[5] = rd32(E1000_CONNSW); 483 regs_buff[6] = rd32(E1000_VET); 484 regs_buff[7] = rd32(E1000_LEDCTL); 485 regs_buff[8] = rd32(E1000_PBA); 486 regs_buff[9] = rd32(E1000_PBS); 487 regs_buff[10] = rd32(E1000_FRTIMER); 488 regs_buff[11] = rd32(E1000_TCPTIMER); 489 490 /* NVM Register */ 491 regs_buff[12] = rd32(E1000_EECD); 492 493 /* Interrupt */ 494 /* Reading EICS for EICR because they read the 495 * same but EICS does not clear on read 496 */ 497 regs_buff[13] = rd32(E1000_EICS); 498 regs_buff[14] = rd32(E1000_EICS); 499 regs_buff[15] = rd32(E1000_EIMS); 500 regs_buff[16] = rd32(E1000_EIMC); 501 regs_buff[17] = rd32(E1000_EIAC); 502 regs_buff[18] = rd32(E1000_EIAM); 503 /* Reading ICS for ICR because they read the 504 * same but ICS does not clear on read 505 */ 506 regs_buff[19] = rd32(E1000_ICS); 507 regs_buff[20] = rd32(E1000_ICS); 508 regs_buff[21] = rd32(E1000_IMS); 509 regs_buff[22] = rd32(E1000_IMC); 510 regs_buff[23] = rd32(E1000_IAC); 511 regs_buff[24] = rd32(E1000_IAM); 512 regs_buff[25] = rd32(E1000_IMIRVP); 513 514 /* Flow Control */ 515 regs_buff[26] = rd32(E1000_FCAL); 516 regs_buff[27] = rd32(E1000_FCAH); 517 regs_buff[28] = rd32(E1000_FCTTV); 518 regs_buff[29] = rd32(E1000_FCRTL); 519 regs_buff[30] = rd32(E1000_FCRTH); 520 regs_buff[31] = rd32(E1000_FCRTV); 521 522 /* Receive */ 523 regs_buff[32] = rd32(E1000_RCTL); 524 regs_buff[33] = rd32(E1000_RXCSUM); 525 regs_buff[34] = rd32(E1000_RLPML); 526 regs_buff[35] = rd32(E1000_RFCTL); 527 regs_buff[36] = rd32(E1000_MRQC); 528 regs_buff[37] = rd32(E1000_VT_CTL); 529 530 /* Transmit */ 531 regs_buff[38] = rd32(E1000_TCTL); 532 regs_buff[39] = rd32(E1000_TCTL_EXT); 533 regs_buff[40] = rd32(E1000_TIPG); 534 regs_buff[41] = rd32(E1000_DTXCTL); 535 536 /* Wake Up */ 537 regs_buff[42] = rd32(E1000_WUC); 538 regs_buff[43] = rd32(E1000_WUFC); 539 regs_buff[44] = rd32(E1000_WUS); 540 regs_buff[45] = rd32(E1000_IPAV); 541 regs_buff[46] = rd32(E1000_WUPL); 542 543 /* MAC */ 544 regs_buff[47] = rd32(E1000_PCS_CFG0); 545 regs_buff[48] = rd32(E1000_PCS_LCTL); 546 regs_buff[49] = rd32(E1000_PCS_LSTAT); 547 regs_buff[50] = rd32(E1000_PCS_ANADV); 548 regs_buff[51] = rd32(E1000_PCS_LPAB); 549 regs_buff[52] = rd32(E1000_PCS_NPTX); 550 regs_buff[53] = rd32(E1000_PCS_LPABNP); 551 552 /* Statistics */ 553 regs_buff[54] = adapter->stats.crcerrs; 554 regs_buff[55] = adapter->stats.algnerrc; 555 regs_buff[56] = adapter->stats.symerrs; 556 regs_buff[57] = adapter->stats.rxerrc; 557 regs_buff[58] = adapter->stats.mpc; 558 regs_buff[59] = adapter->stats.scc; 559 regs_buff[60] = adapter->stats.ecol; 560 regs_buff[61] = adapter->stats.mcc; 561 regs_buff[62] = adapter->stats.latecol; 562 regs_buff[63] = adapter->stats.colc; 563 regs_buff[64] = adapter->stats.dc; 564 regs_buff[65] = adapter->stats.tncrs; 565 regs_buff[66] = adapter->stats.sec; 566 regs_buff[67] = adapter->stats.htdpmc; 567 regs_buff[68] = adapter->stats.rlec; 568 regs_buff[69] = adapter->stats.xonrxc; 569 regs_buff[70] = adapter->stats.xontxc; 570 regs_buff[71] = adapter->stats.xoffrxc; 571 regs_buff[72] = adapter->stats.xofftxc; 572 regs_buff[73] = adapter->stats.fcruc; 573 regs_buff[74] = adapter->stats.prc64; 574 regs_buff[75] = adapter->stats.prc127; 575 regs_buff[76] = adapter->stats.prc255; 576 regs_buff[77] = adapter->stats.prc511; 577 regs_buff[78] = adapter->stats.prc1023; 578 regs_buff[79] = adapter->stats.prc1522; 579 regs_buff[80] = adapter->stats.gprc; 580 regs_buff[81] = adapter->stats.bprc; 581 regs_buff[82] = adapter->stats.mprc; 582 regs_buff[83] = adapter->stats.gptc; 583 regs_buff[84] = adapter->stats.gorc; 584 regs_buff[86] = adapter->stats.gotc; 585 regs_buff[88] = adapter->stats.rnbc; 586 regs_buff[89] = adapter->stats.ruc; 587 regs_buff[90] = adapter->stats.rfc; 588 regs_buff[91] = adapter->stats.roc; 589 regs_buff[92] = adapter->stats.rjc; 590 regs_buff[93] = adapter->stats.mgprc; 591 regs_buff[94] = adapter->stats.mgpdc; 592 regs_buff[95] = adapter->stats.mgptc; 593 regs_buff[96] = adapter->stats.tor; 594 regs_buff[98] = adapter->stats.tot; 595 regs_buff[100] = adapter->stats.tpr; 596 regs_buff[101] = adapter->stats.tpt; 597 regs_buff[102] = adapter->stats.ptc64; 598 regs_buff[103] = adapter->stats.ptc127; 599 regs_buff[104] = adapter->stats.ptc255; 600 regs_buff[105] = adapter->stats.ptc511; 601 regs_buff[106] = adapter->stats.ptc1023; 602 regs_buff[107] = adapter->stats.ptc1522; 603 regs_buff[108] = adapter->stats.mptc; 604 regs_buff[109] = adapter->stats.bptc; 605 regs_buff[110] = adapter->stats.tsctc; 606 regs_buff[111] = adapter->stats.iac; 607 regs_buff[112] = adapter->stats.rpthc; 608 regs_buff[113] = adapter->stats.hgptc; 609 regs_buff[114] = adapter->stats.hgorc; 610 regs_buff[116] = adapter->stats.hgotc; 611 regs_buff[118] = adapter->stats.lenerrs; 612 regs_buff[119] = adapter->stats.scvpc; 613 regs_buff[120] = adapter->stats.hrmpc; 614 615 for (i = 0; i < 4; i++) 616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 617 for (i = 0; i < 4; i++) 618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 619 for (i = 0; i < 4; i++) 620 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 621 for (i = 0; i < 4; i++) 622 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 623 for (i = 0; i < 4; i++) 624 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 625 for (i = 0; i < 4; i++) 626 regs_buff[141 + i] = rd32(E1000_RDH(i)); 627 for (i = 0; i < 4; i++) 628 regs_buff[145 + i] = rd32(E1000_RDT(i)); 629 for (i = 0; i < 4; i++) 630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 631 632 for (i = 0; i < 10; i++) 633 regs_buff[153 + i] = rd32(E1000_EITR(i)); 634 for (i = 0; i < 8; i++) 635 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 636 for (i = 0; i < 8; i++) 637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 638 for (i = 0; i < 16; i++) 639 regs_buff[179 + i] = rd32(E1000_RAL(i)); 640 for (i = 0; i < 16; i++) 641 regs_buff[195 + i] = rd32(E1000_RAH(i)); 642 643 for (i = 0; i < 4; i++) 644 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 645 for (i = 0; i < 4; i++) 646 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 647 for (i = 0; i < 4; i++) 648 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 649 for (i = 0; i < 4; i++) 650 regs_buff[223 + i] = rd32(E1000_TDH(i)); 651 for (i = 0; i < 4; i++) 652 regs_buff[227 + i] = rd32(E1000_TDT(i)); 653 for (i = 0; i < 4; i++) 654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 655 for (i = 0; i < 4; i++) 656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 657 for (i = 0; i < 4; i++) 658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 659 for (i = 0; i < 4; i++) 660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 661 662 for (i = 0; i < 4; i++) 663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 664 for (i = 0; i < 4; i++) 665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 666 for (i = 0; i < 32; i++) 667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 668 for (i = 0; i < 128; i++) 669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 670 for (i = 0; i < 128; i++) 671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 672 for (i = 0; i < 4; i++) 673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 674 675 regs_buff[547] = rd32(E1000_TDFH); 676 regs_buff[548] = rd32(E1000_TDFT); 677 regs_buff[549] = rd32(E1000_TDFHS); 678 regs_buff[550] = rd32(E1000_TDFPC); 679 680 if (hw->mac.type > e1000_82580) { 681 regs_buff[551] = adapter->stats.o2bgptc; 682 regs_buff[552] = adapter->stats.b2ospc; 683 regs_buff[553] = adapter->stats.o2bspc; 684 regs_buff[554] = adapter->stats.b2ogprc; 685 } 686 687 if (hw->mac.type == e1000_82576) { 688 for (i = 0; i < 12; i++) 689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 690 for (i = 0; i < 4; i++) 691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 692 for (i = 0; i < 12; i++) 693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 694 for (i = 0; i < 12; i++) 695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 696 for (i = 0; i < 12; i++) 697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 698 for (i = 0; i < 12; i++) 699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 700 for (i = 0; i < 12; i++) 701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 702 for (i = 0; i < 12; i++) 703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 704 705 for (i = 0; i < 12; i++) 706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 713 for (i = 0; i < 12; i++) 714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 715 for (i = 0; i < 12; i++) 716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 717 for (i = 0; i < 12; i++) 718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 719 for (i = 0; i < 12; i++) 720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 721 } 722 723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) 724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY); 725 } 726 727 static int igb_get_eeprom_len(struct net_device *netdev) 728 { 729 struct igb_adapter *adapter = netdev_priv(netdev); 730 return adapter->hw.nvm.word_size * 2; 731 } 732 733 static int igb_get_eeprom(struct net_device *netdev, 734 struct ethtool_eeprom *eeprom, u8 *bytes) 735 { 736 struct igb_adapter *adapter = netdev_priv(netdev); 737 struct e1000_hw *hw = &adapter->hw; 738 u16 *eeprom_buff; 739 int first_word, last_word; 740 int ret_val = 0; 741 u16 i; 742 743 if (eeprom->len == 0) 744 return -EINVAL; 745 746 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 747 748 first_word = eeprom->offset >> 1; 749 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 750 751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 752 GFP_KERNEL); 753 if (!eeprom_buff) 754 return -ENOMEM; 755 756 if (hw->nvm.type == e1000_nvm_eeprom_spi) 757 ret_val = hw->nvm.ops.read(hw, first_word, 758 last_word - first_word + 1, 759 eeprom_buff); 760 else { 761 for (i = 0; i < last_word - first_word + 1; i++) { 762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 763 &eeprom_buff[i]); 764 if (ret_val) 765 break; 766 } 767 } 768 769 /* Device's eeprom is always little-endian, word addressable */ 770 for (i = 0; i < last_word - first_word + 1; i++) 771 le16_to_cpus(&eeprom_buff[i]); 772 773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 774 eeprom->len); 775 kfree(eeprom_buff); 776 777 return ret_val; 778 } 779 780 static int igb_set_eeprom(struct net_device *netdev, 781 struct ethtool_eeprom *eeprom, u8 *bytes) 782 { 783 struct igb_adapter *adapter = netdev_priv(netdev); 784 struct e1000_hw *hw = &adapter->hw; 785 u16 *eeprom_buff; 786 void *ptr; 787 int max_len, first_word, last_word, ret_val = 0; 788 u16 i; 789 790 if (eeprom->len == 0) 791 return -EOPNOTSUPP; 792 793 if ((hw->mac.type >= e1000_i210) && 794 !igb_get_flash_presence_i210(hw)) { 795 return -EOPNOTSUPP; 796 } 797 798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 799 return -EFAULT; 800 801 max_len = hw->nvm.word_size * 2; 802 803 first_word = eeprom->offset >> 1; 804 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 805 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 806 if (!eeprom_buff) 807 return -ENOMEM; 808 809 ptr = (void *)eeprom_buff; 810 811 if (eeprom->offset & 1) { 812 /* need read/modify/write of first changed EEPROM word 813 * only the second byte of the word is being modified 814 */ 815 ret_val = hw->nvm.ops.read(hw, first_word, 1, 816 &eeprom_buff[0]); 817 ptr++; 818 } 819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 820 /* need read/modify/write of last changed EEPROM word 821 * only the first byte of the word is being modified 822 */ 823 ret_val = hw->nvm.ops.read(hw, last_word, 1, 824 &eeprom_buff[last_word - first_word]); 825 } 826 827 /* Device's eeprom is always little-endian, word addressable */ 828 for (i = 0; i < last_word - first_word + 1; i++) 829 le16_to_cpus(&eeprom_buff[i]); 830 831 memcpy(ptr, bytes, eeprom->len); 832 833 for (i = 0; i < last_word - first_word + 1; i++) 834 cpu_to_le16s(&eeprom_buff[i]); 835 836 ret_val = hw->nvm.ops.write(hw, first_word, 837 last_word - first_word + 1, eeprom_buff); 838 839 /* Update the checksum if nvm write succeeded */ 840 if (ret_val == 0) 841 hw->nvm.ops.update(hw); 842 843 igb_set_fw_version(adapter); 844 kfree(eeprom_buff); 845 return ret_val; 846 } 847 848 static void igb_get_drvinfo(struct net_device *netdev, 849 struct ethtool_drvinfo *drvinfo) 850 { 851 struct igb_adapter *adapter = netdev_priv(netdev); 852 853 strscpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 854 855 /* EEPROM image version # is reported as firmware version # for 856 * 82575 controllers 857 */ 858 strscpy(drvinfo->fw_version, adapter->fw_version, 859 sizeof(drvinfo->fw_version)); 860 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), 861 sizeof(drvinfo->bus_info)); 862 863 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN; 864 } 865 866 static void igb_get_ringparam(struct net_device *netdev, 867 struct ethtool_ringparam *ring, 868 struct kernel_ethtool_ringparam *kernel_ring, 869 struct netlink_ext_ack *extack) 870 { 871 struct igb_adapter *adapter = netdev_priv(netdev); 872 873 ring->rx_max_pending = IGB_MAX_RXD; 874 ring->tx_max_pending = IGB_MAX_TXD; 875 ring->rx_pending = adapter->rx_ring_count; 876 ring->tx_pending = adapter->tx_ring_count; 877 } 878 879 static int igb_set_ringparam(struct net_device *netdev, 880 struct ethtool_ringparam *ring, 881 struct kernel_ethtool_ringparam *kernel_ring, 882 struct netlink_ext_ack *extack) 883 { 884 struct igb_adapter *adapter = netdev_priv(netdev); 885 struct igb_ring *temp_ring; 886 int i, err = 0; 887 u16 new_rx_count, new_tx_count; 888 889 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 890 return -EINVAL; 891 892 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 893 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 894 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 895 896 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 897 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 898 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 899 900 if ((new_tx_count == adapter->tx_ring_count) && 901 (new_rx_count == adapter->rx_ring_count)) { 902 /* nothing to do */ 903 return 0; 904 } 905 906 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 907 usleep_range(1000, 2000); 908 909 if (!netif_running(adapter->netdev)) { 910 for (i = 0; i < adapter->num_tx_queues; i++) 911 adapter->tx_ring[i]->count = new_tx_count; 912 for (i = 0; i < adapter->num_rx_queues; i++) 913 adapter->rx_ring[i]->count = new_rx_count; 914 adapter->tx_ring_count = new_tx_count; 915 adapter->rx_ring_count = new_rx_count; 916 goto clear_reset; 917 } 918 919 if (adapter->num_tx_queues > adapter->num_rx_queues) 920 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 921 adapter->num_tx_queues)); 922 else 923 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 924 adapter->num_rx_queues)); 925 926 if (!temp_ring) { 927 err = -ENOMEM; 928 goto clear_reset; 929 } 930 931 igb_down(adapter); 932 933 /* We can't just free everything and then setup again, 934 * because the ISRs in MSI-X mode get passed pointers 935 * to the Tx and Rx ring structs. 936 */ 937 if (new_tx_count != adapter->tx_ring_count) { 938 for (i = 0; i < adapter->num_tx_queues; i++) { 939 memcpy(&temp_ring[i], adapter->tx_ring[i], 940 sizeof(struct igb_ring)); 941 942 temp_ring[i].count = new_tx_count; 943 err = igb_setup_tx_resources(&temp_ring[i]); 944 if (err) { 945 while (i) { 946 i--; 947 igb_free_tx_resources(&temp_ring[i]); 948 } 949 goto err_setup; 950 } 951 } 952 953 for (i = 0; i < adapter->num_tx_queues; i++) { 954 igb_free_tx_resources(adapter->tx_ring[i]); 955 956 memcpy(adapter->tx_ring[i], &temp_ring[i], 957 sizeof(struct igb_ring)); 958 } 959 960 adapter->tx_ring_count = new_tx_count; 961 } 962 963 if (new_rx_count != adapter->rx_ring_count) { 964 for (i = 0; i < adapter->num_rx_queues; i++) { 965 memcpy(&temp_ring[i], adapter->rx_ring[i], 966 sizeof(struct igb_ring)); 967 968 temp_ring[i].count = new_rx_count; 969 err = igb_setup_rx_resources(&temp_ring[i]); 970 if (err) { 971 while (i) { 972 i--; 973 igb_free_rx_resources(&temp_ring[i]); 974 } 975 goto err_setup; 976 } 977 978 } 979 980 for (i = 0; i < adapter->num_rx_queues; i++) { 981 igb_free_rx_resources(adapter->rx_ring[i]); 982 983 memcpy(adapter->rx_ring[i], &temp_ring[i], 984 sizeof(struct igb_ring)); 985 } 986 987 adapter->rx_ring_count = new_rx_count; 988 } 989 err_setup: 990 igb_up(adapter); 991 vfree(temp_ring); 992 clear_reset: 993 clear_bit(__IGB_RESETTING, &adapter->state); 994 return err; 995 } 996 997 /* ethtool register test data */ 998 struct igb_reg_test { 999 u16 reg; 1000 u16 reg_offset; 1001 u16 array_len; 1002 u16 test_type; 1003 u32 mask; 1004 u32 write; 1005 }; 1006 1007 /* In the hardware, registers are laid out either singly, in arrays 1008 * spaced 0x100 bytes apart, or in contiguous tables. We assume 1009 * most tests take place on arrays or single registers (handled 1010 * as a single-element array) and special-case the tables. 1011 * Table tests are always pattern tests. 1012 * 1013 * We also make provision for some required setup steps by specifying 1014 * registers to be written without any read-back testing. 1015 */ 1016 1017 #define PATTERN_TEST 1 1018 #define SET_READ_TEST 2 1019 #define WRITE_NO_TEST 3 1020 #define TABLE32_TEST 4 1021 #define TABLE64_TEST_LO 5 1022 #define TABLE64_TEST_HI 6 1023 1024 /* i210 reg test */ 1025 static struct igb_reg_test reg_test_i210[] = { 1026 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1027 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1028 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1029 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1030 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1031 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1032 /* RDH is read-only for i210, only test RDT. */ 1033 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1034 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1035 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1036 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1037 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1038 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1039 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1040 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1041 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1042 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1043 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1044 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1045 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1046 0xFFFFFFFF, 0xFFFFFFFF }, 1047 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1048 0x900FFFFF, 0xFFFFFFFF }, 1049 { E1000_MTA, 0, 128, TABLE32_TEST, 1050 0xFFFFFFFF, 0xFFFFFFFF }, 1051 { 0, 0, 0, 0, 0 } 1052 }; 1053 1054 /* i350 reg test */ 1055 static struct igb_reg_test reg_test_i350[] = { 1056 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1057 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1058 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1059 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1060 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1061 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1062 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1063 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1064 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1065 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1066 /* RDH is read-only for i350, only test RDT. */ 1067 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1068 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1069 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1070 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1071 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1072 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1073 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1074 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1075 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1076 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1077 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1078 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1079 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1080 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1081 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1082 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1083 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1084 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1085 0xFFFFFFFF, 0xFFFFFFFF }, 1086 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1087 0xC3FFFFFF, 0xFFFFFFFF }, 1088 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1089 0xFFFFFFFF, 0xFFFFFFFF }, 1090 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1091 0xC3FFFFFF, 0xFFFFFFFF }, 1092 { E1000_MTA, 0, 128, TABLE32_TEST, 1093 0xFFFFFFFF, 0xFFFFFFFF }, 1094 { 0, 0, 0, 0 } 1095 }; 1096 1097 /* 82580 reg test */ 1098 static struct igb_reg_test reg_test_82580[] = { 1099 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1100 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1101 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1102 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1103 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1104 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1105 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1106 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1107 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1108 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1109 /* RDH is read-only for 82580, only test RDT. */ 1110 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1111 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1112 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1113 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1114 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1115 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1116 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1117 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1118 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1119 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1120 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1121 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1122 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1123 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1124 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1125 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1126 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1127 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1128 0xFFFFFFFF, 0xFFFFFFFF }, 1129 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1130 0x83FFFFFF, 0xFFFFFFFF }, 1131 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1132 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1134 0x83FFFFFF, 0xFFFFFFFF }, 1135 { E1000_MTA, 0, 128, TABLE32_TEST, 1136 0xFFFFFFFF, 0xFFFFFFFF }, 1137 { 0, 0, 0, 0 } 1138 }; 1139 1140 /* 82576 reg test */ 1141 static struct igb_reg_test reg_test_82576[] = { 1142 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1143 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1144 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1145 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1146 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1147 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1148 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1149 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1150 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1151 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1152 /* Enable all RX queues before testing. */ 1153 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1154 E1000_RXDCTL_QUEUE_ENABLE }, 1155 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1156 E1000_RXDCTL_QUEUE_ENABLE }, 1157 /* RDH is read-only for 82576, only test RDT. */ 1158 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1159 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1160 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1161 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1162 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1163 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1164 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1165 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1166 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1167 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1168 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1169 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1170 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1171 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1172 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1173 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1174 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1175 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1176 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1177 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1178 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1179 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1180 { 0, 0, 0, 0 } 1181 }; 1182 1183 /* 82575 register test */ 1184 static struct igb_reg_test reg_test_82575[] = { 1185 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1186 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1187 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1188 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1189 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1190 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1191 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1192 /* Enable all four RX queues before testing. */ 1193 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1194 E1000_RXDCTL_QUEUE_ENABLE }, 1195 /* RDH is read-only for 82575, only test RDT. */ 1196 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1197 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1198 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1199 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1200 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1201 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1202 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1203 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1204 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1205 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1206 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1207 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1208 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1209 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1210 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1211 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1212 { 0, 0, 0, 0 } 1213 }; 1214 1215 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1216 int reg, u32 mask, u32 write) 1217 { 1218 struct e1000_hw *hw = &adapter->hw; 1219 u32 pat, val; 1220 static const u32 _test[] = { 1221 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1222 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1223 wr32(reg, (_test[pat] & write)); 1224 val = rd32(reg) & mask; 1225 if (val != (_test[pat] & write & mask)) { 1226 dev_err(&adapter->pdev->dev, 1227 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1228 reg, val, (_test[pat] & write & mask)); 1229 *data = reg; 1230 return true; 1231 } 1232 } 1233 1234 return false; 1235 } 1236 1237 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1238 int reg, u32 mask, u32 write) 1239 { 1240 struct e1000_hw *hw = &adapter->hw; 1241 u32 val; 1242 1243 wr32(reg, write & mask); 1244 val = rd32(reg); 1245 if ((write & mask) != (val & mask)) { 1246 dev_err(&adapter->pdev->dev, 1247 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1248 reg, (val & mask), (write & mask)); 1249 *data = reg; 1250 return true; 1251 } 1252 1253 return false; 1254 } 1255 1256 #define REG_PATTERN_TEST(reg, mask, write) \ 1257 do { \ 1258 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1259 return 1; \ 1260 } while (0) 1261 1262 #define REG_SET_AND_CHECK(reg, mask, write) \ 1263 do { \ 1264 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1265 return 1; \ 1266 } while (0) 1267 1268 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1269 { 1270 struct e1000_hw *hw = &adapter->hw; 1271 struct igb_reg_test *test; 1272 u32 value, before, after; 1273 u32 i, toggle; 1274 1275 switch (adapter->hw.mac.type) { 1276 case e1000_i350: 1277 case e1000_i354: 1278 test = reg_test_i350; 1279 toggle = 0x7FEFF3FF; 1280 break; 1281 case e1000_i210: 1282 case e1000_i211: 1283 test = reg_test_i210; 1284 toggle = 0x7FEFF3FF; 1285 break; 1286 case e1000_82580: 1287 test = reg_test_82580; 1288 toggle = 0x7FEFF3FF; 1289 break; 1290 case e1000_82576: 1291 test = reg_test_82576; 1292 toggle = 0x7FFFF3FF; 1293 break; 1294 default: 1295 test = reg_test_82575; 1296 toggle = 0x7FFFF3FF; 1297 break; 1298 } 1299 1300 /* Because the status register is such a special case, 1301 * we handle it separately from the rest of the register 1302 * tests. Some bits are read-only, some toggle, and some 1303 * are writable on newer MACs. 1304 */ 1305 before = rd32(E1000_STATUS); 1306 value = (rd32(E1000_STATUS) & toggle); 1307 wr32(E1000_STATUS, toggle); 1308 after = rd32(E1000_STATUS) & toggle; 1309 if (value != after) { 1310 dev_err(&adapter->pdev->dev, 1311 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1312 after, value); 1313 *data = 1; 1314 return 1; 1315 } 1316 /* restore previous status */ 1317 wr32(E1000_STATUS, before); 1318 1319 /* Perform the remainder of the register test, looping through 1320 * the test table until we either fail or reach the null entry. 1321 */ 1322 while (test->reg) { 1323 for (i = 0; i < test->array_len; i++) { 1324 switch (test->test_type) { 1325 case PATTERN_TEST: 1326 REG_PATTERN_TEST(test->reg + 1327 (i * test->reg_offset), 1328 test->mask, 1329 test->write); 1330 break; 1331 case SET_READ_TEST: 1332 REG_SET_AND_CHECK(test->reg + 1333 (i * test->reg_offset), 1334 test->mask, 1335 test->write); 1336 break; 1337 case WRITE_NO_TEST: 1338 writel(test->write, 1339 (adapter->hw.hw_addr + test->reg) 1340 + (i * test->reg_offset)); 1341 break; 1342 case TABLE32_TEST: 1343 REG_PATTERN_TEST(test->reg + (i * 4), 1344 test->mask, 1345 test->write); 1346 break; 1347 case TABLE64_TEST_LO: 1348 REG_PATTERN_TEST(test->reg + (i * 8), 1349 test->mask, 1350 test->write); 1351 break; 1352 case TABLE64_TEST_HI: 1353 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1354 test->mask, 1355 test->write); 1356 break; 1357 } 1358 } 1359 test++; 1360 } 1361 1362 *data = 0; 1363 return 0; 1364 } 1365 1366 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1367 { 1368 struct e1000_hw *hw = &adapter->hw; 1369 1370 *data = 0; 1371 1372 /* Validate eeprom on all parts but flashless */ 1373 switch (hw->mac.type) { 1374 case e1000_i210: 1375 case e1000_i211: 1376 if (igb_get_flash_presence_i210(hw)) { 1377 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1378 *data = 2; 1379 } 1380 break; 1381 default: 1382 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1383 *data = 2; 1384 break; 1385 } 1386 1387 return *data; 1388 } 1389 1390 static irqreturn_t igb_test_intr(int irq, void *data) 1391 { 1392 struct igb_adapter *adapter = (struct igb_adapter *) data; 1393 struct e1000_hw *hw = &adapter->hw; 1394 1395 adapter->test_icr |= rd32(E1000_ICR); 1396 1397 return IRQ_HANDLED; 1398 } 1399 1400 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1401 { 1402 struct e1000_hw *hw = &adapter->hw; 1403 struct net_device *netdev = adapter->netdev; 1404 u32 mask, ics_mask, i = 0, shared_int = true; 1405 u32 irq = adapter->pdev->irq; 1406 1407 *data = 0; 1408 1409 /* Hook up test interrupt handler just for this test */ 1410 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1411 if (request_irq(adapter->msix_entries[0].vector, 1412 igb_test_intr, 0, netdev->name, adapter)) { 1413 *data = 1; 1414 return -1; 1415 } 1416 wr32(E1000_IVAR_MISC, E1000_IVAR_VALID << 8); 1417 wr32(E1000_EIMS, BIT(0)); 1418 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1419 shared_int = false; 1420 if (request_irq(irq, 1421 igb_test_intr, 0, netdev->name, adapter)) { 1422 *data = 1; 1423 return -1; 1424 } 1425 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1426 netdev->name, adapter)) { 1427 shared_int = false; 1428 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1429 netdev->name, adapter)) { 1430 *data = 1; 1431 return -1; 1432 } 1433 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1434 (shared_int ? "shared" : "unshared")); 1435 1436 /* Disable all the interrupts */ 1437 wr32(E1000_IMC, ~0); 1438 wrfl(); 1439 usleep_range(10000, 11000); 1440 1441 /* Define all writable bits for ICS */ 1442 switch (hw->mac.type) { 1443 case e1000_82575: 1444 ics_mask = 0x37F47EDD; 1445 break; 1446 case e1000_82576: 1447 ics_mask = 0x77D4FBFD; 1448 break; 1449 case e1000_82580: 1450 ics_mask = 0x77DCFED5; 1451 break; 1452 case e1000_i350: 1453 case e1000_i354: 1454 case e1000_i210: 1455 case e1000_i211: 1456 ics_mask = 0x77DCFED5; 1457 break; 1458 default: 1459 ics_mask = 0x7FFFFFFF; 1460 break; 1461 } 1462 1463 /* Test each interrupt */ 1464 for (; i < 31; i++) { 1465 /* Interrupt to test */ 1466 mask = BIT(i); 1467 1468 if (!(mask & ics_mask)) 1469 continue; 1470 1471 if (!shared_int) { 1472 /* Disable the interrupt to be reported in 1473 * the cause register and then force the same 1474 * interrupt and see if one gets posted. If 1475 * an interrupt was posted to the bus, the 1476 * test failed. 1477 */ 1478 adapter->test_icr = 0; 1479 1480 /* Flush any pending interrupts */ 1481 wr32(E1000_ICR, ~0); 1482 1483 wr32(E1000_IMC, mask); 1484 wr32(E1000_ICS, mask); 1485 wrfl(); 1486 usleep_range(10000, 11000); 1487 1488 if (adapter->test_icr & mask) { 1489 *data = 3; 1490 break; 1491 } 1492 } 1493 1494 /* Enable the interrupt to be reported in 1495 * the cause register and then force the same 1496 * interrupt and see if one gets posted. If 1497 * an interrupt was not posted to the bus, the 1498 * test failed. 1499 */ 1500 adapter->test_icr = 0; 1501 1502 /* Flush any pending interrupts */ 1503 wr32(E1000_ICR, ~0); 1504 1505 wr32(E1000_IMS, mask); 1506 wr32(E1000_ICS, mask); 1507 wrfl(); 1508 usleep_range(10000, 11000); 1509 1510 if (!(adapter->test_icr & mask)) { 1511 *data = 4; 1512 break; 1513 } 1514 1515 if (!shared_int) { 1516 /* Disable the other interrupts to be reported in 1517 * the cause register and then force the other 1518 * interrupts and see if any get posted. If 1519 * an interrupt was posted to the bus, the 1520 * test failed. 1521 */ 1522 adapter->test_icr = 0; 1523 1524 /* Flush any pending interrupts */ 1525 wr32(E1000_ICR, ~0); 1526 1527 wr32(E1000_IMC, ~mask); 1528 wr32(E1000_ICS, ~mask); 1529 wrfl(); 1530 usleep_range(10000, 11000); 1531 1532 if (adapter->test_icr & mask) { 1533 *data = 5; 1534 break; 1535 } 1536 } 1537 } 1538 1539 /* Disable all the interrupts */ 1540 wr32(E1000_IMC, ~0); 1541 wrfl(); 1542 usleep_range(10000, 11000); 1543 1544 /* Unhook test interrupt handler */ 1545 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1546 free_irq(adapter->msix_entries[0].vector, adapter); 1547 else 1548 free_irq(irq, adapter); 1549 1550 return *data; 1551 } 1552 1553 static void igb_free_desc_rings(struct igb_adapter *adapter) 1554 { 1555 igb_free_tx_resources(&adapter->test_tx_ring); 1556 igb_free_rx_resources(&adapter->test_rx_ring); 1557 } 1558 1559 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1560 { 1561 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1562 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1563 struct e1000_hw *hw = &adapter->hw; 1564 int ret_val; 1565 1566 /* Setup Tx descriptor ring and Tx buffers */ 1567 tx_ring->count = IGB_DEFAULT_TXD; 1568 tx_ring->dev = &adapter->pdev->dev; 1569 tx_ring->netdev = adapter->netdev; 1570 tx_ring->reg_idx = adapter->vfs_allocated_count; 1571 1572 if (igb_setup_tx_resources(tx_ring)) { 1573 ret_val = 1; 1574 goto err_nomem; 1575 } 1576 1577 igb_setup_tctl(adapter); 1578 igb_configure_tx_ring(adapter, tx_ring); 1579 1580 /* Setup Rx descriptor ring and Rx buffers */ 1581 rx_ring->count = IGB_DEFAULT_RXD; 1582 rx_ring->dev = &adapter->pdev->dev; 1583 rx_ring->netdev = adapter->netdev; 1584 rx_ring->reg_idx = adapter->vfs_allocated_count; 1585 1586 if (igb_setup_rx_resources(rx_ring)) { 1587 ret_val = 3; 1588 goto err_nomem; 1589 } 1590 1591 /* set the default queue to queue 0 of PF */ 1592 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1593 1594 /* enable receive ring */ 1595 igb_setup_rctl(adapter); 1596 igb_configure_rx_ring(adapter, rx_ring); 1597 1598 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1599 1600 return 0; 1601 1602 err_nomem: 1603 igb_free_desc_rings(adapter); 1604 return ret_val; 1605 } 1606 1607 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1608 { 1609 struct e1000_hw *hw = &adapter->hw; 1610 1611 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1612 igb_write_phy_reg(hw, 29, 0x001F); 1613 igb_write_phy_reg(hw, 30, 0x8FFC); 1614 igb_write_phy_reg(hw, 29, 0x001A); 1615 igb_write_phy_reg(hw, 30, 0x8FF0); 1616 } 1617 1618 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1619 { 1620 struct e1000_hw *hw = &adapter->hw; 1621 u32 ctrl_reg = 0; 1622 1623 hw->mac.autoneg = false; 1624 1625 if (hw->phy.type == e1000_phy_m88) { 1626 if (hw->phy.id != I210_I_PHY_ID) { 1627 /* Auto-MDI/MDIX Off */ 1628 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1629 /* reset to update Auto-MDI/MDIX */ 1630 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1631 /* autoneg off */ 1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1633 } else { 1634 /* force 1000, set loopback */ 1635 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1636 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1637 } 1638 } else if (hw->phy.type == e1000_phy_82580) { 1639 /* enable MII loopback */ 1640 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1641 } 1642 1643 /* add small delay to avoid loopback test failure */ 1644 msleep(50); 1645 1646 /* force 1000, set loopback */ 1647 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1648 1649 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1650 ctrl_reg = rd32(E1000_CTRL); 1651 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1652 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1653 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1654 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1655 E1000_CTRL_FD | /* Force Duplex to FULL */ 1656 E1000_CTRL_SLU); /* Set link up enable bit */ 1657 1658 if (hw->phy.type == e1000_phy_m88) 1659 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1660 1661 wr32(E1000_CTRL, ctrl_reg); 1662 1663 /* Disable the receiver on the PHY so when a cable is plugged in, the 1664 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1665 */ 1666 if (hw->phy.type == e1000_phy_m88) 1667 igb_phy_disable_receiver(adapter); 1668 1669 msleep(500); 1670 return 0; 1671 } 1672 1673 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1674 { 1675 return igb_integrated_phy_loopback(adapter); 1676 } 1677 1678 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1679 { 1680 struct e1000_hw *hw = &adapter->hw; 1681 u32 reg; 1682 1683 reg = rd32(E1000_CTRL_EXT); 1684 1685 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1686 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1687 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1688 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1689 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1690 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1691 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1692 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1693 /* Enable DH89xxCC MPHY for near end loopback */ 1694 reg = rd32(E1000_MPHY_ADDR_CTL); 1695 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1696 E1000_MPHY_PCS_CLK_REG_OFFSET; 1697 wr32(E1000_MPHY_ADDR_CTL, reg); 1698 1699 reg = rd32(E1000_MPHY_DATA); 1700 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1701 wr32(E1000_MPHY_DATA, reg); 1702 } 1703 1704 reg = rd32(E1000_RCTL); 1705 reg |= E1000_RCTL_LBM_TCVR; 1706 wr32(E1000_RCTL, reg); 1707 1708 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1709 1710 reg = rd32(E1000_CTRL); 1711 reg &= ~(E1000_CTRL_RFCE | 1712 E1000_CTRL_TFCE | 1713 E1000_CTRL_LRST); 1714 reg |= E1000_CTRL_SLU | 1715 E1000_CTRL_FD; 1716 wr32(E1000_CTRL, reg); 1717 1718 /* Unset switch control to serdes energy detect */ 1719 reg = rd32(E1000_CONNSW); 1720 reg &= ~E1000_CONNSW_ENRGSRC; 1721 wr32(E1000_CONNSW, reg); 1722 1723 /* Unset sigdetect for SERDES loopback on 1724 * 82580 and newer devices. 1725 */ 1726 if (hw->mac.type >= e1000_82580) { 1727 reg = rd32(E1000_PCS_CFG0); 1728 reg |= E1000_PCS_CFG_IGN_SD; 1729 wr32(E1000_PCS_CFG0, reg); 1730 } 1731 1732 /* Set PCS register for forced speed */ 1733 reg = rd32(E1000_PCS_LCTL); 1734 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1735 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1736 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1737 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1738 E1000_PCS_LCTL_FSD | /* Force Speed */ 1739 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1740 wr32(E1000_PCS_LCTL, reg); 1741 1742 return 0; 1743 } 1744 1745 return igb_set_phy_loopback(adapter); 1746 } 1747 1748 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1749 { 1750 struct e1000_hw *hw = &adapter->hw; 1751 u32 rctl; 1752 u16 phy_reg; 1753 1754 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1755 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1756 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1757 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1758 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1759 u32 reg; 1760 1761 /* Disable near end loopback on DH89xxCC */ 1762 reg = rd32(E1000_MPHY_ADDR_CTL); 1763 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1764 E1000_MPHY_PCS_CLK_REG_OFFSET; 1765 wr32(E1000_MPHY_ADDR_CTL, reg); 1766 1767 reg = rd32(E1000_MPHY_DATA); 1768 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1769 wr32(E1000_MPHY_DATA, reg); 1770 } 1771 1772 rctl = rd32(E1000_RCTL); 1773 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1774 wr32(E1000_RCTL, rctl); 1775 1776 hw->mac.autoneg = true; 1777 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1778 if (phy_reg & MII_CR_LOOPBACK) { 1779 phy_reg &= ~MII_CR_LOOPBACK; 1780 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1781 igb_phy_sw_reset(hw); 1782 } 1783 } 1784 1785 static void igb_create_lbtest_frame(struct sk_buff *skb, 1786 unsigned int frame_size) 1787 { 1788 memset(skb->data, 0xFF, frame_size); 1789 frame_size /= 2; 1790 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1791 skb->data[frame_size + 10] = 0xBE; 1792 skb->data[frame_size + 12] = 0xAF; 1793 } 1794 1795 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1796 unsigned int frame_size) 1797 { 1798 unsigned char *data; 1799 bool match = true; 1800 1801 frame_size >>= 1; 1802 1803 data = kmap_local_page(rx_buffer->page); 1804 1805 if (data[3] != 0xFF || 1806 data[frame_size + 10] != 0xBE || 1807 data[frame_size + 12] != 0xAF) 1808 match = false; 1809 1810 kunmap_local(data); 1811 1812 return match; 1813 } 1814 1815 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1816 struct igb_ring *tx_ring, 1817 unsigned int size) 1818 { 1819 union e1000_adv_rx_desc *rx_desc; 1820 struct igb_rx_buffer *rx_buffer_info; 1821 struct igb_tx_buffer *tx_buffer_info; 1822 u16 rx_ntc, tx_ntc, count = 0; 1823 1824 /* initialize next to clean and descriptor values */ 1825 rx_ntc = rx_ring->next_to_clean; 1826 tx_ntc = tx_ring->next_to_clean; 1827 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1828 1829 while (rx_desc->wb.upper.length) { 1830 /* check Rx buffer */ 1831 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1832 1833 /* sync Rx buffer for CPU read */ 1834 dma_sync_single_for_cpu(rx_ring->dev, 1835 rx_buffer_info->dma, 1836 size, 1837 DMA_FROM_DEVICE); 1838 1839 /* verify contents of skb */ 1840 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1841 count++; 1842 1843 /* sync Rx buffer for device write */ 1844 dma_sync_single_for_device(rx_ring->dev, 1845 rx_buffer_info->dma, 1846 size, 1847 DMA_FROM_DEVICE); 1848 1849 /* unmap buffer on Tx side */ 1850 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1851 1852 /* Free all the Tx ring sk_buffs */ 1853 dev_kfree_skb_any(tx_buffer_info->skb); 1854 1855 /* unmap skb header data */ 1856 dma_unmap_single(tx_ring->dev, 1857 dma_unmap_addr(tx_buffer_info, dma), 1858 dma_unmap_len(tx_buffer_info, len), 1859 DMA_TO_DEVICE); 1860 dma_unmap_len_set(tx_buffer_info, len, 0); 1861 1862 /* increment Rx/Tx next to clean counters */ 1863 rx_ntc++; 1864 if (rx_ntc == rx_ring->count) 1865 rx_ntc = 0; 1866 tx_ntc++; 1867 if (tx_ntc == tx_ring->count) 1868 tx_ntc = 0; 1869 1870 /* fetch next descriptor */ 1871 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1872 } 1873 1874 netdev_tx_reset_queue(txring_txq(tx_ring)); 1875 1876 /* re-map buffers to ring, store next to clean values */ 1877 igb_alloc_rx_buffers(rx_ring, count); 1878 rx_ring->next_to_clean = rx_ntc; 1879 tx_ring->next_to_clean = tx_ntc; 1880 1881 return count; 1882 } 1883 1884 static int igb_run_loopback_test(struct igb_adapter *adapter) 1885 { 1886 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1887 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1888 u16 i, j, lc, good_cnt; 1889 int ret_val = 0; 1890 unsigned int size = IGB_RX_HDR_LEN; 1891 netdev_tx_t tx_ret_val; 1892 struct sk_buff *skb; 1893 1894 /* allocate test skb */ 1895 skb = alloc_skb(size, GFP_KERNEL); 1896 if (!skb) 1897 return 11; 1898 1899 /* place data into test skb */ 1900 igb_create_lbtest_frame(skb, size); 1901 skb_put(skb, size); 1902 1903 /* Calculate the loop count based on the largest descriptor ring 1904 * The idea is to wrap the largest ring a number of times using 64 1905 * send/receive pairs during each loop 1906 */ 1907 1908 if (rx_ring->count <= tx_ring->count) 1909 lc = ((tx_ring->count / 64) * 2) + 1; 1910 else 1911 lc = ((rx_ring->count / 64) * 2) + 1; 1912 1913 for (j = 0; j <= lc; j++) { /* loop count loop */ 1914 /* reset count of good packets */ 1915 good_cnt = 0; 1916 1917 /* place 64 packets on the transmit queue*/ 1918 for (i = 0; i < 64; i++) { 1919 skb_get(skb); 1920 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1921 if (tx_ret_val == NETDEV_TX_OK) 1922 good_cnt++; 1923 } 1924 1925 if (good_cnt != 64) { 1926 ret_val = 12; 1927 break; 1928 } 1929 1930 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1931 msleep(200); 1932 1933 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1934 if (good_cnt != 64) { 1935 ret_val = 13; 1936 break; 1937 } 1938 } /* end loop count loop */ 1939 1940 /* free the original skb */ 1941 kfree_skb(skb); 1942 1943 return ret_val; 1944 } 1945 1946 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1947 { 1948 /* PHY loopback cannot be performed if SoL/IDER 1949 * sessions are active 1950 */ 1951 if (igb_check_reset_block(&adapter->hw)) { 1952 dev_err(&adapter->pdev->dev, 1953 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1954 *data = 0; 1955 goto out; 1956 } 1957 1958 if (adapter->hw.mac.type == e1000_i354) { 1959 dev_info(&adapter->pdev->dev, 1960 "Loopback test not supported on i354.\n"); 1961 *data = 0; 1962 goto out; 1963 } 1964 *data = igb_setup_desc_rings(adapter); 1965 if (*data) 1966 goto out; 1967 *data = igb_setup_loopback_test(adapter); 1968 if (*data) 1969 goto err_loopback; 1970 *data = igb_run_loopback_test(adapter); 1971 igb_loopback_cleanup(adapter); 1972 1973 err_loopback: 1974 igb_free_desc_rings(adapter); 1975 out: 1976 return *data; 1977 } 1978 1979 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1980 { 1981 struct e1000_hw *hw = &adapter->hw; 1982 *data = 0; 1983 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1984 int i = 0; 1985 1986 hw->mac.serdes_has_link = false; 1987 1988 /* On some blade server designs, link establishment 1989 * could take as long as 2-3 minutes 1990 */ 1991 do { 1992 hw->mac.ops.check_for_link(&adapter->hw); 1993 if (hw->mac.serdes_has_link) 1994 return *data; 1995 msleep(20); 1996 } while (i++ < 3750); 1997 1998 *data = 1; 1999 } else { 2000 hw->mac.ops.check_for_link(&adapter->hw); 2001 if (hw->mac.autoneg) 2002 msleep(5000); 2003 2004 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 2005 *data = 1; 2006 } 2007 return *data; 2008 } 2009 2010 static void igb_diag_test(struct net_device *netdev, 2011 struct ethtool_test *eth_test, u64 *data) 2012 { 2013 struct igb_adapter *adapter = netdev_priv(netdev); 2014 u16 autoneg_advertised; 2015 u8 forced_speed_duplex, autoneg; 2016 bool if_running = netif_running(netdev); 2017 2018 set_bit(__IGB_TESTING, &adapter->state); 2019 2020 /* can't do offline tests on media switching devices */ 2021 if (adapter->hw.dev_spec._82575.mas_capable) 2022 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 2023 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2024 /* Offline tests */ 2025 2026 /* save speed, duplex, autoneg settings */ 2027 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2028 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2029 autoneg = adapter->hw.mac.autoneg; 2030 2031 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2032 2033 /* power up link for link test */ 2034 igb_power_up_link(adapter); 2035 2036 /* Link test performed before hardware reset so autoneg doesn't 2037 * interfere with test result 2038 */ 2039 if (igb_link_test(adapter, &data[TEST_LINK])) 2040 eth_test->flags |= ETH_TEST_FL_FAILED; 2041 2042 if (if_running) 2043 /* indicate we're in test mode */ 2044 igb_close(netdev); 2045 else 2046 igb_reset(adapter); 2047 2048 if (igb_reg_test(adapter, &data[TEST_REG])) 2049 eth_test->flags |= ETH_TEST_FL_FAILED; 2050 2051 igb_reset(adapter); 2052 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2053 eth_test->flags |= ETH_TEST_FL_FAILED; 2054 2055 igb_reset(adapter); 2056 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2057 eth_test->flags |= ETH_TEST_FL_FAILED; 2058 2059 igb_reset(adapter); 2060 /* power up link for loopback test */ 2061 igb_power_up_link(adapter); 2062 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2063 eth_test->flags |= ETH_TEST_FL_FAILED; 2064 2065 /* restore speed, duplex, autoneg settings */ 2066 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2067 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2068 adapter->hw.mac.autoneg = autoneg; 2069 2070 /* force this routine to wait until autoneg complete/timeout */ 2071 adapter->hw.phy.autoneg_wait_to_complete = true; 2072 igb_reset(adapter); 2073 adapter->hw.phy.autoneg_wait_to_complete = false; 2074 2075 clear_bit(__IGB_TESTING, &adapter->state); 2076 if (if_running) 2077 igb_open(netdev); 2078 } else { 2079 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2080 2081 /* PHY is powered down when interface is down */ 2082 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2083 eth_test->flags |= ETH_TEST_FL_FAILED; 2084 else 2085 data[TEST_LINK] = 0; 2086 2087 /* Online tests aren't run; pass by default */ 2088 data[TEST_REG] = 0; 2089 data[TEST_EEP] = 0; 2090 data[TEST_IRQ] = 0; 2091 data[TEST_LOOP] = 0; 2092 2093 clear_bit(__IGB_TESTING, &adapter->state); 2094 } 2095 msleep_interruptible(4 * 1000); 2096 } 2097 2098 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2099 { 2100 struct igb_adapter *adapter = netdev_priv(netdev); 2101 2102 wol->wolopts = 0; 2103 2104 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2105 return; 2106 2107 wol->supported = WAKE_UCAST | WAKE_MCAST | 2108 WAKE_BCAST | WAKE_MAGIC | 2109 WAKE_PHY; 2110 2111 /* apply any specific unsupported masks here */ 2112 switch (adapter->hw.device_id) { 2113 default: 2114 break; 2115 } 2116 2117 if (adapter->wol & E1000_WUFC_EX) 2118 wol->wolopts |= WAKE_UCAST; 2119 if (adapter->wol & E1000_WUFC_MC) 2120 wol->wolopts |= WAKE_MCAST; 2121 if (adapter->wol & E1000_WUFC_BC) 2122 wol->wolopts |= WAKE_BCAST; 2123 if (adapter->wol & E1000_WUFC_MAG) 2124 wol->wolopts |= WAKE_MAGIC; 2125 if (adapter->wol & E1000_WUFC_LNKC) 2126 wol->wolopts |= WAKE_PHY; 2127 } 2128 2129 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2130 { 2131 struct igb_adapter *adapter = netdev_priv(netdev); 2132 2133 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER)) 2134 return -EOPNOTSUPP; 2135 2136 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2137 return wol->wolopts ? -EOPNOTSUPP : 0; 2138 2139 /* these settings will always override what we currently have */ 2140 adapter->wol = 0; 2141 2142 if (wol->wolopts & WAKE_UCAST) 2143 adapter->wol |= E1000_WUFC_EX; 2144 if (wol->wolopts & WAKE_MCAST) 2145 adapter->wol |= E1000_WUFC_MC; 2146 if (wol->wolopts & WAKE_BCAST) 2147 adapter->wol |= E1000_WUFC_BC; 2148 if (wol->wolopts & WAKE_MAGIC) 2149 adapter->wol |= E1000_WUFC_MAG; 2150 if (wol->wolopts & WAKE_PHY) 2151 adapter->wol |= E1000_WUFC_LNKC; 2152 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2153 2154 return 0; 2155 } 2156 2157 /* bit defines for adapter->led_status */ 2158 #define IGB_LED_ON 0 2159 2160 static int igb_set_phys_id(struct net_device *netdev, 2161 enum ethtool_phys_id_state state) 2162 { 2163 struct igb_adapter *adapter = netdev_priv(netdev); 2164 struct e1000_hw *hw = &adapter->hw; 2165 2166 switch (state) { 2167 case ETHTOOL_ID_ACTIVE: 2168 igb_blink_led(hw); 2169 return 2; 2170 case ETHTOOL_ID_ON: 2171 igb_blink_led(hw); 2172 break; 2173 case ETHTOOL_ID_OFF: 2174 igb_led_off(hw); 2175 break; 2176 case ETHTOOL_ID_INACTIVE: 2177 igb_led_off(hw); 2178 clear_bit(IGB_LED_ON, &adapter->led_status); 2179 igb_cleanup_led(hw); 2180 break; 2181 } 2182 2183 return 0; 2184 } 2185 2186 static int igb_set_coalesce(struct net_device *netdev, 2187 struct ethtool_coalesce *ec, 2188 struct kernel_ethtool_coalesce *kernel_coal, 2189 struct netlink_ext_ack *extack) 2190 { 2191 struct igb_adapter *adapter = netdev_priv(netdev); 2192 int i; 2193 2194 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2195 ((ec->rx_coalesce_usecs > 3) && 2196 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2197 (ec->rx_coalesce_usecs == 2)) 2198 return -EINVAL; 2199 2200 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2201 ((ec->tx_coalesce_usecs > 3) && 2202 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2203 (ec->tx_coalesce_usecs == 2)) 2204 return -EINVAL; 2205 2206 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2207 return -EINVAL; 2208 2209 /* If ITR is disabled, disable DMAC */ 2210 if (ec->rx_coalesce_usecs == 0) { 2211 if (adapter->flags & IGB_FLAG_DMAC) 2212 adapter->flags &= ~IGB_FLAG_DMAC; 2213 } 2214 2215 /* convert to rate of irq's per second */ 2216 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2217 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2218 else 2219 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2220 2221 /* convert to rate of irq's per second */ 2222 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2223 adapter->tx_itr_setting = adapter->rx_itr_setting; 2224 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2225 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2226 else 2227 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2228 2229 for (i = 0; i < adapter->num_q_vectors; i++) { 2230 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2231 q_vector->tx.work_limit = adapter->tx_work_limit; 2232 if (q_vector->rx.ring) 2233 q_vector->itr_val = adapter->rx_itr_setting; 2234 else 2235 q_vector->itr_val = adapter->tx_itr_setting; 2236 if (q_vector->itr_val && q_vector->itr_val <= 3) 2237 q_vector->itr_val = IGB_START_ITR; 2238 q_vector->set_itr = 1; 2239 } 2240 2241 return 0; 2242 } 2243 2244 static int igb_get_coalesce(struct net_device *netdev, 2245 struct ethtool_coalesce *ec, 2246 struct kernel_ethtool_coalesce *kernel_coal, 2247 struct netlink_ext_ack *extack) 2248 { 2249 struct igb_adapter *adapter = netdev_priv(netdev); 2250 2251 if (adapter->rx_itr_setting <= 3) 2252 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2253 else 2254 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2255 2256 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2257 if (adapter->tx_itr_setting <= 3) 2258 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2259 else 2260 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int igb_nway_reset(struct net_device *netdev) 2267 { 2268 struct igb_adapter *adapter = netdev_priv(netdev); 2269 if (netif_running(netdev)) 2270 igb_reinit_locked(adapter); 2271 return 0; 2272 } 2273 2274 static int igb_get_sset_count(struct net_device *netdev, int sset) 2275 { 2276 switch (sset) { 2277 case ETH_SS_STATS: 2278 return IGB_STATS_LEN; 2279 case ETH_SS_TEST: 2280 return IGB_TEST_LEN; 2281 case ETH_SS_PRIV_FLAGS: 2282 return IGB_PRIV_FLAGS_STR_LEN; 2283 default: 2284 return -ENOTSUPP; 2285 } 2286 } 2287 2288 static void igb_get_ethtool_stats(struct net_device *netdev, 2289 struct ethtool_stats *stats, u64 *data) 2290 { 2291 struct igb_adapter *adapter = netdev_priv(netdev); 2292 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2293 unsigned int start; 2294 struct igb_ring *ring; 2295 int i, j; 2296 char *p; 2297 2298 spin_lock(&adapter->stats64_lock); 2299 igb_update_stats(adapter); 2300 2301 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2302 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2303 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2304 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2305 } 2306 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2307 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2308 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2309 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2310 } 2311 for (j = 0; j < adapter->num_tx_queues; j++) { 2312 u64 restart2; 2313 2314 ring = adapter->tx_ring[j]; 2315 do { 2316 start = u64_stats_fetch_begin(&ring->tx_syncp); 2317 data[i] = ring->tx_stats.packets; 2318 data[i+1] = ring->tx_stats.bytes; 2319 data[i+2] = ring->tx_stats.restart_queue; 2320 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 2321 do { 2322 start = u64_stats_fetch_begin(&ring->tx_syncp2); 2323 restart2 = ring->tx_stats.restart_queue2; 2324 } while (u64_stats_fetch_retry(&ring->tx_syncp2, start)); 2325 data[i+2] += restart2; 2326 2327 i += IGB_TX_QUEUE_STATS_LEN; 2328 } 2329 for (j = 0; j < adapter->num_rx_queues; j++) { 2330 ring = adapter->rx_ring[j]; 2331 do { 2332 start = u64_stats_fetch_begin(&ring->rx_syncp); 2333 data[i] = ring->rx_stats.packets; 2334 data[i+1] = ring->rx_stats.bytes; 2335 data[i+2] = ring->rx_stats.drops; 2336 data[i+3] = ring->rx_stats.csum_err; 2337 data[i+4] = ring->rx_stats.alloc_failed; 2338 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 2339 i += IGB_RX_QUEUE_STATS_LEN; 2340 } 2341 spin_unlock(&adapter->stats64_lock); 2342 } 2343 2344 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2345 { 2346 struct igb_adapter *adapter = netdev_priv(netdev); 2347 u8 *p = data; 2348 int i; 2349 2350 switch (stringset) { 2351 case ETH_SS_TEST: 2352 memcpy(data, igb_gstrings_test, sizeof(igb_gstrings_test)); 2353 break; 2354 case ETH_SS_STATS: 2355 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) 2356 ethtool_sprintf(&p, 2357 igb_gstrings_stats[i].stat_string); 2358 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) 2359 ethtool_sprintf(&p, 2360 igb_gstrings_net_stats[i].stat_string); 2361 for (i = 0; i < adapter->num_tx_queues; i++) { 2362 ethtool_sprintf(&p, "tx_queue_%u_packets", i); 2363 ethtool_sprintf(&p, "tx_queue_%u_bytes", i); 2364 ethtool_sprintf(&p, "tx_queue_%u_restart", i); 2365 } 2366 for (i = 0; i < adapter->num_rx_queues; i++) { 2367 ethtool_sprintf(&p, "rx_queue_%u_packets", i); 2368 ethtool_sprintf(&p, "rx_queue_%u_bytes", i); 2369 ethtool_sprintf(&p, "rx_queue_%u_drops", i); 2370 ethtool_sprintf(&p, "rx_queue_%u_csum_err", i); 2371 ethtool_sprintf(&p, "rx_queue_%u_alloc_failed", i); 2372 } 2373 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2374 break; 2375 case ETH_SS_PRIV_FLAGS: 2376 memcpy(data, igb_priv_flags_strings, 2377 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 2378 break; 2379 } 2380 } 2381 2382 static int igb_get_ts_info(struct net_device *dev, 2383 struct ethtool_ts_info *info) 2384 { 2385 struct igb_adapter *adapter = netdev_priv(dev); 2386 2387 if (adapter->ptp_clock) 2388 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2389 else 2390 info->phc_index = -1; 2391 2392 switch (adapter->hw.mac.type) { 2393 case e1000_82575: 2394 info->so_timestamping = 2395 SOF_TIMESTAMPING_TX_SOFTWARE | 2396 SOF_TIMESTAMPING_RX_SOFTWARE | 2397 SOF_TIMESTAMPING_SOFTWARE; 2398 return 0; 2399 case e1000_82576: 2400 case e1000_82580: 2401 case e1000_i350: 2402 case e1000_i354: 2403 case e1000_i210: 2404 case e1000_i211: 2405 info->so_timestamping = 2406 SOF_TIMESTAMPING_TX_SOFTWARE | 2407 SOF_TIMESTAMPING_RX_SOFTWARE | 2408 SOF_TIMESTAMPING_SOFTWARE | 2409 SOF_TIMESTAMPING_TX_HARDWARE | 2410 SOF_TIMESTAMPING_RX_HARDWARE | 2411 SOF_TIMESTAMPING_RAW_HARDWARE; 2412 2413 info->tx_types = 2414 BIT(HWTSTAMP_TX_OFF) | 2415 BIT(HWTSTAMP_TX_ON); 2416 2417 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2418 2419 /* 82576 does not support timestamping all packets. */ 2420 if (adapter->hw.mac.type >= e1000_82580) 2421 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2422 else 2423 info->rx_filters |= 2424 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2425 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2426 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2427 2428 return 0; 2429 default: 2430 return -EOPNOTSUPP; 2431 } 2432 } 2433 2434 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2435 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2436 struct ethtool_rxnfc *cmd) 2437 { 2438 struct ethtool_rx_flow_spec *fsp = &cmd->fs; 2439 struct igb_nfc_filter *rule = NULL; 2440 2441 /* report total rule count */ 2442 cmd->data = IGB_MAX_RXNFC_FILTERS; 2443 2444 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2445 if (fsp->location <= rule->sw_idx) 2446 break; 2447 } 2448 2449 if (!rule || fsp->location != rule->sw_idx) 2450 return -EINVAL; 2451 2452 if (rule->filter.match_flags) { 2453 fsp->flow_type = ETHER_FLOW; 2454 fsp->ring_cookie = rule->action; 2455 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2456 fsp->h_u.ether_spec.h_proto = rule->filter.etype; 2457 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; 2458 } 2459 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) { 2460 fsp->flow_type |= FLOW_EXT; 2461 fsp->h_ext.vlan_tci = rule->filter.vlan_tci; 2462 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK); 2463 } 2464 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2465 ether_addr_copy(fsp->h_u.ether_spec.h_dest, 2466 rule->filter.dst_addr); 2467 /* As we only support matching by the full 2468 * mask, return the mask to userspace 2469 */ 2470 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest); 2471 } 2472 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2473 ether_addr_copy(fsp->h_u.ether_spec.h_source, 2474 rule->filter.src_addr); 2475 /* As we only support matching by the full 2476 * mask, return the mask to userspace 2477 */ 2478 eth_broadcast_addr(fsp->m_u.ether_spec.h_source); 2479 } 2480 2481 return 0; 2482 } 2483 return -EINVAL; 2484 } 2485 2486 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter, 2487 struct ethtool_rxnfc *cmd, 2488 u32 *rule_locs) 2489 { 2490 struct igb_nfc_filter *rule; 2491 int cnt = 0; 2492 2493 /* report total rule count */ 2494 cmd->data = IGB_MAX_RXNFC_FILTERS; 2495 2496 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2497 if (cnt == cmd->rule_cnt) 2498 return -EMSGSIZE; 2499 rule_locs[cnt] = rule->sw_idx; 2500 cnt++; 2501 } 2502 2503 cmd->rule_cnt = cnt; 2504 2505 return 0; 2506 } 2507 2508 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2509 struct ethtool_rxnfc *cmd) 2510 { 2511 cmd->data = 0; 2512 2513 /* Report default options for RSS on igb */ 2514 switch (cmd->flow_type) { 2515 case TCP_V4_FLOW: 2516 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2517 fallthrough; 2518 case UDP_V4_FLOW: 2519 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2520 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2521 fallthrough; 2522 case SCTP_V4_FLOW: 2523 case AH_ESP_V4_FLOW: 2524 case AH_V4_FLOW: 2525 case ESP_V4_FLOW: 2526 case IPV4_FLOW: 2527 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2528 break; 2529 case TCP_V6_FLOW: 2530 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2531 fallthrough; 2532 case UDP_V6_FLOW: 2533 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2534 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2535 fallthrough; 2536 case SCTP_V6_FLOW: 2537 case AH_ESP_V6_FLOW: 2538 case AH_V6_FLOW: 2539 case ESP_V6_FLOW: 2540 case IPV6_FLOW: 2541 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2542 break; 2543 default: 2544 return -EINVAL; 2545 } 2546 2547 return 0; 2548 } 2549 2550 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2551 u32 *rule_locs) 2552 { 2553 struct igb_adapter *adapter = netdev_priv(dev); 2554 int ret = -EOPNOTSUPP; 2555 2556 switch (cmd->cmd) { 2557 case ETHTOOL_GRXRINGS: 2558 cmd->data = adapter->num_rx_queues; 2559 ret = 0; 2560 break; 2561 case ETHTOOL_GRXCLSRLCNT: 2562 cmd->rule_cnt = adapter->nfc_filter_count; 2563 ret = 0; 2564 break; 2565 case ETHTOOL_GRXCLSRULE: 2566 ret = igb_get_ethtool_nfc_entry(adapter, cmd); 2567 break; 2568 case ETHTOOL_GRXCLSRLALL: 2569 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs); 2570 break; 2571 case ETHTOOL_GRXFH: 2572 ret = igb_get_rss_hash_opts(adapter, cmd); 2573 break; 2574 default: 2575 break; 2576 } 2577 2578 return ret; 2579 } 2580 2581 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2582 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2583 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2584 struct ethtool_rxnfc *nfc) 2585 { 2586 u32 flags = adapter->flags; 2587 2588 /* RSS does not support anything other than hashing 2589 * to queues on src and dst IPs and ports 2590 */ 2591 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2592 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2593 return -EINVAL; 2594 2595 switch (nfc->flow_type) { 2596 case TCP_V4_FLOW: 2597 case TCP_V6_FLOW: 2598 if (!(nfc->data & RXH_IP_SRC) || 2599 !(nfc->data & RXH_IP_DST) || 2600 !(nfc->data & RXH_L4_B_0_1) || 2601 !(nfc->data & RXH_L4_B_2_3)) 2602 return -EINVAL; 2603 break; 2604 case UDP_V4_FLOW: 2605 if (!(nfc->data & RXH_IP_SRC) || 2606 !(nfc->data & RXH_IP_DST)) 2607 return -EINVAL; 2608 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2609 case 0: 2610 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2611 break; 2612 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2613 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2614 break; 2615 default: 2616 return -EINVAL; 2617 } 2618 break; 2619 case UDP_V6_FLOW: 2620 if (!(nfc->data & RXH_IP_SRC) || 2621 !(nfc->data & RXH_IP_DST)) 2622 return -EINVAL; 2623 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2624 case 0: 2625 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2626 break; 2627 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2628 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2629 break; 2630 default: 2631 return -EINVAL; 2632 } 2633 break; 2634 case AH_ESP_V4_FLOW: 2635 case AH_V4_FLOW: 2636 case ESP_V4_FLOW: 2637 case SCTP_V4_FLOW: 2638 case AH_ESP_V6_FLOW: 2639 case AH_V6_FLOW: 2640 case ESP_V6_FLOW: 2641 case SCTP_V6_FLOW: 2642 if (!(nfc->data & RXH_IP_SRC) || 2643 !(nfc->data & RXH_IP_DST) || 2644 (nfc->data & RXH_L4_B_0_1) || 2645 (nfc->data & RXH_L4_B_2_3)) 2646 return -EINVAL; 2647 break; 2648 default: 2649 return -EINVAL; 2650 } 2651 2652 /* if we changed something we need to update flags */ 2653 if (flags != adapter->flags) { 2654 struct e1000_hw *hw = &adapter->hw; 2655 u32 mrqc = rd32(E1000_MRQC); 2656 2657 if ((flags & UDP_RSS_FLAGS) && 2658 !(adapter->flags & UDP_RSS_FLAGS)) 2659 dev_err(&adapter->pdev->dev, 2660 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2661 2662 adapter->flags = flags; 2663 2664 /* Perform hash on these packet types */ 2665 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2666 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2667 E1000_MRQC_RSS_FIELD_IPV6 | 2668 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2669 2670 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2671 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2672 2673 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2674 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2675 2676 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2677 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2678 2679 wr32(E1000_MRQC, mrqc); 2680 } 2681 2682 return 0; 2683 } 2684 2685 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter, 2686 struct igb_nfc_filter *input) 2687 { 2688 struct e1000_hw *hw = &adapter->hw; 2689 u8 i; 2690 u32 etqf; 2691 u16 etype; 2692 2693 /* find an empty etype filter register */ 2694 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { 2695 if (!adapter->etype_bitmap[i]) 2696 break; 2697 } 2698 if (i == MAX_ETYPE_FILTER) { 2699 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n"); 2700 return -EINVAL; 2701 } 2702 2703 adapter->etype_bitmap[i] = true; 2704 2705 etqf = rd32(E1000_ETQF(i)); 2706 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK); 2707 2708 etqf |= E1000_ETQF_FILTER_ENABLE; 2709 etqf &= ~E1000_ETQF_ETYPE_MASK; 2710 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2711 2712 etqf &= ~E1000_ETQF_QUEUE_MASK; 2713 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2714 & E1000_ETQF_QUEUE_MASK); 2715 etqf |= E1000_ETQF_QUEUE_ENABLE; 2716 2717 wr32(E1000_ETQF(i), etqf); 2718 2719 input->etype_reg_index = i; 2720 2721 return 0; 2722 } 2723 2724 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter, 2725 struct igb_nfc_filter *input) 2726 { 2727 struct e1000_hw *hw = &adapter->hw; 2728 u8 vlan_priority; 2729 u16 queue_index; 2730 u32 vlapqf; 2731 2732 vlapqf = rd32(E1000_VLAPQF); 2733 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2734 >> VLAN_PRIO_SHIFT; 2735 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2736 2737 /* check whether this vlan prio is already set */ 2738 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) && 2739 (queue_index != input->action)) { 2740 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n"); 2741 return -EEXIST; 2742 } 2743 2744 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority); 2745 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action); 2746 2747 wr32(E1000_VLAPQF, vlapqf); 2748 2749 return 0; 2750 } 2751 2752 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2753 { 2754 struct e1000_hw *hw = &adapter->hw; 2755 int err = -EINVAL; 2756 2757 if (hw->mac.type == e1000_i210 && 2758 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) { 2759 dev_err(&adapter->pdev->dev, 2760 "i210 doesn't support flow classification rules specifying only source addresses.\n"); 2761 return -EOPNOTSUPP; 2762 } 2763 2764 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2765 err = igb_rxnfc_write_etype_filter(adapter, input); 2766 if (err) 2767 return err; 2768 } 2769 2770 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2771 err = igb_add_mac_steering_filter(adapter, 2772 input->filter.dst_addr, 2773 input->action, 0); 2774 err = min_t(int, err, 0); 2775 if (err) 2776 return err; 2777 } 2778 2779 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2780 err = igb_add_mac_steering_filter(adapter, 2781 input->filter.src_addr, 2782 input->action, 2783 IGB_MAC_STATE_SRC_ADDR); 2784 err = min_t(int, err, 0); 2785 if (err) 2786 return err; 2787 } 2788 2789 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2790 err = igb_rxnfc_write_vlan_prio_filter(adapter, input); 2791 2792 return err; 2793 } 2794 2795 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter, 2796 u16 reg_index) 2797 { 2798 struct e1000_hw *hw = &adapter->hw; 2799 u32 etqf = rd32(E1000_ETQF(reg_index)); 2800 2801 etqf &= ~E1000_ETQF_QUEUE_ENABLE; 2802 etqf &= ~E1000_ETQF_QUEUE_MASK; 2803 etqf &= ~E1000_ETQF_FILTER_ENABLE; 2804 2805 wr32(E1000_ETQF(reg_index), etqf); 2806 2807 adapter->etype_bitmap[reg_index] = false; 2808 } 2809 2810 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter, 2811 u16 vlan_tci) 2812 { 2813 struct e1000_hw *hw = &adapter->hw; 2814 u8 vlan_priority; 2815 u32 vlapqf; 2816 2817 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2818 2819 vlapqf = rd32(E1000_VLAPQF); 2820 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority); 2821 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority, 2822 E1000_VLAPQF_QUEUE_MASK); 2823 2824 wr32(E1000_VLAPQF, vlapqf); 2825 } 2826 2827 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2828 { 2829 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) 2830 igb_clear_etype_filter_regs(adapter, 2831 input->etype_reg_index); 2832 2833 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2834 igb_clear_vlan_prio_filter(adapter, 2835 ntohs(input->filter.vlan_tci)); 2836 2837 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) 2838 igb_del_mac_steering_filter(adapter, input->filter.src_addr, 2839 input->action, 2840 IGB_MAC_STATE_SRC_ADDR); 2841 2842 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) 2843 igb_del_mac_steering_filter(adapter, input->filter.dst_addr, 2844 input->action, 0); 2845 2846 return 0; 2847 } 2848 2849 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter, 2850 struct igb_nfc_filter *input, 2851 u16 sw_idx) 2852 { 2853 struct igb_nfc_filter *rule, *parent; 2854 int err = -EINVAL; 2855 2856 parent = NULL; 2857 rule = NULL; 2858 2859 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2860 /* hash found, or no matching entry */ 2861 if (rule->sw_idx >= sw_idx) 2862 break; 2863 parent = rule; 2864 } 2865 2866 /* if there is an old rule occupying our place remove it */ 2867 if (rule && (rule->sw_idx == sw_idx)) { 2868 if (!input) 2869 err = igb_erase_filter(adapter, rule); 2870 2871 hlist_del(&rule->nfc_node); 2872 kfree(rule); 2873 adapter->nfc_filter_count--; 2874 } 2875 2876 /* If no input this was a delete, err should be 0 if a rule was 2877 * successfully found and removed from the list else -EINVAL 2878 */ 2879 if (!input) 2880 return err; 2881 2882 /* initialize node */ 2883 INIT_HLIST_NODE(&input->nfc_node); 2884 2885 /* add filter to the list */ 2886 if (parent) 2887 hlist_add_behind(&input->nfc_node, &parent->nfc_node); 2888 else 2889 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list); 2890 2891 /* update counts */ 2892 adapter->nfc_filter_count++; 2893 2894 return 0; 2895 } 2896 2897 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, 2898 struct ethtool_rxnfc *cmd) 2899 { 2900 struct net_device *netdev = adapter->netdev; 2901 struct ethtool_rx_flow_spec *fsp = 2902 (struct ethtool_rx_flow_spec *)&cmd->fs; 2903 struct igb_nfc_filter *input, *rule; 2904 int err = 0; 2905 2906 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 2907 return -EOPNOTSUPP; 2908 2909 /* Don't allow programming if the action is a queue greater than 2910 * the number of online Rx queues. 2911 */ 2912 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) || 2913 (fsp->ring_cookie >= adapter->num_rx_queues)) { 2914 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n"); 2915 return -EINVAL; 2916 } 2917 2918 /* Don't allow indexes to exist outside of available space */ 2919 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) { 2920 dev_err(&adapter->pdev->dev, "Location out of range\n"); 2921 return -EINVAL; 2922 } 2923 2924 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW) 2925 return -EINVAL; 2926 2927 input = kzalloc(sizeof(*input), GFP_KERNEL); 2928 if (!input) 2929 return -ENOMEM; 2930 2931 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) { 2932 input->filter.etype = fsp->h_u.ether_spec.h_proto; 2933 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE; 2934 } 2935 2936 /* Only support matching addresses by the full mask */ 2937 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) { 2938 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR; 2939 ether_addr_copy(input->filter.src_addr, 2940 fsp->h_u.ether_spec.h_source); 2941 } 2942 2943 /* Only support matching addresses by the full mask */ 2944 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) { 2945 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR; 2946 ether_addr_copy(input->filter.dst_addr, 2947 fsp->h_u.ether_spec.h_dest); 2948 } 2949 2950 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) { 2951 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) { 2952 err = -EINVAL; 2953 goto err_out; 2954 } 2955 input->filter.vlan_tci = fsp->h_ext.vlan_tci; 2956 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2957 } 2958 2959 input->action = fsp->ring_cookie; 2960 input->sw_idx = fsp->location; 2961 2962 spin_lock(&adapter->nfc_lock); 2963 2964 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2965 if (!memcmp(&input->filter, &rule->filter, 2966 sizeof(input->filter))) { 2967 err = -EEXIST; 2968 dev_err(&adapter->pdev->dev, 2969 "ethtool: this filter is already set\n"); 2970 goto err_out_w_lock; 2971 } 2972 } 2973 2974 err = igb_add_filter(adapter, input); 2975 if (err) 2976 goto err_out_w_lock; 2977 2978 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); 2979 2980 spin_unlock(&adapter->nfc_lock); 2981 return 0; 2982 2983 err_out_w_lock: 2984 spin_unlock(&adapter->nfc_lock); 2985 err_out: 2986 kfree(input); 2987 return err; 2988 } 2989 2990 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter, 2991 struct ethtool_rxnfc *cmd) 2992 { 2993 struct ethtool_rx_flow_spec *fsp = 2994 (struct ethtool_rx_flow_spec *)&cmd->fs; 2995 int err; 2996 2997 spin_lock(&adapter->nfc_lock); 2998 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location); 2999 spin_unlock(&adapter->nfc_lock); 3000 3001 return err; 3002 } 3003 3004 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3005 { 3006 struct igb_adapter *adapter = netdev_priv(dev); 3007 int ret = -EOPNOTSUPP; 3008 3009 switch (cmd->cmd) { 3010 case ETHTOOL_SRXFH: 3011 ret = igb_set_rss_hash_opt(adapter, cmd); 3012 break; 3013 case ETHTOOL_SRXCLSRLINS: 3014 ret = igb_add_ethtool_nfc_entry(adapter, cmd); 3015 break; 3016 case ETHTOOL_SRXCLSRLDEL: 3017 ret = igb_del_ethtool_nfc_entry(adapter, cmd); 3018 break; 3019 default: 3020 break; 3021 } 3022 3023 return ret; 3024 } 3025 3026 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3027 { 3028 struct igb_adapter *adapter = netdev_priv(netdev); 3029 struct e1000_hw *hw = &adapter->hw; 3030 u32 ret_val; 3031 u16 phy_data; 3032 3033 if ((hw->mac.type < e1000_i350) || 3034 (hw->phy.media_type != e1000_media_type_copper)) 3035 return -EOPNOTSUPP; 3036 3037 edata->supported = (SUPPORTED_1000baseT_Full | 3038 SUPPORTED_100baseT_Full); 3039 if (!hw->dev_spec._82575.eee_disable) 3040 edata->advertised = 3041 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 3042 3043 /* The IPCNFG and EEER registers are not supported on I354. */ 3044 if (hw->mac.type == e1000_i354) { 3045 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 3046 } else { 3047 u32 eeer; 3048 3049 eeer = rd32(E1000_EEER); 3050 3051 /* EEE status on negotiated link */ 3052 if (eeer & E1000_EEER_EEE_NEG) 3053 edata->eee_active = true; 3054 3055 if (eeer & E1000_EEER_TX_LPI_EN) 3056 edata->tx_lpi_enabled = true; 3057 } 3058 3059 /* EEE Link Partner Advertised */ 3060 switch (hw->mac.type) { 3061 case e1000_i350: 3062 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 3063 &phy_data); 3064 if (ret_val) 3065 return -ENODATA; 3066 3067 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3068 break; 3069 case e1000_i354: 3070 case e1000_i210: 3071 case e1000_i211: 3072 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 3073 E1000_EEE_LP_ADV_DEV_I210, 3074 &phy_data); 3075 if (ret_val) 3076 return -ENODATA; 3077 3078 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3079 3080 break; 3081 default: 3082 break; 3083 } 3084 3085 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 3086 3087 if ((hw->mac.type == e1000_i354) && 3088 (edata->eee_enabled)) 3089 edata->tx_lpi_enabled = true; 3090 3091 /* Report correct negotiated EEE status for devices that 3092 * wrongly report EEE at half-duplex 3093 */ 3094 if (adapter->link_duplex == HALF_DUPLEX) { 3095 edata->eee_enabled = false; 3096 edata->eee_active = false; 3097 edata->tx_lpi_enabled = false; 3098 edata->advertised &= ~edata->advertised; 3099 } 3100 3101 return 0; 3102 } 3103 3104 static int igb_set_eee(struct net_device *netdev, 3105 struct ethtool_eee *edata) 3106 { 3107 struct igb_adapter *adapter = netdev_priv(netdev); 3108 struct e1000_hw *hw = &adapter->hw; 3109 struct ethtool_eee eee_curr; 3110 bool adv1g_eee = true, adv100m_eee = true; 3111 s32 ret_val; 3112 3113 if ((hw->mac.type < e1000_i350) || 3114 (hw->phy.media_type != e1000_media_type_copper)) 3115 return -EOPNOTSUPP; 3116 3117 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 3118 3119 ret_val = igb_get_eee(netdev, &eee_curr); 3120 if (ret_val) 3121 return ret_val; 3122 3123 if (eee_curr.eee_enabled) { 3124 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 3125 dev_err(&adapter->pdev->dev, 3126 "Setting EEE tx-lpi is not supported\n"); 3127 return -EINVAL; 3128 } 3129 3130 /* Tx LPI timer is not implemented currently */ 3131 if (edata->tx_lpi_timer) { 3132 dev_err(&adapter->pdev->dev, 3133 "Setting EEE Tx LPI timer is not supported\n"); 3134 return -EINVAL; 3135 } 3136 3137 if (!edata->advertised || (edata->advertised & 3138 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 3139 dev_err(&adapter->pdev->dev, 3140 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 3141 return -EINVAL; 3142 } 3143 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 3144 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 3145 3146 } else if (!edata->eee_enabled) { 3147 dev_err(&adapter->pdev->dev, 3148 "Setting EEE options are not supported with EEE disabled\n"); 3149 return -EINVAL; 3150 } 3151 3152 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 3153 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 3154 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 3155 adapter->flags |= IGB_FLAG_EEE; 3156 3157 /* reset link */ 3158 if (netif_running(netdev)) 3159 igb_reinit_locked(adapter); 3160 else 3161 igb_reset(adapter); 3162 } 3163 3164 if (hw->mac.type == e1000_i354) 3165 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 3166 else 3167 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 3168 3169 if (ret_val) { 3170 dev_err(&adapter->pdev->dev, 3171 "Problem setting EEE advertisement options\n"); 3172 return -EINVAL; 3173 } 3174 3175 return 0; 3176 } 3177 3178 static int igb_get_module_info(struct net_device *netdev, 3179 struct ethtool_modinfo *modinfo) 3180 { 3181 struct igb_adapter *adapter = netdev_priv(netdev); 3182 struct e1000_hw *hw = &adapter->hw; 3183 u32 status = 0; 3184 u16 sff8472_rev, addr_mode; 3185 bool page_swap = false; 3186 3187 if ((hw->phy.media_type == e1000_media_type_copper) || 3188 (hw->phy.media_type == e1000_media_type_unknown)) 3189 return -EOPNOTSUPP; 3190 3191 /* Check whether we support SFF-8472 or not */ 3192 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 3193 if (status) 3194 return -EIO; 3195 3196 /* addressing mode is not supported */ 3197 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 3198 if (status) 3199 return -EIO; 3200 3201 /* addressing mode is not supported */ 3202 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 3203 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3204 page_swap = true; 3205 } 3206 3207 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 3208 /* We have an SFP, but it does not support SFF-8472 */ 3209 modinfo->type = ETH_MODULE_SFF_8079; 3210 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3211 } else { 3212 /* We have an SFP which supports a revision of SFF-8472 */ 3213 modinfo->type = ETH_MODULE_SFF_8472; 3214 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3215 } 3216 3217 return 0; 3218 } 3219 3220 static int igb_get_module_eeprom(struct net_device *netdev, 3221 struct ethtool_eeprom *ee, u8 *data) 3222 { 3223 struct igb_adapter *adapter = netdev_priv(netdev); 3224 struct e1000_hw *hw = &adapter->hw; 3225 u32 status = 0; 3226 u16 *dataword; 3227 u16 first_word, last_word; 3228 int i = 0; 3229 3230 if (ee->len == 0) 3231 return -EINVAL; 3232 3233 first_word = ee->offset >> 1; 3234 last_word = (ee->offset + ee->len - 1) >> 1; 3235 3236 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16), 3237 GFP_KERNEL); 3238 if (!dataword) 3239 return -ENOMEM; 3240 3241 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 3242 for (i = 0; i < last_word - first_word + 1; i++) { 3243 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 3244 &dataword[i]); 3245 if (status) { 3246 /* Error occurred while reading module */ 3247 kfree(dataword); 3248 return -EIO; 3249 } 3250 3251 be16_to_cpus(&dataword[i]); 3252 } 3253 3254 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 3255 kfree(dataword); 3256 3257 return 0; 3258 } 3259 3260 static int igb_ethtool_begin(struct net_device *netdev) 3261 { 3262 struct igb_adapter *adapter = netdev_priv(netdev); 3263 pm_runtime_get_sync(&adapter->pdev->dev); 3264 return 0; 3265 } 3266 3267 static void igb_ethtool_complete(struct net_device *netdev) 3268 { 3269 struct igb_adapter *adapter = netdev_priv(netdev); 3270 pm_runtime_put(&adapter->pdev->dev); 3271 } 3272 3273 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 3274 { 3275 return IGB_RETA_SIZE; 3276 } 3277 3278 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3279 u8 *hfunc) 3280 { 3281 struct igb_adapter *adapter = netdev_priv(netdev); 3282 int i; 3283 3284 if (hfunc) 3285 *hfunc = ETH_RSS_HASH_TOP; 3286 if (!indir) 3287 return 0; 3288 for (i = 0; i < IGB_RETA_SIZE; i++) 3289 indir[i] = adapter->rss_indir_tbl[i]; 3290 3291 return 0; 3292 } 3293 3294 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 3295 { 3296 struct e1000_hw *hw = &adapter->hw; 3297 u32 reg = E1000_RETA(0); 3298 u32 shift = 0; 3299 int i = 0; 3300 3301 switch (hw->mac.type) { 3302 case e1000_82575: 3303 shift = 6; 3304 break; 3305 case e1000_82576: 3306 /* 82576 supports 2 RSS queues for SR-IOV */ 3307 if (adapter->vfs_allocated_count) 3308 shift = 3; 3309 break; 3310 default: 3311 break; 3312 } 3313 3314 while (i < IGB_RETA_SIZE) { 3315 u32 val = 0; 3316 int j; 3317 3318 for (j = 3; j >= 0; j--) { 3319 val <<= 8; 3320 val |= adapter->rss_indir_tbl[i + j]; 3321 } 3322 3323 wr32(reg, val << shift); 3324 reg += 4; 3325 i += 4; 3326 } 3327 } 3328 3329 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 3330 const u8 *key, const u8 hfunc) 3331 { 3332 struct igb_adapter *adapter = netdev_priv(netdev); 3333 struct e1000_hw *hw = &adapter->hw; 3334 int i; 3335 u32 num_queues; 3336 3337 /* We do not allow change in unsupported parameters */ 3338 if (key || 3339 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3340 return -EOPNOTSUPP; 3341 if (!indir) 3342 return 0; 3343 3344 num_queues = adapter->rss_queues; 3345 3346 switch (hw->mac.type) { 3347 case e1000_82576: 3348 /* 82576 supports 2 RSS queues for SR-IOV */ 3349 if (adapter->vfs_allocated_count) 3350 num_queues = 2; 3351 break; 3352 default: 3353 break; 3354 } 3355 3356 /* Verify user input. */ 3357 for (i = 0; i < IGB_RETA_SIZE; i++) 3358 if (indir[i] >= num_queues) 3359 return -EINVAL; 3360 3361 3362 for (i = 0; i < IGB_RETA_SIZE; i++) 3363 adapter->rss_indir_tbl[i] = indir[i]; 3364 3365 igb_write_rss_indir_tbl(adapter); 3366 3367 return 0; 3368 } 3369 3370 static unsigned int igb_max_channels(struct igb_adapter *adapter) 3371 { 3372 return igb_get_max_rss_queues(adapter); 3373 } 3374 3375 static void igb_get_channels(struct net_device *netdev, 3376 struct ethtool_channels *ch) 3377 { 3378 struct igb_adapter *adapter = netdev_priv(netdev); 3379 3380 /* Report maximum channels */ 3381 ch->max_combined = igb_max_channels(adapter); 3382 3383 /* Report info for other vector */ 3384 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3385 ch->max_other = NON_Q_VECTORS; 3386 ch->other_count = NON_Q_VECTORS; 3387 } 3388 3389 ch->combined_count = adapter->rss_queues; 3390 } 3391 3392 static int igb_set_channels(struct net_device *netdev, 3393 struct ethtool_channels *ch) 3394 { 3395 struct igb_adapter *adapter = netdev_priv(netdev); 3396 unsigned int count = ch->combined_count; 3397 unsigned int max_combined = 0; 3398 3399 /* Verify they are not requesting separate vectors */ 3400 if (!count || ch->rx_count || ch->tx_count) 3401 return -EINVAL; 3402 3403 /* Verify other_count is valid and has not been changed */ 3404 if (ch->other_count != NON_Q_VECTORS) 3405 return -EINVAL; 3406 3407 /* Verify the number of channels doesn't exceed hw limits */ 3408 max_combined = igb_max_channels(adapter); 3409 if (count > max_combined) 3410 return -EINVAL; 3411 3412 if (count != adapter->rss_queues) { 3413 adapter->rss_queues = count; 3414 igb_set_flag_queue_pairs(adapter, max_combined); 3415 3416 /* Hardware has to reinitialize queues and interrupts to 3417 * match the new configuration. 3418 */ 3419 return igb_reinit_queues(adapter); 3420 } 3421 3422 return 0; 3423 } 3424 3425 static u32 igb_get_priv_flags(struct net_device *netdev) 3426 { 3427 struct igb_adapter *adapter = netdev_priv(netdev); 3428 u32 priv_flags = 0; 3429 3430 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3431 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX; 3432 3433 return priv_flags; 3434 } 3435 3436 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3437 { 3438 struct igb_adapter *adapter = netdev_priv(netdev); 3439 unsigned int flags = adapter->flags; 3440 3441 flags &= ~IGB_FLAG_RX_LEGACY; 3442 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX) 3443 flags |= IGB_FLAG_RX_LEGACY; 3444 3445 if (flags != adapter->flags) { 3446 adapter->flags = flags; 3447 3448 /* reset interface to repopulate queues */ 3449 if (netif_running(netdev)) 3450 igb_reinit_locked(adapter); 3451 } 3452 3453 return 0; 3454 } 3455 3456 static const struct ethtool_ops igb_ethtool_ops = { 3457 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3458 .get_drvinfo = igb_get_drvinfo, 3459 .get_regs_len = igb_get_regs_len, 3460 .get_regs = igb_get_regs, 3461 .get_wol = igb_get_wol, 3462 .set_wol = igb_set_wol, 3463 .get_msglevel = igb_get_msglevel, 3464 .set_msglevel = igb_set_msglevel, 3465 .nway_reset = igb_nway_reset, 3466 .get_link = igb_get_link, 3467 .get_eeprom_len = igb_get_eeprom_len, 3468 .get_eeprom = igb_get_eeprom, 3469 .set_eeprom = igb_set_eeprom, 3470 .get_ringparam = igb_get_ringparam, 3471 .set_ringparam = igb_set_ringparam, 3472 .get_pauseparam = igb_get_pauseparam, 3473 .set_pauseparam = igb_set_pauseparam, 3474 .self_test = igb_diag_test, 3475 .get_strings = igb_get_strings, 3476 .set_phys_id = igb_set_phys_id, 3477 .get_sset_count = igb_get_sset_count, 3478 .get_ethtool_stats = igb_get_ethtool_stats, 3479 .get_coalesce = igb_get_coalesce, 3480 .set_coalesce = igb_set_coalesce, 3481 .get_ts_info = igb_get_ts_info, 3482 .get_rxnfc = igb_get_rxnfc, 3483 .set_rxnfc = igb_set_rxnfc, 3484 .get_eee = igb_get_eee, 3485 .set_eee = igb_set_eee, 3486 .get_module_info = igb_get_module_info, 3487 .get_module_eeprom = igb_get_module_eeprom, 3488 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3489 .get_rxfh = igb_get_rxfh, 3490 .set_rxfh = igb_set_rxfh, 3491 .get_channels = igb_get_channels, 3492 .set_channels = igb_set_channels, 3493 .get_priv_flags = igb_get_priv_flags, 3494 .set_priv_flags = igb_set_priv_flags, 3495 .begin = igb_ethtool_begin, 3496 .complete = igb_ethtool_complete, 3497 .get_link_ksettings = igb_get_link_ksettings, 3498 .set_link_ksettings = igb_set_link_ksettings, 3499 }; 3500 3501 void igb_set_ethtool_ops(struct net_device *netdev) 3502 { 3503 netdev->ethtool_ops = &igb_ethtool_ops; 3504 } 3505