1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* ethtool support for igb */ 5 6 #include <linux/vmalloc.h> 7 #include <linux/netdevice.h> 8 #include <linux/pci.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/if_ether.h> 12 #include <linux/ethtool.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/highmem.h> 17 #include <linux/mdio.h> 18 19 #include "igb.h" 20 21 struct igb_stats { 22 char stat_string[ETH_GSTRING_LEN]; 23 int sizeof_stat; 24 int stat_offset; 25 }; 26 27 #define IGB_STAT(_name, _stat) { \ 28 .stat_string = _name, \ 29 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 30 .stat_offset = offsetof(struct igb_adapter, _stat) \ 31 } 32 static const struct igb_stats igb_gstrings_stats[] = { 33 IGB_STAT("rx_packets", stats.gprc), 34 IGB_STAT("tx_packets", stats.gptc), 35 IGB_STAT("rx_bytes", stats.gorc), 36 IGB_STAT("tx_bytes", stats.gotc), 37 IGB_STAT("rx_broadcast", stats.bprc), 38 IGB_STAT("tx_broadcast", stats.bptc), 39 IGB_STAT("rx_multicast", stats.mprc), 40 IGB_STAT("tx_multicast", stats.mptc), 41 IGB_STAT("multicast", stats.mprc), 42 IGB_STAT("collisions", stats.colc), 43 IGB_STAT("rx_crc_errors", stats.crcerrs), 44 IGB_STAT("rx_no_buffer_count", stats.rnbc), 45 IGB_STAT("rx_missed_errors", stats.mpc), 46 IGB_STAT("tx_aborted_errors", stats.ecol), 47 IGB_STAT("tx_carrier_errors", stats.tncrs), 48 IGB_STAT("tx_window_errors", stats.latecol), 49 IGB_STAT("tx_abort_late_coll", stats.latecol), 50 IGB_STAT("tx_deferred_ok", stats.dc), 51 IGB_STAT("tx_single_coll_ok", stats.scc), 52 IGB_STAT("tx_multi_coll_ok", stats.mcc), 53 IGB_STAT("tx_timeout_count", tx_timeout_count), 54 IGB_STAT("rx_long_length_errors", stats.roc), 55 IGB_STAT("rx_short_length_errors", stats.ruc), 56 IGB_STAT("rx_align_errors", stats.algnerrc), 57 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 59 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 61 IGB_STAT("tx_flow_control_xon", stats.xontxc), 62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 63 IGB_STAT("rx_long_byte_count", stats.gorc), 64 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 65 IGB_STAT("tx_smbus", stats.mgptc), 66 IGB_STAT("rx_smbus", stats.mgprc), 67 IGB_STAT("dropped_smbus", stats.mgpdc), 68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped), 74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 75 }; 76 77 #define IGB_NETDEV_STAT(_net_stat) { \ 78 .stat_string = __stringify(_net_stat), \ 79 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 81 } 82 static const struct igb_stats igb_gstrings_net_stats[] = { 83 IGB_NETDEV_STAT(rx_errors), 84 IGB_NETDEV_STAT(tx_errors), 85 IGB_NETDEV_STAT(tx_dropped), 86 IGB_NETDEV_STAT(rx_length_errors), 87 IGB_NETDEV_STAT(rx_over_errors), 88 IGB_NETDEV_STAT(rx_frame_errors), 89 IGB_NETDEV_STAT(rx_fifo_errors), 90 IGB_NETDEV_STAT(tx_fifo_errors), 91 IGB_NETDEV_STAT(tx_heartbeat_errors) 92 }; 93 94 #define IGB_GLOBAL_STATS_LEN \ 95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 96 #define IGB_NETDEV_STATS_LEN \ 97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 98 #define IGB_RX_QUEUE_STATS_LEN \ 99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 100 101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 102 103 #define IGB_QUEUE_STATS_LEN \ 104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 105 IGB_RX_QUEUE_STATS_LEN) + \ 106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 107 IGB_TX_QUEUE_STATS_LEN)) 108 #define IGB_STATS_LEN \ 109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 110 111 enum igb_diagnostics_results { 112 TEST_REG = 0, 113 TEST_EEP, 114 TEST_IRQ, 115 TEST_LOOP, 116 TEST_LINK 117 }; 118 119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 120 [TEST_REG] = "Register test (offline)", 121 [TEST_EEP] = "Eeprom test (offline)", 122 [TEST_IRQ] = "Interrupt test (offline)", 123 [TEST_LOOP] = "Loopback test (offline)", 124 [TEST_LINK] = "Link test (on/offline)" 125 }; 126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 127 128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = { 129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) 130 "legacy-rx", 131 }; 132 133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings) 134 135 static int igb_get_link_ksettings(struct net_device *netdev, 136 struct ethtool_link_ksettings *cmd) 137 { 138 struct igb_adapter *adapter = netdev_priv(netdev); 139 struct e1000_hw *hw = &adapter->hw; 140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 142 u32 status; 143 u32 speed; 144 u32 supported, advertising; 145 146 status = rd32(E1000_STATUS); 147 if (hw->phy.media_type == e1000_media_type_copper) { 148 149 supported = (SUPPORTED_10baseT_Half | 150 SUPPORTED_10baseT_Full | 151 SUPPORTED_100baseT_Half | 152 SUPPORTED_100baseT_Full | 153 SUPPORTED_1000baseT_Full| 154 SUPPORTED_Autoneg | 155 SUPPORTED_TP | 156 SUPPORTED_Pause); 157 advertising = ADVERTISED_TP; 158 159 if (hw->mac.autoneg == 1) { 160 advertising |= ADVERTISED_Autoneg; 161 /* the e1000 autoneg seems to match ethtool nicely */ 162 advertising |= hw->phy.autoneg_advertised; 163 } 164 165 cmd->base.port = PORT_TP; 166 cmd->base.phy_address = hw->phy.addr; 167 } else { 168 supported = (SUPPORTED_FIBRE | 169 SUPPORTED_1000baseKX_Full | 170 SUPPORTED_Autoneg | 171 SUPPORTED_Pause); 172 advertising = (ADVERTISED_FIBRE | 173 ADVERTISED_1000baseKX_Full); 174 if (hw->mac.type == e1000_i354) { 175 if ((hw->device_id == 176 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 177 !(status & E1000_STATUS_2P5_SKU_OVER)) { 178 supported |= SUPPORTED_2500baseX_Full; 179 supported &= ~SUPPORTED_1000baseKX_Full; 180 advertising |= ADVERTISED_2500baseX_Full; 181 advertising &= ~ADVERTISED_1000baseKX_Full; 182 } 183 } 184 if (eth_flags->e100_base_fx) { 185 supported |= SUPPORTED_100baseT_Full; 186 advertising |= ADVERTISED_100baseT_Full; 187 } 188 if (hw->mac.autoneg == 1) 189 advertising |= ADVERTISED_Autoneg; 190 191 cmd->base.port = PORT_FIBRE; 192 } 193 if (hw->mac.autoneg != 1) 194 advertising &= ~(ADVERTISED_Pause | 195 ADVERTISED_Asym_Pause); 196 197 switch (hw->fc.requested_mode) { 198 case e1000_fc_full: 199 advertising |= ADVERTISED_Pause; 200 break; 201 case e1000_fc_rx_pause: 202 advertising |= (ADVERTISED_Pause | 203 ADVERTISED_Asym_Pause); 204 break; 205 case e1000_fc_tx_pause: 206 advertising |= ADVERTISED_Asym_Pause; 207 break; 208 default: 209 advertising &= ~(ADVERTISED_Pause | 210 ADVERTISED_Asym_Pause); 211 } 212 if (status & E1000_STATUS_LU) { 213 if ((status & E1000_STATUS_2P5_SKU) && 214 !(status & E1000_STATUS_2P5_SKU_OVER)) { 215 speed = SPEED_2500; 216 } else if (status & E1000_STATUS_SPEED_1000) { 217 speed = SPEED_1000; 218 } else if (status & E1000_STATUS_SPEED_100) { 219 speed = SPEED_100; 220 } else { 221 speed = SPEED_10; 222 } 223 if ((status & E1000_STATUS_FD) || 224 hw->phy.media_type != e1000_media_type_copper) 225 cmd->base.duplex = DUPLEX_FULL; 226 else 227 cmd->base.duplex = DUPLEX_HALF; 228 } else { 229 speed = SPEED_UNKNOWN; 230 cmd->base.duplex = DUPLEX_UNKNOWN; 231 } 232 cmd->base.speed = speed; 233 if ((hw->phy.media_type == e1000_media_type_fiber) || 234 hw->mac.autoneg) 235 cmd->base.autoneg = AUTONEG_ENABLE; 236 else 237 cmd->base.autoneg = AUTONEG_DISABLE; 238 239 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 240 if (hw->phy.media_type == e1000_media_type_copper) 241 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 242 ETH_TP_MDI; 243 else 244 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 245 246 if (hw->phy.mdix == AUTO_ALL_MODES) 247 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 248 else 249 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; 250 251 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 252 supported); 253 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 254 advertising); 255 256 return 0; 257 } 258 259 static int igb_set_link_ksettings(struct net_device *netdev, 260 const struct ethtool_link_ksettings *cmd) 261 { 262 struct igb_adapter *adapter = netdev_priv(netdev); 263 struct e1000_hw *hw = &adapter->hw; 264 u32 advertising; 265 266 /* When SoL/IDER sessions are active, autoneg/speed/duplex 267 * cannot be changed 268 */ 269 if (igb_check_reset_block(hw)) { 270 dev_err(&adapter->pdev->dev, 271 "Cannot change link characteristics when SoL/IDER is active.\n"); 272 return -EINVAL; 273 } 274 275 /* MDI setting is only allowed when autoneg enabled because 276 * some hardware doesn't allow MDI setting when speed or 277 * duplex is forced. 278 */ 279 if (cmd->base.eth_tp_mdix_ctrl) { 280 if (hw->phy.media_type != e1000_media_type_copper) 281 return -EOPNOTSUPP; 282 283 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 284 (cmd->base.autoneg != AUTONEG_ENABLE)) { 285 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 286 return -EINVAL; 287 } 288 } 289 290 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 291 usleep_range(1000, 2000); 292 293 ethtool_convert_link_mode_to_legacy_u32(&advertising, 294 cmd->link_modes.advertising); 295 296 if (cmd->base.autoneg == AUTONEG_ENABLE) { 297 hw->mac.autoneg = 1; 298 if (hw->phy.media_type == e1000_media_type_fiber) { 299 hw->phy.autoneg_advertised = advertising | 300 ADVERTISED_FIBRE | 301 ADVERTISED_Autoneg; 302 switch (adapter->link_speed) { 303 case SPEED_2500: 304 hw->phy.autoneg_advertised = 305 ADVERTISED_2500baseX_Full; 306 break; 307 case SPEED_1000: 308 hw->phy.autoneg_advertised = 309 ADVERTISED_1000baseT_Full; 310 break; 311 case SPEED_100: 312 hw->phy.autoneg_advertised = 313 ADVERTISED_100baseT_Full; 314 break; 315 default: 316 break; 317 } 318 } else { 319 hw->phy.autoneg_advertised = advertising | 320 ADVERTISED_TP | 321 ADVERTISED_Autoneg; 322 } 323 advertising = hw->phy.autoneg_advertised; 324 if (adapter->fc_autoneg) 325 hw->fc.requested_mode = e1000_fc_default; 326 } else { 327 u32 speed = cmd->base.speed; 328 /* calling this overrides forced MDI setting */ 329 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { 330 clear_bit(__IGB_RESETTING, &adapter->state); 331 return -EINVAL; 332 } 333 } 334 335 /* MDI-X => 2; MDI => 1; Auto => 3 */ 336 if (cmd->base.eth_tp_mdix_ctrl) { 337 /* fix up the value for auto (3 => 0) as zero is mapped 338 * internally to auto 339 */ 340 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 341 hw->phy.mdix = AUTO_ALL_MODES; 342 else 343 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; 344 } 345 346 /* reset the link */ 347 if (netif_running(adapter->netdev)) { 348 igb_down(adapter); 349 igb_up(adapter); 350 } else 351 igb_reset(adapter); 352 353 clear_bit(__IGB_RESETTING, &adapter->state); 354 return 0; 355 } 356 357 static u32 igb_get_link(struct net_device *netdev) 358 { 359 struct igb_adapter *adapter = netdev_priv(netdev); 360 struct e1000_mac_info *mac = &adapter->hw.mac; 361 362 /* If the link is not reported up to netdev, interrupts are disabled, 363 * and so the physical link state may have changed since we last 364 * looked. Set get_link_status to make sure that the true link 365 * state is interrogated, rather than pulling a cached and possibly 366 * stale link state from the driver. 367 */ 368 if (!netif_carrier_ok(netdev)) 369 mac->get_link_status = 1; 370 371 return igb_has_link(adapter); 372 } 373 374 static void igb_get_pauseparam(struct net_device *netdev, 375 struct ethtool_pauseparam *pause) 376 { 377 struct igb_adapter *adapter = netdev_priv(netdev); 378 struct e1000_hw *hw = &adapter->hw; 379 380 pause->autoneg = 381 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 382 383 if (hw->fc.current_mode == e1000_fc_rx_pause) 384 pause->rx_pause = 1; 385 else if (hw->fc.current_mode == e1000_fc_tx_pause) 386 pause->tx_pause = 1; 387 else if (hw->fc.current_mode == e1000_fc_full) { 388 pause->rx_pause = 1; 389 pause->tx_pause = 1; 390 } 391 } 392 393 static int igb_set_pauseparam(struct net_device *netdev, 394 struct ethtool_pauseparam *pause) 395 { 396 struct igb_adapter *adapter = netdev_priv(netdev); 397 struct e1000_hw *hw = &adapter->hw; 398 int retval = 0; 399 400 /* 100basefx does not support setting link flow control */ 401 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 402 return -EINVAL; 403 404 adapter->fc_autoneg = pause->autoneg; 405 406 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 407 usleep_range(1000, 2000); 408 409 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 410 hw->fc.requested_mode = e1000_fc_default; 411 if (netif_running(adapter->netdev)) { 412 igb_down(adapter); 413 igb_up(adapter); 414 } else { 415 igb_reset(adapter); 416 } 417 } else { 418 if (pause->rx_pause && pause->tx_pause) 419 hw->fc.requested_mode = e1000_fc_full; 420 else if (pause->rx_pause && !pause->tx_pause) 421 hw->fc.requested_mode = e1000_fc_rx_pause; 422 else if (!pause->rx_pause && pause->tx_pause) 423 hw->fc.requested_mode = e1000_fc_tx_pause; 424 else if (!pause->rx_pause && !pause->tx_pause) 425 hw->fc.requested_mode = e1000_fc_none; 426 427 hw->fc.current_mode = hw->fc.requested_mode; 428 429 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 430 igb_force_mac_fc(hw) : igb_setup_link(hw)); 431 } 432 433 clear_bit(__IGB_RESETTING, &adapter->state); 434 return retval; 435 } 436 437 static u32 igb_get_msglevel(struct net_device *netdev) 438 { 439 struct igb_adapter *adapter = netdev_priv(netdev); 440 return adapter->msg_enable; 441 } 442 443 static void igb_set_msglevel(struct net_device *netdev, u32 data) 444 { 445 struct igb_adapter *adapter = netdev_priv(netdev); 446 adapter->msg_enable = data; 447 } 448 449 static int igb_get_regs_len(struct net_device *netdev) 450 { 451 #define IGB_REGS_LEN 739 452 return IGB_REGS_LEN * sizeof(u32); 453 } 454 455 static void igb_get_regs(struct net_device *netdev, 456 struct ethtool_regs *regs, void *p) 457 { 458 struct igb_adapter *adapter = netdev_priv(netdev); 459 struct e1000_hw *hw = &adapter->hw; 460 u32 *regs_buff = p; 461 u8 i; 462 463 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 464 465 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 466 467 /* General Registers */ 468 regs_buff[0] = rd32(E1000_CTRL); 469 regs_buff[1] = rd32(E1000_STATUS); 470 regs_buff[2] = rd32(E1000_CTRL_EXT); 471 regs_buff[3] = rd32(E1000_MDIC); 472 regs_buff[4] = rd32(E1000_SCTL); 473 regs_buff[5] = rd32(E1000_CONNSW); 474 regs_buff[6] = rd32(E1000_VET); 475 regs_buff[7] = rd32(E1000_LEDCTL); 476 regs_buff[8] = rd32(E1000_PBA); 477 regs_buff[9] = rd32(E1000_PBS); 478 regs_buff[10] = rd32(E1000_FRTIMER); 479 regs_buff[11] = rd32(E1000_TCPTIMER); 480 481 /* NVM Register */ 482 regs_buff[12] = rd32(E1000_EECD); 483 484 /* Interrupt */ 485 /* Reading EICS for EICR because they read the 486 * same but EICS does not clear on read 487 */ 488 regs_buff[13] = rd32(E1000_EICS); 489 regs_buff[14] = rd32(E1000_EICS); 490 regs_buff[15] = rd32(E1000_EIMS); 491 regs_buff[16] = rd32(E1000_EIMC); 492 regs_buff[17] = rd32(E1000_EIAC); 493 regs_buff[18] = rd32(E1000_EIAM); 494 /* Reading ICS for ICR because they read the 495 * same but ICS does not clear on read 496 */ 497 regs_buff[19] = rd32(E1000_ICS); 498 regs_buff[20] = rd32(E1000_ICS); 499 regs_buff[21] = rd32(E1000_IMS); 500 regs_buff[22] = rd32(E1000_IMC); 501 regs_buff[23] = rd32(E1000_IAC); 502 regs_buff[24] = rd32(E1000_IAM); 503 regs_buff[25] = rd32(E1000_IMIRVP); 504 505 /* Flow Control */ 506 regs_buff[26] = rd32(E1000_FCAL); 507 regs_buff[27] = rd32(E1000_FCAH); 508 regs_buff[28] = rd32(E1000_FCTTV); 509 regs_buff[29] = rd32(E1000_FCRTL); 510 regs_buff[30] = rd32(E1000_FCRTH); 511 regs_buff[31] = rd32(E1000_FCRTV); 512 513 /* Receive */ 514 regs_buff[32] = rd32(E1000_RCTL); 515 regs_buff[33] = rd32(E1000_RXCSUM); 516 regs_buff[34] = rd32(E1000_RLPML); 517 regs_buff[35] = rd32(E1000_RFCTL); 518 regs_buff[36] = rd32(E1000_MRQC); 519 regs_buff[37] = rd32(E1000_VT_CTL); 520 521 /* Transmit */ 522 regs_buff[38] = rd32(E1000_TCTL); 523 regs_buff[39] = rd32(E1000_TCTL_EXT); 524 regs_buff[40] = rd32(E1000_TIPG); 525 regs_buff[41] = rd32(E1000_DTXCTL); 526 527 /* Wake Up */ 528 regs_buff[42] = rd32(E1000_WUC); 529 regs_buff[43] = rd32(E1000_WUFC); 530 regs_buff[44] = rd32(E1000_WUS); 531 regs_buff[45] = rd32(E1000_IPAV); 532 regs_buff[46] = rd32(E1000_WUPL); 533 534 /* MAC */ 535 regs_buff[47] = rd32(E1000_PCS_CFG0); 536 regs_buff[48] = rd32(E1000_PCS_LCTL); 537 regs_buff[49] = rd32(E1000_PCS_LSTAT); 538 regs_buff[50] = rd32(E1000_PCS_ANADV); 539 regs_buff[51] = rd32(E1000_PCS_LPAB); 540 regs_buff[52] = rd32(E1000_PCS_NPTX); 541 regs_buff[53] = rd32(E1000_PCS_LPABNP); 542 543 /* Statistics */ 544 regs_buff[54] = adapter->stats.crcerrs; 545 regs_buff[55] = adapter->stats.algnerrc; 546 regs_buff[56] = adapter->stats.symerrs; 547 regs_buff[57] = adapter->stats.rxerrc; 548 regs_buff[58] = adapter->stats.mpc; 549 regs_buff[59] = adapter->stats.scc; 550 regs_buff[60] = adapter->stats.ecol; 551 regs_buff[61] = adapter->stats.mcc; 552 regs_buff[62] = adapter->stats.latecol; 553 regs_buff[63] = adapter->stats.colc; 554 regs_buff[64] = adapter->stats.dc; 555 regs_buff[65] = adapter->stats.tncrs; 556 regs_buff[66] = adapter->stats.sec; 557 regs_buff[67] = adapter->stats.htdpmc; 558 regs_buff[68] = adapter->stats.rlec; 559 regs_buff[69] = adapter->stats.xonrxc; 560 regs_buff[70] = adapter->stats.xontxc; 561 regs_buff[71] = adapter->stats.xoffrxc; 562 regs_buff[72] = adapter->stats.xofftxc; 563 regs_buff[73] = adapter->stats.fcruc; 564 regs_buff[74] = adapter->stats.prc64; 565 regs_buff[75] = adapter->stats.prc127; 566 regs_buff[76] = adapter->stats.prc255; 567 regs_buff[77] = adapter->stats.prc511; 568 regs_buff[78] = adapter->stats.prc1023; 569 regs_buff[79] = adapter->stats.prc1522; 570 regs_buff[80] = adapter->stats.gprc; 571 regs_buff[81] = adapter->stats.bprc; 572 regs_buff[82] = adapter->stats.mprc; 573 regs_buff[83] = adapter->stats.gptc; 574 regs_buff[84] = adapter->stats.gorc; 575 regs_buff[86] = adapter->stats.gotc; 576 regs_buff[88] = adapter->stats.rnbc; 577 regs_buff[89] = adapter->stats.ruc; 578 regs_buff[90] = adapter->stats.rfc; 579 regs_buff[91] = adapter->stats.roc; 580 regs_buff[92] = adapter->stats.rjc; 581 regs_buff[93] = adapter->stats.mgprc; 582 regs_buff[94] = adapter->stats.mgpdc; 583 regs_buff[95] = adapter->stats.mgptc; 584 regs_buff[96] = adapter->stats.tor; 585 regs_buff[98] = adapter->stats.tot; 586 regs_buff[100] = adapter->stats.tpr; 587 regs_buff[101] = adapter->stats.tpt; 588 regs_buff[102] = adapter->stats.ptc64; 589 regs_buff[103] = adapter->stats.ptc127; 590 regs_buff[104] = adapter->stats.ptc255; 591 regs_buff[105] = adapter->stats.ptc511; 592 regs_buff[106] = adapter->stats.ptc1023; 593 regs_buff[107] = adapter->stats.ptc1522; 594 regs_buff[108] = adapter->stats.mptc; 595 regs_buff[109] = adapter->stats.bptc; 596 regs_buff[110] = adapter->stats.tsctc; 597 regs_buff[111] = adapter->stats.iac; 598 regs_buff[112] = adapter->stats.rpthc; 599 regs_buff[113] = adapter->stats.hgptc; 600 regs_buff[114] = adapter->stats.hgorc; 601 regs_buff[116] = adapter->stats.hgotc; 602 regs_buff[118] = adapter->stats.lenerrs; 603 regs_buff[119] = adapter->stats.scvpc; 604 regs_buff[120] = adapter->stats.hrmpc; 605 606 for (i = 0; i < 4; i++) 607 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 608 for (i = 0; i < 4; i++) 609 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 610 for (i = 0; i < 4; i++) 611 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 612 for (i = 0; i < 4; i++) 613 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 614 for (i = 0; i < 4; i++) 615 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 616 for (i = 0; i < 4; i++) 617 regs_buff[141 + i] = rd32(E1000_RDH(i)); 618 for (i = 0; i < 4; i++) 619 regs_buff[145 + i] = rd32(E1000_RDT(i)); 620 for (i = 0; i < 4; i++) 621 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 622 623 for (i = 0; i < 10; i++) 624 regs_buff[153 + i] = rd32(E1000_EITR(i)); 625 for (i = 0; i < 8; i++) 626 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 627 for (i = 0; i < 8; i++) 628 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 629 for (i = 0; i < 16; i++) 630 regs_buff[179 + i] = rd32(E1000_RAL(i)); 631 for (i = 0; i < 16; i++) 632 regs_buff[195 + i] = rd32(E1000_RAH(i)); 633 634 for (i = 0; i < 4; i++) 635 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 636 for (i = 0; i < 4; i++) 637 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 638 for (i = 0; i < 4; i++) 639 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 640 for (i = 0; i < 4; i++) 641 regs_buff[223 + i] = rd32(E1000_TDH(i)); 642 for (i = 0; i < 4; i++) 643 regs_buff[227 + i] = rd32(E1000_TDT(i)); 644 for (i = 0; i < 4; i++) 645 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 646 for (i = 0; i < 4; i++) 647 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 648 for (i = 0; i < 4; i++) 649 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 650 for (i = 0; i < 4; i++) 651 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 652 653 for (i = 0; i < 4; i++) 654 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 655 for (i = 0; i < 4; i++) 656 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 657 for (i = 0; i < 32; i++) 658 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 659 for (i = 0; i < 128; i++) 660 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 661 for (i = 0; i < 128; i++) 662 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 663 for (i = 0; i < 4; i++) 664 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 665 666 regs_buff[547] = rd32(E1000_TDFH); 667 regs_buff[548] = rd32(E1000_TDFT); 668 regs_buff[549] = rd32(E1000_TDFHS); 669 regs_buff[550] = rd32(E1000_TDFPC); 670 671 if (hw->mac.type > e1000_82580) { 672 regs_buff[551] = adapter->stats.o2bgptc; 673 regs_buff[552] = adapter->stats.b2ospc; 674 regs_buff[553] = adapter->stats.o2bspc; 675 regs_buff[554] = adapter->stats.b2ogprc; 676 } 677 678 if (hw->mac.type != e1000_82576) 679 return; 680 for (i = 0; i < 12; i++) 681 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 682 for (i = 0; i < 4; i++) 683 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 684 for (i = 0; i < 12; i++) 685 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 686 for (i = 0; i < 12; i++) 687 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 688 for (i = 0; i < 12; i++) 689 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 690 for (i = 0; i < 12; i++) 691 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 692 for (i = 0; i < 12; i++) 693 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 694 for (i = 0; i < 12; i++) 695 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 696 697 for (i = 0; i < 12; i++) 698 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 699 for (i = 0; i < 12; i++) 700 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 701 for (i = 0; i < 12; i++) 702 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 703 for (i = 0; i < 12; i++) 704 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 705 for (i = 0; i < 12; i++) 706 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 713 } 714 715 static int igb_get_eeprom_len(struct net_device *netdev) 716 { 717 struct igb_adapter *adapter = netdev_priv(netdev); 718 return adapter->hw.nvm.word_size * 2; 719 } 720 721 static int igb_get_eeprom(struct net_device *netdev, 722 struct ethtool_eeprom *eeprom, u8 *bytes) 723 { 724 struct igb_adapter *adapter = netdev_priv(netdev); 725 struct e1000_hw *hw = &adapter->hw; 726 u16 *eeprom_buff; 727 int first_word, last_word; 728 int ret_val = 0; 729 u16 i; 730 731 if (eeprom->len == 0) 732 return -EINVAL; 733 734 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 735 736 first_word = eeprom->offset >> 1; 737 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 738 739 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 740 GFP_KERNEL); 741 if (!eeprom_buff) 742 return -ENOMEM; 743 744 if (hw->nvm.type == e1000_nvm_eeprom_spi) 745 ret_val = hw->nvm.ops.read(hw, first_word, 746 last_word - first_word + 1, 747 eeprom_buff); 748 else { 749 for (i = 0; i < last_word - first_word + 1; i++) { 750 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 751 &eeprom_buff[i]); 752 if (ret_val) 753 break; 754 } 755 } 756 757 /* Device's eeprom is always little-endian, word addressable */ 758 for (i = 0; i < last_word - first_word + 1; i++) 759 le16_to_cpus(&eeprom_buff[i]); 760 761 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 762 eeprom->len); 763 kfree(eeprom_buff); 764 765 return ret_val; 766 } 767 768 static int igb_set_eeprom(struct net_device *netdev, 769 struct ethtool_eeprom *eeprom, u8 *bytes) 770 { 771 struct igb_adapter *adapter = netdev_priv(netdev); 772 struct e1000_hw *hw = &adapter->hw; 773 u16 *eeprom_buff; 774 void *ptr; 775 int max_len, first_word, last_word, ret_val = 0; 776 u16 i; 777 778 if (eeprom->len == 0) 779 return -EOPNOTSUPP; 780 781 if ((hw->mac.type >= e1000_i210) && 782 !igb_get_flash_presence_i210(hw)) { 783 return -EOPNOTSUPP; 784 } 785 786 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 787 return -EFAULT; 788 789 max_len = hw->nvm.word_size * 2; 790 791 first_word = eeprom->offset >> 1; 792 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 793 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 794 if (!eeprom_buff) 795 return -ENOMEM; 796 797 ptr = (void *)eeprom_buff; 798 799 if (eeprom->offset & 1) { 800 /* need read/modify/write of first changed EEPROM word 801 * only the second byte of the word is being modified 802 */ 803 ret_val = hw->nvm.ops.read(hw, first_word, 1, 804 &eeprom_buff[0]); 805 ptr++; 806 } 807 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 808 /* need read/modify/write of last changed EEPROM word 809 * only the first byte of the word is being modified 810 */ 811 ret_val = hw->nvm.ops.read(hw, last_word, 1, 812 &eeprom_buff[last_word - first_word]); 813 } 814 815 /* Device's eeprom is always little-endian, word addressable */ 816 for (i = 0; i < last_word - first_word + 1; i++) 817 le16_to_cpus(&eeprom_buff[i]); 818 819 memcpy(ptr, bytes, eeprom->len); 820 821 for (i = 0; i < last_word - first_word + 1; i++) 822 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 823 824 ret_val = hw->nvm.ops.write(hw, first_word, 825 last_word - first_word + 1, eeprom_buff); 826 827 /* Update the checksum if nvm write succeeded */ 828 if (ret_val == 0) 829 hw->nvm.ops.update(hw); 830 831 igb_set_fw_version(adapter); 832 kfree(eeprom_buff); 833 return ret_val; 834 } 835 836 static void igb_get_drvinfo(struct net_device *netdev, 837 struct ethtool_drvinfo *drvinfo) 838 { 839 struct igb_adapter *adapter = netdev_priv(netdev); 840 841 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 842 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 843 844 /* EEPROM image version # is reported as firmware version # for 845 * 82575 controllers 846 */ 847 strlcpy(drvinfo->fw_version, adapter->fw_version, 848 sizeof(drvinfo->fw_version)); 849 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 850 sizeof(drvinfo->bus_info)); 851 852 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN; 853 } 854 855 static void igb_get_ringparam(struct net_device *netdev, 856 struct ethtool_ringparam *ring) 857 { 858 struct igb_adapter *adapter = netdev_priv(netdev); 859 860 ring->rx_max_pending = IGB_MAX_RXD; 861 ring->tx_max_pending = IGB_MAX_TXD; 862 ring->rx_pending = adapter->rx_ring_count; 863 ring->tx_pending = adapter->tx_ring_count; 864 } 865 866 static int igb_set_ringparam(struct net_device *netdev, 867 struct ethtool_ringparam *ring) 868 { 869 struct igb_adapter *adapter = netdev_priv(netdev); 870 struct igb_ring *temp_ring; 871 int i, err = 0; 872 u16 new_rx_count, new_tx_count; 873 874 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 875 return -EINVAL; 876 877 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 878 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 879 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 880 881 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 882 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 883 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 884 885 if ((new_tx_count == adapter->tx_ring_count) && 886 (new_rx_count == adapter->rx_ring_count)) { 887 /* nothing to do */ 888 return 0; 889 } 890 891 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 892 usleep_range(1000, 2000); 893 894 if (!netif_running(adapter->netdev)) { 895 for (i = 0; i < adapter->num_tx_queues; i++) 896 adapter->tx_ring[i]->count = new_tx_count; 897 for (i = 0; i < adapter->num_rx_queues; i++) 898 adapter->rx_ring[i]->count = new_rx_count; 899 adapter->tx_ring_count = new_tx_count; 900 adapter->rx_ring_count = new_rx_count; 901 goto clear_reset; 902 } 903 904 if (adapter->num_tx_queues > adapter->num_rx_queues) 905 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 906 adapter->num_tx_queues)); 907 else 908 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 909 adapter->num_rx_queues)); 910 911 if (!temp_ring) { 912 err = -ENOMEM; 913 goto clear_reset; 914 } 915 916 igb_down(adapter); 917 918 /* We can't just free everything and then setup again, 919 * because the ISRs in MSI-X mode get passed pointers 920 * to the Tx and Rx ring structs. 921 */ 922 if (new_tx_count != adapter->tx_ring_count) { 923 for (i = 0; i < adapter->num_tx_queues; i++) { 924 memcpy(&temp_ring[i], adapter->tx_ring[i], 925 sizeof(struct igb_ring)); 926 927 temp_ring[i].count = new_tx_count; 928 err = igb_setup_tx_resources(&temp_ring[i]); 929 if (err) { 930 while (i) { 931 i--; 932 igb_free_tx_resources(&temp_ring[i]); 933 } 934 goto err_setup; 935 } 936 } 937 938 for (i = 0; i < adapter->num_tx_queues; i++) { 939 igb_free_tx_resources(adapter->tx_ring[i]); 940 941 memcpy(adapter->tx_ring[i], &temp_ring[i], 942 sizeof(struct igb_ring)); 943 } 944 945 adapter->tx_ring_count = new_tx_count; 946 } 947 948 if (new_rx_count != adapter->rx_ring_count) { 949 for (i = 0; i < adapter->num_rx_queues; i++) { 950 memcpy(&temp_ring[i], adapter->rx_ring[i], 951 sizeof(struct igb_ring)); 952 953 temp_ring[i].count = new_rx_count; 954 err = igb_setup_rx_resources(&temp_ring[i]); 955 if (err) { 956 while (i) { 957 i--; 958 igb_free_rx_resources(&temp_ring[i]); 959 } 960 goto err_setup; 961 } 962 963 } 964 965 for (i = 0; i < adapter->num_rx_queues; i++) { 966 igb_free_rx_resources(adapter->rx_ring[i]); 967 968 memcpy(adapter->rx_ring[i], &temp_ring[i], 969 sizeof(struct igb_ring)); 970 } 971 972 adapter->rx_ring_count = new_rx_count; 973 } 974 err_setup: 975 igb_up(adapter); 976 vfree(temp_ring); 977 clear_reset: 978 clear_bit(__IGB_RESETTING, &adapter->state); 979 return err; 980 } 981 982 /* ethtool register test data */ 983 struct igb_reg_test { 984 u16 reg; 985 u16 reg_offset; 986 u16 array_len; 987 u16 test_type; 988 u32 mask; 989 u32 write; 990 }; 991 992 /* In the hardware, registers are laid out either singly, in arrays 993 * spaced 0x100 bytes apart, or in contiguous tables. We assume 994 * most tests take place on arrays or single registers (handled 995 * as a single-element array) and special-case the tables. 996 * Table tests are always pattern tests. 997 * 998 * We also make provision for some required setup steps by specifying 999 * registers to be written without any read-back testing. 1000 */ 1001 1002 #define PATTERN_TEST 1 1003 #define SET_READ_TEST 2 1004 #define WRITE_NO_TEST 3 1005 #define TABLE32_TEST 4 1006 #define TABLE64_TEST_LO 5 1007 #define TABLE64_TEST_HI 6 1008 1009 /* i210 reg test */ 1010 static struct igb_reg_test reg_test_i210[] = { 1011 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1012 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1013 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1014 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1015 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1016 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1017 /* RDH is read-only for i210, only test RDT. */ 1018 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1019 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1020 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1021 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1022 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1023 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1024 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1025 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1026 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1027 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1028 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1029 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1030 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1031 0xFFFFFFFF, 0xFFFFFFFF }, 1032 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1033 0x900FFFFF, 0xFFFFFFFF }, 1034 { E1000_MTA, 0, 128, TABLE32_TEST, 1035 0xFFFFFFFF, 0xFFFFFFFF }, 1036 { 0, 0, 0, 0, 0 } 1037 }; 1038 1039 /* i350 reg test */ 1040 static struct igb_reg_test reg_test_i350[] = { 1041 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1042 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1043 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1044 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1045 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1046 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1047 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1048 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1049 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1050 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1051 /* RDH is read-only for i350, only test RDT. */ 1052 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1053 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1054 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1055 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1056 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1057 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1058 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1059 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1060 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1061 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1062 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1063 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1064 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1065 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1066 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1067 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1068 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1069 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1070 0xFFFFFFFF, 0xFFFFFFFF }, 1071 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1072 0xC3FFFFFF, 0xFFFFFFFF }, 1073 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1074 0xFFFFFFFF, 0xFFFFFFFF }, 1075 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1076 0xC3FFFFFF, 0xFFFFFFFF }, 1077 { E1000_MTA, 0, 128, TABLE32_TEST, 1078 0xFFFFFFFF, 0xFFFFFFFF }, 1079 { 0, 0, 0, 0 } 1080 }; 1081 1082 /* 82580 reg test */ 1083 static struct igb_reg_test reg_test_82580[] = { 1084 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1085 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1086 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1087 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1088 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1089 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1090 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1091 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1092 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1093 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1094 /* RDH is read-only for 82580, only test RDT. */ 1095 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1096 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1097 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1098 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1099 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1100 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1101 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1102 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1103 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1104 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1105 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1106 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1107 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1108 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1109 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1110 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1111 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1112 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1113 0xFFFFFFFF, 0xFFFFFFFF }, 1114 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1115 0x83FFFFFF, 0xFFFFFFFF }, 1116 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1117 0xFFFFFFFF, 0xFFFFFFFF }, 1118 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1119 0x83FFFFFF, 0xFFFFFFFF }, 1120 { E1000_MTA, 0, 128, TABLE32_TEST, 1121 0xFFFFFFFF, 0xFFFFFFFF }, 1122 { 0, 0, 0, 0 } 1123 }; 1124 1125 /* 82576 reg test */ 1126 static struct igb_reg_test reg_test_82576[] = { 1127 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1128 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1129 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1130 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1131 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1132 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1134 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1135 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1136 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1137 /* Enable all RX queues before testing. */ 1138 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1139 E1000_RXDCTL_QUEUE_ENABLE }, 1140 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1141 E1000_RXDCTL_QUEUE_ENABLE }, 1142 /* RDH is read-only for 82576, only test RDT. */ 1143 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1144 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1145 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1146 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1147 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1148 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1149 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1150 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1151 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1152 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1153 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1154 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1155 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1156 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1157 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1158 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1159 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1160 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1161 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1162 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1163 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1164 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1165 { 0, 0, 0, 0 } 1166 }; 1167 1168 /* 82575 register test */ 1169 static struct igb_reg_test reg_test_82575[] = { 1170 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1171 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1172 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1173 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1174 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1175 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1176 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1177 /* Enable all four RX queues before testing. */ 1178 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1179 E1000_RXDCTL_QUEUE_ENABLE }, 1180 /* RDH is read-only for 82575, only test RDT. */ 1181 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1182 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1183 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1184 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1185 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1186 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1187 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1188 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1189 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1190 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1191 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1192 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1193 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1194 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1195 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1196 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1197 { 0, 0, 0, 0 } 1198 }; 1199 1200 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1201 int reg, u32 mask, u32 write) 1202 { 1203 struct e1000_hw *hw = &adapter->hw; 1204 u32 pat, val; 1205 static const u32 _test[] = { 1206 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1207 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1208 wr32(reg, (_test[pat] & write)); 1209 val = rd32(reg) & mask; 1210 if (val != (_test[pat] & write & mask)) { 1211 dev_err(&adapter->pdev->dev, 1212 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1213 reg, val, (_test[pat] & write & mask)); 1214 *data = reg; 1215 return true; 1216 } 1217 } 1218 1219 return false; 1220 } 1221 1222 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1223 int reg, u32 mask, u32 write) 1224 { 1225 struct e1000_hw *hw = &adapter->hw; 1226 u32 val; 1227 1228 wr32(reg, write & mask); 1229 val = rd32(reg); 1230 if ((write & mask) != (val & mask)) { 1231 dev_err(&adapter->pdev->dev, 1232 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1233 reg, (val & mask), (write & mask)); 1234 *data = reg; 1235 return true; 1236 } 1237 1238 return false; 1239 } 1240 1241 #define REG_PATTERN_TEST(reg, mask, write) \ 1242 do { \ 1243 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1244 return 1; \ 1245 } while (0) 1246 1247 #define REG_SET_AND_CHECK(reg, mask, write) \ 1248 do { \ 1249 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1250 return 1; \ 1251 } while (0) 1252 1253 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1254 { 1255 struct e1000_hw *hw = &adapter->hw; 1256 struct igb_reg_test *test; 1257 u32 value, before, after; 1258 u32 i, toggle; 1259 1260 switch (adapter->hw.mac.type) { 1261 case e1000_i350: 1262 case e1000_i354: 1263 test = reg_test_i350; 1264 toggle = 0x7FEFF3FF; 1265 break; 1266 case e1000_i210: 1267 case e1000_i211: 1268 test = reg_test_i210; 1269 toggle = 0x7FEFF3FF; 1270 break; 1271 case e1000_82580: 1272 test = reg_test_82580; 1273 toggle = 0x7FEFF3FF; 1274 break; 1275 case e1000_82576: 1276 test = reg_test_82576; 1277 toggle = 0x7FFFF3FF; 1278 break; 1279 default: 1280 test = reg_test_82575; 1281 toggle = 0x7FFFF3FF; 1282 break; 1283 } 1284 1285 /* Because the status register is such a special case, 1286 * we handle it separately from the rest of the register 1287 * tests. Some bits are read-only, some toggle, and some 1288 * are writable on newer MACs. 1289 */ 1290 before = rd32(E1000_STATUS); 1291 value = (rd32(E1000_STATUS) & toggle); 1292 wr32(E1000_STATUS, toggle); 1293 after = rd32(E1000_STATUS) & toggle; 1294 if (value != after) { 1295 dev_err(&adapter->pdev->dev, 1296 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1297 after, value); 1298 *data = 1; 1299 return 1; 1300 } 1301 /* restore previous status */ 1302 wr32(E1000_STATUS, before); 1303 1304 /* Perform the remainder of the register test, looping through 1305 * the test table until we either fail or reach the null entry. 1306 */ 1307 while (test->reg) { 1308 for (i = 0; i < test->array_len; i++) { 1309 switch (test->test_type) { 1310 case PATTERN_TEST: 1311 REG_PATTERN_TEST(test->reg + 1312 (i * test->reg_offset), 1313 test->mask, 1314 test->write); 1315 break; 1316 case SET_READ_TEST: 1317 REG_SET_AND_CHECK(test->reg + 1318 (i * test->reg_offset), 1319 test->mask, 1320 test->write); 1321 break; 1322 case WRITE_NO_TEST: 1323 writel(test->write, 1324 (adapter->hw.hw_addr + test->reg) 1325 + (i * test->reg_offset)); 1326 break; 1327 case TABLE32_TEST: 1328 REG_PATTERN_TEST(test->reg + (i * 4), 1329 test->mask, 1330 test->write); 1331 break; 1332 case TABLE64_TEST_LO: 1333 REG_PATTERN_TEST(test->reg + (i * 8), 1334 test->mask, 1335 test->write); 1336 break; 1337 case TABLE64_TEST_HI: 1338 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1339 test->mask, 1340 test->write); 1341 break; 1342 } 1343 } 1344 test++; 1345 } 1346 1347 *data = 0; 1348 return 0; 1349 } 1350 1351 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1352 { 1353 struct e1000_hw *hw = &adapter->hw; 1354 1355 *data = 0; 1356 1357 /* Validate eeprom on all parts but flashless */ 1358 switch (hw->mac.type) { 1359 case e1000_i210: 1360 case e1000_i211: 1361 if (igb_get_flash_presence_i210(hw)) { 1362 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1363 *data = 2; 1364 } 1365 break; 1366 default: 1367 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1368 *data = 2; 1369 break; 1370 } 1371 1372 return *data; 1373 } 1374 1375 static irqreturn_t igb_test_intr(int irq, void *data) 1376 { 1377 struct igb_adapter *adapter = (struct igb_adapter *) data; 1378 struct e1000_hw *hw = &adapter->hw; 1379 1380 adapter->test_icr |= rd32(E1000_ICR); 1381 1382 return IRQ_HANDLED; 1383 } 1384 1385 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1386 { 1387 struct e1000_hw *hw = &adapter->hw; 1388 struct net_device *netdev = adapter->netdev; 1389 u32 mask, ics_mask, i = 0, shared_int = true; 1390 u32 irq = adapter->pdev->irq; 1391 1392 *data = 0; 1393 1394 /* Hook up test interrupt handler just for this test */ 1395 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1396 if (request_irq(adapter->msix_entries[0].vector, 1397 igb_test_intr, 0, netdev->name, adapter)) { 1398 *data = 1; 1399 return -1; 1400 } 1401 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1402 shared_int = false; 1403 if (request_irq(irq, 1404 igb_test_intr, 0, netdev->name, adapter)) { 1405 *data = 1; 1406 return -1; 1407 } 1408 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1409 netdev->name, adapter)) { 1410 shared_int = false; 1411 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1412 netdev->name, adapter)) { 1413 *data = 1; 1414 return -1; 1415 } 1416 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1417 (shared_int ? "shared" : "unshared")); 1418 1419 /* Disable all the interrupts */ 1420 wr32(E1000_IMC, ~0); 1421 wrfl(); 1422 usleep_range(10000, 11000); 1423 1424 /* Define all writable bits for ICS */ 1425 switch (hw->mac.type) { 1426 case e1000_82575: 1427 ics_mask = 0x37F47EDD; 1428 break; 1429 case e1000_82576: 1430 ics_mask = 0x77D4FBFD; 1431 break; 1432 case e1000_82580: 1433 ics_mask = 0x77DCFED5; 1434 break; 1435 case e1000_i350: 1436 case e1000_i354: 1437 case e1000_i210: 1438 case e1000_i211: 1439 ics_mask = 0x77DCFED5; 1440 break; 1441 default: 1442 ics_mask = 0x7FFFFFFF; 1443 break; 1444 } 1445 1446 /* Test each interrupt */ 1447 for (; i < 31; i++) { 1448 /* Interrupt to test */ 1449 mask = BIT(i); 1450 1451 if (!(mask & ics_mask)) 1452 continue; 1453 1454 if (!shared_int) { 1455 /* Disable the interrupt to be reported in 1456 * the cause register and then force the same 1457 * interrupt and see if one gets posted. If 1458 * an interrupt was posted to the bus, the 1459 * test failed. 1460 */ 1461 adapter->test_icr = 0; 1462 1463 /* Flush any pending interrupts */ 1464 wr32(E1000_ICR, ~0); 1465 1466 wr32(E1000_IMC, mask); 1467 wr32(E1000_ICS, mask); 1468 wrfl(); 1469 usleep_range(10000, 11000); 1470 1471 if (adapter->test_icr & mask) { 1472 *data = 3; 1473 break; 1474 } 1475 } 1476 1477 /* Enable the interrupt to be reported in 1478 * the cause register and then force the same 1479 * interrupt and see if one gets posted. If 1480 * an interrupt was not posted to the bus, the 1481 * test failed. 1482 */ 1483 adapter->test_icr = 0; 1484 1485 /* Flush any pending interrupts */ 1486 wr32(E1000_ICR, ~0); 1487 1488 wr32(E1000_IMS, mask); 1489 wr32(E1000_ICS, mask); 1490 wrfl(); 1491 usleep_range(10000, 11000); 1492 1493 if (!(adapter->test_icr & mask)) { 1494 *data = 4; 1495 break; 1496 } 1497 1498 if (!shared_int) { 1499 /* Disable the other interrupts to be reported in 1500 * the cause register and then force the other 1501 * interrupts and see if any get posted. If 1502 * an interrupt was posted to the bus, the 1503 * test failed. 1504 */ 1505 adapter->test_icr = 0; 1506 1507 /* Flush any pending interrupts */ 1508 wr32(E1000_ICR, ~0); 1509 1510 wr32(E1000_IMC, ~mask); 1511 wr32(E1000_ICS, ~mask); 1512 wrfl(); 1513 usleep_range(10000, 11000); 1514 1515 if (adapter->test_icr & mask) { 1516 *data = 5; 1517 break; 1518 } 1519 } 1520 } 1521 1522 /* Disable all the interrupts */ 1523 wr32(E1000_IMC, ~0); 1524 wrfl(); 1525 usleep_range(10000, 11000); 1526 1527 /* Unhook test interrupt handler */ 1528 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1529 free_irq(adapter->msix_entries[0].vector, adapter); 1530 else 1531 free_irq(irq, adapter); 1532 1533 return *data; 1534 } 1535 1536 static void igb_free_desc_rings(struct igb_adapter *adapter) 1537 { 1538 igb_free_tx_resources(&adapter->test_tx_ring); 1539 igb_free_rx_resources(&adapter->test_rx_ring); 1540 } 1541 1542 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1543 { 1544 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1545 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1546 struct e1000_hw *hw = &adapter->hw; 1547 int ret_val; 1548 1549 /* Setup Tx descriptor ring and Tx buffers */ 1550 tx_ring->count = IGB_DEFAULT_TXD; 1551 tx_ring->dev = &adapter->pdev->dev; 1552 tx_ring->netdev = adapter->netdev; 1553 tx_ring->reg_idx = adapter->vfs_allocated_count; 1554 1555 if (igb_setup_tx_resources(tx_ring)) { 1556 ret_val = 1; 1557 goto err_nomem; 1558 } 1559 1560 igb_setup_tctl(adapter); 1561 igb_configure_tx_ring(adapter, tx_ring); 1562 1563 /* Setup Rx descriptor ring and Rx buffers */ 1564 rx_ring->count = IGB_DEFAULT_RXD; 1565 rx_ring->dev = &adapter->pdev->dev; 1566 rx_ring->netdev = adapter->netdev; 1567 rx_ring->reg_idx = adapter->vfs_allocated_count; 1568 1569 if (igb_setup_rx_resources(rx_ring)) { 1570 ret_val = 3; 1571 goto err_nomem; 1572 } 1573 1574 /* set the default queue to queue 0 of PF */ 1575 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1576 1577 /* enable receive ring */ 1578 igb_setup_rctl(adapter); 1579 igb_configure_rx_ring(adapter, rx_ring); 1580 1581 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1582 1583 return 0; 1584 1585 err_nomem: 1586 igb_free_desc_rings(adapter); 1587 return ret_val; 1588 } 1589 1590 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1591 { 1592 struct e1000_hw *hw = &adapter->hw; 1593 1594 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1595 igb_write_phy_reg(hw, 29, 0x001F); 1596 igb_write_phy_reg(hw, 30, 0x8FFC); 1597 igb_write_phy_reg(hw, 29, 0x001A); 1598 igb_write_phy_reg(hw, 30, 0x8FF0); 1599 } 1600 1601 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1602 { 1603 struct e1000_hw *hw = &adapter->hw; 1604 u32 ctrl_reg = 0; 1605 1606 hw->mac.autoneg = false; 1607 1608 if (hw->phy.type == e1000_phy_m88) { 1609 if (hw->phy.id != I210_I_PHY_ID) { 1610 /* Auto-MDI/MDIX Off */ 1611 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1612 /* reset to update Auto-MDI/MDIX */ 1613 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1614 /* autoneg off */ 1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1616 } else { 1617 /* force 1000, set loopback */ 1618 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1619 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1620 } 1621 } else if (hw->phy.type == e1000_phy_82580) { 1622 /* enable MII loopback */ 1623 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1624 } 1625 1626 /* add small delay to avoid loopback test failure */ 1627 msleep(50); 1628 1629 /* force 1000, set loopback */ 1630 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1631 1632 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1633 ctrl_reg = rd32(E1000_CTRL); 1634 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1635 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1636 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1637 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1638 E1000_CTRL_FD | /* Force Duplex to FULL */ 1639 E1000_CTRL_SLU); /* Set link up enable bit */ 1640 1641 if (hw->phy.type == e1000_phy_m88) 1642 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1643 1644 wr32(E1000_CTRL, ctrl_reg); 1645 1646 /* Disable the receiver on the PHY so when a cable is plugged in, the 1647 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1648 */ 1649 if (hw->phy.type == e1000_phy_m88) 1650 igb_phy_disable_receiver(adapter); 1651 1652 msleep(500); 1653 return 0; 1654 } 1655 1656 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1657 { 1658 return igb_integrated_phy_loopback(adapter); 1659 } 1660 1661 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1662 { 1663 struct e1000_hw *hw = &adapter->hw; 1664 u32 reg; 1665 1666 reg = rd32(E1000_CTRL_EXT); 1667 1668 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1669 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1670 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1671 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1672 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1673 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1674 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1675 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1676 /* Enable DH89xxCC MPHY for near end loopback */ 1677 reg = rd32(E1000_MPHY_ADDR_CTL); 1678 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1679 E1000_MPHY_PCS_CLK_REG_OFFSET; 1680 wr32(E1000_MPHY_ADDR_CTL, reg); 1681 1682 reg = rd32(E1000_MPHY_DATA); 1683 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1684 wr32(E1000_MPHY_DATA, reg); 1685 } 1686 1687 reg = rd32(E1000_RCTL); 1688 reg |= E1000_RCTL_LBM_TCVR; 1689 wr32(E1000_RCTL, reg); 1690 1691 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1692 1693 reg = rd32(E1000_CTRL); 1694 reg &= ~(E1000_CTRL_RFCE | 1695 E1000_CTRL_TFCE | 1696 E1000_CTRL_LRST); 1697 reg |= E1000_CTRL_SLU | 1698 E1000_CTRL_FD; 1699 wr32(E1000_CTRL, reg); 1700 1701 /* Unset switch control to serdes energy detect */ 1702 reg = rd32(E1000_CONNSW); 1703 reg &= ~E1000_CONNSW_ENRGSRC; 1704 wr32(E1000_CONNSW, reg); 1705 1706 /* Unset sigdetect for SERDES loopback on 1707 * 82580 and newer devices. 1708 */ 1709 if (hw->mac.type >= e1000_82580) { 1710 reg = rd32(E1000_PCS_CFG0); 1711 reg |= E1000_PCS_CFG_IGN_SD; 1712 wr32(E1000_PCS_CFG0, reg); 1713 } 1714 1715 /* Set PCS register for forced speed */ 1716 reg = rd32(E1000_PCS_LCTL); 1717 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1718 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1719 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1720 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1721 E1000_PCS_LCTL_FSD | /* Force Speed */ 1722 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1723 wr32(E1000_PCS_LCTL, reg); 1724 1725 return 0; 1726 } 1727 1728 return igb_set_phy_loopback(adapter); 1729 } 1730 1731 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1732 { 1733 struct e1000_hw *hw = &adapter->hw; 1734 u32 rctl; 1735 u16 phy_reg; 1736 1737 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1738 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1739 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1740 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1741 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1742 u32 reg; 1743 1744 /* Disable near end loopback on DH89xxCC */ 1745 reg = rd32(E1000_MPHY_ADDR_CTL); 1746 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1747 E1000_MPHY_PCS_CLK_REG_OFFSET; 1748 wr32(E1000_MPHY_ADDR_CTL, reg); 1749 1750 reg = rd32(E1000_MPHY_DATA); 1751 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1752 wr32(E1000_MPHY_DATA, reg); 1753 } 1754 1755 rctl = rd32(E1000_RCTL); 1756 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1757 wr32(E1000_RCTL, rctl); 1758 1759 hw->mac.autoneg = true; 1760 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1761 if (phy_reg & MII_CR_LOOPBACK) { 1762 phy_reg &= ~MII_CR_LOOPBACK; 1763 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1764 igb_phy_sw_reset(hw); 1765 } 1766 } 1767 1768 static void igb_create_lbtest_frame(struct sk_buff *skb, 1769 unsigned int frame_size) 1770 { 1771 memset(skb->data, 0xFF, frame_size); 1772 frame_size /= 2; 1773 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1774 memset(&skb->data[frame_size + 10], 0xBE, 1); 1775 memset(&skb->data[frame_size + 12], 0xAF, 1); 1776 } 1777 1778 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1779 unsigned int frame_size) 1780 { 1781 unsigned char *data; 1782 bool match = true; 1783 1784 frame_size >>= 1; 1785 1786 data = kmap(rx_buffer->page); 1787 1788 if (data[3] != 0xFF || 1789 data[frame_size + 10] != 0xBE || 1790 data[frame_size + 12] != 0xAF) 1791 match = false; 1792 1793 kunmap(rx_buffer->page); 1794 1795 return match; 1796 } 1797 1798 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1799 struct igb_ring *tx_ring, 1800 unsigned int size) 1801 { 1802 union e1000_adv_rx_desc *rx_desc; 1803 struct igb_rx_buffer *rx_buffer_info; 1804 struct igb_tx_buffer *tx_buffer_info; 1805 u16 rx_ntc, tx_ntc, count = 0; 1806 1807 /* initialize next to clean and descriptor values */ 1808 rx_ntc = rx_ring->next_to_clean; 1809 tx_ntc = tx_ring->next_to_clean; 1810 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1811 1812 while (rx_desc->wb.upper.length) { 1813 /* check Rx buffer */ 1814 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1815 1816 /* sync Rx buffer for CPU read */ 1817 dma_sync_single_for_cpu(rx_ring->dev, 1818 rx_buffer_info->dma, 1819 size, 1820 DMA_FROM_DEVICE); 1821 1822 /* verify contents of skb */ 1823 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1824 count++; 1825 1826 /* sync Rx buffer for device write */ 1827 dma_sync_single_for_device(rx_ring->dev, 1828 rx_buffer_info->dma, 1829 size, 1830 DMA_FROM_DEVICE); 1831 1832 /* unmap buffer on Tx side */ 1833 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1834 1835 /* Free all the Tx ring sk_buffs */ 1836 dev_kfree_skb_any(tx_buffer_info->skb); 1837 1838 /* unmap skb header data */ 1839 dma_unmap_single(tx_ring->dev, 1840 dma_unmap_addr(tx_buffer_info, dma), 1841 dma_unmap_len(tx_buffer_info, len), 1842 DMA_TO_DEVICE); 1843 dma_unmap_len_set(tx_buffer_info, len, 0); 1844 1845 /* increment Rx/Tx next to clean counters */ 1846 rx_ntc++; 1847 if (rx_ntc == rx_ring->count) 1848 rx_ntc = 0; 1849 tx_ntc++; 1850 if (tx_ntc == tx_ring->count) 1851 tx_ntc = 0; 1852 1853 /* fetch next descriptor */ 1854 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1855 } 1856 1857 netdev_tx_reset_queue(txring_txq(tx_ring)); 1858 1859 /* re-map buffers to ring, store next to clean values */ 1860 igb_alloc_rx_buffers(rx_ring, count); 1861 rx_ring->next_to_clean = rx_ntc; 1862 tx_ring->next_to_clean = tx_ntc; 1863 1864 return count; 1865 } 1866 1867 static int igb_run_loopback_test(struct igb_adapter *adapter) 1868 { 1869 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1870 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1871 u16 i, j, lc, good_cnt; 1872 int ret_val = 0; 1873 unsigned int size = IGB_RX_HDR_LEN; 1874 netdev_tx_t tx_ret_val; 1875 struct sk_buff *skb; 1876 1877 /* allocate test skb */ 1878 skb = alloc_skb(size, GFP_KERNEL); 1879 if (!skb) 1880 return 11; 1881 1882 /* place data into test skb */ 1883 igb_create_lbtest_frame(skb, size); 1884 skb_put(skb, size); 1885 1886 /* Calculate the loop count based on the largest descriptor ring 1887 * The idea is to wrap the largest ring a number of times using 64 1888 * send/receive pairs during each loop 1889 */ 1890 1891 if (rx_ring->count <= tx_ring->count) 1892 lc = ((tx_ring->count / 64) * 2) + 1; 1893 else 1894 lc = ((rx_ring->count / 64) * 2) + 1; 1895 1896 for (j = 0; j <= lc; j++) { /* loop count loop */ 1897 /* reset count of good packets */ 1898 good_cnt = 0; 1899 1900 /* place 64 packets on the transmit queue*/ 1901 for (i = 0; i < 64; i++) { 1902 skb_get(skb); 1903 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1904 if (tx_ret_val == NETDEV_TX_OK) 1905 good_cnt++; 1906 } 1907 1908 if (good_cnt != 64) { 1909 ret_val = 12; 1910 break; 1911 } 1912 1913 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1914 msleep(200); 1915 1916 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1917 if (good_cnt != 64) { 1918 ret_val = 13; 1919 break; 1920 } 1921 } /* end loop count loop */ 1922 1923 /* free the original skb */ 1924 kfree_skb(skb); 1925 1926 return ret_val; 1927 } 1928 1929 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1930 { 1931 /* PHY loopback cannot be performed if SoL/IDER 1932 * sessions are active 1933 */ 1934 if (igb_check_reset_block(&adapter->hw)) { 1935 dev_err(&adapter->pdev->dev, 1936 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1937 *data = 0; 1938 goto out; 1939 } 1940 1941 if (adapter->hw.mac.type == e1000_i354) { 1942 dev_info(&adapter->pdev->dev, 1943 "Loopback test not supported on i354.\n"); 1944 *data = 0; 1945 goto out; 1946 } 1947 *data = igb_setup_desc_rings(adapter); 1948 if (*data) 1949 goto out; 1950 *data = igb_setup_loopback_test(adapter); 1951 if (*data) 1952 goto err_loopback; 1953 *data = igb_run_loopback_test(adapter); 1954 igb_loopback_cleanup(adapter); 1955 1956 err_loopback: 1957 igb_free_desc_rings(adapter); 1958 out: 1959 return *data; 1960 } 1961 1962 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1963 { 1964 struct e1000_hw *hw = &adapter->hw; 1965 *data = 0; 1966 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1967 int i = 0; 1968 1969 hw->mac.serdes_has_link = false; 1970 1971 /* On some blade server designs, link establishment 1972 * could take as long as 2-3 minutes 1973 */ 1974 do { 1975 hw->mac.ops.check_for_link(&adapter->hw); 1976 if (hw->mac.serdes_has_link) 1977 return *data; 1978 msleep(20); 1979 } while (i++ < 3750); 1980 1981 *data = 1; 1982 } else { 1983 hw->mac.ops.check_for_link(&adapter->hw); 1984 if (hw->mac.autoneg) 1985 msleep(5000); 1986 1987 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1988 *data = 1; 1989 } 1990 return *data; 1991 } 1992 1993 static void igb_diag_test(struct net_device *netdev, 1994 struct ethtool_test *eth_test, u64 *data) 1995 { 1996 struct igb_adapter *adapter = netdev_priv(netdev); 1997 u16 autoneg_advertised; 1998 u8 forced_speed_duplex, autoneg; 1999 bool if_running = netif_running(netdev); 2000 2001 set_bit(__IGB_TESTING, &adapter->state); 2002 2003 /* can't do offline tests on media switching devices */ 2004 if (adapter->hw.dev_spec._82575.mas_capable) 2005 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 2006 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2007 /* Offline tests */ 2008 2009 /* save speed, duplex, autoneg settings */ 2010 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2011 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2012 autoneg = adapter->hw.mac.autoneg; 2013 2014 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2015 2016 /* power up link for link test */ 2017 igb_power_up_link(adapter); 2018 2019 /* Link test performed before hardware reset so autoneg doesn't 2020 * interfere with test result 2021 */ 2022 if (igb_link_test(adapter, &data[TEST_LINK])) 2023 eth_test->flags |= ETH_TEST_FL_FAILED; 2024 2025 if (if_running) 2026 /* indicate we're in test mode */ 2027 igb_close(netdev); 2028 else 2029 igb_reset(adapter); 2030 2031 if (igb_reg_test(adapter, &data[TEST_REG])) 2032 eth_test->flags |= ETH_TEST_FL_FAILED; 2033 2034 igb_reset(adapter); 2035 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2036 eth_test->flags |= ETH_TEST_FL_FAILED; 2037 2038 igb_reset(adapter); 2039 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2040 eth_test->flags |= ETH_TEST_FL_FAILED; 2041 2042 igb_reset(adapter); 2043 /* power up link for loopback test */ 2044 igb_power_up_link(adapter); 2045 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2046 eth_test->flags |= ETH_TEST_FL_FAILED; 2047 2048 /* restore speed, duplex, autoneg settings */ 2049 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2050 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2051 adapter->hw.mac.autoneg = autoneg; 2052 2053 /* force this routine to wait until autoneg complete/timeout */ 2054 adapter->hw.phy.autoneg_wait_to_complete = true; 2055 igb_reset(adapter); 2056 adapter->hw.phy.autoneg_wait_to_complete = false; 2057 2058 clear_bit(__IGB_TESTING, &adapter->state); 2059 if (if_running) 2060 igb_open(netdev); 2061 } else { 2062 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2063 2064 /* PHY is powered down when interface is down */ 2065 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2066 eth_test->flags |= ETH_TEST_FL_FAILED; 2067 else 2068 data[TEST_LINK] = 0; 2069 2070 /* Online tests aren't run; pass by default */ 2071 data[TEST_REG] = 0; 2072 data[TEST_EEP] = 0; 2073 data[TEST_IRQ] = 0; 2074 data[TEST_LOOP] = 0; 2075 2076 clear_bit(__IGB_TESTING, &adapter->state); 2077 } 2078 msleep_interruptible(4 * 1000); 2079 } 2080 2081 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2082 { 2083 struct igb_adapter *adapter = netdev_priv(netdev); 2084 2085 wol->wolopts = 0; 2086 2087 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2088 return; 2089 2090 wol->supported = WAKE_UCAST | WAKE_MCAST | 2091 WAKE_BCAST | WAKE_MAGIC | 2092 WAKE_PHY; 2093 2094 /* apply any specific unsupported masks here */ 2095 switch (adapter->hw.device_id) { 2096 default: 2097 break; 2098 } 2099 2100 if (adapter->wol & E1000_WUFC_EX) 2101 wol->wolopts |= WAKE_UCAST; 2102 if (adapter->wol & E1000_WUFC_MC) 2103 wol->wolopts |= WAKE_MCAST; 2104 if (adapter->wol & E1000_WUFC_BC) 2105 wol->wolopts |= WAKE_BCAST; 2106 if (adapter->wol & E1000_WUFC_MAG) 2107 wol->wolopts |= WAKE_MAGIC; 2108 if (adapter->wol & E1000_WUFC_LNKC) 2109 wol->wolopts |= WAKE_PHY; 2110 } 2111 2112 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2113 { 2114 struct igb_adapter *adapter = netdev_priv(netdev); 2115 2116 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2117 return -EOPNOTSUPP; 2118 2119 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2120 return wol->wolopts ? -EOPNOTSUPP : 0; 2121 2122 /* these settings will always override what we currently have */ 2123 adapter->wol = 0; 2124 2125 if (wol->wolopts & WAKE_UCAST) 2126 adapter->wol |= E1000_WUFC_EX; 2127 if (wol->wolopts & WAKE_MCAST) 2128 adapter->wol |= E1000_WUFC_MC; 2129 if (wol->wolopts & WAKE_BCAST) 2130 adapter->wol |= E1000_WUFC_BC; 2131 if (wol->wolopts & WAKE_MAGIC) 2132 adapter->wol |= E1000_WUFC_MAG; 2133 if (wol->wolopts & WAKE_PHY) 2134 adapter->wol |= E1000_WUFC_LNKC; 2135 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2136 2137 return 0; 2138 } 2139 2140 /* bit defines for adapter->led_status */ 2141 #define IGB_LED_ON 0 2142 2143 static int igb_set_phys_id(struct net_device *netdev, 2144 enum ethtool_phys_id_state state) 2145 { 2146 struct igb_adapter *adapter = netdev_priv(netdev); 2147 struct e1000_hw *hw = &adapter->hw; 2148 2149 switch (state) { 2150 case ETHTOOL_ID_ACTIVE: 2151 igb_blink_led(hw); 2152 return 2; 2153 case ETHTOOL_ID_ON: 2154 igb_blink_led(hw); 2155 break; 2156 case ETHTOOL_ID_OFF: 2157 igb_led_off(hw); 2158 break; 2159 case ETHTOOL_ID_INACTIVE: 2160 igb_led_off(hw); 2161 clear_bit(IGB_LED_ON, &adapter->led_status); 2162 igb_cleanup_led(hw); 2163 break; 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int igb_set_coalesce(struct net_device *netdev, 2170 struct ethtool_coalesce *ec) 2171 { 2172 struct igb_adapter *adapter = netdev_priv(netdev); 2173 int i; 2174 2175 if (ec->rx_max_coalesced_frames || 2176 ec->rx_coalesce_usecs_irq || 2177 ec->rx_max_coalesced_frames_irq || 2178 ec->tx_max_coalesced_frames || 2179 ec->tx_coalesce_usecs_irq || 2180 ec->stats_block_coalesce_usecs || 2181 ec->use_adaptive_rx_coalesce || 2182 ec->use_adaptive_tx_coalesce || 2183 ec->pkt_rate_low || 2184 ec->rx_coalesce_usecs_low || 2185 ec->rx_max_coalesced_frames_low || 2186 ec->tx_coalesce_usecs_low || 2187 ec->tx_max_coalesced_frames_low || 2188 ec->pkt_rate_high || 2189 ec->rx_coalesce_usecs_high || 2190 ec->rx_max_coalesced_frames_high || 2191 ec->tx_coalesce_usecs_high || 2192 ec->tx_max_coalesced_frames_high || 2193 ec->rate_sample_interval) 2194 return -ENOTSUPP; 2195 2196 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2197 ((ec->rx_coalesce_usecs > 3) && 2198 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2199 (ec->rx_coalesce_usecs == 2)) 2200 return -EINVAL; 2201 2202 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2203 ((ec->tx_coalesce_usecs > 3) && 2204 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2205 (ec->tx_coalesce_usecs == 2)) 2206 return -EINVAL; 2207 2208 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2209 return -EINVAL; 2210 2211 /* If ITR is disabled, disable DMAC */ 2212 if (ec->rx_coalesce_usecs == 0) { 2213 if (adapter->flags & IGB_FLAG_DMAC) 2214 adapter->flags &= ~IGB_FLAG_DMAC; 2215 } 2216 2217 /* convert to rate of irq's per second */ 2218 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2219 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2220 else 2221 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2222 2223 /* convert to rate of irq's per second */ 2224 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2225 adapter->tx_itr_setting = adapter->rx_itr_setting; 2226 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2227 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2228 else 2229 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2230 2231 for (i = 0; i < adapter->num_q_vectors; i++) { 2232 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2233 q_vector->tx.work_limit = adapter->tx_work_limit; 2234 if (q_vector->rx.ring) 2235 q_vector->itr_val = adapter->rx_itr_setting; 2236 else 2237 q_vector->itr_val = adapter->tx_itr_setting; 2238 if (q_vector->itr_val && q_vector->itr_val <= 3) 2239 q_vector->itr_val = IGB_START_ITR; 2240 q_vector->set_itr = 1; 2241 } 2242 2243 return 0; 2244 } 2245 2246 static int igb_get_coalesce(struct net_device *netdev, 2247 struct ethtool_coalesce *ec) 2248 { 2249 struct igb_adapter *adapter = netdev_priv(netdev); 2250 2251 if (adapter->rx_itr_setting <= 3) 2252 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2253 else 2254 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2255 2256 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2257 if (adapter->tx_itr_setting <= 3) 2258 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2259 else 2260 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int igb_nway_reset(struct net_device *netdev) 2267 { 2268 struct igb_adapter *adapter = netdev_priv(netdev); 2269 if (netif_running(netdev)) 2270 igb_reinit_locked(adapter); 2271 return 0; 2272 } 2273 2274 static int igb_get_sset_count(struct net_device *netdev, int sset) 2275 { 2276 switch (sset) { 2277 case ETH_SS_STATS: 2278 return IGB_STATS_LEN; 2279 case ETH_SS_TEST: 2280 return IGB_TEST_LEN; 2281 case ETH_SS_PRIV_FLAGS: 2282 return IGB_PRIV_FLAGS_STR_LEN; 2283 default: 2284 return -ENOTSUPP; 2285 } 2286 } 2287 2288 static void igb_get_ethtool_stats(struct net_device *netdev, 2289 struct ethtool_stats *stats, u64 *data) 2290 { 2291 struct igb_adapter *adapter = netdev_priv(netdev); 2292 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2293 unsigned int start; 2294 struct igb_ring *ring; 2295 int i, j; 2296 char *p; 2297 2298 spin_lock(&adapter->stats64_lock); 2299 igb_update_stats(adapter); 2300 2301 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2302 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2303 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2304 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2305 } 2306 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2307 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2308 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2309 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2310 } 2311 for (j = 0; j < adapter->num_tx_queues; j++) { 2312 u64 restart2; 2313 2314 ring = adapter->tx_ring[j]; 2315 do { 2316 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2317 data[i] = ring->tx_stats.packets; 2318 data[i+1] = ring->tx_stats.bytes; 2319 data[i+2] = ring->tx_stats.restart_queue; 2320 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2321 do { 2322 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2323 restart2 = ring->tx_stats.restart_queue2; 2324 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2325 data[i+2] += restart2; 2326 2327 i += IGB_TX_QUEUE_STATS_LEN; 2328 } 2329 for (j = 0; j < adapter->num_rx_queues; j++) { 2330 ring = adapter->rx_ring[j]; 2331 do { 2332 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2333 data[i] = ring->rx_stats.packets; 2334 data[i+1] = ring->rx_stats.bytes; 2335 data[i+2] = ring->rx_stats.drops; 2336 data[i+3] = ring->rx_stats.csum_err; 2337 data[i+4] = ring->rx_stats.alloc_failed; 2338 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2339 i += IGB_RX_QUEUE_STATS_LEN; 2340 } 2341 spin_unlock(&adapter->stats64_lock); 2342 } 2343 2344 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2345 { 2346 struct igb_adapter *adapter = netdev_priv(netdev); 2347 u8 *p = data; 2348 int i; 2349 2350 switch (stringset) { 2351 case ETH_SS_TEST: 2352 memcpy(data, *igb_gstrings_test, 2353 IGB_TEST_LEN*ETH_GSTRING_LEN); 2354 break; 2355 case ETH_SS_STATS: 2356 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2357 memcpy(p, igb_gstrings_stats[i].stat_string, 2358 ETH_GSTRING_LEN); 2359 p += ETH_GSTRING_LEN; 2360 } 2361 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2362 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2363 ETH_GSTRING_LEN); 2364 p += ETH_GSTRING_LEN; 2365 } 2366 for (i = 0; i < adapter->num_tx_queues; i++) { 2367 sprintf(p, "tx_queue_%u_packets", i); 2368 p += ETH_GSTRING_LEN; 2369 sprintf(p, "tx_queue_%u_bytes", i); 2370 p += ETH_GSTRING_LEN; 2371 sprintf(p, "tx_queue_%u_restart", i); 2372 p += ETH_GSTRING_LEN; 2373 } 2374 for (i = 0; i < adapter->num_rx_queues; i++) { 2375 sprintf(p, "rx_queue_%u_packets", i); 2376 p += ETH_GSTRING_LEN; 2377 sprintf(p, "rx_queue_%u_bytes", i); 2378 p += ETH_GSTRING_LEN; 2379 sprintf(p, "rx_queue_%u_drops", i); 2380 p += ETH_GSTRING_LEN; 2381 sprintf(p, "rx_queue_%u_csum_err", i); 2382 p += ETH_GSTRING_LEN; 2383 sprintf(p, "rx_queue_%u_alloc_failed", i); 2384 p += ETH_GSTRING_LEN; 2385 } 2386 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2387 break; 2388 case ETH_SS_PRIV_FLAGS: 2389 memcpy(data, igb_priv_flags_strings, 2390 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 2391 break; 2392 } 2393 } 2394 2395 static int igb_get_ts_info(struct net_device *dev, 2396 struct ethtool_ts_info *info) 2397 { 2398 struct igb_adapter *adapter = netdev_priv(dev); 2399 2400 if (adapter->ptp_clock) 2401 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2402 else 2403 info->phc_index = -1; 2404 2405 switch (adapter->hw.mac.type) { 2406 case e1000_82575: 2407 info->so_timestamping = 2408 SOF_TIMESTAMPING_TX_SOFTWARE | 2409 SOF_TIMESTAMPING_RX_SOFTWARE | 2410 SOF_TIMESTAMPING_SOFTWARE; 2411 return 0; 2412 case e1000_82576: 2413 case e1000_82580: 2414 case e1000_i350: 2415 case e1000_i354: 2416 case e1000_i210: 2417 case e1000_i211: 2418 info->so_timestamping = 2419 SOF_TIMESTAMPING_TX_SOFTWARE | 2420 SOF_TIMESTAMPING_RX_SOFTWARE | 2421 SOF_TIMESTAMPING_SOFTWARE | 2422 SOF_TIMESTAMPING_TX_HARDWARE | 2423 SOF_TIMESTAMPING_RX_HARDWARE | 2424 SOF_TIMESTAMPING_RAW_HARDWARE; 2425 2426 info->tx_types = 2427 BIT(HWTSTAMP_TX_OFF) | 2428 BIT(HWTSTAMP_TX_ON); 2429 2430 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2431 2432 /* 82576 does not support timestamping all packets. */ 2433 if (adapter->hw.mac.type >= e1000_82580) 2434 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2435 else 2436 info->rx_filters |= 2437 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2438 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2439 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2440 2441 return 0; 2442 default: 2443 return -EOPNOTSUPP; 2444 } 2445 } 2446 2447 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2448 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2449 struct ethtool_rxnfc *cmd) 2450 { 2451 struct ethtool_rx_flow_spec *fsp = &cmd->fs; 2452 struct igb_nfc_filter *rule = NULL; 2453 2454 /* report total rule count */ 2455 cmd->data = IGB_MAX_RXNFC_FILTERS; 2456 2457 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2458 if (fsp->location <= rule->sw_idx) 2459 break; 2460 } 2461 2462 if (!rule || fsp->location != rule->sw_idx) 2463 return -EINVAL; 2464 2465 if (rule->filter.match_flags) { 2466 fsp->flow_type = ETHER_FLOW; 2467 fsp->ring_cookie = rule->action; 2468 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2469 fsp->h_u.ether_spec.h_proto = rule->filter.etype; 2470 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; 2471 } 2472 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) { 2473 fsp->flow_type |= FLOW_EXT; 2474 fsp->h_ext.vlan_tci = rule->filter.vlan_tci; 2475 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK); 2476 } 2477 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2478 ether_addr_copy(fsp->h_u.ether_spec.h_dest, 2479 rule->filter.dst_addr); 2480 /* As we only support matching by the full 2481 * mask, return the mask to userspace 2482 */ 2483 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest); 2484 } 2485 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2486 ether_addr_copy(fsp->h_u.ether_spec.h_source, 2487 rule->filter.src_addr); 2488 /* As we only support matching by the full 2489 * mask, return the mask to userspace 2490 */ 2491 eth_broadcast_addr(fsp->m_u.ether_spec.h_source); 2492 } 2493 2494 return 0; 2495 } 2496 return -EINVAL; 2497 } 2498 2499 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter, 2500 struct ethtool_rxnfc *cmd, 2501 u32 *rule_locs) 2502 { 2503 struct igb_nfc_filter *rule; 2504 int cnt = 0; 2505 2506 /* report total rule count */ 2507 cmd->data = IGB_MAX_RXNFC_FILTERS; 2508 2509 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2510 if (cnt == cmd->rule_cnt) 2511 return -EMSGSIZE; 2512 rule_locs[cnt] = rule->sw_idx; 2513 cnt++; 2514 } 2515 2516 cmd->rule_cnt = cnt; 2517 2518 return 0; 2519 } 2520 2521 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2522 struct ethtool_rxnfc *cmd) 2523 { 2524 cmd->data = 0; 2525 2526 /* Report default options for RSS on igb */ 2527 switch (cmd->flow_type) { 2528 case TCP_V4_FLOW: 2529 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2530 /* Fall through */ 2531 case UDP_V4_FLOW: 2532 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2533 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2534 /* Fall through */ 2535 case SCTP_V4_FLOW: 2536 case AH_ESP_V4_FLOW: 2537 case AH_V4_FLOW: 2538 case ESP_V4_FLOW: 2539 case IPV4_FLOW: 2540 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2541 break; 2542 case TCP_V6_FLOW: 2543 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2544 /* Fall through */ 2545 case UDP_V6_FLOW: 2546 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2547 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2548 /* Fall through */ 2549 case SCTP_V6_FLOW: 2550 case AH_ESP_V6_FLOW: 2551 case AH_V6_FLOW: 2552 case ESP_V6_FLOW: 2553 case IPV6_FLOW: 2554 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2555 break; 2556 default: 2557 return -EINVAL; 2558 } 2559 2560 return 0; 2561 } 2562 2563 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2564 u32 *rule_locs) 2565 { 2566 struct igb_adapter *adapter = netdev_priv(dev); 2567 int ret = -EOPNOTSUPP; 2568 2569 switch (cmd->cmd) { 2570 case ETHTOOL_GRXRINGS: 2571 cmd->data = adapter->num_rx_queues; 2572 ret = 0; 2573 break; 2574 case ETHTOOL_GRXCLSRLCNT: 2575 cmd->rule_cnt = adapter->nfc_filter_count; 2576 ret = 0; 2577 break; 2578 case ETHTOOL_GRXCLSRULE: 2579 ret = igb_get_ethtool_nfc_entry(adapter, cmd); 2580 break; 2581 case ETHTOOL_GRXCLSRLALL: 2582 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs); 2583 break; 2584 case ETHTOOL_GRXFH: 2585 ret = igb_get_rss_hash_opts(adapter, cmd); 2586 break; 2587 default: 2588 break; 2589 } 2590 2591 return ret; 2592 } 2593 2594 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2595 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2596 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2597 struct ethtool_rxnfc *nfc) 2598 { 2599 u32 flags = adapter->flags; 2600 2601 /* RSS does not support anything other than hashing 2602 * to queues on src and dst IPs and ports 2603 */ 2604 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2605 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2606 return -EINVAL; 2607 2608 switch (nfc->flow_type) { 2609 case TCP_V4_FLOW: 2610 case TCP_V6_FLOW: 2611 if (!(nfc->data & RXH_IP_SRC) || 2612 !(nfc->data & RXH_IP_DST) || 2613 !(nfc->data & RXH_L4_B_0_1) || 2614 !(nfc->data & RXH_L4_B_2_3)) 2615 return -EINVAL; 2616 break; 2617 case UDP_V4_FLOW: 2618 if (!(nfc->data & RXH_IP_SRC) || 2619 !(nfc->data & RXH_IP_DST)) 2620 return -EINVAL; 2621 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2622 case 0: 2623 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2624 break; 2625 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2626 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2627 break; 2628 default: 2629 return -EINVAL; 2630 } 2631 break; 2632 case UDP_V6_FLOW: 2633 if (!(nfc->data & RXH_IP_SRC) || 2634 !(nfc->data & RXH_IP_DST)) 2635 return -EINVAL; 2636 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2637 case 0: 2638 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2639 break; 2640 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2641 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2642 break; 2643 default: 2644 return -EINVAL; 2645 } 2646 break; 2647 case AH_ESP_V4_FLOW: 2648 case AH_V4_FLOW: 2649 case ESP_V4_FLOW: 2650 case SCTP_V4_FLOW: 2651 case AH_ESP_V6_FLOW: 2652 case AH_V6_FLOW: 2653 case ESP_V6_FLOW: 2654 case SCTP_V6_FLOW: 2655 if (!(nfc->data & RXH_IP_SRC) || 2656 !(nfc->data & RXH_IP_DST) || 2657 (nfc->data & RXH_L4_B_0_1) || 2658 (nfc->data & RXH_L4_B_2_3)) 2659 return -EINVAL; 2660 break; 2661 default: 2662 return -EINVAL; 2663 } 2664 2665 /* if we changed something we need to update flags */ 2666 if (flags != adapter->flags) { 2667 struct e1000_hw *hw = &adapter->hw; 2668 u32 mrqc = rd32(E1000_MRQC); 2669 2670 if ((flags & UDP_RSS_FLAGS) && 2671 !(adapter->flags & UDP_RSS_FLAGS)) 2672 dev_err(&adapter->pdev->dev, 2673 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2674 2675 adapter->flags = flags; 2676 2677 /* Perform hash on these packet types */ 2678 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2679 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2680 E1000_MRQC_RSS_FIELD_IPV6 | 2681 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2682 2683 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2684 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2685 2686 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2687 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2688 2689 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2690 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2691 2692 wr32(E1000_MRQC, mrqc); 2693 } 2694 2695 return 0; 2696 } 2697 2698 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter, 2699 struct igb_nfc_filter *input) 2700 { 2701 struct e1000_hw *hw = &adapter->hw; 2702 u8 i; 2703 u32 etqf; 2704 u16 etype; 2705 2706 /* find an empty etype filter register */ 2707 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { 2708 if (!adapter->etype_bitmap[i]) 2709 break; 2710 } 2711 if (i == MAX_ETYPE_FILTER) { 2712 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n"); 2713 return -EINVAL; 2714 } 2715 2716 adapter->etype_bitmap[i] = true; 2717 2718 etqf = rd32(E1000_ETQF(i)); 2719 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK); 2720 2721 etqf |= E1000_ETQF_FILTER_ENABLE; 2722 etqf &= ~E1000_ETQF_ETYPE_MASK; 2723 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2724 2725 etqf &= ~E1000_ETQF_QUEUE_MASK; 2726 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2727 & E1000_ETQF_QUEUE_MASK); 2728 etqf |= E1000_ETQF_QUEUE_ENABLE; 2729 2730 wr32(E1000_ETQF(i), etqf); 2731 2732 input->etype_reg_index = i; 2733 2734 return 0; 2735 } 2736 2737 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter, 2738 struct igb_nfc_filter *input) 2739 { 2740 struct e1000_hw *hw = &adapter->hw; 2741 u8 vlan_priority; 2742 u16 queue_index; 2743 u32 vlapqf; 2744 2745 vlapqf = rd32(E1000_VLAPQF); 2746 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2747 >> VLAN_PRIO_SHIFT; 2748 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2749 2750 /* check whether this vlan prio is already set */ 2751 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) && 2752 (queue_index != input->action)) { 2753 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n"); 2754 return -EEXIST; 2755 } 2756 2757 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority); 2758 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action); 2759 2760 wr32(E1000_VLAPQF, vlapqf); 2761 2762 return 0; 2763 } 2764 2765 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2766 { 2767 struct e1000_hw *hw = &adapter->hw; 2768 int err = -EINVAL; 2769 2770 if (hw->mac.type == e1000_i210 && 2771 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) { 2772 dev_err(&adapter->pdev->dev, 2773 "i210 doesn't support flow classification rules specifying only source addresses.\n"); 2774 return -EOPNOTSUPP; 2775 } 2776 2777 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2778 err = igb_rxnfc_write_etype_filter(adapter, input); 2779 if (err) 2780 return err; 2781 } 2782 2783 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2784 err = igb_add_mac_steering_filter(adapter, 2785 input->filter.dst_addr, 2786 input->action, 0); 2787 err = min_t(int, err, 0); 2788 if (err) 2789 return err; 2790 } 2791 2792 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2793 err = igb_add_mac_steering_filter(adapter, 2794 input->filter.src_addr, 2795 input->action, 2796 IGB_MAC_STATE_SRC_ADDR); 2797 err = min_t(int, err, 0); 2798 if (err) 2799 return err; 2800 } 2801 2802 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2803 err = igb_rxnfc_write_vlan_prio_filter(adapter, input); 2804 2805 return err; 2806 } 2807 2808 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter, 2809 u16 reg_index) 2810 { 2811 struct e1000_hw *hw = &adapter->hw; 2812 u32 etqf = rd32(E1000_ETQF(reg_index)); 2813 2814 etqf &= ~E1000_ETQF_QUEUE_ENABLE; 2815 etqf &= ~E1000_ETQF_QUEUE_MASK; 2816 etqf &= ~E1000_ETQF_FILTER_ENABLE; 2817 2818 wr32(E1000_ETQF(reg_index), etqf); 2819 2820 adapter->etype_bitmap[reg_index] = false; 2821 } 2822 2823 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter, 2824 u16 vlan_tci) 2825 { 2826 struct e1000_hw *hw = &adapter->hw; 2827 u8 vlan_priority; 2828 u32 vlapqf; 2829 2830 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2831 2832 vlapqf = rd32(E1000_VLAPQF); 2833 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority); 2834 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority, 2835 E1000_VLAPQF_QUEUE_MASK); 2836 2837 wr32(E1000_VLAPQF, vlapqf); 2838 } 2839 2840 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2841 { 2842 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) 2843 igb_clear_etype_filter_regs(adapter, 2844 input->etype_reg_index); 2845 2846 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2847 igb_clear_vlan_prio_filter(adapter, 2848 ntohs(input->filter.vlan_tci)); 2849 2850 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) 2851 igb_del_mac_steering_filter(adapter, input->filter.src_addr, 2852 input->action, 2853 IGB_MAC_STATE_SRC_ADDR); 2854 2855 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) 2856 igb_del_mac_steering_filter(adapter, input->filter.dst_addr, 2857 input->action, 0); 2858 2859 return 0; 2860 } 2861 2862 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter, 2863 struct igb_nfc_filter *input, 2864 u16 sw_idx) 2865 { 2866 struct igb_nfc_filter *rule, *parent; 2867 int err = -EINVAL; 2868 2869 parent = NULL; 2870 rule = NULL; 2871 2872 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2873 /* hash found, or no matching entry */ 2874 if (rule->sw_idx >= sw_idx) 2875 break; 2876 parent = rule; 2877 } 2878 2879 /* if there is an old rule occupying our place remove it */ 2880 if (rule && (rule->sw_idx == sw_idx)) { 2881 if (!input) 2882 err = igb_erase_filter(adapter, rule); 2883 2884 hlist_del(&rule->nfc_node); 2885 kfree(rule); 2886 adapter->nfc_filter_count--; 2887 } 2888 2889 /* If no input this was a delete, err should be 0 if a rule was 2890 * successfully found and removed from the list else -EINVAL 2891 */ 2892 if (!input) 2893 return err; 2894 2895 /* initialize node */ 2896 INIT_HLIST_NODE(&input->nfc_node); 2897 2898 /* add filter to the list */ 2899 if (parent) 2900 hlist_add_behind(&input->nfc_node, &parent->nfc_node); 2901 else 2902 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list); 2903 2904 /* update counts */ 2905 adapter->nfc_filter_count++; 2906 2907 return 0; 2908 } 2909 2910 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, 2911 struct ethtool_rxnfc *cmd) 2912 { 2913 struct net_device *netdev = adapter->netdev; 2914 struct ethtool_rx_flow_spec *fsp = 2915 (struct ethtool_rx_flow_spec *)&cmd->fs; 2916 struct igb_nfc_filter *input, *rule; 2917 int err = 0; 2918 2919 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 2920 return -EOPNOTSUPP; 2921 2922 /* Don't allow programming if the action is a queue greater than 2923 * the number of online Rx queues. 2924 */ 2925 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) || 2926 (fsp->ring_cookie >= adapter->num_rx_queues)) { 2927 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n"); 2928 return -EINVAL; 2929 } 2930 2931 /* Don't allow indexes to exist outside of available space */ 2932 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) { 2933 dev_err(&adapter->pdev->dev, "Location out of range\n"); 2934 return -EINVAL; 2935 } 2936 2937 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW) 2938 return -EINVAL; 2939 2940 input = kzalloc(sizeof(*input), GFP_KERNEL); 2941 if (!input) 2942 return -ENOMEM; 2943 2944 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) { 2945 input->filter.etype = fsp->h_u.ether_spec.h_proto; 2946 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE; 2947 } 2948 2949 /* Only support matching addresses by the full mask */ 2950 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) { 2951 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR; 2952 ether_addr_copy(input->filter.src_addr, 2953 fsp->h_u.ether_spec.h_source); 2954 } 2955 2956 /* Only support matching addresses by the full mask */ 2957 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) { 2958 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR; 2959 ether_addr_copy(input->filter.dst_addr, 2960 fsp->h_u.ether_spec.h_dest); 2961 } 2962 2963 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) { 2964 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) { 2965 err = -EINVAL; 2966 goto err_out; 2967 } 2968 input->filter.vlan_tci = fsp->h_ext.vlan_tci; 2969 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2970 } 2971 2972 input->action = fsp->ring_cookie; 2973 input->sw_idx = fsp->location; 2974 2975 spin_lock(&adapter->nfc_lock); 2976 2977 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2978 if (!memcmp(&input->filter, &rule->filter, 2979 sizeof(input->filter))) { 2980 err = -EEXIST; 2981 dev_err(&adapter->pdev->dev, 2982 "ethtool: this filter is already set\n"); 2983 goto err_out_w_lock; 2984 } 2985 } 2986 2987 err = igb_add_filter(adapter, input); 2988 if (err) 2989 goto err_out_w_lock; 2990 2991 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); 2992 2993 spin_unlock(&adapter->nfc_lock); 2994 return 0; 2995 2996 err_out_w_lock: 2997 spin_unlock(&adapter->nfc_lock); 2998 err_out: 2999 kfree(input); 3000 return err; 3001 } 3002 3003 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter, 3004 struct ethtool_rxnfc *cmd) 3005 { 3006 struct ethtool_rx_flow_spec *fsp = 3007 (struct ethtool_rx_flow_spec *)&cmd->fs; 3008 int err; 3009 3010 spin_lock(&adapter->nfc_lock); 3011 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location); 3012 spin_unlock(&adapter->nfc_lock); 3013 3014 return err; 3015 } 3016 3017 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3018 { 3019 struct igb_adapter *adapter = netdev_priv(dev); 3020 int ret = -EOPNOTSUPP; 3021 3022 switch (cmd->cmd) { 3023 case ETHTOOL_SRXFH: 3024 ret = igb_set_rss_hash_opt(adapter, cmd); 3025 break; 3026 case ETHTOOL_SRXCLSRLINS: 3027 ret = igb_add_ethtool_nfc_entry(adapter, cmd); 3028 break; 3029 case ETHTOOL_SRXCLSRLDEL: 3030 ret = igb_del_ethtool_nfc_entry(adapter, cmd); 3031 default: 3032 break; 3033 } 3034 3035 return ret; 3036 } 3037 3038 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3039 { 3040 struct igb_adapter *adapter = netdev_priv(netdev); 3041 struct e1000_hw *hw = &adapter->hw; 3042 u32 ret_val; 3043 u16 phy_data; 3044 3045 if ((hw->mac.type < e1000_i350) || 3046 (hw->phy.media_type != e1000_media_type_copper)) 3047 return -EOPNOTSUPP; 3048 3049 edata->supported = (SUPPORTED_1000baseT_Full | 3050 SUPPORTED_100baseT_Full); 3051 if (!hw->dev_spec._82575.eee_disable) 3052 edata->advertised = 3053 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 3054 3055 /* The IPCNFG and EEER registers are not supported on I354. */ 3056 if (hw->mac.type == e1000_i354) { 3057 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 3058 } else { 3059 u32 eeer; 3060 3061 eeer = rd32(E1000_EEER); 3062 3063 /* EEE status on negotiated link */ 3064 if (eeer & E1000_EEER_EEE_NEG) 3065 edata->eee_active = true; 3066 3067 if (eeer & E1000_EEER_TX_LPI_EN) 3068 edata->tx_lpi_enabled = true; 3069 } 3070 3071 /* EEE Link Partner Advertised */ 3072 switch (hw->mac.type) { 3073 case e1000_i350: 3074 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 3075 &phy_data); 3076 if (ret_val) 3077 return -ENODATA; 3078 3079 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3080 break; 3081 case e1000_i354: 3082 case e1000_i210: 3083 case e1000_i211: 3084 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 3085 E1000_EEE_LP_ADV_DEV_I210, 3086 &phy_data); 3087 if (ret_val) 3088 return -ENODATA; 3089 3090 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3091 3092 break; 3093 default: 3094 break; 3095 } 3096 3097 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 3098 3099 if ((hw->mac.type == e1000_i354) && 3100 (edata->eee_enabled)) 3101 edata->tx_lpi_enabled = true; 3102 3103 /* Report correct negotiated EEE status for devices that 3104 * wrongly report EEE at half-duplex 3105 */ 3106 if (adapter->link_duplex == HALF_DUPLEX) { 3107 edata->eee_enabled = false; 3108 edata->eee_active = false; 3109 edata->tx_lpi_enabled = false; 3110 edata->advertised &= ~edata->advertised; 3111 } 3112 3113 return 0; 3114 } 3115 3116 static int igb_set_eee(struct net_device *netdev, 3117 struct ethtool_eee *edata) 3118 { 3119 struct igb_adapter *adapter = netdev_priv(netdev); 3120 struct e1000_hw *hw = &adapter->hw; 3121 struct ethtool_eee eee_curr; 3122 bool adv1g_eee = true, adv100m_eee = true; 3123 s32 ret_val; 3124 3125 if ((hw->mac.type < e1000_i350) || 3126 (hw->phy.media_type != e1000_media_type_copper)) 3127 return -EOPNOTSUPP; 3128 3129 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 3130 3131 ret_val = igb_get_eee(netdev, &eee_curr); 3132 if (ret_val) 3133 return ret_val; 3134 3135 if (eee_curr.eee_enabled) { 3136 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 3137 dev_err(&adapter->pdev->dev, 3138 "Setting EEE tx-lpi is not supported\n"); 3139 return -EINVAL; 3140 } 3141 3142 /* Tx LPI timer is not implemented currently */ 3143 if (edata->tx_lpi_timer) { 3144 dev_err(&adapter->pdev->dev, 3145 "Setting EEE Tx LPI timer is not supported\n"); 3146 return -EINVAL; 3147 } 3148 3149 if (!edata->advertised || (edata->advertised & 3150 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 3151 dev_err(&adapter->pdev->dev, 3152 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 3153 return -EINVAL; 3154 } 3155 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 3156 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 3157 3158 } else if (!edata->eee_enabled) { 3159 dev_err(&adapter->pdev->dev, 3160 "Setting EEE options are not supported with EEE disabled\n"); 3161 return -EINVAL; 3162 } 3163 3164 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 3165 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 3166 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 3167 adapter->flags |= IGB_FLAG_EEE; 3168 3169 /* reset link */ 3170 if (netif_running(netdev)) 3171 igb_reinit_locked(adapter); 3172 else 3173 igb_reset(adapter); 3174 } 3175 3176 if (hw->mac.type == e1000_i354) 3177 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 3178 else 3179 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 3180 3181 if (ret_val) { 3182 dev_err(&adapter->pdev->dev, 3183 "Problem setting EEE advertisement options\n"); 3184 return -EINVAL; 3185 } 3186 3187 return 0; 3188 } 3189 3190 static int igb_get_module_info(struct net_device *netdev, 3191 struct ethtool_modinfo *modinfo) 3192 { 3193 struct igb_adapter *adapter = netdev_priv(netdev); 3194 struct e1000_hw *hw = &adapter->hw; 3195 u32 status = 0; 3196 u16 sff8472_rev, addr_mode; 3197 bool page_swap = false; 3198 3199 if ((hw->phy.media_type == e1000_media_type_copper) || 3200 (hw->phy.media_type == e1000_media_type_unknown)) 3201 return -EOPNOTSUPP; 3202 3203 /* Check whether we support SFF-8472 or not */ 3204 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 3205 if (status) 3206 return -EIO; 3207 3208 /* addressing mode is not supported */ 3209 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 3210 if (status) 3211 return -EIO; 3212 3213 /* addressing mode is not supported */ 3214 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 3215 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3216 page_swap = true; 3217 } 3218 3219 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 3220 /* We have an SFP, but it does not support SFF-8472 */ 3221 modinfo->type = ETH_MODULE_SFF_8079; 3222 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3223 } else { 3224 /* We have an SFP which supports a revision of SFF-8472 */ 3225 modinfo->type = ETH_MODULE_SFF_8472; 3226 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3227 } 3228 3229 return 0; 3230 } 3231 3232 static int igb_get_module_eeprom(struct net_device *netdev, 3233 struct ethtool_eeprom *ee, u8 *data) 3234 { 3235 struct igb_adapter *adapter = netdev_priv(netdev); 3236 struct e1000_hw *hw = &adapter->hw; 3237 u32 status = 0; 3238 u16 *dataword; 3239 u16 first_word, last_word; 3240 int i = 0; 3241 3242 if (ee->len == 0) 3243 return -EINVAL; 3244 3245 first_word = ee->offset >> 1; 3246 last_word = (ee->offset + ee->len - 1) >> 1; 3247 3248 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16), 3249 GFP_KERNEL); 3250 if (!dataword) 3251 return -ENOMEM; 3252 3253 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 3254 for (i = 0; i < last_word - first_word + 1; i++) { 3255 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 3256 &dataword[i]); 3257 if (status) { 3258 /* Error occurred while reading module */ 3259 kfree(dataword); 3260 return -EIO; 3261 } 3262 3263 be16_to_cpus(&dataword[i]); 3264 } 3265 3266 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 3267 kfree(dataword); 3268 3269 return 0; 3270 } 3271 3272 static int igb_ethtool_begin(struct net_device *netdev) 3273 { 3274 struct igb_adapter *adapter = netdev_priv(netdev); 3275 pm_runtime_get_sync(&adapter->pdev->dev); 3276 return 0; 3277 } 3278 3279 static void igb_ethtool_complete(struct net_device *netdev) 3280 { 3281 struct igb_adapter *adapter = netdev_priv(netdev); 3282 pm_runtime_put(&adapter->pdev->dev); 3283 } 3284 3285 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 3286 { 3287 return IGB_RETA_SIZE; 3288 } 3289 3290 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3291 u8 *hfunc) 3292 { 3293 struct igb_adapter *adapter = netdev_priv(netdev); 3294 int i; 3295 3296 if (hfunc) 3297 *hfunc = ETH_RSS_HASH_TOP; 3298 if (!indir) 3299 return 0; 3300 for (i = 0; i < IGB_RETA_SIZE; i++) 3301 indir[i] = adapter->rss_indir_tbl[i]; 3302 3303 return 0; 3304 } 3305 3306 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 3307 { 3308 struct e1000_hw *hw = &adapter->hw; 3309 u32 reg = E1000_RETA(0); 3310 u32 shift = 0; 3311 int i = 0; 3312 3313 switch (hw->mac.type) { 3314 case e1000_82575: 3315 shift = 6; 3316 break; 3317 case e1000_82576: 3318 /* 82576 supports 2 RSS queues for SR-IOV */ 3319 if (adapter->vfs_allocated_count) 3320 shift = 3; 3321 break; 3322 default: 3323 break; 3324 } 3325 3326 while (i < IGB_RETA_SIZE) { 3327 u32 val = 0; 3328 int j; 3329 3330 for (j = 3; j >= 0; j--) { 3331 val <<= 8; 3332 val |= adapter->rss_indir_tbl[i + j]; 3333 } 3334 3335 wr32(reg, val << shift); 3336 reg += 4; 3337 i += 4; 3338 } 3339 } 3340 3341 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 3342 const u8 *key, const u8 hfunc) 3343 { 3344 struct igb_adapter *adapter = netdev_priv(netdev); 3345 struct e1000_hw *hw = &adapter->hw; 3346 int i; 3347 u32 num_queues; 3348 3349 /* We do not allow change in unsupported parameters */ 3350 if (key || 3351 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3352 return -EOPNOTSUPP; 3353 if (!indir) 3354 return 0; 3355 3356 num_queues = adapter->rss_queues; 3357 3358 switch (hw->mac.type) { 3359 case e1000_82576: 3360 /* 82576 supports 2 RSS queues for SR-IOV */ 3361 if (adapter->vfs_allocated_count) 3362 num_queues = 2; 3363 break; 3364 default: 3365 break; 3366 } 3367 3368 /* Verify user input. */ 3369 for (i = 0; i < IGB_RETA_SIZE; i++) 3370 if (indir[i] >= num_queues) 3371 return -EINVAL; 3372 3373 3374 for (i = 0; i < IGB_RETA_SIZE; i++) 3375 adapter->rss_indir_tbl[i] = indir[i]; 3376 3377 igb_write_rss_indir_tbl(adapter); 3378 3379 return 0; 3380 } 3381 3382 static unsigned int igb_max_channels(struct igb_adapter *adapter) 3383 { 3384 return igb_get_max_rss_queues(adapter); 3385 } 3386 3387 static void igb_get_channels(struct net_device *netdev, 3388 struct ethtool_channels *ch) 3389 { 3390 struct igb_adapter *adapter = netdev_priv(netdev); 3391 3392 /* Report maximum channels */ 3393 ch->max_combined = igb_max_channels(adapter); 3394 3395 /* Report info for other vector */ 3396 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3397 ch->max_other = NON_Q_VECTORS; 3398 ch->other_count = NON_Q_VECTORS; 3399 } 3400 3401 ch->combined_count = adapter->rss_queues; 3402 } 3403 3404 static int igb_set_channels(struct net_device *netdev, 3405 struct ethtool_channels *ch) 3406 { 3407 struct igb_adapter *adapter = netdev_priv(netdev); 3408 unsigned int count = ch->combined_count; 3409 unsigned int max_combined = 0; 3410 3411 /* Verify they are not requesting separate vectors */ 3412 if (!count || ch->rx_count || ch->tx_count) 3413 return -EINVAL; 3414 3415 /* Verify other_count is valid and has not been changed */ 3416 if (ch->other_count != NON_Q_VECTORS) 3417 return -EINVAL; 3418 3419 /* Verify the number of channels doesn't exceed hw limits */ 3420 max_combined = igb_max_channels(adapter); 3421 if (count > max_combined) 3422 return -EINVAL; 3423 3424 if (count != adapter->rss_queues) { 3425 adapter->rss_queues = count; 3426 igb_set_flag_queue_pairs(adapter, max_combined); 3427 3428 /* Hardware has to reinitialize queues and interrupts to 3429 * match the new configuration. 3430 */ 3431 return igb_reinit_queues(adapter); 3432 } 3433 3434 return 0; 3435 } 3436 3437 static u32 igb_get_priv_flags(struct net_device *netdev) 3438 { 3439 struct igb_adapter *adapter = netdev_priv(netdev); 3440 u32 priv_flags = 0; 3441 3442 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3443 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX; 3444 3445 return priv_flags; 3446 } 3447 3448 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3449 { 3450 struct igb_adapter *adapter = netdev_priv(netdev); 3451 unsigned int flags = adapter->flags; 3452 3453 flags &= ~IGB_FLAG_RX_LEGACY; 3454 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX) 3455 flags |= IGB_FLAG_RX_LEGACY; 3456 3457 if (flags != adapter->flags) { 3458 adapter->flags = flags; 3459 3460 /* reset interface to repopulate queues */ 3461 if (netif_running(netdev)) 3462 igb_reinit_locked(adapter); 3463 } 3464 3465 return 0; 3466 } 3467 3468 static const struct ethtool_ops igb_ethtool_ops = { 3469 .get_drvinfo = igb_get_drvinfo, 3470 .get_regs_len = igb_get_regs_len, 3471 .get_regs = igb_get_regs, 3472 .get_wol = igb_get_wol, 3473 .set_wol = igb_set_wol, 3474 .get_msglevel = igb_get_msglevel, 3475 .set_msglevel = igb_set_msglevel, 3476 .nway_reset = igb_nway_reset, 3477 .get_link = igb_get_link, 3478 .get_eeprom_len = igb_get_eeprom_len, 3479 .get_eeprom = igb_get_eeprom, 3480 .set_eeprom = igb_set_eeprom, 3481 .get_ringparam = igb_get_ringparam, 3482 .set_ringparam = igb_set_ringparam, 3483 .get_pauseparam = igb_get_pauseparam, 3484 .set_pauseparam = igb_set_pauseparam, 3485 .self_test = igb_diag_test, 3486 .get_strings = igb_get_strings, 3487 .set_phys_id = igb_set_phys_id, 3488 .get_sset_count = igb_get_sset_count, 3489 .get_ethtool_stats = igb_get_ethtool_stats, 3490 .get_coalesce = igb_get_coalesce, 3491 .set_coalesce = igb_set_coalesce, 3492 .get_ts_info = igb_get_ts_info, 3493 .get_rxnfc = igb_get_rxnfc, 3494 .set_rxnfc = igb_set_rxnfc, 3495 .get_eee = igb_get_eee, 3496 .set_eee = igb_set_eee, 3497 .get_module_info = igb_get_module_info, 3498 .get_module_eeprom = igb_get_module_eeprom, 3499 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3500 .get_rxfh = igb_get_rxfh, 3501 .set_rxfh = igb_set_rxfh, 3502 .get_channels = igb_get_channels, 3503 .set_channels = igb_set_channels, 3504 .get_priv_flags = igb_get_priv_flags, 3505 .set_priv_flags = igb_set_priv_flags, 3506 .begin = igb_ethtool_begin, 3507 .complete = igb_ethtool_complete, 3508 .get_link_ksettings = igb_get_link_ksettings, 3509 .set_link_ksettings = igb_set_link_ksettings, 3510 }; 3511 3512 void igb_set_ethtool_ops(struct net_device *netdev) 3513 { 3514 netdev->ethtool_ops = &igb_ethtool_ops; 3515 } 3516