1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* ethtool support for igb */ 25 26 #include <linux/vmalloc.h> 27 #include <linux/netdevice.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/interrupt.h> 31 #include <linux/if_ether.h> 32 #include <linux/ethtool.h> 33 #include <linux/sched.h> 34 #include <linux/slab.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/highmem.h> 37 #include <linux/mdio.h> 38 39 #include "igb.h" 40 41 struct igb_stats { 42 char stat_string[ETH_GSTRING_LEN]; 43 int sizeof_stat; 44 int stat_offset; 45 }; 46 47 #define IGB_STAT(_name, _stat) { \ 48 .stat_string = _name, \ 49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 50 .stat_offset = offsetof(struct igb_adapter, _stat) \ 51 } 52 static const struct igb_stats igb_gstrings_stats[] = { 53 IGB_STAT("rx_packets", stats.gprc), 54 IGB_STAT("tx_packets", stats.gptc), 55 IGB_STAT("rx_bytes", stats.gorc), 56 IGB_STAT("tx_bytes", stats.gotc), 57 IGB_STAT("rx_broadcast", stats.bprc), 58 IGB_STAT("tx_broadcast", stats.bptc), 59 IGB_STAT("rx_multicast", stats.mprc), 60 IGB_STAT("tx_multicast", stats.mptc), 61 IGB_STAT("multicast", stats.mprc), 62 IGB_STAT("collisions", stats.colc), 63 IGB_STAT("rx_crc_errors", stats.crcerrs), 64 IGB_STAT("rx_no_buffer_count", stats.rnbc), 65 IGB_STAT("rx_missed_errors", stats.mpc), 66 IGB_STAT("tx_aborted_errors", stats.ecol), 67 IGB_STAT("tx_carrier_errors", stats.tncrs), 68 IGB_STAT("tx_window_errors", stats.latecol), 69 IGB_STAT("tx_abort_late_coll", stats.latecol), 70 IGB_STAT("tx_deferred_ok", stats.dc), 71 IGB_STAT("tx_single_coll_ok", stats.scc), 72 IGB_STAT("tx_multi_coll_ok", stats.mcc), 73 IGB_STAT("tx_timeout_count", tx_timeout_count), 74 IGB_STAT("rx_long_length_errors", stats.roc), 75 IGB_STAT("rx_short_length_errors", stats.ruc), 76 IGB_STAT("rx_align_errors", stats.algnerrc), 77 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 79 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 81 IGB_STAT("tx_flow_control_xon", stats.xontxc), 82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 83 IGB_STAT("rx_long_byte_count", stats.gorc), 84 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 85 IGB_STAT("tx_smbus", stats.mgptc), 86 IGB_STAT("rx_smbus", stats.mgprc), 87 IGB_STAT("dropped_smbus", stats.mgpdc), 88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 94 }; 95 96 #define IGB_NETDEV_STAT(_net_stat) { \ 97 .stat_string = __stringify(_net_stat), \ 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 100 } 101 static const struct igb_stats igb_gstrings_net_stats[] = { 102 IGB_NETDEV_STAT(rx_errors), 103 IGB_NETDEV_STAT(tx_errors), 104 IGB_NETDEV_STAT(tx_dropped), 105 IGB_NETDEV_STAT(rx_length_errors), 106 IGB_NETDEV_STAT(rx_over_errors), 107 IGB_NETDEV_STAT(rx_frame_errors), 108 IGB_NETDEV_STAT(rx_fifo_errors), 109 IGB_NETDEV_STAT(tx_fifo_errors), 110 IGB_NETDEV_STAT(tx_heartbeat_errors) 111 }; 112 113 #define IGB_GLOBAL_STATS_LEN \ 114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 115 #define IGB_NETDEV_STATS_LEN \ 116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 117 #define IGB_RX_QUEUE_STATS_LEN \ 118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 119 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 121 122 #define IGB_QUEUE_STATS_LEN \ 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 124 IGB_RX_QUEUE_STATS_LEN) + \ 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 126 IGB_TX_QUEUE_STATS_LEN)) 127 #define IGB_STATS_LEN \ 128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 129 130 enum igb_diagnostics_results { 131 TEST_REG = 0, 132 TEST_EEP, 133 TEST_IRQ, 134 TEST_LOOP, 135 TEST_LINK 136 }; 137 138 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 139 [TEST_REG] = "Register test (offline)", 140 [TEST_EEP] = "Eeprom test (offline)", 141 [TEST_IRQ] = "Interrupt test (offline)", 142 [TEST_LOOP] = "Loopback test (offline)", 143 [TEST_LINK] = "Link test (on/offline)" 144 }; 145 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 146 147 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 148 { 149 struct igb_adapter *adapter = netdev_priv(netdev); 150 struct e1000_hw *hw = &adapter->hw; 151 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 152 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 153 u32 status; 154 u32 speed; 155 156 status = rd32(E1000_STATUS); 157 if (hw->phy.media_type == e1000_media_type_copper) { 158 159 ecmd->supported = (SUPPORTED_10baseT_Half | 160 SUPPORTED_10baseT_Full | 161 SUPPORTED_100baseT_Half | 162 SUPPORTED_100baseT_Full | 163 SUPPORTED_1000baseT_Full| 164 SUPPORTED_Autoneg | 165 SUPPORTED_TP | 166 SUPPORTED_Pause); 167 ecmd->advertising = ADVERTISED_TP; 168 169 if (hw->mac.autoneg == 1) { 170 ecmd->advertising |= ADVERTISED_Autoneg; 171 /* the e1000 autoneg seems to match ethtool nicely */ 172 ecmd->advertising |= hw->phy.autoneg_advertised; 173 } 174 175 ecmd->port = PORT_TP; 176 ecmd->phy_address = hw->phy.addr; 177 ecmd->transceiver = XCVR_INTERNAL; 178 } else { 179 ecmd->supported = (SUPPORTED_FIBRE | 180 SUPPORTED_1000baseKX_Full | 181 SUPPORTED_Autoneg | 182 SUPPORTED_Pause); 183 ecmd->advertising = (ADVERTISED_FIBRE | 184 ADVERTISED_1000baseKX_Full); 185 if (hw->mac.type == e1000_i354) { 186 if ((hw->device_id == 187 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 188 !(status & E1000_STATUS_2P5_SKU_OVER)) { 189 ecmd->supported |= SUPPORTED_2500baseX_Full; 190 ecmd->supported &= 191 ~SUPPORTED_1000baseKX_Full; 192 ecmd->advertising |= ADVERTISED_2500baseX_Full; 193 ecmd->advertising &= 194 ~ADVERTISED_1000baseKX_Full; 195 } 196 } 197 if (eth_flags->e100_base_fx) { 198 ecmd->supported |= SUPPORTED_100baseT_Full; 199 ecmd->advertising |= ADVERTISED_100baseT_Full; 200 } 201 if (hw->mac.autoneg == 1) 202 ecmd->advertising |= ADVERTISED_Autoneg; 203 204 ecmd->port = PORT_FIBRE; 205 ecmd->transceiver = XCVR_EXTERNAL; 206 } 207 if (hw->mac.autoneg != 1) 208 ecmd->advertising &= ~(ADVERTISED_Pause | 209 ADVERTISED_Asym_Pause); 210 211 switch (hw->fc.requested_mode) { 212 case e1000_fc_full: 213 ecmd->advertising |= ADVERTISED_Pause; 214 break; 215 case e1000_fc_rx_pause: 216 ecmd->advertising |= (ADVERTISED_Pause | 217 ADVERTISED_Asym_Pause); 218 break; 219 case e1000_fc_tx_pause: 220 ecmd->advertising |= ADVERTISED_Asym_Pause; 221 break; 222 default: 223 ecmd->advertising &= ~(ADVERTISED_Pause | 224 ADVERTISED_Asym_Pause); 225 } 226 if (status & E1000_STATUS_LU) { 227 if ((status & E1000_STATUS_2P5_SKU) && 228 !(status & E1000_STATUS_2P5_SKU_OVER)) { 229 speed = SPEED_2500; 230 } else if (status & E1000_STATUS_SPEED_1000) { 231 speed = SPEED_1000; 232 } else if (status & E1000_STATUS_SPEED_100) { 233 speed = SPEED_100; 234 } else { 235 speed = SPEED_10; 236 } 237 if ((status & E1000_STATUS_FD) || 238 hw->phy.media_type != e1000_media_type_copper) 239 ecmd->duplex = DUPLEX_FULL; 240 else 241 ecmd->duplex = DUPLEX_HALF; 242 } else { 243 speed = SPEED_UNKNOWN; 244 ecmd->duplex = DUPLEX_UNKNOWN; 245 } 246 ethtool_cmd_speed_set(ecmd, speed); 247 if ((hw->phy.media_type == e1000_media_type_fiber) || 248 hw->mac.autoneg) 249 ecmd->autoneg = AUTONEG_ENABLE; 250 else 251 ecmd->autoneg = AUTONEG_DISABLE; 252 253 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 254 if (hw->phy.media_type == e1000_media_type_copper) 255 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 256 ETH_TP_MDI; 257 else 258 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 259 260 if (hw->phy.mdix == AUTO_ALL_MODES) 261 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 262 else 263 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; 264 265 return 0; 266 } 267 268 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 269 { 270 struct igb_adapter *adapter = netdev_priv(netdev); 271 struct e1000_hw *hw = &adapter->hw; 272 273 /* When SoL/IDER sessions are active, autoneg/speed/duplex 274 * cannot be changed 275 */ 276 if (igb_check_reset_block(hw)) { 277 dev_err(&adapter->pdev->dev, 278 "Cannot change link characteristics when SoL/IDER is active.\n"); 279 return -EINVAL; 280 } 281 282 /* MDI setting is only allowed when autoneg enabled because 283 * some hardware doesn't allow MDI setting when speed or 284 * duplex is forced. 285 */ 286 if (ecmd->eth_tp_mdix_ctrl) { 287 if (hw->phy.media_type != e1000_media_type_copper) 288 return -EOPNOTSUPP; 289 290 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 291 (ecmd->autoneg != AUTONEG_ENABLE)) { 292 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 293 return -EINVAL; 294 } 295 } 296 297 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 298 usleep_range(1000, 2000); 299 300 if (ecmd->autoneg == AUTONEG_ENABLE) { 301 hw->mac.autoneg = 1; 302 if (hw->phy.media_type == e1000_media_type_fiber) { 303 hw->phy.autoneg_advertised = ecmd->advertising | 304 ADVERTISED_FIBRE | 305 ADVERTISED_Autoneg; 306 switch (adapter->link_speed) { 307 case SPEED_2500: 308 hw->phy.autoneg_advertised = 309 ADVERTISED_2500baseX_Full; 310 break; 311 case SPEED_1000: 312 hw->phy.autoneg_advertised = 313 ADVERTISED_1000baseT_Full; 314 break; 315 case SPEED_100: 316 hw->phy.autoneg_advertised = 317 ADVERTISED_100baseT_Full; 318 break; 319 default: 320 break; 321 } 322 } else { 323 hw->phy.autoneg_advertised = ecmd->advertising | 324 ADVERTISED_TP | 325 ADVERTISED_Autoneg; 326 } 327 ecmd->advertising = hw->phy.autoneg_advertised; 328 if (adapter->fc_autoneg) 329 hw->fc.requested_mode = e1000_fc_default; 330 } else { 331 u32 speed = ethtool_cmd_speed(ecmd); 332 /* calling this overrides forced MDI setting */ 333 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 334 clear_bit(__IGB_RESETTING, &adapter->state); 335 return -EINVAL; 336 } 337 } 338 339 /* MDI-X => 2; MDI => 1; Auto => 3 */ 340 if (ecmd->eth_tp_mdix_ctrl) { 341 /* fix up the value for auto (3 => 0) as zero is mapped 342 * internally to auto 343 */ 344 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 345 hw->phy.mdix = AUTO_ALL_MODES; 346 else 347 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl; 348 } 349 350 /* reset the link */ 351 if (netif_running(adapter->netdev)) { 352 igb_down(adapter); 353 igb_up(adapter); 354 } else 355 igb_reset(adapter); 356 357 clear_bit(__IGB_RESETTING, &adapter->state); 358 return 0; 359 } 360 361 static u32 igb_get_link(struct net_device *netdev) 362 { 363 struct igb_adapter *adapter = netdev_priv(netdev); 364 struct e1000_mac_info *mac = &adapter->hw.mac; 365 366 /* If the link is not reported up to netdev, interrupts are disabled, 367 * and so the physical link state may have changed since we last 368 * looked. Set get_link_status to make sure that the true link 369 * state is interrogated, rather than pulling a cached and possibly 370 * stale link state from the driver. 371 */ 372 if (!netif_carrier_ok(netdev)) 373 mac->get_link_status = 1; 374 375 return igb_has_link(adapter); 376 } 377 378 static void igb_get_pauseparam(struct net_device *netdev, 379 struct ethtool_pauseparam *pause) 380 { 381 struct igb_adapter *adapter = netdev_priv(netdev); 382 struct e1000_hw *hw = &adapter->hw; 383 384 pause->autoneg = 385 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 386 387 if (hw->fc.current_mode == e1000_fc_rx_pause) 388 pause->rx_pause = 1; 389 else if (hw->fc.current_mode == e1000_fc_tx_pause) 390 pause->tx_pause = 1; 391 else if (hw->fc.current_mode == e1000_fc_full) { 392 pause->rx_pause = 1; 393 pause->tx_pause = 1; 394 } 395 } 396 397 static int igb_set_pauseparam(struct net_device *netdev, 398 struct ethtool_pauseparam *pause) 399 { 400 struct igb_adapter *adapter = netdev_priv(netdev); 401 struct e1000_hw *hw = &adapter->hw; 402 int retval = 0; 403 404 /* 100basefx does not support setting link flow control */ 405 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 406 return -EINVAL; 407 408 adapter->fc_autoneg = pause->autoneg; 409 410 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 411 usleep_range(1000, 2000); 412 413 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 414 hw->fc.requested_mode = e1000_fc_default; 415 if (netif_running(adapter->netdev)) { 416 igb_down(adapter); 417 igb_up(adapter); 418 } else { 419 igb_reset(adapter); 420 } 421 } else { 422 if (pause->rx_pause && pause->tx_pause) 423 hw->fc.requested_mode = e1000_fc_full; 424 else if (pause->rx_pause && !pause->tx_pause) 425 hw->fc.requested_mode = e1000_fc_rx_pause; 426 else if (!pause->rx_pause && pause->tx_pause) 427 hw->fc.requested_mode = e1000_fc_tx_pause; 428 else if (!pause->rx_pause && !pause->tx_pause) 429 hw->fc.requested_mode = e1000_fc_none; 430 431 hw->fc.current_mode = hw->fc.requested_mode; 432 433 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 434 igb_force_mac_fc(hw) : igb_setup_link(hw)); 435 } 436 437 clear_bit(__IGB_RESETTING, &adapter->state); 438 return retval; 439 } 440 441 static u32 igb_get_msglevel(struct net_device *netdev) 442 { 443 struct igb_adapter *adapter = netdev_priv(netdev); 444 return adapter->msg_enable; 445 } 446 447 static void igb_set_msglevel(struct net_device *netdev, u32 data) 448 { 449 struct igb_adapter *adapter = netdev_priv(netdev); 450 adapter->msg_enable = data; 451 } 452 453 static int igb_get_regs_len(struct net_device *netdev) 454 { 455 #define IGB_REGS_LEN 739 456 return IGB_REGS_LEN * sizeof(u32); 457 } 458 459 static void igb_get_regs(struct net_device *netdev, 460 struct ethtool_regs *regs, void *p) 461 { 462 struct igb_adapter *adapter = netdev_priv(netdev); 463 struct e1000_hw *hw = &adapter->hw; 464 u32 *regs_buff = p; 465 u8 i; 466 467 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 468 469 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 470 471 /* General Registers */ 472 regs_buff[0] = rd32(E1000_CTRL); 473 regs_buff[1] = rd32(E1000_STATUS); 474 regs_buff[2] = rd32(E1000_CTRL_EXT); 475 regs_buff[3] = rd32(E1000_MDIC); 476 regs_buff[4] = rd32(E1000_SCTL); 477 regs_buff[5] = rd32(E1000_CONNSW); 478 regs_buff[6] = rd32(E1000_VET); 479 regs_buff[7] = rd32(E1000_LEDCTL); 480 regs_buff[8] = rd32(E1000_PBA); 481 regs_buff[9] = rd32(E1000_PBS); 482 regs_buff[10] = rd32(E1000_FRTIMER); 483 regs_buff[11] = rd32(E1000_TCPTIMER); 484 485 /* NVM Register */ 486 regs_buff[12] = rd32(E1000_EECD); 487 488 /* Interrupt */ 489 /* Reading EICS for EICR because they read the 490 * same but EICS does not clear on read 491 */ 492 regs_buff[13] = rd32(E1000_EICS); 493 regs_buff[14] = rd32(E1000_EICS); 494 regs_buff[15] = rd32(E1000_EIMS); 495 regs_buff[16] = rd32(E1000_EIMC); 496 regs_buff[17] = rd32(E1000_EIAC); 497 regs_buff[18] = rd32(E1000_EIAM); 498 /* Reading ICS for ICR because they read the 499 * same but ICS does not clear on read 500 */ 501 regs_buff[19] = rd32(E1000_ICS); 502 regs_buff[20] = rd32(E1000_ICS); 503 regs_buff[21] = rd32(E1000_IMS); 504 regs_buff[22] = rd32(E1000_IMC); 505 regs_buff[23] = rd32(E1000_IAC); 506 regs_buff[24] = rd32(E1000_IAM); 507 regs_buff[25] = rd32(E1000_IMIRVP); 508 509 /* Flow Control */ 510 regs_buff[26] = rd32(E1000_FCAL); 511 regs_buff[27] = rd32(E1000_FCAH); 512 regs_buff[28] = rd32(E1000_FCTTV); 513 regs_buff[29] = rd32(E1000_FCRTL); 514 regs_buff[30] = rd32(E1000_FCRTH); 515 regs_buff[31] = rd32(E1000_FCRTV); 516 517 /* Receive */ 518 regs_buff[32] = rd32(E1000_RCTL); 519 regs_buff[33] = rd32(E1000_RXCSUM); 520 regs_buff[34] = rd32(E1000_RLPML); 521 regs_buff[35] = rd32(E1000_RFCTL); 522 regs_buff[36] = rd32(E1000_MRQC); 523 regs_buff[37] = rd32(E1000_VT_CTL); 524 525 /* Transmit */ 526 regs_buff[38] = rd32(E1000_TCTL); 527 regs_buff[39] = rd32(E1000_TCTL_EXT); 528 regs_buff[40] = rd32(E1000_TIPG); 529 regs_buff[41] = rd32(E1000_DTXCTL); 530 531 /* Wake Up */ 532 regs_buff[42] = rd32(E1000_WUC); 533 regs_buff[43] = rd32(E1000_WUFC); 534 regs_buff[44] = rd32(E1000_WUS); 535 regs_buff[45] = rd32(E1000_IPAV); 536 regs_buff[46] = rd32(E1000_WUPL); 537 538 /* MAC */ 539 regs_buff[47] = rd32(E1000_PCS_CFG0); 540 regs_buff[48] = rd32(E1000_PCS_LCTL); 541 regs_buff[49] = rd32(E1000_PCS_LSTAT); 542 regs_buff[50] = rd32(E1000_PCS_ANADV); 543 regs_buff[51] = rd32(E1000_PCS_LPAB); 544 regs_buff[52] = rd32(E1000_PCS_NPTX); 545 regs_buff[53] = rd32(E1000_PCS_LPABNP); 546 547 /* Statistics */ 548 regs_buff[54] = adapter->stats.crcerrs; 549 regs_buff[55] = adapter->stats.algnerrc; 550 regs_buff[56] = adapter->stats.symerrs; 551 regs_buff[57] = adapter->stats.rxerrc; 552 regs_buff[58] = adapter->stats.mpc; 553 regs_buff[59] = adapter->stats.scc; 554 regs_buff[60] = adapter->stats.ecol; 555 regs_buff[61] = adapter->stats.mcc; 556 regs_buff[62] = adapter->stats.latecol; 557 regs_buff[63] = adapter->stats.colc; 558 regs_buff[64] = adapter->stats.dc; 559 regs_buff[65] = adapter->stats.tncrs; 560 regs_buff[66] = adapter->stats.sec; 561 regs_buff[67] = adapter->stats.htdpmc; 562 regs_buff[68] = adapter->stats.rlec; 563 regs_buff[69] = adapter->stats.xonrxc; 564 regs_buff[70] = adapter->stats.xontxc; 565 regs_buff[71] = adapter->stats.xoffrxc; 566 regs_buff[72] = adapter->stats.xofftxc; 567 regs_buff[73] = adapter->stats.fcruc; 568 regs_buff[74] = adapter->stats.prc64; 569 regs_buff[75] = adapter->stats.prc127; 570 regs_buff[76] = adapter->stats.prc255; 571 regs_buff[77] = adapter->stats.prc511; 572 regs_buff[78] = adapter->stats.prc1023; 573 regs_buff[79] = adapter->stats.prc1522; 574 regs_buff[80] = adapter->stats.gprc; 575 regs_buff[81] = adapter->stats.bprc; 576 regs_buff[82] = adapter->stats.mprc; 577 regs_buff[83] = adapter->stats.gptc; 578 regs_buff[84] = adapter->stats.gorc; 579 regs_buff[86] = adapter->stats.gotc; 580 regs_buff[88] = adapter->stats.rnbc; 581 regs_buff[89] = adapter->stats.ruc; 582 regs_buff[90] = adapter->stats.rfc; 583 regs_buff[91] = adapter->stats.roc; 584 regs_buff[92] = adapter->stats.rjc; 585 regs_buff[93] = adapter->stats.mgprc; 586 regs_buff[94] = adapter->stats.mgpdc; 587 regs_buff[95] = adapter->stats.mgptc; 588 regs_buff[96] = adapter->stats.tor; 589 regs_buff[98] = adapter->stats.tot; 590 regs_buff[100] = adapter->stats.tpr; 591 regs_buff[101] = adapter->stats.tpt; 592 regs_buff[102] = adapter->stats.ptc64; 593 regs_buff[103] = adapter->stats.ptc127; 594 regs_buff[104] = adapter->stats.ptc255; 595 regs_buff[105] = adapter->stats.ptc511; 596 regs_buff[106] = adapter->stats.ptc1023; 597 regs_buff[107] = adapter->stats.ptc1522; 598 regs_buff[108] = adapter->stats.mptc; 599 regs_buff[109] = adapter->stats.bptc; 600 regs_buff[110] = adapter->stats.tsctc; 601 regs_buff[111] = adapter->stats.iac; 602 regs_buff[112] = adapter->stats.rpthc; 603 regs_buff[113] = adapter->stats.hgptc; 604 regs_buff[114] = adapter->stats.hgorc; 605 regs_buff[116] = adapter->stats.hgotc; 606 regs_buff[118] = adapter->stats.lenerrs; 607 regs_buff[119] = adapter->stats.scvpc; 608 regs_buff[120] = adapter->stats.hrmpc; 609 610 for (i = 0; i < 4; i++) 611 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 612 for (i = 0; i < 4; i++) 613 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 614 for (i = 0; i < 4; i++) 615 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 616 for (i = 0; i < 4; i++) 617 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 618 for (i = 0; i < 4; i++) 619 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 620 for (i = 0; i < 4; i++) 621 regs_buff[141 + i] = rd32(E1000_RDH(i)); 622 for (i = 0; i < 4; i++) 623 regs_buff[145 + i] = rd32(E1000_RDT(i)); 624 for (i = 0; i < 4; i++) 625 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 626 627 for (i = 0; i < 10; i++) 628 regs_buff[153 + i] = rd32(E1000_EITR(i)); 629 for (i = 0; i < 8; i++) 630 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 631 for (i = 0; i < 8; i++) 632 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 633 for (i = 0; i < 16; i++) 634 regs_buff[179 + i] = rd32(E1000_RAL(i)); 635 for (i = 0; i < 16; i++) 636 regs_buff[195 + i] = rd32(E1000_RAH(i)); 637 638 for (i = 0; i < 4; i++) 639 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 640 for (i = 0; i < 4; i++) 641 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 642 for (i = 0; i < 4; i++) 643 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 644 for (i = 0; i < 4; i++) 645 regs_buff[223 + i] = rd32(E1000_TDH(i)); 646 for (i = 0; i < 4; i++) 647 regs_buff[227 + i] = rd32(E1000_TDT(i)); 648 for (i = 0; i < 4; i++) 649 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 650 for (i = 0; i < 4; i++) 651 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 652 for (i = 0; i < 4; i++) 653 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 654 for (i = 0; i < 4; i++) 655 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 656 657 for (i = 0; i < 4; i++) 658 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 659 for (i = 0; i < 4; i++) 660 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 661 for (i = 0; i < 32; i++) 662 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 663 for (i = 0; i < 128; i++) 664 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 665 for (i = 0; i < 128; i++) 666 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 667 for (i = 0; i < 4; i++) 668 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 669 670 regs_buff[547] = rd32(E1000_TDFH); 671 regs_buff[548] = rd32(E1000_TDFT); 672 regs_buff[549] = rd32(E1000_TDFHS); 673 regs_buff[550] = rd32(E1000_TDFPC); 674 675 if (hw->mac.type > e1000_82580) { 676 regs_buff[551] = adapter->stats.o2bgptc; 677 regs_buff[552] = adapter->stats.b2ospc; 678 regs_buff[553] = adapter->stats.o2bspc; 679 regs_buff[554] = adapter->stats.b2ogprc; 680 } 681 682 if (hw->mac.type != e1000_82576) 683 return; 684 for (i = 0; i < 12; i++) 685 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 686 for (i = 0; i < 4; i++) 687 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 688 for (i = 0; i < 12; i++) 689 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 690 for (i = 0; i < 12; i++) 691 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 692 for (i = 0; i < 12; i++) 693 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 694 for (i = 0; i < 12; i++) 695 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 696 for (i = 0; i < 12; i++) 697 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 698 for (i = 0; i < 12; i++) 699 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 700 701 for (i = 0; i < 12; i++) 702 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 703 for (i = 0; i < 12; i++) 704 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 705 for (i = 0; i < 12; i++) 706 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 713 for (i = 0; i < 12; i++) 714 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 715 for (i = 0; i < 12; i++) 716 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 717 } 718 719 static int igb_get_eeprom_len(struct net_device *netdev) 720 { 721 struct igb_adapter *adapter = netdev_priv(netdev); 722 return adapter->hw.nvm.word_size * 2; 723 } 724 725 static int igb_get_eeprom(struct net_device *netdev, 726 struct ethtool_eeprom *eeprom, u8 *bytes) 727 { 728 struct igb_adapter *adapter = netdev_priv(netdev); 729 struct e1000_hw *hw = &adapter->hw; 730 u16 *eeprom_buff; 731 int first_word, last_word; 732 int ret_val = 0; 733 u16 i; 734 735 if (eeprom->len == 0) 736 return -EINVAL; 737 738 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 739 740 first_word = eeprom->offset >> 1; 741 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 742 743 eeprom_buff = kmalloc(sizeof(u16) * 744 (last_word - first_word + 1), GFP_KERNEL); 745 if (!eeprom_buff) 746 return -ENOMEM; 747 748 if (hw->nvm.type == e1000_nvm_eeprom_spi) 749 ret_val = hw->nvm.ops.read(hw, first_word, 750 last_word - first_word + 1, 751 eeprom_buff); 752 else { 753 for (i = 0; i < last_word - first_word + 1; i++) { 754 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 755 &eeprom_buff[i]); 756 if (ret_val) 757 break; 758 } 759 } 760 761 /* Device's eeprom is always little-endian, word addressable */ 762 for (i = 0; i < last_word - first_word + 1; i++) 763 le16_to_cpus(&eeprom_buff[i]); 764 765 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 766 eeprom->len); 767 kfree(eeprom_buff); 768 769 return ret_val; 770 } 771 772 static int igb_set_eeprom(struct net_device *netdev, 773 struct ethtool_eeprom *eeprom, u8 *bytes) 774 { 775 struct igb_adapter *adapter = netdev_priv(netdev); 776 struct e1000_hw *hw = &adapter->hw; 777 u16 *eeprom_buff; 778 void *ptr; 779 int max_len, first_word, last_word, ret_val = 0; 780 u16 i; 781 782 if (eeprom->len == 0) 783 return -EOPNOTSUPP; 784 785 if ((hw->mac.type >= e1000_i210) && 786 !igb_get_flash_presence_i210(hw)) { 787 return -EOPNOTSUPP; 788 } 789 790 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 791 return -EFAULT; 792 793 max_len = hw->nvm.word_size * 2; 794 795 first_word = eeprom->offset >> 1; 796 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 797 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 798 if (!eeprom_buff) 799 return -ENOMEM; 800 801 ptr = (void *)eeprom_buff; 802 803 if (eeprom->offset & 1) { 804 /* need read/modify/write of first changed EEPROM word 805 * only the second byte of the word is being modified 806 */ 807 ret_val = hw->nvm.ops.read(hw, first_word, 1, 808 &eeprom_buff[0]); 809 ptr++; 810 } 811 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 812 /* need read/modify/write of last changed EEPROM word 813 * only the first byte of the word is being modified 814 */ 815 ret_val = hw->nvm.ops.read(hw, last_word, 1, 816 &eeprom_buff[last_word - first_word]); 817 } 818 819 /* Device's eeprom is always little-endian, word addressable */ 820 for (i = 0; i < last_word - first_word + 1; i++) 821 le16_to_cpus(&eeprom_buff[i]); 822 823 memcpy(ptr, bytes, eeprom->len); 824 825 for (i = 0; i < last_word - first_word + 1; i++) 826 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 827 828 ret_val = hw->nvm.ops.write(hw, first_word, 829 last_word - first_word + 1, eeprom_buff); 830 831 /* Update the checksum if nvm write succeeded */ 832 if (ret_val == 0) 833 hw->nvm.ops.update(hw); 834 835 igb_set_fw_version(adapter); 836 kfree(eeprom_buff); 837 return ret_val; 838 } 839 840 static void igb_get_drvinfo(struct net_device *netdev, 841 struct ethtool_drvinfo *drvinfo) 842 { 843 struct igb_adapter *adapter = netdev_priv(netdev); 844 845 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 846 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 847 848 /* EEPROM image version # is reported as firmware version # for 849 * 82575 controllers 850 */ 851 strlcpy(drvinfo->fw_version, adapter->fw_version, 852 sizeof(drvinfo->fw_version)); 853 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 854 sizeof(drvinfo->bus_info)); 855 } 856 857 static void igb_get_ringparam(struct net_device *netdev, 858 struct ethtool_ringparam *ring) 859 { 860 struct igb_adapter *adapter = netdev_priv(netdev); 861 862 ring->rx_max_pending = IGB_MAX_RXD; 863 ring->tx_max_pending = IGB_MAX_TXD; 864 ring->rx_pending = adapter->rx_ring_count; 865 ring->tx_pending = adapter->tx_ring_count; 866 } 867 868 static int igb_set_ringparam(struct net_device *netdev, 869 struct ethtool_ringparam *ring) 870 { 871 struct igb_adapter *adapter = netdev_priv(netdev); 872 struct igb_ring *temp_ring; 873 int i, err = 0; 874 u16 new_rx_count, new_tx_count; 875 876 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 877 return -EINVAL; 878 879 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 880 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 881 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 882 883 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 884 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 885 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 886 887 if ((new_tx_count == adapter->tx_ring_count) && 888 (new_rx_count == adapter->rx_ring_count)) { 889 /* nothing to do */ 890 return 0; 891 } 892 893 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 894 usleep_range(1000, 2000); 895 896 if (!netif_running(adapter->netdev)) { 897 for (i = 0; i < adapter->num_tx_queues; i++) 898 adapter->tx_ring[i]->count = new_tx_count; 899 for (i = 0; i < adapter->num_rx_queues; i++) 900 adapter->rx_ring[i]->count = new_rx_count; 901 adapter->tx_ring_count = new_tx_count; 902 adapter->rx_ring_count = new_rx_count; 903 goto clear_reset; 904 } 905 906 if (adapter->num_tx_queues > adapter->num_rx_queues) 907 temp_ring = vmalloc(adapter->num_tx_queues * 908 sizeof(struct igb_ring)); 909 else 910 temp_ring = vmalloc(adapter->num_rx_queues * 911 sizeof(struct igb_ring)); 912 913 if (!temp_ring) { 914 err = -ENOMEM; 915 goto clear_reset; 916 } 917 918 igb_down(adapter); 919 920 /* We can't just free everything and then setup again, 921 * because the ISRs in MSI-X mode get passed pointers 922 * to the Tx and Rx ring structs. 923 */ 924 if (new_tx_count != adapter->tx_ring_count) { 925 for (i = 0; i < adapter->num_tx_queues; i++) { 926 memcpy(&temp_ring[i], adapter->tx_ring[i], 927 sizeof(struct igb_ring)); 928 929 temp_ring[i].count = new_tx_count; 930 err = igb_setup_tx_resources(&temp_ring[i]); 931 if (err) { 932 while (i) { 933 i--; 934 igb_free_tx_resources(&temp_ring[i]); 935 } 936 goto err_setup; 937 } 938 } 939 940 for (i = 0; i < adapter->num_tx_queues; i++) { 941 igb_free_tx_resources(adapter->tx_ring[i]); 942 943 memcpy(adapter->tx_ring[i], &temp_ring[i], 944 sizeof(struct igb_ring)); 945 } 946 947 adapter->tx_ring_count = new_tx_count; 948 } 949 950 if (new_rx_count != adapter->rx_ring_count) { 951 for (i = 0; i < adapter->num_rx_queues; i++) { 952 memcpy(&temp_ring[i], adapter->rx_ring[i], 953 sizeof(struct igb_ring)); 954 955 temp_ring[i].count = new_rx_count; 956 err = igb_setup_rx_resources(&temp_ring[i]); 957 if (err) { 958 while (i) { 959 i--; 960 igb_free_rx_resources(&temp_ring[i]); 961 } 962 goto err_setup; 963 } 964 965 } 966 967 for (i = 0; i < adapter->num_rx_queues; i++) { 968 igb_free_rx_resources(adapter->rx_ring[i]); 969 970 memcpy(adapter->rx_ring[i], &temp_ring[i], 971 sizeof(struct igb_ring)); 972 } 973 974 adapter->rx_ring_count = new_rx_count; 975 } 976 err_setup: 977 igb_up(adapter); 978 vfree(temp_ring); 979 clear_reset: 980 clear_bit(__IGB_RESETTING, &adapter->state); 981 return err; 982 } 983 984 /* ethtool register test data */ 985 struct igb_reg_test { 986 u16 reg; 987 u16 reg_offset; 988 u16 array_len; 989 u16 test_type; 990 u32 mask; 991 u32 write; 992 }; 993 994 /* In the hardware, registers are laid out either singly, in arrays 995 * spaced 0x100 bytes apart, or in contiguous tables. We assume 996 * most tests take place on arrays or single registers (handled 997 * as a single-element array) and special-case the tables. 998 * Table tests are always pattern tests. 999 * 1000 * We also make provision for some required setup steps by specifying 1001 * registers to be written without any read-back testing. 1002 */ 1003 1004 #define PATTERN_TEST 1 1005 #define SET_READ_TEST 2 1006 #define WRITE_NO_TEST 3 1007 #define TABLE32_TEST 4 1008 #define TABLE64_TEST_LO 5 1009 #define TABLE64_TEST_HI 6 1010 1011 /* i210 reg test */ 1012 static struct igb_reg_test reg_test_i210[] = { 1013 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1014 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1015 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1016 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1017 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1018 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1019 /* RDH is read-only for i210, only test RDT. */ 1020 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1021 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1022 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1023 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1024 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1025 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1026 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1027 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1028 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1029 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1030 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1031 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1032 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1033 0xFFFFFFFF, 0xFFFFFFFF }, 1034 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1035 0x900FFFFF, 0xFFFFFFFF }, 1036 { E1000_MTA, 0, 128, TABLE32_TEST, 1037 0xFFFFFFFF, 0xFFFFFFFF }, 1038 { 0, 0, 0, 0, 0 } 1039 }; 1040 1041 /* i350 reg test */ 1042 static struct igb_reg_test reg_test_i350[] = { 1043 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1044 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1045 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1046 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1047 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1048 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1049 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1050 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1051 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1052 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1053 /* RDH is read-only for i350, only test RDT. */ 1054 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1055 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1056 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1057 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1058 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1059 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1060 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1061 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1062 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1063 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1064 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1065 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1066 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1067 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1068 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1069 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1070 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1071 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1072 0xFFFFFFFF, 0xFFFFFFFF }, 1073 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1074 0xC3FFFFFF, 0xFFFFFFFF }, 1075 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1076 0xFFFFFFFF, 0xFFFFFFFF }, 1077 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1078 0xC3FFFFFF, 0xFFFFFFFF }, 1079 { E1000_MTA, 0, 128, TABLE32_TEST, 1080 0xFFFFFFFF, 0xFFFFFFFF }, 1081 { 0, 0, 0, 0 } 1082 }; 1083 1084 /* 82580 reg test */ 1085 static struct igb_reg_test reg_test_82580[] = { 1086 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1087 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1088 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1089 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1090 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1091 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1092 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1093 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1094 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1095 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1096 /* RDH is read-only for 82580, only test RDT. */ 1097 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1098 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1099 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1100 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1101 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1102 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1103 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1104 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1105 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1106 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1107 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1108 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1109 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1110 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1111 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1112 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1113 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1114 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1115 0xFFFFFFFF, 0xFFFFFFFF }, 1116 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1117 0x83FFFFFF, 0xFFFFFFFF }, 1118 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1119 0xFFFFFFFF, 0xFFFFFFFF }, 1120 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1121 0x83FFFFFF, 0xFFFFFFFF }, 1122 { E1000_MTA, 0, 128, TABLE32_TEST, 1123 0xFFFFFFFF, 0xFFFFFFFF }, 1124 { 0, 0, 0, 0 } 1125 }; 1126 1127 /* 82576 reg test */ 1128 static struct igb_reg_test reg_test_82576[] = { 1129 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1130 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1131 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1132 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1134 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1135 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1136 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1137 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1138 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1139 /* Enable all RX queues before testing. */ 1140 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1141 E1000_RXDCTL_QUEUE_ENABLE }, 1142 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1143 E1000_RXDCTL_QUEUE_ENABLE }, 1144 /* RDH is read-only for 82576, only test RDT. */ 1145 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1146 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1147 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1148 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1149 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1150 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1151 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1152 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1153 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1154 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1155 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1156 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1157 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1158 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1159 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1160 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1161 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1162 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1163 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1164 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1165 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1166 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1167 { 0, 0, 0, 0 } 1168 }; 1169 1170 /* 82575 register test */ 1171 static struct igb_reg_test reg_test_82575[] = { 1172 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1173 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1174 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1175 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1176 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1177 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1178 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1179 /* Enable all four RX queues before testing. */ 1180 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1181 E1000_RXDCTL_QUEUE_ENABLE }, 1182 /* RDH is read-only for 82575, only test RDT. */ 1183 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1184 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1185 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1186 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1187 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1188 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1189 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1190 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1191 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1192 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1193 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1194 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1195 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1196 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1197 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1198 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1199 { 0, 0, 0, 0 } 1200 }; 1201 1202 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1203 int reg, u32 mask, u32 write) 1204 { 1205 struct e1000_hw *hw = &adapter->hw; 1206 u32 pat, val; 1207 static const u32 _test[] = { 1208 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1209 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1210 wr32(reg, (_test[pat] & write)); 1211 val = rd32(reg) & mask; 1212 if (val != (_test[pat] & write & mask)) { 1213 dev_err(&adapter->pdev->dev, 1214 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1215 reg, val, (_test[pat] & write & mask)); 1216 *data = reg; 1217 return true; 1218 } 1219 } 1220 1221 return false; 1222 } 1223 1224 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1225 int reg, u32 mask, u32 write) 1226 { 1227 struct e1000_hw *hw = &adapter->hw; 1228 u32 val; 1229 1230 wr32(reg, write & mask); 1231 val = rd32(reg); 1232 if ((write & mask) != (val & mask)) { 1233 dev_err(&adapter->pdev->dev, 1234 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1235 reg, (val & mask), (write & mask)); 1236 *data = reg; 1237 return true; 1238 } 1239 1240 return false; 1241 } 1242 1243 #define REG_PATTERN_TEST(reg, mask, write) \ 1244 do { \ 1245 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1246 return 1; \ 1247 } while (0) 1248 1249 #define REG_SET_AND_CHECK(reg, mask, write) \ 1250 do { \ 1251 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1252 return 1; \ 1253 } while (0) 1254 1255 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1256 { 1257 struct e1000_hw *hw = &adapter->hw; 1258 struct igb_reg_test *test; 1259 u32 value, before, after; 1260 u32 i, toggle; 1261 1262 switch (adapter->hw.mac.type) { 1263 case e1000_i350: 1264 case e1000_i354: 1265 test = reg_test_i350; 1266 toggle = 0x7FEFF3FF; 1267 break; 1268 case e1000_i210: 1269 case e1000_i211: 1270 test = reg_test_i210; 1271 toggle = 0x7FEFF3FF; 1272 break; 1273 case e1000_82580: 1274 test = reg_test_82580; 1275 toggle = 0x7FEFF3FF; 1276 break; 1277 case e1000_82576: 1278 test = reg_test_82576; 1279 toggle = 0x7FFFF3FF; 1280 break; 1281 default: 1282 test = reg_test_82575; 1283 toggle = 0x7FFFF3FF; 1284 break; 1285 } 1286 1287 /* Because the status register is such a special case, 1288 * we handle it separately from the rest of the register 1289 * tests. Some bits are read-only, some toggle, and some 1290 * are writable on newer MACs. 1291 */ 1292 before = rd32(E1000_STATUS); 1293 value = (rd32(E1000_STATUS) & toggle); 1294 wr32(E1000_STATUS, toggle); 1295 after = rd32(E1000_STATUS) & toggle; 1296 if (value != after) { 1297 dev_err(&adapter->pdev->dev, 1298 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1299 after, value); 1300 *data = 1; 1301 return 1; 1302 } 1303 /* restore previous status */ 1304 wr32(E1000_STATUS, before); 1305 1306 /* Perform the remainder of the register test, looping through 1307 * the test table until we either fail or reach the null entry. 1308 */ 1309 while (test->reg) { 1310 for (i = 0; i < test->array_len; i++) { 1311 switch (test->test_type) { 1312 case PATTERN_TEST: 1313 REG_PATTERN_TEST(test->reg + 1314 (i * test->reg_offset), 1315 test->mask, 1316 test->write); 1317 break; 1318 case SET_READ_TEST: 1319 REG_SET_AND_CHECK(test->reg + 1320 (i * test->reg_offset), 1321 test->mask, 1322 test->write); 1323 break; 1324 case WRITE_NO_TEST: 1325 writel(test->write, 1326 (adapter->hw.hw_addr + test->reg) 1327 + (i * test->reg_offset)); 1328 break; 1329 case TABLE32_TEST: 1330 REG_PATTERN_TEST(test->reg + (i * 4), 1331 test->mask, 1332 test->write); 1333 break; 1334 case TABLE64_TEST_LO: 1335 REG_PATTERN_TEST(test->reg + (i * 8), 1336 test->mask, 1337 test->write); 1338 break; 1339 case TABLE64_TEST_HI: 1340 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1341 test->mask, 1342 test->write); 1343 break; 1344 } 1345 } 1346 test++; 1347 } 1348 1349 *data = 0; 1350 return 0; 1351 } 1352 1353 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1354 { 1355 struct e1000_hw *hw = &adapter->hw; 1356 1357 *data = 0; 1358 1359 /* Validate eeprom on all parts but flashless */ 1360 switch (hw->mac.type) { 1361 case e1000_i210: 1362 case e1000_i211: 1363 if (igb_get_flash_presence_i210(hw)) { 1364 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1365 *data = 2; 1366 } 1367 break; 1368 default: 1369 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1370 *data = 2; 1371 break; 1372 } 1373 1374 return *data; 1375 } 1376 1377 static irqreturn_t igb_test_intr(int irq, void *data) 1378 { 1379 struct igb_adapter *adapter = (struct igb_adapter *) data; 1380 struct e1000_hw *hw = &adapter->hw; 1381 1382 adapter->test_icr |= rd32(E1000_ICR); 1383 1384 return IRQ_HANDLED; 1385 } 1386 1387 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1388 { 1389 struct e1000_hw *hw = &adapter->hw; 1390 struct net_device *netdev = adapter->netdev; 1391 u32 mask, ics_mask, i = 0, shared_int = true; 1392 u32 irq = adapter->pdev->irq; 1393 1394 *data = 0; 1395 1396 /* Hook up test interrupt handler just for this test */ 1397 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1398 if (request_irq(adapter->msix_entries[0].vector, 1399 igb_test_intr, 0, netdev->name, adapter)) { 1400 *data = 1; 1401 return -1; 1402 } 1403 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1404 shared_int = false; 1405 if (request_irq(irq, 1406 igb_test_intr, 0, netdev->name, adapter)) { 1407 *data = 1; 1408 return -1; 1409 } 1410 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1411 netdev->name, adapter)) { 1412 shared_int = false; 1413 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1414 netdev->name, adapter)) { 1415 *data = 1; 1416 return -1; 1417 } 1418 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1419 (shared_int ? "shared" : "unshared")); 1420 1421 /* Disable all the interrupts */ 1422 wr32(E1000_IMC, ~0); 1423 wrfl(); 1424 usleep_range(10000, 11000); 1425 1426 /* Define all writable bits for ICS */ 1427 switch (hw->mac.type) { 1428 case e1000_82575: 1429 ics_mask = 0x37F47EDD; 1430 break; 1431 case e1000_82576: 1432 ics_mask = 0x77D4FBFD; 1433 break; 1434 case e1000_82580: 1435 ics_mask = 0x77DCFED5; 1436 break; 1437 case e1000_i350: 1438 case e1000_i354: 1439 case e1000_i210: 1440 case e1000_i211: 1441 ics_mask = 0x77DCFED5; 1442 break; 1443 default: 1444 ics_mask = 0x7FFFFFFF; 1445 break; 1446 } 1447 1448 /* Test each interrupt */ 1449 for (; i < 31; i++) { 1450 /* Interrupt to test */ 1451 mask = BIT(i); 1452 1453 if (!(mask & ics_mask)) 1454 continue; 1455 1456 if (!shared_int) { 1457 /* Disable the interrupt to be reported in 1458 * the cause register and then force the same 1459 * interrupt and see if one gets posted. If 1460 * an interrupt was posted to the bus, the 1461 * test failed. 1462 */ 1463 adapter->test_icr = 0; 1464 1465 /* Flush any pending interrupts */ 1466 wr32(E1000_ICR, ~0); 1467 1468 wr32(E1000_IMC, mask); 1469 wr32(E1000_ICS, mask); 1470 wrfl(); 1471 usleep_range(10000, 11000); 1472 1473 if (adapter->test_icr & mask) { 1474 *data = 3; 1475 break; 1476 } 1477 } 1478 1479 /* Enable the interrupt to be reported in 1480 * the cause register and then force the same 1481 * interrupt and see if one gets posted. If 1482 * an interrupt was not posted to the bus, the 1483 * test failed. 1484 */ 1485 adapter->test_icr = 0; 1486 1487 /* Flush any pending interrupts */ 1488 wr32(E1000_ICR, ~0); 1489 1490 wr32(E1000_IMS, mask); 1491 wr32(E1000_ICS, mask); 1492 wrfl(); 1493 usleep_range(10000, 11000); 1494 1495 if (!(adapter->test_icr & mask)) { 1496 *data = 4; 1497 break; 1498 } 1499 1500 if (!shared_int) { 1501 /* Disable the other interrupts to be reported in 1502 * the cause register and then force the other 1503 * interrupts and see if any get posted. If 1504 * an interrupt was posted to the bus, the 1505 * test failed. 1506 */ 1507 adapter->test_icr = 0; 1508 1509 /* Flush any pending interrupts */ 1510 wr32(E1000_ICR, ~0); 1511 1512 wr32(E1000_IMC, ~mask); 1513 wr32(E1000_ICS, ~mask); 1514 wrfl(); 1515 usleep_range(10000, 11000); 1516 1517 if (adapter->test_icr & mask) { 1518 *data = 5; 1519 break; 1520 } 1521 } 1522 } 1523 1524 /* Disable all the interrupts */ 1525 wr32(E1000_IMC, ~0); 1526 wrfl(); 1527 usleep_range(10000, 11000); 1528 1529 /* Unhook test interrupt handler */ 1530 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1531 free_irq(adapter->msix_entries[0].vector, adapter); 1532 else 1533 free_irq(irq, adapter); 1534 1535 return *data; 1536 } 1537 1538 static void igb_free_desc_rings(struct igb_adapter *adapter) 1539 { 1540 igb_free_tx_resources(&adapter->test_tx_ring); 1541 igb_free_rx_resources(&adapter->test_rx_ring); 1542 } 1543 1544 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1545 { 1546 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1547 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1548 struct e1000_hw *hw = &adapter->hw; 1549 int ret_val; 1550 1551 /* Setup Tx descriptor ring and Tx buffers */ 1552 tx_ring->count = IGB_DEFAULT_TXD; 1553 tx_ring->dev = &adapter->pdev->dev; 1554 tx_ring->netdev = adapter->netdev; 1555 tx_ring->reg_idx = adapter->vfs_allocated_count; 1556 1557 if (igb_setup_tx_resources(tx_ring)) { 1558 ret_val = 1; 1559 goto err_nomem; 1560 } 1561 1562 igb_setup_tctl(adapter); 1563 igb_configure_tx_ring(adapter, tx_ring); 1564 1565 /* Setup Rx descriptor ring and Rx buffers */ 1566 rx_ring->count = IGB_DEFAULT_RXD; 1567 rx_ring->dev = &adapter->pdev->dev; 1568 rx_ring->netdev = adapter->netdev; 1569 rx_ring->reg_idx = adapter->vfs_allocated_count; 1570 1571 if (igb_setup_rx_resources(rx_ring)) { 1572 ret_val = 3; 1573 goto err_nomem; 1574 } 1575 1576 /* set the default queue to queue 0 of PF */ 1577 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1578 1579 /* enable receive ring */ 1580 igb_setup_rctl(adapter); 1581 igb_configure_rx_ring(adapter, rx_ring); 1582 1583 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1584 1585 return 0; 1586 1587 err_nomem: 1588 igb_free_desc_rings(adapter); 1589 return ret_val; 1590 } 1591 1592 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1593 { 1594 struct e1000_hw *hw = &adapter->hw; 1595 1596 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1597 igb_write_phy_reg(hw, 29, 0x001F); 1598 igb_write_phy_reg(hw, 30, 0x8FFC); 1599 igb_write_phy_reg(hw, 29, 0x001A); 1600 igb_write_phy_reg(hw, 30, 0x8FF0); 1601 } 1602 1603 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1604 { 1605 struct e1000_hw *hw = &adapter->hw; 1606 u32 ctrl_reg = 0; 1607 1608 hw->mac.autoneg = false; 1609 1610 if (hw->phy.type == e1000_phy_m88) { 1611 if (hw->phy.id != I210_I_PHY_ID) { 1612 /* Auto-MDI/MDIX Off */ 1613 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1614 /* reset to update Auto-MDI/MDIX */ 1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1616 /* autoneg off */ 1617 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1618 } else { 1619 /* force 1000, set loopback */ 1620 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1621 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1622 } 1623 } else if (hw->phy.type == e1000_phy_82580) { 1624 /* enable MII loopback */ 1625 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1626 } 1627 1628 /* add small delay to avoid loopback test failure */ 1629 msleep(50); 1630 1631 /* force 1000, set loopback */ 1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1633 1634 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1635 ctrl_reg = rd32(E1000_CTRL); 1636 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1637 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1638 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1639 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1640 E1000_CTRL_FD | /* Force Duplex to FULL */ 1641 E1000_CTRL_SLU); /* Set link up enable bit */ 1642 1643 if (hw->phy.type == e1000_phy_m88) 1644 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1645 1646 wr32(E1000_CTRL, ctrl_reg); 1647 1648 /* Disable the receiver on the PHY so when a cable is plugged in, the 1649 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1650 */ 1651 if (hw->phy.type == e1000_phy_m88) 1652 igb_phy_disable_receiver(adapter); 1653 1654 mdelay(500); 1655 return 0; 1656 } 1657 1658 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1659 { 1660 return igb_integrated_phy_loopback(adapter); 1661 } 1662 1663 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1664 { 1665 struct e1000_hw *hw = &adapter->hw; 1666 u32 reg; 1667 1668 reg = rd32(E1000_CTRL_EXT); 1669 1670 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1671 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1672 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1673 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1674 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1675 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1676 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1677 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1678 /* Enable DH89xxCC MPHY for near end loopback */ 1679 reg = rd32(E1000_MPHY_ADDR_CTL); 1680 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1681 E1000_MPHY_PCS_CLK_REG_OFFSET; 1682 wr32(E1000_MPHY_ADDR_CTL, reg); 1683 1684 reg = rd32(E1000_MPHY_DATA); 1685 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1686 wr32(E1000_MPHY_DATA, reg); 1687 } 1688 1689 reg = rd32(E1000_RCTL); 1690 reg |= E1000_RCTL_LBM_TCVR; 1691 wr32(E1000_RCTL, reg); 1692 1693 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1694 1695 reg = rd32(E1000_CTRL); 1696 reg &= ~(E1000_CTRL_RFCE | 1697 E1000_CTRL_TFCE | 1698 E1000_CTRL_LRST); 1699 reg |= E1000_CTRL_SLU | 1700 E1000_CTRL_FD; 1701 wr32(E1000_CTRL, reg); 1702 1703 /* Unset switch control to serdes energy detect */ 1704 reg = rd32(E1000_CONNSW); 1705 reg &= ~E1000_CONNSW_ENRGSRC; 1706 wr32(E1000_CONNSW, reg); 1707 1708 /* Unset sigdetect for SERDES loopback on 1709 * 82580 and newer devices. 1710 */ 1711 if (hw->mac.type >= e1000_82580) { 1712 reg = rd32(E1000_PCS_CFG0); 1713 reg |= E1000_PCS_CFG_IGN_SD; 1714 wr32(E1000_PCS_CFG0, reg); 1715 } 1716 1717 /* Set PCS register for forced speed */ 1718 reg = rd32(E1000_PCS_LCTL); 1719 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1720 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1721 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1722 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1723 E1000_PCS_LCTL_FSD | /* Force Speed */ 1724 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1725 wr32(E1000_PCS_LCTL, reg); 1726 1727 return 0; 1728 } 1729 1730 return igb_set_phy_loopback(adapter); 1731 } 1732 1733 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1734 { 1735 struct e1000_hw *hw = &adapter->hw; 1736 u32 rctl; 1737 u16 phy_reg; 1738 1739 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1740 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1741 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1742 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1743 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1744 u32 reg; 1745 1746 /* Disable near end loopback on DH89xxCC */ 1747 reg = rd32(E1000_MPHY_ADDR_CTL); 1748 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1749 E1000_MPHY_PCS_CLK_REG_OFFSET; 1750 wr32(E1000_MPHY_ADDR_CTL, reg); 1751 1752 reg = rd32(E1000_MPHY_DATA); 1753 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1754 wr32(E1000_MPHY_DATA, reg); 1755 } 1756 1757 rctl = rd32(E1000_RCTL); 1758 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1759 wr32(E1000_RCTL, rctl); 1760 1761 hw->mac.autoneg = true; 1762 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1763 if (phy_reg & MII_CR_LOOPBACK) { 1764 phy_reg &= ~MII_CR_LOOPBACK; 1765 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1766 igb_phy_sw_reset(hw); 1767 } 1768 } 1769 1770 static void igb_create_lbtest_frame(struct sk_buff *skb, 1771 unsigned int frame_size) 1772 { 1773 memset(skb->data, 0xFF, frame_size); 1774 frame_size /= 2; 1775 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1776 memset(&skb->data[frame_size + 10], 0xBE, 1); 1777 memset(&skb->data[frame_size + 12], 0xAF, 1); 1778 } 1779 1780 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1781 unsigned int frame_size) 1782 { 1783 unsigned char *data; 1784 bool match = true; 1785 1786 frame_size >>= 1; 1787 1788 data = kmap(rx_buffer->page); 1789 1790 if (data[3] != 0xFF || 1791 data[frame_size + 10] != 0xBE || 1792 data[frame_size + 12] != 0xAF) 1793 match = false; 1794 1795 kunmap(rx_buffer->page); 1796 1797 return match; 1798 } 1799 1800 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1801 struct igb_ring *tx_ring, 1802 unsigned int size) 1803 { 1804 union e1000_adv_rx_desc *rx_desc; 1805 struct igb_rx_buffer *rx_buffer_info; 1806 struct igb_tx_buffer *tx_buffer_info; 1807 u16 rx_ntc, tx_ntc, count = 0; 1808 1809 /* initialize next to clean and descriptor values */ 1810 rx_ntc = rx_ring->next_to_clean; 1811 tx_ntc = tx_ring->next_to_clean; 1812 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1813 1814 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1815 /* check Rx buffer */ 1816 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1817 1818 /* sync Rx buffer for CPU read */ 1819 dma_sync_single_for_cpu(rx_ring->dev, 1820 rx_buffer_info->dma, 1821 IGB_RX_BUFSZ, 1822 DMA_FROM_DEVICE); 1823 1824 /* verify contents of skb */ 1825 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1826 count++; 1827 1828 /* sync Rx buffer for device write */ 1829 dma_sync_single_for_device(rx_ring->dev, 1830 rx_buffer_info->dma, 1831 IGB_RX_BUFSZ, 1832 DMA_FROM_DEVICE); 1833 1834 /* unmap buffer on Tx side */ 1835 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1836 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1837 1838 /* increment Rx/Tx next to clean counters */ 1839 rx_ntc++; 1840 if (rx_ntc == rx_ring->count) 1841 rx_ntc = 0; 1842 tx_ntc++; 1843 if (tx_ntc == tx_ring->count) 1844 tx_ntc = 0; 1845 1846 /* fetch next descriptor */ 1847 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1848 } 1849 1850 netdev_tx_reset_queue(txring_txq(tx_ring)); 1851 1852 /* re-map buffers to ring, store next to clean values */ 1853 igb_alloc_rx_buffers(rx_ring, count); 1854 rx_ring->next_to_clean = rx_ntc; 1855 tx_ring->next_to_clean = tx_ntc; 1856 1857 return count; 1858 } 1859 1860 static int igb_run_loopback_test(struct igb_adapter *adapter) 1861 { 1862 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1863 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1864 u16 i, j, lc, good_cnt; 1865 int ret_val = 0; 1866 unsigned int size = IGB_RX_HDR_LEN; 1867 netdev_tx_t tx_ret_val; 1868 struct sk_buff *skb; 1869 1870 /* allocate test skb */ 1871 skb = alloc_skb(size, GFP_KERNEL); 1872 if (!skb) 1873 return 11; 1874 1875 /* place data into test skb */ 1876 igb_create_lbtest_frame(skb, size); 1877 skb_put(skb, size); 1878 1879 /* Calculate the loop count based on the largest descriptor ring 1880 * The idea is to wrap the largest ring a number of times using 64 1881 * send/receive pairs during each loop 1882 */ 1883 1884 if (rx_ring->count <= tx_ring->count) 1885 lc = ((tx_ring->count / 64) * 2) + 1; 1886 else 1887 lc = ((rx_ring->count / 64) * 2) + 1; 1888 1889 for (j = 0; j <= lc; j++) { /* loop count loop */ 1890 /* reset count of good packets */ 1891 good_cnt = 0; 1892 1893 /* place 64 packets on the transmit queue*/ 1894 for (i = 0; i < 64; i++) { 1895 skb_get(skb); 1896 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1897 if (tx_ret_val == NETDEV_TX_OK) 1898 good_cnt++; 1899 } 1900 1901 if (good_cnt != 64) { 1902 ret_val = 12; 1903 break; 1904 } 1905 1906 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1907 msleep(200); 1908 1909 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1910 if (good_cnt != 64) { 1911 ret_val = 13; 1912 break; 1913 } 1914 } /* end loop count loop */ 1915 1916 /* free the original skb */ 1917 kfree_skb(skb); 1918 1919 return ret_val; 1920 } 1921 1922 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1923 { 1924 /* PHY loopback cannot be performed if SoL/IDER 1925 * sessions are active 1926 */ 1927 if (igb_check_reset_block(&adapter->hw)) { 1928 dev_err(&adapter->pdev->dev, 1929 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1930 *data = 0; 1931 goto out; 1932 } 1933 1934 if (adapter->hw.mac.type == e1000_i354) { 1935 dev_info(&adapter->pdev->dev, 1936 "Loopback test not supported on i354.\n"); 1937 *data = 0; 1938 goto out; 1939 } 1940 *data = igb_setup_desc_rings(adapter); 1941 if (*data) 1942 goto out; 1943 *data = igb_setup_loopback_test(adapter); 1944 if (*data) 1945 goto err_loopback; 1946 *data = igb_run_loopback_test(adapter); 1947 igb_loopback_cleanup(adapter); 1948 1949 err_loopback: 1950 igb_free_desc_rings(adapter); 1951 out: 1952 return *data; 1953 } 1954 1955 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1956 { 1957 struct e1000_hw *hw = &adapter->hw; 1958 *data = 0; 1959 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1960 int i = 0; 1961 1962 hw->mac.serdes_has_link = false; 1963 1964 /* On some blade server designs, link establishment 1965 * could take as long as 2-3 minutes 1966 */ 1967 do { 1968 hw->mac.ops.check_for_link(&adapter->hw); 1969 if (hw->mac.serdes_has_link) 1970 return *data; 1971 msleep(20); 1972 } while (i++ < 3750); 1973 1974 *data = 1; 1975 } else { 1976 hw->mac.ops.check_for_link(&adapter->hw); 1977 if (hw->mac.autoneg) 1978 msleep(5000); 1979 1980 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1981 *data = 1; 1982 } 1983 return *data; 1984 } 1985 1986 static void igb_diag_test(struct net_device *netdev, 1987 struct ethtool_test *eth_test, u64 *data) 1988 { 1989 struct igb_adapter *adapter = netdev_priv(netdev); 1990 u16 autoneg_advertised; 1991 u8 forced_speed_duplex, autoneg; 1992 bool if_running = netif_running(netdev); 1993 1994 set_bit(__IGB_TESTING, &adapter->state); 1995 1996 /* can't do offline tests on media switching devices */ 1997 if (adapter->hw.dev_spec._82575.mas_capable) 1998 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 1999 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2000 /* Offline tests */ 2001 2002 /* save speed, duplex, autoneg settings */ 2003 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2004 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2005 autoneg = adapter->hw.mac.autoneg; 2006 2007 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2008 2009 /* power up link for link test */ 2010 igb_power_up_link(adapter); 2011 2012 /* Link test performed before hardware reset so autoneg doesn't 2013 * interfere with test result 2014 */ 2015 if (igb_link_test(adapter, &data[TEST_LINK])) 2016 eth_test->flags |= ETH_TEST_FL_FAILED; 2017 2018 if (if_running) 2019 /* indicate we're in test mode */ 2020 igb_close(netdev); 2021 else 2022 igb_reset(adapter); 2023 2024 if (igb_reg_test(adapter, &data[TEST_REG])) 2025 eth_test->flags |= ETH_TEST_FL_FAILED; 2026 2027 igb_reset(adapter); 2028 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2029 eth_test->flags |= ETH_TEST_FL_FAILED; 2030 2031 igb_reset(adapter); 2032 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2033 eth_test->flags |= ETH_TEST_FL_FAILED; 2034 2035 igb_reset(adapter); 2036 /* power up link for loopback test */ 2037 igb_power_up_link(adapter); 2038 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2039 eth_test->flags |= ETH_TEST_FL_FAILED; 2040 2041 /* restore speed, duplex, autoneg settings */ 2042 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2043 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2044 adapter->hw.mac.autoneg = autoneg; 2045 2046 /* force this routine to wait until autoneg complete/timeout */ 2047 adapter->hw.phy.autoneg_wait_to_complete = true; 2048 igb_reset(adapter); 2049 adapter->hw.phy.autoneg_wait_to_complete = false; 2050 2051 clear_bit(__IGB_TESTING, &adapter->state); 2052 if (if_running) 2053 igb_open(netdev); 2054 } else { 2055 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2056 2057 /* PHY is powered down when interface is down */ 2058 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2059 eth_test->flags |= ETH_TEST_FL_FAILED; 2060 else 2061 data[TEST_LINK] = 0; 2062 2063 /* Online tests aren't run; pass by default */ 2064 data[TEST_REG] = 0; 2065 data[TEST_EEP] = 0; 2066 data[TEST_IRQ] = 0; 2067 data[TEST_LOOP] = 0; 2068 2069 clear_bit(__IGB_TESTING, &adapter->state); 2070 } 2071 msleep_interruptible(4 * 1000); 2072 } 2073 2074 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2075 { 2076 struct igb_adapter *adapter = netdev_priv(netdev); 2077 2078 wol->wolopts = 0; 2079 2080 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2081 return; 2082 2083 wol->supported = WAKE_UCAST | WAKE_MCAST | 2084 WAKE_BCAST | WAKE_MAGIC | 2085 WAKE_PHY; 2086 2087 /* apply any specific unsupported masks here */ 2088 switch (adapter->hw.device_id) { 2089 default: 2090 break; 2091 } 2092 2093 if (adapter->wol & E1000_WUFC_EX) 2094 wol->wolopts |= WAKE_UCAST; 2095 if (adapter->wol & E1000_WUFC_MC) 2096 wol->wolopts |= WAKE_MCAST; 2097 if (adapter->wol & E1000_WUFC_BC) 2098 wol->wolopts |= WAKE_BCAST; 2099 if (adapter->wol & E1000_WUFC_MAG) 2100 wol->wolopts |= WAKE_MAGIC; 2101 if (adapter->wol & E1000_WUFC_LNKC) 2102 wol->wolopts |= WAKE_PHY; 2103 } 2104 2105 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2106 { 2107 struct igb_adapter *adapter = netdev_priv(netdev); 2108 2109 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2110 return -EOPNOTSUPP; 2111 2112 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2113 return wol->wolopts ? -EOPNOTSUPP : 0; 2114 2115 /* these settings will always override what we currently have */ 2116 adapter->wol = 0; 2117 2118 if (wol->wolopts & WAKE_UCAST) 2119 adapter->wol |= E1000_WUFC_EX; 2120 if (wol->wolopts & WAKE_MCAST) 2121 adapter->wol |= E1000_WUFC_MC; 2122 if (wol->wolopts & WAKE_BCAST) 2123 adapter->wol |= E1000_WUFC_BC; 2124 if (wol->wolopts & WAKE_MAGIC) 2125 adapter->wol |= E1000_WUFC_MAG; 2126 if (wol->wolopts & WAKE_PHY) 2127 adapter->wol |= E1000_WUFC_LNKC; 2128 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2129 2130 return 0; 2131 } 2132 2133 /* bit defines for adapter->led_status */ 2134 #define IGB_LED_ON 0 2135 2136 static int igb_set_phys_id(struct net_device *netdev, 2137 enum ethtool_phys_id_state state) 2138 { 2139 struct igb_adapter *adapter = netdev_priv(netdev); 2140 struct e1000_hw *hw = &adapter->hw; 2141 2142 switch (state) { 2143 case ETHTOOL_ID_ACTIVE: 2144 igb_blink_led(hw); 2145 return 2; 2146 case ETHTOOL_ID_ON: 2147 igb_blink_led(hw); 2148 break; 2149 case ETHTOOL_ID_OFF: 2150 igb_led_off(hw); 2151 break; 2152 case ETHTOOL_ID_INACTIVE: 2153 igb_led_off(hw); 2154 clear_bit(IGB_LED_ON, &adapter->led_status); 2155 igb_cleanup_led(hw); 2156 break; 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int igb_set_coalesce(struct net_device *netdev, 2163 struct ethtool_coalesce *ec) 2164 { 2165 struct igb_adapter *adapter = netdev_priv(netdev); 2166 int i; 2167 2168 if (ec->rx_max_coalesced_frames || 2169 ec->rx_coalesce_usecs_irq || 2170 ec->rx_max_coalesced_frames_irq || 2171 ec->tx_max_coalesced_frames || 2172 ec->tx_coalesce_usecs_irq || 2173 ec->stats_block_coalesce_usecs || 2174 ec->use_adaptive_rx_coalesce || 2175 ec->use_adaptive_tx_coalesce || 2176 ec->pkt_rate_low || 2177 ec->rx_coalesce_usecs_low || 2178 ec->rx_max_coalesced_frames_low || 2179 ec->tx_coalesce_usecs_low || 2180 ec->tx_max_coalesced_frames_low || 2181 ec->pkt_rate_high || 2182 ec->rx_coalesce_usecs_high || 2183 ec->rx_max_coalesced_frames_high || 2184 ec->tx_coalesce_usecs_high || 2185 ec->tx_max_coalesced_frames_high || 2186 ec->rate_sample_interval) 2187 return -ENOTSUPP; 2188 2189 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2190 ((ec->rx_coalesce_usecs > 3) && 2191 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2192 (ec->rx_coalesce_usecs == 2)) 2193 return -EINVAL; 2194 2195 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2196 ((ec->tx_coalesce_usecs > 3) && 2197 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2198 (ec->tx_coalesce_usecs == 2)) 2199 return -EINVAL; 2200 2201 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2202 return -EINVAL; 2203 2204 /* If ITR is disabled, disable DMAC */ 2205 if (ec->rx_coalesce_usecs == 0) { 2206 if (adapter->flags & IGB_FLAG_DMAC) 2207 adapter->flags &= ~IGB_FLAG_DMAC; 2208 } 2209 2210 /* convert to rate of irq's per second */ 2211 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2212 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2213 else 2214 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2215 2216 /* convert to rate of irq's per second */ 2217 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2218 adapter->tx_itr_setting = adapter->rx_itr_setting; 2219 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2220 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2221 else 2222 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2223 2224 for (i = 0; i < adapter->num_q_vectors; i++) { 2225 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2226 q_vector->tx.work_limit = adapter->tx_work_limit; 2227 if (q_vector->rx.ring) 2228 q_vector->itr_val = adapter->rx_itr_setting; 2229 else 2230 q_vector->itr_val = adapter->tx_itr_setting; 2231 if (q_vector->itr_val && q_vector->itr_val <= 3) 2232 q_vector->itr_val = IGB_START_ITR; 2233 q_vector->set_itr = 1; 2234 } 2235 2236 return 0; 2237 } 2238 2239 static int igb_get_coalesce(struct net_device *netdev, 2240 struct ethtool_coalesce *ec) 2241 { 2242 struct igb_adapter *adapter = netdev_priv(netdev); 2243 2244 if (adapter->rx_itr_setting <= 3) 2245 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2246 else 2247 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2248 2249 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2250 if (adapter->tx_itr_setting <= 3) 2251 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2252 else 2253 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2254 } 2255 2256 return 0; 2257 } 2258 2259 static int igb_nway_reset(struct net_device *netdev) 2260 { 2261 struct igb_adapter *adapter = netdev_priv(netdev); 2262 if (netif_running(netdev)) 2263 igb_reinit_locked(adapter); 2264 return 0; 2265 } 2266 2267 static int igb_get_sset_count(struct net_device *netdev, int sset) 2268 { 2269 switch (sset) { 2270 case ETH_SS_STATS: 2271 return IGB_STATS_LEN; 2272 case ETH_SS_TEST: 2273 return IGB_TEST_LEN; 2274 default: 2275 return -ENOTSUPP; 2276 } 2277 } 2278 2279 static void igb_get_ethtool_stats(struct net_device *netdev, 2280 struct ethtool_stats *stats, u64 *data) 2281 { 2282 struct igb_adapter *adapter = netdev_priv(netdev); 2283 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2284 unsigned int start; 2285 struct igb_ring *ring; 2286 int i, j; 2287 char *p; 2288 2289 spin_lock(&adapter->stats64_lock); 2290 igb_update_stats(adapter, net_stats); 2291 2292 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2293 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2294 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2295 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2296 } 2297 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2298 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2299 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2300 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2301 } 2302 for (j = 0; j < adapter->num_tx_queues; j++) { 2303 u64 restart2; 2304 2305 ring = adapter->tx_ring[j]; 2306 do { 2307 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2308 data[i] = ring->tx_stats.packets; 2309 data[i+1] = ring->tx_stats.bytes; 2310 data[i+2] = ring->tx_stats.restart_queue; 2311 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2312 do { 2313 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2314 restart2 = ring->tx_stats.restart_queue2; 2315 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2316 data[i+2] += restart2; 2317 2318 i += IGB_TX_QUEUE_STATS_LEN; 2319 } 2320 for (j = 0; j < adapter->num_rx_queues; j++) { 2321 ring = adapter->rx_ring[j]; 2322 do { 2323 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2324 data[i] = ring->rx_stats.packets; 2325 data[i+1] = ring->rx_stats.bytes; 2326 data[i+2] = ring->rx_stats.drops; 2327 data[i+3] = ring->rx_stats.csum_err; 2328 data[i+4] = ring->rx_stats.alloc_failed; 2329 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2330 i += IGB_RX_QUEUE_STATS_LEN; 2331 } 2332 spin_unlock(&adapter->stats64_lock); 2333 } 2334 2335 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2336 { 2337 struct igb_adapter *adapter = netdev_priv(netdev); 2338 u8 *p = data; 2339 int i; 2340 2341 switch (stringset) { 2342 case ETH_SS_TEST: 2343 memcpy(data, *igb_gstrings_test, 2344 IGB_TEST_LEN*ETH_GSTRING_LEN); 2345 break; 2346 case ETH_SS_STATS: 2347 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2348 memcpy(p, igb_gstrings_stats[i].stat_string, 2349 ETH_GSTRING_LEN); 2350 p += ETH_GSTRING_LEN; 2351 } 2352 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2353 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2354 ETH_GSTRING_LEN); 2355 p += ETH_GSTRING_LEN; 2356 } 2357 for (i = 0; i < adapter->num_tx_queues; i++) { 2358 sprintf(p, "tx_queue_%u_packets", i); 2359 p += ETH_GSTRING_LEN; 2360 sprintf(p, "tx_queue_%u_bytes", i); 2361 p += ETH_GSTRING_LEN; 2362 sprintf(p, "tx_queue_%u_restart", i); 2363 p += ETH_GSTRING_LEN; 2364 } 2365 for (i = 0; i < adapter->num_rx_queues; i++) { 2366 sprintf(p, "rx_queue_%u_packets", i); 2367 p += ETH_GSTRING_LEN; 2368 sprintf(p, "rx_queue_%u_bytes", i); 2369 p += ETH_GSTRING_LEN; 2370 sprintf(p, "rx_queue_%u_drops", i); 2371 p += ETH_GSTRING_LEN; 2372 sprintf(p, "rx_queue_%u_csum_err", i); 2373 p += ETH_GSTRING_LEN; 2374 sprintf(p, "rx_queue_%u_alloc_failed", i); 2375 p += ETH_GSTRING_LEN; 2376 } 2377 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2378 break; 2379 } 2380 } 2381 2382 static int igb_get_ts_info(struct net_device *dev, 2383 struct ethtool_ts_info *info) 2384 { 2385 struct igb_adapter *adapter = netdev_priv(dev); 2386 2387 if (adapter->ptp_clock) 2388 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2389 else 2390 info->phc_index = -1; 2391 2392 switch (adapter->hw.mac.type) { 2393 case e1000_82575: 2394 info->so_timestamping = 2395 SOF_TIMESTAMPING_TX_SOFTWARE | 2396 SOF_TIMESTAMPING_RX_SOFTWARE | 2397 SOF_TIMESTAMPING_SOFTWARE; 2398 return 0; 2399 case e1000_82576: 2400 case e1000_82580: 2401 case e1000_i350: 2402 case e1000_i354: 2403 case e1000_i210: 2404 case e1000_i211: 2405 info->so_timestamping = 2406 SOF_TIMESTAMPING_TX_SOFTWARE | 2407 SOF_TIMESTAMPING_RX_SOFTWARE | 2408 SOF_TIMESTAMPING_SOFTWARE | 2409 SOF_TIMESTAMPING_TX_HARDWARE | 2410 SOF_TIMESTAMPING_RX_HARDWARE | 2411 SOF_TIMESTAMPING_RAW_HARDWARE; 2412 2413 info->tx_types = 2414 BIT(HWTSTAMP_TX_OFF) | 2415 BIT(HWTSTAMP_TX_ON); 2416 2417 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2418 2419 /* 82576 does not support timestamping all packets. */ 2420 if (adapter->hw.mac.type >= e1000_82580) 2421 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2422 else 2423 info->rx_filters |= 2424 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2425 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2426 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2427 2428 return 0; 2429 default: 2430 return -EOPNOTSUPP; 2431 } 2432 } 2433 2434 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2435 struct ethtool_rxnfc *cmd) 2436 { 2437 cmd->data = 0; 2438 2439 /* Report default options for RSS on igb */ 2440 switch (cmd->flow_type) { 2441 case TCP_V4_FLOW: 2442 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2443 /* Fall through */ 2444 case UDP_V4_FLOW: 2445 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2446 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2447 /* Fall through */ 2448 case SCTP_V4_FLOW: 2449 case AH_ESP_V4_FLOW: 2450 case AH_V4_FLOW: 2451 case ESP_V4_FLOW: 2452 case IPV4_FLOW: 2453 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2454 break; 2455 case TCP_V6_FLOW: 2456 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2457 /* Fall through */ 2458 case UDP_V6_FLOW: 2459 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2460 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2461 /* Fall through */ 2462 case SCTP_V6_FLOW: 2463 case AH_ESP_V6_FLOW: 2464 case AH_V6_FLOW: 2465 case ESP_V6_FLOW: 2466 case IPV6_FLOW: 2467 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2468 break; 2469 default: 2470 return -EINVAL; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2477 u32 *rule_locs) 2478 { 2479 struct igb_adapter *adapter = netdev_priv(dev); 2480 int ret = -EOPNOTSUPP; 2481 2482 switch (cmd->cmd) { 2483 case ETHTOOL_GRXRINGS: 2484 cmd->data = adapter->num_rx_queues; 2485 ret = 0; 2486 break; 2487 case ETHTOOL_GRXFH: 2488 ret = igb_get_rss_hash_opts(adapter, cmd); 2489 break; 2490 default: 2491 break; 2492 } 2493 2494 return ret; 2495 } 2496 2497 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2498 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2499 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2500 struct ethtool_rxnfc *nfc) 2501 { 2502 u32 flags = adapter->flags; 2503 2504 /* RSS does not support anything other than hashing 2505 * to queues on src and dst IPs and ports 2506 */ 2507 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2508 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2509 return -EINVAL; 2510 2511 switch (nfc->flow_type) { 2512 case TCP_V4_FLOW: 2513 case TCP_V6_FLOW: 2514 if (!(nfc->data & RXH_IP_SRC) || 2515 !(nfc->data & RXH_IP_DST) || 2516 !(nfc->data & RXH_L4_B_0_1) || 2517 !(nfc->data & RXH_L4_B_2_3)) 2518 return -EINVAL; 2519 break; 2520 case UDP_V4_FLOW: 2521 if (!(nfc->data & RXH_IP_SRC) || 2522 !(nfc->data & RXH_IP_DST)) 2523 return -EINVAL; 2524 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2525 case 0: 2526 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2527 break; 2528 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2529 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2530 break; 2531 default: 2532 return -EINVAL; 2533 } 2534 break; 2535 case UDP_V6_FLOW: 2536 if (!(nfc->data & RXH_IP_SRC) || 2537 !(nfc->data & RXH_IP_DST)) 2538 return -EINVAL; 2539 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2540 case 0: 2541 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2542 break; 2543 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2544 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2545 break; 2546 default: 2547 return -EINVAL; 2548 } 2549 break; 2550 case AH_ESP_V4_FLOW: 2551 case AH_V4_FLOW: 2552 case ESP_V4_FLOW: 2553 case SCTP_V4_FLOW: 2554 case AH_ESP_V6_FLOW: 2555 case AH_V6_FLOW: 2556 case ESP_V6_FLOW: 2557 case SCTP_V6_FLOW: 2558 if (!(nfc->data & RXH_IP_SRC) || 2559 !(nfc->data & RXH_IP_DST) || 2560 (nfc->data & RXH_L4_B_0_1) || 2561 (nfc->data & RXH_L4_B_2_3)) 2562 return -EINVAL; 2563 break; 2564 default: 2565 return -EINVAL; 2566 } 2567 2568 /* if we changed something we need to update flags */ 2569 if (flags != adapter->flags) { 2570 struct e1000_hw *hw = &adapter->hw; 2571 u32 mrqc = rd32(E1000_MRQC); 2572 2573 if ((flags & UDP_RSS_FLAGS) && 2574 !(adapter->flags & UDP_RSS_FLAGS)) 2575 dev_err(&adapter->pdev->dev, 2576 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2577 2578 adapter->flags = flags; 2579 2580 /* Perform hash on these packet types */ 2581 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2582 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2583 E1000_MRQC_RSS_FIELD_IPV6 | 2584 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2585 2586 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2587 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2588 2589 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2590 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2591 2592 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2593 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2594 2595 wr32(E1000_MRQC, mrqc); 2596 } 2597 2598 return 0; 2599 } 2600 2601 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2602 { 2603 struct igb_adapter *adapter = netdev_priv(dev); 2604 int ret = -EOPNOTSUPP; 2605 2606 switch (cmd->cmd) { 2607 case ETHTOOL_SRXFH: 2608 ret = igb_set_rss_hash_opt(adapter, cmd); 2609 break; 2610 default: 2611 break; 2612 } 2613 2614 return ret; 2615 } 2616 2617 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 2618 { 2619 struct igb_adapter *adapter = netdev_priv(netdev); 2620 struct e1000_hw *hw = &adapter->hw; 2621 u32 ret_val; 2622 u16 phy_data; 2623 2624 if ((hw->mac.type < e1000_i350) || 2625 (hw->phy.media_type != e1000_media_type_copper)) 2626 return -EOPNOTSUPP; 2627 2628 edata->supported = (SUPPORTED_1000baseT_Full | 2629 SUPPORTED_100baseT_Full); 2630 if (!hw->dev_spec._82575.eee_disable) 2631 edata->advertised = 2632 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 2633 2634 /* The IPCNFG and EEER registers are not supported on I354. */ 2635 if (hw->mac.type == e1000_i354) { 2636 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 2637 } else { 2638 u32 eeer; 2639 2640 eeer = rd32(E1000_EEER); 2641 2642 /* EEE status on negotiated link */ 2643 if (eeer & E1000_EEER_EEE_NEG) 2644 edata->eee_active = true; 2645 2646 if (eeer & E1000_EEER_TX_LPI_EN) 2647 edata->tx_lpi_enabled = true; 2648 } 2649 2650 /* EEE Link Partner Advertised */ 2651 switch (hw->mac.type) { 2652 case e1000_i350: 2653 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 2654 &phy_data); 2655 if (ret_val) 2656 return -ENODATA; 2657 2658 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2659 break; 2660 case e1000_i354: 2661 case e1000_i210: 2662 case e1000_i211: 2663 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 2664 E1000_EEE_LP_ADV_DEV_I210, 2665 &phy_data); 2666 if (ret_val) 2667 return -ENODATA; 2668 2669 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2670 2671 break; 2672 default: 2673 break; 2674 } 2675 2676 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 2677 2678 if ((hw->mac.type == e1000_i354) && 2679 (edata->eee_enabled)) 2680 edata->tx_lpi_enabled = true; 2681 2682 /* Report correct negotiated EEE status for devices that 2683 * wrongly report EEE at half-duplex 2684 */ 2685 if (adapter->link_duplex == HALF_DUPLEX) { 2686 edata->eee_enabled = false; 2687 edata->eee_active = false; 2688 edata->tx_lpi_enabled = false; 2689 edata->advertised &= ~edata->advertised; 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int igb_set_eee(struct net_device *netdev, 2696 struct ethtool_eee *edata) 2697 { 2698 struct igb_adapter *adapter = netdev_priv(netdev); 2699 struct e1000_hw *hw = &adapter->hw; 2700 struct ethtool_eee eee_curr; 2701 bool adv1g_eee = true, adv100m_eee = true; 2702 s32 ret_val; 2703 2704 if ((hw->mac.type < e1000_i350) || 2705 (hw->phy.media_type != e1000_media_type_copper)) 2706 return -EOPNOTSUPP; 2707 2708 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 2709 2710 ret_val = igb_get_eee(netdev, &eee_curr); 2711 if (ret_val) 2712 return ret_val; 2713 2714 if (eee_curr.eee_enabled) { 2715 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 2716 dev_err(&adapter->pdev->dev, 2717 "Setting EEE tx-lpi is not supported\n"); 2718 return -EINVAL; 2719 } 2720 2721 /* Tx LPI timer is not implemented currently */ 2722 if (edata->tx_lpi_timer) { 2723 dev_err(&adapter->pdev->dev, 2724 "Setting EEE Tx LPI timer is not supported\n"); 2725 return -EINVAL; 2726 } 2727 2728 if (!edata->advertised || (edata->advertised & 2729 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 2730 dev_err(&adapter->pdev->dev, 2731 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 2732 return -EINVAL; 2733 } 2734 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 2735 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 2736 2737 } else if (!edata->eee_enabled) { 2738 dev_err(&adapter->pdev->dev, 2739 "Setting EEE options are not supported with EEE disabled\n"); 2740 return -EINVAL; 2741 } 2742 2743 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 2744 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 2745 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 2746 adapter->flags |= IGB_FLAG_EEE; 2747 2748 /* reset link */ 2749 if (netif_running(netdev)) 2750 igb_reinit_locked(adapter); 2751 else 2752 igb_reset(adapter); 2753 } 2754 2755 if (hw->mac.type == e1000_i354) 2756 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 2757 else 2758 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 2759 2760 if (ret_val) { 2761 dev_err(&adapter->pdev->dev, 2762 "Problem setting EEE advertisement options\n"); 2763 return -EINVAL; 2764 } 2765 2766 return 0; 2767 } 2768 2769 static int igb_get_module_info(struct net_device *netdev, 2770 struct ethtool_modinfo *modinfo) 2771 { 2772 struct igb_adapter *adapter = netdev_priv(netdev); 2773 struct e1000_hw *hw = &adapter->hw; 2774 u32 status = 0; 2775 u16 sff8472_rev, addr_mode; 2776 bool page_swap = false; 2777 2778 if ((hw->phy.media_type == e1000_media_type_copper) || 2779 (hw->phy.media_type == e1000_media_type_unknown)) 2780 return -EOPNOTSUPP; 2781 2782 /* Check whether we support SFF-8472 or not */ 2783 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 2784 if (status) 2785 return -EIO; 2786 2787 /* addressing mode is not supported */ 2788 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 2789 if (status) 2790 return -EIO; 2791 2792 /* addressing mode is not supported */ 2793 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 2794 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 2795 page_swap = true; 2796 } 2797 2798 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 2799 /* We have an SFP, but it does not support SFF-8472 */ 2800 modinfo->type = ETH_MODULE_SFF_8079; 2801 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 2802 } else { 2803 /* We have an SFP which supports a revision of SFF-8472 */ 2804 modinfo->type = ETH_MODULE_SFF_8472; 2805 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2806 } 2807 2808 return 0; 2809 } 2810 2811 static int igb_get_module_eeprom(struct net_device *netdev, 2812 struct ethtool_eeprom *ee, u8 *data) 2813 { 2814 struct igb_adapter *adapter = netdev_priv(netdev); 2815 struct e1000_hw *hw = &adapter->hw; 2816 u32 status = 0; 2817 u16 *dataword; 2818 u16 first_word, last_word; 2819 int i = 0; 2820 2821 if (ee->len == 0) 2822 return -EINVAL; 2823 2824 first_word = ee->offset >> 1; 2825 last_word = (ee->offset + ee->len - 1) >> 1; 2826 2827 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1), 2828 GFP_KERNEL); 2829 if (!dataword) 2830 return -ENOMEM; 2831 2832 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 2833 for (i = 0; i < last_word - first_word + 1; i++) { 2834 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 2835 &dataword[i]); 2836 if (status) { 2837 /* Error occurred while reading module */ 2838 kfree(dataword); 2839 return -EIO; 2840 } 2841 2842 be16_to_cpus(&dataword[i]); 2843 } 2844 2845 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 2846 kfree(dataword); 2847 2848 return 0; 2849 } 2850 2851 static int igb_ethtool_begin(struct net_device *netdev) 2852 { 2853 struct igb_adapter *adapter = netdev_priv(netdev); 2854 pm_runtime_get_sync(&adapter->pdev->dev); 2855 return 0; 2856 } 2857 2858 static void igb_ethtool_complete(struct net_device *netdev) 2859 { 2860 struct igb_adapter *adapter = netdev_priv(netdev); 2861 pm_runtime_put(&adapter->pdev->dev); 2862 } 2863 2864 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 2865 { 2866 return IGB_RETA_SIZE; 2867 } 2868 2869 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2870 u8 *hfunc) 2871 { 2872 struct igb_adapter *adapter = netdev_priv(netdev); 2873 int i; 2874 2875 if (hfunc) 2876 *hfunc = ETH_RSS_HASH_TOP; 2877 if (!indir) 2878 return 0; 2879 for (i = 0; i < IGB_RETA_SIZE; i++) 2880 indir[i] = adapter->rss_indir_tbl[i]; 2881 2882 return 0; 2883 } 2884 2885 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 2886 { 2887 struct e1000_hw *hw = &adapter->hw; 2888 u32 reg = E1000_RETA(0); 2889 u32 shift = 0; 2890 int i = 0; 2891 2892 switch (hw->mac.type) { 2893 case e1000_82575: 2894 shift = 6; 2895 break; 2896 case e1000_82576: 2897 /* 82576 supports 2 RSS queues for SR-IOV */ 2898 if (adapter->vfs_allocated_count) 2899 shift = 3; 2900 break; 2901 default: 2902 break; 2903 } 2904 2905 while (i < IGB_RETA_SIZE) { 2906 u32 val = 0; 2907 int j; 2908 2909 for (j = 3; j >= 0; j--) { 2910 val <<= 8; 2911 val |= adapter->rss_indir_tbl[i + j]; 2912 } 2913 2914 wr32(reg, val << shift); 2915 reg += 4; 2916 i += 4; 2917 } 2918 } 2919 2920 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 2921 const u8 *key, const u8 hfunc) 2922 { 2923 struct igb_adapter *adapter = netdev_priv(netdev); 2924 struct e1000_hw *hw = &adapter->hw; 2925 int i; 2926 u32 num_queues; 2927 2928 /* We do not allow change in unsupported parameters */ 2929 if (key || 2930 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 2931 return -EOPNOTSUPP; 2932 if (!indir) 2933 return 0; 2934 2935 num_queues = adapter->rss_queues; 2936 2937 switch (hw->mac.type) { 2938 case e1000_82576: 2939 /* 82576 supports 2 RSS queues for SR-IOV */ 2940 if (adapter->vfs_allocated_count) 2941 num_queues = 2; 2942 break; 2943 default: 2944 break; 2945 } 2946 2947 /* Verify user input. */ 2948 for (i = 0; i < IGB_RETA_SIZE; i++) 2949 if (indir[i] >= num_queues) 2950 return -EINVAL; 2951 2952 2953 for (i = 0; i < IGB_RETA_SIZE; i++) 2954 adapter->rss_indir_tbl[i] = indir[i]; 2955 2956 igb_write_rss_indir_tbl(adapter); 2957 2958 return 0; 2959 } 2960 2961 static unsigned int igb_max_channels(struct igb_adapter *adapter) 2962 { 2963 struct e1000_hw *hw = &adapter->hw; 2964 unsigned int max_combined = 0; 2965 2966 switch (hw->mac.type) { 2967 case e1000_i211: 2968 max_combined = IGB_MAX_RX_QUEUES_I211; 2969 break; 2970 case e1000_82575: 2971 case e1000_i210: 2972 max_combined = IGB_MAX_RX_QUEUES_82575; 2973 break; 2974 case e1000_i350: 2975 if (!!adapter->vfs_allocated_count) { 2976 max_combined = 1; 2977 break; 2978 } 2979 /* fall through */ 2980 case e1000_82576: 2981 if (!!adapter->vfs_allocated_count) { 2982 max_combined = 2; 2983 break; 2984 } 2985 /* fall through */ 2986 case e1000_82580: 2987 case e1000_i354: 2988 default: 2989 max_combined = IGB_MAX_RX_QUEUES; 2990 break; 2991 } 2992 2993 return max_combined; 2994 } 2995 2996 static void igb_get_channels(struct net_device *netdev, 2997 struct ethtool_channels *ch) 2998 { 2999 struct igb_adapter *adapter = netdev_priv(netdev); 3000 3001 /* Report maximum channels */ 3002 ch->max_combined = igb_max_channels(adapter); 3003 3004 /* Report info for other vector */ 3005 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3006 ch->max_other = NON_Q_VECTORS; 3007 ch->other_count = NON_Q_VECTORS; 3008 } 3009 3010 ch->combined_count = adapter->rss_queues; 3011 } 3012 3013 static int igb_set_channels(struct net_device *netdev, 3014 struct ethtool_channels *ch) 3015 { 3016 struct igb_adapter *adapter = netdev_priv(netdev); 3017 unsigned int count = ch->combined_count; 3018 unsigned int max_combined = 0; 3019 3020 /* Verify they are not requesting separate vectors */ 3021 if (!count || ch->rx_count || ch->tx_count) 3022 return -EINVAL; 3023 3024 /* Verify other_count is valid and has not been changed */ 3025 if (ch->other_count != NON_Q_VECTORS) 3026 return -EINVAL; 3027 3028 /* Verify the number of channels doesn't exceed hw limits */ 3029 max_combined = igb_max_channels(adapter); 3030 if (count > max_combined) 3031 return -EINVAL; 3032 3033 if (count != adapter->rss_queues) { 3034 adapter->rss_queues = count; 3035 igb_set_flag_queue_pairs(adapter, max_combined); 3036 3037 /* Hardware has to reinitialize queues and interrupts to 3038 * match the new configuration. 3039 */ 3040 return igb_reinit_queues(adapter); 3041 } 3042 3043 return 0; 3044 } 3045 3046 static const struct ethtool_ops igb_ethtool_ops = { 3047 .get_settings = igb_get_settings, 3048 .set_settings = igb_set_settings, 3049 .get_drvinfo = igb_get_drvinfo, 3050 .get_regs_len = igb_get_regs_len, 3051 .get_regs = igb_get_regs, 3052 .get_wol = igb_get_wol, 3053 .set_wol = igb_set_wol, 3054 .get_msglevel = igb_get_msglevel, 3055 .set_msglevel = igb_set_msglevel, 3056 .nway_reset = igb_nway_reset, 3057 .get_link = igb_get_link, 3058 .get_eeprom_len = igb_get_eeprom_len, 3059 .get_eeprom = igb_get_eeprom, 3060 .set_eeprom = igb_set_eeprom, 3061 .get_ringparam = igb_get_ringparam, 3062 .set_ringparam = igb_set_ringparam, 3063 .get_pauseparam = igb_get_pauseparam, 3064 .set_pauseparam = igb_set_pauseparam, 3065 .self_test = igb_diag_test, 3066 .get_strings = igb_get_strings, 3067 .set_phys_id = igb_set_phys_id, 3068 .get_sset_count = igb_get_sset_count, 3069 .get_ethtool_stats = igb_get_ethtool_stats, 3070 .get_coalesce = igb_get_coalesce, 3071 .set_coalesce = igb_set_coalesce, 3072 .get_ts_info = igb_get_ts_info, 3073 .get_rxnfc = igb_get_rxnfc, 3074 .set_rxnfc = igb_set_rxnfc, 3075 .get_eee = igb_get_eee, 3076 .set_eee = igb_set_eee, 3077 .get_module_info = igb_get_module_info, 3078 .get_module_eeprom = igb_get_module_eeprom, 3079 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3080 .get_rxfh = igb_get_rxfh, 3081 .set_rxfh = igb_set_rxfh, 3082 .get_channels = igb_get_channels, 3083 .set_channels = igb_set_channels, 3084 .begin = igb_ethtool_begin, 3085 .complete = igb_ethtool_complete, 3086 }; 3087 3088 void igb_set_ethtool_ops(struct net_device *netdev) 3089 { 3090 netdev->ethtool_ops = &igb_ethtool_ops; 3091 } 3092